text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
CONFIG_ARM_MPU=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_USE_DT_CODE_PARTITION=y
``` | /content/code_sandbox/boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```ini
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
source [find interface/jlink.cfg]
transport select swd
source [find target/xmc4xxx.cfg]
``` | /content/code_sandbox/boards/infineon/xmc45_relax_kit/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
/*
*
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*
*/
/dts-v1/;
#include <infineon/cat3/xmc/xmc4500_F100x1024.dtsi>
#include <infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include "xmc45_relax_kit-pinctrl.dtsi"
/ {
model = "Infineon XMC4500 Relax Kit";
compatible = "infineon,xm4500-relax-kit", "infineon,xmc4500",
"infineon,xmc4xxx";
aliases {
led0 = &led1;
die-temp0 = &die_temp;
pwm-led0 = &pwm_led1;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
/* leds are labelled LED1 and LED2 in the relax kit documentation */
led1: led1 {
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
};
led2: led2 {
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led1: pwm_led1 {
pwms = <&pwm_ccu40 2 PWM_SEC(1) PWM_POLARITY_NORMAL>;
label = "PWM LED1";
};
pwm_led2: pwm_led2 {
pwms = <&pwm_ccu40 3 PWM_SEC(1) PWM_POLARITY_NORMAL>;
label = "PWM LED2";
};
};
chosen {
zephyr,sram = &dsram1;
zephyr,flash = &flash0;
zephyr,console = &usic1ch1;
zephyr,shell-uart = &usic1ch1;
zephyr,flash-controller = &flash_controller;
zephyr,code-partition = &code_partition;
};
};
&psram1 {
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "PSRAM1";
};
&dsram2 {
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "DSRAM2";
};
&flash_controller {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
code_partition: partition@0 {
reg = <0x0 0x80000>;
read-only;
};
storage_partition: partition@80000 {
label = "storage";
reg = <0x80000 0x80000>;
};
};
};
&cpu0 {
clock-frequency = <120000000>;
};
&usic1ch1 {
compatible = "infineon,xmc4xxx-uart";
current-speed = <115200>;
pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
pinctrl-names = "default";
input-src = "DX0D";
interrupts = <90 1 91 1>;
interrupt-names = "tx", "rx";
fifo-start-offset = <0>;
fifo-tx-size = <16>;
fifo-rx-size = <16>;
status = "okay";
};
&adc0 {
vref-internal-mv = <3300>;
};
&adc1 {
vref-internal-mv = <3300>;
};
&adc2 {
vref-internal-mv = <3300>;
};
&adc3 {
vref-internal-mv = <3300>;
};
&gpio1 {
status = "okay";
};
&pwm_ccu40 {
slice-prescaler = <15 15 15 15>;
pinctrl-0 = <&pwm_out_p1_0_ccu40_ch3 &pwm_out_p1_1_ccu40_ch2>;
pinctrl-names = "default";
};
ð {
status = "okay";
pinctrl-0 = <ð_p2_4_rxer ð_p2_2_rxd0 ð_p2_3_rxd1
ð_p15_8_clk_rmii ð_p15_9_crs_dv ð_p2_5_tx_en
ð_p2_8_txd0 ð_p2_9_txd1>;
pinctrl-names = "default";
rxer-port-ctrl = "P2_4";
rxd0-port-ctrl = "P2_2";
rxd1-port-ctrl = "P2_3";
rmii-rx-clk-port-ctrl = "P15_8";
crs-rx-dv-port-ctrl = "P15_9";
phy-connection-type = "rmii";
phy-handle = <&phy>;
};
&mdio {
status = "okay";
mdi-port-ctrl = "P2_0";
pinctrl-0 = <ð_p2_0_mdo ð_p2_7_mdc>;
pinctrl-names = "default";
phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0>;
};
};
``` | /content/code_sandbox/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,203 |
```cmake
#**************************************************************************
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-Licence-Identifier: Apache-2.0
#***************************************************************************
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
board_runner_args(pyocd "--target=cy8c6xx7_nosmif")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```restructuredtext
.. _xmc45_relax_kit:
INFINEON XMC45-RELAX-KIT
########################
Overview
********
The XMC4500 Relax Kit is designed to evaluate the capabilities of the XMC4500
Microcontroller. It is based on High performance ARM Cortex-M4F which can run
up to 120MHz.
.. image:: xmc45_relax_kit.jpg
:align: center
:alt: XMC45-RELAX-KIT
Features:
=========
* ARM Cortex-M4F XMC4500
* 32 Mbit Quad-SPI Flash
* 4 x SPI-Master, 3x I2C, 3 x I2S, 3 x UART, 2 x CAN, 17 x ADC
* 2 pin header x1 and x2 with 80 pins
* Two buttons and two LEDs for user interaction
* Detachable on-board debugger (second XMC4500) with Segger J-Link
Details on the Relax Kit development board can be found in the `Relax Kit User Manual`_.
Supported Features
==================
* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz.
The Relax Kit development board configuration supports the following hardware features:
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+-----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-----------------------+
| UART | on-chip | serial port |
+-----------+------------+-----------------------+
| SPI | on-chip | spi |
+-----------+------------+-----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-----------------------+
| FLASH | on-chip | flash |
+-----------+------------+-----------------------+
| ADC | on-chip | adc |
+-----------+------------+-----------------------+
| DMA | on-chip | dma |
+-----------+------------+-----------------------+
| PWM | on-chip | pwm |
+-----------+------------+-----------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-----------------------+
| MDIO | on-chip | mdio |
+-----------+------------+-----------------------+
| ETHERNET | on-chip | ethernet |
+-----------+------------+-----------------------+
| PTP | on-chip | ethernet |
+-----------+------------+-----------------------+
More details about the supported peripherals are available in `XMC4500 TRM`_
Other hardware features are not currently supported by the Zephyr kernel.
Building and Flashing
*********************
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: xmc45_relax_kit
:goals: flash
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: xmc45_relax_kit
:goals: debug
Step through the application in your debugger.
References
**********
.. _Relax Kit User Manual:
path_to_url
.. _XMC4500 TRM:
path_to_url
``` | /content/code_sandbox/boards/infineon/xmc45_relax_kit/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 773 |
```yaml
#
#
identifier: cy8cproto_063_ble
name: CY8CPROTO-063-BLE PSoC 6 BLE Prototyping Kit
type: mcu
arch: arm
ram: 288
flash: 1024
toolchain:
- zephyr
- gnuarmemb
supported:
- adc
- gpio
- uart
- i2c
- watchdog
- spi
- timer
vendor: infineon
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```yaml
board:
name: cy8cproto_063_ble
vendor: infineon
socs:
- name: cyble_416045_02
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
/dts-v1/;
#include <infineon/cat1a/mpns/CYBLE_416045_02.dtsi>
#include <infineon/cat1a/system_clocks.dtsi>
#include "cy8cproto_063_ble-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "CY8CPROTO-063-BLE PSoC 6 BLE Prototyping Kit";
compatible = "cypress,cy8cproto_063_ble", "cypress,PSoC6";
aliases {
uart-5 = &uart5;
led0 = &user_led;
sw0 = &user_bt;
watchdog0 = &watchdog0;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart5;
zephyr,shell-uart = &uart5;
zephyr,bt-hci = &bluetooth;
};
/delete-node/ cpu@0;
leds {
compatible = "gpio-leds";
user_led: led_0 {
label = "LED_0";
gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt: button_0 {
label = "SW_0";
gpios = <&gpio_prt0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&gpio_prt0 {
status = "okay";
};
&gpio_prt5 {
status = "okay";
};
&gpio_prt6 {
status = "okay";
};
&gpio_prt7 {
status = "okay";
};
&gpio_prt9 {
status = "okay";
};
&gpio_prt10 {
status = "okay";
};
&gpio_prt12 {
status = "okay";
};
uart5: &scb5 {
compatible = "infineon,cat1-uart";
status = "okay";
current-speed = <115200>;
/* UART pins */
pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
pinctrl-names = "default";
};
/* System clock configuration */
&fll0 {
status = "okay";
clock-frequency = <100000000>;
};
&clk_hf0 {
clock-div = <1>;
clocks = <&fll0>;
};
/* CM4 core clock = 100MHz
* &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
*/
&clk_fast {
clock-div = <1>;
};
/* CM0+ core clock = 50MHz
* &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
*/
&clk_slow {
clock-div = <2>;
};
/* PERI core clock = 100MHz
* &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
*/
&clk_peri {
clock-div = <1>;
};
&bluetooth {
status = "okay";
};
&watchdog0 {
status = "okay";
};
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 766 |
```unknown
# CY8CPROTO-063-BLE PSoC 6 BLE Prototyping Kit
# an affiliate of Cypress Semiconductor Corporation
if BOARD_CY8CPROTO_063_BLE
# No defaults to change for now
endif # BOARD_CY8CPROTO_063_BLE
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
/*
* an affiliate of Cypress Semiconductor Corporation
*/
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# CY8CPROTO-063-BLE PSoC 6 BLE Prototyping Kit
#
# an affiliate of Cypress Semiconductor Corporation
config BOARD_CY8CPROTO_063_BLE
select SOC_CYBLE_416045_02
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
#**************************************************************************
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-Licence-Identifier: Apache-2.0
#***************************************************************************
# General configuration
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable pin controller
CONFIG_PINCTRL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable clock controller
CONFIG_CLOCK_CONTROL=y
# Main Stack Size
CONFIG_MAIN_STACK_SIZE=2048
# Add catcm0p sleep images for CM0 Devices
CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```ini
#**************************************************************************
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-Licence-Identifier: Apache-2.0
#***************************************************************************
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
# By default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/psoc6.cfg]
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```restructuredtext
.. _boards-sipeed:
Sipeed
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/sipeed/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
board_runner_args(openocd --cmd-pre-init "source [find target/gd32vf103.cfg]")
board_runner_args(openocd "--cmd-pre-load=gd32vf103-pre-load")
board_runner_args(openocd "--cmd-load=gd32vf103-load")
board_runner_args(openocd "--cmd-post-verify=gd32vf103-post-verify")
board_runner_args(dfu-util "--pid=28e9:0189" "--alt=0" "--dfuse")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
``` | /content/code_sandbox/boards/sipeed/longan_nano/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```yaml
identifier: longan_nano
name: Sipeed Longan Nano
type: mcu
arch: riscv
toolchain:
- zephyr
- xtools
flash: 128
ram: 32
supported:
- watchdog
- dma
- spi
vendor: sipeed
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
config BOARD_LONGAN_NANO
select SOC_GD32VF103
``` | /content/code_sandbox/boards/sipeed/longan_nano/Kconfig.longan_nano | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```restructuredtext
.. _cy8cproto_063_ble:
INFINEON CY8CPROTO-063-BLE
###########################
Overview
********
The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that
enables design and debug of the Cypress PSoC 63 BLE MCU.
.. image:: img/cy8cproto-063-ble.jpg
:align: center
:alt: CY8CPROTO-063-BLE
Hardware
********
For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board:
- `PSoC 63 BLE MCU SoC Website`_
- `PSoC 63 BLE MCU Datasheet`_
- `PSoC 63 BLE MCU Architecture Reference Manual`_
- `PSoC 63 BLE MCU Register Reference Manual`_
- `CY8CPROTO-063-BLE Website`_
- `CY8CPROTO-063-BLE User Guide`_
- `CY8CPROTO-063-BLE Schematics`_
Supported Features
==================
The board configuration supports the following hardware features:
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+-----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-----------------------+
| PINCTRL | on-chip | pin control |
+-----------+------------+-----------------------+
| SPI | on-chip | spi |
+-----------+------------+-----------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-----------------------+
| I2C | on-chip | I2C |
+-----------+------------+-----------------------+
| PWM | on-chip | PWM |
+-----------+------------+-----------------------+
| Counter | on-chip | Counter |
+-----------+------------+-----------------------+
| Bluetooth | on-chip | Bluetooth |
+-----------+------------+-----------------------+
The default configurations can be found in
:zephyr_file:`boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig`
System Clock
============
The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
system clock are provided in the SOC, depending on your system requirements.
OpenOCD Installation
====================
To get the OpenOCD package, it is required that you
1. Download the software ModusToolbox 3.1. path_to_url
2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox
export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts
3. Add the OpenOCD executable file's path to west flash/debug.
4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd
5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd
Fetch Binary Blobs
******************
cy8cproto_063_ble board requires fetch binary files
(e.g Bluetooth controller firmware, CM0p prebuilt images, etc).
To fetch Binary Blobs:
.. code-block:: console
west blobs fetch hal_infineon
Programming and Debugging
*************************
The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with
mass storage programming to provide debugging, flash programming, and serial
communication over USB. Flash and debug commands must be pointed to the Cypress
OpenOCD you downloaded above.
On Windows:
.. code-block:: console
west flash --openocd path/to/infineon/openocd/bin/openocd.exe
west debug --openocd path/to/infineon/openocd/bin/openocd.exe
On Linux:
.. code-block:: console
west flash --openocd path/to/infineon/openocd/bin/openocd
west debug --openocd path/to/infineon/openocd/bin/openocd
References
**********
.. _PSoC 63 BLE MCU SoC Website:
path_to_url
.. _PSoC 63 BLE MCU Datasheet:
path_to_url
.. _PSoC 63 BLE MCU Architecture Reference Manual:
path_to_url
.. _PSoC 63 BLE MCU Register Reference Manual:
path_to_url
.. _CY8CPROTO-063-BLE Website:
path_to_url
.. _CY8CPROTO-063-BLE User Guide:
path_to_url#!?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812
.. _CY8CPROTO-063-BLE Schematics:
path_to_url#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821
.. _Infineon OpenOCD:
path_to_url
``` | /content/code_sandbox/boards/infineon/cy8cproto_063_ble/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,186 |
```unknown
/*
*/
#include <dt-bindings/pinctrl/gd32vf103c(b-8)xx-pinctrl.h>
&pinctrl {
usart0_default: usart0_default {
group1 {
pinmux = <USART0_TX_PA9_NORMP>, <USART0_RX_PA10_NORMP>;
};
};
pwm1_default: pwm1_default {
group1 {
pinmux = <TIMER1_CH1_PA1_OUT_NORMP>, <TIMER1_CH2_PA2_OUT_NORMP>;
};
};
dac_default: dac_default {
group1 {
pinmux = <DAC_OUT0_PA4>;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <SPI0_NSS_PA4_OUT_NORMP>, <SPI0_SCK_PA5_OUT_NORMP>,
<SPI0_MISO_PA6_INP_NORMP>, <SPI0_MOSI_PA7_OUT_NORMP>;
};
};
spi1_default: spi1_default {
group1 {
pinmux = <SPI1_MISO_PB14_INP>, <SPI1_SCK_PB13_OUT>,
<SPI1_MOSI_PB15_OUT>, <SPI1_NSS_PB12_OUT>;
};
};
adc0_default: adc0_default {
group1 {
pinmux = <ADC01_IN0_PA0>;
};
};
};
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 318 |
```unknown
# Sipeed longan nano Development Board Configuration
#
#
CONFIG_GD32_HXTAL_8MHZ=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
chosen {
zephyr,console = &usart0;
zephyr,shell-uart = &usart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,display = &lcd0;
sdhc0 = &sdhc0;
};
leds {
compatible = "gpio-leds";
led_red: led_red {
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
label = "LED_R";
};
led_green: led_green {
gpios = <&gpioa 1 GPIO_ACTIVE_LOW>;
label = "LED_G";
};
led_blue: led_blue {
gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
label = "LED_B";
};
};
gpio_keys {
compatible = "gpio-keys";
button_boot0: button_boot0 {
label = "BUTTON_BOOT0";
gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds {
compatible = "pwm-leds";
/* NOTE: bridge TIMER1_CH1 and LED_GREEN (PA1) */
pwm_led_green: pwm_led_green {
pwms = <&pwm1 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "PWM_LED_G";
};
/* NOTE: bridge TIMER1_CH2 and LED_BLUE (PA2) */
pwm_led_blue: pwm_led_blue {
pwms = <&pwm1 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "PWM_LED_B";
};
};
aliases {
led0 = &led_red;
led1 = &led_green;
led2 = &led_blue;
pwm-led0 = &pwm_led_green;
pwm-led1 = &pwm_led_blue;
sw0 = &button_boot0;
watchdog0 = &fwdgt;
};
mipi_dbi {
compatible = "zephyr,mipi-dbi-spi";
reset-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
dc-gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
spi-dev = <&spi0>;
write-only;
#address-cells = <1>;
#size-cells = <0>;
/* longan nano has LCD with st7735s controller.
* It can use with st7735r driver.
*/
lcd0: lcd@0 {
compatible = "sitronix,st7735r";
reg = <0>;
status = "okay";
width = <160>;
height = <80>;
inversion-on;
rgb-is-inverted;
x-offset = <1>;
y-offset = <26>;
pwctr1 = [62 02 04];
pwctr2 = [C0];
pwctr3 = [0D 00];
pwctr4 = [8D 6A];
pwctr5 = [8D EE];
invctr = <3>;
frmctr1 = [05 3A 3A];
frmctr2 = [05 3A 3A];
frmctr3 = [05 3A 3A 05 3A 3A];
vmctr1 = <14>;
gamctrp1 = [10 0E 02 03 0E 07 02 07 0A 12 27 37 00 0D 0E 10];
gamctrn1 = [10 0E 03 03 0F 06 02 08 0A 13 26 36 00 0D 0E 10];
colmod = <5>;
madctl = <120>;
caset = [00 01 00 a0];
raset = [00 1a 00 69];
mipi-mode = <MIPI_DBI_MODE_SPI_4WIRE>;
mipi-max-frequency = <4000000>;
};
};
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&usart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&usart0_default>;
pinctrl-names = "default";
};
&timer1 {
status = "okay";
prescaler = <4096>;
pwm1: pwm {
status = "okay";
pinctrl-0 = <&pwm1_default>;
pinctrl-names = "default";
};
};
&dac {
status = "okay";
pinctrl-0 = <&dac_default>;
pinctrl-names = "default";
};
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
};
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
sdhc0: sdhc@0 {
compatible = "zephyr,sdhc-spi-slot";
reg = <0>;
status = "okay";
spi-max-frequency = <24000000>;
mmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&fwdgt {
status = "okay";
};
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano-common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,343 |
```yaml
identifier: longan_nano/gd32vf103/lite
name: Sipeed Longan Nano Lite
type: mcu
arch: riscv
toolchain:
- zephyr
- xtools
flash: 64
ram: 20
supported:
- watchdog
- dma
- spi
vendor: sipeed
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```yaml
board:
name: longan_nano
vendor: sipeed
socs:
- name: gd32vf103
variants:
- name: lite
``` | /content/code_sandbox/boards/sipeed/longan_nano/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```unknown
/*
*
*/
/dts-v1/;
#include <gd/gd32vf103X8.dtsi>
#include "longan_nano-pinctrl.dtsi"
#include "longan_nano-common.dtsi"
/ {
model = "Sipeed Longan Nano Lite";
compatible = "sipeed,longan_nano_lite";
};
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
# Sipeed longan nano Development Board Configuration
#
#
CONFIG_GD32_HXTAL_8MHZ=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
# Sipeed longan nano Development Board Configuration
if BOARD_LONGAN_NANO
config DISK_DRIVER_SDMMC
default y if DISK_DRIVERS
endif # BOARD_LONGAN_NANO
``` | /content/code_sandbox/boards/sipeed/longan_nano/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
/*
*
*/
/dts-v1/;
#include <gd/gd32vf103Xb.dtsi>
#include "longan_nano-pinctrl.dtsi"
#include "longan_nano-common.dtsi"
/ {
model = "Sipeed Longan Nano";
compatible = "sipeed,longan_nano";
};
``` | /content/code_sandbox/boards/sipeed/longan_nano/longan_nano.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```ini
interface ftdi
ftdi_device_desc "Dual RS232"
#ftdi_device_desc "Sipeed-Debug"
#ftdi_device_desc "JTAG Debugger"
ftdi_vid_pid 0x0403 0x6010
#ftdi_channel 0
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
adapter speed 2000
transport select jtag
proc gd32vf103-pre-load {} {
halt
}
proc gd32vf103-load {file} {
flash protect 0 0 last off
flash write_image erase $file
}
proc gd32vf103-post-verify {} {
mww 0xe004200c 0x4b5a6978
mww 0xe0042008 0x01
resume
}
``` | /content/code_sandbox/boards/sipeed/longan_nano/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 193 |
```restructuredtext
.. _boards-lowrisc:
lowRISC
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/lowrisc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
identifier: opentitan_earlgrey
name: OpenTitan Earl Grey
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 128
testing:
ignore_tags:
- net
- bluetooth
supported:
- watchdog
vendor: lowrisc
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config BOARD_OPENTITAN_EARLGREY
select SOC_OPENTITAN
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
CONFIG_XIP=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_BIN=n
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```yaml
board:
name: opentitan_earlgrey
vendor: lowrisc
socs:
- name: opentitan
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <lowrisc/opentitan_earlgrey.dtsi>
/ {
model = "OpenTitan Earlgrey";
compatible = "lowrisc,opentitan-earlgrey";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
zephyr,flash = &flash0;
};
};
&uart0 {
status = "okay";
clock-frequency = <125000>;
current-speed = <7200>;
};
&mtimer {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```restructuredtext
.. _longan_nano:
Sipeed Longan Nano
##################
.. image:: img/longan_nano.jpg
:align: center
:alt: longan_nano
Overview
********
The Sipeed Longan Nano and Longan Nano Lite is an simple and tiny development board with
an GigaDevice GD32VF103 SoC that based on N200 RISC-V IP core by Nuclei system technology.
More information can be found on:
- `Sipeed Longan website <path_to_url`_
- `GD32VF103 datasheet <path_to_url`_
- `GD32VF103 user manual <path_to_url`_
- `Nuclei website <path_to_url`_
- `Nuclei Bumblebee core documents <path_to_url`_
- `Nuclei ISA Spec <path_to_url`_
Hardware
********
- 4 x universal 16-bit timer
- 2 x basic 16-bit timer
- 1 x advanced 16-bit timer
- Watchdog timer
- RTC
- Systick
- 3 x USART
- 2 x I2C
- 3 x SPI
- 2 x I2S
- 2 x CAN
- 1 x USBFS(OTG)
- 2 x ADC(10 channel)
- 2 x DAC
Supported Features
==================
The board configuration supports the following hardware features:
.. list-table::
:header-rows: 1
* - Peripheral
- Kconfig option
- Devicetree compatible
* - GPIO
- :kconfig:option:`CONFIG_GPIO`
- :dtcompatible:`gd,gd32-gpio`
* - Machine timer
- :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER`
- :dtcompatible:`riscv,machine-timer`
* - Nuclei ECLIC Interrupt Controller
- :kconfig:option:`CONFIG_NUCLEI_ECLIC`
- :dtcompatible:`nuclei,eclic`
* - PWM
- :kconfig:option:`CONFIG_PWM`
- :dtcompatible:`gd,gd32-pwm`
* - USART
- :kconfig:option:`CONFIG_SERIAL`
- :dtcompatible:`gd,gd32-usart`
* - I2C
- :kconfig:option:`CONFIG_I2C`
- :dtcompatible:`gd,gd32-i2c`
* - DAC
- :kconfig:option:`CONFIG_DAC`
- :dtcompatible:`gd,gd32-dac`
* - ADC
- :kconfig:option:`CONFIG_ADC`
- :dtcompatible:`gd,gd32-adc`
* - SPI
- :kconfig:option:`CONFIG_SPI`
- :dtcompatible:`gd,gd32-spi`
The microSD card reader in Longan Nano board is connected to SPI1.
Serial Port
===========
USART0 is on the opposite end of the USB.
Connect to TX0 (PA9) and RX0 (PA10).
Programming and debugging
*************************
Building & Flashing
===================
Here is an example for building the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: longan_nano
:goals: build flash
When using a custom toolchain it should be enough to have the downloaded
version of the binary in your ``PATH``.
The default runner tries to flash the board via an external programmer using openocd.
To flash via the USB port, select the DFU runner when flashing:
.. code-block:: console
west flash --runner dfu-util
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: longan_nano
:maybe-skip-config:
:goals: debug
``` | /content/code_sandbox/boards/sipeed/longan_nano/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 889 |
```restructuredtext
.. _boards-luatos:
Luatos
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/luatos/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO43>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO44>;
bias-pull-up;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO1>,
<I2C0_SCL_GPIO2>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <I2C1_SDA_GPIO4>,
<I2C1_SCL_GPIO5>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO13>,
<SPIM2_SCLK_GPIO12>,
<SPIM2_CSEL_GPIO10>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO11>;
output-low;
};
};
spim3_default: spim3_default {
group1 {
pinmux = <SPIM3_MISO_GPIO37>,
<SPIM3_SCLK_GPIO36>,
<SPIM3_CSEL_GPIO38>;
};
group2 {
pinmux = <SPIM3_MOSI_GPIO39>;
output-low;
};
};
twai_default: twai_default {
group1 {
pinmux = <TWAI_TX_GPIO5>,
<TWAI_RX_GPIO6>;
};
};
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 456 |
```restructuredtext
.. _opentitan_earlgrey:
OpenTitan Earl Grey
###################
Overview
********
The OpenTitan Earl Grey chip is a low-power secure microcontroller that is
designed for several use cases requiring hardware security. The `OpenTitan
Github`_ page contains HDL code, utilities, and documentation relevant to the
chip.
Hardware
********
- RV32IMCB RISC-V "Ibex" core
- 128kB main SRAM
- Fixed-frequency and AON timers
- 32 x GPIO
- 4 x UART
- 3 x I2C
- 2 x SPI host
- 1 x SPI device
- Various security peripherals
Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_.
Supported Features
==================
The ``opentitan_earlgrey`` board configuration is designed and tested to run on
the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| Timer | on-chip | RISC-V Machine Timer |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling |
+-----------+------------+-------------------------------------+
| SPI | on-chip | SPI host |
+-----------+------------+-------------------------------------+
| WDT | on-chip | Always-On Timer (Watchdog) |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
Programming and Debugging
*************************
First, build and install Verilator as described in the `OpenTitan Verilator
Setup`_ guide .
Building and Flashing
=====================
Here is an example for building the :ref:`hello_world` application. The
following steps were tested on OpenTitan master branch @ 6a3c2e98.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: opentitan_earlgrey
:goals: build
The OpenTitan Vchip_sim_tb tool can take the Zephyr .elf as input and place it
in simulated flash. The OpenTitan test ROM will then run in simulation, read
the manifest header from simulated flash, and begin executing Zephyr from the
entry point.
.. code-block:: console
$OT_HOME/bazel-bin/hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verbose-mem-load \
-r $OT_HOME/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.39.scr.vmem \
--meminit=otp,$OT_HOME/bazel-out/k8-fastbuild/bin/hw/ip/otp_ctrl/data/img_rma.24.vmem \
--meminit=flash,$ZEPHYR_PATH/build/zephyr/zephyr.elf
UART output:
.. code-block:: console
I00000 test_rom.c:135] Version: earlgrey_silver_release_v5-9599-g6a3c2e988, Build Date: 2023-01-17 16:02:09
I00001 test_rom.c:237] Test ROM complete, jumping to flash (addr: 20000384)!
*** Booting Zephyr OS build zephyr-v3.2.0-3494-gf0729b494b98 ***
Hello World! opentitan_earlgrey
References
**********
.. target-notes::
.. _OpenTitan Earl Grey Chip Datasheet: path_to_url
.. _OpenTitan GitHub: path_to_url
.. _OpenTitan Verilator Setup: path_to_url
``` | /content/code_sandbox/boards/lowrisc/opentitan_earlgrey/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 840 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```yaml
identifier: esp32s3_luatos_core/esp32s3/procpu/usb
name: ESP32-S3 LuatOS Core PROCPU USB
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- uart
- i2c
- spi
- can
- counter
- watchdog
- entropy
- pwm
- dma
testing:
ignore_tags:
- net
- bluetooth
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
/ {
model = "ESP32S3 Luatos Core USB APPCPU";
compatible = "espressif,esp32s3";
chosen {
zephyr,sram = &sram0;
zephyr,ipc_shm = &shm0;
zephyr,ipc = &ipm0;
};
};
&trng0 {
status = "okay";
};
&ipm0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 64kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 410 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```yaml
identifier: esp32s3_luatos_core/esp32s3/appcpu/usb
name: ESP32-S3 LuatOS Core APPCPU USB
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- uart
testing:
ignore_tags:
- net
- bluetooth
- flash
- cpp
- posix
- watchdog
- logging
- kernel
- pm
- gpio
- crypto
- eeprom
- heap
- cmsis_rtos
- jwt
- zdsp
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 140 |
```yaml
identifier: esp32s3_luatos_core/esp32s3/procpu
name: ESP32-S3 LuatOS Core PROCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- uart
- i2c
- spi
- can
- counter
- watchdog
- entropy
- pwm
- dma
testing:
ignore_tags:
- net
- bluetooth
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
/*
*
*/
#include <espressif/esp32s3/esp32s3_mini_n8.dtsi>
#include "esp32s3_luatos_core-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds {
compatible = "gpio-leds";
led0: led0 {
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
label = "LEDA";
};
led1: led1 {
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
label = "LEDB";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "BOOT Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&i2c0 {
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&i2c1 {
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&spi3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim3_default>;
pinctrl-names = "default";
};
&twai {
pinctrl-0 = <&twai_default>;
pinctrl-names = "default";
};
&timer0 {
status = "disabled";
};
&timer1 {
status = "disabled";
};
&timer2 {
status = "disabled";
};
&timer3 {
status = "disabled";
};
&wdt0 {
status = "okay";
};
&trng0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 64kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 824 |
```unknown
/*
*
*/
/dts-v1/;
#include "esp32s3_luatos_core.dtsi"
/ {
model = "ESP32S3 Luatos Core USB PROCPU";
compatible = "espressif,esp32s3";
aliases {
led0 = &led0;
led1 = &led1;
i2c-0 = &i2c0;
watchdog0 = &wdt0;
uart-0 = &usb_serial;
sw0 = &button0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash = &flash0;
zephyr,bt_hci = &esp32_bt_hci;
};
};
&usb_serial {
status = "okay";
};
&uart0 {
status = "disabled";
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 207 |
```yaml
board:
name: esp32s3_luatos_core
vendor: luatos
socs:
- name: esp32s3
variants:
- name: usb
cpucluster: procpu
- name: usb
cpucluster: appcpu
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config BOARD_ESP32S3_LUATOS_CORE
select SOC_ESP32S3_MINI_N8
select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB
select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```unknown
# ESP32S3 Core board configuration
if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB
if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB
config HEAP_MEM_POOL_ADD_SIZE_BOARD
default 256
endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 222 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
/ {
model = "ESP32S3 Luatos Core APPCPU";
compatible = "espressif,esp32s3";
chosen {
zephyr,sram = &sram0;
zephyr,ipc_shm = &shm0;
zephyr,ipc = &ipm0;
};
};
&trng0 {
status = "okay";
};
&ipm0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 64kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 409 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
/*
*
*/
/dts-v1/;
#include "esp32s3_luatos_core.dtsi"
/ {
model = "ESP32S3 Luatos Core PROCPU";
compatible = "espressif,esp32s3";
aliases {
led0 = &led0;
led1 = &led1;
i2c-0 = &i2c0;
watchdog0 = &wdt0;
uart-0 = &uart0;
sw0 = &button0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &esp32_bt_hci;
};
};
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 200 |
```yaml
identifier: esp32s3_luatos_core/esp32s3/appcpu
name: ESP32-S3 LuatOS Core APPCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- uart
testing:
ignore_tags:
- net
- bluetooth
- flash
- cpp
- posix
- watchdog
- logging
- kernel
- pm
- gpio
- crypto
- eeprom
- heap
- cmsis_rtos
- jwt
- zdsp
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```ini
set ESP_RTOS none
set ESP32_ONLYCPU 1
# Source the JTAG interface configuration file
source [find interface/esp_usb_jtag.cfg]
# Source the ESP32-S3 configuration file
source [find target/esp32s3.cfg]
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
/*
*
*/
/dts-v1/;
#include "esp32c3_luatos_core.dtsi"
/ {
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &esp32_bt_hci;
};
};
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
config BOARD_ESP32C3_LUATOS_CORE
select SOC_ESP32C3_MINI_N4
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
#include <espressif/esp32c3/esp32c3_mini_n4.dtsi>
#include "esp32c3_luatos_core-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "ESP32C3 Luatos Core";
compatible = "espressif,esp32c3";
aliases {
sw0 = &user_button1;
i2c-0 = &i2c0;
watchdog0 = &wdt0;
led0 = &led_d4;
led1 = &led_d5;
};
gpio_keys {
compatible = "gpio-keys";
user_button1: button_1 {
label = "User SW1";
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
leds {
compatible = "gpio-leds";
led_d4: led_1 {
label = "D4";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
led_d5: led_2 {
label = "D5";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&trng0 {
status = "okay";
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&timer0 {
status = "disabled";
};
&timer1 {
status = "disabled";
};
&twai {
/* requires external CAN transceiver or jumper on RX and TX pins for loopback testing */
status = "disabled";
pinctrl-0 = <&twai_default>;
pinctrl-names = "default";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 824 |
```unknown
/*
*
*/
/dts-v1/;
#include "esp32c3_luatos_core.dtsi"
/ {
chosen {
zephyr,sram = &sram0;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash = &flash0;
};
};
&uart0 {
status = "disabled";
};
&usb_serial {
status = "okay";
};
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```restructuredtext
.. _esp32s3_luatos_core:
ESP32S3-Luatos-Core
###################
Overview
********
The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3.
The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities.
For more information, check `ESP32S3-LUATOS-CORE`_ (chinese)
.. image:: img/esp32s3_luatos_core.jpg
:align: center
:alt: esp32s3_luatos_core
Hardware
********
ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
and Bluetooth Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
(Xtensa 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
RF module, and numerous peripherals.
ESP32S3-LUATOS-CORE includes the following features:
- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
- Additional vector instructions support for AI acceleration
- 512KB of SRAM
- 384KB of ROM
- 8MB of PSRAM
- 16MB of FLASH
- Wi-Fi 802.11b/g/n
- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate
Digital interfaces:
- 4x SPI
- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411
- 1x DVP 8-bit ~16-bit camera interface
- 3x UART
- 2x I2C
- 2x I2S
- 1x RMT (TX/RX)
- 1x pulse counter
- LED PWM controller, up to 8 channels
- 1x USB Port with USB switcher, supporting following modes:
- 1x full-speed USB OTG or 1x USB Serial/JTAG controller
- USB to serial chip CH343
- 2x MCPWM
- 1x SDIO host controller with 2 slots
- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels
- 1x TWAI controller, compatible with ISO 11898-1 (CAN Specification 2.0)
- 2x Blue LED
Analog interfaces:
- 2x 12-bit SAR ADCs, up to 20 channels
Timers:
- 4x 54-bit general-purpose timers
- 1x 52-bit system timer
- 3x watchdog timers
Low Power:
- Power Management Unit with five power modes
- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM
Security:
- Secure boot
- Flash encryption
- 4-Kbit OTP, up to 1792 bits for users
- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature)
For more information, check the datasheet at `ESP32-S3 Datasheet`_.
.. image:: img/esp32s3_luatos_core_pinout.jpg
:align: center
:alt: esp32s3_luatos_core_pinout
Supported Features
==================
Current Zephyr's ESP32S3-LUATOS-Core board supports the following features:
+------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+============+============+=====================================+
| UART | on-chip | serial port |
+------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+------------+------------+-------------------------------------+
| USB-JTAG | on-chip | hardware interface |
+------------+------------+-------------------------------------+
| SPI Master | on-chip | spi |
+------------+------------+-------------------------------------+
| TWAI/CAN | on-chip | can |
+------------+------------+-------------------------------------+
| Timers | on-chip | counter |
+------------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+------------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+------------+------------+-------------------------------------+
| LEDC | on-chip | pwm |
+------------+------------+-------------------------------------+
| MCPWM | on-chip | pwm |
+------------+------------+-------------------------------------+
| PCNT | on-chip | qdec |
+------------+------------+-------------------------------------+
| GDMA | on-chip | dma |
+------------+------------+-------------------------------------+
| USB-CDC | on-chip | serial |
+------------+------------+-------------------------------------+
Prerequisites
-------------
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
*******************
Simple boot
===========
The board could be loaded using the single binary image, without 2nd stage bootloader.
It is the default option when building the application without additional configuration.
.. note::
Simple boot does not provide any security features nor OTA updates.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: esp32s3_luatos_core
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s3_luatos_core/esp32s3/procpu
:goals: build
If CH343 chip is disabled, You need use the following command to build:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s3_luatos_core/esp32s3/procpu/usb
:goals: build
The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s3_luatos_core/esp32s3/procpu
:goals: flash
Open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! esp32s3_luatos_core
Debugging
*********
ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
Download and install OpenOCD from `OpenOCD`_.
ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary.
Further documentation can be obtained from the SoC vendor in `JTAG debugging
for ESP32-S3`_.
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s3_luatos_core/esp32s3/procpu
:goals: build flash
You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s3_luatos_core/esp32s3/procpu
:goals: debug
.. _`JTAG debugging for ESP32-S3`: path_to_url
.. _`OpenOCD`: path_to_url
.. _`ESP32S3-LUATOS-CORE`: path_to_url
References
**********
.. _ESP32S3-LUATOS-CORE User Guide: path_to_url
.. _ESP32-S3 Datasheet: path_to_url
.. _ESP32 Technical Reference Manual: path_to_url
``` | /content/code_sandbox/boards/luatos/esp32s3_luatos_core/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,295 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO21>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO20>;
bias-pull-up;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO2>,
<SPIM2_SCLK_GPIO6>,
<SPIM2_CSEL_GPIO10>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO7>;
output-low;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO1>,
<I2C0_SCL_GPIO3>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
twai_default: twai_default {
group1 {
pinmux = <TWAI_TX_GPIO4>,
<TWAI_RX_GPIO5>;
};
};
};
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 315 |
```yaml
board:
name: esp32c3_luatos_core
vendor: luatos
socs:
- name: esp32c3
variants:
- name: usb
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
identifier: esp32c3_luatos_core/esp32c3/usb
name: ESP32C3 LuatOS Core USB
type: mcu
arch: riscv
toolchain:
- zephyr
supported:
- adc
- gpio
- i2c
- watchdog
- uart
- dma
- pwm
- spi
- counter
- entropy
testing:
ignore_tags:
- net
- bluetooth
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# ESP32C3 core board configuration
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```ini
set ESP_RTOS none
# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+).
# Uncomment the line below to enable USB debugging.
source [find interface/esp_usb_jtag.cfg]
# Otherwise, use external JTAG programmer as ESP-Prog
# source [find interface/ftdi/esp32_devkitj_v1.cfg]
source [find target/esp32c3.cfg]
adapter speed 5000
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```yaml
identifier: esp32c3_luatos_core/esp32c3
name: ESP32C3 LuatOS Core
type: mcu
arch: riscv
toolchain:
- zephyr
supported:
- adc
- gpio
- i2c
- watchdog
- uart
- dma
- pwm
- spi
- counter
- entropy
testing:
ignore_tags:
- net
- bluetooth
vendor: luatos
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```restructuredtext
.. _boards-ene:
ENE
###
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/ene/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```cmake
board_runner_args(jlink "--device=KB1200" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/ene/kb1200_evb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```yaml
identifier: kb1200_evb
name: KB1200 EVB
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- uart
ram: 64
flash: 256
``` | /content/code_sandbox/boards/ene/kb1200_evb/kb1200_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
config BOARD_KB1200_EVB
select SOC_KB1200
``` | /content/code_sandbox/boards/ene/kb1200_evb/Kconfig.kb1200_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```unknown
# Enable console & UART driver
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable GPIO
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/ene/kb1200_evb/kb1200_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```yaml
board:
name: kb1200_evb
vendor: ene
socs:
- name: kb1200
``` | /content/code_sandbox/boards/ene/kb1200_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
/dts-v1/;
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <ene/kb1200.dtsi>
#include <ene/kb1200-pinctrl.dtsi>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "KB1200 board";
compatible = "ene,kb1200";
aliases {
uart0 = &uart0;
led0 = &led0;
led1 = &led1;
sw0 = &user_button;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpio0x1x 0x10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
};
leds {
compatible = "gpio-leds";
/* green led */
led0: led_0 {
gpios = <&gpio0x1x 0x0f GPIO_ACTIVE_HIGH>;
label = "LED0";
};
/* blue led */
led1: led_1 {
gpios = <&gpio0x1x 0x11 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
};
};
&uart0 {
pinctrl-0 = <&uart0_tx_gpio03 &uart0_rx_gpio01>;
pinctrl-names = "default";
status = "okay";
current-speed = <115200>;
};
&uart1 {
pinctrl-0 = <&uart1_tx_gpio36 &uart1_rx_gpio28>;
pinctrl-names = "default";
status = "okay";
current-speed = <115200>;
};
&uart2 {
pinctrl-0 = <&uart2_tx_gpio04 &uart2_rx_gpio55>;
pinctrl-names = "default";
status = "okay";
current-speed = <115200>;
};
&gpio0x1x {
status = "okay";
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc0_gpio0a &adc1_gpio0b &adc2_gpio0c &adc3_gpio0d>;
pinctrl-names = "default";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_gpio3a>;
pinctrl-names = "default";
};
&pwm4 {
status = "okay";
pinctrl-0 = <&pwm4_gpio31>;
pinctrl-names = "default";
};
&pwm5 {
status = "okay";
pinctrl-0 = <&pwm5_gpio30>;
pinctrl-names = "default";
};
&pwm6 {
status = "okay";
pinctrl-0 = <&pwm6_gpio37>;
pinctrl-names = "default";
};
&tach0 {
status = "okay";
pinctrl-0 = <&tach0_gpio48>;
pinctrl-names = "default";
pulses-per-round = <2>;
sample-time-us = <2>;
};
&tach1 {
status = "okay";
pinctrl-0 = <&tach1_gpio4e>;
pinctrl-names = "default";
pulses-per-round = <1>;
sample-time-us = <8>;
};
&tach2 {
status = "okay";
pinctrl-0 = <&tach2_gpio0e>;
pinctrl-names = "default";
pulses-per-round = <2>;
sample-time-us = <16>;
};
&tach3 {
status = "okay";
pinctrl-0 = <&tach3_gpio43>;
pinctrl-names = "default";
pulses-per-round = <1>;
sample-time-us = <64>;
};
&wdt0 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_clk_gpio2c &i2c0_dat_gpio2d>;
pinctrl-names = "default";
};
&i2c8 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c8_clk_gpio70 &i2c8_dat_gpio71>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/ene/kb1200_evb/kb1200_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 964 |
```restructuredtext
.. _esp32c3_luatos_core:
ESP32C3_LUATOS_CORE
###################
Overview
********
ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC,
based on the open-source RISC-V architecture. It strikes the right balance of power,
I/O capabilities and security, thus offering the optimal cost-effective
solution for connected devices.
The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy,
but it also facilitates a variety of use-cases based on dual connectivity. [1]_
The features include the following:
- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz
- 400 KB of internal RAM
- 802.11b/g/n/e/i
- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh
- Various peripherals:
- 12-bit ADC with up to 6 channels
- TWAI compatible with CAN bus 2.0
- Temperature sensor
- 3x SPI
- 1x I2S
- 1x I2C
- 2x UART
- LED PWM with up to 6 channels
- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES)
There are two version hardware of this board. The difference between them is the ch343 chip.
1. USB-C connect to UART over CH343 chip(esp32c3_luatos_core)
.. image:: img/esp32c3_luatos_core.jpg
:align: center
:alt: esp32c3_luatos_core
2. USB-C connect to esp32 chip directly(esp32c3_luatos_core/esp32c3/usb)
.. image:: img/esp32c3_luatos_core_usb.jpg
:align: center
:alt: esp32c3_luatos_core/esp32c3/usb
Supported Features
==================
Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features:
+------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+============+============+=====================================+
| UART | on-chip | serial port |
+------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+------------+------------+-------------------------------------+
| USB-JTAG | on-chip | hardware interface |
+------------+------------+-------------------------------------+
| SPI Master | on-chip | spi |
+------------+------------+-------------------------------------+
| Timers | on-chip | counter |
+------------+------------+-------------------------------------+
| Watchdog | on-chip | watchdog |
+------------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+------------+------------+-------------------------------------+
| LEDC | on-chip | pwm |
+------------+------------+-------------------------------------+
| SPI DMA | on-chip | spi |
+------------+------------+-------------------------------------+
| TWAI | on-chip | can |
+------------+------------+-------------------------------------+
| USB-CDC | on-chip | serial |
+------------+------------+-------------------------------------+
| ADC | on-chip | adc |
+------------+------------+-------------------------------------+
| Wi-Fi | on-chip | |
+------------+------------+-------------------------------------+
| Bluetooth | on-chip | |
+------------+------------+-------------------------------------+
.. image:: img/esp32c3_luatos_core_pinfunc.jpg
:align: center
:alt: esp32c3_luatos_core_pinfunc
System requirements
*******************
Prerequisites
=============
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
*******************
Simple boot
===========
The board could be loaded using the single binary image, without 2nd stage bootloader.
It is the default option when building the application without additional configuration.
.. note::
Simple boot does not provide any security features nor OTA updates.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: esp32c3_luatos_core
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32c3_luatos_core
:goals: build
The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32c3_luatos_core
:goals: flash
Open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! esp32c3_luatos_core
Debugging
*********
As with much custom hardware, the ESP32-C3 modules require patches to
OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
parameter when building.
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32c3_luatos_core
:goals: build flash
:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32c3_luatos_core
:goals: debug
.. _`OpenOCD ESP32`: path_to_url
References
**********
.. [1] path_to_url
.. _ESP32C3 Core Website: path_to_url
.. _ESP32C3 Technical Reference Manual: path_to_url
.. _ESP32C3 Datasheet: path_to_url
``` | /content/code_sandbox/boards/luatos/esp32c3_luatos_core/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,964 |
```ini
source [find interface/jlink.cfg]
transport select swd
source [find target/swj-dp.tcl]
# Set Chipname
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME kb1200
}
# SWD DAP ID of ENE KB1200 Cortex-M4.
if { [info exists CPUDAPID ] } {
set _CPUDAPID $CPUDAPID
} else {
set _CPUDAPID 0x2ba01477
}
# Work-area is a space in RAM used for flash programming
# By default use 32kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x8000
}
# Debug Adapter Target Settings
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# Initial JTAG/SWD speed
# For safety purposes, set for the lowest cpu clock configuration
# 4MHz / 6 = 666KHz, so use 600KHz for it
adapter speed 600
# For safety purposes, set for the lowest cpu clock configuration
$_TARGETNAME configure -event reset-start {adapter speed 600}
# use sysresetreq to perform a system reset
cortex_m reset_config sysresetreq
# ENE internal spi flash
flash bank ispif eneispif 0x60000000 0 0 0 $_TARGETNAME 0x50101000
``` | /content/code_sandbox/boards/ene/kb1200_evb/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 420 |
```restructuredtext
.. _boards-wiznet:
WIZnet
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/wiznet/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```restructuredtext
.. _ene_kb1200_evb:
ENE KB1200_EVB
##############
Overview
********
The KB1200_EVB kit is a development platform to evaluate the
ENE KB1200 series microcontrollers. This board needs to be mated with
part number KB1200.
Hardware
********
- ARM Cortex-M4F Processor
- 512KB Flash and 320KB RAM
- ADC & GPIO headers
- SER1, SER2 and SER3
- FAN PWM interface
- ENE Debug interface
Supported Features
==================
The following features are supported:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc controller |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c port/controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| PMU | on-chip | power management |
+-----------+------------+-------------------------------------+
| PSL | on-chip | power switch logic |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pulse width modulator |
+-----------+------------+-------------------------------------+
| TACH | on-chip | tachometer sensor |
+-----------+------------+-------------------------------------+
| SER | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
System Clock
============
The KB1200 MCU is configured to use the 96Mhz internal oscillator with the
on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz.
See Processor clock control register (refer 5.1 General Configuration)
Programming and Debugging
*************************
Flashing
========
If the correct headers are installed, this board supports SWD Debug Interface.
To flash with SWD, install the drivers for your programmer, for example:
SEGGER J-link's drivers are at path_to_url
Debugging
=========
Use SWD with a J-Link
References
==========
.. target-notes::
``` | /content/code_sandbox/boards/ene/kb1200_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 591 |
```cmake
# This configuration allows selecting what debug adapter debugging w5500_evb_pico
# by a command-line argument.
# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd'
# adapter described in "Getting started with Raspberry Pi Pico".
# And any other SWD debug adapter might also be usable with this configuration.
# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments.
# e.g.) west build -b w5500_evb_pico -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd
# The value is treated as a part of an interface file name that
# the debugger's configuration file.
# The value must be the 'stem' part of the name of one of the files
# in the openocd interface configuration file.
# The setting is store to CMakeCache.txt.
if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "")
set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap")
endif()
board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]")
board_runner_args(openocd --cmd-pre-init "transport select swd")
board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]")
# The adapter speed is expected to be set by interface configuration.
# But if not so, set 2000 to adapter speed.
board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000")
board_runner_args(jlink "--device=RP2040_M0_0")
board_runner_args(uf2 "--board-id=RPI-RP2")
board_runner_args(pyocd "--target=rp2040")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 456 |
```unknown
config BOARD_W5500_EVB_PICO
select SOC_RP2040
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```yaml
identifier: w5500_evb_pico
name: Wiznet W5500 Evaluation Board
type: mcu
arch: arm
flash: 16384
ram: 264
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- uart
- gpio
- adc
- i2c
- spi
- hwinfo
- watchdog
- pwm
- flash
- dma
- counter
- clock
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_P0>;
};
group2 {
pinmux = <UART0_RX_P1>;
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_P4>, <I2C0_SCL_P5>;
input-enable;
input-schmitt-enable;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <I2C1_SDA_P6>, <I2C1_SCL_P7>;
input-enable;
input-schmitt-enable;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <SPI0_CSN_P17>, <SPI0_SCK_P18>, <SPI0_TX_P19>;
};
group2 {
pinmux = <SPI0_RX_P16>;
input-enable;
};
};
pwm_ch4b_default: pwm_ch4b_default {
group1 {
pinmux = <PWM_4B_P25>;
};
};
adc_default: adc_default {
group1 {
pinmux = <ADC_CH0_P26>, <ADC_CH1_P27>, <ADC_CH2_P28>, <ADC_CH3_P29>;
input-enable;
};
};
clocks_default: clocks_default {
};
};
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 364 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
CONFIG_USE_DT_CODE_PARTITION=y
CONFIG_BUILD_OUTPUT_UF2=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_RESET=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
board:
name: w5500_evb_pico
vendor: wiznet
socs:
- name: rp2040
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
if BOARD_W5500_EVB_PICO
config RP2_FLASH_W25Q080
default y
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
if I2C_DW
config I2C_DW_CLOCK_SPEED
default 125
endif # I2C_DW
config USB_SELF_POWERED
default n
endif # BOARD_W5500_EVB_PICO
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```ini
# Checking and set 'adapter speed'.
# Set the adaptor speed, if unset, and given as an argument.
proc set_adapter_speed_if_not_set { speed } {
puts "checking adapter speed..."
if { [catch {adapter speed} ret] } {
adapter speed $speed
}
}
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
/*
*
*/
/dts-v1/;
#include <freq.h>
#include <rpi_pico/rp2040.dtsi>
#include "w5500_evb_pico-pinctrl.dtsi"
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
/ {
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,flash-controller = &ssi;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,code-partition = &code_partition;
};
pico_header: connector {
compatible = "raspberrypi,pico-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 0 0>, /* GP0 */
<1 0 &gpio0 1 0>, /* GP1 */
<2 0 &gpio0 2 0>, /* GP2 */
<3 0 &gpio0 3 0>, /* GP3 */
<4 0 &gpio0 4 0>, /* GP4 */
<5 0 &gpio0 5 0>, /* GP5 */
<6 0 &gpio0 6 0>, /* GP6 */
<7 0 &gpio0 7 0>, /* GP7 */
<8 0 &gpio0 8 0>, /* GP8 */
<9 0 &gpio0 9 0>, /* GP9 */
<10 0 &gpio0 10 0>, /* GP10 */
<11 0 &gpio0 11 0>, /* GP11 */
<12 0 &gpio0 12 0>, /* GP12 */
<13 0 &gpio0 13 0>, /* GP13 */
<14 0 &gpio0 14 0>, /* GP14 */
<15 0 &gpio0 15 0>, /* GP15 */
<16 0 &gpio0 16 0>, /* GP16 */
<17 0 &gpio0 17 0>, /* GP17 */
<18 0 &gpio0 18 0>, /* GP18 */
<19 0 &gpio0 19 0>, /* GP19 */
<20 0 &gpio0 20 0>, /* GP20 */
<21 0 &gpio0 21 0>, /* GP21 */
<22 0 &gpio0 22 0>, /* GP22 */
<26 0 &gpio0 26 0>, /* GP26 */
<27 0 &gpio0 27 0>, /* GP27 */
<28 0 &gpio0 28 0>; /* GP28 */
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
label = "LED";
};
};
pwm_leds {
compatible = "pwm-leds";
status = "disabled";
pwm_led0: pwm_led_0 {
pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "PWM_LED";
};
};
aliases {
led0 = &led0;
pwm-led0 = &pwm_led0;
watchdog0 = &wdt0;
};
};
&flash0 {
/* 16MB of flash minus the 0x100 used for
* the second stage bootloader
*/
reg = <0x10000000 DT_SIZE_M(16)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserved memory for the second stage bootloader */
second_stage_bootloader: partition@0 {
label = "second_stage_bootloader";
reg = <0x00000000 0x100>;
read-only;
};
/*
* Usable flash. Starts at 0x100, after the bootloader. The partition
* size is 16MB minus the 0x100 bytes taken by the bootloader.
*/
code_partition: partition@100 {
label = "code-partition";
reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
read-only;
};
};
};
&clocks {
pinctrl-0 = <&clocks_default>;
pinctrl-names = "default";
};
&uart0 {
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&i2c0 {
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&i2c1 {
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
status = "disabled";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi0 {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
ethernet: w5500@0 {
compatible = "wiznet,w5500";
reg = <0x0>;
spi-max-frequency = <50000000>;
int-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
local-mac-address = [00 00 00 01 02 03];
status = "okay";
};
};
&timer {
status = "okay";
};
&wdt0 {
status = "okay";
};
&adc {
status = "okay";
pinctrl-0 = <&adc_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usbd {
status = "okay";
};
&pwm {
pinctrl-0 = <&pwm_ch4b_default>;
pinctrl-names = "default";
divider-int-0 = <255>;
};
&vreg {
regulator-always-on;
regulator-allowed-modes = <REGULATOR_RPI_PICO_MODE_NORMAL>;
};
pico_spi: &spi0 {};
pico_i2c0: &i2c0 {};
pico_i2c1: &i2c1 {};
``` | /content/code_sandbox/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,559 |
```restructuredtext
.. _boards-space-cubics:
Space Cubics
############
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/sc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```cmake
board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/sc/scobc_module1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_ARM_MPU=n
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
CONFIG_FLASH_SIZE=0
CONFIG_FLASH_BASE_ADDRESS=0x0
``` | /content/code_sandbox/boards/sc/scobc_module1/scobc_module1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
/*
*
*/
/dts-v1/;
#include <arm/armv7-m.dtsi>
#include <mem.h>
/ {
model = "Space Cubics OBC module 1";
chosen {
zephyr,console = &uartlite0;
zephyr,shell-uart = &uartlite0;
zephyr,sram = &hrmem;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
soc {
hrmem: memory@0 {
compatible = "sc,hrmem";
reg = <0x00000000 DT_SIZE_K(128)>;
};
uartlite0: uartlite@50010000 {
compatible = "xlnx,xps-uartlite-1.00.a";
interrupts = <0 0>;
reg = <0x50010000 0x10000>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};
``` | /content/code_sandbox/boards/sc/scobc_module1/scobc_module1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 326 |
```unknown
# Space Cubics OBC module 1 configuration
config BOARD_SCOBC_MODULE1
select SOC_DESIGNSTART_FPGA_CORTEX_M3
``` | /content/code_sandbox/boards/sc/scobc_module1/Kconfig.scobc_module1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
board:
name: scobc_module1
vendor: spacecubics
socs:
- name: designstart_fpga_cortex_m3
``` | /content/code_sandbox/boards/sc/scobc_module1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
# Space Cubics OBC module 1
if BOARD_SCOBC_MODULE1
config CPU_CORTEX_M_HAS_SYSTICK
default y
config CPU_HAS_ARM_MPU
default y
config NUM_IRQS
default 7
endif # BOARD_SCOBC_MODULE1
``` | /content/code_sandbox/boards/sc/scobc_module1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```yaml
identifier: scobc_module1
name: Space Cubics OBC module 1
type: mcu
arch: arm
toolchain:
- zephyr
supported:
- uart
``` | /content/code_sandbox/boards/sc/scobc_module1/scobc_module1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
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