text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
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```cmake
# BMD-360-EVAL board configuration
board_runner_args(jlink "--device=nRF52811_xxAA" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
# BMD-360-EVAL board configuration
config BOARD_UBX_BMD360EVAL
select SOC_NRF52811_QFAA
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# BMD-360-EVAL board configuration
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```yaml
identifier: ubx_bmd360eval/nrf52811
name: UBX_BMD360EVAL_NRF52811
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 24
flash: 192
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_spi
- gpio
- counter
- nvs
- i2c
- pwm
- spi
- watchdog
vendor: u-blox
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: ubx_bmd360eval
vendor: u-blox
socs:
- name: nrf52811
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# BMD-360-EVAL board configuration
if BOARD_UBX_BMD360EVAL
endif # BOARD_UBX_BMD360EVAL
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# BMD-360-EVAL board configuration
# BT_CTLR depends on BT. When BT is enabled we should default to also
# enabling the controller.
config BT_CTLR
default y if BT
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52811_qfaa.dtsi>
#include "ubx_bmd360eval_nrf52811-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "u-blox BMD-360-EVAL EVK nRF52811";
compatible = "u-blox,ubx-bmd360eval-nrf52811";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
label = "Red LED 0";
};
led1: led_1 {
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
label = "Red LED 1";
};
led2: led_2 {
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
label = "Green LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio0 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio0 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 3";
zephyr,code = <INPUT_KEY_3>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 3 0>, /* A0 */
<1 0 &gpio0 4 0>, /* A1 */
<2 0 &gpio0 28 0>, /* A2 */
<3 0 &gpio0 29 0>, /* A3 */
<4 0 &gpio0 30 0>, /* A4 */
<5 0 &gpio0 31 0>, /* A5 */
<6 0 &gpio0 11 0>, /* D0 */
<7 0 &gpio0 12 0>, /* D1 */
<8 0 &gpio0 13 0>, /* D2 */
<9 0 &gpio0 14 0>, /* D3 */
<10 0 &gpio0 15 0>, /* D4 */
<11 0 &gpio0 16 0>, /* D5 */
<12 0 &gpio0 17 0>, /* D6 */
<13 0 &gpio0 18 0>, /* D7 */
<14 0 &gpio0 19 0>, /* D8 */
<15 0 &gpio0 20 0>, /* D9 */
<16 0 &gpio0 22 0>, /* D10 */
<17 0 &gpio0 23 0>, /* D11 */
<18 0 &gpio0 24 0>, /* D12 */
<19 0 &gpio0 25 0>, /* D13 */
<20 0 &gpio0 26 0>, /* D14 */
<21 0 &gpio0 27 0>; /* D15 */
};
arduino_adc: analog-connector {
compatible = "arduino,uno-adc";
#io-channel-cells = <1>;
io-channel-map = <0 &adc 1>, /* A0 = P0.3 = AIN1 */
<1 &adc 2>, /* A1 = P0.4 = AIN2 */
<2 &adc 4>, /* A2 = P0.28 = AIN4 */
<3 &adc 5>, /* A3 = P0.29 = AIN5 */
<4 &adc 6>, /* A4 = P0.30 = AIN6 */
<5 &adc 7>; /* A5 = P0.31 = AIN7 */
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
pwm-led0 = &pwm_led0;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
bootloader-led0 = &led0;
mcuboot-button0 = &button0;
mcuboot-led0 = &led0;
watchdog0 = &wdt0;
};
};
® {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
arduino_serial: &uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_i2c: &i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
/* Arduino compatible PINs */
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_spi: &spi0 {
compatible = "nordic,nrf-spi";
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi0_default>;
pinctrl-1 = <&spi0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0xd000>;
};
slot1_partition: partition@19000 {
label = "image-1";
reg = <0x00019000 0xd000>;
};
scratch_partition: partition@26000 {
label = "image-scratch";
reg = <0x00026000 0x3000>;
};
storage_partition: partition@29000 {
label = "storage";
reg = <0x00029000 0x00007000>;
};
};
};
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,955 |
```restructuredtext
.. _ubx_bmd345eval_nrf52840:
u-blox EVK-BMD-34/38: BMD-345-EVAL
##################################
Overview
********
The BMD-345-EVALhardware provides support for the u-blox BMD-345
Bluetooth 5.0 modules, based on the Nordic Semiconductor nRF52840
ARM Cortex-M4F CPU and Skyworks RFX2411 Front End Module (FEM),
also known as a Power Amplifier / Low Noise Amplifier (PA/LNA).
Both support the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy and 802.15.4)
* :abbr:`RTC (nRF RTC System Clock)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`USB (Universal Serial Bus)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/bmd-345-eval_features.jpg
:align: center
:alt: BMD 345 EVAL
BMD-345-EVAL (Credit: ublox AG)
More information about the BMD-345-EVAL and BMD-345 module can be
found at the `u-blox website`_.
Hardware
********
The BMD-345 on the BMD-345-EVAL contains an internal high-frequency
oscillator at 32MHz. There is also a low frequency (slow)
oscillator of 32.768kHz. The BMD-345 does not include the slow
crystal; however, the BMD-345-EVAL does.
.. note::
When targeting a custom design without a slow crystal, be sure
to modify code to utilize the internal RC oscillator for the
slow clock.
Front End Module
================
BMD-345 utilizes the Skyworks RFX2411 front end module (FEM).
The FEM provides higher output power and better sensitivity.
FEM pin assignments
-------------------
+-------------+--------------+----------+--------+----------+---------+
| GPIO Number | Signal Name | Shutdown | Bypass | Transmit | Receive |
+=============+==============+==========+========+==========+=========+
| P1.05 | TX_EN | Low | Low | High | Low |
+-------------+--------------+----------+--------+----------+---------+
| P1.06 | RX_EN | Low | Low | Low | High |
+-------------+--------------+----------+--------+----------+---------+
| P1.04 | MODE | Low | High | Low | Low |
+-------------+--------------+----------+--------+----------+---------+
| P1.02 | A_SEL | Low | Low | Low | Low |
+-------------+--------------+----------+--------+----------+---------+
Supported Features
==================
The BMD-345-EVAL board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| ADC | on-chip | adc |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth, |
| | | IEEE 802.15.4 |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| USB | on-chip | usb |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
See the `u-blox website`_ for a complete list of BMD-345-EVAL
hardware features.
Connections and IOs
===================
LED
---
* LED1 (red) = P0.13
* LED2 (red) = P0.14
* LED3 (green) = P0.15
* LED4 (green) = P0.16
* D5 (red) = OB LED 1
* D6 (green) = OB LED 2
Push buttons
------------
* BUTTON1 = SW1 = P0.11
* BUTTON2 = SW2 = P0.12
* BUTTON3 = SW3 = P0.24
* BUTTON4 = SW4 = P0.25
* BOOT = SW5 = boot/reset
External Connectors
-------------------
.. figure:: img/bmd-345-eval_pin_out.jpg
:align: center
:alt: BMD-345-EVAL pin-out
.. note::
The pin numbers noted below are referenced to
the pin 1 markings on the BMD-340-EVAL or
BMD-341-EVAL for each header
J-Link Prog Connector (J2)
+-------+--------------+
| PIN # | Signal Name |
+=======+==============+
| 1 | VDD |
+-------+--------------+
| 2 | IMCU_TMSS |
+-------+--------------+
| 3 | GND |
+-------+--------------+
| 4 | IMCU_TCKS |
+-------+--------------+
| 5 | V5V |
+-------+--------------+
| 6 | IMCU_TDOS |
+-------+--------------+
| 7 | Cut off |
+-------+--------------+
| 8 | IMCU_TDIS |
+-------+--------------+
| 9 | Cut off |
+-------+--------------+
| 10 | IMCU_RESET |
+-------+--------------+
Debug OUT (J3)
+-------+----------------+
| PIN # | Signal Name |
+=======+================+
| 1 | EXT_VTG |
+-------+----------------+
| 2 | EXT_SWDIO |
+-------+----------------+
| 3 | GND |
+-------+----------------+
| 4 | EXT_SWDCLK |
+-------+----------------+
| 5 | GND |
+-------+----------------+
| 6 | EXT_SWO |
+-------+----------------+
| 7 | N/C |
+-------+----------------+
| 8 | N/C |
+-------+----------------+
| 9 | EXT_GND_DETECT |
+-------+----------------+
| 10 | EXT_RESET |
+-------+----------------+
Debug IN (J26)
+-------+----------------+
| PIN # | Signal Name |
+=======+================+
| 1 | BMD-340_VCC |
+-------+----------------+
| 2 | BMD-340_SWDIO |
+-------+----------------+
| 3 | GND |
+-------+----------------+
| 4 | BMD-340_SWDCLK |
+-------+----------------+
| 5 | GND |
+-------+----------------+
| 6 | BMD-340_SWO |
+-------+----------------+
| 7 | N/C |
+-------+----------------+
| 8 | N/C |
+-------+----------------+
| 9 | GND |
+-------+----------------+
| 10 | BMD-340_RESET |
+-------+----------------+
Auxiliary (J9)
+-------+----------------+
| PIN # | Signal Name |
+=======+================+
| 1 | P0.10 / NFC2 |
+-------+----------------+
| 2 | P0.09 / NFC1 |
+-------+----------------+
| 3 | P0.08 |
+-------+----------------+
| 4 | P0.07 |
+-------+----------------+
| 5 | P0.06 |
+-------+----------------+
| 6 | P0.05 / AIN3 |
+-------+----------------+
| 7 | P0.01 / XL2 |
+-------+----------------+
| 8 | P0.00 / XL1 |
+-------+----------------+
Auxiliary (J10)
+-------+-------------------+
| PIN # | Signal Name |
+=======+===================+
| 1 | P0.11 / TRACED[2] |
+-------+-------------------+
| 2 | P0.12 / TRACED[1] |
+-------+-------------------+
| 3 | P0.13 |
+-------+-------------------+
| 4 | P0.14 |
+-------+-------------------+
| 5 | P0.15 |
+-------+-------------------+
| 6 | P0.16 |
+-------+-------------------+
| 7 | P0.17 / QSPI_CS |
+-------+-------------------+
| 8 | P0.18 / RESET |
+-------+-------------------+
| 9 | P0.19 / QSPI_CLK |
+-------+-------------------+
| 10 | P0.20 / QSPI_D0 |
+-------+-------------------+
| 11 | P0.21 / QSPI_D1 |
+-------+-------------------+
| 12 | P0.22 / QSPI_D2 |
+-------+-------------------+
| 13 | P0.23 / QSPI_D3 |
+-------+-------------------+
| 14 | P0.24 |
+-------+-------------------+
| 15 | P0.25 |
+-------+-------------------+
| 16 | P1.00 / TRACED[0] |
+-------+-------------------+
| 17 | P1.09 / TRACED[3] |
+-------+-------------------+
| 18 | No connection |
+-------+-------------------+
Arduino Headers
---------------
Power (J5)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-345 Functions |
+=======+==============+=========================+
| 1 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 2 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 3 | RESET | P0.18 / RESET |
+-------+--------------+-------------------------+
| 4 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 5 | V5V | N/A |
+-------+--------------+-------------------------+
| 6 | GND | N/A |
+-------+--------------+-------------------------+
| 7 | GND | N/A |
+-------+--------------+-------------------------+
| 8 | N/C | N/A |
+-------+--------------+-------------------------+
Analog in (J8)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-345 Functions |
+=======+==============+=========================+
| 1 | A0 | P0.03 / AIN1 |
+-------+--------------+-------------------------+
| 2 | A1 | P0.04 / AIN2 |
+-------+--------------+-------------------------+
| 3 | A2 | P0.28 / AIN4 |
+-------+--------------+-------------------------+
| 4 | A3 | P0.29 / AIN5 |
+-------+--------------+-------------------------+
| 5 | A4 | P0.30 / AIN6 |
+-------+--------------+-------------------------+
| 6 | A5 | P0.31 / AIN7 |
+-------+--------------+-------------------------+
Digital I/O (J7)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-345 Functions |
+=======+==============+=========================+
| 1 | D7 | P1.08 |
+-------+--------------+-------------------------+
| 2 | D6 | P1.07 |
+-------+--------------+-------------------------+
| 3 | N/C | N/A |
+-------+--------------+-------------------------+
| 4 | N/C | N/A |
+-------+--------------+-------------------------+
| 5 | N/C | N/A |
+-------+--------------+-------------------------+
| 6 | D2 | P1.03 |
+-------+--------------+-------------------------+
| 7 | N/C | N/A |
+-------+--------------+-------------------------+
| 8 | D0 (RX) | P1.01 |
+-------+--------------+-------------------------+
Digital I/O (J6)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-345 Functions |
+=======+==============+=========================+
| 1 | SCL | P0.27 |
+-------+--------------+-------------------------+
| 2 | SDA | P0.26 |
+-------+--------------+-------------------------+
| 3 | AREF | P0.02 / AIN0 |
+-------+--------------+-------------------------+
| 4 | GND | N/A |
+-------+--------------+-------------------------+
| 5 | D13 (SCK) | P1.15 |
+-------+--------------+-------------------------+
| 6 | D12 (MISO) | P1.14 |
+-------+--------------+-------------------------+
| 7 | D11 (MOSI) | P1.13 |
+-------+--------------+-------------------------+
| 8 | D10 (SS) | P1.12 |
+-------+--------------+-------------------------+
| 9 | D9 | P1.11 |
+-------+--------------+-------------------------+
| 10 | D8 | P1.10 |
+-------+--------------+-------------------------+
J11
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-345 Functions |
+=======+==============+=========================+
| 1 | D12 (MISO) | P0.14 |
+-------+--------------+-------------------------+
| 2 | V5V | N/A |
+-------+--------------+-------------------------+
| 3 | D13 (SCK) | P0.15 |
+-------+--------------+-------------------------+
| 4 | D11 (MOSI) | P0.13 |
+-------+--------------+-------------------------+
| 5 | RESET | N/A |
+-------+--------------+-------------------------+
| 6 | N/A | N/A |
+-------+--------------+-------------------------+
Programming and Debugging
*************************
Applications for the BMD-345-EVAL board
configurations can be built and flashed in the usual way
(see :ref:`build_an_application` and :ref:`application_run`
for more details); however, the standard debugging targets
are not currently available.
Flashing
========
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`. Then build and flash
applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :ref:`hello_world` application.
First, run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the BMD-345-EVAL
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
Then build and flash the application in the usual way.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: ubx_bmd345eval/nrf52840
:goals: build flash
Debugging
=========
Refer to the :ref:`nordic_segger` page to learn about debugging
u-blox boards with a Segger J-LINK-OB IC.
Testing the LEDs and buttons in the BMD-345-EVAL
*****************************************************************
There are 2 samples that allow you to test that the buttons
(switches) and LEDs on the board are working properly with Zephyr:
.. code-block:: console
samples/basic/blinky
samples/basic/button
You can build and flash the examples to make sure Zephyr is running
correctly on your board. The button and LED definitions can be found
in
:zephyr_file:`boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts`.
Using UART1
***********
The following approach can be used when an application needs to use
more than one UART for connecting peripheral devices:
1. Add device tree overlay file to the main directory of your
application:
.. code-block:: devicetree
&pinctrl {
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 14)>,
<NRF_PSEL(UART_RX, 0, 16)>;
};
};
/* required if CONFIG_PM_DEVICE=y */
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 14)>,
<NRF_PSEL(UART_RX, 0, 16)>;
low-power-enable;
};
};
};
&uart1 {
compatible = "nordic,nrf-uarte";
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
};
In the overlay file above, pin P0.16 is used for RX and P0.14 is
used for TX
2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))``
Overlay file naming
===================
The file has to be named ``<board>.overlay`` and placed in the app
main directory to be picked up automatically by the device tree
compiler.
Selecting the pins
==================
Pins can be configured in the board pinctrl file. To see the available mappings,
open the data sheet for the BMD-345 at the `u-blox website`_, Section 2
'Pin definition'. In the table 3 select the pins marked 'GPIO'.
Note that pins marked as 'Standard drive, low frequency I/O only
(<10 kH' can only be used in under-10KHz applications.
They are not suitable for 115200 speed of UART.
.. note:
Pins are defined according to the "nRF52" pin number, not the module
pad number.
References
**********
.. target-notes::
.. _u-blox website: path_to_url
``` | /content/code_sandbox/boards/u-blox/ubx_bmd345eval/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,448 |
```restructuredtext
.. _boards-maker-diary:
Maker Diary
###########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/makerdiary/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```cmake
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```unknown
/*
*
*/
/* Flash partition table compatible with Nordic nRF5 bootloader */
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* MCUboot placed after Nordic MBR.
* The size of this partition ensures that MCUBoot
* can be built with CDC ACM support and w/o optimizations.
*/
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000f000>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x0005e000>;
};
slot1_partition: partition@6e000 {
label = "image-1";
reg = <0x0006e000 0x0005e000>;
};
storage_partition: partition@cc000 {
label = "storage";
reg = <0x000cc000 0x00004000>;
};
scratch_partition: partition@d0000 {
label = "image-scratch";
reg = <0x000d0000 0x00010000>;
};
/* Nordic nRF5 bootloader <0xe0000 0x1c000>
*
* In addition, the last and second last flash pages
* are used by the nRF5 bootloader and MBR to store settings.
*/
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/fstab-stock.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 337 |
```unknown
/*
*
*/
/* Flash partition table without support for Nordic nRF5 bootloader */
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* The size of this partition ensures that MCUBoot can be built
* with an RTT console, CDC ACM support, and w/o optimizations.
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00012000>;
};
slot0_partition: partition@12000 {
label = "image-0";
reg = <0x00012000 0x00069000>;
};
slot1_partition: partition@7b000 {
label = "image-1";
reg = <0x0007b000 0x00069000>;
};
scratch_partition: partition@e4000 {
label = "image-scratch";
reg = <0x000e4000 0x00018000>;
};
storage_partition: partition@fc000 {
label = "storage";
reg = <0x000fc000 0x00004000>;
};
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 277 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 7)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```yaml
board:
name: nrf52840_mdk_usb_dongle
vendor: makerdiary
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```restructuredtext
.. _ubx_bmd360eval_nrf52811:
u-blox EVK-BMD-360: BMD-360-EVAL
################################
Overview
********
The BMD-360-EVAL hardware provides support for the
u-blox BMD-360 Bluetooth 5 module, based on The
Nordic Semiconductor nRF52811 ARM Cortex-M4 CPU and
the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy)
* :abbr:`RTC (nRF RTC System Clock)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/BMD-30-33-35-36-EVAL.jpg
:align: center
:alt: BMD-300-EVAL
BMD-300-EVAL (Credit: u-blox AG)
.. note::
The BMD-360-EVAL shares the same pin headers and assignments as the
BMD-300-EVAL. The BMD-300-EVAL is shown here.
More information about the BMD-360-EVAL and the BMD-360 module
can be found at the `u-blox website`_.
Hardware
********
The BMD-360 on the BMD-360-EVAL contains an internal
high-frequency oscillator at 32MHz. There is also a low frequency
(slow) oscillator of 32.768kHz. The BMD-360 itself does not include
the slow crystal; however, the BMD-360-EVAL does.
.. note::
When targeting a custom design without a slow crystal,
be sure to modify code to utilize the internal RC
oscillator for the slow clock.
Supported Features
==================
The BMD-360-EVAL configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| ADC | on-chip | adc |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
See the `u-blox website`_ for a complete list of
BMD-360-EVAL hardware features.
Connections and IOs
===================
LED
---
* LED1 (red) = P0.17
* LED2 (red) = P0.18
* LED3 (green) = P0.19
* LED4 (green) = P0.20
* D5 (red) = OB LED 1
* D6 (green) = OB LED 2
Push buttons
------------
* BUTTON1 = SW1 = P0.13
* BUTTON2 = SW2 = P0.14
* BUTTON3 = SW3 = P0.15
* BUTTON4 = SW4 = P0.16
* BOOT = SW5 = boot/reset
External Connectors
-------------------
.. figure:: img/bmd-300-eval_pin_out.jpg
:align: center
:alt: BMD-300-EVAL pin-out
BMD-300-EVAL pin-out (Credit: u-blox AG)
.. note::
The BMD-360-EVAL shares the same pin headers and assignments
as the BMD-300-EVAL. The BMD-300-EVAL is shown here.
.. note::
The pin numbers noted below are referenced to
the pin 1 markings on the BMD-360-EVAL
for each header
J-Link Prog Connector (J2)
+-------+--------------+
| PIN # | Signal Name |
+=======+==============+
| 1 | VDD |
+-------+--------------+
| 2 | IMCU_TMSS |
+-------+--------------+
| 3 | GND |
+-------+--------------+
| 4 | IMCU_TCKS |
+-------+--------------+
| 5 | V5V |
+-------+--------------+
| 6 | IMCU_TDOS |
+-------+--------------+
| 7 | Cut off |
+-------+--------------+
| 8 | IMCU_TDIS |
+-------+--------------+
| 9 | Cut off |
+-------+--------------+
| 10 | IMCU_RESET |
+-------+--------------+
Debug OUT (J3)
+-------+----------------+
| PIN # | Signal Name |
+=======+================+
| 1 | EXT_VTG |
+-------+----------------+
| 2 | EXT_SWDIO |
+-------+----------------+
| 3 | GND |
+-------+----------------+
| 4 | EXT_SWDCLK |
+-------+----------------+
| 5 | GND |
+-------+----------------+
| 6 | EXT_SWO |
+-------+----------------+
| 7 | N/C |
+-------+----------------+
| 8 | N/C |
+-------+----------------+
| 9 | EXT_GND_DETECT |
+-------+----------------+
| 10 | EXT_RESET |
+-------+----------------+
Auxiliary (J9)
+-------+----------------+
| PIN # | Signal Name |
+=======+================+
| 1 | P0.10 |
+-------+----------------+
| 2 | P0.09 |
+-------+----------------+
| 3 | P0.08 |
+-------+----------------+
| 4 | P0.07 |
+-------+----------------+
| 5 | P0.06 |
+-------+----------------+
| 6 | P0.05 / AIN3 |
+-------+----------------+
| 7 | P0.21 / RESET |
+-------+----------------+
| 8 | P0.01 / XL2 |
+-------+----------------+
| 9 | P0.00 / XL1 |
+-------+----------------+
| 10 | GND |
+-------+----------------+
Arduino Headers
---------------
Power (J5)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-360 Functions |
+=======+==============+=========================+
| 1 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 2 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 3 | RESET | P0.21 / RESET |
+-------+--------------+-------------------------+
| 4 | VSHLD | N/A |
+-------+--------------+-------------------------+
| 5 | V5V | N/A |
+-------+--------------+-------------------------+
| 6 | GND | N/A |
+-------+--------------+-------------------------+
| 7 | GND | N/A |
+-------+--------------+-------------------------+
| 8 | N/C | N/A |
+-------+--------------+-------------------------+
Analog in (J8)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-360 Functions |
+=======+==============+=========================+
| 1 | A0 | P0.03 / AIN1 |
+-------+--------------+-------------------------+
| 2 | A1 | P0.04 / AIN2 |
+-------+--------------+-------------------------+
| 3 | A2 | P0.28 / AIN4 |
+-------+--------------+-------------------------+
| 4 | A3 | P0.29 / AIN5 |
+-------+--------------+-------------------------+
| 5 | A4 | P0.30 / AIN6 |
+-------+--------------+-------------------------+
| 6 | A5 | P0.31 / AIN7 |
+-------+--------------+-------------------------+
Digital I/O (J7)
+-------+--------------+----------------------------+
| PIN # | Signal Name | BMD-360 Functions |
+=======+==============+============================+
| 1 | D7 | P0.18 |
+-------+--------------+----------------------------+
| 2 | D6 | P0.17 |
+-------+--------------+----------------------------+
| 3 | D5 | P0.16 |
+-------+--------------+----------------------------+
| 4 | D4 | P0.15 |
+-------+--------------+----------------------------+
| 5 | D3 | P0.14 |
+-------+--------------+----------------------------+
| 6 | D2 | P0.13 |
+-------+--------------+----------------------------+
| 7 | D1 (TX) | P0.12 |
+-------+--------------+----------------------------+
| 8 | D0 (RX) | P0.11 |
+-------+--------------+----------------------------+
Digital I/O (J6)
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-360 Functions |
+=======+==============+=========================+
| 1 | SCL | P0.27 |
+-------+--------------+-------------------------+
| 2 | SDA | P0.26 |
+-------+--------------+-------------------------+
| 3 | AREF | P0.02 / AIN0 |
+-------+--------------+-------------------------+
| 4 | GND | N/A |
+-------+--------------+-------------------------+
| 5 | D13 (SCK) | P0.25 |
+-------+--------------+-------------------------+
| 6 | D12 (MISO) | P0.24 |
+-------+--------------+-------------------------+
| 7 | D11 (MOSI) | P0.23 |
+-------+--------------+-------------------------+
| 8 | D10 (SS) | P0.22 |
+-------+--------------+-------------------------+
| 9 | D9 | P0.20 |
+-------+--------------+-------------------------+
| 10 | D8 | P0.19 |
+-------+--------------+-------------------------+
J11
+-------+--------------+-------------------------+
| PIN # | Signal Name | BMD-360 Functions |
+=======+==============+=========================+
| 1 | D12 (MISO) | P0.24 |
+-------+--------------+-------------------------+
| 2 | V5V | N/A |
+-------+--------------+-------------------------+
| 3 | D13 (SCK) | P0.25 |
+-------+--------------+-------------------------+
| 4 | D11 (MOSI) | P0.23 |
+-------+--------------+-------------------------+
| 5 | RESET | N/A |
+-------+--------------+-------------------------+
| 6 | N/A | N/A |
+-------+--------------+-------------------------+
Programming and Debugging
*************************
Flashing
========
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`. Then build and flash
applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :ref:`hello_world` application.
First, run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the
BMD-360-EVAL can be found. For example, under Linux,
:code:`/dev/ttyACM0`.
Then build and flash the application in the usual way.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: ubx_bmd360eval/nrf52811
:goals: build flash
Debugging
=========
Refer to the :ref:`nordic_segger` page to learn about debugging
u-blox boards with a Segger J-LINK-OB IC.
Testing the LEDs and buttons in the BMD-360-EVAL
************************************************
There are 2 samples that allow you to test that the buttons
(switches) and LEDs on the board are working properly with Zephyr:
.. code-block:: console
samples/basic/blinky
samples/basic/button
You can build and flash the examples to make sure Zephyr is
running correctly on your board. The button and LED definitions
can be found in :zephyr_file:`boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts`.
References
**********
.. target-notes::
.. _u-blox website: path_to_url
``` | /content/code_sandbox/boards/u-blox/ubx_bmd360eval/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,149 |
```yaml
identifier: nrf52840_mdk_usb_dongle
name: nRF52840-MDK-USB-Dongle
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- usb_device
- ble
- watchdog
- counter
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Console
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "nrf52840_mdk_usb_dongle-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "nRF52840 MDK USB Dongle";
compatible = "nrf52840_mdk_usb_dongle";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0_red: led_0 {
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
label = "Red LED 0";
};
led0_green: led_1 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Green LED 0";
};
led0_blue: led_2 {
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
label = "Blue LED 0";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
green_pwm_led: pwm_led_1 {
pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
blue_pwm_led: pwm_led_2 {
pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
buttons {
compatible = "gpio-keys";
reset_button: button_0 {
gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "reset button";
zephyr,code = <INPUT_KEY_0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0_red;
led1 = &led0_green;
led2 = &led0_blue;
led0-red = &led0_red;
led0-green = &led0_green;
led0-blue = &led0_blue;
pwm-led0 = &red_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &blue_pwm_led;
red-pwm-led = &red_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
watchdog0 = &wdt0;
};
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&gpiote {
status = "okay";
};
&uicr {
nfct-pins-as-gpios;
gpio-as-nreset;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&ieee802154 {
status = "okay";
};
/* Include flash partition table.
* Two partition tables are available:
* fstab-stock -compatible with Nordic nRF5 bootloader, default
* fstab-debugger -to use an external debugger, w/o the nRF5 bootloader
*/
#include "fstab-stock.dtsi"
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 930 |
```unknown
# nRF52840 MDK USB Dongle board configuration
config BOARD_NRF52840_MDK_USB_DONGLE
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
# nRF52840 MDK USB Dongle board configuration
#
#
#
if BOARD_NRF52840_MDK_USB_DONGLE
# To let the nRF5 bootloader load an application, the application
# must be linked after Nordic MBR, that is factory-programmed on the board.
# Nordic nRF5 bootloader exists outside of the partitions specified in the
# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application
# correctly, after Nordic MBR.
# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION
# which will make it link into the correct partition specified in DTS file,
# so no override is necessary.
config FLASH_LOAD_OFFSET
default 0x1000
depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION
if USB_DEVICE_STACK
# Enable UART driver, needed for CDC ACM
config SERIAL
default y
endif # USB_DEVICE_STACK
config BT_CTLR
default BT
endif # BOARD_NRF52840_MDK_USB_DONGLE
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 221 |
```unknown
# nRF52840 MDK USB Dongle board configuration
config BOARD_HAS_NRF5_BOOTLOADER
bool "Board has nRF5 bootloader"
default y
depends on BOARD_NRF52840_MDK_USB_DONGLE
help
If selected, applications are linked so that they can be loaded by Nordic
nRF5 bootloader.
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```cmake
board_runner_args(pyocd "--target=nrf52840")
set(OPENOCD_NRF5_INTERFACE "cmsis-dap")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# nRF52840-MDK board configuration
config BOARD_NRF52840_MDK
select SOC_NRF52840_QIAA
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/Kconfig.nrf52840_mdk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/nrf52840_mdk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```restructuredtext
.. _nrf52840_mdk_usb_dongle:
nRF52840 MDK USB Dongle
#######################
Overview
********
The nRF52840 MDK USB Dongle is a small and low-cost development platform enabled
by the nRF5240 multiprotocol SoC in a convenient USB dongle form factor.
The design features a programmable user button, RGB LED, up to 12 GPIOs and 2.4G
Chip antenna on board. It can be used as a low-cost
Bluetooth5/Tread/802.15.4/ANT/2.4GHz multiprotocol node or development
board. Alternatively the USB Dongle can be used as a Network Co-Processor(NCP)
with a simple connection to a PC or other USB enabled device.
.. figure:: nrf52840-mdk-usb-dongle-pinout.jpg
:align: center
:alt: nRF52840 MDK USB Dongle
nRF52840 MDK USB Dongle
See `nrf52840-mdk-usb-dongle website`_ for more information about the development
board and `nRF52840 website`_ for the official reference on the IC itself.
References
**********
.. target-notes::
.. _nRF52840 website:
path_to_url
.. _nrf52840-mdk-usb-dongle website:
path_to_url
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 298 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
identifier: nrf52840_mdk
name: nRF52840-MDK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- usb_device
- ble
- pwm
vendor: makerdiary
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```yaml
board:
name: nrf52840_mdk
vendor: makerdiary
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
low-power-enable;
};
};
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
<NRF_PSEL(TWIM_SCL, 0, 31)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
<NRF_PSEL(TWIM_SCL, 0, 31)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
<NRF_PSEL(PWM_OUT1, 0, 23)>,
<NRF_PSEL(PWM_OUT2, 0, 24)>;
nordic,invert;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
<NRF_PSEL(PWM_OUT1, 0, 23)>,
<NRF_PSEL(PWM_OUT2, 0, 24)>;
low-power-enable;
};
};
qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 1, 3)>,
<NRF_PSEL(QSPI_IO0, 1, 5)>,
<NRF_PSEL(QSPI_IO1, 1, 4)>,
<NRF_PSEL(QSPI_IO2, 1, 2)>,
<NRF_PSEL(QSPI_IO3, 1, 1)>,
<NRF_PSEL(QSPI_CSN, 1, 6)>;
};
};
qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 1, 3)>,
<NRF_PSEL(QSPI_IO0, 1, 5)>,
<NRF_PSEL(QSPI_IO1, 1, 4)>,
<NRF_PSEL(QSPI_IO2, 1, 2)>,
<NRF_PSEL(QSPI_IO3, 1, 1)>;
low-power-enable;
};
group2 {
psels = <NRF_PSEL(QSPI_CSN, 1, 6)>;
low-power-enable;
bias-pull-up;
};
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 900 |
```unknown
# nRF52840-MDK board configuration
if BOARD_NRF52840_MDK
config BT_CTLR
default BT
endif # BOARD_NRF52840_MDK
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```restructuredtext
.. _nrf52840_mdk:
nRF52840-mdk
#################
Overview
********
The nRF52840-MDK is a versatile, easy-to-use IoT hardware platform for
Bluetooth 5, Bluetooth Mesh, Thread, IEEE 802.15.4, ANT and 2.4GHz proprietary
applications using the nRF52840 SoC.
The development kit comes with a fully integrated debugger (also known as
DAPLink) that provides USB drag-and-drop programming, USB Virtual COM port
and CMSIS-DAP interface.
The kit contains a Microchip USB 2.0 Hi-Speed hub controller with two downstream
ports: one for DAPLink interface and one for nRF52840 USB device controller.
The kit also features ultra-low power 64-Mb QSPI FLASH memory, programmable
user button, RGB LED, up to 24 GPIOs, antenna selection for custom applications.
See `nRF52840-mdk website`_ for more information about the development
board and `nRF52840 website`_ for the official reference on the IC itself.
References
**********
.. target-notes::
.. _nRF52840 website: path_to_url
.. _nRF52840-mdk website: path_to_url
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 263 |
```cmake
board_runner_args(pyocd "--target=nrf52832")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: nrf52832_mdk
name: nRF52832-MDK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- pwm
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
# nRF52832-MDK board configuration
config BOARD_NRF52832_MDK
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/Kconfig.nrf52832_mdk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/nrf52832_mdk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: nrf52832_mdk
vendor: makerdiary
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "nrf52840_mdk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "nRF52840-MDK Dev Kit";
compatible = "nordic,pca10056-dk";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0_green: led_0 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Green LED 0";
};
led1_red: led_1 {
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
label = "Red LED 1";
};
led2_blue: led_2 {
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
label = "Blue LED 2";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0_green: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Green PWM LED 0";
};
pwm_led1_red: pwm_led_1 {
pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Red PWM LED 1";
};
pwm_led2_blue: pwm_led_2 {
pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Blue PWM LED 2";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 0";
zephyr,code = <INPUT_KEY_0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
sw0 = &button0;
led0 = &led0_green;
led1 = &led1_red;
led2 = &led2_blue;
led0-green = &led0_green;
led1-red = &led1_red;
led1-blue = &led2_blue;
pwm-led0 = &pwm_led0_green;
pwm-led1 = &pwm_led1_red;
pwm-led2 = &pwm_led2_blue;
green-pwm-led = &pwm_led0_green;
red-pwm-led = &pwm_led1_red;
blue-pwm-led = &pwm_led2_blue;
watchdog0 = &wdt0;
};
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uart";
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c1 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&qspi {
status = "okay";
pinctrl-0 = <&qspi_default>;
pinctrl-1 = <&qspi_sleep>;
pinctrl-names = "default", "sleep";
mx25r64: mx25r6435f@0 {
compatible = "nordic,qspi-nor";
reg = <0>;
writeoc = "pp4io";
readoc = "read4io";
sck-frequency = <8000000>;
jedec-id = [c2 28 17];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};
&ieee802154 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
scratch_partition: partition@da000 {
label = "image-scratch";
reg = <0x000da000 0x0001e000>;
};
/*
* The flash starting at 0x000f8000 and ending at
* 0x000fffff is reserved for use by the application.
*/
/*
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
``` | /content/code_sandbox/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,681 |
```unknown
# nRF52832-MDK board configuration
if BOARD_NRF52832_MDK
config BT_CTLR
default BT
endif # BOARD_NRF52832_MDK
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>,
<NRF_PSEL(UART_RTS, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 7)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
<NRF_PSEL(TWIM_SCL, 0, 27)>;
low-power-enable;
};
};
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
<NRF_PSEL(TWIM_SCL, 0, 31)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
<NRF_PSEL(TWIM_SCL, 0, 31)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
<NRF_PSEL(PWM_OUT1, 0, 23)>,
<NRF_PSEL(PWM_OUT2, 0, 24)>;
nordic,invert;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
<NRF_PSEL(PWM_OUT1, 0, 23)>,
<NRF_PSEL(PWM_OUT2, 0, 24)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 615 |
```restructuredtext
.. _nrf52832_mdk:
nRF52832-mdk
#################
Overview
********
The nrf52832_mdk board is a fully open-source, versatile single board
development kit for Bluetooth low energy, ANT and 2.4GHz proprietary
applications using the nRF52832 SoC.
The kit gives access to 24 I/Os and interfaces via headers and has a
RGB LED which is user-programmable. It also has a 2.4GHz chip antenna
onboard which is quite convenient to develop IoT wireless applications.
See `nRF52832-mdk website`_ for more information about the development
board and `nRF52832 website`_ for the official reference on the IC itself.
References
**********
.. target-notes::
.. _nRF52832 website: path_to_url
.. _nRF52832-mdk website: path_to_url
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 189 |
```restructuredtext
.. _boards-franzininho:
Franzininho
###########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/franzininho/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
# ESP32S2 Franzininho board configuration
config BOARD_ESP32S2_FRANZININHO
select SOC_ESP32S2_WROOM
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: esp32s2_franzininho
name: ESP32-S2 Franzininho
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- i2c
- watchdog
- uart
- pinmux
- nvs
testing:
ignore_tags:
- heap
- net
- bluetooth
vendor: franzininho
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "nrf52832_mdk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "nRF52832-MDK Micro Dev Kit";
compatible = "nrf52832-mdk";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
led0_green: led_0 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Green LED 0";
};
led1_red: led_1 {
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
label = "Red LED 1";
};
led2_blue: led_2 {
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
label = "Blue LED 1";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0_green: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Green PWM LED 0";
};
pwm_led1_red: pwm_led_1 {
pwms = <&pwm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Red PWM LED 1";
};
pwm_led2_blue: pwm_led_2 {
pwms = <&pwm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "Blue PWM LED 1";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button switch 0";
zephyr,code = <INPUT_KEY_0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
sw0 = &button0;
led0 = &led0_green;
led1 = &led1_red;
led2 = &led2_blue;
led0-green = &led0_green;
led1-red = &led1_red;
led2-blue = &led2_blue;
pwm-led0 = &pwm_led0_green;
pwm-led1 = &pwm_led1_red;
pwm-led2 = &pwm_led2_blue;
green-pwm-led = &pwm_led0_green;
red-pwm-led = &pwm_led1_red;
blue-pwm-led = &pwm_led2_blue;
watchdog0 = &wdt0;
};
};
® {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
compatible = "nordic,nrf-uart";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c1 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x32000>;
};
slot1_partition: partition@3e000 {
label = "image-1";
reg = <0x0003E000 0x32000>;
};
scratch_partition: partition@70000 {
label = "image-scratch";
reg = <0x00070000 0xa000>;
};
storage_partition: partition@7a000 {
label = "storage";
reg = <0x0007a000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,237 |
```yaml
board:
name: esp32s2_franzininho
vendor: espressif
socs:
- name: esp32s2
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32s2-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32s2-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO43>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO44>;
bias-pull-up;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO13>,
<SPIM2_SCLK_GPIO12>,
<SPIM2_CSEL_GPIO10>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO11>;
output-low;
};
};
spim3_default: spim3_default {
group1 {
pinmux = <SPIM3_MISO_GPIO37>,
<SPIM3_SCLK_GPIO36>,
<SPIM3_CSEL_GPIO34>;
};
group2 {
pinmux = <SPIM3_MOSI_GPIO35>;
output-low;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO8>,
<I2C0_SCL_GPIO9>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <I2C1_SDA_GPIO3>,
<I2C1_SCL_GPIO4>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
};
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 417 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# ESP32S2 Franzininho board configuration
config ENTROPY_GENERATOR
default y
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 32768 if WIFI
default 4096
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32s2/esp32s2_wroom.dtsi>
#include "esp32s2_franzininho-pinctrl.dtsi"
/ {
model = "ESP32S2 Franzininho";
compatible = "espressif,esp32s2";
aliases {
led0 = &user_led_0;
led1 = &user_led_1;
i2c-0 = &i2c0;
watchdog0 = &wdt0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
user_led_0: led_0 {
gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
label = "User - LED0";
};
user_led_1: led_1 {
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
label = "User - LED1";
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&timer2 {
status = "okay";
};
&timer3 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&i2c1 {
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
};
&trng0 {
status = "okay";
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&spi3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim3_default>;
pinctrl-names = "default";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&wdt0 {
status = "okay";
};
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 870 |
```ini
set ESP_RTOS none
source [find interface/ftdi/esp32s2_kaluga_v1.cfg]
source [find target/esp32s2.cfg]
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```restructuredtext
.. _boards-sifive:
SiFive
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/sifive/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PINCTRL=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
config BOARD_HIFIVE1
select SOC_SIFIVE_FREEDOM_FE310
``` | /content/code_sandbox/boards/sifive/hifive1/Kconfig.hifive1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```cmake
set(SUPPORTED_EMU_PLATFORMS renode qemu)
set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive1.resc)
set(RENODE_UART sysbus.uart0)
set(QEMU_binary_suffix riscv32)
set(QEMU_CPU_TYPE_${ARCH} riscv32)
set(QEMU_FLAGS_${ARCH}
-nographic
-machine sifive_e
)
if("${BOARD_REVISION}" STREQUAL "A")
board_set_flasher_ifnset(hifive1)
board_finalize_runner_args(hifive1)
board_runner_args(openocd --cmd-load "hifive1-load")
board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt")
board_runner_args(openocd --cmd-post-verify "hifive1-post-verify")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
elseif("${BOARD_REVISION}" STREQUAL "B")
board_runner_args(jlink "--device=FE310")
board_runner_args(jlink "--iface=JTAG")
board_runner_args(jlink "--speed=4000")
board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
board_runner_args(jlink "--tool-opt=-autoconnect 1")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()
set_ifndef(BOARD_SIM_RUNNER renode)
set_ifndef(BOARD_ROBOT_RUNNER renode-robot)
include(${ZEPHYR_BASE}/boards/common/renode.board.cmake)
include(${ZEPHYR_BASE}/boards/common/renode_robot.board.cmake)
``` | /content/code_sandbox/boards/sifive/hifive1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 359 |
```yaml
identifier: hifive1
name: SiFive HiFive1
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 16
simulation: renode
simulation_exec: renode
supported:
- pwm
- gpio
- spi
- arduino_gpio
- arduino_i2c
testing:
ignore_tags:
- net
- bluetooth
- flash
- newlib
renode:
uart: sysbus.uart0
resc: boards/sifive/hifive1/support/hifive1.resc
vendor: sifive
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 141 |
```restructuredtext
.. _esp32s2_franzininho:
ESP32-S2 Franzininho
####################
Overview
********
Franzininho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC,
designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities. [1]_
The features include the following:
- RSA-3072-based secure boot
- AES-XTS-256-based flash encryption
- Protected private key and device secrets from software access
- Cryptographic accelerators for enhanced performance
- Protection against physical fault injection attacks
- Various peripherals:
- 43x programmable GPIOs
- 14x configurable capacitive touch GPIOs
- USB OTG
- LCD interface
- camera interface
- SPI
- I2S
- UART
- ADC
- DAC
- LED PWM with up to 8 channels
.. figure:: img/esp32_s2_franzininho.jpg
:align: center
:alt: ESP32-S2 FRANZININHO
System requirements
===================
Prerequisites
-------------
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
*******************
Simple boot
===========
The board could be loaded using the single binary image, without 2nd stage bootloader.
It is the default option when building the application without additional configuration.
.. note::
Simple boot does not provide any security features nor OTA updates.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: esp32s2_franzininho
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s2_franzininho
:goals: build
The usual ``flash`` target will work with the ``esp32s2_franzininho`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: esp32s2_franzininho
:goals: flash
Open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! esp32s2_franzininho
References
**********
.. [1] path_to_url
.. _`ESP32S2 Technical Reference Manual`: path_to_url
.. _`ESP32S2 Datasheet`: path_to_url
``` | /content/code_sandbox/boards/franzininho/esp32s2_franzininho/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,080 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
&pinctrl {
/* UART0 */
uart0_rx_default: uart0_rx_default {
pinmux = <16 SIFIVE_PINMUX_IOF0>;
};
uart0_tx_default: uart0_tx_default {
pinmux = <17 SIFIVE_PINMUX_IOF0>;
};
/* SPI1 */
spi1_cs0_default: spi1_cs0_default {
pinmux = <2 SIFIVE_PINMUX_IOF0>;
};
spi1_mosi_default: spi1_mosi_default {
pinmux = <3 SIFIVE_PINMUX_IOF0>;
};
spi1_miso_default: spi1_miso_default {
pinmux = <4 SIFIVE_PINMUX_IOF0>;
};
spi1_sck_default: spi1_sck_default {
pinmux = <5 SIFIVE_PINMUX_IOF0>;
};
spi1_cs2_default: spi1_cs2_default {
pinmux = <9 SIFIVE_PINMUX_IOF0>;
};
spi1_cs3_default: spi1_cs3_default {
pinmux = <10 SIFIVE_PINMUX_IOF0>;
};
/* PWM0 */
pwm0_0_default: pwm0_0_default {
pinmux = <0 SIFIVE_PINMUX_IOF1>;
};
pwm0_1_default: pwm0_1_default {
pinmux = <1 SIFIVE_PINMUX_IOF1>;
};
pwm0_2_default: pwm0_2_default {
pinmux = <2 SIFIVE_PINMUX_IOF1>;
};
pwm0_3_default: pwm0_3_default {
pinmux = <3 SIFIVE_PINMUX_IOF1>;
};
/* PWM1 */
pwm1_0_default: pwm1_0_default {
pinmux = <20 SIFIVE_PINMUX_IOF1>;
};
pwm1_1_default: pwm1_1_default {
pinmux = <19 SIFIVE_PINMUX_IOF1>;
};
pwm1_2_default: pwm1_2_default {
pinmux = <21 SIFIVE_PINMUX_IOF1>;
};
pwm1_3_default: pwm1_3_default {
pinmux = <22 SIFIVE_PINMUX_IOF1>;
};
/* PWM2 */
pwm2_0_default: pwm2_0_default {
pinmux = <10 SIFIVE_PINMUX_IOF1>;
};
pwm2_1_default: pwm2_1_default {
pinmux = <11 SIFIVE_PINMUX_IOF1>;
};
pwm2_2_default: pwm2_2_default {
pinmux = <12 SIFIVE_PINMUX_IOF1>;
};
pwm2_3_default: pwm2_3_default {
pinmux = <13 SIFIVE_PINMUX_IOF1>;
};
/* I2C0 */
i2c0_0_default: i2c0_0_default {
pinmux = <12 SIFIVE_PINMUX_IOF0>;
};
i2c0_1_default: i2c0_1_default {
pinmux = <13 SIFIVE_PINMUX_IOF0>;
};
};
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 745 |
```yaml
board:
name: hifive1
vendor: sifive
socs:
- name: fe310
revision:
format: letter
default: "A"
revisions:
- name: "A"
- name: "B"
``` | /content/code_sandbox/boards/sifive/hifive1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
CONFIG_BUILD_OUTPUT_HEX=y
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1_fe310_A_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8 |
```yaml
identifier: hifive1@B
name: SiFive HiFive1 Rev B
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 16
testing:
ignore_tags:
- net
- bluetooth
supported:
- arduino_gpio
- arduino_i2c
- gpio
- i2c
vendor: sifive
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1_fe310_B.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
if BOARD_HIFIVE1_FE310
config SYS_CLOCK_TICKS_PER_SEC
default 128
if "$(BOARD_REVISION)" = "B"
config HAS_FLASH_LOAD_OFFSET
default y
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/spi@10014000,1)
config FLASH_LOAD_OFFSET
default 0x0
endif # "$(BOARD_REVISION)" = "B"
endif # BOARD_HIFIVE1_FE310
``` | /content/code_sandbox/boards/sifive/hifive1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
/*
*
*/
/ {
model = "SiFive HiFive 1 Rev. B";
compatible = "sifive,hifive1_revb";
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
&spi0 {
reg = <0x10014000 0x1000 0x20010000 0x3c0900>;
};
&spi2 {
status = "okay";
pinctrl-0 = <&spi1_cs2_default
&spi1_mosi_default
&spi1_miso_default
&spi1_sck_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1_fe310_B.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
/dts-v1/;
#include <sifive/riscv32-fe310.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include "hifive1-pinctrl.dtsi"
/ {
model = "SiFive HiFive 1";
compatible = "sifive,hifive1";
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
pwm-led0 = &pwmled0;
pwm-led1 = &pwmled1;
pwm-led2 = &pwmled2;
watchdog0 = &wdog0;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtim;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
led1: led_1 {
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
led2: led_2 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
};
pwmleds {
compatible = "pwm-leds";
pwmled0: pwmled_0 {
pwms = <&pwm1 1 PWM_MSEC(20)>;
label = "Green LED";
};
pwmled1: pwmled_1 {
pwms = <&pwm1 2 PWM_MSEC(20)>;
label = "Blue LED";
};
pwmled2: pwmled_2 {
pwms = <&pwm1 3 PWM_MSEC(20)>;
label = "Red LED";
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = /* A0 not connected */
<1 0 &gpio0 9 0>, /* A1, also CS2 */
<2 0 &gpio0 10 0>, /* A2, also WF_INT */
<3 0 &gpio0 11 0>, /* A3 */
<4 0 &gpio0 12 0>, /* A4 */
<5 0 &gpio0 13 0>, /* A5 */
<6 0 &gpio0 16 0>, /* D0, also TX */
<7 0 &gpio0 17 0>, /* D1, also RX */
<8 0 &gpio0 18 0>, /* D2 */
<9 0 &gpio0 19 0>, /* D3 */
<10 0 &gpio0 20 0>, /* D4 */
<11 0 &gpio0 21 0>, /* D5 */
<12 0 &gpio0 22 0>, /* D6 */
<13 0 &gpio0 23 0>, /* D7 */
<14 0 &gpio0 0 0>, /* D8 */
<15 0 &gpio0 1 0>, /* D9 */
<16 0 &gpio0 2 0>, /* D10 */
<17 0 &gpio0 3 0>, /* D11, also MOSI */
<18 0 &gpio0 4 0>, /* D12, also MISO */
<19 0 &gpio0 5 0>, /* D13, also SCK */
<20 0 &gpio0 12 0>, /* D14, also SDA */
<21 0 &gpio0 13 0>; /* D15, also SCL */
};
};
&gpio0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
pinctrl-names = "default";
};
/* disabled (used by Flash ROM by default) */
&spi0 {
reg = <0x10014000 0x1000 0x20400000 0xc00000>;
flash0: flash@0 {
compatible = "issi,is25lp128", "jedec,spi-nor";
status = "disabled";
size = <134217728>;
jedec-id = [96 60 18];
reg = <0>;
spi-max-frequency = <133000000>;
};
};
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_cs0_default &spi1_cs2_default &spi1_cs3_default
&spi1_mosi_default &spi1_miso_default &spi1_sck_default>;
pinctrl-names = "default";
};
&spi2 {
status = "okay";
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
pinctrl-0 = <&pwm1_1_default &pwm1_2_default &pwm1_3_default>;
pinctrl-names = "default";
};
&pwm2 {
status = "okay";
pinctrl-0 = <&pwm2_1_default &pwm2_2_default &pwm2_3_default>;
pinctrl-names = "default";
};
arduino_i2c: &i2c0 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_0_default &i2c0_1_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/sifive/hifive1/hifive1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,336 |
```ini
adapter speed 10000
adapter driver ftdi
ftdi device_desc "Dual RS232-HS"
ftdi vid_pid 0x0403 0x6010
ftdi layout_init 0x0008 0x000b
ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
proc hifive1-load {file} {
flash protect 0 64 last off
flash write_image erase $file
}
proc hifive1-reset-halt {} {
halt
}
proc hifive1-post-verify {} {
# `reset halt` not correctly works.
# toggles the nSRST directly.
ftdi set_signal nSRST 0
ftdi set_signal nSRST z
shutdown
}
$_TARGETNAME configure -event gdb-attach {
halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
resume
shutdown
}
``` | /content/code_sandbox/boards/sifive/hifive1/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 321 |
```unknown
:description: This script is prepared to run Zephyr on SiFive-FE310 board.
:name: SiFive-FE310
$name?="SiFive-FE310"
set platform
"""
using "platforms/cpus/sifive-fe310.repl"
clint:
frequency: 16000000
"""
using sysbus
mach create $name
machine LoadPlatformDescriptionFromString $platform
sysbus Tag <0x10008000 4> "PRCI_HFROSCCFG" 0xFFFFFFFF
sysbus Tag <0x10008008 4> "PRCI_PLLCFG" 0xFFFFFFFF
cpu PerformanceInMips 320
showAnalyzer uart0
macro reset
"""
sysbus LoadELF $elf
"""
runMacro $reset
``` | /content/code_sandbox/boards/sifive/hifive1/support/hifive1.resc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```cmake
set(SUPPORTED_EMU_PLATFORMS renode)
set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive_unmatched.resc)
set(RENODE_UART sysbus.uart0)
set(OPENOCD_USE_LOAD_IMAGE NO)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unmatched.cfg")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
/*
*
*/
/dts-v1/;
#include <sifive/riscv64-fu740.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &l2lim;
};
ram0: ram0@80000000 {
compatible = "memory";
reg = <0x0 0x80000000 0x4 0x00000000>;
reg-names = "mem";
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
/* disabled (used by Flash ROM by default) */
&spi0 {
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x2000000>;
flash0: flash@0 {
compatible = "issi,is25wp256d", "jedec,spi-nor";
status = "disabled";
size = <33554432>;
jedec-id = [96 60 18];
reg = <0>;
spi-max-frequency = <133000000>;
};
};
&spi1 {
status = "okay";
};
&spi2 {
status = "okay";
};
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/hifive_unmatched.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 290 |
```unknown
config BOARD_HIFIVE_UNMATCHED
select SOC_SIFIVE_FREEDOM_FU740
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
board:
name: hifive_unmatched
vendor: sifive
socs:
- name: fu740
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```restructuredtext
.. _hifive1:
SiFive HiFive1
##############
Overview
********
The HiFive1 is an Arduino-compatible development board with
an FE310 RISC-V SoC. Two revisions of this board are supported in Zephyr:
`HiFive1 <path_to_url`__ (also known as HiFive1 Rev A)
and `HiFive1 Rev B <path_to_url`__.
.. figure:: img/hifive1.jpg
:align: center
:alt: SiFive HiFive1 board
SiFive HiFive1 board (image courtesy of SiFive)
.. figure:: img/hifive1_revb.jpg
:align: center
:alt: SiFive HiFive1 Rev B board
SiFive HiFive1 Rev B board (image courtesy of SiFive)
Programming and debugging
*************************
Building
========
Applications for the HiFive1 board configuration can be built as usual (see
:ref:`build_an_application`) using the corresponding board name:
.. tabs::
.. group-tab:: HiFive1
.. zephyr-app-commands::
:board: hifive1
:goals: build
.. group-tab:: HiFive1 Rev B
.. zephyr-app-commands::
:board: hifive1@B
:goals: build
Flashing
========
HiFive1
-------
.. tabs::
.. group-tab:: HiFive1
In order to upload the application to the device, you'll need OpenOCD with
RISC-V support. Download the tarball for your OS from the `SiFive website
<path_to_url`_ and extract it.
The Zephyr SDK uses a bundled version of OpenOCD by default. You can
overwrite that behavior by adding the
``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>`` parameter when building:
.. zephyr-app-commands::
:board: hifive1
:goals: build
:gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
When using a custom toolchain it should be enough to have the downloaded
version of the binary in your ``PATH``.
.. group-tab:: HiFive1 Rev B
The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and
debug the board, you'll need to install the
`Segger J-Link Software and Documentation Pack
<path_to_url#J-LinkSoftwareAndDocumentationPack>`_
and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are
available).
Now you can flash the application as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details):
.. code-block:: console
west flash
Depending on your OS you might have to run the flash command as superuser.
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/sifive/hifive1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 661 |
```unknown
if BOARD_HIFIVE_UNMATCHED
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # BOARD_HIFIVE_UNMATCHED
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```yaml
identifier: hifive_unmatched
name: SiFive HiFive Unmatched
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
simulation: renode
simulation_exec: renode
testing:
ignore_tags:
- net
- bluetooth
renode:
uart: sysbus.uart0
resc: boards/sifive/hifive_unmatched/support/hifive_unmatched.resc
supported:
- spi
- memc
vendor: sifive
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/hifive_unmatched.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```unknown
:description: This script is prepared to run Zephyr on SiFive-FU740 board.
:name: SiFive-FU740
$name?="SiFive-FU740"
using sysbus
mach create $name
set platform
"""
using "platforms/cpus/sifive-fu740.repl"
clint:
frequency: 10000000
"""
machine LoadPlatformDescriptionFromString $platform
machine PyDevFromFile @scripts/pydev/flipflop.py 0x10000000 0x100 True
showAnalyzer uart0
macro reset
"""
sysbus LoadELF $elf
"""
runMacro $reset
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```ini
adapter speed 10000
adapter driver ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 322 |
```cmake
set(SUPPORTED_EMU_PLATFORMS renode)
set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive_unleashed.resc)
set(RENODE_UART sysbus.uart0)
set(OPENOCD_USE_LOAD_IMAGE NO)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unleashed.cfg")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```restructuredtext
.. _hifive_unmatched:
SiFive HiFive Unmatched
#######################
Overview
********
The HiFive Unmatched is a development board with a SiFive FU740-C000
multi-core 64bit RISC-V SoC.
.. image:: img/hifive_unmatched.jpg
:align: center
:alt: SiFive HiFive Unmatched board
Programming and debugging
*************************
Building
========
Applications for the ``hifive_unmatched`` board configuration can be built as
usual (see :ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: hifive_unmatched
:goals: build
Flashing
========
Current version has not yet supported flashing binary to onboard Flash ROM.
This board has USB-JTAG interface and this can be used with OpenOCD.
Load applications on DDR and run as follows:
.. code-block:: console
openocd -c 'bindto 0.0.0.0' \
-f boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg
riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
(gdb) target remote :3333
(gdb) c
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/sifive/hifive_unmatched/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 298 |
```unknown
CONFIG_CONSOLE=y
CONFIG_GPIO=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
board:
name: hifive_unleashed
vendor: sifive
socs:
- name: fu540
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
if BOARD_HIFIVE_UNLEASHED
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # BOARD_HIFIVE_UNLEASHED
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
config BOARD_HIFIVE_UNLEASHED
select SOC_SIFIVE_FREEDOM_FU540
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
identifier: hifive_unleashed
name: SiFive HiFive Unleashed
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
simulation: renode
simulation_exec: renode
testing:
ignore_tags:
- net
- bluetooth
- flash
- newlib
- crypto
renode:
uart: sysbus.uart0
resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc
supported:
- gpio
- spi
vendor: sifive
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/hifive_unleashed.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 136 |
```ini
adapter speed 10000
adapter driver ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 322 |
```unknown
/*
*
*/
/dts-v1/;
#include <sifive/riscv64-fu540.dtsi>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram0;
};
ram0: ram0@80000000 {
compatible = "memory";
reg = <0x80000000 0xf0000000>;
reg-names = "mem";
};
lscon_96b: connector {
compatible = "linaro,96b-lscon-1v8";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <22 0 &gpio0 0 0>, /* GPIO-A */
<23 0 &gpio0 1 0>, /* GPIO-B */
<24 0 &gpio0 2 0>, /* GPIO-C */
<25 0 &gpio0 3 0>, /* GPIO-D */
<26 0 &gpio0 4 0>, /* GPIO-E */
<27 0 &gpio0 5 0>, /* GPIO-F */
<38 0 &gpio0 6 0>, /* GPIO-G */
<39 0 &gpio0 7 0>, /* GPIO-H */
<30 0 &gpio0 8 0>, /* GPIO-I */
<31 0 &gpio0 9 0>, /* GPIO-J */
<32 0 &gpio0 15 0>; /* GPIO-K */
/* GPIO-L not connected */
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
/* disabled (used by Flash ROM by default) */
&spi0 {
reg = <0x10040000 0x1000 0x20000000 0x2000000>;
flash0: flash@0 {
compatible = "issi,is25wp256d", "jedec,spi-nor";
status = "disabled";
size = <33554432>;
jedec-id = [96 60 18];
reg = <0>;
spi-max-frequency = <133000000>;
};
};
&spi1 {
status = "okay";
};
&spi2 {
status = "okay";
};
&gpio0 {
status = "okay";
};
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/hifive_unleashed.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 551 |
```unknown
:description: This script is prepared to run Zephyr on SiFive-FU540 board.
:name: SiFive-FU540
$name?="SiFive-FU540"
using sysbus
mach create $name
set platform
"""
using "platforms/cpus/sifive-fu540.repl"
clint:
frequency: 10000000
"""
machine LoadPlatformDescriptionFromString $platform
machine PyDevFromFile @scripts/pydev/flipflop.py 0x10000000 0x100 True
showAnalyzer uart0
macro reset
"""
sysbus LoadELF $elf
"""
runMacro $reset
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```restructuredtext
.. _hifive_unleashed:
SiFive HiFive Unleashed
#######################
Overview
********
The HiFive Unleashed is a development board with a SiFive FU540-C000
multi-core 64bit RISC-V SoC.
.. image:: img/hifive_unleashed.jpg
:align: center
:alt: SiFive HiFive Unleashed board
Programming and debugging
*************************
Building
========
Applications for the ``hifive_unleashed`` board configuration can be built as
usual (see :ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: hifive_unleashed
:goals: build
Flashing
========
Current version has not yet supported flashing binary to onboard Flash ROM.
This board has USB-JTAG interface and this can be used with OpenOCD.
Load applications on DDR and run as follows:
.. code-block:: console
openocd -c 'bindto 0.0.0.0' \
-f boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg
riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
(gdb) target remote :3333
(gdb) c
Debugging
=========
Refer to the detailed overview about :ref:`application_debugging`.
``` | /content/code_sandbox/boards/sifive/hifive_unleashed/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```unknown
/*
*
*/
/dts-v1/;
#include <arm/xilinx/zynqmp_rpu.dtsi>
#include "mercury_xu-pinctrl.dtsi"
/ {
model = "Mercury XU";
compatible = "xlnx,zynqmp";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
fpga0: fpga {
status = "okay";
compatible = "xlnx,fpga";
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <99999901>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&uart1 {
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&ttc0 {
status = "okay";
clock-frequency = <5000000>;
};
&psgpio {
status = "okay";
};
``` | /content/code_sandbox/boards/enclustra/mercury_xu/mercury_xu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 237 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
static int mercury_xu_init(void)
{
return 0;
}
SYS_INIT(mercury_xu_init, PRE_KERNEL_2,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
``` | /content/code_sandbox/boards/enclustra/mercury_xu/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable timer
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/enclustra/mercury_xu/mercury_xu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
board:
name: mercury_xu
vendor: enclustra
socs:
- name: zynqmp_rpu
``` | /content/code_sandbox/boards/enclustra/mercury_xu/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
identifier: mercury_xu
name: MERCURY-XU
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
vendor: xlnx
``` | /content/code_sandbox/boards/enclustra/mercury_xu/mercury_xu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
if BOARD_MERCURY_XU
config FLASH_SIZE
int
default 64
config FLASH_BASE_ADDRESS
default 0x08000000
endif
``` | /content/code_sandbox/boards/enclustra/mercury_xu/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
/*
*
*/
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_RX_38>;
};
group2 {
pinmux = <UART0_TX_39>;
};
};
uart1_default: uart1_default {
group1 {
pinmux = <UART1_RX_21>;
};
group2 {
pinmux = <UART1_TX_20>;
};
};
};
``` | /content/code_sandbox/boards/enclustra/mercury_xu/mercury_xu-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```restructuredtext
.. _boards-up:
UP Bridge the Gap.
##################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/up-bridge-the-gap/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
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