text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
rsource "*/Kconfig"
``` | /content/code_sandbox/drivers/pinctrl/renesas/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9 |
```unknown
config PINCTRL_RPI_PICO
bool "RaspberryPi Pico pin controller driver"
default y
depends on DT_HAS_RASPBERRYPI_PICO_PINCTRL_ENABLED
select PICOSDK_USE_GPIO
help
RaspberryPi Pico pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
config PINCTRL_RZT2M
bool "Renesas RZ/T2M pin controller driver"
default y
depends on DT_HAS_RENESAS_RZT2M_PINCTRL_ENABLED
help
Renesas RZ/T2M pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/renesas/rz/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_rzt2m_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define PORT_NSR DT_INST_REG_ADDR_BY_NAME(0, port_nsr)
#define PTADR DT_INST_REG_ADDR_BY_NAME(0, ptadr)
/* Port m mode control register */
#define PMC(port) (PORT_NSR + 0x400 + port)
/* Port m function control register */
#define PFC(port) (PORT_NSR + 0x600 + (0x4 * port))
/* IO Buffer m function switching register */
#define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin)
/* Port m region select register */
#define RSELP(port) (PTADR + port)
#define DRCTL_DRIVE_STRENGTH(val) (val & 0x3)
#define DRCTL_PULL_UP_DOWN(val) ((val & 0x3) << 2)
#define DRCTL_SCHMITT(val) ((val & 0x1) << 4)
#define DRCTL_SLEW_RATE(val) ((val & 0x1) << 5)
#define DRCTL_CONFIG(drive, pull, schmitt, slew) \
(DRCTL_DRIVE_STRENGTH(drive) | DRCTL_PULL_UP_DOWN(pull) | DRCTL_SCHMITT(schmitt) | \
DRCTL_SLEW_RATE(slew))
#define PFC_FUNC_MASK(pin) (0xf << (pin * 4))
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint8_t rselp = sys_read8(RSELP(pin->port));
uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin));
uint8_t pmc = sys_read8(PMC(pin->port));
/* Set proper bit in the RSELP register to use as non-safety domain. */
sys_write8(rselp | BIT(pin->pin), RSELP(pin->port));
sys_write8(DRCTL_CONFIG(
pin->drive_strength, (pin->pull_up == 1 ? 1U : (pin->pull_down == 1 ? 2U : 0)),
pin->schmitt_enable, pin->slew_rate),
DRCTL(pin->port, pin->pin));
/* Select function for the pin. */
sys_write32(pfc | pin->func << (pin->pin * 4), PFC(pin->port));
/* Set proper bit in the PMC register to use the pin as a peripheral IO. */
sys_write8(pmc | BIT(pin->pin), PMC(pin->port));
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/rz/pinctrl_rzt2m.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 662 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <string.h>
#define DT_DRV_COMPAT renesas_ra_pinctrl
#define PORT_NUM 15
#define PIN_NUM 16
enum {
PWPR_PFSWE_POS = 6,
PWPR_B0WI_POS = 7,
};
static inline uint32_t pinctrl_ra_read_PmnFPS(size_t port, size_t pin)
{
return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4);
}
static inline void pinctrl_ra_write_PmnFPS(size_t port, size_t pin, uint32_t value)
{
sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, pfs) + (port * PIN_NUM + pin) * 4);
}
static inline uint8_t pinctrl_ra_read_PMISC_PWPR(size_t port, size_t pin)
{
return sys_read8(DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr));
}
static inline void pinctrl_ra_write_PMISC_PWPR(uint8_t value)
{
sys_write8(value, DT_INST_REG_ADDR_BY_NAME(0, pmisc_pwpr));
}
static void pinctrl_ra_configure_pfs(const pinctrl_soc_pin_t *pinc)
{
pinctrl_soc_pin_t pincfg;
memcpy(&pincfg, pinc, sizeof(pinctrl_soc_pin_t));
pincfg.pin = 0;
pincfg.port = 0;
/* Clear PMR bits before configuring */
if ((pincfg.config & PmnPFS_PMR_POS)) {
uint32_t val = pinctrl_ra_read_PmnFPS(pinc->port, pinc->pin);
pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, val & ~(BIT(PmnPFS_PMR_POS)));
pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config & ~PmnPFS_PMR_POS);
}
pinctrl_ra_write_PmnFPS(pinc->port, pinc->pin, pincfg.config);
}
int pinctrl_ra_query_config(uint32_t port, uint32_t pin, struct pinctrl_ra_pin *const pincfg)
{
if (port >= PORT_NUM || pin >= PIN_NUM) {
return -EINVAL;
}
pincfg->config = pinctrl_ra_read_PmnFPS(port, pin);
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
pinctrl_ra_write_PMISC_PWPR(0);
pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_PFSWE_POS));
for (int i = 0; i < pin_cnt; i++) {
pinctrl_ra_configure_pfs(&pins[i]);
}
pinctrl_ra_write_PMISC_PWPR(0);
pinctrl_ra_write_PMISC_PWPR(BIT(PWPR_B0WI_POS));
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/ra/pinctrl_renesas_ra.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 668 |
```unknown
config PINCTRL_RENESAS_RA
bool "Renesas RA series pin controller driver"
default y
depends on DT_HAS_RENESAS_RA_PINCTRL_ENABLED
help
Enable Renesas RA series pin controller driver.
config PINCTRL_RENESAS_RA_PFS
bool "Renesas RA pinctrl driver"
default y
depends on DT_HAS_RENESAS_RA_PINCTRL_PFS_ENABLED
help
Enable the Renesas RA series pinctrl driver with PFS secure register.
``` | /content/code_sandbox/drivers/pinctrl/renesas/ra/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define PORT_POS (8)
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
bsp_io_port_pin_t port_pin;
R_BSP_PinAccessEnable();
for (uint8_t i = 0U; i < pin_cnt; i++) {
const pinctrl_soc_pin_t *pin = &pins[i];
port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
R_BSP_PinCfg(port_pin, pin->cfg);
}
R_BSP_PinAccessDisable();
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/ra/pinctrl_ra.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <DA1469xAB.h>
/** Utility macro to retrieve starting mode register and pin count for GPIO port from DT */
#define GPIO_PORT_ENTRY(nodelabel) \
{ DT_REG_ADDR_BY_IDX(DT_NODELABEL(nodelabel), 1), \
DT_PROP(DT_NODELABEL(nodelabel), ngpios) }
struct gpio_port {
uint32_t p0_mode_addr;
uint8_t pin_count;
};
static const struct gpio_port smartbond_gpio_ports[] = {
GPIO_PORT_ENTRY(gpio0),
GPIO_PORT_ENTRY(gpio1),
};
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
volatile uint32_t *reg;
uint32_t reg_val;
__ASSERT_NO_MSG(pin->port < ARRAY_SIZE(smartbond_gpio_ports));
__ASSERT_NO_MSG(pin->pin < smartbond_gpio_ports[pin->port].pin_count);
reg = (volatile uint32_t *)smartbond_gpio_ports[pin->port].p0_mode_addr;
reg += pin->pin;
reg_val = pin->func << GPIO_P0_00_MODE_REG_PID_Pos;
if (pin->bias_pull_up) {
reg_val |= 0x01 << GPIO_P0_00_MODE_REG_PUPD_Pos;
} else if (pin->bias_pull_down) {
reg_val |= 0x02 << GPIO_P0_00_MODE_REG_PUPD_Pos;
} else if (pin->output_enable) {
reg_val |= 0x03 << GPIO_P0_00_MODE_REG_PUPD_Pos;
}
*reg = reg_val;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/smartbond/pinctrl_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 421 |
```unknown
config PINCTRL_SMARTBOND
bool "Renesas SmartBond(tm) pinctrl driver"
default y
depends on DT_HAS_RENESAS_SMARTBOND_PINCTRL_ENABLED
help
Enable pinctrl driver for Renesas SmartBond(tm) MCU family.
``` | /content/code_sandbox/drivers/pinctrl/renesas/smartbond/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_PINCTRL_PFC_RCAR_H_
#define ZEPHYR_DRIVERS_PINCTRL_PFC_RCAR_H_
#include <stdint.h>
#include <pinctrl_soc.h>
const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void);
const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void);
/**
* @brief set the register index for a given pin
*
* @param the pin
* @param pointer for the resulting register index
* @return 0 if the register index is found, negative
* errno otherwise.
*/
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index);
#endif /* ZEPHYR_DRIVERS_PINCTRL_PFC_RCAR_H_ */
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/pfc_rcar.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 165 |
```c
/*
*
*
*/
#include <pinctrl_soc.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
const struct pfc_drive_reg pfc_drive_regs[] = {
/* DRVCTRL0 */
{ 0x0300, {
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
/* DRVCTRL1 */
{ 0x0304, {
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
/* DRVCTRL2 */
{ 0x0308, {
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
/* DRVCTRL3 */
{ 0x030c, {
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
/* DRVCTRL4 */
{ 0x0310, {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
} },
/* DRVCTRL5 */
{ 0x0314, {
{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
} },
/* DRVCTRL6 */
{ 0x0318, {
{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
} },
/* DRVCTRL7 */
{ 0x031c, {
{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
/* DRVCTRL8 */
{ 0x0320, {
{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
} },
/* DRVCTRL9 */
{ 0x0324, {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
} },
/* DRVCTRL10 */
{ 0x0328, {
{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
/* DRVCTRL11 */
{ 0x032c, {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
/* DRVCTRL12 */
{ 0x0330, {
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
/* DRVCTRL13 */
{ 0x0334, {
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
/* DRVCTRL14 */
{ 0x0338, {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
} },
/* DRVCTRL15 */
{ 0x033c, {
{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
} },
/* DRVCTRL16 */
{ 0x0340, {
{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
} },
/* DRVCTRL17 */
{ 0x0344, {
{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
} },
/* DRVCTRL18 */
{ 0x0348, {
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
} },
/* DRVCTRL19 */
{ 0x034c, {
{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
} },
/* DRVCTRL20 */
{ 0x0350, {
{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
/* DRVCTRL21 */
{ 0x0354, {
{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
} },
/* DRVCTRL22 */
{ 0x0358, {
{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
} },
/* DRVCTRL23 */
{ 0x035c, {
{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
} },
/* DRVCTRL24 */
{ 0x0360, {
{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
{ },
};
#define PFC_BIAS_REG(r1, r2) \
.puen = r1, \
.pud = r2, \
.pins =
const struct pfc_bias_reg pfc_bias_regs[] = {
{ PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */
[0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
} },
{ PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */
[0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
[1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
[2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
[3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
[4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
[5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
[6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
[7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
[8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
[9] = RCAR_GP_PIN(2, 6), /* PWM0 */
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
[12] = RCAR_GP_PIN(1, 0), /* A0 */
[13] = RCAR_GP_PIN(1, 1), /* A1 */
[14] = RCAR_GP_PIN(1, 2), /* A2 */
[15] = RCAR_GP_PIN(1, 3), /* A3 */
[16] = RCAR_GP_PIN(1, 4), /* A4 */
[17] = RCAR_GP_PIN(1, 5), /* A5 */
[18] = RCAR_GP_PIN(1, 6), /* A6 */
[19] = RCAR_GP_PIN(1, 7), /* A7 */
[20] = RCAR_GP_PIN(1, 8), /* A8 */
[21] = RCAR_GP_PIN(1, 9), /* A9 */
[22] = RCAR_GP_PIN(1, 10), /* A10 */
[23] = RCAR_GP_PIN(1, 11), /* A11 */
[24] = RCAR_GP_PIN(1, 12), /* A12 */
[25] = RCAR_GP_PIN(1, 13), /* A13 */
[26] = RCAR_GP_PIN(1, 14), /* A14 */
[27] = RCAR_GP_PIN(1, 15), /* A15 */
[28] = RCAR_GP_PIN(1, 16), /* A16 */
[29] = RCAR_GP_PIN(1, 17), /* A17 */
[30] = RCAR_GP_PIN(1, 18), /* A18 */
[31] = RCAR_GP_PIN(1, 19), /* A19 */
} },
{ PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */
[0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
[1] = RCAR_GP_PIN(1, 20), /* CS0_N */
[2] = RCAR_GP_PIN(1, 21), /* CS1_N */
[3] = RCAR_GP_PIN(1, 22), /* BS_N */
[4] = RCAR_GP_PIN(1, 23), /* RD_N */
[5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
[6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
[13] = RCAR_GP_PIN(0, 3), /* D3 */
[14] = RCAR_GP_PIN(0, 4), /* D4 */
[15] = RCAR_GP_PIN(0, 5), /* D5 */
[16] = RCAR_GP_PIN(0, 6), /* D6 */
[17] = RCAR_GP_PIN(0, 7), /* D7 */
[18] = RCAR_GP_PIN(0, 8), /* D8 */
[19] = RCAR_GP_PIN(0, 9), /* D9 */
[20] = RCAR_GP_PIN(0, 10), /* D10 */
[21] = RCAR_GP_PIN(0, 11), /* D11 */
[22] = RCAR_GP_PIN(0, 12), /* D12 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
[24] = RCAR_GP_PIN(0, 14), /* D14 */
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
[0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[2] = PIN_FSCLKST_N, /* FSCLKST# */
[3] = PIN_EXTALR, /* EXTALR*/
[4] = PIN_TRST_N, /* TRST# */
[5] = PIN_TCK, /* TCK */
[6] = PIN_TMS, /* TMS */
[7] = PIN_TDI, /* TDI */
[8] = PIN_NONE,
[9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
} },
{ PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
[0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
[1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
[2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
[3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
[4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
[5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
[6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
[7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
[8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
} },
{ PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */
[0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
[1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
[2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
[3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[6] = PIN_MLB_REF, /* MLB_REF */
[7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
} },
{ PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */
[0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
[1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
[2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
[3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
[4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
[6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
[7] = PIN_NONE,
[8] = PIN_NONE,
[9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ /* sentinel */ },
};
const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
{
return pfc_bias_regs;
}
const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
{
return pfc_drive_regs;
}
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
{
/* There is only one register on Gen 3 */
*reg_index = 0;
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/pfc_r8a77951.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,156 |
```c
/*
*
*
*/
#include <pinctrl_soc.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
const struct pfc_drive_reg pfc_drive_regs[] = {
/* DRVCTRL0 */
{ 0x0300, {
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
/* DRVCTRL1 */
{ 0x0304, {
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
/* DRVCTRL2 */
{ 0x0308, {
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
/* DRVCTRL3 */
{ 0x030c, {
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
/* DRVCTRL4 */
{ 0x0310, {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
} },
/* DRVCTRL5 */
{ 0x0314, {
{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
} },
/* DRVCTRL6 */
{ 0x0318, {
{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
} },
/* DRVCTRL7 */
{ 0x031c, {
{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
/* DRVCTRL8 */
{ 0x0320, {
{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
} },
/* DRVCTRL9 */
{ 0x0324, {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
} },
/* DRVCTRL10 */
{ 0x0328, {
{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
/* DRVCTRL11 */
{ 0x032c, {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
/* DRVCTRL12 */
{ 0x0330, {
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
/* DRVCTRL13 */
{ 0x0334, {
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
/* DRVCTRL14 */
{ 0x0338, {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
} },
/* DRVCTRL15 */
{ 0x033c, {
{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
} },
/* DRVCTRL16 */
{ 0x0340, {
{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
} },
/* DRVCTRL17 */
{ 0x0344, {
{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
} },
/* DRVCTRL18 */
{ 0x0348, {
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
} },
/* DRVCTRL19 */
{ 0x034c, {
{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
} },
/* DRVCTRL20 */
{ 0x0350, {
{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
/* DRVCTRL21 */
{ 0x0354, {
{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
} },
/* DRVCTRL22 */
{ 0x0358, {
{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
} },
/* DRVCTRL23 */
{ 0x035c, {
{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
} },
/* DRVCTRL24 */
{ 0x0360, {
{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
{ },
};
#define PFC_BIAS_REG(r1, r2) \
.puen = r1, \
.pud = r2, \
.pins =
const struct pfc_bias_reg pfc_bias_regs[] = {
{ PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */
[0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
} },
{ PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */
[0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
[1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
[2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
[3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
[4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
[5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
[6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
[7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
[8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
[9] = RCAR_GP_PIN(2, 6), /* PWM0 */
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
[12] = RCAR_GP_PIN(1, 0), /* A0 */
[13] = RCAR_GP_PIN(1, 1), /* A1 */
[14] = RCAR_GP_PIN(1, 2), /* A2 */
[15] = RCAR_GP_PIN(1, 3), /* A3 */
[16] = RCAR_GP_PIN(1, 4), /* A4 */
[17] = RCAR_GP_PIN(1, 5), /* A5 */
[18] = RCAR_GP_PIN(1, 6), /* A6 */
[19] = RCAR_GP_PIN(1, 7), /* A7 */
[20] = RCAR_GP_PIN(1, 8), /* A8 */
[21] = RCAR_GP_PIN(1, 9), /* A9 */
[22] = RCAR_GP_PIN(1, 10), /* A10 */
[23] = RCAR_GP_PIN(1, 11), /* A11 */
[24] = RCAR_GP_PIN(1, 12), /* A12 */
[25] = RCAR_GP_PIN(1, 13), /* A13 */
[26] = RCAR_GP_PIN(1, 14), /* A14 */
[27] = RCAR_GP_PIN(1, 15), /* A15 */
[28] = RCAR_GP_PIN(1, 16), /* A16 */
[29] = RCAR_GP_PIN(1, 17), /* A17 */
[30] = RCAR_GP_PIN(1, 18), /* A18 */
[31] = RCAR_GP_PIN(1, 19), /* A19 */
} },
{ PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */
[0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
[1] = RCAR_GP_PIN(1, 20), /* CS0_N */
[2] = RCAR_GP_PIN(1, 21), /* CS1_N */
[3] = RCAR_GP_PIN(1, 22), /* BS_N */
[4] = RCAR_GP_PIN(1, 23), /* RD_N */
[5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
[6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
[13] = RCAR_GP_PIN(0, 3), /* D3 */
[14] = RCAR_GP_PIN(0, 4), /* D4 */
[15] = RCAR_GP_PIN(0, 5), /* D5 */
[16] = RCAR_GP_PIN(0, 6), /* D6 */
[17] = RCAR_GP_PIN(0, 7), /* D7 */
[18] = RCAR_GP_PIN(0, 8), /* D8 */
[19] = RCAR_GP_PIN(0, 9), /* D9 */
[20] = RCAR_GP_PIN(0, 10), /* D10 */
[21] = RCAR_GP_PIN(0, 11), /* D11 */
[22] = RCAR_GP_PIN(0, 12), /* D12 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
[24] = RCAR_GP_PIN(0, 14), /* D14 */
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
[0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[2] = PIN_FSCLKST_N, /* FSCLKST# */
[3] = PIN_EXTALR, /* EXTALR*/
[4] = PIN_TRST_N, /* TRST# */
[5] = PIN_TCK, /* TCK */
[6] = PIN_TMS, /* TMS */
[7] = PIN_TDI, /* TDI */
[8] = PIN_NONE,
[9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
} },
{ PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
[0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
[1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
[2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
[3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
[4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
[5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
[6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
[7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
[8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
} },
{ PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */
[0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
[1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
[2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
[3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[6] = PIN_MLB_REF, /* MLB_REF */
[7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
} },
{ PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */
[0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
[1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
[2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
[3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
[4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
[6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
[7] = PIN_NONE,
[8] = PIN_NONE,
[9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ /* sentinel */ },
};
const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
{
return pfc_bias_regs;
}
const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
{
return pfc_drive_regs;
}
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
{
/* There is only one register on Gen 3 */
*reg_index = 0;
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/pfc_r8a77961.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,156 |
```c
/*
*
*
*/
#define DT_DRV_COMPAT renesas_rcar_pfc
#include "pfc_rcar.h"
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/device_mmio.h>
#define PFC_RCAR_PMMR 0x0
/* Gen3 only has one base address, Gen4 has one per GPIO controller */
#if defined(CONFIG_SOC_SERIES_RCAR_GEN3)
#define PFC_RCAR_GPSR 0x100
#define PFC_RCAR_IPSR 0x200
#elif defined(CONFIG_SOC_SERIES_RCAR_GEN4)
#define PFC_RCAR_GPSR 0x040
#define PFC_RCAR_IPSR 0x060
#else
#error Unsupported SoC Series
#endif
/* swap both arguments */
#define PFC_REG_ADDRESS(idx, inst) DT_INST_REG_ADDR_BY_IDX(inst, idx)
static uintptr_t reg_base[] = {
LISTIFY(DT_NUM_REGS(DT_DRV_INST(0)), PFC_REG_ADDRESS, (,), 0)
};
#define PFC_REG_SIZE(idx, inst) DT_INST_REG_SIZE_BY_IDX(inst, idx)
static const uintptr_t __maybe_unused reg_sizes[] = {
LISTIFY(DT_NUM_REGS(DT_DRV_INST(0)), PFC_REG_SIZE, (,), 0)
};
#ifdef CONFIG_PINCTRL_RCAR_VOLTAGE_CONTROL
/* POC Control Register can control IO voltage level that is supplied to the pin */
struct pfc_pocctrl_reg {
uint32_t offset;
const uint16_t pins[32];
};
#endif /* CONFIG_PINCTRL_RCAR_VOLTAGE_CONTROL */
/*
* Each drive step is either encoded in 2 or 3 bits.
* So based on a 24 mA maximum value each step is either
* 24/4 mA or 24/8 mA.
*/
#define PFC_RCAR_DRIVE_MAX 24U
#define PFC_RCAR_DRIVE_STEP(size) \
(size == 2 ? PFC_RCAR_DRIVE_MAX / 4 : PFC_RCAR_DRIVE_MAX / 8)
/* Some registers such as IPSR GPSR or DRVCTRL are protected and
* must be preceded to a write to PMMR with the inverse value.
*/
static void pfc_rcar_write(uintptr_t pfc_base, uint32_t offs, uint32_t val)
{
sys_write32(~val, pfc_base + PFC_RCAR_PMMR);
sys_write32(val, pfc_base + offs);
}
/* Set the pin either in gpio or peripheral */
static void pfc_rcar_set_gpsr(uintptr_t pfc_base,
uint16_t pin, bool peripheral)
{
#if defined(CONFIG_SOC_SERIES_RCAR_GEN3)
/* On Gen3 we have multiple GPSR at one base address */
uint8_t bank = pin / 32;
#elif defined(CONFIG_SOC_SERIES_RCAR_GEN4)
/* On Gen4 we have one GPSR at multiple base address */
uint8_t bank = 0;
#endif
uint8_t bit = pin % 32;
uint32_t val = sys_read32(pfc_base + PFC_RCAR_GPSR +
bank * sizeof(uint32_t));
if (peripheral) {
val |= BIT(bit);
} else {
val &= ~BIT(bit);
}
pfc_rcar_write(pfc_base, PFC_RCAR_GPSR + bank * sizeof(uint32_t), val);
}
/* Set peripheral function */
static void pfc_rcar_set_ipsr(uintptr_t pfc_base,
const struct rcar_pin_func *rcar_func)
{
uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t);
uint32_t val = sys_read32(pfc_base + reg_offs);
val &= ~(0xFU << rcar_func->shift);
val |= (rcar_func->func << rcar_func->shift);
pfc_rcar_write(pfc_base, reg_offs, val);
}
static uint32_t pfc_rcar_get_drive_reg(uint16_t pin, uint8_t *offset,
uint8_t *size)
{
const struct pfc_drive_reg *drive_regs = pfc_rcar_get_drive_regs();
while (drive_regs->reg != 0U) {
for (size_t i = 0U; i < ARRAY_SIZE(drive_regs->fields); i++) {
if (drive_regs->fields[i].pin == pin) {
*offset = drive_regs->fields[i].offset;
*size = drive_regs->fields[i].size;
return drive_regs->reg;
}
}
drive_regs++;
}
return 0;
}
/*
* Maximum drive strength is 24mA. This value can be lowered
* using DRVCTRLx registers, some pins have 8 steps (3 bits size encoded)
* some have 4 steps (2 bits size encoded).
*/
static int pfc_rcar_set_drive_strength(uintptr_t pfc_base, uint16_t pin,
uint8_t strength)
{
uint8_t offset, size, step;
uint32_t reg, val;
reg = pfc_rcar_get_drive_reg(pin, &offset, &size);
if (reg == 0U) {
return -EINVAL;
}
step = PFC_RCAR_DRIVE_STEP(size);
if ((strength < step) || (strength > PFC_RCAR_DRIVE_MAX)) {
return -EINVAL;
}
/* Convert the value from mA based on a full drive strength
* value of 24mA.
*/
strength = (strength / step) - 1U;
/* clear previous drive strength value */
val = sys_read32(pfc_base + reg);
val &= ~GENMASK(offset + size - 1U, offset);
val |= strength << offset;
pfc_rcar_write(pfc_base, reg, val);
return 0;
}
static const struct pfc_bias_reg *pfc_rcar_get_bias_reg(uint16_t pin,
uint8_t *bit)
{
const struct pfc_bias_reg *bias_regs = pfc_rcar_get_bias_regs();
/* Loop around all the registers to find the bit for a given pin */
while (bias_regs->puen && bias_regs->pud) {
for (size_t i = 0U; i < ARRAY_SIZE(bias_regs->pins); i++) {
if (bias_regs->pins[i] == pin) {
*bit = i;
return bias_regs;
}
}
bias_regs++;
}
return NULL;
}
int pfc_rcar_set_bias(uintptr_t pfc_base, uint16_t pin, uint16_t flags)
{
uint32_t val;
uint8_t bit;
const struct pfc_bias_reg *bias_reg = pfc_rcar_get_bias_reg(pin, &bit);
if (bias_reg == NULL) {
return -EINVAL;
}
/* pull enable/disable*/
val = sys_read32(pfc_base + bias_reg->puen);
if ((flags & RCAR_PIN_FLAGS_PUEN) == 0U) {
sys_write32(val & ~BIT(bit), pfc_base + bias_reg->puen);
return 0;
}
sys_write32(val | BIT(bit), pfc_base + bias_reg->puen);
/* pull - up/down */
val = sys_read32(pfc_base + bias_reg->pud);
if (flags & RCAR_PIN_FLAGS_PUD) {
sys_write32(val | BIT(bit), pfc_base + bias_reg->pud);
} else {
sys_write32(val & ~BIT(bit), pfc_base + bias_reg->pud);
}
return 0;
}
#ifdef CONFIG_PINCTRL_RCAR_VOLTAGE_CONTROL
const struct pfc_pocctrl_reg pfc_r8a77951_r8a77961_volt_regs[] = {
{
.offset = 0x0380,
.pins = {
[0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[6] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
[7] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
[8] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
[9] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
[10] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
[11] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
[12] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
[13] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
[14] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
[15] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
[16] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
[17] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
[18] = RCAR_GP_PIN(4, 6), /* SD2_DS */
[19] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
[20] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
[21] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
[22] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
[23] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
[24] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
[25] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
[26] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
[27] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
[28] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
[29] = RCAR_GP_PIN(4, 17), /* SD3_DS */
[30] = -1,
[31] = -1,
}
},
{ /* sentinel */ },
};
static const struct pfc_pocctrl_reg *pfc_rcar_get_io_voltage_regs(void)
{
return pfc_r8a77951_r8a77961_volt_regs;
}
static const struct pfc_pocctrl_reg *pfc_rcar_get_pocctrl_reg(uint16_t pin, uint8_t *bit)
{
const struct pfc_pocctrl_reg *voltage_regs = pfc_rcar_get_io_voltage_regs();
BUILD_ASSERT(ARRAY_SIZE(voltage_regs->pins) < UINT8_MAX);
/* Loop around all the registers to find the bit for a given pin */
while (voltage_regs && voltage_regs->offset) {
uint8_t i;
for (i = 0U; i < ARRAY_SIZE(voltage_regs->pins); i++) {
if (voltage_regs->pins[i] == pin) {
*bit = i;
return voltage_regs;
}
}
voltage_regs++;
}
return NULL;
}
static void pfc_rcar_set_voltage(uintptr_t pfc_base, uint16_t pin, uint16_t voltage)
{
uint32_t val;
uint8_t bit;
const struct pfc_pocctrl_reg *voltage_reg;
voltage_reg = pfc_rcar_get_pocctrl_reg(pin, &bit);
if (!voltage_reg) {
return;
}
val = sys_read32(pfc_base + voltage_reg->offset);
switch (voltage) {
case PIN_VOLTAGE_1P8V:
if (!(val & BIT(bit))) {
return;
}
val &= ~BIT(bit);
break;
case PIN_VOLTAGE_3P3V:
if (val & BIT(bit)) {
return;
}
val |= BIT(bit);
break;
default:
break;
}
pfc_rcar_write(pfc_base, voltage_reg->offset, val);
}
#endif /* CONFIG_PINCTRL_RCAR_VOLTAGE_CONTROL */
int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
int ret = 0;
uint8_t reg_index;
uintptr_t pfc_base;
ret = pfc_rcar_get_reg_index(pin->pin, ®_index);
if (ret) {
return ret;
}
if (reg_index >= ARRAY_SIZE(reg_base)) {
return -EINVAL;
}
pfc_base = reg_base[reg_index];
/* Set pin as GPIO if capable */
if (RCAR_IS_GP_PIN(pin->pin)) {
pfc_rcar_set_gpsr(pfc_base, pin->pin, false);
} else if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) == 0U) {
/* A function must be set for non GPIO capable pin */
return -EINVAL;
}
#ifdef CONFIG_PINCTRL_RCAR_VOLTAGE_CONTROL
if (pin->voltage != PIN_VOLTAGE_NONE) {
pfc_rcar_set_voltage(pfc_base, pin->pin, pin->voltage);
}
#endif
/* Select function for pin */
if ((pin->flags & RCAR_PIN_FLAGS_FUNC_SET) != 0U) {
if ((pin->flags & RCAR_PIN_FLAGS_FUNC_DUMMY) == 0U) {
pfc_rcar_set_ipsr(pfc_base, &pin->func);
}
if (RCAR_IS_GP_PIN(pin->pin)) {
pfc_rcar_set_gpsr(pfc_base, pin->pin, true);
}
if ((pin->flags & RCAR_PIN_FLAGS_PULL_SET) != 0U) {
ret = pfc_rcar_set_bias(pfc_base, pin->pin, pin->flags);
if (ret < 0) {
return ret;
}
}
}
if (pin->drive_strength != 0U) {
ret = pfc_rcar_set_drive_strength(pfc_base, pin->pin,
pin->drive_strength);
}
return ret;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
int ret = 0;
ARG_UNUSED(reg);
while (pin_cnt-- > 0U) {
ret = pinctrl_configure_pin(pins++);
if (ret < 0) {
break;
}
}
return ret;
}
#if defined(DEVICE_MMIO_IS_IN_RAM)
__boot_func static int pfc_rcar_driver_init(void)
{
for (unsigned int i = 0; i < ARRAY_SIZE(reg_base); i++) {
device_map(reg_base + i, reg_base[i], reg_sizes[i], K_MEM_CACHE_NONE);
}
return 0;
}
SYS_INIT(pfc_rcar_driver_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/pfc_rcar.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,473 |
```unknown
config PINCTRL_RCAR_PFC
bool "Pin controller driver for Renesas RCar SoC"
default y
depends on DT_HAS_RENESAS_RCAR_PFC_ENABLED
help
Enable pin controller driver for Renesas RCar SoC
config PINCTRL_RCAR_VOLTAGE_CONTROL
bool "Voltage control functionality of Renesas R-Car PFC driver"
default y if SOC_SERIES_RCAR_GEN3
depends on PINCTRL_RCAR_PFC
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```c
/*
*
*/
#include <zephyr/syscall_handler.h>
#include <zephyr/drivers/haptics.h>
static inline int z_vrfy_haptics_start_output(const struct device *dev)
{
Z_OOPS(Z_SYSCALL_DRIVER_HAPTICS(dev, start_output));
return z_impl_haptics_start_output(dev);
}
#include <syscalls/haptics_start_output_mrsh.c>
static inline int z_vrfy_haptics_stop_output(const struct device *dev)
{
Z_OOPS(Z_SYSCALL_DRIVER_HAPTICS(dev, stop_output));
z_impl_haptics_stop_output(dev);
}
#include <syscalls/haptics_stop_output_mrsh.c>
``` | /content/code_sandbox/drivers/haptics/haptics_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 140 |
```c
/*
*
*
* DRV2605 Datasheet: path_to_url
*/
#define DT_DRV_COMPAT ti_drv2605
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/haptics.h>
#include <zephyr/drivers/haptics/drv2605.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/haptics.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(DRV2605, CONFIG_HAPTICS_LOG_LEVEL);
#define DRV2605_REG_STATUS 0x0
#define DRV2605_DEVICE_ID GENMASK(7, 5)
#define DRV2605_DEVICE_ID_DRV2605 0x3
#define DRV2605_DEVICE_ID_DRV2605L 0x7
#define DRV2605_DIAG_RESULT BIT(3)
#define DRV2605_FB_STS BIT(2)
#define DRV2605_OVER_TEMP BIT(1)
#define DRV2605_OC_DETECT BIT(0)
#define DRV2605_REG_MODE 0x1
#define DRV2605_DEV_RESET BIT(7)
#define DRV2605_STANDBY BIT(6)
#define DRV2605_MODE GENMASK(2, 0)
#define DRV2605_REG_RT_PLAYBACK_INPUT 0x2
#define DRV2605_REG_UNNAMED 0x3
#define DRV2605_HI_Z_OUTPUT BIT(4)
#define DRV2605_LIBRARY_SEL GENMASK(2, 0)
#define DRV2605_REG_WAVEFORM_SEQUENCER 0x4
#define DRV2605_WAIT BIT(7)
#define DRV2605_WAV_FRM_SEQ GENMASK(6, 0)
#define DRV2605_REG_GO 0xc
#define DRV2605_GO BIT(0)
#define DRV2605_REG_OVERDRIVE_TIME_OFFSET 0xd
#define DRV2605_REG_SUSTAIN_TIME_OFFSET_POS 0xe
#define DRV2605_REG_SUSTAIN_TIME_OFFSET_NEG 0xf
#define DRV2605_REG_BRAKE_TIME_OFFSET 0x10
#define DRV2605_TIME_STEP_MS 5
#define DRV2605_REG_AUDIO_TO_VIBE_CONTROL 0x11
#define DRV2605_ATH_PEAK_TIME GENMASK(3, 2)
#define DRV2605_ATH_FILTER GENMASK(1, 0)
#define DRV2605_REG_AUDIO_TO_VIBE_MIN_INPUT_LEVEL 0x12
#define DRV2605_REG_AUDIO_TO_VIBE_MAX_INPUT_LEVEL 0x13
#define DRV2605_ATH_INPUT_STEP_UV (1800000 / 255)
#define DRV2605_REG_AUDIO_TO_VIBE_MIN_OUTPUT_DRIVE 0x14
#define DRV2605_REG_AUDIO_TO_VIBE_MAX_OUTPUT_DRIVE 0x15
#define DRV2605_ATH_OUTPUT_DRIVE_PCT (100 * 255)
#define DRV2605_REG_RATED_VOLTAGE 0x16
#define DRV2605_REG_OVERDRIVE_CLAMP_VOLTAGE 0x17
#define DRV2605_REG_AUTO_CAL_COMP_RESULT 0x18
#define DRV2605_REG_AUTO_CAL_BACK_EMF_RESULT 0x19
#define DRV2605_REG_FEEDBACK_CONTROL 0x1a
#define DRV2605_N_ERM_LRA BIT(7)
#define DRV2605_FB_BRAKE_FACTOR GENMASK(6, 4)
#define DRV2605_LOOP_GAIN GENMASK(3, 2)
#define DRV2605_BEMF_GAIN GENMASK(1, 0)
#define DRV2605_ACTUATOR_MODE_ERM 0
#define DRV2605_ACTUATOR_MODE_LRA 1
#define DRV2605_REG_CONTROL1 0x1b
#define DRV2605_STARTUP_BOOST BIT(7)
#define DRV2605_AC_COUPLE BIT(5)
#define DRV2605_DRIVE_TIME GENMASK(4, 0)
#define DRV2605_REG_CONTROL2 0x1c
#define DRV2605_BIDIR_INPUT BIT(7)
#define DRV2605_BRAKE_STABILIZER BIT(6)
#define DRV2605_SAMPLE_TIME GENMASK(5, 4)
#define DRV2605_BLANKING_TIME GENMASK(3, 2)
#define DRV2605_IDISS_TIME GENMASK(1, 0)
#define DRV2605_REG_CONTROL3 0x1d
#define DRV2605_NG_THRESH GENMASK(7, 6)
#define DRV2605_ERM_OPEN_LOOP BIT(5)
#define DRV2605_SUPPLY_COMP_DIS BIT(4)
#define DRV2605_DATA_FORMAT_RTP BIT(3)
#define DRV2605_LRA_DRIVE_MODE BIT(2)
#define DRV2605_N_PWM_ANALOG BIT(1)
#define DRV2605_LRA_OPEN_LOOP BIT(0)
#define DRV2605_REG_CONTROL4 0x1e
#define DRV2605_ZERO_CROSSING_TIME GENMASK(7, 6)
#define DRV2605_AUTO_CAL_TIME GENMASK(5, 4)
#define DRV2605_OTP_STATUS BIT(2)
#define DRV2605_OTP_PROGRAM BIT(0)
#define DRV2605_REG_BATT_VOLTAGE_MONITOR 0x21
#define DRV2605_VBAT_STEP_UV (5600000 / 255)
#define DRV2605_REG_LRA_RESONANCE_PERIOD 0x22
#define DRV2605_POWER_UP_DELAY_US 250
#define DRV2605_VOLTAGE_SCALE_FACTOR_MV 5600
#define DRV2605_CALCULATE_VOLTAGE(_volt) ((_volt * 255) / DRV2605_VOLTAGE_SCALE_FACTOR_MV)
struct drv2605_config {
struct i2c_dt_spec i2c;
struct gpio_dt_spec en_gpio;
struct gpio_dt_spec in_trig_gpio;
uint8_t feedback_brake_factor;
uint8_t loop_gain;
uint8_t rated_voltage;
uint8_t overdrive_clamp_voltage;
uint8_t auto_cal_time;
uint8_t drive_time;
bool actuator_mode;
};
struct drv2605_data {
const struct device *dev;
struct k_work rtp_work;
const struct drv2605_rtp_data *rtp_data;
enum drv2605_mode mode;
};
static inline int drv2605_haptic_config_audio(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
int ret;
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_CONTROL3, DRV2605_N_PWM_ANALOG,
DRV2605_N_PWM_ANALOG);
if (ret < 0) {
return ret;
}
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_CONTROL1, DRV2605_AC_COUPLE,
DRV2605_AC_COUPLE);
if (ret < 0) {
return ret;
}
data->mode = DRV2605_MODE_AUDIO_TO_VIBE;
return 0;
}
static inline int drv2605_haptic_config_pwm_analog(const struct device *dev, const bool analog)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
uint8_t value = 0;
int ret;
if (analog) {
value = DRV2605_N_PWM_ANALOG;
}
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_CONTROL3, DRV2605_N_PWM_ANALOG,
value);
if (ret < 0) {
return ret;
}
data->mode = DRV2605_MODE_PWM_ANALOG_INPUT;
return 0;
}
static void drv2605_rtp_work_handler(struct k_work *work)
{
struct drv2605_data *data = CONTAINER_OF(work, struct drv2605_data, rtp_work);
const struct drv2605_rtp_data *rtp_data = data->rtp_data;
const struct drv2605_config *config = data->dev->config;
int i;
for (i = 0; i < rtp_data->size; i++) {
i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_RT_PLAYBACK_INPUT,
rtp_data->rtp_input[i]);
k_usleep(rtp_data->rtp_hold_us[i]);
}
}
static inline int drv2605_haptic_config_rtp(const struct device *dev,
const struct drv2605_rtp_data *rtp_data)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
int ret;
data->rtp_data = rtp_data;
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_RT_PLAYBACK_INPUT, 0);
if (ret < 0) {
return ret;
}
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_MODE,
(uint8_t)DRV2605_MODE_RTP);
if (ret < 0) {
return ret;
}
data->mode = DRV2605_MODE_RTP;
return 0;
}
static inline int drv2605_haptic_config_rom(const struct device *dev,
const struct drv2605_rom_data *rom_data)
{
const struct drv2605_config *config = dev->config;
uint8_t reg_addr = DRV2605_REG_WAVEFORM_SEQUENCER;
struct drv2605_data *data = dev->data;
int i, ret;
switch (rom_data->trigger) {
case DRV2605_MODE_INTERNAL_TRIGGER:
case DRV2605_MODE_EXTERNAL_EDGE_TRIGGER:
case DRV2605_MODE_EXTERNAL_LEVEL_TRIGGER:
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_MODE,
(uint8_t)rom_data->trigger);
if (ret < 0) {
return ret;
}
data->mode = rom_data->trigger;
break;
default:
return -EINVAL;
}
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_UNNAMED, DRV2605_LIBRARY_SEL,
(uint8_t)rom_data->library);
if (ret < 0) {
return ret;
}
for (i = 0; i < DRV2605_WAVEFORM_SEQUENCER_MAX; i++) {
ret = i2c_reg_write_byte_dt(&config->i2c, reg_addr, rom_data->seq_regs[i]);
if (ret < 0) {
return ret;
}
reg_addr++;
if (rom_data->seq_regs[i] == 0U) {
break;
}
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_OVERDRIVE_TIME_OFFSET,
rom_data->overdrive_time);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_SUSTAIN_TIME_OFFSET_POS,
rom_data->sustain_pos_time);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_SUSTAIN_TIME_OFFSET_NEG,
rom_data->sustain_neg_time);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_BRAKE_TIME_OFFSET,
rom_data->brake_time);
if (ret < 0) {
return ret;
}
return 0;
}
int drv2605_haptic_config(const struct device *dev, enum drv2605_haptics_source source,
const union drv2605_config_data *config_data)
{
switch (source) {
case DRV2605_HAPTICS_SOURCE_ROM:
return drv2605_haptic_config_rom(dev, config_data->rom_data);
case DRV2605_HAPTICS_SOURCE_RTP:
return drv2605_haptic_config_rtp(dev, config_data->rtp_data);
case DRV2605_HAPTICS_SOURCE_AUDIO:
return drv2605_haptic_config_audio(dev);
case DRV2605_HAPTICS_SOURCE_PWM:
return drv2605_haptic_config_pwm_analog(dev, false);
case DRV2605_HAPTICS_SOURCE_ANALOG:
return drv2605_haptic_config_pwm_analog(dev, true);
default:
return -ENOTSUP;
}
return 0;
}
static inline int drv2605_edge_mode_event(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
int ret;
ret = gpio_pin_set_dt(&config->in_trig_gpio, 1);
if (ret < 0) {
return ret;
}
return gpio_pin_set_dt(&config->in_trig_gpio, 0);
}
static int drv2605_stop_output(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
uint8_t value;
int ret;
switch (data->mode) {
case DRV2605_MODE_DIAGNOSTICS:
case DRV2605_MODE_AUTO_CAL:
ret = i2c_reg_read_byte_dt(&config->i2c, DRV2605_REG_GO, &value);
if (ret < 0) {
return ret;
}
if (FIELD_GET(DRV2605_GO, value)) {
LOG_DBG("Playback mode: %d is uninterruptible", data->mode);
return -EBUSY;
}
break;
case DRV2605_MODE_INTERNAL_TRIGGER:
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_GO, DRV2605_GO, 0);
case DRV2605_MODE_EXTERNAL_EDGE_TRIGGER:
return drv2605_edge_mode_event(dev);
case DRV2605_MODE_EXTERNAL_LEVEL_TRIGGER:
return gpio_pin_set_dt(&config->in_trig_gpio, 0);
case DRV2605_MODE_PWM_ANALOG_INPUT:
case DRV2605_MODE_AUDIO_TO_VIBE:
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_MODE,
(uint8_t)DRV2605_MODE_INTERNAL_TRIGGER);
if (ret < 0) {
return ret;
}
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_GO, DRV2605_GO, 0);
case DRV2605_MODE_RTP:
return k_work_cancel(&data->rtp_work);
default:
return -ENOTSUP;
}
return 0;
}
static int drv2605_start_output(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
switch (data->mode) {
case DRV2605_MODE_DIAGNOSTICS:
case DRV2605_MODE_AUTO_CAL:
case DRV2605_MODE_INTERNAL_TRIGGER:
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_GO, DRV2605_GO, DRV2605_GO);
case DRV2605_MODE_EXTERNAL_EDGE_TRIGGER:
return drv2605_edge_mode_event(dev);
case DRV2605_MODE_EXTERNAL_LEVEL_TRIGGER:
return gpio_pin_set_dt(&config->in_trig_gpio, 1);
case DRV2605_MODE_AUDIO_TO_VIBE:
case DRV2605_MODE_PWM_ANALOG_INPUT:
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_MODE,
(uint8_t)data->mode);
case DRV2605_MODE_RTP:
return k_work_submit(&data->rtp_work);
default:
return -ENOTSUP;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int drv2605_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct drv2605_config *config = dev->config;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_STANDBY, 0);
case PM_DEVICE_ACTION_SUSPEND:
return i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_STANDBY,
DRV2605_STANDBY);
case PM_DEVICE_ACTION_TURN_OFF:
if (config->en_gpio.port != NULL) {
gpio_pin_set_dt(&config->en_gpio, 0);
}
break;
case PM_DEVICE_ACTION_TURN_ON:
if (config->en_gpio.port != NULL) {
gpio_pin_set_dt(&config->en_gpio, 1);
}
break;
default:
return -ENOTSUP;
}
return 0;
}
#endif
static int drv2605_hw_config(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
uint8_t mask, value;
int ret;
value = FIELD_PREP(DRV2605_N_ERM_LRA, config->actuator_mode) |
FIELD_PREP(DRV2605_FB_BRAKE_FACTOR, config->feedback_brake_factor) |
FIELD_PREP(DRV2605_LOOP_GAIN, config->loop_gain);
mask = DRV2605_N_ERM_LRA | DRV2605_FB_BRAKE_FACTOR | DRV2605_LOOP_GAIN;
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_FEEDBACK_CONTROL, mask, value);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_RATED_VOLTAGE, config->rated_voltage);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, DRV2605_REG_OVERDRIVE_CLAMP_VOLTAGE,
config->overdrive_clamp_voltage);
if (ret < 0) {
return ret;
}
if (config->actuator_mode == DRV2605_ACTUATOR_MODE_LRA) {
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_CONTROL3,
DRV2605_LRA_OPEN_LOOP, DRV2605_LRA_OPEN_LOOP);
if (ret < 0) {
return ret;
}
}
return 0;
}
static int drv2605_reset(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
int retries = 5, ret;
uint8_t value;
i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_STANDBY, 0);
ret = i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_DEV_RESET,
DRV2605_DEV_RESET);
if (ret < 0) {
return ret;
}
k_msleep(100);
while (retries > 0) {
i2c_reg_read_byte_dt(&config->i2c, DRV2605_REG_MODE, &value);
if ((value & DRV2605_DEV_RESET) == 0U) {
i2c_reg_update_byte_dt(&config->i2c, DRV2605_REG_MODE, DRV2605_STANDBY, 0);
return 0;
}
retries--;
k_usleep(10000);
}
return -ETIMEDOUT;
}
static int drv2605_check_devid(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
uint8_t value;
int ret;
ret = i2c_reg_read_byte_dt(&config->i2c, DRV2605_REG_STATUS, &value);
if (ret < 0) {
return ret;
}
value = FIELD_GET(DRV2605_DEVICE_ID, value);
switch (value) {
case DRV2605_DEVICE_ID_DRV2605:
case DRV2605_DEVICE_ID_DRV2605L:
break;
default:
LOG_ERR("Invalid device ID found");
return -ENOTSUP;
}
LOG_DBG("Found DRV2605, DEVID: 0x%x", value);
return 0;
}
static int drv2605_gpio_config(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
int ret;
if (config->en_gpio.port != NULL) {
if (!gpio_is_ready_dt(&config->en_gpio)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->en_gpio, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
return ret;
}
}
if (config->in_trig_gpio.port != NULL) {
if (!gpio_is_ready_dt(&config->in_trig_gpio)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->in_trig_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
return ret;
}
}
return 0;
}
static int drv2605_init(const struct device *dev)
{
const struct drv2605_config *config = dev->config;
struct drv2605_data *data = dev->data;
int ret;
data->dev = dev;
k_usleep(DRV2605_POWER_UP_DELAY_US);
if (!i2c_is_ready_dt(&config->i2c)) {
return -ENODEV;
}
k_work_init(&data->rtp_work, drv2605_rtp_work_handler);
ret = drv2605_gpio_config(dev);
if (ret < 0) {
LOG_DBG("Failed to allocate GPIOs: %d", ret);
return ret;
}
ret = drv2605_check_devid(dev);
if (ret < 0) {
return ret;
}
ret = drv2605_reset(dev);
if (ret < 0) {
LOG_DBG("Failed to reset device: %d", ret);
return ret;
}
ret = drv2605_hw_config(dev);
if (ret < 0) {
LOG_DBG("Failed to configure device: %d", ret);
return ret;
}
return 0;
}
static const struct haptics_driver_api drv2605_driver_api = {
.start_output = &drv2605_start_output,
.stop_output = &drv2605_stop_output,
};
#define HAPTICS_DRV2605_DEFINE(inst) \
\
static const struct drv2605_config drv2605_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.en_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, en_gpios, {}), \
.in_trig_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, in_trig_gpios, {}), \
.feedback_brake_factor = DT_INST_ENUM_IDX(inst, feedback_brake_factor), \
.loop_gain = DT_INST_ENUM_IDX(inst, loop_gain), \
.actuator_mode = DT_INST_ENUM_IDX(inst, actuator_mode), \
.rated_voltage = DRV2605_CALCULATE_VOLTAGE(DT_INST_PROP(inst, vib_rated_mv)), \
.overdrive_clamp_voltage = \
DRV2605_CALCULATE_VOLTAGE(DT_INST_PROP(inst, vib_overdrive_mv)), \
}; \
\
static struct drv2605_data drv2605_data_##inst = { \
.mode = DRV2605_MODE_INTERNAL_TRIGGER, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(inst, drv2605_pm_action); \
\
DEVICE_DT_INST_DEFINE(inst, drv2605_init, PM_DEVICE_DT_INST_GET(inst), \
&drv2605_data_##inst, &drv2605_config_##inst, POST_KERNEL, \
CONFIG_HAPTICS_INIT_PRIORITY, &drv2605_driver_api);
DT_INST_FOREACH_STATUS_OKAY(HAPTICS_DRV2605_DEFINE)
``` | /content/code_sandbox/drivers/haptics/drv2605.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,193 |
```unknown
#
menuconfig HAPTICS
bool "Haptic feedback drivers"
help
Enable haptics driver configuration.
if HAPTICS
module = HAPTICS
module-str = haptics
source "subsys/logging/Kconfig.template.log_config"
config HAPTICS_INIT_PRIORITY
int "Haptic driver init priority"
default 90
help
Haptic driver initialization priority.
source "drivers/haptics/Kconfig.drv2605"
endif # HAPTICS
``` | /content/code_sandbox/drivers/haptics/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
config HAPTICS_DRV2605
bool "DRV2605 Haptics Driver"
default y
depends on DT_HAS_TI_DRV2605_ENABLED
select I2C
help
Enable I2C-based driver for the Texas Instruments DRV2605 Haptics
Driver.
``` | /content/code_sandbox/drivers/haptics/Kconfig.drv2605 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
config RTC_ATMEL_SAM
bool "Atmel SAM RTC driver"
default y
depends on DT_HAS_ATMEL_SAM_RTC_ENABLED
help
Atmel Real-Time Clock (RTC) driver used on SAM SoC series.
``` | /content/code_sandbox/drivers/rtc/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# Author: Sri Surya <srisurya@linumiz.com>
config RTC_AM1805
bool "AMBIQ AM1805 RTC driver"
default y
depends on DT_HAS_AMBIQ_AM1805_ENABLED
select I2C
help
Enable the AMBIQ AM1805 RTC driver.
if RTC_AM1805
config RTC_AM1805_THREAD_STACK_SIZE
int "Stack size for the am1805 interrupt thread"
default 512
help
Size of the stack used for the thread handling interrupts and dispatching callbacks.
config RTC_AM1805_THREAD_PRIO
int "Priority for the am1805 interrupt thread"
default 0
help
Priority level for the thread handling interrupts and dispatching callbacks.
endif
``` | /content/code_sandbox/drivers/rtc/Kconfig.am1805 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 162 |
```unknown
config RTC_AMBIQ
bool "AMBIQ RTC driver"
default y
depends on DT_HAS_AMBIQ_RTC_ENABLED
select AMBIQ_HAL
help
Enable the AMBIQ RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```c
/*
*
*
*/
#include <errno.h>
#include <pinctrl_soc.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
const struct pfc_drive_reg pfc_drive_regs[] = {
/* DRV0CTRL0 */
{ 0x80, {
{ RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
{ RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
{ RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
{ RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
{ RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
{ RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
{ RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
} },
/* DRV1CTRL0 */
{ 0x84, {
{ RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
{ RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
{ RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
{ RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
} },
/* DRV2CTRL0 */
{ 0x88, {
{ RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
} },
/* DRV3CTRL0 is empty */
/* DRV0CTRL1 */
{ 0x80, {
{ RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
{ RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
{ RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
{ RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
{ RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
{ RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
{ RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
{ RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
} },
/* DRV1CTRL1 */
{ 0x84, {
{ RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
{ RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
{ RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
{ RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
{ RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
{ RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
{ RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
{ RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
} },
/* DRV2CTRL1 */
{ 0x88, {
{ RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
{ RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
{ RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
{ RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
{ RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
{ RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
{ RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
} },
/* DRV3CTRL1 */
{ 0x8c, {
{ RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
} },
/* DRV0CTRL2 */
{ 0x80, {
{ RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
{ RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
{ RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
{ RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
{ RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
{ RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
{ RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
{ RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
} },
/* DRV1CTRL2 */
{ 0x84, {
{ RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
{ RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
{ RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
{ RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
{ RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
{ RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
{ RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
{ RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
} },
/* DRV2CTRL2 */
{ 0x88, {
{ RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
} },
/* DRV3CTRL2 is empty */
/* DRV0CTRL3 */
{ 0x80, {
{ RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
{ RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
{ RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
{ RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
{ RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
{ RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
{ RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
{ RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
} },
/* DRV1CTRL3 */
{ 0x84, {
{ RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
{ RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
} },
/* DRV2CTRL3 */
{ 0x88, {
{ RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
} },
/* DRV3CTRL3 is empty */
/* DRV0CTRL4 */
{ 0x80, {
{ RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
{ RCAR_GP_PIN(4, 6), 24, 3 }, /* GP4_06 */
{ RCAR_GP_PIN(4, 5), 20, 3 }, /* GP4_05 */
{ RCAR_GP_PIN(4, 4), 16, 3 }, /* GP4_04 */
{ RCAR_GP_PIN(4, 3), 12, 3 }, /* GP4_03 */
{ RCAR_GP_PIN(4, 2), 8, 3 }, /* GP4_02 */
{ RCAR_GP_PIN(4, 1), 4, 3 }, /* GP4_01 */
{ RCAR_GP_PIN(4, 0), 0, 3 }, /* GP4_00 */
} },
/* DRV1CTRL4 */
{ 0x84, {
{ RCAR_GP_PIN(4, 15), 28, 3 }, /* GP4_15 */
{ RCAR_GP_PIN(4, 14), 24, 3 }, /* GP4_14 */
{ RCAR_GP_PIN(4, 13), 20, 3 }, /* GP4_13 */
{ RCAR_GP_PIN(4, 12), 16, 3 }, /* GP4_12 */
{ RCAR_GP_PIN(4, 11), 12, 3 }, /* GP4_11 */
{ RCAR_GP_PIN(4, 10), 8, 3 }, /* GP4_10 */
{ RCAR_GP_PIN(4, 9), 4, 3 }, /* GP4_09 */
{ RCAR_GP_PIN(4, 8), 0, 3 }, /* GP4_08 */
} },
/* DRV2CTRL4 */
{ 0x88, {
{ RCAR_GP_PIN(4, 23), 28, 3 }, /* MSPI0CSS1 */
{ RCAR_GP_PIN(4, 22), 24, 3 }, /* MPSI0SO/MSPI0DCS */
{ RCAR_GP_PIN(4, 21), 20, 3 }, /* MPSI0SI */
{ RCAR_GP_PIN(4, 20), 16, 3 }, /* MSPI0SC */
{ RCAR_GP_PIN(4, 19), 12, 3 }, /* GP4_19 */
{ RCAR_GP_PIN(4, 18), 8, 3 }, /* GP4_18 */
{ RCAR_GP_PIN(4, 17), 4, 3 }, /* GP4_17 */
{ RCAR_GP_PIN(4, 16), 0, 3 }, /* GP4_16 */
} },
/* DRV3CTRL4 */
{ 0x8c, {
{ RCAR_GP_PIN(4, 30), 24, 3 }, /* MSPI1CSS1 */
{ RCAR_GP_PIN(4, 29), 20, 3 }, /* MSPI1CSS2 */
{ RCAR_GP_PIN(4, 28), 16, 3 }, /* MSPI1SC */
{ RCAR_GP_PIN(4, 27), 12, 3 }, /* MSPI1CSS0 */
{ RCAR_GP_PIN(4, 26), 8, 3 }, /* MPSI1SO/MSPI1DCS */
{ RCAR_GP_PIN(4, 25), 4, 3 }, /* MSPI1SI */
{ RCAR_GP_PIN(4, 24), 0, 3 }, /* MSPI0CSS0 */
} },
/* DRV0CTRL5 */
{ 0x80, {
{ RCAR_GP_PIN(5, 7), 28, 3 }, /* ETNB0RXD3 */
{ RCAR_GP_PIN(5, 6), 24, 3 }, /* ETNB0RXER */
{ RCAR_GP_PIN(5, 5), 20, 3 }, /* ETNB0MDC */
{ RCAR_GP_PIN(5, 4), 16, 3 }, /* ETNB0LINKSTA */
{ RCAR_GP_PIN(5, 3), 12, 3 }, /* ETNB0WOL */
{ RCAR_GP_PIN(5, 2), 8, 3 }, /* ETNB0MD */
{ RCAR_GP_PIN(5, 1), 4, 3 }, /* RIIC0SDA */
{ RCAR_GP_PIN(5, 0), 0, 3 }, /* RIIC0SCL */
} },
/* DRV1CTRL5 */
{ 0x84, {
{ RCAR_GP_PIN(5, 15), 28, 3 }, /* ETNB0TXCLK */
{ RCAR_GP_PIN(5, 14), 24, 3 }, /* ETNB0TXD3 */
{ RCAR_GP_PIN(5, 13), 20, 3 }, /* ETNB0TXER */
{ RCAR_GP_PIN(5, 12), 16, 3 }, /* ETNB0RXCLK */
{ RCAR_GP_PIN(5, 11), 12, 3 }, /* ETNB0RXD0 */
{ RCAR_GP_PIN(5, 10), 8, 3 }, /* ETNB0RXDV */
{ RCAR_GP_PIN(5, 9), 4, 3 }, /* ETNB0RXD2 */
{ RCAR_GP_PIN(5, 8), 0, 3 }, /* ETNB0RXD1 */
} },
/* DRV2CTRL5 */
{ 0x88, {
{ RCAR_GP_PIN(5, 19), 12, 3 }, /* ETNB0TXD0 */
{ RCAR_GP_PIN(5, 18), 8, 3 }, /* ETNB0TXEN */
{ RCAR_GP_PIN(5, 17), 4, 3 }, /* ETNB0TXD2 */
{ RCAR_GP_PIN(5, 16), 0, 3 }, /* ETNB0TXD1 */
} },
/* DRV3CTRL5 is empty */
/* DRV0CTRL6 */
{ 0x80, {
{ RCAR_GP_PIN(6, 7), 28, 3 }, /* RLIN34RX/INTP20 */
{ RCAR_GP_PIN(6, 6), 24, 3 }, /* RLIN34TX */
{ RCAR_GP_PIN(6, 5), 20, 3 }, /* RLIN35RX/INTP21 */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* RLIN35TX */
{ RCAR_GP_PIN(6, 3), 12, 3 }, /* RLIN36RX/INTP22 */
{ RCAR_GP_PIN(6, 2), 8, 3 }, /* RLIN36TX */
{ RCAR_GP_PIN(6, 1), 4, 3 }, /* RLIN37RX/INTP23 */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* RLIN37TX */
} },
/* DRV1CTRL6 */
{ 0x84, {
{ RCAR_GP_PIN(6, 15), 28, 3 }, /* RLIN30RX/INTP16 */
{ RCAR_GP_PIN(6, 14), 24, 3 }, /* RLIN30TX */
{ RCAR_GP_PIN(6, 13), 20, 3 }, /* RLIN31RX/INTP17 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* RLIN31TX */
{ RCAR_GP_PIN(6, 11), 12, 3 }, /* RLIN32RX/INTP18 */
{ RCAR_GP_PIN(6, 10), 8, 3 }, /* RLIN32TX */
{ RCAR_GP_PIN(6, 9), 4, 3 }, /* RLIN33RX/INTP19 */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* RLIN33TX */
} },
/* DRV2CTRL6 */
{ 0x88, {
{ RCAR_GP_PIN(6, 22), 24, 3 }, /* NMI1 */
{ RCAR_GP_PIN(6, 21), 20, 3 }, /* INTP32 */
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* INTP33 */
{ RCAR_GP_PIN(6, 19), 12, 3 }, /* INTP34 */
{ RCAR_GP_PIN(6, 18), 8, 3 }, /* INTP35 */
{ RCAR_GP_PIN(6, 17), 4, 3 }, /* INTP36 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* INTP37 */
} },
/* DRV3CTRL6 */
{ 0x8c, {
{ RCAR_GP_PIN(6, 31), 28, 3 }, /* PRESETOUT1# */
} },
/* DRV0CTRL7 */
{ 0x80, {
{ RCAR_GP_PIN(7, 7), 28, 3 }, /* CAN3RX/INTP3 */
{ RCAR_GP_PIN(7, 6), 24, 3 }, /* CAN3TX */
{ RCAR_GP_PIN(7, 5), 20, 3 }, /* CAN2RX/INTP2 */
{ RCAR_GP_PIN(7, 4), 16, 3 }, /* CAN2TX */
{ RCAR_GP_PIN(7, 3), 12, 3 }, /* CAN1RX/INTP1 */
{ RCAR_GP_PIN(7, 2), 8, 3 }, /* CAN1TX */
{ RCAR_GP_PIN(7, 1), 4, 3 }, /* CAN0RX/INTP0 */
{ RCAR_GP_PIN(7, 0), 0, 3 }, /* CAN0TX */
} },
/* DRV1CTRL7 */
{ 0x84, {
{ RCAR_GP_PIN(7, 15), 28, 3 }, /* CAN7RX/INTP7 */
{ RCAR_GP_PIN(7, 14), 24, 3 }, /* CAN7TX */
{ RCAR_GP_PIN(7, 13), 20, 3 }, /* CAN6RX/INTP6 */
{ RCAR_GP_PIN(7, 12), 16, 3 }, /* CAN6TX */
{ RCAR_GP_PIN(7, 11), 12, 3 }, /* CAN5RX/INTP5 */
{ RCAR_GP_PIN(7, 10), 8, 3 }, /* CAN5TX */
{ RCAR_GP_PIN(7, 9), 4, 3 }, /* CAN4RX/INTP4 */
{ RCAR_GP_PIN(7, 8), 0, 3 }, /* CAN4TX */
} },
/* DRV2CTRL7 */
{ 0x88, {
{ RCAR_GP_PIN(7, 23), 28, 3 }, /* CAN11RX/INTP11 */
{ RCAR_GP_PIN(7, 22), 24, 3 }, /* CAN11TX */
{ RCAR_GP_PIN(7, 21), 20, 3 }, /* CAN10RX/INTP10 */
{ RCAR_GP_PIN(7, 20), 16, 3 }, /* CAN10TX */
{ RCAR_GP_PIN(7, 19), 12, 3 }, /* CAN9RX/INTP9 */
{ RCAR_GP_PIN(7, 18), 8, 3 }, /* CAN9TX */
{ RCAR_GP_PIN(7, 17), 4, 3 }, /* CAN8RX/INTP8 */
{ RCAR_GP_PIN(7, 16), 0, 3 }, /* CAN8TX */
} },
/* DRV3CTRL7 */
{ 0x8c, {
{ RCAR_GP_PIN(7, 31), 28, 3 }, /* CAN15RX/INTP15 */
{ RCAR_GP_PIN(7, 30), 24, 3 }, /* CAN15TX */
{ RCAR_GP_PIN(7, 29), 20, 3 }, /* CAN14RX/INTP14 */
{ RCAR_GP_PIN(7, 28), 16, 3 }, /* CAN14TX */
{ RCAR_GP_PIN(7, 27), 12, 3 }, /* CAN13RX/INTP13 */
{ RCAR_GP_PIN(7, 26), 8, 3 }, /* CAN13TX */
{ RCAR_GP_PIN(7, 25), 4, 3 }, /* CAN12RX/INTP12 */
{ RCAR_GP_PIN(7, 24), 0, 3 }, /* CAN12TX */
} },
/* DRV0CTRLSYS0 */
{ 0x80, {
{ RCAR_GP_PIN(8, 0), 0, 3 }, /* PRESETOUT0# */
} },
/* DRV1CTRLSYS0 */
{ 0x84, {
{ RCAR_GP_PIN(8, 12), 16, 2 }, /* DCUTCK0 */
{ RCAR_GP_PIN(8, 11), 12, 2 }, /* DCUTDO0 */
{ RCAR_GP_PIN(8, 10), 8, 2 }, /* DCUTDI0 */
{ RCAR_GP_PIN(8, 9), 4, 2 }, /* DCUTDY0# */
{ RCAR_GP_PIN(8, 8), 0, 2 }, /* DCUTMS0 */
} },
{ },
};
#define PFC_BIAS_REG(r1, r2) \
.puen = r1, \
.pud = r2, \
.pins =
const struct pfc_bias_reg pfc_bias_regs[] = {
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN0, PUD0 */
[0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
[1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
[2] = RCAR_GP_PIN(0, 2), /* HRX0 */
[3] = RCAR_GP_PIN(0, 3), /* HTX0 */
[4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
[5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
[6] = RCAR_GP_PIN(0, 6), /* RX0 */
[7] = RCAR_GP_PIN(0, 7), /* TX0 */
[8] = RCAR_GP_PIN(0, 8), /* SCK0 */
[9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
[10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
[11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
[12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
[13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
[14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
[15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
[16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
[17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
[18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
[19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
[20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN1, PUD1 */
[0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
[1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
[2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
[3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
[4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
[5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
[6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
[7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
[8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
[9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
[10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
[11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
[12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
[13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
[14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
[15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
[16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
[17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
[18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
[19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
[20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
[21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
[22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
[23] = RCAR_GP_PIN(1, 23), /* SD_CD */
[24] = RCAR_GP_PIN(1, 24), /* SD_WP */
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN2, PUD2 */
[0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
[1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
[2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
[3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
[4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
[5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
[6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
[7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
[8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
[9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
[10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
[11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
[12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
[13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
[14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
[15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
[16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN3, PUD3 */
[0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
[1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
[2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
[3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
[4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
[5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
[6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
[7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
[8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
[9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
[10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
[11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
[12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
[13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
[14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
[15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
[16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
[17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
[18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN4, PUD4 */
[0] = RCAR_GP_PIN(4, 0), /* GP4_00 */
[1] = RCAR_GP_PIN(4, 1), /* GP4_01 */
[2] = RCAR_GP_PIN(4, 2), /* GP4_02 */
[3] = RCAR_GP_PIN(4, 3), /* GP4_03 */
[4] = RCAR_GP_PIN(4, 4), /* GP4_04 */
[5] = RCAR_GP_PIN(4, 5), /* GP4_05 */
[6] = RCAR_GP_PIN(4, 6), /* GP4_06 */
[7] = RCAR_GP_PIN(4, 7), /* GP4_07 */
[8] = RCAR_GP_PIN(4, 8), /* GP4_08 */
[9] = RCAR_GP_PIN(4, 9), /* GP4_09 */
[10] = RCAR_GP_PIN(4, 10), /* GP4_10 */
[11] = RCAR_GP_PIN(4, 11), /* GP4_11 */
[12] = RCAR_GP_PIN(4, 12), /* GP4_12 */
[13] = RCAR_GP_PIN(4, 13), /* GP4_13 */
[14] = RCAR_GP_PIN(4, 14), /* GP4_14 */
[15] = RCAR_GP_PIN(4, 15), /* GP4_15 */
[16] = RCAR_GP_PIN(4, 16), /* GP4_16 */
[17] = RCAR_GP_PIN(4, 17), /* GP4_17 */
[18] = RCAR_GP_PIN(4, 18), /* GP4_18 */
[19] = RCAR_GP_PIN(4, 19), /* GP4_19 */
[20] = RCAR_GP_PIN(4, 20), /* MSPI0SC */
[21] = RCAR_GP_PIN(4, 21), /* MSPI0SI */
[22] = RCAR_GP_PIN(4, 22), /* MSPI0SO/MSPI0DCS */
[23] = RCAR_GP_PIN(4, 23), /* MSPI0CSS1 */
[24] = RCAR_GP_PIN(4, 24), /* MSPI0CSS0 */
[25] = RCAR_GP_PIN(4, 25), /* MSPI1SI */
[26] = RCAR_GP_PIN(4, 26), /* MSPI1SO/MSPI1DCS */
[27] = RCAR_GP_PIN(4, 27), /* MSPI1CSS0 */
[28] = RCAR_GP_PIN(4, 28), /* MSPI1SC */
[29] = RCAR_GP_PIN(4, 29), /* MSPI1CSS2 */
[30] = RCAR_GP_PIN(4, 30), /* MSPI1CSS1 */
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN5, PUD5 */
[0] = RCAR_GP_PIN(5, 0), /* RIIC0SCL */
[1] = RCAR_GP_PIN(5, 1), /* RIIC0SDA */
[2] = RCAR_GP_PIN(5, 2), /* ETNB0MD */
[3] = RCAR_GP_PIN(5, 3), /* ETNB0WOL */
[4] = RCAR_GP_PIN(5, 4), /* ETNB0LINKSTA */
[5] = RCAR_GP_PIN(5, 5), /* ETNB0MDC */
[6] = RCAR_GP_PIN(5, 6), /* ETNB0RXER */
[7] = RCAR_GP_PIN(5, 7), /* ETNB0RXD3 */
[8] = RCAR_GP_PIN(5, 8), /* ETNB0RXD1 */
[9] = RCAR_GP_PIN(5, 9), /* ETNB0RXD2 */
[10] = RCAR_GP_PIN(5, 10), /* ETNB0RXDV */
[11] = RCAR_GP_PIN(5, 11), /* ETNB0RXD0 */
[12] = RCAR_GP_PIN(5, 12), /* ETNB0RXCLK */
[13] = RCAR_GP_PIN(5, 13), /* ETNB0TXER */
[14] = RCAR_GP_PIN(5, 14), /* ETNB0TXD3 */
[15] = RCAR_GP_PIN(5, 15), /* ETNB0TXCLK */
[16] = RCAR_GP_PIN(5, 16), /* ETNB0TXD1 */
[17] = RCAR_GP_PIN(5, 17), /* ETNB0TXD2 */
[18] = RCAR_GP_PIN(5, 18), /* ETNB0TXEN */
[19] = RCAR_GP_PIN(5, 19), /* ETNB0TXD0 */
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN6, PUD6 */
[0] = RCAR_GP_PIN(6, 0), /* RLIN37TX */
[1] = RCAR_GP_PIN(6, 1), /* RLIN37RX/INTP23 */
[2] = RCAR_GP_PIN(6, 2), /* RLIN36TX */
[3] = RCAR_GP_PIN(6, 3), /* RLIN36RX/INTP22 */
[4] = RCAR_GP_PIN(6, 4), /* RLIN35TX */
[5] = RCAR_GP_PIN(6, 5), /* RLIN35RX/INTP21 */
[6] = RCAR_GP_PIN(6, 6), /* RLIN34TX */
[7] = RCAR_GP_PIN(6, 7), /* RLIN34RX/INTP20 */
[8] = RCAR_GP_PIN(6, 8), /* RLIN33TX */
[9] = RCAR_GP_PIN(6, 9), /* RLIN33RX/INTP19 */
[10] = RCAR_GP_PIN(6, 10), /* RLIN32TX */
[11] = RCAR_GP_PIN(6, 11), /* RLIN32RX/INTP18 */
[12] = RCAR_GP_PIN(6, 12), /* RLIN31TX */
[13] = RCAR_GP_PIN(6, 13), /* RLIN31RX/INTP17 */
[14] = RCAR_GP_PIN(6, 14), /* RLIN30TX */
[15] = RCAR_GP_PIN(6, 15), /* RLIN30RX/INTP16 */
[16] = RCAR_GP_PIN(6, 16), /* INTP37 */
[17] = RCAR_GP_PIN(6, 17), /* INTP36 */
[18] = RCAR_GP_PIN(6, 18), /* INTP35 */
[19] = RCAR_GP_PIN(6, 19), /* INTP34 */
[20] = RCAR_GP_PIN(6, 20), /* INTP33 */
[21] = RCAR_GP_PIN(6, 21), /* INTP32 */
[22] = RCAR_GP_PIN(6, 22), /* NMI1 */
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
} },
{ PFC_BIAS_REG(0xc0, 0xe0) { /* PUEN7, PUD7 */
[0] = RCAR_GP_PIN(7, 0), /* CAN0TX */
[1] = RCAR_GP_PIN(7, 1), /* CAN0RX/INTP0 */
[2] = RCAR_GP_PIN(7, 2), /* CAN1TX */
[3] = RCAR_GP_PIN(7, 3), /* CAN1RX/INTP1 */
[4] = RCAR_GP_PIN(7, 4), /* CAN2TX */
[5] = RCAR_GP_PIN(7, 5), /* CAN2RX/INTP2 */
[6] = RCAR_GP_PIN(7, 6), /* CAN3TX */
[7] = RCAR_GP_PIN(7, 7), /* CAN3RX/INTP3 */
[8] = RCAR_GP_PIN(7, 8), /* CAN4TX */
[9] = RCAR_GP_PIN(7, 9), /* CAN4RX/INTP4 */
[10] = RCAR_GP_PIN(7, 10), /* CAN5TX */
[11] = RCAR_GP_PIN(7, 11), /* CAN5RX/INTP5 */
[12] = RCAR_GP_PIN(7, 12), /* CAN6TX */
[13] = RCAR_GP_PIN(7, 13), /* CAN6RX/INTP6 */
[14] = RCAR_GP_PIN(7, 14), /* CAN7TX */
[15] = RCAR_GP_PIN(7, 15), /* CAN7RX/INTP7 */
[16] = RCAR_GP_PIN(7, 16), /* CAN8TX */
[17] = RCAR_GP_PIN(7, 17), /* CAN8RX/INTP8 */
[18] = RCAR_GP_PIN(7, 18), /* CAN9TX */
[19] = RCAR_GP_PIN(7, 19), /* CAN9RX/INTP9 */
[20] = RCAR_GP_PIN(7, 20), /* CAN10TX */
[21] = RCAR_GP_PIN(7, 21), /* CAN10RX/INTP10 */
[22] = RCAR_GP_PIN(7, 22), /* CAN11TX */
[23] = RCAR_GP_PIN(7, 23), /* CAN11RX/INTP11 */
[24] = RCAR_GP_PIN(7, 24), /* CAN12TX */
[25] = RCAR_GP_PIN(7, 25), /* CAN12RX/INTP12 */
[26] = RCAR_GP_PIN(7, 26), /* CAN13TX */
[27] = RCAR_GP_PIN(7, 27), /* CAN13RX/INTP13 */
[28] = RCAR_GP_PIN(7, 28), /* CAN14TX */
[29] = RCAR_GP_PIN(7, 29), /* CAN14RX/INTP14 */
[30] = RCAR_GP_PIN(7, 30), /* CAN15TX */
[31] = RCAR_GP_PIN(7, 31), /* CAN15RX/INTP15 */
} },
{ /* sentinel */ },
};
const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
{
return pfc_bias_regs;
}
const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
{
return pfc_drive_regs;
}
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
{
if (RCAR_IS_GP_PIN(pin) == false) {
return -EINVAL;
}
*reg_index = pin / 32;
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11,676 |
```unknown
# Intel SoC RTC configuration options
config RTC_MOTOROLA_MC146818
bool "RTC driver for x86 CMOS/RTC clock"
default y if !COUNTER
depends on DT_HAS_MOTOROLA_MC146818_ENABLED
``` | /content/code_sandbox/drivers/rtc/Kconfig.mc146818 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_fake_rtc
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/drivers/rtc/rtc_fake.h>
#ifdef CONFIG_ZTEST
#include <zephyr/ztest.h>
#endif /* CONFIG_ZTEST */
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_set_time, const struct device *, const struct rtc_time *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_get_time, const struct device *, struct rtc_time *);
#ifdef CONFIG_RTC_ALARM
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_supported_fields, const struct device *, uint16_t,
uint16_t *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_time, const struct device *, uint16_t, uint16_t,
const struct rtc_time *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t *,
struct rtc_time *);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_is_pending, const struct device *, uint16_t);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *, uint16_t,
rtc_alarm_callback, void *);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *,
rtc_update_callback, void *);
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_set_calibration, const struct device *, int32_t);
DEFINE_FAKE_VALUE_FUNC(int, rtc_fake_get_calibration, const struct device *, int32_t *);
#endif /* CONFIG_RTC_CALIBRATION */
#ifdef CONFIG_ZTEST
static void fake_rtc_reset_rule_before(const struct ztest_unit_test *test, void *fixture)
{
ARG_UNUSED(test);
ARG_UNUSED(fixture);
RESET_FAKE(rtc_fake_set_time);
RESET_FAKE(rtc_fake_get_time);
#ifdef CONFIG_RTC_ALARM
RESET_FAKE(rtc_fake_alarm_get_supported_fields);
RESET_FAKE(rtc_fake_alarm_set_time);
RESET_FAKE(rtc_fake_alarm_get_time);
RESET_FAKE(rtc_fake_alarm_is_pending);
RESET_FAKE(rtc_fake_alarm_set_callback);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
RESET_FAKE(rtc_fake_update_set_callback);
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
RESET_FAKE(rtc_fake_set_calibration);
RESET_FAKE(rtc_fake_get_calibration);
#endif /* CONFIG_RTC_CALIBRATION */
}
ZTEST_RULE(fake_rtc_reset_rule, fake_rtc_reset_rule_before, NULL);
#endif /* CONFIG_ZTEST */
static const struct rtc_driver_api rtc_fake_driver_api = {
.set_time = rtc_fake_set_time,
.get_time = rtc_fake_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rtc_fake_alarm_get_supported_fields,
.alarm_set_time = rtc_fake_alarm_set_time,
.alarm_get_time = rtc_fake_alarm_get_time,
.alarm_is_pending = rtc_fake_alarm_is_pending,
.alarm_set_callback = rtc_fake_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
.update_set_callback = rtc_fake_update_set_callback,
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = rtc_fake_set_calibration,
.get_calibration = rtc_fake_get_calibration,
#endif /* CONFIG_RTC_CALIBRATION */
};
#define RTC_FAKE_DEVICE_INIT(inst) \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, NULL, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
&rtc_fake_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RTC_FAKE_DEVICE_INIT);
``` | /content/code_sandbox/drivers/rtc/rtc_fake.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 772 |
```unknown
config RTC_STM32
bool "STM32 RTC driver"
default y if !COUNTER
depends on DT_HAS_ST_STM32_RTC_ENABLED && !SOC_SERIES_STM32F1X
select USE_STM32_LL_RTC
select USE_STM32_LL_PWR
select USE_STM32_LL_RCC
help
Build RTC driver for STM32 SoCs, excluding STM32F1 series.
``` | /content/code_sandbox/drivers/rtc/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include "rtc_utils.h"
#include <stdint.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/sys/timeutil.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pcf8563);
#define DT_DRV_COMPAT nxp_pcf8563
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int1_gpios) && \
(defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE))
/* The user may need only alarms but not interrupts so we will only
* include all the interrupt code if the user configured it in the dts
*/
#define PCF8563_INT1_GPIOS_IN_USE 1
#endif
/* The device registers */
#define PCF8563_TIME_DATE_REGISTER 0x02
#define PCF8563_ALARM_REGISTER 0x09
#define PCF8563_CONTROL1_REGISTER 0x00
#define PCF8563_CONTROL2_REGISTER 0x01
#define PCF8563_CONTROL2_REGISTER_TIE_EN (1 << 0)
#define PCF8563_CONTROL2_REGISTER_AIE_EN (1 << 1)
/* These masks were retrieved from the datasheet
* path_to_url
* page 6, section 8.2 Register organization.
* Basically, I clean the unused bits and the bits used
* for other stuff
*/
#define PCF8563_SECONDS_MASK GENMASK(6, 0)
#define PCF8563_MINUTES_MASK GENMASK(6, 0)
#define PCF8563_HOURS_MASK GENMASK(5, 0)
#define PCF8563_DAYS_MASK GENMASK(5, 0)
#define PCF8563_WEEKDAYS_MASK GENMASK(2, 0)
#define PCF8563_MONTHS_MASK GENMASK(4, 0)
/* RTC alarm time fields supported by the PCF8563, page 7 of the datasheet */
#define PCF8563_RTC_ALARM_TIME_MASK \
(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY | \
RTC_ALARM_TIME_MASK_WEEKDAY)
#define PCF8563_RTC_TIME_MASK \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR | \
RTC_ALARM_TIME_MASK_WEEKDAY)
struct pcf8563_config {
const struct i2c_dt_spec i2c;
#ifdef PCF8563_INT1_GPIOS_IN_USE
const struct gpio_dt_spec int1;
#endif
};
#ifdef PCF8563_INT1_GPIOS_IN_USE
/* This work will run the user callback function */
void callback_work_handler(struct k_work *work);
K_WORK_DEFINE(callback_work, callback_work_handler);
#endif
struct pcf8563_data {
#ifdef PCF8563_INT1_GPIOS_IN_USE
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
const struct device *dev;
struct gpio_callback int1_callback;
struct k_work callback_work;
#endif
};
/**
* The format described below is described in the datasheet
* path_to_url page 10 starting
* with 8.4.2 Register Minutes.
*
* For seconds, first bit is ignored (it is used to check the clock integrity).
* The upper digit takes the next 3 bits for the tens place and then the rest
* bits for the unit
* So for example, value 43 is 40 * 10 + 3, so the tens digit is 4 and unit digit is 3.
* Then we put the number 3 in the last 4 bits and the number 4 in next 3 bits
* It uses BCD notation so the number 3 is 0011 and the number for is 100 so the final
* byte is 0 (ignored bit) 100 (the 4) 0011 (the 3) -> 0100001
* Luckily, zephyr provides a couple of functions to do exactlly this: bin2bcd and bcd2bin,
* but we will take care about the bits marked as non used in
* the datasheet because they may contain unexpected values. Applying a mask will help us
* to sanitize the read values
*/
int pcf8563_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
const struct pcf8563_config *config = dev->config;
int ret;
uint8_t raw_time[7];
if (!rtc_utils_validate_rtc_time(timeptr, PCF8563_RTC_TIME_MASK)) {
LOG_ERR("invalid time");
return -EINVAL;
}
/* Set seconds */
raw_time[0] = bin2bcd(timeptr->tm_sec);
/* Set minutes */
raw_time[1] = bin2bcd(timeptr->tm_min);
/* Set hours */
raw_time[2] = bin2bcd(timeptr->tm_hour);
/* Set days */
raw_time[3] = bin2bcd(timeptr->tm_mday);
/* Set weekdays */
raw_time[4] = timeptr->tm_wday;
/*Set month */
raw_time[5] = bin2bcd(timeptr->tm_mon);
/* Set year */
raw_time[6] = bin2bcd(timeptr->tm_year);
/* Write to device */
ret = i2c_burst_write_dt(&config->i2c, PCF8563_TIME_DATE_REGISTER,
raw_time, sizeof(raw_time));
if (ret) {
LOG_ERR("Error when setting time: %i", ret);
return ret;
}
return 0;
}
int pcf8563_get_time(const struct device *dev, struct rtc_time *timeptr)
{
const struct pcf8563_config *config = dev->config;
int ret;
uint8_t raw_time[7];
ret = i2c_burst_read_dt(&config->i2c, PCF8563_TIME_DATE_REGISTER,
raw_time, sizeof(raw_time));
if (ret) {
LOG_ERR("Unable to get time. Err: %i", ret);
return ret;
}
/* Check integrity, if the first bit is 1 it is ok */
if (raw_time[0] & BIT(7)) {
LOG_WRN("Clock integrity failed");
return -ENODATA;
}
/* Nanoseconds */
timeptr->tm_nsec = 0;
/* Get seconds */
timeptr->tm_sec = bcd2bin(raw_time[0] & PCF8563_SECONDS_MASK);
/* Get minutes */
timeptr->tm_min = bcd2bin(raw_time[1] & PCF8563_MINUTES_MASK);
/* Get hours */
timeptr->tm_hour = bcd2bin(raw_time[2] & PCF8563_HOURS_MASK);
/* Get days */
timeptr->tm_mday = bcd2bin(raw_time[3] & PCF8563_DAYS_MASK);
/* Get weekdays */
timeptr->tm_wday = raw_time[4] & PCF8563_WEEKDAYS_MASK;
/* Get month */
timeptr->tm_mon = bcd2bin(raw_time[5] & PCF8563_MONTHS_MASK);
/* Get year */
timeptr->tm_year = bcd2bin(raw_time[6]);
/* Day number not used */
timeptr->tm_yday = -1;
/* DST not used */
timeptr->tm_isdst = -1;
return 0;
}
#ifdef CONFIG_RTC_ALARM
static int pcf8563_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
ARG_UNUSED(dev);
/* This device only has one channel*/
if (id != 0) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
*mask = PCF8563_RTC_ALARM_TIME_MASK;
return 0;
}
static int pcf8563_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
const struct pcf8563_config *config = dev->config;
uint8_t regs[4];
int ret;
if (id != 0) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
if ((mask & ~(PCF8563_RTC_ALARM_TIME_MASK)) != 0) {
LOG_ERR("invalid alarm field mask 0x%04x", mask);
return -EINVAL;
}
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_ERR("invalid alarm time");
return -EINVAL;
}
/*
* The first bit is used as enabled/disabled flag.
* The mask will clean it and also the unused bits
*/
if ((mask & RTC_ALARM_TIME_MASK_MINUTE) != 0) {
regs[0] = bin2bcd(timeptr->tm_min) & PCF8563_MINUTES_MASK;
} else {
/* First bit to 1 is alarm disabled */
regs[0] = BIT(7);
}
if ((mask & RTC_ALARM_TIME_MASK_HOUR) != 0) {
regs[1] = bin2bcd(timeptr->tm_hour) & PCF8563_HOURS_MASK;
} else {
regs[1] = BIT(7);
}
if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) != 0) {
regs[2] = bin2bcd(timeptr->tm_mday) & PCF8563_DAYS_MASK;
} else {
regs[2] = BIT(7);
}
if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) != 0) {
regs[3] = bin2bcd(timeptr->tm_wday) & PCF8563_WEEKDAYS_MASK;
} else {
regs[3] = BIT(7);
}
ret = i2c_burst_write_dt(&config->i2c, PCF8563_ALARM_REGISTER, regs, sizeof(regs));
if (ret) {
LOG_ERR("Error when setting alarm: %i", ret);
return ret;
}
/* Dont forget to enable interrupts */
i2c_reg_write_byte_dt(
&config->i2c,
PCF8563_CONTROL2_REGISTER,
PCF8563_CONTROL2_REGISTER_TIE_EN | PCF8563_CONTROL2_REGISTER_AIE_EN
);
return 0;
}
static int pcf8563_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
const struct pcf8563_config *config = dev->config;
uint8_t regs[4];
int err;
if (id != 0) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
err = i2c_burst_read_dt(&config->i2c, PCF8563_ALARM_REGISTER, regs, sizeof(regs));
if (err) {
LOG_ERR("Error when getting alarm time: %i", err);
return err;
}
/* Initialize data structure and mask */
memset(timeptr, 0U, sizeof(*timeptr));
*mask = 0U;
/* The first bit is the enabled flag */
if (regs[0] & BIT(7)) {
timeptr->tm_min = bcd2bin(regs[0] & GENMASK(6, 0));
*mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if (regs[1] & BIT(7)) {
timeptr->tm_hour = bcd2bin(regs[1] & GENMASK(5, 0));
*mask |= RTC_ALARM_TIME_MASK_HOUR;
}
if (regs[2] & BIT(7)) {
timeptr->tm_mday = bcd2bin(regs[2] & GENMASK(5, 0));
*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
if (regs[3] & BIT(7)) {
timeptr->tm_wday = bcd2bin(regs[3] & GENMASK(2, 0));
*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
}
return 0;
}
static int pcf8563_alarm_is_pending(const struct device *dev, uint16_t id)
{
/* The description of this register is at page 7, section 8.3.2 Register Control_status_2
* There are several kinds of alarms, but here we only need to know that anything but 0
* means that there was some kind of alarm active
*/
const struct pcf8563_config *config = dev->config;
uint8_t reg;
int err;
if (id != 0) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
err = i2c_reg_read_byte_dt(&config->i2c, PCF8563_CONTROL2_REGISTER, ®);
if (err) {
LOG_ERR("Error when getting the control register 2: %i", err);
return err;
}
/* Only the last bits use useful here */
if (reg & GENMASK(3, 2)) {
/* Clean the alarm */
err = i2c_reg_write_byte_dt(&config->i2c, PCF8563_CONTROL2_REGISTER, GENMASK(1, 0));
if (err) {
LOG_ERR("Error when clearing alarms: %d", err);
return err;
}
/* There was an alarm */
return 1;
}
/* No alarms */
return 0;
}
#endif
#ifdef PCF8563_INT1_GPIOS_IN_USE
/* The logic related to the pin interrupt logic */
void callback_work_handler(struct k_work *work)
{
/* This function is run as a work so the user can spend here all the necessary time */
struct pcf8563_data *data = CONTAINER_OF(work, struct pcf8563_data, callback_work);
if (data->alarm_callback == NULL) {
LOG_WRN("No PCF8563 alarm callback function provided");
} else {
data->alarm_callback(data->dev, 0, data->alarm_user_data);
}
}
/* The function called when the clock alarm activates the interrupt*/
void gpio_callback_function(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
struct pcf8563_data *data = CONTAINER_OF(cb, struct pcf8563_data, int1_callback);
LOG_DBG("PCF8563 interrupt detected");
/* By using a work we are able to run "heavier" code */
k_work_submit(&(data->callback_work));
}
#endif
static int pcf8563_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
#ifndef PCF8563_INT1_GPIOS_IN_USE
ARG_UNUSED(dev);
ARG_UNUSED(id);
ARG_UNUSED(callback);
ARG_UNUSED(user_data);
return -ENOTSUP;
#else
const struct pcf8563_config *config = dev->config;
struct pcf8563_data *data = dev->data;
int ret;
if (config->int1.port == NULL) {
return -ENOTSUP;
}
if (id != 0) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
data->alarm_callback = callback;
data->alarm_user_data = user_data;
data->dev = dev;
/* The PCF8563 int pin requires a pull up to work */
ret = gpio_pin_configure_dt(&config->int1, GPIO_INPUT | GPIO_PULL_UP);
if (ret < 0) {
LOG_ERR("Error %d: failed to configure %s pin %d",
ret, config->int1.port->name, config->int1.pin);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->int1, GPIO_INT_EDGE_FALLING);
if (ret < 0) {
LOG_ERR("Error %d: failed to configure interrupt on %s pin %d",
ret, config->int1.port->name, config->int1.pin);
return ret;
}
gpio_init_callback(&data->int1_callback, gpio_callback_function, BIT(config->int1.pin));
gpio_add_callback(config->int1.port, &data->int1_callback);
LOG_DBG("Alarm set");
return 0;
#endif
}
static const struct rtc_driver_api pcf8563_driver_api = {
.set_time = pcf8563_set_time,
.get_time = pcf8563_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = pcf8563_alarm_get_supported_fields,
.alarm_set_time = pcf8563_alarm_set_time,
.alarm_get_time = pcf8563_alarm_get_time,
.alarm_is_pending = pcf8563_alarm_is_pending,
.alarm_set_callback = pcf8563_alarm_set_callback,
#endif
};
int pcf8563_init(const struct device *dev)
{
const struct pcf8563_config *config = dev->config;
int ret;
uint8_t reg;
#ifdef PCF8563_INT1_GPIOS_IN_USE
struct pcf8563_data *data = dev->data;
data->callback_work = callback_work;
#endif
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("Failed to get pointer to %s device!", config->i2c.bus->name);
return -ENODEV;
}
/* Check if it's alive. */
ret = i2c_reg_read_byte_dt(&config->i2c, PCF8563_CONTROL1_REGISTER, ®);
if (ret) {
LOG_ERR("Failed to read from PCF85063! (err %i)", ret);
return -ENODEV;
}
LOG_INF("%s is initialized!", dev->name);
return 0;
}
#define PCF8563_INIT(inst) \
static const struct pcf8563_config pcf8563_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
IF_ENABLED(PCF8563_INT1_GPIOS_IN_USE, \
(.int1 = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0}))) \
}; \
\
static struct pcf8563_data pcf8563_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &pcf8563_init, NULL, \
&pcf8563_data_##inst, &pcf8563_config_##inst, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, &pcf8563_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PCF8563_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_pcf8563.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,098 |
```c
/*
*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/rtc.h>
#include <time.h>
#include <stdlib.h>
/* Formats accepted when setting date and/or time */
static const char format_iso8601[] = "%FT%T";
static const char format_time[] = "%T"; /* hh:mm:ss */
static const char format_date[] = " %F"; /* yyyy-mm-dd */
static const char *consume_chars(const char *s, char *dest, unsigned int cnt)
{
if (strlen(s) < cnt) {
return NULL;
}
memcpy(dest, s, cnt);
dest[cnt] = '\0';
return s + cnt;
}
static const char *consume_char(const char *s, char ch)
{
if (*s != ch) {
return NULL;
}
return ++s;
}
static const char *consume_date(const char *s, struct tm *tm_time)
{
char year[4 + 1];
char month[2 + 1];
char day[2 + 1];
s = consume_chars(s, year, 4);
if (!s) {
return NULL;
}
s = consume_char(s, '-');
if (!s) {
return NULL;
}
s = consume_chars(s, month, 2);
if (!s) {
return NULL;
}
s = consume_char(s, '-');
if (!s) {
return NULL;
}
s = consume_chars(s, day, 2);
if (!s) {
return NULL;
}
tm_time->tm_year = atoi(year) - 1900;
tm_time->tm_mon = atoi(month) - 1;
tm_time->tm_mday = atoi(day);
return s;
}
static const char *consume_time(const char *s, struct tm *tm_time)
{
char hour[2 + 1];
char minute[2 + 1];
char second[2 + 1];
s = consume_chars(s, hour, 2);
if (!s) {
return NULL;
}
s = consume_char(s, ':');
if (!s) {
return NULL;
}
s = consume_chars(s, minute, 2);
if (!s) {
return NULL;
}
s = consume_char(s, ':');
if (!s) {
return NULL;
}
s = consume_chars(s, second, 2);
if (!s) {
return NULL;
}
tm_time->tm_hour = atoi(hour);
tm_time->tm_min = atoi(minute);
tm_time->tm_sec = atoi(second);
return s;
}
static char *strptime(const char *s, const char *format, struct tm *tm_time)
{
/* Reduced implementation of strptime -
* accepting only the 3 different format strings
*/
if (!strcmp(format, format_iso8601)) {
s = consume_date(s, tm_time);
if (!s) {
return NULL;
}
s = consume_char(s, 'T');
if (!s) {
return NULL;
}
s = consume_time(s, tm_time);
if (!s) {
return NULL;
}
return (char *)s;
} else if (!strcmp(format, format_time)) {
return (char *)consume_time(s, tm_time);
} else if (!strcmp(format, format_date)) {
return (char *)consume_date(s, tm_time);
} else {
return NULL;
}
}
static int cmd_set(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev = device_get_binding(argv[1]);
if (!device_is_ready(dev)) {
shell_error(sh, "device %s not ready", argv[1]);
return -ENODEV;
}
argc--;
argv++;
struct rtc_time rtctime = {0};
struct tm *tm_time = rtc_time_to_tm(&rtctime);
(void)rtc_get_time(dev, &rtctime);
const char *format;
if (strchr(argv[1], 'T')) {
format = format_iso8601;
} else if (strchr(argv[1], '-')) {
format = format_date;
} else {
format = format_time;
}
char *parseRes = strptime(argv[1], format, tm_time);
if (!parseRes || *parseRes != '\0') {
shell_error(sh, "Error in argument format");
return -EINVAL;
}
int res = rtc_set_time(dev, &rtctime);
if (-EINVAL == res) {
shell_error(sh, "error in time");
return -EINVAL;
}
return res;
}
static int cmd_get(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev = device_get_binding(argv[1]);
if (!device_is_ready(dev)) {
shell_error(sh, "device %s not ready", argv[1]);
return -ENODEV;
}
struct rtc_time rtctime;
int res = rtc_get_time(dev, &rtctime);
if (-ENODATA == res) {
shell_print(sh, "RTC not set");
return 0;
}
if (res < 0) {
return res;
}
shell_print(sh, "%04d-%02d-%02dT%02d:%02d:%02d.%03d", rtctime.tm_year + 1900,
rtctime.tm_mon + 1, rtctime.tm_mday, rtctime.tm_hour, rtctime.tm_min,
rtctime.tm_sec, rtctime.tm_nsec / 1000000);
return 0;
}
static void device_name_get(size_t idx, struct shell_static_entry *entry)
{
const struct device *dev = shell_device_lookup(idx, NULL);
entry->syntax = (dev != NULL) ? dev->name : NULL;
entry->handler = NULL;
entry->help = NULL;
entry->subcmd = NULL;
}
#define RTC_GET_HELP \
("Get current time (UTC)\n" \
"Usage: rtc get <device>")
#define RTC_SET_HELP \
("Set UTC time\n" \
"Usage: rtc set <device> <YYYY-MM-DDThh:mm:ss> | <YYYY-MM-DD> | <hh:mm:ss>")
SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
SHELL_STATIC_SUBCMD_SET_CREATE(sub_rtc,
/* Alphabetically sorted */
SHELL_CMD_ARG(set, &dsub_device_name, RTC_SET_HELP, cmd_set, 3, 0),
SHELL_CMD_ARG(get, &dsub_device_name, RTC_GET_HELP, cmd_get, 2, 0),
SHELL_SUBCMD_SET_END);
SHELL_CMD_REGISTER(rtc, &sub_rtc, "RTC commands", NULL);
``` | /content/code_sandbox/drivers/rtc/rtc_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,455 |
```c
/*
*
*/
#define DT_DRV_COMPAT motorola_mc146818
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/spinlock.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/sys/sys_io.h>
#define RTC_STD_INDEX (DT_INST_REG_ADDR_BY_IDX(0, 0))
#define RTC_STD_TARGET (DT_INST_REG_ADDR_BY_IDX(0, 1))
/* Time indices in RTC RAM */
#define RTC_SEC 0x00
#define RTC_MIN 0x02
#define RTC_HOUR 0x04
/* Day of week index in RTC RAM */
#define RTC_WDAY 0x06
/* Day of month index in RTC RAM */
#define RTC_MDAY 0x07
/* Month and year index in RTC RAM */
#define RTC_MONTH 0x08
#define RTC_YEAR 0x09
/* Y2K Bugfix */
#define RTC_CENTURY 0x32
/* Alarm time indices in RTC RAM */
#define RTC_ALARM_SEC 0x01
#define RTC_ALARM_MIN 0x03
#define RTC_ALARM_HOUR 0x05
/* Registers A-D indeces in RTC RAM */
#define RTC_REG_A 0x0A
#define RTC_REG_B 0x0B
#define RTC_REG_C 0x0C
#define RTC_REG_D 0x0D
#define RTC_UIP RTC_REG_A
#define RTC_DATA RTC_REG_B
#define RTC_FLAG RTC_REG_C
/* Alarm don't case state */
#define RTC_ALARM_DC 0xFF
/* Update In Progress bit in REG_A */
#define RTC_UIP_BIT BIT(7)
/* Update Cycle Inhibit bit in REG_B */
#define RTC_UCI_BIT BIT(7)
/* Periodic Interrupt Enable bit in REG_B */
#define RTC_PIE_BIT BIT(6)
/* Alarm Interrupt Enable bit in REG_B */
#define RTC_AIE_BIT BIT(5)
/* Update-ended Interrupt Enable bit in REG_B */
#define RTC_UIE_BIT BIT(4)
/* Data mode bit in REG_B */
#define RTC_DMODE_BIT BIT(2)
/* Hour Format bit in REG_B */
#define RTC_HFORMAT_BIT BIT(1)
/* Daylight Savings Enable Format bit in REG_B */
#define RTC_DSE_BIT BIT(0)
/* Interrupt Request Flag bit in REG_C */
#define RTC_IRF_BIT BIT(7)
/* Periodic Flag bit in REG_C */
#define RTC_PF_BIT BIT(6)
/* Alarm Flag bit in REG_C */
#define RTC_AF_BIT BIT(5)
/* Update-end Flag bit in REG_C */
#define RTC_UEF_BIT BIT(4)
/* VRT bit in REG_D */
#define RTC_VRT_BIT BIT(7)
/* Month day Alarm bits in REG_D */
#define RTC_MDAY_ALARM BIT_MASK(5)
/* Maximum and Minimum values of time */
#define MIN_SEC 0
#define MAX_SEC 59
#define MIN_MIN 0
#define MAX_MIN 59
#define MIN_HOUR 0
#define MAX_HOUR 23
#define MAX_WDAY 7
#define MIN_WDAY 1
#define MAX_MDAY 31
#define MIN_MDAY 1
#define MAX_MON 12
#define MIN_MON 1
#define MIN_YEAR_DIFF 0 /* YEAR - 1900 */
#define MAX_YEAR_DIFF 99 /* YEAR - 1999 */
/* Input clock frequency mapped to divider bits */
#define RTC_IN_CLK_DIV_BITS_4194304 (0)
#define RTC_IN_CLK_DIV_BITS_1048576 (1 << 4)
#define RTC_IN_CLK_DIV_BITS_32768 (2 << 4)
struct rtc_mc146818_data {
struct k_spinlock lock;
bool alarm_pending;
rtc_alarm_callback cb;
void *cb_data;
rtc_update_callback update_cb;
void *update_cb_data;
};
static uint8_t rtc_read(int reg)
{
uint8_t value;
sys_out8(reg, RTC_STD_INDEX);
value = sys_in8(RTC_STD_TARGET);
return value;
}
static void rtc_write(int reg, uint8_t value)
{
sys_out8(reg, RTC_STD_INDEX);
sys_out8(value, RTC_STD_TARGET);
}
static bool rtc_mc146818_validate_time(const struct rtc_time *timeptr)
{
if (timeptr->tm_sec < MIN_SEC || timeptr->tm_sec > MAX_SEC) {
return false;
}
if (timeptr->tm_min < MIN_MIN || timeptr->tm_min > MAX_MIN) {
return false;
}
if (timeptr->tm_hour < MIN_HOUR || timeptr->tm_hour > MAX_HOUR) {
return false;
}
if (timeptr->tm_wday + 1 < MIN_WDAY || timeptr->tm_wday + 1 > MAX_WDAY) {
return false;
}
if (timeptr->tm_mday < MIN_MDAY || timeptr->tm_mday > MAX_MDAY) {
return false;
}
if (timeptr->tm_mon + 1 < MIN_MON || timeptr->tm_mon + 1 > MAX_MON) {
return false;
}
if (timeptr->tm_year - 70 < MIN_YEAR_DIFF || timeptr->tm_year - 70 > MAX_YEAR_DIFF) {
return false;
}
return true;
}
static int rtc_mc146818_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_mc146818_data * const dev_data = dev->data;
uint8_t value;
int year;
int cent;
int ret;
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
if (timeptr == NULL) {
ret = -EINVAL;
goto out;
}
/* Check time valid */
if (!rtc_mc146818_validate_time(timeptr)) {
ret = -EINVAL;
goto out;
}
value = rtc_read(RTC_DATA);
rtc_write(RTC_DATA, value | RTC_UCI_BIT);
year = (1900 + timeptr->tm_year) % 100;
cent = (1900 + timeptr->tm_year) / 100;
rtc_write(RTC_SEC, (uint8_t)timeptr->tm_sec);
rtc_write(RTC_MIN, (uint8_t)timeptr->tm_min);
rtc_write(RTC_HOUR, (uint8_t)timeptr->tm_hour);
rtc_write(RTC_WDAY, (uint8_t)timeptr->tm_wday);
rtc_write(RTC_MDAY, (uint8_t)timeptr->tm_mday);
rtc_write(RTC_MONTH, (uint8_t)timeptr->tm_mon + 1);
rtc_write(RTC_YEAR, year);
rtc_write(RTC_CENTURY, cent);
value &= (~RTC_UCI_BIT);
rtc_write(RTC_DATA, value);
ret = 0;
out:
k_spin_unlock(&dev_data->lock, key);
return ret;
}
static int rtc_mc146818_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_mc146818_data * const dev_data = dev->data;
int ret;
uint8_t cent;
uint8_t year;
uint8_t value;
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
/* Validate arguments */
if (timeptr == NULL) {
ret = -EINVAL;
goto out;
}
if (!(rtc_read(RTC_REG_D) & RTC_VRT_BIT)) {
ret = -ENODATA;
goto out;
}
while (rtc_read(RTC_UIP) & RTC_UIP_BIT) {
continue;
}
cent = rtc_read(RTC_CENTURY);
year = rtc_read(RTC_YEAR);
timeptr->tm_mon = rtc_read(RTC_MONTH) - 1;
timeptr->tm_mday = rtc_read(RTC_MDAY);
timeptr->tm_wday = rtc_read(RTC_WDAY) - 1;
timeptr->tm_hour = rtc_read(RTC_HOUR);
timeptr->tm_min = rtc_read(RTC_MIN);
timeptr->tm_sec = rtc_read(RTC_SEC);
timeptr->tm_year = 100 * (int)cent + year - 1900;
timeptr->tm_nsec = 0;
timeptr->tm_yday = 0;
value = rtc_read(RTC_DATA);
/* Check time valid */
if (!rtc_mc146818_validate_time(timeptr)) {
ret = -ENODATA;
goto out;
}
ret = 0;
out:
k_spin_unlock(&dev_data->lock, key);
return ret;
}
#if defined(CONFIG_RTC_ALARM)
static bool rtc_mc146818_validate_alarm(const struct rtc_time *timeptr, uint32_t mask)
{
if ((mask & RTC_ALARM_TIME_MASK_SECOND) &&
(timeptr->tm_sec < MIN_SEC || timeptr->tm_sec > MAX_SEC)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_MINUTE) &&
(timeptr->tm_min < MIN_MIN || timeptr->tm_min > MAX_MIN)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_HOUR) &&
(timeptr->tm_hour < MIN_HOUR || timeptr->tm_hour > MAX_HOUR)) {
return false;
}
return true;
}
static int rtc_mc146818_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
ARG_UNUSED(dev);
if (id != 0) {
return -EINVAL;
}
(*mask) = (RTC_ALARM_TIME_MASK_SECOND
| RTC_ALARM_TIME_MASK_MINUTE
| RTC_ALARM_TIME_MASK_HOUR);
return 0;
}
static int rtc_mc146818_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
struct rtc_mc146818_data * const dev_data = dev->data;
int ret;
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
if (id != 0) {
ret = -EINVAL;
goto out;
}
if ((mask > 0) && (timeptr == NULL)) {
ret = -EINVAL;
goto out;
}
/* Check time valid */
if (!rtc_mc146818_validate_alarm(timeptr, mask)) {
ret = -EINVAL;
goto out;
}
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
rtc_write(RTC_ALARM_SEC, timeptr->tm_sec);
} else {
rtc_write(RTC_ALARM_SEC, RTC_ALARM_DC);
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
rtc_write(RTC_ALARM_MIN, timeptr->tm_min);
} else {
rtc_write(RTC_ALARM_SEC, RTC_ALARM_DC);
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
rtc_write(RTC_ALARM_HOUR, timeptr->tm_hour);
} else {
rtc_write(RTC_ALARM_SEC, RTC_ALARM_DC);
}
rtc_write(RTC_DATA, rtc_read(RTC_DATA) | RTC_AIE_BIT);
ret = 0;
out:
k_spin_unlock(&dev_data->lock, key);
return ret;
}
static int rtc_mc146818_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_mc146818_data * const dev_data = dev->data;
uint8_t value;
int ret;
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
if (id != 0) {
ret = -EINVAL;
goto out;
}
if (timeptr == NULL) {
ret = -EINVAL;
goto out;
}
(*mask) = 0;
value = rtc_read(RTC_ALARM_SEC);
if (value <= MAX_SEC) {
timeptr->tm_sec = value;
(*mask) |= RTC_ALARM_TIME_MASK_SECOND;
}
value = rtc_read(RTC_ALARM_MIN);
if (value <= MAX_MIN) {
timeptr->tm_min = value;
(*mask) |= RTC_ALARM_TIME_MASK_MINUTE;
}
value = rtc_read(RTC_ALARM_HOUR);
if (value <= MAX_HOUR) {
timeptr->tm_hour = value;
(*mask) |= RTC_ALARM_TIME_MASK_HOUR;
}
ret = 0;
out:
k_spin_unlock(&dev_data->lock, key);
return ret;
}
static int rtc_mc146818_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_mc146818_data * const dev_data = dev->data;
if (id != 0) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
dev_data->cb = callback;
dev_data->cb_data = user_data;
if (callback != NULL) {
/* Enable Alarm callback */
rtc_write(RTC_DATA, (rtc_read(RTC_DATA) | RTC_AIE_BIT));
} else {
/* Disable Alarm callback */
rtc_write(RTC_DATA, (rtc_read(RTC_DATA) & (~RTC_AIE_BIT)));
}
k_spin_unlock(&dev_data->lock, key);
return 0;
}
static int rtc_mc146818_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_mc146818_data * const dev_data = dev->data;
int ret;
if (id != 0) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
ret = dev_data->alarm_pending ? 1 : 0;
dev_data->alarm_pending = false;
k_spin_unlock(&dev_data->lock, key);
return ret;
}
#endif /* CONFIG_RTC_ALARM */
#if defined(CONFIG_RTC_UPDATE)
static int rtc_mc146818_update_set_callback(const struct device *dev,
rtc_update_callback callback, void *user_data)
{
struct rtc_mc146818_data * const dev_data = dev->data;
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
dev_data->update_cb = callback;
dev_data->update_cb_data = user_data;
if (callback != NULL) {
/* Enable update callback */
rtc_write(RTC_DATA, (rtc_read(RTC_DATA) | RTC_UIE_BIT));
} else {
/* Disable update callback */
rtc_write(RTC_DATA, (rtc_read(RTC_DATA) & (~RTC_UIE_BIT)));
}
k_spin_unlock(&dev_data->lock, key);
return 0;
}
#endif /* CONFIG_RTC_UPDATE */
static void rtc_mc146818_isr(const struct device *dev)
{
struct rtc_mc146818_data * const dev_data = dev->data;
uint8_t regc;
ARG_UNUSED(dev_data);
/* Read register, which clears the register */
regc = rtc_read(RTC_FLAG);
#if defined(CONFIG_RTC_ALARM)
if (regc & RTC_AF_BIT) {
if (dev_data->cb) {
dev_data->cb(dev, 0, dev_data->cb_data);
dev_data->alarm_pending = false;
} else {
dev_data->alarm_pending = true;
}
}
#endif
#if defined(CONFIG_RTC_UPDATE)
if (regc & RTC_UEF_BIT) {
if (dev_data->update_cb) {
dev_data->update_cb(dev, dev_data->update_cb_data);
}
}
#endif
}
static const struct rtc_driver_api rtc_mc146818_driver_api = {
.set_time = rtc_mc146818_set_time,
.get_time = rtc_mc146818_get_time,
#if defined(CONFIG_RTC_ALARM)
.alarm_get_supported_fields = rtc_mc146818_alarm_get_supported_fields,
.alarm_set_time = rtc_mc146818_alarm_set_time,
.alarm_get_time = rtc_mc146818_alarm_get_time,
.alarm_is_pending = rtc_mc146818_alarm_is_pending,
.alarm_set_callback = rtc_mc146818_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#if defined(CONFIG_RTC_UPDATE)
.update_set_callback = rtc_mc146818_update_set_callback,
#endif /* CONFIG_RTC_UPDATE */
};
#define RTC_MC146818_INIT_FN_DEFINE(n) \
static int rtc_mc146818_init##n(const struct device *dev) \
{ \
rtc_write(RTC_REG_A, \
_CONCAT(RTC_IN_CLK_DIV_BITS_, \
DT_INST_PROP(n, clock_frequency))); \
\
rtc_write(RTC_REG_B, RTC_DMODE_BIT | RTC_HFORMAT_BIT); \
\
IRQ_CONNECT(DT_INST_IRQN(0), \
DT_INST_IRQ(0, priority), \
rtc_mc146818_isr, DEVICE_DT_INST_GET(n), \
DT_INST_IRQ(0, sense)); \
\
irq_enable(DT_INST_IRQN(0)); \
\
return 0; \
}
#define RTC_MC146818_DEV_CFG(inst) \
struct rtc_mc146818_data rtc_mc146818_data##inst; \
\
RTC_MC146818_INIT_FN_DEFINE(inst) \
\
DEVICE_DT_INST_DEFINE(inst, &rtc_mc146818_init##inst, NULL, \
&rtc_mc146818_data##inst, NULL, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, \
&rtc_mc146818_driver_api); \
DT_INST_FOREACH_STATUS_OKAY(RTC_MC146818_DEV_CFG)
``` | /content/code_sandbox/drivers/rtc/rtc_mc146818.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,767 |
```c
/*
*
*
*/
#define DT_DRV_COMPAT st_stm32_rtc
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <soc.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_rtc.h>
#include <stm32_hsem.h>
#ifdef CONFIG_RTC_ALARM
#include <stm32_ll_exti.h>
#endif /* CONFIG_RTC_ALARM */
#include <zephyr/logging/log.h>
#ifdef CONFIG_RTC_ALARM
#include <zephyr/irq.h>
#endif /* CONFIG_RTC_ALARM */
#include <stdbool.h>
#include "rtc_utils.h"
#include "rtc_ll_stm32.h"
LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL);
#if (defined(CONFIG_SOC_SERIES_STM32L1X) && !defined(RTC_SUBSECOND_SUPPORT)) \
|| defined(CONFIG_SOC_SERIES_STM32F2X)
/* subsecond counting is not supported by some STM32L1x MCUs (Cat.1) & by STM32F2x SoC series */
#define HW_SUBSECOND_SUPPORT (0)
#else
#define HW_SUBSECOND_SUPPORT (1)
#endif
/* RTC start time: 1st, Jan, 2000 */
#define RTC_YEAR_REF 2000
/* struct tm start time: 1st, Jan, 1900 */
#define TM_YEAR_REF 1900
/* Convert part per billion calibration value to a number of clock pulses added or removed each
* 2^20 clock cycles so it is suitable for the CALR register fields
*
* nb_pulses = ppb * 2^20 / 10^9 = ppb * 2^11 / 5^9 = ppb * 2048 / 1953125
*/
#define PPB_TO_NB_PULSES(ppb) DIV_ROUND_CLOSEST((ppb) * 2048, 1953125)
/* Convert CALR register value (number of clock pulses added or removed each 2^20 clock cycles)
* to part ber billion calibration value
*
* ppb = nb_pulses * 10^9 / 2^20 = nb_pulses * 5^9 / 2^11 = nb_pulses * 1953125 / 2048
*/
#define NB_PULSES_TO_PPB(pulses) DIV_ROUND_CLOSEST((pulses) * 1953125, 2048)
/* CALP field can only be 512 or 0 as in reality CALP is a single bit field representing 512 pulses
* added every 2^20 clock cycles
*/
#define MAX_CALP (512)
#define MAX_CALM (511)
#define MAX_PPB NB_PULSES_TO_PPB(MAX_CALP)
#define MIN_PPB -NB_PULSES_TO_PPB(MAX_CALM)
/* Timeout in microseconds used to wait for flags */
#define RTC_TIMEOUT 1000000
#ifdef CONFIG_RTC_ALARM
#define RTC_STM32_ALARMS_COUNT DT_INST_PROP(0, alarms_count)
#define RTC_STM32_ALRM_A 0U
#define RTC_STM32_ALRM_B 1U
/* Zephyr mask supported by RTC device, values from RTC_ALARM_TIME_MASK */
#define RTC_STM32_SUPPORTED_ALARM_FIELDS \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE \
| RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_WEEKDAY \
| RTC_ALARM_TIME_MASK_MONTHDAY)
#if DT_INST_NODE_HAS_PROP(0, alrm_exti_line)
#define RTC_STM32_EXTI_LINE CONCAT(LL_EXTI_LINE_, DT_INST_PROP(0, alrm_exti_line))
#else
#define RTC_STM32_EXTI_LINE 0
#endif /* DT_INST_NODE_HAS_PROP(0, alrm_exti_line) */
#endif /* CONFIG_RTC_ALARM */
#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
/*
* After system reset, the RTC registers are protected against parasitic write access by the
* DBP bit in the power control peripheral (PWR).
* Hence, DBP bit must be set in order to enable RTC registers write access.
*/
#define RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION (1)
#else
#define RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION (0)
#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPCR_DBP || PWR_DBPR_DBP */
struct rtc_stm32_config {
uint32_t async_prescaler;
uint32_t sync_prescaler;
const struct stm32_pclken *pclken;
#if DT_INST_NODE_HAS_PROP(0, calib_out_freq)
uint32_t cal_out_freq;
#endif
};
#ifdef CONFIG_RTC_ALARM
struct rtc_stm32_alrm {
LL_RTC_AlarmTypeDef ll_rtc_alrm;
/* user-defined alarm mask, values from RTC_ALARM_TIME_MASK */
uint16_t user_mask;
rtc_alarm_callback user_callback;
void *user_data;
bool is_pending;
};
#endif /* CONFIG_RTC_ALARM */
struct rtc_stm32_data {
struct k_mutex lock;
#ifdef CONFIG_RTC_ALARM
struct rtc_stm32_alrm rtc_alrm_a;
struct rtc_stm32_alrm rtc_alrm_b;
#endif /* CONFIG_RTC_ALARM */
};
static int rtc_stm32_configure(const struct device *dev)
{
const struct rtc_stm32_config *cfg = dev->config;
int err = 0;
uint32_t hour_format = LL_RTC_GetHourFormat(RTC);
uint32_t sync_prescaler = LL_RTC_GetSynchPrescaler(RTC);
uint32_t async_prescaler = LL_RTC_GetAsynchPrescaler(RTC);
LL_RTC_DisableWriteProtection(RTC);
/* configuration process requires to stop the RTC counter so do it
* only if needed to avoid inducing time drift at each reset
*/
if ((hour_format != LL_RTC_HOURFORMAT_24HOUR) ||
(sync_prescaler != cfg->sync_prescaler) ||
(async_prescaler != cfg->async_prescaler)) {
ErrorStatus status = LL_RTC_EnterInitMode(RTC);
if (status == SUCCESS) {
LL_RTC_SetHourFormat(RTC, LL_RTC_HOURFORMAT_24HOUR);
LL_RTC_SetSynchPrescaler(RTC, cfg->sync_prescaler);
LL_RTC_SetAsynchPrescaler(RTC, cfg->async_prescaler);
} else {
err = -EIO;
}
LL_RTC_DisableInitMode(RTC);
}
#if DT_INST_NODE_HAS_PROP(0, calib_out_freq)
LL_RTC_CAL_SetOutputFreq(RTC, cfg->cal_out_freq);
#else
LL_RTC_CAL_SetOutputFreq(RTC, LL_RTC_CALIB_OUTPUT_NONE);
#endif
#ifdef RTC_CR_BYPSHAD
LL_RTC_EnableShadowRegBypass(RTC);
#endif /* RTC_CR_BYPSHAD */
LL_RTC_EnableWriteProtection(RTC);
return err;
}
#ifdef CONFIG_RTC_ALARM
static inline ErrorStatus rtc_stm32_init_alarm(RTC_TypeDef *rtc, uint32_t format,
LL_RTC_AlarmTypeDef *ll_alarm_struct, uint16_t id)
{
ll_alarm_struct->AlarmDateWeekDaySel = RTC_STM32_ALRM_DATEWEEKDAYSEL_DATE;
/*
* RTC write protection is disabled & enabled again inside LL_RTC_ALMx_Init functions
* The LL_RTC_ALMx_Init does convert bin2bcd by itself
*/
if (id == RTC_STM32_ALRM_A) {
return LL_RTC_ALMA_Init(rtc, format, ll_alarm_struct);
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
return LL_RTC_ALMB_Init(rtc, format, ll_alarm_struct);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
return 0;
}
static inline void rtc_stm32_clear_alarm_flag(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
LL_RTC_ClearFlag_ALRA(rtc);
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
LL_RTC_ClearFlag_ALRB(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
static inline uint32_t rtc_stm32_is_active_alarm(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
return LL_RTC_IsActiveFlag_ALRA(rtc);
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
return LL_RTC_IsActiveFlag_ALRB(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
return 0;
}
static inline void rtc_stm32_enable_interrupt_alarm(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
LL_RTC_EnableIT_ALRA(rtc);
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
LL_RTC_EnableIT_ALRB(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
static inline void rtc_stm32_disable_interrupt_alarm(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
LL_RTC_DisableIT_ALRA(rtc);
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
LL_RTC_DisableIT_ALRB(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
static inline void rtc_stm32_enable_alarm(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
LL_RTC_ALMA_Enable(rtc);
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
LL_RTC_ALMB_Enable(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
static inline void rtc_stm32_disable_alarm(RTC_TypeDef *rtc, uint16_t id)
{
if (id == RTC_STM32_ALRM_A) {
LL_RTC_ALMA_Disable(rtc);
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
LL_RTC_ALMB_Disable(rtc);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
void rtc_stm32_isr(const struct device *dev)
{
struct rtc_stm32_data *data = dev->data;
struct rtc_stm32_alrm *p_rtc_alrm;
int id = 0;
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
for (id = 0; id < RTC_STM32_ALARMS_COUNT; id++) {
if (rtc_stm32_is_active_alarm(RTC, (uint16_t)id) != 0) {
LL_RTC_DisableWriteProtection(RTC);
rtc_stm32_clear_alarm_flag(RTC, (uint16_t)id);
LL_RTC_EnableWriteProtection(RTC);
if (id == RTC_STM32_ALRM_A) {
p_rtc_alrm = &(data->rtc_alrm_a);
} else {
p_rtc_alrm = &(data->rtc_alrm_b);
}
p_rtc_alrm->is_pending = true;
if (p_rtc_alrm->user_callback != NULL) {
p_rtc_alrm->user_callback(dev, (uint16_t)id, p_rtc_alrm->user_data);
}
}
}
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_DisableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
ll_func_exti_clear_rtc_alarm_flag(RTC_STM32_EXTI_LINE);
}
static void rtc_stm32_irq_config(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
rtc_stm32_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* CONFIG_RTC_ALARM */
static int rtc_stm32_init(const struct device *dev)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
const struct rtc_stm32_config *cfg = dev->config;
struct rtc_stm32_data *data = dev->data;
int err = 0;
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Enable RTC bus clock */
if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}
k_mutex_init(&data->lock);
/* Enable Backup access */
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
/* Enable RTC clock source */
if (clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL) != 0) {
LOG_ERR("clock configure failed\n");
return -EIO;
}
/*
* On STM32WBAX series, there is no bit in BCDR register to enable RTC.
* Enabling RTC is done directly via the RCC APB register bit.
*/
#ifndef CONFIG_SOC_SERIES_STM32WBAX
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
LL_RCC_EnableRTC();
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
#endif /* CONFIG_SOC_SERIES_STM32WBAX */
err = rtc_stm32_configure(dev);
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_DisableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
#ifdef CONFIG_RTC_ALARM
rtc_stm32_irq_config(dev);
ll_func_exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE);
k_mutex_lock(&data->lock, K_FOREVER);
memset(&(data->rtc_alrm_a), 0, sizeof(struct rtc_stm32_alrm));
memset(&(data->rtc_alrm_b), 0, sizeof(struct rtc_stm32_alrm));
k_mutex_unlock(&data->lock);
#endif /* CONFIG_RTC_ALARM */
return err;
}
static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_stm32_data *data = dev->data;
LL_RTC_TimeTypeDef rtc_time;
LL_RTC_DateTypeDef rtc_date;
uint32_t real_year = timeptr->tm_year + TM_YEAR_REF;
int err = 0;
if (real_year < RTC_YEAR_REF) {
/* RTC does not support years before 2000 */
return -EINVAL;
}
if (timeptr->tm_wday == -1) {
/* day of the week is expected */
return -EINVAL;
}
err = k_mutex_lock(&data->lock, K_NO_WAIT);
if (err) {
return err;
}
LOG_DBG("Setting clock");
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
/* Enter Init mode inside the LL_RTC_Time and Date Init functions */
rtc_time.Hours = bin2bcd(timeptr->tm_hour);
rtc_time.Minutes = bin2bcd(timeptr->tm_min);
rtc_time.Seconds = bin2bcd(timeptr->tm_sec);
LL_RTC_TIME_Init(RTC, LL_RTC_FORMAT_BCD, &rtc_time);
/* Set Date after Time to be sure the DR is correctly updated on stm32F2 serie. */
rtc_date.Year = bin2bcd((real_year - RTC_YEAR_REF));
rtc_date.Month = bin2bcd((timeptr->tm_mon + 1));
rtc_date.Day = bin2bcd(timeptr->tm_mday);
rtc_date.WeekDay = ((timeptr->tm_wday == 0) ? (LL_RTC_WEEKDAY_SUNDAY) : (timeptr->tm_wday));
/* WeekDay sunday (tm_wday = 0) is not represented by the same value in hardware,
* all the other values are consistent with what is expected by hardware.
*/
LL_RTC_DATE_Init(RTC, LL_RTC_FORMAT_BCD, &rtc_date);
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_DisableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
#ifdef CONFIG_SOC_SERIES_STM32F2X
/*
* Because stm32F2 serie has no shadow registers,
* wait until TR and DR registers are synchronised : flag RS
*/
while (LL_RTC_IsActiveFlag_RS(RTC) != 1) {
;
}
#endif /* CONFIG_SOC_SERIES_STM32F2X */
k_mutex_unlock(&data->lock);
LOG_DBG("Calendar set : %d/%d/%d - %dh%dm%ds",
LL_RTC_DATE_GetDay(RTC),
LL_RTC_DATE_GetMonth(RTC),
LL_RTC_DATE_GetYear(RTC),
LL_RTC_TIME_GetHour(RTC),
LL_RTC_TIME_GetMinute(RTC),
LL_RTC_TIME_GetSecond(RTC)
);
return err;
}
static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_stm32_data *data = dev->data;
uint32_t rtc_date, rtc_time;
#if HW_SUBSECOND_SUPPORT
const struct rtc_stm32_config *cfg = dev->config;
uint32_t rtc_subsecond;
#endif /* HW_SUBSECOND_SUPPORT */
if (timeptr == NULL) {
LOG_ERR("NULL rtc_time pointer");
return -EINVAL;
}
int err = k_mutex_lock(&data->lock, K_NO_WAIT);
if (err) {
return err;
}
if (!LL_RTC_IsActiveFlag_INITS(RTC)) {
/* INITS flag is set when the calendar has been initialiazed. This flag is
* reset only on backup domain reset, so it can be read after a system
* reset to check if the calendar has been initialized.
*/
k_mutex_unlock(&data->lock);
return -ENODATA;
}
do {
/* read date, time and subseconds and relaunch if a day increment occurred
* while doing so as it will result in an erroneous result otherwise
*/
rtc_date = LL_RTC_DATE_Get(RTC);
do {
/* read time and subseconds and relaunch if a second increment occurred
* while doing so as it will result in an erroneous result otherwise
*/
rtc_time = LL_RTC_TIME_Get(RTC);
#if HW_SUBSECOND_SUPPORT
rtc_subsecond = LL_RTC_TIME_GetSubSecond(RTC);
#endif /* HW_SUBSECOND_SUPPORT */
} while (rtc_time != LL_RTC_TIME_Get(RTC));
} while (rtc_date != LL_RTC_DATE_Get(RTC));
k_mutex_unlock(&data->lock);
/* tm_year is the value since 1900 and Rtc year is from 2000 */
timeptr->tm_year = bcd2bin(__LL_RTC_GET_YEAR(rtc_date)) + (RTC_YEAR_REF - TM_YEAR_REF);
/* tm_mon allowed values are 0-11 */
timeptr->tm_mon = bcd2bin(__LL_RTC_GET_MONTH(rtc_date)) - 1;
timeptr->tm_mday = bcd2bin(__LL_RTC_GET_DAY(rtc_date));
int hw_wday = __LL_RTC_GET_WEEKDAY(rtc_date);
if (hw_wday == LL_RTC_WEEKDAY_SUNDAY) {
/* LL_RTC_WEEKDAY_SUNDAY = 7 but a 0 is expected in tm_wday for sunday */
timeptr->tm_wday = 0;
} else {
/* all other values are consistent between hardware and rtc_time structure */
timeptr->tm_wday = hw_wday;
}
timeptr->tm_hour = bcd2bin(__LL_RTC_GET_HOUR(rtc_time));
timeptr->tm_min = bcd2bin(__LL_RTC_GET_MINUTE(rtc_time));
timeptr->tm_sec = bcd2bin(__LL_RTC_GET_SECOND(rtc_time));
#if HW_SUBSECOND_SUPPORT
uint64_t temp = ((uint64_t)(cfg->sync_prescaler - rtc_subsecond)) * 1000000000L;
timeptr->tm_nsec = temp / (cfg->sync_prescaler + 1);
#else
timeptr->tm_nsec = 0;
#endif
/* unknown values */
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
/* __LL_RTC_GET_YEAR(rtc_date)is the real year (from 2000) */
LOG_DBG("Calendar get : %d/%d/%d - %dh%dm%ds",
timeptr->tm_mday,
timeptr->tm_mon,
__LL_RTC_GET_YEAR(rtc_date),
timeptr->tm_hour,
timeptr->tm_min,
timeptr->tm_sec);
return 0;
}
#ifdef CONFIG_RTC_ALARM
static void rtc_stm32_init_ll_alrm_struct(LL_RTC_AlarmTypeDef *p_rtc_alarm,
const struct rtc_time *timeptr, uint16_t mask)
{
LL_RTC_TimeTypeDef *p_rtc_alrm_time = &(p_rtc_alarm->AlarmTime);
uint32_t ll_mask = 0;
/*
* STM32 RTC Alarm LL mask should be set for all fields beyond the broadest one
* that's being matched with RTC calendar to trigger alarm periodically,
* the opposite of Zephyr RTC Alarm mask which is set for active fields.
*/
ll_mask = RTC_STM32_ALRM_MASK_ALL;
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
ll_mask &= ~RTC_STM32_ALRM_MASK_SECONDS;
p_rtc_alrm_time->Seconds = bin2bcd(timeptr->tm_sec);
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
ll_mask &= ~RTC_STM32_ALRM_MASK_MINUTES;
p_rtc_alrm_time->Minutes = bin2bcd(timeptr->tm_min);
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
ll_mask &= ~RTC_STM32_ALRM_MASK_HOURS;
p_rtc_alrm_time->Hours = bin2bcd(timeptr->tm_hour);
}
if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
/* the Alarm Mask field compares with the day of the week */
ll_mask &= ~RTC_STM32_ALRM_MASK_DATEWEEKDAY;
p_rtc_alarm->AlarmDateWeekDaySel = RTC_STM32_ALRM_DATEWEEKDAYSEL_WEEKDAY;
if (timeptr->tm_wday == 0) {
/* sunday (tm_wday = 0) is not represented by the same value in hardware */
p_rtc_alarm->AlarmDateWeekDay = LL_RTC_WEEKDAY_SUNDAY;
} else {
/* all the other values are consistent with what is expected by hardware */
p_rtc_alarm->AlarmDateWeekDay = bin2bcd(timeptr->tm_wday);
}
} else if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
/* the Alarm compares with the day number & ignores the day of the week */
ll_mask &= ~RTC_STM32_ALRM_MASK_DATEWEEKDAY;
p_rtc_alarm->AlarmDateWeekDaySel = RTC_STM32_ALRM_DATEWEEKDAYSEL_DATE;
p_rtc_alarm->AlarmDateWeekDay = bin2bcd(timeptr->tm_mday);
}
p_rtc_alrm_time->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
p_rtc_alarm->AlarmMask = ll_mask;
}
static inline void rtc_stm32_get_ll_alrm_time(uint16_t id, struct rtc_time *timeptr)
{
if (id == RTC_STM32_ALRM_A) {
timeptr->tm_sec = bcd2bin(LL_RTC_ALMA_GetSecond(RTC));
timeptr->tm_min = bcd2bin(LL_RTC_ALMA_GetMinute(RTC));
timeptr->tm_hour = bcd2bin(LL_RTC_ALMA_GetHour(RTC));
timeptr->tm_wday = bcd2bin(LL_RTC_ALMA_GetWeekDay(RTC));
timeptr->tm_mday = bcd2bin(LL_RTC_ALMA_GetDay(RTC));
return;
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
timeptr->tm_sec = bcd2bin(LL_RTC_ALMB_GetSecond(RTC));
timeptr->tm_min = bcd2bin(LL_RTC_ALMB_GetMinute(RTC));
timeptr->tm_hour = bcd2bin(LL_RTC_ALMB_GetHour(RTC));
timeptr->tm_wday = bcd2bin(LL_RTC_ALMB_GetWeekDay(RTC));
timeptr->tm_mday = bcd2bin(LL_RTC_ALMB_GetDay(RTC));
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
}
static inline uint16_t rtc_stm32_get_ll_alrm_mask(uint16_t id)
{
uint32_t ll_alarm_mask = 0;
uint16_t zephyr_alarm_mask = 0;
uint32_t week_day = 0;
/*
* STM32 RTC Alarm LL mask is set for all fields beyond the broadest one
* that's being matched with RTC calendar to trigger alarm periodically,
* the opposite of Zephyr RTC Alarm mask which is set for active fields.
*/
if (id == RTC_STM32_ALRM_A) {
ll_alarm_mask = LL_RTC_ALMA_GetMask(RTC);
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
ll_alarm_mask = LL_RTC_ALMB_GetMask(RTC);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
if ((ll_alarm_mask & RTC_STM32_ALRM_MASK_SECONDS) == 0x0) {
zephyr_alarm_mask = RTC_ALARM_TIME_MASK_SECOND;
}
if ((ll_alarm_mask & RTC_STM32_ALRM_MASK_MINUTES) == 0x0) {
zephyr_alarm_mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if ((ll_alarm_mask & RTC_STM32_ALRM_MASK_HOURS) == 0x0) {
zephyr_alarm_mask |= RTC_ALARM_TIME_MASK_HOUR;
}
if ((ll_alarm_mask & RTC_STM32_ALRM_MASK_DATEWEEKDAY) == 0x0) {
if (id == RTC_STM32_ALRM_A) {
week_day = LL_RTC_ALMA_GetWeekDay(RTC);
}
#if RTC_STM32_ALARMS_COUNT > 1
if (id == RTC_STM32_ALRM_B) {
week_day = LL_RTC_ALMB_GetWeekDay(RTC);
}
#endif /* RTC_STM32_ALARMS_COUNT > 1 */
if (week_day) {
zephyr_alarm_mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
} else {
zephyr_alarm_mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
}
return zephyr_alarm_mask;
}
static int rtc_stm32_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
if (mask == NULL) {
LOG_ERR("NULL mask pointer");
return -EINVAL;
}
if ((id != RTC_STM32_ALRM_A) && (id != RTC_STM32_ALRM_B)) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
*mask = (uint16_t)RTC_STM32_SUPPORTED_ALARM_FIELDS;
return 0;
}
static int rtc_stm32_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_stm32_data *data = dev->data;
struct rtc_stm32_alrm *p_rtc_alrm;
LL_RTC_AlarmTypeDef *p_ll_rtc_alarm;
LL_RTC_TimeTypeDef *p_ll_rtc_alrm_time;
int err = 0;
if ((mask == NULL) || (timeptr == NULL)) {
LOG_ERR("NULL pointer");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
if (id == RTC_STM32_ALRM_A) {
p_rtc_alrm = &(data->rtc_alrm_a);
} else if (id == RTC_STM32_ALRM_B) {
p_rtc_alrm = &(data->rtc_alrm_b);
} else {
LOG_ERR("invalid alarm ID %d", id);
err = -EINVAL;
goto unlock;
}
p_ll_rtc_alarm = &(p_rtc_alrm->ll_rtc_alrm);
p_ll_rtc_alrm_time = &(p_ll_rtc_alarm->AlarmTime);
memset(timeptr, -1, sizeof(struct rtc_time));
rtc_stm32_get_ll_alrm_time(id, timeptr);
p_rtc_alrm->user_mask = rtc_stm32_get_ll_alrm_mask(id);
*mask = p_rtc_alrm->user_mask;
LOG_DBG("get alarm: mday = %d, wday = %d, hour = %d, min = %d, sec = %d, "
"mask = 0x%04x", timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour,
timeptr->tm_min, timeptr->tm_sec, *mask);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int rtc_stm32_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
struct rtc_stm32_data *data = dev->data;
struct rtc_stm32_alrm *p_rtc_alrm;
LL_RTC_AlarmTypeDef *p_ll_rtc_alarm;
LL_RTC_TimeTypeDef *p_ll_rtc_alrm_time;
int err = 0;
k_mutex_lock(&data->lock, K_FOREVER);
if (id == RTC_STM32_ALRM_A) {
p_rtc_alrm = &(data->rtc_alrm_a);
} else if (id == RTC_STM32_ALRM_B) {
p_rtc_alrm = &(data->rtc_alrm_b);
} else {
LOG_ERR("invalid alarm ID %d", id);
err = -EINVAL;
goto unlock;
}
if ((mask == 0) && (timeptr == NULL)) {
memset(&(p_rtc_alrm->ll_rtc_alrm), 0, sizeof(LL_RTC_AlarmTypeDef));
p_rtc_alrm->user_callback = NULL;
p_rtc_alrm->user_data = NULL;
p_rtc_alrm->is_pending = false;
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
if (rtc_stm32_is_active_alarm(RTC, id)) {
LL_RTC_DisableWriteProtection(RTC);
rtc_stm32_disable_alarm(RTC, id);
rtc_stm32_disable_interrupt_alarm(RTC, id);
LL_RTC_EnableWriteProtection(RTC);
}
LOG_DBG("Alarm %d has been disabled", id);
goto disable_bkup_access;
}
if ((mask & ~RTC_STM32_SUPPORTED_ALARM_FIELDS) != 0) {
LOG_ERR("unsupported alarm %d field mask 0x%04x", id, mask);
err = -EINVAL;
goto unlock;
}
if (timeptr == NULL) {
LOG_ERR("timeptr is invalid");
err = -EINVAL;
goto unlock;
}
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_DBG("One or multiple time values are invalid");
err = -EINVAL;
goto unlock;
}
p_ll_rtc_alarm = &(p_rtc_alrm->ll_rtc_alrm);
p_ll_rtc_alrm_time = &(p_ll_rtc_alarm->AlarmTime);
memset(p_ll_rtc_alrm_time, 0, sizeof(LL_RTC_TimeTypeDef));
rtc_stm32_init_ll_alrm_struct(p_ll_rtc_alarm, timeptr, mask);
p_rtc_alrm->user_mask = mask;
LOG_DBG("set alarm %d : second = %d, min = %d, hour = %d,"
" wday = %d, mday = %d, mask = 0x%04x",
id, timeptr->tm_sec, timeptr->tm_min, timeptr->tm_hour,
timeptr->tm_wday, timeptr->tm_mday, mask);
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTC);
/* Disable ALARM so that the RTC_ISR_ALRAWF/RTC_ISR_ALRBWF is 0 */
rtc_stm32_disable_alarm(RTC, id);
rtc_stm32_disable_interrupt_alarm(RTC, id);
#ifdef RTC_ISR_ALRAWF
if (id == RTC_STM32_ALRM_A) {
/* Wait till RTC ALRAWF flag is set before writing to RTC registers */
while (!LL_RTC_IsActiveFlag_ALRAW(RTC)) {
;
}
}
#endif /* RTC_ISR_ALRAWF */
#ifdef RTC_ISR_ALRBWF
if (id == RTC_STM32_ALRM_B) {
/* Wait till RTC ALRBWF flag is set before writing to RTC registers */
while (!LL_RTC_IsActiveFlag_ALRBW(RTC)) {
;
}
}
#endif /* RTC_ISR_ALRBWF */
/* init Alarm */
/* write protection is disabled & enabled again inside the LL_RTC_ALMx_Init function */
if (rtc_stm32_init_alarm(RTC, LL_RTC_FORMAT_BCD, p_ll_rtc_alarm, id) != SUCCESS) {
LOG_ERR("Could not initialize Alarm %d", id);
err = -ECANCELED;
goto disable_bkup_access;
}
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTC);
/* Enable Alarm */
rtc_stm32_enable_alarm(RTC, id);
/* Clear Alarm flag */
rtc_stm32_clear_alarm_flag(RTC, id);
/* Enable Alarm IT */
rtc_stm32_enable_interrupt_alarm(RTC, id);
ll_func_exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE);
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTC);
disable_bkup_access:
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_DisableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
unlock:
k_mutex_unlock(&data->lock);
if (id == RTC_STM32_ALRM_A) {
LOG_DBG("Alarm A : %dh%dm%ds mask = 0x%x",
LL_RTC_ALMA_GetHour(RTC),
LL_RTC_ALMA_GetMinute(RTC),
LL_RTC_ALMA_GetSecond(RTC),
LL_RTC_ALMA_GetMask(RTC));
}
#ifdef RTC_ALARM_B
if (id == RTC_STM32_ALRM_B) {
LOG_DBG("Alarm B : %dh%dm%ds mask = 0x%x",
LL_RTC_ALMB_GetHour(RTC),
LL_RTC_ALMB_GetMinute(RTC),
LL_RTC_ALMB_GetSecond(RTC),
LL_RTC_ALMB_GetMask(RTC));
}
#endif /* #ifdef RTC_ALARM_B */
return err;
}
static int rtc_stm32_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_stm32_data *data = dev->data;
struct rtc_stm32_alrm *p_rtc_alrm;
int err = 0;
k_mutex_lock(&data->lock, K_FOREVER);
if (id == RTC_STM32_ALRM_A) {
p_rtc_alrm = &(data->rtc_alrm_a);
} else if (id == RTC_STM32_ALRM_B) {
p_rtc_alrm = &(data->rtc_alrm_b);
} else {
LOG_ERR("invalid alarm ID %d", id);
err = -EINVAL;
goto unlock;
}
/* Passing the callback function and userdata filled by the user */
p_rtc_alrm->user_callback = callback;
p_rtc_alrm->user_data = user_data;
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int rtc_stm32_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_stm32_data *data = dev->data;
struct rtc_stm32_alrm *p_rtc_alrm;
int ret = 0;
k_mutex_lock(&data->lock, K_FOREVER);
if (id == RTC_STM32_ALRM_A) {
p_rtc_alrm = &(data->rtc_alrm_a);
} else if (id == RTC_STM32_ALRM_B) {
p_rtc_alrm = &(data->rtc_alrm_b);
} else {
LOG_ERR("invalid alarm ID %d", id);
ret = -EINVAL;
goto unlock;
}
__disable_irq();
ret = p_rtc_alrm->is_pending ? 1 : 0;
p_rtc_alrm->is_pending = false;
__enable_irq();
unlock:
k_mutex_unlock(&data->lock);
return ret;
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_CALIBRATION
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
!(defined(CONFIG_SOC_SERIES_STM32L1X) && !defined(RTC_SMOOTHCALIB_SUPPORT))
static int rtc_stm32_set_calibration(const struct device *dev, int32_t calibration)
{
ARG_UNUSED(dev);
/* Note : calibration is considered here to be ppb value to apply
* on clock period (not frequency) but with an opposite sign
*/
if ((calibration > MAX_PPB) || (calibration < MIN_PPB)) {
/* out of supported range */
return -EINVAL;
}
int32_t nb_pulses = PPB_TO_NB_PULSES(calibration);
/* we tested calibration against supported range
* so theoretically nb_pulses is also within range
*/
__ASSERT_NO_MSG(nb_pulses <= MAX_CALP);
__ASSERT_NO_MSG(nb_pulses >= -MAX_CALM);
uint32_t calp, calm;
if (nb_pulses > 0) {
calp = LL_RTC_CALIB_INSERTPULSE_SET;
calm = MAX_CALP - nb_pulses;
} else {
calp = LL_RTC_CALIB_INSERTPULSE_NONE;
calm = -nb_pulses;
}
/* wait for recalibration to be ok if a previous recalibration occurred */
if (!WAIT_FOR(LL_RTC_IsActiveFlag_RECALP(RTC) == 0, 100000, k_msleep(1))) {
return -EIO;
}
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_EnableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
LL_RTC_DisableWriteProtection(RTC);
MODIFY_REG(RTC->CALR, RTC_CALR_CALP | RTC_CALR_CALM, calp | calm);
LL_RTC_EnableWriteProtection(RTC);
#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
LL_PWR_DisableBkUpAccess();
#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
return 0;
}
static int rtc_stm32_get_calibration(const struct device *dev, int32_t *calibration)
{
ARG_UNUSED(dev);
uint32_t calr = sys_read32((mem_addr_t) &RTC->CALR);
bool calp_enabled = READ_BIT(calr, RTC_CALR_CALP);
uint32_t calm = READ_BIT(calr, RTC_CALR_CALM);
int32_t nb_pulses = -((int32_t) calm);
if (calp_enabled) {
nb_pulses += MAX_CALP;
}
*calibration = NB_PULSES_TO_PPB(nb_pulses);
return 0;
}
#endif
#endif /* CONFIG_RTC_CALIBRATION */
static const struct rtc_driver_api rtc_stm32_driver_api = {
.set_time = rtc_stm32_set_time,
.get_time = rtc_stm32_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rtc_stm32_alarm_get_supported_fields,
.alarm_set_time = rtc_stm32_alarm_set_time,
.alarm_get_time = rtc_stm32_alarm_get_time,
.alarm_set_callback = rtc_stm32_alarm_set_callback,
.alarm_is_pending = rtc_stm32_alarm_is_pending,
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_CALIBRATION
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
!(defined(CONFIG_SOC_SERIES_STM32L1X) && !defined(RTC_SMOOTHCALIB_SUPPORT))
.set_calibration = rtc_stm32_set_calibration,
.get_calibration = rtc_stm32_get_calibration,
#else
#error RTC calibration for devices without smooth calibration feature is not supported yet
#endif
#endif /* CONFIG_RTC_CALIBRATION */
};
static const struct stm32_pclken rtc_clk[] = STM32_DT_INST_CLOCKS(0);
BUILD_ASSERT(DT_INST_CLOCKS_HAS_IDX(0, 1), "RTC source clock not defined in the device tree");
static const struct rtc_stm32_config rtc_config = {
#if DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSI
/* prescaler values for LSI @ 32 KHz */
.async_prescaler = 0x7F,
.sync_prescaler = 0x00F9,
#else /* DT_INST_CLOCKS_CELL_BY_IDX(0, 1, bus) == STM32_SRC_LSE */
/* prescaler values for LSE @ 32768 Hz */
.async_prescaler = 0x7F,
.sync_prescaler = 0x00FF,
#endif
.pclken = rtc_clk,
#if DT_INST_NODE_HAS_PROP(0, calib_out_freq)
.cal_out_freq = _CONCAT(_CONCAT(LL_RTC_CALIB_OUTPUT_, DT_INST_PROP(0, calib_out_freq)), HZ),
#endif
};
static struct rtc_stm32_data rtc_data;
DEVICE_DT_INST_DEFINE(0, &rtc_stm32_init, NULL, &rtc_data, &rtc_config, PRE_KERNEL_1,
CONFIG_RTC_INIT_PRIORITY, &rtc_stm32_driver_api);
``` | /content/code_sandbox/drivers/rtc/rtc_ll_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,459 |
```unknown
# NUMAKER RTC Driver configuration options
config RTC_NUMAKER
bool "Nuvoton NuMaker MCU RTC driver"
default y
select HAS_NUMAKER_RTC
depends on DT_HAS_NUVOTON_NUMAKER_RTC_ENABLED
help
This option enables the RTC driver for Nuvoton NuMaker family of
processors.
Say y if you wish to enable NuMaker RTC.
``` | /content/code_sandbox/drivers/rtc/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# Fake RTC configuration options
#
config RTC_FAKE
bool "Fake RTC driver"
default y
depends on DT_HAS_ZEPHYR_FAKE_RTC_ENABLED
help
Enable support for the FFF-based fake RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.fake | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/spinlock.h>
#include <hardware/irq.h>
#include <hardware/rtc.h>
#include <hardware/regs/rtc.h>
#include "rtc_utils.h"
#define DT_DRV_COMPAT raspberrypi_pico_rtc
#define CLK_DRV DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0))
#define CLK_ID (clock_control_subsys_t) DT_INST_PHA_BY_IDX(0, clocks, 0, clk_id)
/* struct tm start time: 1st, Jan, 1900 */
#define TM_YEAR_REF 1900
/* See section 4.8.1 of the RP2040 datasheet. */
#define RP2040_RTC_YEAR_MAX 4095
#ifdef CONFIG_RTC_ALARM
static int rtc_rpi_pico_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr);
#endif
struct rtc_rpi_pico_data {
struct k_spinlock lock;
#ifdef CONFIG_RTC_ALARM
struct rtc_time alarm_time;
uint16_t alarm_mask;
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
bool alarm_pending;
#endif /* CONFIG_RTC_ALARM */
};
static struct rtc_rpi_pico_data rtc_data;
LOG_MODULE_REGISTER(rtc_rpi, CONFIG_RTC_LOG_LEVEL);
#ifdef CONFIG_RTC_ALARM
static void rtc_rpi_isr(const struct device *dev)
{
struct rtc_rpi_pico_data *data = dev->data;
rtc_alarm_callback callback;
void *user_data;
rtc_disable_alarm();
K_SPINLOCK(&data->lock) {
callback = data->alarm_callback;
user_data = data->alarm_user_data;
}
if (callback != NULL) {
callback(dev, 0, user_data);
} else {
data->alarm_pending = true;
}
/* re-enable the alarm. */
rtc_enable_alarm();
}
#endif
static int rtc_rpi_pico_init(const struct device *dev)
{
int ret;
#ifdef CONFIG_RTC_ALARM
struct rtc_rpi_pico_data *data = dev->data;
#endif
ret = clock_control_on(CLK_DRV, CLK_ID);
if (ret < 0) {
return ret;
}
#ifdef CONFIG_RTC_ALARM
data->alarm_mask = 0;
data->alarm_callback = NULL;
data->alarm_pending = false;
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rtc_rpi_isr, DEVICE_DT_INST_GET(0),
0);
irq_enable(DT_INST_IRQN(0));
#endif
rtc_init();
return 0;
}
static int rtc_rpi_pico_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_rpi_pico_data *data = dev->data;
int err = 0;
if (timeptr->tm_year + TM_YEAR_REF > RP2040_RTC_YEAR_MAX) {
return -EINVAL;
}
if (timeptr->tm_wday == -1) {
/* day of the week is expected */
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
datetime_t dt = {
.year = timeptr->tm_year + TM_YEAR_REF,
.month = timeptr->tm_mon + 1,
.day = timeptr->tm_mday,
.dotw = timeptr->tm_wday,
.hour = timeptr->tm_hour,
.min = timeptr->tm_min,
.sec = timeptr->tm_sec,
};
/* Use the validation in the Pico SDK. */
if (!rtc_set_datetime(&dt)) {
err = -EINVAL;
}
k_spin_unlock(&data->lock, key);
return err;
}
static int rtc_rpi_pico_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_rpi_pico_data *data = dev->data;
datetime_t dt;
int err = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (!rtc_get_datetime(&dt)) {
err = -ENODATA;
}
timeptr->tm_sec = dt.sec;
timeptr->tm_min = dt.min;
timeptr->tm_hour = dt.hour;
timeptr->tm_mday = dt.day;
timeptr->tm_mon = dt.month - 1;
timeptr->tm_year = dt.year - TM_YEAR_REF;
timeptr->tm_wday = dt.dotw;
/* unknown values */
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
timeptr->tm_nsec = 0;
k_spin_unlock(&data->lock, key);
return err;
}
#if defined(CONFIG_RTC_ALARM)
static int rtc_rpi_pico_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *supported_fields)
{
ARG_UNUSED(dev);
if (id != 0) {
return -EINVAL;
}
*supported_fields = RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE |
RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_WEEKDAY |
RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_MONTH |
RTC_ALARM_TIME_MASK_YEAR;
return 0;
}
static int rtc_rpi_pico_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *alarm)
{
struct rtc_rpi_pico_data *data = dev->data;
int err = 0;
uint16_t mask_available;
(void)rtc_rpi_pico_alarm_get_supported_fields(NULL, 0, &mask_available);
if (mask & ~mask_available) {
return -EINVAL;
}
if (!rtc_utils_validate_rtc_time(alarm, mask)) {
return -EINVAL;
}
LOG_INF("Setting alarm");
rtc_disable_alarm();
if (mask == 0) {
/* Disable the alarm */
data->alarm_mask = 0;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Clear before updating. */
rtc_hw->irq_setup_0 = 0;
rtc_hw->irq_setup_1 = 0;
/* Set the match enable bits for things we care about */
if (mask & RTC_ALARM_TIME_MASK_YEAR) {
hw_set_bits(&rtc_hw->irq_setup_0,
RTC_IRQ_SETUP_0_YEAR_ENA_BITS |
((alarm->tm_year + TM_YEAR_REF) << RTC_IRQ_SETUP_0_YEAR_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
hw_set_bits(&rtc_hw->irq_setup_0,
RTC_IRQ_SETUP_0_MONTH_ENA_BITS |
(alarm->tm_mon << RTC_IRQ_SETUP_0_MONTH_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
hw_set_bits(&rtc_hw->irq_setup_0,
RTC_IRQ_SETUP_0_DAY_ENA_BITS |
((alarm->tm_mday + 1) << RTC_IRQ_SETUP_0_DAY_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
hw_set_bits(&rtc_hw->irq_setup_1,
RTC_IRQ_SETUP_1_DOTW_ENA_BITS |
(alarm->tm_wday << RTC_IRQ_SETUP_1_DOTW_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
hw_set_bits(&rtc_hw->irq_setup_1,
RTC_IRQ_SETUP_1_HOUR_ENA_BITS |
(alarm->tm_hour << RTC_IRQ_SETUP_1_HOUR_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
hw_set_bits(&rtc_hw->irq_setup_1,
RTC_IRQ_SETUP_1_MIN_ENA_BITS |
(alarm->tm_min << RTC_IRQ_SETUP_1_MIN_LSB));
}
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
hw_set_bits(&rtc_hw->irq_setup_1,
RTC_IRQ_SETUP_1_SEC_ENA_BITS |
(alarm->tm_sec << RTC_IRQ_SETUP_1_SEC_LSB));
}
data->alarm_time = *alarm;
data->alarm_mask = mask;
k_spin_unlock(&data->lock, key);
/* Enable the IRQ at the peri */
rtc_hw->inte = RTC_INTE_RTC_BITS;
rtc_enable_alarm();
return err;
}
static int rtc_rpi_pico_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_rpi_pico_data *data = dev->data;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
*timeptr = data->alarm_time;
*mask = data->alarm_mask;
}
return 0;
}
static int rtc_rpi_pico_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_rpi_pico_data *data = dev->data;
int ret = 0;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
ret = data->alarm_pending ? 1 : 0;
data->alarm_pending = false;
}
return ret;
}
static int rtc_rpi_pico_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_rpi_pico_data *data = dev->data;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
data->alarm_callback = callback;
data->alarm_user_data = user_data;
if ((callback == NULL) && (user_data == NULL)) {
rtc_disable_alarm();
}
}
return 0;
}
#endif /* CONFIG_RTC_ALARM */
static const struct rtc_driver_api rtc_rpi_pico_driver_api = {
.set_time = rtc_rpi_pico_set_time,
.get_time = rtc_rpi_pico_get_time,
#if defined(CONFIG_RTC_ALARM)
.alarm_get_supported_fields = rtc_rpi_pico_alarm_get_supported_fields,
.alarm_set_time = rtc_rpi_pico_alarm_set_time,
.alarm_get_time = rtc_rpi_pico_alarm_get_time,
.alarm_is_pending = rtc_rpi_pico_alarm_is_pending,
.alarm_set_callback = rtc_rpi_pico_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
};
DEVICE_DT_INST_DEFINE(0, &rtc_rpi_pico_init, NULL, &rtc_data, NULL, POST_KERNEL,
CONFIG_RTC_INIT_PRIORITY, &rtc_rpi_pico_driver_api);
``` | /content/code_sandbox/drivers/rtc/rtc_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,312 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_pcf8523
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(pcf8523, CONFIG_RTC_LOG_LEVEL);
/* PCF8523 register addresses */
#define PCF8523_CONTROL_1 0x00U
#define PCF8523_CONTROL_2 0x01U
#define PCF8523_CONTROL_3 0x02U
#define PCF8523_SECONDS 0x03U
#define PCF8523_MINUTES 0x04U
#define PCF8523_HOURS 0x05U
#define PCF8523_DAYS 0x06U
#define PCF8523_WEEKDAYS 0x07U
#define PCF8523_MONTHS 0x08U
#define PCF8523_YEARS 0x09U
#define PCF8523_MINUTE_ALARM 0x0aU
#define PCF8523_HOUR_ALARM 0x0bU
#define PCF8523_DAY_ALARM 0x0cU
#define PCF8523_WEEKDAY_ALARM 0x0dU
#define PCF8523_OFFSET 0x0eU
#define PCF8523_TMR_CLKOUT_CTRL 0x0fU
#define PCF8523_TMR_A_FREQ_CTRL 0x10U
#define PCF8523_TMR_A_REG 0x11U
#define PCF8523_TMR_B_FREQ_CTRL 0x12U
#define PCF8523_TMR_B_REG 0x13U
/* Control register bits */
#define PCF8523_CONTROL_1_CAP_SEL BIT(7)
#define PCF8523_CONTROL_1_T BIT(6)
#define PCF8523_CONTROL_1_STOP BIT(5)
#define PCF8523_CONTROL_1_SR BIT(4)
#define PCF8523_CONTROL_1_12_24 BIT(3)
#define PCF8523_CONTROL_1_SIE BIT(2)
#define PCF8523_CONTROL_1_AIE BIT(1)
#define PCF8523_CONTROL_1_CIE BIT(0)
#define PCF8523_CONTROL_2_WTAF BIT(7)
#define PCF8523_CONTROL_2_CTAF BIT(6)
#define PCF8523_CONTROL_2_CTBF BIT(5)
#define PCF8523_CONTROL_2_SF BIT(4)
#define PCF8523_CONTROL_2_AF BIT(3)
#define PCF8523_CONTROL_2_WTAIE BIT(2)
#define PCF8523_CONTROL_2_CTAIE BIT(1)
#define PCF8523_CONTROL_2_CTBIE BIT(0)
#define PCF8523_CONTROL_3_PM_MASK GENMASK(7, 5)
#define PCF8523_CONTROL_3_BSF BIT(3)
#define PCF8523_CONTROL_3_BLF BIT(2)
#define PCF8523_CONTROL_3_BSIE BIT(1)
#define PCF8523_CONTROL_3_BLIE BIT(0)
/* Time and date register bits */
#define PCF8523_SECONDS_OS BIT(7)
#define PCF8523_SECONDS_MASK GENMASK(6, 0)
#define PCF8523_MINUTES_MASK GENMASK(6, 0)
#define PCF8523_HOURS_AMPM BIT(5)
#define PCF8523_HOURS_12H_MASK GENMASK(4, 0)
#define PCF8523_HOURS_24H_MASK GENMASK(5, 0)
#define PCF8523_DAYS_MASK GENMASK(5, 0)
#define PCF8523_WEEKDAYS_MASK GENMASK(2, 0)
#define PCF8523_MONTHS_MASK GENMASK(4, 0)
#define PCF8523_YEARS_MASK GENMASK(7, 0)
/* Alarm register bits */
#define PCF8523_MINUTE_ALARM_AEN_M BIT(7)
#define PCF8523_MINUTE_ALARM_MASK GENMASK(6, 0)
#define PCF8523_HOUR_ALARM_AEN_H BIT(7)
#define PCF8523_HOUR_ALARM_AMPM BIT(5)
#define PCF8523_HOUR_ALARM_12H_MASK GENMASK(4, 0)
#define PCF8523_HOUR_ALARM_24H_MASK GENMASK(5, 0)
#define PCF8523_DAY_ALARM_AEN_D BIT(7)
#define PCF8523_DAY_ALARM_MASK GENMASK(5, 0)
#define PCF8523_WEEKDAY_ALARM_AEN_W BIT(7)
#define PCF8523_WEEKDAY_ALARM_MASK GENMASK(5, 0)
/* Timer register bits */
#define PCF8523_TMR_CLKOUT_CTRL_TAM BIT(7)
#define PCF8523_TMR_CLKOUT_CTRL_TBM BIT(6)
#define PCF8523_TMR_CLKOUT_CTRL_COF_MASK GENMASK(5, 3)
#define PCF8523_TMR_CLKOUT_CTRL_TAC_MASK GENMASK(2, 1)
#define PCF8523_TMR_CLKOUT_CTRL_TBC BIT(0)
#define PCF8523_TMR_A_FREQ_CTRL_TAQ_MASK GENMASK(2, 0)
#define PCF8523_TMR_A_REG_T_A_MASK GENMASK(7, 0)
#define PCF8523_TMR_B_FREQ_CTRL_TBW_MASK GENMASK(6, 4)
#define PCF8523_TMR_B_FREQ_CTRL_TBQ_MASK GENMASK(2, 0)
#define PCF8523_TMR_B_REG_T_B_MASK GENMASK(7, 0)
/* Offset register bits */
#define PCF8523_OFFSET_MODE BIT(7)
#define PCF8523_OFFSET_MASK GENMASK(6, 0)
/* RTC alarm time fields supported by the PCF8523 */
#define PCF8523_RTC_ALARM_TIME_MASK \
(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY | \
RTC_ALARM_TIME_MASK_WEEKDAY)
/* The PCF8523 only supports two-digit years, calculate offset to use */
#define PCF8523_YEARS_OFFSET (2000 - 1900)
/* The PCF8523 enumerates months 1 to 12, RTC API uses 0 to 11 */
#define PCF8523_MONTHS_OFFSET 1
/* Helper macro to guard int1-gpios related code */
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int1_gpios) && \
(defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE))
#define PCF8523_INT1_GPIOS_IN_USE 1
#endif
struct pcf8523_config {
const struct i2c_dt_spec i2c;
#ifdef PCF8523_INT1_GPIOS_IN_USE
struct gpio_dt_spec int1;
#endif /* PCF8523_INT1_GPIOS_IN_USE */
uint8_t cof;
uint8_t pm;
bool cap_sel;
bool wakeup_source;
};
struct pcf8523_data {
struct k_mutex lock;
#if PCF8523_INT1_GPIOS_IN_USE
struct gpio_callback int1_callback;
struct k_thread int1_thread;
struct k_sem int1_sem;
K_KERNEL_STACK_MEMBER(int1_stack, CONFIG_RTC_PCF8523_THREAD_STACK_SIZE);
#ifdef CONFIG_RTC_ALARM
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
rtc_update_callback update_callback;
void *update_user_data;
#endif /* CONFIG_RTC_UPDATE */
#endif /* PCF8523_INT1_GPIOS_IN_USE */
};
static int pcf8523_read_regs(const struct device *dev, uint8_t addr, void *buf, size_t len)
{
const struct pcf8523_config *config = dev->config;
int err;
err = i2c_write_read_dt(&config->i2c, &addr, sizeof(addr), buf, len);
if (err != 0) {
LOG_ERR("failed to read reg addr 0x%02x, len %d (err %d)", addr, len, err);
return err;
}
return 0;
}
static int pcf8523_read_reg8(const struct device *dev, uint8_t addr, uint8_t *val)
{
return pcf8523_read_regs(dev, addr, val, sizeof(*val));
}
static int pcf8523_write_regs(const struct device *dev, uint8_t addr, void *buf, size_t len)
{
const struct pcf8523_config *config = dev->config;
uint8_t block[sizeof(addr) + len];
int err;
block[0] = addr;
memcpy(&block[1], buf, len);
err = i2c_write_dt(&config->i2c, block, sizeof(block));
if (err != 0) {
LOG_ERR("failed to write reg addr 0x%02x, len %d (err %d)", addr, len, err);
return err;
}
return 0;
}
static int pcf8523_write_reg8(const struct device *dev, uint8_t addr, uint8_t val)
{
return pcf8523_write_regs(dev, addr, &val, sizeof(val));
}
static int pcf8523_write_stop_bit_unlocked(const struct device *dev, bool value)
{
uint8_t control_1;
int err;
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_1, &control_1);
if (err != 0) {
return err;
}
if (value) {
control_1 |= PCF8523_CONTROL_1_STOP;
} else {
control_1 &= ~(PCF8523_CONTROL_1_STOP);
}
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_1, control_1);
if (err != 0) {
return err;
}
return 0;
}
#if PCF8523_INT1_GPIOS_IN_USE
static int pcf8523_int1_enable_unlocked(const struct device *dev, bool enable)
{
const struct pcf8523_config *config = dev->config;
uint8_t tmr_clkout_ctrl;
int err;
if (!config->wakeup_source) {
/* Only change COF if not configured as wakeup-source */
err = pcf8523_read_reg8(dev, PCF8523_TMR_CLKOUT_CTRL, &tmr_clkout_ctrl);
if (err != 0) {
return err;
}
if (enable) {
/* Disable CLKOUT */
tmr_clkout_ctrl |= PCF8523_TMR_CLKOUT_CTRL_COF_MASK;
} else if (!config->wakeup_source) {
/* Enable CLKOUT */
tmr_clkout_ctrl &= ~(PCF8523_TMR_CLKOUT_CTRL_COF_MASK);
tmr_clkout_ctrl |=
FIELD_PREP(PCF8523_TMR_CLKOUT_CTRL_COF_MASK, config->cof);
}
err = pcf8523_write_reg8(dev, PCF8523_TMR_CLKOUT_CTRL, tmr_clkout_ctrl);
if (err != 0) {
return err;
}
}
/* Use edge interrupts to avoid multiple GPIO IRQs while servicing the IRQ in the thread */
err = gpio_pin_interrupt_configure_dt(&config->int1,
enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE);
if (err != 0) {
LOG_ERR("failed to %s GPIO IRQ (err %d)", enable ? "enable" : "disable", err);
return err;
}
return 0;
}
static void pcf8523_int1_thread(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
const struct device *dev = p1;
struct pcf8523_data *data = dev->data;
rtc_alarm_callback alarm_callback = NULL;
void *alarm_user_data = NULL;
rtc_update_callback update_callback = NULL;
void *update_user_data = NULL;
uint8_t control_2;
int err;
while (true) {
k_sem_take(&data->int1_sem, K_FOREVER);
k_mutex_lock(&data->lock, K_FOREVER);
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_2, &control_2);
if (err != 0) {
goto unlock;
}
#ifdef CONFIG_RTC_ALARM
if ((control_2 & PCF8523_CONTROL_2_AF) != 0 && data->alarm_callback != NULL) {
control_2 &= ~(PCF8523_CONTROL_2_AF);
alarm_callback = data->alarm_callback;
alarm_user_data = data->alarm_user_data;
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
if ((control_2 & PCF8523_CONTROL_2_SF) != 0) {
control_2 &= ~(PCF8523_CONTROL_2_SF);
update_callback = data->update_callback;
update_user_data = data->update_user_data;
}
#endif /* CONFIG_RTC_UPDATE */
control_2 |= PCF8523_CONTROL_2_CTAF | PCF8523_CONTROL_2_CTBF;
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_2, control_2);
if (err != 0) {
goto unlock;
}
/* Check if interrupt occurred between CONTROL_2 read/write */
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_2, &control_2);
if (err != 0) {
goto unlock;
}
if (((control_2 & PCF8523_CONTROL_2_AF) != 0U && alarm_callback != NULL) ||
((control_2 & PCF8523_CONTROL_2_SF) != 0U)) {
/*
* Another interrupt occurred while servicing this one, process current
* callback(s) and yield.
*/
k_sem_give(&data->int1_sem);
}
unlock:
k_mutex_unlock(&data->lock);
if (alarm_callback != NULL) {
alarm_callback(dev, 0U, alarm_user_data);
alarm_callback = NULL;
}
if (update_callback != NULL) {
update_callback(dev, update_user_data);
update_callback = NULL;
}
}
}
static void pcf8523_int1_callback_handler(const struct device *port, struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct pcf8523_data *data = CONTAINER_OF(cb, struct pcf8523_data, int1_callback);
ARG_UNUSED(port);
ARG_UNUSED(pins);
k_sem_give(&data->int1_sem);
}
#endif /* PCF8523_INT1_GPIOS_IN_USE */
static int pcf8523_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct pcf8523_data *data = dev->data;
uint8_t regs[7];
int err;
if (timeptr->tm_year < PCF8523_YEARS_OFFSET ||
timeptr->tm_year > PCF8523_YEARS_OFFSET + 99) {
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
/* Freeze the time circuits */
err = pcf8523_write_stop_bit_unlocked(dev, true);
if (err != 0) {
goto unlock;
}
LOG_DBG("set time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
regs[0] = bin2bcd(timeptr->tm_sec) & PCF8523_SECONDS_MASK;
regs[1] = bin2bcd(timeptr->tm_min) & PCF8523_MINUTES_MASK;
regs[2] = bin2bcd(timeptr->tm_hour) & PCF8523_HOURS_24H_MASK;
regs[3] = bin2bcd(timeptr->tm_mday) & PCF8523_DAYS_MASK;
regs[4] = bin2bcd(timeptr->tm_wday) & PCF8523_WEEKDAYS_MASK;
regs[5] = bin2bcd(timeptr->tm_mon + PCF8523_MONTHS_OFFSET) & PCF8523_MONTHS_MASK;
regs[6] = bin2bcd(timeptr->tm_year - PCF8523_YEARS_OFFSET) & PCF8523_YEARS_MASK;
/* Write registers PCF8523_SECONDS through PCF8523_YEARS */
err = pcf8523_write_regs(dev, PCF8523_SECONDS, ®s, sizeof(regs));
if (err != 0) {
goto unlock;
}
/* Unfreeze time circuits */
err = pcf8523_write_stop_bit_unlocked(dev, false);
if (err != 0) {
goto unlock;
}
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int pcf8523_get_time(const struct device *dev, struct rtc_time *timeptr)
{
uint8_t regs[10];
int err;
/* Read registers PCF8523_CONTROL_1 through PCF8523_YEARS */
err = pcf8523_read_regs(dev, PCF8523_CONTROL_1, ®s, sizeof(regs));
if (err != 0) {
return err;
}
if ((regs[0] & PCF8523_CONTROL_1_STOP) != 0) {
LOG_WRN("time circuits frozen");
return -ENODATA;
}
if ((regs[3] & PCF8523_SECONDS_OS) != 0) {
LOG_WRN("oscillator stopped or interrupted");
return -ENODATA;
}
memset(timeptr, 0U, sizeof(*timeptr));
timeptr->tm_sec = bcd2bin(regs[3] & PCF8523_SECONDS_MASK);
timeptr->tm_min = bcd2bin(regs[4] & PCF8523_MINUTES_MASK);
timeptr->tm_hour = bcd2bin(regs[5] & PCF8523_HOURS_24H_MASK);
timeptr->tm_mday = bcd2bin(regs[6] & PCF8523_DAYS_MASK);
timeptr->tm_wday = bcd2bin(regs[7] & PCF8523_WEEKDAYS_MASK);
timeptr->tm_mon = bcd2bin(regs[8] & PCF8523_MONTHS_MASK) - PCF8523_MONTHS_OFFSET;
timeptr->tm_year = bcd2bin(regs[9] & PCF8523_YEARS_MASK) + PCF8523_YEARS_OFFSET;
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
LOG_DBG("get time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
return 0;
}
#ifdef CONFIG_RTC_ALARM
static int pcf8523_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
{
ARG_UNUSED(dev);
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
*mask = PCF8523_RTC_ALARM_TIME_MASK;
return 0;
}
static int pcf8523_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
uint8_t regs[4];
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
if ((mask & ~(PCF8523_RTC_ALARM_TIME_MASK)) != 0U) {
LOG_ERR("unsupported alarm field mask 0x%04x", mask);
return -EINVAL;
}
if ((mask & RTC_ALARM_TIME_MASK_MINUTE) != 0U) {
regs[0] = bin2bcd(timeptr->tm_min) & PCF8523_MINUTE_ALARM_MASK;
} else {
regs[0] = PCF8523_MINUTE_ALARM_AEN_M;
}
if ((mask & RTC_ALARM_TIME_MASK_HOUR) != 0U) {
regs[1] = bin2bcd(timeptr->tm_hour) & PCF8523_HOUR_ALARM_24H_MASK;
} else {
regs[1] = PCF8523_HOUR_ALARM_AEN_H;
}
if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) != 0U) {
regs[2] = bin2bcd(timeptr->tm_mday) & PCF8523_DAY_ALARM_MASK;
} else {
regs[2] = PCF8523_DAY_ALARM_AEN_D;
}
if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) != 0U) {
regs[3] = bin2bcd(timeptr->tm_wday) & PCF8523_WEEKDAY_ALARM_MASK;
} else {
regs[3] = PCF8523_WEEKDAY_ALARM_AEN_W;
}
LOG_DBG("set alarm: year = %d, mon = %d, mday = %d, hour = %d, min = %d, mask = 0x%04x",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_hour,
timeptr->tm_min, mask);
/* Write registers PCF8523_MINUTE_ALARM through PCF8523_WEEKDAY_ALARM */
return pcf8523_write_regs(dev, PCF8523_MINUTE_ALARM, ®s, sizeof(regs));
}
static int pcf8523_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
uint8_t regs[4];
int err;
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
/* Read registers PCF8523_MINUTE_ALARM through PCF8523_WEEKDAY_ALARM */
err = pcf8523_read_regs(dev, PCF8523_MINUTE_ALARM, ®s, sizeof(regs));
if (err != 0) {
return err;
}
memset(timeptr, 0U, sizeof(*timeptr));
*mask = 0U;
if ((regs[0] & PCF8523_MINUTE_ALARM_AEN_M) == 0) {
timeptr->tm_min = bcd2bin(regs[0] & PCF8523_MINUTE_ALARM_MASK);
*mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if ((regs[1] & PCF8523_HOUR_ALARM_AEN_H) == 0) {
timeptr->tm_hour = bcd2bin(regs[1] & PCF8523_HOUR_ALARM_24H_MASK);
*mask |= RTC_ALARM_TIME_MASK_HOUR;
}
if ((regs[2] & PCF8523_DAY_ALARM_AEN_D) == 0) {
timeptr->tm_mday = bcd2bin(regs[2] & PCF8523_DAY_ALARM_MASK);
*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
if ((regs[3] & PCF8523_WEEKDAY_ALARM_AEN_W) == 0) {
timeptr->tm_wday = bcd2bin(regs[3] & PCF8523_WEEKDAY_ALARM_MASK);
*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
}
LOG_DBG("get alarm: year = %d, mon = %d, mday = %d, hour = %d, min = %d, mask = 0x%04x",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_hour,
timeptr->tm_min, *mask);
return 0;
}
static int pcf8523_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct pcf8523_data *data = dev->data;
uint8_t control_2;
int err;
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_2, &control_2);
if (err != 0) {
goto unlock;
}
if ((control_2 & PCF8523_CONTROL_2_AF) != 0) {
/* Clear alarm flag */
control_2 &= ~(PCF8523_CONTROL_2_AF);
/* Ensure other flags are left unchanged (PCF8523 performs logic AND at write) */
control_2 |= PCF8523_CONTROL_2_CTAF | PCF8523_CONTROL_2_CTBF | PCF8523_CONTROL_2_SF;
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_2, control_2);
if (err != 0) {
goto unlock;
}
/* Alarm pending */
err = 1;
}
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int pcf8523_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
#ifndef PCF8523_INT1_GPIOS_IN_USE
ARG_UNUSED(dev);
ARG_UNUSED(id);
ARG_UNUSED(callback);
ARG_UNUSED(user_data);
return -ENOTSUP;
#else
const struct pcf8523_config *config = dev->config;
struct pcf8523_data *data = dev->data;
uint8_t control_1;
int err = 0;
if (config->int1.port == NULL) {
return -ENOTSUP;
}
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
data->alarm_callback = callback;
data->alarm_user_data = user_data;
if (!config->wakeup_source) {
/* Only change AIE if not configured as wakeup-source */
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_1, &control_1);
if (err != 0) {
goto unlock;
}
if (callback != NULL) {
control_1 |= PCF8523_CONTROL_1_AIE;
} else {
control_1 &= ~(PCF8523_CONTROL_1_AIE);
}
if ((control_1 & PCF8523_CONTROL_1_SIE) == 0U) {
/* Only change INT1 GPIO if seconds timer interrupt not enabled */
err = pcf8523_int1_enable_unlocked(dev, callback != NULL);
if (err != 0) {
goto unlock;
}
}
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_1, control_1);
if (err != 0) {
goto unlock;
}
}
unlock:
k_mutex_unlock(&data->lock);
/* Wake up the INT1 thread since the alarm flag may already be set */
k_sem_give(&data->int1_sem);
return err;
#endif /* PCF8523_INT1_GPIOS_IN_USE */
}
#endif /* CONFIG_RTC_ALARM */
#if PCF8523_INT1_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE)
static int pcf8523_update_set_callback(const struct device *dev, rtc_update_callback callback,
void *user_data)
{
const struct pcf8523_config *config = dev->config;
struct pcf8523_data *data = dev->data;
uint8_t control_1;
int err;
if (config->int1.port == NULL) {
return -ENOTSUP;
}
k_mutex_lock(&data->lock, K_FOREVER);
data->update_callback = callback;
data->update_user_data = user_data;
err = pcf8523_read_reg8(dev, PCF8523_CONTROL_1, &control_1);
if (err != 0) {
goto unlock;
}
if (callback != NULL) {
control_1 |= PCF8523_CONTROL_1_SIE;
} else {
control_1 &= ~(PCF8523_CONTROL_1_SIE);
}
if ((control_1 & PCF8523_CONTROL_1_AIE) == 0U) {
/* Only change INT1 GPIO if alarm interrupt not enabled */
err = pcf8523_int1_enable_unlocked(dev, callback != NULL);
if (err != 0) {
goto unlock;
}
}
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_1, control_1);
if (err != 0) {
goto unlock;
}
unlock:
k_mutex_unlock(&data->lock);
/* Wake up the INT1 thread since the seconds flag may already be set */
k_sem_give(&data->int1_sem);
return err;
}
#endif /* PCF8523_INT1_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE) */
#ifdef CONFIG_RTC_CALIBRATION
/* See PCF8523 data sheet table 29 */
#if defined(CONFIG_RTC_PCF8523_OFFSET_MODE_SLOW)
#define PCF8523_OFFSET_PPB_PER_LSB 4340
#elif defined(CONFIG_RTC_PCF8523_OFFSET_MODE_FAST)
#define PCF8523_OFFSET_PPB_PER_LSB 4069
#else
#error Unsupported offset mode
#endif
#define PCF8523_OFFSET_PPB_MIN (-64 * PCF8523_OFFSET_PPB_PER_LSB)
#define PCF8523_OFFSET_PPB_MAX (63 * PCF8523_OFFSET_PPB_PER_LSB)
static int pcf8523_set_calibration(const struct device *dev, int32_t freq_ppb)
{
int32_t period_ppb = freq_ppb * -1;
int8_t offset;
if (period_ppb < PCF8523_OFFSET_PPB_MIN || period_ppb > PCF8523_OFFSET_PPB_MAX) {
LOG_WRN("calibration value (%d ppb) out of range", freq_ppb);
return -EINVAL;
}
offset = period_ppb / PCF8523_OFFSET_PPB_PER_LSB;
if (IS_ENABLED(CONFIG_RTC_PCF8523_OFFSET_MODE_FAST)) {
offset |= PCF8523_OFFSET_MODE;
}
LOG_DBG("freq_ppb = %d, period_ppb = %d, offset = %d", freq_ppb, period_ppb, offset);
return pcf8523_write_reg8(dev, PCF8523_OFFSET, offset);
}
static int pcf8523_get_calibration(const struct device *dev, int32_t *freq_ppb)
{
int32_t period_ppb;
int8_t offset;
int err;
err = pcf8523_read_reg8(dev, PCF8523_OFFSET, &offset);
if (err != 0) {
return err;
}
/* Clear mode bit and sign extend the offset */
period_ppb = (offset << 1U) >> 1U;
period_ppb = period_ppb * PCF8523_OFFSET_PPB_PER_LSB;
*freq_ppb = period_ppb * -1;
LOG_DBG("freq_ppb = %d, period_ppb = %d, offset = %d", *freq_ppb, period_ppb, offset);
return 0;
}
#endif /* CONFIG_RTC_CALIBRATION */
static int pcf8523_init(const struct device *dev)
{
const struct pcf8523_config *config = dev->config;
struct pcf8523_data *data = dev->data;
uint8_t tmr_clkout_ctrl;
uint8_t regs[3];
int err;
k_mutex_init(&data->lock);
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C bus not ready");
return -ENODEV;
}
#if PCF8523_INT1_GPIOS_IN_USE
k_tid_t tid;
if (config->int1.port != NULL) {
k_sem_init(&data->int1_sem, 0, INT_MAX);
if (!gpio_is_ready_dt(&config->int1)) {
LOG_ERR("GPIO not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->int1, GPIO_INPUT);
if (err != 0) {
LOG_ERR("failed to configure GPIO (err %d)", err);
return -ENODEV;
}
gpio_init_callback(&data->int1_callback, pcf8523_int1_callback_handler,
BIT(config->int1.pin));
err = gpio_add_callback_dt(&config->int1, &data->int1_callback);
if (err != 0) {
LOG_ERR("failed to add GPIO callback (err %d)", err);
return -ENODEV;
}
tid = k_thread_create(&data->int1_thread, data->int1_stack,
K_THREAD_STACK_SIZEOF(data->int1_stack),
pcf8523_int1_thread, (void *)dev, NULL,
NULL, CONFIG_RTC_PCF8523_THREAD_PRIO, 0, K_NO_WAIT);
k_thread_name_set(tid, "pcf8523");
/*
* Defer GPIO interrupt configuration due to INT1/CLKOUT pin sharing. This allows
* using the CLKOUT square-wave signal for RTC calibration when no alarm/update
* callbacks are enabled (and not configured as a wakeup-source).
*/
}
#endif /* PCF8523_INT1_GPIOS_IN_USE */
/*
* Manually initialize the required PCF8523 registers as performing a software reset will
* reset the time circuits.
*/
/* Read registers PCF8523_CONTROL_1 through PCF8523_CONTROL_3 */
err = pcf8523_read_regs(dev, PCF8523_CONTROL_1, ®s, sizeof(regs));
if (err != 0) {
return -ENODEV;
}
/* Set quartz crystal load capacitance */
if (config->cap_sel) {
regs[0] |= PCF8523_CONTROL_1_CAP_SEL;
} else {
regs[0] &= ~(PCF8523_CONTROL_1_CAP_SEL);
}
/* Use 24h time format */
regs[0] &= ~(PCF8523_CONTROL_1_12_24);
/* Disable second, alarm, and correction interrupts */
regs[0] &= ~(PCF8523_CONTROL_1_SIE | PCF8523_CONTROL_1_AIE | PCF8523_CONTROL_1_CIE);
if (config->wakeup_source) {
/*
* Always set AIE if wakeup-source. This allows the RTC to wake up the system even
* if the INT1 interrupt output is not directly connected to a GPIO (i.e. if
* connected to a PMIC input).
*/
regs[0] |= PCF8523_CONTROL_1_AIE;
}
/* Clear interrupt flags (except alarm flag, as a wake-up alarm may be pending) */
regs[1] &= ~(PCF8523_CONTROL_2_CTAF | PCF8523_CONTROL_2_CTBF | PCF8523_CONTROL_2_SF);
/* Disable watchdog, timer A, and timer B interrupts */
regs[1] &= ~(PCF8523_CONTROL_2_WTAIE | PCF8523_CONTROL_2_CTAIE | PCF8523_CONTROL_2_CTBIE);
/* Configure battery switch-over function */
regs[2] &= ~(PCF8523_CONTROL_3_PM_MASK);
regs[2] |= FIELD_PREP(PCF8523_CONTROL_3_PM_MASK, config->pm);
/* Clear battery status interrupt flag */
regs[2] &= ~(PCF8523_CONTROL_3_BSF);
/* Disable battery status interrupts */
regs[2] &= ~(PCF8523_CONTROL_3_BSIE | PCF8523_CONTROL_3_BLIE);
/* Write registers PCF8523_CONTROL_1 through PCF8523_CONTROL_3 */
err = pcf8523_write_regs(dev, PCF8523_CONTROL_1, ®s, sizeof(regs));
if (err != 0) {
return -ENODEV;
}
/* Disable watchdog and countdown timers, configure IRQ level*/
tmr_clkout_ctrl = 0U;
if (config->wakeup_source) {
/* Disable CLKOUT */
tmr_clkout_ctrl |= PCF8523_TMR_CLKOUT_CTRL_COF_MASK;
} else {
/* Configure CLKOUT frequency */
tmr_clkout_ctrl |= FIELD_PREP(PCF8523_TMR_CLKOUT_CTRL_COF_MASK, config->cof);
}
err = pcf8523_write_reg8(dev, PCF8523_TMR_CLKOUT_CTRL, tmr_clkout_ctrl);
if (err != 0) {
return -ENODEV;
}
return 0;
}
/* Mapping from DT battery-switch-over enum to CONTROL_3 PM field value */
#define PCF8523_PM_STANDARD 4U
#define PCF8523_PM_DIRECT 5U
#define PCF8523_PM_DISABLED 7U
#ifdef CONFIG_PM_DEVICE
static int pcf8523_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct pcf8523_config *config = dev->config;
uint8_t control_3;
int err;
if (config->pm == PCF8523_PM_DISABLED) {
/* Only one power supply */
return -ENOTSUP;
}
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
/* Disable battery switch-over function */
control_3 = FIELD_PREP(PCF8523_CONTROL_3_PM_MASK, PCF8523_PM_DISABLED);
break;
case PM_DEVICE_ACTION_RESUME:
/* Re-enable battery switch-over function */
control_3 = FIELD_PREP(PCF8523_CONTROL_3_PM_MASK, config->pm);
break;
default:
return -ENOTSUP;
}
err = pcf8523_write_reg8(dev, PCF8523_CONTROL_3, control_3);
if (err != 0) {
return -EIO;
}
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static const struct rtc_driver_api pcf8523_driver_api = {
.set_time = pcf8523_set_time,
.get_time = pcf8523_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = pcf8523_alarm_get_supported_fields,
.alarm_set_time = pcf8523_alarm_set_time,
.alarm_get_time = pcf8523_alarm_get_time,
.alarm_is_pending = pcf8523_alarm_is_pending,
.alarm_set_callback = pcf8523_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#if PCF8523_INT1_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE)
.update_set_callback = pcf8523_update_set_callback,
#endif /* PCF8523_INT1_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE) */
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = pcf8523_set_calibration,
.get_calibration = pcf8523_get_calibration,
#endif /* CONFIG_RTC_CALIBRATION */
};
#define PCF8523_PM_FROM_DT_INST(inst) \
UTIL_CAT(PCF8523_PM_, DT_INST_STRING_UPPER_TOKEN(inst, battery_switch_over))
#define PCF8523_CAP_SEL_FROM_DT_INST(inst) (DT_INST_PROP(inst, quartz_load_femtofarads) == 12500)
#define PCF8523_INIT(inst) \
static const struct pcf8523_config pcf8523_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.cof = DT_INST_ENUM_IDX(inst, clkout_frequency), \
.pm = PCF8523_PM_FROM_DT_INST(inst), \
.cap_sel = PCF8523_CAP_SEL_FROM_DT_INST(inst), \
.wakeup_source = DT_INST_PROP(inst, wakeup_source), \
IF_ENABLED(PCF8523_INT1_GPIOS_IN_USE, \
(.int1 = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0})))}; \
\
static struct pcf8523_data pcf8523_data_##inst; \
\
PM_DEVICE_DT_INST_DEFINE(inst, pcf8523_pm_action); \
\
DEVICE_DT_INST_DEFINE(inst, &pcf8523_init, PM_DEVICE_DT_INST_GET(inst), \
&pcf8523_data_##inst, &pcf8523_config_##inst, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, &pcf8523_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PCF8523_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_pcf8523.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,989 |
```c
/*
*
*/
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#include "rtc_utils.h"
#define DT_DRV_COMPAT ambiq_rtc
LOG_MODULE_REGISTER(ambiq_rtc, CONFIG_RTC_LOG_LEVEL);
#include <am_mcu_apollo.h>
#define AMBIQ_RTC_ALARM_TIME_MASK \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_WEEKDAY | RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY)
/* struct tm start time: 1st, Jan, 1900 */
#define TM_YEAR_REF 1900
#define AMBIQ_RTC_YEAR_MAX 2199
struct ambiq_rtc_config {
uint8_t clk_src;
};
struct ambiq_rtc_data {
struct k_spinlock lock;
#ifdef CONFIG_RTC_ALARM
struct rtc_time alarm_time;
uint16_t alarm_set_mask;
rtc_alarm_callback alarm_user_callback;
void *alarm_user_data;
bool alarm_pending;
#endif
};
static void rtc_time_to_ambiq_time_set(const struct rtc_time *tm, am_hal_rtc_time_t *atm)
{
atm->ui32CenturyBit = ((tm->tm_year <= 99) || (tm->tm_year >= 200));
atm->ui32Year = tm->tm_year;
if (tm->tm_year > 99) {
atm->ui32Year = tm->tm_year % 100;
}
atm->ui32Weekday = tm->tm_wday;
atm->ui32Month = tm->tm_mon + 1;
atm->ui32DayOfMonth = tm->tm_mday;
atm->ui32Hour = tm->tm_hour;
atm->ui32Minute = tm->tm_min;
atm->ui32Second = tm->tm_sec;
/* Nanoseconds times 10mil is hundredths */
atm->ui32Hundredths = tm->tm_nsec / 10000000;
if (atm->ui32Hundredths > 99) {
uint16_t value = atm->ui32Hundredths / 100;
atm->ui32Second += value;
atm->ui32Hundredths -= value*100;
}
}
/* To set the timer registers */
static void ambiq_time_to_rtc_time_set(const am_hal_rtc_time_t *atm, struct rtc_time *tm)
{
tm->tm_year = atm->ui32Year;
if (atm->ui32CenturyBit == 0)
tm->tm_year += 100;
else
tm->tm_year += 200;
tm->tm_wday = atm->ui32Weekday;
tm->tm_mon = atm->ui32Month - 1;
tm->tm_mday = atm->ui32DayOfMonth;
tm->tm_hour = atm->ui32Hour;
tm->tm_min = atm->ui32Minute;
tm->tm_sec = atm->ui32Second;
/* Nanoseconds times 10mil is hundredths */
tm->tm_nsec = atm->ui32Hundredths * 10000000;
}
static int test_for_rollover(am_hal_rtc_time_t *atm)
{
if ((atm->ui32Year == 99) &&
(atm->ui32Month == 12) &&
(atm->ui32DayOfMonth == 31)) {
return -EINVAL;
}
return 0;
}
/* To set the timer registers */
static int ambiq_rtc_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
int err = 0;
am_hal_rtc_time_t ambiq_time = {0};
struct ambiq_rtc_data *data = dev->data;
if (timeptr->tm_year + TM_YEAR_REF > AMBIQ_RTC_YEAR_MAX) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
LOG_DBG("set time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
/* Convertn to Ambiq Time */
rtc_time_to_ambiq_time_set(timeptr, &ambiq_time);
if (test_for_rollover(&ambiq_time)) {
return -EINVAL;
}
err = am_hal_rtc_time_set(&ambiq_time);
if (err) {
LOG_WRN("Set Timer returned an error - %d!", err);
}
k_spin_unlock(&data->lock, key);
return err;
}
/* To get from the timer registers */
static int ambiq_rtc_get_time(const struct device *dev, struct rtc_time *timeptr)
{
int err = 0;
am_hal_rtc_time_t ambiq_time = {0};
struct ambiq_rtc_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
err = am_hal_rtc_time_get(&ambiq_time);
if (err != 0) {
LOG_WRN("Get Timer returned an error - %d!", err);
goto unlock;
}
ambiq_time_to_rtc_time_set(&ambiq_time, timeptr);
LOG_DBG("get time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
unlock:
k_spin_unlock(&data->lock, key);
return err;
}
#ifdef CONFIG_RTC_ALARM
static int ambiq_rtc_alarm_get_supported_fields(const struct device *dev,
uint16_t id, uint16_t *mask)
{
ARG_UNUSED(dev);
if (id != 0U) {
LOG_ERR("Invalid ID %d", id);
return -EINVAL;
}
*mask = AMBIQ_RTC_ALARM_TIME_MASK;
return 0;
}
/* To get from the alarm registers */
static int ambiq_rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
int err = 0;
am_hal_rtc_time_t ambiq_time = {0};
struct ambiq_rtc_data *data = dev->data;
if (id != 0U) {
LOG_ERR("Invalid ID %d", id);
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
err = am_hal_rtc_alarm_get(&ambiq_time, NULL);
if (err != 0) {
LOG_DBG("Invalid Input Value");
return -EINVAL;
}
ambiq_time_to_rtc_time_set(&ambiq_time, timeptr);
*mask = data->alarm_set_mask;
LOG_DBG("get alarm: wday = %d, mon = %d, mday = %d, hour = %d, min = %d, sec = %d, "
"mask = 0x%04x", timeptr->tm_wday, timeptr->tm_mon, timeptr->tm_mday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec, *mask);
k_spin_unlock(&data->lock, key);
return err;
}
static int ambiq_rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
int err = 0;
struct ambiq_rtc_data *data = dev->data;
am_hal_rtc_time_t ambiq_time = {0};
uint16_t mask_available;
if (id != 0U) {
LOG_ERR("Invalid ID %d", id);
return -EINVAL;
}
if (rtc_utils_validate_rtc_time(timeptr, mask) == false) {
LOG_DBG("Invalid Input Value");
return -EINVAL;
}
(void)ambiq_rtc_alarm_get_supported_fields(NULL, 0, &mask_available);
if (mask & ~mask_available) {
return -EINVAL;
}
data->alarm_set_mask = mask;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Disable and clear the alarm */
am_hal_rtc_interrupt_disable(AM_HAL_RTC_INT_ALM);
am_hal_rtc_interrupt_clear(AM_HAL_RTC_INT_ALM);
/* When mask is 0 */
if (mask == 0) {
LOG_DBG("The alarm is disabled");
goto unlock;
}
LOG_DBG("set alarm: second = %d, min = %d, hour = %d, mday = %d, month = %d,"
"wday = %d, mask = 0x%04x",
timeptr->tm_sec, timeptr->tm_min, timeptr->tm_hour, timeptr->tm_mday,
timeptr->tm_mon, timeptr->tm_wday, mask);
/* Convertn to Ambiq Time */
rtc_time_to_ambiq_time_set(timeptr, &ambiq_time);
/* Set RTC ALARM, Ambiq must have interval != AM_HAL_RTC_ALM_RPT_DIS */
if (0 != am_hal_rtc_alarm_set(&ambiq_time, AM_HAL_RTC_ALM_RPT_YR)) {
LOG_DBG("Invalid Input Value");
err = -EINVAL;
goto unlock;
}
am_hal_rtc_interrupt_enable(AM_HAL_RTC_INT_ALM);
unlock:
k_spin_unlock(&data->lock, key);
return err;
}
static int ambiq_rtc_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct ambiq_rtc_data *data = dev->data;
int ret = 0;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
ret = data->alarm_pending ? 1 : 0;
data->alarm_pending = false;
}
return ret;
}
static void ambiq_rtc_isr(const struct device *dev)
{
/* Clear the RTC alarm interrupt. 8*/
am_hal_rtc_interrupt_clear(AM_HAL_RTC_INT_ALM);
#if defined(CONFIG_RTC_ALARM)
struct ambiq_rtc_data *data = dev->data;
if (data->alarm_user_callback) {
data->alarm_user_callback(dev, 0, data->alarm_user_data);
data->alarm_pending = false;
} else {
data->alarm_pending = true;
}
#endif
}
static int ambiq_rtc_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct ambiq_rtc_data *data = dev->data;
if (id != 0U) {
LOG_ERR("Invalid ID %d", id);
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
data->alarm_user_callback = callback;
data->alarm_user_data = user_data;
if ((callback == NULL) && (user_data == NULL)) {
am_hal_rtc_interrupt_disable(AM_HAL_RTC_INT_ALM);
}
}
return 0;
}
#endif
static int ambiq_rtc_init(const struct device *dev)
{
const struct ambiq_rtc_config *config = dev->config;
#
#ifdef CONFIG_RTC_ALARM
struct ambiq_rtc_data *data = dev->data;
#endif
/* Enable the clock for RTC. */
am_hal_clkgen_control(config->clk_src, NULL);
/* Enable the RTC. */
am_hal_rtc_osc_enable();
#ifdef CONFIG_RTC_ALARM
data->alarm_user_callback = NULL;
data->alarm_pending = false;
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), ambiq_rtc_isr, DEVICE_DT_INST_GET(0),
0);
irq_enable(DT_INST_IRQN(0));
#endif
return 0;
}
static const struct rtc_driver_api ambiq_rtc_driver_api = {
.set_time = ambiq_rtc_set_time,
.get_time = ambiq_rtc_get_time,
/* RTC_UPDATE not supported */
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = ambiq_rtc_alarm_get_supported_fields,
.alarm_set_time = ambiq_rtc_alarm_set_time,
.alarm_get_time = ambiq_rtc_alarm_get_time,
.alarm_is_pending = ambiq_rtc_alarm_is_pending,
.alarm_set_callback = ambiq_rtc_alarm_set_callback,
#endif
};
#define AMBIQ_RTC_INIT(inst) \
static const struct ambiq_rtc_config ambiq_rtc_config_##inst = { \
.clk_src = DT_INST_ENUM_IDX(inst, clock)}; \
\
static struct ambiq_rtc_data ambiq_rtc_data##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &ambiq_rtc_init, NULL, &ambiq_rtc_data##inst, \
&ambiq_rtc_config_##inst, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, &ambiq_rtc_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_RTC_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,968 |
```unknown
config RTC_RV3028
bool "Micro Crystal RV3028 I2C extreme low power RTC driver"
default y
depends on DT_HAS_MICROCRYSTAL_RV3028_ENABLED
select I2C
help
Enable the Micro Crystal RV3028 I2C RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.rv3028 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
config RTC_SMARTBOND
bool "Smartbond RTC driver"
depends on DT_HAS_RENESAS_SMARTBOND_RTC_ENABLED
default y
help
Build RTC driver for Smartbond SoCs.
``` | /content/code_sandbox/drivers/rtc/Kconfig.smartbond | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```c
/*
*
*/
#define DT_DRV_COMPAT microcrystal_rv3028
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include "rtc_utils.h"
LOG_MODULE_REGISTER(rv3028, CONFIG_RTC_LOG_LEVEL);
/* RV3028 RAM register addresses */
#define RV3028_REG_SECONDS 0x00
#define RV3028_REG_MINUTES 0x01
#define RV3028_REG_HOURS 0x02
#define RV3028_REG_WEEKDAY 0x03
#define RV3028_REG_DATE 0x04
#define RV3028_REG_MONTH 0x05
#define RV3028_REG_YEAR 0x06
#define RV3028_REG_ALARM_MINUTES 0x07
#define RV3028_REG_ALARM_HOURS 0x08
#define RV3028_REG_ALARM_WEEKDAY 0x09
#define RV3028_REG_STATUS 0x0E
#define RV3028_REG_CONTROL1 0x0F
#define RV3028_REG_CONTROL2 0x10
#define RV3028_REG_EVENT_CONTROL 0x13
#define RV3028_REG_TS_COUNT 0x14
#define RV3028_REG_TS_SECONDS 0x15
#define RV3028_REG_TS_MINUTES 0x16
#define RV3028_REG_TS_HOURS 0x17
#define RV3028_REG_TS_DATE 0x18
#define RV3028_REG_TS_MONTH 0x19
#define RV3028_REG_TS_YEAR 0x1A
#define RV3028_REG_UNIXTIME0 0x1B
#define RV3028_REG_UNIXTIME1 0x1C
#define RV3028_REG_UNIXTIME2 0x1D
#define RV3028_REG_UNIXTIME3 0x1E
#define RV3028_REG_USER_RAM1 0x1F
#define RV3028_REG_USER_RAM2 0x20
#define RV3028_REG_EEPROM_ADDRESS 0x25
#define RV3028_REG_EEPROM_DATA 0x26
#define RV3028_REG_EEPROM_COMMAND 0x27
#define RV3028_REG_ID 0x28
#define RV3028_REG_CLKOUT 0x35
#define RV3028_REG_OFFSET 0x36
#define RV3028_REG_BACKUP 0x37
#define RV3028_CONTROL1_TD BIT(0)
#define RV3028_CONTROL1_TE GENMASK(2, 1)
#define RV3028_CONTROL1_EERD BIT(3)
#define RV3028_CONTROL1_USEL BIT(4)
#define RV3028_CONTROL1_WADA BIT(5)
#define RV3028_CONTROL1_TRPT BIT(7)
#define RV3028_CONTROL2_RESET BIT(0)
#define RV3028_CONTROL2_12_24 BIT(1)
#define RV3028_CONTROL2_EIE BIT(2)
#define RV3028_CONTROL2_AIE BIT(3)
#define RV3028_CONTROL2_TIE BIT(4)
#define RV3028_CONTROL2_UIE BIT(5)
#define RV3028_CONTROL2_TSE BIT(7)
#define RV3028_STATUS_PORF BIT(0)
#define RV3028_STATUS_EVF BIT(1)
#define RV3028_STATUS_AF BIT(2)
#define RV3028_STATUS_TF BIT(3)
#define RV3028_STATUS_UF BIT(4)
#define RV3028_STATUS_BSF BIT(5)
#define RV3028_STATUS_CLKF BIT(6)
#define RV3028_STATUS_EEBUSY BIT(7)
#define RV3028_CLKOUT_FD GENMASK(2, 0)
#define RV3028_CLKOUT_PORIE BIT(3)
#define RV3028_CLKOUT_CLKSY BIT(6)
#define RV3028_CLKOUT_CLKOE BIT(7)
#define RV3028_CLKOUT_FD_LOW 0x7
#define RV3028_BACKUP_TCE BIT(5)
#define RV3028_BACKUP_TCR GENMASK(1, 0)
#define RV3028_BACKUP_BSM GENMASK(3, 2)
#define RV3028_BSM_LEVEL 0x3
#define RV3028_BSM_DIRECT 0x1
#define RV3028_BSM_DISABLED 0x0
/* RV3028 EE command register values */
#define RV3028_EEPROM_CMD_INIT 0x00
#define RV3028_EEPROM_CMD_UPDATE 0x11
#define RV3028_EEPROM_CMD_REFRESH 0x12
#define RV3028_EEPROM_CMD_WRITE 0x21
#define RV3028_EEPROM_CMD_READ 0x22
#define RV3028_SECONDS_MASK GENMASK(6, 0)
#define RV3028_MINUTES_MASK GENMASK(6, 0)
#define RV3028_HOURS_AMPM BIT(5)
#define RV3028_HOURS_12H_MASK GENMASK(4, 0)
#define RV3028_HOURS_24H_MASK GENMASK(5, 0)
#define RV3028_DATE_MASK GENMASK(5, 0)
#define RV3028_WEEKDAY_MASK GENMASK(2, 0)
#define RV3028_MONTH_MASK GENMASK(4, 0)
#define RV3028_YEAR_MASK GENMASK(7, 0)
#define RV3028_ALARM_MINUTES_AE_M BIT(7)
#define RV3028_ALARM_MINUTES_MASK GENMASK(6, 0)
#define RV3028_ALARM_HOURS_AE_H BIT(7)
#define RV3028_ALARM_HOURS_AMPM BIT(5)
#define RV3028_ALARM_HOURS_12H_MASK GENMASK(4, 0)
#define RV3028_ALARM_HOURS_24H_MASK GENMASK(5, 0)
#define RV3028_ALARM_DATE_AE_WD BIT(7)
#define RV3028_ALARM_DATE_MASK GENMASK(5, 0)
/* The RV3028 only supports two-digit years. Leap years are correctly handled from 2000 to 2099 */
#define RV3028_YEAR_OFFSET (2000 - 1900)
/* The RV3028 enumerates months 1 to 12 */
#define RV3028_MONTH_OFFSET 1
#define RV3028_EEBUSY_POLL_US 10000
#define RV3028_EEBUSY_TIMEOUT_MS 100
/* RTC alarm time fields supported by the RV3028 */
#define RV3028_RTC_ALARM_TIME_MASK \
(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY)
/* RTC time fields supported by the RV3028 */
#define RV3028_RTC_TIME_MASK \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR | \
RTC_ALARM_TIME_MASK_WEEKDAY)
/* Helper macro to guard int-gpios related code */
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) && \
(defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE))
#define RV3028_INT_GPIOS_IN_USE 1
#endif
struct rv3028_config {
const struct i2c_dt_spec i2c;
#ifdef RV3028_INT_GPIOS_IN_USE
struct gpio_dt_spec gpio_int;
#endif /* RV3028_INT_GPIOS_IN_USE */
uint8_t cof;
uint8_t backup;
};
struct rv3028_data {
struct k_sem lock;
#if RV3028_INT_GPIOS_IN_USE
const struct device *dev;
struct gpio_callback int_callback;
struct k_work work;
#ifdef CONFIG_RTC_ALARM
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
rtc_update_callback update_callback;
void *update_user_data;
#endif /* CONFIG_RTC_UPDATE */
#endif /* RV3028_INT_GPIOS_IN_USE */
};
static void rv3028_lock_sem(const struct device *dev)
{
struct rv3028_data *data = dev->data;
(void)k_sem_take(&data->lock, K_FOREVER);
}
static void rv3028_unlock_sem(const struct device *dev)
{
struct rv3028_data *data = dev->data;
k_sem_give(&data->lock);
}
static int rv3028_read_regs(const struct device *dev, uint8_t addr, void *buf, size_t len)
{
const struct rv3028_config *config = dev->config;
int err;
err = i2c_write_read_dt(&config->i2c, &addr, sizeof(addr), buf, len);
if (err) {
LOG_ERR("failed to read reg addr 0x%02x, len %d (err %d)", addr, len, err);
return err;
}
return 0;
}
static int rv3028_read_reg8(const struct device *dev, uint8_t addr, uint8_t *val)
{
return rv3028_read_regs(dev, addr, val, sizeof(*val));
}
static int rv3028_write_regs(const struct device *dev, uint8_t addr, void *buf, size_t len)
{
const struct rv3028_config *config = dev->config;
uint8_t block[sizeof(addr) + len];
int err;
block[0] = addr;
memcpy(&block[1], buf, len);
err = i2c_write_dt(&config->i2c, block, sizeof(block));
if (err) {
LOG_ERR("failed to write reg addr 0x%02x, len %d (err %d)", addr, len, err);
return err;
}
return 0;
}
static int rv3028_write_reg8(const struct device *dev, uint8_t addr, uint8_t val)
{
return rv3028_write_regs(dev, addr, &val, sizeof(val));
}
static int rv3028_update_reg8(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
{
const struct rv3028_config *config = dev->config;
int err;
err = i2c_reg_update_byte_dt(&config->i2c, addr, mask, val);
if (err) {
LOG_ERR("failed to update reg addr 0x%02x, mask 0x%02x, val 0x%02x (err %d)", addr,
mask, val, err);
return err;
}
return 0;
}
static int rv3028_eeprom_wait_busy(const struct device *dev)
{
uint8_t status = 0;
int err;
int64_t timeout_time = k_uptime_get() + RV3028_EEBUSY_TIMEOUT_MS;
/* Wait while the EEPROM is busy */
for (;;) {
err = rv3028_read_reg8(dev, RV3028_REG_STATUS, &status);
if (err) {
return err;
}
if (!(status & RV3028_STATUS_EEBUSY)) {
break;
}
if (k_uptime_get() > timeout_time) {
return -ETIME;
}
k_busy_wait(RV3028_EEBUSY_POLL_US);
}
return 0;
}
static int rv3028_exit_eerd(const struct device *dev)
{
return rv3028_update_reg8(dev, RV3028_REG_CONTROL1, RV3028_CONTROL1_EERD, 0);
}
static int rv3028_enter_eerd(const struct device *dev)
{
uint8_t ctrl1;
bool eerd;
int ret;
ret = rv3028_read_reg8(dev, RV3028_REG_CONTROL1, &ctrl1);
if (ret) {
return ret;
}
eerd = ctrl1 & RV3028_CONTROL1_EERD;
if (eerd) {
return 0;
}
ret = rv3028_update_reg8(dev, RV3028_REG_CONTROL1, RV3028_CONTROL1_EERD,
RV3028_CONTROL1_EERD);
ret = rv3028_eeprom_wait_busy(dev);
if (ret) {
rv3028_exit_eerd(dev);
return ret;
}
return ret;
}
static int rv3028_eeprom_command(const struct device *dev, uint8_t command)
{
int err;
err = rv3028_write_reg8(dev, RV3028_REG_EEPROM_COMMAND, RV3028_EEPROM_CMD_INIT);
if (err) {
return err;
}
return rv3028_write_reg8(dev, RV3028_REG_EEPROM_COMMAND, command);
}
static int rv3028_update(const struct device *dev)
{
int err;
err = rv3028_eeprom_command(dev, RV3028_EEPROM_CMD_UPDATE);
if (err) {
goto exit_eerd;
}
err = rv3028_eeprom_wait_busy(dev);
exit_eerd:
rv3028_exit_eerd(dev);
return err;
}
static int rv3028_refresh(const struct device *dev)
{
int err;
err = rv3028_eeprom_command(dev, RV3028_EEPROM_CMD_REFRESH);
if (err) {
goto exit_eerd;
}
err = rv3028_eeprom_wait_busy(dev);
exit_eerd:
rv3028_exit_eerd(dev);
return err;
}
static int rv3028_update_cfg(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
{
uint8_t val_old, val_new;
int err;
err = rv3028_read_reg8(dev, addr, &val_old);
if (err) {
return err;
}
val_new = (val_old & ~mask) | (val & mask);
if (val_new == val_old) {
return 0;
}
err = rv3028_enter_eerd(dev);
if (err) {
return err;
}
err = rv3028_write_reg8(dev, addr, val_new);
if (err) {
rv3028_exit_eerd(dev);
return err;
}
return rv3028_update(dev);
}
#if RV3028_INT_GPIOS_IN_USE
static void rv3028_work_cb(struct k_work *work)
{
struct rv3028_data *data = CONTAINER_OF(work, struct rv3028_data, work);
const struct device *dev = data->dev;
rtc_alarm_callback alarm_callback = NULL;
void *alarm_user_data = NULL;
rtc_update_callback update_callback = NULL;
void *update_user_data = NULL;
uint8_t status;
int err;
rv3028_lock_sem(dev);
err = rv3028_read_reg8(data->dev, RV3028_REG_STATUS, &status);
if (err) {
goto unlock;
}
#ifdef CONFIG_RTC_ALARM
if ((status & RV3028_STATUS_AF) && data->alarm_callback != NULL) {
status &= ~(RV3028_STATUS_AF);
alarm_callback = data->alarm_callback;
alarm_user_data = data->alarm_user_data;
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
if ((status & RV3028_STATUS_UF) && data->update_callback != NULL) {
status &= ~(RV3028_STATUS_UF);
update_callback = data->update_callback;
update_user_data = data->update_user_data;
}
#endif /* CONFIG_RTC_UPDATE */
err = rv3028_write_reg8(dev, RV3028_REG_STATUS, status);
if (err) {
goto unlock;
}
/* Check if interrupt occurred between STATUS read/write */
err = rv3028_read_reg8(dev, RV3028_REG_STATUS, &status);
if (err) {
goto unlock;
}
if (((status & RV3028_STATUS_AF) && alarm_callback != NULL) ||
((status & RV3028_STATUS_UF) && update_callback != NULL)) {
/* Another interrupt occurred while servicing this one */
k_work_submit(&data->work);
}
unlock:
rv3028_unlock_sem(dev);
if (alarm_callback != NULL) {
alarm_callback(dev, 0U, alarm_user_data);
alarm_callback = NULL;
}
if (update_callback != NULL) {
update_callback(dev, update_user_data);
update_callback = NULL;
}
}
static void rv3028_int_handler(const struct device *port, struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct rv3028_data *data = CONTAINER_OF(cb, struct rv3028_data, int_callback);
ARG_UNUSED(port);
ARG_UNUSED(pins);
k_work_submit(&data->work);
}
#endif /* RV3028_INT_GPIOS_IN_USE */
static int rv3028_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
uint8_t date[7];
int err;
if (timeptr == NULL ||
!rtc_utils_validate_rtc_time(timeptr, RV3028_RTC_TIME_MASK) ||
(timeptr->tm_year < RV3028_YEAR_OFFSET)) {
LOG_ERR("invalid time");
return -EINVAL;
}
rv3028_lock_sem(dev);
LOG_DBG("set time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
date[0] = bin2bcd(timeptr->tm_sec) & RV3028_SECONDS_MASK;
date[1] = bin2bcd(timeptr->tm_min) & RV3028_MINUTES_MASK;
date[2] = bin2bcd(timeptr->tm_hour) & RV3028_HOURS_24H_MASK;
date[3] = bin2bcd(timeptr->tm_wday) & RV3028_WEEKDAY_MASK;
date[4] = bin2bcd(timeptr->tm_mday) & RV3028_DATE_MASK;
date[5] = bin2bcd(timeptr->tm_mon + RV3028_MONTH_OFFSET) & RV3028_MONTH_MASK;
date[6] = bin2bcd(timeptr->tm_year - RV3028_YEAR_OFFSET) & RV3028_YEAR_MASK;
err = rv3028_write_regs(dev, RV3028_REG_SECONDS, &date, sizeof(date));
if (err) {
goto unlock;
}
/* Clear Power On Reset Flag */
err = rv3028_update_reg8(dev, RV3028_REG_STATUS, RV3028_STATUS_PORF, 0);
unlock:
rv3028_unlock_sem(dev);
return err;
}
static int rv3028_get_time(const struct device *dev, struct rtc_time *timeptr)
{
uint8_t status;
uint8_t date[7];
int err;
if (timeptr == NULL) {
return -EINVAL;
}
err = rv3028_read_reg8(dev, RV3028_REG_STATUS, &status);
if (err) {
return err;
}
if (status & RV3028_STATUS_PORF) {
/* Power On Reset Flag indicates invalid data */
return -ENODATA;
}
err = rv3028_read_regs(dev, RV3028_REG_SECONDS, date, sizeof(date));
if (err) {
return err;
}
memset(timeptr, 0U, sizeof(*timeptr));
timeptr->tm_sec = bcd2bin(date[0] & RV3028_SECONDS_MASK);
timeptr->tm_min = bcd2bin(date[1] & RV3028_MINUTES_MASK);
timeptr->tm_hour = bcd2bin(date[2] & RV3028_HOURS_24H_MASK);
timeptr->tm_wday = bcd2bin(date[3] & RV3028_WEEKDAY_MASK);
timeptr->tm_mday = bcd2bin(date[4] & RV3028_DATE_MASK);
timeptr->tm_mon = bcd2bin(date[5] & RV3028_MONTH_MASK) - RV3028_MONTH_OFFSET;
timeptr->tm_year = bcd2bin(date[6] & RV3028_YEAR_MASK) + RV3028_YEAR_OFFSET;
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
LOG_DBG("get time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
return 0;
}
#ifdef CONFIG_RTC_ALARM
static int rv3028_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
{
ARG_UNUSED(dev);
if (id != 0U) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
*mask = RV3028_RTC_ALARM_TIME_MASK;
return 0;
}
static int rv3028_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
uint8_t regs[3];
if (id != 0U) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
if (mask & ~(RV3028_RTC_ALARM_TIME_MASK)) {
LOG_ERR("unsupported alarm field mask 0x%04x", mask);
return -EINVAL;
}
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_ERR("invalid alarm time");
return -EINVAL;
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
regs[0] = bin2bcd(timeptr->tm_min) & RV3028_ALARM_MINUTES_MASK;
} else {
regs[0] = RTC_ALARM_TIME_MASK_MINUTE;
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
regs[1] = bin2bcd(timeptr->tm_hour) & RV3028_ALARM_HOURS_24H_MASK;
} else {
regs[1] = RV3028_ALARM_HOURS_AE_H;
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
regs[2] = bin2bcd(timeptr->tm_mday) & RV3028_ALARM_DATE_MASK;
} else {
regs[2] = RV3028_ALARM_DATE_AE_WD;
}
LOG_DBG("set alarm: mday = %d, hour = %d, min = %d, mask = 0x%04x",
timeptr->tm_mday, timeptr->tm_hour, timeptr->tm_min, mask);
/* Write registers RV3028_REG_ALARM_MINUTES through RV3028_REG_ALARM_WEEKDAY */
return rv3028_write_regs(dev, RV3028_REG_ALARM_MINUTES, ®s, sizeof(regs));
}
static int rv3028_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
uint8_t regs[3];
int err;
if (id != 0U) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
/* Read registers RV3028_REG_ALARM_MINUTES through RV3028_REG_ALARM_WEEKDAY */
err = rv3028_read_regs(dev, RV3028_REG_ALARM_MINUTES, ®s, sizeof(regs));
if (err) {
return err;
}
memset(timeptr, 0U, sizeof(*timeptr));
*mask = 0U;
if ((regs[0] & RV3028_ALARM_MINUTES_AE_M) == 0) {
timeptr->tm_min = bcd2bin(regs[0] & RV3028_ALARM_MINUTES_MASK);
*mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if ((regs[1] & RV3028_ALARM_HOURS_AE_H) == 0) {
timeptr->tm_hour = bcd2bin(regs[1] & RV3028_ALARM_HOURS_24H_MASK);
*mask |= RTC_ALARM_TIME_MASK_HOUR;
}
if ((regs[2] & RV3028_ALARM_DATE_AE_WD) == 0) {
timeptr->tm_mday = bcd2bin(regs[2] & RV3028_ALARM_DATE_MASK);
*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
LOG_DBG("get alarm: mday = %d, hour = %d, min = %d, mask = 0x%04x",
timeptr->tm_mday, timeptr->tm_hour, timeptr->tm_min, *mask);
return 0;
}
static int rv3028_alarm_is_pending(const struct device *dev, uint16_t id)
{
uint8_t status;
int err;
if (id != 0U) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
rv3028_lock_sem(dev);
err = rv3028_read_reg8(dev, RV3028_REG_STATUS, &status);
if (err) {
goto unlock;
}
if (status & RV3028_STATUS_AF) {
/* Clear alarm flag */
status &= ~(RV3028_STATUS_AF);
err = rv3028_write_reg8(dev, RV3028_REG_STATUS, status);
if (err) {
goto unlock;
}
/* Alarm pending */
err = 1;
}
unlock:
rv3028_unlock_sem(dev);
return err;
}
static int rv3028_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
#ifndef RV3028_INT_GPIOS_IN_USE
ARG_UNUSED(dev);
ARG_UNUSED(id);
ARG_UNUSED(callback);
ARG_UNUSED(user_data);
return -ENOTSUP;
#else
const struct rv3028_config *config = dev->config;
struct rv3028_data *data = dev->data;
int err = 0;
if (config->gpio_int.port == NULL) {
return -ENOTSUP;
}
if (id != 0U) {
LOG_ERR("invalid alarm ID %d", id);
return -EINVAL;
}
rv3028_lock_sem(dev);
data->alarm_callback = callback;
data->alarm_user_data = user_data;
err = rv3028_update_reg8(dev, RV3028_REG_CONTROL2, RV3028_CONTROL2_AIE,
callback != NULL ? RV3028_CONTROL2_AIE : 0);
if (err) {
goto unlock;
}
unlock:
rv3028_unlock_sem(dev);
/* Alarm flag may already be set */
k_work_submit(&data->work);
return err;
#endif /* RV3028_INT_GPIOS_IN_USE */
}
#endif /* CONFIG_RTC_ALARM */
#if RV3028_INT_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE)
static int rv3028_update_set_callback(const struct device *dev, rtc_update_callback callback,
void *user_data)
{
const struct rv3028_config *config = dev->config;
struct rv3028_data *data = dev->data;
int err;
if (config->gpio_int.port == NULL) {
return -ENOTSUP;
}
rv3028_lock_sem(dev);
data->update_callback = callback;
data->update_user_data = user_data;
err = rv3028_update_reg8(dev, RV3028_REG_CONTROL2, RV3028_CONTROL2_UIE,
callback != NULL ? RV3028_CONTROL2_UIE : 0);
if (err) {
goto unlock;
}
unlock:
rv3028_unlock_sem(dev);
/* Seconds flag may already be set */
k_work_submit(&data->work);
return err;
}
#endif /* RV3028_INT_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE) */
static int rv3028_init(const struct device *dev)
{
const struct rv3028_config *config = dev->config;
struct rv3028_data *data = dev->data;
uint8_t regs[3];
uint8_t val;
int err;
k_sem_init(&data->lock, 1, 1);
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C bus not ready");
return -ENODEV;
}
err = rv3028_read_reg8(dev, RV3028_REG_ID, &val);
if (err) {
return -ENODEV;
}
LOG_DBG("HID: 0x%02x, VID: 0x%02x", (val & 0xF0) >> 0x04, val & 0x0F);
#if RV3028_INT_GPIOS_IN_USE
if (config->gpio_int.port != NULL) {
if (!gpio_is_ready_dt(&config->gpio_int)) {
LOG_ERR("GPIO not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
if (err) {
LOG_ERR("failed to configure GPIO (err %d)", err);
return -ENODEV;
}
err = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
if (err) {
LOG_ERR("failed to enable GPIO interrupt (err %d)", err);
return err;
}
gpio_init_callback(&data->int_callback, rv3028_int_handler,
BIT(config->gpio_int.pin));
err = gpio_add_callback_dt(&config->gpio_int, &data->int_callback);
if (err) {
LOG_ERR("failed to add GPIO callback (err %d)", err);
return -ENODEV;
}
data->dev = dev;
data->work.handler = rv3028_work_cb;
}
#endif /* RV3028_INT_GPIOS_IN_USE */
err = rv3028_read_reg8(dev, RV3028_REG_STATUS, &val);
if (err) {
return -ENODEV;
}
if (val & RV3028_STATUS_AF) {
LOG_WRN("an alarm may have been missed");
}
/* Refresh the settings in the RAM with the settings from the EEPROM */
err = rv3028_enter_eerd(dev);
if (err) {
return -ENODEV;
}
err = rv3028_refresh(dev);
if (err) {
return -ENODEV;
}
/* Configure the CLKOUT register */
val = FIELD_PREP(RV3028_CLKOUT_FD, config->cof) |
(config->cof != RV3028_CLKOUT_FD_LOW ? RV3028_CLKOUT_CLKOE : 0);
err = rv3028_update_cfg(dev,
RV3028_REG_CLKOUT,
RV3028_CLKOUT_FD | RV3028_CLKOUT_CLKOE,
val);
if (err) {
return -ENODEV;
}
err = rv3028_update_cfg(dev,
RV3028_REG_BACKUP,
RV3028_BACKUP_TCE | RV3028_BACKUP_TCR | RV3028_BACKUP_BSM,
config->backup);
if (err) {
return -ENODEV;
}
err = rv3028_update_reg8(dev, RV3028_REG_CONTROL1, RV3028_CONTROL1_WADA,
RV3028_CONTROL1_WADA);
if (err) {
return -ENODEV;
}
/* Disable the alarms */
err = rv3028_update_reg8(dev,
RV3028_REG_CONTROL2,
RV3028_CONTROL2_AIE | RV3028_CONTROL2_UIE,
0);
if (err) {
return -ENODEV;
}
err = rv3028_read_regs(dev, RV3028_REG_ALARM_MINUTES, regs, sizeof(regs));
if (err) {
return -ENODEV;
}
regs[0] |= RV3028_ALARM_MINUTES_AE_M;
regs[1] |= RV3028_ALARM_HOURS_AE_H;
regs[2] |= RV3028_ALARM_DATE_AE_WD;
err = rv3028_write_regs(dev, RV3028_REG_ALARM_MINUTES, regs, sizeof(regs));
if (err) {
return -ENODEV;
}
return 0;
}
static const struct rtc_driver_api rv3028_driver_api = {
.set_time = rv3028_set_time,
.get_time = rv3028_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rv3028_alarm_get_supported_fields,
.alarm_set_time = rv3028_alarm_set_time,
.alarm_get_time = rv3028_alarm_get_time,
.alarm_is_pending = rv3028_alarm_is_pending,
.alarm_set_callback = rv3028_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#if RV3028_INT_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE)
.update_set_callback = rv3028_update_set_callback,
#endif /* RV3028_INT_GPIOS_IN_USE && defined(CONFIG_RTC_UPDATE) */
};
#define RV3028_BSM_FROM_DT_INST(inst) \
UTIL_CAT(RV3028_BSM_, DT_INST_STRING_UPPER_TOKEN(inst, backup_switch_mode))
#define RV3028_BACKUP_FROM_DT_INST(inst) \
((FIELD_PREP(RV3028_BACKUP_BSM, RV3028_BSM_FROM_DT_INST(inst))) | \
(FIELD_PREP(RV3028_BACKUP_TCR, DT_INST_ENUM_IDX_OR(inst, trickle_resistor_ohms, 0))) | \
(DT_INST_NODE_HAS_PROP(inst, trickle_resistor_ohms) ? RV3028_BACKUP_TCE : 0))
#define RV3028_INIT(inst) \
static const struct rv3028_config rv3028_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.cof = DT_INST_ENUM_IDX_OR(inst, clkout_frequency, RV3028_CLKOUT_FD_LOW), \
.backup = RV3028_BACKUP_FROM_DT_INST(inst), \
IF_ENABLED(RV3028_INT_GPIOS_IN_USE, \
(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0})))}; \
\
static struct rv3028_data rv3028_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &rv3028_init, NULL, &rv3028_data_##inst, \
&rv3028_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
&rv3028_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RV3028_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_rv3028.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,472 |
```c
/*
*
*/
#include <zephyr/drivers/rtc.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_rtc_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, set_time));
K_OOPS(K_SYSCALL_MEMORY_READ(timeptr, sizeof(struct rtc_time)));
return z_impl_rtc_set_time(dev, timeptr);
}
#include <zephyr/syscalls/rtc_set_time_mrsh.c>
static inline int z_vrfy_rtc_get_time(const struct device *dev, struct rtc_time *timeptr)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, get_time));
K_OOPS(K_SYSCALL_MEMORY_WRITE(timeptr, sizeof(struct rtc_time)));
return z_impl_rtc_get_time(dev, timeptr);
}
#include <zephyr/syscalls/rtc_get_time_mrsh.c>
#ifdef CONFIG_RTC_ALARM
static inline int z_vrfy_rtc_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, alarm_get_supported_fields));
K_OOPS(K_SYSCALL_MEMORY_WRITE(mask, sizeof(uint16_t)));
return z_impl_rtc_alarm_get_supported_fields(dev, id, mask);
}
#include <zephyr/syscalls/rtc_alarm_get_supported_fields_mrsh.c>
static inline int z_vrfy_rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, alarm_set_time));
K_OOPS(K_SYSCALL_MEMORY_READ(timeptr, sizeof(struct rtc_time)));
return z_impl_rtc_alarm_set_time(dev, id, mask, timeptr);
}
#include <zephyr/syscalls/rtc_alarm_set_time_mrsh.c>
static inline int z_vrfy_rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, alarm_get_time));
K_OOPS(K_SYSCALL_MEMORY_WRITE(mask, sizeof(uint16_t)));
K_OOPS(K_SYSCALL_MEMORY_WRITE(timeptr, sizeof(struct rtc_time)));
return z_impl_rtc_alarm_get_time(dev, id, mask, timeptr);
}
#include <zephyr/syscalls/rtc_alarm_get_time_mrsh.c>
static inline int z_vrfy_rtc_alarm_is_pending(const struct device *dev, uint16_t id)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, alarm_is_pending));
return z_impl_rtc_alarm_is_pending(dev, id);
}
#include <zephyr/syscalls/rtc_alarm_is_pending_mrsh.c>
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_CALIBRATION
static inline int z_vrfy_rtc_set_calibration(const struct device *dev, int32_t calibration)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, set_calibration));
return z_impl_rtc_set_calibration(dev, calibration);
}
#include <zephyr/syscalls/rtc_set_calibration_mrsh.c>
static inline int z_vrfy_rtc_get_calibration(const struct device *dev, int32_t *calibration)
{
K_OOPS(K_SYSCALL_DRIVER_RTC(dev, get_calibration));
K_OOPS(K_SYSCALL_MEMORY_WRITE(calibration, sizeof(int32_t)));
return z_impl_rtc_get_calibration(dev, calibration);
}
#include <zephyr/syscalls/rtc_get_calibration_mrsh.c>
#endif /* CONFIG_RTC_CALIBRATION */
``` | /content/code_sandbox/drivers/rtc/rtc_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 741 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_rtc
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include "rtc_utils.h"
LOG_MODULE_REGISTER(rtc_numaker, CONFIG_RTC_LOG_LEVEL);
/* RTC support 2000 ~ 2099 */
#define NVT_RTC_YEAR_MIN 2000U
#define NVT_RTC_YEAR_MAX 2099U
/* struct tm start time: 1st, Jan, 1900 */
#define TM_YEAR_REF 1900U
#define NVT_TIME_SCALE RTC_CLOCK_24
#define NVT_ALARM_MSK 0x3fU
#define NVT_ALARM_UNIT_MSK 0x03U
struct rtc_numaker_config {
RTC_T *rtc_base;
uint32_t clk_modidx;
const struct device *clk_dev;
uint32_t oscillator;
};
struct rtc_numaker_data {
struct k_spinlock lock;
#ifdef CONFIG_RTC_ALARM
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
bool alarm_pending;
#endif /* CONFIG_RTC_ALARM */
};
struct rtc_numaker_time {
uint32_t year; /* Year value */
uint32_t month; /* Month value */
uint32_t day; /* Day value */
uint32_t day_of_week; /* Day of week value */
uint32_t hour; /* Hour value */
uint32_t minute; /* Minute value */
uint32_t second; /* Second value */
uint32_t time_scale; /* 12-Hour, 24-Hour */
uint32_t am_pm; /* Only Time Scale select 12-hr used */
};
static int rtc_numaker_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_numaker_time curr_time;
struct rtc_numaker_data *data = dev->data;
uint32_t real_year = timeptr->tm_year + TM_YEAR_REF;
#ifdef CONFIG_RTC_ALARM
const struct rtc_numaker_config *config = dev->config;
RTC_T *rtc_base = config->rtc_base;
#endif
if (real_year < NVT_RTC_YEAR_MIN || real_year > NVT_RTC_YEAR_MAX) {
/* RTC can't support years out of 2000 ~ 2099 */
return -EINVAL;
}
if (timeptr->tm_wday == -1) {
return -EINVAL;
}
curr_time.year = real_year;
curr_time.month = timeptr->tm_mon + 1;
curr_time.day = timeptr->tm_mday;
curr_time.hour = timeptr->tm_hour;
curr_time.minute = timeptr->tm_min;
curr_time.second = timeptr->tm_sec;
curr_time.day_of_week = timeptr->tm_wday;
curr_time.time_scale = NVT_TIME_SCALE;
k_spinlock_key_t key = k_spin_lock(&data->lock);
RTC_SetDateAndTime((S_RTC_TIME_DATA_T *)&curr_time);
#ifdef CONFIG_RTC_ALARM
/* Restore RTC alarm mask */
rtc_base->CAMSK = rtc_base->SPR[1];
rtc_base->TAMSK = rtc_base->SPR[2];
#endif
k_spin_unlock(&data->lock, key);
return 0;
}
static int rtc_numaker_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_numaker_data *data = dev->data;
struct rtc_numaker_time curr_time;
curr_time.time_scale = NVT_TIME_SCALE;
k_spinlock_key_t key = k_spin_lock(&data->lock);
RTC_GetDateAndTime((S_RTC_TIME_DATA_T *)&curr_time);
k_spin_unlock(&data->lock, key);
timeptr->tm_year = curr_time.year - TM_YEAR_REF;
timeptr->tm_mon = curr_time.month - 1;
timeptr->tm_mday = curr_time.day;
timeptr->tm_wday = curr_time.day_of_week;
timeptr->tm_hour = curr_time.hour;
timeptr->tm_min = curr_time.minute;
timeptr->tm_sec = curr_time.second;
timeptr->tm_nsec = 0;
/* unknown values */
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
return 0;
}
static void rtc_numaker_isr(const struct device *dev)
{
const struct rtc_numaker_config *config = dev->config;
RTC_T *rtc_base = config->rtc_base;
uint32_t int_status;
#ifdef CONFIG_RTC_ALARM
struct rtc_numaker_data *data = dev->data;
#endif
int_status = rtc_base->INTSTS;
if (int_status & RTC_INTSTS_TICKIF_Msk) {
/* Clear RTC Tick interrupt flag */
rtc_base->INTSTS = RTC_INTSTS_TICKIF_Msk;
}
#ifdef CONFIG_RTC_ALARM
if (int_status & RTC_INTSTS_ALMIF_Msk) {
rtc_alarm_callback callback;
void *user_data;
/* Clear RTC Alarm interrupt flag */
rtc_base->INTSTS = RTC_INTSTS_ALMIF_Msk;
rtc_base->CAMSK = 0x00;
rtc_base->TAMSK = 0x00;
callback = data->alarm_callback;
user_data = data->alarm_user_data;
data->alarm_pending = callback ? false : true;
if (callback != NULL) {
callback(dev, 0, user_data);
}
}
#endif /* CONFIG_RTC_ALARM */
}
#ifdef CONFIG_RTC_ALARM
static int rtc_numaker_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
ARG_UNUSED(dev);
ARG_UNUSED(id);
*mask = RTC_ALARM_TIME_MASK_SECOND
| RTC_ALARM_TIME_MASK_MINUTE
| RTC_ALARM_TIME_MASK_HOUR
| RTC_ALARM_TIME_MASK_MONTHDAY
| RTC_ALARM_TIME_MASK_MONTH
| RTC_ALARM_TIME_MASK_YEAR;
return 0;
}
static int rtc_numaker_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
struct rtc_numaker_data *data = dev->data;
const struct rtc_numaker_config *config = dev->config;
RTC_T *rtc_base = config->rtc_base;
uint16_t mask_capable;
struct rtc_numaker_time alarm_time;
rtc_numaker_alarm_get_supported_fields(dev, 0, &mask_capable);
if ((id != 0)) {
return -EINVAL;
}
if ((mask != 0) && (timeptr == NULL)) {
return -EINVAL;
}
if (mask & ~mask_capable) {
return -EINVAL;
}
if (rtc_utils_validate_rtc_time(timeptr, mask) == false) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
irq_disable(DT_INST_IRQN(0));
if ((mask == 0) || (timeptr == NULL)) {
/* Disable the alarm */
rtc_base->SPR[0] = mask;
rtc_base->SPR[1] = 0x00;
rtc_base->SPR[2] = 0x00;
irq_enable(DT_INST_IRQN(0));
k_spin_unlock(&data->lock, key);
rtc_base->CAMSK = rtc_base->SPR[1];
rtc_base->TAMSK = rtc_base->SPR[2];
/* Disable RTC Alarm Interrupt */
RTC_DisableInt(RTC_INTEN_ALMIEN_Msk);
return 0;
}
alarm_time.time_scale = NVT_TIME_SCALE;
RTC_GetDateAndTime((S_RTC_TIME_DATA_T *)&alarm_time);
/* Reset RTC alarm mask of camsk & tamsk */
uint32_t camsk = NVT_ALARM_MSK;
uint32_t tamsk = NVT_ALARM_MSK;
/* Set H/W care to match bits */
if (mask & RTC_ALARM_TIME_MASK_YEAR) {
alarm_time.year = timeptr->tm_year + TM_YEAR_REF;
camsk &= ~(NVT_ALARM_UNIT_MSK << RTC_CAMSK_MYEAR_Pos);
}
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
alarm_time.month = timeptr->tm_mon + 1;
camsk &= ~(NVT_ALARM_UNIT_MSK << RTC_CAMSK_MMON_Pos);
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
alarm_time.day = timeptr->tm_mday;
camsk &= ~(NVT_ALARM_UNIT_MSK << RTC_CAMSK_MDAY_Pos);
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
alarm_time.hour = timeptr->tm_hour;
tamsk &= ~(NVT_ALARM_UNIT_MSK << RTC_TAMSK_MHR_Pos);
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
alarm_time.minute = timeptr->tm_min;
tamsk &= ~(NVT_ALARM_UNIT_MSK << RTC_TAMSK_MMIN_Pos);
}
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
alarm_time.second = timeptr->tm_sec;
tamsk &= ~(NVT_ALARM_UNIT_MSK << RTC_TAMSK_MSEC_Pos);
}
/* Disable RTC Alarm Interrupt */
RTC_DisableInt(RTC_INTEN_ALMIEN_Msk);
/* Set the alarm time */
RTC_SetAlarmDateAndTime((S_RTC_TIME_DATA_T *)&alarm_time);
/* Clear RTC alarm interrupt flag */
RTC_CLEAR_ALARM_INT_FLAG();
rtc_base->SPR[0] = mask;
rtc_base->SPR[1] = camsk;
rtc_base->SPR[2] = tamsk;
rtc_base->CAMSK = rtc_base->SPR[1];
rtc_base->TAMSK = rtc_base->SPR[2];
k_spin_unlock(&data->lock, key);
irq_enable(DT_INST_IRQN(0));
/* Enable RTC Alarm Interrupt */
RTC_EnableInt(RTC_INTEN_ALMIEN_Msk);
return 0;
}
static int rtc_numaker_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_numaker_data *data = dev->data;
const struct rtc_numaker_config *config = dev->config;
RTC_T *rtc_base = config->rtc_base;
struct rtc_numaker_time alarm_time;
if ((id != 0) || (mask == NULL) || (timeptr == NULL)) {
return -EINVAL;
}
alarm_time.time_scale = NVT_TIME_SCALE;
K_SPINLOCK(&data->lock) {
RTC_GetAlarmDateAndTime((S_RTC_TIME_DATA_T *)&alarm_time);
}
*mask = rtc_base->SPR[0];
if (*mask & RTC_ALARM_TIME_MASK_YEAR) {
timeptr->tm_year = alarm_time.year - TM_YEAR_REF;
}
if (*mask & RTC_ALARM_TIME_MASK_MONTH) {
timeptr->tm_mon = alarm_time.month - 1;
}
if (*mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
timeptr->tm_mday = alarm_time.day;
}
if (*mask & RTC_ALARM_TIME_MASK_HOUR) {
timeptr->tm_hour = alarm_time.hour;
}
if (*mask & RTC_ALARM_TIME_MASK_MINUTE) {
timeptr->tm_min = alarm_time.minute;
}
if (*mask & RTC_ALARM_TIME_MASK_SECOND) {
timeptr->tm_sec = alarm_time.second;
}
return 0;
}
static int rtc_numaker_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_numaker_data *data = dev->data;
int ret;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
ret = data->alarm_pending ? 1 : 0;
data->alarm_pending = false;
}
return ret;
}
static int rtc_numaker_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_numaker_data *data = dev->data;
if (id != 0) {
return -EINVAL;
}
K_SPINLOCK(&data->lock) {
irq_disable(DT_INST_IRQN(0));
data->alarm_callback = callback;
data->alarm_user_data = user_data;
if ((callback == NULL) && (user_data == NULL)) {
/* Disable RTC Alarm Interrupt */
RTC_DisableInt(RTC_INTEN_ALMIEN_Msk);
}
irq_enable(DT_INST_IRQN(0));
}
return 0;
}
#endif /* CONFIG_RTC_ALARM */
static const struct rtc_driver_api rtc_numaker_driver_api = {
.set_time = rtc_numaker_set_time,
.get_time = rtc_numaker_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rtc_numaker_alarm_get_supported_fields,
.alarm_set_time = rtc_numaker_alarm_set_time,
.alarm_get_time = rtc_numaker_alarm_get_time,
.alarm_is_pending = rtc_numaker_alarm_is_pending,
.alarm_set_callback = rtc_numaker_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
};
static int rtc_numaker_init(const struct device *dev)
{
const struct rtc_numaker_config *cfg = dev->config;
struct numaker_scc_subsys scc_subsys;
RTC_T *rtc_base = cfg->rtc_base;
int err;
/* CLK controller */
memset(&scc_subsys, 0x00, sizeof(scc_subsys));
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
scc_subsys.pcc.clk_modidx = cfg->clk_modidx;
SYS_UnlockReg();
/* CLK_EnableModuleClock */
err = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys);
if (err != 0) {
goto done;
}
RTC_SetClockSource(cfg->oscillator);
/* Enable spare registers */
rtc_base->SPRCTL = RTC_SPRCTL_SPRRWEN_Msk;
irq_disable(DT_INST_IRQN(0));
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rtc_numaker_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
err = RTC_Open(0);
done:
SYS_LockReg();
return err;
}
static struct rtc_numaker_data rtc_data;
/* Set config based on DTS */
static const struct rtc_numaker_config rtc_config = {
.rtc_base = (RTC_T *)DT_INST_REG_ADDR(0),
.clk_modidx = DT_INST_CLOCKS_CELL(0, clock_module_index),
.clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(0))),
.oscillator = DT_ENUM_IDX(DT_NODELABEL(rtc), oscillator),
};
DEVICE_DT_INST_DEFINE(0, &rtc_numaker_init, NULL, &rtc_data, &rtc_config, PRE_KERNEL_1,
CONFIG_RTC_INIT_PRIORITY, &rtc_numaker_driver_api);
``` | /content/code_sandbox/drivers/rtc/rtc_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,294 |
```unknown
config RTC_EMUL
bool "Emulated RTC driver"
default y
depends on DT_HAS_ZEPHYR_RTC_EMUL_ENABLED
help
Enable emulated Real-Time Clock (RTC) driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.emul | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
# NXP PCF8523 RTC
config RTC_PCF8563
bool "NXP PCF8563 RTC driver"
default y
depends on DT_HAS_NXP_PCF8563_ENABLED
select I2C
help
Enable the NXP PCF8563 RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.pcf8563 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_rtc_emul
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/rtc.h>
#include "rtc_utils.h"
struct rtc_emul_data;
struct rtc_emul_work_delayable {
struct k_work_delayable dwork;
const struct device *dev;
};
struct rtc_emul_alarm {
struct rtc_time datetime;
rtc_alarm_callback callback;
void *user_data;
uint16_t mask;
bool pending;
};
struct rtc_emul_data {
bool datetime_set;
struct rtc_time datetime;
struct k_spinlock lock;
struct rtc_emul_work_delayable dwork;
#ifdef CONFIG_RTC_ALARM
struct rtc_emul_alarm *alarms;
uint16_t alarms_count;
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
rtc_update_callback update_callback;
void *update_callback_user_data;
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
int32_t calibration;
#endif /* CONFIG_RTC_CALIBRATION */
};
static const uint8_t rtc_emul_days_in_month[12] = {
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
static const uint8_t rtc_emul_days_in_month_with_leap[12] = {
31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
static bool rtc_emul_is_leap_year(struct rtc_time *datetime)
{
if ((datetime->tm_year % 400 == 0) ||
(((datetime->tm_year % 100) > 0) && ((datetime->tm_year % 4) == 0))) {
return true;
}
return false;
}
static int rtc_emul_get_days_in_month(struct rtc_time *datetime)
{
const uint8_t *dim = (rtc_emul_is_leap_year(datetime) == true) ?
(rtc_emul_days_in_month_with_leap) :
(rtc_emul_days_in_month);
return dim[datetime->tm_mon];
}
static void rtc_emul_increment_tm(struct rtc_time *datetime)
{
/* Increment second */
datetime->tm_sec++;
/* Validate second limit */
if (datetime->tm_sec < 60) {
return;
}
datetime->tm_sec = 0;
/* Increment minute */
datetime->tm_min++;
/* Validate minute limit */
if (datetime->tm_min < 60) {
return;
}
datetime->tm_min = 0;
/* Increment hour */
datetime->tm_hour++;
/* Validate hour limit */
if (datetime->tm_hour < 24) {
return;
}
datetime->tm_hour = 0;
/* Increment day */
datetime->tm_wday++;
datetime->tm_mday++;
datetime->tm_yday++;
/* Limit week day */
if (datetime->tm_wday > 6) {
datetime->tm_wday = 0;
}
/* Validate month limit */
if (datetime->tm_mday <= rtc_emul_get_days_in_month(datetime)) {
return;
}
datetime->tm_mday = 1;
/* Increment month */
datetime->tm_mon++;
/* Validate month limit */
if (datetime->tm_mon < 12) {
return;
}
/* Increment year */
datetime->tm_mon = 0;
datetime->tm_yday = 0;
datetime->tm_year++;
}
#ifdef CONFIG_RTC_ALARM
static void rtc_emul_test_alarms(const struct device *dev)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
struct rtc_emul_alarm *alarm;
for (uint16_t i = 0; i < data->alarms_count; i++) {
alarm = &data->alarms[i];
if (alarm->mask == 0) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_SECOND) &&
(alarm->datetime.tm_sec != data->datetime.tm_sec)) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_MINUTE) &&
(alarm->datetime.tm_min != data->datetime.tm_min)) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_HOUR) &&
(alarm->datetime.tm_hour != data->datetime.tm_hour)) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_MONTHDAY) &&
(alarm->datetime.tm_mday != data->datetime.tm_mday)) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_MONTH) &&
(alarm->datetime.tm_mon != data->datetime.tm_mon)) {
continue;
}
if ((alarm->mask & RTC_ALARM_TIME_MASK_WEEKDAY) &&
(alarm->datetime.tm_wday != data->datetime.tm_wday)) {
continue;
}
if (alarm->callback == NULL) {
alarm->pending = true;
continue;
}
alarm->callback(dev, i, alarm->user_data);
alarm->pending = false;
}
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
static void rtc_emul_invoke_update_callback(const struct device *dev)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
if (data->update_callback == NULL) {
return;
}
data->update_callback(dev, data->update_callback_user_data);
}
#endif /* CONFIG_RTC_UPDATE */
static void rtc_emul_update(struct k_work *work)
{
struct rtc_emul_work_delayable *work_delayable = (struct rtc_emul_work_delayable *)work;
const struct device *dev = work_delayable->dev;
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
k_work_schedule(&work_delayable->dwork, K_MSEC(1000));
K_SPINLOCK(&data->lock) {
rtc_emul_increment_tm(&data->datetime);
#ifdef CONFIG_RTC_ALARM
rtc_emul_test_alarms(dev);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
rtc_emul_invoke_update_callback(dev);
#endif /* CONFIG_RTC_UPDATE */
}
}
static int rtc_emul_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
/* Validate arguments */
if (timeptr == NULL) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
data->datetime = *timeptr;
data->datetime.tm_isdst = -1;
data->datetime.tm_nsec = 0;
data->datetime_set = true;
}
return 0;
}
static int rtc_emul_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
int ret = 0;
/* Validate arguments */
if (timeptr == NULL) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
/* Validate RTC time is set */
if (data->datetime_set == false) {
ret = -ENODATA;
K_SPINLOCK_BREAK;
}
*timeptr = data->datetime;
}
return ret;
}
#ifdef CONFIG_RTC_ALARM
static int rtc_emul_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
if (data->alarms_count <= id) {
return -EINVAL;
}
*mask = (RTC_ALARM_TIME_MASK_SECOND
| RTC_ALARM_TIME_MASK_MINUTE
| RTC_ALARM_TIME_MASK_HOUR
| RTC_ALARM_TIME_MASK_MONTHDAY
| RTC_ALARM_TIME_MASK_MONTH
| RTC_ALARM_TIME_MASK_WEEKDAY);
return 0;
}
static int rtc_emul_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
if (data->alarms_count <= id) {
return -EINVAL;
}
if ((mask > 0) && (timeptr == NULL)) {
return -EINVAL;
}
if (mask > 0) {
if (rtc_utils_validate_rtc_time(timeptr, mask) == false) {
return -EINVAL;
}
}
K_SPINLOCK(&data->lock)
{
data->alarms[id].mask = mask;
if (timeptr != NULL) {
data->alarms[id].datetime = *timeptr;
}
}
return 0;
}
static int rtc_emul_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
if (data->alarms_count <= id) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
*timeptr = data->alarms[id].datetime;
*mask = data->alarms[id].mask;
}
return 0;
}
static int rtc_emul_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
int ret = 0;
if (data->alarms_count <= id) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
ret = (data->alarms[id].pending == true) ? 1 : 0;
data->alarms[id].pending = false;
}
return ret;
}
static int rtc_emul_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
if (data->alarms_count <= id) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
data->alarms[id].callback = callback;
data->alarms[id].user_data = user_data;
}
return 0;
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
static int rtc_emul_update_set_callback(const struct device *dev,
rtc_update_callback callback, void *user_data)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
K_SPINLOCK(&data->lock)
{
data->update_callback = callback;
data->update_callback_user_data = user_data;
}
return 0;
}
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
static int rtc_emul_set_calibration(const struct device *dev, int32_t calibration)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
K_SPINLOCK(&data->lock)
{
data->calibration = calibration;
}
return 0;
}
static int rtc_emul_get_calibration(const struct device *dev, int32_t *calibration)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
K_SPINLOCK(&data->lock)
{
*calibration = data->calibration;
}
return 0;
}
#endif /* CONFIG_RTC_CALIBRATION */
static const struct rtc_driver_api rtc_emul_driver_api = {
.set_time = rtc_emul_set_time,
.get_time = rtc_emul_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rtc_emul_alarm_get_supported_fields,
.alarm_set_time = rtc_emul_alarm_set_time,
.alarm_get_time = rtc_emul_alarm_get_time,
.alarm_is_pending = rtc_emul_alarm_is_pending,
.alarm_set_callback = rtc_emul_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
.update_set_callback = rtc_emul_update_set_callback,
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = rtc_emul_set_calibration,
.get_calibration = rtc_emul_get_calibration,
#endif /* CONFIG_RTC_CALIBRATION */
};
int rtc_emul_init(const struct device *dev)
{
struct rtc_emul_data *data = (struct rtc_emul_data *)dev->data;
data->dwork.dev = dev;
k_work_init_delayable(&data->dwork.dwork, rtc_emul_update);
k_work_schedule(&data->dwork.dwork, K_MSEC(1000));
return 0;
}
#ifdef CONFIG_RTC_ALARM
#define RTC_EMUL_DEVICE_DATA(id) \
static struct rtc_emul_alarm rtc_emul_alarms_##id[DT_INST_PROP(id, alarms_count)]; \
\
struct rtc_emul_data rtc_emul_data_##id = { \
.alarms = rtc_emul_alarms_##id, \
.alarms_count = ARRAY_SIZE(rtc_emul_alarms_##id), \
};
#else
#define RTC_EMUL_DEVICE_DATA(id) \
struct rtc_emul_data rtc_emul_data_##id;
#endif /* CONFIG_RTC_ALARM */
#define RTC_EMUL_DEVICE(id) \
RTC_EMUL_DEVICE_DATA(id) \
\
DEVICE_DT_INST_DEFINE(id, rtc_emul_init, NULL, &rtc_emul_data_##id, NULL, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, &rtc_emul_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RTC_EMUL_DEVICE);
``` | /content/code_sandbox/drivers/rtc/rtc_emul.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,958 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_
#define ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/drivers/rtc.h>
/**
* @brief Validate a datetime with a mask
*
* Ensure that any fields selected by mask contain a valid value.
*
* @param timeptr The time to set
* @param mask Mask of fields to validate
*
* @return true if the required fields are valid.
*/
bool rtc_utils_validate_rtc_time(const struct rtc_time *timeptr, uint16_t mask);
#endif /* ZEPHYR_DRIVERS_RTC_RTC_UTILS_H_ */
``` | /content/code_sandbox/drivers/rtc/rtc_utils.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 142 |
```unknown
# Author: Arunmani Alagarsamy <arunmani27100@gmail.com>
config RTC_DS1307
bool "MAXIM DS1307 RTC driver"
default y
depends on DT_HAS_MAXIM_DS1307_ENABLED
select I2C
help
Enable the MAXIM DS1307 RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.ds1307 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
# Author: Daniel Kampert <DanielKampert@Kampis-Elektroecke.de>
config RTC_RV8263
bool "Micro Crystal RV-8263-C8 RTC driver"
default y
depends on DT_HAS_MICROCRYSTAL_RV_8263_C8_ENABLED
select I2C
help
Micro Crystal RV-8263-C8 RTC driver.
``` | /content/code_sandbox/drivers/rtc/Kconfig.rv8263 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```c
/*
*
*/
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/drivers/rtc.h>
#include "rtc_utils.h"
bool rtc_utils_validate_rtc_time(const struct rtc_time *timeptr, uint16_t mask)
{
if ((mask & RTC_ALARM_TIME_MASK_SECOND) && (timeptr->tm_sec < 0 || timeptr->tm_sec > 59)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_MINUTE) && (timeptr->tm_min < 0 || timeptr->tm_min > 59)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_HOUR) && (timeptr->tm_hour < 0 || timeptr->tm_hour > 23)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_MONTH) && (timeptr->tm_mon < 0 || timeptr->tm_mon > 11)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) &&
(timeptr->tm_mday < 1 || timeptr->tm_mday > 31)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_YEAR) && (timeptr->tm_year < 0 || timeptr->tm_year > 199)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) &&
(timeptr->tm_wday < 0 || timeptr->tm_wday > 6)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_YEARDAY) &&
(timeptr->tm_yday < 0 || timeptr->tm_yday > 365)) {
return false;
}
if ((mask & RTC_ALARM_TIME_MASK_NSEC) &&
(timeptr->tm_nsec < 0 || timeptr->tm_nsec > 999999999)) {
return false;
}
return true;
}
``` | /content/code_sandbox/drivers/rtc/rtc_utils.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 407 |
```unknown
menuconfig RTC
bool "Real-Time Clock (RTC) drivers"
help
Enable RTC driver configuration.
if RTC
module = RTC
module-str = rtc
source "subsys/logging/Kconfig.template.log_config"
config RTC_INIT_PRIORITY
int "RTC init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
RTC device driver initialization priority.
config RTC_ALARM
bool "RTC driver alarm support"
help
This is an option which enables driver support for RTC alarms.
config RTC_UPDATE
bool "RTC driver update event callback support"
help
This is an option which enables driver support for the RTC
update event callback.
config RTC_CALIBRATION
bool "RTC driver clock calibration support"
help
This is an option which enables driver support for RTC clock
calibration.
config RTC_SHELL
bool "RTC Shell commands"
depends on SHELL
help
RTC Shell commands
source "drivers/rtc/Kconfig.am1805"
source "drivers/rtc/Kconfig.ambiq"
source "drivers/rtc/Kconfig.ds1307"
source "drivers/rtc/Kconfig.emul"
source "drivers/rtc/Kconfig.fake"
source "drivers/rtc/Kconfig.mc146818"
source "drivers/rtc/Kconfig.pcf8523"
source "drivers/rtc/Kconfig.pcf8563"
source "drivers/rtc/Kconfig.rpi_pico"
source "drivers/rtc/Kconfig.rv3028"
source "drivers/rtc/Kconfig.sam"
source "drivers/rtc/Kconfig.smartbond"
source "drivers/rtc/Kconfig.stm32"
source "drivers/rtc/Kconfig.numaker"
source "drivers/rtc/Kconfig.rv8263"
endif # RTC
``` | /content/code_sandbox/drivers/rtc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 355 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_
#define ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_
#ifdef CONFIG_RTC_ALARM
/* STM32 RTC alarms, A & B, LL masks are equal */
#define RTC_STM32_ALRM_MASK_ALL LL_RTC_ALMA_MASK_ALL
#define RTC_STM32_ALRM_MASK_SECONDS LL_RTC_ALMA_MASK_SECONDS
#define RTC_STM32_ALRM_MASK_MINUTES LL_RTC_ALMA_MASK_MINUTES
#define RTC_STM32_ALRM_MASK_HOURS LL_RTC_ALMA_MASK_HOURS
#define RTC_STM32_ALRM_MASK_DATEWEEKDAY LL_RTC_ALMA_MASK_DATEWEEKDAY
#define RTC_STM32_ALRM_DATEWEEKDAYSEL_WEEKDAY LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY
#define RTC_STM32_ALRM_DATEWEEKDAYSEL_DATE LL_RTC_ALMA_DATEWEEKDAYSEL_DATE
static inline void ll_func_exti_enable_rtc_alarm_it(uint32_t exti_line)
{
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
LL_C2_EXTI_EnableIT_0_31(exti_line);
LL_EXTI_EnableRisingTrig_0_31(exti_line);
#elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
/* in STM32U5 & STM32WBAX series, RTC Alarm event is not routed to EXTI */
#else
LL_EXTI_EnableIT_0_31(exti_line);
LL_EXTI_EnableRisingTrig_0_31(exti_line);
#endif /* CONFIG_SOC_SERIES_STM32H7X and CONFIG_CPU_CORTEX_M4 */
}
static inline void ll_func_exti_clear_rtc_alarm_flag(uint32_t exti_line)
{
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
LL_C2_EXTI_ClearFlag_0_31(exti_line);
#elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
/* in STM32U5 & STM32WBAX series, RTC Alarm event is not routed to EXTI */
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
LL_EXTI_ClearRisingFlag_0_31(exti_line);
#else
LL_EXTI_ClearFlag_0_31(exti_line);
#endif /* CONFIG_SOC_SERIES_STM32H7X and CONFIG_CPU_CORTEX_M4 */
}
#endif /* CONFIG_RTC_ALARM */
#endif /* ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_ */
``` | /content/code_sandbox/drivers/rtc/rtc_ll_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 564 |
```c
/*
*
* Author: Arunmani Alagarsamy <arunmani27100@gmail.com>
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#define DT_DRV_COMPAT maxim_ds1307
LOG_MODULE_REGISTER(ds1307, CONFIG_RTC_LOG_LEVEL);
/* DS1307 registers */
#define DS1307_REG_SECONDS 0x00
#define DS1307_REG_MINUTES 0x01
#define DS1307_REG_HOURS 0x02
#define DS1307_REG_DAY 0x03
#define DS1307_REG_DATE 0x04
#define DS1307_REG_MONTH 0x05
#define DS1307_REG_YEAR 0x06
#define DS1307_REG_CTRL 0x07
#define SECONDS_BITS GENMASK(6, 0)
#define MINUTES_BITS GENMASK(7, 0)
#define HOURS_BITS GENMASK(5, 0)
#define DATE_BITS GENMASK(5, 0)
#define MONTHS_BITS GENMASK(4, 0)
#define WEEKDAY_BITS GENMASK(2, 0)
#define YEAR_BITS GENMASK(7, 0)
#define VALIDATE_24HR BIT(6)
struct ds1307_config {
struct i2c_dt_spec i2c_bus;
};
struct ds1307_data {
struct k_spinlock lock;
};
static int ds1307_set_time(const struct device *dev, const struct rtc_time *tm)
{
int err;
uint8_t regs[7];
struct ds1307_data *data = dev->data;
const struct ds1307_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
LOG_DBG("set time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min,
tm->tm_sec);
regs[0] = bin2bcd(tm->tm_sec) & SECONDS_BITS;
regs[1] = bin2bcd(tm->tm_min);
regs[2] = bin2bcd(tm->tm_hour);
regs[3] = bin2bcd(tm->tm_wday);
regs[4] = bin2bcd(tm->tm_mday);
regs[5] = bin2bcd(tm->tm_mon);
regs[6] = bin2bcd((tm->tm_year % 100));
err = i2c_burst_write_dt(&config->i2c_bus, DS1307_REG_SECONDS, regs, sizeof(regs));
k_spin_unlock(&data->lock, key);
return err;
}
static int ds1307_get_time(const struct device *dev, struct rtc_time *timeptr)
{
int err;
uint8_t regs[7];
struct ds1307_data *data = dev->data;
const struct ds1307_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
err = i2c_burst_read_dt(&config->i2c_bus, DS1307_REG_SECONDS, regs, sizeof(regs));
if (err != 0) {
goto unlock;
}
timeptr->tm_sec = bcd2bin(regs[0] & SECONDS_BITS);
timeptr->tm_min = bcd2bin(regs[1] & MINUTES_BITS);
timeptr->tm_hour = bcd2bin(regs[2] & HOURS_BITS); /* 24hr mode */
timeptr->tm_wday = bcd2bin(regs[3] & WEEKDAY_BITS);
timeptr->tm_mday = bcd2bin(regs[4] & DATE_BITS);
timeptr->tm_mon = bcd2bin(regs[5] & MONTHS_BITS);
timeptr->tm_year = bcd2bin(regs[6] & YEAR_BITS);
timeptr->tm_year = timeptr->tm_year + 100;
/* Not used */
timeptr->tm_nsec = 0;
timeptr->tm_isdst = -1;
timeptr->tm_yday = -1;
/* Validate the chip in 24hr mode */
if (regs[2] & VALIDATE_24HR) {
err = -ENODATA;
goto unlock;
}
LOG_DBG("get time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
unlock:
k_spin_unlock(&data->lock, key);
return err;
}
static const struct rtc_driver_api ds1307_driver_api = {
.set_time = ds1307_set_time,
.get_time = ds1307_get_time,
};
static int ds1307_init(const struct device *dev)
{
int err;
const struct ds1307_config *config = dev->config;
if (!i2c_is_ready_dt(&config->i2c_bus)) {
LOG_ERR("I2C bus not ready");
return -ENODEV;
}
/* Disable squarewave output */
err = i2c_reg_write_byte_dt(&config->i2c_bus, DS1307_REG_CTRL, 0x00);
if (err < 0) {
LOG_ERR("Error: SQW:%d\n", err);
}
/* Make clock halt = 0 */
err = i2c_reg_write_byte_dt(&config->i2c_bus, DS1307_REG_SECONDS, 0x00);
if (err < 0) {
LOG_ERR("Error: Set clock halt bit:%d\n", err);
}
return 0;
}
#define DS1307_DEFINE(inst) \
static struct ds1307_data ds1307_data_##inst; \
static const struct ds1307_config ds1307_config_##inst = { \
.i2c_bus = I2C_DT_SPEC_INST_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, &ds1307_init, NULL, &ds1307_data_##inst, \
&ds1307_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
&ds1307_driver_api);
DT_INST_FOREACH_STATUS_OKAY(DS1307_DEFINE)
``` | /content/code_sandbox/drivers/rtc/rtc_ds1307.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,447 |
```unknown
# NXP PCF8523 RTC
config RTC_PCF8523
bool "NXP PCF8523 RTC driver"
default y
depends on DT_HAS_NXP_PCF8523_ENABLED
select I2C
help
Enable the NXP PCF8523 RTC driver.
if RTC_PCF8523
choice RTC_PCF8523_OFFSET_MODE
prompt "Offset mode"
default RTC_PCF8523_OFFSET_MODE_SLOW
depends on RTC_CALIBRATION
help
Offset register mode selection.
config RTC_PCF8523_OFFSET_MODE_SLOW
bool "Slow"
help
Offset correction is made once per two hours and then correction pulses are applied once
per minute until the programmed correction values have been implemented (MODE = 0).
config RTC_PCF8523_OFFSET_MODE_FAST
bool "Fast"
help
Offset correction is made once per minute and then correction pulses are applied once per
second up to a maximum of 60 pulses. When correction values greater than 60 pulses are
used, additional correction pulses are made in the 59th second (MODE = 1).
endchoice
if RTC_ALARM || RTC_UPDATE
config RTC_PCF8523_THREAD_STACK_SIZE
int "Stack size for the PCF8523 interrupt thread"
default 512
help
Size of the stack used for the thread handling interrupts and dispatching callbacks.
config RTC_PCF8523_THREAD_PRIO
int "Priority for the PCF8523 interrupt thread"
default 0
help
Priority level for the thread handling interrupts and dispatching callbacks.
endif # RTC_ALARM || RTC_UPDATE
endif # RTC_PCF8523
``` | /content/code_sandbox/drivers/rtc/Kconfig.pcf8523 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 349 |
```c
/*
*
* Author: Sri Surya <srisurya@linumiz.com>
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#define DT_DRV_COMPAT ambiq_am1805
LOG_MODULE_REGISTER(am1805, CONFIG_RTC_LOG_LEVEL);
#define AM1805_IDENTITY_CODE 0x69
/* AM1805 register address */
#define REG_HUNDREDS_ADDR 0x00
#define REG_SECONDS_ADDR 0x01
#define REG_MINUTES_ADDR 0x02
#define REG_HOURS_ADDR 0x03
#define REG_MDAY_ADDR 0x04
#define REG_MONTH_ADDR 0x05
#define REG_YEAR_ADDR 0x06
#define REG_WDAY_ADDR 0x07
#define REG_ALM_HUNDREDS_ADDR 0x08
#define REG_ALM_SECONDS_ADDR 0x09
#define REG_ALM_MINUTES_ADDR 0x0A
#define REG_ALM_HOURS_ADDR 0x0B
#define REG_ALM_MDAY_ADDR 0x0C
#define REG_ALM_MONTH_ADDR 0x0D
#define REG_ALM_WDAY_ADDR 0x0E
#define REG_STATUS_ADDR 0x0F
#define REG_CONTROL1_ADDR 0x10
#define REG_CONTROL2_ADDR 0x11
#define REG_XT_CALIB_ADDR 0x14
#define REG_TIMER_CTRL_ADDR 0x18
#define REG_IRQ_MASK_ADDR 0x12
#define REG_WATCHDOG_ADDR 0x1B
#define REG_OSC_STATUS_ADDR 0x1D
/* AM1805 control bits */
#define SECONDS_BITS GENMASK(6, 0)
#define MINUTES_BITS GENMASK(6, 0)
#define HOURS_BITS GENMASK(5, 0)
#define DATE_BITS GENMASK(5, 0)
#define MONTHS_BITS GENMASK(4, 0)
#define WEEKDAY_BITS GENMASK(2, 0)
#define YEAR_BITS GENMASK(7, 0)
#define REG_CONTROL2_OUT2S_BITS GENMASK(4, 2)
#define REG_TIMER_CTRL_RPT_BITS GENMASK(4, 2)
#define REG_XT_CALIB_OFF_MASK GENMASK(6, 0)
#define REG_STATUS_ALM BIT(2)
#define REG_CONTROL1_STOP BIT(7)
#define REG_IRQ_MASK_AIE BIT(2)
#define REG_XT_CALIB_CMDX BIT(7)
#define TIMER_CTRL_ALM_OFF 0x00
#define TIMER_CTRL_ALM_DAY BIT(4)
#define TIMER_CTRL_ALM_YEAR BIT(2)
#define TIMER_CTRL_ALM_HR (BIT(2) | BIT(4))
#define TIMER_CTRL_ALM_SEC GENMASK(4, 2)
#define TIMER_CTRL_ALM_MIN GENMASK(4, 3)
#define TIMER_CTRL_ALM_WEEK GENMASK(3, 2)
#define REG_WATCHDOG_WDS BIT(7)
#define WRB_1_SECOND BIT(1)
#define WRB_4_SECONDS GENMASK(1, 0)
#define REG_OSC_STATUS_ACAL_0 0x00
#define REG_OSC_STATUS_ACAL_1 BIT(6)
#define REG_OSC_STATUS_ACAL_2 BIT(7)
#define REG_OSC_STATUS_ACAL_3 GENMASK(7, 6)
#define REG_OSC_STATUS_MASK BIT(1)
#define REG_STATUS_DEFAULT 0x00
#define AM1805_RTC_ALARM_TIME_MASK \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_WEEKDAY)
#ifdef CONFIG_RTC_ALARM
/* am1805-gpios property must be in the devicetree inorder to use the RTC_ALARM */
#if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(am1805_gpios)
#error "am1805-gpios" - property not available in devicetree.
#endif
#endif
struct am1805_config {
const struct i2c_dt_spec int_i2c;
#ifdef CONFIG_RTC_ALARM
struct gpio_dt_spec int_gpio;
#endif
};
struct am1805_data {
struct k_mutex lock;
#ifdef CONFIG_RTC_ALARM
rtc_alarm_callback alarm_user_callback;
void *alarm_user_data;
/* For gpio-interrupt */
struct gpio_callback am1805_callback;
struct k_thread am1805_thread;
struct k_sem int_sem;
K_KERNEL_STACK_MEMBER(am1805_stack, CONFIG_RTC_AM1805_THREAD_STACK_SIZE);
#endif
};
/* To set the timer registers */
static int am1805_set_time(const struct device *dev, const struct rtc_time *tm)
{
int err;
uint8_t regs[7];
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
k_mutex_lock(&data->lock, K_FOREVER);
/* To unlock Stop-bit */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_CONTROL1_ADDR,
REG_CONTROL1_STOP, REG_CONTROL1_STOP);
if (err != 0) {
goto unlock;
}
LOG_DBG("set time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min,
tm->tm_sec);
regs[0] = bin2bcd(tm->tm_sec) & SECONDS_BITS;
regs[1] = bin2bcd(tm->tm_min) & MINUTES_BITS;
regs[2] = bin2bcd(tm->tm_hour) & HOURS_BITS;
regs[3] = bin2bcd(tm->tm_mday) & DATE_BITS;
regs[4] = bin2bcd(tm->tm_mon) & MONTHS_BITS;
regs[5] = bin2bcd(tm->tm_year) & YEAR_BITS;
regs[6] = bin2bcd(tm->tm_wday) & WEEKDAY_BITS;
err = i2c_burst_write_dt(&config->int_i2c, REG_SECONDS_ADDR, regs, sizeof(regs));
if (err != 0) {
goto unlock;
}
/* To lock Stop-bit */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_CONTROL1_ADDR, REG_CONTROL1_STOP, 0);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
/* To get from the timer registers */
static int am1805_get_time(const struct device *dev, struct rtc_time *timeptr)
{
int err;
uint8_t ctl_reg;
uint8_t regs[7];
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
k_mutex_lock(&data->lock, K_FOREVER);
err = i2c_reg_read_byte_dt(&config->int_i2c, REG_CONTROL1_ADDR, &ctl_reg);
if (err != 0) {
goto unlock;
}
err = ctl_reg & REG_CONTROL1_STOP;
if (err != 0) {
LOG_WRN("No control to get time now!!");
goto unlock;
}
err = i2c_burst_read_dt(&config->int_i2c, REG_SECONDS_ADDR, regs, sizeof(regs));
if (err != 0) {
goto unlock;
}
timeptr->tm_sec = bcd2bin(regs[0] & SECONDS_BITS);
timeptr->tm_min = bcd2bin(regs[1] & MINUTES_BITS);
timeptr->tm_hour = bcd2bin(regs[2] & HOURS_BITS);
timeptr->tm_mday = bcd2bin(regs[3] & DATE_BITS);
timeptr->tm_mon = bcd2bin(regs[4] & MONTHS_BITS);
timeptr->tm_year = bcd2bin(regs[5] & YEAR_BITS);
timeptr->tm_wday = bcd2bin(regs[6] & WEEKDAY_BITS);
LOG_DBG("get time: year = %d, mon = %d, mday = %d, wday = %d, hour = %d, "
"min = %d, sec = %d",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
#ifdef CONFIG_RTC_CALIBRATION
/* To Calibrate the XT oscillator */
static int am1805_set_calibration(const struct device *dev, int32_t xt_clock_adj)
{
int err;
uint8_t xt_calib_value;
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
uint8_t reg = REG_OSC_STATUS_MASK;
if (xt_clock_adj < -320 || xt_clock_adj > 127) {
LOG_DBG("Cannot be calibrated adj = %d\n", xt_clock_adj);
return -EINVAL;
} else if (xt_clock_adj < -256) {
/* XTCAL=3 CMDX=1 OFFSETX=(adj+192)/2 */
reg |= REG_OSC_STATUS_ACAL_3;
xt_calib_value = ((uint8_t)(xt_clock_adj + 192) >> 1);
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
xt_calib_value |= REG_XT_CALIB_CMDX;
} else if (xt_clock_adj < -192) {
/* XTCAL=3 CMDX=0 OFFSETX=(adj+192) */
reg |= REG_OSC_STATUS_ACAL_3;
xt_calib_value = (uint8_t)(xt_clock_adj + 192);
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
} else if (xt_clock_adj < -128) {
/* XTCAL=2 CMDX=0 OFFSETX=(adj+128) */
reg |= REG_OSC_STATUS_ACAL_2;
xt_calib_value = (uint8_t)(xt_clock_adj + 128);
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
} else if (xt_clock_adj < -64) {
/* XTCAL=1 CMDX=0 OFFSETX=(adj+64) */
reg |= REG_OSC_STATUS_ACAL_1;
xt_calib_value = (uint8_t)(xt_clock_adj + 64);
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
} else if (xt_clock_adj < 64) {
/* XTCAL=0 CMDX=0 OFFSETX=(adj) */
reg |= REG_OSC_STATUS_ACAL_0;
xt_calib_value = (uint8_t)(xt_clock_adj);
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
} else if (xt_clock_adj < 128) {
/* XTCAL=0 CMDX=1 OFFSETX=(adj)/2 */
reg |= REG_OSC_STATUS_ACAL_0;
xt_calib_value = ((uint8_t)(xt_clock_adj >> 1));
xt_calib_value &= REG_XT_CALIB_OFF_MASK;
xt_calib_value |= REG_XT_CALIB_CMDX;
}
k_mutex_lock(&data->lock, K_FOREVER);
err = i2c_reg_write_byte_dt(&config->int_i2c, REG_OSC_STATUS_ADDR, reg);
if (err != 0) {
LOG_DBG("fail to set oscillator status register\n");
goto unlock;
}
/* Calibration XT Register */
reg = xt_calib_value;
err = i2c_reg_write_byte_dt(&config->int_i2c, REG_XT_CALIB_ADDR, reg);
if (err != 0) {
LOG_DBG("fail to set XT calibration register\n");
}
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int am1805_get_calibration(const struct device *dev, int32_t *calib)
{
int err;
bool cmdx;
uint8_t reg;
uint8_t xtcal;
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
k_mutex_lock(&data->lock, K_FOREVER);
err = i2c_reg_read_byte_dt(&config->int_i2c, REG_OSC_STATUS_ADDR, ®);
if (err != 0) {
goto unlock;
}
/* First 2-bits (from MSB) */
xtcal = reg >> 6;
err = i2c_reg_read_byte_dt(&config->int_i2c, REG_XT_CALIB_ADDR, ®);
if (err != 0) {
goto unlock;
}
*calib = reg;
/* First bit (from MSB) */
cmdx = reg & BIT(7);
/* Set or Clear the bit-7 based on bit-6, to achieve the given range (in datasheet) */
WRITE_BIT(reg, 7, (reg & BIT(6)));
WRITE_BIT(reg, 6, 0);
LOG_DBG("XTCAL = %d, CMDX = %d, OFFSETX = %d\n", xtcal, cmdx, (int8_t) reg);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
#endif
#ifdef CONFIG_RTC_ALARM
/* To get from the alarm registers */
static int am1805_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
int err;
uint8_t regs[6];
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
err = i2c_burst_read_dt(&config->int_i2c, REG_ALM_SECONDS_ADDR, regs, sizeof(regs));
if (err != 0) {
goto unlock;
}
timeptr->tm_sec = bcd2bin(regs[0] & SECONDS_BITS);
timeptr->tm_min = bcd2bin(regs[1] & MINUTES_BITS);
timeptr->tm_hour = bcd2bin(regs[2] & HOURS_BITS);
timeptr->tm_mday = bcd2bin(regs[3] & DATE_BITS);
timeptr->tm_mon = bcd2bin(regs[4] & MONTHS_BITS);
timeptr->tm_wday = bcd2bin(regs[5] & WEEKDAY_BITS);
*mask = (AM1805_RTC_ALARM_TIME_MASK);
LOG_DBG("get alarm: wday = %d, mon = %d, mday = %d, hour = %d, min = %d, sec = %d, "
"mask = 0x%04x", timeptr->tm_wday, timeptr->tm_mon, timeptr->tm_mday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec, *mask);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int am1805_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
int err;
uint8_t regs[6];
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
if ((mask & ~(AM1805_RTC_ALARM_TIME_MASK)) != 0U) {
LOG_ERR("unsupported alarm field mask 0x%04x", mask);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
/* Disable timer control registers before the initialization */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_TIMER_CTRL_ADDR,
REG_TIMER_CTRL_RPT_BITS, 0);
if (err != 0) {
goto unlock;
}
/* Clear the interrupt mask for alarm */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_IRQ_MASK_ADDR,
REG_IRQ_MASK_AIE, 0);
if (err != 0) {
goto unlock;
}
/* Clear the status bit */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_STATUS_ADDR,
REG_STATUS_ALM, 0);
if (err != 0) {
goto unlock;
}
/* When mask is 0 */
if (mask == 0) {
LOG_DBG("The alarm is disabled");
goto unlock;
}
regs[0] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS;
regs[1] = bin2bcd(timeptr->tm_min) & MINUTES_BITS;
regs[2] = bin2bcd(timeptr->tm_hour) & HOURS_BITS;
regs[3] = bin2bcd(timeptr->tm_mday) & DATE_BITS;
regs[4] = bin2bcd(timeptr->tm_mon) & MONTHS_BITS;
regs[5] = bin2bcd(timeptr->tm_wday) & WEEKDAY_BITS;
LOG_DBG("set alarm: second = %d, min = %d, hour = %d, mday = %d, month = %d,"
"wday = %d, mask = 0x%04x",
timeptr->tm_sec, timeptr->tm_min, timeptr->tm_hour, timeptr->tm_mday,
timeptr->tm_mon, timeptr->tm_wday, mask);
err = i2c_burst_write_dt(&config->int_i2c, REG_ALM_SECONDS_ADDR, regs, sizeof(regs));
if (err != 0) {
goto unlock;
}
/* Enable irq timer after the initialization */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_IRQ_MASK_ADDR,
REG_IRQ_MASK_AIE, REG_IRQ_MASK_AIE);
if (err != 0) {
goto unlock;
}
/* Enable timer after the initialization for the config of repetation */
err = i2c_reg_update_byte_dt(&config->int_i2c, REG_TIMER_CTRL_ADDR,
TIMER_CTRL_ALM_SEC, TIMER_CTRL_ALM_SEC);
unlock:
k_mutex_unlock(&data->lock);
return err;
}
static int am1805_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
{
ARG_UNUSED(dev);
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
*mask = AM1805_RTC_ALARM_TIME_MASK;
return 0;
}
static int am1805_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct am1805_data *data = dev->data;
const struct am1805_config *config = dev->config;
if (config->int_gpio.port == NULL) {
return -ENOTSUP;
}
if (id != 0U) {
LOG_ERR("invalid ID %d", id);
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
/* Passing the callback function and userdata filled by the user */
data->alarm_user_callback = callback;
data->alarm_user_data = user_data;
k_mutex_unlock(&data->lock);
return 0;
}
static void am1805_interrupt_thread(const struct device *dev)
{
struct am1805_data *data = dev->data;
while (1) {
k_sem_take(&data->int_sem, K_FOREVER);
if (data->alarm_user_callback == NULL) {
LOG_DBG("Interrupt received, But No Alarm-Callback Initilized!!\n");
continue;
}
data->alarm_user_callback(dev, 0, data->alarm_user_data);
}
}
static void am1805_gpio_callback_handler(const struct device *port, struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct am1805_data *data = CONTAINER_OF(cb, struct am1805_data, am1805_callback);
ARG_UNUSED(port);
ARG_UNUSED(pins);
k_sem_give(&data->int_sem);
}
#endif
static int am1805_init(const struct device *dev)
{
int err;
uint8_t reg;
const struct am1805_config *config = dev->config;
struct am1805_data *data = dev->data;
k_mutex_init(&data->lock);
if (!i2c_is_ready_dt(&config->int_i2c)) {
LOG_ERR("I2C bus not ready");
return -ENODEV;
}
err = i2c_reg_read_byte_dt(&config->int_i2c, REG_STATUS_ADDR, ®);
if (err != 0) {
LOG_ERR("failed to read the status register");
return -ENODEV;
}
#ifdef CONFIG_RTC_ALARM
k_tid_t tid;
k_sem_init(&data->int_sem, 0, INT_MAX);
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("GPIO not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (err != 0) {
LOG_ERR("failed to configure GPIO (err %d)", err);
return -ENODEV;
}
err = gpio_pin_interrupt_configure_dt(&config->int_gpio,
GPIO_INT_EDGE_TO_INACTIVE);
if (err != 0) {
LOG_ERR("failed to configure interrupt (err %d)", err);
return -ENODEV;
}
gpio_init_callback(&data->am1805_callback, am1805_gpio_callback_handler,
BIT(config->int_gpio.pin));
err = gpio_add_callback_dt(&config->int_gpio, &data->am1805_callback);
if (err != 0) {
LOG_ERR("failed to add GPIO callback (err %d)", err);
return -ENODEV;
}
tid = k_thread_create(&data->am1805_thread, data->am1805_stack,
K_THREAD_STACK_SIZEOF(data->am1805_stack),
(k_thread_entry_t)am1805_interrupt_thread, (void *)dev, NULL,
NULL, CONFIG_RTC_AM1805_THREAD_PRIO, 0, K_NO_WAIT);
k_thread_name_set(tid, dev->name);
#endif
return 0;
}
static const struct rtc_driver_api am1805_driver_api = {
.set_time = am1805_set_time,
.get_time = am1805_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = am1805_alarm_get_supported_fields,
.alarm_set_time = am1805_alarm_set_time,
.alarm_get_time = am1805_alarm_get_time,
.alarm_set_callback = am1805_alarm_set_callback,
#endif
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = am1805_set_calibration,
.get_calibration = am1805_get_calibration,
#endif
};
#define AM1805_INIT(inst) \
static const struct am1805_config am1805_config_##inst = { \
.int_i2c = I2C_DT_SPEC_INST_GET(inst), \
IF_ENABLED(CONFIG_RTC_ALARM, \
(.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, am1805_gpios, {0})))}; \
\
static struct am1805_data am1805_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &am1805_init, NULL, &am1805_data_##inst, \
&am1805_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
&am1805_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AM1805_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_am1805.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,275 |
```c
* Author: Daniel Kampert <DanielKampert@kampis-Elektroecke.de>
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include "rtc_utils.h"
#define RV8263C8_REGISTER_CONTROL_1 0x00
#define RV8263C8_REGISTER_CONTROL_2 0x01
#define RV8263C8_REGISTER_OFFSET 0x02
#define RV8263C8_REGISTER_RAM 0x03
#define RV8263C8_REGISTER_SECONDS 0x04
#define RV8263C8_REGISTER_MINUTES 0x05
#define RV8263C8_REGISTER_HOURS 0x06
#define RV8263C8_REGISTER_DATE 0x07
#define RV8263C8_REGISTER_WEEKDAY 0x08
#define RV8263C8_REGISTER_MONTH 0x09
#define RV8263C8_REGISTER_YEAR 0x0A
#define RV8263C8_REGISTER_SECONDS_ALARM 0x0B
#define RV8263C8_REGISTER_MINUTES_ALARM 0x0C
#define RV8263C8_REGISTER_HOURS_ALARM 0x0D
#define RV8263C8_REGISTER_DATE_ALARM 0x0E
#define RV8263C8_REGISTER_WEEKDAY_ALARM 0x0F
#define RV8263C8_REGISTER_TIMER_VALUE 0x10
#define RV8263C8_REGISTER_TIMER_MODE 0x11
#define RV8263_BM_FAST_MODE (0x01 << 7)
#define RV8263_BM_NORMAL_MODE (0x00 << 7)
#define RV8263C8_BM_24H_MODE_ENABLE (0x00 << 1)
#define RV8263C8_BM_24H_MODE_DISABLE (0x00 << 1)
#define RV8263C8_BM_CLOCK_ENABLE (0x00 << 5)
#define RV8263C8_BM_CLOCK_DISABLE (0x01 << 5)
#define RV8263C8_BM_ALARM_INT_ENABLE (0x01 << 7)
#define RV8263C8_BM_ALARM_INT_DISABLE (0x00 << 7)
#define RV8263C8_BM_MINUTE_INT_ENABLE (0x01 << 5)
#define RV8263C8_BM_MINUTE_INT_DISABLE (0x00 << 5)
#define RV8263C8_BM_HALF_MINUTE_INT_ENABLE (0x01 << 4)
#define RV8263C8_BM_HALF_MINUTE_INT_DISABLE (0x00 << 4)
#define RV8263C8_BM_ALARM_ENABLE (0x00 << 7)
#define RV8263C8_BM_ALARM_DISABLE (0x01 << 7)
#define RV8263C8_BM_AF (0x01 << 6)
#define RV8263C8_BM_TF (0x01 << 3)
#define RV8263_BM_MODE (0x01 << 7)
#define RV8263_BM_TD_1HZ (0x02 << 3)
#define RV8263_BM_TE_ENABLE (0x01 << 2)
#define RV8263_BM_TIE_ENABLE (0x01 << 1)
#define RV8263_BM_TI_TP_PULSE (0x01 << 0)
#define RV8263_BM_OS (0x01 << 7)
#define RV8263C8_BM_SOFTWARE_RESET (0x58)
#define RV8263C8_BM_REGISTER_OFFSET 0x7F
#define RV8263_YEAR_OFFSET (2000 - 1900)
#define SECONDS_BITS GENMASK(6, 0)
#define MINUTES_BITS GENMASK(7, 0)
#define HOURS_BITS GENMASK(5, 0)
#define DATE_BITS GENMASK(5, 0)
#define MONTHS_BITS GENMASK(4, 0)
#define WEEKDAY_BITS GENMASK(2, 0)
#define YEAR_BITS GENMASK(7, 0)
#define VALIDATE_24HR BIT(6)
#define DT_DRV_COMPAT microcrystal_rv_8263_c8
LOG_MODULE_REGISTER(microcrystal_rv8263c8, CONFIG_RTC_LOG_LEVEL);
struct rv8263c8_config {
struct i2c_dt_spec i2c_bus;
uint32_t clkout;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
struct gpio_dt_spec int_gpio;
#endif
};
struct rv8263c8_data {
struct k_sem lock;
#if (CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE) && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
const struct device *dev;
struct gpio_callback gpio_cb;
#endif
#if CONFIG_RTC_ALARM && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
rtc_alarm_callback alarm_cb;
void *alarm_cb_data;
struct k_work alarm_work;
#endif
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
rtc_update_callback update_cb;
void *update_cb_data;
struct k_work update_work;
#endif
};
static int rv8263c8_update_disable_timer(const struct device *dev)
{
int err;
uint8_t buf[2];
const struct rv8263c8_config *config = dev->config;
/* Value 0 disables the timer. */
buf[0] = RV8263C8_REGISTER_TIMER_VALUE;
buf[1] = 0;
err = i2c_write_dt(&config->i2c_bus, buf, 2);
if (err < 0) {
return err;
}
buf[0] = RV8263C8_REGISTER_TIMER_MODE;
return i2c_write_dt(&config->i2c_bus, buf, 2);
}
#if (CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE) && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
static void rv8263c8_gpio_callback_handler(const struct device *p_port, struct gpio_callback *p_cb,
gpio_port_pins_t pins)
{
ARG_UNUSED(pins);
ARG_UNUSED(p_port);
struct rv8263c8_data *data = CONTAINER_OF(p_cb, struct rv8263c8_data, gpio_cb);
#if CONFIG_RTC_ALARM
k_work_submit(&data->alarm_work);
#endif
#if CONFIG_RTC_UPDATE
k_work_submit(&data->update_work);
#endif
}
#endif
#if CONFIG_RTC_ALARM && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
static void rv8263c8_alarm_worker(struct k_work *p_work)
{
struct rv8263c8_data *data = CONTAINER_OF(p_work, struct rv8263c8_data, alarm_work);
const struct rv8263c8_config *config = data->dev->config;
LOG_DBG("Process alarm worker from interrupt");
if (data->alarm_cb != NULL) {
uint8_t reg;
i2c_reg_read_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, ®);
if (reg & RV8263C8_BM_AF) {
reg &= ~RV8263C8_BM_AF;
LOG_DBG("Calling alarm callback");
data->alarm_cb(data->dev, 0, data->alarm_cb_data);
i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, reg);
}
}
}
#endif
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
static int rv8263c8_update_enable_timer(const struct device *dev)
{
int err;
const struct rv8263c8_config *config = dev->config;
uint8_t buf[2];
/* Set the timer preload value for 1 second. */
buf[0] = RV8263C8_REGISTER_TIMER_VALUE;
buf[1] = 1;
err = i2c_write_dt(&config->i2c_bus, buf, 2);
if (err < 0) {
return err;
}
buf[0] = RV8263C8_REGISTER_TIMER_MODE;
buf[1] = RV8263_BM_TD_1HZ | RV8263_BM_TE_ENABLE | RV8263_BM_TIE_ENABLE |
RV8263_BM_TI_TP_PULSE;
return i2c_write_dt(&config->i2c_bus, buf, 2);
}
static void rv8263c8_update_worker(struct k_work *p_work)
{
uint8_t reg;
struct rv8263c8_data *data = CONTAINER_OF(p_work, struct rv8263c8_data, update_work);
const struct rv8263c8_config *config = data->dev->config;
LOG_DBG("Process update worker from interrupt");
if (data->update_cb != NULL) {
i2c_reg_read_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, ®);
if (reg & RV8263C8_BM_TF) {
LOG_DBG("Calling update callback");
data->update_cb(data->dev, data->update_cb_data);
}
}
rv8263c8_update_enable_timer(data->dev);
i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, RV8263C8_BM_TF,
RV8263C8_BM_TF);
}
#endif
static int rv8263c8_time_set(const struct device *dev, const struct rtc_time *timeptr)
{
uint8_t regs[8];
const struct rv8263c8_config *config = dev->config;
if (timeptr == NULL || (timeptr->tm_year < RV8263_YEAR_OFFSET)) {
LOG_ERR("invalid time");
return -EINVAL;
}
LOG_DBG("Set time: year = %u, mon = %u, mday = %u, wday = %u, hour = %u, min = %u, sec = "
"%u",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
regs[0] = RV8263C8_REGISTER_SECONDS;
regs[1] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS;
regs[2] = bin2bcd(timeptr->tm_min) & MINUTES_BITS;
regs[3] = bin2bcd(timeptr->tm_hour) & HOURS_BITS;
regs[4] = bin2bcd(timeptr->tm_mday) & DATE_BITS;
regs[5] = bin2bcd(timeptr->tm_wday) & WEEKDAY_BITS;
regs[6] = bin2bcd(timeptr->tm_mon) & MONTHS_BITS;
regs[7] = bin2bcd(timeptr->tm_year - RV8263_YEAR_OFFSET) & YEAR_BITS;
return i2c_write_dt(&config->i2c_bus, regs, sizeof(regs));
}
static int rv8263c8_time_get(const struct device *dev, struct rtc_time *timeptr)
{
int err;
uint8_t regs[7];
const struct rv8263c8_config *config = dev->config;
if (timeptr == NULL) {
return -EINVAL;
}
err = i2c_burst_read_dt(&config->i2c_bus, RV8263C8_REGISTER_SECONDS, regs, sizeof(regs));
if (err < 0) {
return err;
}
/* Return an error when the oscillator is stopped. */
if (regs[0] & RV8263_BM_OS) {
return -ENODATA;
}
timeptr->tm_sec = bcd2bin(regs[0] & SECONDS_BITS);
timeptr->tm_min = bcd2bin(regs[1] & MINUTES_BITS);
timeptr->tm_hour = bcd2bin(regs[2] & HOURS_BITS);
timeptr->tm_mday = bcd2bin(regs[3] & DATE_BITS);
timeptr->tm_wday = bcd2bin(regs[4] & WEEKDAY_BITS);
timeptr->tm_mon = bcd2bin(regs[5] & MONTHS_BITS);
timeptr->tm_year = bcd2bin(regs[6] & YEAR_BITS) + RV8263_YEAR_OFFSET;
/* Unused. */
timeptr->tm_nsec = 0;
timeptr->tm_isdst = -1;
timeptr->tm_yday = -1;
/* Validate the chip in 24hr mode. */
if (regs[2] & VALIDATE_24HR) {
return -ENODATA;
}
LOG_DBG("Get time: year = %u, mon = %u, mday = %u, wday = %u, hour = %u, min = %u, sec = "
"%u",
timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
return 0;
}
static int rv8263c8_init(const struct device *dev)
{
int err;
int temp;
struct rv8263c8_data *data = dev->data;
const struct rv8263c8_config *config = dev->config;
#if (CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE) && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
if (config->int_gpio.port == NULL) {
return -EINVAL;
}
#endif
if (!i2c_is_ready_dt(&config->i2c_bus)) {
LOG_ERR("I2C bus not ready!");
return -ENODEV;
}
k_sem_init(&data->lock, 1, 1);
err = rv8263c8_update_disable_timer(dev);
if (err < 0) {
LOG_ERR("Error while disabling the timer! Error: %i", err);
return err;
}
err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_1,
RV8263C8_BM_24H_MODE_DISABLE | RV8263C8_BM_CLOCK_ENABLE);
if (err < 0) {
LOG_ERR("Error while writing CONTROL_1! Error: %i", err);
return err;
}
temp = config->clkout;
LOG_DBG("Configure ClkOut: %u", temp);
err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
RV8263C8_BM_AF | temp);
if (err < 0) {
LOG_ERR("Error while writing CONTROL_2! Error: %i", err);
return err;
}
LOG_DBG("Configure ClkOut: %u", temp);
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
uint8_t buf[2];
buf[0] = RV8263C8_REGISTER_TIMER_MODE;
buf[1] = 0;
err = i2c_write_dt(&config->i2c_bus, buf, 2);
if (err < 0) {
LOG_ERR("Error while writing CONTROL2! Error: %i", err);
return err;
}
#endif
#if (CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE) && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("GPIO not ready!");
return err;
}
err = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (err < 0) {
LOG_ERR("Failed to configure GPIO! Error: %u", err);
return err;
}
err = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_FALLING);
if (err < 0) {
LOG_ERR("Failed to configure interrupt! Error: %u", err);
return err;
}
gpio_init_callback(&data->gpio_cb, rv8263c8_gpio_callback_handler,
BIT(config->int_gpio.pin));
err = gpio_add_callback_dt(&config->int_gpio, &data->gpio_cb);
if (err < 0) {
LOG_ERR("Failed to add GPIO callback! Error: %u", err);
return err;
}
#endif
(void)k_sem_take(&data->lock, K_FOREVER);
#if CONFIG_RTC_ALARM && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
data->alarm_work.handler = rv8263c8_alarm_worker;
#endif
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
data->update_work.handler = rv8263c8_update_worker;
#endif
#if (CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE) && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
data->dev = dev;
#endif
k_sem_give(&data->lock);
return 0;
}
#if CONFIG_RTC_ALARM
static int rv8263c8_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *p_mask)
{
ARG_UNUSED(dev);
ARG_UNUSED(id);
(*p_mask) = (RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE |
RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY |
RTC_ALARM_TIME_MASK_WEEKDAY);
return 0;
}
static int rv8263c8_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
int err;
uint8_t regs[6];
const struct rv8263c8_config *config = dev->config;
ARG_UNUSED(id);
if ((mask > 0) && (timeptr == NULL)) {
return -EINVAL;
}
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_ERR("Invalid mask!");
return -EINVAL;
}
if (mask == 0) {
err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
RV8263C8_BM_ALARM_INT_ENABLE | RV8263C8_BM_AF,
RV8263C8_BM_ALARM_INT_DISABLE);
} else {
/* Clear the AIE and AF bit to prevent false triggering of the alarm. */
err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
RV8263C8_BM_ALARM_INT_ENABLE | RV8263C8_BM_AF, 0);
}
if (err < 0) {
LOG_ERR("Error while enabling alarm! Error: %i", err);
return err;
}
regs[0] = RV8263C8_REGISTER_SECONDS_ALARM;
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
regs[1] = bin2bcd(timeptr->tm_sec) & SECONDS_BITS;
} else {
regs[1] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
regs[2] = bin2bcd(timeptr->tm_min) & MINUTES_BITS;
} else {
regs[2] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
regs[3] = bin2bcd(timeptr->tm_min) & HOURS_BITS;
} else {
regs[3] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
regs[4] = bin2bcd(timeptr->tm_min) & DATE_BITS;
} else {
regs[4] = RV8263C8_BM_ALARM_DISABLE;
}
if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
regs[5] = bin2bcd(timeptr->tm_min) & WEEKDAY_BITS;
} else {
regs[5] = RV8263C8_BM_ALARM_DISABLE;
}
err = i2c_write_dt(&config->i2c_bus, regs, sizeof(regs));
if (err < 0) {
LOG_ERR("Error while setting alarm time! Error: %i", < err);
return err;
}
if (mask != 0) {
/* Enable the alarm interrupt */
err = i2c_reg_update_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2,
RV8263C8_BM_ALARM_INT_ENABLE,
RV8263C8_BM_ALARM_INT_ENABLE);
}
return err;
}
static int rv8263c8_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *p_mask,
struct rtc_time *timeptr)
{
int err;
const struct rv8263c8_config *config = dev->config;
uint8_t value[5];
ARG_UNUSED(id);
if (timeptr == NULL) {
return -EINVAL;
}
(*p_mask) = 0;
err = i2c_burst_read_dt(&config->i2c_bus, RV8263C8_REGISTER_SECONDS_ALARM, value,
sizeof(value));
if (err < 0) {
LOG_ERR("Error while reading alarm! Error: %i", err);
return err;
}
/* Check if the highest bit is not set. If so the alarm is enabled. */
if ((value[0] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_sec = bcd2bin(value[0]) & SECONDS_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_SECOND;
}
if ((value[1] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_min = bcd2bin(value[1]) & MINUTES_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_MINUTE;
}
if ((value[2] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_hour = bcd2bin(value[2]) & HOURS_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_HOUR;
}
if ((value[3] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_mday = bcd2bin(value[3]) & DATE_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
if ((value[4] & RV8263C8_BM_ALARM_DISABLE) == 0) {
timeptr->tm_wday = bcd2bin(value[4]) & WEEKDAY_BITS;
(*p_mask) |= RTC_ALARM_TIME_MASK_WEEKDAY;
}
return 0;
}
static int rv8263c8_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
const struct rv8263c8_config *config = dev->config;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
struct rv8263c8_data *data = dev->data;
#endif
ARG_UNUSED(id);
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
if (config->int_gpio.port == NULL) {
return -ENOTSUP;
}
(void)k_sem_take(&data->lock, K_FOREVER);
data->alarm_cb = callback;
data->alarm_cb_data = user_data;
k_sem_give(&data->lock);
#else
return -ENOTSUP;
#endif
return 0;
}
static int rv8263c8_alarm_is_pending(const struct device *dev, uint16_t id)
{
int err;
uint8_t reg;
const struct rv8263c8_config *config = dev->config;
ARG_UNUSED(id);
err = i2c_reg_read_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, ®);
if (err) {
return err;
}
if (reg & RV8263C8_BM_AF) {
reg &= ~RV8263C8_BM_AF;
err = i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_CONTROL_2, reg);
if (err) {
return err;
}
return 1;
}
return 0;
}
#endif
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
int rv8263_update_callback(const struct device *dev, rtc_update_callback callback, void *user_data)
{
struct rv8263c8_data *const data = dev->data;
(void)k_sem_take(&data->lock, K_FOREVER);
data->update_cb = callback;
data->update_cb_data = user_data;
k_sem_give(&data->lock);
/* Disable the update callback. */
if ((callback == NULL) && (user_data == NULL)) {
return rv8263c8_update_disable_timer(dev);
}
return rv8263c8_update_enable_timer(dev);
}
#endif
#ifdef CONFIG_RTC_CALIBRATION
int rv8263c8_calibration_set(const struct device *dev, int32_t calibration)
{
int8_t offset;
int32_t test_mode0;
int32_t test_mode1;
int32_t offset_ppm_mode0;
int32_t offset_ppm_mode1;
const struct rv8263c8_config *config = dev->config;
/* NOTE: The RTC API is using a PPB (Parts Per Billion) value. The RTC is using PPM.
* Here we calculate the offset when using MODE = 0.
* Formula from the application manual:
* Offset [ppm] = (calibration [ppb] / (4.34 [ppm] x 1000))
*/
offset_ppm_mode0 = calibration / 4340;
/* Here we calculate the offset when using MODE = 1.
* Formula from the application manual:
* Offset [ppm] = (calibration [ppb] / (4.069 [ppm] x 1000))
*/
offset_ppm_mode1 = calibration / 4069;
LOG_DBG("Offset Mode = 0: %i", offset_ppm_mode0);
LOG_DBG("Offset Mode = 1: %i", offset_ppm_mode1);
test_mode0 = offset_ppm_mode0 * 4340;
test_mode0 = calibration - test_mode0;
test_mode1 = offset_ppm_mode1 * 4069;
test_mode1 = calibration - test_mode1;
/* Compare the values and select the value with the smallest error. */
test_mode0 = test_mode0 < 0 ? -test_mode0 : test_mode0;
test_mode1 = test_mode1 < 0 ? -test_mode1 : test_mode1;
if (test_mode0 > test_mode1) {
LOG_DBG("Use fast mode (Mode = 1)");
/* Error with MODE = 1 is smaller -> Use MODE = 1. */
offset = RV8263_BM_FAST_MODE | (offset_ppm_mode1 & GENMASK(7, 0));
} else {
LOG_DBG("Use normal mode (Mode = 0)");
/* Error with MODE = 0 is smaller -> Use MODE = 0. */
offset = RV8263_BM_NORMAL_MODE | (offset_ppm_mode0 & GENMASK(7, 0));
}
LOG_DBG("Set offset value: %i", (offset & RV8263C8_BM_REGISTER_OFFSET));
return i2c_reg_write_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_OFFSET, offset);
}
int rv8263c8_calibration_get(const struct device *dev, int32_t *calibration)
{
int err;
int32_t temp;
int8_t offset;
const struct rv8263c8_config *config = dev->config;
if (calibration == NULL) {
return -EINVAL;
}
err = i2c_reg_read_byte_dt(&config->i2c_bus, RV8263C8_REGISTER_OFFSET, &offset);
if (err) {
return err;
}
/* Convert the signed 7 bit into a signed 8 bit value. */
if (offset & (0x01 << 6)) {
temp = offset | (0x01 << 7);
} else {
temp = offset & (0x3F);
temp &= ~(0x01 << 7);
}
LOG_DBG("Read offset: %i", temp);
if (offset & RV8263_BM_FAST_MODE) {
temp = temp * 4340L;
} else {
temp = temp * 4069L;
}
*calibration = temp;
return 0;
}
#endif
static const struct rtc_driver_api rv8263c8_driver_api = {
.set_time = rv8263c8_time_set,
.get_time = rv8263c8_time_get,
#if CONFIG_RTC_ALARM
.alarm_get_supported_fields = rv8263c8_alarm_get_supported_fields,
.alarm_set_time = rv8263c8_alarm_set_time,
.alarm_get_time = rv8263c8_alarm_get_time,
.alarm_is_pending = rv8263c8_alarm_is_pending,
.alarm_set_callback = rv8263c8_alarm_set_callback,
#endif
#if CONFIG_RTC_UPDATE && DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
.update_set_callback = rv8263_update_callback,
#endif
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = rv8263c8_calibration_set,
.get_calibration = rv8263c8_calibration_get,
#endif
};
#define RV8263_DEFINE(inst) \
static struct rv8263c8_data rv8263c8_data_##inst; \
static const struct rv8263c8_config rv8263c8_config_##inst = { \
.i2c_bus = I2C_DT_SPEC_INST_GET(inst), \
.clkout = DT_INST_ENUM_IDX(inst, clkout), \
IF_ENABLED(DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios), \
(.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0})))}; \
DEVICE_DT_INST_DEFINE(inst, &rv8263c8_init, NULL, &rv8263c8_data_##inst, \
&rv8263c8_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, \
&rv8263c8_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RV8263_DEFINE)
``` | /content/code_sandbox/drivers/rtc/rtc_rv8263.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,642 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
#include <DA1469xAB.h>
#include <da1469x_config.h>
#include <da1469x_pdc.h>
#include "rtc_utils.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(rtc_smartbond, CONFIG_RTC_LOG_LEVEL);
#define DT_DRV_COMPAT renesas_smartbond_rtc
#define SMARTBOND_IRQN DT_INST_IRQN(0)
#define SMARTBOND_IRQ_PRIO DT_INST_IRQ(0, priority)
#define RTC_ALARMS_COUNT DT_PROP(DT_NODELABEL(rtc), alarms_count)
#define TM_YEAR_REF 1900
#define RTC_DIV_DENOM_1000 0
#define RTC_DIV_DENOM_1024 1
#define RTC_SMARTBOND_SUPPORTED_ALARM_FIELDS \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY)
#define RTC_TIME_REG_SET_FIELD(_field, _var, _val) \
((_var) = \
((_var) & ~(RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Msk)) | \
(((_val) << RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Pos) & \
(RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Msk)))
#define RTC_CALENDAR_REG_SET_FIELD(_field, _var, _val) \
((_var) = \
((_var) & ~(RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Msk)) | \
(((_val) << RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Pos) & \
(RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Msk)))
#define RTC_CALENDAR_ALARM_REG_SET_FIELD(_field, _var, _val) \
((_var) = \
((_var) & ~(RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _U_Msk)) | \
(((_val) << RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _U_Pos) & \
(RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _U_Msk)))
#define RTC_TIME_ALARM_REG_SET_FIELD(_field, _var, _val) \
((_var) = \
((_var) & ~(RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _U_Msk)) | \
(((_val) << RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _U_Pos) & \
(RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _U_Msk)))
#define RTC_TIME_REG_GET_FIELD(_field, _var) \
(((_var) & (RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Msk)) >> \
RTC_RTC_TIME_REG_RTC_TIME_ ## _field ## _U_Pos)
#define RTC_CALENDAR_REG_GET_FIELD(_field, _var) \
(((_var) & (RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Msk)) >> \
RTC_RTC_CALENDAR_REG_RTC_CAL_ ## _field ## _U_Pos)
#define RTC_CALENDAR_ALARM_REG_GET_FIELD(_field, _var) \
(((_var) & (RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _T_Msk | \
RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _U_Msk)) >> \
RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_ ## _field ## _U_Pos)
#define RTC_TIME_ALARM_REG_GET_FIELD(_field, _var) \
(((_var) & (RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _T_Msk | \
RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _U_Msk)) >> \
RTC_RTC_TIME_ALARM_REG_RTC_TIME_ ## _field ## _U_Pos)
#define CLK_RTCDIV_REG_SET_FIELD(_field, _var, _val) \
((_var) = \
((_var) & ~CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ ## _field ## _Msk) | \
(((_val) << CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ ## _field ## _Pos) & \
CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ ## _field ## _Msk))
struct rtc_smartbond_data {
struct k_mutex lock;
bool is_rtc_configured;
#if defined(CONFIG_RTC_ALARM)
volatile bool is_alarm_pending;
rtc_alarm_callback alarm_cb;
void *alarm_user_data;
#endif
#if defined(CONFIG_RTC_UPDATE)
rtc_update_callback update_cb;
void *update_user_data;
#endif
};
#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE)
static void smartbond_rtc_isr(const struct device *dev)
{
struct rtc_smartbond_data *data = dev->data;
/* Exercise which events asserted the RTC IRQ line. Register is cleared upon read. */
uint32_t rtc_event_flags_reg = RTC->RTC_EVENT_FLAGS_REG;
/* RTC_EVENT_FLASH_REG will be updated regardless of the interrupt mask. */
uint32_t rtc_interrupt_mask_reg = RTC->RTC_INTERRUPT_MASK_REG;
#if defined(CONFIG_RTC_ALARM)
if ((rtc_event_flags_reg & RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk) &&
!(rtc_interrupt_mask_reg & RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk)) {
if (data->alarm_cb) {
data->alarm_cb(dev, 0, data->alarm_user_data);
data->is_alarm_pending = false;
} else {
data->is_alarm_pending = true;
}
}
#endif
#if defined(CONFIG_RTC_UPDATE)
if ((rtc_event_flags_reg & RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk) &&
!(rtc_interrupt_mask_reg & RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk)) {
if (data->update_cb) {
data->update_cb(dev, data->update_user_data);
}
}
#endif
}
#endif
static inline void rtc_smartbond_set_status(bool status)
{
if (status) {
CRG_TOP->CLK_RTCDIV_REG |= CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk;
RTC->RTC_CONTROL_REG = 0;
} else {
RTC->RTC_CONTROL_REG = (RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk |
RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk);
CRG_TOP->CLK_RTCDIV_REG &= ~CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk;
}
}
static uint32_t rtc_time_to_bcd(const struct rtc_time *timeptr)
{
uint32_t rtc_time_reg = 0;
RTC_TIME_REG_SET_FIELD(S, rtc_time_reg, bin2bcd(timeptr->tm_sec)); /*[0, 59]*/
RTC_TIME_REG_SET_FIELD(M, rtc_time_reg, bin2bcd(timeptr->tm_min)); /*[0, 59]*/
RTC_TIME_REG_SET_FIELD(HR, rtc_time_reg, bin2bcd(timeptr->tm_hour)); /*[0, 23]*/
return rtc_time_reg;
}
static uint32_t rtc_calendar_to_bcd(const struct rtc_time *timeptr)
{
uint32_t rtc_calendar_reg = 0;
RTC_CALENDAR_REG_SET_FIELD(D, rtc_calendar_reg, bin2bcd(timeptr->tm_mday)); /*[1, 31]*/
RTC_CALENDAR_REG_SET_FIELD(Y, rtc_calendar_reg,
bin2bcd((timeptr->tm_year + TM_YEAR_REF) % 100)); /*[year - 1900]*/
RTC_CALENDAR_REG_SET_FIELD(C, rtc_calendar_reg,
bin2bcd((timeptr->tm_year + TM_YEAR_REF) / 100));
RTC_CALENDAR_REG_SET_FIELD(M, rtc_calendar_reg, bin2bcd(timeptr->tm_mon + 1)); /*[0, 11]*/
if (timeptr->tm_wday != -1) {
rtc_calendar_reg |= ((timeptr->tm_wday + 1) &
RTC_RTC_CALENDAR_REG_RTC_DAY_Msk); /*[0, 6]*/
}
return rtc_calendar_reg;
}
static void bcd_to_rtc_time(struct rtc_time *timeptr)
{
uint32_t rtc_time_reg = RTC->RTC_TIME_REG;
timeptr->tm_sec = bcd2bin(RTC_TIME_REG_GET_FIELD(S, rtc_time_reg));
timeptr->tm_min = bcd2bin(RTC_TIME_REG_GET_FIELD(M, rtc_time_reg));
timeptr->tm_hour = bcd2bin(RTC_TIME_REG_GET_FIELD(HR, rtc_time_reg));
timeptr->tm_nsec = 0; /*Unknown*/
}
static void bcd_to_rtc_calendar(struct rtc_time *timeptr)
{
uint32_t rtc_calendar_reg = RTC->RTC_CALENDAR_REG;
timeptr->tm_mday = bcd2bin(RTC_CALENDAR_REG_GET_FIELD(D, rtc_calendar_reg));
timeptr->tm_mon = bcd2bin(RTC_CALENDAR_REG_GET_FIELD(M, rtc_calendar_reg)) - 1;
timeptr->tm_year = bcd2bin(RTC_CALENDAR_REG_GET_FIELD(Y, rtc_calendar_reg)) +
(bcd2bin(RTC_CALENDAR_REG_GET_FIELD(C, rtc_calendar_reg)) * 100) - TM_YEAR_REF;
timeptr->tm_wday = (rtc_calendar_reg & RTC_RTC_CALENDAR_REG_RTC_DAY_Msk) - 1;
timeptr->tm_yday = timeptr->tm_isdst = -1; /*Unknown*/
}
static int rtc_smartbond_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_smartbond_data *data = dev->data;
int ret = 0;
uint32_t rtc_time_reg, rtc_calendar_reg, rtc_status_reg;
if (timeptr == NULL) {
LOG_ERR("No pointer is provided to set time");
return -EINVAL;
}
if (timeptr->tm_year + TM_YEAR_REF < TM_YEAR_REF) {
LOG_ERR("RTC time exceeds HW capabilities");
return -EINVAL;
}
if ((timeptr->tm_yday != -1) || (timeptr->tm_isdst != -1) || (timeptr->tm_nsec != 0)) {
LOG_WRN("Unsupported RTC sub-values");
}
k_mutex_lock(&data->lock, K_FOREVER);
rtc_smartbond_set_status(false);
/* Store current counter values as it might happen that the requested time is not valid */
rtc_time_reg = RTC->RTC_TIME_REG;
rtc_calendar_reg = RTC->RTC_CALENDAR_REG;
RTC->RTC_TIME_REG = rtc_time_to_bcd(timeptr);
RTC->RTC_CALENDAR_REG = rtc_calendar_to_bcd(timeptr);
/* Check if the new values were valid, otherwise reset back to the previous ones. */
rtc_status_reg = RTC->RTC_STATUS_REG;
if (!(rtc_status_reg & RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk) ||
!(rtc_status_reg & RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk)) {
RTC->RTC_TIME_REG = rtc_time_reg;
RTC->RTC_CALENDAR_REG = rtc_calendar_reg;
ret = -EINVAL;
}
/* Mark the very first valid RTC configuration; used to check if RTC contains valid data. */
if (!data->is_rtc_configured && (ret == 0)) {
data->is_rtc_configured = true;
}
/* It might happen that the very first time RTC is not configured correctly; do not care. */
rtc_smartbond_set_status(true);
k_mutex_unlock(&data->lock);
return ret;
}
static int rtc_smartbond_get_time(const struct device *dev, struct rtc_time *timeptr)
{
struct rtc_smartbond_data *data = dev->data;
if (timeptr == NULL) {
LOG_ERR("No pointer is provided to store the requested time");
return -EINVAL;
}
if (!data->is_rtc_configured) {
LOG_WRN("RTC is not initialized yet");
}
k_mutex_lock(&data->lock, K_FOREVER);
/* Stop RTC counters to obtain coherent data. */
rtc_smartbond_set_status(false);
bcd_to_rtc_time(timeptr);
bcd_to_rtc_calendar(timeptr);
rtc_smartbond_set_status(true);
k_mutex_unlock(&data->lock);
return 0;
}
#if defined(CONFIG_RTC_ALARM)
BUILD_ASSERT(RTC_ALARMS_COUNT, "At least one alarm event should be supported");
/*
* Parse only the alarm fields indicated by the mask. Default valid values should be assigned
* to unused fields as it might happen that application has provided with invalid values.
*/
static uint32_t alarm_calendar_to_bcd(const struct rtc_time *timeptr, uint16_t mask)
{
uint32_t rtc_calendar_alarm_reg = 0x0108;
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
RTC_CALENDAR_ALARM_REG_SET_FIELD(D, rtc_calendar_alarm_reg,
bin2bcd(timeptr->tm_mday));
}
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
RTC_CALENDAR_ALARM_REG_SET_FIELD(M, rtc_calendar_alarm_reg,
bin2bcd(timeptr->tm_mon + 1));
}
return rtc_calendar_alarm_reg;
}
/*
* Parse only the alarm fields indicated by the mask. Default valid values should be assigned
* to unused fields as it might happen that application has provided with invalid values.
*/
static inline uint32_t alarm_time_to_bcd(const struct rtc_time *timeptr, uint16_t mask)
{
uint32_t rtc_time_alarm_reg = 0;
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
/*[0, 59]*/
RTC_TIME_ALARM_REG_SET_FIELD(S, rtc_time_alarm_reg, bin2bcd(timeptr->tm_sec));
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
/*[0, 59]*/
RTC_TIME_ALARM_REG_SET_FIELD(M, rtc_time_alarm_reg, bin2bcd(timeptr->tm_min));
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
/*[0, 23]*/
RTC_TIME_ALARM_REG_SET_FIELD(HR, rtc_time_alarm_reg, bin2bcd(timeptr->tm_hour));
}
return rtc_time_alarm_reg;
}
static void bcd_to_alarm_calendar(struct rtc_time *timeptr)
{
uint32_t rtc_calendar_alarm_reg = RTC->RTC_CALENDAR_ALARM_REG;
timeptr->tm_mday = bcd2bin(RTC_CALENDAR_ALARM_REG_GET_FIELD(D, rtc_calendar_alarm_reg));
timeptr->tm_mon = bcd2bin(RTC_CALENDAR_ALARM_REG_GET_FIELD(M, rtc_calendar_alarm_reg)) - 1;
timeptr->tm_yday = timeptr->tm_wday = timeptr->tm_isdst = timeptr->tm_year = -1;
}
static void bcd_to_alarm_time(struct rtc_time *timeptr)
{
uint32_t rtc_time_alarm_reg = RTC->RTC_TIME_ALARM_REG;
timeptr->tm_sec = bcd2bin(RTC_TIME_ALARM_REG_GET_FIELD(S, rtc_time_alarm_reg));
timeptr->tm_min = bcd2bin(RTC_TIME_ALARM_REG_GET_FIELD(M, rtc_time_alarm_reg));
timeptr->tm_hour = bcd2bin(RTC_TIME_ALARM_REG_GET_FIELD(HR, rtc_time_alarm_reg));
timeptr->tm_nsec = 0;
}
static uint32_t tm_to_rtc_alarm_mask(uint16_t mask)
{
uint32_t rtc_alarm_enable_reg = 0;
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
rtc_alarm_enable_reg |= RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk;
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
rtc_alarm_enable_reg |= RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk;
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
rtc_alarm_enable_reg |= RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk;
}
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
rtc_alarm_enable_reg |= RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk;
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
rtc_alarm_enable_reg |= RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk;
}
return rtc_alarm_enable_reg;
}
static uint16_t rtc_to_tm_alarm_mask(uint32_t rtc_alarm_enable_reg)
{
uint16_t mask = 0;
if (rtc_alarm_enable_reg & RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk) {
mask |= RTC_ALARM_TIME_MASK_SECOND;
}
if (rtc_alarm_enable_reg & RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk) {
mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if (rtc_alarm_enable_reg & RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk) {
mask |= RTC_ALARM_TIME_MASK_HOUR;
}
if (rtc_alarm_enable_reg & RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk) {
mask |= RTC_ALARM_TIME_MASK_MONTH;
}
if (rtc_alarm_enable_reg & RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk) {
mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
return mask;
}
static int rtc_smartbond_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
int ret = 0;
struct rtc_smartbond_data *data = dev->data;
uint32_t rtc_time_alarm_reg;
uint32_t rtc_calendar_alarm_reg;
uint32_t rtc_alarm_enable_reg;
uint32_t rtc_status_reg;
if (id >= RTC_ALARMS_COUNT) {
LOG_ERR("Alarm id is out of range");
return -EINVAL;
}
if (mask & ~RTC_SMARTBOND_SUPPORTED_ALARM_FIELDS) {
LOG_ERR("Invalid alarm mask");
return -EINVAL;
}
if ((timeptr == NULL) && (mask != 0)) {
LOG_ERR("No pointer is provided to set alarm");
return -EINVAL;
}
if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
LOG_ERR("Invalid alarm fields values");
return -EINVAL;
}
if (!data->is_rtc_configured) {
LOG_WRN("RTC is not initialized yet");
}
k_mutex_lock(&data->lock, K_FOREVER);
rtc_alarm_enable_reg = RTC->RTC_ALARM_ENABLE_REG;
/* Disable alarm to obtain coherency and/or when the alarm mask is empty */
RTC->RTC_ALARM_ENABLE_REG = 0;
RTC->RTC_INTERRUPT_DISABLE_REG = RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk;
if (mask) {
/* Store current counter values as it might happen requested alrm is not valid */
rtc_time_alarm_reg = RTC->RTC_TIME_ALARM_REG;
rtc_calendar_alarm_reg = RTC->RTC_CALENDAR_ALARM_REG;
RTC->RTC_TIME_ALARM_REG = alarm_time_to_bcd(timeptr, mask);
RTC->RTC_CALENDAR_ALARM_REG = alarm_calendar_to_bcd(timeptr, mask);
rtc_status_reg = RTC->RTC_STATUS_REG;
if (!(rtc_status_reg & RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk) ||
!(rtc_status_reg & RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk)) {
RTC->RTC_TIME_ALARM_REG = rtc_time_alarm_reg;
RTC->RTC_CALENDAR_ALARM_REG = rtc_calendar_alarm_reg;
RTC->RTC_ALARM_ENABLE_REG = rtc_alarm_enable_reg;
ret = -EINVAL;
} else {
RTC->RTC_ALARM_ENABLE_REG = tm_to_rtc_alarm_mask(mask);
}
RTC->RTC_INTERRUPT_ENABLE_REG = RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk;
}
k_mutex_unlock(&data->lock);
return ret;
}
static int rtc_smartbond_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_smartbond_data *data = dev->data;
if (id >= RTC_ALARMS_COUNT) {
LOG_ERR("Alarm id is out of range");
return -EINVAL;
}
if ((timeptr == NULL) || (mask == NULL)) {
LOG_ERR("No pointer is provided to store the requested alarm time/mask");
return -EINVAL;
}
if (!data->is_rtc_configured) {
LOG_WRN("RTC is not initialized yet");
}
k_mutex_lock(&data->lock, K_FOREVER);
bcd_to_alarm_calendar(timeptr);
bcd_to_alarm_time(timeptr);
*mask = rtc_to_tm_alarm_mask(RTC->RTC_ALARM_ENABLE_REG);
k_mutex_unlock(&data->lock);
return 0;
}
static int rtc_smartbond_alarm_is_pending(const struct device *dev, uint16_t id)
{
unsigned int key;
int status;
struct rtc_smartbond_data *data = dev->data;
if (id >= RTC_ALARMS_COUNT) {
LOG_ERR("Alarm id is out of range");
return -EINVAL;
}
/* Globally disable interrupts as the status flag can be updated within ISR */
key = DA1469X_IRQ_DISABLE();
status = data->is_alarm_pending;
/* After reading, the alarm status should be cleared. */
data->is_alarm_pending = 0;
DA1469X_IRQ_ENABLE(key);
return status;
}
static int rtc_smartbond_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_smartbond_data *data = dev->data;
if (id >= RTC_ALARMS_COUNT) {
LOG_ERR("Alarm id is out of range");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
data->alarm_cb = callback;
data->alarm_user_data = user_data;
k_mutex_unlock(&data->lock);
return 0;
}
static int rtc_smartbond_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
if (id >= RTC_ALARMS_COUNT) {
LOG_ERR("Alarm id is out of range");
return -EINVAL;
}
if (mask == NULL) {
LOG_ERR("Pointer to store the mask value is missed");
return -EINVAL;
}
*mask = (uint16_t)RTC_SMARTBOND_SUPPORTED_ALARM_FIELDS;
return 0;
}
#endif
#if defined(CONFIG_RTC_UPDATE)
static int rtc_smartbond_update_set_callback(const struct device *dev, rtc_update_callback callback,
void *user_data)
{
struct rtc_smartbond_data *data = dev->data;
k_mutex_lock(&data->lock, K_FOREVER);
data->update_cb = callback;
data->update_user_data = user_data;
if (data->update_cb) {
/* Enable asserting the RTC interrupt line when the second counter rolls over. */
RTC->RTC_INTERRUPT_ENABLE_REG = RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk;
} else {
RTC->RTC_INTERRUPT_DISABLE_REG = RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk;
}
k_mutex_unlock(&data->lock);
return 0;
}
#endif
static const struct rtc_driver_api rtc_smartbond_driver_api = {
.get_time = rtc_smartbond_get_time,
.set_time = rtc_smartbond_set_time,
#if defined(CONFIG_RTC_ALARM)
.alarm_get_time = rtc_smartbond_alarm_get_time,
.alarm_set_time = rtc_smartbond_alarm_set_time,
.alarm_is_pending = rtc_smartbond_alarm_is_pending,
.alarm_set_callback = rtc_smartbond_alarm_set_callback,
.alarm_get_supported_fields = rtc_smartbond_alarm_get_supported_fields,
#endif
#if defined(CONFIG_RTC_UPDATE)
.update_set_callback = rtc_smartbond_update_set_callback,
#endif
};
static void rtc_smartbond_100HZ_clock_cfg(void)
{
const struct device * const dev = DEVICE_DT_GET(DT_NODELABEL(osc));
uint32_t lp_clk_rate;
uint32_t clk_rtcdiv_reg;
if (!device_is_ready(dev)) {
__ASSERT_MSG_INFO("Clock device is not ready");
}
if (clock_control_get_rate(dev, (clock_control_subsys_t)SMARTBOND_CLK_LP_CLK,
&lp_clk_rate) < 0) {
__ASSERT_MSG_INFO("Cannot extract LP clock rate");
}
clk_rtcdiv_reg = CRG_TOP->CLK_RTCDIV_REG;
CLK_RTCDIV_REG_SET_FIELD(DENOM, clk_rtcdiv_reg, RTC_DIV_DENOM_1000);
CLK_RTCDIV_REG_SET_FIELD(INT, clk_rtcdiv_reg, lp_clk_rate / 100);
CLK_RTCDIV_REG_SET_FIELD(FRAC, clk_rtcdiv_reg, (lp_clk_rate % 100) * 10);
CRG_TOP->CLK_RTCDIV_REG = clk_rtcdiv_reg;
}
static int rtc_smartbond_init(const struct device *dev)
{
ARG_UNUSED(dev);
/* Wakeup device from RTC events (alarm/roll over) */
#if CONFIG_PM
bool is_xtal32m_enabled = DT_NODE_HAS_STATUS(DT_NODELABEL(xtal32m), okay);
int pdc_idx = da1469x_pdc_add(MCU_PDC_TRIGGER_RTC_ALARM, MCU_PDC_MASTER_M33,
is_xtal32m_enabled ? MCU_PDC_EN_XTAL : 0);
__ASSERT(pdc_idx >= 0, "Failed to add RTC PDC entry");
da1469x_pdc_set(pdc_idx);
da1469x_pdc_ack(pdc_idx);
#endif
rtc_smartbond_100HZ_clock_cfg();
/* Timer and calendar counters will not reset after SW reset */
RTC->RTC_KEEP_RTC_REG |= RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk;
#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE)
IRQ_CONNECT(SMARTBOND_IRQN, SMARTBOND_IRQ_PRIO, smartbond_rtc_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(SMARTBOND_IRQN);
#endif
return 0;
}
#define SMARTBOND_RTC_INIT(inst) \
BUILD_ASSERT((inst) == 0, "multiple instances are not supported"); \
\
static struct rtc_smartbond_data rtc_smartbond_data_ ## inst; \
\
DEVICE_DT_INST_DEFINE(0, rtc_smartbond_init, NULL, \
&rtc_smartbond_data_ ## inst, NULL, \
POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, \
&rtc_smartbond_driver_api);
DT_INST_FOREACH_STATUS_OKAY(SMARTBOND_RTC_INIT)
``` | /content/code_sandbox/drivers/rtc/rtc_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,926 |
```unknown
config RTC_RPI_PICO
bool "Raspberry Pi Pico RTC driver"
default y
depends on DT_HAS_RASPBERRYPI_PICO_RTC_ENABLED
select PICOSDK_USE_RTC
depends on RESET
``` | /content/code_sandbox/drivers/rtc/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
config COUNTER_SAM_TC
bool "Atmel SAM MCU family counter (TC) driver"
default y
depends on DT_HAS_ATMEL_SAM_TC_ENABLED
help
Enable the Atmel SAM MCU family counter (TC) driver.
``` | /content/code_sandbox/drivers/counter/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_rtc_timer
/*
* Include esp-idf headers first to avoid
* redefining BIT() macro
*/
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc.h"
#include <esp_rom_sys.h>
#include <hal/rtc_cntl_ll.h>
#include <zephyr/device.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/spinlock.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/esp32_clock_control.h>
#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL);
#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t
#else
#define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t
#endif
static void counter_esp32_isr(void *arg);
struct counter_esp32_config {
struct counter_config_info counter_info;
int irq_source;
const struct device *clock_dev;
};
struct counter_esp32_data {
struct counter_alarm_cfg alarm_cfg;
uint32_t ticks;
uint32_t clk_src_freq;
};
static int counter_esp32_init(const struct device *dev)
{
const struct counter_esp32_config *cfg = dev->config;
struct counter_esp32_data *data = dev->data;
/* RTC_SLOW_CLK is the default clk source */
clock_control_get_rate(cfg->clock_dev,
(clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW,
&data->clk_src_freq);
esp_intr_alloc(cfg->irq_source,
0,
(ESP32_COUNTER_RTC_ISR_HANDLER)counter_esp32_isr,
(void *)dev,
NULL);
return 0;
}
static int counter_esp32_start(const struct device *dev)
{
ARG_UNUSED(dev);
/* RTC main timer runs after power-on reset */
return 0;
}
static int counter_esp32_stop(const struct device *dev)
{
ARG_UNUSED(dev);
/*
* Any reset/sleep mode, except for the power-up
* reset, will not stop or reset the RTC timer
* ESP32 TRM v4.6 sec. 31.3.11
*/
return 0;
}
static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
{
ARG_UNUSED(dev);
*ticks = (uint32_t) rtc_cntl_ll_get_rtc_time();
return 0;
}
static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
ARG_UNUSED(chan_id);
struct counter_esp32_data *data = dev->data;
uint32_t now;
uint32_t ticks = 0;
#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32C2) || \
defined(CONFIG_SOC_SERIES_ESP32C3)
/* In ESP32/C3 Series the min possible value is 30 us*/
if (counter_ticks_to_us(dev, alarm_cfg->ticks) < 30) {
return -EINVAL;
}
#endif
data->alarm_cfg.callback = alarm_cfg->callback;
data->alarm_cfg.user_data = alarm_cfg->user_data;
counter_esp32_get_value(dev, &now);
ticks = (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) ? alarm_cfg->ticks
: now + alarm_cfg->ticks;
rtc_cntl_ll_set_wakeup_timer(ticks);
/* RTC main timer set alarm value */
CLEAR_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, 0xffffffff);
/* RTC main timer set alarm enable */
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN);
/* RTC main timer interrupt enable */
SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_MAIN_TIMER_INT_ENA);
return 0;
}
static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
ARG_UNUSED(dev);
ARG_UNUSED(chan_id);
/* RTC main timer interrupt disable */
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR);
/* RTC main timer set alarm disable */
CLEAR_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN);
return 0;
}
static int counter_esp32_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_esp32_config *config = dev->config;
if (cfg->ticks != config->counter_info.max_top_value) {
return -ENOTSUP;
}
return 0;
}
static uint32_t counter_esp32_get_pending_int(const struct device *dev)
{
ARG_UNUSED(dev);
uint32_t rc = READ_PERI_REG(RTC_CNTL_INT_ST_REG) & RTC_CNTL_MAIN_TIMER_INT_ST;
return (rc >> RTC_CNTL_MAIN_TIMER_INT_ST_S);
}
/*
* Espressif's RTC Timer is actually 48-bits in resolution
* However, the top value returned is limited to UINT32_MAX
* as per the counter API.
*/
static uint32_t counter_esp32_get_top_value(const struct device *dev)
{
const struct counter_esp32_config *cfg = dev->config;
return cfg->counter_info.max_top_value;
}
static uint32_t counter_esp32_get_freq(const struct device *dev)
{
struct counter_esp32_data *data = dev->data;
return data->clk_src_freq;
}
static struct counter_esp32_data counter_data;
static const struct counter_esp32_config counter_config = {
.counter_info = {
.max_top_value = UINT32_MAX,
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = 1
},
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.irq_source = DT_INST_IRQN(0),
};
static const struct counter_driver_api rtc_timer_esp32_api = {
.start = counter_esp32_start,
.stop = counter_esp32_stop,
.get_value = counter_esp32_get_value,
.set_alarm = counter_esp32_set_alarm,
.cancel_alarm = counter_esp32_cancel_alarm,
.set_top_value = counter_esp32_set_top_value,
.get_pending_int = counter_esp32_get_pending_int,
.get_top_value = counter_esp32_get_top_value,
.get_freq = counter_esp32_get_freq,
};
static void counter_esp32_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
struct counter_esp32_data *data = dev->data;
uint32_t now;
counter_esp32_cancel_alarm(dev, 0);
counter_esp32_get_value(dev, &now);
if (data->alarm_cfg.callback) {
data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data);
}
/* RTC timer clear interrupt status */
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR);
}
DEVICE_DT_INST_DEFINE(0,
&counter_esp32_init,
NULL,
&counter_data,
&counter_config,
POST_KERNEL,
CONFIG_COUNTER_INIT_PRIORITY,
&rtc_timer_esp32_api);
``` | /content/code_sandbox/drivers/counter/counter_esp32_rtc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,654 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_rtc
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/rtc.h>
#include <zephyr/sys/util.h>
#include <string.h>
#include <soc.h>
#define RTC_SAM_REG_GET_FIELD(value, field) \
((RTC_##field##_Msk & value) >> RTC_##field##_Pos)
#define RTC_SAM_WPMR_DISABLE 0x52544300
#define RTC_SAM_WPMR_ENABLE 0x52544301
#define RTC_SAM_CALIBRATE_PPB_MAX (1950000)
#define RTC_SAM_CALIBRATE_PPB_MIN (-1950000)
#define RTC_SAM_CALIBRATE_PPB_QUANTA (1500)
#define RTC_SAM_CALIBRATE_PPB_LOW_SCALE (30500)
#define RTC_SAM_TIME_MASK \
(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR | \
RTC_ALARM_TIME_MASK_WEEKDAY)
typedef void (*rtc_sam_irq_init_fn_ptr)(void);
struct rtc_sam_config {
Rtc *regs;
uint16_t irq_num;
rtc_sam_irq_init_fn_ptr irq_init_fn_ptr;
};
struct rtc_sam_data {
#ifdef CONFIG_RTC_ALARM
rtc_alarm_callback alarm_callback;
void *alarm_user_data;
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
rtc_update_callback update_callback;
void *update_user_data;
#endif /* CONFIG_RTC_UPDATE */
struct k_spinlock lock;
struct k_sem cr_sec_evt_sem;
struct k_sem cr_upd_ack_sem;
};
static void rtc_sam_disable_wp(void)
{
REG_RTC_WPMR = RTC_SAM_WPMR_DISABLE;
}
static void rtc_sam_enable_wp(void)
{
REG_RTC_WPMR = RTC_SAM_WPMR_ENABLE;
}
static uint32_t rtc_sam_timr_from_tm(const struct rtc_time *timeptr)
{
uint32_t timr;
timr = RTC_TIMR_SEC(bin2bcd(timeptr->tm_sec));
timr |= RTC_TIMR_MIN(bin2bcd(timeptr->tm_min));
timr |= RTC_TIMR_HOUR(bin2bcd(timeptr->tm_hour));
return timr;
}
static uint32_t rtc_sam_calr_from_tm(const struct rtc_time *timeptr)
{
uint32_t calr;
uint8_t centuries;
uint8_t years;
calr = RTC_CALR_DATE(bin2bcd(timeptr->tm_mday));
calr |= RTC_CALR_MONTH(bin2bcd(timeptr->tm_mon + 1));
centuries = (uint8_t)((timeptr->tm_year / 100) + 19);
years = (uint8_t)((timeptr->tm_year % 100));
calr |= RTC_CALR_CENT(bin2bcd(centuries));
calr |= RTC_CALR_YEAR(bin2bcd(years));
calr |= RTC_CALR_DAY(bin2bcd(timeptr->tm_wday + 1));
return calr;
}
static int rtc_sam_set_time(const struct device *dev, const struct rtc_time *timeptr)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
if (rtc_utils_validate_rtc_time(timeptr, RTC_SAM_TIME_MASK) == false) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
k_sem_reset(&data->cr_sec_evt_sem);
k_sem_take(&data->cr_sec_evt_sem, K_MSEC(1100));
k_sem_reset(&data->cr_upd_ack_sem);
/* Enable update acknowledge interrupt */
regs->RTC_IER = RTC_IER_ACKEN;
rtc_sam_disable_wp();
/* Request update */
regs->RTC_CR = (RTC_CR_UPDTIM | RTC_CR_UPDCAL);
/* Await update acknowledge */
if (k_sem_take(&data->cr_upd_ack_sem, K_MSEC(1100)) < 0) {
regs->RTC_CR = 0;
rtc_sam_enable_wp();
/* Disable update acknowledge interrupt */
regs->RTC_IDR = RTC_IDR_ACKDIS;
k_spin_unlock(&data->lock, key);
return -EAGAIN;
}
regs->RTC_TIMR = rtc_sam_timr_from_tm(timeptr);
regs->RTC_CALR = rtc_sam_calr_from_tm(timeptr);
regs->RTC_CR = 0;
rtc_sam_enable_wp();
regs->RTC_IDR = RTC_IDR_ACKDIS;
k_spin_unlock(&data->lock, key);
return 0;
}
static int rtc_sam_get_time(const struct device *dev, struct rtc_time *timeptr)
{
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
uint32_t timr0;
uint32_t calr0;
uint32_t timr1;
uint32_t calr1;
/* Validate time and date */
if (regs->RTC_VER & (RTC_VER_NVTIM | RTC_VER_NVCAL)) {
return -ENODATA;
}
/* Read until synchronized (registers updated async) */
while (1) {
timr0 = regs->RTC_TIMR;
calr0 = regs->RTC_CALR;
timr1 = regs->RTC_TIMR;
calr1 = regs->RTC_CALR;
if ((timr0 == timr1) && (calr0 == calr1)) {
break;
}
}
timeptr->tm_sec = bcd2bin(RTC_SAM_REG_GET_FIELD(timr0, TIMR_SEC));
timeptr->tm_min = bcd2bin(RTC_SAM_REG_GET_FIELD(timr0, TIMR_MIN));
timeptr->tm_hour = bcd2bin(RTC_SAM_REG_GET_FIELD(timr0, TIMR_HOUR));
timeptr->tm_mday = bcd2bin(RTC_SAM_REG_GET_FIELD(calr0, CALR_DATE));
timeptr->tm_mon = bcd2bin(RTC_SAM_REG_GET_FIELD(calr0, CALR_MONTH)) - 1;
timeptr->tm_year = bcd2bin(RTC_SAM_REG_GET_FIELD(calr0, CALR_YEAR));
timeptr->tm_year += ((int)bcd2bin(RTC_SAM_REG_GET_FIELD(calr0, CALR_CENT))) * 100;
timeptr->tm_year -= 1900;
timeptr->tm_wday = bcd2bin(RTC_SAM_REG_GET_FIELD(calr0, CALR_DAY)) - 1;
timeptr->tm_yday = -1;
timeptr->tm_isdst = -1;
timeptr->tm_nsec = 0;
return 0;
}
static void rtc_sam_isr(const struct device *dev)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
uint32_t sr = regs->RTC_SR;
if (sr & RTC_SR_ACKUPD) {
regs->RTC_SCCR = RTC_SCCR_ACKCLR;
k_sem_give(&data->cr_upd_ack_sem);
}
#ifdef CONFIG_RTC_ALARM
if (sr & RTC_SR_ALARM) {
regs->RTC_SCCR = RTC_SCCR_ALRCLR;
if (data->alarm_callback != NULL) {
data->alarm_callback(dev, 0, data->alarm_user_data);
}
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
if (sr & RTC_SR_SEC) {
regs->RTC_SCCR = RTC_SCCR_SECCLR;
if (data->update_callback != NULL) {
data->update_callback(dev, data->update_user_data);
}
k_sem_give(&data->cr_sec_evt_sem);
}
#endif /* CONFIG_RTC_UPDATE */
}
#ifdef CONFIG_RTC_ALARM
static uint16_t rtc_sam_alarm_get_supported_mask(void)
{
return (RTC_ALARM_TIME_MASK_SECOND
| RTC_ALARM_TIME_MASK_MINUTE
| RTC_ALARM_TIME_MASK_HOUR
| RTC_ALARM_TIME_MASK_MONTHDAY
| RTC_ALARM_TIME_MASK_MONTH);
}
static uint32_t rtc_atmel_timalr_from_tm(const struct rtc_time *timeptr, uint32_t mask)
{
uint32_t timalr = 0;
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
timalr |= RTC_TIMALR_SECEN;
timalr |= RTC_TIMALR_SEC(bin2bcd(timeptr->tm_sec));
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
timalr |= RTC_TIMALR_MINEN;
timalr |= RTC_TIMALR_MIN(bin2bcd(timeptr->tm_min));
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
timalr |= RTC_TIMALR_HOUREN;
timalr |= RTC_TIMALR_HOUR(bin2bcd(timeptr->tm_hour));
}
return timalr;
}
static uint32_t rtc_atmel_calalr_from_tm(const struct rtc_time *timeptr, uint32_t mask)
{
uint32_t calalr = RTC_CALALR_MONTH(1) | RTC_CALALR_DATE(1);
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
calalr |= RTC_CALALR_MTHEN;
calalr |= RTC_CALALR_MONTH(bin2bcd(timeptr->tm_mon + 1));
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
calalr |= RTC_CALALR_DATEEN;
calalr |= RTC_CALALR_DATE(bin2bcd(timeptr->tm_mday));
}
return calalr;
}
static uint32_t rtc_sam_alarm_mask_from_timalr(uint32_t timalr)
{
uint32_t mask = 0;
if (timalr & RTC_TIMALR_SECEN) {
mask |= RTC_ALARM_TIME_MASK_SECOND;
}
if (timalr & RTC_TIMALR_MINEN) {
mask |= RTC_ALARM_TIME_MASK_MINUTE;
}
if (timalr & RTC_TIMALR_HOUREN) {
mask |= RTC_ALARM_TIME_MASK_HOUR;
}
return mask;
}
static uint32_t rtc_sam_alarm_mask_from_calalr(uint32_t calalr)
{
uint32_t mask = 0;
if (calalr & RTC_CALALR_MTHEN) {
mask |= RTC_ALARM_TIME_MASK_MONTH;
}
if (calalr & RTC_CALALR_DATEEN) {
mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
}
return mask;
}
static void rtc_sam_tm_from_timalr_calalr(struct rtc_time *timeptr, uint32_t mask,
uint32_t timalr, uint32_t calalr)
{
memset(timeptr, 0x00, sizeof(*timeptr));
if (mask & RTC_ALARM_TIME_MASK_SECOND) {
timeptr->tm_sec = bcd2bin(RTC_SAM_REG_GET_FIELD(timalr, TIMALR_SEC));
}
if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
timeptr->tm_min = bcd2bin(RTC_SAM_REG_GET_FIELD(timalr, TIMALR_MIN));
}
if (mask & RTC_ALARM_TIME_MASK_HOUR) {
timeptr->tm_hour = bcd2bin(RTC_SAM_REG_GET_FIELD(timalr, TIMALR_HOUR));
}
if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
timeptr->tm_mday = bcd2bin(RTC_SAM_REG_GET_FIELD(calalr, CALALR_DATE));
}
if (mask & RTC_ALARM_TIME_MASK_MONTH) {
timeptr->tm_mon = bcd2bin(RTC_SAM_REG_GET_FIELD(calalr, CALALR_MONTH)) - 1;
}
}
static int rtc_sam_alarm_get_supported_fields(const struct device *dev, uint16_t id,
uint16_t *mask)
{
ARG_UNUSED(dev);
ARG_UNUSED(id);
*mask = rtc_sam_alarm_get_supported_mask();
return 0;
}
static int rtc_sam_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
const struct rtc_time *timeptr)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
uint32_t timalr;
uint32_t calalr;
uint32_t mask_supported;
mask_supported = rtc_sam_alarm_get_supported_mask();
if ((id != 0)) {
return -EINVAL;
}
if ((mask > 0) && (timeptr == NULL)) {
return -EINVAL;
}
if (mask & ~mask_supported) {
return -EINVAL;
}
if (rtc_sam_validate_tm(timeptr, mask) == false) {
return -EINVAL;
}
timalr = rtc_atmel_timalr_from_tm(timeptr, mask);
calalr = rtc_atmel_calalr_from_tm(timeptr, mask);
k_spinlock_key_t key = k_spin_lock(&data->lock);
irq_disable(config->irq_num);
rtc_sam_disable_wp();
/* Set RTC alarm time */
regs->RTC_TIMALR = timalr;
regs->RTC_CALALR = calalr;
rtc_sam_enable_wp();
/* Clear alarm pending status */
regs->RTC_SCCR = RTC_SCCR_ALRCLR;
irq_enable(config->irq_num);
k_spin_unlock(&data->lock, key);
return 0;
}
static int rtc_sam_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
struct rtc_time *timeptr)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
uint32_t timalr;
uint32_t calalr;
if ((id != 0) || (mask == NULL) || (timeptr == NULL)) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
timalr = regs->RTC_TIMALR;
calalr = regs->RTC_CALALR;
k_spin_unlock(&data->lock, key);
*mask = rtc_sam_alarm_mask_from_timalr(timalr);
*mask |= rtc_sam_alarm_mask_from_calalr(calalr);
rtc_sam_tm_from_timalr_calalr(timeptr, *mask, timalr, calalr);
return 0;
}
static int rtc_sam_alarm_is_pending(const struct device *dev, uint16_t id)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
if (id != 0) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
if ((regs->RTC_SR & RTC_SR_ALARM) == 0) {
k_spin_unlock(&data->lock, key);
return 0;
}
regs->RTC_SCCR = RTC_SCCR_ALRCLR;
k_spin_unlock(&data->lock, key);
return 1;
}
static int rtc_sam_alarm_set_callback(const struct device *dev, uint16_t id,
rtc_alarm_callback callback, void *user_data)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
if (id != 0) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
irq_disable(config->irq_num);
data->alarm_callback = callback;
data->alarm_user_data = user_data;
if (data->alarm_callback) {
regs->RTC_IER = RTC_IER_ALREN;
} else {
regs->RTC_IDR = RTC_IDR_ALRDIS;
}
irq_enable(config->irq_num);
k_spin_unlock(&data->lock, key);
return 0;
}
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
static int rtc_sam_update_set_callback(const struct device *dev, rtc_update_callback callback,
void *user_data)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
k_spinlock_key_t key = k_spin_lock(&data->lock);
irq_disable(config->irq_num);
data->update_callback = callback;
data->update_user_data = user_data;
if (data->update_callback) {
regs->RTC_IER = RTC_IER_SECEN;
} else {
regs->RTC_IDR = RTC_IDR_SECDIS;
}
irq_enable(config->irq_num);
k_spin_unlock(&data->lock, key);
return 0;
}
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
static int rtc_sam_set_calibration(const struct device *dev, int32_t calibration)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
bool negative_calibration;
bool high_calibration;
uint32_t slow_clock_calibration;
uint32_t mr;
if ((calibration < RTC_SAM_CALIBRATE_PPB_MIN) ||
(calibration > RTC_SAM_CALIBRATE_PPB_MAX)) {
return -EINVAL;
}
/* The value written to the register is absolute */
if (calibration < 0) {
negative_calibration = true;
calibration = -calibration;
} else {
negative_calibration = false;
}
/*
* Formula adapted from
* your_sha256_hashsheet.pdf
* section 15.6.2
*
* Formula if RTC_MR_HIGHPPM is 0
*
* RTC_MR_CORRECTION = (3906 / (20 * ppm)) - 1
*
* Formula if RTC_MR_HIGHPPM is 1
*
* RTC_MR_CORRECTION = (3906 / ppm) - 1
*
* Since we are working with ppb, we adapt the formula by increasing the
* terms of the fraction by 1000, turning the ppm into ppb
*
* Adapted formula if RTC_MR_HIGHPPM is 0
*
* RTC_MR_CORRECTION = (3906000 / (20 * ppb)) - 1
*
* Adapted formula if RTC_MR_HIGHPPM is 1
*
* RTC_MR_CORRECTION = (3906000 / ppb) - 1
*/
if (calibration < RTC_SAM_CALIBRATE_PPB_QUANTA) {
high_calibration = false;
slow_clock_calibration = 0;
} else if (calibration < RTC_SAM_CALIBRATE_PPB_LOW_SCALE) {
high_calibration = false;
slow_clock_calibration = (uint32_t)((3906000 / (20 * calibration)) - 1);
} else {
high_calibration = true;
slow_clock_calibration = (uint32_t)((3906000 / calibration) - 1);
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
rtc_sam_disable_wp();
mr = regs->RTC_MR;
if (negative_calibration == true) {
mr |= RTC_MR_NEGPPM;
} else {
mr &= ~RTC_MR_NEGPPM;
}
mr &= ~RTC_MR_CORRECTION_Msk;
mr |= RTC_MR_CORRECTION(slow_clock_calibration);
if (high_calibration == true) {
mr |= RTC_MR_HIGHPPM;
} else {
mr &= ~RTC_MR_HIGHPPM;
}
regs->RTC_MR = mr;
rtc_sam_enable_wp();
k_spin_unlock(&data->lock, key);
return 0;
}
static int rtc_sam_get_calibration(const struct device *dev, int32_t *calibration)
{
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
uint32_t mr;
int32_t correction;
if (calibration == NULL) {
return -EINVAL;
}
mr = regs->RTC_MR;
correction = (int32_t)RTC_SAM_REG_GET_FIELD(mr, MR_CORRECTION);
/* Formula documented in rtc_sam_set_calibration() */
if (correction == 0) {
*calibration = 0;
} else if (mr & RTC_MR_HIGHPPM) {
*calibration = 3906000 / (correction + 1);
} else {
*calibration = 3906000 / ((correction + 1) * 20);
}
if (mr & RTC_MR_NEGPPM) {
*calibration = -*calibration;
}
return 0;
}
#endif /* CONFIG_RTC_CALIBRATION */
static const struct rtc_driver_api rtc_sam_driver_api = {
.set_time = rtc_sam_set_time,
.get_time = rtc_sam_get_time,
#ifdef CONFIG_RTC_ALARM
.alarm_get_supported_fields = rtc_sam_alarm_get_supported_fields,
.alarm_set_time = rtc_sam_alarm_set_time,
.alarm_get_time = rtc_sam_alarm_get_time,
.alarm_is_pending = rtc_sam_alarm_is_pending,
.alarm_set_callback = rtc_sam_alarm_set_callback,
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_UPDATE
.update_set_callback = rtc_sam_update_set_callback,
#endif /* CONFIG_RTC_UPDATE */
#ifdef CONFIG_RTC_CALIBRATION
.set_calibration = rtc_sam_set_calibration,
.get_calibration = rtc_sam_get_calibration,
#endif /* CONFIG_RTC_CALIBRATION */
};
static int rtc_sam_init(const struct device *dev)
{
struct rtc_sam_data *data = dev->data;
const struct rtc_sam_config *config = dev->config;
Rtc *regs = config->regs;
rtc_sam_disable_wp();
regs->RTC_MR &= ~(RTC_MR_HRMOD | RTC_MR_PERSIAN);
regs->RTC_CR = 0;
rtc_sam_enable_wp();
regs->RTC_IDR = (RTC_IDR_ACKDIS
| RTC_IDR_ALRDIS
| RTC_IDR_SECDIS
| RTC_IDR_TIMDIS
| RTC_IDR_CALDIS
| RTC_IDR_TDERRDIS);
k_sem_init(&data->cr_sec_evt_sem, 0, 1);
k_sem_init(&data->cr_upd_ack_sem, 0, 1);
config->irq_init_fn_ptr();
irq_enable(config->irq_num);
return 0;
}
#define RTC_SAM_DEVICE(id) \
static void rtc_sam_irq_init_##id(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), \
rtc_sam_isr, DEVICE_DT_INST_GET(id), 0); \
} \
\
static const struct rtc_sam_config rtc_sam_config_##id = { \
.regs = (Rtc *)DT_INST_REG_ADDR(id), \
.irq_num = DT_INST_IRQN(id), \
.irq_init_fn_ptr = rtc_sam_irq_init_##id, \
}; \
\
static struct rtc_sam_data rtc_sam_data_##id; \
\
DEVICE_DT_INST_DEFINE(id, rtc_sam_init, NULL, \
&rtc_sam_data_##id, \
&rtc_sam_config_##id, POST_KERNEL, \
CONFIG_RTC_INIT_PRIORITY, \
&rtc_sam_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RTC_SAM_DEVICE);
``` | /content/code_sandbox/drivers/rtc/rtc_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,192 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_pit
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_pit.h>
#define LOG_MODULE_NAME counter_pit
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL);
/* Device holds a pointer to pointer to data */
#define PIT_CHANNEL_DATA(dev) \
(*(struct nxp_pit_channel_data *const *const)dev->data)
/* Device config->data is an array of data pointers ordered by channel number,
* dev->data is a pointer to one of these pointers in that array,
* so the value of the dev->data - dev->config->data is the channel index
*/
#define PIT_CHANNEL_ID(dev) \
(((struct nxp_pit_channel_data *const *)dev->data) - \
((const struct nxp_pit_config *)dev->config)->data)
struct nxp_pit_channel_data {
uint32_t top;
counter_top_callback_t top_callback;
void *top_user_data;
};
struct nxp_pit_config {
struct counter_config_info info;
PIT_Type *base;
bool enableRunInDebug;
int num_channels;
#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
void (*irq_config_func)(const struct device *dev);
#else
void (**irq_config_func)(const struct device *dev);
#endif
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
struct nxp_pit_channel_data *const *data;
const struct device *const *channels;
};
static uint32_t nxp_pit_get_top_value(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
pit_chnl_t channel = PIT_CHANNEL_ID(dev);
/*
* According to RM, the LDVAL trigger = clock ticks -1
* The underlying HAL driver function PIT_SetTimerPeriod()
* automatically subtracted 1 from the value that ends up in
* LDVAL so for reporting purposes we need to add it back in
* here to by consistent.
*/
return (config->base->CHANNEL[channel].LDVAL + 1);
}
static int nxp_pit_start(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
int channel_id = PIT_CHANNEL_ID(dev);
LOG_DBG("period is %d", nxp_pit_get_top_value(dev));
PIT_EnableInterrupts(config->base, channel_id,
kPIT_TimerInterruptEnable);
PIT_StartTimer(config->base, channel_id);
return 0;
}
static int nxp_pit_stop(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
int channel_id = PIT_CHANNEL_ID(dev);
PIT_DisableInterrupts(config->base, channel_id,
kPIT_TimerInterruptEnable);
PIT_StopTimer(config->base, channel_id);
return 0;
}
static int nxp_pit_get_value(const struct device *dev, uint32_t *ticks)
{
const struct nxp_pit_config *config = dev->config;
int channel_id = PIT_CHANNEL_ID(dev);
*ticks = PIT_GetCurrentTimerCount(config->base, channel_id);
return 0;
}
static int nxp_pit_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct nxp_pit_config *config = dev->config;
struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev);
pit_chnl_t channel = PIT_CHANNEL_ID(dev);
if (cfg->ticks == 0) {
return -EINVAL;
}
data->top_callback = cfg->callback;
data->top_user_data = cfg->user_data;
if (config->base->CHANNEL[channel].TCTRL & PIT_TCTRL_TEN_MASK) {
/* Timer already enabled, check flags before resetting */
if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
return -ENOTSUP;
}
PIT_StopTimer(config->base, channel);
PIT_SetTimerPeriod(config->base, channel, cfg->ticks);
PIT_StartTimer(config->base, channel);
} else {
PIT_SetTimerPeriod(config->base, channel, cfg->ticks);
}
return 0;
}
static uint32_t nxp_pit_get_pending_int(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
uint32_t mask = PIT_TFLG_TIF_MASK;
uint32_t flags;
int channel_id = PIT_CHANNEL_ID(dev);
flags = PIT_GetStatusFlags(config->base, channel_id);
return ((flags & mask) == mask);
}
static uint32_t nxp_pit_get_frequency(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
uint32_t clock_rate;
if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) {
LOG_ERR("Failed to get clock rate");
return 0;
}
return clock_rate;
}
#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
static void nxp_pit_isr(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
uint32_t flags;
LOG_DBG("pit counter isr");
for (int channel_index = 0;
channel_index < config->num_channels;
channel_index++) {
flags = PIT_GetStatusFlags(config->base, channel_index);
if (flags) {
struct nxp_pit_channel_data *data =
PIT_CHANNEL_DATA(config->channels[channel_index]);
PIT_ClearStatusFlags(config->base, channel_index, flags);
data->top_callback(dev, data->top_user_data);
}
}
}
#else
static void nxp_pit_isr(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev);
pit_chnl_t channel = PIT_CHANNEL_ID(dev);
uint32_t flags;
LOG_DBG("pit counter isr");
flags = PIT_GetStatusFlags(config->base, channel);
if (flags) {
PIT_ClearStatusFlags(config->base, channel, flags);
if (data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
}
#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */
static int nxp_pit_init(const struct device *dev)
{
const struct nxp_pit_config *config = dev->config;
pit_config_t pit_config;
uint32_t clock_rate;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("Clock control device not ready");
return -ENODEV;
}
PIT_GetDefaultConfig(&pit_config);
pit_config.enableRunInDebug = config->enableRunInDebug;
PIT_Init(config->base, &pit_config);
clock_rate = nxp_pit_get_frequency(dev);
#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
config->irq_config_func(dev);
for (int channel_index = 0;
channel_index < config->num_channels;
channel_index++) {
PIT_SetTimerPeriod(config->base, channel_index,
USEC_TO_COUNT(config->info.max_top_value, clock_rate));
}
#else
for (int channel_index = 0;
channel_index < config->num_channels;
channel_index++) {
if (config->irq_config_func[channel_index]) {
config->irq_config_func[channel_index](dev);
PIT_SetTimerPeriod(config->base, channel_index,
USEC_TO_COUNT(config->info.max_top_value, clock_rate));
}
}
#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */
return 0;
}
static const struct counter_driver_api nxp_pit_driver_api = {
.start = nxp_pit_start,
.stop = nxp_pit_stop,
.get_value = nxp_pit_get_value,
.set_top_value = nxp_pit_set_top_value,
.get_pending_int = nxp_pit_get_pending_int,
.get_top_value = nxp_pit_get_top_value,
.get_freq = nxp_pit_get_frequency,
};
/* Creates a device for a channel (needed for counter API) */
#define NXP_PIT_CHANNEL_DEV_INIT(node, pit_inst) \
DEVICE_DT_DEFINE(node, NULL, NULL, \
(void *) \
&nxp_pit_##pit_inst##_channel_datas[DT_REG_ADDR(node)], \
&nxp_pit_##pit_inst##_config, \
POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \
&nxp_pit_driver_api);
/* Creates a decleration for each pit channel */
#define NXP_PIT_CHANNEL_DECLARATIONS(node) static struct nxp_pit_channel_data \
nxp_pit_channel_data_##node;
/* Initializes an element of the channel data pointer array */
#define NXP_PIT_INSERT_CHANNEL_INTO_ARRAY(node) \
[DT_REG_ADDR(node)] = \
&nxp_pit_channel_data_##node,
#define NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY(node) \
[DT_REG_ADDR(node)] = DEVICE_DT_GET(node),
#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \
static void nxp_pit_irq_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
DT_INST_IRQ_BY_IDX(n, 0, priority), \
nxp_pit_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
};
#define NXP_PIT_SETUP_IRQ_CONFIG(n) NXP_PIT_IRQ_CONFIG_DECLARATIONS(n);
#define NXP_PIT_SETUP_IRQ_ARRAY(ignored)
#else
#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \
static void nxp_pit_irq_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(n), \
DT_IRQ(n, priority), \
nxp_pit_isr, \
DEVICE_DT_GET(n), 0); \
irq_enable(DT_IRQN(n)); \
};
#define NXP_PIT_SETUP_IRQ_CONFIG(n) \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, NXP_PIT_IRQ_CONFIG_DECLARATIONS);
#define NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY(n) \
[DT_REG_ADDR(n)] = &nxp_pit_irq_config_func_##n,
#define NXP_PIT_SETUP_IRQ_ARRAY(n) \
/* Create Array of IRQs -> 1 irq func per channel */ \
void (*nxp_pit_irq_config_array[DT_INST_FOREACH_CHILD_SEP_VARGS(n, \
DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)]) \
(const struct device *dev) = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY) \
};
#endif
#define COUNTER_NXP_PIT_DEVICE_INIT(n) \
\
/* Setup the IRQ either for parent irq or per channel irq */ \
NXP_PIT_SETUP_IRQ_CONFIG(n) \
\
/* Create channel declarations */ \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_PIT_CHANNEL_DECLARATIONS) \
\
/* Array of channel devices */ \
static struct nxp_pit_channel_data *const \
nxp_pit_##n##_channel_datas \
[DT_INST_FOREACH_CHILD_SEP_VARGS( \
n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_PIT_INSERT_CHANNEL_INTO_ARRAY) \
}; \
\
/* forward declaration */ \
static const struct nxp_pit_config nxp_pit_##n##_config; \
\
/* Create all the channel/counter devices */ \
DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, \
NXP_PIT_CHANNEL_DEV_INIT, n) \
\
/* This channel device array is needed by the module device ISR */ \
const struct device *const nxp_pit_##n##_channels \
[DT_INST_FOREACH_CHILD_SEP_VARGS( \
n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY) \
}; \
\
\
NXP_PIT_SETUP_IRQ_ARRAY(n) \
\
/* This config struct is shared by all the channels and parent device */ \
static const struct nxp_pit_config nxp_pit_##n##_config = { \
.info = { \
.max_top_value = \
DT_INST_PROP(n, max_load_value), \
.channels = 0, \
}, \
.base = (PIT_Type *)DT_INST_REG_ADDR(n), \
.irq_config_func = COND_CODE_1(DT_NODE_HAS_PROP( \
DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts), \
(nxp_pit_irq_config_func_##n), \
(&nxp_pit_irq_config_array[0])), \
.num_channels = DT_INST_FOREACH_CHILD_SEP_VARGS( \
n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t) \
DT_INST_CLOCKS_CELL(n, name), \
.data = nxp_pit_##n##_channel_datas, \
.channels = nxp_pit_##n##_channels, \
}; \
\
/* Init parent device in order to handle ISR and init. */ \
DEVICE_DT_INST_DEFINE(n, &nxp_pit_init, NULL, \
NULL, &nxp_pit_##n##_config, POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(COUNTER_NXP_PIT_DEVICE_INIT)
``` | /content/code_sandbox/drivers/counter/counter_nxp_pit.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,276 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_lptmr)
#define DT_DRV_COMPAT nxp_kinetis_lptmr
#else
#define DT_DRV_COMPAT nxp_lptmr
#endif
#include <zephyr/drivers/counter.h>
#include <zephyr/irq.h>
#include <fsl_lptmr.h>
struct mcux_lptmr_config {
struct counter_config_info info;
LPTMR_Type *base;
lptmr_prescaler_clock_select_t clk_source;
lptmr_prescaler_glitch_value_t prescaler_glitch;
bool bypass_prescaler_glitch;
lptmr_timer_mode_t mode;
lptmr_pin_select_t pin;
lptmr_pin_polarity_t polarity;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_lptmr_data {
counter_top_callback_t top_callback;
void *top_user_data;
};
static int mcux_lptmr_start(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
LPTMR_EnableInterrupts(config->base,
kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(config->base);
return 0;
}
static int mcux_lptmr_stop(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
LPTMR_DisableInterrupts(config->base,
kLPTMR_TimerInterruptEnable);
LPTMR_StopTimer(config->base);
return 0;
}
static int mcux_lptmr_get_value(const struct device *dev, uint32_t *ticks)
{
const struct mcux_lptmr_config *config = dev->config;
*ticks = LPTMR_GetCurrentTimerCount(config->base);
return 0;
}
static int mcux_lptmr_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct mcux_lptmr_config *config = dev->config;
struct mcux_lptmr_data *data = dev->data;
if (cfg->ticks == 0) {
return -EINVAL;
}
data->top_callback = cfg->callback;
data->top_user_data = cfg->user_data;
if (config->base->CSR & LPTMR_CSR_TEN_MASK) {
/* Timer already enabled, check flags before resetting */
if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
return -ENOTSUP;
}
LPTMR_StopTimer(config->base);
LPTMR_SetTimerPeriod(config->base, cfg->ticks);
LPTMR_StartTimer(config->base);
} else {
LPTMR_SetTimerPeriod(config->base, cfg->ticks);
}
return 0;
}
static uint32_t mcux_lptmr_get_pending_int(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
uint32_t mask = LPTMR_CSR_TCF_MASK | LPTMR_CSR_TIE_MASK;
uint32_t flags;
flags = LPTMR_GetStatusFlags(config->base);
return ((flags & mask) == mask);
}
static uint32_t mcux_lptmr_get_top_value(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
return (config->base->CMR & LPTMR_CMR_COMPARE_MASK) + 1U;
}
static void mcux_lptmr_isr(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
struct mcux_lptmr_data *data = dev->data;
uint32_t flags;
flags = LPTMR_GetStatusFlags(config->base);
LPTMR_ClearStatusFlags(config->base, flags);
if (data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
static int mcux_lptmr_init(const struct device *dev)
{
const struct mcux_lptmr_config *config = dev->config;
lptmr_config_t lptmr_config;
LPTMR_GetDefaultConfig(&lptmr_config);
lptmr_config.timerMode = config->mode;
lptmr_config.enableFreeRunning = false;
lptmr_config.prescalerClockSource = config->clk_source;
lptmr_config.bypassPrescaler = config->bypass_prescaler_glitch;
lptmr_config.value = config->prescaler_glitch;
if (config->mode == kLPTMR_TimerModePulseCounter) {
lptmr_config.pinSelect = config->pin;
lptmr_config.pinPolarity = config->polarity;
}
LPTMR_Init(config->base, &lptmr_config);
LPTMR_SetTimerPeriod(config->base, config->info.max_top_value);
config->irq_config_func(dev);
return 0;
}
static const struct counter_driver_api mcux_lptmr_driver_api = {
.start = mcux_lptmr_start,
.stop = mcux_lptmr_stop,
.get_value = mcux_lptmr_get_value,
.set_top_value = mcux_lptmr_set_top_value,
.get_pending_int = mcux_lptmr_get_pending_int,
.get_top_value = mcux_lptmr_get_top_value,
};
#define TO_LPTMR_CLK_SEL(val) _DO_CONCAT(kLPTMR_PrescalerClock_, val)
#define TO_LPTMR_PIN_SEL(val) _DO_CONCAT(kLPTMR_PinSelectInput_, val)
/* Prescaler mapping */
#define LPTMR_PRESCALER_2 kLPTMR_Prescale_Glitch_0
#define LPTMR_PRESCALER_4 kLPTMR_Prescale_Glitch_1
#define LPTMR_PRESCALER_8 kLPTMR_Prescale_Glitch_2
#define LPTMR_PRESCALER_16 kLPTMR_Prescale_Glitch_3
#define LPTMR_PRESCALER_32 kLPTMR_Prescale_Glitch_4
#define LPTMR_PRESCALER_64 kLPTMR_Prescale_Glitch_5
#define LPTMR_PRESCALER_128 kLPTMR_Prescale_Glitch_6
#define LPTMR_PRESCALER_256 kLPTMR_Prescale_Glitch_7
#define LPTMR_PRESCALER_512 kLPTMR_Prescale_Glitch_8
#define LPTMR_PRESCALER_1024 kLPTMR_Prescale_Glitch_9
#define LPTMR_PRESCALER_2048 kLPTMR_Prescale_Glitch_10
#define LPTMR_PRESCALER_4096 kLPTMR_Prescale_Glitch_11
#define LPTMR_PRESCALER_8192 kLPTMR_Prescale_Glitch_12
#define LPTMR_PRESCALER_16384 kLPTMR_Prescale_Glitch_13
#define LPTMR_PRESCALER_32768 kLPTMR_Prescale_Glitch_14
#define LPTMR_PRESCALER_65536 kLPTMR_Prescale_Glitch_15
#define TO_LPTMR_PRESCALER(val) _DO_CONCAT(LPTMR_PRESCALER_, val)
/* Glitch filter mapping */
#define LPTMR_GLITCH_2 kLPTMR_Prescale_Glitch_1
#define LPTMR_GLITCH_4 kLPTMR_Prescale_Glitch_2
#define LPTMR_GLITCH_8 kLPTMR_Prescale_Glitch_3
#define LPTMR_GLITCH_16 kLPTMR_Prescale_Glitch_4
#define LPTMR_GLITCH_32 kLPTMR_Prescale_Glitch_5
#define LPTMR_GLITCH_64 kLPTMR_Prescale_Glitch_6
#define LPTMR_GLITCH_128 kLPTMR_Prescale_Glitch_7
#define LPTMR_GLITCH_256 kLPTMR_Prescale_Glitch_8
#define LPTMR_GLITCH_512 kLPTMR_Prescale_Glitch_9
#define LPTMR_GLITCH_1024 kLPTMR_Prescale_Glitch_10
#define LPTMR_GLITCH_2048 kLPTMR_Prescale_Glitch_11
#define LPTMR_GLITCH_4096 kLPTMR_Prescale_Glitch_12
#define LPTMR_GLITCH_8192 kLPTMR_Prescale_Glitch_13
#define LPTMR_GLITCH_16384 kLPTMR_Prescale_Glitch_14
#define LPTMR_GLITCH_32768 kLPTMR_Prescale_Glitch_15
#define TO_LPTMR_GLITCH(val) _DO_CONCAT(LPTMR_GLITCH_, val)
/*
* This driver is single-instance. If the devicetree contains multiple
* instances, this will fail and the driver needs to be revisited.
*/
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
"unsupported lptmr instance");
#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
static struct mcux_lptmr_data mcux_lptmr_data_0;
static void mcux_lptmr_irq_config_0(const struct device *dev);
static struct mcux_lptmr_config mcux_lptmr_config_0 = {
.info = {
.max_top_value = ((DT_INST_PROP(0, resolution) == 32)
? UINT32_MAX : UINT16_MAX),
.freq = DT_INST_PROP(0, clock_frequency) /
DT_INST_PROP(0, prescaler),
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = 0,
},
.base = (LPTMR_Type *)DT_INST_REG_ADDR(0),
.clk_source = TO_LPTMR_CLK_SEL(DT_INST_PROP(0, clk_source)),
#if DT_INST_NODE_HAS_PROP(0, input_pin)
#if DT_INST_PROP(0, prescaler) == 1
.bypass_prescaler_glitch = true,
#else
.prescaler_glitch = TO_LPTMR_GLITCH(DT_INST_PROP(0, prescaler)),
#endif
.mode = kLPTMR_TimerModePulseCounter,
.pin = TO_LPTMR_PIN_SEL(DT_INST_PROP(0, input_pin)),
.polarity = DT_INST_PROP(0, active_low),
#else /* !DT_INST_NODE_HAS_PROP(0, input_pin) */
.mode = kLPTMR_TimerModeTimeCounter,
#if DT_INST_PROP(0, prescaler) == 1
.bypass_prescaler_glitch = true,
#else
.prescaler_glitch = TO_LPTMR_PRESCALER(DT_INST_PROP(0, prescaler)),
#endif
#endif /* !DT_INST_NODE_HAS_PROP(0, input_pin) */
.irq_config_func = mcux_lptmr_irq_config_0,
};
DEVICE_DT_INST_DEFINE(0, &mcux_lptmr_init, NULL,
&mcux_lptmr_data_0,
&mcux_lptmr_config_0,
POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY,
&mcux_lptmr_driver_api);
static void mcux_lptmr_irq_config_0(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
mcux_lptmr_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
``` | /content/code_sandbox/drivers/counter/counter_mcux_lptmr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,531 |
```unknown
config COUNTER_MCUX_LPC_RTC
bool "MCUX LPC RTC driver"
default y
depends on DT_HAS_NXP_LPC_RTC_ENABLED || \
DT_HAS_NXP_LPC_RTC_HIGHRES_ENABLED
help
Enable the LPC rtc driver.
config COUNTER_MCUX_LPC_RTC_1HZ
bool "MCUX LPC RTC 1Hz counter driver"
default y
depends on DT_HAS_NXP_LPC_RTC_ENABLED
help
Enable support for LPC 1Hz counter.
config COUNTER_MCUX_LPC_RTC_HIGHRES
bool "MCUX LPC RTC High Resolution counter driver"
default y
depends on DT_HAS_NXP_LPC_RTC_HIGHRES_ENABLED
help
Enable support for LPC rtc high resolution counter.
``` | /content/code_sandbox/drivers/counter/Kconfig.mcux_lpc_rtc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 158 |
```unknown
# Kconfig Andes ATCPIT100 configuration option
#
#
config COUNTER_ANDES_ATCPIT100
bool "Andes ATCPIT100 PIT driver"
default y
depends on DT_HAS_ANDESTECH_ATCPIT100_ENABLED
help
Enable driver for the Andes ATCPIT100 PIT controller.
``` | /content/code_sandbox/drivers/counter/Kconfig.andes_atcpit100 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_cmsdk_timer
#include <zephyr/drivers/counter.h>
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/arm_clock_control.h>
#include "timer_cmsdk_apb.h"
typedef void (*timer_config_func_t)(const struct device *dev);
struct tmr_cmsdk_apb_cfg {
struct counter_config_info info;
volatile struct timer_cmsdk_apb *timer;
timer_config_func_t timer_config_func;
/* Timer Clock control in Active State */
const struct arm_clock_control_t timer_cc_as;
/* Timer Clock control in Sleep State */
const struct arm_clock_control_t timer_cc_ss;
/* Timer Clock control in Deep Sleep State */
const struct arm_clock_control_t timer_cc_dss;
};
struct tmr_cmsdk_apb_dev_data {
counter_top_callback_t top_callback;
void *top_user_data;
uint32_t load;
};
static int tmr_cmsdk_apb_start(const struct device *dev)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
struct tmr_cmsdk_apb_dev_data *data = dev->data;
/* Set the timer reload to count */
cfg->timer->reload = data->load;
cfg->timer->ctrl = TIMER_CTRL_EN;
return 0;
}
static int tmr_cmsdk_apb_stop(const struct device *dev)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
/* Disable the timer */
cfg->timer->ctrl = 0x0;
return 0;
}
static int tmr_cmsdk_apb_get_value(const struct device *dev, uint32_t *ticks)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
struct tmr_cmsdk_apb_dev_data *data = dev->data;
/* Get Counter Value */
*ticks = data->load - cfg->timer->value;
return 0;
}
static int tmr_cmsdk_apb_set_top_value(const struct device *dev,
const struct counter_top_cfg *top_cfg)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
struct tmr_cmsdk_apb_dev_data *data = dev->data;
/* Counter is always reset when top value is updated. */
if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
return -ENOTSUP;
}
data->top_callback = top_cfg->callback;
data->top_user_data = top_cfg->user_data;
/* Store the reload value */
data->load = top_cfg->ticks;
/* Set value register to count */
cfg->timer->value = top_cfg->ticks;
/* Set the timer reload to count */
cfg->timer->reload = top_cfg->ticks;
/* Enable IRQ */
cfg->timer->ctrl |= TIMER_CTRL_IRQ_EN;
return 0;
}
static uint32_t tmr_cmsdk_apb_get_top_value(const struct device *dev)
{
struct tmr_cmsdk_apb_dev_data *data = dev->data;
uint32_t ticks = data->load;
return ticks;
}
static uint32_t tmr_cmsdk_apb_get_pending_int(const struct device *dev)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
return cfg->timer->intstatus;
}
static const struct counter_driver_api tmr_cmsdk_apb_api = {
.start = tmr_cmsdk_apb_start,
.stop = tmr_cmsdk_apb_stop,
.get_value = tmr_cmsdk_apb_get_value,
.set_top_value = tmr_cmsdk_apb_set_top_value,
.get_pending_int = tmr_cmsdk_apb_get_pending_int,
.get_top_value = tmr_cmsdk_apb_get_top_value,
};
static void tmr_cmsdk_apb_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
struct tmr_cmsdk_apb_dev_data *data = dev->data;
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
cfg->timer->intclear = TIMER_CTRL_INT_CLEAR;
if (data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
static int tmr_cmsdk_apb_init(const struct device *dev)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config;
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
if (!device_is_ready(clk)) {
return -ENODEV;
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_as);
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */
cfg->timer_config_func(dev);
return 0;
}
#define TIMER_CMSDK_INIT(inst) \
static void timer_cmsdk_apb_config_##inst(const struct device *dev); \
\
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_##inst = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 24000000U, \
.flags = 0, \
.channels = 0U, \
}, \
.timer = ((volatile struct timer_cmsdk_apb *)DT_INST_REG_ADDR(inst)), \
.timer_config_func = timer_cmsdk_apb_config_##inst, \
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(inst),}, \
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
}; \
\
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_##inst = { \
.load = UINT32_MAX, \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
tmr_cmsdk_apb_init, \
NULL, \
&tmr_cmsdk_apb_dev_data_##inst, \
&tmr_cmsdk_apb_cfg_##inst, POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, \
&tmr_cmsdk_apb_api); \
\
static void timer_cmsdk_apb_config_##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
tmr_cmsdk_apb_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
}
DT_INST_FOREACH_STATUS_OKAY(TIMER_CMSDK_INIT)
``` | /content/code_sandbox/drivers/counter/timer_tmr_cmsdk_apb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,648 |
```unknown
# STM32 Cube LL RTC
menuconfig COUNTER_RTC_STM32
bool "STM32 Counter RTC driver"
default y if !RTC
depends on DT_HAS_ST_STM32_RTC_ENABLED
select USE_STM32_LL_RTC
select USE_STM32_LL_PWR
select USE_STM32_LL_RCC
select USE_STM32_LL_EXTI
help
Build RTC driver for STM32 SoCs.
Tested on STM32 C0, F0, F2, F3, F4, F7, G0, G4, H7, L1, L4, L5, U5 series
if COUNTER_RTC_STM32
config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS
bool "Save rtc time value between resets"
default n
help
Keep the counter value after each reset.
config COUNTER_RTC_STM32_SUBSECONDS
bool "Use the subseconds as a basic tick."
depends on !SOC_SERIES_STM32F1X
help
Use the subseconds as the basic time tick. It increases resolution
of the counter. The frequency of the time is RTC Source Clock divided
by 2. It is the clock after the first asynchronous prescaler.
The config increases power consumption.
endif # COUNTER_RTC_STM32
``` | /content/code_sandbox/drivers/counter/Kconfig.stm32_rtc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 280 |
```c
/*
*
*/
#define DT_DRV_COMPAT ambiq_counter
#include <zephyr/drivers/counter.h>
#include <zephyr/spinlock.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
/* ambiq-sdk includes */
#include <am_mcu_apollo.h>
LOG_MODULE_REGISTER(ambiq_counter, CONFIG_COUNTER_LOG_LEVEL);
static void counter_ambiq_isr(void *arg);
struct counter_ambiq_config {
struct counter_config_info counter_info;
uint32_t instance;
uint32_t clk_src;
void (*irq_config_func)(void);
};
struct counter_ambiq_data {
counter_alarm_callback_t callback;
void *user_data;
};
static struct k_spinlock lock;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
static void counter_irq_config_func(void)
{
/* Apollo3 counters share the same irq number, connect to counter0 once when init and handle
* different banks in counter_ambiq_isr
*/
static bool global_irq_init = true;
if (!global_irq_init) {
return;
}
global_irq_init = false;
/* Shared irq config default to ctimer0. */
NVIC_ClearPendingIRQ(CTIMER_IRQn);
IRQ_CONNECT(CTIMER_IRQn, DT_INST_IRQ(0, priority), counter_ambiq_isr, DEVICE_DT_INST_GET(0),
0);
irq_enable(CTIMER_IRQn);
};
#endif
static int counter_ambiq_init(const struct device *dev)
{
k_spinlock_key_t key = k_spin_lock(&lock);
const struct counter_ambiq_config *cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
/* Timer configuration */
am_hal_ctimer_config_t sContTimer;
/* Create 32-bit timer */
sContTimer.ui32Link = 1;
/* Set up TimerA. */
sContTimer.ui32TimerAConfig = (AM_HAL_CTIMER_FN_REPEAT | AM_HAL_CTIMER_INT_ENABLE |
(cfg->clk_src << CTIMER_CTRL0_TMRA0CLK_Pos));
/* Set up TimerB. */
sContTimer.ui32TimerBConfig = 0;
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
am_hal_ctimer_clear(cfg->instance, AM_HAL_CTIMER_BOTH);
am_hal_ctimer_config(cfg->instance, &sContTimer);
counter_irq_config_func();
#else
am_hal_timer_config_t tc;
am_hal_timer_default_config_set(&tc);
tc.eInputClock = cfg->clk_src;
tc.eFunction = AM_HAL_TIMER_FN_UPCOUNT;
tc.ui32PatternLimit = 0;
am_hal_timer_config(cfg->instance, &tc);
cfg->irq_config_func();
#endif
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_start(const struct device *dev)
{
const struct counter_ambiq_config *cfg = dev->config;
k_spinlock_key_t key = k_spin_lock(&lock);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_ctimer_start(cfg->instance, AM_HAL_CTIMER_TIMERA);
#else
am_hal_timer_start(cfg->instance);
#endif
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_stop(const struct device *dev)
{
const struct counter_ambiq_config *cfg = dev->config;
k_spinlock_key_t key = k_spin_lock(&lock);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_ctimer_stop(cfg->instance, AM_HAL_CTIMER_BOTH);
#else
am_hal_timer_stop(cfg->instance);
#endif
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_get_value(const struct device *dev, uint32_t *ticks)
{
const struct counter_ambiq_config *cfg = dev->config;
k_spinlock_key_t key = k_spin_lock(&lock);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
*ticks = (am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERA)) |
(am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERB) << 16);
#else
*ticks = am_hal_timer_read(cfg->instance);
#endif
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
ARG_UNUSED(chan_id);
struct counter_ambiq_data *data = dev->data;
const struct counter_ambiq_config *cfg = dev->config;
uint32_t now;
counter_ambiq_get_value(dev, &now);
k_spinlock_key_t key = k_spin_lock(&lock);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_ctimer_int_clear(AM_HAL_CTIMER_INT_TIMERA0C0);
am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA0C0);
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0,
now + alarm_cfg->ticks);
} else {
am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, alarm_cfg->ticks);
}
#else
/* Enable interrupt, due to counter_ambiq_cancel_alarm() disables it*/
am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
am_hal_timer_interrupt_enable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
am_hal_timer_compare1_set(cfg->instance, now + alarm_cfg->ticks);
} else {
am_hal_timer_compare1_set(cfg->instance, alarm_cfg->ticks);
}
#endif
data->user_data = alarm_cfg->user_data;
data->callback = alarm_cfg->callback;
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
ARG_UNUSED(chan_id);
const struct counter_ambiq_config *cfg = dev->config;
k_spinlock_key_t key = k_spin_lock(&lock);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_ctimer_int_disable(AM_HAL_CTIMER_INT_TIMERA0C0);
/* Reset the compare register */
am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, 0);
#else
am_hal_timer_interrupt_disable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
/* Reset the compare register */
am_hal_timer_compare1_set(cfg->instance, 0);
#endif
k_spin_unlock(&lock, key);
return 0;
}
static int counter_ambiq_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
{
const struct counter_ambiq_config *config = dev->config;
if (cfg->ticks != config->counter_info.max_top_value) {
return -ENOTSUP;
} else {
return 0;
}
}
static uint32_t counter_ambiq_get_pending_int(const struct device *dev)
{
return 0;
}
static uint32_t counter_ambiq_get_top_value(const struct device *dev)
{
const struct counter_ambiq_config *config = dev->config;
return config->counter_info.max_top_value;
}
static const struct counter_driver_api counter_api = {
.start = counter_ambiq_start,
.stop = counter_ambiq_stop,
.get_value = counter_ambiq_get_value,
.set_alarm = counter_ambiq_set_alarm,
.cancel_alarm = counter_ambiq_cancel_alarm,
.set_top_value = counter_ambiq_set_top_value,
.get_pending_int = counter_ambiq_get_pending_int,
.get_top_value = counter_ambiq_get_top_value,
};
#define APOLLO3_HANDLE_SHARED_TIMER_IRQ(n) \
static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
struct counter_ambiq_data *const data_##n = dev_##n->data; \
uint32_t status_##n = CTIMERn(n)->INTSTAT; \
status_##n &= CTIMERn(n)->INTEN; \
if (status_##n) { \
CTIMERn(n)->INTCLR = AM_HAL_CTIMER_INT_TIMERA0C0; \
counter_ambiq_get_value(dev_##n, &now); \
if (data_##n->callback) { \
data_##n->callback(dev_##n, 0, now, data_##n->user_data); \
} \
}
static void counter_ambiq_isr(void *arg)
{
uint32_t now = 0;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
ARG_UNUSED(arg);
DT_INST_FOREACH_STATUS_OKAY(APOLLO3_HANDLE_SHARED_TIMER_IRQ)
#else
const struct device *dev = (const struct device *)arg;
struct counter_ambiq_data *data = dev->data;
const struct counter_ambiq_config *cfg = dev->config;
am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
counter_ambiq_get_value(dev, &now);
if (data->callback) {
data->callback(dev, 0, now, data->user_data);
}
#endif
}
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
/* Apollo3 counters share the same irq number, connect irq here will cause build error, so we
* leave this function blank here and do it in counter_irq_config_func
*/
#define AMBIQ_COUNTER_CONFIG_FUNC(idx) static void counter_irq_config_func_##idx(void){};
#else
#define AMBIQ_COUNTER_CONFIG_FUNC(idx) \
static void counter_irq_config_func_##idx(void) \
{ \
NVIC_ClearPendingIRQ(DT_INST_IRQN(idx)); \
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), counter_ambiq_isr, \
DEVICE_DT_INST_GET(idx), 0); \
irq_enable(DT_INST_IRQN(idx)); \
};
#endif
#define AMBIQ_COUNTER_INIT(idx) \
static void counter_irq_config_func_##idx(void); \
static struct counter_ambiq_data counter_data_##idx; \
static const struct counter_ambiq_config counter_config_##idx = { \
.instance = (DT_INST_REG_ADDR(idx) - DT_INST_REG_ADDR(0)) / DT_INST_REG_SIZE(idx), \
.clk_src = DT_INST_PROP(idx, clk_source), \
.counter_info = {.max_top_value = UINT32_MAX, \
.freq = DT_INST_PROP(idx, clock_frequency), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1}, \
.irq_config_func = counter_irq_config_func_##idx, \
}; \
AMBIQ_COUNTER_CONFIG_FUNC(idx) \
DEVICE_DT_INST_DEFINE(idx, counter_ambiq_init, NULL, &counter_data_##idx, \
&counter_config_##idx, PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&counter_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_COUNTER_INIT);
``` | /content/code_sandbox/drivers/counter/counter_ambiq_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,450 |
```unknown
#
config COUNTER_AMBIQ
bool "Ambiq Counter Driver"
default y
depends on DT_HAS_AMBIQ_COUNTER_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_TIMER
help
Enables the Counter driver for Ambiq devices.
``` | /content/code_sandbox/drivers/counter/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
config COUNTER_TIMER_STM32
bool "STM32 counter driver"
default y
depends on DT_HAS_ST_STM32_COUNTER_ENABLED
select USE_STM32_LL_TIM
select RESET
help
Enable the counter driver for STM32 family of processors.
``` | /content/code_sandbox/drivers/counter/Kconfig.stm32_timer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_cmsdk_dtimer
#include <limits.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/arm_clock_control.h>
#include <zephyr/irq.h>
#include "dualtimer_cmsdk_apb.h"
typedef void (*dtimer_config_func_t)(const struct device *dev);
struct dtmr_cmsdk_apb_cfg {
struct counter_config_info info;
volatile struct dualtimer_cmsdk_apb *dtimer;
dtimer_config_func_t dtimer_config_func;
/* Dualtimer Clock control in Active State */
const struct arm_clock_control_t dtimer_cc_as;
/* Dualtimer Clock control in Sleep State */
const struct arm_clock_control_t dtimer_cc_ss;
/* Dualtimer Clock control in Deep Sleep State */
const struct arm_clock_control_t dtimer_cc_dss;
};
struct dtmr_cmsdk_apb_dev_data {
counter_top_callback_t top_callback;
void *top_user_data;
uint32_t load;
};
static int dtmr_cmsdk_apb_start(const struct device *dev)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
struct dtmr_cmsdk_apb_dev_data *data = dev->data;
/* Set the timer reload to count */
cfg->dtimer->timer1load = data->load;
/* Enable the dualtimer in 32 bit mode */
cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32);
return 0;
}
static int dtmr_cmsdk_apb_stop(const struct device *dev)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
/* Disable the dualtimer */
cfg->dtimer->timer1ctrl = 0x0;
return 0;
}
static int dtmr_cmsdk_apb_get_value(const struct device *dev, uint32_t *ticks)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
struct dtmr_cmsdk_apb_dev_data *data = dev->data;
*ticks = data->load - cfg->dtimer->timer1value;
return 0;
}
static int dtmr_cmsdk_apb_set_top_value(const struct device *dev,
const struct counter_top_cfg *top_cfg)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
struct dtmr_cmsdk_apb_dev_data *data = dev->data;
data->top_callback = top_cfg->callback;
data->top_user_data = top_cfg->user_data;
/* Store the reload value */
data->load = top_cfg->ticks;
/* Set the timer to count */
if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
/*
* Write to background load register will not affect
* the current value of the counter.
*/
cfg->dtimer->timer1bgload = top_cfg->ticks;
} else {
/*
* Write to load register will also set
* the current value of the counter.
*/
cfg->dtimer->timer1load = top_cfg->ticks;
}
/* Enable IRQ */
cfg->dtimer->timer1ctrl |= (DUALTIMER_CTRL_INTEN
| DUALTIMER_CTRL_MODE);
return 0;
}
static uint32_t dtmr_cmsdk_apb_get_top_value(const struct device *dev)
{
struct dtmr_cmsdk_apb_dev_data *data = dev->data;
uint32_t ticks = data->load;
return ticks;
}
static uint32_t dtmr_cmsdk_apb_get_pending_int(const struct device *dev)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
return cfg->dtimer->timer1ris;
}
static const struct counter_driver_api dtmr_cmsdk_apb_api = {
.start = dtmr_cmsdk_apb_start,
.stop = dtmr_cmsdk_apb_stop,
.get_value = dtmr_cmsdk_apb_get_value,
.set_top_value = dtmr_cmsdk_apb_set_top_value,
.get_pending_int = dtmr_cmsdk_apb_get_pending_int,
.get_top_value = dtmr_cmsdk_apb_get_top_value,
};
static void dtmr_cmsdk_apb_isr(const struct device *dev)
{
struct dtmr_cmsdk_apb_dev_data *data = dev->data;
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
cfg->dtimer->timer1intclr = DUALTIMER_INTCLR;
if (data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
static int dtmr_cmsdk_apb_init(const struct device *dev)
{
const struct dtmr_cmsdk_apb_cfg * const cfg = dev->config;
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
if (!device_is_ready(clk)) {
return -ENODEV;
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_as);
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */
cfg->dtimer_config_func(dev);
return 0;
}
#define DTIMER_CMSDK_REG(inst) \
((volatile struct dualtimer_cmsdk_apb *)DT_INST_REG_ADDR(inst))
#define DTIMER_CMSDK_INIT(inst) \
static void dtimer_cmsdk_apb_config_##inst(const struct device *dev); \
\
static const struct dtmr_cmsdk_apb_cfg \
dtmr_cmsdk_apb_cfg_##inst = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = 24000000U, \
.flags = 0, \
.channels = 0U, \
}, \
.dtimer = DTIMER_CMSDK_REG(inst), \
.dtimer_config_func = dtimer_cmsdk_apb_config_##inst, \
.dtimer_cc_as = {.bus = CMSDK_APB, \
.state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(inst),}, \
.dtimer_cc_ss = {.bus = CMSDK_APB, \
.state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
.dtimer_cc_dss = {.bus = CMSDK_APB, \
.state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(inst),}, \
}; \
\
static struct dtmr_cmsdk_apb_dev_data \
dtmr_cmsdk_apb_dev_data_##inst = { \
.load = UINT_MAX, \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
dtmr_cmsdk_apb_init, \
NULL, \
&dtmr_cmsdk_apb_dev_data_##inst, \
&dtmr_cmsdk_apb_cfg_##inst, POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, \
&dtmr_cmsdk_apb_api); \
\
static void dtimer_cmsdk_apb_config_##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
dtmr_cmsdk_apb_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
}
DT_INST_FOREACH_STATUS_OKAY(DTIMER_CMSDK_INIT)
``` | /content/code_sandbox/drivers/counter/timer_dtmr_cmsdk_apb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,805 |
```c
/*
*
*/
/*
* MRT (Multirate timer) is a lightweight timer with multiple independent channels, each capable
* of signalling the shared interrupt with a different period. This driver treats all the channels
* as separate devices adhering to the counter API. The parent device is responsible for the
* initialization, interrupt handling, and any other module-wide tasks. The current implementation
* of this driver prioritizes minimizing image size over speed, because it is not expected for the
* functions to be called very often, and this IP is mostly present on low memory devices.
*/
#define DT_DRV_COMPAT nxp_mrt
#include <zephyr/drivers/counter.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/devicetree.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/reset.h>
#include <soc.h>
#define LOG_MODULE_NAME counter_mrt
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL);
/* Device holds a pointer to pointer to data */
#define MRT_CHANNEL_DATA(dev) \
(*(struct nxp_mrt_channel_data *const *const)dev->data)
/* Device config->data is an array of data pointers ordered by channel number,
* dev->data is a pointer to one of these pointers in that array,
* so the value of the dev->data - dev->config->data is the channel index
*/
#define MRT_CHANNEL_ID(dev) \
(((struct nxp_mrt_channel_data *const *)dev->data) - \
((const struct nxp_mrt_config *)dev->config)->data)
/* Specific for each channel */
struct nxp_mrt_channel_data {
uint32_t top;
counter_top_callback_t cb;
void *user_data;
};
/* Shared between all channels */
struct nxp_mrt_config {
struct counter_config_info info;
MRT_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
void (*irq_config_func)(const struct device *dev);
struct nxp_mrt_channel_data *const *data;
const struct device *const *channels;
const struct reset_dt_spec reset;
};
static int nxp_mrt_stop(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
int channel_id = MRT_CHANNEL_ID(dev);
LOG_DBG("MRT@%p channel %d stopped", base, channel_id);
LOG_WRN("MRT channel resets upon stopping");
/* LOAD bit and 0 ivalue allows us to forcibly stop the timer */
base->CHANNEL[channel_id].INTVAL = MRT_CHANNEL_INTVAL_LOAD(1);
return 0;
}
static int nxp_mrt_start(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
struct nxp_mrt_channel_data *data = MRT_CHANNEL_DATA(dev);
int channel_id = MRT_CHANNEL_ID(dev);
if (data->top <= 1) {
/* Zephyr API says default should be max top value */
LOG_INF("\"Started\" MRT@%p channel %d with default value %d",
base, channel_id, config->info.max_top_value);
data->top = config->info.max_top_value;
}
/* Start with previously configured top value (if already running this has no effect) */
base->CHANNEL[channel_id].INTVAL = data->top;
LOG_DBG("MRT@%p channel %d started with top value %d", base, channel_id, data->top);
return 0;
}
static int nxp_mrt_get_value(const struct device *dev, uint32_t *ticks)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
int channel_id = MRT_CHANNEL_ID(dev);
*ticks = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK;
return 0;
}
static int nxp_mrt_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
struct nxp_mrt_channel_data *data = MRT_CHANNEL_DATA(dev);
int channel_id = MRT_CHANNEL_ID(dev);
/* By default in Zephyr API, the counter resets on changing top value */
bool reset = !(cfg->flags & COUNTER_TOP_CFG_DONT_RESET);
bool active = base->CHANNEL[channel_id].STAT & MRT_CHANNEL_STAT_RUN_MASK;
uint32_t current_val = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK;
int ret = 0;
/* Store for use by counter_start */
data->top = cfg->ticks;
/* Used by ISR */
data->cb = cfg->callback;
data->user_data = cfg->user_data;
/* If not yet started, wait for counter_start because setting reg value starts timer */
if (!active) {
LOG_DBG("Set MRT@%p channel %d top value to %d", base, channel_id, data->top);
return ret;
}
/* Otherwise if currently running, need to check for lateness */
if (cfg->ticks < current_val) {
LOG_WRN("MRT@%p channel %d received requested top value %d which is "
"smaller than current count %d",
base, channel_id, cfg->ticks, current_val);
/* Zephyr API says return this error in case of lateness
* when COUNTER_TOP_CFG_DONT_RESET is set but can still set period
*/
ret = reset ? 0 : -ETIME;
/* If user said not to reset, they can also clarify exception for lateness */
reset |= cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE;
}
/* Sets the top value. If we need to reset, LOAD bit does this */
base->CHANNEL[channel_id].INTVAL = MRT_CHANNEL_INTVAL_IVALUE(cfg->ticks) |
MRT_CHANNEL_INTVAL_LOAD(reset ? 1 : 0);
LOG_DBG("Changed MRT@%p channel %d top value while active to %d",
base, channel_id,
base->CHANNEL[channel_id].INTVAL & MRT_CHANNEL_INTVAL_IVALUE_MASK);
return ret;
}
static uint32_t nxp_mrt_get_top_value(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
int channel_id = MRT_CHANNEL_ID(dev);
return base->CHANNEL[channel_id].INTVAL & MRT_CHANNEL_INTVAL_IVALUE_MASK;
}
static uint32_t nxp_mrt_get_pending_int(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
int channel_id = MRT_CHANNEL_ID(dev);
return base->CHANNEL[channel_id].STAT & MRT_CHANNEL_STAT_INTFLAG_MASK;
}
static inline int nxp_mrt_set_alarm(const struct device *dev,
uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
ARG_UNUSED(dev);
ARG_UNUSED(chan_id);
ARG_UNUSED(alarm_cfg);
LOG_ERR("MRT does not support alarms");
return -ENOTSUP;
}
static inline int nxp_mrt_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
ARG_UNUSED(dev);
ARG_UNUSED(chan_id);
LOG_ERR("MRT does not support alarms");
return -ENOTSUP;
}
uint32_t nxp_mrt_get_freq(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
uint32_t freq;
clock_control_get_rate(config->clock_dev, config->clock_subsys, &freq);
return freq;
}
static int nxp_mrt_init(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
uint32_t num_channels = (base->MODCFG & MRT_MODCFG_NOC_MASK) >> MRT_MODCFG_NOC_SHIFT;
int ret = 0;
if (!device_is_ready(config->reset.dev)) {
LOG_ERR("Reset device not ready");
return -ENODEV;
}
ret = reset_line_toggle(config->reset.dev, config->reset.id);
if (ret) {
return ret;
}
clock_control_on(config->clock_dev, config->clock_subsys);
config->irq_config_func(dev);
/* Enable interrupts for all the channels that have devices */
for (int i = 0; i < num_channels; i++) {
if (config->channels[i]) {
base->CHANNEL[i].CTRL = MRT_CHANNEL_CTRL_INTEN_MASK;
}
}
return 0;
}
static void nxp_mrt_isr(const struct device *dev)
{
const struct nxp_mrt_config *config = dev->config;
MRT_Type *base = config->base;
uint32_t irq_pends = base->IRQ_FLAG;
uint32_t num_channels = (base->MODCFG & MRT_MODCFG_NOC_MASK) >> MRT_MODCFG_NOC_SHIFT;
for (int i = 0; i < num_channels; i++) {
/* Channel IRQ pending flags lowest order bits in IRQ_FLAG register */
if (!(irq_pends & (0x1 << i))) {
continue;
}
LOG_DBG("Handling interrupt for MRT%p channel %d", base, i);
/* W1C interrupt flag */
base->CHANNEL[i].STAT |= MRT_CHANNEL_STAT_INTFLAG_MASK;
/* Channel devs & pointer path to channel cbs is in shared config */
if (config->data[i]->cb) {
config->data[i]->cb(config->channels[i], config->data[i]->user_data);
}
}
}
struct counter_driver_api nxp_mrt_api = {
.get_value = nxp_mrt_get_value,
.start = nxp_mrt_start,
.stop = nxp_mrt_stop,
.set_top_value = nxp_mrt_set_top_value,
.get_top_value = nxp_mrt_get_top_value,
.get_pending_int = nxp_mrt_get_pending_int,
.set_alarm = nxp_mrt_set_alarm,
.cancel_alarm = nxp_mrt_cancel_alarm,
.get_freq = nxp_mrt_get_freq,
};
/* Creates a device for a channel (needed for counter API) */
#define NXP_MRT_CHANNEL_DEV_INIT(node, mrt_inst) \
DEVICE_DT_DEFINE(node, NULL, NULL, \
(void *) \
&nxp_mrt_##mrt_inst##_channel_datas[DT_REG_ADDR(node)], \
&nxp_mrt_##mrt_inst##_config, \
POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \
&nxp_mrt_api); \
/* Creates a data struct for a channel device */
#define NXP_MRT_CHANNEL_DATA_INIT(node) \
static struct nxp_mrt_channel_data \
nxp_mrt_channel_data_##node; \
/* Initializes an element of the channel data pointer array */
#define NXP_MRT_CHANNEL_DATA_ARRAY_INIT(node) \
[DT_REG_ADDR(node)] = \
&nxp_mrt_channel_data_##node,
/* Initializes an element of the channel device pointer array */
#define NXP_MRT_CHANNEL_DEV_ARRAY_INIT(node) \
[DT_REG_ADDR(node)] = DEVICE_DT_GET(node),
#define NXP_MRT_INIT(n) \
/* ISR is shared between all channels */ \
static void nxp_mrt_##n##_irq_config_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
nxp_mrt_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
} \
\
/* Initialize all the data structs for active channels */ \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, NXP_MRT_CHANNEL_DATA_INIT) \
\
/* Create an array of const pointers to the data structs */ \
static struct nxp_mrt_channel_data *const nxp_mrt_##n##_channel_datas \
[DT_INST_PROP(n, num_channels)] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_MRT_CHANNEL_DATA_ARRAY_INIT) \
}; \
\
/* Forward declaration */ \
const static struct nxp_mrt_config nxp_mrt_##n##_config; \
\
/* Create all the channel/counter devices */ \
DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, NXP_MRT_CHANNEL_DEV_INIT, n) \
\
/* This channel device array is needed by the module device ISR */ \
const struct device *const nxp_mrt_##n##_channels \
[DT_INST_PROP(n, num_channels)] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
NXP_MRT_CHANNEL_DEV_ARRAY_INIT) \
}; \
\
/* This config struct is shared by all the channels and parent device */\
const static struct nxp_mrt_config nxp_mrt_##n##_config = { \
.info = { \
.max_top_value = \
GENMASK(DT_INST_PROP(n, num_bits) - 1, 0), \
.channels = 0, \
}, \
.base = (MRT_Type *)DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t) \
DT_INST_CLOCKS_CELL(n, name), \
.irq_config_func = nxp_mrt_##n##_irq_config_func, \
.data = nxp_mrt_##n##_channel_datas, \
.channels = nxp_mrt_##n##_channels, \
.reset = RESET_DT_SPEC_INST_GET(n), \
}; \
\
/* Init parent device in order to handle ISR and init. */ \
DEVICE_DT_INST_DEFINE(n, &nxp_mrt_init, NULL, NULL, \
&nxp_mrt_##n##_config, \
POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(NXP_MRT_INIT)
``` | /content/code_sandbox/drivers/counter/counter_nxp_mrt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,210 |
```objective-c
/*
*
*/
#ifndef __COUNTER_ACE_V1X_ART_REGS__
#define __COUNTER_ACE_V1X_ART_REGS__
#if CONFIG_ACE_V1X_ART_COUNTER
#define ACE_ART_COUNTER_ID DT_NODELABEL(ace_art_counter)
#define ACE_TIMESTAMP_ID DT_NODELABEL(ace_timestamp)
#define ACE_TSCTRL (DT_REG_ADDR(ACE_TIMESTAMP_ID))
#define ACE_ARTCS (DT_REG_ADDR(ACE_ART_COUNTER_ID))
#define ACE_ARTCS_LO ACE_ARTCS
#define ACE_ARTCS_HI (ACE_ARTCS_LO + 0x04)
#define ACE_TSCTRL_CDMAS_MASK GENMASK(4, 0)
#define ACE_TSCTRL_ODTS_MASK BIT(5)
#define ACE_TSCTRL_LWCS_MASK BIT(6)
#define ACE_TSCTRL_HHTSE_MASK BIT(7)
#define ACE_TSCTRL_CLNKS_MASK GENMASK(11, 10)
#define ACE_TSCTRL_DMATS_MASK GENMASK(13, 12)
#define ACE_TSCTRL_IONTE_MASK BIT(30)
#define ACE_TSCTRL_NTK_MASK BIT(31)
#endif
#endif /*__COUNTER_ACE_V1X_ART_REGS__*/
``` | /content/code_sandbox/drivers/counter/counter_ace_v1x_art_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 248 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <counter/counter_ace_v1x_rtc_regs.h>
static int counter_ace_v1x_rtc_get_value(const struct device *dev,
uint64_t *value)
{
ARG_UNUSED(dev);
uint32_t hi0, lo, hi1;
do {
hi0 = sys_read32(ACE_RTCWC_HI);
lo = sys_read32(ACE_RTCWC_LO);
hi1 = sys_read32(ACE_RTCWC_HI);
} while (hi0 != hi1);
*value = (((uint64_t)hi0) << 32) | lo;
return 0;
}
int counter_ace_v1x_rtc_init(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static const struct counter_driver_api ace_v1x_rtc_counter_apis = {
.get_value_64 = counter_ace_v1x_rtc_get_value
};
DEVICE_DT_DEFINE(DT_NODELABEL(ace_rtc_counter), counter_ace_v1x_rtc_init, NULL, NULL, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&ace_v1x_rtc_counter_apis);
``` | /content/code_sandbox/drivers/counter/counter_ace_v1x_rtc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 296 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_snvs_rtc
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mcux_snvs, CONFIG_COUNTER_LOG_LEVEL);
#if CONFIG_COUNTER_MCUX_SNVS_SRTC
#define MCUX_SNVS_SRTC
#define MCUX_SNVS_NUM_CHANNELS 2
#else
#define MCUX_SNVS_NUM_CHANNELS 1
#endif
#include <zephyr/drivers/counter.h>
#include <zephyr/irq.h>
#include <fsl_snvs_hp.h>
#ifdef MCUX_SNVS_SRTC
#include <fsl_snvs_lp.h>
#endif
struct mcux_snvs_config {
/* info must be first element */
struct counter_config_info info;
SNVS_Type *base;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_snvs_data {
counter_alarm_callback_t alarm_hp_rtc_callback;
void *alarm_hp_rtc_user_data;
#ifdef MCUX_SNVS_SRTC
counter_alarm_callback_t alarm_lp_srtc_callback;
void *alarm_lp_srtc_user_data;
#endif
};
static int mcux_snvs_start(const struct device *dev)
{
ARG_UNUSED(dev);
return -EALREADY;
}
static int mcux_snvs_stop(const struct device *dev)
{
ARG_UNUSED(dev);
return -ENOTSUP;
}
static int mcux_snvs_get_value(const struct device *dev, uint32_t *ticks)
{
const struct mcux_snvs_config *config = dev->config;
uint32_t tmp = 0;
do {
*ticks = tmp;
tmp = (config->base->HPRTCMR << 17U);
tmp |= (config->base->HPRTCLR >> 15U);
} while (*ticks != tmp);
return 0;
}
static int mcux_snvs_set_alarm(const struct device *dev,
uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct mcux_snvs_config *config = dev->config;
struct mcux_snvs_data *data = dev->data;
uint32_t current, ticks;
mcux_snvs_get_value(dev, ¤t);
ticks = alarm_cfg->ticks;
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
ticks += current;
}
if (ticks < current) {
LOG_ERR("Invalid alarm ticks");
return -EINVAL;
}
if (chan_id == 0) {
if (data->alarm_hp_rtc_callback) {
return -EBUSY;
}
data->alarm_hp_rtc_callback = alarm_cfg->callback;
data->alarm_hp_rtc_user_data = alarm_cfg->user_data;
/* disable RTC alarm interrupt */
config->base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK;
while ((config->base->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0U) {
}
/* Set alarm in seconds*/
config->base->HPTAMR = (uint32_t)(ticks >> 17U);
config->base->HPTALR = (uint32_t)(ticks << 15U);
/* enable RTC alarm interrupt */
config->base->HPCR |= SNVS_HPCR_HPTA_EN_MASK;
#ifdef MCUX_SNVS_SRTC
} else if (chan_id == 1) {
if (data->alarm_lp_srtc_callback) {
return -EBUSY;
}
data->alarm_lp_srtc_callback = alarm_cfg->callback;
data->alarm_lp_srtc_user_data = alarm_cfg->user_data;
/* disable SRTC alarm interrupt */
config->base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK;
while ((config->base->LPCR & SNVS_LPCR_LPTA_EN_MASK) != 0U) {
}
/* Set alarm in seconds*/
config->base->LPTAR = ticks;
/* enable SRTC alarm interrupt */
config->base->LPCR |= SNVS_LPCR_LPTA_EN_MASK;
#endif
} else {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
return 0;
}
static int mcux_snvs_cancel_alarm(const struct device *dev,
uint8_t chan_id)
{
const struct mcux_snvs_config *config = dev->config;
struct mcux_snvs_data *data = dev->data;
if (chan_id == 0) {
/* disable RTC alarm interrupt */
config->base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK;
while ((config->base->HPCR & SNVS_HPCR_HPTA_EN_MASK) != 0U) {
}
/* clear callback */
data->alarm_hp_rtc_callback = NULL;
#ifdef MCUX_SNVS_SRTC
} else if (chan_id == 1) {
/* disable SRTC alarm interrupt */
config->base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK;
while ((config->base->LPCR & SNVS_LPCR_LPTA_EN_MASK) != 0U) {
}
/* clear callback */
data->alarm_lp_srtc_callback = NULL;
#endif
} else {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
return 0;
}
static int mcux_snvs_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
ARG_UNUSED(dev);
ARG_UNUSED(cfg);
return -ENOTSUP;
}
static uint32_t mcux_snvs_get_pending_int(const struct device *dev)
{
const struct mcux_snvs_config *config = dev->config;
uint32_t flags;
flags = SNVS_HP_RTC_GetStatusFlags(config->base) & kSNVS_RTC_AlarmInterruptFlag;
#ifdef MCUX_SNVS_SRTC
flags |= SNVS_LP_SRTC_GetStatusFlags(config->base) & kSNVS_SRTC_AlarmInterruptFlag;
#endif
return flags;
}
static uint32_t mcux_snvs_get_top_value(const struct device *dev)
{
ARG_UNUSED(dev);
return UINT32_MAX;
}
void mcux_snvs_isr(const struct device *dev)
{
const struct mcux_snvs_config *config = dev->config;
struct mcux_snvs_data *data = dev->data;
uint32_t current;
mcux_snvs_get_value(dev, ¤t);
if (SNVS_HP_RTC_GetStatusFlags(config->base) & kSNVS_RTC_AlarmInterruptFlag) {
/* Clear alarm flag */
SNVS_HP_RTC_ClearStatusFlags(config->base, kSNVS_RTC_AlarmInterruptFlag);
if (data->alarm_hp_rtc_callback) {
data->alarm_hp_rtc_callback(dev, 0, current, data->alarm_hp_rtc_user_data);
mcux_snvs_cancel_alarm(dev, 0);
}
}
#ifdef MCUX_SNVS_SRTC
if (SNVS_LP_SRTC_GetStatusFlags(config->base) & kSNVS_SRTC_AlarmInterruptFlag) {
/* Clear alarm flag */
SNVS_LP_SRTC_ClearStatusFlags(config->base, kSNVS_SRTC_AlarmInterruptFlag);
if (data->alarm_lp_srtc_callback) {
data->alarm_lp_srtc_callback(dev, 1, current,
data->alarm_lp_srtc_user_data);
mcux_snvs_cancel_alarm(dev, 1);
}
}
#endif
}
int mcux_snvs_rtc_set(const struct device *dev, uint32_t ticks)
{
const struct mcux_snvs_config *config = dev->config;
#ifdef MCUX_SNVS_SRTC
SNVS_LP_SRTC_StopTimer(config->base);
config->base->LPSRTCMR = (uint32_t)(ticks >> 17U);
config->base->LPSRTCLR = (uint32_t)(ticks << 15U);
SNVS_LP_SRTC_StartTimer(config->base);
/* Sync to our high power RTC */
SNVS_HP_RTC_TimeSynchronize(config->base);
#else
SNVS_HP_RTC_StopTimer(config->base);
config->base->HPRTCMR = (uint32_t)(ticks >> 17U);
config->base->HPRTCLR = (uint32_t)(ticks << 15U);
SNVS_HP_RTC_StartTimer(config->base);
#endif
return 0;
}
static int mcux_snvs_init(const struct device *dev)
{
const struct mcux_snvs_config *config = dev->config;
snvs_hp_rtc_config_t hp_rtc_config;
#ifdef MCUX_SNVS_SRTC
snvs_lp_srtc_config_t lp_srtc_config;
#endif
SNVS_HP_RTC_GetDefaultConfig(&hp_rtc_config);
SNVS_HP_RTC_Init(config->base, &hp_rtc_config);
#ifdef MCUX_SNVS_SRTC
/* Reset power glitch detector */
SNVS_LP_Init(config->base);
/* Init SRTC to default config */
SNVS_LP_SRTC_GetDefaultConfig(&lp_srtc_config);
SNVS_LP_SRTC_Init(config->base, &lp_srtc_config);
#if CONFIG_COUNTER_MCUX_SNVS_SRTC_WAKE
config->base->LPCR |= SNVS_LPCR_LPWUI_EN_MASK;
#endif
/* RTC should always run */
SNVS_LP_SRTC_StartTimer(config->base);
SNVS_HP_RTC_TimeSynchronize(config->base);
#endif
/* RTC should always run */
SNVS_HP_RTC_StartTimer(config->base);
config->irq_config_func(dev);
return 0;
}
static const struct counter_driver_api mcux_snvs_driver_api = {
.start = mcux_snvs_start,
.stop = mcux_snvs_stop,
.get_value = mcux_snvs_get_value,
.set_alarm = mcux_snvs_set_alarm,
.cancel_alarm = mcux_snvs_cancel_alarm,
.set_top_value = mcux_snvs_set_top_value,
.get_pending_int = mcux_snvs_get_pending_int,
.get_top_value = mcux_snvs_get_top_value,
};
/*
* This driver is single-instance. If the devicetree contains multiple
* instances, this will fail and the driver needs to be revisited.
*/
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
"unsupported snvs instance");
#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
static struct mcux_snvs_data mcux_snvs_data_0;
static void mcux_snvs_irq_config_0(const struct device *dev);
static struct mcux_snvs_config mcux_snvs_config_0 = {
.info = {
.max_top_value = 0,
.freq = 1,
.channels = MCUX_SNVS_NUM_CHANNELS,
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
},
.base = (SNVS_Type *)DT_REG_ADDR(DT_INST_PARENT(0)),
.irq_config_func = mcux_snvs_irq_config_0,
};
DEVICE_DT_INST_DEFINE(0, &mcux_snvs_init, NULL,
&mcux_snvs_data_0,
&mcux_snvs_config_0,
POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY,
&mcux_snvs_driver_api);
static void mcux_snvs_irq_config_0(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
mcux_snvs_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
``` | /content/code_sandbox/drivers/counter/counter_mcux_snvs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,494 |
```objective-c
/*
*
*/
#ifndef __COUNTER_ACE_V1X_RTC_REGS__
#define __COUNTER_ACE_V1X_RTC_REGS__
#if CONFIG_ACE_V1X_RTC_COUNTER
#define ACE_RTC_COUNTER_ID DT_NODELABEL(ace_rtc_counter)
#define ACE_RTCWC (DT_REG_ADDR(ACE_RTC_COUNTER_ID))
#define ACE_RTCWC_LO ACE_RTCWC
#define ACE_RTCWC_HI ACE_RTCWC + 0x04
#endif
#endif /*__COUNTER_ACE_V1X_RTC_REGS__*/
``` | /content/code_sandbox/drivers/counter/counter_ace_v1x_rtc_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_smartbond_timer
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
#include <zephyr/irq.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/pm/policy.h>
#include <DA1469xAB.h>
#include <da1469x_pdc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(counter_timer, CONFIG_COUNTER_LOG_LEVEL);
#define LP_CLK_OSC_RC32K 0
#define LP_CLK_OSC_RCX 1
#define LP_CLK_OSC_XTAL32K 2
#define TIMER_TOP_VALUE 0xFFFFFF
#define COUNTER_DT_DEVICE(_idx) DEVICE_DT_GET_OR_NULL(DT_NODELABEL(timer##_idx))
#define PDC_XTAL_EN (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal32m), okay) ? \
MCU_PDC_EN_XTAL : MCU_PDC_EN_NONE)
struct counter_smartbond_data {
counter_alarm_callback_t callback;
void *user_data;
uint32_t guard_period;
uint32_t freq;
#if defined(CONFIG_PM_DEVICE)
uint8_t pdc_idx;
#endif
};
struct counter_smartbond_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_smartbond_config {
struct counter_config_info info;
/* Register set for timer */
TIMER2_Type *timer;
uint8_t prescaler;
/* Timer driven by DIVn if 1 or lp_clk if 0 */
uint8_t clock_src_divn;
uint8_t irqn;
void (*irq_config_func)(const struct device *dev);
LOG_INSTANCE_PTR_DECLARE(log);
};
#if defined(CONFIG_PM_DEVICE)
static void counter_smartbond_pm_policy_state_lock_get(const struct device *dev)
{
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
pm_device_runtime_get(dev);
}
static void counter_smartbond_pm_policy_state_lock_put(const struct device *dev)
{
pm_device_runtime_put(dev);
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
/*
* Routine to check whether the device is allowed to enter the sleep state or not.
* Entering the standby mode should be allowed for TIMER1/2 that are clocked by LP
* clock. Although, TIMER1/2 are powered by a distinct power domain,
* namely PD_TMR which is always enabled (used to generate the sleep tick count),
* the DIVN path which reflects the main crystal, that is XTAL32M, is turned off
* during sleep by PDC. It's worth noting that during sleep the clock source of
* a timer block will automatically be switched from DIVN to LP and vice versa.
*/
static inline bool counter_smartbond_is_sleep_allowed(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
return (((dev == COUNTER_DT_DEVICE(1)) ||
(dev == COUNTER_DT_DEVICE(2))) && !config->clock_src_divn);
}
/* Get the PDC trigger associated with the requested counter device */
static uint8_t counter_smartbond_pdc_trigger_get(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
switch ((uint32_t)config->timer) {
case (uint32_t)TIMER:
return MCU_PDC_TRIGGER_TIMER;
case (uint32_t)TIMER2:
return MCU_PDC_TRIGGER_TIMER2;
case (uint32_t)TIMER3:
return MCU_PDC_TRIGGER_TIMER3;
case (uint32_t)TIMER4:
return MCU_PDC_TRIGGER_TIMER4;
default:
return 0;
}
}
/*
* Add PDC entry so that the application core, which should be turned off during sleep,
* can get notified upon counter events. This routine is called for counter instances
* that are powered by PD_TMR and can operate during sleep.
*/
static void counter_smartbond_pdc_add(const struct device *dev)
{
struct counter_smartbond_data *data = dev->data;
uint8_t trigger = counter_smartbond_pdc_trigger_get(dev);
data->pdc_idx = da1469x_pdc_add(trigger, MCU_PDC_MASTER_M33, PDC_XTAL_EN);
__ASSERT_NO_MSG(data->pdc_idx >= 0);
da1469x_pdc_set(data->pdc_idx);
da1469x_pdc_ack(data->pdc_idx);
}
static void counter_smartbond_pdc_del(const struct device *dev)
{
struct counter_smartbond_data *data = dev->data;
da1469x_pdc_del(data->pdc_idx);
}
#endif
static int counter_smartbond_start(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
TIMER2_Type *timer = config->timer;
#if defined(CONFIG_PM_DEVICE)
if (!counter_smartbond_is_sleep_allowed(dev)) {
/*
* Power mode constraints should be applied as long as the device
* is up and running.
*/
counter_smartbond_pm_policy_state_lock_get(dev);
} else {
counter_smartbond_pdc_add(dev);
}
#endif
/* Enable counter in free running mode */
timer->TIMER2_CTRL_REG |= (TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk |
TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk |
TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk);
return 0;
}
static int counter_smartbond_stop(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
struct counter_smartbond_data *data = dev->data;
TIMER2_Type *timer = config->timer;
/* disable counter */
timer->TIMER2_CTRL_REG &= ~(TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk |
TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk |
TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk);
data->callback = NULL;
#if defined(CONFIG_PM_DEVICE)
if (!counter_smartbond_is_sleep_allowed(dev)) {
counter_smartbond_pm_policy_state_lock_put(dev);
} else {
counter_smartbond_pdc_del(dev);
}
#endif
return 0;
}
static uint32_t counter_smartbond_get_top_value(const struct device *dev)
{
ARG_UNUSED(dev);
return TIMER_TOP_VALUE;
}
static uint32_t counter_smartbond_read(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
TIMER2_Type *timer = config->timer;
return timer->TIMER2_TIMER_VAL_REG;
}
static int counter_smartbond_get_value(const struct device *dev, uint32_t *ticks)
{
*ticks = counter_smartbond_read(dev);
return 0;
}
static int counter_smartbond_set_alarm(const struct device *dev, uint8_t chan,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct counter_smartbond_config *config = dev->config;
struct counter_smartbond_data *data = dev->data;
TIMER2_Type *timer = config->timer;
volatile uint32_t *timer_clear_irq_reg = ((TIMER_Type *)timer) == TIMER ?
&((TIMER_Type *)timer)->TIMER_CLEAR_IRQ_REG :
&timer->TIMER2_CLEAR_IRQ_REG;
bool absolute = alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE;
uint32_t flags = alarm_cfg->flags;
uint32_t val = alarm_cfg->ticks;
bool irq_on_late;
int err = 0;
uint32_t max_rel_val;
uint32_t now;
uint32_t diff;
if (chan != 0 || alarm_cfg->ticks > counter_smartbond_get_top_value(dev)) {
return -EINVAL;
}
if (data->callback) {
return -EBUSY;
}
now = counter_smartbond_read(dev);
data->callback = alarm_cfg->callback;
data->user_data = alarm_cfg->user_data;
__ASSERT_NO_MSG(data->guard_period < TIMER_TOP_VALUE);
if (absolute) {
max_rel_val = TIMER_TOP_VALUE - data->guard_period;
irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
} else {
/* If relative value is smaller than half of the counter range
* it is assumed that there is a risk of setting value too late
* and late detection algorithm must be applied. When late
* setting is detected, interrupt shall be triggered for
* immediate expiration of the timer. Detection is performed
* by limiting relative distance between CC and counter.
*
* Note that half of counter range is an arbitrary value.
*/
irq_on_late = val < (TIMER_TOP_VALUE / 2U);
/* limit max to detect short relative being set too late. */
max_rel_val = irq_on_late ? TIMER_TOP_VALUE / 2U : TIMER_TOP_VALUE;
val = (now + val) & TIMER_TOP_VALUE;
}
timer->TIMER2_RELOAD_REG = val;
*timer_clear_irq_reg = 1;
/* decrement value to detect also case when val == counter_smartbond_read(dev). Otherwise,
* condition would need to include comparing diff against 0.
*/
diff = ((val - 1U) - counter_smartbond_read(dev)) & TIMER_TOP_VALUE;
if (diff > max_rel_val) {
if (absolute) {
err = -ETIME;
}
/* Interrupt is triggered always for relative alarm and
* for absolute depending on the flag.
*/
if (irq_on_late) {
NVIC_SetPendingIRQ(config->irqn);
} else {
data->callback = NULL;
}
} else {
if (diff == 0) {
/* RELOAD value could be set just in time for interrupt
* trigger or too late. In any case time is interrupt
* should be triggered. No need to enable interrupt
* on TIMER just make sure interrupt is pending.
*/
NVIC_SetPendingIRQ(config->irqn);
} else {
timer->TIMER2_CTRL_REG |= TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk;
}
}
return err;
}
static int counter_smartbond_cancel_alarm(const struct device *dev, uint8_t chan)
{
const struct counter_smartbond_config *config = dev->config;
TIMER2_Type *timer = config->timer;
struct counter_smartbond_data *data = dev->data;
ARG_UNUSED(chan);
timer->TIMER2_CTRL_REG &= ~TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk;
data->callback = NULL;
return 0;
}
static int counter_smartbond_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
ARG_UNUSED(dev);
if (cfg->ticks != 0xFFFFFF) {
return -ENOTSUP;
}
return 0;
}
static uint32_t counter_smartbond_get_pending_int(const struct device *dev)
{
const struct counter_smartbond_config *config = dev->config;
/* There is no register to check TIMER peripheral to check for interrupt
* pending, check directly in NVIC.
*/
return NVIC_GetPendingIRQ(config->irqn);
}
static int counter_smartbond_init_timer(const struct device *dev)
{
const struct counter_smartbond_config *cfg = dev->config;
struct counter_smartbond_data *data = dev->data;
TIMER2_Type *timer = cfg->timer;
TIMER_Type *timer0 = ((TIMER_Type *)cfg->timer) == TIMER ? TIMER : NULL;
const struct device *osc_dev;
uint32_t osc_freq;
enum smartbond_clock osc;
if (cfg->clock_src_divn) {
/* Timer clock source is DIVn 32MHz */
timer->TIMER2_CTRL_REG = TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk;
data->freq = DT_PROP(DT_NODELABEL(divn_clk), clock_frequency) /
(cfg->prescaler + 1);
} else {
osc_dev = DEVICE_DT_GET(DT_NODELABEL(osc));
timer->TIMER2_CTRL_REG = 0;
switch ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) >>
CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos) {
case LP_CLK_OSC_RC32K:
osc = SMARTBOND_CLK_RC32K;
break;
case LP_CLK_OSC_RCX:
osc = SMARTBOND_CLK_RCX;
break;
default:
case LP_CLK_OSC_XTAL32K:
osc = SMARTBOND_CLK_XTAL32K;
break;
}
clock_control_get_rate(osc_dev, (clock_control_subsys_t)osc, &osc_freq);
data->freq = osc_freq / (cfg->prescaler + 1);
}
timer->TIMER2_PRESCALER_REG = cfg->prescaler;
timer->TIMER2_RELOAD_REG = counter_get_max_top_value(dev);
timer->TIMER2_GPIO1_CONF_REG = 0;
timer->TIMER2_GPIO2_CONF_REG = 0;
timer->TIMER2_SHOTWIDTH_REG = 0;
timer->TIMER2_CAPTURE_GPIO1_REG = 0;
timer->TIMER2_CAPTURE_GPIO2_REG = 0;
timer->TIMER2_PWM_FREQ_REG = 0;
timer->TIMER2_PWM_DC_REG = 0;
if (timer0) {
timer0->TIMER_CAPTURE_GPIO3_REG = 0;
timer0->TIMER_CAPTURE_GPIO4_REG = 0;
}
/* config/enable IRQ */
cfg->irq_config_func(dev);
#ifdef CONFIG_PM_DEVICE_RUNTIME
/* Make sure device state is marked as suspended */
pm_device_init_suspended(dev);
return pm_device_runtime_enable(dev);
#endif
return 0;
}
static uint32_t counter_smartbond_get_guard_period(const struct device *dev, uint32_t flags)
{
struct counter_smartbond_data *data = dev->data;
ARG_UNUSED(flags);
return data->guard_period;
}
static int counter_smartbond_set_guard_period(const struct device *dev, uint32_t guard,
uint32_t flags)
{
struct counter_smartbond_data *data = dev->data;
ARG_UNUSED(flags);
__ASSERT_NO_MSG(guard < counter_smartbond_get_top_value(dev));
data->guard_period = guard;
return 0;
}
static uint32_t counter_smartbond_get_freq(const struct device *dev)
{
struct counter_smartbond_data *data = dev->data;
return data->freq;
}
#if defined(CONFIG_PM_DEVICE)
static void counter_smartbond_resume(const struct device *dev)
{
const struct counter_smartbond_config *cfg = dev->config;
TIMER2_Type *timer = cfg->timer;
/*
* Resume only for block instances that are powered by PD_SYS
* and so their register contents should reset after sleep.
*/
if (!counter_smartbond_is_sleep_allowed(dev)) {
if (cfg->clock_src_divn) {
timer->TIMER2_CTRL_REG = TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk;
} else {
timer->TIMER2_CTRL_REG = 0;
}
timer->TIMER2_PRESCALER_REG = cfg->prescaler;
timer->TIMER2_RELOAD_REG = counter_get_max_top_value(dev);
}
}
static int counter_smartbond_pm_action(const struct device *dev, enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
break;
case PM_DEVICE_ACTION_RESUME:
counter_smartbond_resume(dev);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif
static const struct counter_driver_api counter_smartbond_driver_api = {
.start = counter_smartbond_start,
.stop = counter_smartbond_stop,
.get_value = counter_smartbond_get_value,
.set_alarm = counter_smartbond_set_alarm,
.cancel_alarm = counter_smartbond_cancel_alarm,
.set_top_value = counter_smartbond_set_top_value,
.get_pending_int = counter_smartbond_get_pending_int,
.get_top_value = counter_smartbond_get_top_value,
.get_guard_period = counter_smartbond_get_guard_period,
.set_guard_period = counter_smartbond_set_guard_period,
.get_freq = counter_smartbond_get_freq,
};
void counter_smartbond_irq_handler(const struct device *dev)
{
const struct counter_smartbond_config *cfg = dev->config;
struct counter_smartbond_data *data = dev->data;
counter_alarm_callback_t alarm_callback = data->callback;
TIMER2_Type *timer = cfg->timer;
/* Timer0 has interrupt clear register in other offset */
__IOM uint32_t *timer_clear_irq_reg = ((TIMER_Type *)timer) == TIMER ?
&((TIMER_Type *)timer)->TIMER_CLEAR_IRQ_REG :
&timer->TIMER2_CLEAR_IRQ_REG;
timer->TIMER2_CTRL_REG &= ~TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk;
*timer_clear_irq_reg = 1;
if (alarm_callback != NULL) {
data->callback = NULL;
alarm_callback(dev, 0, timer->TIMER2_TIMER_VAL_REG,
data->user_data);
}
}
#define TIMERN(idx) DT_DRV_INST(idx)
/** TIMERn instance from DT */
#define TIM(idx) ((TIMER2_Type *)DT_REG_ADDR(TIMERN(idx)))
#define COUNTER_DEVICE_INIT(idx) \
BUILD_ASSERT(DT_PROP(TIMERN(idx), prescaler) <= 32 && \
DT_PROP(TIMERN(idx), prescaler) > 0, \
"TIMER prescaler out of range (1..32)"); \
\
static struct counter_smartbond_data counter##idx##_data; \
\
static void counter##idx##_smartbond_irq_config(const struct device *dev)\
{ \
IRQ_CONNECT(DT_IRQN(TIMERN(idx)), \
DT_IRQ(TIMERN(idx), priority), \
counter_smartbond_irq_handler, \
DEVICE_DT_INST_GET(idx), \
0); \
irq_enable(DT_IRQN(TIMERN(idx))); \
} \
\
static const struct counter_smartbond_config counter##idx##_config = { \
.info = { \
.max_top_value = 0x00FFFFFF, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1, \
}, \
.timer = TIM(idx), \
.prescaler = DT_PROP(TIMERN(idx), prescaler) - 1, \
.clock_src_divn = DT_SAME_NODE(DT_PROP(TIMERN(idx), clock_src), \
DT_NODELABEL(divn_clk)) ? 1 : 0, \
.irq_config_func = counter##idx##_smartbond_irq_config, \
.irqn = DT_IRQN(TIMERN(idx)), \
}; \
\
PM_DEVICE_DT_INST_DEFINE(idx, counter_smartbond_pm_action); \
DEVICE_DT_INST_DEFINE(idx, \
counter_smartbond_init_timer, \
PM_DEVICE_DT_INST_GET(idx), \
&counter##idx##_data, \
&counter##idx##_config, \
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&counter_smartbond_driver_api);
DT_INST_FOREACH_STATUS_OKAY(COUNTER_DEVICE_INIT)
``` | /content/code_sandbox/drivers/counter/counter_smartbond_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,148 |
```unknown
# Silicon Labs Gecko Counter driver config
config COUNTER_GECKO_RTCC
bool "Silicon Labs Gecko Counter (RTCC) driver"
default y
depends on DT_HAS_SILABS_GECKO_RTCC_ENABLED
select SOC_GECKO_CMU
select SOC_GECKO_RTCC
help
Enable counter driver based on RTCC module for Silicon Labs Gecko
chips.
config COUNTER_GECKO_STIMER
bool "Silicon Labs Gecko Counter Sleep Timer driver"
default y
depends on DT_HAS_SILABS_GECKO_STIMER_ENABLED
select SOC_GECKO_RTCC
select SOC_GECKO_PRS
help
Enable the counter driver for Sleep Timer module for Silicon Labs
Gecko chips.
``` | /content/code_sandbox/drivers/counter/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/counter.h>
/* For those APIs that just take one argument which is a counter driver
* instance and return an integral value
*/
#define COUNTER_HANDLER(name) \
static inline int z_vrfy_counter_##name(const struct device *dev) \
{ \
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, name)); \
return z_impl_counter_ ## name((const struct device *)dev); \
}
COUNTER_HANDLER(get_pending_int)
COUNTER_HANDLER(stop)
COUNTER_HANDLER(start)
#include <zephyr/syscalls/counter_get_pending_int_mrsh.c>
#include <zephyr/syscalls/counter_stop_mrsh.c>
#include <zephyr/syscalls/counter_start_mrsh.c>
static inline bool z_vrfy_counter_is_counting_up(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_is_counting_up((const struct device *)dev);
}
#include <zephyr/syscalls/counter_is_counting_up_mrsh.c>
static inline uint8_t z_vrfy_counter_get_num_of_channels(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_get_num_of_channels((const struct device *)dev);
}
#include <zephyr/syscalls/counter_get_num_of_channels_mrsh.c>
static inline uint32_t z_vrfy_counter_get_frequency(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_get_frequency((const struct device *)dev);
}
#include <zephyr/syscalls/counter_get_frequency_mrsh.c>
static inline uint32_t z_vrfy_counter_us_to_ticks(const struct device *dev,
uint64_t us)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_us_to_ticks((const struct device *)dev,
(uint64_t)us);
}
#include <zephyr/syscalls/counter_us_to_ticks_mrsh.c>
static inline uint64_t z_vrfy_counter_ticks_to_us(const struct device *dev,
uint32_t ticks)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_ticks_to_us((const struct device *)dev,
(uint32_t)ticks);
}
#include <zephyr/syscalls/counter_ticks_to_us_mrsh.c>
static inline int z_vrfy_counter_get_value(const struct device *dev,
uint32_t *ticks)
{
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, get_value));
K_OOPS(K_SYSCALL_MEMORY_WRITE(ticks, sizeof(*ticks)));
return z_impl_counter_get_value((const struct device *)dev, ticks);
}
#include <zephyr/syscalls/counter_get_value_mrsh.c>
static inline int z_vrfy_counter_get_value_64(const struct device *dev,
uint64_t *ticks)
{
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, get_value_64));
K_OOPS(K_SYSCALL_MEMORY_WRITE(ticks, sizeof(*ticks)));
return z_impl_counter_get_value_64((const struct device *)dev, ticks);
}
#include <zephyr/syscalls/counter_get_value_64_mrsh.c>
static inline int z_vrfy_counter_set_channel_alarm(const struct device *dev,
uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
struct counter_alarm_cfg cfg_copy;
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, set_alarm));
K_OOPS(k_usermode_from_copy(&cfg_copy, alarm_cfg, sizeof(cfg_copy)));
K_OOPS(K_SYSCALL_VERIFY_MSG(cfg_copy.callback == NULL,
"callbacks may not be set from user mode"));
return z_impl_counter_set_channel_alarm((const struct device *)dev,
(uint8_t)chan_id,
(const struct counter_alarm_cfg *)&cfg_copy);
}
#include <zephyr/syscalls/counter_set_channel_alarm_mrsh.c>
static inline int z_vrfy_counter_cancel_channel_alarm(const struct device *dev,
uint8_t chan_id)
{
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, cancel_alarm));
return z_impl_counter_cancel_channel_alarm((const struct device *)dev,
(uint8_t)chan_id);
}
#include <zephyr/syscalls/counter_cancel_channel_alarm_mrsh.c>
static inline int z_vrfy_counter_set_top_value(const struct device *dev,
const struct counter_top_cfg
*cfg)
{
struct counter_top_cfg cfg_copy;
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, set_top_value));
K_OOPS(k_usermode_from_copy(&cfg_copy, cfg, sizeof(cfg_copy)));
K_OOPS(K_SYSCALL_VERIFY_MSG(cfg_copy.callback == NULL,
"callbacks may not be set from user mode"));
return z_impl_counter_set_top_value((const struct device *)dev,
(const struct counter_top_cfg *)
&cfg_copy);
}
#include <zephyr/syscalls/counter_set_top_value_mrsh.c>
static inline uint32_t z_vrfy_counter_get_top_value(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_COUNTER(dev, get_top_value));
return z_impl_counter_get_top_value((const struct device *)dev);
}
#include <zephyr/syscalls/counter_get_top_value_mrsh.c>
static inline uint32_t z_vrfy_counter_get_max_top_value(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_get_max_top_value((const struct device *)dev);
}
#include <zephyr/syscalls/counter_get_max_top_value_mrsh.c>
static inline uint32_t z_vrfy_counter_get_guard_period(const struct device *dev,
uint32_t flags)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_get_guard_period((const struct device *)dev,
flags);
}
#include <zephyr/syscalls/counter_get_guard_period_mrsh.c>
static inline int z_vrfy_counter_set_guard_period(const struct device *dev,
uint32_t ticks, uint32_t flags)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_COUNTER));
return z_impl_counter_set_guard_period((const struct device *)dev,
ticks,
flags);
}
#include <zephyr/syscalls/counter_set_guard_period_mrsh.c>
``` | /content/code_sandbox/drivers/counter/counter_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,351 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_stimer
#include <errno.h>
#include <stddef.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <em_cmu.h>
#include <sl_atomic.h>
#include <sl_sleeptimer.h>
#include <sli_sleeptimer_hal.h>
LOG_MODULE_REGISTER(counter_gecko, CONFIG_COUNTER_LOG_LEVEL);
#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_RTCC
#define STIMER_IRQ_HANDLER RTCC_IRQHandler
#define STIMER_MAX_VALUE _RTCC_CNT_MASK
#elif SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC
#define STIMER_IRQ_HANDLER SYSRTC_APP_IRQHandler
#define STIMER_MAX_VALUE _SYSRTC_CNT_MASK
#else
#error "Unsupported sleep timer peripheral"
#endif
#define STIMER_ALARM_NUM 2
struct counter_gecko_config {
struct counter_config_info info;
void (*irq_config)(void);
uint32_t prescaler;
};
struct counter_gecko_alarm_data {
counter_alarm_callback_t callback;
uint8_t chan_id;
uint32_t ticks;
struct device *dev;
void *user_data;
};
struct counter_gecko_top_data {
counter_top_callback_t callback;
uint32_t ticks;
struct device *dev;
void *user_data;
};
struct counter_gecko_data {
struct counter_gecko_alarm_data alarm[STIMER_ALARM_NUM];
struct counter_gecko_top_data top_data;
};
static sl_sleeptimer_timer_handle_t alarm_timer[STIMER_ALARM_NUM];
static sl_sleeptimer_timer_handle_t top_timer;
#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
#define ERRATA_RTCC_E201_MESSAGE \
"Errata RTCC_E201: In case RTCC prescaler != 1 the module does not " \
"reset the counter value on CCV1 compare."
#endif
static void alarm_callback(sl_sleeptimer_timer_handle_t *handle, void *data)
{
struct counter_gecko_alarm_data *alarm_data = (struct counter_gecko_alarm_data *)data;
uint32_t count =
((sl_sleeptimer_get_tick_count()) %
(((struct counter_gecko_data *const)(alarm_data->dev)->data)->top_data.ticks));
if (alarm_data->callback != NULL) {
alarm_data->callback(
alarm_data->dev, alarm_data->chan_id, count,
((struct counter_alarm_cfg *)(alarm_data->user_data))->user_data);
}
}
static void top_callback(sl_sleeptimer_timer_handle_t *handle, void *data)
{
struct counter_gecko_top_data *top_data = (struct counter_gecko_top_data *)data;
if (top_data->callback != NULL) {
top_data->callback(top_data->dev,
((struct counter_top_cfg *)(top_data->user_data))->user_data);
}
}
static int counter_gecko_get_value(const struct device *dev, uint32_t *ticks)
{
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
*ticks = ((sl_sleeptimer_get_tick_count()) % (dev_data->top_data.ticks));
return 0;
}
static int counter_gecko_start(const struct device *dev)
{
ARG_UNUSED(dev);
sl_status_t error_code;
bool is_top_timer_running = false;
error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
return 0;
}
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
error_code = sl_sleeptimer_start_timer(&top_timer, dev_data->top_data.ticks, top_callback,
(void *)&dev_data->top_data, 0, 0);
return error_code;
}
static int counter_gecko_stop(const struct device *dev)
{
ARG_UNUSED(dev);
sl_status_t error_code;
bool is_top_timer_running = false;
error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
sl_sleeptimer_stop_timer(&top_timer);
}
return error_code;
}
static int counter_gecko_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
{
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
sl_status_t error_code;
bool is_top_timer_running = false;
#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
const struct counter_gecko_config *const dev_cfg =
(const struct counter_gecko_config *const)(dev)->config;
if (dev_cfg->prescaler != 1) {
LOG_ERR(ERRATA_RTCC_E201_MESSAGE);
return -EINVAL;
}
#endif
error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
sl_sleeptimer_stop_timer(&top_timer);
}
dev_data->top_data.callback = cfg->callback;
dev_data->top_data.ticks = cfg->ticks;
dev_data->top_data.dev = (struct device *)dev;
dev_data->top_data.user_data = (struct counter_top_cfg *)cfg;
error_code = sl_sleeptimer_start_periodic_timer(&top_timer, cfg->ticks, top_callback,
(void *)&dev_data->top_data, 0, cfg->flags);
return error_code;
}
static uint32_t counter_gecko_get_top_value(const struct device *dev)
{
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
return dev_data->top_data.ticks;
}
static int counter_gecko_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
bool is_alarm_timer_running = false;
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
sl_status_t error_code;
uint32_t now_ticks = 0;
uint32_t top_val = counter_gecko_get_top_value(dev);
if ((top_val != 0) && (alarm_cfg->ticks > top_val)) {
return -EINVAL;
}
if (chan_id >= STIMER_ALARM_NUM) {
printk("Alarm timer count exceeded\n");
return -EINVAL;
}
error_code = sl_sleeptimer_is_timer_running(&alarm_timer[chan_id], &is_alarm_timer_running);
if ((error_code == SL_STATUS_OK) && (is_alarm_timer_running == true)) {
sl_sleeptimer_stop_timer(&alarm_timer[chan_id]);
}
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) {
/* Absolute */
error_code = counter_gecko_get_value(dev, &now_ticks);
if (now_ticks < alarm_cfg->ticks) {
dev_data->alarm[chan_id].ticks = top_val + (alarm_cfg->ticks - now_ticks);
} else {
dev_data->alarm[chan_id].ticks =
(top_val - (now_ticks - alarm_cfg->ticks)) % top_val;
}
} else {
/* Relative */
dev_data->alarm[chan_id].ticks = alarm_cfg->ticks;
}
dev_data->alarm[chan_id].callback = alarm_cfg->callback;
dev_data->alarm[chan_id].chan_id = chan_id;
dev_data->alarm[chan_id].dev = (struct device *)dev;
dev_data->alarm[chan_id].user_data = (struct counter_alarm_cfg *)alarm_cfg;
error_code =
sl_sleeptimer_start_timer(&alarm_timer[chan_id], dev_data->alarm[chan_id].ticks,
alarm_callback, (void *)&dev_data->alarm[chan_id], 0, 0);
return 0;
}
static int counter_gecko_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
if (chan_id >= STIMER_ALARM_NUM) {
LOG_DBG("Alarm timer count exceeded\n");
return -EINVAL;
}
sl_sleeptimer_stop_timer(&alarm_timer[chan_id]);
dev_data->alarm[chan_id].callback = NULL;
dev_data->alarm[chan_id].user_data = NULL;
LOG_DBG("cancel alarm: channel %u", chan_id);
return 0;
}
static uint32_t counter_gecko_get_pending_int(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static int counter_gecko_init(const struct device *dev)
{
const struct counter_gecko_config *const dev_cfg =
(const struct counter_gecko_config *const)(dev)->config;
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
sl_sleeptimer_init();
dev_data->top_data.ticks = STIMER_MAX_VALUE;
/* Configure & enable module interrupts */
dev_cfg->irq_config();
LOG_INF("Device %s initialized", (dev)->name);
return 0;
}
static const struct counter_driver_api counter_gecko_driver_api = {
.start = counter_gecko_start,
.stop = counter_gecko_stop,
.get_value = counter_gecko_get_value,
.set_alarm = counter_gecko_set_alarm,
.cancel_alarm = counter_gecko_cancel_alarm,
.set_top_value = counter_gecko_set_top_value,
.get_pending_int = counter_gecko_get_pending_int,
.get_top_value = counter_gecko_get_top_value,
};
BUILD_ASSERT((DT_INST_PROP(0, prescaler) > 0U) && (DT_INST_PROP(0, prescaler) <= 32768U));
static void counter_gecko_0_irq_config(void)
{
IRQ_DIRECT_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), STIMER_IRQ_HANDLER, 0);
irq_enable(DT_INST_IRQN(0));
}
static const struct counter_gecko_config counter_gecko_0_config = {
.info = {
.max_top_value = STIMER_MAX_VALUE,
.freq = DT_INST_PROP(0, clock_frequency) / DT_INST_PROP(0, prescaler),
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = STIMER_ALARM_NUM,
},
.irq_config = counter_gecko_0_irq_config,
.prescaler = DT_INST_PROP(0, prescaler),
};
static struct counter_gecko_data counter_gecko_0_data;
DEVICE_DT_INST_DEFINE(0, counter_gecko_init, NULL, &counter_gecko_0_data, &counter_gecko_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &counter_gecko_driver_api);
``` | /content/code_sandbox/drivers/counter/counter_gecko_stimer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,354 |
```unknown
# ESP32 General Purpose Timer configuration
config COUNTER_TMR_ESP32
bool "ESP32 Counter Driver based on GP-Timers"
default y
depends on DT_HAS_ESPRESSIF_ESP32_TIMER_ENABLED
help
Enables the Counter driver API based on Espressif's General
Purpose Timers for ESP32 series devices.
config COUNTER_TMR_RTC_ESP32
bool "ESP32 Counter Driver based on GP-Timers"
default y
depends on DT_HAS_ESPRESSIF_ESP32_RTC_TIMER_ENABLED
help
Enables the Counter driver API based on Espressif's General
Purpose Timers for ESP32 series devices.
``` | /content/code_sandbox/drivers/counter/Kconfig.esp32_tmr | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/kernel.h>
#include <zephyr/spinlock.h>
#include <soc.h>
#include <counter/counter_ace_v1x_art_regs.h>
static struct k_spinlock lock;
static void counter_ace_v1x_art_ionte_set(bool new_timestamp_enable)
{
uint32_t val;
val = sys_read32(ACE_TSCTRL);
val &= ~ACE_TSCTRL_IONTE_MASK;
val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable);
sys_write32(val, ACE_TSCTRL);
}
static void counter_ace_v1x_art_cdmas_set(uint32_t cdmas)
{
uint32_t val;
val = sys_read32(ACE_TSCTRL);
val &= ~ACE_TSCTRL_CDMAS_MASK;
val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas);
sys_write32(val, ACE_TSCTRL);
}
static void counter_ace_v1x_art_ntk_set(bool new_timestamp_taken)
{
uint32_t val;
val = sys_read32(ACE_TSCTRL);
val &= ~ACE_TSCTRL_NTK_MASK;
val |= FIELD_PREP(ACE_TSCTRL_NTK_MASK, new_timestamp_taken);
sys_write32(val, ACE_TSCTRL);
}
static uint32_t counter_ace_v1x_art_ntk_get(void)
{
return FIELD_GET(ACE_TSCTRL_NTK_MASK, sys_read32(ACE_TSCTRL));
}
static void counter_ace_v1x_art_hhtse_set(bool enable)
{
uint32_t val;
val = sys_read32(ACE_TSCTRL);
val &= ~ACE_TSCTRL_HHTSE_MASK;
val |= FIELD_PREP(ACE_TSCTRL_HHTSE_MASK, enable);
sys_write32(val, ACE_TSCTRL);
}
static uint64_t counter_ace_v1x_art_counter_get(void)
{
uint32_t hi0, lo, hi1;
do {
hi0 = sys_read32(ACE_ARTCS_HI);
lo = sys_read32(ACE_ARTCS_LO);
hi1 = sys_read32(ACE_ARTCS_HI);
} while (hi0 != hi1);
return (((uint64_t)hi1) << 32) | lo;
}
int counter_ace_v1x_art_get_value(const struct device *dev, uint64_t *value)
{
ARG_UNUSED(dev);
k_spinlock_key_t key = k_spin_lock(&lock);
counter_ace_v1x_art_ionte_set(1);
counter_ace_v1x_art_cdmas_set(1);
if (counter_ace_v1x_art_ntk_get()) {
counter_ace_v1x_art_ntk_set(1);
while (counter_ace_v1x_art_ntk_get()) {
k_busy_wait(10);
}
}
counter_ace_v1x_art_hhtse_set(1);
while (!counter_ace_v1x_art_ntk_get()) {
k_busy_wait(10);
}
*value = counter_ace_v1x_art_counter_get();
counter_ace_v1x_art_ntk_set(1);
k_spin_unlock(&lock, key);
return 0;
}
static const struct counter_driver_api ace_v1x_art_counter_apis = {
.get_value_64 = counter_ace_v1x_art_get_value
};
DEVICE_DT_DEFINE(DT_NODELABEL(ace_art_counter), NULL, NULL, NULL, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&ace_v1x_art_counter_apis);
``` | /content/code_sandbox/drivers/counter/counter_ace_v1x_art.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 771 |
```unknown
config COUNTER_NXP_S32_SYS_TIMER
bool "NXP S32 System Timer Module driver"
default y
depends on DT_HAS_NXP_S32_SYS_TIMER_ENABLED
select CLOCK_CONTROL
help
Enable support for NXP S32 System Timer Module (STM) driver.
``` | /content/code_sandbox/drivers/counter/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*/
/**
* @file
*
* Counter driver for the Quad Timer through the MCUxpresso SDK. Based mainly on counter_mcux_gpt.c
*
* Each quad timer module has four channels (0-3) that can operate independently, but the Zephyr
* counter-API does not support starting or stopping different channels independently. Hence, each
* channel is represented as an independent counter device.
*/
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_qtmr.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/barrier.h>
LOG_MODULE_REGISTER(mcux_qtmr, CONFIG_COUNTER_LOG_LEVEL);
struct mcux_qtmr_config {
/* info must be first element */
struct counter_config_info info;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
TMR_Type *base;
clock_name_t clock_source;
qtmr_channel_selection_t channel;
qtmr_config_t qtmr_config;
qtmr_counting_mode_t mode;
};
struct mcux_qtmr_data {
counter_alarm_callback_t alarm_callback;
counter_top_callback_t top_callback;
void *alarm_user_data;
void *top_user_data;
qtmr_status_flags_t interrupt_mask;
uint32_t freq;
};
/* Only one interrupt per QTMR module. Each of which has four timers. */
#define DT_DRV_COMPAT nxp_imx_qtmr
/**
* @brief ISR for a specific timer channel
*
* @param dev timer channel device
*/
void mcux_qtmr_timer_handler(const struct device *dev, uint32_t status)
{
const struct mcux_qtmr_config *config = dev->config;
struct mcux_qtmr_data *data = dev->data;
uint32_t current = QTMR_GetCurrentTimerCount(config->base, config->channel);
QTMR_ClearStatusFlags(config->base, config->channel, status);
barrier_dsync_fence_full();
if ((status & kQTMR_Compare1Flag) && data->alarm_callback) {
QTMR_DisableInterrupts(config->base, config->channel,
kQTMR_Compare1InterruptEnable);
data->interrupt_mask &= ~kQTMR_Compare1InterruptEnable;
counter_alarm_callback_t alarm_cb = data->alarm_callback;
data->alarm_callback = NULL;
alarm_cb(dev, config->channel, current, data->alarm_user_data);
}
if ((status & kQTMR_OverflowFlag) && data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
/**
* @brief ISR for the QTMR
*
* @param timers array containing the counter devices for each channel of the timer module
*/
static void mcux_qtmr_isr(const struct device *timers[])
{
/* the interrupt can be triggered by any of the four channels of the QTMR. Check status
* of all channels and trigger the ISR for the channel(s) that has/have triggered the
* interrupt.
*/
for (qtmr_channel_selection_t ch = kQTMR_Channel_0; ch <= kQTMR_Channel_3 ; ch++) {
if (timers[ch] != NULL) {
const struct mcux_qtmr_config *config = timers[ch]->config;
struct mcux_qtmr_data *data = timers[ch]->data;
uint32_t channel_status = QTMR_GetStatus(config->base, ch);
if ((channel_status & data->interrupt_mask) != 0) {
mcux_qtmr_timer_handler(timers[ch], channel_status);
}
}
}
}
#define INIT_TIMER(node_id) [DT_PROP(node_id, channel)] = DEVICE_DT_GET(node_id),
#define QTMR_DEVICE_INIT_MCUX(n) \
static const struct device *const timers_##n[4] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(n), INIT_TIMER) \
}; \
static int init_irq_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_qtmr_isr, \
timers_##n, 0); \
irq_enable(DT_INST_IRQN(n)); \
return 0; \
} \
\
SYS_INIT(init_irq_##n, POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY);
DT_INST_FOREACH_STATUS_OKAY(QTMR_DEVICE_INIT_MCUX)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT nxp_imx_tmr
static int mcux_qtmr_start(const struct device *dev)
{
const struct mcux_qtmr_config *config = dev->config;
QTMR_StartTimer(config->base, config->channel, config->mode);
return 0;
}
static int mcux_qtmr_stop(const struct device *dev)
{
const struct mcux_qtmr_config *config = dev->config;
QTMR_StopTimer(config->base, config->channel);
return 0;
}
static int mcux_qtmr_get_value(const struct device *dev, uint32_t *ticks)
{
const struct mcux_qtmr_config *config = dev->config;
*ticks = QTMR_GetCurrentTimerCount(config->base, config->channel);
return 0;
}
static int mcux_qtmr_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct mcux_qtmr_config *config = dev->config;
struct mcux_qtmr_data *data = dev->data;
uint32_t current;
uint32_t ticks;
if (chan_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
if (data->alarm_callback) {
return -EBUSY;
}
data->alarm_callback = alarm_cfg->callback;
data->alarm_user_data = alarm_cfg->user_data;
current = QTMR_GetCurrentTimerCount(config->base, config->channel);
ticks = alarm_cfg->ticks;
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
ticks += current;
}
/* this timer always counts up. */
config->base->CHANNEL[config->channel].COMP1 = ticks;
data->interrupt_mask |= kQTMR_Compare1InterruptEnable;
QTMR_EnableInterrupts(config->base, config->channel, data->interrupt_mask);
return 0;
}
static int mcux_qtmr_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
const struct mcux_qtmr_config *config = dev->config;
struct mcux_qtmr_data *data = dev->data;
if (chan_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
QTMR_DisableInterrupts(config->base, config->channel, data->interrupt_mask);
data->interrupt_mask &= ~kQTMR_Compare1InterruptEnable;
data->alarm_callback = NULL;
return 0;
}
static uint32_t mcux_qtmr_get_pending_int(const struct device *dev)
{
const struct mcux_qtmr_config *config = dev->config;
return QTMR_GetStatus(config->base, config->channel);
}
static int mcux_qtmr_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct mcux_qtmr_config *config = dev->config;
struct mcux_qtmr_data *data = dev->data;
if (cfg->ticks != config->info.max_top_value) {
LOG_ERR("Wrap can only be set to 0x%x",
config->info.max_top_value);
return -ENOTSUP;
}
if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) == 0) {
if ((config->base->CHANNEL[config->channel].CTRL & TMR_CTRL_DIR_MASK) != 0U) {
/* counting down, reset to UINT16MAX */
config->base->CHANNEL[config->channel].CNTR = UINT16_MAX;
} else {
/* counting up, reset to 0 */
config->base->CHANNEL[config->channel].CNTR = 0;
}
}
if (cfg->callback != NULL) {
data->top_callback = cfg->callback;
data->top_user_data = cfg->user_data;
data->interrupt_mask |= kQTMR_OverflowInterruptEnable;
QTMR_EnableInterrupts(config->base, config->channel, kQTMR_OverflowInterruptEnable);
}
return 0;
}
static uint32_t mcux_qtmr_get_top_value(const struct device *dev)
{
const struct mcux_qtmr_config *config = dev->config;
return config->info.max_top_value;
}
static uint32_t mcux_qtmr_get_freq(const struct device *dev)
{
struct mcux_qtmr_data *data = dev->data;
return data->freq;
}
/**
* @brief look up table for dividers when using internal clock sources kQTMR_ClockDivide_1 to
* kQTMR_ClockDivide_128
*/
static const uint8_t qtmr_primary_source_divider[] = {1, 2, 4, 8, 16, 32, 64, 128};
static int mcux_qtmr_init(const struct device *dev)
{
const struct mcux_qtmr_config *config = dev->config;
struct mcux_qtmr_data *data = dev->data;
if (config->qtmr_config.primarySource < kQTMR_ClockDivide_1) {
/* for external sources, use the value from the dts (if given) */
data->freq = config->info.freq;
} else {
/* bus clock with divider */
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&data->freq)) {
return -EINVAL;
}
data->freq /= qtmr_primary_source_divider[config->qtmr_config.primarySource -
kQTMR_ClockDivide_1];
}
QTMR_Init(config->base, config->channel, &config->qtmr_config);
return 0;
}
static const struct counter_driver_api mcux_qtmr_driver_api = {
.start = mcux_qtmr_start,
.stop = mcux_qtmr_stop,
.get_value = mcux_qtmr_get_value,
.set_alarm = mcux_qtmr_set_alarm,
.cancel_alarm = mcux_qtmr_cancel_alarm,
.set_top_value = mcux_qtmr_set_top_value,
.get_pending_int = mcux_qtmr_get_pending_int,
.get_top_value = mcux_qtmr_get_top_value,
.get_freq = mcux_qtmr_get_freq,
};
#define TMR_DEVICE_INIT_MCUX(n) \
static struct mcux_qtmr_data mcux_qtmr_data_ ## n; \
\
static const struct mcux_qtmr_config mcux_qtmr_config_ ## n = { \
.base = (void *)DT_REG_ADDR(DT_INST_PARENT(n)), \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
.clock_subsys = \
(clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), name), \
.info = { \
.max_top_value = UINT16_MAX, \
.freq = DT_INST_PROP_OR(n, freq, 0), \
.channels = 1, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
}, \
.channel = DT_INST_PROP(n, channel), \
.qtmr_config = { \
.debugMode = kQTMR_RunNormalInDebug, \
.enableExternalForce = false, \
.enableMasterMode = false, \
.faultFilterCount = DT_INST_PROP_OR(n, filter_count, 0), \
.faultFilterPeriod = DT_INST_PROP_OR(n, filter_count, 0), \
.primarySource = DT_INST_ENUM_IDX(n, primary_source), \
.secondarySource = DT_INST_ENUM_IDX_OR(n, secondary_source, 0), \
}, \
.mode = DT_INST_ENUM_IDX(n, mode), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
mcux_qtmr_init, \
NULL, \
&mcux_qtmr_data_ ## n, \
&mcux_qtmr_config_ ## n, \
POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, \
&mcux_qtmr_driver_api); \
DT_INST_FOREACH_STATUS_OKAY(TMR_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/counter/counter_mcux_qtmr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,848 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_rtcc
#include <stddef.h>
#include <string.h>
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <soc.h>
#include <em_cmu.h>
#include <em_rtcc.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(counter_gecko, CONFIG_COUNTER_LOG_LEVEL);
#define RTCC_MAX_VALUE (_RTCC_CNT_MASK)
#define RTCC_ALARM_NUM 2
struct counter_gecko_config {
struct counter_config_info info;
void (*irq_config)(void);
uint32_t prescaler;
};
struct counter_gecko_alarm_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_gecko_data {
struct counter_gecko_alarm_data alarm[RTCC_ALARM_NUM];
counter_top_callback_t top_callback;
void *top_user_data;
};
#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
#define ERRATA_RTCC_E201_MESSAGE \
"Errata RTCC_E201: In case RTCC prescaler != 1 the module does not " \
"reset the counter value on CCV1 compare."
#endif
/* Map channel id to CC channel provided by the RTCC module */
static uint8_t chan_id2cc_idx(uint8_t chan_id)
{
uint8_t cc_idx;
switch (chan_id) {
case 0:
cc_idx = 2;
break;
default:
cc_idx = 0;
break;
}
return cc_idx;
}
static int counter_gecko_start(const struct device *dev)
{
ARG_UNUSED(dev);
RTCC_Enable(true);
return 0;
}
static int counter_gecko_stop(const struct device *dev)
{
ARG_UNUSED(dev);
RTCC_Enable(false);
return 0;
}
static int counter_gecko_get_value(const struct device *dev, uint32_t *ticks)
{
ARG_UNUSED(dev);
*ticks = RTCC_CounterGet();
return 0;
}
static int counter_gecko_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
struct counter_gecko_data *const dev_data = dev->data;
uint32_t ticks;
uint32_t flags;
int err = 0;
#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
const struct counter_gecko_config *const dev_cfg = dev->config;
if (dev_cfg->prescaler != 1) {
LOG_ERR(ERRATA_RTCC_E201_MESSAGE);
return -EINVAL;
}
#endif
/* Counter top value can only be changed when all alarms are disabled */
for (int i = 0; i < RTCC_ALARM_NUM; i++) {
if (dev_data->alarm[i].callback) {
return -EBUSY;
}
}
RTCC_IntClear(RTCC_IF_CC1);
dev_data->top_callback = cfg->callback;
dev_data->top_user_data = cfg->user_data;
ticks = cfg->ticks;
flags = cfg->flags;
if (!(flags & COUNTER_TOP_CFG_DONT_RESET)) {
RTCC_CounterSet(0);
}
RTCC_ChannelCCVSet(1, ticks);
LOG_DBG("set top value: %u", ticks);
if ((flags & COUNTER_TOP_CFG_DONT_RESET) &&
RTCC_CounterGet() > ticks) {
err = -ETIME;
if (flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
RTCC_CounterSet(0);
}
}
/* Enable the compare interrupt */
RTCC_IntEnable(RTCC_IF_CC1);
return err;
}
static uint32_t counter_gecko_get_top_value(const struct device *dev)
{
ARG_UNUSED(dev);
return RTCC_ChannelCCVGet(1);
}
static int counter_gecko_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
uint32_t count = RTCC_CounterGet();
struct counter_gecko_data *const dev_data = dev->data;
uint32_t top_value = counter_gecko_get_top_value(dev);
uint32_t ccv;
if ((top_value != 0) && (alarm_cfg->ticks > top_value)) {
return -EINVAL;
}
if (dev_data->alarm[chan_id].callback != NULL) {
return -EBUSY;
}
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) {
ccv = alarm_cfg->ticks;
} else {
if (top_value == 0) {
ccv = count + alarm_cfg->ticks;
} else {
uint64_t ccv64 = count + alarm_cfg->ticks;
ccv = (uint32_t)(ccv64 % top_value);
}
}
uint8_t cc_idx = chan_id2cc_idx(chan_id);
RTCC_IntClear(RTCC_IF_CC0 << cc_idx);
dev_data->alarm[chan_id].callback = alarm_cfg->callback;
dev_data->alarm[chan_id].user_data = alarm_cfg->user_data;
RTCC_ChannelCCVSet(cc_idx, ccv);
LOG_DBG("set alarm: channel %u, count %u", chan_id, ccv);
/* Enable the compare interrupt */
RTCC_IntEnable(RTCC_IF_CC0 << cc_idx);
return 0;
}
static int counter_gecko_cancel_alarm(const struct device *dev,
uint8_t chan_id)
{
struct counter_gecko_data *const dev_data = dev->data;
uint8_t cc_idx = chan_id2cc_idx(chan_id);
/* Disable the compare interrupt */
RTCC_IntDisable(RTCC_IF_CC0 << cc_idx);
RTCC_IntClear(RTCC_IF_CC0 << cc_idx);
dev_data->alarm[chan_id].callback = NULL;
dev_data->alarm[chan_id].user_data = NULL;
RTCC_ChannelCCVSet(cc_idx, 0);
LOG_DBG("cancel alarm: channel %u", chan_id);
return 0;
}
static uint32_t counter_gecko_get_pending_int(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static int counter_gecko_init(const struct device *dev)
{
const struct counter_gecko_config *const dev_cfg = dev->config;
RTCC_Init_TypeDef rtcc_config = {
false, /* Don't start counting */
false, /* Disable RTC during debug halt. */
false, /* Don't wrap prescaler on CCV0 */
true, /* Counter wrap on CCV1 */
#if defined(_SILICON_LABS_32B_SERIES_2)
(RTCC_CntPresc_TypeDef)(31UL - __CLZ(dev_cfg->prescaler)),
#else
(RTCC_CntPresc_TypeDef)CMU_DivToLog2(dev_cfg->prescaler),
#endif
rtccCntTickPresc, /* Count according to prescaler value */
#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
false, /* Don't store RTCC counter value in
* RTCC_CCV2 upon backup mode entry.
*/
#endif
#if defined(_RTCC_CTRL_OSCFDETEN_MASK)
false, /* Don't enable LFXO fail detection */
#endif
#if defined (_RTCC_CTRL_CNTMODE_MASK)
rtccCntModeNormal, /* Use RTCC in normal mode */
#endif
#if defined (_RTCC_CTRL_LYEARCORRDIS_MASK)
false /* No leap year correction. */
#endif
};
RTCC_CCChConf_TypeDef rtcc_channel_config = {
rtccCapComChModeCompare, /* Use compare mode */
rtccCompMatchOutActionPulse,/* Don't care */
rtccPRSCh0, /* PRS is not used */
rtccInEdgeNone, /* Capture input is not used */
rtccCompBaseCnt, /* Compare with base CNT register */
#if defined (_RTCC_CC_CTRL_COMPMASK_MASK)
0, /* Compare mask */
#endif
#if defined (_RTCC_CC_CTRL_DAYCC_MASK)
rtccDayCompareModeMonth, /* Don't care */
#endif
};
#if defined(cmuClock_CORELE)
/* Ensure LE modules are clocked. */
CMU_ClockEnable(cmuClock_CORELE, true);
#endif
#if defined(CMU_LFECLKEN0_RTCC)
/* Enable LFECLK in CMU (will also enable oscillator if not enabled). */
CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO);
#elif defined(_SILICON_LABS_32B_SERIES_2)
CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFXO);
#else
/* Enable LFACLK in CMU (will also enable oscillator if not enabled). */
CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);
#endif
/* Enable RTCC module clock */
CMU_ClockEnable(cmuClock_RTCC, true);
/* Initialize RTCC */
RTCC_Init(&rtcc_config);
/* Set up compare channels */
RTCC_ChannelInit(0, &rtcc_channel_config);
RTCC_ChannelInit(1, &rtcc_channel_config);
RTCC_ChannelInit(2, &rtcc_channel_config);
/* Disable module's internal interrupt sources */
RTCC_IntDisable(_RTCC_IF_MASK);
RTCC_IntClear(_RTCC_IF_MASK);
/* Clear the counter */
RTCC->CNT = 0;
/* Configure & enable module interrupts */
dev_cfg->irq_config();
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct counter_driver_api counter_gecko_driver_api = {
.start = counter_gecko_start,
.stop = counter_gecko_stop,
.get_value = counter_gecko_get_value,
.set_alarm = counter_gecko_set_alarm,
.cancel_alarm = counter_gecko_cancel_alarm,
.set_top_value = counter_gecko_set_top_value,
.get_pending_int = counter_gecko_get_pending_int,
.get_top_value = counter_gecko_get_top_value,
};
/* RTCC0 */
ISR_DIRECT_DECLARE(counter_gecko_isr_0)
{
const struct device *const dev = DEVICE_DT_INST_GET(0);
struct counter_gecko_data *const dev_data = dev->data;
counter_alarm_callback_t alarm_callback;
uint32_t count = RTCC_CounterGet();
uint32_t flags = RTCC_IntGetEnabled();
RTCC_IntClear(flags);
if (flags & RTCC_IF_CC1) {
if (dev_data->top_callback) {
dev_data->top_callback(dev, dev_data->top_user_data);
}
}
for (int i = 0; i < RTCC_ALARM_NUM; i++) {
uint8_t cc_idx = chan_id2cc_idx(i);
if (flags & (RTCC_IF_CC0 << cc_idx)) {
if (dev_data->alarm[i].callback) {
alarm_callback = dev_data->alarm[i].callback;
dev_data->alarm[i].callback = NULL;
alarm_callback(dev, i, count,
dev_data->alarm[i].user_data);
}
}
}
ISR_DIRECT_PM();
return 1;
}
BUILD_ASSERT((DT_INST_PROP(0, prescaler) > 0U) &&
(DT_INST_PROP(0, prescaler) <= 32768U));
static void counter_gecko_0_irq_config(void)
{
IRQ_DIRECT_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
counter_gecko_isr_0, 0);
irq_enable(DT_INST_IRQN(0));
}
static const struct counter_gecko_config counter_gecko_0_config = {
.info = {
.max_top_value = RTCC_MAX_VALUE,
.freq = DT_INST_PROP(0, clock_frequency) /
DT_INST_PROP(0, prescaler),
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = RTCC_ALARM_NUM,
},
.irq_config = counter_gecko_0_irq_config,
.prescaler = DT_INST_PROP(0, prescaler),
};
static struct counter_gecko_data counter_gecko_0_data;
DEVICE_DT_INST_DEFINE(0, counter_gecko_init, NULL,
&counter_gecko_0_data, &counter_gecko_0_config,
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY,
&counter_gecko_driver_api);
``` | /content/code_sandbox/drivers/counter/counter_gecko_rtcc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,658 |
```unknown
# Counter driver for x86 "CMOS" clock
config COUNTER_CMOS
bool "Counter driver for x86 CMOS/RTC clock"
default y if !RTC
depends on DT_HAS_MOTOROLA_MC146818_ENABLED
``` | /content/code_sandbox/drivers/counter/Kconfig.cmos | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc_ctimer
#include <zephyr/drivers/counter.h>
#include <fsl_ctimer.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(mcux_ctimer, CONFIG_COUNTER_LOG_LEVEL);
#ifdef CONFIG_COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
/* One of the CTimer channels is reserved to implement set_top_value API */
#define NUM_CHANNELS 3
#else
#define NUM_CHANNELS 4
#endif
struct mcux_lpc_ctimer_channel_data {
counter_alarm_callback_t alarm_callback;
void *alarm_user_data;
};
struct mcux_lpc_ctimer_data {
struct mcux_lpc_ctimer_channel_data channels[NUM_CHANNELS];
counter_top_callback_t top_callback;
void *top_user_data;
};
struct mcux_lpc_ctimer_config {
struct counter_config_info info;
CTIMER_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
ctimer_timer_mode_t mode;
ctimer_capture_channel_t input;
uint32_t prescale;
void (*irq_config_func)(const struct device *dev);
};
static int mcux_lpc_ctimer_start(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
CTIMER_StartTimer(config->base);
return 0;
}
static int mcux_lpc_ctimer_stop(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
CTIMER_StopTimer(config->base);
return 0;
}
static uint32_t mcux_lpc_ctimer_read(CTIMER_Type *base)
{
return CTIMER_GetTimerCountValue(base);
}
static int mcux_lpc_ctimer_get_value(const struct device *dev, uint32_t *ticks)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
*ticks = mcux_lpc_ctimer_read(config->base);
return 0;
}
static uint32_t mcux_lpc_ctimer_get_top_value(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
#ifdef CONFIG_COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
CTIMER_Type *base = config->base;
/* Return the top value if it has been set, else return the max top value */
if (base->MR[NUM_CHANNELS] != 0) {
return base->MR[NUM_CHANNELS];
} else {
return config->info.max_top_value;
}
#else
return config->info.max_top_value;
#endif
}
static int mcux_lpc_ctimer_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
struct mcux_lpc_ctimer_data *data = dev->data;
uint32_t ticks = alarm_cfg->ticks;
uint32_t current = mcux_lpc_ctimer_read(config->base);
uint32_t top = mcux_lpc_ctimer_get_top_value(dev);
if (alarm_cfg->ticks > top) {
return -EINVAL;
}
if (data->channels[chan_id].alarm_callback != NULL) {
LOG_ERR("channel already in use");
return -EBUSY;
}
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
ticks += current;
if (ticks > top) {
ticks %= top;
}
}
data->channels[chan_id].alarm_callback = alarm_cfg->callback;
data->channels[chan_id].alarm_user_data = alarm_cfg->user_data;
ctimer_match_config_t match_config = { .matchValue = ticks,
.enableCounterReset = false,
.enableCounterStop = false,
.outControl = kCTIMER_Output_NoAction,
.outPinInitState = false,
.enableInterrupt = true };
CTIMER_SetupMatch(config->base, chan_id, &match_config);
return 0;
}
static int mcux_lpc_ctimer_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
struct mcux_lpc_ctimer_data *data = dev->data;
CTIMER_DisableInterrupts(config->base, (1 << chan_id));
data->channels[chan_id].alarm_callback = NULL;
data->channels[chan_id].alarm_user_data = NULL;
return 0;
}
static int mcux_lpc_ctimer_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
struct mcux_lpc_ctimer_data *data = dev->data;
#ifndef CONFIG_COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
/* Only allow max value when we do not reserve a ctimer channel for setting top value */
if (cfg->ticks != config->info.max_top_value) {
LOG_ERR("Wrap can only be set to 0x%x",
config->info.max_top_value);
return -ENOTSUP;
}
#endif
data->top_callback = cfg->callback;
data->top_user_data = cfg->user_data;
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
CTIMER_Reset(config->base);
} else if (mcux_lpc_ctimer_read(config->base) >= cfg->ticks) {
if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
CTIMER_Reset(config->base);
}
return -ETIME;
}
#ifdef CONFIG_COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
ctimer_match_config_t match_config = { .matchValue = cfg->ticks,
.enableCounterReset = true,
.enableCounterStop = false,
.outControl = kCTIMER_Output_NoAction,
.outPinInitState = false,
.enableInterrupt = true };
CTIMER_SetupMatch(config->base, NUM_CHANNELS, &match_config);
#endif
return 0;
}
static uint32_t mcux_lpc_ctimer_get_pending_int(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
return (CTIMER_GetStatusFlags(config->base) & 0xF) != 0;
}
static uint32_t mcux_lpc_ctimer_get_freq(const struct device *dev)
{
/*
* The frequency of the timer is not known at compile time so we need to
* calculate at runtime when the frequency is known.
*/
const struct mcux_lpc_ctimer_config *config = dev->config;
uint32_t clk_freq = 0;
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clk_freq)) {
LOG_ERR("unable to get clock frequency");
return 0;
}
/* prescale increments when the prescale counter is 0 so if prescale is 1
* the counter is incremented every 2 cycles of the clock so will actually
* divide by 2 hence the addition of 1 to the value here.
*/
return (clk_freq / (config->prescale + 1));
}
static void mcux_lpc_ctimer_isr(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
struct mcux_lpc_ctimer_data *data = dev->data;
uint32_t interrupt_stat = CTIMER_GetStatusFlags(config->base);
CTIMER_ClearStatusFlags(config->base, interrupt_stat);
uint32_t ticks = mcux_lpc_ctimer_read(config->base);
for (uint8_t chan = 0; chan < NUM_CHANNELS; chan++) {
uint8_t channel_mask = 0x01 << chan;
if (((interrupt_stat & channel_mask) != 0) &&
(data->channels[chan].alarm_callback != NULL)) {
counter_alarm_callback_t alarm_callback =
data->channels[chan].alarm_callback;
void *alarm_user_data = data->channels[chan].alarm_user_data;
data->channels[chan].alarm_callback = NULL;
data->channels[chan].alarm_user_data = NULL;
alarm_callback(dev, chan, ticks, alarm_user_data);
}
}
#ifdef CONFIG_COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
if (((interrupt_stat & (0x01 << NUM_CHANNELS)) != 0) && data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
#endif
}
static int mcux_lpc_ctimer_init(const struct device *dev)
{
const struct mcux_lpc_ctimer_config *config = dev->config;
struct mcux_lpc_ctimer_data *data = dev->data;
ctimer_config_t ctimer_config;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
for (uint8_t chan = 0; chan < NUM_CHANNELS; chan++) {
data->channels[chan].alarm_callback = NULL;
data->channels[chan].alarm_user_data = NULL;
}
CTIMER_GetDefaultConfig(&ctimer_config);
ctimer_config.mode = config->mode;
ctimer_config.input = config->input;
ctimer_config.prescale = config->prescale;
CTIMER_Init(config->base, &ctimer_config);
config->irq_config_func(dev);
return 0;
}
static const struct counter_driver_api mcux_ctimer_driver_api = {
.start = mcux_lpc_ctimer_start,
.stop = mcux_lpc_ctimer_stop,
.get_value = mcux_lpc_ctimer_get_value,
.set_alarm = mcux_lpc_ctimer_set_alarm,
.cancel_alarm = mcux_lpc_ctimer_cancel_alarm,
.set_top_value = mcux_lpc_ctimer_set_top_value,
.get_pending_int = mcux_lpc_ctimer_get_pending_int,
.get_top_value = mcux_lpc_ctimer_get_top_value,
.get_freq = mcux_lpc_ctimer_get_freq,
};
#define COUNTER_LPC_CTIMER_DEVICE(id) \
static void mcux_lpc_ctimer_irq_config_##id(const struct device *dev); \
static struct mcux_lpc_ctimer_config mcux_lpc_ctimer_config_##id = { \
.info = { \
.max_top_value = UINT32_MAX, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = NUM_CHANNELS, \
},\
.base = (CTIMER_Type *)DT_INST_REG_ADDR(id), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
.clock_subsys = \
(clock_control_subsys_t)(DT_INST_CLOCKS_CELL(id, name)),\
.mode = DT_INST_PROP(id, mode), \
.input = DT_INST_PROP(id, input), \
.prescale = DT_INST_PROP(id, prescale), \
.irq_config_func = mcux_lpc_ctimer_irq_config_##id, \
}; \
static struct mcux_lpc_ctimer_data mcux_lpc_ctimer_data_##id; \
DEVICE_DT_INST_DEFINE(id, &mcux_lpc_ctimer_init, NULL, &mcux_lpc_ctimer_data_##id, \
&mcux_lpc_ctimer_config_##id, POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, &mcux_ctimer_driver_api); \
static void mcux_lpc_ctimer_irq_config_##id(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), mcux_lpc_ctimer_isr, \
DEVICE_DT_INST_GET(id), 0); \
irq_enable(DT_INST_IRQN(id)); \
}
DT_INST_FOREACH_STATUS_OKAY(COUNTER_LPC_CTIMER_DEVICE)
``` | /content/code_sandbox/drivers/counter/counter_mcux_ctimer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,612 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_gpt
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_gpt.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/barrier.h>
LOG_MODULE_REGISTER(mcux_gpt, CONFIG_COUNTER_LOG_LEVEL);
#define DEV_CFG(_dev) ((const struct mcux_gpt_config *)(_dev)->config)
#define DEV_DATA(_dev) ((struct mcux_gpt_data *)(_dev)->data)
struct mcux_gpt_config {
/* info must be first element */
struct counter_config_info info;
DEVICE_MMIO_NAMED_ROM(gpt_mmio);
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
clock_name_t clock_source;
};
struct mcux_gpt_data {
DEVICE_MMIO_NAMED_RAM(gpt_mmio);
counter_alarm_callback_t alarm_callback;
counter_top_callback_t top_callback;
void *alarm_user_data;
void *top_user_data;
};
static GPT_Type *get_base(const struct device *dev)
{
return (GPT_Type *)DEVICE_MMIO_NAMED_GET(dev, gpt_mmio);
}
static int mcux_gpt_start(const struct device *dev)
{
GPT_Type *base = get_base(dev);
GPT_StartTimer(base);
return 0;
}
static int mcux_gpt_stop(const struct device *dev)
{
GPT_Type *base = get_base(dev);
GPT_StopTimer(base);
return 0;
}
static int mcux_gpt_get_value(const struct device *dev, uint32_t *ticks)
{
GPT_Type *base = get_base(dev);
*ticks = GPT_GetCurrentTimerCount(base);
return 0;
}
static int mcux_gpt_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
GPT_Type *base = get_base(dev);
struct mcux_gpt_data *data = dev->data;
uint32_t current = GPT_GetCurrentTimerCount(base);
uint32_t ticks = alarm_cfg->ticks;
if (chan_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
ticks += current;
}
if (data->alarm_callback) {
return -EBUSY;
}
data->alarm_callback = alarm_cfg->callback;
data->alarm_user_data = alarm_cfg->user_data;
GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel1,
ticks);
GPT_EnableInterrupts(base, kGPT_OutputCompare1InterruptEnable);
return 0;
}
static int mcux_gpt_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
GPT_Type *base = get_base(dev);
struct mcux_gpt_data *data = dev->data;
if (chan_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
GPT_DisableInterrupts(base, kGPT_OutputCompare1InterruptEnable);
data->alarm_callback = NULL;
return 0;
}
void mcux_gpt_isr(const struct device *dev)
{
GPT_Type *base = get_base(dev);
struct mcux_gpt_data *data = dev->data;
uint32_t current = GPT_GetCurrentTimerCount(base);
uint32_t status;
status = GPT_GetStatusFlags(base, kGPT_OutputCompare1Flag |
kGPT_RollOverFlag);
GPT_ClearStatusFlags(base, status);
barrier_dsync_fence_full();
if ((status & kGPT_OutputCompare1Flag) && data->alarm_callback) {
GPT_DisableInterrupts(base,
kGPT_OutputCompare1InterruptEnable);
counter_alarm_callback_t alarm_cb = data->alarm_callback;
data->alarm_callback = NULL;
alarm_cb(dev, 0, current, data->alarm_user_data);
}
if ((status & kGPT_RollOverFlag) && data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
static uint32_t mcux_gpt_get_pending_int(const struct device *dev)
{
GPT_Type *base = get_base(dev);
return GPT_GetStatusFlags(base, kGPT_OutputCompare1Flag);
}
static int mcux_gpt_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct mcux_gpt_config *config = dev->config;
GPT_Type *base = get_base(dev);
struct mcux_gpt_data *data = dev->data;
if (cfg->ticks != config->info.max_top_value) {
LOG_ERR("Wrap can only be set to 0x%x",
config->info.max_top_value);
return -ENOTSUP;
}
data->top_callback = cfg->callback;
data->top_user_data = cfg->user_data;
GPT_EnableInterrupts(base, kGPT_RollOverFlagInterruptEnable);
return 0;
}
static uint32_t mcux_gpt_get_top_value(const struct device *dev)
{
const struct mcux_gpt_config *config = dev->config;
return config->info.max_top_value;
}
static int mcux_gpt_init(const struct device *dev)
{
const struct mcux_gpt_config *config = dev->config;
gpt_config_t gptConfig;
uint32_t clock_freq;
GPT_Type *base;
DEVICE_MMIO_NAMED_MAP(dev, gpt_mmio, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
/* Adjust divider to match expected freq */
if (clock_freq % config->info.freq) {
LOG_ERR("Cannot Adjust GPT freq to %u\n", config->info.freq);
LOG_ERR("clock src is %u\n", clock_freq);
return -EINVAL;
}
GPT_GetDefaultConfig(&gptConfig);
gptConfig.enableFreeRun = true; /* Do not reset on compare */
gptConfig.clockSource = kGPT_ClockSource_Periph;
gptConfig.divider = clock_freq / config->info.freq;
base = get_base(dev);
GPT_Init(base, &gptConfig);
return 0;
}
static const struct counter_driver_api mcux_gpt_driver_api = {
.start = mcux_gpt_start,
.stop = mcux_gpt_stop,
.get_value = mcux_gpt_get_value,
.set_alarm = mcux_gpt_set_alarm,
.cancel_alarm = mcux_gpt_cancel_alarm,
.set_top_value = mcux_gpt_set_top_value,
.get_pending_int = mcux_gpt_get_pending_int,
.get_top_value = mcux_gpt_get_top_value,
};
#define GPT_DEVICE_INIT_MCUX(n) \
static struct mcux_gpt_data mcux_gpt_data_ ## n; \
\
static const struct mcux_gpt_config mcux_gpt_config_ ## n = { \
DEVICE_MMIO_NAMED_ROM_INIT(gpt_mmio, DT_DRV_INST(n)), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
.info = { \
.max_top_value = UINT32_MAX, \
.freq = DT_INST_PROP(n, gptfreq), \
.channels = 1, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
}, \
}; \
\
static int mcux_gpt_## n ##_init(const struct device *dev); \
DEVICE_DT_INST_DEFINE(n, \
mcux_gpt_## n ##_init, \
NULL, \
&mcux_gpt_data_ ## n, \
&mcux_gpt_config_ ## n, \
POST_KERNEL, \
CONFIG_COUNTER_INIT_PRIORITY, \
&mcux_gpt_driver_api); \
\
static int mcux_gpt_## n ##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mcux_gpt_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
return mcux_gpt_init(dev); \
} \
DT_INST_FOREACH_STATUS_OKAY(GPT_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/counter/counter_mcux_gpt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,915 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_epit
#include <zephyr/drivers/counter.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include "clock_freq.h"
#include "epit.h"
#define COUNTER_MAX_RELOAD 0xFFFFFFFF
struct imx_epit_config {
struct counter_config_info info;
EPIT_Type *base;
uint16_t prescaler;
};
struct imx_epit_data {
volatile counter_top_callback_t callback;
volatile void *user_data;
};
static inline const struct imx_epit_config *get_epit_config(const struct device *dev)
{
return CONTAINER_OF(dev->config, struct imx_epit_config,
info);
}
static void imx_epit_isr(const struct device *dev)
{
EPIT_Type *base = get_epit_config(dev)->base;
struct imx_epit_data *driver_data = dev->data;
EPIT_ClearStatusFlag(base);
if (driver_data->callback != NULL) {
driver_data->callback(dev, (void *)driver_data->user_data);
}
}
static void imx_epit_init(const struct device *dev)
{
struct imx_epit_config *config = (struct imx_epit_config *)
get_epit_config(dev);
EPIT_Type *base = config->base;
epit_init_config_t epit_config = {
.freeRun = true,
.waitEnable = true,
.stopEnable = true,
.dbgEnable = true,
.enableMode = true
};
/* Adjust frequency in the counter configuration info */
config->info.freq = get_epit_clock_freq(base)/(config->prescaler + 1U);
EPIT_Init(base, &epit_config);
}
static int imx_epit_start(const struct device *dev)
{
EPIT_Type *base = get_epit_config(dev)->base;
/* Set EPIT clock source */
EPIT_SetClockSource(base, epitClockSourcePeriph);
/* Set prescaler */
EPIT_SetPrescaler(base, get_epit_config(dev)->prescaler);
/* Start the counter */
EPIT_Enable(base);
return 0;
}
static int imx_epit_stop(const struct device *dev)
{
EPIT_Type *base = get_epit_config(dev)->base;
/* Disable EPIT */
EPIT_Disable(base);
return 0;
}
static int imx_epit_get_value(const struct device *dev, uint32_t *ticks)
{
EPIT_Type *base = get_epit_config(dev)->base;
*ticks = EPIT_GetCounterLoadValue(base) - EPIT_ReadCounter(base);
return 0;
}
static int imx_epit_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
EPIT_Type *base = get_epit_config(dev)->base;
struct imx_epit_data *driver_data = dev->data;
/* Disable EPIT Output Compare interrupt for consistency */
EPIT_SetIntCmd(base, false);
driver_data->callback = cfg->callback;
driver_data->user_data = cfg->user_data;
/* Set reload value and optionally counter to "ticks" */
EPIT_SetOverwriteCounter(base,
!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET));
EPIT_SetCounterLoadValue(base, cfg->ticks);
if (cfg->callback != NULL) {
/* (Re)enable EPIT Output Compare interrupt */
EPIT_SetIntCmd(base, true);
}
return 0;
}
static uint32_t imx_epit_get_pending_int(const struct device *dev)
{
EPIT_Type *base = get_epit_config(dev)->base;
return EPIT_GetStatusFlag(base) ? 1U : 0U;
}
static uint32_t imx_epit_get_top_value(const struct device *dev)
{
EPIT_Type *base = get_epit_config(dev)->base;
return EPIT_GetCounterLoadValue(base);
}
static const struct counter_driver_api imx_epit_driver_api = {
.start = imx_epit_start,
.stop = imx_epit_stop,
.get_value = imx_epit_get_value,
.set_top_value = imx_epit_set_top_value,
.get_pending_int = imx_epit_get_pending_int,
.get_top_value = imx_epit_get_top_value,
};
#define COUNTER_IMX_EPIT_DEVICE(idx) \
static int imx_epit_config_func_##idx(const struct device *dev); \
static const struct imx_epit_config imx_epit_##idx##z_config = { \
.info = { \
.max_top_value = COUNTER_MAX_RELOAD, \
.freq = 1U, \
.flags = 0, \
.channels = 0U, \
}, \
.base = (EPIT_Type *)DT_INST_REG_ADDR(idx), \
.prescaler = DT_INST_PROP(idx, prescaler), \
}; \
static struct imx_epit_data imx_epit_##idx##_data; \
DEVICE_DT_INST_DEFINE(idx, \
&imx_epit_config_func_##idx, \
NULL, \
&imx_epit_##idx##_data, &imx_epit_##idx##z_config.info, \
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&imx_epit_driver_api); \
static int imx_epit_config_func_##idx(const struct device *dev) \
{ \
imx_epit_init(dev); \
IRQ_CONNECT(DT_INST_IRQN(idx), \
DT_INST_IRQ(idx, priority), \
imx_epit_isr, DEVICE_DT_INST_GET(idx), 0); \
irq_enable(DT_INST_IRQN(idx)); \
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(COUNTER_IMX_EPIT_DEVICE)
``` | /content/code_sandbox/drivers/counter/counter_imx_epit.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,277 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_tc32
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(counter_sam0_tc32, CONFIG_COUNTER_LOG_LEVEL);
struct counter_sam0_tc32_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_sam0_tc32_data {
counter_top_callback_t top_cb;
void *top_user_data;
struct counter_sam0_tc32_ch_data ch;
};
struct counter_sam0_tc32_config {
struct counter_config_info info;
TcCount32 *regs;
const struct pinctrl_dev_config *pcfg;
#ifdef MCLK
volatile uint32_t *mclk;
uint32_t mclk_mask;
uint16_t gclk_id;
#else
uint32_t pm_apbcmask;
uint16_t gclk_clkctrl_id;
#endif
uint16_t prescaler;
void (*irq_config_func)(const struct device *dev);
};
static void wait_synchronization(TcCount32 *regs)
{
#if defined(TC_SYNCBUSY_MASK)
/* SYNCBUSY is a register */
while ((regs->SYNCBUSY.reg & TC_SYNCBUSY_MASK) != 0) {
}
#elif defined(TC_STATUS_SYNCBUSY)
/* SYNCBUSY is a bit */
while ((regs->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) {
}
#else
#error Unsupported device
#endif
}
static void read_synchronize_count(TcCount32 *regs)
{
#if defined(TC_READREQ_RREQ)
regs->READREQ.reg = TC_READREQ_RREQ |
TC_READREQ_ADDR(TC_COUNT32_COUNT_OFFSET);
wait_synchronization(regs);
#elif defined(TC_CTRLBSET_CMD_READSYNC)
regs->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
wait_synchronization(regs);
#else
ARG_UNUSED(regs);
#endif
}
static int counter_sam0_tc32_start(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
/*
* This will also reset the current counter value if it's
* already running.
*/
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
wait_synchronization(tc);
return 0;
}
static int counter_sam0_tc32_stop(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
/*
* The older (pre SAML1x) manuals claim the counter retains its
* value on stop, but this doesn't actually seem to happen.
* The SAML1x manual says it resets, which is what the SAMD21
* counter actually appears to do.
*/
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
wait_synchronization(tc);
return 0;
}
static uint32_t counter_sam0_tc32_read(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
read_synchronize_count(tc);
return tc->COUNT.reg;
}
static int counter_sam0_tc32_get_value(const struct device *dev,
uint32_t *ticks)
{
*ticks = counter_sam0_tc32_read(dev);
return 0;
}
static void counter_sam0_tc32_relative_alarm(const struct device *dev,
uint32_t ticks)
{
struct counter_sam0_tc32_data *data = dev->data;
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
uint32_t before;
uint32_t target;
uint32_t after;
uint32_t max;
read_synchronize_count(tc);
before = tc->COUNT.reg;
target = before + ticks;
max = tc->CC[0].reg;
if (target > max) {
target -= max;
}
tc->CC[1].reg = target;
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC1;
read_synchronize_count(tc);
after = tc->COUNT.reg;
/* Pending now, so no further checking required */
if (tc->INTFLAG.bit.MC1) {
goto out_future;
}
/*
* Check if we missed the interrupt and call the handler
* immediately if we did.
*/
if (after < target) {
goto out_future;
}
/* Check wrapped */
if (target < before && after >= before) {
goto out_future;
}
counter_alarm_callback_t cb = data->ch.callback;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
tc->INTFLAG.reg = TC_INTFLAG_MC1;
data->ch.callback = NULL;
cb(dev, 0, target, data->ch.user_data);
return;
out_future:
tc->INTENSET.reg = TC_INTFLAG_MC1;
}
static int counter_sam0_tc32_set_alarm(const struct device *dev,
uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
struct counter_sam0_tc32_data *data = dev->data;
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
ARG_UNUSED(chan_id);
if (alarm_cfg->ticks > tc->CC[0].reg) {
return -EINVAL;
}
unsigned int key = irq_lock();
if (data->ch.callback) {
irq_unlock(key);
return -EBUSY;
}
data->ch.callback = alarm_cfg->callback;
data->ch.user_data = alarm_cfg->user_data;
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) {
tc->CC[1].reg = alarm_cfg->ticks;
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC1;
tc->INTENSET.reg = TC_INTFLAG_MC1;
} else {
counter_sam0_tc32_relative_alarm(dev, alarm_cfg->ticks);
}
irq_unlock(key);
return 0;
}
static int counter_sam0_tc32_cancel_alarm(const struct device *dev,
uint8_t chan_id)
{
struct counter_sam0_tc32_data *data = dev->data;
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
unsigned int key = irq_lock();
ARG_UNUSED(chan_id);
data->ch.callback = NULL;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
tc->INTFLAG.reg = TC_INTFLAG_MC1;
irq_unlock(key);
return 0;
}
static int counter_sam0_tc32_set_top_value(const struct device *dev,
const struct counter_top_cfg *top_cfg)
{
struct counter_sam0_tc32_data *data = dev->data;
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
int err = 0;
unsigned int key = irq_lock();
if (data->ch.callback) {
irq_unlock(key);
return -EBUSY;
}
if (top_cfg->callback) {
data->top_cb = top_cfg->callback;
data->top_user_data = top_cfg->user_data;
tc->INTENSET.reg = TC_INTFLAG_MC0;
} else {
tc->INTENCLR.reg = TC_INTFLAG_MC0;
}
tc->CC[0].reg = top_cfg->ticks;
if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
/*
* Top trigger is on equality of the rising edge only, so
* manually reset it if the counter has missed the new top.
*/
if (counter_sam0_tc32_read(dev) >= top_cfg->ticks) {
err = -ETIME;
if (top_cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
}
}
} else {
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
}
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC0;
irq_unlock(key);
return err;
}
static uint32_t counter_sam0_tc32_get_pending_int(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
return tc->INTFLAG.reg & (TC_INTFLAG_MC0 | TC_INTFLAG_MC1);
}
static uint32_t counter_sam0_tc32_get_top_value(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
/*
* Unsync read is safe here because we're not using
* capture mode, so things are only set from the CPU
* end.
*/
return tc->CC[0].reg;
}
static void counter_sam0_tc32_isr(const struct device *dev)
{
struct counter_sam0_tc32_data *data = dev->data;
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
uint8_t status = tc->INTFLAG.reg;
/* Acknowledge all interrupts */
tc->INTFLAG.reg = status;
if (status & TC_INTFLAG_MC1) {
if (data->ch.callback) {
counter_alarm_callback_t cb = data->ch.callback;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
data->ch.callback = NULL;
cb(dev, 0, tc->CC[1].reg, data->ch.user_data);
}
}
if (status & TC_INTFLAG_MC0) {
if (data->top_cb) {
data->top_cb(dev, data->top_user_data);
}
}
}
static int counter_sam0_tc32_initialize(const struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = dev->config;
TcCount32 *tc = cfg->regs;
int retval;
#ifdef MCLK
/* Enable the GCLK */
GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
GCLK_PCHCTRL_CHEN;
/* Enable TC clock in MCLK */
*cfg->mclk |= cfg->mclk_mask;
#else
/* Enable the GCLK */
GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
/* Enable clock in PM */
PM->APBCMASK.reg |= cfg->pm_apbcmask;
#endif
/*
* In 32 bit mode, NFRQ mode always uses MAX as the counter top, so
* use MFRQ mode which uses CC0 as the top at the expense of only
* having CC1 available for alarms.
*/
tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 |
#ifdef TC_CTRLA_WAVEGEN_MFRQ
TC_CTRLA_WAVEGEN_MFRQ |
#endif
cfg->prescaler;
wait_synchronization(tc);
#ifdef TC_WAVE_WAVEGEN_MFRQ
tc->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
#endif
/* Disable all interrupts */
tc->INTENCLR.reg = TC_INTENCLR_MASK;
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* Set the initial top as the maximum */
tc->CC[0].reg = UINT32_MAX;
cfg->irq_config_func(dev);
tc->CTRLA.bit.ENABLE = 1;
wait_synchronization(tc);
/* Stop the counter initially */
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
wait_synchronization(tc);
return 0;
}
static const struct counter_driver_api counter_sam0_tc32_driver_api = {
.start = counter_sam0_tc32_start,
.stop = counter_sam0_tc32_stop,
.get_value = counter_sam0_tc32_get_value,
.set_alarm = counter_sam0_tc32_set_alarm,
.cancel_alarm = counter_sam0_tc32_cancel_alarm,
.set_top_value = counter_sam0_tc32_set_top_value,
.get_pending_int = counter_sam0_tc32_get_pending_int,
.get_top_value = counter_sam0_tc32_get_top_value,
};
#ifdef MCLK
#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),
#else
#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),
#endif
#define SAM0_TC32_PRESCALER(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, prescaler), \
(DT_INST_PROP(n, prescaler)), (1))
#define COUNTER_SAM0_TC32_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void counter_sam0_tc32_config_##n(const struct device *dev); \
static const struct counter_sam0_tc32_config \
\
counter_sam0_tc32_dev_config_##n = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / \
SAM0_TC32_PRESCALER(n), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1 \
}, \
.regs = (TcCount32 *)DT_INST_REG_ADDR(n), \
COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV, \
SAM0_TC32_PRESCALER(n)), \
.irq_config_func = &counter_sam0_tc32_config_##n, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct counter_sam0_tc32_data counter_sam0_tc32_dev_data_##n;\
\
DEVICE_DT_INST_DEFINE(n, \
&counter_sam0_tc32_initialize, \
NULL, \
&counter_sam0_tc32_dev_data_##n, \
&counter_sam0_tc32_dev_config_##n, \
PRE_KERNEL_1, \
CONFIG_COUNTER_INIT_PRIORITY, \
&counter_sam0_tc32_driver_api); \
\
static void counter_sam0_tc32_config_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
counter_sam0_tc32_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(COUNTER_SAM0_TC32_DEVICE)
``` | /content/code_sandbox/drivers/counter/counter_sam0_tc32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,449 |
```c
/*
*
*/
#include <zephyr/drivers/counter.h>
#include <zephyr/shell/shell.h>
#include <stdio.h>
#include <ctype.h>
#include <stdlib.h>
#define ARGV_DEV 1
#define ARGV_CHN 2
#define ARGV_PERIODIC_TIME 2
#define ARGV_ONESHOT_TIME 3
/* number of periodic interrupts */
#define PERIODIC_CYCLES 10
#define MAX_DELAY UINT32_MAX
#define MAX_CHANNEL 255U
static struct k_sem timer_sem;
void timer_top_handler(const struct device *counter_dev, void *user_data)
{
ARG_UNUSED(counter_dev);
k_sem_give(&timer_sem);
}
void timer_alarm_handler(const struct device *counter_dev, uint8_t chan_id,
uint32_t ticks, void *user_data)
{
ARG_UNUSED(counter_dev);
k_sem_give(&timer_sem);
}
static int cmd_timer_free_running(const struct shell *shctx, size_t argc, char **argv)
{
ARG_UNUSED(argc);
int err = 0;
const struct device *timer_dev;
timer_dev = device_get_binding(argv[ARGV_DEV]);
if (!timer_dev) {
shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]);
return -ENODEV;
}
/* start timer in free running mode */
err = counter_start(timer_dev);
if (err != 0) {
shell_error(shctx, "%s is not available err:%d", argv[ARGV_DEV], err);
return err;
}
shell_info(shctx, "%s: Timer is freerunning", argv[ARGV_DEV]);
return 0;
}
static int cmd_timer_stop(const struct shell *shctx, size_t argc, char **argv)
{
ARG_UNUSED(argc);
uint32_t ticks1 = 0, ticks2 = 0;
const struct device *timer_dev;
timer_dev = device_get_binding(argv[ARGV_DEV]);
if (!timer_dev) {
shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]);
return -ENODEV;
}
counter_stop(timer_dev);
counter_get_value(timer_dev, &ticks1);
counter_get_value(timer_dev, &ticks2);
if (ticks1 == ticks2) {
shell_info(shctx, "Timer Stopped");
} else {
shell_error(shctx, "Failed to stop timer");
return -EIO;
}
return 0;
}
static int cmd_timer_oneshot(const struct shell *shctx, size_t argc, char **argv)
{
ARG_UNUSED(argc);
int err = 0;
unsigned long delay = 0;
unsigned long channel = 0;
const struct device *timer_dev;
struct counter_alarm_cfg alarm_cfg;
k_sem_init(&timer_sem, 0, 1);
timer_dev = device_get_binding(argv[ARGV_DEV]);
if (!timer_dev) {
shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]);
return -ENODEV;
}
delay = shell_strtoul(argv[ARGV_ONESHOT_TIME], 10, &err);
if (err != 0) {
shell_error(shctx, "invalid delay parameter");
return err;
} else if (delay > MAX_DELAY) {
shell_error(shctx, "delay out of range");
return -ERANGE;
}
channel = shell_strtoul(argv[ARGV_CHN], 10, &err);
if (err != 0) {
shell_error(shctx, "invalid channel parameter");
return err;
} else if (channel > MAX_CHANNEL) {
shell_error(shctx, "channel out of range");
return -ERANGE;
}
alarm_cfg.flags = 0;
alarm_cfg.ticks = counter_us_to_ticks(timer_dev, (uint64_t)delay);
alarm_cfg.callback = timer_alarm_handler;
alarm_cfg.user_data = NULL;
/* set an alarm */
err = counter_set_channel_alarm(timer_dev, (uint8_t)channel, &alarm_cfg);
if (err != 0) {
shell_error(shctx, "%s:Failed to set channel alarm, err:%d", argv[ARGV_DEV], err);
return err;
}
k_sem_take(&timer_sem, K_FOREVER);
shell_info(shctx, "%s: Alarm triggered", argv[ARGV_DEV]);
return 0;
}
static int cmd_timer_periodic(const struct shell *shctx, size_t argc, char **argv)
{
ARG_UNUSED(argc);
uint32_t count = 0;
int err = 0;
unsigned long delay = 0;
const struct device *timer_dev;
struct counter_top_cfg top_cfg;
k_sem_init(&timer_sem, 0, 1);
timer_dev = device_get_binding(argv[ARGV_DEV]);
if (!timer_dev) {
shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]);
return -ENODEV;
}
delay = shell_strtoul(argv[ARGV_PERIODIC_TIME], 10, &err);
if (err != 0) {
shell_error(shctx, "invalid delay parameter");
return err;
} else if (delay > MAX_DELAY) {
shell_error(shctx, "delay out of range");
return -ERANGE;
}
top_cfg.flags = 0;
top_cfg.ticks = counter_us_to_ticks(timer_dev, (uint64_t)delay);
/* interrupt will be triggered periodically */
top_cfg.callback = timer_top_handler;
top_cfg.user_data = NULL;
/* set top value */
err = counter_set_top_value(timer_dev, &top_cfg);
if (err != 0) {
shell_error(shctx, "%s: failed to set top value, err: %d", argv[ARGV_DEV], err);
return err;
}
/* Checking periodic interrupt for PERIODIC_CYCLES times and then unblocking shell.
* Timer is still running and interrupt is triggered periodically.
*/
while (++count < PERIODIC_CYCLES) {
k_sem_take(&timer_sem, K_FOREVER);
}
shell_info(shctx, "%s: periodic timer triggered for %d times", argv[ARGV_DEV], count);
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(sub_timer,
SHELL_CMD_ARG(periodic, NULL,
"timer periodic <timer_instance_node_id> <time_in_us>",
cmd_timer_periodic, 3, 0),
SHELL_CMD_ARG(oneshot, NULL,
"timer oneshot <timer_instance_node_id> <channel_id> <time_in_us>",
cmd_timer_oneshot, 4, 0),
SHELL_CMD_ARG(freerun, NULL,
"timer freerun <timer_instance_node_id>",
cmd_timer_free_running, 2, 0),
SHELL_CMD_ARG(stop, NULL,
"timer stop <timer_instance_node_id>",
cmd_timer_stop, 2, 0),
SHELL_SUBCMD_SET_END /* array terminated. */
);
SHELL_CMD_REGISTER(timer, &sub_timer, "Timer commands", NULL);
``` | /content/code_sandbox/drivers/counter/counter_timer_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,531 |
```unknown
#
#
config COUNTER_MAXIM_DS3231
bool "Maxim DS3231 RTC/TCXO"
default y
depends on DT_HAS_MAXIM_DS3231_ENABLED
depends on I2C
select POLL
select NOTIFY
help
Enable counter driver based on Maxim DS3231 I2C device.
``` | /content/code_sandbox/drivers/counter/Kconfig.maxim_ds3231 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
config COUNTER_SMARTBOND_TIMER
bool "Renesas SmartBond(tm) counter driver"
default y
depends on DT_HAS_RENESAS_SMARTBOND_TIMER_ENABLED
select CLOCK_CONTROL_SMARTBOND
select CLOCK_CONTROL
help
Enable the counter driver for for Renesas SmartBond(tm) family of processors.
``` | /content/code_sandbox/drivers/counter/Kconfig.smartbond_timer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
# MCUXpresso SDK CTIMER
config COUNTER_MCUX_CTIMER
bool "MCUX CTIMER driver"
default y
depends on DT_HAS_NXP_LPC_CTIMER_ENABLED
help
Enable support for MCUX CTIMER driver.
config COUNTER_MCUX_CTIMER_RESERVE_CHANNEL_FOR_SETTOP
bool "reserve a ctimer channel to set the top value"
default y
depends on COUNTER_MCUX_CTIMER
help
This reserves a CTimer channel to set the top value. Without
this the set top value can be set only to the max counter value.
``` | /content/code_sandbox/drivers/counter/Kconfig.mcux_ctimer | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_timer
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <soc/rtc_cntl_reg.h>
#include <soc/timer_group_reg.h>
#include <periph_ctrl.h>
#include <driver/timer_types_legacy.h>
#include <soc/periph_defs.h>
#include <hal/timer_hal.h>
#include <hal/timer_ll.h>
#include <string.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/spinlock.h>
#include <zephyr/kernel.h>
#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL);
#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
#define ISR_HANDLER isr_handler_t
#else
#define ISR_HANDLER intr_handler_t
#endif
static void counter_esp32_isr(void *arg);
typedef bool (*timer_isr_t)(void *);
struct timer_isr_func_t {
timer_isr_t fn;
void *args;
struct intr_handle_data_t *timer_isr_handle;
timer_group_t isr_timer_group;
};
struct counter_esp32_config {
struct counter_config_info counter_info;
timer_config_t config;
timer_group_t group;
timer_idx_t index;
int irq_source;
};
struct counter_esp32_data {
struct counter_alarm_cfg alarm_cfg;
uint32_t ticks;
timer_hal_context_t hal_ctx;
struct timer_isr_func_t timer_isr_fun;
};
static struct k_spinlock lock;
static int counter_esp32_init(const struct device *dev)
{
const struct counter_esp32_config *cfg = dev->config;
struct counter_esp32_data *data = dev->data;
switch (cfg->group) {
case TIMER_GROUP_0:
periph_module_enable(PERIPH_TIMG0_MODULE);
break;
#if !defined(CONFIG_SOC_SERIES_ESP32C2)
case TIMER_GROUP_1:
periph_module_enable(PERIPH_TIMG1_MODULE);
break;
#endif
default:
return -ENOTSUP;
}
k_spinlock_key_t key = k_spin_lock(&lock);
timer_hal_init(&data->hal_ctx, cfg->group, cfg->index);
data->alarm_cfg.callback = NULL;
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
false);
timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
timer_ll_enable_auto_reload(data->hal_ctx.dev, data->hal_ctx.timer_id,
cfg->config.auto_reload);
timer_ll_set_clock_prescale(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.divider);
timer_ll_set_count_direction(data->hal_ctx.dev, data->hal_ctx.timer_id,
cfg->config.counter_dir);
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en);
timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0);
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en);
esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_start(const struct device *dev)
{
struct counter_esp32_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&lock);
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_START);
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_stop(const struct device *dev)
{
struct counter_esp32_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&lock);
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_PAUSE);
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
{
struct counter_esp32_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&lock);
*ticks = timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id);
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
ARG_UNUSED(chan_id);
struct counter_esp32_data *data = dev->data;
uint32_t now;
counter_esp32_get_value(dev, &now);
k_spinlock_key_t key = k_spin_lock(&lock);
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
(now + alarm_cfg->ticks));
} else {
timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
alarm_cfg->ticks);
}
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), true);
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_EN);
data->alarm_cfg.callback = alarm_cfg->callback;
data->alarm_cfg.user_data = alarm_cfg->user_data;
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
ARG_UNUSED(chan_id);
struct counter_esp32_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&lock);
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
false);
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_DIS);
k_spin_unlock(&lock, key);
return 0;
}
static int counter_esp32_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_esp32_config *config = dev->config;
if (cfg->ticks != config->counter_info.max_top_value) {
return -ENOTSUP;
} else {
return 0;
}
}
static uint32_t counter_esp32_get_pending_int(const struct device *dev)
{
struct counter_esp32_data *data = dev->data;
return timer_ll_get_intr_status(data->hal_ctx.dev);
}
static uint32_t counter_esp32_get_top_value(const struct device *dev)
{
const struct counter_esp32_config *config = dev->config;
return config->counter_info.max_top_value;
}
static const struct counter_driver_api counter_api = {
.start = counter_esp32_start,
.stop = counter_esp32_stop,
.get_value = counter_esp32_get_value,
.set_alarm = counter_esp32_set_alarm,
.cancel_alarm = counter_esp32_cancel_alarm,
.set_top_value = counter_esp32_set_top_value,
.get_pending_int = counter_esp32_get_pending_int,
.get_top_value = counter_esp32_get_top_value,
};
static void counter_esp32_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
struct counter_esp32_data *data = dev->data;
uint32_t now;
counter_esp32_cancel_alarm(dev, 0);
counter_esp32_get_value(dev, &now);
if (data->alarm_cfg.callback) {
data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data);
}
timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
}
#define ESP32_COUNTER_GET_CLK_DIV(idx) \
(((DT_INST_PROP(idx, prescaler) & UINT16_MAX) < 2) ? \
2 : (DT_INST_PROP(idx, prescaler) & UINT16_MAX))
#define ESP32_COUNTER_INIT(idx) \
\
static struct counter_esp32_data counter_data_##idx; \
\
static const struct counter_esp32_config counter_config_##idx = { \
.counter_info = { \
.max_top_value = UINT32_MAX, \
.freq = (APB_CLK_FREQ / ESP32_COUNTER_GET_CLK_DIV(idx)), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1 \
}, \
.config = { \
.alarm_en = TIMER_ALARM_DIS, \
.counter_en = TIMER_START, \
.intr_type = TIMER_INTR_LEVEL, \
.counter_dir = TIMER_COUNT_UP, \
.auto_reload = TIMER_AUTORELOAD_DIS, \
.divider = ESP32_COUNTER_GET_CLK_DIV(idx), \
}, \
.group = DT_INST_PROP(idx, group), \
.index = DT_INST_PROP(idx, index), \
.irq_source = DT_INST_IRQN(idx), \
}; \
\
\
DEVICE_DT_INST_DEFINE(idx, \
counter_esp32_init, \
NULL, \
&counter_data_##idx, \
&counter_config_##idx, \
PRE_KERNEL_1, \
CONFIG_COUNTER_INIT_PRIORITY, \
&counter_api);
DT_INST_FOREACH_STATUS_OKAY(ESP32_COUNTER_INIT);
``` | /content/code_sandbox/drivers/counter/counter_esp32_tmr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,098 |
```unknown
# ESP32 RTC Timer configuration
config COUNTER_RTC_ESP32
bool "ESP32 Counter driver based on the RTC Timer"
default y
depends on DT_HAS_ESPRESSIF_ESP32_RTC_TIMER_ENABLED
help
Enables the Counter driver API based on Espressif's RTC
Timer for ESP32 series devices.
``` | /content/code_sandbox/drivers/counter/Kconfig.esp32_rtc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_tc
/** @file
* @brief Atmel SAM MCU family counter (TC) driver.
*
* This version of the driver uses a single channel to provide a basic 16-bit
* counter (on SAM4E series the counter is 32-bit). Remaining TC channels could
* be used in the future to provide additional functionality, e.g. input clock
* divider configured via DT properties.
*
* Remarks:
* - The driver is not thread safe.
* - The driver does not implement guard periods.
* - The driver does not guarantee that short relative alarm will trigger the
* interrupt immediately and not after the full cycle / counter overflow.
*
* Use at your own risk or submit a patch.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/util.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(counter_sam_tc, CONFIG_COUNTER_LOG_LEVEL);
#define MAX_ALARMS_PER_TC_CHANNEL 2
#if defined(CONFIG_SOC_SERIES_SAM4E) || defined(CONFIG_SOC_SERIES_SAM3X)
#define COUNTER_SAM_TOP_VALUE_MAX UINT32_MAX
#else
#define COUNTER_SAM_TOP_VALUE_MAX UINT16_MAX
#define COUNTER_SAM_16_BIT
#endif
/* Device constant configuration parameters */
struct counter_sam_dev_cfg {
struct counter_config_info info;
Tc *regs;
uint32_t reg_cmr;
uint32_t reg_rc;
void (*irq_config_func)(const struct device *dev);
const struct atmel_sam_pmc_config clock_cfg[TCCHANNEL_NUMBER];
const struct pinctrl_dev_config *pcfg;
uint8_t clk_sel;
bool nodivclk;
uint8_t tc_chan_num;
};
struct counter_sam_alarm_data {
counter_alarm_callback_t callback;
void *user_data;
};
/* Device run time data */
struct counter_sam_dev_data {
counter_top_callback_t top_cb;
void *top_user_data;
struct counter_sam_alarm_data alarm[MAX_ALARMS_PER_TC_CHANNEL];
};
static const uint32_t sam_tc_input_freq_table[] = {
#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
USEC_PER_SEC,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 8,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 32,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 128,
32768,
#elif defined(CONFIG_SOC_SERIES_SAM4L)
USEC_PER_SEC,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 2,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 8,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 32,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 128,
#else
SOC_ATMEL_SAM_MCK_FREQ_HZ / 2,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 8,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 32,
SOC_ATMEL_SAM_MCK_FREQ_HZ / 128,
32768,
#endif
USEC_PER_SEC, USEC_PER_SEC, USEC_PER_SEC,
};
static int counter_sam_tc_start(const struct device *dev)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
tc_ch->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
return 0;
}
static int counter_sam_tc_stop(const struct device *dev)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
tc_ch->TC_CCR = TC_CCR_CLKDIS;
return 0;
}
static int counter_sam_tc_get_value(const struct device *dev, uint32_t *ticks)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
*ticks = tc_ch->TC_CV;
return 0;
}
static int counter_sam_tc_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
struct counter_sam_dev_data *data = dev->data;
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
uint32_t top_value;
uint32_t alarm_value;
__ASSERT_NO_MSG(alarm_cfg->callback != NULL);
top_value = tc_ch->TC_RC;
if ((top_value != 0) && (alarm_cfg->ticks > top_value)) {
return -EINVAL;
}
#ifdef COUNTER_SAM_16_BIT
if ((top_value == 0) && (alarm_cfg->ticks > UINT16_MAX)) {
return -EINVAL;
}
#endif
if (data->alarm[chan_id].callback != NULL) {
return -EBUSY;
}
if (chan_id == 0) {
tc_ch->TC_IDR = TC_IDR_CPAS;
} else {
tc_ch->TC_IDR = TC_IDR_CPBS;
}
data->alarm[chan_id].callback = alarm_cfg->callback;
data->alarm[chan_id].user_data = alarm_cfg->user_data;
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) {
alarm_value = alarm_cfg->ticks;
} else {
alarm_value = tc_ch->TC_CV + alarm_cfg->ticks;
if (top_value != 0) {
alarm_value %= top_value;
}
}
if (chan_id == 0) {
tc_ch->TC_RA = alarm_value;
/* Clear interrupt status register */
(void)tc_ch->TC_SR;
tc_ch->TC_IER = TC_IER_CPAS;
} else {
tc_ch->TC_RB = alarm_value;
/* Clear interrupt status register */
(void)tc_ch->TC_SR;
tc_ch->TC_IER = TC_IER_CPBS;
}
LOG_DBG("set alarm: channel %u, count %u", chan_id, alarm_value);
return 0;
}
static int counter_sam_tc_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
struct counter_sam_dev_data *data = dev->data;
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
if (chan_id == 0) {
tc_ch->TC_IDR = TC_IDR_CPAS;
tc_ch->TC_RA = 0;
} else {
tc_ch->TC_IDR = TC_IDR_CPBS;
tc_ch->TC_RB = 0;
}
data->alarm[chan_id].callback = NULL;
data->alarm[chan_id].user_data = NULL;
LOG_DBG("cancel alarm: channel %u", chan_id);
return 0;
}
static int counter_sam_tc_set_top_value(const struct device *dev,
const struct counter_top_cfg *top_cfg)
{
struct counter_sam_dev_data *data = dev->data;
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
int ret = 0;
for (int i = 0; i < MAX_ALARMS_PER_TC_CHANNEL; i++) {
if (data->alarm[i].callback) {
return -EBUSY;
}
}
/* Disable the compare interrupt */
tc_ch->TC_IDR = TC_IDR_CPCS;
data->top_cb = top_cfg->callback;
data->top_user_data = top_cfg->user_data;
tc_ch->TC_RC = top_cfg->ticks;
if ((top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) != 0) {
if (tc_ch->TC_CV >= top_cfg->ticks) {
ret = -ETIME;
if ((top_cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) != 0) {
tc_ch->TC_CCR = TC_CCR_SWTRG;
}
}
} else {
tc_ch->TC_CCR = TC_CCR_SWTRG;
}
/* Enable the compare interrupt */
tc_ch->TC_IER = TC_IER_CPCS;
return ret;
}
static uint32_t counter_sam_tc_get_top_value(const struct device *dev)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
return tc_ch->TC_RC;
}
static uint32_t counter_sam_tc_get_pending_int(const struct device *dev)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
return tc_ch->TC_SR & tc_ch->TC_IMR;
}
static void counter_sam_tc_isr(const struct device *dev)
{
struct counter_sam_dev_data *data = dev->data;
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
uint32_t status;
status = tc_ch->TC_SR;
if ((status & TC_SR_CPAS) != 0) {
tc_ch->TC_IDR = TC_IDR_CPAS;
if (data->alarm[0].callback) {
counter_alarm_callback_t cb = data->alarm[0].callback;
data->alarm[0].callback = NULL;
cb(dev, 0, tc_ch->TC_RA, data->alarm[0].user_data);
}
}
if ((status & TC_SR_CPBS) != 0) {
tc_ch->TC_IDR = TC_IDR_CPBS;
if (data->alarm[1].callback) {
counter_alarm_callback_t cb = data->alarm[1].callback;
data->alarm[1].callback = NULL;
cb(dev, 1, tc_ch->TC_RB, data->alarm[1].user_data);
}
}
if ((status & TC_SR_CPCS) != 0) {
if (data->top_cb) {
data->top_cb(dev, data->top_user_data);
}
}
}
static int counter_sam_initialize(const struct device *dev)
{
const struct counter_sam_dev_cfg *const dev_cfg = dev->config;
Tc *const tc = dev_cfg->regs;
TcChannel *tc_ch = &tc->TcChannel[dev_cfg->tc_chan_num];
int retval;
/* Connect pins to the peripheral */
retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* Enable channel's clock */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&dev_cfg->clock_cfg[dev_cfg->tc_chan_num]);
/* Clock and Mode Selection */
tc_ch->TC_CMR = dev_cfg->reg_cmr;
tc_ch->TC_RC = dev_cfg->reg_rc;
#ifdef TC_EMR_NODIVCLK
if (dev_cfg->nodivclk) {
tc_ch->TC_EMR = TC_EMR_NODIVCLK;
}
#endif
dev_cfg->irq_config_func(dev);
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct counter_driver_api counter_sam_driver_api = {
.start = counter_sam_tc_start,
.stop = counter_sam_tc_stop,
.get_value = counter_sam_tc_get_value,
.set_alarm = counter_sam_tc_set_alarm,
.cancel_alarm = counter_sam_tc_cancel_alarm,
.set_top_value = counter_sam_tc_set_top_value,
.get_top_value = counter_sam_tc_get_top_value,
.get_pending_int = counter_sam_tc_get_pending_int,
};
#define COUNTER_SAM_TC_CMR(n) \
(TC_CMR_TCCLKS(DT_INST_PROP_OR(n, clk, 0)) \
| TC_CMR_WAVEFORM_WAVSEL_UP_RC \
| TC_CMR_WAVE)
#define COUNTER_SAM_TC_REG_CMR(n) \
DT_INST_PROP_OR(n, reg_cmr, COUNTER_SAM_TC_CMR(n))
#define COUNTER_SAM_TC_INPUT_FREQUENCY(n) \
COND_CODE_1(DT_INST_PROP(n, nodivclk), \
(SOC_ATMEL_SAM_MCK_FREQ_HZ), \
(sam_tc_input_freq_table[COUNTER_SAM_TC_REG_CMR(n) \
& TC_CMR_TCCLKS_Msk]))
#define COUNTER_SAM_TC_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static void counter_##n##_sam_config_func(const struct device *dev); \
\
static const struct counter_sam_dev_cfg counter_##n##_sam_config = { \
.info = { \
.max_top_value = COUNTER_SAM_TOP_VALUE_MAX, \
.freq = COUNTER_SAM_TC_INPUT_FREQUENCY(n), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = MAX_ALARMS_PER_TC_CHANNEL \
}, \
.regs = (Tc *)DT_INST_REG_ADDR(n), \
.reg_cmr = COUNTER_SAM_TC_REG_CMR(n), \
.reg_rc = DT_INST_PROP_OR(n, reg_rc, 0), \
.irq_config_func = &counter_##n##_sam_config_func, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.nodivclk = DT_INST_PROP(n, nodivclk), \
.tc_chan_num = DT_INST_PROP_OR(n, channel, 0), \
.clock_cfg = SAM_DT_INST_CLOCKS_PMC_CFG(n), \
}; \
\
static struct counter_sam_dev_data counter_##n##_sam_data; \
\
DEVICE_DT_INST_DEFINE(n, counter_sam_initialize, NULL, \
&counter_##n##_sam_data, &counter_##n##_sam_config, \
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&counter_sam_driver_api); \
\
static void counter_##n##_sam_config_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
DT_INST_IRQ_BY_IDX(n, 0, priority), \
counter_sam_tc_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \
DT_INST_IRQ_BY_IDX(n, 1, priority), \
counter_sam_tc_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 2, irq), \
DT_INST_IRQ_BY_IDX(n, 2, priority), \
counter_sam_tc_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, 2, irq)); \
}
DT_INST_FOREACH_STATUS_OKAY(COUNTER_SAM_TC_INIT)
``` | /content/code_sandbox/drivers/counter/counter_sam_tc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,606 |
```unknown
# MCUXpresso SDK SNVS (Secure) RTC
config COUNTER_MCUX_SNVS
bool "IMX SNVS RTC driver"
default y
depends on DT_HAS_NXP_IMX_SNVS_RTC_ENABLED
help
Enable support for the IMX SNVS High/Low Power clock.
config COUNTER_MCUX_SNVS_SRTC
bool "IMX SNVS SRTC low power support"
depends on COUNTER_MCUX_SNVS
default y
help
Enable the low power SRTC in SNVS to synchronise.
config COUNTER_MCUX_SNVS_SRTC_WAKE
bool "IMX SNVS wake-up on SRTC alarm"
depends on COUNTER_MCUX_SNVS_SRTC
default y
help
Assert Wake-Up Interrupt on SRTC alarm
``` | /content/code_sandbox/drivers/counter/Kconfig.mcux_snvs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 166 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_counter
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/irq.h>
#include <zephyr/sys/atomic.h>
#include <stm32_ll_tim.h>
#include <stm32_ll_rcc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(counter_timer_stm32, CONFIG_COUNTER_LOG_LEVEL);
/* L0 series MCUs only have 16-bit timers and don't have below macro defined */
#ifndef IS_TIM_32B_COUNTER_INSTANCE
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
#endif
/** Maximum number of timer channels. */
#define TIMER_MAX_CH 4U
/** Number of channels for timer by index. */
#define NUM_CH(timx) \
(IS_TIM_CCX_INSTANCE(timx, TIM_CHANNEL_4) ? 4U : \
(IS_TIM_CCX_INSTANCE(timx, TIM_CHANNEL_3) ? 3U : \
(IS_TIM_CCX_INSTANCE(timx, TIM_CHANNEL_2) ? 2U : \
(IS_TIM_CCX_INSTANCE(timx, TIM_CHANNEL_1) ? 1U : \
0))))
/** Channel to compare set function mapping. */
static void(*const set_timer_compare[TIMER_MAX_CH])(TIM_TypeDef *,
uint32_t) = {
LL_TIM_OC_SetCompareCH1, LL_TIM_OC_SetCompareCH2,
LL_TIM_OC_SetCompareCH3, LL_TIM_OC_SetCompareCH4,
};
/** Channel to compare get function mapping. */
#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
static uint32_t(*const get_timer_compare[TIMER_MAX_CH])(const TIM_TypeDef *) = {
LL_TIM_OC_GetCompareCH1, LL_TIM_OC_GetCompareCH2,
LL_TIM_OC_GetCompareCH3, LL_TIM_OC_GetCompareCH4,
};
#else
static uint32_t(*const get_timer_compare[TIMER_MAX_CH])(TIM_TypeDef *) = {
LL_TIM_OC_GetCompareCH1, LL_TIM_OC_GetCompareCH2,
LL_TIM_OC_GetCompareCH3, LL_TIM_OC_GetCompareCH4,
};
#endif
/** Channel to interrupt enable function mapping. */
static void(*const enable_it[TIMER_MAX_CH])(TIM_TypeDef *) = {
LL_TIM_EnableIT_CC1, LL_TIM_EnableIT_CC2,
LL_TIM_EnableIT_CC3, LL_TIM_EnableIT_CC4,
};
/** Channel to interrupt enable function mapping. */
static void(*const disable_it[TIMER_MAX_CH])(TIM_TypeDef *) = {
LL_TIM_DisableIT_CC1, LL_TIM_DisableIT_CC2,
LL_TIM_DisableIT_CC3, LL_TIM_DisableIT_CC4,
};
#ifdef CONFIG_ASSERT
/** Channel to interrupt enable check function mapping. */
#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
static uint32_t(*const check_it_enabled[TIMER_MAX_CH])(const TIM_TypeDef *) = {
LL_TIM_IsEnabledIT_CC1, LL_TIM_IsEnabledIT_CC2,
LL_TIM_IsEnabledIT_CC3, LL_TIM_IsEnabledIT_CC4,
};
#else
static uint32_t(*const check_it_enabled[TIMER_MAX_CH])(TIM_TypeDef *) = {
LL_TIM_IsEnabledIT_CC1, LL_TIM_IsEnabledIT_CC2,
LL_TIM_IsEnabledIT_CC3, LL_TIM_IsEnabledIT_CC4,
};
#endif
#endif
/** Channel to interrupt flag clear function mapping. */
static void(*const clear_it_flag[TIMER_MAX_CH])(TIM_TypeDef *) = {
LL_TIM_ClearFlag_CC1, LL_TIM_ClearFlag_CC2,
LL_TIM_ClearFlag_CC3, LL_TIM_ClearFlag_CC4,
};
struct counter_stm32_data {
counter_top_callback_t top_cb;
void *top_user_data;
uint32_t guard_period;
atomic_t cc_int_pending;
uint32_t freq;
};
struct counter_stm32_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_stm32_config {
struct counter_config_info info;
struct counter_stm32_ch_data *ch_data;
TIM_TypeDef *timer;
uint32_t prescaler;
struct stm32_pclken pclken;
void (*irq_config_func)(const struct device *dev);
uint32_t irqn;
/* Reset controller device configuration */
const struct reset_dt_spec reset;
LOG_INSTANCE_PTR_DECLARE(log);
};
static int counter_stm32_start(const struct device *dev)
{
const struct counter_stm32_config *config = dev->config;
TIM_TypeDef *timer = config->timer;
/* enable counter */
LL_TIM_EnableCounter(timer);
return 0;
}
static int counter_stm32_stop(const struct device *dev)
{
const struct counter_stm32_config *config = dev->config;
TIM_TypeDef *timer = config->timer;
/* disable counter */
LL_TIM_DisableCounter(timer);
return 0;
}
static uint32_t counter_stm32_get_top_value(const struct device *dev)
{
const struct counter_stm32_config *config = dev->config;
return LL_TIM_GetAutoReload(config->timer);
}
static uint32_t counter_stm32_read(const struct device *dev)
{
const struct counter_stm32_config *config = dev->config;
return LL_TIM_GetCounter(config->timer);
}
static int counter_stm32_get_value(const struct device *dev, uint32_t *ticks)
{
*ticks = counter_stm32_read(dev);
return 0;
}
static uint32_t counter_stm32_ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
{
uint32_t to_top;
if (likely(IS_BIT_MASK(top))) {
return (val1 + val2) & top;
}
to_top = top - val1;
return (val2 <= to_top) ? val1 + val2 : val2 - to_top - 1U;
}
static uint32_t counter_stm32_ticks_sub(uint32_t val, uint32_t old, uint32_t top)
{
if (likely(IS_BIT_MASK(top))) {
return (val - old) & top;
}
/* if top is not 2^n-1 */
return (val >= old) ? (val - old) : val + top + 1U - old;
}
static void counter_stm32_counter_stm32_set_cc_int_pending(const struct device *dev, uint8_t chan)
{
const struct counter_stm32_config *config = dev->config;
struct counter_stm32_data *data = dev->data;
atomic_or(&data->cc_int_pending, BIT(chan));
NVIC_SetPendingIRQ(config->irqn);
}
static int counter_stm32_set_cc(const struct device *dev, uint8_t id,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct counter_stm32_config *config = dev->config;
struct counter_stm32_data *data = dev->data;
__ASSERT_NO_MSG(data->guard_period < counter_stm32_get_top_value(dev));
uint32_t val = alarm_cfg->ticks;
uint32_t flags = alarm_cfg->flags;
bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
bool irq_on_late;
TIM_TypeDef *timer = config->timer;
uint32_t top = counter_stm32_get_top_value(dev);
int err = 0;
uint32_t prev_val;
uint32_t now;
uint32_t diff;
uint32_t max_rel_val;
__ASSERT(!check_it_enabled[id](timer),
"Expected that CC interrupt is disabled.");
/* First take care of a risk of an event coming from CC being set to
* next tick. Reconfigure CC to future (now tick is the furthest
* future).
*/
now = counter_stm32_read(dev);
prev_val = get_timer_compare[id](timer);
set_timer_compare[id](timer, now);
clear_it_flag[id](timer);
if (absolute) {
max_rel_val = top - data->guard_period;
irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
} else {
/* If relative value is smaller than half of the counter range
* it is assumed that there is a risk of setting value too late
* and late detection algorithm must be applied. When late
* setting is detected, interrupt shall be triggered for
* immediate expiration of the timer. Detection is performed
* by limiting relative distance between CC and counter.
*
* Note that half of counter range is an arbitrary value.
*/
irq_on_late = val < (top / 2U);
/* limit max to detect short relative being set too late. */
max_rel_val = irq_on_late ? top / 2U : top;
val = counter_stm32_ticks_add(now, val, top);
}
set_timer_compare[id](timer, val);
/* decrement value to detect also case when val == counter_stm32_read(dev). Otherwise,
* condition would need to include comparing diff against 0.
*/
diff = counter_stm32_ticks_sub(val - 1U, counter_stm32_read(dev), top);
if (diff > max_rel_val) {
if (absolute) {
err = -ETIME;
}
/* Interrupt is triggered always for relative alarm and
* for absolute depending on the flag.
*/
if (irq_on_late) {
counter_stm32_counter_stm32_set_cc_int_pending(dev, id);
} else {
config->ch_data[id].callback = NULL;
}
} else {
enable_it[id](timer);
}
return err;
}
static int counter_stm32_set_alarm(const struct device *dev, uint8_t chan,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct counter_stm32_config *config = dev->config;
struct counter_stm32_ch_data *chdata = &config->ch_data[chan];
if (alarm_cfg->ticks > counter_stm32_get_top_value(dev)) {
return -EINVAL;
}
if (chdata->callback) {
return -EBUSY;
}
chdata->callback = alarm_cfg->callback;
chdata->user_data = alarm_cfg->user_data;
return counter_stm32_set_cc(dev, chan, alarm_cfg);
}
static int counter_stm32_cancel_alarm(const struct device *dev, uint8_t chan)
{
const struct counter_stm32_config *config = dev->config;
disable_it[chan](config->timer);
config->ch_data[chan].callback = NULL;
return 0;
}
static int counter_stm32_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_stm32_config *config = dev->config;
TIM_TypeDef *timer = config->timer;
struct counter_stm32_data *data = dev->data;
int err = 0;
for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
/* Overflow can be changed only when all alarms are
* disabled.
*/
if (config->ch_data[i].callback) {
return -EBUSY;
}
}
LL_TIM_DisableIT_UPDATE(timer);
LL_TIM_SetAutoReload(timer, cfg->ticks);
LL_TIM_ClearFlag_UPDATE(timer);
data->top_cb = cfg->callback;
data->top_user_data = cfg->user_data;
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
LL_TIM_SetCounter(timer, 0);
} else if (counter_stm32_read(dev) >= cfg->ticks) {
err = -ETIME;
if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
LL_TIM_SetCounter(timer, 0);
}
}
if (cfg->callback) {
LL_TIM_EnableIT_UPDATE(timer);
}
return err;
}
static uint32_t counter_stm32_get_pending_int(const struct device *dev)
{
const struct counter_stm32_config *cfg = dev->config;
uint32_t pending = 0;
switch (counter_get_num_of_channels(dev)) {
case 4U:
pending |= LL_TIM_IsActiveFlag_CC4(cfg->timer);
__fallthrough;
case 3U:
pending |= LL_TIM_IsActiveFlag_CC3(cfg->timer);
__fallthrough;
case 2U:
pending |= LL_TIM_IsActiveFlag_CC2(cfg->timer);
__fallthrough;
case 1U:
pending |= LL_TIM_IsActiveFlag_CC1(cfg->timer);
}
return !!pending;
}
/**
* Obtain timer clock speed.
*
* @param pclken Timer clock control subsystem.
* @param tim_clk Where computed timer clock will be stored.
*
* @return 0 on success, error code otherwise.
*
* This function is ripped from the PWM driver; TODO handle code duplication.
*/
static int counter_stm32_get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
{
int r;
const struct device *clk;
uint32_t bus_clk, apb_psc;
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (!device_is_ready(clk)) {
return -ENODEV;
}
r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
&bus_clk);
if (r < 0) {
return r;
}
#if defined(CONFIG_SOC_SERIES_STM32H7X)
if (pclken->bus == STM32_CLOCK_BUS_APB1) {
apb_psc = STM32_D2PPRE1;
} else {
apb_psc = STM32_D2PPRE2;
}
#else
if (pclken->bus == STM32_CLOCK_BUS_APB1) {
#if defined(CONFIG_SOC_SERIES_STM32MP1X)
apb_psc = (uint32_t)(READ_BIT(RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV));
#else
apb_psc = STM32_APB1_PRESCALER;
#endif /* CONFIG_SOC_SERIES_STM32MP1X */
}
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f0_rcc)
else {
#if defined(CONFIG_SOC_SERIES_STM32MP1X)
apb_psc = (uint32_t)(READ_BIT(RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV));
#else
apb_psc = STM32_APB2_PRESCALER;
#endif /* CONFIG_SOC_SERIES_STM32MP1X */
}
#endif /* ! st_stm32f0_rcc */
#endif /* CONFIG_SOC_SERIES_STM32H7X */
#if defined(RCC_DCKCFGR_TIMPRE) || defined(RCC_DCKCFGR1_TIMPRE) || \
defined(RCC_CFGR_TIMPRE)
/*
* There are certain series (some F4, F7 and H7) that have the TIMPRE
* bit to control the clock frequency of all the timers connected to
* APB1 and APB2 domains.
*
* Up to a certain threshold value of APB{1,2} prescaler, timer clock
* equals to HCLK. This threshold value depends on TIMPRE setting
* (2 if TIMPRE=0, 4 if TIMPRE=1). Above threshold, timer clock is set
* to a multiple of the APB domain clock PCLK{1,2} (2 if TIMPRE=0, 4 if
* TIMPRE=1).
*/
if (LL_RCC_GetTIMPrescaler() == LL_RCC_TIM_PRESCALER_TWICE) {
/* TIMPRE = 0 */
if (apb_psc <= 2u) {
LL_RCC_ClocksTypeDef clocks;
LL_RCC_GetSystemClocksFreq(&clocks);
*tim_clk = clocks.HCLK_Frequency;
} else {
*tim_clk = bus_clk * 2u;
}
} else {
/* TIMPRE = 1 */
if (apb_psc <= 4u) {
LL_RCC_ClocksTypeDef clocks;
LL_RCC_GetSystemClocksFreq(&clocks);
*tim_clk = clocks.HCLK_Frequency;
} else {
*tim_clk = bus_clk * 4u;
}
}
#else
/*
* If the APB prescaler equals 1, the timer clock frequencies
* are set to the same frequency as that of the APB domain.
* Otherwise, they are set to twice (2) the frequency of the
* APB domain.
*/
if (apb_psc == 1u) {
*tim_clk = bus_clk;
} else {
*tim_clk = bus_clk * 2u;
}
#endif
return 0;
}
static int counter_stm32_init_timer(const struct device *dev)
{
const struct counter_stm32_config *cfg = dev->config;
struct counter_stm32_data *data = dev->data;
TIM_TypeDef *timer = cfg->timer;
LL_TIM_InitTypeDef init;
uint32_t tim_clk;
int r;
/* initialize clock and check its speed */
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t)&cfg->pclken);
if (r < 0) {
LOG_ERR("Could not initialize clock (%d)", r);
return r;
}
r = counter_stm32_get_tim_clk(&cfg->pclken, &tim_clk);
if (r < 0) {
LOG_ERR("Could not obtain timer clock (%d)", r);
return r;
}
data->freq = tim_clk / (cfg->prescaler + 1U);
if (!device_is_ready(cfg->reset.dev)) {
LOG_ERR("reset controller not ready");
return -ENODEV;
}
/* Reset timer to default state using RCC */
(void)reset_line_toggle_dt(&cfg->reset);
/* config/enable IRQ */
cfg->irq_config_func(dev);
/* initialize timer */
LL_TIM_StructInit(&init);
init.Prescaler = cfg->prescaler;
init.CounterMode = LL_TIM_COUNTERMODE_UP;
init.Autoreload = counter_get_max_top_value(dev);
init.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
if (LL_TIM_Init(timer, &init) != SUCCESS) {
LOG_ERR("Could not initialize timer");
return -EIO;
}
return 0;
}
static uint32_t counter_stm32_get_guard_period(const struct device *dev, uint32_t flags)
{
struct counter_stm32_data *data = dev->data;
ARG_UNUSED(flags);
return data->guard_period;
}
static int counter_stm32_set_guard_period(const struct device *dev, uint32_t guard,
uint32_t flags)
{
struct counter_stm32_data *data = dev->data;
ARG_UNUSED(flags);
__ASSERT_NO_MSG(guard < counter_stm32_get_top_value(dev));
data->guard_period = guard;
return 0;
}
static uint32_t counter_stm32_get_freq(const struct device *dev)
{
struct counter_stm32_data *data = dev->data;
return data->freq;
}
static void counter_stm32_top_irq_handle(const struct device *dev)
{
struct counter_stm32_data *data = dev->data;
counter_top_callback_t cb = data->top_cb;
__ASSERT(cb != NULL, "top event enabled - expecting callback");
cb(dev, data->top_user_data);
}
static void counter_stm32_alarm_irq_handle(const struct device *dev, uint32_t id)
{
const struct counter_stm32_config *config = dev->config;
struct counter_stm32_data *data = dev->data;
TIM_TypeDef *timer = config->timer;
struct counter_stm32_ch_data *chdata;
counter_alarm_callback_t cb;
atomic_and(&data->cc_int_pending, ~BIT(id));
disable_it[id](timer);
chdata = &config->ch_data[id];
cb = chdata->callback;
chdata->callback = NULL;
if (cb) {
uint32_t cc_val = get_timer_compare[id](timer);
cb(dev, id, cc_val, chdata->user_data);
}
}
static const struct counter_driver_api counter_stm32_driver_api = {
.start = counter_stm32_start,
.stop = counter_stm32_stop,
.get_value = counter_stm32_get_value,
.set_alarm = counter_stm32_set_alarm,
.cancel_alarm = counter_stm32_cancel_alarm,
.set_top_value = counter_stm32_set_top_value,
.get_pending_int = counter_stm32_get_pending_int,
.get_top_value = counter_stm32_get_top_value,
.get_guard_period = counter_stm32_get_guard_period,
.set_guard_period = counter_stm32_set_guard_period,
.get_freq = counter_stm32_get_freq,
};
#define TIM_IRQ_HANDLE_CC(timx, cc) \
do { \
bool hw_irq = LL_TIM_IsActiveFlag_CC##cc(timer) && \
LL_TIM_IsEnabledIT_CC##cc(timer); \
if (hw_irq || (data->cc_int_pending & BIT(cc - 1U))) { \
if (hw_irq) { \
LL_TIM_ClearFlag_CC##cc(timer); \
} \
counter_stm32_alarm_irq_handle(dev, cc - 1U); \
} \
} while (0)
void counter_stm32_irq_handler(const struct device *dev)
{
const struct counter_stm32_config *config = dev->config;
struct counter_stm32_data *data = dev->data;
TIM_TypeDef *timer = config->timer;
/* Capture compare events */
switch (counter_get_num_of_channels(dev)) {
case 4U:
TIM_IRQ_HANDLE_CC(timer, 4);
__fallthrough;
case 3U:
TIM_IRQ_HANDLE_CC(timer, 3);
__fallthrough;
case 2U:
TIM_IRQ_HANDLE_CC(timer, 2);
__fallthrough;
case 1U:
TIM_IRQ_HANDLE_CC(timer, 1);
}
/* TIM Update event */
if (LL_TIM_IsActiveFlag_UPDATE(timer) && LL_TIM_IsEnabledIT_UPDATE(timer)) {
LL_TIM_ClearFlag_UPDATE(timer);
counter_stm32_top_irq_handle(dev);
}
}
#define TIMER(idx) DT_INST_PARENT(idx)
/** TIMx instance from DT */
#define TIM(idx) ((TIM_TypeDef *)DT_REG_ADDR(TIMER(idx)))
#define COUNTER_DEVICE_INIT(idx) \
BUILD_ASSERT(DT_PROP(TIMER(idx), st_prescaler) <= 0xFFFF, \
"TIMER prescaler out of range"); \
BUILD_ASSERT(NUM_CH(TIM(idx)) <= TIMER_MAX_CH, \
"TIMER too many channels"); \
\
static struct counter_stm32_data counter##idx##_data; \
static struct counter_stm32_ch_data counter##idx##_ch_data[TIMER_MAX_CH]; \
\
static void counter_##idx##_stm32_irq_config(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(TIMER(idx)), \
DT_IRQ(TIMER(idx), priority), \
counter_stm32_irq_handler, \
DEVICE_DT_INST_GET(idx), \
0); \
irq_enable(DT_IRQN(TIMER(idx))); \
} \
\
static const struct counter_stm32_config counter##idx##_config = { \
.info = { \
.max_top_value = \
IS_TIM_32B_COUNTER_INSTANCE(TIM(idx)) ? \
0xFFFFFFFF : 0x0000FFFF, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = NUM_CH(TIM(idx)), \
}, \
.ch_data = counter##idx##_ch_data, \
.timer = TIM(idx), \
.prescaler = DT_PROP(TIMER(idx), st_prescaler), \
.pclken = { \
.bus = DT_CLOCKS_CELL(TIMER(idx), bus), \
.enr = DT_CLOCKS_CELL(TIMER(idx), bits) \
}, \
.irq_config_func = counter_##idx##_stm32_irq_config, \
.irqn = DT_IRQN(TIMER(idx)), \
.reset = RESET_DT_SPEC_GET(TIMER(idx)), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, \
counter_stm32_init_timer, \
NULL, \
&counter##idx##_data, \
&counter##idx##_config, \
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&counter_stm32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(COUNTER_DEVICE_INIT)
``` | /content/code_sandbox/drivers/counter/counter_ll_stm32_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,357 |
```c
/*
*
*/
#include <hardware/timer.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/irq.h>
#include <cmsis_core.h>
#define LOG_LEVEL CONFIG_COUNTER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(counter_rpi_pico_timer, LOG_LEVEL);
#define DT_DRV_COMPAT raspberrypi_pico_timer
struct counter_rpi_pico_timer_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_rpi_pico_timer_data {
struct counter_rpi_pico_timer_ch_data *ch_data;
uint32_t guard_period;
};
struct counter_rpi_pico_timer_config {
struct counter_config_info info;
timer_hw_t *timer;
void (*irq_config)();
const struct device *clk_dev;
clock_control_subsys_t clk_id;
const struct reset_dt_spec reset;
};
static int counter_rpi_pico_timer_start(const struct device *dev)
{
const struct counter_rpi_pico_timer_config *config = dev->config;
config->timer->pause = 0;
return 0;
}
static int counter_rpi_pico_timer_stop(const struct device *dev)
{
const struct counter_rpi_pico_timer_config *config = dev->config;
config->timer->pause = 1u;
config->timer->timelw = 0;
config->timer->timehw = 0;
return 0;
}
static uint32_t counter_rpi_pico_timer_get_top_value(const struct device *dev)
{
const struct counter_rpi_pico_timer_config *config = dev->config;
return config->info.max_top_value;
}
static int counter_rpi_pico_timer_get_value(const struct device *dev, uint32_t *ticks)
{
*ticks = time_us_32();
return 0;
}
static int counter_rpi_pico_timer_set_alarm(const struct device *dev, uint8_t id,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct counter_rpi_pico_timer_config *config = dev->config;
struct counter_rpi_pico_timer_data *data = dev->data;
struct counter_rpi_pico_timer_ch_data *chdata = &data->ch_data[id];
uint64_t target = (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) ? 0 : alarm_cfg->ticks;
absolute_time_t alarm_at;
bool missed;
update_us_since_boot(&alarm_at, config->timer->timerawl + target);
if (alarm_cfg->ticks > counter_rpi_pico_timer_get_top_value(dev)) {
return -EINVAL;
}
if (chdata->callback) {
return -EBUSY;
}
chdata->callback = alarm_cfg->callback;
chdata->user_data = alarm_cfg->user_data;
missed = hardware_alarm_set_target(id, alarm_at);
if (missed) {
if (alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE) {
hardware_alarm_force_irq(id);
}
chdata->callback = NULL;
chdata->user_data = NULL;
return -ETIME;
}
return 0;
}
static int counter_rpi_pico_timer_cancel_alarm(const struct device *dev, uint8_t id)
{
struct counter_rpi_pico_timer_data *data = dev->data;
struct counter_rpi_pico_timer_ch_data *chdata = &data->ch_data[id];
chdata->callback = NULL;
chdata->user_data = NULL;
hardware_alarm_cancel(id);
return 0;
}
static int counter_rpi_pico_timer_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
ARG_UNUSED(dev);
ARG_UNUSED(cfg);
return -ENOTSUP;
}
static uint32_t counter_rpi_pico_timer_get_pending_int(const struct device *dev)
{
return 0;
}
static uint32_t counter_rpi_pico_timer_get_guard_period(const struct device *dev, uint32_t flags)
{
struct counter_rpi_pico_timer_data *data = dev->data;
return data->guard_period;
}
static int counter_rpi_pico_timer_set_guard_period(const struct device *dev, uint32_t guard,
uint32_t flags)
{
struct counter_rpi_pico_timer_data *data = dev->data;
__ASSERT_NO_MSG(guard < counter_rpi_pico_timer_get_top_value(dev));
data->guard_period = guard;
return 0;
}
static void counter_rpi_pico_irq_handle(uint32_t ch, void *arg)
{
struct device *dev = arg;
struct counter_rpi_pico_timer_data *data = dev->data;
counter_alarm_callback_t cb = data->ch_data[ch].callback;
void *user_data = data->ch_data[ch].user_data;
if (cb) {
data->ch_data[ch].callback = NULL;
data->ch_data[ch].user_data = NULL;
cb(dev, ch, time_us_32(), user_data);
}
}
static int counter_rpi_pico_timer_init(const struct device *dev)
{
const struct counter_rpi_pico_timer_config *config = dev->config;
int ret;
ret = clock_control_on(config->clk_dev, config->clk_id);
if (ret < 0) {
return ret;
}
ret = reset_line_toggle_dt(&config->reset);
if (ret < 0) {
return ret;
}
config->irq_config();
return 0;
}
static const struct counter_driver_api counter_rpi_pico_driver_api = {
.start = counter_rpi_pico_timer_start,
.stop = counter_rpi_pico_timer_stop,
.get_value = counter_rpi_pico_timer_get_value,
.set_alarm = counter_rpi_pico_timer_set_alarm,
.cancel_alarm = counter_rpi_pico_timer_cancel_alarm,
.set_top_value = counter_rpi_pico_timer_set_top_value,
.get_pending_int = counter_rpi_pico_timer_get_pending_int,
.get_top_value = counter_rpi_pico_timer_get_top_value,
.get_guard_period = counter_rpi_pico_timer_get_guard_period,
.set_guard_period = counter_rpi_pico_timer_set_guard_period,
};
#define RPI_PICO_TIMER_IRQ_ENABLE(node_id, name, idx) \
do { \
hardware_alarm_set_callback(idx, counter_rpi_pico_irq_handle); \
IRQ_CONNECT((DT_IRQ_BY_IDX(node_id, idx, irq)), \
(DT_IRQ_BY_IDX(node_id, idx, priority)), hardware_alarm_irq_handler, \
(DEVICE_DT_GET(node_id)), 0); \
irq_enable((DT_IRQ_BY_IDX(node_id, idx, irq))); \
} while (false);
#define COUNTER_RPI_PICO_TIMER(inst) \
static void counter_irq_config##inst(void) \
{ \
DT_INST_FOREACH_PROP_ELEM(inst, interrupt_names, RPI_PICO_TIMER_IRQ_ENABLE); \
} \
static struct counter_rpi_pico_timer_ch_data \
ch_data##inst[DT_NUM_IRQS(DT_DRV_INST(inst))]; \
static struct counter_rpi_pico_timer_data counter_##inst##_data = { \
.ch_data = ch_data##inst, \
}; \
static const struct counter_rpi_pico_timer_config counter_##inst##_config = { \
.timer = (timer_hw_t *)DT_INST_REG_ADDR(inst), \
.irq_config = counter_irq_config##inst, \
.info = \
{ \
.max_top_value = UINT32_MAX, \
.freq = 1000000, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = ARRAY_SIZE(ch_data##inst), \
}, \
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
.clk_id = (clock_control_subsys_t)DT_INST_PHA_BY_IDX(inst, clocks, 0, clk_id), \
.reset = RESET_DT_SPEC_INST_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, counter_rpi_pico_timer_init, NULL, &counter_##inst##_data, \
&counter_##inst##_config, PRE_KERNEL_1, \
CONFIG_COUNTER_INIT_PRIORITY, &counter_rpi_pico_driver_api);
DT_INST_FOREACH_STATUS_OKAY(COUNTER_RPI_PICO_TIMER)
``` | /content/code_sandbox/drivers/counter/counter_rpi_pico_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,815 |
```unknown
# MCUXpresso SDK RTC
config COUNTER_MCUX_RTC
bool "MCUX RTC driver"
default y
depends on DT_HAS_NXP_KINETIS_RTC_ENABLED
help
Enable support for mcux rtc driver.
``` | /content/code_sandbox/drivers/counter/Kconfig.mcux_rtc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```c
/*
*
*/
#include <zephyr/drivers/counter.h>
#include <hal/nrf_rtc.h>
#ifdef CONFIG_CLOCK_CONTROL_NRF
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#endif
#include <haly/nrfy_rtc.h>
#include <zephyr/sys/atomic.h>
#ifdef DPPI_PRESENT
#include <nrfx_dppi.h>
#else
#include <nrfx_ppi.h>
#endif
#define LOG_MODULE_NAME counter_rtc
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL);
#define ERR(...) LOG_INST_ERR( \
((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__)
#define WRN(...) LOG_INST_WRN( \
((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__)
#define INF(...) LOG_INST_INF( \
((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__)
#define DBG(...) LOG_INST_DBG( \
((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__)
#define DT_DRV_COMPAT nordic_nrf_rtc
#define COUNTER_GET_TOP_CH(dev) counter_get_num_of_channels(dev)
#define IS_FIXED_TOP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \
(((const struct counter_nrfx_config *)dev->config)->fixed_top), (true))
#define IS_PPI_WRAP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \
(((const struct counter_nrfx_config *)dev->config)->use_ppi), (false))
#define CC_ADJUSTED_OFFSET 16
#define CC_ADJ_MASK(chan) (BIT(chan + CC_ADJUSTED_OFFSET))
#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX)
#define MAYBE_CONST_CONFIG
#else
#define MAYBE_CONST_CONFIG const
#endif
struct counter_nrfx_data {
counter_top_callback_t top_cb;
void *top_user_data;
uint32_t top;
uint32_t guard_period;
/* Store channel interrupt pending and CC adjusted flags. */
atomic_t ipend_adj;
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
uint8_t ppi_ch;
#endif
};
struct counter_nrfx_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_nrfx_config {
struct counter_config_info info;
struct counter_nrfx_ch_data *ch_data;
NRF_RTC_Type *rtc;
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
bool use_ppi;
#endif
#if CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT
bool fixed_top;
#endif
LOG_INSTANCE_PTR_DECLARE(log);
};
static int start(const struct device *dev)
{
const struct counter_nrfx_config *config = dev->config;
nrfy_rtc_task_trigger(config->rtc, NRF_RTC_TASK_START);
return 0;
}
static int stop(const struct device *dev)
{
const struct counter_nrfx_config *config = dev->config;
nrfy_rtc_task_trigger(config->rtc, NRF_RTC_TASK_STOP);
return 0;
}
static uint32_t read(const struct device *dev)
{
const struct counter_nrfx_config *config = dev->config;
return nrfy_rtc_counter_get(config->rtc);
}
static int get_value(const struct device *dev, uint32_t *ticks)
{
*ticks = read(dev);
return 0;
}
/* Function calculates distance between to values assuming that one first
* argument is in front and that values wrap.
*/
static uint32_t ticks_sub(const struct device *dev, uint32_t val,
uint32_t old, uint32_t top)
{
if (IS_FIXED_TOP(dev)) {
return (val - old) & NRF_RTC_COUNTER_MAX;
} else if (likely(IS_BIT_MASK(top))) {
return (val - old) & top;
}
/* if top is not 2^n-1 */
return (val >= old) ? (val - old) : val + top + 1 - old;
}
static uint32_t skip_zero_on_custom_top(uint32_t val, uint32_t top)
{
/* From Product Specification: If a CC register value is 0 when
* a CLEAR task is set, this will not trigger a COMPARE event.
*/
if (unlikely(val == 0) && (top != NRF_RTC_COUNTER_MAX)) {
val++;
}
return val;
}
static uint32_t ticks_add(const struct device *dev, uint32_t val1,
uint32_t val2, uint32_t top)
{
uint32_t sum = val1 + val2;
if (IS_FIXED_TOP(dev)) {
ARG_UNUSED(top);
return sum & NRF_RTC_COUNTER_MAX;
}
if (likely(IS_BIT_MASK(top))) {
sum = sum & top;
} else {
sum = sum > top ? sum - (top + 1) : sum;
}
return skip_zero_on_custom_top(sum, top);
}
static void set_cc_int_pending(const struct device *dev, uint8_t chan)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
atomic_or(&data->ipend_adj, BIT(chan));
NRFY_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(config->rtc));
}
/** @brief Handle case when CC value equals COUNTER+1.
*
* RTC will not generate event if CC value equals COUNTER+1. If such CC is
* about to be set then special algorithm is applied. Since counter must not
* expire before expected value, CC is set to COUNTER+2. If COUNTER progressed
* during that time it means that target value is reached and interrupt is
* manually triggered. If not then interrupt is enabled since it is expected
* that CC value will generate event.
*
* Additionally, an information about CC adjustment is stored. This information
* is used in the callback to return original CC value which was requested by
* the user.
*/
static void handle_next_tick_case(const struct device *dev, uint8_t chan,
uint32_t now, uint32_t val)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
val = ticks_add(dev, val, 1, data->top);
nrfy_rtc_cc_set(config->rtc, chan, val);
atomic_or(&data->ipend_adj, CC_ADJ_MASK(chan));
if (nrfy_rtc_counter_get(config->rtc) != now) {
set_cc_int_pending(dev, chan);
} else {
nrfy_rtc_int_enable(config->rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
}
}
/*
* @brief Set COMPARE value with optional too late setting detection.
*
* Setting CC algorithm takes into account:
* - Current COMPARE value written to the register may be close to the current
* COUNTER value thus COMPARE event may be generated at any moment
* - Next COMPARE value may be soon in the future. Taking into account potential
* preemption COMPARE value may be set too late.
* - RTC registers are clocked with LF clock (32kHz) and sampled between two
* LF ticks.
* - Setting COMPARE register to COUNTER+1 does not generate COMPARE event if
* done half tick before tick boundary.
*
* Algorithm assumes that:
* - COMPARE interrupt is disabled
* - absolute value is taking into account guard period. It means that
* it won't be further in future than <top> - <guard_period> from now.
*
* @param dev Device.
* @param chan COMPARE channel.
* @param val Value (absolute or relative).
* @param flags Alarm flags.
*
* @retval 0 if COMPARE value was set on time and COMPARE interrupt is expected.
* @retval -ETIME if absolute alarm was set too late and error reporting is
* enabled.
*
*/
static int set_cc(const struct device *dev, uint8_t chan, uint32_t val,
uint32_t flags)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
__ASSERT_NO_MSG(data->guard_period < data->top);
NRF_RTC_Type *rtc = config->rtc;
nrf_rtc_event_t evt;
uint32_t prev_val;
uint32_t top;
uint32_t now;
uint32_t diff;
uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan);
int err = 0;
uint32_t max_rel_val;
bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
bool irq_on_late;
__ASSERT(nrf_rtc_int_enable_check(rtc, int_mask) == 0,
"Expected that CC interrupt is disabled.");
evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
top = data->top;
now = nrfy_rtc_counter_get(rtc);
/* First take care of a risk of an event coming from CC being set to
* next tick. Reconfigure CC to future (now tick is the furthest
* future). If CC was set to next tick we need to wait for up to 15us
* (half of 32k tick) and clean potential event. After that time there
* is no risk of unwanted event.
*/
prev_val = nrfy_rtc_cc_get(rtc, chan);
nrfy_rtc_event_clear(rtc, evt);
nrfy_rtc_cc_set(rtc, chan, now);
nrfy_rtc_event_enable(rtc, int_mask);
if (ticks_sub(dev, prev_val, now, top) == 1) {
NRFX_DELAY_US(15);
nrfy_rtc_event_clear(rtc, evt);
}
now = nrfy_rtc_counter_get(rtc);
if (absolute) {
val = skip_zero_on_custom_top(val, top);
irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
max_rel_val = top - data->guard_period;
} else {
/* If relative value is smaller than half of the counter range
* it is assumed that there is a risk of setting value too late
* and late detection algorithm must be applied. When late
* setting is detected, interrupt shall be triggered for
* immediate expiration of the timer. Detection is performed
* by limiting relative distance between CC and counter.
*
* Note that half of counter range is an arbitrary value.
*/
irq_on_late = val < (top / 2);
/* limit max to detect short relative being set too late. */
max_rel_val = irq_on_late ? top / 2 : top;
val = ticks_add(dev, now, val, top);
}
diff = ticks_sub(dev, val, now, top);
if (diff == 1) {
/* CC cannot be set to COUNTER+1 because that will not
* generate an event. In that case, special handling is
* performed (attempt to set CC to COUNTER+2).
*/
handle_next_tick_case(dev, chan, now, val);
} else {
nrfy_rtc_cc_set(rtc, chan, val);
now = nrfy_rtc_counter_get(rtc);
/* decrement value to detect also case when val == read(dev).
* Otherwise, condition would need to include comparing diff
* against 0.
*/
diff = ticks_sub(dev, val - 1, now, top);
if (diff > max_rel_val) {
if (absolute) {
err = -ETIME;
}
/* Interrupt is triggered always for relative alarm and
* for absolute depending on the flag.
*/
if (irq_on_late) {
set_cc_int_pending(dev, chan);
} else {
config->ch_data[chan].callback = NULL;
}
} else if (diff == 0) {
/* It is possible that setting CC was interrupted and
* CC might be set to COUNTER+1 value which will not
* generate an event. In that case, special handling
* is performed (attempt to set CC to COUNTER+2).
*/
handle_next_tick_case(dev, chan, now, val);
} else {
nrfy_rtc_int_enable(rtc, int_mask);
}
}
return err;
}
static int set_channel_alarm(const struct device *dev, uint8_t chan,
const struct counter_alarm_cfg *alarm_cfg)
{
const struct counter_nrfx_config *nrfx_config = dev->config;
struct counter_nrfx_data *data = dev->data;
struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan];
if (alarm_cfg->ticks > data->top) {
return -EINVAL;
}
if (chdata->callback) {
return -EBUSY;
}
chdata->callback = alarm_cfg->callback;
chdata->user_data = alarm_cfg->user_data;
atomic_and(&data->ipend_adj, ~CC_ADJ_MASK(chan));
return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
}
static void disable(const struct device *dev, uint8_t chan)
{
const struct counter_nrfx_config *config = dev->config;
NRF_RTC_Type *rtc = config->rtc;
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
nrfy_rtc_event_int_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
nrfy_rtc_event_clear(rtc, evt);
config->ch_data[chan].callback = NULL;
}
static int cancel_alarm(const struct device *dev, uint8_t chan_id)
{
disable(dev, chan_id);
return 0;
}
static int ppi_setup(const struct device *dev, uint8_t chan)
{
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
const struct counter_nrfx_config *nrfx_config = dev->config;
struct counter_nrfx_data *data = dev->data;
NRF_RTC_Type *rtc = nrfx_config->rtc;
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
nrfx_err_t result;
if (!nrfx_config->use_ppi) {
return 0;
}
nrfy_rtc_event_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
#ifdef DPPI_PRESENT
result = nrfx_dppi_channel_alloc(&data->ppi_ch);
if (result != NRFX_SUCCESS) {
ERR("Failed to allocate PPI channel.");
return -ENODEV;
}
nrfy_rtc_subscribe_set(rtc, NRF_RTC_TASK_CLEAR, data->ppi_ch);
nrfy_rtc_publish_set(rtc, evt, data->ppi_ch);
(void)nrfx_dppi_channel_enable(data->ppi_ch);
#else /* DPPI_PRESENT */
uint32_t evt_addr;
uint32_t task_addr;
evt_addr = nrfy_rtc_event_address_get(rtc, evt);
task_addr = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
result = nrfx_ppi_channel_alloc(&data->ppi_ch);
if (result != NRFX_SUCCESS) {
ERR("Failed to allocate PPI channel.");
return -ENODEV;
}
(void)nrfx_ppi_channel_assign(data->ppi_ch, evt_addr, task_addr);
(void)nrfx_ppi_channel_enable(data->ppi_ch);
#endif
#endif /* CONFIG_COUNTER_RTC_WITH_PPI_WRAP */
return 0;
}
static void ppi_free(const struct device *dev, uint8_t chan)
{
#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
const struct counter_nrfx_config *nrfx_config = dev->config;
struct counter_nrfx_data *data = dev->data;
uint8_t ppi_ch = data->ppi_ch;
NRF_RTC_Type *rtc = nrfx_config->rtc;
if (!nrfx_config->use_ppi) {
return;
}
nrfy_rtc_event_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
#ifdef DPPI_PRESENT
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
(void)nrfx_dppi_channel_disable(ppi_ch);
nrfy_rtc_subscribe_clear(rtc, NRF_RTC_TASK_CLEAR);
nrfy_rtc_publish_clear(rtc, evt);
(void)nrfx_dppi_channel_free(ppi_ch);
#else /* DPPI_PRESENT */
(void)nrfx_ppi_channel_disable(ppi_ch);
(void)nrfx_ppi_channel_free(ppi_ch);
#endif
#endif
}
/* Return true if counter must be cleared by the CPU. It is cleared
* automatically in case of max top value or PPI usage.
*/
static bool sw_wrap_required(const struct device *dev)
{
struct counter_nrfx_data *data = dev->data;
return (data->top != NRF_RTC_COUNTER_MAX) && !IS_PPI_WRAP(dev);
}
static int set_fixed_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
NRF_RTC_Type *rtc = config->rtc;
if (cfg->ticks != NRF_RTC_COUNTER_MAX) {
return -EINVAL;
}
nrfy_rtc_int_disable(rtc, NRF_RTC_INT_OVERFLOW_MASK);
data->top_cb = cfg->callback;
data->top_user_data = cfg->user_data;
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
}
if (cfg->callback) {
nrfy_rtc_int_enable(rtc, NRF_RTC_INT_OVERFLOW_MASK);
}
return 0;
}
static int set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
const struct counter_nrfx_config *nrfx_config = dev->config;
NRF_RTC_Type *rtc = nrfx_config->rtc;
struct counter_nrfx_data *dev_data = dev->data;
uint32_t top_ch = COUNTER_GET_TOP_CH(dev);
int err = 0;
if (IS_FIXED_TOP(dev)) {
return set_fixed_top_value(dev, cfg);
}
for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
/* Overflow can be changed only when all alarms are
* disables.
*/
if (nrfx_config->ch_data[i].callback) {
return -EBUSY;
}
}
nrfy_rtc_int_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(top_ch));
if (IS_PPI_WRAP(dev)) {
if ((dev_data->top == NRF_RTC_COUNTER_MAX) &&
cfg->ticks != NRF_RTC_COUNTER_MAX) {
err = ppi_setup(dev, top_ch);
} else if (((dev_data->top != NRF_RTC_COUNTER_MAX) &&
cfg->ticks == NRF_RTC_COUNTER_MAX)) {
ppi_free(dev, top_ch);
}
}
dev_data->top_cb = cfg->callback;
dev_data->top_user_data = cfg->user_data;
dev_data->top = cfg->ticks;
nrfy_rtc_cc_set(rtc, top_ch, cfg->ticks);
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
} else if (read(dev) >= cfg->ticks) {
err = -ETIME;
if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
}
}
if (cfg->callback || sw_wrap_required(dev)) {
nrfy_rtc_int_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(top_ch));
}
return err;
}
static uint32_t get_pending_int(const struct device *dev)
{
return 0;
}
static int init_rtc(const struct device *dev, uint32_t prescaler)
{
MAYBE_CONST_CONFIG struct counter_nrfx_config *nrfx_config =
(MAYBE_CONST_CONFIG struct counter_nrfx_config *) dev->config;
struct counter_nrfx_data *data = dev->data;
struct counter_top_cfg top_cfg = {
.ticks = NRF_RTC_COUNTER_MAX
};
#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX)
/* For simulated devices we need to convert the hardcoded DT address from the real
* peripheral into the correct one for simulation
*/
nrfx_config->rtc = nhw_convert_periph_base_addr(nrfx_config->rtc);
#endif
NRF_RTC_Type *rtc = nrfx_config->rtc;
int err;
#ifdef CONFIG_CLOCK_CONTROL_NRF
z_nrf_clock_control_lf_on(CLOCK_CONTROL_NRF_LF_START_NOWAIT);
#endif
nrfy_rtc_prescaler_set(rtc, prescaler);
NRFY_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(rtc));
data->top = NRF_RTC_COUNTER_MAX;
err = set_top_value(dev, &top_cfg);
DBG("Initialized");
return err;
}
static uint32_t get_top_value(const struct device *dev)
{
struct counter_nrfx_data *data = dev->data;
return data->top;
}
static uint32_t get_guard_period(const struct device *dev, uint32_t flags)
{
struct counter_nrfx_data *data = dev->data;
return data->guard_period;
}
static int set_guard_period(const struct device *dev, uint32_t guard,
uint32_t flags)
{
struct counter_nrfx_data *data = dev->data;
data->guard_period = guard;
return 0;
}
static void top_irq_handle(const struct device *dev)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
NRF_RTC_Type *rtc = config->rtc;
counter_top_callback_t cb = data->top_cb;
nrf_rtc_event_t top_evt;
top_evt = IS_FIXED_TOP(dev) ?
NRF_RTC_EVENT_OVERFLOW :
NRF_RTC_CHANNEL_EVENT_ADDR(counter_get_num_of_channels(dev));
uint32_t event_mask = nrfy_rtc_events_process(rtc, NRFY_EVENT_TO_INT_BITMASK(top_evt));
if (event_mask & NRFY_EVENT_TO_INT_BITMASK(top_evt)) {
/* Perform manual clear if custom top value is used and PPI
* clearing is not used.
*/
if (!IS_FIXED_TOP(dev) && !IS_PPI_WRAP(dev)) {
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR);
}
if (cb) {
cb(dev, data->top_user_data);
}
}
}
static void alarm_irq_handle(const struct device *dev, uint32_t chan)
{
const struct counter_nrfx_config *config = dev->config;
struct counter_nrfx_data *data = dev->data;
NRF_RTC_Type *rtc = config->rtc;
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan);
bool hw_irq_pending = nrfy_rtc_events_process(rtc, NRFY_EVENT_TO_INT_BITMASK(evt)) &
nrfy_rtc_int_enable_check(rtc, NRFY_EVENT_TO_INT_BITMASK(evt));
bool sw_irq_pending = data->ipend_adj & BIT(chan);
if (hw_irq_pending || sw_irq_pending) {
struct counter_nrfx_ch_data *chdata;
counter_alarm_callback_t cb;
atomic_and(&data->ipend_adj, ~BIT(chan));
nrfy_rtc_int_disable(rtc, int_mask);
chdata = &config->ch_data[chan];
cb = chdata->callback;
chdata->callback = NULL;
if (cb) {
uint32_t cc = nrfy_rtc_cc_get(rtc, chan);
if (data->ipend_adj & CC_ADJ_MASK(chan)) {
cc = ticks_sub(dev, cc, 1, data->top);
}
cb(dev, chan, cc, chdata->user_data);
}
}
}
static void irq_handler(const void *arg)
{
const struct device *dev = arg;
top_irq_handle(dev);
for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) {
alarm_irq_handle(dev, i);
}
}
static const struct counter_driver_api counter_nrfx_driver_api = {
.start = start,
.stop = stop,
.get_value = get_value,
.set_alarm = set_channel_alarm,
.cancel_alarm = cancel_alarm,
.set_top_value = set_top_value,
.get_pending_int = get_pending_int,
.get_top_value = get_top_value,
.get_guard_period = get_guard_period,
.set_guard_period = set_guard_period,
};
/*
* Devicetree access is done with node labels due to HAL API
* requirements. In particular, RTCx_CC_NUM values from HALs
* are indexed by peripheral number, so DT_INST APIs won't work.
*/
#define RTC_IRQ_CONNECT(idx) \
COND_CODE_1(DT_INST_PROP(idx, zli), \
(IRQ_DIRECT_CONNECT(DT_INST_IRQN(idx), \
DT_INST_IRQ(idx, priority), \
counter_rtc##idx##_isr_wrapper, \
IRQ_ZERO_LATENCY)), \
(IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), \
irq_handler, DEVICE_DT_INST_GET(idx), 0)) \
)
#define COUNTER_NRF_RTC_DEVICE(idx) \
BUILD_ASSERT((DT_INST_PROP(idx, prescaler) - 1) <= \
RTC_PRESCALER_PRESCALER_Msk, \
"RTC prescaler out of range"); \
COND_CODE_1(DT_INST_PROP(idx, zli), ( \
ISR_DIRECT_DECLARE(counter_rtc##idx##_isr_wrapper) \
{ \
irq_handler(DEVICE_DT_INST_GET(idx)); \
/* No rescheduling, it shall not access zephyr primitives. */ \
return 0; \
}), ()) \
static int counter_##idx##_init(const struct device *dev) \
{ \
RTC_IRQ_CONNECT(idx); \
return init_rtc(dev, DT_INST_PROP(idx, prescaler) - 1); \
} \
static struct counter_nrfx_data counter_##idx##_data; \
static struct counter_nrfx_ch_data \
counter##idx##_ch_data[DT_INST_PROP(idx, cc_num)]; \
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
static MAYBE_CONST_CONFIG \
struct counter_nrfx_config nrfx_counter_##idx##_config = { \
.info = { \
.max_top_value = NRF_RTC_COUNTER_MAX, \
.freq = DT_INST_PROP(idx, clock_frequency) / \
DT_INST_PROP(idx, prescaler), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = DT_INST_PROP(idx, fixed_top) \
? DT_INST_PROP(idx, cc_num) \
: DT_INST_PROP(idx, cc_num) - 1 \
}, \
.ch_data = counter##idx##_ch_data, \
.rtc = (NRF_RTC_Type *)DT_INST_REG_ADDR(idx), \
IF_ENABLED(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \
(.use_ppi = DT_INST_PROP(idx, ppi_wrap),)) \
IF_ENABLED(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \
(.fixed_top = DT_INST_PROP(idx, fixed_top),)) \
LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \
}; \
DEVICE_DT_INST_DEFINE(idx, \
counter_##idx##_init, \
NULL, \
&counter_##idx##_data, \
&nrfx_counter_##idx##_config.info, \
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
&counter_nrfx_driver_api);
DT_INST_FOREACH_STATUS_OKAY(COUNTER_NRF_RTC_DEVICE)
``` | /content/code_sandbox/drivers/counter/counter_nrfx_rtc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,111 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Counter driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_cat1_counter
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/pinctrl.h>
#include <cyhal_timer.h>
#include <cyhal_gpio.h>
#include <cyhal_tcpwm_common.h>
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ifx_cat1_counter, CONFIG_COUNTER_LOG_LEVEL);
struct ifx_cat1_counter_config {
struct counter_config_info counter_info;
TCPWM_CNT_Type *reg_addr;
cyhal_gpio_t external_pin;
IRQn_Type irqn;
uint8_t irq_priority;
};
struct ifx_cat1_counter_data {
cyhal_timer_t counter_obj;
cyhal_timer_cfg_t counter_cfg;
struct counter_alarm_cfg alarm_cfg_counter;
struct counter_top_cfg top_value_cfg_counter;
uint32_t guard_period;
cyhal_resource_inst_t hw_resource;
cyhal_source_t signal_source;
bool alarm_irq_flag;
};
static const cy_stc_tcpwm_counter_config_t cyhal_timer_default_config = {
.period = 32768,
.clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1,
.runMode = CY_TCPWM_COUNTER_CONTINUOUS,
.countDirection = CY_TCPWM_COUNTER_COUNT_UP,
.compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE,
.compare0 = 16384,
.compare1 = 16384,
.enableCompareSwap = false,
.interruptSources = CY_TCPWM_INT_NONE,
.captureInputMode = 0x3U,
.captureInput = CY_TCPWM_INPUT_0,
.reloadInputMode = 0x3U,
.reloadInput = CY_TCPWM_INPUT_0,
.startInputMode = 0x3U,
.startInput = CY_TCPWM_INPUT_0,
.stopInputMode = 0x3U,
.stopInput = CY_TCPWM_INPUT_0,
.countInputMode = 0x3U,
.countInput = CY_TCPWM_INPUT_1,
};
static int get_hw_block_info(TCPWM_CNT_Type *reg_addr, cyhal_resource_inst_t *hw_resource)
{
uint32_t i;
for (i = 0u; i < _CYHAL_TCPWM_INSTANCES; i++) {
uintptr_t base = POINTER_TO_UINT(_CYHAL_TCPWM_DATA[i].base);
uintptr_t cnt = POINTER_TO_UINT(_CYHAL_TCPWM_DATA[i].base->CNT);
uintptr_t reg_addr_ptr = POINTER_TO_UINT(reg_addr);
uintptr_t end_addr = base + sizeof(TCPWM_Type);
if ((reg_addr_ptr > base) && (reg_addr_ptr < end_addr)) {
hw_resource->type = CYHAL_RSC_TCPWM;
hw_resource->block_num = i;
hw_resource->channel_num = ((reg_addr_ptr - cnt) / sizeof(TCPWM_CNT_Type));
if (hw_resource->channel_num >= _CYHAL_TCPWM_DATA[i].num_channels) {
return -EINVAL;
}
return 0;
}
}
return -EINVAL;
}
static void ifx_cat1_counter_event_callback(void *callback_arg, cyhal_timer_event_t event)
{
const struct device *dev = (const struct device *)callback_arg;
struct ifx_cat1_counter_data *const data = dev->data;
const struct ifx_cat1_counter_config *const config = dev->config;
/* Alarm compare/capture event */
if ((data->alarm_cfg_counter.callback != NULL) &&
(((CYHAL_TIMER_IRQ_CAPTURE_COMPARE & event) == CYHAL_TIMER_IRQ_CAPTURE_COMPARE) ||
data->alarm_irq_flag)) {
/* Alarm works as one-shot, so disable event */
cyhal_timer_enable_event(&data->counter_obj, CYHAL_TIMER_IRQ_CAPTURE_COMPARE,
config->irq_priority, false);
/* Call User callback for Alarm */
data->alarm_cfg_counter.callback(dev, 1, cyhal_timer_read(&data->counter_obj),
data->alarm_cfg_counter.user_data);
data->alarm_irq_flag = false;
}
/* Top_value terminal count event */
if ((data->top_value_cfg_counter.callback != NULL) &&
((CYHAL_TIMER_IRQ_TERMINAL_COUNT & event) == CYHAL_TIMER_IRQ_TERMINAL_COUNT)) {
/* Call User callback for top value */
data->top_value_cfg_counter.callback(dev, data->top_value_cfg_counter.user_data);
}
/* NOTE: cyhal handles cleaning of interrupts */
}
static void ifx_cat1_counter_set_int_pending(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
const struct ifx_cat1_counter_config *const config = dev->config;
cyhal_timer_enable_event(&data->counter_obj, CYHAL_TIMER_IRQ_CAPTURE_COMPARE,
config->irq_priority, true);
Cy_TCPWM_SetInterrupt(data->counter_obj.tcpwm.base,
_CYHAL_TCPWM_CNT_NUMBER(data->counter_obj.tcpwm.resource),
CY_TCPWM_INT_ON_CC0);
}
static int ifx_cat1_counter_init(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
cy_rslt_t rslt;
struct ifx_cat1_counter_data *data = dev->data;
const struct ifx_cat1_counter_config *config = dev->config;
/* Dedicate Counter HW resource */
if (get_hw_block_info(config->reg_addr, &data->hw_resource) != 0) {
return -EIO;
}
cyhal_timer_configurator_t timer_configurator = {
.resource = &data->hw_resource,
.config = &cyhal_timer_default_config,
};
/* Initialize timer */
rslt = cyhal_timer_init_cfg(&data->counter_obj, &timer_configurator);
if (rslt != CY_RSLT_SUCCESS) {
return -EIO;
}
/* Initialize counter structure */
data->alarm_irq_flag = false;
data->counter_cfg.compare_value = 0;
data->counter_cfg.period = config->counter_info.max_top_value;
data->counter_cfg.direction = CYHAL_TIMER_DIR_UP;
data->counter_cfg.is_compare = true;
data->counter_cfg.is_continuous = true;
data->counter_cfg.value = 0;
/* Configure timer */
rslt = cyhal_timer_configure(&data->counter_obj, &data->counter_cfg);
if (rslt != CY_RSLT_SUCCESS) {
return -EIO;
}
if (config->external_pin == NC) {
/* Configure frequency */
rslt = cyhal_timer_set_frequency(&data->counter_obj, config->counter_info.freq);
if (rslt != CY_RSLT_SUCCESS) {
return -EIO;
}
} else {
rslt = cyhal_gpio_init(config->external_pin, CYHAL_GPIO_DIR_INPUT,
CYHAL_GPIO_DRIVE_NONE, 0);
if (rslt != CY_RSLT_SUCCESS) {
LOG_ERR("External pin configuration error");
return -EIO;
}
rslt = cyhal_gpio_enable_output(config->external_pin, CYHAL_SIGNAL_TYPE_EDGE,
(cyhal_source_t *)&data->signal_source);
if (rslt != CY_RSLT_SUCCESS) {
if (rslt != CY_RSLT_SUCCESS) {
LOG_ERR("error in the enabling of Counter input pin output");
return -EIO;
}
}
rslt = cyhal_timer_connect_digital(&data->counter_obj, data->signal_source,
CYHAL_TIMER_INPUT_COUNT);
if (rslt != CY_RSLT_SUCCESS) {
LOG_ERR("Error connecting signal source");
return -EIO;
}
}
/* Register timer event callback */
cyhal_timer_register_callback(&data->counter_obj, ifx_cat1_counter_event_callback,
(void *)dev);
return 0;
}
static int ifx_cat1_counter_start(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
if (cyhal_timer_start(&data->counter_obj) != CY_RSLT_SUCCESS) {
return -EIO;
}
return 0;
}
static int ifx_cat1_counter_stop(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
if (cyhal_timer_stop(&data->counter_obj) != CY_RSLT_SUCCESS) {
return -EIO;
}
return 0;
}
static int ifx_cat1_counter_get_value(const struct device *dev, uint32_t *ticks)
{
__ASSERT_NO_MSG(dev != NULL);
__ASSERT_NO_MSG(ticks != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
*ticks = cyhal_timer_read(&data->counter_obj);
return 0;
}
static int ifx_cat1_counter_set_top_value(const struct device *dev,
const struct counter_top_cfg *cfg)
{
__ASSERT_NO_MSG(dev != NULL);
__ASSERT_NO_MSG(cfg != NULL);
cy_rslt_t rslt;
struct ifx_cat1_counter_data *const data = dev->data;
const struct ifx_cat1_counter_config *const config = dev->config;
bool ticks_gt_period;
data->top_value_cfg_counter = *cfg;
data->counter_cfg.period = cfg->ticks;
/* Check new top value limit */
if (cfg->ticks > config->counter_info.max_top_value) {
return -ENOTSUP;
}
ticks_gt_period = cfg->ticks > data->counter_cfg.period;
/* Checks if new period value is not less then old period value */
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
data->counter_cfg.value = 0u;
} else if (ticks_gt_period && (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE)) {
data->counter_cfg.value = 0u;
} else {
/* cyhal_timer_configure resets timer counter register to value
* defined in config structure 'counter_cfg.value', so update
* counter value with current value of counter (read by
* cyhal_timer_read function).
*/
data->counter_cfg.value = cyhal_timer_read(&data->counter_obj);
}
if ((ticks_gt_period == false) ||
((ticks_gt_period == true) && (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE))) {
/* Reconfigure timer */
if (config->external_pin == NC) {
rslt = cyhal_timer_configure(&data->counter_obj, &data->counter_cfg);
if (rslt != CY_RSLT_SUCCESS) {
return -EIO;
}
} else {
TCPWM_CNT_PERIOD(data->counter_obj.tcpwm.base,
_CYHAL_TCPWM_CNT_NUMBER(
data->counter_obj.tcpwm.resource)) = cfg->ticks;
}
/* Register an top_value terminal count event callback handler if
* callback is not NULL.
*/
if (cfg->callback != NULL) {
cyhal_timer_enable_event(&data->counter_obj, CYHAL_TIMER_IRQ_TERMINAL_COUNT,
config->irq_priority, true);
}
}
return 0;
}
static uint32_t ifx_cat1_counter_get_top_value(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
return data->counter_cfg.period;
}
static inline bool counter_is_bit_mask(uint32_t val)
{
/* Return true if value equals 2^n - 1 */
return !(val & (val + 1U));
}
static uint32_t ifx_cat1_counter_ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
{
uint32_t to_top;
/* refer to path_to_url for 'likely' usage */
if (likely(counter_is_bit_mask(top))) {
return (val1 + val2) & top;
}
to_top = top - val1;
return (val2 <= to_top) ? (val1 + val2) : (val2 - to_top - 1U);
}
static uint32_t ifx_cat1_counter_ticks_sub(uint32_t val, uint32_t old, uint32_t top)
{
/* refer to path_to_url for 'likely' usage */
if (likely(counter_is_bit_mask(top))) {
return (val - old) & top;
}
/* if top is not 2^n-1 */
return (val >= old) ? (val - old) : (val + top + 1U - old);
}
static int ifx_cat1_counter_set_alarm(const struct device *dev, uint8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
ARG_UNUSED(chan_id);
__ASSERT_NO_MSG(dev != NULL);
__ASSERT_NO_MSG(alarm_cfg != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
const struct ifx_cat1_counter_config *const config = dev->config;
uint32_t val = alarm_cfg->ticks;
uint32_t top_val = ifx_cat1_counter_get_top_value(dev);
uint32_t flags = alarm_cfg->flags;
uint32_t max_rel_val;
bool absolute = ((flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) ? false : true;
bool irq_on_late;
/* Checks if compare value is not less then period value */
if (alarm_cfg->ticks > top_val) {
return -EINVAL;
}
if (absolute) {
max_rel_val = top_val - data->guard_period;
irq_on_late = ((flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE) == 0) ? false : true;
} else {
/* If relative value is smaller than half of the counter range it is assumed
* that there is a risk of setting value too late and late detection algorithm
* must be applied. When late setting is detected, interrupt shall be
* triggered for immediate expiration of the timer. Detection is performed
* by limiting relative distance between CC and counter.
*
* Note that half of counter range is an arbitrary value.
*/
irq_on_late = val < (top_val / 2U);
/* limit max to detect short relative being set too late. */
max_rel_val = irq_on_late ? (top_val / 2U) : top_val;
val = ifx_cat1_counter_ticks_add(cyhal_timer_read(&data->counter_obj), val,
top_val);
}
/* Decrement value to detect also case when val == counter_read(dev). Otherwise,
* condition would need to include comparing diff against 0.
*/
uint32_t curr = cyhal_timer_read(&data->counter_obj);
uint32_t diff = ifx_cat1_counter_ticks_sub((val - 1), curr, top_val);
if ((absolute && (val < curr)) || (diff > max_rel_val)) {
/* Interrupt is triggered always for relative alarm and for absolute depending
* on the flag.
*/
if (irq_on_late) {
data->alarm_irq_flag = true;
ifx_cat1_counter_set_int_pending(dev);
}
if (absolute) {
return -ETIME;
}
} else {
/* Setting new compare value */
cy_rslt_t rslt;
data->alarm_cfg_counter = *alarm_cfg;
data->counter_cfg.compare_value = val;
/* cyhal_timer_configure resets timer counter register to value
* defined in config structure 'counter_cfg.value', so update
* counter value with current value of counter (read by
* cyhal_timer_read function).
*/
data->counter_cfg.value = cyhal_timer_read(&data->counter_obj);
/* Reconfigure timer */
if (config->external_pin == NC) {
rslt = cyhal_timer_configure(&data->counter_obj, &data->counter_cfg);
if (rslt != CY_RSLT_SUCCESS) {
return -EINVAL;
}
} else {
TCPWM_CNT_CC(data->counter_obj.tcpwm.base,
_CYHAL_TCPWM_CNT_NUMBER(data->counter_obj.tcpwm.resource)) =
data->counter_cfg.compare_value;
}
cyhal_timer_enable_event(&data->counter_obj, CYHAL_TIMER_IRQ_CAPTURE_COMPARE,
config->irq_priority, true);
}
return 0;
}
static int ifx_cat1_counter_cancel_alarm(const struct device *dev, uint8_t chan_id)
{
ARG_UNUSED(chan_id);
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
const struct ifx_cat1_counter_config *const config = dev->config;
cyhal_timer_enable_event(&data->counter_obj, CYHAL_TIMER_IRQ_CAPTURE_COMPARE,
config->irq_priority, false);
return 0;
}
static uint32_t ifx_cat1_counter_get_pending_int(const struct device *dev)
{
__ASSERT_NO_MSG(dev != NULL);
const struct ifx_cat1_counter_config *const config = dev->config;
return NVIC_GetPendingIRQ(config->irqn);
}
static uint32_t ifx_cat1_counter_get_guard_period(const struct device *dev, uint32_t flags)
{
ARG_UNUSED(flags);
__ASSERT_NO_MSG(dev != NULL);
struct ifx_cat1_counter_data *const data = dev->data;
return data->guard_period;
}
static int ifx_cat1_counter_set_guard_period(const struct device *dev, uint32_t guard,
uint32_t flags)
{
ARG_UNUSED(flags);
__ASSERT_NO_MSG(dev != NULL);
__ASSERT_NO_MSG(guard < ifx_cat1_counter_get_top_value(dev));
struct ifx_cat1_counter_data *const data = dev->data;
data->guard_period = guard;
return 0;
}
static const struct counter_driver_api counter_api = {
.start = ifx_cat1_counter_start,
.stop = ifx_cat1_counter_stop,
.get_value = ifx_cat1_counter_get_value,
.set_alarm = ifx_cat1_counter_set_alarm,
.cancel_alarm = ifx_cat1_counter_cancel_alarm,
.set_top_value = ifx_cat1_counter_set_top_value,
.get_pending_int = ifx_cat1_counter_get_pending_int,
.get_top_value = ifx_cat1_counter_get_top_value,
.get_guard_period = ifx_cat1_counter_get_guard_period,
.set_guard_period = ifx_cat1_counter_set_guard_period,
};
#define DT_INST_GET_CYHAL_GPIO_OR(inst, gpios_prop, default) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, gpios_prop), \
(DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(DT_INST(inst, DT_DRV_COMPAT), gpios_prop)), \
(default))
/* Counter driver init macros */
#define INFINEON_CAT1_COUNTER_INIT(n) \
\
static struct ifx_cat1_counter_data ifx_cat1_counter##n##_data; \
\
static const struct ifx_cat1_counter_config ifx_cat1_counter##n##_config = { \
.counter_info = {.max_top_value = (DT_INST_PROP(n, resolution) == 32) \
? UINT32_MAX \
: UINT16_MAX, \
.freq = DT_INST_PROP_OR(n, clock_frequency, 10000), \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1}, \
.reg_addr = (TCPWM_CNT_Type *)DT_INST_REG_ADDR(n), \
.irq_priority = DT_INST_IRQ(n, priority), \
.irqn = DT_INST_IRQN(n), \
.external_pin = \
(cyhal_gpio_t)DT_INST_GET_CYHAL_GPIO_OR(n, external_trigger_gpios, NC)}; \
DEVICE_DT_INST_DEFINE(n, ifx_cat1_counter_init, NULL, &ifx_cat1_counter##n##_data, \
&ifx_cat1_counter##n##_config, PRE_KERNEL_1, \
CONFIG_COUNTER_INIT_PRIORITY, &counter_api);
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_COUNTER_INIT);
``` | /content/code_sandbox/drivers/counter/counter_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,387 |
```unknown
# MCUXpresso SDK TPM
config COUNTER_MCUX_TPM
bool "MCUX TPM counter driver"
default y
depends on DT_HAS_NXP_TPM_TIMER_ENABLED
help
Enable support for mcux Timer PWM Module (TPM) counter driver.
``` | /content/code_sandbox/drivers/counter/Kconfig.mcux_tpm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
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