text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef __DAI_PARAMS_INTEL_IPC3_H__
#define __DAI_PARAMS_INTEL_IPC3_H__
#include <stdint.h>
#define DAI_INTEL_IPC3_SSP_FMT_I2S 1 /**< I2S mode */
#define DAI_INTEL_IPC3_SSP_FMT_RIGHT_J 2 /**< Right Justified mode */
#define DAI_INTEL_IPC3_SSP_FMT_LEFT_J 3 /**< Left Justified mode */
#define DAI_INTEL_IPC3_SSP_FMT_DSP_A 4 /**< L data MSB after FRM LRC */
#define DAI_INTEL_IPC3_SSP_FMT_DSP_B 5 /**< L data MSB during FRM LRC */
#define DAI_INTEL_IPC3_SSP_FMT_PDM 6 /**< Pulse density modulation */
#define DAI_INTEL_IPC3_SSP_FMT_CONT (1 << 4) /**< continuous clock */
#define DAI_INTEL_IPC3_SSP_FMT_GATED (0 << 4) /**< clock is gated */
#define DAI_INTEL_IPC3_SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
#define DAI_INTEL_IPC3_SSP_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
#define DAI_INTEL_IPC3_SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
#define DAI_INTEL_IPC3_SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
#define DAI_INTEL_IPC3_SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
#define DAI_INTEL_IPC3_SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
#define DAI_INTEL_IPC3_SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
#define DAI_INTEL_IPC3_SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
#define DAI_INTEL_IPC3_SSP_FMT_FORMAT_MASK 0x000f
#define DAI_INTEL_IPC3_SSP_FMT_CLOCK_MASK 0x00f0
#define DAI_INTEL_IPC3_SSP_FMT_INV_MASK 0x0f00
#define DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK 0xf000
/*
* DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
* representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
* commands.
*/
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_CMD_MASK 0xF
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_NONE 0 /**< config without stage information */
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< config during hw_params stage */
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_FREE BIT(1) /**< config during hw_free stage */
/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_PAUSE BIT(2)
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_SHIFT 4
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
/*
* This should be used along with the DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS to indicate that
* pipeline stop/pause and DAI DMA stop/pause should happen in two steps. This change is only
* available ABI 3.20 onwards.
*/
#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_2_STEP_STOP BIT(0)
/* ssc1: TINTE */
#define DAI_INTEL_IPC3_SSP_QUIRK_TINTE (1 << 0)
/* ssc1: PINTE */
#define DAI_INTEL_IPC3_SSP_QUIRK_PINTE (1 << 1)
/* ssc2: SMTATF */
#define DAI_INTEL_IPC3_SSP_QUIRK_SMTATF (1 << 2)
/* ssc2: MMRATF */
#define DAI_INTEL_IPC3_SSP_QUIRK_MMRATF (1 << 3)
/* ssc2: PSPSTWFDFD */
#define DAI_INTEL_IPC3_SSP_QUIRK_PSPSTWFDFD (1 << 4)
/* ssc2: PSPSRWFDFD */
#define DAI_INTEL_IPC3_SSP_QUIRK_PSPSRWFDFD (1 << 5)
/* ssc1: LBM */
#define DAI_INTEL_IPC3_SSP_QUIRK_LBM (1 << 6)
/* here is the possibility to define others aux macros */
#define DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX 38
#define DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX 31
/* SSP clocks control settings
*
* Macros for clks_control field in sof_dai_ssp_params struct.
*/
/* mclk 0 disable */
#define DAI_INTEL_IPC3_SSP_MCLK_0_DISABLE BIT(0)
/* mclk 1 disable */
#define DAI_INTEL_IPC3_SSP_MCLK_1_DISABLE BIT(1)
/* mclk keep active */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_KA BIT(2)
/* bclk keep active */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_KA BIT(3)
/* fs keep active */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_FS_KA BIT(4)
/* bclk idle */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
/* mclk early start */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_ES BIT(6)
/* bclk early start */
#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_ES BIT(7)
/* SSP Configuration Request - SOF_DAI_SSP_CONFIG */
struct dai_intel_ipc3_ssp_params {
uint32_t reserved0;
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_rate; /* mclk frequency in Hz */
uint32_t fsync_rate; /* fsync frequency in Hz */
uint32_t bclk_rate; /* bclk frequency in Hz */
/* TDM */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
/* data */
uint32_t sample_valid_bits;
uint16_t tdm_slot_width;
uint16_t reserved2; /* alignment */
/* MCLK */
uint32_t mclk_direction;
uint16_t frame_pulse_width;
uint16_t tdm_per_slot_padding_flag;
uint32_t clks_control;
uint32_t quirks;
uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
* will be driven, before sending data
*/
} __packed;
#endif /* __DAI_PARAMS_INTEL_IPC3_H__ */
``` | /content/code_sandbox/drivers/dai/intel/ssp/dai-params-intel-ipc3.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,597 |
```objective-c
/*
*
*/
#ifndef __DAI_PARAMS_INTEL_IPC4_H__
#define __DAI_PARAMS_INTEL_IPC4_H__
#include <stdint.h>
#define DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT 8
#define I2SIPCMC 8
#define I2SOPCMC 8
/**< Type of the gateway. */
enum dai_intel_ipc4_connector_node_id_type {
/**< HD/A host output (-> DSP). */
dai_intel_ipc4_hda_host_output_class = 0,
/**< HD/A host input (<- DSP). */
dai_intel_ipc4_hda_host_input_class = 1,
/**< HD/A host input/output (rsvd for future use). */
dai_intel_ipc4_hda_host_inout_class = 2,
/**< HD/A link output (DSP ->). */
dai_intel_ipc4_hda_link_output_class = 8,
/**< HD/A link input (DSP <-). */
dai_intel_ipc4_hda_link_input_class = 9,
/**< HD/A link input/output (rsvd for future use). */
dai_intel_ipc4_hda_link_inout_class = 10,
/**< DMIC link input (DSP <-). */
dai_intel_ipc4_dmic_link_input_class = 11,
/**< I2S link output (DSP ->). */
dai_intel_ipc4_i2s_link_output_class = 12,
/**< I2S link input (DSP <-). */
dai_intel_ipc4_i2s_link_input_class = 13,
/**< ALH link output, legacy for SNDW (DSP ->). */
dai_intel_ipc4_alh_link_output_class = 16,
/**< ALH link input, legacy for SNDW (DSP <-). */
dai_intel_ipc4_alh_link_input_class = 17,
/**< SNDW link output (DSP ->). */
dai_intel_ipc4_alh_snd_wire_stream_link_output_class = 16,
/**< SNDW link input (DSP <-). */
dai_intel_ipc4_alh_snd_wire_stream_link_input_class = 17,
/**< UAOL link output (DSP ->). */
dai_intel_ipc4_alh_uaol_stream_link_output_class = 18,
/**< UAOL link input (DSP <-). */
dai_intel_ipc4_alh_uaol_stream_link_input_class = 19,
/**< IPC output (DSP ->). */
dai_intel_ipc4_ipc_output_class = 20,
/**< IPC input (DSP <-). */
dai_intel_ipc4_ipc_input_class = 21,
/**< I2S Multi gtw output (DSP ->). */
dai_intel_ipc4_i2s_multi_link_output_class = 22,
/**< I2S Multi gtw input (DSP <-). */
dai_intel_ipc4_i2s_multi_link_input_class = 23,
/**< GPIO */
dai_intel_ipc4_gpio_class = 24,
/**< SPI */
dai_intel_ipc4_spi_output_class = 25,
dai_intel_ipc4_spi_input_class = 26,
dai_intel_ipc4_max_connector_node_id_type
};
struct ssp_intel_aux_tlv {
uint32_t type;
uint32_t size;
uint32_t val[];
} __packed;
struct ssp_intel_mn_ctl {
uint32_t div_m;
uint32_t div_n;
} __packed;
struct ssp_intel_clk_ctl {
uint32_t start;
uint32_t stop;
} __packed;
struct ssp_intel_tr_ctl {
uint32_t sampling_frequency;
uint32_t bit_depth;
uint32_t channel_map;
uint32_t channel_config;
uint32_t interleaving_style;
uint32_t format;
} __packed;
struct ssp_intel_run_ctl {
uint32_t enabled;
} __packed;
struct ssp_intel_node_ctl {
uint32_t node_id;
uint32_t sampling_rate;
} __packed;
struct ssp_intel_sync_ctl {
uint32_t sync_denominator;
uint32_t count;
} __packed;
struct ssp_intel_ext_ctl {
uint32_t ext_data;
} __packed;
struct ssp_intel_link_ctl {
uint32_t clock_source;
} __packed;
#define SSP_MN_DIVIDER_CONTROLS 0
#define SSP_DMA_CLK_CONTROLS 1
#define SSP_DMA_TRANSMISSION_START 2
#define SSP_DMA_TRANSMISSION_STOP 3
#define SSP_DMA_ALWAYS_RUNNING_MODE 4
#define SSP_DMA_SYNC_DATA 5
#define SSP_DMA_CLK_CONTROLS_EXT 6
#define SSP_LINK_CLK_SOURCE 7
/**< Base top-level structure of an address of a gateway. */
/*!
* The virtual index value, presented on the top level as raw 8 bits,
* is expected to be encoded in a gateway specific way depending on
* the actual type of gateway.
*/
union dai_intel_ipc4_connector_node_id {
/**< Raw 32-bit value of node id. */
uint32_t dw;
/**< Bit fields */
struct {
/**< Index of the virtual DMA at the gateway. */
uint32_t v_index : 8;
/**< Type of the gateway, one of ConnectorNodeId::Type values. */
uint32_t dma_type : 5;
/**< Rsvd field. */
uint32_t _rsvd : 19;
} f; /**<< Bits */
} __packed;
/*!
* Attributes are usually provided along with the gateway configuration
* BLOB when the FW is requested to instantiate that gateway.
*
* There are flags which requests FW to allocate gateway related data
* (buffers and other items used while transferring data, like linked list)
* to be allocated from a special memory area, e.g low power memory.
*/
union dai_intel_ipc4_gateway_attributes {
/**< Raw value */
uint32_t dw;
/**< Access to the fields */
struct {
/**< Gateway data requested in low power memory. */
uint32_t lp_buffer_alloc : 1;
/**< Gateway data requested in register file memory. */
uint32_t alloc_from_reg_file : 1;
/**< Reserved field */
uint32_t _rsvd : 30;
} bits; /**<< Bits */
} __packed;
/**< Configuration for the IPC Gateway */
struct dai_intel_ipc4_gateway_config_blob {
/**< Size of the gateway buffer, specified in bytes */
uint32_t buffer_size;
/**< Flags */
union flags {
struct bits {
/**< Activates high threshold notification */
/*!
* Indicates whether notification should be sent to the host
* when the size of data in the buffer reaches the high threshold
* specified by threshold_high parameter.
*/
uint32_t notif_high : 1;
/**< Activates low threshold notification */
/*!
* Indicates whether notification should be sent to the host
* when the size of data in the buffer reaches the low threshold
* specified by threshold_low parameter.
*/
uint32_t notif_low : 1;
/**< Reserved field */
uint32_t rsvd : 30;
} f; /**<< Bits */
/**< Raw value of flags */
uint32_t flags_raw;
} u; /**<< Flags */
/**< High threshold */
/*!
* Specifies the high threshold (in bytes) for notifying the host
* about the buffered data level.
*/
uint32_t threshold_high;
/**< Low threshold */
/*!
* Specifies the low threshold (in bytes) for notifying the host
* about the buffered data level.
*/
uint32_t threshold_low;
} __packed;
/* i2s Configuration BLOB building blocks */
/* i2s registers for i2s Configuration */
struct dai_intel_ipc4_ssp_config {
uint32_t ssc0;
uint32_t ssc1;
uint32_t sscto;
uint32_t sspsp;
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
uint32_t sstsa;
uint32_t ssrsa;
#endif
uint32_t ssc2;
uint32_t sspsp2;
uint32_t ssc3;
uint32_t ssioc;
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
uint64_t ssmidytsa[I2SIPCMC];
uint64_t ssmodytsa[I2SOPCMC];
#endif
} __packed;
struct dai_intel_ipc4_ssp_mclk_config {
/* master clock divider control register */
uint32_t mdivc;
/* master clock divider ratio register */
uint32_t mdivr;
} __packed;
struct dai_intel_ipc4_ssp_mclk_config_2 {
uint32_t mdivctlr;
uint32_t mdivrcnt;
uint32_t mdivr[];
} __packed;
struct dai_intel_ipc4_ssp_driver_config {
struct dai_intel_ipc4_ssp_config i2s_config;
struct dai_intel_ipc4_ssp_mclk_config mclk_config;
} __packed;
struct dai_intel_ipc4_ssp_start_control {
/* delay in msec between enabling interface (moment when
* Copier instance is being attached to the interface) and actual
* interface start. Value of 0 means no delay.
*/
uint32_t clock_warm_up : 16;
/* specifies if parameters target MCLK (1) or SCLK (0) */
uint32_t mclk : 1;
/* value of 1 means that clock should be started immediately
* even if no Copier instance is currently attached to the interface.
*/
uint32_t warm_up_ovr : 1;
uint32_t rsvd0 : 14;
} __packed;
struct dai_intel_ipc4_ssp_stop_control {
/* delay in msec between stopping the interface
* (moment when Copier instance is being detached from the interface)
* and interface clock stop. Value of 0 means no delay.
*/
uint32_t clock_stop_delay : 16;
/* value of 1 means that clock should be kept running (infinite
* stop delay) after Copier instance detaches from the interface.
*/
uint32_t keep_running : 1;
/* value of 1 means that clock should be stopped immediately */
uint32_t clock_stop_ovr : 1;
uint32_t rsvd1 : 14;
} __packed;
union dai_intel_ipc4_ssp_dma_control {
struct dai_intel_ipc4_ssp_control {
struct dai_intel_ipc4_ssp_start_control start_control;
struct dai_intel_ipc4_ssp_stop_control stop_control;
} control_data;
struct dai_intel_ipc4_mn_div_config {
uint32_t mval;
uint32_t nval;
} mndiv_control_data;
} __packed;
struct dai_intel_ipc4_ssp_configuration_blob {
union dai_intel_ipc4_gateway_attributes gw_attr;
/* TDM time slot mappings */
uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT];
/* i2s port configuration */
struct dai_intel_ipc4_ssp_driver_config i2s_driver_config;
/* optional configuration parameters */
FLEXIBLE_ARRAY_DECLARE(union dai_intel_ipc4_ssp_dma_control, i2s_dma_control);
} __packed;
#define SSP_BLOB_VER_1_5 0xee000105
struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 {
union dai_intel_ipc4_gateway_attributes gw_attr;
uint32_t version;
uint32_t size;
/* TDM time slot mappings */
uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT];
/* i2s port configuration */
struct dai_intel_ipc4_ssp_config i2s_ssp_config;
/* clock configuration parameters */
struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control;
} __packed;
#endif
``` | /content/code_sandbox/drivers/dai/intel/ssp/dai-params-intel-ipc4.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,565 |
```objective-c
/*
*
*/
#ifndef __INTEL_DAI_DRIVER_SSP_REGSV3_H__
#define __INTEL_DAI_DRIVER_SSP_REGSV3_H__
/* SSP register offsets */
#define SSCR0 0x00
#define SSCR1 0x04
#define SSSR 0x08
#define SSITR 0x0C
#define SSTO 0x28
#define SSPSP 0x2C
#define SSTSS 0x38
#define SSCR2 0x40
#define SSPSP2 0x44
#define SSIOC 0x4C
#define SSGFS 0x50
#define I2SIPCMC 8
#define SSMIDyCS(y) 0x60 + 0x10*y
#define SSMIDyD(y) 0x64 + 0x10*y
#define SSMIDyTSA(y) 0x68 + 0x10*y
#define SSMODyCS(y) 0x60 + 0x10*I2SIPCMC + 0x10*y
#define SSMODyD(y) 0x64 + 0x10*I2SIPCMC + 0x10*y
#define SSMODyTSA(y) 0x68 + 0x10*I2SIPCMC + 0x10*y
#define PCMSyCM_OFFSET(x) 0x16 + 0x4*(x)
#define OUT_FIFO SSMODyD(0)
#define IN_FIFO SSMIDyD(0)
/* SSCR0 bits */
#define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
#define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
#define SSCR0_FRF DAI_INTEL_SSP_MASK(5, 4)
#define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0)
#define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
#define SSCR0_NAT DAI_INTEL_SSP_SET_BITS(5, 4, 2)
#define SSCR0_PSP DAI_INTEL_SSP_SET_BITS(5, 4, 3)
#define SSCR0_RSVD1 BIT(6)
#define SSCR0_SSE BIT(7)
#define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
#define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
#define SSCR0_EDSS BIT(20)
#define SSCR0_RSVD2 BIT(21)
#define SSCR0_RIM BIT(22)
#define SSCR0_TIM BIT(23)
#define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
#define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
#define SSCR0_EFRDC BIT(27)
#define SSCR0_EFRDC2 BIT(28)
#define SSCR0_DLE DAI_INTEL_SSP_SET_BITS(30, 29, 0)
#define SSCR0_ACS BIT(30)
#define SSCR0_MOD BIT(31)
/* SSCR1 bits */
#define SSCR1_RIE BIT(0)
#define SSCR1_TIE BIT(1)
#define SSCR1_LBM BIT(2)
#define SSCR1_RSVD1 DAI_INTEL_SSP_MASK(15, 3)
#define SSCR1_IFS BIT(16)
#define SSCR1_PINTE BIT(18)
#define SSCR1_TINTE BIT(19)
#define SSCR1_RSVD21 DAI_INTEL_SSP_MASK(21, 20)
#define SSCR1_TRAIL BIT(22)
#define SSCR1_RWOT BIT(23)
#define SSCR1_SFRMDIR BIT(24)
#define SSCR1_SCLKDIR BIT(25)
#define SSCR1_SCFR BIT(28)
#define SSCR1_EBCEI BIT(29)
#define SSCR1_TTE BIT(30)
#define SSCR1_TTELP BIT(31)
#define SSCR2_TURM1 BIT(1)
#define SSCR2_PSPSRWFDFD BIT(3)
#define SSCR2_PSPSTWFDFD BIT(4)
#define SSCR2_SDFD BIT(14)
#define SSCR2_SDPM BIT(16)
#define SSCR2_LJDFD BIT(17)
#define SSCR2_MMRATF BIT(18)
#define SSCR2_SMTATF BIT(19)
#define SSCR2_SFRMEN BIT(20)
#define SSCR2_ACIOLBS BIT(21)
/* SSR bits */
#define SSSR_BSY BIT(4)
#define SSSR_ROR BIT(7)
#define SSSR_TUR BIT(21)
/* SSPSP bits */
#define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x)
#define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x)
#define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x)
#define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x)
#define SSPSP_SFRMDLY(x) DAI_INTEL_SSP_SET_BITS(15, 9, x)
#define SSPSP_SFRMWDTH(x) DAI_INTEL_SSP_SET_BITS(21, 16, x)
#define SSPSP_DMYSTOP(x) DAI_INTEL_SSP_SET_BITS(24, 23, x)
#define SSPSP_DMYSTOP_BITS 2
#define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
#define SSPSP_FSRT BIT(25)
#define SSPSP_EDMYSTOP(x) DAI_INTEL_SSP_SET_BITS(28, 26, x)
#define SSPSP2 0x44
#define SSPSP2_FEP_MASK 0xff
#define SSPSP2_RFAC DAI_INTEL_SSP_MASK(9, 8)
#define SSPSP2_TFAC DAI_INTEL_SSP_MASK(11, 10)
#define SSPSP2_EFEP DAI_INTEL_SSP_MASK(13, 12)
#define SSPSP2_ESFRMDW DAI_INTEL_SSP_MASK(15, 14)
#define SSCR3 0x48
#define SSIOC 0x4C
#define SSP_REG_MAX SSIOC
/* SSTSA bits */
#define SSTSA_SSTSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x)
#define SSTSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0))
/* SSRSA bits */
#define SSRSA_SSRSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x)
#define SSRSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0))
/* SSCR3 bits */
#define SSCR3_FRM_MST_EN BIT(0)
#define SSCR3_I2S_MODE_EN BIT(1)
#define SSCR3_I2S_FRM_POL(x) DAI_INTEL_SSP_SET_BIT(2, x)
#define SSCR3_I2S_TX_SS_FIX_EN BIT(3)
#define SSCR3_I2S_RX_SS_FIX_EN BIT(4)
#define SSCR3_I2S_TX_EN BIT(9)
#define SSCR3_I2S_RX_EN BIT(10)
#define SSCR3_CLK_EDGE_SEL BIT(12)
#define SSCR3_STRETCH_TX BIT(14)
#define SSCR3_STRETCH_RX BIT(15)
#define SSCR3_MST_CLK_EN BIT(16)
#define SSCR3_SYN_FIX_EN BIT(17)
/* SSCR4 bits */
#define SSCR4_TOT_FRM_PRD(x) ((x) << 7)
/* SSCR5 bits */
#define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
#define SSCR5_FRM_POLARITY(x) DAI_INTEL_SSP_SET_BIT(0, x)
/* SFIFOTT bits */
#define SFIFOTT_TX(x) ((x) - 1)
#define SFIFOTT_RX(x) (((x) - 1) << 16)
/* SFIFOL bits */
#define SFIFOL_TFL(x) ((x) & 0xFFFF)
#define SFIFOL_RFL(x) ((x) >> 16)
#define SSTSA_TSEN BIT(8)
#define SSRSA_RSEN BIT(8)
#define SSCR3_TFL_MASK DAI_INTEL_SSP_MASK(5, 0)
#define SSCR3_RFL_MASK DAI_INTEL_SSP_MASK(13, 8)
#define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
#define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
#define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
#define SSCR3_RX(x) DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
#define SSIOC_TXDPDEB BIT(1)
#define SSIOC_SFCR BIT(4)
#define SSIOC_SCOE BIT(5)
/* SSMIDyCS */
#define SSMIDyCS_RXEN BIT(0)
#define SSMIDyCS_RSRE BIT(1)
#define SSMIDyCS_RFL DAI_INTEL_SSP_MASK(23, 16)
#define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
#define SSMIDyCS_RNE BIT(26)
#define SSMIDyCS_RFS BIT(27)
#define SSMIDyCS_ROR BIT(28)
#define SSMIDyCS_PINT BIT(29)
#define SSMIDyCS_TINT BIT(30)
#define SSMIDyCS_EOC BIT(31)
/* SSMIDyTSA */
#define SSMIDyTSA_RTSA DAI_INTEL_SSP_MASK(63, 0)
#define SSMIDyTSA_SRTSA(x) DAI_INTEL_SSP_MASK(63, 0, x)
/* SSMODyCS */
#define SSMODyCS_TXEN BIT(0)
#define SSMODyCS_TSRE BIT(1)
#define SSMODyCS_TFL DAI_INTEL_SSP_MASK(23, 16)
#define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
#define SSMODyCS_TNF BIT(26)
#define SSMODyCS_TFS BIT(27)
#define SSMODyCS_TUR BIT(28)
/* SSMODyTSA */
#define SSMODyTSA_TTSA DAI_INTEL_SSP_MASK(63, 0)
#define SSMODyTSA_STTSA(x) DAI_INTEL_SSP_MASK(63, 0, x)
/* For 8000 Hz rate one sample is transmitted within 125us */
#define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
/* SSP flush retry counts maximum */
#define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX 16
#define SSP_CLK_MCLK_ES_REQ BIT(0)
#define SSP_CLK_MCLK_ACTIVE BIT(1)
#define SSP_CLK_BCLK_ES_REQ BIT(2)
#define SSP_CLK_BCLK_ACTIVE BIT(3)
#define I2SLCTL_OFFSET 0x04
#define I2SLCTL_OFLEN BIT(4)
#define I2SLCTL_SPA(x) BIT(16 + x)
#define I2SLCTL_CPA(x) BIT(23 + x)
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x)
#define SHIM_CLKCTL 0x78
#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)
/** \brief Offset of MCLK Divider Control Register. */
#define MN_MDIVCTRL 0x100
/** \brief Offset of MCLK Divider x Ratio Register. */
#define MN_MDIVR(x) (0x180 + (x) * 0x4)
/** \brief Enables the output of MCLK Divider. */
#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
/** \brief Bits for setting MCLK source clock. */
#define MCDSS(x) DAI_INTEL_SSP_SET_BITS(17, 16, x)
/** \brief Offset of BCLK x M/N Divider M Value Register. */
#define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
/** \brief Offset of BCLK x M/N Divider N Value Register. */
#define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
/** \brief Bits for setting M/N source clock. */
#define MNDSS(x) DAI_INTEL_SSP_SET_BITS(21, 20, x)
/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
#define MN_SOURCE_CLKS_MASK 0x3
#endif /* __INTEL_DAI_DRIVER_SSP_REGSV1_H__ */
``` | /content/code_sandbox/drivers/dai/intel/ssp/ssp_regs_v3.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,174 |
```unknown
# SOF HDA configuration options
config DAI_INTEL_HDA
bool "Intel HDA driver for Dai interface"
default y
depends on DT_HAS_INTEL_HDA_DAI_ENABLED
select DMA
help
Select this to enable Intel HDA driver.
``` | /content/code_sandbox/drivers/dai/intel/hda/Kconfig.hda | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#include <errno.h>
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/spinlock.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#define DT_DRV_COMPAT intel_hda_dai
#define LOG_DOMAIN dai_intel_hda
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include "hda.h"
static int dai_hda_trigger(const struct device *dev, enum dai_dir dir,
enum dai_trigger_cmd cmd)
{
LOG_DBG("cmd %d", cmd);
return 0;
}
/* Digital Audio interface formatting */
static int dai_hda_set_config_tplg(struct dai_intel_hda *dp, const void *spec_config)
{
struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
const struct dai_intel_ipc_hda_params *config = spec_config;
if (config->channels) {
hda->params.channels = config->channels;
}
if (config->rate) {
hda->params.rate = config->rate;
}
return 0;
}
static int dai_hda_config_get(const struct device *dev, struct dai_config *cfg, enum dai_dir dir)
{
struct dai_config *params = (struct dai_config *)dev->config;
struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
if (!cfg) {
return -EINVAL;
}
params->rate = hda->params.rate;
params->channels = hda->params.channels;
params->word_size = DAI_INTEL_HDA_DEFAULT_WORD_SIZE;
*cfg = *params;
return 0;
}
static int dai_hda_config_set(const struct device *dev, const struct dai_config *cfg,
const void *bespoke_cfg)
{
struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
if (cfg->type == DAI_INTEL_HDA) {
return dai_hda_set_config_tplg(dp, bespoke_cfg);
}
return 0;
}
static const struct dai_properties *dai_hda_get_properties(const struct device *dev,
enum dai_dir dir, int stream_id)
{
struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
struct dai_properties *prop = &hda->props;
prop->fifo_address = 0;
prop->dma_hs_id = 0;
prop->stream_id = 0;
return prop;
}
static int dai_hda_probe(const struct device *dev)
{
LOG_DBG("%s", __func__);
return 0;
}
static int dai_hda_remove(const struct device *dev)
{
LOG_DBG("%s", __func__);
return 0;
}
static const struct dai_driver_api dai_intel_hda_api_funcs = {
.probe = dai_hda_probe,
.remove = dai_hda_remove,
.config_set = dai_hda_config_set,
.config_get = dai_hda_config_get,
.trigger = dai_hda_trigger,
.get_properties = dai_hda_get_properties,
};
#define DAI_INTEL_HDA_DEVICE_INIT(n) \
static struct dai_config dai_intel_hda_config_##n = { \
.type = DAI_INTEL_HDA, \
.dai_index = DT_INST_REG_ADDR(n), \
}; \
static struct dai_intel_hda dai_intel_hda_data_##n = { \
.index = DT_INST_REG_ADDR(n) \
\
}; \
\
DEVICE_DT_INST_DEFINE(n, \
NULL, NULL, \
&dai_intel_hda_data_##n, \
&dai_intel_hda_config_##n, \
POST_KERNEL, 32, \
&dai_intel_hda_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(DAI_INTEL_HDA_DEVICE_INIT)
``` | /content/code_sandbox/drivers/dai/intel/hda/hda.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 883 |
```objective-c
/*
*
*/
#ifndef __INTEL_DAI_DRIVER_HDA_H__
#define __INTEL_DAI_DRIVER_HDA_H__
#include <stdint.h>
#include <zephyr/drivers/dai.h>
#define dai_get_drvdata(dai) &dai->priv_data
#define dai_base(dai) dai->plat_data.base
#define DAI_INTEL_HDA_DEFAULT_WORD_SIZE 16
struct dai_intel_ipc_hda_params {
uint32_t reserved0;
uint32_t link_dma_ch;
uint32_t rate;
uint32_t channels;
} __packed;
struct dai_intel_hda_pdata {
struct dai_config config;
struct dai_properties props;
struct dai_intel_ipc_hda_params params;
};
struct dai_intel_hda {
uint32_t index;
struct k_spinlock lock;
struct dai_intel_hda_pdata priv_data;
};
#endif
``` | /content/code_sandbox/drivers/dai/intel/hda/hda.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 176 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/sys/util_macro.h>
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/spinlock.h>
#include <zephyr/devicetree.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#define LOG_DOMAIN dai_intel_ssp
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include "ssp.h"
#define dai_set_drvdata(dai, data) (dai->priv_data = data)
#define dai_get_drvdata(dai) dai->priv_data
#define dai_get_plat_data(dai) dai->ssp_plat_data
#define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
#define dai_get_ftable(dai) dai->ssp_plat_data->ftable
#define dai_get_fsources(dai) dai->ssp_plat_data->fsources
#define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
#define dai_base(dai) dai->ssp_plat_data->base
#define dai_ip_base(dai) dai->ssp_plat_data->ip_base
#define dai_shim_base(dai) dai->ssp_plat_data->shim_base
#define dai_hdamlssp_base(dai) dai->ssp_plat_data->hdamlssp_base
#define dai_i2svss_base(dai) dai->ssp_plat_data->i2svss_base
#define DAI_DIR_PLAYBACK 0
#define DAI_DIR_CAPTURE 1
#define SSP_ARRAY_INDEX(dir) dir == DAI_DIR_RX ? DAI_DIR_CAPTURE : DAI_DIR_PLAYBACK
static const char irq_name_level5_z[] = "level5";
static struct dai_intel_ssp_freq_table ssp_freq_table[] = {
{ DT_PROP(DT_NODELABEL(audioclk), clock_frequency),
DT_PROP(DT_NODELABEL(audioclk), clock_frequency) / 1000},
{ DT_PROP(DT_NODELABEL(sysclk), clock_frequency),
DT_PROP(DT_NODELABEL(sysclk), clock_frequency) / 1000},
{ DT_PROP(DT_NODELABEL(pllclk), clock_frequency),
DT_PROP(DT_NODELABEL(pllclk), clock_frequency) / 1000},
};
static uint32_t ssp_freq_sources[] = {
DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL,
DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR,
DAI_INTEL_SSP_CLOCK_PLL_FIXED,
};
static struct dai_intel_ssp_mn ssp_mn_divider = {
.base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(ssp0), 1),
};
#define INTEL_SSP_INST_DEFINE(node_id) { \
.is_initialized = false, \
.is_power_en = false, \
.acquire_count = 0, \
.ssp_index = DT_PROP(node_id, ssp_index), \
.base = DT_REG_ADDR_BY_IDX(node_id, 0), \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(sspbase)), \
(.ip_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(sspbase), 0),)) \
.shim_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(shim), 0), \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(hdamlssp)), \
(.hdamlssp_base = DT_REG_ADDR(DT_NODELABEL(hdamlssp)),))\
IF_ENABLED(DT_PROP_HAS_IDX(node_id, i2svss, 0), \
(.i2svss_base = DT_PROP_BY_IDX(node_id, i2svss, 0),)) \
.irq = DT_NUM_IRQS(node_id), \
.irq_name = irq_name_level5_z, \
.fifo[DAI_DIR_PLAYBACK].offset = \
DT_REG_ADDR_BY_IDX(node_id, 0) + OUT_FIFO, \
.fifo[DAI_DIR_PLAYBACK].handshake = \
DT_DMAS_CELL_BY_NAME(node_id, tx, channel), \
.fifo[DAI_DIR_CAPTURE].offset = \
DT_REG_ADDR_BY_IDX(node_id, 0) + IN_FIFO, \
.fifo[DAI_DIR_CAPTURE].handshake = \
DT_DMAS_CELL_BY_NAME(node_id, rx, channel), \
.mn_inst = &ssp_mn_divider, \
.ftable = ssp_freq_table, \
.fsources = ssp_freq_sources, \
.clk_active = 0, \
},
static struct dai_intel_ssp_plat_data ssp_plat_data_table[] = {
DT_FOREACH_STATUS_OKAY(intel_ssp, INTEL_SSP_INST_DEFINE)
};
static uint32_t ssp_get_instance_count(void)
{
return ARRAY_SIZE(ssp_plat_data_table);
}
static struct dai_intel_ssp_plat_data *ssp_get_device_instance(uint32_t ssp_index)
{
uint32_t ssp_instance = ssp_get_instance_count();
uint32_t i;
for (i = 0; i < ssp_instance; i++) {
if (ssp_plat_data_table[i].ssp_index == ssp_index) {
return &ssp_plat_data_table[i];
}
}
return NULL;
}
static void dai_ssp_update_bits(struct dai_intel_ssp *dp, uint32_t reg, uint32_t mask, uint32_t val)
{
uint32_t dest = dai_base(dp) + reg;
LOG_DBG("base %x, reg %x, mask %x, value %x", dai_base(dp), reg, mask, val);
sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest);
}
#if CONFIG_INTEL_MN
static int dai_ssp_gcd(int a, int b)
{
int aux;
int k;
if (a == 0) {
return b;
}
if (b == 0) {
return a;
}
/* If the numbers are negative, convert them to positive numbers
* gcd(a, b) = gcd(-a, -b) = gcd(-a, b) = gcd(a, -b)
*/
if (a < 0) {
a = -a;
}
if (b < 0) {
b = -b;
}
/* Find the greatest power of 2 that devides both a and b */
for (k = 0; ((a | b) & 1) == 0; k++) {
a >>= 1;
b >>= 1;
}
/* divide by 2 until a becomes odd */
while ((a & 1) == 0) {
a >>= 1;
}
do {
/*if b is even, remove all factors of 2*/
while ((b & 1) == 0) {
b >>= 1;
}
/* both a and b are odd now. Swap so a <= b
* then set b = b - a, which is also even
*/
if (a > b) {
aux = a;
a = b;
b = aux;
}
b = b - a;
} while (b != 0);
/* restore common factors of 2 */
return a << k;
}
#endif
/**
* \brief Checks if given clock is used as source for any MCLK.
*
* \return true if any port use given clock source, false otherwise.
*/
static bool dai_ssp_is_mclk_source_in_use(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
bool ret = false;
int i;
for (i = 0; i < ARRAY_SIZE(mp->mclk_sources_ref); i++) {
if (mp->mclk_sources_ref[i] > 0) {
ret = true;
break;
}
}
return ret;
}
/**
* \brief Configures source clock for MCLK.
* All MCLKs share the same source, so it should be changed
* only if there are no other ports using it already.
* \param[in] mclk_rate main clock frequency.
* \return 0 on success, error code otherwise.
*/
static int dai_ssp_setup_initial_mclk_source(struct dai_intel_ssp *dp, uint32_t mclk_id,
uint32_t mclk_rate)
{
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
uint32_t *fs = dai_get_fsources(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
int clk_index = -1;
uint32_t mdivc;
int ret = 0;
int i;
if (mclk_id >= DAI_INTEL_SSP_NUM_MCLK) {
LOG_ERR("can't configure MCLK %d, only %d mclk[s] existed!",
mclk_id, DAI_INTEL_SSP_NUM_MCLK);
ret = -EINVAL;
goto out;
}
/* searching the smallest possible mclk source */
for (i = 0; i <= DAI_INTEL_SSP_MAX_FREQ_INDEX; i++) {
if (ft[i].freq % mclk_rate == 0) {
clk_index = i;
break;
}
}
if (clk_index < 0) {
LOG_ERR("MCLK %d, no valid source", mclk_rate);
ret = -EINVAL;
goto out;
}
mp->mclk_source_clock = clk_index;
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
/* enable MCLK divider */
mdivc |= MN_MDIVCTRL_M_DIV_ENABLE(mclk_id);
/* clear source mclk clock - bits 17-16 */
mdivc &= ~MCDSS(MN_SOURCE_CLKS_MASK);
/* select source clock */
mdivc |= MCDSS(fs[clk_index]);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
mp->mclk_sources_ref[mclk_id]++;
out:
return ret;
}
/**
* \brief Checks if requested MCLK can be achieved with current source.
* \param[in] mclk_rate main clock frequency.
* \return 0 on success, error code otherwise.
*/
static int dai_ssp_check_current_mclk_source(struct dai_intel_ssp *dp, uint16_t mclk_id,
uint32_t mclk_rate)
{
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
uint32_t mdivc;
int ret = 0;
LOG_INF("MCLK %d, source = %d", mclk_rate, mp->mclk_source_clock);
if (ft[mp->mclk_source_clock].freq % mclk_rate != 0) {
LOG_ERR("MCLK %d, no valid configuration for already selected source = %d",
mclk_rate, mp->mclk_source_clock);
ret = -EINVAL;
}
/* if the mclk is already used, can't change its divider, just increase ref count */
if (mp->mclk_sources_ref[mclk_id] > 0) {
if (mp->mclk_rate[mclk_id] != mclk_rate) {
LOG_ERR("Can't set MCLK %d to %d, it is already configured to %d",
mclk_id, mclk_rate, mp->mclk_rate[mclk_id]);
return -EINVAL;
}
mp->mclk_sources_ref[mclk_id]++;
} else {
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
/* enable MCLK divider */
mdivc |= MN_MDIVCTRL_M_DIV_ENABLE(mclk_id);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
mp->mclk_sources_ref[mclk_id]++;
}
return ret;
}
/**
* \brief Sets MCLK divider to given value.
* \param[in] mclk_id ID of MCLK.
* \param[in] mdivr_val divider value.
* \return 0 on success, error code otherwise.
*/
static int dai_ssp_set_mclk_divider(struct dai_intel_ssp *dp, uint16_t mclk_id, uint32_t mdivr_val)
{
uint32_t mdivr;
LOG_INF("mclk_id %d mdivr_val %d", mclk_id, mdivr_val);
switch (mdivr_val) {
case 1:
mdivr = 0x00000fff; /* bypass divider for MCLK */
break;
case 2 ... 8:
mdivr = mdivr_val - 2; /* 1/n */
break;
default:
LOG_ERR("invalid mdivr_val %d", mdivr_val);
return -EINVAL;
}
sys_write32(mdivr, dai_mn_base(dp) + MN_MDIVR(mclk_id));
return 0;
}
static int dai_ssp_mn_set_mclk(struct dai_intel_ssp *dp, uint16_t mclk_id, uint32_t mclk_rate)
{
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
k_spinlock_key_t key;
int ret = 0;
if (mclk_id >= DAI_INTEL_SSP_NUM_MCLK) {
LOG_ERR("mclk ID (%d) >= %d", mclk_id, DAI_INTEL_SSP_NUM_MCLK);
return -EINVAL;
}
key = k_spin_lock(&mp->lock);
if (dai_ssp_is_mclk_source_in_use(dp)) {
ret = dai_ssp_check_current_mclk_source(dp, mclk_id, mclk_rate);
} else {
ret = dai_ssp_setup_initial_mclk_source(dp, mclk_id, mclk_rate);
}
if (ret < 0) {
goto out;
}
LOG_INF("mclk_rate %d, mclk_source_clock %d", mclk_rate, mp->mclk_source_clock);
ret = dai_ssp_set_mclk_divider(dp, mclk_id, ft[mp->mclk_source_clock].freq / mclk_rate);
if (!ret) {
mp->mclk_rate[mclk_id] = mclk_rate;
}
out:
k_spin_unlock(&mp->lock, key);
return ret;
}
static int dai_ssp_mn_set_mclk_blob(struct dai_intel_ssp *dp, uint32_t mdivc, uint32_t mdivr)
{
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
sys_write32(mdivr, dai_mn_base(dp) + MN_MDIVR(0));
return 0;
}
static void dai_ssp_mn_release_mclk(struct dai_intel_ssp *dp, uint32_t mclk_id)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
k_spinlock_key_t key;
uint32_t mdivc;
key = k_spin_lock(&mp->lock);
mp->mclk_sources_ref[mclk_id]--;
/* disable MCLK divider if nobody use it */
if (!mp->mclk_sources_ref[mclk_id]) {
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
mdivc &= ~MN_MDIVCTRL_M_DIV_ENABLE(mclk_id);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
}
/* release the clock source if all mclks are released */
if (!dai_ssp_is_mclk_source_in_use(dp)) {
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
/* clear source mclk clock - bits 17-16 */
mdivc &= ~MCDSS(MN_SOURCE_CLKS_MASK);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
mp->mclk_source_clock = 0;
}
k_spin_unlock(&mp->lock, key);
}
#if CONFIG_INTEL_MN
/**
* \brief Finds valid M/(N * SCR) values for given frequencies.
* \param[in] freq SSP clock frequency.
* \param[in] bclk Bit clock frequency.
* \param[out] out_scr_div SCR divisor.
* \param[out] out_m M value of M/N divider.
* \param[out] out_n N value of M/N divider.
* \return true if found suitable values, false otherwise.
*/
static bool dai_ssp_find_mn(uint32_t freq, uint32_t bclk, uint32_t *out_scr_div, uint32_t *out_m,
uint32_t *out_n)
{
uint32_t m, n, mn_div;
uint32_t scr_div = freq / bclk;
LOG_INF("for freq %d bclk %d", freq, bclk);
/* check if just SCR is enough */
if (freq % bclk == 0 && scr_div < (SSCR0_SCR_MASK >> 8) + 1) {
*out_scr_div = scr_div;
*out_m = 1;
*out_n = 1;
return true;
}
/* M/(N * scr_div) has to be less than 1/2 */
if ((bclk * 2) >= freq) {
return false;
}
/* odd SCR gives lower duty cycle */
if (scr_div > 1 && scr_div % 2 != 0) {
--scr_div;
}
/* clamp to valid SCR range */
scr_div = MIN(scr_div, (SSCR0_SCR_MASK >> 8) + 1);
/* find highest even divisor */
while (scr_div > 1 && freq % scr_div != 0) {
scr_div -= 2;
}
/* compute M/N with smallest dividend and divisor */
mn_div = dai_ssp_gcd(bclk, freq / scr_div);
m = bclk / mn_div;
n = freq / scr_div / mn_div;
/* M/N values can be up to 24 bits */
if (n & (~0xffffff)) {
return false;
}
*out_scr_div = scr_div;
*out_m = m;
*out_n = n;
LOG_INF("m %d n %d", m, n);
return true;
}
/**
* \brief Finds index of clock valid for given BCLK rate.
* Clock that can use just SCR is preferred.
* M/N other than 1/1 is used only if there are no other possibilities.
* \param[in] bclk Bit clock frequency.
* \param[out] scr_div SCR divisor.
* \param[out] m M value of M/N divider.
* \param[out] n N value of M/N divider.
* \return index of suitable clock if could find it, -EINVAL otherwise.
*/
static int dai_ssp_find_bclk_source(struct dai_intel_ssp *dp, uint32_t bclk, uint32_t *scr_div,
uint32_t *m, uint32_t *n)
{
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
int i;
/* check if we can use MCLK source clock */
if (dai_ssp_is_mclk_source_in_use(dp)) {
if (dai_ssp_find_mn(ft[mp->mclk_source_clock].freq, bclk, scr_div, m, n)) {
return mp->mclk_source_clock;
}
LOG_WRN("BCLK %d warning: cannot use MCLK source %d", bclk,
ft[mp->mclk_source_clock].freq);
}
/* searching the smallest possible bclk source */
for (i = 0; i <= DAI_INTEL_SSP_MAX_FREQ_INDEX; i++)
if (ft[i].freq % bclk == 0) {
*scr_div = ft[i].freq / bclk;
return i;
}
/* check if we can get target BCLK with M/N */
for (i = 0; i <= DAI_INTEL_SSP_MAX_FREQ_INDEX; i++) {
if (dai_ssp_find_mn(ft[i].freq, bclk, scr_div, m, n)) {
return i;
}
}
return -EINVAL;
}
/**
* \brief Finds index of SSP clock with the given clock source encoded index.
* \return the index in ssp_freq if could find it, -EINVAL otherwise.
*/
static int dai_ssp_find_clk_ssp_index(struct dai_intel_ssp *dp, uint32_t src_enc)
{
uint32_t *fs = dai_get_fsources(dp);
int i;
/* searching for the encode value matched bclk source */
for (i = 0; i <= DAI_INTEL_SSP_MAX_FREQ_INDEX; i++) {
if (fs[i] == src_enc) {
return i;
}
}
return -EINVAL;
}
/**
* \brief Checks if given clock is used as source for any BCLK.
* \param[in] clk_src Bit clock source.
* \return true if any port use given clock source, false otherwise.
*/
static bool dai_ssp_is_bclk_source_in_use(struct dai_intel_ssp *dp, enum bclk_source clk_src)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
bool ret = false;
int i;
for (i = 0; i < ARRAY_SIZE(mp->bclk_sources); i++) {
if (mp->bclk_sources[i] == clk_src) {
ret = true;
break;
}
}
return ret;
}
/**
* \brief Configures M/N source clock for BCLK.
* All ports that use M/N share the same source, so it should be changed
* only if there are no other ports using M/N already.
* \param[in] bclk Bit clock frequency.
* \param[out] scr_div SCR divisor.
* \param[out] m M value of M/N divider.
* \param[out] n N value of M/N divider.
* \return 0 on success, error code otherwise.
*/
static int dai_ssp_setup_initial_bclk_mn_source(struct dai_intel_ssp *dp, uint32_t bclk,
uint32_t *scr_div, uint32_t *m, uint32_t *n)
{
uint32_t *fs = dai_get_fsources(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
uint32_t mdivc;
int clk_index = dai_ssp_find_bclk_source(dp, bclk, scr_div, m, n);
if (clk_index < 0) {
LOG_ERR("BCLK %d, no valid source", bclk);
return -EINVAL;
}
mp->bclk_source_mn_clock = clk_index;
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
/* clear source bclk clock - 21-20 bits */
mdivc &= ~MNDSS(MN_SOURCE_CLKS_MASK);
/* select source clock */
mdivc |= MNDSS(fs[clk_index]);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
return 0;
}
/**
* \brief Reset M/N source clock for BCLK.
* If no port is using bclk, reset to use SSP_CLOCK_XTAL_OSCILLATOR
* as the default clock source.
*/
static void dai_ssp_reset_bclk_mn_source(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
uint32_t mdivc;
int clk_index = dai_ssp_find_clk_ssp_index(dp, DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR);
if (clk_index < 0) {
LOG_ERR("BCLK reset failed, no SSP_CLOCK_XTAL_OSCILLATOR source!");
return;
}
mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL);
/* reset to use XTAL Oscillator */
mdivc &= ~MNDSS(MN_SOURCE_CLKS_MASK);
mdivc |= MNDSS(DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR);
sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL);
mp->bclk_source_mn_clock = clk_index;
}
/**
* \brief Finds valid M/(N * SCR) values for source clock that is already locked
* because other ports use it.
* \param[in] bclk Bit clock frequency.
* \param[out] scr_div SCR divisor.
* \param[out] m M value of M/N divider.
* \param[out] n N value of M/N divider.
* \return 0 on success, error code otherwise.
*/
static int dai_ssp_setup_current_bclk_mn_source(struct dai_intel_ssp *dp, uint32_t bclk,
uint32_t *scr_div, uint32_t *m, uint32_t *n)
{
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
int ret = 0;
/* source for M/N is already set, no need to do it */
if (dai_ssp_find_mn(ft[mp->bclk_source_mn_clock].freq, bclk, scr_div, m, n)) {
goto out;
}
LOG_ERR("BCLK %d, no valid configuration for already selected source = %d",
bclk, mp->bclk_source_mn_clock);
ret = -EINVAL;
out:
return ret;
}
static bool dai_ssp_check_bclk_xtal_source(uint32_t bclk, bool mn_in_use,
uint32_t *scr_div)
{
/* since cAVS 2.0 bypassing XTAL (ECS=0) is not supported */
return false;
}
static int dai_ssp_mn_set_bclk(struct dai_intel_ssp *dp, uint32_t dai_index, uint32_t bclk_rate,
uint32_t *out_scr_div, bool *out_need_ecs)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
k_spinlock_key_t key;
uint32_t m = 1;
uint32_t n = 1;
int ret = 0;
bool mn_in_use;
key = k_spin_lock(&mp->lock);
mp->bclk_sources[dai_index] = MN_BCLK_SOURCE_NONE;
mn_in_use = dai_ssp_is_bclk_source_in_use(dp, MN_BCLK_SOURCE_MN);
if (dai_ssp_check_bclk_xtal_source(bclk_rate, mn_in_use, out_scr_div)) {
mp->bclk_sources[dai_index] = MN_BCLK_SOURCE_XTAL;
*out_need_ecs = false;
goto out;
}
*out_need_ecs = true;
if (mn_in_use) {
ret = dai_ssp_setup_current_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n);
} else {
ret = dai_ssp_setup_initial_bclk_mn_source(dp, bclk_rate, out_scr_div, &m, &n);
}
if (ret >= 0) {
mp->bclk_sources[dai_index] = MN_BCLK_SOURCE_MN;
LOG_INF("bclk_rate %d, *out_scr_div %d, m %d, n %d", bclk_rate, *out_scr_div, m, n);
sys_write32(m, dai_mn_base(dp) + MN_MDIV_M_VAL(dai_index));
sys_write32(n, dai_mn_base(dp) + MN_MDIV_N_VAL(dai_index));
}
out:
k_spin_unlock(&mp->lock, key);
return ret;
}
static void dai_ssp_mn_release_bclk(struct dai_intel_ssp *dp, uint32_t ssp_index)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
k_spinlock_key_t key;
bool mn_in_use;
key = k_spin_lock(&mp->lock);
mp->bclk_sources[ssp_index] = MN_BCLK_SOURCE_NONE;
mn_in_use = dai_ssp_is_bclk_source_in_use(dp, MN_BCLK_SOURCE_MN);
/* release the M/N clock source if not used */
if (!mn_in_use) {
dai_ssp_reset_bclk_mn_source(dp);
}
k_spin_unlock(&mp->lock, key);
}
static void dai_ssp_mn_reset_bclk_divider(struct dai_intel_ssp *dp, uint32_t ssp_index)
{
struct dai_intel_ssp_mn *mp = dai_get_mn(dp);
k_spinlock_key_t key;
key = k_spin_lock(&mp->lock);
sys_write32(1, dai_mn_base(dp) + MN_MDIV_M_VAL(ssp_index));
sys_write32(1, dai_mn_base(dp) + MN_MDIV_N_VAL(ssp_index));
k_spin_unlock(&mp->lock, key);
}
#endif
static int dai_ssp_poll_for_register_delay(uint32_t reg, uint32_t mask,
uint32_t val, uint64_t us)
{
if (!WAIT_FOR((sys_read32(reg) & mask) == val, us, k_busy_wait(1))) {
LOG_ERR("poll timeout reg %u mask %u val %u us %u", reg, mask, val, (uint32_t)us);
return -EIO;
}
return 0;
}
static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *dp,
uint32_t ssp_index)
{
#if CONFIG_DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING
uint32_t shim_reg;
shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) |
(ssp_index < CONFIG_DAI_INTEL_SSP_NUM_BASE ?
SHIM_CLKCTL_I2SFDCGB(ssp_index) :
SHIM_CLKCTL_I2SEFDCGB(ssp_index -
CONFIG_DAI_INTEL_SSP_NUM_BASE));
sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL);
LOG_INF("ssp_index %d CLKCTL %08x", ssp_index, shim_reg);
#endif
}
static inline void dai_ssp_pm_runtime_en_ssp_clk_gating(struct dai_intel_ssp *dp,
uint32_t ssp_index)
{
#if CONFIG_DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING
uint32_t shim_reg;
shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) &
~(ssp_index < CONFIG_DAI_INTEL_SSP_NUM_BASE ?
SHIM_CLKCTL_I2SFDCGB(ssp_index) :
SHIM_CLKCTL_I2SEFDCGB(ssp_index -
CONFIG_DAI_INTEL_SSP_NUM_BASE));
sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL);
LOG_INF("ssp_index %d CLKCTL %08x", ssp_index, shim_reg);
#endif
}
static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t ssp_index)
{
#if CONFIG_DAI_SSP_HAS_POWER_CONTROL
int ret;
LOG_INF("SSP%d", ssp_index);
#if CONFIG_SOC_INTEL_ACE15_MTPM || CONFIG_SOC_SERIES_INTEL_ADSP_CAVS
sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) | I2SLCTL_SPA(ssp_index),
dai_ip_base(dp) + I2SLCTL_OFFSET);
/* Check if powered on. */
ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index),
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) |
I2SLCTL_SPA(ssp_index),
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
/* Check if powered on. */
ret = dai_ssp_poll_for_register_delay(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index),
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#else
#error need to define SOC
#endif
if (ret) {
LOG_WRN("SSP%d: timeout", ssp_index);
}
#else
ARG_UNUSED(dp);
ARG_UNUSED(ssp_index);
#endif /* CONFIG_DAI_SSP_HAS_POWER_CONTROL */
}
static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t ssp_index)
{
#if CONFIG_DAI_SSP_HAS_POWER_CONTROL
int ret;
LOG_INF("SSP%d", ssp_index);
#if CONFIG_SOC_INTEL_ACE15_MTPM || CONFIG_SOC_SERIES_INTEL_ADSP_CAVS
sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)),
dai_ip_base(dp) + I2SLCTL_OFFSET);
/* Check if powered off. */
ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(ssp_index), 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)),
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
/* Check if powered off. */
ret = dai_ssp_poll_for_register_delay(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(ssp_index), 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#else
#error need to define SOC
#endif
if (ret) {
LOG_WRN("SSP%d: timeout", ssp_index);
}
#else
ARG_UNUSED(dp);
ARG_UNUSED(ssp_index);
#endif /* CONFIG_DAI_SSP_HAS_POWER_CONTROL */
}
static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
const struct dai_config *cfg, uint32_t ssp_index, const void *spec_config)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL)
ARG_UNUSED(spec_config);
uint16_t pcmsycm = cfg->link_config;
/* Set upper slot number from configuration */
pcmsycm = pcmsycm | (dp->ssp_plat_data->params.tdm_slots - 1) << 4;
if (DAI_INTEL_SSP_IS_BIT_SET(cfg->link_config, 15)) {
uint32_t reg_add = dai_ip_base(dp) + 0x1000 * ssp_index + PCMS0CM_OFFSET;
/* Program HDA output stream parameters */
sys_write16((pcmsycm & 0xffff), reg_add);
} else {
uint32_t reg_add = dai_ip_base(dp) + 0x1000 * ssp_index + PCMS1CM_OFFSET;
/* Program HDA input stream parameters */
sys_write16((pcmsycm & 0xffff), reg_add);
}
#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
uint64_t time_slot_map = 0;
uint16_t pcmsycm = cfg->link_config;
uint8_t slot_count = 0;
if (DAI_INTEL_SSP_IS_BIT_SET(cfg->link_config, 15)) {
time_slot_map =
blob->i2s_driver_config.i2s_config.ssmidytsa[cfg->tdm_slot_group];
slot_count = POPCOUNT(time_slot_map >> 32) + POPCOUNT(time_slot_map & 0xFFFFFFFF);
pcmsycm = cfg->link_config | (slot_count - 1) << 4;
uint32_t reg_add = dai_ip_base(dp) + 0x1000 * ssp_index +
PCMSyCM_OFFSET(cfg->tdm_slot_group);
/* Program HDA output stream parameters */
sys_write16((pcmsycm & 0xffff), reg_add);
} else {
time_slot_map =
blob->i2s_driver_config.i2s_config.ssmodytsa[cfg->tdm_slot_group];
slot_count = POPCOUNT(time_slot_map >> 32) + POPCOUNT(time_slot_map & 0xFFFFFFFF);
pcmsycm = cfg->link_config | (slot_count - 1) << 4;
uint32_t reg_add = dai_ip_base(dp) + 0x1000 * ssp_index +
PCMSyCM_OFFSET(cfg->tdm_slot_group + I2SOPCMC);
/* Program HDA input stream parameters */
sys_write16((pcmsycm & 0xffff), reg_add);
}
#else
ARG_UNUSED(dp);
ARG_UNUSED(cfg);
ARG_UNUSED(ssp_index);
ARG_UNUSED(spec_config);
#endif /* CONFIG_SOC_INTEL_ACE20_LNL */
}
/* empty SSP transmit FIFO */
static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
{
int ret;
uint32_t sssr;
/*
* SSSR_TNF is cleared when TX FIFO is empty or full,
* so wait for set TNF then for TFL zero - order matter.
*/
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TNF, SSMODyCS_TNF,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
ret |= dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TFL, 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE *
(DAI_INTEL_SSP_FIFO_DEPTH - 1) / 2);
#else
ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSSR, SSSR_TNF, SSSR_TNF,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
ret |= dai_ssp_poll_for_register_delay(dai_base(dp) + SSCR3, SSCR3_TFL_MASK, 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE *
(DAI_INTEL_SSP_FIFO_DEPTH - 1) / 2);
#endif
if (ret) {
LOG_WRN("timeout");
}
sssr = sys_read32(dai_base(dp) + SSSR);
/* clear interrupt */
if (sssr & SSSR_TUR) {
sys_write32(sssr, dai_base(dp) + SSSR);
}
}
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
{
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
uint32_t i, sssr;
sssr = sys_read32(dai_base(dp) + SSSR);
if (sssr & SSSR_ROR) {
/* The RX FIFO is in overflow condition, empty it */
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
for (i = 0; i < DAI_INTEL_SSP_FIFO_DEPTH; i++)
sys_read32(dai_base(dp) + SSMIDyD(idx));
}
/* Clear the overflow status */
dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
/* Re-read the SSSR register */
sssr = sys_read32(dai_base(dp) + SSSR);
}
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
while ((sys_read32(dai_base(dp) + SSMIDyCS(idx)) & SSMIDyCS_RNE) && retry--) {
uint32_t entries = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) +
SSMIDyCS(idx)));
/* Empty the RX FIFO (the DMA is not running at this point) */
for (i = 0; i < entries + 1; i++)
sys_read32(dai_base(dp) + SSMIDyD(idx));
sssr = sys_read32(dai_base(dp) + SSSR);
}
}
}
static void ssp_empty_rx_fifo_on_stop(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
uint64_t sample_ticks = ssp_plat_data->params.fsync_rate ?
1000000 / ssp_plat_data->params.fsync_rate : 0;
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
uint32_t i, sssr, ssmidycs;
uint32_t entries[2];
sssr = sys_read32(dai_base(dp) + SSSR);
entries[0] = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) + SSMIDyCS(dp->tdm_slot_group)));
while ((sys_read32(dai_base(dp) + SSMIDyCS(dp->tdm_slot_group)) &
SSMIDyCS_RNE) && retry--) {
/* Wait one sample time */
k_busy_wait(sample_ticks);
entries[1] = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) +
SSMIDyCS(dp->tdm_slot_group)));
sssr = sys_read32(dai_base(dp) + SSSR);
ssmidycs = sys_read32(dai_base(dp) + SSMIDyCS(dp->tdm_slot_group));
if (entries[0] > entries[1]) {
/*
* The DMA is reading the FIFO, check the status in the
* next loop
*/
entries[0] = entries[1];
} else if (!(ssmidycs & SSMIDyCS_RFS)) {
/*
* The DMA request is not asserted, read the FIFO
* directly, otherwise let the next loop iteration to
* check the status
*/
for (i = 0; i < entries[1] + 1; i++)
sys_read32(dai_base(dp) + SSMIDyD(dp->tdm_slot_group));
}
sssr = sys_read32(dai_base(dp) + SSSR);
}
/* Just in case clear the overflow status */
dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
}
#else
static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
{
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
uint32_t i, sssr;
sssr = sys_read32(dai_base(dp) + SSSR);
if (sssr & SSSR_ROR) {
/* The RX FIFO is in overflow condition, empty it */
for (i = 0; i < DAI_INTEL_SSP_FIFO_DEPTH; i++)
sys_read32(dai_base(dp) + SSDR);
/* Clear the overflow status */
dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
/* Re-read the SSSR register */
sssr = sys_read32(dai_base(dp) + SSSR);
}
while ((sssr & SSSR_RNE) && retry--) {
uint32_t entries = SSCR3_RFL_VAL(sys_read32(dai_base(dp) + SSCR3));
/* Empty the RX FIFO (the DMA is not running at this point) */
for (i = 0; i < entries + 1; i++)
sys_read32(dai_base(dp) + SSDR);
sssr = sys_read32(dai_base(dp) + SSSR);
}
}
static void ssp_empty_rx_fifo_on_stop(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
uint64_t sample_ticks = ssp_plat_data->params.fsync_rate ?
1000000 / ssp_plat_data->params.fsync_rate : 0;
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
uint32_t entries[2];
uint32_t i, sssr;
sssr = sys_read32(dai_base(dp) + SSSR);
entries[0] = SSCR3_RFL_VAL(sys_read32(dai_base(dp) + SSCR3));
while ((sssr & SSSR_RNE) && retry--) {
/* Wait one sample time */
k_busy_wait(sample_ticks);
entries[1] = SSCR3_RFL_VAL(sys_read32(dai_base(dp) + SSCR3));
sssr = sys_read32(dai_base(dp) + SSSR);
if (entries[0] > entries[1]) {
/*
* The DMA is reading the FIFO, check the status in the
* next loop
*/
entries[0] = entries[1];
} else if (!(sssr & SSSR_RFS)) {
/*
* The DMA request is not asserted, read the FIFO
* directly, otherwise let the next loop iteration to
* check the status
*/
for (i = 0; i < entries[1] + 1; i++)
sys_read32(dai_base(dp) + SSDR);
}
sssr = sys_read32(dai_base(dp) + SSSR);
}
/* Just in case clear the overflow status */
dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
}
#endif
static int dai_ssp_mclk_prepare_enable(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
int ret;
if (ssp_plat_data->clk_active & SSP_CLK_MCLK_ACTIVE) {
return 0;
}
/* MCLK config */
ret = dai_ssp_mn_set_mclk(dp, ssp_plat_data->params.mclk_id,
ssp_plat_data->params.mclk_rate);
if (ret < 0) {
LOG_ERR("invalid mclk_rate = %d for mclk_id = %d", ssp_plat_data->params.mclk_rate,
ssp_plat_data->params.mclk_id);
} else {
ssp_plat_data->clk_active |= SSP_CLK_MCLK_ACTIVE;
}
return ret;
}
static void dai_ssp_mclk_disable_unprepare(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
if (!(ssp_plat_data->clk_active & SSP_CLK_MCLK_ACTIVE)) {
return;
}
dai_ssp_mn_release_mclk(dp, ssp_plat_data->params.mclk_id);
ssp_plat_data->clk_active &= ~SSP_CLK_MCLK_ACTIVE;
}
static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
{
#if !(CONFIG_INTEL_MN)
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
#endif
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
uint32_t sscr0;
uint32_t mdiv;
bool need_ecs = false;
int ret = 0;
if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) {
return 0;
}
sscr0 = sys_read32(dai_base(dp) + SSCR0);
#if CONFIG_INTEL_MN
/* BCLK config */
ret = dai_ssp_mn_set_bclk(dp, dp->dai_index, ssp_plat_data->params.bclk_rate,
&mdiv, &need_ecs);
if (ret < 0) {
LOG_ERR("invalid bclk_rate = %d for ssp_index = %d",
ssp_plat_data->params.bclk_rate, dp->dai_index);
goto out;
}
#else
if (ft[DAI_INTEL_SSP_DEFAULT_IDX].freq % ssp_plat_data->params.bclk_rate != 0) {
LOG_ERR("invalid bclk_rate = %d for ssp_index = %d",
ssp_plat_data->params.bclk_rate, dp->dai_index);
ret = -EINVAL;
goto out;
}
mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;
#endif
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
if (need_ecs) {
sscr0 |= SSCR0_ECS;
}
#endif
/* clock divisor is SCR + 1 */
mdiv -= 1;
/* divisor must be within SCR range */
if (mdiv > (SSCR0_SCR_MASK >> 8)) {
LOG_ERR("divisor %d is not within SCR range", mdiv);
ret = -EINVAL;
goto out;
}
/* set the SCR divisor */
sscr0 &= ~SSCR0_SCR_MASK;
sscr0 |= SSCR0_SCR(mdiv);
sys_write32(sscr0, dai_base(dp) + SSCR0);
LOG_INF("sscr0 = 0x%08x", sscr0);
out:
if (!ret) {
ssp_plat_data->clk_active |= SSP_CLK_BCLK_ACTIVE;
}
return ret;
}
static void dai_ssp_bclk_disable_unprepare(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE)) {
return;
}
#if CONFIG_INTEL_MN
dai_ssp_mn_release_bclk(dp, ssp_plat_data->ssp_index);
#endif
ssp_plat_data->clk_active &= ~SSP_CLK_BCLK_ACTIVE;
}
static void dai_ssp_log_ssp_data(struct dai_intel_ssp *dp)
{
LOG_INF("dai index: %u", dp->dai_index);
LOG_INF("plat_data base: %u", dp->ssp_plat_data->base);
LOG_INF("plat_data irq: %u", dp->ssp_plat_data->irq);
LOG_INF("plat_data fifo playback offset: %u",
dp->ssp_plat_data->fifo[DAI_DIR_PLAYBACK].offset);
LOG_INF("plat_data fifo playback handshake: %u",
dp->ssp_plat_data->fifo[DAI_DIR_PLAYBACK].handshake);
LOG_INF("plat_data fifo capture offset: %u",
dp->ssp_plat_data->fifo[DAI_DIR_CAPTURE].offset);
LOG_INF("plat_data fifo capture handshake: %u",
dp->ssp_plat_data->fifo[DAI_DIR_CAPTURE].handshake);
}
/* Digital Audio interface formatting */
static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_config *config,
const void *bespoke_cfg)
{
struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
uint32_t sscr0;
uint32_t sscr1;
uint32_t sscr2;
uint32_t sscr3;
uint32_t sspsp;
uint32_t sspsp2;
uint32_t sstsa;
uint32_t ssrsa;
uint32_t ssto;
uint32_t ssioc;
uint32_t bdiv;
uint32_t data_size;
uint32_t frame_end_padding;
uint32_t slot_end_padding;
uint32_t frame_len = 0;
uint32_t bdiv_min;
uint32_t tft;
uint32_t rft;
uint32_t active_tx_slots = 2;
uint32_t active_rx_slots = 2;
uint32_t sample_width = 2;
bool inverted_bclk = false;
bool inverted_frame = false;
bool cfs = false;
bool start_delay = false;
k_spinlock_key_t key;
int ret = 0;
dai_ssp_log_ssp_data(dp);
key = k_spin_lock(&dp->lock);
/* ignore config if SSP is already configured */
if (dp->state[DAI_DIR_PLAYBACK] > DAI_STATE_READY ||
dp->state[DAI_DIR_CAPTURE] > DAI_STATE_READY) {
if (!memcmp(&ssp_plat_data->params, bespoke_cfg,
sizeof(struct dai_intel_ipc3_ssp_params))) {
LOG_INF("Already configured. Ignore config");
goto clk;
}
if (ssp_plat_data->clk_active &
(SSP_CLK_MCLK_ACTIVE | SSP_CLK_BCLK_ACTIVE)) {
LOG_WRN("SSP active, cannot change config");
goto clk;
}
/* safe to proceed and change HW config */
}
LOG_INF("SSP%d", dp->dai_index);
/* reset SSP settings */
/* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
/*
* FIXME: MOD, ACS, NCS are not set,
* no support for network mode for now
*/
sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR, RSRE, TSRE */
sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL;
/* sscr2 dynamic setting is LJDFD */
sscr2 = SSCR2_SDFD | SSCR2_TURM1;
/* sscr3 dynamic settings are TFT, RFT */
sscr3 = 0;
/* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */
sspsp = 0;
ssp->config = *config;
memcpy(&ssp_plat_data->params, bespoke_cfg, sizeof(struct dai_intel_ipc3_ssp_params));
/* sspsp2 no dynamic setting */
sspsp2 = 0x0;
/* ssioc dynamic setting is SFCR */
ssioc = SSIOC_SCOE;
/* ssto no dynamic setting */
ssto = 0x0;
/* sstsa dynamic setting is TTSA, default 2 slots */
sstsa = SSTSA_SSTSA(ssp_plat_data->params.tx_slots);
/* ssrsa dynamic setting is RTSA, default 2 slots */
ssrsa = SSRSA_SSRSA(ssp_plat_data->params.rx_slots);
switch (config->format & DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK) {
case DAI_INTEL_IPC3_SSP_FMT_CBP_CFP:
sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
break;
case DAI_INTEL_IPC3_SSP_FMT_CBC_CFC:
sscr1 |= SSCR1_SCFR;
cfs = true;
break;
case DAI_INTEL_IPC3_SSP_FMT_CBP_CFC:
sscr1 |= SSCR1_SCLKDIR;
/* FIXME: this mode has not been tested */
cfs = true;
break;
case DAI_INTEL_IPC3_SSP_FMT_CBC_CFP:
sscr1 |= SSCR1_SCFR | SSCR1_SFRMDIR;
/* FIXME: this mode has not been tested */
break;
default:
LOG_ERR("format & PROVIDER_MASK EINVAL");
ret = -EINVAL;
goto out;
}
/* clock signal polarity */
switch (config->format & DAI_INTEL_IPC3_SSP_FMT_INV_MASK) {
case DAI_INTEL_IPC3_SSP_FMT_NB_NF:
break;
case DAI_INTEL_IPC3_SSP_FMT_NB_IF:
inverted_frame = true; /* handled later with format */
break;
case DAI_INTEL_IPC3_SSP_FMT_IB_IF:
inverted_bclk = true; /* handled later with bclk idle */
inverted_frame = true; /* handled later with format */
break;
case DAI_INTEL_IPC3_SSP_FMT_IB_NF:
inverted_bclk = true; /* handled later with bclk idle */
break;
default:
LOG_ERR("format & INV_MASK EINVAL");
ret = -EINVAL;
goto out;
}
/* supporting bclk idle state */
if (ssp_plat_data->params.clks_control & DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_IDLE_HIGH) {
/* bclk idle state high */
sspsp |= SSPSP_SCMODE((inverted_bclk ^ 0x3) & 0x3);
} else {
/* bclk idle state low */
sspsp |= SSPSP_SCMODE(inverted_bclk);
}
sscr0 |= SSCR0_MOD | SSCR0_ACS;
/* Additional hardware settings */
/* Receiver Time-out Interrupt Disabled/Enabled */
sscr1 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_TINTE) ?
SSCR1_TINTE : 0;
/* Peripheral Trailing Byte Interrupts Disable/Enable */
sscr1 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_PINTE) ?
SSCR1_PINTE : 0;
/* Enable/disable internal loopback. Output of transmit serial
* shifter connected to input of receive serial shifter, internally.
*/
sscr1 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_LBM) ?
SSCR1_LBM : 0;
if (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_LBM) {
LOG_INF("going for loopback!");
} else {
LOG_INF("no loopback!");
}
/* Transmit data are driven at the same/opposite clock edge specified
* in SSPSP.SCMODE[1:0]
*/
sscr2 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_SMTATF) ?
SSCR2_SMTATF : 0;
/* Receive data are sampled at the same/opposite clock edge specified
* in SSPSP.SCMODE[1:0]
*/
sscr2 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_MMRATF) ?
SSCR2_MMRATF : 0;
/* Enable/disable the fix for PSP consumer mode TXD wait for frame
* de-assertion before starting the second channel
*/
sscr2 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_PSPSTWFDFD) ?
SSCR2_PSPSTWFDFD : 0;
/* Enable/disable the fix for PSP provider mode FSRT with dummy stop &
* frame end padding capability
*/
sscr2 |= (ssp_plat_data->params.quirks & DAI_INTEL_IPC3_SSP_QUIRK_PSPSRWFDFD) ?
SSCR2_PSPSRWFDFD : 0;
if (!ssp_plat_data->params.mclk_rate ||
ssp_plat_data->params.mclk_rate > ft[DAI_INTEL_SSP_MAX_FREQ_INDEX].freq) {
LOG_ERR("invalid MCLK = %d Hz (valid < %d)", ssp_plat_data->params.mclk_rate,
ft[DAI_INTEL_SSP_MAX_FREQ_INDEX].freq);
ret = -EINVAL;
goto out;
}
if (!ssp_plat_data->params.bclk_rate ||
ssp_plat_data->params.bclk_rate > ssp_plat_data->params.mclk_rate) {
LOG_ERR("BCLK %d Hz = 0 or > MCLK %d Hz", ssp_plat_data->params.bclk_rate,
ssp_plat_data->params.mclk_rate);
ret = -EINVAL;
goto out;
}
/* calc frame width based on BCLK and rate - must be divisible */
if (ssp_plat_data->params.bclk_rate % ssp_plat_data->params.fsync_rate) {
LOG_ERR("BCLK %d is not divisible by rate %d", ssp_plat_data->params.bclk_rate,
ssp_plat_data->params.fsync_rate);
ret = -EINVAL;
goto out;
}
/* must be enough BCLKs for data */
bdiv = ssp_plat_data->params.bclk_rate / ssp_plat_data->params.fsync_rate;
if (bdiv < ssp_plat_data->params.tdm_slot_width * ssp_plat_data->params.tdm_slots) {
LOG_ERR("not enough BCLKs need %d",
ssp_plat_data->params.tdm_slot_width * ssp_plat_data->params.tdm_slots);
ret = -EINVAL;
goto out;
}
/* tdm_slot_width must be <= 38 for SSP */
if (ssp_plat_data->params.tdm_slot_width > 38) {
LOG_ERR("tdm_slot_width %d > 38", ssp_plat_data->params.tdm_slot_width);
ret = -EINVAL;
goto out;
}
bdiv_min = ssp_plat_data->params.tdm_slots *
(ssp_plat_data->params.tdm_per_slot_padding_flag ?
ssp_plat_data->params.tdm_slot_width : ssp_plat_data->params.sample_valid_bits);
if (bdiv < bdiv_min) {
LOG_ERR("bdiv(%d) < bdiv_min(%d)", bdiv, bdiv_min);
ret = -EINVAL;
goto out;
}
frame_end_padding = bdiv - bdiv_min;
if (frame_end_padding > SSPSP2_FEP_MASK) {
LOG_ERR("frame_end_padding too big: %u", frame_end_padding);
ret = -EINVAL;
goto out;
}
/* format */
switch (config->format & DAI_INTEL_IPC3_SSP_FMT_FORMAT_MASK) {
case DAI_INTEL_IPC3_SSP_FMT_I2S:
start_delay = true;
sscr0 |= SSCR0_FRDC(ssp_plat_data->params.tdm_slots);
if (bdiv % 2) {
LOG_ERR("bdiv %d is not divisible by 2", bdiv);
ret = -EINVAL;
goto out;
}
/* set asserted frame length to half frame length */
frame_len = bdiv / 2;
/*
* handle frame polarity, I2S default is falling/active low,
* non-inverted(inverted_frame=0) -- active low(SFRMP=0),
* inverted(inverted_frame=1) -- rising/active high(SFRMP=1),
* so, we should set SFRMP to inverted_frame.
*/
sspsp |= SSPSP_SFRMP(inverted_frame);
/*
* for I2S/LEFT_J, the padding has to happen at the end
* of each slot
*/
if (frame_end_padding % 2) {
LOG_ERR("frame_end_padding %d is not divisible by 2", frame_end_padding);
ret = -EINVAL;
goto out;
}
slot_end_padding = frame_end_padding / 2;
if (slot_end_padding > DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX) {
/* too big padding */
LOG_ERR("slot_end_padding > %d", DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX);
ret = -EINVAL;
goto out;
}
sspsp |= SSPSP_DMYSTOP(slot_end_padding);
slot_end_padding >>= SSPSP_DMYSTOP_BITS;
sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
break;
case DAI_INTEL_IPC3_SSP_FMT_LEFT_J:
/* default start_delay value is set to false */
sscr0 |= SSCR0_FRDC(ssp_plat_data->params.tdm_slots);
/* LJDFD enable */
sscr2 &= ~SSCR2_LJDFD;
if (bdiv % 2) {
LOG_ERR("bdiv %d is not divisible by 2", bdiv);
ret = -EINVAL;
goto out;
}
/* set asserted frame length to half frame length */
frame_len = bdiv / 2;
/*
* handle frame polarity, LEFT_J default is rising/active high,
* non-inverted(inverted_frame=0) -- active high(SFRMP=1),
* inverted(inverted_frame=1) -- falling/active low(SFRMP=0),
* so, we should set SFRMP to !inverted_frame.
*/
sspsp |= SSPSP_SFRMP(!inverted_frame);
/*
* for I2S/LEFT_J, the padding has to happen at the end
* of each slot
*/
if (frame_end_padding % 2) {
LOG_ERR("frame_end_padding %d is not divisible by 2", frame_end_padding);
ret = -EINVAL;
goto out;
}
slot_end_padding = frame_end_padding / 2;
if (slot_end_padding > 15) {
/* can't handle padding over 15 bits */
LOG_ERR("slot_end_padding %d > 15 bits", slot_end_padding);
ret = -EINVAL;
goto out;
}
sspsp |= SSPSP_DMYSTOP(slot_end_padding);
slot_end_padding >>= SSPSP_DMYSTOP_BITS;
sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
break;
case DAI_INTEL_IPC3_SSP_FMT_DSP_A:
start_delay = true;
/* fallthrough */
case DAI_INTEL_IPC3_SSP_FMT_DSP_B:
/* default start_delay value is set to false */
sscr0 |= SSCR0_MOD | SSCR0_FRDC(ssp_plat_data->params.tdm_slots);
/* set asserted frame length */
frame_len = 1; /* default */
if (cfs && ssp_plat_data->params.frame_pulse_width > 0 &&
ssp_plat_data->params.frame_pulse_width <=
DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX) {
frame_len = ssp_plat_data->params.frame_pulse_width;
}
/* frame_pulse_width must less or equal 38 */
if (ssp_plat_data->params.frame_pulse_width >
DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX) {
LOG_ERR("frame_pulse_width > %d", DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX);
ret = -EINVAL;
goto out;
}
/*
* handle frame polarity, DSP_B default is rising/active high,
* non-inverted(inverted_frame=0) -- active high(SFRMP=1),
* inverted(inverted_frame=1) -- falling/active low(SFRMP=0),
* so, we should set SFRMP to !inverted_frame.
*/
sspsp |= SSPSP_SFRMP(!inverted_frame);
active_tx_slots = POPCOUNT(ssp_plat_data->params.tx_slots);
active_rx_slots = POPCOUNT(ssp_plat_data->params.rx_slots);
/*
* handle TDM mode, TDM mode has padding at the end of
* each slot. The amount of padding is equal to result of
* subtracting slot width and valid bits per slot.
*/
if (ssp_plat_data->params.tdm_per_slot_padding_flag) {
frame_end_padding = bdiv - ssp_plat_data->params.tdm_slots *
ssp_plat_data->params.tdm_slot_width;
slot_end_padding = ssp_plat_data->params.tdm_slot_width -
ssp_plat_data->params.sample_valid_bits;
if (slot_end_padding >
DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX) {
LOG_ERR("slot_end_padding > %d",
DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX);
ret = -EINVAL;
goto out;
}
sspsp |= SSPSP_DMYSTOP(slot_end_padding);
slot_end_padding >>= SSPSP_DMYSTOP_BITS;
sspsp |= SSPSP_EDMYSTOP(slot_end_padding);
}
sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK);
break;
default:
LOG_ERR("invalid format 0x%04x", config->format);
ret = -EINVAL;
goto out;
}
if (start_delay) {
sspsp |= SSPSP_FSRT;
}
sspsp |= SSPSP_SFRMWDTH(frame_len);
data_size = ssp_plat_data->params.sample_valid_bits;
if (data_size > 16) {
sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16));
} else {
sscr0 |= SSCR0_DSIZE(data_size);
}
/* setting TFT and RFT */
switch (ssp_plat_data->params.sample_valid_bits) {
case 16:
/* use 2 bytes for each slot */
sample_width = 2;
break;
case 24:
case 32:
/* use 4 bytes for each slot */
sample_width = 4;
break;
default:
LOG_ERR("sample_valid_bits %d", ssp_plat_data->params.sample_valid_bits);
ret = -EINVAL;
goto out;
}
tft = MIN(DAI_INTEL_SSP_FIFO_DEPTH - DAI_INTEL_SSP_FIFO_WATERMARK,
sample_width * active_tx_slots);
rft = MIN(DAI_INTEL_SSP_FIFO_DEPTH - DAI_INTEL_SSP_FIFO_WATERMARK,
sample_width * active_rx_slots);
sscr3 |= SSCR3_TX(tft) | SSCR3_RX(rft);
sys_write32(sscr0, dai_base(dp) + SSCR0);
sys_write32(sscr1, dai_base(dp) + SSCR1);
sys_write32(sscr2, dai_base(dp) + SSCR2);
sys_write32(sscr3, dai_base(dp) + SSCR3);
sys_write32(sspsp, dai_base(dp) + SSPSP);
sys_write32(sspsp2, dai_base(dp) + SSPSP2);
sys_write32(ssioc, dai_base(dp) + SSIOC);
sys_write32(ssto, dai_base(dp) + SSTO);
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
sys_write64(sstsa, dai_base(dp) + SSMODyTSA(idx));
}
for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) {
sys_write64(ssrsa, dai_base(dp) + SSMIDyTSA(idx));
}
#else
sys_write32(sstsa, dai_base(dp) + SSTSA);
sys_write32(ssrsa, dai_base(dp) + SSRSA);
#endif
LOG_INF("sscr0 = 0x%08x, sscr1 = 0x%08x, ssto = 0x%08x, sspsp = 0x%0x",
sscr0, sscr1, ssto, sspsp);
LOG_INF("sscr2 = 0x%08x, sspsp2 = 0x%08x, sscr3 = 0x%08x, ssioc = 0x%08x",
sscr2, sspsp2, sscr3, ssioc);
LOG_INF("ssrsa = 0x%08x, sstsa = 0x%08x",
ssrsa, sstsa);
dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
clk:
switch (config->options & DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_CMD_MASK) {
case DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS:
if (ssp_plat_data->params.clks_control & DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_ES) {
ret = dai_ssp_mclk_prepare_enable(dp);
if (ret < 0) {
goto out;
}
ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;
LOG_INF("hw_params stage: enabled MCLK clocks for SSP%d...",
dp->dai_index);
}
if (ssp_plat_data->params.clks_control & DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_ES) {
bool enable_sse = false;
if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE)) {
enable_sse = true;
}
ret = dai_ssp_bclk_prepare_enable(dp);
if (ret < 0) {
goto out;
}
ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ;
if (enable_sse) {
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
SSMIDyCS_RSRE, SSMIDyCS_RSRE);
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TSRE, SSMODyCS_TSRE);
#endif
/* enable port */
dai_ssp_update_bits(dp, SSCR0, SSCR0_SSE, SSCR0_SSE);
LOG_INF("SSE set for SSP%d", ssp_plat_data->ssp_index);
}
LOG_INF("hw_params stage: enabled BCLK clocks for SSP%d...",
ssp_plat_data->ssp_index);
}
break;
case DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_FREE:
/* disable SSP port if no users */
if (dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING ||
dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) {
LOG_INF("hw_free stage: ignore since SSP%d still in use",
dp->dai_index);
break;
}
if (ssp_plat_data->params.clks_control & DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_ES) {
LOG_INF("hw_free stage: releasing BCLK clocks for SSP%d...",
dp->dai_index);
if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) {
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) {
dai_ssp_update_bits(dp, SSMODyCS(idx), SSMODyCS_TSRE, 0);
}
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
dai_ssp_update_bits(dp, SSMIDyCS(idx), SSMIDyCS_RSRE, 0);
}
#endif
dai_ssp_update_bits(dp, SSCR0, SSCR0_SSE, 0);
LOG_INF("SSE clear for SSP%d", dp->dai_index);
}
dai_ssp_bclk_disable_unprepare(dp);
ssp_plat_data->clk_active &= ~SSP_CLK_BCLK_ES_REQ;
}
if (ssp_plat_data->params.clks_control & DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_ES) {
LOG_INF("hw_free stage: releasing MCLK clocks for SSP%d...",
dp->dai_index);
dai_ssp_mclk_disable_unprepare(dp);
ssp_plat_data->clk_active &= ~SSP_CLK_MCLK_ES_REQ;
}
break;
default:
break;
}
out:
k_spin_unlock(&dp->lock, key);
return ret;
}
static int dai_ssp_check_aux_data(struct ssp_intel_aux_tlv *aux_tlv, int aux_len, int parsed_len)
{
struct ssp_intel_sync_ctl *sync;
int size, size_left;
switch (aux_tlv->type) {
case SSP_MN_DIVIDER_CONTROLS:
size = sizeof(struct ssp_intel_mn_ctl);
break;
case SSP_DMA_CLK_CONTROLS:
size = sizeof(struct ssp_intel_clk_ctl);
break;
case SSP_DMA_TRANSMISSION_START:
case SSP_DMA_TRANSMISSION_STOP:
size = sizeof(struct ssp_intel_tr_ctl);
case SSP_DMA_ALWAYS_RUNNING_MODE:
size = sizeof(struct ssp_intel_run_ctl);
break;
case SSP_DMA_SYNC_DATA:
size = sizeof(struct ssp_intel_sync_ctl);
sync = (struct ssp_intel_sync_ctl *)&aux_tlv->val;
size += sync->count * sizeof(struct ssp_intel_node_ctl);
break;
case SSP_DMA_CLK_CONTROLS_EXT:
size = sizeof(struct ssp_intel_ext_ctl);
break;
case SSP_LINK_CLK_SOURCE:
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
size = sizeof(struct ssp_intel_link_ctl);
break;
#else
return 0;
#endif
default:
LOG_ERR("undefined aux data type %u", aux_tlv->type);
return -EINVAL;
}
/* check for malformed struct, size greater than aux_data or described in tlv */
size_left = aux_len - parsed_len - sizeof(struct ssp_intel_aux_tlv);
if (size > size_left || size != aux_tlv->size) {
LOG_ERR("malformed struct, size %d, size_left %d, tlv_size %d", size,
size_left, aux_tlv->size);
return -EINVAL;
}
return 0;
}
/**
* This function checks if the provided buffer contains valid DMA control
* TLV (Type-Length-Value) entries. It ensures that only specific types
* of DMA control settings are allowed to be modified at runtime.
*/
static int dai_ssp_check_dma_control(const uint8_t *aux_ptr, int aux_len)
{
int hop;
struct ssp_intel_aux_tlv *aux_tlv;
for (int i = 0; i < aux_len; i += hop) {
aux_tlv = (struct ssp_intel_aux_tlv *)(aux_ptr);
switch (aux_tlv->type) {
case SSP_DMA_CLK_CONTROLS:
case SSP_DMA_TRANSMISSION_START:
case SSP_DMA_TRANSMISSION_STOP:
case SSP_DMA_ALWAYS_RUNNING_MODE:
case SSP_DMA_SYNC_DATA:
case SSP_DMA_CLK_CONTROLS_EXT:
case SSP_LINK_CLK_SOURCE:
break;
default:
LOG_ERR("incorect config type %u", aux_tlv->type);
return -EINVAL;
}
hop = aux_tlv->size + sizeof(struct ssp_intel_aux_tlv);
aux_ptr += hop;
}
return 0;
}
static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, size_t aux_len)
{
int hop, i, j;
struct ssp_intel_aux_tlv *aux_tlv;
struct ssp_intel_mn_ctl *mn;
struct ssp_intel_clk_ctl *clk;
struct ssp_intel_tr_ctl *tr;
struct ssp_intel_run_ctl *run;
struct ssp_intel_node_ctl *node;
struct ssp_intel_sync_ctl *sync;
struct ssp_intel_ext_ctl *ext;
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
struct ssp_intel_link_ctl *link;
#endif
for (i = 0; i < aux_len; i += hop) {
aux_tlv = (struct ssp_intel_aux_tlv *)(aux_ptr);
if (dai_ssp_check_aux_data(aux_tlv, aux_len, i)) {
return -EINVAL;
}
switch (aux_tlv->type) {
case SSP_MN_DIVIDER_CONTROLS:
mn = (struct ssp_intel_mn_ctl *)&aux_tlv->val;
LOG_INF("mn div_m %u, div_n %u", mn->div_m, mn->div_n);
break;
case SSP_DMA_CLK_CONTROLS:
clk = (struct ssp_intel_clk_ctl *)&aux_tlv->val;
LOG_INF("clk start %u, stop %u", clk->start, clk->stop);
break;
case SSP_DMA_TRANSMISSION_START:
case SSP_DMA_TRANSMISSION_STOP:
tr = (struct ssp_intel_tr_ctl *)&aux_tlv->val;
LOG_INF("tr sampling frequency %u, bit_depth %u, channel_map %u,",
tr->sampling_frequency, tr->bit_depth, tr->channel_map);
LOG_INF("channel_config %u, interleaving_style %u, format %u",
tr->channel_config, tr->interleaving_style, tr->format);
break;
case SSP_DMA_ALWAYS_RUNNING_MODE:
run = (struct ssp_intel_run_ctl *)&aux_tlv->val;
LOG_INF("run enabled %u", run->enabled);
break;
case SSP_DMA_SYNC_DATA:
sync = (struct ssp_intel_sync_ctl *)&aux_tlv->val;
LOG_INF("sync sync_denominator %u, count %u",
sync->sync_denominator, sync->count);
node = (struct ssp_intel_node_ctl *)((uint8_t *)sync +
sizeof(struct ssp_intel_sync_ctl));
for (j = 0; j < sync->count; j++) {
LOG_INF("node node_id %u, sampling_rate %u",
node->node_id, node->sampling_rate);
node++;
}
break;
case SSP_DMA_CLK_CONTROLS_EXT:
ext = (struct ssp_intel_ext_ctl *)&aux_tlv->val;
LOG_INF("ext ext_data %u", ext->ext_data);
break;
case SSP_LINK_CLK_SOURCE:
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
#if CONFIG_SOC_INTEL_ACE15_MTPM
sys_write32((sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) &
~I2CLCTL_MLCS(0x7)) |
I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
I2SLCTL_OFFSET);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
~I2CLCTL_MLCS(0x7)) |
I2CLCTL_MLCS(link->clock_source),
dai_i2svss_base(dp) + I2SLCTL_OFFSET);
#endif
LOG_INF("link clock_source %u", link->clock_source);
#endif
break;
default:
LOG_ERR("undefined aux data type %u", aux_tlv->type);
return -EINVAL;
}
hop = aux_tlv->size + sizeof(struct ssp_intel_aux_tlv);
aux_ptr += hop;
}
return 0;
}
static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_config)
{
const struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 *blob = spec_config;
int cfg_len, pre_aux_len, aux_len;
uint8_t *aux_ptr;
cfg_len = blob->size;
pre_aux_len = sizeof(*blob) + blob->i2s_mclk_control.mdivrcnt * sizeof(uint32_t);
aux_len = cfg_len - pre_aux_len;
aux_ptr = (uint8_t *)blob + pre_aux_len;
if (aux_len <= 0) {
return 0;
}
return dai_ssp_parse_tlv(dp, aux_ptr, aux_len);
}
static int dai_ssp_set_clock_control_ver_1_5(struct dai_intel_ssp *dp,
const struct dai_intel_ipc4_ssp_mclk_config_2 *cc)
{
/* currently we only support 1 divider */
if (cc->mdivrcnt != 1) {
LOG_ERR("bad clock divider count %u", cc->mdivrcnt);
return -EINVAL;
}
/* ssp blob is set by pcm_hw_params for ipc4 stream, so enable
* mclk and bclk at this time.
*/
dai_ssp_mn_set_mclk_blob(dp, cc->mdivctlr, cc->mdivr[0]);
return 0;
}
static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp,
const struct dai_intel_ipc4_ssp_mclk_config *cc)
{
/* ssp blob is set by pcm_hw_params for ipc4 stream, so enable
* mclk and bclk at this time.
*/
dai_ssp_mn_set_mclk_blob(dp, cc->mdivc, cc->mdivr);
return 0;
}
static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg,
const struct dai_intel_ipc4_ssp_config *regs)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
uint32_t sscr1 = 0;
uint32_t sstsa = 0;
uint32_t ssrsa = 0;
uint32_t ssc0 = regs->ssc0;
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
sscr1 = regs->ssc1 & ~(SSCR1_RSVD21);
#else
sscr1 = regs->ssc1 & ~(SSCR1_RSRE | SSCR1_TSRE);
sstsa = SSTSA_GET(regs->sstsa);
ssrsa = SSRSA_GET(regs->ssrsa);
#endif
LOG_INF("SSP%d configuration:", dp->dai_index);
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
if (regs->sstsa & SSTSA_TXEN || regs->ssrsa & SSRSA_RXEN ||
regs->ssc1 & (SSCR1_RSRE | SSCR1_TSRE)) {
LOG_INF(" Ignoring %s%s%s%sfrom blob",
regs->sstsa & SSTSA_TXEN ? "SSTSA:TXEN " : "",
regs->ssrsa & SSRSA_RXEN ? "SSRSA:RXEN " : "",
regs->ssc1 & SSCR1_TSRE ? "SSCR1:TSRE " : "",
regs->ssc1 & SSCR1_RSRE ? "SSCR1:RSRE " : "");
}
#endif
sys_write32(ssc0, dai_base(dp) + SSCR0);
sys_write32(regs->ssc2 & ~SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */
sys_write32(sscr1, dai_base(dp) + SSCR1);
sys_write32(regs->ssc2 | SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */
sys_write32(regs->ssc2, dai_base(dp) + SSCR2);
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
sys_write32(regs->ssc3, dai_base(dp) + SSCR3);
#endif
sys_write32(regs->sspsp, dai_base(dp) + SSPSP);
sys_write32(regs->sspsp2, dai_base(dp) + SSPSP2);
sys_write32(regs->ssioc, dai_base(dp) + SSIOC);
sys_write32(regs->sscto, dai_base(dp) + SSTO);
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
sys_write64(regs->ssmidytsa[idx], dai_base(dp) + SSMIDyTSA(idx));
}
for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) {
sys_write64(regs->ssmodytsa[idx], dai_base(dp) + SSMODyTSA(idx));
}
#else
sys_write32(sstsa, dai_base(dp) + SSTSA);
sys_write32(ssrsa, dai_base(dp) + SSRSA);
#endif
LOG_INF(" sscr0 = 0x%08x, sscr1 = 0x%08x, ssto = 0x%08x, sspsp = 0x%0x",
ssc0, sscr1, regs->sscto, regs->sspsp);
LOG_INF(" sscr2 = 0x%08x, sspsp2 = 0x%08x, sscr3 = 0x%08x",
regs->ssc2, regs->sspsp2, regs->ssc3);
LOG_INF(" ssioc = 0x%08x, ssrsa = 0x%08x, sstsa = 0x%08x",
regs->ssioc, ssrsa, sstsa);
ssp_plat_data->params.sample_valid_bits = SSCR0_DSIZE_GET(ssc0);
if (ssc0 & SSCR0_EDSS) {
ssp_plat_data->params.sample_valid_bits += 16;
}
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
ssp_plat_data->params.tx_slots = regs->ssmodytsa[dp->tdm_slot_group];
ssp_plat_data->params.rx_slots = regs->ssmidytsa[dp->tdm_slot_group];
#else
ssp_plat_data->params.tdm_slots = SSCR0_FRDC_GET(ssc0);
ssp_plat_data->params.tx_slots = SSTSA_GET(sstsa);
ssp_plat_data->params.rx_slots = SSRSA_GET(ssrsa);
#endif
ssp_plat_data->params.fsync_rate = cfg->rate;
dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
}
static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_config *cfg,
const void *spec_config)
{
const struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 *blob15 = spec_config;
const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
int err;
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
dp->tdm_slot_group = cfg->tdm_slot_group;
#endif
/* set config only once for playback or capture */
if (ssp_plat_data->is_initialized) {
dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
return 0;
}
if (blob15->version == SSP_BLOB_VER_1_5) {
err = dai_ssp_parse_aux_data(dp, spec_config);
if (err) {
return err;
}
dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
if (err) {
return err;
}
} else {
dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
if (err) {
return err;
}
}
ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;
/* enable port */
dai_ssp_update_bits(dp, SSCR0, SSCR0_SSE, SSCR0_SSE);
ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ;
ssp_plat_data->is_initialized = true;
return 0;
}
/*
* Portion of the SSP configuration should be applied just before the
* SSP dai is activated, for either power saving or params runtime
* configurable flexibility.
*/
static int dai_ssp_pre_start(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
int ret = 0;
/*
* We will test if mclk/bclk is configured in
* ssp_mclk/bclk_prepare_enable/disable functions
*/
if (!(ssp_plat_data->clk_active & SSP_CLK_MCLK_ES_REQ)) {
/* MCLK config */
ret = dai_ssp_mclk_prepare_enable(dp);
if (ret < 0) {
return ret;
}
}
if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ES_REQ)) {
ret = dai_ssp_bclk_prepare_enable(dp);
}
return ret;
}
/*
* For power saving, we should do kinds of power release when the SSP
* dai is changed to inactive, though the runtime param configuration
* don't have to be reset.
*/
static void dai_ssp_post_stop(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
/* release clocks if SSP is inactive */
if (dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_RUNNING &&
dp->state[DAI_DIR_CAPTURE] != DAI_STATE_RUNNING) {
if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ES_REQ)) {
LOG_INF("releasing BCLK clocks for SSP%d...", dp->dai_index);
dai_ssp_bclk_disable_unprepare(dp);
}
if (!(ssp_plat_data->clk_active & SSP_CLK_MCLK_ES_REQ)) {
LOG_INF("releasing MCLK clocks for SSP%d...", dp->dai_index);
dai_ssp_mclk_disable_unprepare(dp);
}
}
}
static void dai_ssp_early_start(struct dai_intel_ssp *dp, int direction)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
k_spinlock_key_t key;
key = k_spin_lock(&dp->lock);
/* RX fifo must be cleared before start */
if (direction == DAI_DIR_CAPTURE) {
LOG_INF("SSP%d RX", dp->dai_index);
ssp_empty_rx_fifo_on_start(dp);
} else {
LOG_INF("SSP%d TX", dp->dai_index);
}
/* request mclk/bclk */
dai_ssp_pre_start(dp);
if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ES_REQ)) {
/* enable port */
LOG_INF("SSP%d: set SSE", dp->dai_index);
dai_ssp_update_bits(dp, SSCR0, SSCR0_SSE, SSCR0_SSE);
}
k_spin_unlock(&dp->lock, key);
}
/* start the SSP for either playback or capture */
static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
{
struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
k_spinlock_key_t key;
key = k_spin_lock(&dp->lock);
/* enable DMA */
#if CONFIG_SOC_INTEL_ACE30_PTL
if (direction == DAI_DIR_PLAYBACK) {
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TSRE, SSMODyCS_TSRE);
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
SSMODyCS_TXEN, SSMODyCS_TXEN);
} else {
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
SSMIDyCS_RSRE, SSMIDyCS_RSRE);
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
SSMIDyCS_RXEN, SSMIDyCS_RXEN);
}
#else
if (direction == DAI_DIR_PLAYBACK) {
LOG_INF("SSP%d TX", dp->dai_index);
dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
dai_ssp_update_bits(dp, SSTSA, SSTSA_TXEN, SSTSA_TXEN);
} else {
LOG_INF("SSP%d RX", dp->dai_index);
dai_ssp_update_bits(dp, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
dai_ssp_update_bits(dp, SSRSA, SSRSA_RXEN, SSRSA_RXEN);
}
#endif
dp->state[direction] = DAI_STATE_RUNNING;
/*
* Wait to get valid fifo status in clock consumer mode. TODO it's
* uncertain which SSP clock consumer modes need the delay atm, but
* these can be added here when confirmed.
*/
switch (ssp->config.format & DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK) {
case DAI_INTEL_IPC3_SSP_FMT_CBC_CFC:
break;
default:
/* delay for all SSP consumed clocks atm - see above */
/* ssp_wait_delay(PLATFORM_SSP_DELAY); */
k_busy_wait(DAI_INTEL_SSP_PLATFORM_DELAY_US);
break;
}
k_spin_unlock(&dp->lock, key);
}
/* stop the SSP for either playback or capture */
static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
{
struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
k_spinlock_key_t key;
key = k_spin_lock(&dp->lock);
/*
* Wait to get valid fifo status in clock consumer mode. TODO it's
* uncertain which SSP clock consumer modes need the delay atm, but
* these can be added here when confirmed.
*/
switch (ssp->config.format & DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK) {
case DAI_INTEL_IPC3_SSP_FMT_CBC_CFC:
break;
default:
/* delay for all SSP consumed clocks atm - see above */
k_busy_wait(DAI_INTEL_SSP_PLATFORM_DELAY_US);
break;
}
/* stop Rx if neeed */
if (direction == DAI_DIR_CAPTURE &&
dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) {
LOG_INF("SSP%d RX", dp->dai_index);
#if CONFIG_SOC_INTEL_ACE30_PTL
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RXEN, 0);
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, 0);
#else
dai_ssp_update_bits(dp, SSRSA, SSRSA_RXEN, 0);
dai_ssp_update_bits(dp, SSCR1, SSCR1_RSRE, 0);
#endif
ssp_empty_rx_fifo_on_stop(dp);
dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
}
/* stop Tx if needed */
if (direction == DAI_DIR_PLAYBACK &&
dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) {
LOG_INF("SSP%d TX", dp->dai_index);
#if CONFIG_SOC_INTEL_ACE30_PTL
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, 0);
dai_ssp_empty_tx_fifo(dp);
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TXEN, 0);
#else
dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, 0);
dai_ssp_empty_tx_fifo(dp);
dai_ssp_update_bits(dp, SSTSA, SSTSA_TXEN, 0);
#endif
dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
}
k_spin_unlock(&dp->lock, key);
}
static void dai_ssp_pause(struct dai_intel_ssp *dp, int direction)
{
if (direction == DAI_DIR_CAPTURE) {
LOG_INF("SSP%d RX", dp->dai_index);
} else {
LOG_INF("SSP%d TX", dp->dai_index);
}
dp->state[direction] = DAI_STATE_PAUSED;
}
static int dai_ssp_trigger(const struct device *dev, enum dai_dir dir,
enum dai_trigger_cmd cmd)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
int array_index = SSP_ARRAY_INDEX(dir);
LOG_DBG("SSP%d: cmd %d", dp->dai_index, cmd);
switch (cmd) {
case DAI_TRIGGER_START:
if (dp->state[array_index] == DAI_STATE_PAUSED ||
dp->state[array_index] == DAI_STATE_PRE_RUNNING) {
dai_ssp_start(dp, array_index);
}
break;
case DAI_TRIGGER_STOP:
dai_ssp_stop(dp, array_index);
break;
case DAI_TRIGGER_PAUSE:
dai_ssp_pause(dp, array_index);
break;
case DAI_TRIGGER_PRE_START:
dai_ssp_early_start(dp, array_index);
break;
default:
break;
}
return 0;
}
static int dai_ssp_config_get(const struct device *dev, struct dai_config *cfg, enum dai_dir dir)
{
struct dai_config *params = (struct dai_config *)dev->config;
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
if (!cfg) {
return -EINVAL;
}
if (!ssp) {
*cfg = *params;
return 0;
}
params->rate = ssp_plat_data->params.fsync_rate;
if (dir == DAI_DIR_PLAYBACK) {
params->channels = POPCOUNT(ssp_plat_data->params.tx_slots);
} else {
params->channels = POPCOUNT(ssp_plat_data->params.rx_slots);
}
params->word_size = ssp_plat_data->params.sample_valid_bits;
*cfg = *params;
return 0;
}
static int dai_ssp_config_set(const struct device *dev, const struct dai_config *cfg,
const void *bespoke_cfg)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
int ret;
if (cfg->type == DAI_INTEL_SSP) {
ret = dai_ssp_set_config_tplg(dp, cfg, bespoke_cfg);
} else {
ret = dai_ssp_set_config_blob(dp, cfg, bespoke_cfg);
}
dai_ssp_program_channel_map(dp, cfg, ssp_plat_data->ssp_index, bespoke_cfg);
return ret;
}
static const struct dai_properties *dai_ssp_get_properties(const struct device *dev,
enum dai_dir dir, int stream_id)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
struct dai_properties *prop = &ssp->props;
int array_index = SSP_ARRAY_INDEX(dir);
prop->fifo_address = ssp_plat_data->fifo[array_index].offset;
prop->dma_hs_id = ssp_plat_data->fifo[array_index].handshake;
if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) {
prop->reg_init_delay = 0;
} else {
prop->reg_init_delay = ssp_plat_data->params.bclk_delay;
}
LOG_INF("SSP%u: fifo %u, handshake %u, init delay %u", dp->dai_index, prop->fifo_address,
prop->dma_hs_id, prop->reg_init_delay);
return prop;
}
static void ssp_acquire_ip(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp = dai_get_plat_data(dp);
ssp->acquire_count++;
if (ssp->acquire_count == 1) {
/* Enable SSP power */
dai_ssp_pm_runtime_en_ssp_power(dp, ssp->ssp_index);
/* Disable dynamic clock gating before touching any register */
dai_ssp_pm_runtime_dis_ssp_clk_gating(dp, ssp->ssp_index);
}
}
static void ssp_release_ip(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp = dai_get_plat_data(dp);
if (ssp->acquire_count == 0) {
return;
}
--ssp->acquire_count;
if (ssp->acquire_count == 0) {
/* disable SSP port if no users */
if (dp->state[DAI_DIR_CAPTURE] == DAI_STATE_PRE_RUNNING &&
dp->state[DAI_DIR_PLAYBACK] == DAI_STATE_PRE_RUNNING &&
COND_CODE_1(CONFIG_INTEL_ADSP_CAVS,
(!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)), (true))) {
dai_ssp_update_bits(dp, SSCR0, SSCR0_SSE, 0);
LOG_INF("%s SSE clear SSP%d", __func__, ssp->ssp_index);
}
dai_ssp_post_stop(dp);
dai_ssp_pm_runtime_en_ssp_clk_gating(dp, ssp->ssp_index);
dai_ssp_mclk_disable_unprepare(dp);
dai_ssp_bclk_disable_unprepare(dp);
/* Disable SSP power */
dai_ssp_pm_runtime_dis_ssp_power(dp, ssp->ssp_index);
ssp->is_initialized = false;
}
}
static int dai_ssp_probe(struct dai_intel_ssp *dp)
{
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
struct dai_intel_ssp_pdata *ssp;
if (dai_get_drvdata(dp)) {
return -EEXIST; /* already created */
}
/* allocate private data */
ssp = k_calloc(1, sizeof(*ssp));
if (!ssp) {
LOG_ERR("SSP%d: alloc failed", ssp_plat_data->ssp_index);
return -ENOMEM;
}
dai_set_drvdata(dp, ssp);
dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_READY;
dp->state[DAI_DIR_CAPTURE] = DAI_STATE_READY;
#if CONFIG_INTEL_MN
/* Reset M/N, power-gating functions need it */
dai_ssp_mn_reset_bclk_divider(dp, ssp_plat_data->ssp_index);
#endif
ssp_acquire_ip(dp);
return 0;
}
static int dai_ssp_remove(struct dai_intel_ssp *dp)
{
ssp_release_ip(dp);
k_free(dai_get_drvdata(dp));
dai_set_drvdata(dp, NULL);
return 0;
}
static int ssp_pm_action(const struct device *dev, enum pm_device_action action)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
dai_ssp_remove(dp);
break;
case PM_DEVICE_ACTION_RESUME:
dai_ssp_probe(dp);
break;
case PM_DEVICE_ACTION_TURN_OFF:
case PM_DEVICE_ACTION_TURN_ON:
/* All device pm is handled during resume and suspend */
break;
default:
return -ENOTSUP;
}
return 0;
}
static int dai_intel_ssp_init_device(const struct device *dev)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
dp->ssp_plat_data = ssp_get_device_instance(dp->ssp_index);
return 0;
};
static int ssp_init(const struct device *dev)
{
dai_intel_ssp_init_device(dev);
if (pm_device_on_power_domain(dev)) {
pm_device_init_off(dev);
} else {
pm_device_init_suspended(dev);
}
return pm_device_runtime_enable(dev);
}
static int dai_ssp_dma_control_set(const struct device *dev,
const void *bespoke_cfg,
size_t size)
{
struct dai_intel_ssp *dp = (struct dai_intel_ssp *)dev->data;
LOG_INF("SSP%d: tlv addr = 0x%x, tlv size = %d",
dp->dai_index, (uint32_t)bespoke_cfg, size);
if (size < sizeof(struct ssp_intel_aux_tlv)) {
return -EINVAL;
}
if (dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_READY ||
dp->state[DAI_DIR_CAPTURE] != DAI_STATE_READY) {
return -EIO;
}
if (dai_ssp_check_dma_control(bespoke_cfg, size)) {
return -EINVAL;
}
return dai_ssp_parse_tlv(dp, bespoke_cfg, size);
}
static struct dai_driver_api dai_intel_ssp_api_funcs = {
.probe = pm_device_runtime_get,
.remove = pm_device_runtime_put,
.config_set = dai_ssp_config_set,
.config_get = dai_ssp_config_get,
.trigger = dai_ssp_trigger,
.get_properties = dai_ssp_get_properties,
.config_update = dai_ssp_dma_control_set,
};
#define DT_DRV_COMPAT intel_ssp_dai
#define DAI_INTEL_SSP_DEVICE_INIT(n) \
static struct dai_config dai_intel_ssp_config_##n = { \
.type = DAI_INTEL_SSP, \
.dai_index = DT_INST_REG_ADDR(n), \
}; \
static struct dai_intel_ssp dai_intel_ssp_data_##n = { \
.dai_index = DT_INST_REG_ADDR(n), \
.ssp_index = DT_PROP(DT_INST_PARENT(n), ssp_index), \
.tdm_slot_group = 0, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(n, ssp_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, \
ssp_init, PM_DEVICE_DT_INST_GET(n), \
&dai_intel_ssp_data_##n, \
&dai_intel_ssp_config_##n, \
POST_KERNEL, 42, \
&dai_intel_ssp_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(DAI_INTEL_SSP_DEVICE_INIT)
``` | /content/code_sandbox/drivers/dai/intel/ssp/ssp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24,749 |
```objective-c
/*
*
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_H__
#define __INTEL_DAI_DRIVER_DMIC_H__
#include <zephyr/sys/util_macro.h>
/* The microphones create a low frequecy thump sound when clock is enabled.
* The unmute linear gain ramp chacteristic is defined here.
* NOTE: Do not set any of these to 0.
*/
#define DMIC_UNMUTE_RAMP_US 1000 /* 1 ms (in microseconds) */
#define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */
#define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */
/* Parameters used in modes computation */
#define DMIC_HW_BITS_CIC 26
#define DMIC_HW_BITS_FIR_COEF 20
#define DMIC_HW_BITS_FIR_GAIN 20
#define DMIC_HW_BITS_FIR_INPUT 22
#define DMIC_HW_BITS_FIR_OUTPUT 24
#define DMIC_HW_BITS_FIR_INTERNAL 26
#define DMIC_HW_BITS_GAIN_OUTPUT 22
#define DMIC_HW_FIR_LENGTH_MAX 250
#define DMIC_HW_CIC_SHIFT_MIN -8
#define DMIC_HW_CIC_SHIFT_MAX 4
#define DMIC_HW_FIR_SHIFT_MIN 0
#define DMIC_HW_FIR_SHIFT_MAX 8
#define DMIC_HW_CIC_DECIM_MIN 5
#define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
#define DMIC_HW_FIR_DECIM_MIN 2
#define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
#define DMIC_HW_SENS_Q28 Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
#define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
/* DC offset compensation time constants */
#define DCCOMP_TC0 0
#define DCCOMP_TC1 1
#define DCCOMP_TC2 2
#define DCCOMP_TC3 3
#define DCCOMP_TC4 4
#define DCCOMP_TC5 5
#define DCCOMP_TC6 6
#define DCCOMP_TC7 7
/* Used for scaling FIR coefficients for HW */
#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
/* Internal precision in gains computation, e.g. Q4.28 in int32_t */
#define DMIC_FIR_SCALE_Q 28
/* Used in unmute ramp values calculation */
#define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
#define DB2LIN_FIXED_INPUT_QY 24
#define DB2LIN_FIXED_OUTPUT_QY 20
/* Hardcoded log ramp parameters. The default ramp is 100 ms for 48 kHz
* and 200 ms for 16 kHz. The first parameter is the initial gain in
* decibels, set to -90 dB.
* The rate dependent ramp duration is provided by 1st order equation
* duration = coef * samplerate + offset.
* E.g. 100 ms @ 48 kHz, 200 ms @ 16 kHz
* y48 = 100; y16 = 200;
* dy = y48 - y16; dx = 48000 - 16000;
* coef = round(dy/dx * 2^15)
* offs = round(y16 - coef/2^15 * 16000)
* Note: The rate dependence can be disabled with zero time_coef with
* use of just the offset.
*/
#define LOGRAMP_START_DB Q_CONVERT_FLOAT(-90, DB2LIN_FIXED_INPUT_QY)
#define LOGRAMP_TIME_COEF_Q15 -102 /* coef = dy/dx */
#define LOGRAMP_TIME_OFFS_Q0 250 /* offs = Offset for line slope in ms */
/* Limits for ramp time from topology */
#define LOGRAMP_TIME_MIN_MS 10 /* Min. 10 ms */
#define LOGRAMP_TIME_MAX_MS 1000 /* Max. 1s */
/* Simplify log ramp step calculation equation with this constant term */
#define LOGRAMP_CONST_TERM ((int32_t) \
((int64_t)-LOGRAMP_START_DB * DMIC_UNMUTE_RAMP_US / 1000))
/* Fractional shift for gain update. Gain format is Q2.30. */
#define Q_SHIFT_GAIN_X_GAIN_COEF \
(Q_SHIFT_BITS_32(30, DB2LIN_FIXED_OUTPUT_QY, 30))
/* Compute the number of shifts
* This will result in a compiler overflow error if shift bits are out of
* range as INT64_MAX/MIN is greater than 32 bit Q shift parameter
*/
#define Q_SHIFT_BITS_64(qx, qy, qz) \
((qx + qy - qz) <= 63 ? (((qx + qy - qz) >= 0) ? \
(qx + qy - qz) : INT64_MIN) : INT64_MAX)
#define Q_SHIFT_BITS_32(qx, qy, qz) \
((qx + qy - qz) <= 31 ? (((qx + qy - qz) >= 0) ? \
(qx + qy - qz) : INT32_MIN) : INT32_MAX)
/* Fractional multiplication with shift and round
* Note that the parameters px and py must be cast to (int64_t) if other type.
*/
#define Q_MULTSR_32X32(px, py, qx, qy, qp) \
((((px) * (py) >> ((qx)+(qy)-(qp)-1)) + 1) >> 1)
/* A more clever macro for Q-shifts */
#define Q_SHIFT(x, src_q, dst_q) ((x) >> ((src_q) - (dst_q)))
#define Q_SHIFT_RND(x, src_q, dst_q) \
((((x) >> ((src_q) - (dst_q) - 1)) + 1) >> 1)
/* Alternative version since compiler does not allow (x >> -1) */
#define Q_SHIFT_LEFT(x, src_q, dst_q) ((x) << ((dst_q) - (src_q)))
/* Convert a float number to fractional Qnx.ny format. Note that there is no
* check for nx+ny number of bits to fit the word length of int. The parameter
* qy must be 31 or less.
*/
#define Q_CONVERT_FLOAT(f, qy) \
((int32_t)(((const double)f) * ((int64_t)1 << (const int)qy) + 0.5))
#define TWO_Q27 Q_CONVERT_FLOAT(2.0, 27) /* Use Q5.27 */
#define MINUS_TWO_Q27 Q_CONVERT_FLOAT(-2.0, 27) /* Use Q5.27 */
#define ONE_Q20 Q_CONVERT_FLOAT(1.0, 20) /* Use Q12.20 */
#define ONE_Q23 Q_CONVERT_FLOAT(1.0, 23) /* Use Q9.23 */
#define LOG10_DIV20_Q27 Q_CONVERT_FLOAT(0.1151292546, 27) /* Use Q5.27 */
#define DMA_HANDSHAKE_DMIC_CH0 0
#define DMA_HANDSHAKE_DMIC_CH1 1
enum dai_dmic_frame_format {
DAI_DMIC_FRAME_S16_LE = 0,
DAI_DMIC_FRAME_S24_4LE,
DAI_DMIC_FRAME_S32_LE,
DAI_DMIC_FRAME_FLOAT,
/* other formats here */
DAI_DMIC_FRAME_S24_3LE,
};
/* Common data for all DMIC DAI instances */
struct dai_dmic_global_shared {
uint32_t active_fifos_mask; /* Bits (dai->index) are set to indicate active FIFO */
uint32_t pause_mask; /* Bits (dai->index) are set to indicate driver pause */
};
struct dai_dmic_plat_fifo_data {
uint32_t offset;
uint32_t width;
uint32_t depth;
uint32_t watermark;
uint32_t handshake;
};
struct dai_intel_dmic {
struct dai_config dai_config_params;
struct k_spinlock lock; /**< locking mechanism */
int sref; /**< simple ref counter, guarded by lock */
enum dai_state state; /* Driver component state */
uint16_t enable[CONFIG_DAI_DMIC_HW_CONTROLLERS];/* Mic 0 and 1 enable bits array for PDMx */
struct dai_dmic_plat_fifo_data fifo; /* dmic capture fifo stream */
int32_t gain_coef; /* Gain update constant */
int32_t gain; /* Gain value to be applied to HW */
int32_t startcount; /* Counter that controls HW unmute */
int32_t unmute_time_ms; /* Unmute ramp time in milliseconds */
/* hardware parameters */
uint32_t reg_base;
uint32_t shim_base;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
uint32_t hdamldmic_base;
uint32_t vshim_base;
#endif
int irq;
uint32_t flags;
uint32_t gain_left;
uint32_t gain_right;
};
static inline int32_t sat_int32(int64_t x)
{
if (x > INT32_MAX)
return INT32_MAX;
else if (x < INT32_MIN)
return INT32_MIN;
else
return (int32_t)x;
}
/* Fractional multiplication with shift and saturation */
static inline int32_t q_multsr_sat_32x32(int32_t x, int32_t y,
const int shift_bits)
{
return sat_int32(((((int64_t)x * y) >> (shift_bits - 1)) + 1) >> 1);
}
static inline int dmic_get_unmute_ramp_from_samplerate(int rate)
{
int time_ms;
time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
LOGRAMP_TIME_OFFS_Q0;
if (time_ms > LOGRAMP_TIME_MAX_MS) {
return LOGRAMP_TIME_MAX_MS;
}
if (time_ms < LOGRAMP_TIME_MIN_MS) {
return LOGRAMP_TIME_MIN_MS;
}
return time_ms;
}
#endif /* __INTEL_DAI_DRIVER_DMIC_H__ */
``` | /content/code_sandbox/drivers/dai/intel/dmic/dmic.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,320 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_dai_dmic
#define LOG_DOMAIN dai_intel_dmic
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <errno.h>
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/kernel.h>
#include <zephyr/spinlock.h>
#include <zephyr/devicetree.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/drivers/dai.h>
#include <zephyr/irq.h>
#include "dmic.h"
#include <dmic_regs.h>
/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
static const uint32_t dmic_base[4] = {PDM0, PDM1, PDM2, PDM3};
/* global data shared between all dmic instances */
struct dai_dmic_global_shared dai_dmic_global;
/* Helper macro to read 64-bit data using two 32-bit data read */
#define sys_read64(addr) (((uint64_t)(sys_read32(addr + 4)) << 32) | \
sys_read32(addr))
int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *spec_config);
/* Exponent function for small values of x. This function calculates
* fairly accurately exponent for x in range -2.0 .. +2.0. The iteration
* uses first 11 terms of Taylor series approximation for exponent
* function. With the current scaling the numerator just remains under
* 64 bits with the 11 terms.
*
* See path_to_url#Computation
*
* The input is Q3.29
* The output is Q9.23
*/
static int32_t exp_small_fixed(int32_t x)
{
int64_t p;
int64_t num = Q_SHIFT_RND(x, 29, 23);
int32_t y = (int32_t)num;
int32_t den = 1;
int32_t inc;
int k;
/* Numerator is x^k, denominator is k! */
for (k = 2; k < 12; k++) {
p = num * x; /* Q9.23 x Q3.29 -> Q12.52 */
num = Q_SHIFT_RND(p, 52, 23);
den = den * k;
inc = (int32_t)(num / den);
y += inc;
}
return y + ONE_Q23;
}
static int32_t exp_fixed(int32_t x)
{
int32_t xs;
int32_t y;
int32_t z;
int i;
int n = 0;
if (x < Q_CONVERT_FLOAT(-11.5, 27)) {
return 0;
}
if (x > Q_CONVERT_FLOAT(7.6245, 27)) {
return INT32_MAX;
}
/* x is Q5.27 */
xs = x;
while (xs >= TWO_Q27 || xs <= MINUS_TWO_Q27) {
xs >>= 1;
n++;
}
/* exp_small_fixed() input is Q3.29, while x1 is Q5.27
* exp_small_fixed() output is Q9.23, while z is Q12.20
*/
z = Q_SHIFT_RND(exp_small_fixed(Q_SHIFT_LEFT(xs, 27, 29)), 23, 20);
y = ONE_Q20;
for (i = 0; i < (1 << n); i++) {
y = (int32_t)Q_MULTSR_32X32((int64_t)y, z, 20, 20, 20);
}
return y;
}
static int32_t db2lin_fixed(int32_t db)
{
int32_t arg;
if (db < Q_CONVERT_FLOAT(-100.0, 24)) {
return 0;
}
/* Q8.24 x Q5.27, result needs to be Q5.27 */
arg = (int32_t)Q_MULTSR_32X32((int64_t)db, LOG10_DIV20_Q27, 24, 27, 27);
return exp_fixed(arg);
}
static void dai_dmic_update_bits(const struct dai_intel_dmic *dmic,
uint32_t reg, uint32_t mask, uint32_t val)
{
uint32_t dest = dmic->reg_base + reg;
sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest);
}
static inline void dai_dmic_write(const struct dai_intel_dmic *dmic,
uint32_t reg, uint32_t val)
{
sys_write32(val, dmic->reg_base + reg);
}
static inline uint32_t dai_dmic_read(const struct dai_intel_dmic *dmic,
uint32_t reg)
{
return sys_read32(dmic->reg_base + reg);
}
#if CONFIG_DAI_DMIC_HAS_OWNERSHIP
static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic)
{
/* DMIC Owner Select to DSP */
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) |
FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET);
}
static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
{
/* DMIC Owner Select back to Host CPU + DSP */
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) &
~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET);
}
#else /* CONFIG_DAI_DMIC_HAS_OWNERSHIP */
static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic) {}
static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) {}
#endif /* CONFIG_DAI_DMIC_HAS_OWNERSHIP */
static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
return dmic->hdamldmic_base;
#else
return dmic->shim_base;
#endif
}
#if CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC
static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic)
{
uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
uint32_t base = dai_dmic_base(dmic);
/* DMIC Change sync period */
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
base + DMICSYNC_OFFSET);
if (!WAIT_FOR((sys_read32(base + DMICSYNC_OFFSET) & DMICSYNC_SYNCPU) == 0, 1000,
k_sleep(K_USEC(100)))) {
LOG_ERR("poll timeout");
}
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET);
#else /* All other CAVS and ACE platforms */
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET);
#endif
}
static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic)
{
uint32_t base = dai_dmic_base(dmic);
/* DMIC Clean sync period */
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD,
base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET);
}
/* Preparing for command synchronization on multiple link segments */
static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic)
{
uint32_t base = dai_dmic_base(dmic);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET);
}
/* Trigering synchronization of command execution */
static void dmic_sync_trigger(const struct dai_intel_dmic *dmic)
{
uint32_t base = dai_dmic_base(dmic);
__ASSERT_NO_MSG((sys_read32(base + DMICSYNC_OFFSET) & DMICSYNC_CMDSYNC) != 0);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) |
DMICSYNC_SYNCGO, base + DMICSYNC_OFFSET);
/* waiting for CMDSYNC bit clearing */
if (!WAIT_FOR((sys_read32(base + DMICSYNC_OFFSET) & DMICSYNC_CMDSYNC) == 0,
1000, k_sleep(K_USEC(100)))) {
LOG_ERR("poll timeout");
}
}
#else /* CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC */
static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_intel_dmic *dmic) {}
static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic) {}
static inline void dai_dmic_sync_prepare(const struct dai_intel_dmic *dmic) {}
static void dmic_sync_trigger(const struct dai_intel_dmic *dmic) {}
#endif /* CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC */
static void dai_dmic_start_fifo_packers(struct dai_intel_dmic *dmic, int fifo_index)
{
/* Start FIFO packers and clear FIFO initialize bits */
dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,
OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL_SIP);
}
static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
int fifo_index)
{
/* Stop FIFO packers and set FIFO initialize bits */
dai_dmic_update_bits(dmic, fifo_index * PDM_CHANNEL_REGS_SIZE + OUTCONTROL,
OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL_FINIT);
}
/* On DMIC IRQ event trace the status register that contains the status and
* error bit fields.
*/
static void dai_dmic_irq_handler(const void *data)
{
struct dai_intel_dmic *dmic = ((struct device *)data)->data;
uint32_t val0;
uint32_t val1;
/* Trace OUTSTAT0 register */
val0 = dai_dmic_read(dmic, OUTSTAT);
val1 = dai_dmic_read(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE);
LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1);
if (val0 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun");
dai_dmic_write(dmic, OUTSTAT, val0);
dai_dmic_stop_fifo_packers(dmic, 0);
}
if (val1 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun");
dai_dmic_write(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE, val1);
dai_dmic_stop_fifo_packers(dmic, 1);
}
}
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Disable DMIC clock gating */
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{
/* Enable DMIC clock gating */
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLVSCTL_OFFSET);
#else /* All other CAVS and ACE platforms */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmic,
const struct dai_config *cfg,
uint32_t index)
{
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
uint16_t pcmsycm = cfg->link_config;
uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
sys_write16(pcmsycm, reg_add);
#else
ARG_UNUSED(dmic);
ARG_UNUSED(cfg);
ARG_UNUSED(index);
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */
}
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
{
uint32_t base = dai_dmic_base(dmic);
/* Enable DMIC power */
sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
base + DMICLCTL_OFFSET);
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
k_sleep(K_USEC(100));
}
#endif
}
static inline void dai_dmic_dis_power(const struct dai_intel_dmic *dmic)
{
uint32_t base = dai_dmic_base(dmic);
/* Disable DMIC power */
sys_write32((sys_read32(base + DMICLCTL_OFFSET) & (~DMICLCTL_SPA)),
base + DMICLCTL_OFFSET);
}
static int dai_dmic_probe(struct dai_intel_dmic *dmic)
{
LOG_INF("dmic_probe()");
/* Set state, note there is no playback direction support */
dmic->state = DAI_STATE_NOT_READY;
/* Enable DMIC power */
dai_dmic_en_power(dmic);
/* Disable dynamic clock gating for dmic before touching any reg */
dai_dmic_dis_clk_gating(dmic);
/* DMIC Change sync period */
dai_dmic_set_sync_period(CONFIG_DAI_DMIC_PLATFORM_SYNC_PERIOD, dmic);
/* DMIC Owner Select to DSP */
dai_dmic_claim_ownership(dmic);
irq_enable(dmic->irq);
return 0;
}
static int dai_dmic_remove(struct dai_intel_dmic *dmic)
{
uint32_t active_fifos_mask = dai_dmic_global.active_fifos_mask;
uint32_t pause_mask = dai_dmic_global.pause_mask;
LOG_INF("dmic_remove()");
irq_disable(dmic->irq);
LOG_INF("dmic_remove(), dmic_active_fifos_mask = 0x%x, dmic_pause_mask = 0x%x",
active_fifos_mask, pause_mask);
/* The next end tasks must be passed if another DAI FIFO still runs.
* Note: dai_put() function that calls remove() applies the spinlock
* so it is not needed here to protect access to mask bits.
*/
if (active_fifos_mask || pause_mask) {
return 0;
}
/* Disable DMIC clock and power */
dai_dmic_en_clk_gating(dmic);
dai_dmic_dis_power(dmic);
/* DMIC Clean sync period */
dai_dmic_clear_sync_period(dmic);
/* DMIC Owner Select back to Host CPU + DSP */
dai_dmic_release_ownership(dmic);
return 0;
}
static int dai_dmic_timestamp_config(const struct device *dev, struct dai_ts_cfg *cfg)
{
cfg->walclk_rate = CONFIG_DAI_DMIC_HW_IOCLK;
return 0;
}
static int dai_timestamp_dmic_start(const struct device *dev, struct dai_ts_cfg *cfg)
{
uint32_t addr = TS_DMIC_LOCAL_TSCTRL;
uint32_t cdmas;
/* Set DMIC timestamp registers */
/* First point CDMAS to GPDMA channel that is used by DMIC
* also clear NTK to be sure there is no old timestamp.
*/
cdmas = FIELD_PREP(TS_LOCAL_TSCTRL_CDMAS, cfg->dma_chan_index +
cfg->dma_chan_count * cfg->dma_id);
sys_write32(TS_LOCAL_TSCTRL_NTK | cdmas, addr);
/* Request on demand timestamp */
sys_write32(TS_LOCAL_TSCTRL_ODTS | cdmas, addr);
return 0;
}
static int dai_timestamp_dmic_stop(const struct device *dev, struct dai_ts_cfg *cfg)
{
/* Clear NTK and write zero to CDMAS */
sys_write32(TS_LOCAL_TSCTRL_NTK, TS_DMIC_LOCAL_TSCTRL);
return 0;
}
static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *cfg,
struct dai_ts_data *tsd)
{
/* Read DMIC timestamp registers */
uint32_t tsctrl = TS_DMIC_LOCAL_TSCTRL;
uint32_t ntk;
/* Read SSP timestamp registers */
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
if (!ntk) {
goto out;
}
/* NTK was set, get wall clock */
tsd->walclk = sys_read64(TS_DMIC_LOCAL_WALCLK);
/* Sample */
tsd->sample = sys_read64(TS_DMIC_LOCAL_SAMPLE);
/* Clear NTK to enable successive timestamps */
sys_write32(TS_LOCAL_TSCTRL_NTK, tsctrl);
out:
tsd->walclk_rate = cfg->walclk_rate;
if (!ntk) {
return -ENODATA;
}
return 0;
}
/* this ramps volume changes over time */
static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
{
k_spinlock_key_t key;
int32_t gval;
uint32_t val;
int i;
/* Currently there's no DMIC HW internal mutings and wait times
* applied into this start sequence. It can be implemented here if
* start of audio capture would contain clicks and/or noise and it
* is not suppressed by gain ramp somewhere in the capture pipe.
*/
LOG_DBG("DMIC gain ramp");
/*
* At run-time dmic->gain is only changed in this function, and this
* function runs in the pipeline task context, so it cannot run
* concurrently on multiple cores, since there's always only one
* task associated with each DAI, so we don't need to hold the lock to
* read the value here.
*/
if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {
return;
}
key = k_spin_lock(&dmic->lock);
/* Increment gain with logarithmic step.
* Gain is Q2.30 and gain modifier is Q12.20.
*/
dmic->startcount++;
dmic->gain = q_multsr_sat_32x32(dmic->gain, dmic->gain_coef, Q_SHIFT_GAIN_X_GAIN_COEF);
/* Gain is stored as Q2.30, while HW register is Q1.19 so shift
* the value right by 11.
*/
gval = dmic->gain >> 11;
/* Note that DMIC gain value zero has a special purpose. Value zero
* sets gain bypass mode in HW. Zero value will be applied after ramp
* is complete. It is because exact 1.0 gain is not possible with Q1.19.
*/
if (gval > DMIC_HW_FIR_GAIN_MAX) {
gval = 0;
dmic->gain = DMIC_HW_FIR_GAIN_MAX << 11;
}
/* Write gain to registers */
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
if (!dmic->enable[i])
continue;
if (dmic->startcount == DMIC_UNMUTE_CIC)
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_MIC_MUTE, 0);
if (dmic->startcount == DMIC_UNMUTE_FIR) {
dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + FIR_CONTROL,
FIR_CONTROL_MUTE, 0);
}
if (gval != 0) {
val = FIELD_PREP(OUT_GAIN, gval);
dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, val);
dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, val);
} else {
dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + OUT_GAIN_LEFT,
dmic->gain_left);
dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT,
dmic->gain_right);
}
}
k_spin_unlock(&dmic->lock, key);
}
static void dai_dmic_start(struct dai_intel_dmic *dmic)
{
k_spinlock_key_t key;
int i;
int mic_a;
int mic_b;
int start_fir;
/* enable port */
key = k_spin_lock(&dmic->lock);
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++)
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0);
#endif
dmic->startcount = 0;
/* Compute unmute ramp gain update coefficient. */
dmic->gain_coef = db2lin_fixed(LOGRAMP_CONST_TERM / dmic->unmute_time_ms);
/* Initial gain value, convert Q12.20 to Q2.30 */
dmic->gain = Q_SHIFT_LEFT(db2lin_fixed(LOGRAMP_START_DB), 20, 30);
dai_dmic_sync_prepare(dmic);
dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index);
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
mic_a = dmic->enable[i] & 1;
mic_b = (dmic->enable[i] & 2) >> 1;
start_fir = dmic->enable[i] > 0;
/* If both microphones are needed start them simultaneously
* to start them in sync. The reset may be cleared for another
* FIFO already. If only one mic, start them independently.
* This makes sure we do not clear start/en for another DAI.
*/
if (mic_a && mic_b) {
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_A |
CIC_CONTROL_CIC_START_B,
FIELD_PREP(CIC_CONTROL_CIC_START_A, 1) |
FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_A |
MIC_CONTROL_PDM_EN_B,
FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1) |
FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
} else if (mic_a) {
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_A,
FIELD_PREP(CIC_CONTROL_CIC_START_A, 1));
dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_A,
FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1));
} else if (mic_b) {
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_B,
FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_B,
FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
}
dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + FIR_CONTROL,
FIR_CONTROL_START,
FIELD_PREP(FIR_CONTROL_START, start_fir));
}
#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
/* Clear soft reset for all/used PDM controllers. This should
* start capture in sync.
*/
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_SOFT_RESET, 0);
LOG_INF("dmic_start(), cic 0x%08x",
dai_dmic_read(dmic, dmic_base[i] + CIC_CONTROL));
}
#endif
/* Set bit dai->index */
dai_dmic_global.active_fifos_mask |= BIT(dmic->dai_config_params.dai_index);
dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);
dmic->state = DAI_STATE_RUNNING;
k_spin_unlock(&dmic->lock, key);
dmic_sync_trigger(dmic);
LOG_INF("dmic_start(), dmic_active_fifos_mask = 0x%x",
dai_dmic_global.active_fifos_mask);
}
static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
{
k_spinlock_key_t key;
int i;
LOG_DBG("dmic_stop()");
key = k_spin_lock(&dmic->lock);
dai_dmic_stop_fifo_packers(dmic, dmic->dai_config_params.dai_index);
/* Set soft reset and mute on for all PDM controllers. */
LOG_INF("dmic_stop(), dmic_active_fifos_mask = 0x%x",
dai_dmic_global.active_fifos_mask);
/* Clear bit dmic->dai_config_params.dai_index for active FIFO.
* If stop for pause, set pause mask bit.
* If stop is not for pausing, it is safe to clear the pause bit.
*/
dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);
if (stop_is_pause) {
dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);
} else {
dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);
}
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
/* Don't stop CIC yet if one FIFO remains active */
if (dai_dmic_global.active_fifos_mask == 0) {
dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
CIC_CONTROL_SOFT_RESET |
CIC_CONTROL_MIC_MUTE,
CIC_CONTROL_SOFT_RESET |
CIC_CONTROL_MIC_MUTE);
}
dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
dmic->dai_config_params.dai_index + FIR_CONTROL,
FIR_CONTROL_MUTE,
FIR_CONTROL_MUTE);
}
k_spin_unlock(&dmic->lock, key);
}
const struct dai_properties *dai_dmic_get_properties(const struct device *dev,
enum dai_dir dir,
int stream_id)
{
const struct dai_intel_dmic *dmic = (const struct dai_intel_dmic *)dev->data;
struct dai_properties *prop = (struct dai_properties *)dev->config;
prop->fifo_address = dmic->fifo.offset;
prop->fifo_depth = dmic->fifo.depth;
prop->dma_hs_id = dmic->fifo.handshake;
prop->reg_init_delay = 0;
return prop;
}
static int dai_dmic_trigger(const struct device *dev, enum dai_dir dir,
enum dai_trigger_cmd cmd)
{
struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;
LOG_DBG("dmic_trigger()");
if (dir != DAI_DIR_RX) {
LOG_ERR("dmic_trigger(): direction != DAI_DIR_RX");
return -EINVAL;
}
switch (cmd) {
case DAI_TRIGGER_START:
if (dmic->state == DAI_STATE_PAUSED ||
dmic->state == DAI_STATE_PRE_RUNNING) {
dai_dmic_start(dmic);
dmic->state = DAI_STATE_RUNNING;
} else {
LOG_ERR("dmic_trigger(): state is not prepare or paused, dmic->state = %u",
dmic->state);
}
break;
case DAI_TRIGGER_STOP:
dai_dmic_stop(dmic, false);
dmic->state = DAI_STATE_PRE_RUNNING;
break;
case DAI_TRIGGER_PAUSE:
dai_dmic_stop(dmic, true);
dmic->state = DAI_STATE_PAUSED;
break;
case DAI_TRIGGER_COPY:
dai_dmic_gain_ramp(dmic);
break;
default:
break;
}
return 0;
}
static int dai_dmic_get_config(const struct device *dev, struct dai_config *cfg, enum dai_dir dir)
{
struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;
if (dir != DAI_DIR_RX) {
return -EINVAL;
}
if (!cfg) {
return -EINVAL;
}
*cfg = dmic->dai_config_params;
return 0;
}
static int dai_dmic_set_config(const struct device *dev,
const struct dai_config *cfg, const void *bespoke_cfg)
{
struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;
int ret = 0;
int di = dmic->dai_config_params.dai_index;
k_spinlock_key_t key;
LOG_INF("dmic_set_config()");
if (di >= CONFIG_DAI_DMIC_HW_FIFOS) {
LOG_ERR("dmic_set_config(): DAI index exceeds number of FIFOs");
return -EINVAL;
}
if (!bespoke_cfg) {
LOG_ERR("dmic_set_config(): NULL config");
return -EINVAL;
}
dai_dmic_program_channel_map(dmic, cfg, di);
key = k_spin_lock(&dmic->lock);
#if CONFIG_DAI_INTEL_DMIC_TPLG_PARAMS
#error DMIC TPLG is not yet implemented
#elif CONFIG_DAI_INTEL_DMIC_NHLT
ret = dai_dmic_set_config_nhlt(dmic, bespoke_cfg);
/* There's no unmute ramp duration in blob, so the default rate dependent is used. */
dmic->unmute_time_ms = dmic_get_unmute_ramp_from_samplerate(dmic->dai_config_params.rate);
#else
#error No DMIC config selected
#endif
if (ret < 0) {
LOG_ERR("dmic_set_config(): Failed to set the requested configuration.");
goto out;
}
dmic->state = DAI_STATE_PRE_RUNNING;
out:
k_spin_unlock(&dmic->lock, key);
return ret;
}
static int dai_dmic_probe_wrapper(const struct device *dev)
{
struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;
k_spinlock_key_t key;
int ret = 0;
key = k_spin_lock(&dmic->lock);
if (dmic->sref == 0) {
ret = dai_dmic_probe(dmic);
}
if (!ret) {
dmic->sref++;
}
k_spin_unlock(&dmic->lock, key);
return ret;
}
static int dai_dmic_remove_wrapper(const struct device *dev)
{
struct dai_intel_dmic *dmic = (struct dai_intel_dmic *)dev->data;
k_spinlock_key_t key;
int ret = 0;
key = k_spin_lock(&dmic->lock);
if (--dmic->sref == 0) {
ret = dai_dmic_remove(dmic);
}
k_spin_unlock(&dmic->lock, key);
return ret;
}
static int dmic_pm_action(const struct device *dev, enum pm_device_action action)
{
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
dai_dmic_remove_wrapper(dev);
break;
case PM_DEVICE_ACTION_RESUME:
dai_dmic_probe_wrapper(dev);
break;
case PM_DEVICE_ACTION_TURN_OFF:
case PM_DEVICE_ACTION_TURN_ON:
/* All device pm is handled during resume and suspend */
break;
default:
return -ENOTSUP;
}
return 0;
}
const struct dai_driver_api dai_dmic_ops = {
.probe = pm_device_runtime_get,
.remove = pm_device_runtime_put,
.config_set = dai_dmic_set_config,
.config_get = dai_dmic_get_config,
.get_properties = dai_dmic_get_properties,
.trigger = dai_dmic_trigger,
.ts_config = dai_dmic_timestamp_config,
.ts_start = dai_timestamp_dmic_start,
.ts_stop = dai_timestamp_dmic_stop,
.ts_get = dai_timestamp_dmic_get
};
static int dai_dmic_initialize_device(const struct device *dev)
{
IRQ_CONNECT(
DT_INST_IRQN(0),
IRQ_DEFAULT_PRIORITY,
dai_dmic_irq_handler,
DEVICE_DT_INST_GET(0),
0);
if (pm_device_on_power_domain(dev)) {
pm_device_init_off(dev);
} else {
pm_device_init_suspended(dev);
}
return pm_device_runtime_enable(dev);
};
#define DAI_INTEL_DMIC_DEVICE_INIT(n) \
static struct dai_properties dai_intel_dmic_properties_##n; \
\
static struct dai_intel_dmic dai_intel_dmic_data_##n = \
{ .dai_config_params = \
{ \
.type = DAI_INTEL_DMIC, \
.dai_index = n \
}, \
.reg_base = DT_INST_REG_ADDR_BY_IDX(n, 0), \
.shim_base = DT_INST_PROP(n, shim), \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(hdamlddmic)), \
(.hdamldmic_base = DT_REG_ADDR(DT_NODELABEL(hdamlddmic)),)) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dmicvss)), \
(.vshim_base = DT_REG_ADDR(DT_NODELABEL(dmicvss)),)) \
.irq = DT_INST_IRQN(n), \
.fifo = \
{ \
.offset = DT_INST_REG_ADDR_BY_IDX(n, 0) \
+ DT_INST_PROP(n, fifo), \
.handshake = DMA_HANDSHAKE_DMIC_CH##n \
}, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(n, dmic_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, \
dai_dmic_initialize_device, \
PM_DEVICE_DT_INST_GET(n), \
&dai_intel_dmic_data_##n, \
&dai_intel_dmic_properties_##n, \
POST_KERNEL, \
CONFIG_DAI_INIT_PRIORITY, \
&dai_dmic_ops);
DT_INST_FOREACH_STATUS_OKAY(DAI_INTEL_DMIC_DEVICE_INIT)
``` | /content/code_sandbox/drivers/dai/intel/dmic/dmic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,113 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_NHLT_H__
#define __INTEL_DAI_DRIVER_DMIC_NHLT_H__
/* For NHLT DMIC configuration parsing */
#define DMIC_HW_CONTROLLERS_MAX 4
#define DMIC_HW_FIFOS_MAX 2
struct nhlt_dmic_gateway_attributes {
uint32_t dw;
};
/* Time-slot mappings */
struct nhlt_dmic_ts_group {
uint32_t ts_group[4];
};
/* Global configuration settings */
struct nhlt_dmic_global_config {
uint32_t clock_on_delay;
};
/* PDM channels to be programmed using data from channel_cfg array. */
struct nhlt_dmic_channel_ctrl_mask {
/* i'th bit = 1 means that configuration for PDM channel # i is provided. */
uint8_t channel_ctrl_mask;
uint8_t clock_source;
uint16_t rsvd;
};
/* Channel configuration, see PDM HW specification for details. */
struct nhlt_dmic_channel_config {
uint32_t out_control;
};
struct nhlt_dmic_config_blob {
struct nhlt_dmic_gateway_attributes gtw_attributes;
struct nhlt_dmic_ts_group time_slot;
struct nhlt_dmic_global_config global_config;
struct nhlt_dmic_channel_ctrl_mask ctrl_mask;
struct nhlt_dmic_channel_config channel_config[];
};
struct nhlt_pdm_ctrl_mask {
uint32_t pdm_ctrl_mask;
};
/* FIR configuration, see PDM HW specification for details.
*
* If there is only one PDM controller configuration passed, the other (missing) one is configured
* by the driver just by clearing CIC_CONTROL.SOFT_RESET bit.
*
* The driver needs to make sure that all mics are disabled before starting to program PDM
* controllers.
*/
struct nhlt_pdm_ctrl_fir_cfg {
uint32_t fir_control;
uint32_t fir_config;
int32_t dc_offset_left;
int32_t dc_offset_right;
int32_t out_gain_left;
int32_t out_gain_right;
uint32_t reserved[2];
};
/* PDM controller configuration, see PDM HW specification for details. */
struct nhlt_pdm_ctrl_cfg {
uint32_t cic_control;
uint32_t cic_config;
uint32_t reserved0;
uint32_t mic_control;
/* PDM SoundWire Map
*
* This field is used on platforms with SoundWire, otherwise ignored.
*/
uint32_t pdm_sdw_map;
/* Index of another nhlt_pdm_ctrl_cfg to be used as a source of FIR coefficients.
*
* The index is 1-based, value of 0 means that FIR coefficients array fir_coeffs is provided
* by this item.
* This is a very common case that the same FIR coefficients are used to program more than
* one PDM controller. In this case, fir_coeffs array may be provided in a single copy
* following nhlt_pdm_ctrl_cfg #0 and be reused by nhlt_pdm_ctrl_cfg #1 by setting
* reuse_fir_from_pdm to 1 (1-based index).
*/
uint32_t reuse_fir_from_pdm;
uint32_t reserved1[2];
/* FIR configurations */
struct nhlt_pdm_ctrl_fir_cfg fir_config[2];
/* Array of FIR coefficients, channel A goes first, then channel B.
*
* Actual size of the array depends on the number of active taps of the FIR filter for
* channel A plus the number of active taps of the FIR filter for channel B (see FIR_CONFIG)
* as well as on the form (packed/unpacked) of values.
*/
uint32_t fir_coeffs[];
};
/* Tag indicating that FIRs are in a packed 24-bit format.
*
* Size of a single coefficient is 20-bit. Coefficients may be sent in either unpacked form where
* each value takes one DWORD (32-bits) or in packed form where the array begins with
* (FIR_COEFFS_PACKED_TO_24_BITS) value to indicate packed form (unpacked coefficient has always
* most significant byte set to 0) followed by array of 24-bit values (in little endian form).
*/
#define FIR_COEFFS_PACKED_TO_24_BITS 0xFFFFFFFF
#endif /* __INTEL_DAI_DRIVER_DMIC_NHLT_H__ */
``` | /content/code_sandbox/drivers/dai/intel/dmic/dmic_nhlt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 924 |
```unknown
# SOF DMIC configuration options
config DAI_INTEL_DMIC
bool "Intel digital PDM microphone driver support for DAI interface"
default y
depends on DT_HAS_INTEL_DAI_DMIC_ENABLED
depends on PM_DEVICE_RUNTIME
help
Enable Intel digital PDM microphone driver for DAI interface
if DAI_INTEL_DMIC
choice
prompt "Driver operation mode"
default DAI_INTEL_DMIC_NHLT
help
The driver can support two operation modes.
1. A HW registers dump blob that is passed via IPC
2. DAI tokens those describe the use case PCM format
and PDM bus and microphone parameters
config DAI_INTEL_DMIC_NHLT
bool "Use NHLT DMIC blob"
help
All registers configuration is retrieved from blob. The
number of channels, sample rate, and PCM format are
defined in the blob and there are no runtime made
configuration choices.
config DAI_INTEL_DMIC_TPLG_PARAMS
bool "Use parameters from topology - WIP"
help
All registers configuration is computed on the fly
based on use case and microphone datasheet parameters
and topology defined PCM format. The parameters are
easy to customize in the topology.
WORK IN PROGRESS, not enabled in the driver yet
endchoice
config DAI_DMIC_HAS_OWNERSHIP
bool "Use DMIC ownership claim/release"
default n
help
a feature introduced in ACE1.5 hardware
dmic ownership must be claimed before use of dmic
config DAI_DMIC_HAS_MULTIPLE_LINE_SYNC
bool "Use DMIC sync for multiple lines"
default n
help
a feature introduced in ACE1.5 hardware
dmic sync registers must be set before use of dmic
config DAI_DMIC_HW_CONTROLLERS
int "Number of hardware controllers in the system"
default 2
config DAI_DMIC_HW_FIFOS
int "Number of stream FIFOs in DMIC controller"
default 2
config DAI_DMIC_HW_IOCLK
int "IO Clock value for DMIC"
default 19200000
config DAI_DMIC_PLATFORM_SYNC_PERIOD
int "Sync period per platform"
default 4000
help
DMIC sync period used for:
CONFIG_DAI_DMIC_HW_IOCLK / CONFIG_DAI_DMIC_PLATFORM_SYNC_PERIOD
From spec: E.g. for 19.2 MHz XTAL oscillator clock, 4 KHz sync period,
the value to be programmed is 4799 (12BFh)
endif
``` | /content/code_sandbox/drivers/dai/intel/dmic/Kconfig.dmic | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 553 |
```c
/*
*
*/
#include <stdint.h>
#include <errno.h>
#include <zephyr/spinlock.h>
#define LOG_DOMAIN dai_intel_dmic_nhlt
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/drivers/dai.h>
#include <adsp_clk.h>
#include "dmic.h"
#include <dmic_regs.h>
#include "dmic_nhlt.h"
extern struct dai_dmic_global_shared dai_dmic_global;
/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
static const uint32_t dmic_base[4] = {PDM0, PDM1, PDM2, PDM3};
static inline void dai_dmic_write(const struct dai_intel_dmic *dmic,
uint32_t reg, uint32_t val)
{
sys_write32(val, dmic->reg_base + reg);
}
static inline uint32_t dai_dmic_read(const struct dai_intel_dmic *dmic, uint32_t reg)
{
return sys_read32(dmic->reg_base + reg);
}
/*
* @brief Move pointer to next coefficient data
*
* @return Returns pointer right after coefficient data
*/
static const uint32_t *dai_dmic_skip_coeff(const uint32_t *coeff, const int length,
const bool packed)
{
if (!packed) {
coeff += length;
} else {
coeff += ROUND_UP(3 * length, sizeof(uint32_t)) / sizeof(uint32_t);
}
return coeff;
}
/*
* @brief Write the fir coefficients in the PDMs' RAM
*/
static void dai_dmic_write_coeff(const struct dai_intel_dmic *dmic, uint32_t base,
const uint32_t *coeff, int length, const bool packed)
{
const uint8_t *coeff_in_bytes;
uint32_t coeff_val;
if (!packed) {
while (length--) {
dai_dmic_write(dmic, base, *coeff++);
base += sizeof(uint32_t);
}
} else {
coeff_in_bytes = (const uint8_t *)coeff;
while (length--) {
coeff_val = coeff_in_bytes[0] +
(coeff_in_bytes[1] << 8) +
(coeff_in_bytes[2] << 16);
dai_dmic_write(dmic, base, coeff_val);
base += sizeof(uint32_t);
coeff_in_bytes += 3;
}
}
}
/*
* @brief Configures the fir coefficients in the PDMs' RAM
*
* @return Returns pointer right after coefficients data
*/
static const uint32_t *dai_dmic_configure_coeff(const struct dai_intel_dmic *dmic,
const struct nhlt_pdm_ctrl_cfg * const pdm_cfg,
const uint32_t pdm_base,
const uint32_t *coeffs)
{
int fir_length_a, fir_length_b;
bool packed = false;
const uint32_t *coeffs_b;
fir_length_a = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[0].fir_config) + 1;
fir_length_b = FIELD_GET(FIR_CONFIG_FIR_LENGTH, pdm_cfg->fir_config[1].fir_config) + 1;
if (fir_length_a > 256 || fir_length_b > 256) {
LOG_ERR("invalid coeff length! %d %d", fir_length_a, fir_length_b);
return NULL;
}
if (*coeffs == FIR_COEFFS_PACKED_TO_24_BITS) {
packed = true;
/* First dword is not included into length_0 and length_1 - skip it. */
coeffs++;
}
coeffs_b = dai_dmic_skip_coeff(coeffs, fir_length_a, packed);
LOG_INF("fir_length_a = %d, fir_length_b = %d, packed = %d", fir_length_a, fir_length_b,
packed);
if (dmic->dai_config_params.dai_index == 0) {
dai_dmic_write_coeff(dmic, pdm_base + PDM_COEFFICIENT_A, coeffs, fir_length_a,
packed);
} else {
dai_dmic_write_coeff(dmic, pdm_base + PDM_COEFFICIENT_B, coeffs_b, fir_length_b,
packed);
}
return dai_dmic_skip_coeff(coeffs_b, fir_length_b, packed);
}
static int dai_nhlt_get_clock_div(const struct dai_intel_dmic *dmic, const int pdm)
{
uint32_t val;
int p_mcic, p_clkdiv, p_mfir, rate_div;
val = dai_dmic_read(dmic, dmic_base[pdm] + CIC_CONFIG);
p_mcic = FIELD_GET(CIC_CONFIG_COMB_COUNT, val) + 1;
val = dai_dmic_read(dmic, dmic_base[pdm] + MIC_CONTROL);
p_clkdiv = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, val) + 2;
val = dai_dmic_read(dmic, dmic_base[pdm] +
FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index + FIR_CONFIG);
LOG_INF("pdm = %d, FIR_CONFIG = 0x%08X", pdm, val);
p_mfir = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val) + 1;
rate_div = p_clkdiv * p_mcic * p_mfir;
LOG_INF("dai_index = %d, rate_div = %d, p_clkdiv = %d, p_mcic = %d, p_mfir = %d",
dmic->dai_config_params.dai_index, rate_div, p_clkdiv, p_mcic, p_mfir);
if (!rate_div) {
LOG_ERR("zero clock divide or decimation factor");
return -EINVAL;
}
return rate_div;
}
static int dai_nhlt_update_rate(struct dai_intel_dmic *dmic, const int clock_source, const int pdm)
{
int rate_div;
rate_div = dai_nhlt_get_clock_div(dmic, pdm);
if (rate_div < 0) {
return rate_div;
}
dmic->dai_config_params.rate = adsp_clock_source_frequency(clock_source) /
rate_div;
LOG_INF("rate = %d, channels = %d, format = %d",
dmic->dai_config_params.rate, dmic->dai_config_params.channels,
dmic->dai_config_params.format);
LOG_INF("io_clk %u, rate_div %d", adsp_clock_source_frequency(clock_source), rate_div);
return 0;
}
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic,
int *count, int pdm_count, int stereo,
int source_pdm)
{
int mic_swap;
if (source_pdm >= CONFIG_DAI_DMIC_HW_CONTROLLERS)
return -EINVAL;
if (*count < pdm_count) {
(*count)++;
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, dai_dmic_read(
dmic, dmic_base[source_pdm] + MIC_CONTROL));
if (stereo)
dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */
else
dmic->enable[source_pdm] = mic_swap ? 0x2 : 0x1; /* PDMi MIC B or MIC A */
}
return 0;
}
static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int clock_source)
{
bool stereo_pdm;
int source_pdm;
int first_pdm;
int num_pdm;
int ret;
int n;
uint32_t outcontrol_val = dai_dmic_read(dmic, dmic->dai_config_params.dai_index *
PDM_CHANNEL_REGS_SIZE + OUTCONTROL);
switch (FIELD_GET(OUTCONTROL_OF, outcontrol_val)) {
case 0:
case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
dmic->dai_config_params.word_size = 16;
break;
case 2:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE;
dmic->dai_config_params.word_size = 32;
break;
default:
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal OF bit field");
return -EINVAL;
}
num_pdm = FIELD_GET(OUTCONTROL_IPM, outcontrol_val);
if (num_pdm > CONFIG_DAI_DMIC_HW_CONTROLLERS) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM PDM controllers count %d",
num_pdm);
return -EINVAL;
}
stereo_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, outcontrol_val);
dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm;
for (n = 0; n < CONFIG_DAI_DMIC_HW_CONTROLLERS; n++)
dmic->enable[n] = 0;
n = 0;
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, outcontrol_val);
first_pdm = source_pdm;
ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_1");
return -EINVAL;
}
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_2");
return -EINVAL;
}
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_3");
return -EINVAL;
}
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_4");
return -EINVAL;
}
return dai_nhlt_update_rate(dmic, clock_source, first_pdm);
}
/*
* @brief Set clock source used by device
*
* @param source Clock source index
*/
static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)
{
uint32_t val;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
val &= ~DMICLVSCTL_MLCS;
val |= FIELD_PREP(DMICLVSCTL_MLCS, source);
sys_write32(val, dmic->vshim_base + DMICLVSCTL_OFFSET);
#else
val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET);
val &= ~DMICLCTL_MLCS;
val |= FIELD_PREP(DMICLCTL_MLCS, source);
sys_write32(val, dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
/*
* @brief Get clock source used by device
*
* @return Clock source index
*/
static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic)
{
uint32_t val;
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
return FIELD_GET(DMICLVSCTL_MLCS, val);
#else
val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET);
return FIELD_GET(DMICLCTL_MLCS, val);
#endif
}
/*
* @brief Set clock source used by device
*
* @param source Clock source index
*/
static int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t clock_source)
{
LOG_DBG("%s(): clock_source = %u", __func__, clock_source);
if (!adsp_clock_source_is_supported(clock_source)) {
return -ENOTSUP;
}
#if defined(CONFIG_SOC_INTEL_ACE15_MTPM)
if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) {
return -ENOTSUP;
}
#endif
dai_dmic_clock_select_set(dmic, clock_source);
return 0;
}
#else
static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic)
{
uint32_t outcontrol;
uint32_t fir_control[2];
uint32_t mic_control[2];
int fir_stereo[2];
int mic_swap;
outcontrol = dai_dmic_read(dmic, dmic->dai_config_params.dai_index * PDM_CHANNEL_REGS_SIZE +
OUTCONTROL);
switch (FIELD_GET(OUTCONTROL_OF, outcontrol)) {
case 0:
case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
break;
case 2:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S32_LE;
break;
default:
LOG_ERR("Illegal OF bit field");
return -EINVAL;
}
fir_control[0] = dai_dmic_read(dmic, dmic_base[0] +
dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE +
FIR_CONTROL);
fir_control[1] = dai_dmic_read(dmic, dmic_base[1] +
dmic->dai_config_params.dai_index * FIR_CHANNEL_REGS_SIZE +
FIR_CONTROL);
mic_control[0] = dai_dmic_read(dmic, dmic_base[0] + MIC_CONTROL);
mic_control[1] = dai_dmic_read(dmic, dmic_base[1] + MIC_CONTROL);
switch (FIELD_GET(OUTCONTROL_IPM, outcontrol)) {
case 0:
fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_control[0]);
if (fir_stereo[0]) {
dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
dmic->enable[1] = 0x0; /* PDM1 none */
} else {
dmic->dai_config_params.channels = 1;
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, mic_control[0]);
dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */
dmic->enable[1] = 0x0; /* PDM1 */
}
break;
case 1:
fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_control[1]);
if (fir_stereo[1]) {
dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x0; /* PDM0 none */
dmic->enable[1] = 0x3; /* PDM1 MIC A and B */
} else {
dmic->dai_config_params.channels = 1;
dmic->enable[0] = 0x0; /* PDM0 none */
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, mic_control[1]);
dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */
}
break;
case 2:
fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_control[0]);
fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_control[1]);
if (fir_stereo[0] == fir_stereo[1]) {
dmic->dai_config_params.channels = 4;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
dmic->enable[1] = 0x3; /* PDM1 MIC A and B */
LOG_INF("set 4ch pdm0 and pdm1");
} else {
LOG_ERR("Illegal 4ch configuration");
return -EINVAL;
}
break;
default:
LOG_ERR("Illegal OF bit field");
return -EINVAL;
}
return dai_nhlt_update_rate(dmic, 0, 0);
}
static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t clock_source)
{
return 0;
}
#endif
static int print_outcontrol(uint32_t val)
{
int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8;
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
int bf9, bf10, bf11, bf12, bf13;
#endif
uint32_t ref;
bf1 = FIELD_GET(OUTCONTROL_TIE, val);
bf2 = FIELD_GET(OUTCONTROL_SIP, val);
bf3 = FIELD_GET(OUTCONTROL_FINIT, val);
bf4 = FIELD_GET(OUTCONTROL_FCI, val);
bf5 = FIELD_GET(OUTCONTROL_BFTH, val);
bf6 = FIELD_GET(OUTCONTROL_OF, val);
bf7 = FIELD_GET(OUTCONTROL_IPM, val);
bf8 = FIELD_GET(OUTCONTROL_TH, val);
LOG_INF("OUTCONTROL = %08x", val);
LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4);
LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8);
if (bf5 > OUTCONTROL_BFTH_MAX) {
LOG_WRN("illegal BFTH value %d", bf5);
return -EINVAL;
}
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
bf12 = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, val);
bf13 = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, val);
LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12);
LOG_INF(" ipms_mode=%d", bf13);
ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13);
#else
ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_TH, bf8);
#endif
if (ref != val) {
LOG_WRN("Some reserved bits are set in OUTCONTROL = 0x%08x", val);
}
return 0;
}
static void print_cic_control(uint32_t val)
{
int bf1, bf2, bf3, bf4, bf5, bf6, bf7;
uint32_t ref;
bf1 = FIELD_GET(CIC_CONTROL_SOFT_RESET, val);
bf2 = FIELD_GET(CIC_CONTROL_CIC_START_B, val);
bf3 = FIELD_GET(CIC_CONTROL_CIC_START_A, val);
bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
#else
bf7 = -1;
#endif
LOG_DBG("CIC_CONTROL = %08x", val);
LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d",
bf1, bf2, bf3);
LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d",
bf4, bf5, bf6);
ref = FIELD_PREP(CIC_CONTROL_SOFT_RESET, bf1) |
FIELD_PREP(CIC_CONTROL_CIC_START_B, bf2) |
FIELD_PREP(CIC_CONTROL_CIC_START_A, bf3) |
FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
#endif
;
LOG_DBG(" stereo_mode=%d", bf7);
if (ref != val) {
LOG_WRN("Some reserved bits are set in CIC_CONTROL = 0x%08x", val);
}
}
static void print_fir_control(uint32_t val)
{
int bf1, bf2, bf3, bf4, bf5, bf6;
uint32_t ref;
bf1 = FIELD_GET(FIR_CONTROL_START, val);
bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
#else
bf3 = -1;
#endif
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
LOG_DBG("FIR_CONTROL = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
#endif
FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
FIELD_PREP(FIR_CONTROL_MUTE, bf5) |
FIELD_PREP(FIR_CONTROL_STEREO, bf6);
if (ref != val) {
LOG_WRN("Some reserved bits are set in FIR_CONTROL = 0x%08x", val);
}
}
static void print_pdm_ctrl(const struct nhlt_pdm_ctrl_cfg *pdm_cfg)
{
int bf1, bf2, bf3, bf4, bf5;
uint32_t val;
LOG_DBG("CIC_CONTROL = %08x", pdm_cfg->cic_control);
val = pdm_cfg->cic_config;
bf1 = FIELD_GET(CIC_CONFIG_CIC_SHIFT, val);
bf2 = FIELD_GET(CIC_CONFIG_COMB_COUNT, val);
LOG_DBG("CIC_CONFIG = %08x", val);
LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, bf2);
val = pdm_cfg->mic_control;
#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
#else
bf1 = -1;
#endif
bf2 = FIELD_GET(MIC_CONTROL_CLK_EDGE, val);
bf3 = FIELD_GET(MIC_CONTROL_PDM_EN_B, val);
bf4 = FIELD_GET(MIC_CONTROL_PDM_EN_A, val);
bf5 = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, val);
LOG_DBG("MIC_CONTROL = %08x", val);
LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", bf5, bf1, bf2);
LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4);
}
static void print_fir_config(const struct nhlt_pdm_ctrl_fir_cfg *fir_cfg)
{
uint32_t val;
int fir_decimation, fir_shift, fir_length;
val = fir_cfg->fir_config;
fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
LOG_DBG("FIR_CONFIG = %08x", val);
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
fir_decimation, fir_shift, fir_length);
print_fir_control(fir_cfg->fir_control);
/* Use DC_OFFSET and GAIN as such */
LOG_DBG("DC_OFFSET_LEFT = %08x", fir_cfg->dc_offset_left);
LOG_DBG("DC_OFFSET_RIGHT = %08x", fir_cfg->dc_offset_right);
LOG_DBG("OUT_GAIN_LEFT = %08x", fir_cfg->out_gain_left);
LOG_DBG("OUT_GAIN_RIGHT = %08x", fir_cfg->out_gain_right);
}
static void configure_fir(struct dai_intel_dmic *dmic, const uint32_t base,
const struct nhlt_pdm_ctrl_fir_cfg *fir_cfg)
{
uint32_t val;
print_fir_config(fir_cfg);
/* Use FIR_CONFIG as such */
val = fir_cfg->fir_config;
dai_dmic_write(dmic, base + FIR_CONFIG, val);
val = fir_cfg->fir_control;
print_fir_control(val);
/* Clear START, set MUTE */
val = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
dai_dmic_write(dmic, base + FIR_CONTROL, val);
LOG_DBG("FIR_CONTROL = %08x", val);
/* Use DC_OFFSET and GAIN as such */
dai_dmic_write(dmic, base + DC_OFFSET_LEFT, fir_cfg->dc_offset_left);
dai_dmic_write(dmic, base + DC_OFFSET_RIGHT, fir_cfg->dc_offset_right);
dai_dmic_write(dmic, base + OUT_GAIN_LEFT, fir_cfg->out_gain_left);
dai_dmic_write(dmic, base + OUT_GAIN_RIGHT, fir_cfg->out_gain_right);
dmic->gain_left = fir_cfg->out_gain_left;
dmic->gain_right = fir_cfg->out_gain_right;
}
int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cfg)
{
const struct nhlt_pdm_ctrl_cfg *pdm_cfg;
struct nhlt_dmic_channel_ctrl_mask *dmic_cfg;
uint32_t channel_ctrl_mask;
uint32_t pdm_ctrl_mask;
uint32_t pdm_base;
int pdm_idx;
uint32_t val;
uint32_t outcontrol;
const uint8_t *p = bespoke_cfg;
int num_fifos;
int num_pdm;
int n;
int ret;
const uint32_t *fir_coeffs;
/* Array of pointers to pdm coefficient data. Used to reuse coefficient from another pdm. */
const uint32_t *pdm_coeff_ptr[DMIC_HW_CONTROLLERS_MAX] = { 0 };
if (dmic->dai_config_params.dai_index >= DMIC_HW_FIFOS_MAX) {
LOG_ERR("dmic_set_config_nhlt(): illegal DAI index %d",
dmic->dai_config_params.dai_index);
return -EINVAL;
}
/* Skip not used headers */
p += sizeof(struct nhlt_dmic_gateway_attributes);
p += sizeof(struct nhlt_dmic_ts_group);
p += sizeof(struct nhlt_dmic_global_config);
/* Channel_ctlr_mask bits indicate the FIFOs enabled*/
dmic_cfg = (struct nhlt_dmic_channel_ctrl_mask *)p;
channel_ctrl_mask = dmic_cfg->channel_ctrl_mask;
num_fifos = POPCOUNT(channel_ctrl_mask); /* Count set bits */
p += sizeof(struct nhlt_dmic_channel_ctrl_mask);
LOG_DBG("dmic_set_config_nhlt(): channel_ctrl_mask = %d", channel_ctrl_mask);
/* Configure clock source */
ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source);
if (ret) {
return ret;
}
/* Get OUTCONTROLx configuration */
if (num_fifos < 1 || num_fifos > DMIC_HW_FIFOS_MAX) {
LOG_ERR("dmic_set_config_nhlt(): illegal number of FIFOs %d", num_fifos);
return -EINVAL;
}
for (n = 0; n < DMIC_HW_FIFOS_MAX; n++) {
if (!(channel_ctrl_mask & (1 << n))) {
continue;
}
val = *(uint32_t *)p;
ret = print_outcontrol(val);
if (ret) {
return ret;
}
if (dmic->dai_config_params.dai_index == n) {
/* Write the FIFO control registers. The clear/set of bits is the same for
* all DMIC_HW_VERSION
*/
/* Clear TIE, SIP, FCI, set FINIT, the rest of bits as such */
outcontrol = (val & ~(OUTCONTROL_TIE | OUTCONTROL_SIP | OUTCONTROL_FCI)) |
OUTCONTROL_FINIT;
dai_dmic_write(dmic, dmic->dai_config_params.dai_index *
PDM_CHANNEL_REGS_SIZE + OUTCONTROL, outcontrol);
LOG_INF("OUTCONTROL%d = %08x", dmic->dai_config_params.dai_index,
outcontrol);
/* Pass 2^BFTH to plat_data fifo depth. It will be used later in DMA
* configuration
*/
val = FIELD_GET(OUTCONTROL_BFTH, outcontrol);
dmic->fifo.depth = 1 << val;
}
p += sizeof(uint32_t);
}
/* Get PDMx registers */
pdm_ctrl_mask = ((const struct nhlt_pdm_ctrl_mask *)p)->pdm_ctrl_mask;
num_pdm = POPCOUNT(pdm_ctrl_mask); /* Count set bits */
p += sizeof(struct nhlt_pdm_ctrl_mask);
LOG_DBG("dmic_set_config_nhlt(): pdm_ctrl_mask = %d", pdm_ctrl_mask);
if (num_pdm < 1 || num_pdm > CONFIG_DAI_DMIC_HW_CONTROLLERS) {
LOG_ERR("dmic_set_config_nhlt(): illegal number of PDMs %d", num_pdm);
return -EINVAL;
}
pdm_cfg = (const struct nhlt_pdm_ctrl_cfg *)p;
for (pdm_idx = 0; pdm_idx < CONFIG_DAI_DMIC_HW_CONTROLLERS; pdm_idx++) {
pdm_base = dmic_base[pdm_idx];
if (!(pdm_ctrl_mask & (1 << pdm_idx))) {
/* Set MIC_MUTE bit to unused PDM */
dai_dmic_write(dmic, pdm_base + CIC_CONTROL, CIC_CONTROL_MIC_MUTE);
continue;
}
LOG_DBG("PDM%d", pdm_idx);
/* Get CIC configuration */
if (dai_dmic_global.active_fifos_mask == 0) {
print_pdm_ctrl(pdm_cfg);
val = pdm_cfg->cic_control;
print_cic_control(val);
/* Clear CIC_START_A and CIC_START_B */
val = (val & ~(CIC_CONTROL_CIC_START_A | CIC_CONTROL_CIC_START_B));
dai_dmic_write(dmic, pdm_base + CIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
/* Use CIC_CONFIG as such */
val = pdm_cfg->cic_config;
dai_dmic_write(dmic, pdm_base + CIC_CONFIG, val);
/* Clear PDM_EN_A and PDM_EN_B */
val = pdm_cfg->mic_control;
val &= ~(MIC_CONTROL_PDM_EN_A | MIC_CONTROL_PDM_EN_B);
dai_dmic_write(dmic, pdm_base + MIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
}
configure_fir(dmic, pdm_base +
FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index,
&pdm_cfg->fir_config[dmic->dai_config_params.dai_index]);
/* Configure fir coefficients */
/* Check if FIR coeffs should be reused */
if (pdm_cfg->reuse_fir_from_pdm == 0) {
/* get ptr, where FIR coeffs starts */
fir_coeffs = pdm_cfg->fir_coeffs;
/* and save it for future pdms reference */
pdm_coeff_ptr[pdm_idx] = fir_coeffs;
} else {
if (pdm_cfg->reuse_fir_from_pdm > pdm_idx) {
LOG_ERR("invalid reuse fir index %u", pdm_cfg->reuse_fir_from_pdm);
return -EINVAL;
}
/* get FIR coeffs from another pdm */
fir_coeffs = pdm_coeff_ptr[pdm_cfg->reuse_fir_from_pdm - 1];
if (!fir_coeffs) {
LOG_ERR("unable to reuse fir from %u", pdm_cfg->reuse_fir_from_pdm);
return -EINVAL;
}
}
fir_coeffs = dai_dmic_configure_coeff(dmic, pdm_cfg, pdm_base, fir_coeffs);
/* Update pdm_cfg ptr for next PDM Ctrl. */
if (pdm_cfg->reuse_fir_from_pdm) {
/* fir_coeffs array is empty if reusing previous coeffs */
pdm_cfg = (const struct nhlt_pdm_ctrl_cfg *)&pdm_cfg->fir_coeffs;
} else {
pdm_cfg = (const struct nhlt_pdm_ctrl_cfg *)fir_coeffs;
}
}
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source);
#else
ret = dai_nhlt_dmic_dai_params_get(dmic);
#endif
if (ret) {
return ret;
}
LOG_INF("dmic_set_config_nhlt(): enable0 %u, enable1 %u",
dmic->enable[0], dmic->enable[1]);
return 0;
}
``` | /content/code_sandbox/drivers/dai/intel/dmic/dmic_nhlt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,925 |
```unknown
config DAI_NXP_ESAI
bool "NXP Enhanced Serial Audio Interface (ESAI) driver"
default y
depends on DT_HAS_NXP_DAI_ESAI_ENABLED
help
Select this to enable NXP ESAI driver.
``` | /content/code_sandbox/drivers/dai/nxp/esai/Kconfig.esai | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#include "esai.h"
/* TODO:
* 1) Some pin functions can be inferred from software ctx. For instance,
* if you use more than 1 data line, it's obvious you're going
* to want to keep the pins of the data lines in ESAI mode.
*
* 2) Add function for handling underrun/overrun. Preferably
* we should do the same as we did for SAI to ease the testing
* process. This approach will do for now. In the future, this
* can be handled in a more sophisticated maner.
*
* notes:
* 1) EXTAL clock is divided as follows:
* a) Initial EXTAL signal is automatically divided by 2.
* b) If prescaler is enabled the resulting EXTAL from a)
* is divided by 8.
* c) The resulting EXTAL signal from b) can be divided
* by 1 up to 256 (configured via xPM0-xPM7). The resulting
* signal is referred to as HCLK.
* d) HCLK obtained from c) can be further divided by 1
* up to 16 (configured via xFP0-xFP3). The resulting signal is
* referred to as BCLK.
*/
static int esai_get_clock_rate_config(uint32_t extal_rate, uint32_t hclk_rate,
uint32_t bclk_rate, bool variable_hclk,
bool allow_bclk_configuration,
struct esai_transceiver_config *cfg)
{
uint32_t hclk_div_ratio, bclk_div_ratio;
/* sanity checks */
if (!cfg) {
LOG_ERR("got NULL clock configuration");
return -EINVAL;
}
if (!extal_rate || !hclk_rate || !bclk_rate) {
LOG_ERR("got NULL clock rate");
return -EINVAL;
}
if (hclk_rate > extal_rate) {
LOG_ERR("HCLK rate cannot be higher than EXTAL rate");
return -EINVAL;
}
if (bclk_rate > extal_rate) {
LOG_ERR("BCLK rate cannot be higher than EXTAL rate");
return -EINVAL;
}
if (DIV_ROUND_UP(extal_rate, bclk_rate) > 2 * 8 * 256 * 16) {
LOG_ERR("BCLK rate %u cannot be obtained from EXTAL rate %u",
bclk_rate, extal_rate);
return -EINVAL;
}
/* TODO: add explanation */
if (DIV_ROUND_UP(extal_rate / 2, bclk_rate) == 1) {
LOG_ERR("HCLK prescaler bypass with divider bypass is not supported");
return -EINVAL;
}
hclk_div_ratio = 1;
bclk_div_ratio = 1;
/* check if HCLK is in (EXTAL_RATE / 2, EXTAL_RATE). If so,
* return an error as any rates from this interval cannot be obtained.
*/
if (hclk_rate > extal_rate / 2 && hclk_rate < extal_rate) {
LOG_ERR("HCLK rate cannot be higher than EXTAL's rate divided by 2");
return -EINVAL;
}
/* compute HCLK configuration - only required if HCLK pad output is used */
if (!variable_hclk) {
if (extal_rate == hclk_rate) {
/* HCLK rate from pad is the same as EXTAL rate */
cfg->hclk_bypass = true;
} else {
/* EXTAL is automatically divided by 2 */
extal_rate /= 2;
/* compute prescaler divide ratio w/ prescaler bypass */
hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate);
if (hclk_div_ratio > 256) {
/* can't obtain HCLK w/o prescaler */
cfg->hclk_prescaler_en = true;
extal_rate /= 8;
/* recompute ratio w/ prescaler */
hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate);
if (hclk_div_ratio > 256) {
LOG_ERR("cannot obtain HCLK rate %u from EXTAL rate %u",
hclk_rate, extal_rate);
return -EINVAL;
}
}
}
}
cfg->hclk_div_ratio = hclk_div_ratio;
if (!allow_bclk_configuration) {
return 0;
}
extal_rate = DIV_ROUND_UP(extal_rate, hclk_div_ratio);
/* compute BCLK configuration */
if (variable_hclk || cfg->hclk_bypass) {
/* attempt to find a configuration that satisfies BCLK's rate */
extal_rate /= 2;
hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate);
/* check if prescaler is required */
if (hclk_div_ratio > 256 * 16) {
extal_rate /= 8;
cfg->hclk_prescaler_en = true;
hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate);
}
/* check if we really need to loop through TPM div ratios */
if (hclk_div_ratio < 256) {
cfg->bclk_div_ratio = 1;
cfg->hclk_div_ratio = hclk_div_ratio;
return 0;
}
for (int i = 1; i < 256; i++) {
hclk_div_ratio = DIV_ROUND_UP(extal_rate / i, bclk_rate);
bclk_div_ratio = DIV_ROUND_UP(extal_rate / hclk_div_ratio, bclk_rate);
if (bclk_div_ratio <= 16) {
/* found valid configuration, let caller know */
cfg->bclk_div_ratio = bclk_div_ratio;
cfg->hclk_div_ratio = hclk_div_ratio;
return 0;
}
}
/* no valid configuration found */
LOG_ERR("no valid configuration for BCLK rate %u and EXTAL rate %u",
bclk_rate, extal_rate);
return -EINVAL;
}
/* can the BCLK rate be obtained w/o modifying divided EXTAL? */
bclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate);
if (bclk_div_ratio > 16) {
LOG_ERR("cannot obtain BCLK rate %d from EXTAL rate %d",
bclk_rate, extal_rate);
return -EINVAL;
}
/* save ratios before returning */
cfg->bclk_div_ratio = bclk_div_ratio;
cfg->hclk_div_ratio = hclk_div_ratio;
return 0;
}
static int esai_get_clk_provider_config(const struct dai_config *cfg,
struct esai_transceiver_config *xceiver_cfg)
{
switch (cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK) {
case DAI_CBC_CFC:
/* default FSYNC and BCLK are OUTPUT */
break;
case DAI_CBP_CFP:
xceiver_cfg->bclk_dir = kESAI_ClockInput;
xceiver_cfg->fsync_dir = kESAI_ClockInput;
break;
default:
LOG_ERR("invalid clock provider configuration: %d",
cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
return 0;
}
static int esai_get_clk_inversion_config(const struct dai_config *cfg,
struct esai_transceiver_config *xceiver_cfg)
{
switch (cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK) {
case DAI_INVERSION_IB_IF:
ESAI_INVERT_POLARITY(xceiver_cfg->bclk_polarity);
ESAI_INVERT_POLARITY(xceiver_cfg->fsync_polarity);
break;
case DAI_INVERSION_IB_NF:
ESAI_INVERT_POLARITY(xceiver_cfg->bclk_polarity);
break;
case DAI_INVERSION_NB_IF:
ESAI_INVERT_POLARITY(xceiver_cfg->fsync_polarity);
break;
case DAI_INVERSION_NB_NF:
/* nothing to do here */
break;
default:
LOG_ERR("invalid clock inversion configuration: %d",
cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK);
return -EINVAL;
}
return 0;
}
static int esai_get_proto_config(const struct dai_config *cfg,
struct esai_transceiver_config *xceiver_cfg)
{
switch (cfg->format & DAI_FORMAT_PROTOCOL_MASK) {
case DAI_PROTO_I2S:
xceiver_cfg->bclk_polarity = kESAI_ClockActiveLow;
xceiver_cfg->fsync_polarity = kESAI_ClockActiveLow;
break;
case DAI_PROTO_DSP_A:
xceiver_cfg->bclk_polarity = kESAI_ClockActiveLow;
xceiver_cfg->fsync_is_bit_wide = true;
break;
default:
LOG_ERR("invalid DAI protocol: %d",
cfg->format & DAI_FORMAT_PROTOCOL_MASK);
return -EINVAL;
}
return 0;
}
static int esai_get_slot_format(uint32_t slot_width, uint32_t word_width,
struct esai_transceiver_config *cfg)
{
/* sanity check */
if (!ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width, word_width)) {
LOG_ERR("invalid slot %d word %d width configuration",
slot_width, word_width);
return -EINVAL;
}
cfg->slot_format = ESAI_SLOT_FORMAT(slot_width, word_width);
return 0;
}
static void esai_get_xceiver_default_config(struct esai_transceiver_config *cfg)
{
memset(cfg, 0, sizeof(*cfg));
cfg->hclk_prescaler_en = false;
cfg->hclk_div_ratio = 1;
cfg->bclk_div_ratio = 1;
cfg->hclk_bypass = false;
cfg->hclk_src = kESAI_HckSourceExternal;
cfg->hclk_dir = kESAI_ClockOutput;
cfg->hclk_polarity = kESAI_ClockActiveHigh;
cfg->bclk_dir = kESAI_ClockOutput;
cfg->bclk_polarity = kESAI_ClockActiveHigh;
cfg->fsync_dir = kESAI_ClockOutput;
cfg->fsync_polarity = kESAI_ClockActiveHigh;
cfg->fsync_is_bit_wide = false;
cfg->zero_pad_en = true;
cfg->fsync_early = true;
cfg->mode = kESAI_NetworkMode;
cfg->data_order = kESAI_ShifterMSB;
cfg->data_left_aligned = true;
}
static void esai_commit_config(ESAI_Type *base,
enum dai_dir dir,
struct esai_transceiver_config *cfg)
{
if (dir == DAI_DIR_TX) {
base->TCCR &= ~(ESAI_TCCR_THCKD_MASK | ESAI_TCCR_TFSD_MASK |
ESAI_TCCR_TCKD_MASK | ESAI_TCCR_THCKP_MASK |
ESAI_TCCR_TFSP_MASK | ESAI_TCCR_TCKP_MASK |
ESAI_TCCR_TFP_MASK | ESAI_TCCR_TDC_MASK |
ESAI_TCCR_TPSR_MASK | ESAI_TCCR_TPM_MASK);
base->TCCR |= ESAI_TCCR_THCKD(cfg->hclk_dir) |
ESAI_TCCR_TFSD(cfg->fsync_dir) |
ESAI_TCCR_TCKD(cfg->bclk_dir) |
ESAI_TCCR_THCKP(cfg->hclk_polarity) |
ESAI_TCCR_TFSP(cfg->fsync_polarity) |
ESAI_TCCR_TCKP(cfg->bclk_polarity) |
ESAI_TCCR_TFP(cfg->bclk_div_ratio - 1) |
ESAI_TCCR_TDC(cfg->fsync_div - 1) |
ESAI_TCCR_TPSR(!cfg->hclk_prescaler_en) |
ESAI_TCCR_TPM(cfg->hclk_div_ratio - 1);
base->TCR &= ~(ESAI_TCR_PADC_MASK | ESAI_TCR_TFSR_MASK |
ESAI_TCR_TFSL_MASK | ESAI_TCR_TMOD_MASK |
ESAI_TCR_TWA_MASK | ESAI_TCR_TSHFD_MASK);
base->TCR |= ESAI_TCR_PADC(cfg->zero_pad_en) |
ESAI_TCR_TFSR(cfg->fsync_early) |
ESAI_TCR_TFSL(cfg->fsync_is_bit_wide) |
ESAI_TCR_TSWS(cfg->slot_format) |
ESAI_TCR_TMOD(cfg->mode) |
ESAI_TCR_TWA(!cfg->data_left_aligned) |
ESAI_TCR_TSHFD(cfg->data_order);
base->ECR &= ~(ESAI_ECR_ETI_MASK |
ESAI_ECR_ETO_MASK);
base->ECR |= ESAI_ECR_ETI(cfg->hclk_src) |
ESAI_ECR_ETO(cfg->hclk_bypass);
base->TFCR &= ~(ESAI_TFCR_TFWM_MASK | ESAI_TFCR_TWA_MASK);
base->TFCR |= ESAI_TFCR_TFWM(cfg->watermark) |
ESAI_TFCR_TWA(cfg->word_alignment);
ESAI_TxSetSlotMask(base, cfg->slot_mask);
} else {
base->RCCR &= ~(ESAI_RCCR_RHCKD_MASK | ESAI_RCCR_RFSD_MASK |
ESAI_RCCR_RCKD_MASK | ESAI_RCCR_RHCKP_MASK |
ESAI_RCCR_RFSP_MASK | ESAI_RCCR_RCKP_MASK |
ESAI_RCCR_RFP_MASK | ESAI_RCCR_RDC_MASK |
ESAI_RCCR_RPSR_MASK | ESAI_RCCR_RPM_MASK);
base->RCCR |= ESAI_RCCR_RHCKD(cfg->hclk_dir) |
ESAI_RCCR_RFSD(cfg->fsync_dir) |
ESAI_RCCR_RCKD(cfg->bclk_dir) |
ESAI_RCCR_RHCKP(cfg->hclk_polarity) |
ESAI_RCCR_RFSP(cfg->fsync_polarity) |
ESAI_RCCR_RCKP(cfg->bclk_polarity) |
ESAI_RCCR_RFP(cfg->bclk_div_ratio - 1) |
ESAI_RCCR_RDC(cfg->fsync_div - 1) |
ESAI_RCCR_RPSR(!cfg->hclk_prescaler_en) |
ESAI_RCCR_RPM(cfg->hclk_div_ratio - 1);
base->RCR &= ~(ESAI_RCR_RFSR_MASK | ESAI_RCR_RFSL_MASK |
ESAI_RCR_RMOD_MASK | ESAI_RCR_RWA_MASK |
ESAI_RCR_RSHFD_MASK);
base->RCR |= ESAI_RCR_RFSR(cfg->fsync_early) |
ESAI_RCR_RFSL(cfg->fsync_is_bit_wide) |
ESAI_RCR_RSWS(cfg->slot_format) |
ESAI_RCR_RMOD(cfg->mode) |
ESAI_RCR_RWA(!cfg->data_left_aligned) |
ESAI_RCR_RSHFD(cfg->data_order);
base->ECR &= ~(ESAI_ECR_ERI_MASK |
ESAI_ECR_ERO_MASK);
base->ECR |= ESAI_ECR_ERI(cfg->hclk_src) |
ESAI_ECR_ERO(cfg->hclk_bypass);
base->RFCR &= ~(ESAI_RFCR_RFWM_MASK | ESAI_RFCR_RWA_MASK);
base->RFCR |= ESAI_RFCR_RFWM(cfg->watermark) |
ESAI_RFCR_RWA(cfg->word_alignment);
EASI_RxSetSlotMask(base, cfg->slot_mask);
}
}
static int esai_config_set(const struct device *dev,
const struct dai_config *cfg,
const void *bespoke_data)
{
const struct esai_bespoke_config *bespoke;
struct esai_data *data;
const struct esai_config *esai_cfg;
struct esai_transceiver_config tx_config;
struct esai_transceiver_config rx_config;
ESAI_Type *base;
int ret;
if (!cfg || !bespoke_data) {
return -EINVAL;
}
if (cfg->type != DAI_IMX_ESAI) {
LOG_ERR("wrong DAI type: %d", cfg->type);
return -EINVAL;
}
data = dev->data;
esai_cfg = dev->config;
bespoke = bespoke_data;
base = UINT_TO_ESAI(data->regmap);
/* config_set() configures both the transmitter and the receiver.
* As such, the following state transitions make sure that the
* directions are stopped. This means that they can be safely
* reset and re-configured.
*/
ret = esai_update_state(data, DAI_DIR_TX, DAI_STATE_READY);
if (ret < 0) {
LOG_ERR("failed to update TX state");
return ret;
}
ret = esai_update_state(data, DAI_DIR_RX, DAI_STATE_READY);
if (ret < 0) {
LOG_ERR("failed to update RX state");
return ret;
}
ESAI_Enable(base, true);
/* disconnect all ESAI pins */
base->PCRC &= ~ESAI_PCRC_PC_MASK;
base->PRRC &= ~ESAI_PRRC_PDC_MASK;
/* go back to known configuration through reset */
ESAI_Reset(UINT_TO_ESAI(data->regmap));
/* get default configuration */
esai_get_xceiver_default_config(&tx_config);
/* TODO: for now, only network mode is supported */
tx_config.fsync_div = bespoke->tdm_slots;
/* clock provider configuration */
ret = esai_get_clk_provider_config(cfg, &tx_config);
if (ret < 0) {
return ret;
}
/* protocol configuration */
ret = esai_get_proto_config(cfg, &tx_config);
if (ret < 0) {
return ret;
}
/* clock inversion configuration */
ret = esai_get_clk_inversion_config(cfg, &tx_config);
if (ret < 0) {
return ret;
}
ret = esai_get_slot_format(bespoke->tdm_slot_width,
esai_cfg->word_width, &tx_config);
if (ret < 0) {
return ret;
}
tx_config.word_alignment = ESAI_WORD_ALIGNMENT(esai_cfg->word_width);
/* duplicate TX configuration */
memcpy(&rx_config, &tx_config, sizeof(tx_config));
/* parse clock configuration from DTS. This will overwrite
* directions set in bespoke data.
*/
ret = esai_parse_clock_config(esai_cfg, &tx_config, &rx_config);
if (ret < 0) {
return ret;
}
/* compute TX clock configuration */
ret = esai_get_clock_rate_config(bespoke->mclk_rate, bespoke->mclk_rate,
bespoke->bclk_rate,
!ESAI_PIN_IS_USED(data, ESAI_PIN_HCKT),
tx_config.bclk_dir,
&tx_config);
if (ret < 0) {
return ret;
}
/* compute RX clock configuration */
ret = esai_get_clock_rate_config(bespoke->mclk_rate, bespoke->mclk_rate,
bespoke->bclk_rate,
!ESAI_PIN_IS_USED(data, ESAI_PIN_HCKR),
rx_config.bclk_dir,
&rx_config);
if (ret < 0) {
return ret;
}
tx_config.watermark = esai_cfg->tx_fifo_watermark;
rx_config.watermark = esai_cfg->rx_fifo_watermark;
tx_config.slot_mask = bespoke->tx_slots;
rx_config.slot_mask = bespoke->rx_slots;
LOG_DBG("dumping TX configuration");
esai_dump_xceiver_config(&tx_config);
LOG_DBG("dumping RX configuration");
esai_dump_xceiver_config(&rx_config);
/* enable ESAI to allow committing the configurations */
ESAI_Enable(base, true);
esai_dump_register_data(base);
esai_commit_config(base, DAI_DIR_TX, &tx_config);
esai_commit_config(base, DAI_DIR_RX, &rx_config);
/* allow each TX data register to be initialized from TX FIFO */
base->TFCR |= ESAI_TFCR_TIEN_MASK;
/* enable FIFO usage
*
* TODO: for now, only 1 data line per direction is supported.
*/
esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_TX, BIT(0), true);
esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_RX, BIT(0), true);
/* re-connect pins based on DTS pin configuration */
base->PCRC = data->pcrc;
base->PRRC = data->prrc;
data->cfg.rate = bespoke->fsync_rate;
data->cfg.channels = bespoke->tdm_slots;
esai_dump_register_data(base);
return 0;
}
static int esai_config_get(const struct device *dev,
struct dai_config *cfg,
enum dai_dir dir)
{
struct esai_data *data = dev->data;
if (!cfg) {
return -EINVAL;
}
memcpy(cfg, &data->cfg, sizeof(*cfg));
return 0;
}
static int esai_trigger_start(const struct device *dev, enum dai_dir dir)
{
struct esai_data *data;
ESAI_Type *base;
int ret, i;
data = dev->data;
base = UINT_TO_ESAI(data->regmap);
ret = esai_update_state(data, dir, DAI_STATE_RUNNING);
if (ret < 0) {
LOG_ERR("failed to transition to RUNNING");
return -EINVAL;
}
LOG_DBG("starting direction %d", dir);
/* enable the FIFO */
esai_tx_rx_enable_disable_fifo(base, dir, true);
/* TODO: without this, the ESAI won't enter underrun
* but playing a song while doing pause-resume very
* fast seems to result in a degraded sound quality?
*
* TODO: for multiple channels, this needs to be changed.
*/
if (dir == DAI_DIR_TX) {
for (i = 0; i < 1; i++) {
ESAI_WriteData(base, 0x0);
}
}
/* enable the transmitter/receiver */
esai_tx_rx_enable_disable(base, dir, BIT(0), true);
return 0;
}
static int esai_trigger_stop(const struct device *dev, enum dai_dir dir)
{
struct esai_data *data;
int ret;
ESAI_Type *base;
data = dev->data;
base = UINT_TO_ESAI(data->regmap);
ret = esai_update_state(data, dir, DAI_STATE_STOPPING);
if (ret < 0) {
LOG_ERR("failed to transition to STOPPING");
return -EINVAL;
}
LOG_DBG("stopping direction %d", dir);
/* disable transmitter/receiver */
esai_tx_rx_enable_disable(base, dir, BIT(0), false);
/* disable FIFO */
esai_tx_rx_enable_disable_fifo(base, dir, false);
return 0;
}
static int esai_trigger(const struct device *dev,
enum dai_dir dir,
enum dai_trigger_cmd cmd)
{
/* TX/RX should be triggered individually */
if (dir != DAI_DIR_RX && dir != DAI_DIR_TX) {
LOG_ERR("invalid direction: %d", dir);
return -EINVAL;
}
switch (cmd) {
case DAI_TRIGGER_START:
return esai_trigger_start(dev, dir);
case DAI_TRIGGER_PAUSE:
case DAI_TRIGGER_STOP:
return esai_trigger_stop(dev, dir);
case DAI_TRIGGER_PRE_START:
case DAI_TRIGGER_COPY:
/* nothing to do here, return success code */
return 0;
default:
LOG_ERR("invalid trigger command: %d", cmd);
return -EINVAL;
}
return 0;
}
static const struct dai_properties
*esai_get_properties(const struct device *dev, enum dai_dir dir, int stream_id)
{
const struct esai_config *cfg = dev->config;
switch (dir) {
case DAI_DIR_RX:
return cfg->rx_props;
case DAI_DIR_TX:
return cfg->tx_props;
default:
LOG_ERR("invalid direction: %d", dir);
return NULL;
}
}
static int esai_probe(const struct device *dev)
{
/* nothing to be done here but mandatory to implement */
return 0;
}
static int esai_remove(const struct device *dev)
{
/* nothing to be done here but mandatory to implement */
return 0;
}
static const struct dai_driver_api esai_api = {
.config_set = esai_config_set,
.config_get = esai_config_get,
.trigger = esai_trigger,
.get_properties = esai_get_properties,
.probe = esai_probe,
.remove = esai_remove,
};
static int esai_init(const struct device *dev)
{
const struct esai_config *cfg;
struct esai_data *data;
int ret;
cfg = dev->config;
data = dev->data;
device_map(&data->regmap, cfg->regmap_phys, cfg->regmap_size, K_MEM_CACHE_NONE);
ESAI_Reset(UINT_TO_ESAI(data->regmap));
ret = esai_parse_pinmodes(cfg, data);
if (ret < 0) {
return ret;
}
return 0;
}
#define ESAI_INIT(inst) \
\
BUILD_ASSERT(ESAI_TX_FIFO_WATERMARK(inst) >= 1 && \
ESAI_TX_FIFO_WATERMARK(inst) <= _ESAI_FIFO_DEPTH(inst), \
"invalid TX watermark value"); \
\
BUILD_ASSERT(ESAI_RX_FIFO_WATERMARK(inst) >= 1 && \
ESAI_RX_FIFO_WATERMARK(inst) <= _ESAI_FIFO_DEPTH(inst), \
"invalid RX watermark value"); \
\
BUILD_ASSERT(ESAI_FIFO_DEPTH(inst) >= 1 && \
ESAI_FIFO_DEPTH(inst) <= _ESAI_FIFO_DEPTH(inst), \
"invalid FIFO depth value"); \
\
BUILD_ASSERT(ESAI_WORD_WIDTH(inst) == 8 || \
ESAI_WORD_WIDTH(inst) == 12 || \
ESAI_WORD_WIDTH(inst) == 16 || \
ESAI_WORD_WIDTH(inst) == 20 || \
ESAI_WORD_WIDTH(inst) == 24, \
"invalid word width value"); \
\
static const struct dai_properties esai_tx_props_##inst = { \
.fifo_address = ESAI_TX_FIFO_BASE(inst), \
.fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \
.dma_hs_id = ESAI_TX_RX_DMA_HANDSHAKE(inst, tx), \
}; \
\
static const struct dai_properties esai_rx_props_##inst = { \
.fifo_address = ESAI_RX_FIFO_BASE(inst), \
.fifo_depth = ESAI_FIFO_DEPTH(inst) * 4, \
.dma_hs_id = ESAI_TX_RX_DMA_HANDSHAKE(inst, rx), \
}; \
\
static uint32_t pinmodes_##inst[] = \
DT_INST_PROP_OR(inst, esai_pin_modes, {}); \
\
BUILD_ASSERT(ARRAY_SIZE(pinmodes_##inst) % 2 == 0, \
"bad pinmask array size"); \
\
static uint32_t clock_cfg_##inst[] = \
DT_INST_PROP_OR(inst, esai_clock_configuration, {}); \
\
BUILD_ASSERT(ARRAY_SIZE(clock_cfg_##inst) % 2 == 0, \
"bad clock configuration array size"); \
\
static struct esai_config esai_config_##inst = { \
.regmap_phys = DT_INST_REG_ADDR(inst), \
.regmap_size = DT_INST_REG_SIZE(inst), \
.tx_props = &esai_tx_props_##inst, \
.rx_props = &esai_rx_props_##inst, \
.tx_fifo_watermark = ESAI_TX_FIFO_WATERMARK(inst), \
.rx_fifo_watermark = ESAI_RX_FIFO_WATERMARK(inst), \
.word_width = ESAI_WORD_WIDTH(inst), \
.pinmodes = pinmodes_##inst, \
.pinmodes_size = ARRAY_SIZE(pinmodes_##inst), \
.clock_cfg = clock_cfg_##inst, \
.clock_cfg_size = ARRAY_SIZE(clock_cfg_##inst), \
}; \
\
static struct esai_data esai_data_##inst = { \
.cfg.type = DAI_IMX_ESAI, \
.cfg.dai_index = DT_INST_PROP_OR(inst, dai_index, 0), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &esai_init, NULL, \
&esai_data_##inst, &esai_config_##inst, \
POST_KERNEL, CONFIG_DAI_INIT_PRIORITY, \
&esai_api); \
DT_INST_FOREACH_STATUS_OKAY(ESAI_INIT);
``` | /content/code_sandbox/drivers/dai/nxp/esai/esai.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,392 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_
#define ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_
#include <zephyr/logging/log.h>
#include <zephyr/drivers/dai.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/dai/esai.h>
#include <fsl_esai.h>
LOG_MODULE_REGISTER(nxp_dai_esai);
/* used for binding the driver */
#define DT_DRV_COMPAT nxp_dai_esai
/* workaround the fact that device_map() doesn't exist for SoCs with no MMU */
#ifndef DEVICE_MMIO_IS_IN_RAM
#define device_map(virt, phys, size, flags) *(virt) = (phys)
#endif /* DEVICE_MMIO_IS_IN_RAM */
/* macros used for parsing DTS data */
#define _ESAI_FIFO_DEPTH(inst)\
FSL_FEATURE_ESAI_FIFO_SIZEn(UINT_TO_ESAI(DT_INST_REG_ADDR(inst)))
/* used to fetch the depth of the FIFO. If the "fifo-depth" property is
* not specified, the FIFO depth that will be reported to the upper layers
* will be 128 * 4 (which is the maximum value, or, well, the actual FIFO
* depth)
*/
#define ESAI_FIFO_DEPTH(inst)\
DT_INST_PROP_OR(inst, fifo_depth, _ESAI_FIFO_DEPTH(inst))
/* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
* property is not specified, this will be set to half of the FIFO depth.
*/
#define ESAI_TX_FIFO_WATERMARK(inst)\
DT_INST_PROP_OR(inst, tx_fifo_watermark, (_ESAI_FIFO_DEPTH(inst) / 2))
/* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
* property is not specified, this will be set to half of the FIFO depth.
*/
#define ESAI_RX_FIFO_WATERMARK(inst)\
DT_INST_PROP_OR(inst, rx_fifo_watermark, (_ESAI_FIFO_DEPTH(inst) / 2))
/* use to fetch the handshake value for a given direction. The handshake
* is computed as follows:
* handshake = CHANNEL_ID | (MUX_VALUE << 8)
* The channel ID and MUX value are each encoded in 8 bits.
*/
#define ESAI_TX_RX_DMA_HANDSHAKE(inst, dir)\
((DT_INST_DMAS_CELL_BY_NAME(inst, dir, channel) & GENMASK(7, 0)) |\
((DT_INST_DMAS_CELL_BY_NAME(inst, dir, mux) << 8) & GENMASK(15, 8)))
/* used to fetch the word width. If the "word-width" property is not specified,
* this will default to 24.
*/
#define ESAI_WORD_WIDTH(inst) DT_INST_PROP_OR(inst, word_width, 24)
/* utility macros */
/* convert uint to ESAI_Type * */
#define UINT_TO_ESAI(x) ((ESAI_Type *)(uintptr_t)(x))
/* invert a clock's polarity. This works because a clock's polarity
* is expressed as a 0 or as a 1.
*/
#define ESAI_INVERT_POLARITY(polarity) (polarity) = !(polarity)
#define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4))
/* used to check if a slot/word width combination is valid */
#define ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width, word_width)\
(_ESAI_SLOT_WORD_WIDTH_IS_VALID(slot_width) && \
_ESAI_SLOT_WORD_WIDTH_IS_VALID(word_width) && \
((word_width) < 32) && ((word_width) <= (slot_width)))
/* used to convert slot/word width combination to a value that can be written
* to TCR's TSWS or RCR's RSWS.
*/
#define ESAI_SLOT_FORMAT(s, w)\
((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f))
/* used to compute the word alignment based on the word width value.
* This returns a value that can be written to TFCR's TWA or RFCR's
* RWA.
*/
#define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4)
#define _ESAI_RX_FIFO_USAGE_EN(mask)\
(((mask) << ESAI_RFCR_RE0_SHIFT) &\
(ESAI_RFCR_RE0_MASK | ESAI_RFCR_RE1_MASK |\
ESAI_RFCR_RE2_MASK | ESAI_RFCR_RE3_MASK))
#define _ESAI_TX_FIFO_USAGE_EN(mask)\
(((mask) << ESAI_TFCR_TE0_SHIFT) &\
(ESAI_TFCR_TE0_MASK | ESAI_TFCR_TE1_MASK | ESAI_TFCR_TE2_MASK |\
ESAI_TFCR_TE3_MASK | ESAI_TFCR_TE4_MASK | ESAI_TFCR_TE5_MASK))
/* used to fetch the mask for setting TX/RX FIFO usage. By FIFO usage
* we mean we allow receivers/transmitters to use the "global" TX/RX
* FIFO (i.e: the FIFO that's common to all transmitters/receivers).
* More specifically, this macro returns the mask required for setting
* TFCR's TEx fields or RFCR's REx fields.
*/
#define ESAI_TX_RX_FIFO_USAGE_EN(dir, mask)\
((dir) == DAI_DIR_TX ? _ESAI_TX_FIFO_USAGE_EN(mask) :\
_ESAI_RX_FIFO_USAGE_EN(mask))
#define _ESAI_TX_EN(mask)\
(((mask) << ESAI_TCR_TE0_SHIFT) &\
(ESAI_TCR_TE0_MASK | ESAI_TCR_TE1_MASK | ESAI_TCR_TE2_MASK |\
ESAI_TCR_TE3_MASK | ESAI_TCR_TE4_MASK | ESAI_TCR_TE5_MASK))
#define _ESAI_RX_EN(mask)\
(((mask) << ESAI_RCR_RE0_SHIFT) &\
(ESAI_RCR_RE0_MASK | ESAI_RCR_RE1_MASK | ESAI_RCR_RE2_MASK |\
ESAI_RCR_RE3_MASK))
/* used to fetch the mask for enabling transmitters/receivers.
* More specifically, this refers to TCR's TEx bits or RCR's REx
* bits.
*/
#define ESAI_TX_RX_EN(dir, mask)\
((dir) == DAI_DIR_TX ? _ESAI_TX_EN(mask) : _ESAI_RX_EN(mask))
/* used to fetch the base address of the TX FIFO */
#define ESAI_TX_FIFO_BASE(inst)\
POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ETDR))
/* used to fetch the base address of the RX FIFO */
#define ESAI_RX_FIFO_BASE(inst)\
POINTER_TO_UINT(&(UINT_TO_ESAI(DT_INST_REG_ADDR(inst))->ERDR))
/* used to check if an ESAI pin is used. An ESAI pin is considered to
* be used if PDC and PC bits for that pin are set (i.e: pin is in ESAI
* mode).
*
* The ESAI pins support 4 functionalities which can be configured
* via PCRC and PRRC:
* 1) Disconnected
* 2) GPIO input
* 3) GPIO output
* 4) ESAI
*/
#define ESAI_PIN_IS_USED(data, which)\
(((data)->pcrc & BIT(which)) && ((data->prrc) & BIT(which)))
struct esai_data {
mm_reg_t regmap;
struct dai_config cfg;
/* transmitter state */
enum dai_state tx_state;
/* receiver state */
enum dai_state rx_state;
/* value to be committed to PRRC. This is computed
* during esai_init() and committed during config_set()
* stage.
*/
uint32_t prrc;
/* value to be committed to PCRC. Computed and committed
* during the same stages as PRRC.
*/
uint32_t pcrc;
};
struct esai_config {
uint32_t regmap_phys;
uint32_t regmap_size;
const struct dai_properties *tx_props;
const struct dai_properties *rx_props;
uint32_t rx_fifo_watermark;
uint32_t tx_fifo_watermark;
uint32_t word_width;
uint32_t *pinmodes;
uint32_t pinmodes_size;
uint32_t *clock_cfg;
uint32_t clock_cfg_size;
};
/* this needs to perfectly match SOF's struct sof_ipc_dai_esai_params */
struct esai_bespoke_config {
uint32_t reserved0;
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_direction;
/* clock-related data */
uint32_t mclk_rate;
uint32_t fsync_rate;
uint32_t bclk_rate;
/* TDM-related data */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
uint16_t tdm_slot_width;
uint16_t reserved2;
};
struct esai_transceiver_config {
/* enable/disable the HCLK prescaler */
bool hclk_prescaler_en;
/* controls the divison value of HCLK (i.e: TPM0-TPM7) */
uint32_t hclk_div_ratio;
/* controls the division value of HCLK before reaching
* BCLK consumers (i.e: TFP0-TFP3)
*/
uint32_t bclk_div_ratio;
/* should the HCLK divison be bypassed or not?
* If in bypass, HCLK pad will be the same as EXTAL
*/
bool hclk_bypass;
/* HCLK direction - input or output */
esai_clock_direction_t hclk_dir;
/* HCLK source - EXTAL or IPG clock */
esai_hclk_source_t hclk_src;
/* HCLK polarity - LOW or HIGH */
esai_clock_polarity_t hclk_polarity;
/* BCLK direction - input or output */
esai_clock_direction_t bclk_dir;
/* BCLK polarity - LOW or HIGH */
esai_clock_polarity_t bclk_polarity;
/* FSYNC direction - input or output */
esai_clock_direction_t fsync_dir;
/* FSYNC polarity - LOW or HIGH */
esai_clock_polarity_t fsync_polarity;
/* should FSYNC be bit-wide or word-wide? */
bool fsync_is_bit_wide;
/* enable/disable padding word with zeros. If
* disabled, pad will be done using last/first
* bit - see TCR's PADC bit for more info.
*/
bool zero_pad_en;
/* should FSYNC be asserted before MSB transmission
* or alongside it?
*/
bool fsync_early;
/* FSYNC divison value - for network mode this is
* the same as the number of slots - 1.
*/
uint32_t fsync_div;
/* slot format - see TCR's TSWS or RCR's RSWS */
esai_slot_format_t slot_format;
/* mode - network or normal
* TODO: at the moment, only network mode is supported.
*/
esai_mode_t mode;
/* controls whether MSB or LSB is transmitted first */
esai_shift_direction_t data_order;
/* controls the word alignment inside a slot. If enabled
* word is left-aligned, otherwise it will be right-aligned.
* For details, see TCR/RCR's TWA/RWA.
*/
bool data_left_aligned;
/* TX/RX watermark value */
uint32_t watermark;
/* concatenation of TSMA+TSMB/RSMA+RSMB. Controls which
* slots should be High-Z or data.
*/
uint32_t slot_mask;
/* controls the alignment of data written to FIFO.
* See TFCR's TWA or RFCR's RWA for more details.
*/
uint32_t word_alignment;
};
static int esai_parse_clock_config(const struct esai_config *cfg,
struct esai_transceiver_config *tx_cfg,
struct esai_transceiver_config *rx_cfg)
{
int i;
uint32_t crt_clock, crt_dir;
for (i = 0; i < cfg->clock_cfg_size; i += 2) {
crt_clock = cfg->clock_cfg[i];
crt_dir = cfg->clock_cfg[i + 1];
/* sanity checks */
if (crt_clock > ESAI_CLOCK_FST) {
LOG_ERR("invalid clock configuration ID: %d", crt_clock);
return -EINVAL;
}
if (crt_dir > ESAI_CLOCK_OUTPUT) {
LOG_ERR("invalid clock configuration direction: %d", crt_dir);
return -EINVAL;
}
switch (crt_clock) {
case ESAI_CLOCK_HCKT:
tx_cfg->hclk_dir = crt_dir;
break;
case ESAI_CLOCK_HCKR:
rx_cfg->hclk_dir = crt_dir;
break;
case ESAI_CLOCK_SCKT:
tx_cfg->bclk_dir = crt_dir;
break;
case ESAI_CLOCK_SCKR:
rx_cfg->bclk_dir = crt_dir;
break;
case ESAI_CLOCK_FST:
tx_cfg->fsync_dir = crt_dir;
break;
case ESAI_CLOCK_FSR:
rx_cfg->fsync_dir = crt_dir;
break;
}
}
return 0;
}
static int esai_parse_pinmodes(const struct esai_config *cfg,
struct esai_data *data)
{
int i;
uint32_t pin, pin_mode;
/* initially, the assumption is that all pins are in ESAI mode */
data->pcrc = ESAI_PCRC_PC_MASK;
data->prrc = ESAI_PRRC_PDC_MASK;
for (i = 0; i < cfg->pinmodes_size; i += 2) {
pin = cfg->pinmodes[i];
pin_mode = cfg->pinmodes[i + 1];
if (pin > ESAI_PIN_SDO0 || pin_mode > ESAI_PIN_ESAI) {
return -EINVAL;
}
switch (pin_mode) {
case ESAI_PIN_DISCONNECTED:
data->pcrc &= ~BIT(pin);
data->prrc &= ~BIT(pin);
break;
case ESAI_PIN_GPIO_INPUT:
data->pcrc &= ~BIT(pin);
break;
case ESAI_PIN_GPIO_OUTPUT:
data->prrc &= ~BIT(pin);
break;
case ESAI_PIN_ESAI:
/* nothing to be done here, this is the default */
break;
}
}
return 0;
}
static inline uint32_t esai_get_state(struct esai_data *data,
enum dai_dir dir)
{
if (dir == DAI_DIR_RX) {
return data->rx_state;
} else {
return data->tx_state;
}
}
static inline int esai_update_state(struct esai_data *data,
enum dai_dir dir, enum dai_state new_state)
{
enum dai_state old_state = esai_get_state(data, dir);
LOG_DBG("attempting state transition from %d to %d", old_state, new_state);
switch (new_state) {
case DAI_STATE_NOT_READY:
/* initial state, transition is not possible */
return -EPERM;
case DAI_STATE_READY:
if (old_state != DAI_STATE_NOT_READY &&
old_state != DAI_STATE_READY &&
old_state != DAI_STATE_STOPPING) {
return -EPERM;
}
break;
case DAI_STATE_RUNNING:
if (old_state != DAI_STATE_STOPPING &&
old_state != DAI_STATE_READY) {
return -EPERM;
}
break;
case DAI_STATE_STOPPING:
if (old_state != DAI_STATE_RUNNING) {
return -EPERM;
}
break;
default:
LOG_ERR("invalid new state: %d", new_state);
return -EINVAL;
}
if (dir == DAI_DIR_RX) {
data->rx_state = new_state;
} else {
data->tx_state = new_state;
}
return 0;
}
static inline void esai_tx_rx_enable_disable_fifo(ESAI_Type *base,
enum dai_dir dir,
bool enable)
{
if (enable) {
if (dir == DAI_DIR_RX) {
base->RFCR |= ESAI_RFCR_RFE_MASK;
} else {
base->TFCR |= ESAI_TFCR_TFE_MASK;
}
} else {
if (dir == DAI_DIR_RX) {
base->RFCR &= ~ESAI_RFCR_RFE_MASK;
} else {
base->TFCR &= ~ESAI_TFCR_TFE_MASK;
}
}
}
static inline void esai_tx_rx_enable_disable(ESAI_Type *base,
enum dai_dir dir,
uint32_t which, bool enable)
{
uint32_t val = ESAI_TX_RX_EN(dir, which);
if (enable) {
if (dir == DAI_DIR_RX) {
base->RCR |= val;
} else {
base->TCR |= val;
}
} else {
if (dir == DAI_DIR_RX) {
base->RCR &= ~val;
} else {
base->TCR &= ~val;
}
}
}
static inline void esai_tx_rx_enable_disable_fifo_usage(ESAI_Type *base,
enum dai_dir dir,
uint32_t which, bool enable)
{
uint32_t val = ESAI_TX_RX_FIFO_USAGE_EN(dir, which);
if (enable) {
if (dir == DAI_DIR_RX) {
base->RFCR |= val;
} else {
base->TFCR |= val;
}
} else {
if (dir == DAI_DIR_RX) {
base->RFCR &= ~val;
} else {
base->TFCR &= ~val;
}
}
}
static inline void esai_dump_xceiver_config(struct esai_transceiver_config *cfg)
{
LOG_DBG("HCLK prescaler enable: %d", cfg->hclk_prescaler_en);
LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio);
LOG_DBG("BCLK divider ratio: %d", cfg->bclk_div_ratio);
LOG_DBG("HCLK bypass: %d", cfg->hclk_bypass);
LOG_DBG("HCLK direction: %d", cfg->hclk_dir);
LOG_DBG("HCLK source: %d", cfg->hclk_src);
LOG_DBG("HCLK polarity: %d", cfg->hclk_polarity);
LOG_DBG("BCLK direction: %d", cfg->bclk_dir);
LOG_DBG("BCLK polarity: %d", cfg->bclk_polarity);
LOG_DBG("FSYNC direction: %d", cfg->fsync_dir);
LOG_DBG("FSYNC polarity: %d", cfg->fsync_polarity);
LOG_DBG("FSYNC is bit wide: %d", cfg->fsync_is_bit_wide);
LOG_DBG("zero pad enable: %d", cfg->zero_pad_en);
LOG_DBG("FSYNC asserted early: %d", cfg->fsync_early);
LOG_DBG("watermark: %d", cfg->watermark);
LOG_DBG("slot mask: 0x%x", cfg->slot_mask);
LOG_DBG("word alignment: 0x%x", cfg->word_alignment);
}
static inline void esai_dump_register_data(ESAI_Type *base)
{
LOG_DBG("ECR: 0x%x", base->ECR);
LOG_DBG("ESR: 0x%x", base->ESR);
LOG_DBG("TFCR: 0x%x", base->TFCR);
LOG_DBG("TFSR: 0x%x", base->TFSR);
LOG_DBG("RFCR: 0x%x", base->RFCR);
LOG_DBG("RFSR: 0x%x", base->RFSR);
LOG_DBG("TSR: 0x%x", base->TSR);
LOG_DBG("SAISR: 0x%x", base->SAISR);
LOG_DBG("SAICR: 0x%x", base->SAICR);
LOG_DBG("TCR: 0x%x", base->TCR);
LOG_DBG("TCCR: 0x%x", base->TCCR);
LOG_DBG("RCR: 0x%x", base->RCR);
LOG_DBG("RCCR: 0x%x", base->RCCR);
LOG_DBG("TSMA: 0x%x", base->TSMA);
LOG_DBG("TSMB: 0x%x", base->TSMB);
LOG_DBG("RSMA: 0x%x", base->RSMA);
LOG_DBG("RSMB: 0x%x", base->RSMB);
LOG_DBG("PRRC: 0x%x", base->PRRC);
LOG_DBG("PCRC: 0x%x", base->PCRC);
}
#endif /* ZEPHYR_DRIVERS_DAI_NXP_ESAI_H_ */
``` | /content/code_sandbox/drivers/dai/nxp/esai/esai.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,544 |
```unknown
config DAI_NXP_SAI
bool "NXP Synchronous Audio Interface (SAI) driver"
default y
depends on DT_HAS_NXP_DAI_SAI_ENABLED
select PINCTRL
help
Select this to enable NXP SAI driver.
if DAI_NXP_SAI
config SAI_HAS_MCLK_CONFIG_OPTION
bool "Set if SAI has MCLK configuration options"
default n
help
Select this if the SAI IP allows configuration
of the master clock. Master clock configuration
refers to enabling/disabling the master clock,
setting the signal as input or output or dividing
the master clock output.
config SAI_FIFO_WORD_SIZE
int "Size (in bytes) of a FIFO word"
default 4
help
Use this to set the size (in bytes) of a SAI
FIFO word.
config SAI_IMX93_ERRATA_051421
bool "Set if your SAI IP version is affected by i.MX93's ERRATA 051421"
default n
help
Select this if your SAI ip version is affected by
i.MX93's ERRATA 051421. The errata states that if
the SAI is FSYNC/BCLK master, one of the directions
is SYNC with the other, and the ASYNC direction has
the BYP bit toggled, the SYNC direction's BCLK won't
be generated properly.
endif # DAI_NXP_SAI
``` | /content/code_sandbox/drivers/dai/nxp/sai/Kconfig.sai | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 323 |
```objective-c
*
*/
#ifndef ZEPHYR_DRIVERS_DAI_NXP_SAI_H_
#define ZEPHYR_DRIVERS_DAI_NXP_SAI_H_
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <fsl_sai.h>
LOG_MODULE_REGISTER(nxp_dai_sai);
#ifdef CONFIG_SAI_HAS_MCLK_CONFIG_OPTION
#define SAI_MCLK_MCR_MSEL_SHIFT 24
#define SAI_MCLK_MCR_MSEL_MASK GENMASK(24, 25)
#endif /* CONFIG_SAI_HAS_MCLK_CONFIG_OPTION */
/* workaround the fact that device_map() doesn't exist for SoCs with no MMU */
#ifndef DEVICE_MMIO_IS_IN_RAM
#define device_map(virt, phys, size, flags) *(virt) = (phys)
#endif /* DEVICE_MMIO_IS_IN_RAM */
/* used to convert an uint to I2S_Type * */
#define UINT_TO_I2S(x) ((I2S_Type *)(uintptr_t)(x))
/* macros used for parsing DTS data */
/* used instead of IDENTITY because LISTIFY expects the used macro function
* to also take a variable number of arguments.
*/
#define IDENTITY_VARGS(V, ...) IDENTITY(V)
/* used to generate the list of clock indexes */
#define _SAI_CLOCK_INDEX_ARRAY(inst)\
LISTIFY(DT_INST_PROP_LEN_OR(inst, clocks, 0), IDENTITY_VARGS, (,))
/* used to retrieve a clock's ID using its index generated via _SAI_CLOCK_INDEX_ARRAY */
#define _SAI_GET_CLOCK_ID(clock_idx, inst)\
DT_INST_CLOCKS_CELL_BY_IDX(inst, clock_idx, name)
/* used to retrieve a clock's name using its index generated via _SAI_CLOCK_INDEX_ARRAY */
#define _SAI_GET_CLOCK_NAME(clock_idx, inst)\
DT_INST_PROP_BY_IDX(inst, clock_names, clock_idx)
/* used to convert the clocks property into an array of clock IDs */
#define _SAI_CLOCK_ID_ARRAY(inst)\
FOR_EACH_FIXED_ARG(_SAI_GET_CLOCK_ID, (,), inst, _SAI_CLOCK_INDEX_ARRAY(inst))
/* used to convert the clock-names property into an array of clock names */
#define _SAI_CLOCK_NAME_ARRAY(inst)\
FOR_EACH_FIXED_ARG(_SAI_GET_CLOCK_NAME, (,), inst, _SAI_CLOCK_INDEX_ARRAY(inst))
/* used to convert a clocks property into an array of clock IDs. If the property
* is not specified then this macro will return {}.
*/
#define _SAI_GET_CLOCK_ARRAY(inst)\
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, nxp_dai_sai), clocks),\
({ _SAI_CLOCK_ID_ARRAY(inst) }),\
({ }))
/* used to retrieve a const struct device *dev pointing to the clock controller.
* It is assumed that all SAI clocks come from a single clock provider.
* This macro returns a NULL if the clocks property doesn't exist.
*/
#define _SAI_GET_CLOCK_CONTROLLER(inst)\
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, nxp_dai_sai), clocks),\
(DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst))),\
(NULL))
/* used to convert a clock-names property into an array of clock names. If the
* property is not specified then this macro will return {}.
*/
#define _SAI_GET_CLOCK_NAMES(inst)\
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, nxp_dai_sai), clocks),\
({ _SAI_CLOCK_NAME_ARRAY(inst) }),\
({ }))
/* used to declare a struct clock_data */
#define SAI_CLOCK_DATA_DECLARE(inst) \
{ \
.clocks = (uint32_t [])_SAI_GET_CLOCK_ARRAY(inst), \
.clock_num = DT_INST_PROP_LEN_OR(inst, clocks, 0), \
.dev = _SAI_GET_CLOCK_CONTROLLER(inst), \
.clock_names = (const char *[])_SAI_GET_CLOCK_NAMES(inst), \
}
/* used to parse the tx-fifo-watermark property. If said property is not
* specified then this macro will return half of the number of words in the
* FIFO.
*/
#define SAI_TX_FIFO_WATERMARK(inst)\
DT_INST_PROP_OR(inst, tx_fifo_watermark,\
FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2)
/* used to parse the rx-fifo-watermark property. If said property is not
* specified then this macro will return half of the number of words in the
* FIFO.
*/
#define SAI_RX_FIFO_WATERMARK(inst)\
DT_INST_PROP_OR(inst, rx_fifo_watermark,\
FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2)
/* used to retrieve TDR0's address based on SAI's physical address */
#define SAI_TX_FIFO_BASE(inst, idx)\
POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[idx]))
/* used to retrieve RDR0's address based on SAI's physical address */
#define SAI_RX_FIFO_BASE(inst, idx)\
POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[idx]))
/* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */
#define _SAI_FIFO_DEPTH(inst)\
FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)))
/* used to retrieve the TX/RX FIFO's size (in FIFO words) */
#define SAI_FIFO_DEPTH(inst)\
DT_INST_PROP_OR(inst, fifo_depth, _SAI_FIFO_DEPTH(inst))
/* used to retrieve the DMA MUX for transmitter */
#define SAI_TX_DMA_MUX(inst)\
FSL_FEATURE_SAI_TX_DMA_MUXn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)))
/* used to retrieve the DMA MUX for receiver */
#define SAI_RX_DMA_MUX(inst)\
FSL_FEATURE_SAI_RX_DMA_MUXn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)))
/* used to retrieve the synchronization mode of the transmitter. If this
* property is not specified, ASYNC mode will be used.
*/
#define SAI_TX_SYNC_MODE(inst)\
DT_INST_PROP_OR(inst, tx_sync_mode, kSAI_ModeAsync)
/* used to retrieve the synchronization mode of the receiver. If this property
* is not specified, ASYNC mode will be used.
*/
#define SAI_RX_SYNC_MODE(inst)\
DT_INST_PROP_OR(inst, rx_sync_mode, kSAI_ModeAsync)
/* used to retrieve the handshake value for given direction. The handshake
* is computed as follows:
* handshake = CHANNEL_ID | (MUX_VALUE << 8)
* The channel ID and MUX value are each encoded in 8 bits.
*/
#define SAI_TX_RX_DMA_HANDSHAKE(inst, dir)\
((DT_INST_DMAS_CELL_BY_NAME(inst, dir, channel) & GENMASK(7, 0)) |\
((DT_INST_DMAS_CELL_BY_NAME(inst, dir, mux) << 8) & GENMASK(15, 8)))
/* used to retrieve the number of supported transmission/receive lines */
#define SAI_DLINE_COUNT(inst)\
FSL_FEATURE_SAI_CHANNEL_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst)))
/* used to retrieve the index of the transmission line */
#define SAI_TX_DLINE_INDEX(inst) DT_INST_PROP_OR(inst, tx_dataline, 0)
/* used to retrieve the index of the receive line */
#define SAI_RX_DLINE_INDEX(inst) DT_INST_PROP_OR(inst, rx_dataline, 0)
/* utility macros */
/* invert a clock's polarity. This works because a clock's polarity is expressed
* as a 0 or as a 1.
*/
#define SAI_INVERT_POLARITY(polarity) (polarity) = !(polarity)
/* used to issue a software reset of the transmitter/receiver */
#define SAI_TX_RX_SW_RESET(dir, regmap)\
((dir) == DAI_DIR_RX ? SAI_RxSoftwareReset(UINT_TO_I2S(regmap), kSAI_ResetTypeSoftware) :\
SAI_TxSoftwareReset(UINT_TO_I2S(regmap), kSAI_ResetTypeSoftware))
/* used to enable/disable the transmitter/receiver.
* When enabling the SYNC component, the ASYNC component will also be enabled.
* Attempting to disable the SYNC component will fail unless the SYNC bit is
* cleared. It is recommended to use sai_tx_rx_force_disable() instead of this
* macro when disabling transmitter/receiver.
*/
#define SAI_TX_RX_ENABLE_DISABLE(dir, regmap, enable)\
((dir) == DAI_DIR_RX ? SAI_RxEnable(UINT_TO_I2S(regmap), enable) :\
SAI_TxEnable(UINT_TO_I2S(regmap), enable))
/* used to enable/disable the DMA requests for transmitter/receiver */
#define SAI_TX_RX_DMA_ENABLE_DISABLE(dir, regmap, enable)\
((dir) == DAI_DIR_RX ? SAI_RxEnableDMA(UINT_TO_I2S(regmap),\
kSAI_FIFORequestDMAEnable, enable) :\
SAI_TxEnableDMA(UINT_TO_I2S(regmap), kSAI_FIFORequestDMAEnable, enable))
/* used to check if the hardware transmitter/receiver is enabled */
#define SAI_TX_RX_IS_HW_ENABLED(dir, regmap)\
((dir) == DAI_DIR_RX ? (UINT_TO_I2S(regmap)->RCSR & I2S_RCSR_RE_MASK) : \
(UINT_TO_I2S(regmap)->TCSR & I2S_TCSR_TE_MASK))
/* used to enable various transmitter/receiver interrupts */
#define _SAI_TX_RX_ENABLE_IRQ(dir, regmap, which)\
((dir) == DAI_DIR_RX ? SAI_RxEnableInterrupts(UINT_TO_I2S(regmap), which) : \
SAI_TxEnableInterrupts(UINT_TO_I2S(regmap), which))
/* used to disable various transmitter/receiver interrupts */
#define _SAI_TX_RX_DISABLE_IRQ(dir, regmap, which)\
((dir) == DAI_DIR_RX ? SAI_RxDisableInterrupts(UINT_TO_I2S(regmap), which) : \
SAI_TxDisableInterrupts(UINT_TO_I2S(regmap), which))
/* used to enable/disable various transmitter/receiver interrupts */
#define SAI_TX_RX_ENABLE_DISABLE_IRQ(dir, regmap, which, enable)\
((enable == true) ? _SAI_TX_RX_ENABLE_IRQ(dir, regmap, which) :\
_SAI_TX_RX_DISABLE_IRQ(dir, regmap, which))
/* used to check if a status flag is set */
#define SAI_TX_RX_STATUS_IS_SET(dir, regmap, which)\
((dir) == DAI_DIR_RX ? ((UINT_TO_I2S(regmap))->RCSR & (which)) : \
((UINT_TO_I2S(regmap))->TCSR & (which)))
/* used to retrieve the SYNC direction. Use this macro when you know for sure
* you have 1 SYNC direction with 1 ASYNC direction.
*/
#define SAI_TX_RX_GET_SYNC_DIR(cfg)\
((cfg)->tx_sync_mode == kSAI_ModeSync ? DAI_DIR_TX : DAI_DIR_RX)
/* used to retrieve the ASYNC direction. Use this macro when you know for sure
* you have 1 SYNC direction with 1 ASYNC direction.
*/
#define SAI_TX_RX_GET_ASYNC_DIR(cfg)\
((cfg)->tx_sync_mode == kSAI_ModeAsync ? DAI_DIR_TX : DAI_DIR_RX)
/* used to check if transmitter/receiver is SW enabled */
#define SAI_TX_RX_DIR_IS_SW_ENABLED(dir, data)\
((dir) == DAI_DIR_TX ? data->tx_enabled : data->rx_enabled)
/* used to compute the mask for the transmission/receive lines based on
* the index passed from the DTS.
*/
#define SAI_TX_RX_DLINE_MASK(dir, cfg)\
((dir) == DAI_DIR_TX ? BIT((cfg)->tx_dline) : BIT((cfg)->rx_dline))
struct sai_clock_data {
uint32_t *clocks;
uint32_t clock_num;
/* assumption: all clocks belong to the same producer */
const struct device *dev;
const char **clock_names;
};
struct sai_data {
mm_reg_t regmap;
sai_transceiver_t rx_config;
sai_transceiver_t tx_config;
bool tx_enabled;
bool rx_enabled;
enum dai_state tx_state;
enum dai_state rx_state;
struct dai_config cfg;
};
struct sai_config {
uint32_t regmap_phys;
uint32_t regmap_size;
struct sai_clock_data clk_data;
bool mclk_is_output;
/* if the tx/rx-fifo-watermark properties are not specified, it's going
* to be assumed that the watermark should be set to half of the FIFO
* size.
*/
uint32_t rx_fifo_watermark;
uint32_t tx_fifo_watermark;
const struct dai_properties *tx_props;
const struct dai_properties *rx_props;
uint32_t dai_index;
/* RX synchronization mode - may be SYNC or ASYNC */
sai_sync_mode_t rx_sync_mode;
/* TX synchronization mode - may be SYNC or ASYNC */
sai_sync_mode_t tx_sync_mode;
void (*irq_config)(void);
uint32_t tx_dline;
uint32_t rx_dline;
const struct pinctrl_dev_config *pincfg;
};
/* this needs to perfectly match SOF's struct sof_ipc_dai_sai_params */
struct sai_bespoke_config {
uint32_t reserved0;
uint16_t reserved1;
uint16_t mclk_id;
uint32_t mclk_direction;
/* CLOCK-related data */
uint32_t mclk_rate;
uint32_t fsync_rate;
uint32_t bclk_rate;
/* TDM-related data */
uint32_t tdm_slots;
uint32_t rx_slots;
uint32_t tx_slots;
uint16_t tdm_slot_width;
uint16_t reserved2;
};
#ifdef CONFIG_SAI_HAS_MCLK_CONFIG_OPTION
static int get_msel(sai_bclk_source_t bclk_source, uint32_t *msel)
{
switch (bclk_source) {
case kSAI_BclkSourceMclkOption1:
*msel = 0;
break;
case kSAI_BclkSourceMclkOption2:
*msel = (0x2 << SAI_MCLK_MCR_MSEL_SHIFT);
break;
case kSAI_BclkSourceMclkOption3:
*msel = (0x3 << SAI_MCLK_MCR_MSEL_SHIFT);
break;
default:
return -EINVAL;
}
return 0;
}
static void set_msel(uint32_t regmap, int msel)
{
UINT_TO_I2S(regmap)->MCR &= ~SAI_MCLK_MCR_MSEL_MASK;
UINT_TO_I2S(regmap)->MCR |= msel;
}
static int clk_lookup_by_name(const struct sai_clock_data *clk_data, char *name)
{
int i;
for (i = 0; i < clk_data->clock_num; i++) {
if (!strcmp(name, clk_data->clock_names[i])) {
return i;
}
}
return -EINVAL;
}
static int get_mclk_rate(const struct sai_clock_data *clk_data,
sai_bclk_source_t bclk_source,
uint32_t *rate)
{
int clk_idx;
char *clk_name;
switch (bclk_source) {
case kSAI_BclkSourceMclkOption1:
clk_name = "mclk1";
break;
case kSAI_BclkSourceMclkOption2:
clk_name = "mclk2";
break;
case kSAI_BclkSourceMclkOption3:
clk_name = "mclk3";
break;
default:
LOG_ERR("invalid bitclock source: %d", bclk_source);
return -EINVAL;
}
clk_idx = clk_lookup_by_name(clk_data, clk_name);
if (clk_idx < 0) {
LOG_ERR("failed to get clock index for %s", clk_name);
return clk_idx;
}
return clock_control_get_rate(clk_data->dev,
UINT_TO_POINTER(clk_data->clocks[clk_idx]),
rate);
}
#endif /* CONFIG_SAI_HAS_MCLK_CONFIG_OPTION */
static inline void get_bclk_default_config(sai_bit_clock_t *cfg)
{
memset(cfg, 0, sizeof(sai_bit_clock_t));
/* by default, BCLK has the following properties:
*
* 1) BCLK is active HIGH.
* 2) BCLK uses MCLK1 source. (only applicable to master mode)
* 3) No source swap.
* 4) No input delay.
*/
cfg->bclkPolarity = kSAI_PolarityActiveHigh;
cfg->bclkSource = kSAI_BclkSourceMclkOption1;
}
static inline void get_fsync_default_config(sai_frame_sync_t *cfg)
{
memset(cfg, 0, sizeof(sai_frame_sync_t));
/* by default, FSYNC has the following properties:
*
* 1) FSYNC is asserted one bit early with respect to the next
* frame.
* 2) FSYNC is active HIGH.
*/
cfg->frameSyncEarly = true;
cfg->frameSyncPolarity = kSAI_PolarityActiveHigh;
}
static inline void get_serial_default_config(sai_serial_data_t *cfg)
{
memset(cfg, 0, sizeof(sai_serial_data_t));
/* by default, the serial configuration has the following quirks:
*
* 1) Data pin is not tri-stated.
* 2) MSB is first.
*/
/* note: this is equivalent to checking if the SAI has xCR4's CHMOD bit */
#if FSL_FEATURE_SAI_HAS_CHANNEL_MODE
cfg->dataMode = kSAI_DataPinStateOutputZero;
#endif /* FSL_FEATURE_SAI_HAS_CHANNEL_MODE */
cfg->dataOrder = kSAI_DataMSB;
}
static inline void get_fifo_default_config(sai_fifo_t *cfg)
{
memset(cfg, 0, sizeof(sai_fifo_t));
}
static inline uint32_t sai_get_state(enum dai_dir dir,
struct sai_data *data)
{
if (dir == DAI_DIR_RX) {
return data->rx_state;
} else {
return data->tx_state;
}
}
static int sai_update_state(enum dai_dir dir,
struct sai_data *data,
enum dai_state new_state)
{
enum dai_state old_state = sai_get_state(dir, data);
LOG_DBG("attempting to transition from %d to %d", old_state, new_state);
/* check if transition is possible */
switch (new_state) {
case DAI_STATE_NOT_READY:
/* this shouldn't be possible */
return -EPERM;
case DAI_STATE_READY:
if (old_state != DAI_STATE_NOT_READY &&
old_state != DAI_STATE_READY &&
old_state != DAI_STATE_STOPPING) {
return -EPERM;
}
break;
case DAI_STATE_RUNNING:
if (old_state != DAI_STATE_PAUSED &&
old_state != DAI_STATE_STOPPING &&
old_state != DAI_STATE_READY) {
return -EPERM;
}
break;
case DAI_STATE_PAUSED:
if (old_state != DAI_STATE_RUNNING) {
return -EPERM;
}
break;
case DAI_STATE_STOPPING:
if (old_state != DAI_STATE_READY &&
old_state != DAI_STATE_RUNNING &&
old_state != DAI_STATE_PAUSED) {
return -EPERM;
}
break;
case DAI_STATE_ERROR:
case DAI_STATE_PRE_RUNNING:
/* these states are not used so transitioning to them
* is considered invalid.
*/
default:
return -EINVAL;
}
if (dir == DAI_DIR_RX) {
data->rx_state = new_state;
} else {
data->tx_state = new_state;
}
return 0;
}
static inline void sai_tx_rx_force_disable(enum dai_dir dir,
uint32_t regmap)
{
I2S_Type *base = UINT_TO_I2S(regmap);
if (dir == DAI_DIR_RX) {
base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK));
} else {
base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK));
}
}
static inline void sai_tx_rx_sw_enable_disable(enum dai_dir dir,
struct sai_data *data,
bool enable)
{
if (dir == DAI_DIR_RX) {
data->rx_enabled = enable;
} else {
data->tx_enabled = enable;
}
}
static inline int count_leading_zeros(uint32_t word)
{
int num = 0;
while (word) {
if (!(word & 0x1)) {
num++;
} else {
break;
}
word = word >> 1;
}
return num;
}
static inline void sai_tx_rx_set_dline_mask(enum dai_dir dir, uint32_t regmap, uint32_t mask)
{
I2S_Type *base = UINT_TO_I2S(regmap);
if (dir == DAI_DIR_RX) {
base->RCR3 &= ~I2S_RCR3_RCE_MASK;
base->RCR3 |= I2S_RCR3_RCE(mask);
} else {
base->TCR3 &= ~I2S_TCR3_TCE_MASK;
base->TCR3 |= I2S_TCR3_TCE(mask);
}
}
static inline void sai_dump_register_data(uint32_t regmap)
{
I2S_Type *base = UINT_TO_I2S(regmap);
LOG_DBG("TCSR: 0x%x", base->TCSR);
LOG_DBG("RCSR: 0x%x", base->RCSR);
LOG_DBG("TCR1: 0x%x", base->TCR1);
LOG_DBG("RCR1: 0x%x", base->RCR1);
LOG_DBG("TCR2: 0x%x", base->TCR2);
LOG_DBG("RCR2: 0x%x", base->RCR2);
LOG_DBG("TCR3: 0x%x", base->TCR3);
LOG_DBG("RCR3: 0x%x", base->RCR3);
LOG_DBG("TCR4: 0x%x", base->TCR4);
LOG_DBG("RCR4: 0x%x", base->RCR4);
LOG_DBG("TCR5: 0x%x", base->TCR5);
LOG_DBG("RCR5: 0x%x", base->RCR5);
LOG_DBG("TMR: 0x%x", base->TMR);
LOG_DBG("RMR: 0x%x", base->RMR);
#ifdef CONFIG_SAI_HAS_MCLK_CONFIG_OPTION
LOG_DBG("MCR: 0x%x", base->MCR);
#endif /* CONFIG_SAI_HAS_MCLK_CONFIG_OPTION */
}
#endif /* ZEPHYR_DRIVERS_DAI_NXP_SAI_H_ */
``` | /content/code_sandbox/drivers/dai/nxp/sai/sai.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,988 |
```c
/*
*
*/
#include <zephyr/drivers/dai.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include "sai.h"
/* used for binding the driver */
#define DT_DRV_COMPAT nxp_dai_sai
#define SAI_TX_RX_HW_DISABLE_TIMEOUT 50
/* TODO list:
*
* 1) No busy waiting should be performed in any of the operations.
* In the case of STOP(), the operation should be split into TRIGGER_STOP
* and TRIGGER_POST_STOP. (SOF)
*
* 2) The SAI ISR should stop the SAI whenever a FIFO error interrupt
* is raised.
*
* 3) Transmitter/receiver may remain enabled after sai_tx_rx_disable().
* Fix this.
*/
#ifdef CONFIG_SAI_HAS_MCLK_CONFIG_OPTION
/* note: i.MX8 boards don't seem to support the MICS field in the MCR
* register. As such, the MCLK source field of sai_master_clock_t is
* useless. I'm assuming the source is selected through xCR2's MSEL.
*
* TODO: for now, this function will set MCR's MSEL to the same value
* as xCR2's MSEL or, rather, to the same MCLK as the one used for
* generating BCLK. Is there a need to support different MCLKs in
* xCR2 and MCR?
*/
static int sai_mclk_config(const struct device *dev,
sai_bclk_source_t bclk_source,
const struct sai_bespoke_config *bespoke)
{
const struct sai_config *cfg;
struct sai_data *data;
sai_master_clock_t mclk_config;
uint32_t msel, mclk_rate;
int ret;
cfg = dev->config;
data = dev->data;
mclk_config.mclkOutputEnable = cfg->mclk_is_output;
ret = get_msel(bclk_source, &msel);
if (ret < 0) {
LOG_ERR("invalid MCLK source %d for MSEL", bclk_source);
return ret;
}
/* get MCLK's rate */
ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate);
if (ret < 0) {
LOG_ERR("failed to query MCLK's rate");
return ret;
}
LOG_DBG("source MCLK is %u", mclk_rate);
LOG_DBG("target MCLK is %u", bespoke->mclk_rate);
/* source MCLK rate */
mclk_config.mclkSourceClkHz = mclk_rate;
/* target MCLK rate */
mclk_config.mclkHz = bespoke->mclk_rate;
/* commit configuration */
SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config);
set_msel(data->regmap, msel);
return 0;
}
#endif /* CONFIG_SAI_HAS_MCLK_CONFIG_OPTION */
void sai_isr(const void *parameter)
{
const struct device *dev;
struct sai_data *data;
dev = parameter;
data = dev->data;
/* check for TX FIFO error */
if (SAI_TX_RX_STATUS_IS_SET(DAI_DIR_TX, data->regmap, kSAI_FIFOErrorFlag)) {
LOG_ERR("FIFO underrun detected");
/* TODO: this will crash the program and should be addressed as
* mentioned in TODO list's 2).
*/
z_irq_spurious(NULL);
}
/* check for RX FIFO error */
if (SAI_TX_RX_STATUS_IS_SET(DAI_DIR_RX, data->regmap, kSAI_FIFOErrorFlag)) {
LOG_ERR("FIFO overrun detected");
/* TODO: this will crash the program and should be addressed as
* mentioned in TODO list's 2).
*/
z_irq_spurious(NULL);
}
}
static int sai_config_get(const struct device *dev,
struct dai_config *cfg,
enum dai_dir dir)
{
struct sai_data *data = dev->data;
/* dump content of the DAI configuration */
memcpy(cfg, &data->cfg, sizeof(*cfg));
return 0;
}
static const struct dai_properties
*sai_get_properties(const struct device *dev, enum dai_dir dir, int stream_id)
{
const struct sai_config *cfg = dev->config;
switch (dir) {
case DAI_DIR_RX:
return cfg->rx_props;
case DAI_DIR_TX:
return cfg->tx_props;
default:
LOG_ERR("invalid direction: %d", dir);
return NULL;
}
CODE_UNREACHABLE;
}
#ifdef CONFIG_SAI_IMX93_ERRATA_051421
/* notes:
* 1) TX and RX operate in the same mode: master/slave. As such,
* there's no need to check the mode for both directions.
*
* 2) Only one of the directions can operate in SYNC mode at a
* time.
*
* 3) What this piece of code does is it makes the SYNC direction
* use the ASYNC direction's BCLK that comes from its input pad.
* Logically speaking, this would look like:
*
* +--------+ +--------+
* | TX | | RX |
* | module | | module |
* +--------+ +--------+
* | ^ |
* | | |
* TX_BCLK | |____________| RX_BCLK
* | |
* V V
* +---------+ +---------+
* | TX BCLK | | RX BCLK |
* | pad | | pad |
* +---------+ +---------+
* | |
* | TX_BCLK | RX_BCLK
* V V
*
* Without BCI enabled, the TX module would use an RX_BCLK
* that's divided instead of the one that's obtained from
* bypassing the MCLK (i.e: TX_BCLK would have the value of
* MCLK / ((RX_DIV + 1) * 2)). If BCI is 1, then TX_BCLK will
* be the same as the RX_BCLK that's obtained from bypassing
* the MCLK on RX's side.
*
* 4) The check for BCLK == MCLK is there to see if the ASYNC
* direction will have the BYP bit toggled.
*
* IMPORTANT1: in the above diagram and information, RX is SYNC
* with TX. The same applies if RX is SYNC with TX. Also, this
* applies to i.MX93. For other SoCs, things may be different
* so use this information with caution.
*
* IMPORTANT2: for this to work, you also need to enable the
* pad's input path. For i.MX93, this can be achieved by setting
* the pad's SION bit.
*/
static void sai_config_set_err_051421(I2S_Type *base,
const struct sai_config *cfg,
const struct sai_bespoke_config *bespoke,
sai_transceiver_t *rx_config,
sai_transceiver_t *tx_config)
{
if (tx_config->masterSlave == kSAI_Master &&
bespoke->mclk_rate == bespoke->bclk_rate) {
if (cfg->tx_sync_mode == kSAI_ModeSync) {
base->TCR2 |= I2S_TCR2_BCI(1);
}
if (cfg->rx_sync_mode == kSAI_ModeSync) {
base->RCR2 |= I2S_RCR2_BCI(1);
}
}
}
#endif /* CONFIG_SAI_IMX93_ERRATA_051421 */
static int sai_config_set(const struct device *dev,
const struct dai_config *cfg,
const void *bespoke_data)
{
const struct sai_bespoke_config *bespoke;
sai_transceiver_t *rx_config, *tx_config;
struct sai_data *data;
const struct sai_config *sai_cfg;
int ret;
if (cfg->type != DAI_IMX_SAI) {
LOG_ERR("wrong DAI type: %d", cfg->type);
return -EINVAL;
}
bespoke = bespoke_data;
data = dev->data;
sai_cfg = dev->config;
rx_config = &data->rx_config;
tx_config = &data->tx_config;
/* since this function configures the transmitter AND the receiver, that
* means both of them need to be stopped. As such, doing the state
* transition here will also result in a state check.
*/
ret = sai_update_state(DAI_DIR_TX, data, DAI_STATE_READY);
if (ret < 0) {
LOG_ERR("failed to update TX state. Reason: %d", ret);
return ret;
}
ret = sai_update_state(DAI_DIR_RX, data, DAI_STATE_READY);
if (ret < 0) {
LOG_ERR("failed to update RX state. Reason: %d", ret);
return ret;
}
/* condition: BCLK = FSYNC * TDM_SLOT_WIDTH * TDM_SLOTS */
if (bespoke->bclk_rate !=
(bespoke->fsync_rate * bespoke->tdm_slot_width * bespoke->tdm_slots)) {
LOG_ERR("bad BCLK value: %d", bespoke->bclk_rate);
return -EINVAL;
}
/* TODO: this should be removed if we're to support sw channels != hw channels */
if (count_leading_zeros(~bespoke->tx_slots) != bespoke->tdm_slots ||
count_leading_zeros(~bespoke->rx_slots) != bespoke->tdm_slots) {
LOG_ERR("number of TX/RX slots doesn't match number of TDM slots");
return -EINVAL;
}
/* get default configurations */
get_bclk_default_config(&tx_config->bitClock);
get_fsync_default_config(&tx_config->frameSync);
get_serial_default_config(&tx_config->serialData);
get_fifo_default_config(&tx_config->fifo);
/* note1: this may be obvious but enabling multiple SAI
* channels (or data lines) may lead to FIFO starvation/
* overflow if data is not written/read from the respective
* TDR/RDR registers.
*
* note2: the SAI data line should be enabled based on
* the direction (TX/RX) we're enabling. Enabling the
* data line for the opposite direction will lead to FIFO
* overrun/underrun when working with a SYNC direction.
*
* note3: the TX/RX data line shall be enabled/disabled
* via the sai_trigger_() suite to avoid scenarios in
* which one configures both direction but only starts
* the SYNC direction which would lead to a FIFO underrun.
*/
tx_config->channelMask = 0x0;
/* TODO: for now, only MCLK1 is supported */
tx_config->bitClock.bclkSource = kSAI_BclkSourceMclkOption1;
/* FSYNC is asserted for tdm_slot_width BCLKs */
tx_config->frameSync.frameSyncWidth = bespoke->tdm_slot_width;
/* serial data common configuration */
tx_config->serialData.dataWord0Length = bespoke->tdm_slot_width;
tx_config->serialData.dataWordNLength = bespoke->tdm_slot_width;
tx_config->serialData.dataFirstBitShifted = bespoke->tdm_slot_width;
tx_config->serialData.dataWordNum = bespoke->tdm_slots;
/* clock provider configuration */
switch (cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK) {
case DAI_CBP_CFP:
tx_config->masterSlave = kSAI_Slave;
break;
case DAI_CBC_CFC:
tx_config->masterSlave = kSAI_Master;
break;
case DAI_CBC_CFP:
case DAI_CBP_CFC:
LOG_ERR("unsupported provider configuration: %d",
cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK);
return -ENOTSUP;
default:
LOG_ERR("invalid provider configuration: %d",
cfg->format & DAI_FORMAT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
LOG_DBG("SAI is in %d mode", tx_config->masterSlave);
/* protocol configuration */
switch (cfg->format & DAI_FORMAT_PROTOCOL_MASK) {
case DAI_PROTO_I2S:
/* BCLK is active LOW */
tx_config->bitClock.bclkPolarity = kSAI_PolarityActiveLow;
/* FSYNC is active LOW */
tx_config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
break;
case DAI_PROTO_DSP_A:
/* FSYNC is asserted for a single BCLK */
tx_config->frameSync.frameSyncWidth = 1;
/* BCLK is active LOW */
tx_config->bitClock.bclkPolarity = kSAI_PolarityActiveLow;
break;
default:
LOG_ERR("unsupported DAI protocol: %d",
cfg->format & DAI_FORMAT_PROTOCOL_MASK);
return -EINVAL;
}
LOG_DBG("SAI uses protocol: %d",
cfg->format & DAI_FORMAT_PROTOCOL_MASK);
/* clock inversion configuration */
switch (cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK) {
case DAI_INVERSION_IB_IF:
SAI_INVERT_POLARITY(tx_config->bitClock.bclkPolarity);
SAI_INVERT_POLARITY(tx_config->frameSync.frameSyncPolarity);
break;
case DAI_INVERSION_IB_NF:
SAI_INVERT_POLARITY(tx_config->bitClock.bclkPolarity);
break;
case DAI_INVERSION_NB_IF:
SAI_INVERT_POLARITY(tx_config->frameSync.frameSyncPolarity);
break;
case DAI_INVERSION_NB_NF:
/* nothing to do here */
break;
default:
LOG_ERR("invalid clock inversion configuration: %d",
cfg->format & DAI_FORMAT_CLOCK_INVERSION_MASK);
return -EINVAL;
}
LOG_DBG("FSYNC polarity: %d", tx_config->frameSync.frameSyncPolarity);
LOG_DBG("BCLK polarity: %d", tx_config->bitClock.bclkPolarity);
/* duplicate TX configuration */
memcpy(rx_config, tx_config, sizeof(sai_transceiver_t));
tx_config->serialData.dataMaskedWord = ~bespoke->tx_slots;
rx_config->serialData.dataMaskedWord = ~bespoke->rx_slots;
tx_config->fifo.fifoWatermark = sai_cfg->tx_fifo_watermark - 1;
rx_config->fifo.fifoWatermark = sai_cfg->rx_fifo_watermark - 1;
LOG_DBG("RX watermark: %d", sai_cfg->rx_fifo_watermark);
LOG_DBG("TX watermark: %d", sai_cfg->tx_fifo_watermark);
/* set the synchronization mode based on data passed from the DTS */
tx_config->syncMode = sai_cfg->tx_sync_mode;
rx_config->syncMode = sai_cfg->rx_sync_mode;
/* commit configuration */
SAI_RxSetConfig(UINT_TO_I2S(data->regmap), rx_config);
SAI_TxSetConfig(UINT_TO_I2S(data->regmap), tx_config);
/* a few notes here:
* 1) TX and RX operate in the same mode: master or slave.
* 2) Setting BCLK's rate needs to be performed explicitly
* since SetConfig() doesn't do it for us.
* 3) Setting BCLK's rate has to be performed after the
* SetConfig() call as that resets the SAI registers.
*/
if (tx_config->masterSlave == kSAI_Master) {
SAI_TxSetBitClockRate(UINT_TO_I2S(data->regmap), bespoke->mclk_rate,
bespoke->fsync_rate, bespoke->tdm_slot_width,
bespoke->tdm_slots);
SAI_RxSetBitClockRate(UINT_TO_I2S(data->regmap), bespoke->mclk_rate,
bespoke->fsync_rate, bespoke->tdm_slot_width,
bespoke->tdm_slots);
}
#ifdef CONFIG_SAI_HAS_MCLK_CONFIG_OPTION
ret = sai_mclk_config(dev, tx_config->bitClock.bclkSource, bespoke);
if (ret < 0) {
LOG_ERR("failed to set MCLK configuration");
return ret;
}
#endif /* CONFIG_SAI_HAS_MCLK_CONFIG_OPTION */
#ifdef CONFIG_SAI_IMX93_ERRATA_051421
sai_config_set_err_051421(UINT_TO_I2S(data->regmap),
sai_cfg, bespoke,
rx_config, tx_config);
#endif /* CONFIG_SAI_IMX93_ERRATA_051421 */
/* this is needed so that rates different from FSYNC_RATE
* will not be allowed.
*
* this is because the hardware is configured to match
* the topology rates so attempting to play a file using
* a different rate from the one configured in the hardware
* doesn't work properly.
*
* if != 0, SOF will raise an error if the PCM rate is
* different than the hardware rate (a.k.a this one).
*/
data->cfg.rate = bespoke->fsync_rate;
/* SOF note: we don't support a variable number of channels
* at the moment so leaving the number of channels as 0 is
* unnecessary and leads to issues (e.g: the mixer buffers
* use this value to set the number of channels so having
* a 0 as this value leads to mixer buffers having 0 channels,
* which, in turn, leads to the DAI ending up with 0 channels,
* thus resulting in an error)
*/
data->cfg.channels = bespoke->tdm_slots;
sai_dump_register_data(data->regmap);
return 0;
}
/* SOF note: please be very careful with this function as it does
* busy waiting and may mess up your timing in time critial applications
* (especially with timer domain). If this becomes unusable, the busy
* waiting should be removed altogether and the HW state check should
* be performed in sai_trigger_start() or in sai_config_set().
*
* TODO: seems like the transmitter still remains active (even if 1ms
* has passed after doing a sai_trigger_stop()!). Most likely this is
* because sai_trigger_stop() immediately stops the data line w/o
* checking the HW state of the transmitter/receiver. As such, to get
* rid of the busy waiting, the STOP operation may have to be split into
* 2 operations: TRIG_STOP and TRIG_POST_STOP.
*/
static bool sai_dir_disable(struct sai_data *data, enum dai_dir dir)
{
/* VERY IMPORTANT: DO NOT use SAI_TxEnable/SAI_RxEnable
* here as they do not disable the ASYNC direction.
* Since the software logic assures that the ASYNC direction
* is not disabled before the SYNC direction, we can force
* the disablement of the given direction.
*/
sai_tx_rx_force_disable(dir, data->regmap);
/* please note the difference between the transmitter/receiver's
* hardware states and their software states. The software
* states can be obtained by reading data->tx/rx_enabled, while
* the hardware states can be obtained by reading TCSR/RCSR. The
* hardware state can actually differ from the software state.
* Here, we're interested in reading the hardware state which
* indicates if the transmitter/receiver was actually disabled
* or not.
*/
return WAIT_FOR(!SAI_TX_RX_IS_HW_ENABLED(dir, data->regmap),
SAI_TX_RX_HW_DISABLE_TIMEOUT, k_busy_wait(1));
}
static int sai_tx_rx_disable(struct sai_data *data,
const struct sai_config *cfg, enum dai_dir dir)
{
enum dai_dir sync_dir, async_dir;
bool ret;
/* sai_disable() should never be called from ISR context
* as it does some busy waiting.
*/
if (k_is_in_isr()) {
LOG_ERR("sai_disable() should never be called from ISR context");
return -EINVAL;
}
if (cfg->tx_sync_mode == kSAI_ModeAsync &&
cfg->rx_sync_mode == kSAI_ModeAsync) {
ret = sai_dir_disable(data, dir);
if (!ret) {
LOG_ERR("timed out while waiting for dir %d disable", dir);
return -ETIMEDOUT;
}
} else {
sync_dir = SAI_TX_RX_GET_SYNC_DIR(cfg);
async_dir = SAI_TX_RX_GET_ASYNC_DIR(cfg);
if (dir == sync_dir) {
ret = sai_dir_disable(data, sync_dir);
if (!ret) {
LOG_ERR("timed out while waiting for dir %d disable",
sync_dir);
return -ETIMEDOUT;
}
if (!SAI_TX_RX_DIR_IS_SW_ENABLED(async_dir, data)) {
ret = sai_dir_disable(data, async_dir);
if (!ret) {
LOG_ERR("timed out while waiting for dir %d disable",
async_dir);
return -ETIMEDOUT;
}
}
} else {
if (!SAI_TX_RX_DIR_IS_SW_ENABLED(sync_dir, data)) {
ret = sai_dir_disable(data, async_dir);
if (!ret) {
LOG_ERR("timed out while waiting for dir %d disable",
async_dir);
return -ETIMEDOUT;
}
}
}
}
return 0;
}
static int sai_trigger_pause(const struct device *dev,
enum dai_dir dir)
{
struct sai_data *data;
const struct sai_config *cfg;
int ret;
data = dev->data;
cfg = dev->config;
if (dir != DAI_DIR_RX && dir != DAI_DIR_TX) {
LOG_ERR("invalid direction: %d", dir);
return -EINVAL;
}
/* attempt to change state */
ret = sai_update_state(dir, data, DAI_STATE_PAUSED);
if (ret < 0) {
LOG_ERR("failed to transition to PAUSED from %d. Reason: %d",
sai_get_state(dir, data), ret);
return ret;
}
LOG_DBG("pause on direction %d", dir);
ret = sai_tx_rx_disable(data, cfg, dir);
if (ret < 0) {
return ret;
}
/* disable TX/RX data line */
sai_tx_rx_set_dline_mask(dir, data->regmap, 0x0);
/* update the software state of TX/RX */
sai_tx_rx_sw_enable_disable(dir, data, false);
return 0;
}
static int sai_trigger_stop(const struct device *dev,
enum dai_dir dir)
{
struct sai_data *data;
const struct sai_config *cfg;
int ret;
uint32_t old_state;
data = dev->data;
cfg = dev->config;
old_state = sai_get_state(dir, data);
if (dir != DAI_DIR_RX && dir != DAI_DIR_TX) {
LOG_ERR("invalid direction: %d", dir);
return -EINVAL;
}
/* attempt to change state */
ret = sai_update_state(dir, data, DAI_STATE_STOPPING);
if (ret < 0) {
LOG_ERR("failed to transition to STOPPING from %d. Reason: %d",
sai_get_state(dir, data), ret);
return ret;
}
LOG_DBG("stop on direction %d", dir);
if (old_state == DAI_STATE_PAUSED) {
/* if SAI was previously paused then all that's
* left to do is disable the DMA requests and
* the data line.
*/
goto out_dmareq_disable;
}
ret = sai_tx_rx_disable(data, cfg, dir);
if (ret < 0) {
return ret;
}
/* update the software state of TX/RX */
sai_tx_rx_sw_enable_disable(dir, data, false);
/* disable TX/RX data line */
sai_tx_rx_set_dline_mask(dir, data->regmap, 0x0);
out_dmareq_disable:
/* disable DMA requests */
SAI_TX_RX_DMA_ENABLE_DISABLE(dir, data->regmap, false);
/* disable error interrupt */
SAI_TX_RX_ENABLE_DISABLE_IRQ(dir, data->regmap,
kSAI_FIFOErrorInterruptEnable, false);
return 0;
}
/* notes:
* 1) The "rx_sync_mode" and "tx_sync_mode" properties force the user to pick from
* SYNC and ASYNC for each direction. As such, there are 4 possible combinations
* that need to be covered here:
* a) TX ASYNC, RX ASYNC
* b) TX SYNC, RX ASYNC
* c) TX ASYNC, RX SYNC
* d) TX SYNC, RX SYNC
*
* Combination d) is not valid and is covered by a BUILD_ASSERT(). As such, there are 3 valid
* combinations that need to be supported. Since the main branch of the IF statement covers
* combination a), there's only combinations b) and c) to be covered here.
*
* 2) We can distinguish between 3 types of directions:
* a) The target direction. This is the direction on which we want to perform the
* software reset.
* b) The SYNC direction. This is, well, the direction that's in SYNC with the other
* direction.
* c) The ASYNC direction.
*
* Of course, the target direction may differ from the SYNC or ASYNC directions, but it
* can't differ from both of them at the same time (i.e: TARGET != SYNC AND TARGET != ASYNC).
*
* If the target direction is the same as the SYNC direction then we can safely perform the
* software reset on the target direction as there's nothing depending on it. We also want
* to do a software reset on the ASYNC direction. We can only do this if the ASYNC direction
* wasn't software enabled (i.e: through an explicit trigger_start() call).
*
* If the target direction is the same as the ASYNC direction then we can only perform a
* software reset on it only if the SYNC direction wasn't software enabled (i.e: through an
* explicit trigger_start() call).
*/
static void sai_tx_rx_sw_reset(struct sai_data *data,
const struct sai_config *cfg, enum dai_dir dir)
{
enum dai_dir sync_dir, async_dir;
if (cfg->tx_sync_mode == kSAI_ModeAsync &&
cfg->rx_sync_mode == kSAI_ModeAsync) {
/* both directions are ASYNC w.r.t each other. As such, do
* software reset only on the targeted direction.
*/
SAI_TX_RX_SW_RESET(dir, data->regmap);
} else {
sync_dir = SAI_TX_RX_GET_SYNC_DIR(cfg);
async_dir = SAI_TX_RX_GET_ASYNC_DIR(cfg);
if (dir == sync_dir) {
SAI_TX_RX_SW_RESET(sync_dir, data->regmap);
if (!SAI_TX_RX_DIR_IS_SW_ENABLED(async_dir, data)) {
SAI_TX_RX_SW_RESET(async_dir, data->regmap);
}
} else {
if (!SAI_TX_RX_DIR_IS_SW_ENABLED(sync_dir, data)) {
SAI_TX_RX_SW_RESET(async_dir, data->regmap);
}
}
}
}
static int sai_trigger_start(const struct device *dev,
enum dai_dir dir)
{
struct sai_data *data;
const struct sai_config *cfg;
uint32_t old_state;
int ret, i;
data = dev->data;
cfg = dev->config;
old_state = sai_get_state(dir, data);
/* TX and RX should be triggered independently */
if (dir != DAI_DIR_RX && dir != DAI_DIR_TX) {
LOG_ERR("invalid direction: %d", dir);
return -EINVAL;
}
/* attempt to change state */
ret = sai_update_state(dir, data, DAI_STATE_RUNNING);
if (ret < 0) {
LOG_ERR("failed to transition to RUNNING from %d. Reason: %d",
sai_get_state(dir, data), ret);
return ret;
}
if (old_state == DAI_STATE_PAUSED) {
/* if the SAI has been paused then there's no
* point in issuing a software reset. As such,
* skip this part and go directly to the TX/RX
* enablement.
*/
goto out_enable_dline;
}
LOG_DBG("start on direction %d", dir);
sai_tx_rx_sw_reset(data, cfg, dir);
/* enable error interrupt */
SAI_TX_RX_ENABLE_DISABLE_IRQ(dir, data->regmap,
kSAI_FIFOErrorInterruptEnable, true);
/* avoid initial underrun by writing a frame's worth of 0s */
if (dir == DAI_DIR_TX) {
for (i = 0; i < data->cfg.channels; i++) {
SAI_WriteData(UINT_TO_I2S(data->regmap), cfg->tx_dline, 0x0);
}
}
/* TODO: for now, only DMA mode is supported */
SAI_TX_RX_DMA_ENABLE_DISABLE(dir, data->regmap, true);
out_enable_dline:
/* enable TX/RX data line. This translates to TX_DLINE0/RX_DLINE0
* being enabled.
*
* TODO: for now we only support 1 data line per direction.
*/
sai_tx_rx_set_dline_mask(dir, data->regmap,
SAI_TX_RX_DLINE_MASK(dir, cfg));
/* this will also enable the async side */
SAI_TX_RX_ENABLE_DISABLE(dir, data->regmap, true);
/* update the software state of TX/RX */
sai_tx_rx_sw_enable_disable(dir, data, true);
return 0;
}
static int sai_trigger(const struct device *dev,
enum dai_dir dir,
enum dai_trigger_cmd cmd)
{
switch (cmd) {
case DAI_TRIGGER_START:
return sai_trigger_start(dev, dir);
case DAI_TRIGGER_PAUSE:
return sai_trigger_pause(dev, dir);
case DAI_TRIGGER_STOP:
return sai_trigger_stop(dev, dir);
case DAI_TRIGGER_PRE_START:
case DAI_TRIGGER_COPY:
/* COPY and PRE_START don't require the SAI
* driver to do anything at the moment so
* mark them as successful via a NULL return
*
* note: although the rest of the unhandled
* trigger commands may be valid, return
* an error code for them as they aren't
* implemented ATM (since they're not
* mandatory for the SAI driver to work).
*/
return 0;
default:
LOG_ERR("invalid trigger command: %d", cmd);
return -EINVAL;
}
CODE_UNREACHABLE;
}
static int sai_probe(const struct device *dev)
{
/* nothing to be done here but sadly mandatory to implement */
return 0;
}
static int sai_remove(const struct device *dev)
{
/* nothing to be done here but sadly mandatory to implement */
return 0;
}
static const struct dai_driver_api sai_api = {
.config_set = sai_config_set,
.config_get = sai_config_get,
.trigger = sai_trigger,
.get_properties = sai_get_properties,
.probe = sai_probe,
.remove = sai_remove,
};
static int sai_init(const struct device *dev)
{
const struct sai_config *cfg;
struct sai_data *data;
int i, ret;
cfg = dev->config;
data = dev->data;
device_map(&data->regmap, cfg->regmap_phys, cfg->regmap_size, K_MEM_CACHE_NONE);
/* enable clocks if any */
for (i = 0; i < cfg->clk_data.clock_num; i++) {
ret = clock_control_on(cfg->clk_data.dev,
UINT_TO_POINTER(cfg->clk_data.clocks[i]));
if (ret < 0) {
return ret;
}
LOG_DBG("clock %s has been ungated", cfg->clk_data.clock_names[i]);
}
/* note: optional operation so -ENOENT is allowed (i.e: we
* allow the default state to not be defined)
*/
ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (ret < 0 && ret != -ENOENT) {
return ret;
}
/* set TX/RX default states */
data->tx_state = DAI_STATE_NOT_READY;
data->rx_state = DAI_STATE_NOT_READY;
/* register ISR and enable IRQ */
cfg->irq_config();
return 0;
}
#define SAI_INIT(inst) \
\
PINCTRL_DT_INST_DEFINE(inst); \
\
BUILD_ASSERT(SAI_FIFO_DEPTH(inst) > 0 && \
SAI_FIFO_DEPTH(inst) <= _SAI_FIFO_DEPTH(inst), \
"invalid FIFO depth"); \
\
BUILD_ASSERT(SAI_RX_FIFO_WATERMARK(inst) > 0 && \
SAI_RX_FIFO_WATERMARK(inst) <= _SAI_FIFO_DEPTH(inst), \
"invalid RX FIFO watermark"); \
\
BUILD_ASSERT(SAI_TX_FIFO_WATERMARK(inst) > 0 && \
SAI_TX_FIFO_WATERMARK(inst) <= _SAI_FIFO_DEPTH(inst), \
"invalid TX FIFO watermark"); \
\
BUILD_ASSERT(IS_ENABLED(CONFIG_SAI_HAS_MCLK_CONFIG_OPTION) || \
!DT_INST_PROP(inst, mclk_is_output), \
"SAI doesn't support MCLK config but mclk_is_output is specified");\
\
BUILD_ASSERT(SAI_TX_SYNC_MODE(inst) != SAI_RX_SYNC_MODE(inst) || \
SAI_TX_SYNC_MODE(inst) != kSAI_ModeSync, \
"transmitter and receiver can't be both SYNC with each other"); \
\
BUILD_ASSERT(SAI_DLINE_COUNT(inst) != -1, \
"bad or unsupported SAI instance. Is the base address correct?"); \
\
BUILD_ASSERT(SAI_TX_DLINE_INDEX(inst) >= 0 && \
(SAI_TX_DLINE_INDEX(inst) < SAI_DLINE_COUNT(inst)), \
"invalid TX data line index"); \
\
BUILD_ASSERT(SAI_RX_DLINE_INDEX(inst) >= 0 && \
(SAI_RX_DLINE_INDEX(inst) < SAI_DLINE_COUNT(inst)), \
"invalid RX data line index"); \
\
static const struct dai_properties sai_tx_props_##inst = { \
.fifo_address = SAI_TX_FIFO_BASE(inst, SAI_TX_DLINE_INDEX(inst)), \
.fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \
.dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, tx), \
}; \
\
static const struct dai_properties sai_rx_props_##inst = { \
.fifo_address = SAI_RX_FIFO_BASE(inst, SAI_RX_DLINE_INDEX(inst)), \
.fifo_depth = SAI_FIFO_DEPTH(inst) * CONFIG_SAI_FIFO_WORD_SIZE, \
.dma_hs_id = SAI_TX_RX_DMA_HANDSHAKE(inst, rx), \
}; \
\
void irq_config_##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
0, \
sai_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
} \
\
static struct sai_config sai_config_##inst = { \
.regmap_phys = DT_INST_REG_ADDR(inst), \
.regmap_size = DT_INST_REG_SIZE(inst), \
.clk_data = SAI_CLOCK_DATA_DECLARE(inst), \
.rx_fifo_watermark = SAI_RX_FIFO_WATERMARK(inst), \
.tx_fifo_watermark = SAI_TX_FIFO_WATERMARK(inst), \
.mclk_is_output = DT_INST_PROP(inst, mclk_is_output), \
.tx_props = &sai_tx_props_##inst, \
.rx_props = &sai_rx_props_##inst, \
.irq_config = irq_config_##inst, \
.tx_sync_mode = SAI_TX_SYNC_MODE(inst), \
.rx_sync_mode = SAI_RX_SYNC_MODE(inst), \
.tx_dline = SAI_TX_DLINE_INDEX(inst), \
.rx_dline = SAI_RX_DLINE_INDEX(inst), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
static struct sai_data sai_data_##inst = { \
.cfg.type = DAI_IMX_SAI, \
.cfg.dai_index = DT_INST_PROP_OR(inst, dai_index, 0), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &sai_init, NULL, \
&sai_data_##inst, &sai_config_##inst, \
POST_KERNEL, CONFIG_DAI_INIT_PRIORITY, \
&sai_api); \
DT_INST_FOREACH_STATUS_OKAY(SAI_INIT);
``` | /content/code_sandbox/drivers/dai/nxp/sai/sai.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,119 |
```unknown
config AUXDISPLAY_PT6314
bool "PTC PT6314 dot character VFD driver"
default y
select SPI
depends on DT_HAS_PTC_PT6314_ENABLED
help
Enable driver for PTC PT6314.
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig.pt6314 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```c
/*
*
*/
#define DT_DRV_COMPAT sparkfun_serlcd
#include <stdlib.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(auxdisplay_serlcd, CONFIG_AUXDISPLAY_LOG_LEVEL);
/*
* | in ASCII, used to begin a display command
*/
#define SERLCD_BEGIN_COMMAND 0x7C
/*
* special command for the underlying display controller
*/
#define SERLCD_BEGIN_SPECIAL_COMMAND 0xFE
/*
* maximum amount of custom chars the display supports
*/
#define SERLCD_CUSTOM_CHAR_MAX_COUNT 8
/*
* height of a custom char in bits
*/
#define SERLCD_CUSTOM_CHAR_HEIGHT 8
/*
* width of a custom char in bits
*/
#define SERLCD_CUSTOM_CHAR_WIDTH 5
/*
* char code for the first custom char
*/
#define SERLCD_CUSTOM_CHAR_INDEX_BASE 0x08
/*
* bitmask for custom character detection
*/
#define SERLCD_CUSTOM_CHAR_BITMASK 0xf8
/*
* bit to set in the display control special command to indicate the display should be powered on
*/
#define SERLCD_DISPLAY_CONTROL_POWER_BIT BIT(2)
/*
* bit to set in the display control special command to indicate the cursor should be displayed
*/
#define SERLCD_DISPLAY_CONTROL_CURSOR_BIT BIT(1)
/*
* bit to set in the display control special command to indicate the cursor should be blinking
*/
#define SERLCD_DISPLAY_CONTROL_BLINKING_BIT BIT(0)
struct auxdisplay_serlcd_data {
bool power;
bool cursor;
bool blinking;
uint16_t cursor_x;
uint16_t cursor_y;
};
struct auxdisplay_serlcd_config {
struct auxdisplay_capabilities capabilities;
struct i2c_dt_spec bus;
uint16_t command_delay_ms;
uint16_t special_command_delay_ms;
};
enum auxdisplay_serlcd_command {
SERLCD_COMMAND_SET_CUSTOM_CHAR = 0x1B,
SERLCD_COMMAND_WRITE_CUSTOM_CHAR = 0x23,
SERLCD_COMMAND_CLEAR = 0x2D,
};
enum auxdisplay_serlcd_special_command {
SERLCD_SPECIAL_RETURN_HOME = 0x02,
SERLCD_SPECIAL_DISPLAY_CONTROL = 0x08,
SERLCD_SPECIAL_SET_DD_RAM_ADDRESS = 0x80,
};
static int auxdisplay_serlcd_send_command(const struct device *dev,
const enum auxdisplay_serlcd_command command)
{
const struct auxdisplay_serlcd_config *config = dev->config;
const uint8_t buffer[2] = {SERLCD_BEGIN_COMMAND, command};
int rc = i2c_write_dt(&config->bus, buffer, sizeof(buffer));
k_sleep(K_MSEC(config->command_delay_ms));
return rc;
}
static int
auxdisplay_serlcd_send_special_command(const struct device *dev,
const enum auxdisplay_serlcd_special_command command)
{
const struct auxdisplay_serlcd_config *config = dev->config;
const uint8_t buffer[2] = {SERLCD_BEGIN_SPECIAL_COMMAND, command};
int rc = i2c_write_dt(&config->bus, buffer, sizeof(buffer));
k_sleep(K_MSEC(config->special_command_delay_ms));
return rc;
}
static int auxdisplay_serlcd_send_display_state(const struct device *dev,
const struct auxdisplay_serlcd_data *data)
{
uint8_t command = SERLCD_SPECIAL_DISPLAY_CONTROL;
if (data->power) {
command |= SERLCD_DISPLAY_CONTROL_POWER_BIT;
}
if (data->cursor) {
command |= SERLCD_DISPLAY_CONTROL_CURSOR_BIT;
}
if (data->blinking) {
command |= SERLCD_DISPLAY_CONTROL_BLINKING_BIT;
}
return auxdisplay_serlcd_send_special_command(dev, command);
}
static int auxdisplay_serlcd_display_on(const struct device *dev)
{
struct auxdisplay_serlcd_data *data = dev->data;
data->power = true;
return auxdisplay_serlcd_send_display_state(dev, data);
}
static int auxdisplay_serlcd_display_off(const struct device *dev)
{
struct auxdisplay_serlcd_data *data = dev->data;
data->power = false;
return auxdisplay_serlcd_send_display_state(dev, data);
}
static int auxdisplay_serlcd_cursor_set_enabled(const struct device *dev, bool enable)
{
struct auxdisplay_serlcd_data *data = dev->data;
data->cursor = enable;
return auxdisplay_serlcd_send_display_state(dev, data);
}
static int auxdisplay_serlcd_position_blinking_set_enabled(const struct device *dev, bool enable)
{
struct auxdisplay_serlcd_data *data = dev->data;
data->blinking = enable;
return auxdisplay_serlcd_send_display_state(dev, data);
}
static int auxdisplay_serlcd_cursor_position_set(const struct device *dev,
enum auxdisplay_position type, int16_t x,
int16_t y)
{
static const uint8_t row_offsets[] = {0x00, 0x40, 0x14, 0x54};
const struct auxdisplay_serlcd_config *config = dev->config;
const struct auxdisplay_capabilities capabilities = config->capabilities;
const uint16_t columns = capabilities.columns;
const uint16_t rows = capabilities.rows;
struct auxdisplay_serlcd_data *data = dev->data;
if (type == AUXDISPLAY_POSITION_ABSOLUTE) {
/*
* shortcut for (0,0) position
*/
if (x == 0 && y == 0) {
data->cursor_x = x;
data->cursor_y = y;
return auxdisplay_serlcd_send_special_command(dev,
SERLCD_SPECIAL_RETURN_HOME);
}
/*
* bounds checking
*/
if (x < 0 || x >= columns) {
return -EINVAL;
}
if (y < 0 || y >= rows) {
return -EINVAL;
}
data->cursor_x = x;
data->cursor_y = y;
const uint8_t cursor_address = x + row_offsets[y];
return auxdisplay_serlcd_send_special_command(
dev, SERLCD_SPECIAL_SET_DD_RAM_ADDRESS | cursor_address);
} else if (type == AUXDISPLAY_POSITION_RELATIVE) {
/*
* clip relative move to display dimensions
*/
const int new_x = (data->cursor_x + x) % columns;
const int new_y = (data->cursor_y + y + x / columns) % rows;
const uint16_t column = new_x < 0 ? new_x + columns : new_x;
const uint16_t row = new_y < 0 ? new_y + rows : new_y;
data->cursor_x = column;
data->cursor_y = row;
const uint8_t cursor_address = column + row_offsets[row];
return auxdisplay_serlcd_send_special_command(
dev, SERLCD_SPECIAL_SET_DD_RAM_ADDRESS | cursor_address);
}
/*
* other types of movement are not implemented/supported
*/
return -ENOSYS;
}
static int auxdisplay_serlcd_cursor_position_get(const struct device *dev, int16_t *x, int16_t *y)
{
const struct auxdisplay_serlcd_data *data = dev->data;
*x = (int16_t)data->cursor_x;
*y = (int16_t)data->cursor_y;
return 0;
}
static int auxdisplay_serlcd_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
const struct auxdisplay_serlcd_config *config = dev->config;
memcpy(capabilities, &config->capabilities, sizeof(struct auxdisplay_capabilities));
return 0;
}
static int auxdisplay_serlcd_clear(const struct device *dev)
{
const struct auxdisplay_serlcd_config *config = dev->config;
int rc = auxdisplay_serlcd_send_command(dev, SERLCD_COMMAND_CLEAR);
k_sleep(K_MSEC(config->command_delay_ms));
return rc;
}
static int auxdisplay_serlcd_custom_character_set(const struct device *dev,
struct auxdisplay_character *character)
{
const struct auxdisplay_serlcd_config *config = dev->config;
int rc;
/*
* only indexes 0..7 are supported
*/
const uint8_t char_index = character->index;
if (char_index > (SERLCD_CUSTOM_CHAR_MAX_COUNT - 1)) {
return -EINVAL;
}
/*
* custom characters are accessible via char codes 0x08..0x0f
*/
character->character_code = SERLCD_CUSTOM_CHAR_INDEX_BASE | char_index;
rc = auxdisplay_serlcd_send_command(dev, SERLCD_COMMAND_SET_CUSTOM_CHAR + char_index);
if (!rc) {
return rc;
}
/*
* the display expects the custom character as 8 lines of 5 bit each, shades are not
* supported
*/
for (int l = 0; l < SERLCD_CUSTOM_CHAR_HEIGHT; ++l) {
uint8_t buffer = 0;
for (int i = 0; i < SERLCD_CUSTOM_CHAR_WIDTH; ++i) {
if (character->data[(l * 5) + i]) {
buffer |= BIT(4 - i);
}
}
rc = i2c_write_dt(&config->bus, &buffer, sizeof(buffer));
if (!rc) {
return rc;
}
}
return rc;
}
static void auxdisplay_serlcd_advance_current_position(const struct device *dev)
{
const struct auxdisplay_serlcd_config *config = dev->config;
struct auxdisplay_serlcd_data *data = dev->data;
++(data->cursor_x);
if (data->cursor_x >= config->capabilities.columns) {
data->cursor_x = 0;
++(data->cursor_y);
}
if (data->cursor_y >= config->capabilities.rows) {
data->cursor_y = 0;
}
}
static int auxdisplay_serlcd_write(const struct device *dev, const uint8_t *text, uint16_t len)
{
const struct auxdisplay_serlcd_config *config = dev->config;
int rc = 0;
/*
* the display wraps around by itself, just write the text and update the position data
*/
for (int i = 0; i < len; ++i) {
uint8_t character = text[i];
/*
* customer characters require a special command, so check for custom char
*/
if ((character & SERLCD_CUSTOM_CHAR_BITMASK) == SERLCD_CUSTOM_CHAR_INDEX_BASE) {
const uint8_t command = SERLCD_COMMAND_WRITE_CUSTOM_CHAR +
(character & ~SERLCD_CUSTOM_CHAR_BITMASK);
rc = auxdisplay_serlcd_send_command(dev, command);
if (!rc) {
return rc;
}
auxdisplay_serlcd_advance_current_position(dev);
} else if (character == SERLCD_BEGIN_COMMAND ||
character == SERLCD_BEGIN_SPECIAL_COMMAND) {
/*
* skip these characters in text, as they have a special meaning, if
* required a custom character can be used as replacement
*/
continue;
} else {
rc = i2c_write_dt(&config->bus, text, len);
if (!rc) {
return rc;
}
auxdisplay_serlcd_advance_current_position(dev);
}
}
return rc;
}
static int auxdisplay_serlcd_init(const struct device *dev)
{
const struct auxdisplay_serlcd_config *config = dev->config;
struct auxdisplay_serlcd_data *data = dev->data;
/*
* Initialize our data structure
*/
data->power = true;
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
auxdisplay_serlcd_clear(dev);
return 0;
}
static const struct auxdisplay_driver_api auxdisplay_serlcd_auxdisplay_api = {
.display_on = auxdisplay_serlcd_display_on,
.display_off = auxdisplay_serlcd_display_off,
.cursor_set_enabled = auxdisplay_serlcd_cursor_set_enabled,
.position_blinking_set_enabled = auxdisplay_serlcd_position_blinking_set_enabled,
.cursor_position_set = auxdisplay_serlcd_cursor_position_set,
.cursor_position_get = auxdisplay_serlcd_cursor_position_get,
.capabilities_get = auxdisplay_serlcd_capabilities_get,
.clear = auxdisplay_serlcd_clear,
.custom_character_set = auxdisplay_serlcd_custom_character_set,
.write = auxdisplay_serlcd_write,
};
#define AUXDISPLAY_SERLCD_INST(inst) \
static const struct auxdisplay_serlcd_config auxdisplay_serlcd_config_##inst = { \
.capabilities = { \
.columns = DT_INST_PROP(inst, columns), \
.rows = DT_INST_PROP(inst, rows), \
.mode = 0, \
.brightness.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.brightness.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.custom_characters = SERLCD_CUSTOM_CHAR_MAX_COUNT, \
.custom_character_width = SERLCD_CUSTOM_CHAR_WIDTH, \
.custom_character_height = SERLCD_CUSTOM_CHAR_HEIGHT, \
}, \
.bus = I2C_DT_SPEC_INST_GET(inst), \
.command_delay_ms = DT_INST_PROP(inst, command_delay_ms), \
.special_command_delay_ms = DT_INST_PROP(inst, special_command_delay_ms), \
}; \
\
static struct auxdisplay_serlcd_data auxdisplay_serlcd_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, &auxdisplay_serlcd_init, NULL, &auxdisplay_serlcd_data_##inst, \
&auxdisplay_serlcd_config_##inst, POST_KERNEL, \
CONFIG_AUXDISPLAY_INIT_PRIORITY, &auxdisplay_serlcd_auxdisplay_api);
DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_SERLCD_INST)
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_serlcd.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,967 |
```unknown
config AUXDISPLAY_JHD1313
bool "Jinghua Display JHD1313 driver"
default y
select I2C
depends on DT_HAS_JHD_JHD1313_ENABLED
help
Enable driver for Jinghua Display JHD1313 display.
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig.jhd1313 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#define DT_DRV_COMPAT jhd_jhd1313
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(auxdisplay_jhd1313, CONFIG_AUXDISPLAY_LOG_LEVEL);
#define JHD1313_BACKLIGHT_ADDR (0x62)
/* Defines for the JHD1313_CMD_CURSOR_SHIFT */
#define JHD1313_CS_DISPLAY_SHIFT (1 << 3)
#define JHD1313_CS_RIGHT_SHIFT (1 << 2)
/* Defines for the JHD1313_CMD_INPUT_SET to change text direction */
#define JHD1313_IS_INCREMENT (1 << 1)
#define JHD1313_IS_DECREMENT (0 << 1)
#define JHD1313_IS_SHIFT (1 << 0)
/* Defines for the JHD1313_CMD_FUNCTION_SET */
#define JHD1313_FS_8BIT_MODE (1 << 4)
#define JHD1313_FS_ROWS_2 (1 << 3)
#define JHD1313_FS_ROWS_1 (0 << 3)
#define JHD1313_FS_DOT_SIZE_BIG (1 << 2)
#define JHD1313_FS_DOT_SIZE_LITTLE (0 << 2)
/* LCD Display Commands */
#define JHD1313_CMD_SCREEN_CLEAR (1 << 0)
#define JHD1313_CMD_CURSOR_RETURN (1 << 1)
#define JHD1313_CMD_INPUT_SET (1 << 2)
#define JHD1313_CMD_DISPLAY_SWITCH (1 << 3)
#define JHD1313_CMD_CURSOR_SHIFT (1 << 4)
#define JHD1313_CMD_FUNCTION_SET (1 << 5)
#define JHD1313_CMD_SET_CGRAM_ADDR (1 << 6)
#define JHD1313_CMD_SET_DDRAM_ADDR (1 << 7)
#define JHD1313_DS_DISPLAY_ON (1 << 2)
#define JHD1313_DS_CURSOR_ON (1 << 1)
#define JHD1313_DS_BLINK_ON (1 << 0)
#define JHD1313_LED_REG_R 0x04
#define JHD1313_LED_REG_G 0x03
#define JHD1313_LED_REG_B 0x02
#define JHD1313_LINE_FIRST 0x80
#define JHD1313_LINE_SECOND 0xC0
#define CLEAR_DELAY_MS 20
#define UPDATE_DELAY_MS 5
struct auxdisplay_jhd1313_data {
uint8_t input_set;
bool power;
bool cursor;
bool blinking;
uint8_t function;
uint8_t backlight;
};
struct auxdisplay_jhd1313_config {
struct auxdisplay_capabilities capabilities;
struct i2c_dt_spec bus;
};
static const uint8_t colour_define[][4] = {
{ 0, 0, 0 }, /* Off */
{ 255, 255, 255 }, /* White */
{ 255, 0, 0 }, /* Red */
{ 0, 255, 0 }, /* Green */
{ 0, 0, 255 }, /* Blue */
};
static void auxdisplay_jhd1313_reg_set(const struct device *i2c, uint8_t addr, uint8_t data)
{
uint8_t command[2] = { addr, data };
i2c_write(i2c, command, sizeof(command), JHD1313_BACKLIGHT_ADDR);
}
static int auxdisplay_jhd1313_print(const struct device *dev, const uint8_t *data, uint16_t size)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
uint8_t buf[] = { JHD1313_CMD_SET_CGRAM_ADDR, 0 };
int rc = 0;
int16_t i;
for (i = 0; i < size; i++) {
buf[1] = data[i];
rc = i2c_write_dt(&config->bus, buf, sizeof(buf));
}
return rc;
}
static int auxdisplay_jhd1313_cursor_position_set(const struct device *dev,
enum auxdisplay_position type, int16_t x,
int16_t y)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
unsigned char data[2];
if (type != AUXDISPLAY_POSITION_ABSOLUTE) {
return -EINVAL;
}
if (y == 0U) {
x |= JHD1313_LINE_FIRST;
} else {
x |= JHD1313_LINE_SECOND;
}
data[0] = JHD1313_CMD_SET_DDRAM_ADDR;
data[1] = x;
return i2c_write_dt(&config->bus, data, 2);
}
static int auxdisplay_jhd1313_clear(const struct device *dev)
{
int rc;
const struct auxdisplay_jhd1313_config *config = dev->config;
uint8_t clear[] = { 0, JHD1313_CMD_SCREEN_CLEAR };
rc = i2c_write_dt(&config->bus, clear, sizeof(clear));
LOG_DBG("Clear, delay 20 ms");
k_sleep(K_MSEC(CLEAR_DELAY_MS));
return rc;
}
static int auxdisplay_jhd1313_update_display_state(
const struct auxdisplay_jhd1313_config *config,
struct auxdisplay_jhd1313_data *data)
{
int rc;
uint8_t buf[] = { 0, JHD1313_CMD_DISPLAY_SWITCH };
if (data->power) {
buf[1] |= JHD1313_DS_DISPLAY_ON;
}
if (data->cursor) {
buf[1] |= JHD1313_DS_CURSOR_ON;
}
if (data->blinking) {
buf[1] |= JHD1313_DS_BLINK_ON;
}
rc = i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("Set display_state options, delay 5 ms");
k_sleep(K_MSEC(UPDATE_DELAY_MS));
return rc;
}
static int auxdisplay_jhd1313_cursor_set_enabled(const struct device *dev, bool enabled)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
data->cursor = enabled;
return auxdisplay_jhd1313_update_display_state(config, data);
}
static int auxdisplay_jhd1313_position_blinking_set_enabled(const struct device *dev, bool enabled)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
data->blinking = enabled;
return auxdisplay_jhd1313_update_display_state(config, data);
}
static void auxdisplay_jhd1313_input_state_set(const struct device *dev, uint8_t opt)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
uint8_t buf[] = { 0, 0 };
data->input_set = opt;
buf[1] = (opt | JHD1313_CMD_INPUT_SET);
i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("Set the input_set, no delay");
}
static int auxdisplay_jhd1313_backlight_set(const struct device *dev, uint8_t colour)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
if (colour > ARRAY_SIZE(colour_define)) {
LOG_WRN("Selected colour is too high a value");
return -EINVAL;
}
data->backlight = colour;
auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_R, colour_define[colour][0]);
auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_G, colour_define[colour][1]);
auxdisplay_jhd1313_reg_set(config->bus.bus, JHD1313_LED_REG_B, colour_define[colour][2]);
return 0;
}
static int auxdisplay_jhd1313_backlight_get(const struct device *dev, uint8_t *backlight)
{
struct auxdisplay_jhd1313_data *data = dev->data;
*backlight = data->backlight;
return 0;
}
static void auxdisplay_jhd1313_function_set(const struct device *dev, uint8_t opt)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
uint8_t buf[] = { 0, 0 };
data->function = opt;
buf[1] = (opt | JHD1313_CMD_FUNCTION_SET);
i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("Set function options, delay 5 ms");
k_sleep(K_MSEC(5));
}
static int auxdisplay_jhd1313_initialize(const struct device *dev)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
uint8_t cmd;
LOG_DBG("Initialize called");
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
/*
* Initialization sequence from the data sheet:
* 1 - Power on
* - Wait for more than 30 ms AFTER VDD rises to 4.5v
* 2 - Send FUNCTION set
* - Wait for 39 us
* 3 - Send DISPLAY Control
* - wait for 39 us
* 4 - send DISPLAY Clear
* - wait for 1.5 ms
* 5 - send ENTRY Mode
* 6 - Initialization is done
*/
/*
* We're here! Let's just make sure we've had enough time for the
* VDD to power on, so pause a little here, 30 ms min, so we go 50
*/
LOG_DBG("Delay 50 ms while the VDD powers on");
k_sleep(K_MSEC(50));
/* Configure everything for the display function first */
cmd = JHD1313_CMD_FUNCTION_SET | JHD1313_FS_ROWS_2;
auxdisplay_jhd1313_function_set(dev, cmd);
/* Turn the display on - by default no cursor and no blinking */
auxdisplay_jhd1313_update_display_state(config, data);
/* Clear the screen */
auxdisplay_jhd1313_clear(dev);
/*
* Initialize to the default text direction for romance languages
* (increment, no shift)
*/
cmd = JHD1313_IS_INCREMENT;
auxdisplay_jhd1313_input_state_set(dev, cmd);
/* Now power on the background RGB control */
LOG_INF("Configuring the RGB background");
auxdisplay_jhd1313_reg_set(config->bus.bus, 0x00, 0x00);
auxdisplay_jhd1313_reg_set(config->bus.bus, 0x01, 0x05);
auxdisplay_jhd1313_reg_set(config->bus.bus, 0x08, 0xAA);
/* Now set the background colour to black */
LOG_DBG("Background set to off");
auxdisplay_jhd1313_backlight_set(dev, 0);
return 0;
}
static int auxdisplay_jhd1313_display_on(const struct device *dev)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
data->power = true;
return auxdisplay_jhd1313_update_display_state(config, data);
}
static int auxdisplay_jhd1313_display_off(const struct device *dev)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
struct auxdisplay_jhd1313_data *data = dev->data;
data->power = false;
return auxdisplay_jhd1313_update_display_state(config, data);
}
static int auxdisplay_jhd1313_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
const struct auxdisplay_jhd1313_config *config = dev->config;
memcpy(capabilities, &config->capabilities, sizeof(struct auxdisplay_capabilities));
return 0;
}
static const struct auxdisplay_driver_api auxdisplay_jhd1313_auxdisplay_api = {
.display_on = auxdisplay_jhd1313_display_on,
.display_off = auxdisplay_jhd1313_display_off,
.cursor_set_enabled = auxdisplay_jhd1313_cursor_set_enabled,
.position_blinking_set_enabled = auxdisplay_jhd1313_position_blinking_set_enabled,
.cursor_position_set = auxdisplay_jhd1313_cursor_position_set,
.capabilities_get = auxdisplay_jhd1313_capabilities_get,
.clear = auxdisplay_jhd1313_clear,
.backlight_get = auxdisplay_jhd1313_backlight_get,
.backlight_set = auxdisplay_jhd1313_backlight_set,
.write = auxdisplay_jhd1313_print,
};
#define AUXDISPLAY_JHD1313_DEVICE(inst) \
static const struct auxdisplay_jhd1313_config auxdisplay_jhd1313_config_##inst = { \
.capabilities = { \
.columns = 16, \
.rows = 2, \
.mode = 0, \
.brightness.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.brightness.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.minimum = 0, \
.backlight.maximum = ARRAY_SIZE(colour_define), \
.custom_characters = 0, \
}, \
.bus = I2C_DT_SPEC_INST_GET(inst), \
}; \
static struct auxdisplay_jhd1313_data auxdisplay_jhd1313_data_##inst = { \
.power = true, \
.cursor = false, \
.blinking = false, \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&auxdisplay_jhd1313_initialize, \
NULL, \
&auxdisplay_jhd1313_data_##inst, \
&auxdisplay_jhd1313_config_##inst, \
POST_KERNEL, \
CONFIG_AUXDISPLAY_INIT_PRIORITY, \
&auxdisplay_jhd1313_auxdisplay_api);
DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_JHD1313_DEVICE)
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_jhd1313.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,190 |
```unknown
config AUXDISPLAY_ITRON
bool "Noritake Itron VFD driver"
default y
select GPIO
select SERIAL
depends on DT_HAS_NORITAKE_ITRON_ENABLED
help
Enable driver for Noritake Itron VFD.
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig.itron | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
config AUXDISPLAY_HD44780
bool "Hitachi HD44780 LCD driver"
default y
depends on DT_HAS_HIT_HD44780_ENABLED
help
Enable driver for Hitachi HD44780 and compatible LCDs.
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig.hd44780 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT noritake_itron
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
#include "auxdisplay_itron.h"
LOG_MODULE_REGISTER(auxdisplay_itron, CONFIG_AUXDISPLAY_LOG_LEVEL);
/* Display commands */
#define AUXDISPLAY_ITRON_CMD_USER_SETTING 0x1f
#define AUXDISPLAY_ITRON_CMD_ESCAPE 0x1b
#define AUXDISPLAY_ITRON_CMD_BRIGHTNESS 0x58
#define AUXDISPLAY_ITRON_CMD_DISPLAY_CLEAR 0x0c
#define AUXDISPLAY_ITRON_CMD_CURSOR 0x43
#define AUXDISPLAY_ITRON_CMD_CURSOR_SET 0x24
#define AUXDISPLAY_ITRON_CMD_ACTION 0x28
#define AUXDISPLAY_ITRON_CMD_N 0x61
#define AUXDISPLAY_ITRON_CMD_SCREEN_SAVER 0x40
/* Time values when multithreading is disabled */
#define AUXDISPLAY_ITRON_RESET_TIME K_MSEC(2)
#define AUXDISPLAY_ITRON_RESET_WAIT_TIME K_MSEC(101)
#define AUXDISPLAY_ITRON_BUSY_DELAY_TIME_CHECK K_MSEC(4)
#define AUXDISPLAY_ITRON_BUSY_WAIT_LOOPS 125
/* Time values when multithreading is enabled */
#define AUXDISPLAY_ITRON_BUSY_MAX_TIME K_MSEC(500)
struct auxdisplay_itron_data {
uint16_t character_x;
uint16_t character_y;
uint8_t brightness;
bool powered;
#ifdef CONFIG_MULTITHREADING
struct k_sem lock_sem;
struct k_sem busy_wait_sem;
struct gpio_callback busy_wait_callback;
#endif
};
struct auxdisplay_itron_config {
const struct device *uart;
struct auxdisplay_capabilities capabilities;
struct gpio_dt_spec reset_gpio;
struct gpio_dt_spec busy_gpio;
};
static int send_cmd(const struct device *dev, const uint8_t *command, uint8_t length, bool pm,
bool lock);
static int auxdisplay_itron_is_busy(const struct device *dev);
static int auxdisplay_itron_clear(const struct device *dev);
static int auxdisplay_itron_set_powered(const struct device *dev, bool enabled);
#ifdef CONFIG_MULTITHREADING
void auxdisplay_itron_busy_gpio_change_callback(const struct device *port,
struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct auxdisplay_itron_data *data = CONTAINER_OF(cb,
struct auxdisplay_itron_data, busy_wait_callback);
k_sem_give(&data->busy_wait_sem);
}
#endif
static int auxdisplay_itron_init(const struct device *dev)
{
const struct auxdisplay_itron_config *config = dev->config;
struct auxdisplay_itron_data *data = dev->data;
int rc;
if (!device_is_ready(config->uart)) {
LOG_ERR("UART device not ready");
return -ENODEV;
}
/* Configure and set busy GPIO */
if (config->busy_gpio.port) {
rc = gpio_pin_configure_dt(&config->busy_gpio, GPIO_INPUT);
if (rc < 0) {
LOG_ERR("Configuration of text display busy GPIO failed: %d", rc);
return rc;
}
#ifdef CONFIG_MULTITHREADING
k_sem_init(&data->lock_sem, 1, 1);
k_sem_init(&data->busy_wait_sem, 0, 1);
gpio_init_callback(&data->busy_wait_callback,
auxdisplay_itron_busy_gpio_change_callback,
BIT(config->busy_gpio.pin));
rc = gpio_add_callback(config->busy_gpio.port, &data->busy_wait_callback);
if (rc != 0) {
LOG_ERR("Configuration of busy interrupt failed: %d", rc);
return rc;
}
#endif
}
/* Configure and set reset GPIO */
if (config->reset_gpio.port) {
rc = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (rc < 0) {
LOG_ERR("Configuration of text display reset GPIO failed");
return rc;
}
}
data->character_x = 0;
data->character_y = 0;
data->brightness = 0;
/* Reset display to known configuration */
if (config->reset_gpio.port) {
uint8_t wait_loops = 0;
gpio_pin_set_dt(&config->reset_gpio, 1);
k_sleep(AUXDISPLAY_ITRON_RESET_TIME);
gpio_pin_set_dt(&config->reset_gpio, 0);
k_sleep(AUXDISPLAY_ITRON_RESET_WAIT_TIME);
while (auxdisplay_itron_is_busy(dev) == 1) {
/* Display is busy, wait */
k_sleep(AUXDISPLAY_ITRON_BUSY_DELAY_TIME_CHECK);
++wait_loops;
if (wait_loops >= AUXDISPLAY_ITRON_BUSY_WAIT_LOOPS) {
/* Waited long enough for display not to be busy, bailing */
return -EIO;
}
}
} else {
/* Ensure display is powered on so that it can be initialised */
(void)auxdisplay_itron_set_powered(dev, true);
auxdisplay_itron_clear(dev);
}
return 0;
}
static int auxdisplay_itron_set_powered(const struct device *dev, bool enabled)
{
int rc = 0;
uint8_t cmd[] = {AUXDISPLAY_ITRON_CMD_USER_SETTING, AUXDISPLAY_ITRON_CMD_ACTION,
AUXDISPLAY_ITRON_CMD_N, AUXDISPLAY_ITRON_CMD_SCREEN_SAVER, 0};
if (enabled) {
cmd[4] = 1;
}
return send_cmd(dev, cmd, sizeof(cmd), true, true);
}
static bool auxdisplay_itron_is_powered(const struct device *dev)
{
struct auxdisplay_itron_data *data = dev->data;
bool is_powered;
#ifdef CONFIG_MULTITHREADING
k_sem_take(&data->lock_sem, K_FOREVER);
#endif
is_powered = data->powered;
#ifdef CONFIG_MULTITHREADING
k_sem_give(&data->lock_sem);
#endif
return is_powered;
}
static int auxdisplay_itron_display_on(const struct device *dev)
{
return auxdisplay_itron_set_powered(dev, true);
}
static int auxdisplay_itron_display_off(const struct device *dev)
{
return auxdisplay_itron_set_powered(dev, false);
}
static int auxdisplay_itron_cursor_set_enabled(const struct device *dev, bool enabled)
{
uint8_t cmd[] = {AUXDISPLAY_ITRON_CMD_USER_SETTING, AUXDISPLAY_ITRON_CMD_CURSOR,
(uint8_t)enabled};
return send_cmd(dev, cmd, sizeof(cmd), false, true);
}
static int auxdisplay_itron_cursor_position_set(const struct device *dev,
enum auxdisplay_position type,
int16_t x, int16_t y)
{
uint8_t cmd[] = {AUXDISPLAY_ITRON_CMD_USER_SETTING, AUXDISPLAY_ITRON_CMD_CURSOR_SET,
0, 0, 0, 0};
if (type != AUXDISPLAY_POSITION_ABSOLUTE) {
return -EINVAL;
}
sys_put_le16(x, &cmd[2]);
sys_put_le16(y, &cmd[4]);
return send_cmd(dev, cmd, sizeof(cmd), false, true);
}
static int auxdisplay_itron_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
const struct auxdisplay_itron_config *config = dev->config;
memcpy(capabilities, &config->capabilities, sizeof(struct auxdisplay_capabilities));
return 0;
}
static int auxdisplay_itron_clear(const struct device *dev)
{
uint8_t cmd[] = {AUXDISPLAY_ITRON_CMD_DISPLAY_CLEAR};
return send_cmd(dev, cmd, sizeof(cmd), false, true);
}
static int auxdisplay_itron_brightness_get(const struct device *dev, uint8_t *brightness)
{
struct auxdisplay_itron_data *data = dev->data;
#ifdef CONFIG_MULTITHREADING
k_sem_take(&data->lock_sem, K_FOREVER);
#endif
*brightness = data->brightness;
#ifdef CONFIG_MULTITHREADING
k_sem_give(&data->lock_sem);
#endif
return 0;
}
static int auxdisplay_itron_brightness_set(const struct device *dev, uint8_t brightness)
{
struct auxdisplay_itron_data *data = dev->data;
uint8_t cmd[] = {AUXDISPLAY_ITRON_CMD_USER_SETTING, AUXDISPLAY_ITRON_CMD_BRIGHTNESS,
brightness};
int rc;
if (brightness < AUXDISPLAY_ITRON_BRIGHTNESS_MIN ||
brightness > AUXDISPLAY_ITRON_BRIGHTNESS_MAX) {
return -EINVAL;
}
#ifdef CONFIG_MULTITHREADING
k_sem_take(&data->lock_sem, K_FOREVER);
#endif
rc = send_cmd(dev, cmd, sizeof(cmd), false, false);
if (rc == 0) {
data->brightness = brightness;
}
#ifdef CONFIG_MULTITHREADING
k_sem_give(&data->lock_sem);
#endif
return rc;
}
static int auxdisplay_itron_is_busy(const struct device *dev)
{
const struct auxdisplay_itron_config *config = dev->config;
int rc;
if (config->busy_gpio.port == NULL) {
return -ENOTSUP;
}
rc = gpio_pin_get_dt(&config->busy_gpio);
return rc;
}
static int auxdisplay_itron_is_busy_check(const struct device *dev)
{
struct auxdisplay_itron_data *data = dev->data;
int rc;
#ifdef CONFIG_MULTITHREADING
k_sem_take(&data->lock_sem, K_FOREVER);
#endif
rc = auxdisplay_itron_is_busy(dev);
#ifdef CONFIG_MULTITHREADING
k_sem_give(&data->lock_sem);
#endif
return rc;
}
static int send_cmd(const struct device *dev, const uint8_t *command, uint8_t length, bool pm,
bool lock)
{
uint8_t i = 0;
const struct auxdisplay_itron_config *config = dev->config;
const struct device *uart = config->uart;
int rc = 0;
#ifdef CONFIG_MULTITHREADING
struct auxdisplay_itron_data *data = dev->data;
#endif
if (pm == false && auxdisplay_itron_is_powered(dev) == false) {
/* Display is not powered, only PM commands can be used */
return -ESHUTDOWN;
}
#ifdef CONFIG_MULTITHREADING
if (lock) {
k_sem_take(&data->lock_sem, K_FOREVER);
}
#endif
#ifdef CONFIG_MULTITHREADING
/* Enable interrupt triggering */
rc = gpio_pin_interrupt_configure_dt(&config->busy_gpio, GPIO_INT_EDGE_TO_INACTIVE);
if (rc != 0) {
LOG_ERR("Failed to enable busy interrupt: %d", rc);
goto end;
}
#endif
while (i < length) {
#ifdef CONFIG_MULTITHREADING
if (auxdisplay_itron_is_busy(dev) == 1) {
if (k_sem_take(&data->busy_wait_sem,
AUXDISPLAY_ITRON_BUSY_MAX_TIME) != 0) {
rc = -EIO;
goto cleanup;
}
}
#else
uint8_t wait_loops = 0;
while (auxdisplay_itron_is_busy(dev) == 1) {
/* Display is busy, wait */
k_sleep(AUXDISPLAY_ITRON_BUSY_DELAY_TIME_CHECK);
++wait_loops;
if (wait_loops >= AUXDISPLAY_ITRON_BUSY_WAIT_LOOPS) {
/* Waited long enough for display not to be busy, bailing */
return -EIO;
}
}
#endif
uart_poll_out(uart, command[i]);
++i;
}
#ifdef CONFIG_MULTITHREADING
cleanup:
(void)gpio_pin_interrupt_configure_dt(&config->busy_gpio, GPIO_INT_DISABLE);
#endif
end:
#ifdef CONFIG_MULTITHREADING
if (lock) {
k_sem_give(&data->lock_sem);
}
#endif
return rc;
}
static int auxdisplay_itron_write(const struct device *dev, const uint8_t *data, uint16_t len)
{
uint16_t i = 0;
/* Check all characters are valid */
while (i < len) {
if (data[i] < AUXDISPLAY_ITRON_CHARACTER_MIN &&
data[i] != AUXDISPLAY_ITRON_CHARACTER_BACK_SPACE &&
data[i] != AUXDISPLAY_ITRON_CHARACTER_TAB &&
data[i] != AUXDISPLAY_ITRON_CHARACTER_LINE_FEED &&
data[i] != AUXDISPLAY_ITRON_CHARACTER_CARRIAGE_RETURN) {
return -EINVAL;
}
++i;
}
return send_cmd(dev, data, len, false, true);
}
static const struct auxdisplay_driver_api auxdisplay_itron_auxdisplay_api = {
.display_on = auxdisplay_itron_display_on,
.display_off = auxdisplay_itron_display_off,
.cursor_set_enabled = auxdisplay_itron_cursor_set_enabled,
.cursor_position_set = auxdisplay_itron_cursor_position_set,
.capabilities_get = auxdisplay_itron_capabilities_get,
.clear = auxdisplay_itron_clear,
.brightness_get = auxdisplay_itron_brightness_get,
.brightness_set = auxdisplay_itron_brightness_set,
.is_busy = auxdisplay_itron_is_busy_check,
.write = auxdisplay_itron_write,
};
#define AUXDISPLAY_ITRON_DEVICE(inst) \
static struct auxdisplay_itron_data auxdisplay_itron_data_##inst; \
static const struct auxdisplay_itron_config auxdisplay_itron_config_##inst = { \
.uart = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.capabilities = { \
.columns = DT_INST_PROP(inst, columns), \
.rows = DT_INST_PROP(inst, rows), \
.mode = AUXDISPLAY_ITRON_MODE_UART, \
.brightness.minimum = AUXDISPLAY_ITRON_BRIGHTNESS_MIN, \
.brightness.maximum = AUXDISPLAY_ITRON_BRIGHTNESS_MAX, \
.backlight.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
}, \
.busy_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, busy_gpios, {0}), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&auxdisplay_itron_init, \
NULL, \
&auxdisplay_itron_data_##inst, \
&auxdisplay_itron_config_##inst, \
POST_KERNEL, \
CONFIG_AUXDISPLAY_INIT_PRIORITY, \
&auxdisplay_itron_auxdisplay_api);
DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_ITRON_DEVICE)
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_itron.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,170 |
```c
/*
*
*/
#define DT_DRV_COMPAT ptc_pt6314
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
/* Defines for the PT6314_INST_DISPLAY_ON_OFF */
#define PT6314_DO_BLINKING_ON (1 << 0)
#define PT6314_DO_CURSOR_ON (1 << 1)
#define PT6314_DO_DISPLAY_ON (1 << 2)
/* Defines for the PT6314_INST_FUNCTION_SET */
#define PT6314_FS_BRIGHTNESS(BR) (4 - (BR & BIT_MASK(2)))
#define PT6314_FS_ROWS_1 (0 << 3)
#define PT6314_FS_ROWS_2 (1 << 3)
#define PT6314_FS_8BIT_MODE (1 << 4)
#define PT6314_BRIGHTNESS_MIN 1
#define PT6314_BRIGHTNESS_MAX 4
/* Defines for the PT6314_INST_DDRAM_ADDRESS_SET */
#define PT6314_DA_BASE_ROW_1 (0x00)
#define PT6314_DA_BASE_ROW_2 (0x40)
/* Display Commands */
#define PT6314_INST_CLEAR_DISPLAY BIT(0)
#define PT6314_INST_CURSOR_HOME BIT(1)
#define PT6314_INST_ENTRY_MODE_SET BIT(2)
#define PT6314_INST_DISPLAY_ON_OFF BIT(3)
#define PT6314_INST_CURSOR_OR_DISPLAY_SHIFT BIT(4)
#define PT6314_INST_FUNCTION_SET BIT(5)
#define PT6314_INST_CGRAM_ADDRESS_SET BIT(6)
#define PT6314_INST_DDRAM_ADDRESS_SET BIT(7)
/* Start Byte */
#define PT6314_SB_RS_INST (0 << 1)
#define PT6314_SB_RS_DATA (1 << 1)
#define PT6314_SB_RW_WRITE (0 << 2)
#define PT6314_SB_RW_READ (1 << 2)
#define PT6314_SB_SYNC_BITS (BIT_MASK(5) << 3)
struct auxdisplay_pt6314_data {
bool power;
bool cursor;
bool blinking;
uint8_t brightness;
uint16_t cursor_x;
uint16_t cursor_y;
};
struct auxdisplay_pt6314_config {
struct auxdisplay_capabilities capabilities;
struct spi_dt_spec bus;
};
static int auxdisplay_pt6314_spi_write(const struct device *dev, uint8_t flags, uint8_t val)
{
const struct auxdisplay_pt6314_config *config = dev->config;
uint8_t buf[2] = {PT6314_SB_SYNC_BITS | PT6314_SB_RW_WRITE | flags, val};
struct spi_buf tx_buf[] = {{.buf = buf, .len = sizeof(buf)}};
const struct spi_buf_set tx = {.buffers = tx_buf, .count = 1};
return spi_write_dt(&config->bus, &tx);
}
static inline int auxdisplay_pt6314_inst(const struct device *dev, uint8_t inst)
{
return auxdisplay_pt6314_spi_write(dev, PT6314_SB_RS_INST, inst);
}
static inline int auxdisplay_pt6314_data(const struct device *dev, uint8_t data)
{
return auxdisplay_pt6314_spi_write(dev, PT6314_SB_RS_DATA, data);
}
static int auxdisplay_pt6314_display_on_off(const struct device *dev)
{
struct auxdisplay_pt6314_data *data = dev->data;
uint8_t inst;
inst = (data->power ? PT6314_DO_DISPLAY_ON : 0) | (data->cursor ? PT6314_DO_CURSOR_ON : 0) |
(data->blinking ? PT6314_DO_BLINKING_ON : 0);
return auxdisplay_pt6314_inst(dev, PT6314_INST_DISPLAY_ON_OFF | inst);
}
static int auxdisplay_pt6314_function_set(const struct device *dev)
{
const struct auxdisplay_pt6314_config *config = dev->config;
struct auxdisplay_pt6314_data *data = dev->data;
uint8_t inst;
inst = PT6314_FS_8BIT_MODE |
(config->capabilities.rows == 2 ? PT6314_FS_ROWS_2 : PT6314_FS_ROWS_1) |
PT6314_FS_BRIGHTNESS(data->brightness);
return auxdisplay_pt6314_inst(dev, PT6314_INST_FUNCTION_SET | inst);
}
static int auxdisplay_pt6314_ddram_address_set(const struct device *dev)
{
struct auxdisplay_pt6314_data *data = dev->data;
uint8_t inst;
inst = (data->cursor_y == 0 ? PT6314_DA_BASE_ROW_1 : PT6314_DA_BASE_ROW_2) + data->cursor_x;
return auxdisplay_pt6314_inst(dev, PT6314_INST_DDRAM_ADDRESS_SET | inst);
}
static int auxdisplay_pt6314_display_on(const struct device *dev)
{
struct auxdisplay_pt6314_data *data = dev->data;
data->power = true;
return auxdisplay_pt6314_display_on_off(dev);
}
static int auxdisplay_pt6314_display_off(const struct device *dev)
{
struct auxdisplay_pt6314_data *data = dev->data;
data->power = false;
return auxdisplay_pt6314_display_on_off(dev);
}
static int auxdisplay_pt6314_cursor_set_enabled(const struct device *dev, bool enable)
{
struct auxdisplay_pt6314_data *data = dev->data;
data->cursor = enable;
return auxdisplay_pt6314_display_on_off(dev);
}
static int auxdisplay_pt6314_position_blinking_set_enabled(const struct device *dev, bool enable)
{
struct auxdisplay_pt6314_data *data = dev->data;
data->blinking = enable;
return auxdisplay_pt6314_display_on_off(dev);
}
static int auxdisplay_pt6314_cursor_position_set(const struct device *dev,
enum auxdisplay_position type, int16_t x,
int16_t y)
{
const struct auxdisplay_pt6314_config *config = dev->config;
struct auxdisplay_pt6314_data *data = dev->data;
uint8_t inst;
if (type == AUXDISPLAY_POSITION_RELATIVE) {
x += data->cursor_x;
y += data->cursor_y;
} else if (type == AUXDISPLAY_POSITION_RELATIVE_DIRECTION) {
return -EINVAL;
}
if (x < 0 || y < 0) {
return -EINVAL;
} else if (x >= config->capabilities.columns || y >= config->capabilities.rows) {
return -EINVAL;
}
data->cursor_x = (uint16_t)x;
data->cursor_y = (uint16_t)y;
return auxdisplay_pt6314_ddram_address_set(dev);
}
static int auxdisplay_pt6314_cursor_position_get(const struct device *dev, int16_t *x, int16_t *y)
{
struct auxdisplay_pt6314_data *data = dev->data;
*x = (int16_t)data->cursor_x;
*y = (int16_t)data->cursor_y;
return 0;
}
static int auxdisplay_pt6314_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
const struct auxdisplay_pt6314_config *config = dev->config;
memcpy(capabilities, &config->capabilities, sizeof(struct auxdisplay_capabilities));
return 0;
}
static int auxdisplay_pt6314_clear(const struct device *dev)
{
struct auxdisplay_pt6314_data *data = dev->data;
data->cursor_x = 0;
data->cursor_y = 0;
return auxdisplay_pt6314_inst(dev, PT6314_INST_CLEAR_DISPLAY);
}
static int auxdisplay_pt6314_brightness_set(const struct device *dev, uint8_t brightness)
{
struct auxdisplay_pt6314_data *data = dev->data;
if (brightness < PT6314_BRIGHTNESS_MIN || brightness > PT6314_BRIGHTNESS_MAX) {
return -EINVAL;
}
data->brightness = brightness;
return auxdisplay_pt6314_function_set(dev);
}
static int auxdisplay_pt6314_brightness_get(const struct device *dev, uint8_t *brightness)
{
struct auxdisplay_pt6314_data *data = dev->data;
*brightness = data->brightness;
return 0;
}
static int auxdisplay_pt6314_write(const struct device *dev, const uint8_t *text, uint16_t len)
{
const struct auxdisplay_pt6314_config *config = dev->config;
struct auxdisplay_pt6314_data *data = dev->data;
int ret;
int16_t i;
for (i = 0; i < len; i++) {
ret = auxdisplay_pt6314_data(dev, text[i]);
if (ret) {
return ret;
}
data->cursor_x++;
if (data->cursor_x == config->capabilities.columns) {
data->cursor_x = 0;
data->cursor_y++;
if (data->cursor_y == config->capabilities.rows) {
data->cursor_y = 0;
}
ret = auxdisplay_pt6314_ddram_address_set(dev);
if (ret) {
return ret;
}
}
}
return 0;
}
static int auxdisplay_pt6314_init(const struct device *dev)
{
const struct auxdisplay_pt6314_config *config = dev->config;
struct auxdisplay_pt6314_data *data = dev->data;
uint8_t inst;
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
auxdisplay_pt6314_function_set(dev);
auxdisplay_pt6314_display_on_off(dev);
auxdisplay_pt6314_clear(dev);
return 0;
}
static const struct auxdisplay_driver_api auxdisplay_pt6314_auxdisplay_api = {
.display_on = auxdisplay_pt6314_display_on,
.display_off = auxdisplay_pt6314_display_off,
.cursor_set_enabled = auxdisplay_pt6314_cursor_set_enabled,
.position_blinking_set_enabled = auxdisplay_pt6314_position_blinking_set_enabled,
.cursor_position_set = auxdisplay_pt6314_cursor_position_set,
.cursor_position_get = auxdisplay_pt6314_cursor_position_get,
.capabilities_get = auxdisplay_pt6314_capabilities_get,
.clear = auxdisplay_pt6314_clear,
.brightness_get = auxdisplay_pt6314_brightness_get,
.brightness_set = auxdisplay_pt6314_brightness_set,
.write = auxdisplay_pt6314_write,
};
#define AUXDISPLAY_PT6314_INST(n) \
static const struct auxdisplay_pt6314_config auxdisplay_pt6314_config_##n = { \
.capabilities = \
{ \
.columns = DT_INST_PROP(n, columns), \
.rows = DT_INST_PROP(n, rows), \
.mode = 0, \
.brightness.minimum = PT6314_BRIGHTNESS_MIN, \
.brightness.maximum = PT6314_BRIGHTNESS_MAX, \
.backlight.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.custom_characters = 0, \
}, \
.bus = SPI_DT_SPEC_INST_GET(n, \
SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | \
SPI_TRANSFER_MSB | SPI_WORD_SET(8), \
0), \
}; \
\
static struct auxdisplay_pt6314_data auxdisplay_pt6314_data_##n = { \
.power = true, \
.cursor = false, \
.blinking = false, \
.brightness = PT6314_BRIGHTNESS_MAX, \
.cursor_x = 0, \
.cursor_y = 0, \
}; \
\
DEVICE_DT_INST_DEFINE(n, &auxdisplay_pt6314_init, NULL, &auxdisplay_pt6314_data_##n, \
&auxdisplay_pt6314_config_##n, POST_KERNEL, \
CONFIG_AUXDISPLAY_INIT_PRIORITY, &auxdisplay_pt6314_auxdisplay_api);
DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_PT6314_INST)
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_pt6314.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,605 |
```c
/*
*
*/
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_auxdisplay_display_on(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_display_on(dev);
}
#include <zephyr/syscalls/auxdisplay_display_on_mrsh.c>
static inline int z_vrfy_auxdisplay_display_off(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_display_off(dev);
}
#include <zephyr/syscalls/auxdisplay_display_off_mrsh.c>
static inline int z_vrfy_auxdisplay_cursor_set_enabled(const struct device *dev, bool enabled)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_cursor_set_enabled(dev, enabled);
}
#include <zephyr/syscalls/auxdisplay_cursor_set_enabled_mrsh.c>
static inline int z_vrfy_auxdisplay_position_blinking_set_enabled(const struct device *dev,
bool enabled)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_position_blinking_set_enabled(dev, enabled);
}
#include <zephyr/syscalls/auxdisplay_position_blinking_set_enabled_mrsh.c>
static inline int z_vrfy_auxdisplay_cursor_shift_set(const struct device *dev, uint8_t direction,
bool display_shift)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_cursor_shift_set(dev, direction, display_shift);
}
#include <zephyr/syscalls/auxdisplay_cursor_shift_set_mrsh.c>
static inline int z_vrfy_auxdisplay_cursor_position_set(const struct device *dev,
enum auxdisplay_position type,
int16_t x, int16_t y)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_cursor_position_set(dev, type, x, y);
}
#include <zephyr/syscalls/auxdisplay_cursor_position_set_mrsh.c>
static inline int z_vrfy_auxdisplay_cursor_position_get(const struct device *dev, int16_t *x,
int16_t *y)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_cursor_position_get(dev, x, y);
}
#include <zephyr/syscalls/auxdisplay_cursor_position_get_mrsh.c>
static inline int z_vrfy_auxdisplay_display_position_set(const struct device *dev,
enum auxdisplay_position type,
int16_t x, int16_t y)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_display_position_set(dev, type, x, y);
}
#include <zephyr/syscalls/auxdisplay_display_position_set_mrsh.c>
static inline int z_vrfy_auxdisplay_display_position_get(const struct device *dev, int16_t *x,
int16_t *y)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_display_position_get(dev, x, y);
}
#include <zephyr/syscalls/auxdisplay_display_position_get_mrsh.c>
static inline int z_vrfy_auxdisplay_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_capabilities_get(dev, capabilities);
}
#include <zephyr/syscalls/auxdisplay_capabilities_get_mrsh.c>
static inline int z_vrfy_auxdisplay_clear(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_clear(dev);
}
#include <zephyr/syscalls/auxdisplay_clear_mrsh.c>
static inline int z_vrfy_auxdisplay_brightness_get(const struct device *dev,
uint8_t *brightness)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_brightness_get(dev, brightness);
}
#include <zephyr/syscalls/auxdisplay_brightness_get_mrsh.c>
static inline int z_vrfy_auxdisplay_brightness_set(const struct device *dev,
uint8_t brightness)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_brightness_set(dev, brightness);
}
#include <zephyr/syscalls/auxdisplay_brightness_set_mrsh.c>
static inline int z_vrfy_auxdisplay_backlight_get(const struct device *dev,
uint8_t *backlight)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_backlight_get(dev, backlight);
}
#include <zephyr/syscalls/auxdisplay_backlight_get_mrsh.c>
static inline int z_vrfy_auxdisplay_backlight_set(const struct device *dev,
uint8_t backlight)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_backlight_set(dev, backlight);
}
#include <zephyr/syscalls/auxdisplay_backlight_set_mrsh.c>
static inline int z_vrfy_auxdisplay_is_busy(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_is_busy(dev);
}
#include <zephyr/syscalls/auxdisplay_is_busy_mrsh.c>
static inline int z_vrfy_auxdisplay_custom_character_set(const struct device *dev,
struct auxdisplay_character *character)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_custom_character_set(dev, character);
}
#include <zephyr/syscalls/auxdisplay_custom_character_set_mrsh.c>
static inline int z_vrfy_auxdisplay_write(const struct device *dev, const uint8_t *data,
uint16_t len)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_write(dev, data, len);
}
#include <zephyr/syscalls/auxdisplay_write_mrsh.c>
static inline int z_vrfy_auxdisplay_custom_command(const struct device *dev,
struct auxdisplay_custom_data *data)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_AUXDISPLAY));
return z_impl_auxdisplay_custom_command(dev, data);
}
#include <zephyr/syscalls/auxdisplay_custom_command_mrsh.c>
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,372 |
```objective-c
/*
*
*/
#ifndef H_AUXDISPLAY_ITRON_
#define H_AUXDISPLAY_ITRON_
#define AUXDISPLAY_ITRON_BRIGHTNESS_MIN 1
#define AUXDISPLAY_ITRON_BRIGHTNESS_MAX 8
#define AUXDISPLAY_ITRON_CHARACTER_MIN 0x20
#define AUXDISPLAY_ITRON_CHARACTER_BACK_SPACE 0x08
#define AUXDISPLAY_ITRON_CHARACTER_TAB 0x09
#define AUXDISPLAY_ITRON_CHARACTER_LINE_FEED 0x0a
#define AUXDISPLAY_ITRON_CHARACTER_CARRIAGE_RETURN 0x0d
enum {
AUXDISPLAY_ITRON_MODE_UNKNOWN = 0,
AUXDISPLAY_ITRON_MODE_UART,
};
#endif /* H_AUXDISPLAY_ITRON_ */
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_itron.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 141 |
```unknown
# Auxiliary Display drivers
menuconfig AUXDISPLAY
bool "Auxiliary (textual) Display Drivers"
help
Enable auxiliary/texual display drivers (e.g. alphanumerical displays)
if AUXDISPLAY
config AUXDISPLAY_INIT_PRIORITY
int "Auxiliary display devices init priority"
default 85
help
Auxiliary (textual) display devices initialization priority.
module = AUXDISPLAY
module-str = auxdisplay
source "subsys/logging/Kconfig.template.log_config"
source "drivers/auxdisplay/Kconfig.hd44780"
source "drivers/auxdisplay/Kconfig.itron"
source "drivers/auxdisplay/Kconfig.jhd1313"
source "drivers/auxdisplay/Kconfig.pt6314"
source "drivers/auxdisplay/Kconfig.serlcd"
endif # AUXDISPLAY
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```unknown
config AUXDISPLAY_SERLCD
bool "SparkFun SerLCD dot character LCD driver"
default y
select I2C
depends on DT_HAS_SPARKFUN_SERLCD_ENABLED
help
Enable driver for SparkFun SerLCD.
``` | /content/code_sandbox/drivers/auxdisplay/Kconfig.serlcd | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config PINCTRL_SAM
bool "Atmel SAM pin controller driver"
default y
depends on DT_HAS_ATMEL_SAM_PINCTRL_ENABLED
help
Atmel pin controller driver is used on SAM and SAM4L SoC series
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <gpio.h>
#define ADI_MAX32_GET_PORT_ADDR_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),))
/** GPIO port addresses */
static const uint32_t gpios[] = {
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio0)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio1)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio2)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio3)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio4)
ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio5)
};
static int pinctrl_configure_pin(pinctrl_soc_pin_t soc_pin)
{
uint32_t port;
uint32_t pin;
uint32_t afx;
int pincfg;
mxc_gpio_cfg_t gpio_cfg;
port = MAX32_PINMUX_PORT(soc_pin.pinmux);
pin = MAX32_PINMUX_PIN(soc_pin.pinmux);
afx = MAX32_PINMUX_MODE(soc_pin.pinmux);
pincfg = soc_pin.pincfg;
if (gpios[port] == 0) {
return -EINVAL;
}
gpio_cfg.port = (mxc_gpio_regs_t *)gpios[port];
gpio_cfg.mask = BIT(pin);
if (pincfg & BIT(MAX32_BIAS_PULL_UP_SHIFT)) {
gpio_cfg.pad = MXC_GPIO_PAD_PULL_UP;
} else if (pincfg & BIT(MAX32_BIAS_PULL_DOWN_SHIFT)) {
gpio_cfg.pad = MXC_GPIO_PAD_PULL_DOWN;
} else {
gpio_cfg.pad = MXC_GPIO_PAD_NONE;
}
if (pincfg & BIT(MAX32_INPUT_ENABLE_SHIFT)) {
gpio_cfg.func = MXC_GPIO_FUNC_IN;
} else if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) {
gpio_cfg.func = MXC_GPIO_FUNC_OUT;
} else {
/* Add +1 to index match */
gpio_cfg.func = (mxc_gpio_func_t)(afx + 1);
}
if (pincfg & BIT(MAX32_POWER_SOURCE_SHIFT)) {
gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIOH;
} else {
gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIO;
}
switch (pincfg & MAX32_GPIO_DRV_STRENGTH_MASK) {
case MAX32_GPIO_DRV_STRENGTH_1:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_1;
break;
case MAX32_GPIO_DRV_STRENGTH_2:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_2;
break;
case MAX32_GPIO_DRV_STRENGTH_3:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_3;
break;
default:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_0;
break;
}
if (MXC_GPIO_Config(&gpio_cfg) != 0) {
return -ENOTSUP;
}
if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) {
if (pincfg & BIT(MAX32_OUTPUT_HIGH_SHIFT)) {
MXC_GPIO_OutSet(gpio_cfg.port, BIT(pin));
} else {
MXC_GPIO_OutClr(gpio_cfg.port, BIT(pin));
}
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
int ret;
for (uint8_t i = 0U; i < pin_cnt; i++) {
ret = pinctrl_configure_pin(*pins++);
if (ret) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_max32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 855 |
```c
/*
*
*/
#define DT_DRV_COMPAT quicklogic_eos_s3_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
#include <soc.h>
LOG_MODULE_REGISTER(pinctrl_eos_s3, CONFIG_PINCTRL_LOG_LEVEL);
#define FUNCTION_REGISTER(func) (func >> 13)
#define PAD_FUNC_SEL_MASK GENMASK(2, 0)
#define PAD_CTRL_SEL_BIT0 3
#define PAD_CTRL_SEL_BIT1 4
#define PAD_OUTPUT_EN_BIT 5
#define PAD_PULL_UP_BIT 6
#define PAD_PULL_DOWN_BIT 7
#define PAD_DRIVE_STRENGTH_BIT0 8
#define PAD_DRIVE_STRENGTH_BIT1 9
#define PAD_SLEW_RATE_BIT 10
#define PAD_INPUT_EN_BIT 11
#define PAD_SCHMITT_EN_BIT 12
/*
* Program IOMUX_func_SEL register.
*/
static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg)
{
volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE;
if (sel_reg <= IO_MUX_MAX_PAD_NR || sel_reg > IO_MUX_REG_MAX_OFFSET) {
return -EINVAL;
}
reg += sel_reg;
*reg = pin;
return 0;
}
/*
* Program IOMUX_PAD_x_CTRL register.
*/
static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func)
{
volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE;
if (pin > IO_MUX_REG_MAX_OFFSET) {
return -EINVAL;
}
reg += pin;
*reg = func;
return 0;
}
static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_t reg_value = 0;
/* Set function. */
reg_value |= (pin->iof & PAD_FUNC_SEL_MASK);
/* Output enable is active low. */
WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1);
/* These are active high. */
WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable);
WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate);
WRITE_BIT(reg_value, PAD_SCHMITT_EN_BIT, pin->schmitt_enable);
WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT0, pin->control_selection & BIT(0));
WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT1, pin->control_selection & BIT(1));
switch (pin->drive_strength) {
case 2:
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);
break;
case 4:
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);
break;
case 8:
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);
break;
case 12:
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);
WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);
break;
default:
LOG_ERR("Selected drive-strength is not supported: %d\n", pin->drive_strength);
}
/* Enable pull-up by default; overwrite if any setting was chosen. */
WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 1);
WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, 0);
if (pin->high_impedance) {
WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 0);
} else if (pin->pull_up | pin->pull_down) {
WRITE_BIT(reg_value, PAD_PULL_UP_BIT, pin->pull_up);
WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, pin->pull_down);
}
/* Program registers. */
pinctrl_eos_s3_set(pin->pin, reg_value);
if (pin->input_enable && FUNCTION_REGISTER(pin->iof)) {
pinctrl_eos_s3_input_selection(pin->pin, FUNCTION_REGISTER(pin->iof));
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (int i = 0; i < pin_cnt; i++) {
pinctrl_eos_s3_configure_pin(&pins[i]);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_eos_s3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,043 |
```c
/*
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_pinmux
#include <zephyr/drivers/pinctrl.h>
#include <fsl_clock.h>
#include <soc.h>
/* Port register addresses. */
static PORT_Type *ports[] = {
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
};
#define PIN(mux) (((mux) & 0xFC00000) >> 22)
#define PORT(mux) (((mux) & 0xF0000000) >> 28)
#define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK)
struct pinctrl_rv32m1_config {
clock_ip_name_t clock_ip_name;
};
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0; i < pin_cnt; i++) {
PORT_Type *base = ports[PORT(pins[i])];
uint8_t pin = PIN(pins[i]);
uint16_t mux = PINCFG(pins[i]);
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux;
}
return 0;
}
static int pinctrl_rv32m1_init(const struct device *dev)
{
const struct pinctrl_rv32m1_config *config = dev->config;
CLOCK_EnableClock(config->clock_ip_name);
return 0;
}
#define PINCTRL_RV32M1_INIT(n) \
static const struct pinctrl_rv32m1_config pinctrl_rv32m1_##n##_config = {\
.clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
&pinctrl_rv32m1_init, \
NULL, \
NULL, &pinctrl_rv32m1_##n##_config, \
PRE_KERNEL_1, \
CONFIG_PINCTRL_RV32M1_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_RV32M1_INIT)
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_rv32m1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 537 |
```c
/*
*
*/
#define DT_DRV_COMPAT sifive_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
#include <soc.h>
#define MAX_PIN_NUM DT_PROP(DT_INST_PARENT(0), ngpios)
#define PINCTRL_BASE_ADDR DT_INST_REG_ADDR(0)
#define PINCTRL_IOF_EN (PINCTRL_BASE_ADDR + 0x0)
#define PINCTRL_IOF_SEL (PINCTRL_BASE_ADDR + 0x4)
static int pinctrl_sifive_set(uint32_t pin, uint32_t func)
{
uint32_t val;
if (func > SIFIVE_PINMUX_IOF1 || pin >= MAX_PIN_NUM) {
return -EINVAL;
}
val = sys_read32(PINCTRL_IOF_SEL);
if (func == SIFIVE_PINMUX_IOF1) {
val |= (SIFIVE_PINMUX_IOF1 << pin);
} else {
val &= ~(SIFIVE_PINMUX_IOF1 << pin);
}
sys_write32(val, PINCTRL_IOF_SEL);
/* Enable IO function for this pin */
val = sys_read32(PINCTRL_IOF_EN);
val |= BIT(pin);
sys_write32(val, PINCTRL_IOF_EN);
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
int i;
for (i = 0; i < pin_cnt; i++) {
pinctrl_sifive_set(pins[i].pin, pins[i].iof);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 384 |
```unknown
config PINCTRL_TI_CC32XX
bool "TI CC32XX pinctrl driver"
default y
depends on DT_HAS_TI_CC32XX_PINCTRL_ENABLED
help
Enable the TI CC32XX pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.ti_cc32xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config PINCTRL_NXP_IOCON
bool "IOCON Pin controller driver for NXP LPC MCUs"
default y
depends on DT_HAS_NXP_LPC_IOCON_PINCTRL_ENABLED || \
DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED || \
DT_HAS_NXP_RT_IOCON_PINCTRL_ENABLED
help
Enable pin controller driver for NXP LPC MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.lpc_iocon | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
#
config PINCTRL_AMBIQ
bool "Ambiq Apollo pin controller driver"
default y
depends on DT_HAS_AMBIQ_APOLLO4_PINCTRL_ENABLED || DT_HAS_AMBIQ_APOLLO3_PINCTRL_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_GPIO
help
Ambiq Apollo pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
/* pico-sdk includes */
#include <hardware/gpio.h>
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
gpio_init(pin->pin_num);
gpio_set_function(pin->pin_num, pin->alt_func);
gpio_set_pulls(pin->pin_num, pin->pullup, pin->pulldown);
gpio_set_drive_strength(pin->pin_num, pin->drive_strength);
gpio_set_slew_rate(pin->pin_num, (pin->slew_rate ?
GPIO_SLEW_RATE_FAST : GPIO_SLEW_RATE_SLOW));
gpio_set_input_hysteresis_enabled(pin->pin_num, pin->schmitt_enable);
gpio_set_input_enabled(pin->pin_num, pin->input_enable);
gpio_set_oeover(pin->pin_num, pin->oe_override);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 250 |
```unknown
config PINCTRL_GECKO
bool "Gecko pin controller driver"
default y
depends on DT_HAS_SILABS_GECKO_PINCTRL_ENABLED
select PINCTRL_STORE_REG
help
Gecko pin controller driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
config PINCTRL_CC13XX_CC26XX
bool "TI SimpleLink CC13xx / CC26xx pinctrl driver"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_PINCTRL_ENABLED
help
Enable the TI SimpleLink CC13xx / CC26xx pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.cc13xx_cc26xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```unknown
config PINCTRL_STM32
bool "Pin controller driver for STM32 MCUs"
default y
depends on DT_HAS_ST_STM32_PINCTRL_ENABLED || DT_HAS_ST_STM32F1_PINCTRL_ENABLED
help
Enable pin controller driver for STM32 MCUs
config PINCTRL_STM32_REMAP_INIT_PRIORITY
int "Remap initialization priority"
default 2
depends on PINCTRL_STM32
help
Initialization priority for the routine in charge of configuring the
remap for pins PA11/12.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```c
/*
*
*/
#define DT_DRV_COMPAT hit_hd44780
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/auxdisplay.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(auxdisplay_hd44780, CONFIG_AUXDISPLAY_LOG_LEVEL);
#define AUXDISPLAY_HD44780_BACKLIGHT_MIN 0
#define AUXDISPLAY_HD44780_BACKLIGHT_MAX 1
#define AUXDISPLAY_HD44780_CUSTOM_CHARACTERS 8
#define AUXDISPLAY_HD44780_CUSTOM_CHARACTER_WIDTH 5
#define AUXDISPLAY_HD44780_CUSTOM_CHARACTER_HEIGHT 8
enum {
AUXDISPLAY_HD44780_MODE_4_BIT = 0,
AUXDISPLAY_HD44780_MODE_8_BIT = 1,
/* Reserved for internal driver use only */
AUXDISPLAY_HD44780_MODE_4_BIT_ONCE,
};
/* Display commands */
#define AUXDISPLAY_HD44780_CMD_CLEAR 0x01
#define AUXDISPLAY_HD44780_CMD_ENTRY_MODE 0x04
#define AUXDISPLAY_HD44780_CMD_DISPLAY_MODE 0x08
#define AUXDISPLAY_HD44780_CMD_CGRAM_SET 0x40
#define AUXDISPLAY_HD44780_CMD_POSITION_SET 0x80
#define AUXDISPLAY_HD44780_CMD_SETUP 0x20
#define AUXDISPLAY_HD44780_8_BIT_CONFIG 0x10
#define AUXDISPLAY_HD44780_2_LINE_CONFIG 0x08
#define AUXDISPLAY_HD44780_POSITION_BLINK_ENABLED 0x01
#define AUXDISPLAY_HD44780_CURSOR_ENABLED 0x02
#define AUXDISPLAY_HD44780_DISPLAY_ENABLED 0x04
#define AUXDISPLAY_HD44780_DISPLAY_SHIFT 0x01
#define AUXDISPLAY_HD44780_CURSOR_MOVE_RIGHT 0x02
struct auxdisplay_hd44780_data {
uint16_t character_x;
uint16_t character_y;
bool cursor_enabled;
bool position_blink_enabled;
uint8_t direction;
bool display_shift;
bool backlight_state;
};
struct auxdisplay_hd44780_config {
struct auxdisplay_capabilities capabilities;
struct gpio_dt_spec rs_gpio;
struct gpio_dt_spec rw_gpio;
struct gpio_dt_spec e_gpio;
struct gpio_dt_spec db_gpios[8];
struct gpio_dt_spec backlight_gpio;
uint8_t line_addresses[4];
uint16_t enable_line_rise_delay;
uint16_t enable_line_fall_delay;
uint16_t clear_delay;
uint16_t boot_delay;
};
static void auxdisplay_hd44780_set_entry_mode(const struct device *dev);
static void auxdisplay_hd44780_set_display_mode(const struct device *dev, bool enabled);
static void auxdisplay_hd44780_command(const struct device *dev, bool rs, uint8_t cmd,
uint8_t mode)
{
const struct auxdisplay_hd44780_config *config = dev->config;
int8_t i = 7;
if (mode == AUXDISPLAY_HD44780_MODE_8_BIT) {
while (i >= 0) {
gpio_pin_set_dt(&config->db_gpios[i], ((cmd & BIT(i)) ? 1 : 0));
--i;
}
} else {
while (i >= 4) {
gpio_pin_set_dt(&config->db_gpios[i], ((cmd & BIT(i)) ? 1 : 0));
--i;
}
}
gpio_pin_set_dt(&config->rs_gpio, rs);
if (config->rw_gpio.port) {
gpio_pin_set_dt(&config->rw_gpio, 0);
}
gpio_pin_set_dt(&config->e_gpio, 1);
k_sleep(K_USEC(config->enable_line_rise_delay));
gpio_pin_set_dt(&config->e_gpio, 0);
k_sleep(K_USEC(config->enable_line_fall_delay));
if (mode == AUXDISPLAY_HD44780_MODE_4_BIT) {
while (i >= 0) {
gpio_pin_set_dt(&config->db_gpios[(i + 4)], ((cmd & BIT(i)) ? 1 : 0));
--i;
}
gpio_pin_set_dt(&config->e_gpio, 1);
k_sleep(K_USEC(config->enable_line_rise_delay));
gpio_pin_set_dt(&config->e_gpio, 0);
k_sleep(K_USEC(config->enable_line_fall_delay));
}
}
static int auxdisplay_hd44780_init(const struct device *dev)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
int rc;
uint8_t i = 0;
uint8_t cmd = AUXDISPLAY_HD44780_CMD_SETUP | AUXDISPLAY_HD44780_8_BIT_CONFIG;
if (config->capabilities.mode > AUXDISPLAY_HD44780_MODE_8_BIT) {
/* This index is reserved for internal driver usage */
LOG_ERR("HD44780 mode must be 4 or 8-bit");
return -EINVAL;
}
/* Configure and set GPIOs */
rc = gpio_pin_configure_dt(&config->rs_gpio, GPIO_OUTPUT);
if (rc < 0) {
LOG_ERR("Configuration of RS GPIO failed: %d", rc);
return rc;
}
if (config->rw_gpio.port) {
rc = gpio_pin_configure_dt(&config->rw_gpio, GPIO_OUTPUT);
if (rc < 0) {
LOG_ERR("Configuration of RW GPIO failed: %d", rc);
return rc;
}
}
rc = gpio_pin_configure_dt(&config->e_gpio, GPIO_OUTPUT);
if (rc < 0) {
LOG_ERR("Configuration of E GPIO failed: %d", rc);
return rc;
}
if (config->capabilities.mode == AUXDISPLAY_HD44780_MODE_4_BIT) {
i = 4;
}
while (i < 8) {
if (config->db_gpios[i].port) {
rc = gpio_pin_configure_dt(&config->db_gpios[i], GPIO_OUTPUT);
if (rc < 0) {
LOG_ERR("Configuration of DB%d GPIO failed: %d", i, rc);
return rc;
}
} else if (config->capabilities.mode == AUXDISPLAY_HD44780_MODE_4_BIT && i > 3) {
/* Required pin missing */
LOG_ERR("Required DB%d pin missing (DB4-DB7 needed for 4-bit mode)", i);
return -EINVAL;
} else if (config->capabilities.mode == AUXDISPLAY_HD44780_MODE_8_BIT) {
/* Required pin missing */
LOG_ERR("Required DB%d pin missing", i);
return -EINVAL;
}
++i;
}
if (config->backlight_gpio.port) {
rc = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT);
if (rc < 0) {
LOG_ERR("Configuration of backlight GPIO failed: %d", rc);
return rc;
}
gpio_pin_set_dt(&config->backlight_gpio, 0);
}
data->character_x = 0;
data->character_y = 0;
data->backlight_state = false;
data->cursor_enabled = false;
data->position_blink_enabled = false;
data->direction = AUXDISPLAY_DIRECTION_RIGHT;
if (config->boot_delay != 0) {
/* Boot delay is set, wait for a period of time for the LCD to become ready to
* accept commands
*/
k_sleep(K_MSEC(config->boot_delay));
}
if (config->capabilities.mode == AUXDISPLAY_HD44780_MODE_4_BIT) {
/* Reset display to known state in 8-bit mode */
auxdisplay_hd44780_command(dev, false, cmd, AUXDISPLAY_HD44780_MODE_4_BIT_ONCE);
auxdisplay_hd44780_command(dev, false, cmd, AUXDISPLAY_HD44780_MODE_4_BIT_ONCE);
/* Put display into 4-bit mode */
cmd = AUXDISPLAY_HD44780_CMD_SETUP;
auxdisplay_hd44780_command(dev, false, cmd, AUXDISPLAY_HD44780_MODE_4_BIT_ONCE);
}
if (config->capabilities.rows > 1) {
cmd |= AUXDISPLAY_HD44780_2_LINE_CONFIG;
}
/* Configure display */
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
auxdisplay_hd44780_set_display_mode(dev, true);
auxdisplay_hd44780_set_entry_mode(dev);
auxdisplay_hd44780_command(dev, false, AUXDISPLAY_HD44780_CMD_CLEAR,
config->capabilities.mode);
k_sleep(K_USEC(config->clear_delay));
return 0;
}
static int auxdisplay_hd44780_capabilities_get(const struct device *dev,
struct auxdisplay_capabilities *capabilities)
{
const struct auxdisplay_hd44780_config *config = dev->config;
memcpy(capabilities, &config->capabilities, sizeof(struct auxdisplay_capabilities));
return 0;
}
static int auxdisplay_hd44780_clear(const struct device *dev)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
auxdisplay_hd44780_command(dev, false, AUXDISPLAY_HD44780_CMD_CLEAR,
config->capabilities.mode);
data->character_x = 0;
data->character_y = 0;
k_sleep(K_USEC(config->clear_delay));
return 0;
}
static void auxdisplay_hd44780_set_entry_mode(const struct device *dev)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
uint8_t cmd = AUXDISPLAY_HD44780_CMD_ENTRY_MODE;
if (data->direction == AUXDISPLAY_DIRECTION_RIGHT) {
cmd |= AUXDISPLAY_HD44780_CURSOR_MOVE_RIGHT;
}
if (data->display_shift) {
cmd |= AUXDISPLAY_HD44780_DISPLAY_SHIFT;
}
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
}
static void auxdisplay_hd44780_set_display_mode(const struct device *dev, bool enabled)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
uint8_t cmd = AUXDISPLAY_HD44780_CMD_DISPLAY_MODE;
if (data->cursor_enabled) {
cmd |= AUXDISPLAY_HD44780_CURSOR_ENABLED;
}
if (data->position_blink_enabled) {
cmd |= AUXDISPLAY_HD44780_POSITION_BLINK_ENABLED;
}
if (enabled) {
cmd |= AUXDISPLAY_HD44780_DISPLAY_ENABLED;
}
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
}
static int auxdisplay_hd44780_display_on(const struct device *dev)
{
auxdisplay_hd44780_set_display_mode(dev, true);
return 0;
}
static int auxdisplay_hd44780_display_off(const struct device *dev)
{
auxdisplay_hd44780_set_display_mode(dev, false);
return 0;
}
static int auxdisplay_hd44780_cursor_set_enabled(const struct device *dev, bool enabled)
{
struct auxdisplay_hd44780_data *data = dev->data;
data->cursor_enabled = enabled;
auxdisplay_hd44780_set_display_mode(dev, true);
return 0;
}
static int auxdisplay_hd44780_position_blinking_set_enabled(const struct device *dev, bool enabled)
{
struct auxdisplay_hd44780_data *data = dev->data;
data->position_blink_enabled = enabled;
auxdisplay_hd44780_set_display_mode(dev, true);
return 0;
}
static int auxdisplay_hd44780_cursor_shift_set(const struct device *dev, uint8_t direction,
bool display_shift)
{
struct auxdisplay_hd44780_data *data = dev->data;
if (display_shift) {
/* Not currently supported */
return -EINVAL;
}
data->direction = direction;
data->display_shift = (display_shift ? true : false);
auxdisplay_hd44780_set_entry_mode(dev);
return 0;
}
static int auxdisplay_hd44780_cursor_position_set(const struct device *dev,
enum auxdisplay_position type, int16_t x,
int16_t y)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
uint8_t cmd = AUXDISPLAY_HD44780_CMD_POSITION_SET;
if (type == AUXDISPLAY_POSITION_RELATIVE) {
x += (int16_t)data->character_x;
y += (int16_t)data->character_y;
} else if (type == AUXDISPLAY_POSITION_RELATIVE_DIRECTION) {
if (data->direction == AUXDISPLAY_DIRECTION_RIGHT) {
x += (int16_t)data->character_x;
y += (int16_t)data->character_y;
} else {
x -= (int16_t)data->character_x;
y -= (int16_t)data->character_y;
}
}
/* Check position is valid before applying */
if (x < 0 || y < 0) {
return -EINVAL;
} else if (x >= config->capabilities.columns || y >= config->capabilities.rows) {
return -EINVAL;
}
data->character_x = (uint16_t)x;
data->character_y = (uint16_t)y;
cmd |= config->line_addresses[data->character_y] + data->character_x;
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
return 0;
}
static int auxdisplay_hd44780_cursor_position_get(const struct device *dev, int16_t *x, int16_t *y)
{
struct auxdisplay_hd44780_data *data = dev->data;
*x = (int16_t)data->character_x;
*y = (int16_t)data->character_y;
return 0;
}
static int auxdisplay_hd44780_backlight_get(const struct device *dev, uint8_t *backlight)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
if (!config->backlight_gpio.port) {
return -ENOTSUP;
}
*backlight = (data->backlight_state == true ? 1 : 0);
return 0;
}
static int auxdisplay_hd44780_backlight_set(const struct device *dev, uint8_t backlight)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
if (!config->backlight_gpio.port) {
return -ENOTSUP;
}
data->backlight_state = (bool)backlight;
gpio_pin_set_dt(&config->backlight_gpio, (uint8_t)data->backlight_state);
return 0;
}
static int auxdisplay_hd44780_custom_character_set(const struct device *dev,
struct auxdisplay_character *character)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
uint8_t i = 0;
uint8_t cmd = AUXDISPLAY_HD44780_CMD_CGRAM_SET | (character->index << 3);
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
/* HD44780 accepts 5x8 font but needs 8x8 data to be sent, mask off top 3 bits
* for each line sent
*/
while (i < 8) {
uint8_t l = 0;
cmd = 0;
while (l < 5) {
if (character->data[(i * 5) + (4 - l)]) {
cmd |= BIT(l);
}
++l;
}
auxdisplay_hd44780_command(dev, true, cmd, config->capabilities.mode);
++i;
}
character->character_code = character->index;
/* Send last known address to switch back to DDRAM entry mode */
cmd = AUXDISPLAY_HD44780_CMD_POSITION_SET |
(config->line_addresses[data->character_y] +
data->character_x);
auxdisplay_hd44780_command(dev, false, cmd, config->capabilities.mode);
return 0;
}
static int auxdisplay_hd44780_write(const struct device *dev, const uint8_t *text, uint16_t len)
{
const struct auxdisplay_hd44780_config *config = dev->config;
struct auxdisplay_hd44780_data *data = dev->data;
uint16_t i = 0;
while (i < len) {
auxdisplay_hd44780_command(dev, true, text[i], config->capabilities.mode);
++i;
if (data->direction == AUXDISPLAY_DIRECTION_RIGHT) {
/* Increment */
++data->character_x;
if (data->character_x == config->capabilities.columns) {
data->character_x = 0;
++data->character_y;
if (data->character_y == config->capabilities.rows) {
data->character_y = 0;
}
/* Send command to set position */
uint8_t cmd = AUXDISPLAY_HD44780_CMD_POSITION_SET |
config->line_addresses[data->character_y];
auxdisplay_hd44780_command(dev, false, cmd,
config->capabilities.mode);
}
} else {
/* Decrement */
if (data->character_x == 0) {
data->character_x = config->capabilities.columns - 1;
if (data->character_y == 0) {
data->character_y = config->capabilities.rows - 1;
} else {
--data->character_y;
}
/* Send command to set position */
uint8_t cmd = AUXDISPLAY_HD44780_CMD_POSITION_SET |
(config->line_addresses[data->character_y] +
data->character_x);
auxdisplay_hd44780_command(dev, false, cmd,
config->capabilities.mode);
} else {
--data->character_x;
}
}
}
return 0;
}
static const struct auxdisplay_driver_api auxdisplay_hd44780_auxdisplay_api = {
.display_on = auxdisplay_hd44780_display_on,
.display_off = auxdisplay_hd44780_display_off,
.cursor_set_enabled = auxdisplay_hd44780_cursor_set_enabled,
.position_blinking_set_enabled = auxdisplay_hd44780_position_blinking_set_enabled,
.cursor_shift_set = auxdisplay_hd44780_cursor_shift_set,
.cursor_position_set = auxdisplay_hd44780_cursor_position_set,
.cursor_position_get = auxdisplay_hd44780_cursor_position_get,
.capabilities_get = auxdisplay_hd44780_capabilities_get,
.clear = auxdisplay_hd44780_clear,
.backlight_get = auxdisplay_hd44780_backlight_get,
.backlight_set = auxdisplay_hd44780_backlight_set,
.custom_character_set = auxdisplay_hd44780_custom_character_set,
.write = auxdisplay_hd44780_write,
};
/* Returns desired value if backlight is enabled, otherwise returns not supported value */
#define BACKLIGHT_CHECK(inst, value) \
COND_CODE_1(DT_PROP_HAS_IDX(DT_DRV_INST(inst), backlight_gpios, 0), (value), \
(AUXDISPLAY_LIGHT_NOT_SUPPORTED))
#define AUXDISPLAY_HD44780_DEVICE(inst) \
static struct auxdisplay_hd44780_data auxdisplay_hd44780_data_##inst; \
static const struct auxdisplay_hd44780_config auxdisplay_hd44780_config_##inst = { \
.capabilities = { \
.columns = DT_INST_PROP(inst, columns), \
.rows = DT_INST_PROP(inst, rows), \
.mode = DT_INST_ENUM_IDX(inst, mode), \
.brightness.minimum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.brightness.maximum = AUXDISPLAY_LIGHT_NOT_SUPPORTED, \
.backlight.minimum = BACKLIGHT_CHECK(inst, \
AUXDISPLAY_HD44780_BACKLIGHT_MIN), \
.backlight.maximum = BACKLIGHT_CHECK(inst, \
AUXDISPLAY_HD44780_BACKLIGHT_MAX), \
.custom_characters = AUXDISPLAY_HD44780_CUSTOM_CHARACTERS, \
.custom_character_width = AUXDISPLAY_HD44780_CUSTOM_CHARACTER_WIDTH, \
.custom_character_height = AUXDISPLAY_HD44780_CUSTOM_CHARACTER_HEIGHT, \
}, \
.rs_gpio = GPIO_DT_SPEC_INST_GET(inst, register_select_gpios), \
.rw_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, read_write_gpios, {0}), \
.e_gpio = GPIO_DT_SPEC_INST_GET(inst, enable_gpios), \
.db_gpios[0] = GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, data_bus_gpios, 0, {0}), \
.db_gpios[1] = GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, data_bus_gpios, 1, {0}), \
.db_gpios[2] = GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, data_bus_gpios, 2, {0}), \
.db_gpios[3] = GPIO_DT_SPEC_INST_GET_BY_IDX_OR(inst, data_bus_gpios, 3, {0}), \
.db_gpios[4] = GPIO_DT_SPEC_INST_GET_BY_IDX(inst, data_bus_gpios, 4), \
.db_gpios[5] = GPIO_DT_SPEC_INST_GET_BY_IDX(inst, data_bus_gpios, 5), \
.db_gpios[6] = GPIO_DT_SPEC_INST_GET_BY_IDX(inst, data_bus_gpios, 6), \
.db_gpios[7] = GPIO_DT_SPEC_INST_GET_BY_IDX(inst, data_bus_gpios, 7), \
.line_addresses[0] = DT_INST_PROP_BY_IDX(inst, line_addresses, 0), \
.line_addresses[1] = DT_INST_PROP_BY_IDX(inst, line_addresses, 1), \
.line_addresses[2] = DT_INST_PROP_BY_IDX(inst, line_addresses, 2), \
.line_addresses[3] = DT_INST_PROP_BY_IDX(inst, line_addresses, 3), \
.backlight_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, backlight_gpios, {0}), \
.enable_line_rise_delay = DT_INST_PROP(inst, enable_line_rise_delay_us), \
.enable_line_fall_delay = DT_INST_PROP(inst, enable_line_fall_delay_us), \
.clear_delay = DT_INST_PROP(inst, clear_command_delay_us), \
.boot_delay = DT_INST_PROP(inst, boot_delay_ms), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&auxdisplay_hd44780_init, \
NULL, \
&auxdisplay_hd44780_data_##inst, \
&auxdisplay_hd44780_config_##inst, \
POST_KERNEL, \
CONFIG_AUXDISPLAY_INIT_PRIORITY, \
&auxdisplay_hd44780_auxdisplay_api);
DT_INST_FOREACH_STATUS_OKAY(AUXDISPLAY_HD44780_DEVICE)
``` | /content/code_sandbox/drivers/auxdisplay/auxdisplay_hd44780.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,041 |
```unknown
config PINCTRL_NXP_KINETIS
bool "Pin controller driver for NXP Kinetis MCUs"
default y
depends on DT_HAS_NXP_KINETIS_PINMUX_ENABLED
help
Enable pin controller driver for NXP Kinetis MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.kinetis | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Pin control driver for Infineon CAT1 MCU family.
*/
#include <zephyr/drivers/pinctrl.h>
#include <cy_gpio.h>
#define GPIO_PORT_OR_NULL(node_id) \
COND_CODE_1(DT_NODE_EXISTS(node_id), ((GPIO_PRT_Type *)DT_REG_ADDR(node_id)), (NULL))
/* @brief Array containing pointers to each GPIO port.
*
* Entries will be NULL if the GPIO port is not enabled.
*/
static GPIO_PRT_Type *const gpio_ports[] = {
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt0)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt1)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt2)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt3)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt4)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt5)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt6)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt7)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt8)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt9)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt10)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt11)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt12)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt13)),
GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt14))
};
/* @brief This function returns gpio drive mode, according to.
* bias and drive mode params defined in pinctrl node.
*
* @param flags - bias and drive mode flags from pinctrl node.
*/
static uint32_t soc_gpio_get_drv_mode(uint32_t flags)
{
uint32_t drv_mode = CY_GPIO_DM_ANALOG;
uint32_t _flags;
_flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
if (_flags & SOC_GPIO_OPENDRAIN) {
/* drive_open_drain */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW
: CY_GPIO_DM_OD_DRIVESLOW_IN_OFF;
} else if (_flags & SOC_GPIO_OPENSOURCE) {
/* drive_open_source */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH
: CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
} else if (_flags & SOC_GPIO_PUSHPULL) {
/* drive_push_pull */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG
: CY_GPIO_DM_STRONG_IN_OFF;
} else if ((_flags & SOC_GPIO_PULLUP) && (_flags & SOC_GPIO_PULLDOWN)) {
/* bias_pull_up and bias_pull_down */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN
: CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
} else if (_flags & SOC_GPIO_PULLUP) {
/* bias_pull_up */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP
: CY_GPIO_DM_PULLUP_IN_OFF;
} else if (_flags & SOC_GPIO_PULLDOWN) {
/* bias_pull_down */
drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN
: CY_GPIO_DM_PULLDOWN_IN_OFF;
} else if ((_flags & SOC_GPIO_HIGHZ) | (_flags & SOC_GPIO_INPUTENABLE)) {
/* bias_pull_down */
drv_mode = CY_GPIO_DM_HIGHZ;
} else {
/* nothing do here */
}
return drv_mode;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
uint32_t drv_mode = soc_gpio_get_drv_mode(pins[i].pincfg);
uint32_t hsiom = CAT1_PINMUX_GET_HSIOM_FUNC(pins[i].pinmux);
uint32_t port_num = CAT1_PINMUX_GET_PORT_NUM(pins[i].pinmux);
uint32_t pin_num = CAT1_PINMUX_GET_PIN_NUM(pins[i].pinmux);
/* Initialize pin */
Cy_GPIO_Pin_FastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom);
/* Force output to enable pulls */
switch (drv_mode) {
case CY_GPIO_DM_PULLUP:
Cy_GPIO_Write(gpio_ports[port_num], pin_num, 1);
break;
case CY_GPIO_DM_PULLDOWN:
Cy_GPIO_Write(gpio_ports[port_num], pin_num, 0);
break;
default:
/* do nothing */
break;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,073 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_pinctrl
#include <zephyr/drivers/pinctrl.h>
static int pinctrl_c13xx_cc26xx_set(uint32_t pin, uint32_t func, uint32_t mode)
{
if (pin >= NUM_IO_MAX || func >= NUM_IO_PORTS) {
return -EINVAL;
}
IOCPortConfigureSet(pin, func, mode);
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_c13xx_cc26xx_set(pins[i].pin, pins[i].iofunc, pins[i].iomode);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 183 |
```unknown
config PINCTRL_NXP_S32
bool "Pin controller driver for NXP S32 processors"
default y
depends on DT_HAS_NXP_S32ZE_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_PINCTRL_ENABLED
help
Enable pin controller driver for NXP S32 processors.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
config PINCTRL_MAX32
bool "Analog Devices MAX32 MCUs pin controller driver"
default y
depends on DT_HAS_ADI_MAX32_PINCTRL_ENABLED
help
Pin controller driver support for max32 SoC series
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.max32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config PINCTRL_NRF
bool "nRF pin controller driver"
default y
depends on DT_HAS_NORDIC_NRF_PINCTRL_ENABLED
select PINCTRL_STORE_REG
help
nRF pin controller driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.nrf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
config PINCTRL_ESP32
bool "ESP32 pin controller"
default y
depends on DT_HAS_ESPRESSIF_ESP32_PINCTRL_ENABLED
help
Enables ESP32 pin controller
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_pinmux
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <fsl_clock.h>
LOG_MODULE_REGISTER(pinctrl_kinetis, CONFIG_PINCTRL_LOG_LEVEL);
/* Port register addresses. */
static PORT_Type *ports[] = {
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
#endif
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
#endif
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 5
(PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portf)),
#endif
};
#define PIN(mux) (((mux) & 0xFC00000) >> 22)
#define PORT(mux) (((mux) & 0xF0000000) >> 28)
#define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK)
struct pinctrl_mcux_config {
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
};
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0; i < pin_cnt; i++) {
PORT_Type *base = ports[PORT(pins[i])];
uint8_t pin = PIN(pins[i]);
uint16_t mux = PINCFG(pins[i]);
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_KINETIS_PCR_MASK)) | mux;
}
return 0;
}
/* Kinetis pinmux driver binds to the same DTS nodes,
* and handles clock init. Only bind to these nodes if pinmux driver
* is disabled.
*/
static int pinctrl_mcux_init(const struct device *dev)
{
const struct pinctrl_mcux_config *config = dev->config;
int err;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
err = clock_control_on(config->clock_dev, config->clock_subsys);
if (err) {
LOG_ERR("failed to enable clock (err %d)", err);
return -EINVAL;
}
return 0;
}
#if DT_NODE_HAS_STATUS(DT_INST(0, nxp_kinetis_sim), okay)
#define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
CLK_GATE_DEFINE(DT_INST_CLOCKS_CELL(n, offset), \
DT_INST_CLOCKS_CELL(n, bits))
#else
#define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
DT_INST_CLOCKS_CELL(n, name)
#endif
#define PINCTRL_MCUX_INIT(n) \
static const struct pinctrl_mcux_config pinctrl_mcux_##n##_config = {\
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t) \
PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
&pinctrl_mcux_init, \
NULL, \
NULL, &pinctrl_mcux_##n##_config, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_MCUX_INIT)
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_kinetis.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 827 |
```c
/*
*
*/
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <hal/gpio_ll.h>
#include <hal/rtc_io_hal.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/pinctrl/pinctrl_esp32_common.h>
#ifdef CONFIG_SOC_SERIES_ESP32C2
#define out out.val
#define in in.val
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
#elif CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data
#define in in.data
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
#elif CONFIG_SOC_SERIES_ESP32C6
/* gpio structs in esp32c6 are also different */
#define out out.out_data_orig
#define in in.in_data_next
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
#endif
#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0
#endif
#define ESP32_INVALID_PORT_ADDR 0UL
#define ESP32_GPIO_PORT_ADDR(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),), \
(ESP32_INVALID_PORT_ADDR))
/**
* @brief Array containing each GPIO port address.
*
* Entries will be an invalid address if the port is not enabled.
*/
static const uint32_t esp32_gpio_ports_addrs[] = {
ESP32_GPIO_PORT_ADDR(gpio0)
ESP32_GPIO_PORT_ADDR(gpio1)
};
/** Number of GPIO ports. */
static const size_t esp32_gpio_ports_cnt = ARRAY_SIZE(esp32_gpio_ports_addrs);
static inline bool rtc_gpio_is_valid_gpio(uint32_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
return (gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
#else
return false;
#endif
}
static inline bool esp32_pin_is_valid(uint32_t pin)
{
return ((BIT(pin) & SOC_GPIO_VALID_GPIO_MASK) != 0);
}
static inline bool esp32_pin_is_output_capable(uint32_t pin)
{
return ((BIT(pin) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0);
}
static int esp32_pin_apply_config(uint32_t pin, uint32_t flags)
{
gpio_dev_t *const gpio_base = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0));
uint32_t io_pin = (uint32_t) pin + ((ESP32_PORT_IDX(pin) == 1 && pin < 32) ? 32 : 0);
int ret = 0;
if (!esp32_pin_is_valid(io_pin)) {
return -EINVAL;
}
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_pin)) {
rtcio_hal_function_select(rtc_io_num_map[io_pin], RTCIO_FUNC_DIGITAL);
}
#endif
if (io_pin >= GPIO_NUM_MAX) {
ret = -EINVAL;
goto end;
}
/* Set pin function as GPIO */
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[io_pin], PIN_FUNC_GPIO);
if (flags & ESP32_PULL_UP_FLAG) {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pulldown_dis(&GPIO, io_pin);
gpio_ll_pullup_en(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
rtcio_hal_pulldown_disable(rtc_io_num_map[io_pin]);
if (rtc_io_desc[rtcio_num].pullup) {
rtcio_hal_pullup_enable(rtc_io_num_map[io_pin]);
} else {
ret = -ENOTSUP;
goto end;
}
#endif
}
} else if (flags & ESP32_PULL_DOWN_FLAG) {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pullup_dis(&GPIO, io_pin);
gpio_ll_pulldown_en(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
rtcio_hal_pulldown_enable(rtc_io_num_map[io_pin]);
if (rtc_io_desc[rtcio_num].pullup) {
rtcio_hal_pullup_disable(rtc_io_num_map[io_pin]);
} else {
ret = -ENOTSUP;
goto end;
}
#endif
}
}
if (flags & ESP32_DIR_OUT_FLAG) {
if (!esp32_pin_is_output_capable(pin)) {
ret = -EINVAL;
goto end;
}
if (flags & ESP32_OPEN_DRAIN_FLAG) {
gpio_ll_od_enable(gpio_base, io_pin);
} else {
gpio_ll_od_disable(gpio_base, io_pin);
}
/* Set output pin initial value */
if (flags & ESP32_PIN_OUT_HIGH_FLAG) {
gpio_ll_set_level(gpio_base, io_pin, 1);
} else if (flags & ESP32_PIN_OUT_LOW_FLAG) {
gpio_ll_set_level(gpio_base, io_pin, 0);
}
gpio_ll_output_enable(&GPIO, io_pin);
esp_rom_gpio_matrix_out(io_pin, SIG_GPIO_OUT_IDX, false, false);
} else {
if (!(flags & ESP32_PIN_OUT_EN_FLAG)) {
gpio_ll_output_disable(&GPIO, io_pin);
}
}
if (flags & ESP32_DIR_INP_FLAG) {
gpio_ll_input_enable(&GPIO, io_pin);
} else {
if (!(flags & ESP32_PIN_IN_EN_FLAG)) {
gpio_ll_input_disable(&GPIO, io_pin);
}
}
end:
return ret;
}
static int esp32_pin_configure(const uint32_t pin_mux, const uint32_t pin_cfg)
{
uint32_t port_addr;
uint32_t pin_num = ESP32_PIN_NUM(pin_mux);
uint32_t sig_in = ESP32_PIN_SIGI(pin_mux);
uint32_t sig_out = ESP32_PIN_SIGO(pin_mux);
uint32_t flags = 0;
if (ESP32_PORT_IDX(pin_num) >= esp32_gpio_ports_cnt) {
return -EINVAL;
}
port_addr = esp32_gpio_ports_addrs[ESP32_PORT_IDX(pin_num)];
if (port_addr == ESP32_INVALID_PORT_ADDR) {
return -EINVAL;
}
switch (ESP32_PIN_BIAS(pin_cfg)) {
case ESP32_PULL_UP:
flags |= ESP32_PULL_UP_FLAG;
break;
case ESP32_PULL_DOWN:
flags |= ESP32_PULL_DOWN_FLAG;
break;
default:
break;
}
switch (ESP32_PIN_DRV(pin_cfg)) {
case ESP32_PUSH_PULL:
flags |= ESP32_PUSH_PULL_FLAG;
break;
case ESP32_OPEN_DRAIN:
flags |= ESP32_OPEN_DRAIN_FLAG;
break;
default:
break;
}
if (sig_in == ESP_SIG_INVAL && sig_out == ESP_SIG_INVAL) {
return -ENOTSUP;
}
if (sig_in != ESP_SIG_INVAL) {
flags |= ESP32_DIR_INP_FLAG;
}
if (sig_out != ESP_SIG_INVAL) {
flags |= ESP32_DIR_OUT_FLAG;
}
switch (ESP32_PIN_MODE_OUT(pin_cfg)) {
case ESP32_PIN_OUT_HIGH:
flags |= ESP32_PIN_OUT_HIGH_FLAG;
break;
case ESP32_PIN_OUT_LOW:
flags |= ESP32_PIN_OUT_LOW_FLAG;
break;
default:
break;
}
switch (ESP32_PIN_EN_DIR(pin_cfg)) {
case ESP32_PIN_OUT_EN:
flags |= ESP32_PIN_OUT_EN_FLAG;
break;
case ESP32_PIN_IN_EN:
flags |= ESP32_PIN_IN_EN_FLAG;
break;
default:
break;
}
if (flags & ESP32_PIN_OUT_HIGH_FLAG) {
if (ESP32_PORT_IDX(pin_num) == 0) {
gpio_dev_t *const gpio_dev =
(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0));
gpio_dev->out_w1ts = BIT(pin_num);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
gpio_dev_t *const gpio_dev =
(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio1));
gpio_dev->out1_w1ts.data = BIT(pin_num - 32);
#endif
}
}
if (flags & ESP32_PIN_OUT_LOW_FLAG) {
if (ESP32_PORT_IDX(pin_num) == 0) {
gpio_dev_t *const gpio_dev =
(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0));
gpio_dev->out_w1tc = BIT(pin_num);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
gpio_dev_t *const gpio_dev =
(gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio1));
gpio_dev->out1_w1tc.data = BIT(pin_num - 32);
#endif
}
}
esp32_pin_apply_config(pin_num, flags);
if (flags & ESP32_DIR_OUT_FLAG) {
esp_rom_gpio_matrix_out(pin_num, sig_out, 0, 0);
}
if (flags & ESP32_DIR_INP_FLAG) {
esp_rom_gpio_matrix_in(pin_num, sig_in, 0);
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
uint32_t pin_mux, pin_cfg;
int ret = 0;
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pin_mux = pins[i].pinmux;
pin_cfg = pins[i].pincfg;
ret = esp32_pin_configure(pin_mux, pin_cfg);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,248 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <gpio/gpio_stm32.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_gpio.h>
#include <stm32_ll_system.h>
/** Helper to extract IO port number from STM32PIN() encoded value */
#define STM32_PORT(__pin) \
((__pin) >> 4)
/** Helper to extract IO pin number from STM32PIN() encoded value */
#define STM32_PIN(__pin) \
((__pin) & 0xf)
/** Helper to extract IO port number from STM32_PINMUX() encoded value */
#define STM32_DT_PINMUX_PORT(__pin) \
(((__pin) >> STM32_PORT_SHIFT) & STM32_PORT_MASK)
/** Helper to extract IO pin number from STM32_PINMUX() encoded value */
#define STM32_DT_PINMUX_LINE(__pin) \
(((__pin) >> STM32_LINE_SHIFT) & STM32_LINE_MASK)
/** Helper to extract IO pin func from STM32_PINMUX() encoded value */
#define STM32_DT_PINMUX_FUNC(__pin) \
(((__pin) >> STM32_MODE_SHIFT) & STM32_MODE_MASK)
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
/** Helper to extract IO pin remap from STM32_PINMUX() encoded value */
#define STM32_DT_PINMUX_REMAP(__pin) \
(((__pin) >> STM32_REMAP_SHIFT) & STM32_REMAP_MASK)
#endif
/**
* @brief Array containing pointers to each GPIO port.
*
* Entries will be NULL if the GPIO port is not enabled.
*/
static const struct device *const gpio_ports[] = {
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioa)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiob)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioc)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiod)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioe)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiof)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiog)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioh)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioi)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioj)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiok)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiol)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiom)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpion)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioo)),
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiop)),
};
/** Number of GPIO ports. */
static const size_t gpio_ports_cnt = ARRAY_SIZE(gpio_ports);
#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11)
#define REMAP_PA11 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11)
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa12)
#define REMAP_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa12)
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
#define REMAP_PA11_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
#endif
#if REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12
int stm32_pinmux_init_remap(void)
{
#if REMAP_PA11 || REMAP_PA12
#if !defined(CONFIG_SOC_SERIES_STM32G0X) && !defined(CONFIG_SOC_SERIES_STM32C0X)
#error "Pin remap property available only on STM32G0 and STM32C0 SoC series"
#endif
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
#if REMAP_PA11
LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
#endif
#if REMAP_PA12
LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
#endif
#elif REMAP_PA11_PA12
#if !defined(SYSCFG_CFGR1_PA11_PA12_RMP)
#error "Pin remap property available only on STM32F070x SoC series"
#endif
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
LL_SYSCFG_EnablePinRemap();
#endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
return 0;
}
SYS_INIT(stm32_pinmux_init_remap, PRE_KERNEL_1,
CONFIG_PINCTRL_STM32_REMAP_INIT_PRIORITY);
#endif /* REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12 */
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
/* ignore swj-cfg reset state (default value) */
#if ((DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg)) && \
(DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) != 0))
static int stm32f1_swj_cfg_init(void)
{
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
/* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */
/* only one of the 3 bits can be set */
#if (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 1)
/* 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST */
/* releases: PB4 */
LL_GPIO_AF_Remap_SWJ_NONJTRST();
#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 2)
/* 010: JTAG-DP Disabled and SW-DP Enabled */
/* releases: PB4 PB3 PA15 */
LL_GPIO_AF_Remap_SWJ_NOJTAG();
#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 3)
/* 100: JTAG-DP Disabled and SW-DP Disabled */
/* releases: PB4 PB3 PA13 PA14 PA15 */
LL_GPIO_AF_DisableRemap_SWJ();
#endif
return 0;
}
SYS_INIT(stm32f1_swj_cfg_init, PRE_KERNEL_1, 0);
#endif /* DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg) */
/**
* @brief Helper function to check and apply provided pinctrl remap
* configuration.
*
* Check operation verifies that pin remapping configuration is the same on all
* pins. If configuration is valid AFIO clock is enabled and remap is applied
*
* @param pins List of pins to be configured.
* @param pin_cnt Number of pins.
*
* @retval 0 If successful
* @retval -EINVAL If pins have an incompatible set of remaps.
*/
static int stm32_pins_remap(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt)
{
uint32_t reg_val;
uint16_t remap;
remap = (uint16_t)STM32_DT_PINMUX_REMAP(pins[0].pinmux);
/* not remappable */
if (remap == NO_REMAP) {
return 0;
}
for (size_t i = 1U; i < pin_cnt; i++) {
if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
return -EINVAL;
}
}
/* A valid remapping configuration is available */
/* Apply remapping before proceeding with pin configuration */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
if (STM32_REMAP_REG_GET(remap) == 0U) {
/* read initial value, ignore write-only SWJ_CFG */
reg_val = AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG;
reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
/* apply undocumented '111' (AFIO_MAPR_SWJ_CFG) to affirm SWJ_CFG */
/* the pins are not remapped without that (when SWJ_CFG is not default) */
AFIO->MAPR = reg_val | AFIO_MAPR_SWJ_CFG;
} else {
reg_val = AFIO->MAPR2;
reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
AFIO->MAPR2 = reg_val;
}
return 0;
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
static int stm32_pin_configure(uint32_t pin, uint32_t pin_cgf, uint32_t pin_func)
{
const struct device *port_device;
if (STM32_PORT(pin) >= gpio_ports_cnt) {
return -EINVAL;
}
port_device = gpio_ports[STM32_PORT(pin)];
if ((port_device == NULL) || (!device_is_ready(port_device))) {
return -ENODEV;
}
return gpio_stm32_configure(port_device, STM32_PIN(pin), pin_cgf, pin_func);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
uint32_t pin, mux;
uint32_t pin_cgf = 0;
int ret = 0;
ARG_UNUSED(reg);
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
ret = stm32_pins_remap(pins, pin_cnt);
if (ret < 0) {
return ret;
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
for (uint8_t i = 0U; i < pin_cnt; i++) {
mux = pins[i].pinmux;
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
uint32_t pupd;
if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) {
pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC;
} else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) {
pin_cgf = pins[i].pincfg | STM32_MODE_INPUT | STM32_CNF_IN_ANALOG;
} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) {
pin_cgf = pins[i].pincfg | STM32_MODE_INPUT;
pupd = pin_cgf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
if (pupd == STM32_PUPD_NO_PULL) {
pin_cgf = pin_cgf | STM32_CNF_IN_FLOAT;
} else {
pin_cgf = pin_cgf | STM32_CNF_IN_PUPD;
}
} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_OUT) {
pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT;
} else {
/* Not supported */
__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
}
#else
if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) {
pin_cgf = pins[i].pincfg | STM32_MODER_ALT_MODE;
} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
pin_cgf = STM32_MODER_ANALOG_MODE;
} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_GPIO) {
pin_cgf = pins[i].pincfg;
} else {
/* Not supported */
__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
STM32_DT_PINMUX_LINE(mux));
ret = stm32_pin_configure(pin, pin_cgf, STM32_DT_PINMUX_FUNC(mux));
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,707 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_k3_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/pinctrl.h>
#define PINCTRL_NODE DT_NODELABEL(pinctrl)
static struct pinctrl_ti_k3_dev_data {
DEVICE_MMIO_RAM;
} pinctrl_ti_k3_dev;
static struct pinctrl_ti_k3_cfg_data {
DEVICE_MMIO_ROM;
} pinctrl_ti_k3_cfg = {
DEVICE_MMIO_ROM_INIT(PINCTRL_NODE)
};
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
const struct device *dev = DEVICE_DT_GET(PINCTRL_NODE);
uintptr_t virt_reg_base = DEVICE_MMIO_GET(dev);
for (uint8_t i = 0; i < pin_cnt; i++) {
sys_write32(pins[i].value, virt_reg_base + pins[i].offset);
}
return 0;
}
static int pinctrl_ti_k3_init(const struct device *dev)
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
return 0;
}
DEVICE_DT_DEFINE(PINCTRL_NODE,
pinctrl_ti_k3_init,
NULL,
&pinctrl_ti_k3_dev,
&pinctrl_ti_k3_cfg,
PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
NULL);
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ti_k3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 303 |
```unknown
config PINCTRL_SIFIVE
bool "SiFive Freedom SoC pinmux driver"
default y
depends on DT_HAS_SIFIVE_PINCTRL_ENABLED
help
Enable driver for the SiFive Freedom SoC pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.sifive | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
config PINCTRL_MCI_IO_MUX
bool "NXP MCI IO MUX Pinctrl Driver"
default y
depends on DT_HAS_NXP_MCI_IO_MUX_ENABLED
help
Enable pin controller driver for NXP MCI_IO_MUX
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.mci_io_mux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
# Nuvoton NuMaker Pin Controller configuration options
config PINCTRL_NUMAKER
bool "Nuvoton NuMaker pin controller driver"
default y
depends on DT_HAS_NUVOTON_NUMAKER_PINCTRL_ENABLED
help
This option enables the pin controller driver for Nuvoton NuMaker MCUs.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
config PINCTRL_TI_K3
bool "TI K3 pinctrl driver"
default y
depends on DT_HAS_TI_K3_PINCTRL_ENABLED
help
Enable the TI K3 pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.ti_k3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
config PINCTRL_ITE_IT8XXX2
bool "ITE IT8XXX2 pin controller driver"
default y
depends on DT_HAS_ITE_IT8XXX2_PINCTRL_FUNC_ENABLED
help
Enable IT8XXX2 pin controller driver.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config PINCTRL_NUMICRO
bool "Pin controller driver for Nuvoton NuMicro MCUs"
default y
depends on DT_HAS_NUVOTON_NUMICRO_PINCTRL_ENABLED
help
Enable pin controller driver for Nuvoton NuMicro MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.numicro | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_pinctrl
#include <zephyr/drivers/pinctrl.h>
#include <NuMicro.h>
/* Get mfp_base, it should be == (&SYS->GPA_MFP0) */
#define MFP_BASE DT_INST_REG_ADDR_BY_NAME(0, mfp)
#define MFOS_BASE DT_INST_REG_ADDR_BY_NAME(0, mfos)
#define GPA_BASE DT_REG_ADDR(DT_NODELABEL(gpioa))
#define GPIO_SIZE DT_REG_SIZE(DT_NODELABEL(gpioa))
#define SLEWCTL_PIN_SHIFT(pin_idx) ((pin_idx) * 2)
#define SLEWCTL_MASK(pin_idx) (3 << SLEWCTL_PIN_SHIFT(pin_idx))
#define DINOFF_PIN_SHIFT(pin_idx) (pin_idx + GPIO_DINOFF_DINOFF0_Pos)
#define DINOFF_MASK(pin_idx) (1 << DINOFF_PIN_SHIFT(pin_idx))
static void gpio_configure(const pinctrl_soc_pin_t *pin, uint8_t port_idx, uint8_t pin_idx)
{
GPIO_T *port;
port = (GPIO_T *)(GPA_BASE + port_idx * GPIO_SIZE);
port->SMTEN = (port->SMTEN & ~BIT(pin_idx)) |
((pin->schmitt_enable ? 1 : 0) << pin_idx);
port->SLEWCTL = (port->SLEWCTL & ~SLEWCTL_MASK(pin_idx)) |
(pin->slew_rate << SLEWCTL_PIN_SHIFT(pin_idx));
port->DINOFF = (port->DINOFF & ~DINOFF_MASK(pin_idx)) |
((pin->digital_disable ? 1 : 0) << DINOFF_PIN_SHIFT(pin_idx));
}
/**
* Configure pin multi-function
*/
static void configure_pin(const pinctrl_soc_pin_t *pin)
{
uint32_t pin_mux = pin->pin_mux;
uint8_t pin_index = PIN_INDEX(pin_mux);
uint8_t port_index = PORT_INDEX(pin_mux);
uint32_t mfp_cfg = MFP_CFG(pin_mux);
uint32_t *GPx_MFPx = ((uint32_t *)MFP_BASE) + port_index * 4 + (pin_index / 4);
uint32_t *GPx_MFOSx = ((uint32_t *)MFOS_BASE) + port_index;
uint32_t pinMask = NU_MFP_MASK(pin_index);
/*
* E.g.: SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SYS_GPA_MFP0_PA0MFP_Msk) ) |
* SYS_GPA_MFP0_PA0MFP_SC0_CD;
*/
*GPx_MFPx = (*GPx_MFPx & (~pinMask)) | mfp_cfg;
if (pin->open_drain != 0) {
*GPx_MFOSx |= BIT(pin_index);
} else {
*GPx_MFOSx &= ~BIT(pin_index);
}
gpio_configure(pin, port_index, pin_index);
}
/* Pinctrl API implementation */
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
/* Configure all peripheral devices' properties here. */
for (uint8_t i = 0U; i < pin_cnt; i++) {
configure_pin(&pins[i]);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 735 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <soc_gpio.h>
/** Utility macro that expands to the GPIO port address if it exists */
#define SAM_PORT_ADDR_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),))
/** Utility macro that expands to the GPIO Peripheral ID if it exists */
#define SAM_PORT_CLOCKS_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(SAM_DT_CLOCK_PMC_CFG(0, DT_NODELABEL(nodelabel)),))
/** SAM port addresses */
static const uint32_t sam_port_addrs[] = {
#ifdef ID_GPIO
SAM_PORT_ADDR_OR_NONE(gpioa)
SAM_PORT_ADDR_OR_NONE(gpiob)
SAM_PORT_ADDR_OR_NONE(gpioc)
#else
SAM_PORT_ADDR_OR_NONE(pioa)
SAM_PORT_ADDR_OR_NONE(piob)
SAM_PORT_ADDR_OR_NONE(pioc)
SAM_PORT_ADDR_OR_NONE(piod)
SAM_PORT_ADDR_OR_NONE(pioe)
SAM_PORT_ADDR_OR_NONE(piof)
#endif
};
/** SAM port clocks */
static const struct atmel_sam_pmc_config sam_port_clocks[] = {
#ifdef ID_GPIO
SAM_PORT_CLOCKS_OR_NONE(gpioa)
SAM_PORT_CLOCKS_OR_NONE(gpiob)
SAM_PORT_CLOCKS_OR_NONE(gpioc)
#else
SAM_PORT_CLOCKS_OR_NONE(pioa)
SAM_PORT_CLOCKS_OR_NONE(piob)
SAM_PORT_CLOCKS_OR_NONE(pioc)
SAM_PORT_CLOCKS_OR_NONE(piod)
SAM_PORT_CLOCKS_OR_NONE(pioe)
SAM_PORT_CLOCKS_OR_NONE(piof)
#endif
};
static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
{
struct soc_gpio_pin soc_pin;
uint8_t port_idx, port_func;
port_idx = SAM_PINMUX_PORT_GET(pin);
__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(sam_port_addrs));
port_func = SAM_PINMUX_FUNC_GET(pin);
#ifdef ID_GPIO
soc_pin.regs = (Gpio *) sam_port_addrs[port_idx];
#else
soc_pin.regs = (Pio *) sam_port_addrs[port_idx];
#endif
soc_pin.periph_id = sam_port_clocks[port_idx].peripheral_id;
soc_pin.mask = 1 << SAM_PINMUX_PIN_GET(pin);
soc_pin.flags = SAM_PINCTRL_FLAGS_GET(pin) << SOC_GPIO_FLAGS_POS;
if (port_func == SAM_PINMUX_FUNC_periph) {
soc_pin.flags |= (SAM_PINMUX_PERIPH_GET(pin)
<< SOC_GPIO_FUNC_POS);
}
soc_gpio_configure(&soc_pin);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(*pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 678 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <svc/pad/pad_api.h>
#include <main/ipc.h>
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins,
uint8_t pin_cnt, uintptr_t reg)
{
sc_ipc_t ipc_handle;
int ret, i;
ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
if (ret != SC_ERR_NONE) {
return -ENODEV;
}
for (i = 0; i < pin_cnt; i++) {
/* TODO: for now, pad configuration is not supported. As such,
* the state of the pad is the following:
* 1) Normal configuration (no OD)
* 2) ISO off
* 3) Pull select and drive strength initialized by another
* entity (e.g: SCFW, Linux etc...) or set to the default
* values as specified in the TRM.
*/
ret = sc_pad_set_mux(ipc_handle, pins[i].pad, pins[i].mux, 0, 0);
if (ret != SC_ERR_NONE) {
return -EINVAL;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_imx_scu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 267 |
```unknown
config PINCTRL_XLNX_ZYNQ
bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
default y
depends on DT_HAS_XLNX_PINCTRL_ZYNQ_ENABLED
depends on SYSCON
help
Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.xlnx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
config PINCTRL_QUICKLOGIC_EOS_S3
bool "QuickLogic EOS S3 SoC pinctrl driver"
default y
depends on DT_HAS_QUICKLOGIC_EOS_S3_PINCTRL_ENABLED
help
Enable driver for the QuickLogic EOS S3 SoC pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.eos_s3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <gd32_gpio.h>
BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) &&
(GD32_PUPD_PULLUP == GPIO_PUPD_PULLUP) &&
(GD32_PUPD_PULLDOWN == GPIO_PUPD_PULLDOWN),
"pinctrl pull-up/down definitions != HAL definitions");
BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) &&
(GD32_OTYPE_OD == GPIO_OTYPE_OD),
"pinctrl output type definitions != HAL definitions");
BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) &&
#if defined(CONFIG_SOC_SERIES_GD32F3X0) || \
defined(CONFIG_SOC_SERIES_GD32A50X) || \
defined(CONFIG_SOC_SERIES_GD32L23X)
(GD32_OSPEED_10MHZ == GPIO_OSPEED_10MHZ) &&
(GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
#else
(GD32_OSPEED_25MHZ == GPIO_OSPEED_25MHZ) &&
(GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
(GD32_OSPEED_MAX == GPIO_OSPEED_MAX) &&
#endif
1U,
"pinctrl output speed definitions != HAL definitions");
/** Utility macro that expands to the GPIO port address if it exists */
#define GD32_PORT_ADDR_OR_NONE(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),), ())
/** Utility macro that expands to the GPIO clock id if it exists */
#define GD32_PORT_CLOCK_ID_OR_NONE(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_CLOCKS_CELL(DT_NODELABEL(nodelabel), id),), ())
/** GD32 port addresses */
static const uint32_t gd32_port_addrs[] = {
GD32_PORT_ADDR_OR_NONE(gpioa)
GD32_PORT_ADDR_OR_NONE(gpiob)
GD32_PORT_ADDR_OR_NONE(gpioc)
GD32_PORT_ADDR_OR_NONE(gpiod)
GD32_PORT_ADDR_OR_NONE(gpioe)
GD32_PORT_ADDR_OR_NONE(gpiof)
GD32_PORT_ADDR_OR_NONE(gpiog)
GD32_PORT_ADDR_OR_NONE(gpioh)
GD32_PORT_ADDR_OR_NONE(gpioi)
};
/** GD32 port clock identifiers */
static const uint16_t gd32_port_clkids[] = {
GD32_PORT_CLOCK_ID_OR_NONE(gpioa)
GD32_PORT_CLOCK_ID_OR_NONE(gpiob)
GD32_PORT_CLOCK_ID_OR_NONE(gpioc)
GD32_PORT_CLOCK_ID_OR_NONE(gpiod)
GD32_PORT_CLOCK_ID_OR_NONE(gpioe)
GD32_PORT_CLOCK_ID_OR_NONE(gpiof)
GD32_PORT_CLOCK_ID_OR_NONE(gpiog)
GD32_PORT_CLOCK_ID_OR_NONE(gpioh)
GD32_PORT_CLOCK_ID_OR_NONE(gpioi)
};
/**
* @brief Configure a pin.
*
* @param pin The pin to configure.
*/
static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
{
uint8_t port_idx;
uint32_t port, pin_num, af, mode;
uint16_t clkid;
port_idx = GD32_PORT_GET(pin);
__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(gd32_port_addrs));
clkid = gd32_port_clkids[port_idx];
port = gd32_port_addrs[port_idx];
pin_num = BIT(GD32_PIN_GET(pin));
af = GD32_AF_GET(pin);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&clkid);
if (af != GD32_ANALOG) {
mode = GPIO_MODE_AF;
gpio_af_set(port, af, pin_num);
} else {
mode = GPIO_MODE_ANALOG;
}
gpio_mode_set(port, mode, GD32_PUPD_GET(pin), pin_num);
gpio_output_options_set(port, GD32_OTYPE_GET(pin),
GD32_OSPEED_GET(pin), pin_num);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins[i]);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_gd32_af.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,014 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
/* SIUL2 Multiplexed Signal Configuration Register */
#define SIUL2_MSCR(n) (0x240 + 0x4 * (n))
/* SIUL2 Input Multiplexed Signal Configuration Register */
#define SIUL2_IMCR(n) (0xa40 + 0x4 * (n))
#define SIUL2_MSCR_MAX_IDX 512U
#define SIUL2_IMCR_MAX_IDX 512U
/*
* Utility macro that expands to the SIUL2 base address if it exists or zero.
* Note that some devices may have instance gaps, hence the need to keep them in the array.
*/
#define SIUL2_BASE_OR_ZERO(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel))), (0U))
static mem_addr_t siul2_bases[] = {
SIUL2_BASE_OR_ZERO(siul2_0), SIUL2_BASE_OR_ZERO(siul2_1), SIUL2_BASE_OR_ZERO(siul2_2),
SIUL2_BASE_OR_ZERO(siul2_3), SIUL2_BASE_OR_ZERO(siul2_4), SIUL2_BASE_OR_ZERO(siul2_5),
};
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
mem_addr_t base;
/* Multiplexed Signal Configuration */
__ASSERT_NO_MSG(pin->mscr.inst < ARRAY_SIZE(siul2_bases));
base = siul2_bases[pin->mscr.inst];
__ASSERT_NO_MSG(base != 0);
__ASSERT_NO_MSG(pin->mscr.idx < SIUL2_MSCR_MAX_IDX);
sys_write32(pin->mscr.val, (base + SIUL2_MSCR(pin->mscr.idx)));
/* Input Multiplexed Signal Configuration */
if (pin->mscr.val & SIUL2_MSCR_IBE_MASK) {
__ASSERT_NO_MSG(pin->imcr.inst < ARRAY_SIZE(siul2_bases));
base = siul2_bases[pin->imcr.inst];
__ASSERT_NO_MSG(base != 0);
__ASSERT_NO_MSG(pin->imcr.idx < SIUL2_IMCR_MAX_IDX);
sys_write32(pin->imcr.val, (base + SIUL2_IMCR(pin->imcr.idx)));
}
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 585 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
/* ambiq-sdk includes */
#include <am_mcu_apollo.h>
static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
{
am_hal_gpio_pincfg_t pin_config = {0};
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
pin_config.uFuncSel = pin->alt_func;
pin_config.eGPInput =
pin->input_enable ? AM_HAL_GPIO_PIN_INPUT_ENABLE : AM_HAL_GPIO_PIN_INPUT_NONE;
pin_config.eGPOutcfg = pin->push_pull ? AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL
: pin->open_drain ? AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
: pin->tristate ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE
: AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
pin_config.eDriveStrength = pin->drive_strength;
pin_config.uNCE = pin->iom_nce;
#if defined(CONFIG_SOC_APOLLO3P_BLUE)
pin_config.bIomMSPIn = pin->iom_mspi;
#endif
pin_config.uIOMnum = pin->iom_num;
if (pin->bias_pull_up) {
pin_config.ePullup = pin->ambiq_pull_up_ohms + AM_HAL_GPIO_PIN_PULLUP_1_5K;
} else if (pin->bias_pull_down) {
pin_config.ePullup = AM_HAL_GPIO_PIN_PULLDOWN;
}
#else
pin_config.GP.cfg_b.uFuncSel = pin->alt_func;
pin_config.GP.cfg_b.eGPInput =
pin->input_enable ? AM_HAL_GPIO_PIN_INPUT_ENABLE : AM_HAL_GPIO_PIN_INPUT_NONE;
pin_config.GP.cfg_b.eGPOutCfg = pin->push_pull ? AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL
: pin->open_drain ? AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN
: pin->tristate ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE
: AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
pin_config.GP.cfg_b.eDriveStrength = pin->drive_strength;
pin_config.GP.cfg_b.uSlewRate = pin->slew_rate;
pin_config.GP.cfg_b.uNCE = pin->iom_nce;
pin_config.GP.cfg_b.eIntDir = pin->interrupt_direction;
if (pin->bias_pull_up) {
pin_config.GP.cfg_b.ePullup = pin->ambiq_pull_up_ohms + AM_HAL_GPIO_PIN_PULLUP_1_5K;
} else if (pin->bias_pull_down) {
pin_config.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLDOWN_50K;
}
#endif
am_hal_gpio_pinconfig(pin->pin_num, pin_config);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 680 |
```c
/*
*
*/
#define DT_DRV_COMPAT ene_kb1200_pinctrl
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h>
#include <zephyr/sys/util.h>
#include <reg/gcfg.h>
#include <reg/gpio.h>
/*
* PINMUX_FUNC_A : GPIO Function
* PINMUX_FUNC_B : AltOutput 1 Function
* PINMUX_FUNC_C : AltOutput 2 Function
* PINMUX_FUNC_D : AltOutput 3 Function
* PINMUX_FUNC_E : AltOutput 4 Function
*
* GPIO Alternate Output Function Selection
* (PINMUX_FUNC_A) (PINMUX_FUNC_B) (PINMUX_FUNC_C) (PINMUX_FUNC_D) (PINMUX_FUNC_E)
* GPIO00 PWMLED0 PWM8
* GPIO01 SER_RXD1 UART_SIN SBUD_DAT
* GPIO03 SER_TXD1 UART_SOUT SBUD_CLK
* GPIO22 ESBDAT PWM9
* GPIO28 32KOUT SERCLK2
* GPIO36 UARTSOUT SERTXD2
* GPIO5C KSO6 P80DAT
* GPIO5D KSO7 P80CLK
* GPIO5E KSO8 SERRXD1
* GPIO5F KSO9 SERTXD1
* GPIO71 SDA8 UARTRTS
* GPIO38 SCL4 PWM1
*/
/*
* f is function number
* b[7:5] = pin bank
* b[4:0] = pin position in bank
* b[11:8] = function
*/
#define ENE_KB1200_PINMUX_PIN(p) FIELD_GET(GENMASK(4, 0), p)
#define ENE_KB1200_PINMUX_PORT(p) FIELD_GET(GENMASK(7, 5), p)
#define ENE_KB1200_PINMUX_FUNC(p) FIELD_GET(GENMASK(11, 8), p)
#define ENE_KB1200_PINMUX_PORT_PIN(p) FIELD_GET(GENMASK(7, 0), p)
static const uint32_t gcfg_reg_addr = DT_REG_ADDR(DT_NODELABEL(gcfg));
static const uint32_t gpio_reg_bases[] = {
DT_REG_ADDR(DT_NODELABEL(gpio0x1x)),
DT_REG_ADDR(DT_NODELABEL(gpio2x3x)),
DT_REG_ADDR(DT_NODELABEL(gpio4x5x)),
DT_REG_ADDR(DT_NODELABEL(gpio6x7x)),
};
static int kb1200_config_pin(uint32_t gpio, uint32_t conf, uint32_t func)
{
uint32_t port = ENE_KB1200_PINMUX_PORT(gpio);
uint32_t pin = (uint32_t)ENE_KB1200_PINMUX_PIN(gpio);
struct gpio_regs *gpio_regs = (struct gpio_regs *)gpio_reg_bases[port];
struct gcfg_regs *gcfg_regs = (struct gcfg_regs *)gcfg_reg_addr;
if (port >= NUM_KB1200_GPIO_PORTS) {
return -EINVAL;
}
if (func == PINMUX_FUNC_GPIO) { /* only GPIO function */
WRITE_BIT(gpio_regs->GPIOFS, pin, 0);
} else {
func -= 1; /*for change to GPIOALT setting value*/
switch (gpio) {
case GPIO00_PWMLED0_PWM8:
WRITE_BIT(gcfg_regs->GPIOALT, 0, func);
break;
case GPIO01_SERRXD1_UARTSIN:
gcfg_regs->GPIOMUX = (gcfg_regs->GPIOMUX & ~(3 << 9)) | (func << 9);
break;
case GPIO03_SERTXD1_UARTSOUT:
gcfg_regs->GPIOMUX = (gcfg_regs->GPIOMUX & ~(3 << 9)) | (func << 9);
break;
case GPIO22_ESBDAT_PWM9:
WRITE_BIT(gcfg_regs->GPIOALT, 1, func);
break;
case GPIO28_32KOUT_SERCLK2:
WRITE_BIT(gcfg_regs->GPIOALT, 2, func);
break;
case GPIO36_UARTSOUT_SERTXD2:
WRITE_BIT(gcfg_regs->GPIOALT, 3, func);
break;
case GPIO5C_KSO6_P80DAT:
WRITE_BIT(gcfg_regs->GPIOALT, 4, func);
break;
case GPIO5D_KSO7_P80CLK:
WRITE_BIT(gcfg_regs->GPIOALT, 5, func);
break;
case GPIO5E_KSO8_SERRXD1:
WRITE_BIT(gcfg_regs->GPIOALT, 6, func);
break;
case GPIO5F_KSO9_SERTXD1:
WRITE_BIT(gcfg_regs->GPIOALT, 7, func);
break;
case GPIO71_SDA8_UARTRTS:
WRITE_BIT(gcfg_regs->GPIOALT, 8, func);
break;
case GPIO38_SCL4_PWM1:
WRITE_BIT(gcfg_regs->GPIOALT, 9, func);
break;
}
WRITE_BIT(gpio_regs->GPIOFS, pin, 1);
}
/*Input always enable for loopback*/
WRITE_BIT(gpio_regs->GPIOIE, pin, 1);
if (conf & BIT(ENE_KB1200_NO_PUD_POS)) {
WRITE_BIT(gpio_regs->GPIOPU, pin, 0);
WRITE_BIT(gpio_regs->GPIOPD, pin, 0);
}
if (conf & BIT(ENE_KB1200_PU_POS)) {
WRITE_BIT(gpio_regs->GPIOPU, pin, 1);
}
if (conf & BIT(ENE_KB1200_PD_POS)) {
WRITE_BIT(gpio_regs->GPIOPD, pin, 1);
}
if (conf & BIT(ENE_KB1200_OUT_DIS_POS)) {
WRITE_BIT(gpio_regs->GPIOOE, pin, 0);
}
if (conf & BIT(ENE_KB1200_OUT_EN_POS)) {
WRITE_BIT(gpio_regs->GPIOOE, pin, 1);
}
if (conf & BIT(ENE_KB1200_OUT_LO_POS)) {
WRITE_BIT(gpio_regs->GPIOD, pin, 0);
}
if (conf & BIT(ENE_KB1200_OUT_HI_POS)) {
WRITE_BIT(gpio_regs->GPIOD, pin, 1);
}
if (conf & BIT(ENE_KB1200_PUSH_PULL_POS)) {
WRITE_BIT(gpio_regs->GPIOOD, pin, 0);
}
if (conf & BIT(ENE_KB1200_OPEN_DRAIN_POS)) {
WRITE_BIT(gpio_regs->GPIOOD, pin, 1);
}
if (conf & BIT(ENE_KB1200_PIN_LOW_POWER_POS)) {
WRITE_BIT(gpio_regs->GPIOLV, pin, 1);
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
uint32_t portpin, pinmux, func;
int ret;
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinmux = pins[i];
func = ENE_KB1200_PINMUX_FUNC(pinmux);
if (func >= PINMUX_FUNC_MAX) {
return -EINVAL;
}
portpin = ENE_KB1200_PINMUX_PORT_PIN(pinmux);
ret = kb1200_config_pin(portpin, pinmux, func);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ene_kb1200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,764 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc_gpio.h>
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
USART_TypeDef *base = (USART_TypeDef *)reg;
uint8_t loc;
#ifdef CONFIG_SOC_FAMILY_SILABS_S1
LEUART_TypeDef *lebase = (LEUART_TypeDef *)reg;
#else
#if USART_COUNT > 1
int usart_num = USART_NUM(base);
#else
int usart_num = 0;
(void)base;
#endif /*USART_COUNT > 1*/
#endif
#ifdef CONFIG_I2C_GECKO
I2C_TypeDef *i2c_base = (I2C_TypeDef *)reg;
#endif
#ifdef CONFIG_UART_GECKO
struct soc_gpio_pin rxpin = {0, 0, 0, 0};
struct soc_gpio_pin txpin = {0, 0, 0, 0};
#endif /* CONFIG_UART_GECKO */
struct soc_gpio_pin pin_config = {0, 0, 0, 0};
for (uint8_t i = 0U; i < pin_cnt; i++) {
pin_config.port = GECKO_GET_PORT(pins[i]);
pin_config.pin = GECKO_GET_PIN(pins[i]);
loc = GECKO_GET_LOC(pins[i]);
switch (GECKO_GET_FUN(pins[i])) {
#ifdef CONFIG_UART_GECKO
case GECKO_FUN_UART_RX:
rxpin.port = GECKO_GET_PORT(pins[i]);
rxpin.pin = GECKO_GET_PIN(pins[i]);
rxpin.mode = gpioModeInput;
rxpin.out = 1;
GPIO_PinModeSet(rxpin.port, rxpin.pin, rxpin.mode,
rxpin.out);
break;
case GECKO_FUN_UART_TX:
txpin.port = GECKO_GET_PORT(pins[i]);
txpin.pin = GECKO_GET_PIN(pins[i]);
txpin.mode = gpioModePushPull;
txpin.out = 1;
GPIO_PinModeSet(txpin.port, txpin.pin, txpin.mode,
txpin.out);
break;
#ifdef CONFIG_SOC_FAMILY_SILABS_S1
case GECKO_FUN_UART_RTS:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_UART_CTS:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_UART_RX_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_UART_TX_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_TXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_TXLOC_SHIFT);
break;
case GECKO_FUN_UART_RTS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RTSPEN;
base->ROUTELOC1 &= ~_USART_ROUTELOC1_RTSLOC_MASK;
base->ROUTELOC1 |= (loc << _USART_ROUTELOC1_RTSLOC_SHIFT);
break;
case GECKO_FUN_UART_CTS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CTSPEN;
base->ROUTELOC1 &= ~_USART_ROUTELOC1_CTSLOC_MASK;
base->ROUTELOC1 |= (loc << _USART_ROUTELOC1_CTSLOC_SHIFT);
break;
case GECKO_FUN_LEUART_RX_LOC:
lebase->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN;
lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_RXLOC_MASK;
lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_LEUART_TX_LOC:
lebase->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN;
lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_TXLOC_MASK;
lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_TXLOC_SHIFT);
break;
#else /* CONFIG_SOC_FAMILY_SILABS_S1 */
case GECKO_FUN_UART_LOC:
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
/* For SOCs with configurable pin_cfg locations (set in SOC Kconfig) */
base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN;
base->ROUTELOC0 = (loc << _USART_ROUTELOC0_TXLOC_SHIFT) |
(loc << _USART_ROUTELOC0_RXLOC_SHIFT);
base->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
#elif defined(USART_ROUTE_RXPEN) && defined(USART_ROUTE_TXPEN)
/* For olders SOCs with only one pin location */
base->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | (loc << 8);
#elif defined(GPIO_USART_ROUTEEN_RXPEN) && defined(GPIO_USART_ROUTEEN_TXPEN)
GPIO->USARTROUTE[usart_num].ROUTEEN =
GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN;
GPIO->USARTROUTE[usart_num].TXROUTE =
(txpin.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(txpin.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
GPIO->USARTROUTE[usart_num].RXROUTE =
(rxpin.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(rxpin.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
#ifdef UART_GECKO_HW_FLOW_CONTROL
/* Configure HW flow control (RTS, CTS) */
if (config->hw_flowcontrol) {
GPIO_PinModeSet(config->pin_rts.port,
config->pin_rts.pin,
config->pin_rts.mode,
config->pin_rts.out);
GPIO_PinModeSet(config->pin_cts.port,
config->pin_cts.pin,
config->pin_cts.mode,
config->pin_cts.out);
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
config->base->ROUTEPEN =
USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN |
USART_ROUTEPEN_RTSPEN | USART_ROUTEPEN_CTSPEN;
config->base->ROUTELOC1 =
(config->loc_rts << _USART_ROUTELOC1_RTSLOC_SHIFT) |
(config->loc_cts << _USART_ROUTELOC1_CTSLOC_SHIFT);
#elif defined(GPIO_USART_ROUTEEN_RTSPEN) && defined(GPIO_USART_ROUTEEN_CTSPEN)
GPIO->USARTROUTE[usart_num].ROUTEEN =
GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN |
GPIO_USART_ROUTEPEN_RTSPEN | GPIO_USART_ROUTEPEN_CTSPEN;
GPIO->USARTROUTE[usart_num].RTSROUTE =
(config->pin_rts.pin << _GPIO_USART_RTSROUTE_PIN_SHIFT) |
(config->pin_rts.port << _GPIO_USART_RTSROUTE_PORT_SHIFT);
GPIO->USARTROUTE[usart_num].CTSROUTE =
(config->pin_cts.pin << _GPIO_USART_CTSROUTE_PIN_SHIFT) |
(config->pin_cts.port << _GPIO_USART_CTSROUTE_PORT_SHIFT);
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
}
#endif /* UART_GECKO_HW_FLOW_CONTROL */
break;
#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */
#endif /* CONFIG_UART_GECKO */
#ifdef CONFIG_SPI_GECKO
#ifdef CONFIG_SOC_FAMILY_SILABS_S1
case GECKO_FUN_SPIM_SCK:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_MOSI:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_MISO:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_CS:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_SCK:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_MOSI:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_MISO:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_CS:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPI_SCK_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CLKPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_CLKLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CLKLOC_SHIFT);
break;
case GECKO_FUN_SPI_MOSI_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_TXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_TXLOC_SHIFT);
break;
case GECKO_FUN_SPI_MISO_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_SPI_CS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CSPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CSLOC_SHIFT);
break;
#else /* CONFIG_SOC_FAMILY_SILABS_S1 */
case GECKO_FUN_SPI_SCK:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_CLKPEN;
GPIO->USARTROUTE[usart_num].CLKROUTE =
(pin_config.pin << _GPIO_USART_CLKROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_CLKROUTE_PORT_SHIFT);
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPI_MOSI:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_TXPEN;
GPIO->USARTROUTE[usart_num].TXROUTE =
(pin_config.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPI_MISO:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_RXPEN;
GPIO->USARTROUTE[usart_num].RXROUTE =
(pin_config.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */
#endif /* CONFIG_SPI_GECKO */
#ifdef CONFIG_I2C_GECKO
case GECKO_FUN_I2C_SDA:
pin_config.mode = gpioModeWiredAnd;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
#if defined(GPIO_I2C_ROUTEEN_SDAPEN)
GPIO->I2CROUTE[I2C_NUM(i2c_base)].SDAROUTE =
(pin_config.pin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_I2C_SDAROUTE_PORT_SHIFT);
GPIO->I2CROUTE[I2C_NUM(i2c_base)].ROUTEEN |= GPIO_I2C_ROUTEEN_SDAPEN;
#endif
break;
case GECKO_FUN_I2C_SCL:
pin_config.mode = gpioModeWiredAnd;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
#if defined(GPIO_I2C_ROUTEEN_SCLPEN)
GPIO->I2CROUTE[I2C_NUM(i2c_base)].SCLROUTE =
(pin_config.pin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_I2C_SCLROUTE_PORT_SHIFT);
GPIO->I2CROUTE[I2C_NUM(i2c_base)].ROUTEEN |= GPIO_I2C_ROUTEEN_SCLPEN;
#endif
break;
case GECKO_FUN_I2C_SDA_LOC:
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
i2c_base->ROUTEPEN |= I2C_ROUTEPEN_SDAPEN;
i2c_base->ROUTELOC0 &= ~_I2C_ROUTELOC0_SDALOC_MASK;
i2c_base->ROUTELOC0 |= (loc << _I2C_ROUTELOC0_SDALOC_SHIFT);
#elif defined(I2C_ROUTE_SDAPEN)
i2c_base->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << 8);
#endif
break;
case GECKO_FUN_I2C_SCL_LOC:
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
i2c_base->ROUTEPEN |= I2C_ROUTEPEN_SCLPEN;
i2c_base->ROUTELOC0 &= ~_I2C_ROUTELOC0_SCLLOC_MASK;
i2c_base->ROUTELOC0 |= (loc << _I2C_ROUTELOC0_SCLLOC_SHIFT);
#elif defined(I2C_ROUTE_SCLPEN)
i2c_base->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << 8);
#endif
break;
#endif /* CONFIG_I2C_GECKO */
default:
return -ENOTSUP;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,515 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/init.h>
#if !defined(CONFIG_SOC_SERIES_LPC11U6X)
#include <fsl_clock.h>
#endif
#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
#define TYPE(mux) (((mux) & 0xC0000) >> 18)
#define IOCON_TYPE_D 0x0
#define IOCON_TYPE_I 0x1
#define IOCON_TYPE_A 0x2
static volatile uint32_t *iocon =
(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0; i < pin_cnt; i++) {
uint32_t pin_mux = pins[i];
uint32_t offset = OFFSET(pin_mux);
/* Check if this is an analog or i2c type pin */
switch (TYPE(pin_mux)) {
case IOCON_TYPE_D:
pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK;
break;
case IOCON_TYPE_I:
pin_mux &= Z_PINCTRL_IOCON_I_PIN_MASK;
break;
case IOCON_TYPE_A:
pin_mux &= Z_PINCTRL_IOCON_A_PIN_MASK;
break;
default:
/* Should not occur */
__ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A);
}
/* Set pinmux */
*(iocon + offset) = pin_mux;
}
return 0;
}
#if defined(CONFIG_SOC_FAMILY_LPC) && !defined(CONFIG_SOC_SERIES_LPC11U6X)
/* LPC family (except 11u6x) needs iocon clock to be enabled */
static int pinctrl_clock_init(void)
{
/* Enable IOCon clock */
CLOCK_EnableClock(kCLOCK_Iocon);
return 0;
}
SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
#endif /* CONFIG_SOC_FAMILY_LPC && !CONFIG_SOC_SERIES_LPC11U6X */
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_lpc_iocon.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 468 |
```unknown
config PINCTRL_GD32_AF
bool "GD32 AF pin controller driver"
default y
depends on DT_HAS_GD_GD32_PINCTRL_AF_ENABLED
help
GD32 AF pin controller driver. This driver is used by series using the
AF pin multiplexing model.
config PINCTRL_GD32_AFIO
bool "GD32 AFIO pin controller driver"
default y
depends on DT_HAS_GD_GD32_PINCTRL_AFIO_ENABLED
help
GD32 AFIO pin controller driver. This driver is used by series using the
AFIO pin multiplexing model.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
config PINCTRL_RV32M1
bool "RV32M1 pin controller driver"
default y
depends on DT_HAS_OPENISA_RV32M1_PINMUX_ENABLED
help
Enable the RV32M1 pin controller driver.
config PINCTRL_RV32M1_INIT_PRIORITY
int "RV32M1 initialization priority"
default 35
depends on PINCTRL_RV32M1
help
RV32M1 pin controller initialization priority.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.rv32m1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numicro_pinctrl
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/numicro-pinctrl.h>
#include <NuMicro.h>
#define MODE_PIN_SHIFT(pin) ((pin) * 2)
#define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin))
#define DINOFF_PIN_SHIFT(pin) ((pin) + 16)
#define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin))
#define PUSEL_PIN_SHIFT(pin) ((pin) * 2)
#define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin))
#define SLEWCTL_PIN_SHIFT(pin) ((pin) * 2)
#define SLEWCTL_MASK(pin) (3 << SLEWCTL_PIN_SHIFT(pin))
#define PORT_PIN_MASK 0xFFFF
#define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \
((port) * 8) + \
((pin) > 7 ? 4 : 0)))
#define REG_MFOS(port) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfos) + \
((port) * 4)))
#define MFP_CTL(pin, mfp) ((mfp) << (((pin) % 8) * 4))
/** Utility macro that expands to the GPIO port address if it exists */
#define NUMICRO_PORT_ADDR_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),))
/** Port addresses */
static const uint32_t gpio_port_addrs[] = {
NUMICRO_PORT_ADDR_OR_NONE(gpioa)
NUMICRO_PORT_ADDR_OR_NONE(gpiob)
NUMICRO_PORT_ADDR_OR_NONE(gpioc)
NUMICRO_PORT_ADDR_OR_NONE(gpiod)
NUMICRO_PORT_ADDR_OR_NONE(gpioe)
NUMICRO_PORT_ADDR_OR_NONE(gpiof)
NUMICRO_PORT_ADDR_OR_NONE(gpiog)
NUMICRO_PORT_ADDR_OR_NONE(gpioh)
};
static int gpio_configure(const pinctrl_soc_pin_t *pin)
{
uint8_t port_idx, pin_idx;
GPIO_T *port;
uint32_t bias = GPIO_PUSEL_DISABLE;
port_idx = NUMICRO_PORT(pin->pinmux);
if (port_idx >= ARRAY_SIZE(gpio_port_addrs)) {
return -EINVAL;
}
pin_idx = NUMICRO_PIN(pin->pinmux);
port = (GPIO_T *)gpio_port_addrs[port_idx];
if (pin->pull_up != 0) {
bias = GPIO_PUSEL_PULL_UP;
} else if (pin->pull_down != 0) {
bias = GPIO_PUSEL_PULL_DOWN;
}
port->MODE = (port->MODE & ~MODE_MASK(pin_idx)) |
((pin->open_drain ? 2 : 0) << MODE_PIN_SHIFT(pin_idx));
port->DBEN = (port->DBEN & ~BIT(pin_idx)) |
((pin->input_debounce ? 1 : 0) << pin_idx);
port->SMTEN = (port->SMTEN & ~BIT(pin_idx)) |
((pin->schmitt_trigger ? 1 : 0) << pin_idx);
port->DINOFF = (port->SMTEN & ~DINOFF_MASK(pin_idx)) |
((pin->input_disable ? 1 : 0) << DINOFF_PIN_SHIFT(pin_idx));
port->PUSEL = (port->PUSEL & ~PUSEL_MASK(pin_idx)) |
(bias << PUSEL_PIN_SHIFT(pin_idx));
port->SLEWCTL = (port->SLEWCTL & ~SLEWCTL_MASK(pin_idx)) |
(pin->slew_rate << SLEWCTL_PIN_SHIFT(pin_idx));
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
int ret = 0;
for (uint8_t i = 0U; i < pin_cnt; i++) {
uint32_t port = NUMICRO_PORT(pins[i].pinmux);
uint32_t pin = NUMICRO_PIN(pins[i].pinmux);
uint32_t mfp = NUMICRO_MFP(pins[i].pinmux);
REG_MFP(port, pin) = (REG_MFP(port, pin) & ~MFP_CTL(pin, 0xf)) |
MFP_CTL(pin, mfp);
if (pins[i].open_drain != 0) {
REG_MFOS(port) |= BIT(pin);
} else {
REG_MFOS(port) &= ~BIT(pin);
}
ret = gpio_configure(&pins[i]);
if (ret != 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_numicro.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,103 |
```unknown
config PINCTRL_MCHP_XEC
bool "Pin controller driver for MCHP XEC MCUs"
default y
depends on DT_HAS_MICROCHIP_XEC_PINCTRL_ENABLED
help
Enable pin controller driver for Microchip XEC MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc_port.h>
/** Utility macro that expands to the PORT port address if it exists */
#define SAM_PORT_ADDR_OR_NONE(nodelabel) \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),))
/** SAM0 port addresses */
static const uint32_t sam_port_addrs[] = {
SAM_PORT_ADDR_OR_NONE(porta)
SAM_PORT_ADDR_OR_NONE(portb)
SAM_PORT_ADDR_OR_NONE(portc)
SAM_PORT_ADDR_OR_NONE(portd)
SAM_PORT_ADDR_OR_NONE(porte)
SAM_PORT_ADDR_OR_NONE(portf)
};
static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
{
struct soc_port_pin soc_pin;
uint8_t port_idx, port_func;
port_idx = SAM_PINMUX_PORT_GET(pin);
__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(sam_port_addrs));
port_func = SAM_PINMUX_FUNC_GET(pin);
soc_pin.regs = (PortGroup *) sam_port_addrs[port_idx];
soc_pin.pinum = SAM_PINMUX_PIN_GET(pin);
soc_pin.flags = SAM_PINCTRL_FLAGS_GET(pin) << SOC_PORT_FLAGS_POS;
if (port_func == SAM_PINMUX_FUNC_periph) {
soc_pin.flags |= (SAM_PINMUX_PERIPH_GET(pin)
<< SOC_PORT_FUNC_POS)
| SOC_PORT_PMUXEN_ENABLE;
}
soc_port_configure(&soc_pin);
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_configure_pin(*pins++);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 394 |
```unknown
# NPCX Pin Controller configuration options
config PINCTRL_NPCX
bool "Nuvoton NPCX embedded controller (EC) pin controller driver"
default y
depends on DT_HAS_NUVOTON_NPCX_PINCTRL_ENABLED
help
This option enables the pin controller driver for NPCX family of
processors.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```unknown
config PINCTRL_EMSDP
bool "EMSDP pinmux driver"
default y
depends on DT_HAS_SNPS_EMSDP_PINCTRL_ENABLED
help
Enable driver for the synopsys ARC EMSDP pinctrl driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.emsdp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_pinctrl
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
#include <xmc_gpio.h>
#define GPIO_REG_SIZE 0x100
static int pinctrl_configure_pin(const pinctrl_soc_pin_t pinmux)
{
int port_id, pin, alt_fun, hwctrl;
XMC_GPIO_CONFIG_t pin_cfg = {0};
XMC_GPIO_PORT_t *gpio_port;
port_id = XMC4XXX_PINMUX_GET_PORT(pinmux);
if (port_id >= DT_INST_REG_SIZE(0) / GPIO_REG_SIZE) {
return -EINVAL;
}
pin = XMC4XXX_PINMUX_GET_PIN(pinmux);
if (XMC4XXX_PINMUX_GET_PULL_DOWN(pinmux)) {
pin_cfg.mode = XMC_GPIO_MODE_INPUT_PULL_DOWN;
}
if (XMC4XXX_PINMUX_GET_PULL_UP(pinmux)) {
pin_cfg.mode = XMC_GPIO_MODE_INPUT_PULL_UP;
}
if (XMC4XXX_PINMUX_GET_INV_INPUT(pinmux)) {
pin_cfg.mode |= 0x4;
}
if (XMC4XXX_PINMUX_GET_OPEN_DRAIN(pinmux)) {
pin_cfg.mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN;
}
if (XMC4XXX_PINMUX_GET_PUSH_PULL(pinmux)) {
pin_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
}
alt_fun = XMC4XXX_PINMUX_GET_ALT(pinmux);
pin_cfg.mode |= alt_fun << PORT0_IOCR0_PC0_Pos;
/* only has effect if mode is push_pull */
if (XMC4XXX_PINMUX_GET_OUT_HIGH(pinmux)) {
pin_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
}
/* only has effect if mode is push_pull */
if (XMC4XXX_PINMUX_GET_OUT_LOW(pinmux)) {
pin_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
}
/* only has effect if mode is push_pull */
pin_cfg.output_strength = XMC4XXX_PINMUX_GET_DRIVE(pinmux);
gpio_port = (XMC_GPIO_PORT_t *)((uint32_t)DT_INST_REG_ADDR(0) + port_id * GPIO_REG_SIZE);
XMC_GPIO_Init(gpio_port, pin, &pin_cfg);
hwctrl = XMC4XXX_PINMUX_GET_HWCTRL(pinmux);
if (hwctrl) {
XMC_GPIO_SetHardwareControl(gpio_port, pin, hwctrl);
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
int ret = pinctrl_configure_pin(*pins++);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 654 |
```unknown
config PINCTRL_XLNX_ZYNQMP
bool "Xilinx ZynqMP pin controller driver"
default y
depends on DT_HAS_XLNX_PINCTRL_ZYNQMP_ENABLED
help
Enable the Xilinx ZynqMP processor system MIO pin controller driver.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.zynqmp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <chip_chipregs.h>
LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
#define GPIO_IT8XXX2_REG_BASE \
((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
#define GPIO_GROUP_MEMBERS 8
struct pinctrl_it8xxx2_gpio {
/* gpio port control register (byte mapping to pin) */
uint8_t *reg_gpcr;
/* port driving select control */
uint8_t *reg_pdsc;
/* function 3 general control register */
uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
/* function 3 enable mask */
uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
/* function 3 external control register */
uintptr_t func3_ext[GPIO_GROUP_MEMBERS];
/* function 3 external mask */
uint8_t func3_ext_mask[GPIO_GROUP_MEMBERS];
/* function 4 general control register */
uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
/* function 4 enable mask */
uint8_t func4_en_mask[GPIO_GROUP_MEMBERS];
/* Input voltage selection */
uintptr_t volt_sel[GPIO_GROUP_MEMBERS];
/* Input voltage selection mask */
uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
};
struct pinctrl_it8xxx2_ksi_kso {
/*
* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
* (bit mapping to pin)
*/
uint8_t *reg_gctrl;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
uint8_t *reg_ctrl;
/*
* KSO push-pull/open-drain bit of KSO[15:0] control register
* (this bit apply to all pins)
*/
int pp_od_mask;
/*
* KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
* (this bit apply to all pins)
*/
int pullup_mask;
};
struct pinctrl_it8xxx2_config {
bool gpio_group;
union {
struct pinctrl_it8xxx2_gpio gpio;
struct pinctrl_it8xxx2_ksi_kso ksi_kso;
};
};
static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
uint32_t pincfg = pins->pincfg;
uint8_t pin = pins->pin;
volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);
volatile uint8_t *reg_pdsc = (uint8_t *)gpio->reg_pdsc;
/* Setting pull-up or pull-down. */
switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
case IT8XXX2_PULL_PIN_DEFAULT:
/* No pull-up or pull-down */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
GPCR_PORT_PIN_MODE_PULLDOWN);
break;
case IT8XXX2_PULL_UP:
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
~GPCR_PORT_PIN_MODE_PULLDOWN;
break;
case IT8XXX2_PULL_DOWN:
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
~GPCR_PORT_PIN_MODE_PULLUP;
break;
default:
LOG_ERR("This pull level is not supported.");
return -EINVAL;
}
/*
* Since not all GPIOs support voltage selection, configure voltage
* selection register only if it is present.
*/
if (reg_volt_sel != NULL) {
/* Setting voltage 3.3V or 1.8V. */
switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
case IT8XXX2_VOLTAGE_3V3:
/* Input voltage selection 3.3V. */
*reg_volt_sel &= ~gpio->volt_sel_mask[pin];
break;
case IT8XXX2_VOLTAGE_1V8:
__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
== IT8XXX2_PULL_UP),
"Don't enable internal pullup if 1.8V voltage is used");
/* Input voltage selection 1.8V. */
*reg_volt_sel |= gpio->volt_sel_mask[pin];
break;
default:
LOG_ERR("The voltage selection is not supported");
return -EINVAL;
}
}
/* Setting tri-state mode. */
if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) {
*reg_gpcr |= (GPCR_PORT_PIN_MODE_PULLUP |
GPCR_PORT_PIN_MODE_PULLDOWN);
}
/* Driving current selection. */
if (reg_pdsc != NULL &&
IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) != IT8XXX2_DRIVE_DEFAULT) {
if (IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) & IT8XXX2_PDSCX_MASK) {
/* Driving current selects low. */
*reg_pdsc |= BIT(pin);
} else {
/* Driving current selects high. */
*reg_pdsc &= ~BIT(pin);
}
}
return 0;
}
static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
uint8_t pin = pins->pin;
volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
volatile uint8_t *reg_func3_ext = (uint8_t *)(gpio->func3_ext[pin]);
/* Handle PIN configuration. */
if (pinctrl_it8xxx2_set(pins)) {
LOG_ERR("Pin configuration is invalid.");
return -EINVAL;
}
/*
* Default input mode prevents leakage during changes to extended
* setting (e.g. enabling i2c functionality on GPIO E1/E2 on IT82002)
*/
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
/*
* If pincfg is input, we don't need to handle
* alternate function.
*/
if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {
return 0;
}
/*
* Handle alternate function.
*/
if (reg_func3_gcr != NULL) {
*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
}
/* Ensure that func3-ext setting is in default state. */
if (reg_func3_ext != NULL) {
*reg_func3_ext &= ~gpio->func3_ext_mask[pin];
}
switch (pins->alt_func) {
case IT8XXX2_ALT_FUNC_1:
/* Func1: Alternate function will be set below. */
break;
case IT8XXX2_ALT_FUNC_2:
/* Func2: WUI function: pin has been set as input above.*/
return 0;
case IT8XXX2_ALT_FUNC_3:
/*
* Func3: In addition to the alternate setting above,
* Func3 also need to set the general control.
*/
if (reg_func3_gcr != NULL) {
*reg_func3_gcr |= gpio->func3_en_mask[pin];
}
/* Func3-external: Some pins require external setting. */
if (reg_func3_ext != NULL) {
*reg_func3_ext |= gpio->func3_ext_mask[pin];
}
break;
case IT8XXX2_ALT_FUNC_4:
/*
* Func4: In addition to the alternate setting above,
* Func4 also need to set the general control.
*/
*reg_func4_gcr |= gpio->func4_en_mask[pin];
break;
case IT8XXX2_ALT_DEFAULT:
*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
*reg_func4_gcr &= ~gpio->func4_en_mask[pin];
return 0;
default:
LOG_ERR("This function is not supported.");
return -EINVAL;
}
/* Common settings for alternate function. */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
return 0;
}
static int pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;
uint8_t pullup_mask = ksi_kso->pullup_mask;
uint8_t pp_od_mask = ksi_kso->pp_od_mask;
uint32_t pincfg = pins->pincfg;
/*
* Enable or disable internal pull-up (this bit apply to all pins):
* If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
* pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
* If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
*/
switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) {
case IT8XXX2_PULL_PIN_DEFAULT:
/* Disable internal pulll-up */
*reg_ctrl &= ~pullup_mask;
break;
case IT8XXX2_PULL_UP:
*reg_ctrl |= pullup_mask;
break;
default:
LOG_ERR("This pull level is not supported.");
return -EINVAL;
}
/*
* Set push-pull or open-drain mode (this bit apply to all pins):
* KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.
* If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
* setting 0 selects push-pull mode.
* If KSO[15:0] is in GPIO mode, then this bit is always disabled.
*/
if (pp_od_mask != NO_FUNC) {
switch (IT8XXX2_DT_PINCFG_PP_OD(pincfg)) {
case IT8XXX2_PUSH_PULL:
*reg_ctrl &= ~pp_od_mask;
break;
case IT8XXX2_OPEN_DRAIN:
*reg_ctrl |= pp_od_mask;
break;
default:
LOG_ERR("This pull mode is not supported.");
return -EINVAL;
}
}
return 0;
}
static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
{
const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
/* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
if (pinctrl_kscan_it8xxx2_set(pins)) {
return -EINVAL;
}
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
uint8_t pin_mask = BIT(pins->pin);
volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
switch (pins->alt_func) {
case IT8XXX2_ALT_FUNC_1:
/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
*reg_gctrl &= ~pin_mask;
break;
case IT8XXX2_ALT_DEFAULT:
/* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
*reg_gctrl |= pin_mask;
break;
#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
uint8_t pin = pins->pin;
volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl + pin;
switch (pins->alt_func) {
case IT8XXX2_ALT_FUNC_1:
/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
*reg_gctrl &= ~(GPCR_PORT_PIN_MODE_INPUT |
GPCR_PORT_PIN_MODE_OUTPUT);
break;
case IT8XXX2_ALT_DEFAULT:
/* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
*reg_gctrl = (*reg_gctrl | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
break;
#endif
default:
LOG_ERR("Alternate function not supported");
return -ENOTSUP;
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
const struct pinctrl_it8xxx2_config *pinctrl_config;
int status;
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinctrl_config = pins[i].pinctrls->config;
if (pinctrl_config->gpio_group) {
status = pinctrl_gpio_it8xxx2_configure_pins(&pins[i]);
} else {
status = pinctrl_kscan_it8xxx2_configure_pins(&pins[i]);
}
if (status < 0) {
LOG_ERR("%s pin%d configuration is invalid.",
pins[i].pinctrls->name, pins[i].pin);
return status;
}
}
return 0;
}
static int pinctrl_it8xxx2_init(const struct device *dev)
{
struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
/*
* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
* If LPC reset is enabled on GPB7, we have to clear bit2:1
* to 00b.
*/
gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
#if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS(DT_NODELABEL(i2c5), okay)
const struct gpio_dt_spec scl_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), scl_gpios);
const struct gpio_dt_spec sda_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), sda_gpios);
/*
* When setting these pins as I2C alternate mode and then setting
* GCR7 or func3-ext of GPIO extended, it will cause leakage.
* In order to prevent leakage, it must be set to GPIO INPUT mode.
*/
/* Set I2C5 SCL as GPIO input to prevent leakage */
gpio_pin_configure_dt(&scl_gpios, GPIO_INPUT);
/* Set I2C5 SDA as GPIO input to prevent leakage */
gpio_pin_configure_dt(&sda_gpios, GPIO_INPUT);
#endif
/*
* Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
* and I2C3 SMCLK3/SMDAT3 pins from GPB2/GPB5 to GPH1/GPH2,
* and I2C5 SMCLK5/SMDAT5 pins from GPE1/GPE2 to GPA4/GPA5,
*/
gpio_base->GPIO_GCR7 &= ~(IT8XXX2_GPIO_SMB2PS |
IT8XXX2_GPIO_SMB3PS |
IT8XXX2_GPIO_SMB5PS);
#endif
return 0;
}
#define INIT_UNION_CONFIG(inst) \
COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
(.gpio = { \
.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_pdsc = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
.func3_ext = DT_INST_PROP_OR(inst, func3_ext, {0}), \
.func3_ext_mask = DT_INST_PROP_OR(inst, func3_ext_mask, {0}), \
.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
.volt_sel = DT_INST_PROP(inst, volt_sel), \
.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
}), \
(.ksi_kso = { \
.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
}) \
)
#define PINCTRL_ITE_INIT(inst) \
static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
.gpio_group = DT_INST_PROP(inst, gpio_group), \
{ \
INIT_UNION_CONFIG(inst) \
} \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
NULL, \
NULL, \
&pinctrl_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,237 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <hal/nrf_gpio.h>
BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) &&
(NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) &&
(NRF_PULL_UP == NRF_GPIO_PIN_PULLUP)),
"nRF pinctrl pull settings do not match HAL values");
#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
#define NRF_DRIVE_COUNT (NRF_DRIVE_E0E1 + 1)
#else
#define NRF_DRIVE_COUNT (NRF_DRIVE_H0D1 + 1)
#endif
static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
[NRF_DRIVE_S0S1] = NRF_GPIO_PIN_S0S1,
[NRF_DRIVE_H0S1] = NRF_GPIO_PIN_H0S1,
[NRF_DRIVE_S0H1] = NRF_GPIO_PIN_S0H1,
[NRF_DRIVE_H0H1] = NRF_GPIO_PIN_H0H1,
[NRF_DRIVE_D0S1] = NRF_GPIO_PIN_D0S1,
[NRF_DRIVE_D0H1] = NRF_GPIO_PIN_D0H1,
[NRF_DRIVE_S0D1] = NRF_GPIO_PIN_S0D1,
[NRF_DRIVE_H0D1] = NRF_GPIO_PIN_H0D1,
#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
[NRF_DRIVE_E0E1] = NRF_GPIO_PIN_E0E1,
#endif
};
/* value to indicate pin level doesn't need initialization */
#define NO_WRITE UINT32_MAX
#define PSEL_DISCONNECTED 0xFFFFFFFFUL
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart) || defined(CONFIG_NRFX_UART)
#define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte) || defined(CONFIG_NRFX_UARTE)
#include <hal/nrf_uarte.h>
#define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) || defined(CONFIG_NRFX_SPI)
#define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) || defined(CONFIG_NRFX_SPIM)
#include <hal/nrf_spim.h>
#define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) || defined(CONFIG_NRFX_SPIS)
#include <hal/nrf_spis.h>
#if defined(NRF51)
#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line
#else
#define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line
#endif
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twi) || defined(CONFIG_NRFX_TWI)
#if !defined(TWI_PSEL_SCL_CONNECT_Pos)
#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line
#else
#define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line
#endif
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim) || defined(CONFIG_NRFX_TWIM)
#include <hal/nrf_twim.h>
#define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_i2s) || defined(CONFIG_NRFX_I2S)
#define NRF_PSEL_I2S(reg, line) ((NRF_I2S_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pdm) || defined(CONFIG_NRFX_PDM)
#define NRF_PSEL_PDM(reg, line) ((NRF_PDM_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm) || defined(CONFIG_NRFX_PWM)
#define NRF_PSEL_PWM(reg, line) ((NRF_PWM_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qdec) || defined(CONFIG_NRFX_QDEC)
#define NRF_PSEL_QDEC(reg, line) ((NRF_QDEC_Type *)reg)->PSEL.line
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qspi) || defined(CONFIG_NRFX_QSPI)
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0U; i < pin_cnt; i++) {
nrf_gpio_pin_drive_t drive;
uint8_t drive_idx = NRF_GET_DRIVE(pins[i]);
uint32_t psel = NRF_GET_PIN(pins[i]);
uint32_t write = NO_WRITE;
nrf_gpio_pin_dir_t dir;
nrf_gpio_pin_input_t input;
if (drive_idx < ARRAY_SIZE(drive_modes)) {
drive = drive_modes[drive_idx];
} else {
return -EINVAL;
}
if (psel == NRF_PIN_DISCONNECTED) {
psel = PSEL_DISCONNECTED;
}
switch (NRF_GET_FUN(pins[i])) {
#if defined(NRF_PSEL_UART)
case NRF_FUN_UART_TX:
NRF_PSEL_UART(reg, TXD) = psel;
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_UART_RX:
NRF_PSEL_UART(reg, RXD) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_UART_RTS:
NRF_PSEL_UART(reg, RTS) = psel;
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_UART_CTS:
NRF_PSEL_UART(reg, CTS) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_UART) */
#if defined(NRF_PSEL_SPIM)
case NRF_FUN_SPIM_SCK:
NRF_PSEL_SPIM(reg, SCK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_SPIM_MOSI:
NRF_PSEL_SPIM(reg, MOSI) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_SPIM_MISO:
NRF_PSEL_SPIM(reg, MISO) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_SPIM) */
#if defined(NRF_PSEL_SPIS)
case NRF_FUN_SPIS_SCK:
NRF_PSEL_SPIS(reg, SCK) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_SPIS_MOSI:
NRF_PSEL_SPIS(reg, MOSI) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_SPIS_MISO:
NRF_PSEL_SPIS(reg, MISO) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_SPIS_CSN:
NRF_PSEL_SPIS(reg, CSN) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_SPIS) */
#if defined(NRF_PSEL_TWIM)
case NRF_FUN_TWIM_SCL:
NRF_PSEL_TWIM(reg, SCL) = psel;
if (drive == NRF_GPIO_PIN_S0S1) {
/* Override the default drive setting with one
* suitable for TWI/TWIM peripherals (S0D1).
* This drive cannot be used always so that
* users are able to select e.g. H0D1 or E0E1
* in devicetree.
*/
drive = NRF_GPIO_PIN_S0D1;
}
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_TWIM_SDA:
NRF_PSEL_TWIM(reg, SDA) = psel;
if (drive == NRF_GPIO_PIN_S0S1) {
drive = NRF_GPIO_PIN_S0D1;
}
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_TWIM) */
#if defined(NRF_PSEL_I2S)
case NRF_FUN_I2S_SCK_M:
NRF_PSEL_I2S(reg, SCK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_I2S_SCK_S:
NRF_PSEL_I2S(reg, SCK) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_I2S_LRCK_M:
NRF_PSEL_I2S(reg, LRCK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_I2S_LRCK_S:
NRF_PSEL_I2S(reg, LRCK) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_I2S_SDIN:
NRF_PSEL_I2S(reg, SDIN) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_I2S_SDOUT:
NRF_PSEL_I2S(reg, SDOUT) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_I2S_MCK:
NRF_PSEL_I2S(reg, MCK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
#endif /* defined(NRF_PSEL_I2S) */
#if defined(NRF_PSEL_PDM)
case NRF_FUN_PDM_CLK:
NRF_PSEL_PDM(reg, CLK) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_PDM_DIN:
NRF_PSEL_PDM(reg, DIN) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_PDM) */
#if defined(NRF_PSEL_PWM)
case NRF_FUN_PWM_OUT0:
NRF_PSEL_PWM(reg, OUT[0]) = psel;
write = NRF_GET_INVERT(pins[i]);
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_PWM_OUT1:
NRF_PSEL_PWM(reg, OUT[1]) = psel;
write = NRF_GET_INVERT(pins[i]);
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_PWM_OUT2:
NRF_PSEL_PWM(reg, OUT[2]) = psel;
write = NRF_GET_INVERT(pins[i]);
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_PWM_OUT3:
NRF_PSEL_PWM(reg, OUT[3]) = psel;
write = NRF_GET_INVERT(pins[i]);
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
#endif /* defined(NRF_PSEL_PWM) */
#if defined(NRF_PSEL_QDEC)
case NRF_FUN_QDEC_A:
NRF_PSEL_QDEC(reg, A) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_QDEC_B:
NRF_PSEL_QDEC(reg, B) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
case NRF_FUN_QDEC_LED:
NRF_PSEL_QDEC(reg, LED) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_QDEC) */
#if defined(NRF_PSEL_QSPI)
case NRF_FUN_QSPI_SCK:
NRF_PSEL_QSPI(reg, SCK) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_QSPI_CSN:
NRF_PSEL_QSPI(reg, CSN) = psel;
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_QSPI_IO0:
NRF_PSEL_QSPI(reg, IO0) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_QSPI_IO1:
NRF_PSEL_QSPI(reg, IO1) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_QSPI_IO2:
NRF_PSEL_QSPI(reg, IO2) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_QSPI_IO3:
NRF_PSEL_QSPI(reg, IO3) = psel;
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
#endif /* defined(NRF_PSEL_QSPI) */
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can)
/* Pin routing is controlled by secure domain, via UICR */
case NRF_FUN_CAN_TX:
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
break;
case NRF_FUN_CAN_RX:
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */
default:
return -ENOTSUP;
}
/* configure GPIO properties */
if (psel != PSEL_DISCONNECTED) {
uint32_t pin = psel;
if (write != NO_WRITE) {
nrf_gpio_pin_write(pin, write);
}
/* force input and disconnected buffer for low power */
if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
}
nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
drive, NRF_GPIO_PIN_NOSENSE);
#if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
#endif
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_nrf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,540 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/drivers/pinctrl.h>
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
/* configure all pins */
for (uint8_t i = 0U; i < pin_cnt; i++) {
uint32_t mux_register = pins[i].pinmux.mux_register;
uint32_t mux_mode = pins[i].pinmux.mux_mode;
uint32_t input_register = pins[i].pinmux.input_register;
uint32_t input_daisy = pins[i].pinmux.input_daisy;
uint32_t config_register = pins[i].pinmux.config_register;
uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
volatile uint32_t *gpr_register =
(volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register);
if (gpr_register) {
/* Set or clear specified GPR bit for this mux */
if (pins[i].pinmux.gpr_val) {
*gpr_register |=
(pins[i].pinmux.gpr_val << pins[i].pinmux.gpr_shift);
} else {
*gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
}
}
#endif
#ifdef CONFIG_SOC_MIMX9352_A55
sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
(mem_addr_t)mux_register);
if (input_register) {
sys_write32(IOMUXC1_SELECT_INPUT_DAISY(input_daisy),
(mem_addr_t)input_register);
}
if (config_register) {
sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
(mem_addr_t)config_register);
}
#elif defined(CONFIG_SOC_MIMX8UD7)
if (mux_register == config_register) {
sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode) |
pin_ctrl_flags, (mem_addr_t)mux_register);
} else {
sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode),
(mem_addr_t)mux_register);
if (config_register) {
sys_write32(pin_ctrl_flags, (mem_addr_t)config_register);
}
}
if (input_register) {
sys_write32(IOMUXC_PSMI_SSS(input_daisy), (mem_addr_t)input_register);
}
#else
sys_write32(
IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
(mem_addr_t)mux_register);
if (input_register) {
sys_write32(IOMUXC_SELECT_INPUT_DAISY(input_daisy),
(mem_addr_t)input_register);
}
if (config_register) {
sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
config_register);
}
#endif
}
return 0;
}
static int imx_pinctrl_init(void)
{
#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc);
#ifdef CONFIG_SOC_SERIES_IMXRT10XX
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
CLOCK_EnableClock(kCLOCK_IomuxcGpr);
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
#endif /* CONFIG_SOC_SERIES_IMXRT10XX */
#elif defined(CONFIG_SOC_MIMX8MQ6)
CLOCK_EnableClock(kCLOCK_Iomux);
#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */
#if defined(CONFIG_SOC_SERIES_IMXRT118X)
CLOCK_EnableClock(kCLOCK_Iomuxc1);
CLOCK_EnableClock(kCLOCK_Iomuxc2);
#endif /* CONFIG_SOC_SERIES_IMXRT118X */
return 0;
}
SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_imx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 980 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
const struct pinctrl_state **state)
{
*state = &config->states[0];
while (*state < &config->states[config->state_cnt]) {
if (id == (*state)->id) {
return 0;
}
(*state)++;
}
return -ENOENT;
}
#ifdef CONFIG_PINCTRL_DYNAMIC
int pinctrl_update_states(struct pinctrl_dev_config *config,
const struct pinctrl_state *states,
uint8_t state_cnt)
{
uint8_t equal = 0U;
/* check we are inserting same number of states */
if (config->state_cnt != state_cnt) {
return -EINVAL;
}
/* check we have the same states */
for (uint8_t i = 0U; i < state_cnt; i++) {
for (uint8_t j = 0U; j < config->state_cnt; j++) {
if (states[i].id == config->states[j].id) {
equal++;
break;
}
}
}
if (equal != state_cnt) {
return -EINVAL;
}
/* replace current states */
config->states = states;
return 0;
}
#endif /* CONFIG_PINCTRL_DYNAMIC */
``` | /content/code_sandbox/drivers/pinctrl/common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 302 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <gd32_gpio.h>
/** AFIO DT node */
#define AFIO_NODE DT_NODELABEL(afio)
/** GPIO mode: input floating (CTL bits) */
#define GPIO_MODE_INP_FLOAT 0x4U
/** GPIO mode: input with pull-up/down (CTL bits) */
#define GPIO_MODE_INP_PUPD 0x8U
/** GPIO mode: output push-pull (CTL bits) */
#define GPIO_MODE_ALT_PP 0x8U
/** GPIO mode: output open-drain (CTL bits) */
#define GPIO_MODE_ALT_OD 0xCU
/** Utility macro that expands to the GPIO port address if it exists */
#define GD32_PORT_ADDR_OR_NONE(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_REG_ADDR(DT_NODELABEL(nodelabel)),), ())
/** Utility macro that expands to the GPIO clock id if it exists */
#define GD32_PORT_CLOCK_ID_OR_NONE(nodelabel) \
COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
(DT_CLOCKS_CELL(DT_NODELABEL(nodelabel), id),), ())
/** GD32 port addresses */
static const uint32_t gd32_port_addrs[] = {
GD32_PORT_ADDR_OR_NONE(gpioa)
GD32_PORT_ADDR_OR_NONE(gpiob)
GD32_PORT_ADDR_OR_NONE(gpioc)
GD32_PORT_ADDR_OR_NONE(gpiod)
GD32_PORT_ADDR_OR_NONE(gpioe)
GD32_PORT_ADDR_OR_NONE(gpiof)
GD32_PORT_ADDR_OR_NONE(gpiog)
};
/** GD32 port clock identifiers */
static const uint16_t gd32_port_clkids[] = {
GD32_PORT_CLOCK_ID_OR_NONE(gpioa)
GD32_PORT_CLOCK_ID_OR_NONE(gpiob)
GD32_PORT_CLOCK_ID_OR_NONE(gpioc)
GD32_PORT_CLOCK_ID_OR_NONE(gpiod)
GD32_PORT_CLOCK_ID_OR_NONE(gpioe)
GD32_PORT_CLOCK_ID_OR_NONE(gpiof)
GD32_PORT_CLOCK_ID_OR_NONE(gpiog)
};
/**
* @brief Initialize AFIO
*
* This function enables AFIO clock and configures the I/O compensation if
* available and enabled in Devicetree.
*
* @retval 0 Always
*/
static int afio_init(void)
{
uint16_t clkid = DT_CLOCKS_CELL(AFIO_NODE, id);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&clkid);
#ifdef AFIO_CPSCTL
if (DT_PROP(AFIO_NODE, enable_cps)) {
gpio_compensation_config(GPIO_COMPENSATION_ENABLE);
while (gpio_compensation_flag_get() == RESET)
;
}
#endif /* AFIO_CPSCTL */
return 0;
}
SYS_INIT(afio_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
/**
* @brief Helper function to configure the SPD register if available.
*
* @param port GPIO port address.
* @param pin_bit GPIO pin, set as bit position.
* @param speed GPIO speed.
*
* @return Value of the mode register (speed) that should be set later.
*/
static inline uint8_t configure_spd(uint32_t port, uint32_t pin_bit,
uint8_t speed)
{
switch (speed) {
case GD32_OSPEED_MAX:
#ifdef GPIOx_SPD
GPIOx_SPD(port) |= pin_bit;
#endif /* GPIOx_SPD */
return speed;
default:
#ifdef GPIOx_SPD
GPIOx_SPD(port) &= ~pin_bit;
#endif /* GPIOx_SPD */
return speed + 1U;
}
}
/**
* @brief Configure a pin.
*
* @param pin The pin to configure.
*/
static void configure_pin(pinctrl_soc_pin_t pin)
{
uint8_t port_idx, mode, pin_num;
uint32_t port, pin_bit, reg_val;
volatile uint32_t *reg;
uint16_t clkid;
port_idx = GD32_PORT_GET(pin);
__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(gd32_port_addrs));
clkid = gd32_port_clkids[port_idx];
port = gd32_port_addrs[port_idx];
pin_num = GD32_PIN_GET(pin);
pin_bit = BIT(pin_num);
mode = GD32_MODE_GET(pin);
if (pin_num < 8U) {
reg = &GPIO_CTL0(port);
} else {
reg = &GPIO_CTL1(port);
pin_num -= 8U;
}
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&clkid);
reg_val = *reg;
reg_val &= ~GPIO_MODE_MASK(pin_num);
if (mode == GD32_MODE_ALTERNATE) {
uint8_t new_mode;
new_mode = configure_spd(port, pin_bit, GD32_OSPEED_GET(pin));
if (GD32_OTYPE_GET(pin) == GD32_OTYPE_PP) {
new_mode |= GPIO_MODE_ALT_PP;
} else {
new_mode |= GPIO_MODE_ALT_OD;
}
reg_val |= GPIO_MODE_SET(pin_num, new_mode);
} else if (mode == GD32_MODE_GPIO_IN) {
uint8_t pupd = GD32_PUPD_GET(pin);
if (pupd == GD32_PUPD_NONE) {
reg_val |= GPIO_MODE_SET(pin_num, GPIO_MODE_INP_FLOAT);
} else {
reg_val |= GPIO_MODE_SET(pin_num, GPIO_MODE_INP_PUPD);
if (pupd == GD32_PUPD_PULLDOWN) {
GPIO_BC(port) = pin_bit;
} else if (pupd == GD32_PUPD_PULLUP) {
GPIO_BOP(port) = pin_bit;
}
}
}
*reg = reg_val;
}
/**
* @brief Configure remap.
*
* @param remap Remap bit field as encoded by #GD32_REMAP.
*/
static void configure_remap(uint16_t remap)
{
uint8_t pos;
uint32_t reg_val;
volatile uint32_t *reg;
/* not remappable */
if (remap == GD32_NORMP) {
return;
}
if (GD32_REMAP_REG_GET(remap) == 0U) {
reg = &AFIO_PCF0;
} else {
reg = &AFIO_PCF1;
}
pos = GD32_REMAP_POS_GET(remap);
reg_val = *reg;
reg_val &= ~(GD32_REMAP_MSK_GET(remap) << pos);
reg_val |= GD32_REMAP_VAL_GET(remap) << pos;
*reg = reg_val;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
if (pin_cnt == 0U) {
return -EINVAL;
}
/* same remap is encoded in all pins, so just pick the first */
configure_remap(GD32_REMAP_GET(pins[0]));
/* configure all pins */
for (uint8_t i = 0U; i < pin_cnt; i++) {
configure_pin(pins[i]);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_gd32_afio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,610 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_pinctrl
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/*
* Microchip XEC: each GPIO pin has two 32-bit control register.
* The first 32-bit register contains all pin features except
* slew rate and driver strength in the second control register.
* We compute the register index from the beginning of the GPIO
* control address space which is the same range of the PINCTRL
* parent node. A zero value in the PINCTRL pinmux field means
* do not touch.
*/
static void config_drive_slew(struct gpio_regs * const regs, uint32_t idx, uint32_t conf)
{
uint32_t slew = (conf >> MCHP_XEC_SLEW_RATE_POS) & MCHP_XEC_SLEW_RATE_MSK0;
uint32_t drvstr = (conf >> MCHP_XEC_DRV_STR_POS) & MCHP_XEC_DRV_STR_MSK0;
uint32_t msk = 0, val = 0;
if (slew) {
msk |= MCHP_GPIO_CTRL2_SLEW_MASK;
/* slow slew value is 0 */
if (slew == MCHP_XEC_SLEW_RATE_FAST0) {
val |= MCHP_GPIO_CTRL2_SLEW_FAST;
}
}
if (drvstr) {
msk |= MCHP_GPIO_CTRL2_DRV_STR_MASK;
/* drive strength values are 0 based */
val |= ((drvstr - 1u) << MCHP_GPIO_CTRL2_DRV_STR_POS);
}
if (!msk) {
return;
}
regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk);
}
/*
* Internal pulls feature:
* None, weak pull-up, weak pull-down, or repeater mode (both pulls enabled).
* We do not touch this field unless one or more of the DT booleans are set.
* If the no-bias boolean is set then disable internal pulls.
* If pull up and/or down is set enable the respective pull or both for what
* MCHP calls repeater(keeper) mode.
*/
static uint32_t prog_pud(uint32_t pcr1, uint32_t conf)
{
if (conf & BIT(MCHP_XEC_NO_PUD_POS)) {
pcr1 &= ~(MCHP_GPIO_CTRL_PUD_MASK);
pcr1 |= MCHP_GPIO_CTRL_PUD_NONE;
return pcr1;
}
if (conf & (BIT(MCHP_XEC_PU_POS) | BIT(MCHP_XEC_PD_POS))) {
pcr1 &= ~(MCHP_GPIO_CTRL_PUD_MASK);
if (conf & BIT(MCHP_XEC_PU_POS)) {
pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
}
if (conf & BIT(MCHP_XEC_PD_POS)) {
pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
}
}
return pcr1;
}
/*
* DT enable booleans take precedence over disable booleans.
* We initially clear alternate output disable allowing us to set output state
* in the control register. Hardware sets output state bit in both control and
* parallel output register bits. Alternate output disable only controls which
* register bit is writable by the EC. We also clear the input pad disable
* bit because we need the input pin state and we don't know if the requested
* alternate function is input or bi-directional.
* Note 1: hardware allows input and output to be simultaneously enabled.
* Note 2: hardware interrupt detection is only on the input path.
*/
static int xec_config_pin(uint32_t portpin, uint32_t conf, uint32_t altf)
{
struct gpio_regs * const regs = (struct gpio_regs * const)DT_INST_REG_ADDR(0);
uint32_t port = MCHP_XEC_PINMUX_PORT(portpin);
uint32_t pin = (uint32_t)MCHP_XEC_PINMUX_PIN(portpin);
uint32_t idx = 0u, pcr1 = 0u;
if (port >= NUM_MCHP_GPIO_PORTS) {
return -EINVAL;
}
/* MCHP XEC family is 32 pins per port */
idx = (port * 32U) + pin;
config_drive_slew(regs, idx, conf);
/* Clear alternate output disable and input pad disable */
regs->CTRL[idx] &= ~(BIT(MCHP_GPIO_CTRL_AOD_POS) | BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS));
pcr1 = regs->CTRL[idx]; /* current configuration including pin input state */
pcr1 = regs->CTRL[idx]; /* read multiple times to allow propagation from pad */
pcr1 = regs->CTRL[idx]; /* Is this necessary? */
pcr1 = prog_pud(pcr1, conf);
/* Touch output enable. We always enable input */
if (conf & BIT(MCHP_XEC_OUT_DIS_POS)) {
pcr1 &= ~(MCHP_GPIO_CTRL_DIR_OUTPUT);
}
if (conf & BIT(MCHP_XEC_OUT_EN_POS)) {
pcr1 |= MCHP_GPIO_CTRL_DIR_OUTPUT;
}
/* Touch output state? Bit can be set even if the direction is input only */
if (conf & BIT(MCHP_XEC_OUT_LO_POS)) {
pcr1 &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
}
if (conf & BIT(MCHP_XEC_OUT_HI_POS)) {
pcr1 |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
}
/* Touch output buffer type? */
if (conf & BIT(MCHP_XEC_PUSH_PULL_POS)) {
pcr1 &= ~(MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
}
if (conf & BIT(MCHP_XEC_OPEN_DRAIN_POS)) {
pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
}
/* Always touch power gate */
pcr1 &= ~MCHP_GPIO_CTRL_PWRG_MASK;
if (conf & BIT(MCHP_XEC_PIN_LOW_POWER_POS)) {
pcr1 |= MCHP_GPIO_CTRL_PWRG_OFF;
} else {
pcr1 |= MCHP_GPIO_CTRL_PWRG_VTR_IO;
}
/* Always touch MUX (alternate function) */
pcr1 &= ~MCHP_GPIO_CTRL_MUX_MASK;
pcr1 |= (uint32_t)((altf & MCHP_GPIO_CTRL_MUX_MASK0) << MCHP_GPIO_CTRL_MUX_POS);
/* Always touch invert of alternate function. Need another bit to avoid touching */
if (conf & BIT(MCHP_XEC_FUNC_INV_POS)) {
pcr1 |= BIT(MCHP_GPIO_CTRL_POL_POS);
} else {
pcr1 &= ~BIT(MCHP_GPIO_CTRL_POL_POS);
}
/* output state set in control & parallel regs */
regs->CTRL[idx] = pcr1;
/* make output state in control read-only in control and read-write in parallel reg */
regs->CTRL[idx] = pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS);
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
uint32_t portpin, pinmux, func;
int ret;
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
pinmux = pins[i];
func = MCHP_XEC_PINMUX_FUNC(pinmux);
if (func >= MCHP_AFMAX) {
return -EINVAL;
}
portpin = MEC_XEC_PINMUX_PORT_PIN(pinmux);
ret = xec_config_pin(portpin, pinmux, func);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,708 |
```unknown
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
default y
help
Enable pin controller driver for NXP iMX series MCUs
config PINCTRL_IMX_SCU
bool "Pin controller driver for SCU-based i.MX SoCs"
depends on DT_HAS_NXP_IMX_IOMUXC_SCU_ENABLED
default y
help
Enable pin controller driver for SCU-based NXP i.MX SoCs.
# TODO: Find better place for this option
config MCUX_XBARA
bool "MCUX XBARA driver"
depends on HAS_MCUX_XBARA
help
Enable the MCUX XBARA driver.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.imx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 178 |
```unknown
menuconfig PINCTRL
bool "Pin controller drivers"
if PINCTRL
module = PINCTRL
module-str = PINCTRL
source "subsys/logging/Kconfig.template.log_config"
config PINCTRL_STORE_REG
bool
help
This option must be selected by drivers that require access to the device
register address. This can happen, for example, if certain pin control
actions are device dependent or require access to device specific
registers
config PINCTRL_NON_STATIC
bool
help
This option can be selected if the pin control configuration defined by
a driver has to be accessed externally. This can happen, for example, when
dynamic pin control is enabled or in testing environments.
config PINCTRL_DYNAMIC
bool "Dynamic configuration of pins"
select PINCTRL_NON_STATIC
help
When this option is enabled pin control configuration can be changed at
runtime. This can be useful, for example, to change the pins assigned to a
peripheral at early boot stages depending on a certain input.
source "drivers/pinctrl/Kconfig.b91"
source "drivers/pinctrl/Kconfig.ambiq"
source "drivers/pinctrl/Kconfig.gd32"
source "drivers/pinctrl/Kconfig.it8xxx2"
source "drivers/pinctrl/Kconfig.npcx"
source "drivers/pinctrl/Kconfig.numicro"
source "drivers/pinctrl/Kconfig.nrf"
source "drivers/pinctrl/Kconfig.rpi_pico"
source "drivers/pinctrl/Kconfig.sam"
source "drivers/pinctrl/Kconfig.sam0"
source "drivers/pinctrl/Kconfig.stm32"
source "drivers/pinctrl/Kconfig.kinetis"
source "drivers/pinctrl/Kconfig.xec"
source "drivers/pinctrl/Kconfig.imx"
source "drivers/pinctrl/Kconfig.sifive"
source "drivers/pinctrl/Kconfig.lpc_iocon"
source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
source "drivers/pinctrl/Kconfig.esp32"
source "drivers/pinctrl/Kconfig.rv32m1"
source "drivers/pinctrl/Kconfig.ifx_cat1"
source "drivers/pinctrl/Kconfig.xlnx"
source "drivers/pinctrl/Kconfig.xmc4xxx"
source "drivers/pinctrl/Kconfig.nxp_s32"
source "drivers/pinctrl/Kconfig.gecko"
source "drivers/pinctrl/Kconfig.ti_k3"
source "drivers/pinctrl/Kconfig.emsdp"
source "drivers/pinctrl/Kconfig.ti_cc32xx"
source "drivers/pinctrl/Kconfig.numaker"
source "drivers/pinctrl/Kconfig.eos_s3"
source "drivers/pinctrl/Kconfig.mci_io_mux"
source "drivers/pinctrl/Kconfig.ene"
source "drivers/pinctrl/Kconfig.zynqmp"
source "drivers/pinctrl/Kconfig.max32"
rsource "renesas/Kconfig"
endif # PINCTRL
``` | /content/code_sandbox/drivers/pinctrl/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 627 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pinctrl_xlnx_zynq, CONFIG_PINCTRL_LOG_LEVEL);
#define DT_DRV_COMPAT xlnx_pinctrl_zynq
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"Unsupported number of instances");
/* Relative SLCR register offsets for use in asserts */
#define MIO_PIN_53_OFFSET 0x00d4
#define SD0_WP_CD_SEL_OFFSET 0x0130
#define SD1_WP_CD_SEL_OFFSET 0x0134
static const struct device *const slcr = DEVICE_DT_GET(DT_INST_PHANDLE(0, syscon));
static mm_reg_t base = DT_INST_REG_ADDR(0);
K_SEM_DEFINE(pinctrl_lock, 1, 1);
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
uint16_t addr;
uint32_t val;
uint8_t i;
int err = 0;
ARG_UNUSED(reg);
if (!device_is_ready(slcr)) {
LOG_ERR("SLCR device not ready");
return -ENODEV;
}
/* Guard the read-modify-write operations */
k_sem_take(&pinctrl_lock, K_FOREVER);
for (i = 0; i < pin_cnt; i++) {
__ASSERT_NO_MSG(pins[i].offset <= MIO_PIN_53_OFFSET ||
pins[i].offset == SD0_WP_CD_SEL_OFFSET ||
pins[i].offset == SD1_WP_CD_SEL_OFFSET);
addr = base + pins[i].offset;
err = syscon_read_reg(slcr, addr, &val);
if (err != 0) {
LOG_ERR("failed to read SLCR addr 0x%04x (err %d)", addr, err);
break;
}
LOG_DBG("0x%04x: mask 0x%08x, val 0x%08x", addr, pins[i].mask, pins[i].val);
LOG_DBG("0x%04x r: 0x%08x", addr, val);
val &= ~(pins[i].mask);
val |= pins[i].val;
LOG_DBG("0x%04x w: 0x%08x", addr, val);
err = syscon_write_reg(slcr, addr, val);
if (err != 0) {
LOG_ERR("failed to write SLCR addr 0x%04x (err %d)", addr, err);
break;
}
}
k_sem_give(&pinctrl_lock);
return err;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_xlnx_zynq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 613 |
```c
/*
*
*/
#include "analog.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
#include <zephyr/init.h>
#define DT_DRV_COMPAT telink_b91_pinctrl
/**
* GPIO Function Enable Register
* ADDR PINS
* gpio_en: PORT_A[0-7]
* gpio_en + 1*8: PORT_B[0-7]
* gpio_en + 2*8: PORT_C[0-7]
* gpio_en + 3*8: PORT_D[0-7]
* gpio_en + 4*8: PORT_E[0-7]
* gpio_en + 5*8: PORT_F[0-7]
*/
#define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \
((pin >> 8) * 8)))
/**
* Function Multiplexer Register
* ADDR PINS
* pin_mux: PORT_A[0-3]
* pin_mux + 1: PORT_A[4-7]
* pin_mux + 2: PORT_B[0-3]
* pin_mux + 3: PORT_B[4-7]
* pin_mux + 4: PORT_C[0-3]
* pin_mux + 5: PORT_C[4-7]
* pin_mux + 6: PORT_D[0-3]
* pin_mux + 7: PORT_D[4-7]
* pin_mux + 0x20: PORT_E[0-3]
* pin_mux + 0x21: PORT_E[4-7]
* pin_mux + 0x26: PORT_F[0-3]
* pin_mux + 0x27: PORT_F[4-7]
*/
#define reg_pin_mux(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, pin_mux) + \
(((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
(((pin >> 8) == 4) ? 0x20 : 0) + \
(((pin >> 8) == 5) ? 0x26 : 0) + \
((pin & 0x0f0) ? 1 : 0)))
/**
* Pull Up resistors enable
* ADDR PINS
* pull_up_en: PORT_A[0-3]
* pull_up_en + 1: PORT_A[4-7]
* pull_up_en + 2: PORT_B[0-3]
* pull_up_en + 3: PORT_B[4-7]
* pull_up_en + 4: PORT_C[0-3]
* pull_up_en + 5: PORT_C[4-7]
* pull_up_en + 6: PORT_D[0-3]
* pull_up_en + 7: PORT_D[4-7]
* pull_up_en + 8: PORT_E[0-3]
* pull_up_en + 9: PORT_E[4-7]
* pull_up_en + 10: PORT_F[0-3]
* pull_up_en + 11: PORT_F[4-7]
*/
#define reg_pull_up_en(pin) ((uint8_t)(DT_INST_REG_ADDR_BY_NAME(0, pull_up_en) + \
((pin >> 8) * 2) + \
((pin & 0xf0) ? 1 : 0)))
/* Pinctrl driver initialization */
static int pinctrl_b91_init(void)
{
/* set pad_mul_sel register value from dts */
reg_gpio_pad_mul_sel |= DT_INST_PROP(0, pad_mul_sel);
return 0;
}
SYS_INIT(pinctrl_b91_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
/* Act as GPIO function disable */
static inline void pinctrl_b91_gpio_function_disable(uint32_t pin)
{
uint8_t bit = pin & 0xff;
reg_gpio_en(pin) &= ~bit;
}
/* Get function value bits start position (offset) */
static inline int pinctrl_b91_get_offset(uint32_t pin, uint8_t *offset)
{
switch (B91_PINMUX_GET_PIN_ID(pin)) {
case B91_PIN_0:
*offset = B91_PIN_0_FUNC_POS;
break;
case B91_PIN_1:
*offset = B91_PIN_1_FUNC_POS;
break;
case B91_PIN_2:
*offset = B91_PIN_2_FUNC_POS;
break;
case B91_PIN_3:
*offset = B91_PIN_3_FUNC_POS;
break;
case B91_PIN_4:
*offset = B91_PIN_4_FUNC_POS;
break;
case B91_PIN_5:
*offset = B91_PIN_5_FUNC_POS;
break;
case B91_PIN_6:
*offset = B91_PIN_6_FUNC_POS;
break;
case B91_PIN_7:
*offset = B91_PIN_7_FUNC_POS;
break;
default:
return -EINVAL;
}
return 0;
}
/* Set pin's function */
static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pinctrl)
{
int status;
uint8_t mask;
uint8_t offset = 0;
uint8_t pull = B91_PINMUX_GET_PULL(*pinctrl);
uint8_t func = B91_PINMUX_GET_FUNC(*pinctrl);
uint32_t pin = B91_PINMUX_GET_PIN(*pinctrl);
uint8_t pull_up_en_addr = reg_pull_up_en(pin);
/* calculate offset and mask for the func and pull values */
status = pinctrl_b91_get_offset(pin, &offset);
if (status != 0) {
return status;
}
mask = (uint8_t) ~(BIT(offset) | BIT(offset + 1));
/* disable GPIO function (can be enabled back by GPIO init using GPIO driver) */
pinctrl_b91_gpio_function_disable(pin);
/* set func value */
func = func << offset;
reg_pin_mux(pin) = (reg_pin_mux(pin) & mask) | func;
/* set pull value */
pull = pull << offset;
analog_write_reg8(pull_up_en_addr, (analog_read_reg8(pull_up_en_addr) & mask) | pull);
return status;
}
/* API implementation: configure_pins */
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
int status = 0;
for (uint8_t i = 0; i < pin_cnt; i++) {
status = pinctrl_configure_pin(pins++);
if (status < 0) {
break;
}
}
return status;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_b91.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,562 |
```c
/*
*
*/
#include <assert.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/* Driver config */
struct npcx_pinctrl_config {
/* Device base address used for pinctrl driver */
uintptr_t base_scfg;
uintptr_t base_glue;
};
static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
.base_scfg = NPCX_SCFG_REG_ADDR,
.base_glue = NPCX_GLUE_REG_ADDR,
};
/* PWM pinctrl config */
struct npcx_pwm_pinctrl_config {
uintptr_t base;
int channel;
};
#define NPCX_PWM_PINCTRL_CFG_INIT(node_id) \
{ \
.base = DT_REG_ADDR(node_id), \
.channel = DT_PROP(node_id, pwm_channel), \
},
static const struct npcx_pwm_pinctrl_config pwm_pinctrl_cfg[] = {
DT_FOREACH_STATUS_OKAY(nuvoton_npcx_pwm, NPCX_PWM_PINCTRL_CFG_INIT)
};
/* Pin-control local functions for peripheral devices */
static bool npcx_periph_pinmux_has_lock(int group)
{
if ((BIT(group) & NPCX_DEVALT_LK_GROUP_MASK) != 0) {
return true;
}
return false;
}
static void npcx_periph_pinmux_configure(const struct npcx_periph *alt, bool is_alternate,
bool is_locked)
{
const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
uint8_t alt_mask = BIT(alt->bit);
/*
* is_alternate == 0 means select GPIO, otherwise Alternate Func.
* inverted == 0:
* Set devalt bit to select Alternate Func.
* inverted == 1:
* Clear devalt bit to select Alternate Func.
*/
if (is_alternate != alt->inverted) {
NPCX_DEVALT(scfg_base, alt->group) |= alt_mask;
} else {
NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;
}
if (is_locked && npcx_periph_pinmux_has_lock(alt->group)) {
NPCX_DEVALT_LK(scfg_base, alt->group) |= alt_mask;
}
}
static void npcx_periph_pupd_configure(const struct npcx_periph *pupd,
enum npcx_io_bias_type type)
{
const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
if (type == NPCX_BIAS_TYPE_NONE) {
NPCX_PUPD_EN(scfg_base, pupd->group) &= ~BIT(pupd->bit);
} else {
NPCX_PUPD_EN(scfg_base, pupd->group) |= BIT(pupd->bit);
}
}
static void npcx_periph_pwm_drive_mode_configure(const struct npcx_periph *periph,
bool is_od)
{
uintptr_t reg = 0;
/* Find selected pwm module which enables open-drain prop. */
for (int i = 0; i < ARRAY_SIZE(pwm_pinctrl_cfg); i++) {
if (periph->group == pwm_pinctrl_cfg[i].channel) {
reg = pwm_pinctrl_cfg[i].base;
break;
}
}
if (reg == 0) {
return;
}
struct pwm_reg *const inst = (struct pwm_reg *)(reg);
if (is_od) {
inst->PWMCTLEX |= BIT(NPCX_PWMCTLEX_OD_OUT);
} else {
inst->PWMCTLEX &= ~BIT(NPCX_PWMCTLEX_OD_OUT);
}
}
static void npcx_periph_configure(const pinctrl_soc_pin_t *pin, uintptr_t reg)
{
if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PINMUX) {
/* Configure peripheral device's pinmux functionality */
npcx_periph_pinmux_configure(&pin->cfg.periph,
!pin->flags.pinmux_gpio,
pin->flags.pinmux_lock);
} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_PUPD) {
/* Configure peripheral device's internal PU/PD */
npcx_periph_pupd_configure(&pin->cfg.periph,
pin->flags.io_bias_type);
} else if (pin->cfg.periph.type == NPCX_PINCTRL_TYPE_PERIPH_DRIVE) {
/* Configure peripheral device's drive mode. (Only PWM pads support it) */
npcx_periph_pwm_drive_mode_configure(&pin->cfg.periph,
pin->flags.io_drive_type == NPCX_DRIVE_TYPE_OPEN_DRAIN);
}
}
static void npcx_psl_input_detection_configure(const pinctrl_soc_pin_t *pin)
{
struct glue_reg *inst_glue = (struct glue_reg *)(npcx_pinctrl_cfg.base_glue);
const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
const struct npcx_psl_input *psl_in = (const struct npcx_psl_input *)&pin->cfg.psl_in;
/* Configure detection polarity of PSL input pads */
if (pin->flags.psl_in_polarity == NPCX_PSL_IN_POL_HIGH) {
NPCX_DEVALT(scfg_base, psl_in->pol_group) |= BIT(psl_in->pol_bit);
} else {
NPCX_DEVALT(scfg_base, psl_in->pol_group) &= ~BIT(psl_in->pol_bit);
}
/* Configure detection mode of PSL input pads */
if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) {
inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(psl_in->port);
} else {
inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(psl_in->port);
}
}
static void npcx_device_control_configure(const pinctrl_soc_pin_t *pin)
{
const struct npcx_dev_ctl *ctrl = (const struct npcx_dev_ctl *)&pin->cfg.dev_ctl;
const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
SET_FIELD(NPCX_DEV_CTL(scfg_base, ctrl->offest),
FIELD(ctrl->field_offset, ctrl->field_size),
ctrl->field_value);
}
/* Pinctrl API implementation */
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
ARG_UNUSED(reg);
/* Configure all peripheral devices' properties here. */
for (uint8_t i = 0; i < pin_cnt; i++) {
if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PERIPH) {
/* Configure peripheral device's pinmux functionality */
npcx_periph_configure(&pins[i], reg);
} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_DEVICE_CTRL) {
/* Configure device's io characteristics */
npcx_device_control_configure(&pins[i]);
} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PSL_IN) {
/* Configure SPL input's detection mode */
npcx_psl_input_detection_configure(&pins[i]);
} else {
return -ENOTSUP;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_npcx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,590 |
```c
/*
*/
#define DT_DRV_COMPAT ti_cc32xx_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
#define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU
/* pin to pad mapping (255 indicates invalid pin) */
static const uint8_t pin2pad[] = {
10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 255U, 255U, 18U, 19U, 20U,
21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
255U, 255U, 26U, 27U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U,
255U, 255U, 255U, 255U, 255U, 31U, 255U, 255U, 255U, 255U, 0U, 255U, 32U,
30U, 255U, 1U, 255U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
};
static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg)
{
uint8_t pin;
pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK;
if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) {
return -EINVAL;
}
sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U));
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
for (uint8_t i = 0U; i < pin_cnt; i++) {
int ret;
ret = pinctrl_configure_pin(pins[i]);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_ti_cc32xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 596 |
```c
/*
*
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
static MCI_IO_MUX_Type *mci_iomux =
(MCI_IO_MUX_Type *)DT_REG_ADDR(DT_NODELABEL(pinctrl));
static SOCCIU_Type *soc_ctrl =
(SOCCIU_Type *)DT_REG_ADDR(DT_NODELABEL(soc_ctrl));
static AON_SOC_CIU_Type *aon_soc_ciu =
(AON_SOC_CIU_Type *)DT_REG_ADDR(DT_NODELABEL(aon_soc_ctrl));
/*
* GPIO mux option definitions. Stored as a static array, because
* these mux options are needed to clear pin mux settings to
* a known good state before selecting a new alternate function.
*/
static uint64_t gpio_muxes[] = {IOMUX_GPIO_OPS};
/*
* Helper function to handle setting pin properties,
* such as pin bias and slew rate
*/
static void configure_pin_props(uint32_t pin_mux, uint8_t gpio_idx)
{
uint32_t mask, set;
volatile uint32_t *pull_reg = &soc_ctrl->PAD_PU_PD_EN0;
volatile uint32_t *slew_reg = &soc_ctrl->SR_CONFIG0;
volatile uint32_t *sleep_force_en = &soc_ctrl->PAD_SLP_EN0;
volatile uint32_t *sleep_force_val = &soc_ctrl->PAD_SLP_VAL0;
/* GPIO 22-27 use always on configuration registers */
if (gpio_idx > 21 && gpio_idx < 28) {
pull_reg = (&aon_soc_ciu->PAD_PU_PD_EN1 - 1);
slew_reg = (&aon_soc_ciu->SR_CONFIG1 - 1);
sleep_force_en = &aon_soc_ciu->PAD_SLP_EN0;
sleep_force_val = &aon_soc_ciu->PAD_SLP_VAL0;
}
/* Calculate register offset for pull and slew regs.
* Use bit shifting as opposed to division
*/
pull_reg += (gpio_idx >> 4);
slew_reg += (gpio_idx >> 4);
sleep_force_en += (gpio_idx >> 5);
sleep_force_val += (gpio_idx >> 5);
/* Set pull-up/pull-down */
/* Use mask and bitshift here as opposed to modulo and multiplication.
* equivalent to ((gpio_idx % 16) * 2)
*/
mask = 0x3 << ((gpio_idx & 0xF) << 1);
set = IOMUX_PAD_GET_PULL(pin_mux) << ((gpio_idx & 0xF) << 1);
*pull_reg = (*pull_reg & ~mask) | set;
/* Set slew rate */
set = IOMUX_PAD_GET_SLEW(pin_mux) << ((gpio_idx & 0xF) << 1);
*slew_reg = (*slew_reg & ~mask) | set;
/* Set sleep force enable bit */
mask = (0x1 << (gpio_idx & 0x1F));
set = (IOMUX_PAD_GET_SLEEP_FORCE_EN(pin_mux) << (gpio_idx & 0x1F));
*sleep_force_en = (*sleep_force_en & ~mask) | set;
set = (IOMUX_PAD_GET_SLEEP_FORCE_VAL(pin_mux) << (gpio_idx & 0x1F));
*sleep_force_val = (*sleep_force_val & ~mask) | set;
}
static void select_gpio_mode(uint8_t gpio_idx)
{
uint64_t gpio_setting = gpio_muxes[gpio_idx];
volatile uint32_t *flexcomm_reg = &mci_iomux->FC0;
/* Clear flexcomm settings */
flexcomm_reg += IOMUX_GET_FLEXCOMM_CLR_IDX(gpio_setting);
*flexcomm_reg &= ~IOMUX_GET_FLEXCOMM_CLR_MASK(gpio_setting);
/* Clear fsel settings */
mci_iomux->FSEL &= ~IOMUX_GET_FSEL_CLR_MASK(gpio_setting);
/* Clear CTimer in/out, if required */
if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) {
mci_iomux->C_TIMER_IN &=
~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting));
mci_iomux->C_TIMER_OUT &=
~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting));
}
/* Clear SCTimer in/out, if required */
if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) {
mci_iomux->SC_TIMER &=
~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting));
}
if (IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(gpio_setting)) {
mci_iomux->SC_TIMER &=
~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16));
}
/* Clear security gpio enable */
mci_iomux->S_GPIO &= ~(0x1 << (gpio_idx - 32));
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
volatile uint32_t *flexcomm_reg;
volatile uint32_t *iomux_en_reg;
for (uint8_t i = 0; i < pin_cnt; i++) {
flexcomm_reg = &mci_iomux->FC0;
iomux_en_reg = &soc_ctrl->MCI_IOMUX_EN0;
uint32_t pin_mux = pins[i];
uint8_t gpio_idx = IOMUX_GET_GPIO_IDX(pin_mux);
uint8_t type = IOMUX_GET_TYPE(pin_mux);
/*
* Before selecting an alternate function, we must clear any
* conflicting pin configuration. We do this by resetting the
* pin to a gpio configuration, then selecting the alternate
* function.
*/
select_gpio_mode(gpio_idx);
switch (type) {
case IOMUX_FLEXCOMM:
flexcomm_reg += IOMUX_GET_FLEXCOMM_IDX(pin_mux);
*flexcomm_reg |=
(0x1 << IOMUX_GET_FLEXCOMM_BIT(pin_mux));
break;
case IOMUX_FSEL:
mci_iomux->FSEL |=
(0x1 << IOMUX_GET_FSEL_BIT(pin_mux));
break;
case IOMUX_CTIMER_IN:
mci_iomux->C_TIMER_IN |=
(0x1 << IOMUX_GET_CTIMER_BIT(pin_mux));
break;
case IOMUX_CTIMER_OUT:
mci_iomux->C_TIMER_OUT |=
(0x1 << IOMUX_GET_CTIMER_BIT(pin_mux));
break;
case IOMUX_SCTIMER_IN:
mci_iomux->SC_TIMER |=
(0x1 << IOMUX_GET_SCTIMER_BIT(pin_mux));
break;
case IOMUX_SCTIMER_OUT:
mci_iomux->SC_TIMER |=
(0x1 << (IOMUX_GET_SCTIMER_BIT(pin_mux) + 16));
break;
case IOMUX_SGPIO:
mci_iomux->S_GPIO |= (0x1 << (gpio_idx - 32));
break;
case IOMUX_GPIO:
if (gpio_idx > 32) {
mci_iomux->GPIO_GRP1 |= (0x1 << (gpio_idx - 32));
} else {
mci_iomux->GPIO_GRP0 |= (0x1 << gpio_idx);
}
break;
case IOMUX_AON:
/* No selection bits should be set */
break;
default:
/* Unsupported type passed */
return -ENOTSUP;
}
configure_pin_props(pin_mux, gpio_idx);
/* Now, enable pin controller access to this pin */
if (gpio_idx > 21 && gpio_idx < 28) {
/* GPIO 22-27 use always on soc controller */
iomux_en_reg = &aon_soc_ciu->MCI_IOMUX_EN0;
}
iomux_en_reg += (gpio_idx >> 5);
*iomux_en_reg |= (0x1 << (gpio_idx & 0x1F));
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_mci_io_mux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,777 |
```c
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <zephyr/logging/log.h>
#include "pinctrl_soc.h"
LOG_MODULE_REGISTER(pinctrl_xlnx_zynqmp, CONFIG_PINCTRL_LOG_LEVEL);
#define DT_DRV_COMPAT xlnx_pinctrl_zynqmp
static mm_reg_t base = DT_INST_REG_ADDR(0);
static uint8_t mio_pin_offset = 0x04;
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
for (uint8_t i = 0U; i < pin_cnt; i++) {
uint32_t sel = 0;
switch (pins[i].func) {
case UART_FUNCTION: {
sel = UARTX_SEL;
break;
}
default: {
LOG_ERR("Unsupported function enum was selected");
break;
}
}
sys_write32(sel, base + mio_pin_offset * pins[i].pin);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_xlnx_zynqmp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```unknown
# Infineon CAT1 Pin controller configuration options
# an affiliate of Cypress Semiconductor Corporation
config PINCTRL_INFINEON_CAT1
bool "Pin controller driver for Infineon CAT1 MCUs"
default y
depends on DT_HAS_INFINEON_CAT1_PINCTRL_ENABLED
help
Enable Pin controller driver for Infineon CAT1 MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.ifx_cat1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```c
/*
*
*/
#define DT_DRV_COMPAT snps_emsdp_pinctrl
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/emsdp-pinctrl.h>
/**
* Mux Control Register Index
*/
#define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0 */
#define ARDUINO_MUX_CTRL 4 /*!< 32-bits, offset 0x4 */
#define EMSDP_CREG_BASE DT_INST_REG_ADDR(0)
#define EMSDP_CREG_PMOD_MUX_OFFSET (0x0030)
#define MUX_SEL0_OFFSET (0)
#define MUX_SEL1_OFFSET (4)
#define MUX_SEL2_OFFSET (8)
#define MUX_SEL3_OFFSET (12)
#define MUX_SEL4_OFFSET (16)
#define MUX_SEL5_OFFSET (20)
#define MUX_SEL6_OFFSET (24)
#define MUX_SEL7_OFFSET (28)
#define MUX_SEL0_MASK (0xf << MUX_SEL0_OFFSET)
#define MUX_SEL1_MASK (0xf << MUX_SEL1_OFFSET)
#define MUX_SEL2_MASK (0xf << MUX_SEL2_OFFSET)
#define MUX_SEL3_MASK (0xf << MUX_SEL3_OFFSET)
#define MUX_SEL4_MASK (0xf << MUX_SEL4_OFFSET)
#define MUX_SEL5_MASK (0xf << MUX_SEL5_OFFSET)
#define MUX_SEL6_MASK (0xf << MUX_SEL6_OFFSET)
#define MUX_SEL7_MASK (0xf << MUX_SEL7_OFFSET)
/**
* PMOD A Multiplexor
*/
#define PM_A_CFG0_GPIO ((0) << MUX_SEL0_OFFSET)
#define PM_A_CFG0_I2C ((1) << MUX_SEL0_OFFSET) /* io_i2c_mst2 */
#define PM_A_CFG0_SPI ((2) << MUX_SEL0_OFFSET) /* io_spi_mst1, cs_0 */
#define PM_A_CFG0_UART1a ((3) << MUX_SEL0_OFFSET) /* io_uart1 */
#define PM_A_CFG0_UART1b ((4) << MUX_SEL0_OFFSET) /* io_uart1 */
#define PM_A_CFG0_PWM1 ((5) << MUX_SEL0_OFFSET)
#define PM_A_CFG0_PWM2 ((6) << MUX_SEL0_OFFSET)
#define PM_A_CFG1_GPIO ((0) << MUX_SEL1_OFFSET)
/**
* PMOD B Multiplexor
*/
#define PM_B_CFG0_GPIO ((0) << MUX_SEL2_OFFSET)
#define PM_B_CFG0_I2C ((1) << MUX_SEL2_OFFSET) /* io_i2c_mst2 */
#define PM_B_CFG0_SPI ((2) << MUX_SEL2_OFFSET) /* io_spi_mst1, cs_1 */
#define PM_B_CFG0_UART2a ((3) << MUX_SEL2_OFFSET) /* io_uart2 */
#define PM_B_CFG0_UART2b ((4) << MUX_SEL2_OFFSET) /* io_uart2 */
#define PM_B_CFG0_PWM1 ((5) << MUX_SEL2_OFFSET)
#define PM_B_CFG0_PWM2 ((6) << MUX_SEL2_OFFSET)
#define PM_B_CFG1_GPIO ((0) << MUX_SEL3_OFFSET)
/**
* PMOD C Multiplexor
*/
#define PM_C_CFG0_GPIO ((0) << MUX_SEL4_OFFSET)
#define PM_C_CFG0_I2C ((1) << MUX_SEL4_OFFSET) /* io_i2c_mst2 */
#define PM_C_CFG0_SPI ((2) << MUX_SEL4_OFFSET) /* io_spi_mst1, cs_2 */
#define PM_C_CFG0_UART3a ((3) << MUX_SEL4_OFFSET) /* io_uart3 */
#define PM_C_CFG0_UART3b ((4) << MUX_SEL4_OFFSET) /* io_uart3 */
#define PM_C_CFG0_PWM1 ((5) << MUX_SEL4_OFFSET)
#define PM_C_CFG0_PWM2 ((6) << MUX_SEL4_OFFSET)
#define PM_C_CFG1_GPIO ((0) << MUX_SEL5_OFFSET)
/**
* Arduino Multiplexor
*/
#define ARDUINO_CFG0_GPIO ((0) << MUX_SEL0_OFFSET)
#define ARDUINO_CFG0_UART ((1) << MUX_SEL0_OFFSET) /* io_uart0 */
#define ARDUINO_CFG1_GPIO ((0) << MUX_SEL1_OFFSET)
#define ARDUINO_CFG1_PWM ((1) << MUX_SEL1_OFFSET)
#define ARDUINO_CFG2_GPIO ((0) << MUX_SEL2_OFFSET)
#define ARDUINO_CFG2_PWM ((1) << MUX_SEL2_OFFSET)
#define ARDUINO_CFG3_GPIO ((0) << MUX_SEL3_OFFSET)
#define ARDUINO_CFG3_PWM ((1) << MUX_SEL3_OFFSET)
#define ARDUINO_CFG4_GPIO ((0) << MUX_SEL4_OFFSET)
#define ARDUINO_CFG4_PWM ((1) << MUX_SEL4_OFFSET)
#define ARDUINO_CFG5_GPIO ((0) << MUX_SEL5_OFFSET)
#define ARDUINO_CFG5_SPI ((1) << MUX_SEL5_OFFSET) /* io_spi_mst0, cs_0 */
#define ARDUINO_CFG5_PWM1 ((2) << MUX_SEL5_OFFSET)
#define ARDUINO_CFG5_PWM2 ((3) << MUX_SEL5_OFFSET)
#define ARDUINO_CFG5_PWM3 ((4) << MUX_SEL5_OFFSET)
#define ARDUINO_CFG6_GPIO ((0) << MUX_SEL6_OFFSET)
#define ARDUINO_CFG6_I2C ((1) << MUX_SEL6_OFFSET) /* io_i2c_mst1 */
static int pinctrl_emsdp_set(uint32_t pin, uint32_t type)
{
const uint32_t mux_regs = (EMSDP_CREG_BASE + EMSDP_CREG_PMOD_MUX_OFFSET);
uint32_t reg;
if (pin == UNMUXED_PIN) {
return 0;
}
if (pin <= PMOD_C) {
reg = sys_read32(mux_regs + PMOD_MUX_CTRL);
} else {
reg = sys_read32(mux_regs + ARDUINO_MUX_CTRL);
}
switch (pin) {
case PMOD_A:
reg &= ~(MUX_SEL0_MASK);
switch (type) {
case PMOD_GPIO:
reg |= PM_A_CFG0_GPIO;
break;
case PMOD_UARTA:
reg |= PM_A_CFG0_UART1a;
break;
case PMOD_UARTB:
reg |= PM_A_CFG0_UART1b;
break;
case PMOD_SPI:
reg |= PM_A_CFG0_SPI;
break;
case PMOD_I2C:
reg |= PM_A_CFG0_I2C;
break;
case PMOD_PWM_MODE1:
reg |= PM_A_CFG0_PWM1;
break;
case PMOD_PWM_MODE2:
reg |= PM_A_CFG0_PWM2;
break;
default:
break;
}
break;
case PMOD_B:
reg &= ~(MUX_SEL2_MASK);
switch (type) {
case PMOD_GPIO:
reg |= PM_B_CFG0_GPIO;
break;
case PMOD_UARTA:
reg |= PM_B_CFG0_UART2a;
break;
case PMOD_UARTB:
reg |= PM_A_CFG0_UART1b;
break;
case PMOD_SPI:
reg |= PM_B_CFG0_SPI;
break;
case PMOD_I2C:
reg |= PM_B_CFG0_I2C;
break;
case PMOD_PWM_MODE1:
reg |= PM_B_CFG0_PWM1;
break;
case PMOD_PWM_MODE2:
reg |= PM_B_CFG0_PWM2;
break;
default:
break;
}
break;
case PMOD_C:
reg &= ~(MUX_SEL4_MASK);
switch (type) {
case PMOD_GPIO:
reg |= PM_C_CFG0_GPIO;
break;
case PMOD_UARTA:
reg |= PM_C_CFG0_UART3a;
break;
case PMOD_UARTB:
reg |= PM_C_CFG0_UART3b;
break;
case PMOD_SPI:
reg |= PM_C_CFG0_SPI;
break;
case PMOD_I2C:
reg |= PM_C_CFG0_I2C;
break;
case PMOD_PWM_MODE1:
reg |= PM_C_CFG0_PWM1;
break;
case PMOD_PWM_MODE2:
reg |= PM_C_CFG0_PWM2;
break;
default:
break;
}
break;
case ARDUINO_PIN_0:
case ARDUINO_PIN_1:
reg &= ~MUX_SEL0_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG0_GPIO;
} else if (type == ARDUINO_UART) {
reg |= ARDUINO_CFG0_UART;
}
break;
case ARDUINO_PIN_2:
case ARDUINO_PIN_3:
reg &= ~MUX_SEL1_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG1_GPIO;
} else if (type == ARDUINO_PWM) {
reg |= ARDUINO_CFG1_PWM;
}
break;
case ARDUINO_PIN_4:
case ARDUINO_PIN_5:
reg &= ~MUX_SEL2_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG2_GPIO;
} else if (type == ARDUINO_PWM) {
reg |= ARDUINO_CFG2_PWM;
}
break;
case ARDUINO_PIN_6:
case ARDUINO_PIN_7:
reg &= ~MUX_SEL3_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG3_GPIO;
} else if (type == ARDUINO_PWM) {
reg |= ARDUINO_CFG3_PWM;
}
break;
case ARDUINO_PIN_8:
case ARDUINO_PIN_9:
reg &= ~MUX_SEL4_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG4_GPIO;
} else if (type == ARDUINO_PWM) {
reg |= ARDUINO_CFG4_PWM;
}
break;
case ARDUINO_PIN_10:
case ARDUINO_PIN_11:
case ARDUINO_PIN_12:
case ARDUINO_PIN_13:
reg &= ~MUX_SEL5_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG5_GPIO;
} else if (type == ARDUINO_SPI) {
reg |= ARDUINO_CFG5_SPI;
} else if (type == ARDUINO_PWM) {
reg |= ARDUINO_CFG5_PWM1;
}
break;
case ARDUINO_PIN_AD4:
case ARDUINO_PIN_AD5:
reg &= ~MUX_SEL6_MASK;
if (type == ARDUINO_GPIO) {
reg |= ARDUINO_CFG6_GPIO;
} else if (type == ARDUINO_I2C) {
reg |= ARDUINO_CFG6_I2C;
}
break;
default:
break;
}
if (pin <= PMOD_C) {
sys_write32(reg, mux_regs + PMOD_MUX_CTRL);
} else {
sys_write32(reg, mux_regs + ARDUINO_MUX_CTRL);
}
return 0;
}
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
ARG_UNUSED(reg);
int i;
for (i = 0; i < pin_cnt; i++) {
pinctrl_emsdp_set(pins[i].pin, pins[i].type);
}
return 0;
}
``` | /content/code_sandbox/drivers/pinctrl/pinctrl_emsdp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,569 |
```unknown
config PINCTRL_XMC4XXX
bool "XMC4XXX pin controller driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_PINCTRL_ENABLED
help
Enables XMC4XXX pin controller driver.
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config PINCTRL_ENE_KB1200
bool "ENE KB1200 Pin controller driver"
default y
depends on DT_HAS_ENE_KB1200_PINCTRL_ENABLED
help
Enable pin controller driver for ENE KB1200 MCUs
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.ene | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config PINCTRL_SAM0
bool "Atmel SAM0 pin controller driver"
default y
depends on DT_HAS_ATMEL_SAM0_PINCTRL_ENABLED
help
Atmel pin controller driver is used on SAM0 SoC series
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config PINCTRL_TELINK_B91
bool "Telink B91 pin controller driver"
default y
depends on DT_HAS_TELINK_B91_PINCTRL_ENABLED
help
Enables Telink B91 pin controller driver
``` | /content/code_sandbox/drivers/pinctrl/Kconfig.b91 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
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