text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
config REGULATOR_NPM1300
bool "nPM1300 PMIC regulator driver"
default y
depends on DT_HAS_NORDIC_NPM1300_REGULATOR_ENABLED
select I2C
select MFD
help
Enable the Nordic nPM1300 PMIC regulator driver
if REGULATOR_NPM1300
config REGULATOR_NPM1300_COMMON_INIT_PRIORITY
int "nPM1300 regulator driver init priority (common part)"
default 85
help
Init priority for the Nordic nPM1300 regulator driver (common part).
It must be greater than I2C init priority.
config REGULATOR_NPM1300_INIT_PRIORITY
int "nPM1300 regulator driver init priority"
default 86
help
Init priority for the Nordic nPM1300 regulator driver. It must be
greater than REGULATOR_NPM1300_COMMON_INIT_PRIORITY.
endif
``` | /content/code_sandbox/drivers/regulator/Kconfig.npm1300 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```c
/*
*/
#define DT_DRV_COMPAT nxp_vref
#include <errno.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/dt-bindings/regulator/nxp_vref.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/linear_range.h>
#include <zephyr/sys/util.h>
#include <fsl_device_registers.h>
static const struct linear_range utrim_range = LINEAR_RANGE_INIT(1000000, 100000U, 0x0U, 0xBU);
struct regulator_nxp_vref_data {
struct regulator_common_data common;
};
struct regulator_nxp_vref_config {
struct regulator_common_config common;
VREF_Type *base;
uint16_t buf_start_delay;
uint16_t bg_start_time;
};
static int regulator_nxp_vref_enable(const struct device *dev)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
volatile uint32_t *const csr = &base->CSR;
*csr |= VREF_CSR_LPBGEN_MASK | VREF_CSR_LPBG_BUF_EN_MASK;
/* Wait for bandgap startup */
k_busy_wait(config->bg_start_time);
/* Enable high accuracy bandgap */
*csr |= VREF_CSR_HCBGEN_MASK;
/* Monitor until stable */
while (!(*csr & VREF_CSR_VREFST_MASK)) {
;
}
/* Enable output buffer */
*csr |= VREF_CSR_BUF21EN_MASK;
return 0;
}
static int regulator_nxp_vref_disable(const struct device *dev)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
/*
* Disable HC Bandgap, LP Bandgap, and Buf21
* to achieve "Off" mode of VREF
*/
base->CSR &= ~(VREF_CSR_BUF21EN_MASK | VREF_CSR_HCBGEN_MASK | VREF_CSR_LPBGEN_MASK);
return 0;
}
static int regulator_nxp_vref_set_mode(const struct device *dev, regulator_mode_t mode)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
uint32_t csr = base->CSR;
if (mode == NXP_VREF_MODE_STANDBY) {
csr &= ~VREF_CSR_REGEN_MASK &
~VREF_CSR_CHOPEN_MASK &
~VREF_CSR_HI_PWR_LV_MASK &
~VREF_CSR_BUF21EN_MASK;
} else if (mode == NXP_VREF_MODE_LOW_POWER) {
csr &= ~VREF_CSR_REGEN_MASK &
~VREF_CSR_CHOPEN_MASK &
~VREF_CSR_HI_PWR_LV_MASK;
csr |= VREF_CSR_BUF21EN_MASK;
} else if (mode == NXP_VREF_MODE_HIGH_POWER) {
csr &= ~VREF_CSR_REGEN_MASK &
~VREF_CSR_CHOPEN_MASK;
csr |= VREF_CSR_HI_PWR_LV_MASK &
VREF_CSR_BUF21EN_MASK;
} else if (mode == NXP_VREF_MODE_INTERNAL_REGULATOR) {
csr |= VREF_CSR_REGEN_MASK &
VREF_CSR_CHOPEN_MASK &
VREF_CSR_HI_PWR_LV_MASK &
VREF_CSR_BUF21EN_MASK;
} else {
return -EINVAL;
}
base->CSR = csr;
k_busy_wait(config->buf_start_delay);
return 0;
}
static int regulator_nxp_vref_get_mode(const struct device *dev, regulator_mode_t *mode)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
uint32_t csr = base->CSR;
/* Check bits to determine mode */
if (csr & VREF_CSR_REGEN_MASK) {
*mode = NXP_VREF_MODE_INTERNAL_REGULATOR;
} else if (csr & VREF_CSR_HI_PWR_LV_MASK) {
*mode = NXP_VREF_MODE_HIGH_POWER;
} else if (csr & VREF_CSR_BUF21EN_MASK) {
*mode = NXP_VREF_MODE_LOW_POWER;
} else {
*mode = NXP_VREF_MODE_STANDBY;
}
return 0;
}
static inline unsigned int regulator_nxp_vref_count_voltages(const struct device *dev)
{
return linear_range_values_count(&utrim_range);
}
static int regulator_nxp_vref_list_voltage(const struct device *dev,
unsigned int idx, int32_t *volt_uv)
{
return linear_range_get_value(&utrim_range, idx, volt_uv);
}
static int regulator_nxp_vref_set_voltage(const struct device *dev,
int32_t min_uv, int32_t max_uv)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
uint16_t idx;
int ret;
ret = linear_range_get_win_index(&utrim_range, min_uv, max_uv, &idx);
if (ret < 0) {
return ret;
}
base->UTRIM &= ~VREF_UTRIM_TRIM2V1_MASK;
base->UTRIM |= VREF_UTRIM_TRIM2V1_MASK & idx;
return 0;
}
static int regulator_nxp_vref_get_voltage(const struct device *dev,
int32_t *volt_uv)
{
const struct regulator_nxp_vref_config *config = dev->config;
VREF_Type *const base = config->base;
uint16_t idx;
int ret;
/* Linear range index is the register value */
idx = (base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT;
ret = linear_range_get_value(&utrim_range, idx, volt_uv);
return ret;
}
static const struct regulator_driver_api api = {
.enable = regulator_nxp_vref_enable,
.disable = regulator_nxp_vref_disable,
.set_mode = regulator_nxp_vref_set_mode,
.get_mode = regulator_nxp_vref_get_mode,
.set_voltage = regulator_nxp_vref_set_voltage,
.get_voltage = regulator_nxp_vref_get_voltage,
.list_voltage = regulator_nxp_vref_list_voltage,
.count_voltages = regulator_nxp_vref_count_voltages,
};
static int regulator_nxp_vref_init(const struct device *dev)
{
int ret;
regulator_common_data_init(dev);
ret = regulator_nxp_vref_disable(dev);
if (ret < 0) {
return ret;
}
return regulator_common_init(dev, false);
}
#define REGULATOR_NXP_VREF_DEFINE(inst) \
static struct regulator_nxp_vref_data data_##inst; \
\
static const struct regulator_nxp_vref_config config_##inst = { \
.common = REGULATOR_DT_INST_COMMON_CONFIG_INIT(inst), \
.base = (VREF_Type *) DT_INST_REG_ADDR(inst), \
.buf_start_delay = DT_INST_PROP(inst, \
nxp_buffer_startup_delay_us), \
.bg_start_time = DT_INST_PROP(inst, \
nxp_bandgap_startup_time_us), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, regulator_nxp_vref_init, NULL, &data_##inst,\
&config_##inst, POST_KERNEL, \
CONFIG_REGULATOR_NXP_VREF_INIT_PRIORITY, &api); \
DT_INST_FOREACH_STATUS_OKAY(REGULATOR_NXP_VREF_DEFINE)
``` | /content/code_sandbox/drivers/regulator/regulator_nxp_vref.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,639 |
```unknown
config REGULATOR_RPI_PICO
bool "RaspberryPi Pico regulator driver"
default y
depends on DT_HAS_RASPBERRYPI_CORE_SUPPLY_REGULATOR_ENABLED
help
Enable support for the RaspberryPi Pico regulator.
if REGULATOR_RPI_PICO
config REGULATOR_RPI_PICO_INIT_PRIORITY
int "RaspberryPi Pico regulator driver init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
Init priority for the RaspberryPi Pico regulator driver.
endif
``` | /content/code_sandbox/drivers/regulator/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
# Hidden option for turning on the dummy driver for vnd,i2c devices
# used in testing.
config I2C_TEST
def_bool DT_HAS_VND_I2C_ENABLED
depends on DT_HAS_VND_I2C_ENABLED
``` | /content/code_sandbox/drivers/i2c/Kconfig.test | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*/
#define DT_DRV_COMPAT adi_adp5360_regulator
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/dt-bindings/regulator/adp5360.h>
#include <zephyr/sys/linear_range.h>
#include <zephyr/sys/util.h>
/* ADP5360 regulator related registers */
#define ADP5360_BUCK_CFG 0x29U
#define ADP5360_BUCK_OUTPUT 0x2AU
#define ADP5360_BUCKBST_CFG 0x2BU
#define ADP5360_BUCKBST_OUTPUT 0x2CU
/* Buck/boost configure register. */
#define ADP5360_BUCK_CFG_SS_MSK GENMASK(7, 6)
#define ADP5360_BUCK_CFG_SS_POS 6U
#define ADP5360_BUCK_CFG_BST_ILIM_MSK GENMASK(5, 3)
#define ADP5360_BUCK_CFG_BST_ILIM_POS 3U
#define ADP5360_BUCK_CFG_BUCK_ILIM_MSK GENMASK(5, 3)
#define ADP5360_BUCK_CFG_BUCK_ILIM_POS 3U
#define ADP5360_BUCK_CFG_BUCK_MODE_MSK BIT(3)
#define ADP5360_BUCK_CFG_BUCK_MODE_POS 3U
#define ADP5360_BUCK_CFG_STP_MSK BIT(2)
#define ADP5360_BUCK_CFG_DISCHG_MSK BIT(1)
#define ADP5360_BUCK_CFG_EN_MSK BIT(0)
/* Buck/boost output voltage setting register. */
#define ADP5360_BUCK_OUTPUT_VOUT_MSK GENMASK(5, 0)
#define ADP5360_BUCK_OUTPUT_VOUT_POS 0U
#define ADP5360_BUCK_OUTPUT_DLY_MSK GENMASK(7, 6)
#define ADP5360_BUCK_OUTPUT_DLY_POS 6U
struct regulator_adp5360_desc {
uint8_t cfg_reg;
uint8_t out_reg;
bool has_modes;
const struct linear_range *ranges;
uint8_t nranges;
};
static const struct linear_range buck_ranges[] = {
LINEAR_RANGE_INIT(600000, 50000U, 0x0U, 0x3FU),
};
static const struct regulator_adp5360_desc buck_desc = {
.cfg_reg = ADP5360_BUCK_CFG,
.out_reg = ADP5360_BUCK_OUTPUT,
.has_modes = true,
.ranges = buck_ranges,
.nranges = ARRAY_SIZE(buck_ranges),
};
static const struct linear_range buckboost_ranges[] = {
LINEAR_RANGE_INIT(1800000, 100000U, 0x0U, 0x0BU),
LINEAR_RANGE_INIT(2950000, 50000U, 0xCU, 0x3FU),
};
static const struct regulator_adp5360_desc buckboost_desc = {
.cfg_reg = ADP5360_BUCKBST_CFG,
.out_reg = ADP5360_BUCKBST_OUTPUT,
.has_modes = false,
.ranges = buckboost_ranges,
.nranges = ARRAY_SIZE(buckboost_ranges),
};
struct regulator_adp5360_config {
struct regulator_common_config common;
struct i2c_dt_spec i2c;
const struct regulator_adp5360_desc *desc;
int8_t dly_idx;
int8_t ss_idx;
int8_t ilim_idx;
bool stp_en;
bool dis_en;
};
struct regulator_adp5360_data {
struct regulator_common_data data;
};
static unsigned int regulator_adp5360_count_voltages(const struct device *dev)
{
const struct regulator_adp5360_config *config = dev->config;
return linear_range_group_values_count(config->desc->ranges, config->desc->nranges);
}
static int regulator_adp5360_list_voltage(const struct device *dev, unsigned int idx,
int32_t *volt_uv)
{
const struct regulator_adp5360_config *config = dev->config;
return linear_range_group_get_value(config->desc->ranges, config->desc->nranges, idx,
volt_uv);
}
static int regulator_adp5360_set_voltage(const struct device *dev, int32_t min_uv, int32_t max_uv)
{
const struct regulator_adp5360_config *config = dev->config;
uint16_t idx;
int ret;
ret = linear_range_group_get_win_index(config->desc->ranges, config->desc->nranges, min_uv,
max_uv, &idx);
if (ret == -EINVAL) {
return ret;
}
return i2c_reg_update_byte_dt(&config->i2c, config->desc->out_reg,
ADP5360_BUCK_OUTPUT_VOUT_MSK,
(uint8_t)idx << ADP5360_BUCK_OUTPUT_VOUT_POS);
}
static int regulator_adp5360_get_voltage(const struct device *dev, int32_t *volt_uv)
{
const struct regulator_adp5360_config *config = dev->config;
int ret;
uint8_t raw_reg;
ret = i2c_reg_read_byte_dt(&config->i2c, config->desc->out_reg, &raw_reg);
if (ret < 0) {
return ret;
}
raw_reg = (raw_reg & ADP5360_BUCK_OUTPUT_VOUT_MSK) >> ADP5360_BUCK_OUTPUT_VOUT_POS;
return linear_range_group_get_value(config->desc->ranges, config->desc->nranges, raw_reg,
volt_uv);
}
static int regulator_adp5360_set_mode(const struct device *dev, regulator_mode_t mode)
{
const struct regulator_adp5360_config *config = dev->config;
if (!config->desc->has_modes || (mode > ADP5360_MODE_PWM)) {
return -ENOTSUP;
}
return i2c_reg_update_byte_dt(&config->i2c, config->desc->cfg_reg,
ADP5360_BUCK_CFG_BUCK_MODE_MSK,
mode << ADP5360_BUCK_CFG_BUCK_MODE_POS);
}
static int regulator_adp5360_get_mode(const struct device *dev, regulator_mode_t *mode)
{
const struct regulator_adp5360_config *config = dev->config;
uint8_t val;
int ret;
if (!config->desc->has_modes) {
return -ENOTSUP;
}
ret = i2c_reg_read_byte_dt(&config->i2c, config->desc->cfg_reg, &val);
if (ret < 0) {
return ret;
}
*mode = (val & ADP5360_BUCK_CFG_BUCK_MODE_MSK) >> ADP5360_BUCK_CFG_BUCK_MODE_POS;
return 0;
}
static int regulator_adp5360_enable(const struct device *dev)
{
const struct regulator_adp5360_config *config = dev->config;
return i2c_reg_update_byte_dt(&config->i2c, config->desc->cfg_reg, ADP5360_BUCK_CFG_EN_MSK,
1U);
}
static int regulator_adp5360_disable(const struct device *dev)
{
const struct regulator_adp5360_config *config = dev->config;
return i2c_reg_update_byte_dt(&config->i2c, config->desc->cfg_reg, ADP5360_BUCK_CFG_EN_MSK,
0U);
}
static int regulator_adp5360_init(const struct device *dev)
{
const struct regulator_adp5360_config *config = dev->config;
int ret;
uint8_t val, nval, msk;
regulator_common_data_init(dev);
if (!i2c_is_ready_dt(&config->i2c)) {
return -ENODEV;
}
/* apply optional delay */
msk = 0U;
nval = 0U;
ret = i2c_reg_read_byte_dt(&config->i2c, config->desc->out_reg, &val);
if (ret < 0) {
return ret;
}
if (config->dly_idx >= 0) {
msk |= ADP5360_BUCK_OUTPUT_DLY_MSK;
nval |= ((uint8_t)config->dly_idx << ADP5360_BUCK_OUTPUT_DLY_POS) &
ADP5360_BUCK_OUTPUT_DLY_MSK;
}
if (msk != 0U) {
ret = i2c_reg_write_byte_dt(&config->i2c, config->desc->out_reg,
(val & ~msk) | nval);
if (ret < 0) {
return ret;
}
}
/* apply optional initial configuration */
msk = 0U;
nval = 0U;
ret = i2c_reg_read_byte_dt(&config->i2c, config->desc->cfg_reg, &val);
if (ret < 0) {
return ret;
}
if (config->ss_idx >= 0) {
msk |= ADP5360_BUCK_CFG_SS_MSK;
nval |= ((uint8_t)config->ss_idx << ADP5360_BUCK_CFG_SS_POS) &
ADP5360_BUCK_CFG_SS_MSK;
}
if (config->ilim_idx >= 0) {
if (config->desc->has_modes) {
msk |= ADP5360_BUCK_CFG_BUCK_ILIM_MSK;
nval |= ((uint8_t)config->ilim_idx << ADP5360_BUCK_CFG_BUCK_ILIM_POS) &
ADP5360_BUCK_CFG_BUCK_ILIM_MSK;
} else {
msk |= ADP5360_BUCK_CFG_BST_ILIM_MSK;
nval |= ((uint8_t)config->ilim_idx << ADP5360_BUCK_CFG_BST_ILIM_POS) &
ADP5360_BUCK_CFG_BST_ILIM_MSK;
}
}
if (config->stp_en) {
msk |= ADP5360_BUCK_CFG_STP_MSK;
nval |= ADP5360_BUCK_CFG_STP_MSK;
}
if (config->dis_en) {
msk |= ADP5360_BUCK_CFG_DISCHG_MSK;
nval |= ADP5360_BUCK_CFG_DISCHG_MSK;
}
if (msk != 0U) {
ret = i2c_reg_write_byte_dt(&config->i2c, config->desc->cfg_reg,
(val & ~msk) | nval);
if (ret < 0) {
return ret;
}
}
return regulator_common_init(dev, (val & ADP5360_BUCK_CFG_EN_MSK) != 0U);
}
static const struct regulator_driver_api api = {
.enable = regulator_adp5360_enable,
.disable = regulator_adp5360_disable,
.count_voltages = regulator_adp5360_count_voltages,
.list_voltage = regulator_adp5360_list_voltage,
.set_voltage = regulator_adp5360_set_voltage,
.get_voltage = regulator_adp5360_get_voltage,
.set_mode = regulator_adp5360_set_mode,
.get_mode = regulator_adp5360_get_mode,
};
#define REGULATOR_ADP5360_DEFINE(node_id, id, name) \
static struct regulator_adp5360_data data_##id; \
\
static const struct regulator_adp5360_config config_##id = { \
.common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id), \
.i2c = I2C_DT_SPEC_GET(DT_GPARENT(node_id)), \
.desc = &name##_desc, \
.dly_idx = DT_ENUM_IDX_OR(node_id, adi_switch_delay_us, -1), \
.ss_idx = DT_ENUM_IDX_OR(node_id, adi_soft_start_ms, -1), \
.ilim_idx = DT_ENUM_IDX_OR(node_id, adi_ilim_milliamp, -1), \
.stp_en = DT_PROP(node_id, adi_enable_stop_pulse), \
.dis_en = DT_PROP(node_id, adi_enable_output_discharge), \
}; \
\
DEVICE_DT_DEFINE(node_id, regulator_adp5360_init, NULL, &data_##id, &config_##id, \
POST_KERNEL, CONFIG_REGULATOR_ADP5360_INIT_PRIORITY, &api);
#define REGULATOR_ADP5360_DEFINE_COND(inst, child) \
COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
(REGULATOR_ADP5360_DEFINE(DT_INST_CHILD(inst, child), child##inst, child)), \
())
#define REGULATOR_ADP5360_DEFINE_ALL(inst) \
REGULATOR_ADP5360_DEFINE_COND(inst, buck) \
REGULATOR_ADP5360_DEFINE_COND(inst, buckboost)
DT_INST_FOREACH_STATUS_OKAY(REGULATOR_ADP5360_DEFINE_ALL)
``` | /content/code_sandbox/drivers/regulator/regulator_adp5360.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,787 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief I2C driver for Infineon XMC MCU family.
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_i2c
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_infineon_xmc4, CONFIG_I2C_LOG_LEVEL);
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include "i2c-priv.h"
#include <xmc_i2c.h>
#include <xmc_usic.h>
#define USIC_IRQ_MIN 84
#define IRQS_PER_USIC 6
#define I2C_XMC_EVENTS_MASK ( \
XMC_I2C_CH_EVENT_RECEIVE_START | \
XMC_I2C_CH_EVENT_DATA_LOST | \
XMC_I2C_CH_EVENT_TRANSMIT_SHIFT | \
XMC_I2C_CH_EVENT_TRANSMIT_BUFFER | \
XMC_I2C_CH_EVENT_STANDARD_RECEIVE | \
XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE | \
XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR | \
XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED | \
XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED | \
XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED | \
XMC_I2C_CH_EVENT_NACK | \
XMC_I2C_CH_EVENT_ARBITRATION_LOST | \
XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST | \
XMC_I2C_CH_EVENT_ERROR | \
XMC_I2C_CH_EVENT_ACK)
#define I2C_XMC_STATUS_FLAG_ERROR_MASK ( \
XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND | \
XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED | \
XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST | \
XMC_I2C_CH_STATUS_FLAG_ERROR | \
XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION)
/* I2C speed */
#define XMC4_I2C_SPEED_STANDARD (100000UL)
#define XMC4_I2C_SPEED_FAST (400000UL)
/* Data structure */
struct ifx_xmc4_i2c_data {
XMC_I2C_CH_CONFIG_t cfg;
struct k_sem operation_sem;
struct k_sem target_sem;
struct i2c_target_config *p_target_config;
uint32_t dev_config;
uint8_t target_wr_byte;
uint8_t target_wr_buffer[CONFIG_I2C_INFINEON_XMC4_TARGET_BUF];
bool ignore_slave_select;
bool is_configured;
};
/* Device config structure */
struct ifx_xmc4_i2c_config {
XMC_USIC_CH_t *i2c;
const struct pinctrl_dev_config *pcfg;
uint8_t scl_src;
uint8_t sda_src;
uint32_t bitrate;
void (*irq_config_func)(const struct device *dev);
};
static int ifx_xmc4_i2c_configure(const struct device *dev, uint32_t dev_config)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
/* This is deprecated and could be ignored in the future */
if (dev_config & I2C_ADDR_10_BITS) {
LOG_ERR("Use I2C_MSG_ADDR_10_BITS instead of I2C_ADDR_10_BITS");
return -EIO;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
data->cfg.baudrate = XMC4_I2C_SPEED_STANDARD;
break;
case I2C_SPEED_FAST:
data->cfg.baudrate = XMC4_I2C_SPEED_FAST;
break;
default:
LOG_ERR("Unsupported speed");
return -ERANGE;
}
data->dev_config = dev_config;
/* Acquire semaphore (block I2C operation for another thread) */
if (k_sem_take(&data->operation_sem, K_FOREVER)) {
return -EIO;
}
XMC_I2C_CH_Stop(config->i2c);
/* Configure the I2C resource */
data->cfg.normal_divider_mode = false;
XMC_I2C_CH_Init(config->i2c, &data->cfg);
XMC_I2C_CH_SetInputSource(config->i2c, XMC_I2C_CH_INPUT_SCL, config->scl_src);
XMC_I2C_CH_SetInputSource(config->i2c, XMC_I2C_CH_INPUT_SDA, config->sda_src);
if (data->dev_config & I2C_MODE_CONTROLLER) {
XMC_USIC_CH_SetFractionalDivider(config->i2c,
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL,
1023U);
} else {
config->irq_config_func(dev);
}
XMC_I2C_CH_Start(config->i2c);
data->is_configured = true;
/* Release semaphore */
k_sem_give(&data->operation_sem);
return 0;
}
static int ifx_xmc4_i2c_get_config(const struct device *dev, uint32_t *dev_config)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
if (!data->is_configured) {
/* if not yet configured return configuration that will be used */
/* when transfer() is called */
uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
*dev_config = I2C_MODE_CONTROLLER | bitrate_cfg;
return 0;
}
*dev_config = data->dev_config;
return 0;
}
static int ifx_xmc4_i2c_msg_validate(struct i2c_msg *msg, uint8_t num_msgs)
{
for (uint32_t i = 0u; i < num_msgs; i++) {
if ((I2C_MSG_ADDR_10_BITS & msg[i].flags) || (msg[i].buf == NULL)) {
return -EINVAL;
}
}
return 0;
}
static int ifx_xmc4_i2c_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs,
uint16_t addr)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
XMC_I2C_CH_CMD_t cmd_type;
if (!num_msgs) {
return 0;
}
if (!data->is_configured) {
int ret;
uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
ret = ifx_xmc4_i2c_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret) {
return ret;
}
}
/* Acquire semaphore (block I2C transfer for another thread) */
if (k_sem_take(&data->operation_sem, K_FOREVER)) {
return -EIO;
}
/* This function checks if msg.buf is not NULL and if target address is not 10 bit. */
if (ifx_xmc4_i2c_msg_validate(msg, num_msgs) != 0) {
k_sem_give(&data->operation_sem);
return -EINVAL;
}
for (uint32_t msg_index = 0u; msg_index < num_msgs; msg_index++) {
XMC_I2C_CH_ClearStatusFlag(config->i2c, 0xFFFFFFFF);
if ((msg_index == 0) || (msg[msg_index].flags & I2C_MSG_RESTART)) {
/* Send START condition */
cmd_type = ((msg[msg_index].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) ?
XMC_I2C_CH_CMD_READ : XMC_I2C_CH_CMD_WRITE;
if (msg[msg_index].flags & I2C_MSG_RESTART) {
XMC_I2C_CH_MasterRepeatedStart(config->i2c, addr << 1, cmd_type);
} else {
XMC_I2C_CH_MasterStart(config->i2c, addr << 1, cmd_type);
}
/* Wait for acknowledge */
while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U) {
/* wait for ACK from slave */
if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
I2C_XMC_STATUS_FLAG_ERROR_MASK) {
k_sem_give(&data->operation_sem);
return -EIO;
}
}
XMC_I2C_CH_ClearStatusFlag(config->i2c,
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED);
}
for (uint32_t buf_index = 0u; buf_index < msg[msg_index].len; buf_index++) {
if (cmd_type == XMC_I2C_CH_CMD_WRITE) {
/* Transmit next command from I2C master to I2C slave */
XMC_I2C_CH_MasterTransmit(config->i2c,
msg[msg_index].buf[buf_index]);
/* Wait for acknowledge */
while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U) {
/* wait for ACK from slave */
if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
I2C_XMC_STATUS_FLAG_ERROR_MASK) {
k_sem_give(&data->operation_sem);
return -EIO;
}
}
XMC_I2C_CH_ClearStatusFlag(config->i2c,
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED);
/* Wait until TX FIFO is empty */
while (!XMC_USIC_CH_TXFIFO_IsEmpty(config->i2c)) {
/* wait until all data is sent by HW */
if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
I2C_XMC_STATUS_FLAG_ERROR_MASK) {
k_sem_give(&data->operation_sem);
return -EIO;
}
}
} else {
if (buf_index == (msg[msg_index].len - 1)) {
XMC_I2C_CH_MasterReceiveNack(config->i2c);
} else {
XMC_I2C_CH_MasterReceiveAck(config->i2c);
}
while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
(XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION |
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION)) == 0U) {
/* wait for data byte from slave */
if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
I2C_XMC_STATUS_FLAG_ERROR_MASK) {
k_sem_give(&data->operation_sem);
return -EIO;
}
}
XMC_I2C_CH_ClearStatusFlag(config->i2c,
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION |
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION);
msg[msg_index].buf[buf_index] =
XMC_I2C_CH_GetReceivedData(config->i2c);
}
}
/* Send STOP condition */
if (msg[msg_index].flags & I2C_MSG_STOP) {
XMC_I2C_CH_MasterStop(config->i2c);
}
}
/* Release semaphore (After I2C transfer is complete) */
k_sem_give(&data->operation_sem);
return 0;
}
static int ifx_xmc4_i2c_init(const struct device *dev)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
int ret;
/* Configure semaphores */
ret = k_sem_init(&data->operation_sem, 1, 1);
if (ret) {
return ret;
}
ret = k_sem_init(&data->target_sem, 1, 1);
if (ret) {
return ret;
}
/* Configure dt provided device signals when available */
return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
}
static int ifx_xmc4_i2c_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
uint32_t bitrate_cfg;
if (!cfg ||
!cfg->callbacks->read_requested ||
!cfg->callbacks->read_processed ||
!cfg->callbacks->write_requested ||
!cfg->callbacks->write_received ||
!cfg->callbacks->stop) {
return -EINVAL;
}
if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -ENOTSUP;
}
/* Acquire semaphore (block I2C operation for another thread) */
if (k_sem_take(&data->target_sem, K_FOREVER)) {
return -EIO;
}
data->p_target_config = cfg;
data->cfg.address = cfg->address << 1;
if (data->is_configured) {
uint32_t bitrate;
bitrate = I2C_SPEED_GET(data->dev_config);
bitrate_cfg = i2c_map_dt_bitrate(bitrate);
} else {
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
}
if (ifx_xmc4_i2c_configure(dev, bitrate_cfg) != 0) {
/* Release semaphore */
k_sem_give(&data->target_sem);
return -EIO;
}
k_sem_give(&data->target_sem);
return 0;
}
static int ifx_xmc4_i2c_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
/* Acquire semaphore (block I2C operation for another thread) */
if (k_sem_take(&data->operation_sem, K_FOREVER)) {
return -EIO;
}
data->p_target_config = NULL;
XMC_I2C_CH_DisableEvent(config->i2c, I2C_XMC_EVENTS_MASK);
/* Release semaphore */
k_sem_give(&data->operation_sem);
return 0;
}
static void i2c_xmc4_isr(const struct device *dev)
{
struct ifx_xmc4_i2c_data *data = dev->data;
const struct ifx_xmc4_i2c_config *config = dev->config;
const struct i2c_target_callbacks *callbacks = data->p_target_config->callbacks;
uint32_t status = XMC_I2C_CH_GetStatusFlag(config->i2c);
while (status) {
XMC_I2C_CH_ClearStatusFlag(config->i2c, status);
if (status & XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED) {
/* Flush the TX buffer */
XMC_USIC_CH_SetTransmitBufferStatus(config->i2c,
XMC_USIC_CH_TBUF_STATUS_SET_IDLE);
callbacks->stop(data->p_target_config);
break;
}
if (!data->ignore_slave_select && (status & XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT)) {
data->ignore_slave_select = true;
/* Start a slave read */
if (status & XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED) {
callbacks->read_requested(data->p_target_config,
&data->target_wr_byte);
XMC_I2C_CH_SlaveTransmit(config->i2c, data->target_wr_byte);
} else {
callbacks->write_requested(data->p_target_config);
}
}
/* Continue a slave read */
if (status & XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION) {
callbacks->read_processed(data->p_target_config, &data->target_wr_byte);
XMC_I2C_CH_SlaveTransmit(config->i2c, data->target_wr_byte);
}
/* Start/Continue a slave write */
if (status & (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION |
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION)) {
callbacks->write_received(data->p_target_config,
XMC_I2C_CH_GetReceivedData(config->i2c));
}
if ((status & XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED) ||
(status & XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED)) {
data->ignore_slave_select = false;
}
status = XMC_I2C_CH_GetStatusFlag(config->i2c);
}
}
/* I2C API structure */
static const struct i2c_driver_api i2c_xmc4_driver_api = {
.configure = ifx_xmc4_i2c_configure,
.transfer = ifx_xmc4_i2c_transfer,
.get_config = ifx_xmc4_i2c_get_config,
.target_register = ifx_xmc4_i2c_target_register,
.target_unregister = ifx_xmc4_i2c_target_unregister};
/* Macros for I2C instance declaration */
#define XMC4_IRQ_HANDLER_INIT(index) \
static void i2c_xmc4_irq_setup_##index(const struct device *dev) \
{ \
const struct ifx_xmc4_i2c_config *config = dev->config; \
uint8_t irq_num = DT_INST_IRQN(index); \
uint8_t service_request = (irq_num - USIC_IRQ_MIN) % IRQS_PER_USIC; \
\
XMC_I2C_CH_SelectInterruptNodePointer(config->i2c, \
XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE, service_request); \
XMC_I2C_CH_SelectInterruptNodePointer(config->i2c, \
XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, service_request); \
\
XMC_I2C_CH_EnableEvent(config->i2c, I2C_XMC_EVENTS_MASK); \
\
IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), i2c_xmc4_isr, \
DEVICE_DT_INST_GET(index), 0); \
\
irq_enable(irq_num); \
}
#define XMC4_IRQ_HANDLER_STRUCT_INIT(index) .irq_config_func = i2c_xmc4_irq_setup_##index
#define INFINEON_XMC4_I2C_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
XMC4_IRQ_HANDLER_INIT(n) \
\
static struct ifx_xmc4_i2c_data ifx_xmc4_i2c_data##n; \
\
static const struct ifx_xmc4_i2c_config i2c_xmc4_cfg_##n = { \
.i2c = (XMC_USIC_CH_t *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.scl_src = DT_INST_ENUM_IDX(n, scl_src), \
.sda_src = DT_INST_ENUM_IDX(n, sda_src), \
.bitrate = DT_INST_PROP_OR(n, clock_frequency, I2C_SPEED_STANDARD), \
XMC4_IRQ_HANDLER_STRUCT_INIT(n) \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(n, ifx_xmc4_i2c_init, NULL, &ifx_xmc4_i2c_data##n, \
&i2c_xmc4_cfg_##n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_xmc4_driver_api);
DT_INST_FOREACH_STATUS_OKAY(INFINEON_XMC4_I2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_ifx_xmc4.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,427 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_
#define ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_
#include <zephyr/pm/device.h>
#include <nrfx_twi.h>
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_NRFX_TWI_INVALID_FREQUENCY ((nrf_twi_frequency_t)-1)
#define I2C_NRFX_TWI_FREQUENCY(bitrate) \
(bitrate == I2C_BITRATE_STANDARD ? NRF_TWI_FREQ_100K \
: bitrate == 250000 ? NRF_TWI_FREQ_250K \
: bitrate == I2C_BITRATE_FAST ? NRF_TWI_FREQ_400K \
: I2C_NRFX_TWI_INVALID_FREQUENCY)
#define I2C(idx) DT_NODELABEL(i2c##idx)
#define I2C_FREQUENCY(idx) \
I2C_NRFX_TWI_FREQUENCY(DT_PROP(I2C(idx), clock_frequency))
struct i2c_nrfx_twi_common_data {
uint32_t dev_config;
};
struct i2c_nrfx_twi_config {
nrfx_twi_t twi;
nrfx_twi_config_t config;
nrfx_twi_evt_handler_t event_handler;
const struct pinctrl_dev_config *pcfg;
};
static inline nrfx_err_t i2c_nrfx_twi_get_evt_result(nrfx_twi_evt_t const *p_event)
{
switch (p_event->type) {
case NRFX_TWI_EVT_DONE:
return NRFX_SUCCESS;
case NRFX_TWI_EVT_ADDRESS_NACK:
return NRFX_ERROR_DRV_TWI_ERR_ANACK;
case NRFX_TWI_EVT_DATA_NACK:
return NRFX_ERROR_DRV_TWI_ERR_DNACK;
default:
return NRFX_ERROR_INTERNAL;
}
}
int i2c_nrfx_twi_init(const struct device *dev);
int i2c_nrfx_twi_configure(const struct device *dev, uint32_t dev_config);
int i2c_nrfx_twi_recover_bus(const struct device *dev);
int i2c_nrfx_twi_msg_transfer(const struct device *dev, uint8_t flags,
uint8_t *buf, size_t buf_len,
uint16_t i2c_addr, bool more_msgs);
#ifdef CONFIG_PM_DEVICE
int twi_nrfx_pm_action(const struct device *dev, enum pm_device_action action);
#endif
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_nrfx_twi_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 564 |
```unknown
# I2C configuration options
menuconfig I2C_MCUX_FLEXCOMM
bool "MCUX FLEXCOMM I2C driver"
default y
depends on DT_HAS_NXP_LPC_I2C_ENABLED
select PINCTRL
select RESET
help
Enable the mcux flexcomm i2c driver.
config I2C_NXP_TRANSFER_TIMEOUT
int "Transfer timeout [ms]"
default 0
depends on I2C_MCUX_FLEXCOMM
help
Timeout in milliseconds used for each I2C transfer.
0 means that the driver should use the K_FOREVER value,
i.e. it should wait as long as necessary.
In conjunction with this, FSL_FEATURE_I2C_TIMEOUT_RECOVERY
must be enabled to allow the driver to fully recover.
``` | /content/code_sandbox/drivers/i2c/Kconfig.mcux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_i2c
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
#define SPEED_100KHZ_BUS 0
#define SPEED_400KHZ_BUS 1
#define SPEED_1MHZ_BUS 2
#define EC_OWN_I2C_ADDR 0x7F
#define RESET_WAIT_US 20
#define BUS_IDLE_US_DFLT 5
/* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
#define WAIT_INTERVAL 50
#define WAIT_COUNT 200
/* Line High Timeout is 2.5 ms (WAIT_LINE_HIGH_USEC * WAIT_LINE_HIGH_COUNT) */
#define WAIT_LINE_HIGH_USEC 25
#define WAIT_LINE_HIGH_COUNT 100
/* I2C Read/Write bit pos */
#define I2C_READ_WRITE_POS 0
struct xec_speed_cfg {
uint32_t bus_clk;
uint32_t data_timing;
uint32_t start_hold_time;
uint32_t config;
uint32_t timeout_scale;
};
struct i2c_xec_config {
uint32_t port_sel;
uint32_t base_addr;
uint8_t girq_id;
uint8_t girq_bit;
uint8_t pcr_idx;
uint8_t pcr_bitpos;
struct gpio_dt_spec sda_gpio;
struct gpio_dt_spec scl_gpio;
const struct pinctrl_dev_config *pcfg;
void (*irq_config_func)(void);
};
struct i2c_xec_data {
uint32_t pending_stop;
uint32_t error_seen;
uint32_t timeout_seen;
uint32_t previously_in_read;
uint32_t speed_id;
struct i2c_target_config *slave_cfg;
bool slave_attached;
bool slave_read;
};
/* Recommended programming values based on 16MHz
* i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
* bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
* (16MHz/400KHz -2) = 0x0F + 0x17
* (16MHz/1MHz -2) = 0x05 + 0x09
*/
static const struct xec_speed_cfg xec_cfg_params[] = {
[SPEED_100KHZ_BUS] = {
.bus_clk = 0x00004F4F,
.data_timing = 0x0C4D5006,
.start_hold_time = 0x0000004D,
.config = 0x01FC01ED,
.timeout_scale = 0x4B9CC2C7,
},
[SPEED_400KHZ_BUS] = {
.bus_clk = 0x00000F17,
.data_timing = 0x040A0A06,
.start_hold_time = 0x0000000A,
.config = 0x01000050,
.timeout_scale = 0x159CC2C7,
},
[SPEED_1MHZ_BUS] = {
.bus_clk = 0x00000509,
.data_timing = 0x04060601,
.start_hold_time = 0x00000006,
.config = 0x10000050,
.timeout_scale = 0x089CC2C7,
},
};
static void i2c_xec_reset_config(const struct device *dev)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
uint32_t ba = config->base_addr;
/* Assert RESET */
z_mchp_xec_pcr_periph_reset(config->pcr_idx, config->pcr_bitpos);
/* Write 0x80. i.e Assert PIN bit, ESO = 0 and Interrupts
* disabled (ENI)
*/
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN;
/* Enable controller and I2C filters */
MCHP_I2C_SMB_CFG(ba) = MCHP_I2C_SMB_CFG_GC_EN |
MCHP_I2C_SMB_CFG_ENAB |
MCHP_I2C_SMB_CFG_FEN |
(config->port_sel &
MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
/* Configure bus clock register, Data Timing register,
* Repeated Start Hold Time register,
* and Timeout Scaling register
*/
MCHP_I2C_SMB_BUS_CLK(ba) = xec_cfg_params[data->speed_id].bus_clk;
MCHP_I2C_SMB_DATA_TM(ba) = xec_cfg_params[data->speed_id].data_timing;
MCHP_I2C_SMB_RSHT(ba) =
xec_cfg_params[data->speed_id].start_hold_time;
MCHP_I2C_SMB_TMTSC(ba) = xec_cfg_params[data->speed_id].timeout_scale;
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ACK;
k_busy_wait(RESET_WAIT_US);
}
static int xec_spin_yield(int *counter)
{
*counter = *counter + 1;
if (*counter > WAIT_COUNT) {
return -ETIMEDOUT;
}
k_busy_wait(WAIT_INTERVAL);
return 0;
}
static void cleanup_registers(uint32_t ba)
{
uint32_t cfg = MCHP_I2C_SMB_CFG(ba);
cfg |= MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
MCHP_I2C_SMB_CFG(ba) = cfg;
cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
cfg |= MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
MCHP_I2C_SMB_CFG(ba) = cfg;
cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
cfg |= MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
MCHP_I2C_SMB_CFG(ba) = cfg;
cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
cfg |= MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
MCHP_I2C_SMB_CFG(ba) = cfg;
cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
}
#ifdef CONFIG_I2C_TARGET
static void restart_slave(uint32_t ba)
{
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ACK |
MCHP_I2C_SMB_CTRL_ENI;
}
#endif
static void recover_from_error(const struct device *dev)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
uint32_t ba = config->base_addr;
cleanup_registers(ba);
i2c_xec_reset_config(dev);
}
static int wait_bus_free(const struct device *dev)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
int ret;
int counter = 0;
uint32_t ba = config->base_addr;
while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
ret = xec_spin_yield(&counter);
if (ret < 0) {
return ret;
}
}
/* Check for bus error */
if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
recover_from_error(dev);
return -EBUSY;
}
return 0;
}
/*
* Wait with timeout for I2C controller to finish transmit/receive of one
* byte(address or data).
* When transmit/receive operation is started the I2C PIN status is 1. Upon
* normal completion I2C PIN status asserts(0).
* We loop checking I2C status for the following events:
* Bus Error:
* Reset controller and return -EBUSY
* Lost Arbitration:
* Return -EPERM. We lost bus to another controller. No reset.
* PIN == 0: I2C Status LRB is valid and contains ACK/NACK data on 9th clock.
* ACK return 0 (success)
* NACK Issue STOP, wait for bus minimum idle time, return -EIO.
* Timeout:
* Reset controller and return -ETIMEDOUT
*
* NOTE: After generating a STOP the controller will not generate a START until
* Bus Minimum Idle time has expired.
*/
static int wait_completion(const struct device *dev)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
int ret;
int counter = 0;
uint32_t ba = config->base_addr;
while (1) {
uint8_t status = MCHP_I2C_SMB_STS_RO(ba);
/* Is bus error ? */
if (status & MCHP_I2C_SMB_STS_BER) {
recover_from_error(dev);
return -EBUSY;
}
/* Is Lost arbitration ? */
status = MCHP_I2C_SMB_STS_RO(ba);
if (status & MCHP_I2C_SMB_STS_LAB) {
recover_from_error(dev);
return -EPERM;
}
status = MCHP_I2C_SMB_STS_RO(ba);
/* PIN -> 0 indicates I2C is done */
if (!(status & MCHP_I2C_SMB_STS_PIN)) {
/* PIN == 0. LRB contains state of 9th bit */
if (status & MCHP_I2C_SMB_STS_LRB_AD0) { /* NACK? */
/* Send STOP */
MCHP_I2C_SMB_CTRL_WO(ba) =
MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO |
MCHP_I2C_SMB_CTRL_ACK;
k_busy_wait(BUS_IDLE_US_DFLT);
return -EIO;
}
break; /* success: ACK */
}
ret = xec_spin_yield(&counter);
if (ret < 0) {
return ret;
}
}
return 0;
}
/*
* Call GPIO driver to read state of pins.
* Return boolean true if both lines HIGH else return boolean false
*/
static bool check_lines_high(const struct device *dev)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const)(dev->config);
gpio_port_value_t sda = 0, scl = 0;
if (gpio_port_get_raw(config->sda_gpio.port, &sda)) {
LOG_ERR("gpio_port_get_raw for %s SDA failed", dev->name);
return false;
}
/* both pins could be on same GPIO group */
if (config->sda_gpio.port == config->scl_gpio.port) {
scl = sda;
} else {
if (gpio_port_get_raw(config->scl_gpio.port, &scl)) {
LOG_ERR("gpio_port_get_raw for %s SCL failed",
dev->name);
return false;
}
}
return (sda & BIT(config->sda_gpio.pin)) && (scl & BIT(config->scl_gpio.pin));
}
static int i2c_xec_configure(const struct device *dev,
uint32_t dev_config_raw)
{
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
return -ENOTSUP;
}
if (dev_config_raw & I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
data->speed_id = SPEED_100KHZ_BUS;
break;
case I2C_SPEED_FAST:
data->speed_id = SPEED_400KHZ_BUS;
break;
case I2C_SPEED_FAST_PLUS:
data->speed_id = SPEED_1MHZ_BUS;
break;
default:
return -EINVAL;
}
i2c_xec_reset_config(dev);
return 0;
}
static int i2c_xec_poll_write(const struct device *dev, struct i2c_msg msg,
uint16_t addr)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
uint32_t ba = config->base_addr;
uint8_t i2c_timer = 0, byte;
int ret;
if (data->timeout_seen == 1) {
/* Wait to see if the slave has released the CLK */
ret = wait_completion(dev);
if (ret) {
data->timeout_seen = 1;
LOG_ERR("%s: %s wait_completion failure %d\n",
__func__, dev->name, ret);
return ret;
}
data->timeout_seen = 0;
/* If we are here, it means the slave has finally released
* the CLK. The master needs to end that transaction
* gracefully by sending a STOP on the bus.
*/
LOG_DBG("%s: %s Force Stop", __func__, dev->name);
MCHP_I2C_SMB_CTRL_WO(ba) =
MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO |
MCHP_I2C_SMB_CTRL_ACK;
k_busy_wait(BUS_IDLE_US_DFLT);
data->pending_stop = 0;
/* If the timeout had occurred while the master was reading
* something from the slave, that read needs to be completed
* to clear the bus.
*/
if (data->previously_in_read == 1) {
data->previously_in_read = 0;
byte = MCHP_I2C_SMB_DATA(ba);
}
return -EBUSY;
}
if ((data->pending_stop == 0) || (data->error_seen == 1)) {
/* Wait till clock and data lines are HIGH */
while (check_lines_high(dev) == false) {
if (i2c_timer >= WAIT_LINE_HIGH_COUNT) {
LOG_DBG("%s: %s not high",
__func__, dev->name);
data->error_seen = 1;
return -EBUSY;
}
k_busy_wait(WAIT_LINE_HIGH_USEC);
i2c_timer++;
}
if (data->error_seen) {
LOG_DBG("%s: Recovering %s previously in error",
__func__, dev->name);
data->error_seen = 0;
recover_from_error(dev);
}
/* Wait until bus is free */
ret = wait_bus_free(dev);
if (ret) {
data->error_seen = 1;
LOG_DBG("%s: %s wait_bus_free failure %d",
__func__, dev->name, ret);
return ret;
}
/* Send slave address */
MCHP_I2C_SMB_DATA(ba) = (addr & ~BIT(0));
/* Send start and ack bits */
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
MCHP_I2C_SMB_CTRL_ACK;
ret = wait_completion(dev);
switch (ret) {
case 0: /* Success */
break;
case -EIO:
LOG_WRN("%s: No Addr ACK from Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
default:
data->error_seen = 1;
LOG_ERR("%s: %s wait_comp error %d for addr send",
__func__, dev->name, ret);
return ret;
}
}
/* Send bytes */
for (int i = 0U; i < msg.len; i++) {
MCHP_I2C_SMB_DATA(ba) = msg.buf[i];
ret = wait_completion(dev);
switch (ret) {
case 0: /* Success */
break;
case -EIO:
LOG_ERR("%s: No Data ACK from Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
case -ETIMEDOUT:
data->timeout_seen = 1;
LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
default:
data->error_seen = 1;
LOG_ERR("%s: %s wait_completion error %d for data send",
__func__, dev->name, ret);
return ret;
}
}
/* Handle stop bit for last byte to write */
if (msg.flags & I2C_MSG_STOP) {
/* Send stop and ack bits */
MCHP_I2C_SMB_CTRL_WO(ba) =
MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO |
MCHP_I2C_SMB_CTRL_ACK;
data->pending_stop = 0;
} else {
data->pending_stop = 1;
}
return 0;
}
static int i2c_xec_poll_read(const struct device *dev, struct i2c_msg msg,
uint16_t addr)
{
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
uint32_t ba = config->base_addr;
uint8_t byte, ctrl, i2c_timer = 0;
int ret;
if (data->timeout_seen == 1) {
/* Wait to see if the slave has released the CLK */
ret = wait_completion(dev);
if (ret) {
data->timeout_seen = 1;
LOG_ERR("%s: %s wait_completion failure %d\n",
__func__, dev->name, ret);
return ret;
}
data->timeout_seen = 0;
/* If we are here, it means the slave has finally released
* the CLK. The master needs to end that transaction
* gracefully by sending a STOP on the bus.
*/
LOG_DBG("%s: %s Force Stop", __func__, dev->name);
MCHP_I2C_SMB_CTRL_WO(ba) =
MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO |
MCHP_I2C_SMB_CTRL_ACK;
k_busy_wait(BUS_IDLE_US_DFLT);
return -EBUSY;
}
if (!(msg.flags & I2C_MSG_RESTART) || (data->error_seen == 1)) {
/* Wait till clock and data lines are HIGH */
while (check_lines_high(dev) == false) {
if (i2c_timer >= WAIT_LINE_HIGH_COUNT) {
LOG_DBG("%s: %s not high",
__func__, dev->name);
data->error_seen = 1;
return -EBUSY;
}
k_busy_wait(WAIT_LINE_HIGH_USEC);
i2c_timer++;
}
if (data->error_seen) {
LOG_DBG("%s: Recovering %s previously in error",
__func__, dev->name);
data->error_seen = 0;
recover_from_error(dev);
}
/* Wait until bus is free */
ret = wait_bus_free(dev);
if (ret) {
data->error_seen = 1;
LOG_DBG("%s: %s wait_bus_free failure %d",
__func__, dev->name, ret);
return ret;
}
}
/* MCHP I2C spec recommends that for repeated start to write to control
* register before writing to data register
*/
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STA | MCHP_I2C_SMB_CTRL_ACK;
/* Send slave address */
MCHP_I2C_SMB_DATA(ba) = (addr | BIT(0));
ret = wait_completion(dev);
switch (ret) {
case 0: /* Success */
break;
case -EIO:
data->error_seen = 1;
LOG_WRN("%s: No Addr ACK from Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
case -ETIMEDOUT:
data->previously_in_read = 1;
data->timeout_seen = 1;
LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
default:
data->error_seen = 1;
LOG_ERR("%s: %s wait_completion error %d for address send",
__func__, dev->name, ret);
return ret;
}
if (msg.len == 1) {
/* Send NACK for last transaction */
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
}
/* Read dummy byte */
byte = MCHP_I2C_SMB_DATA(ba);
for (int i = 0U; i < msg.len; i++) {
ret = wait_completion(dev);
switch (ret) {
case 0: /* Success */
break;
case -EIO:
LOG_ERR("%s: No Data ACK from Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
case -ETIMEDOUT:
data->previously_in_read = 1;
data->timeout_seen = 1;
LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
__func__, addr >> 1, dev->name);
return ret;
default:
data->error_seen = 1;
LOG_ERR("%s: %s wait_completion error %d for data send",
__func__, dev->name, ret);
return ret;
}
if (i == (msg.len - 1)) {
if (msg.flags & I2C_MSG_STOP) {
/* Send stop and ack bits */
ctrl = (MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO |
MCHP_I2C_SMB_CTRL_ACK);
MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
data->pending_stop = 0;
}
} else if (i == (msg.len - 2)) {
/* Send NACK for last transaction */
MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
}
msg.buf[i] = MCHP_I2C_SMB_DATA(ba);
}
return 0;
}
static int i2c_xec_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
int ret = 0;
#ifdef CONFIG_I2C_TARGET
struct i2c_xec_data *data = dev->data;
if (data->slave_attached) {
LOG_ERR("%s Device is registered as slave", dev->name);
return -EBUSY;
}
#endif
addr <<= 1;
for (int i = 0U; i < num_msgs; i++) {
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = i2c_xec_poll_write(dev, msgs[i], addr);
if (ret) {
LOG_ERR("%s Write error: %d", dev->name, ret);
return ret;
}
} else {
ret = i2c_xec_poll_read(dev, msgs[i], addr);
if (ret) {
LOG_ERR("%s Read error: %d", dev->name, ret);
return ret;
}
}
}
return 0;
}
static void i2c_xec_bus_isr(const struct device *dev)
{
#ifdef CONFIG_I2C_TARGET
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data = dev->data;
const struct i2c_target_callbacks *slave_cb = data->slave_cfg->callbacks;
uint32_t ba = config->base_addr;
uint32_t status;
uint8_t val;
uint8_t dummy = 0U;
if (!data->slave_attached) {
return;
}
/* Get current status */
status = MCHP_I2C_SMB_STS_RO(ba);
/* Bus Error */
if (status & MCHP_I2C_SMB_STS_BER) {
if (slave_cb->stop) {
slave_cb->stop(data->slave_cfg);
}
restart_slave(ba);
goto clear_iag;
}
/* External stop */
if (status & MCHP_I2C_SMB_STS_EXT_STOP) {
if (slave_cb->stop) {
slave_cb->stop(data->slave_cfg);
}
dummy = MCHP_I2C_SMB_DATA(ba);
restart_slave(ba);
goto clear_iag;
}
/* Address byte handling */
if (status & MCHP_I2C_SMB_STS_AAS) {
uint8_t slv_data = MCHP_I2C_SMB_DATA(ba);
if (!(slv_data & BIT(I2C_READ_WRITE_POS))) {
/* Slave receive */
data->slave_read = false;
if (slave_cb->write_requested) {
slave_cb->write_requested(data->slave_cfg);
}
goto clear_iag;
} else {
/* Slave transmit */
data->slave_read = true;
if (slave_cb->read_requested) {
slave_cb->read_requested(data->slave_cfg, &val);
}
MCHP_I2C_SMB_DATA(ba) = val;
goto clear_iag;
}
}
/* Slave transmit */
if (data->slave_read) {
/* Master has Nacked, then just write a dummy byte */
if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_LRB_AD0) {
MCHP_I2C_SMB_DATA(ba) = dummy;
} else {
if (slave_cb->read_processed) {
slave_cb->read_processed(data->slave_cfg, &val);
}
MCHP_I2C_SMB_DATA(ba) = val;
}
} else {
val = MCHP_I2C_SMB_DATA(ba);
/* TODO NACK Master */
if (slave_cb->write_received) {
slave_cb->write_received(data->slave_cfg, val);
}
}
clear_iag:
MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
#endif
}
#ifdef CONFIG_I2C_TARGET
static int i2c_xec_target_register(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data = dev->data;
uint32_t ba = cfg->base_addr;
int ret;
int counter = 0;
if (!config) {
return -EINVAL;
}
if (data->slave_attached) {
return -EBUSY;
}
/* Wait for any outstanding transactions to complete so that
* the bus is free
*/
while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
ret = xec_spin_yield(&counter);
if (ret < 0) {
return ret;
}
}
data->slave_cfg = config;
/* Set own address */
MCHP_I2C_SMB_OWN_ADDR(ba) = data->slave_cfg->address;
restart_slave(ba);
data->slave_attached = true;
/* Clear before enabling girq bit */
MCHP_GIRQ_SRC(cfg->girq_id) = BIT(cfg->girq_bit);
MCHP_GIRQ_ENSET(cfg->girq_id) = BIT(cfg->girq_bit);
return 0;
}
static int i2c_xec_target_unregister(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data = dev->data;
if (!data->slave_attached) {
return -EINVAL;
}
data->slave_attached = false;
MCHP_GIRQ_ENCLR(cfg->girq_id) = BIT(cfg->girq_bit);
return 0;
}
#endif
static const struct i2c_driver_api i2c_xec_driver_api = {
.configure = i2c_xec_configure,
.transfer = i2c_xec_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_xec_target_register,
.target_unregister = i2c_xec_target_unregister,
#endif
};
static int i2c_xec_init(const struct device *dev)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
int ret;
data->pending_stop = 0;
data->slave_attached = false;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC I2C pinctrl setup failed (%d)", ret);
return ret;
}
if (!gpio_is_ready_dt(&cfg->sda_gpio)) {
LOG_ERR("%s GPIO device is not ready for SDA GPIO", dev->name);
return -ENODEV;
}
if (!gpio_is_ready_dt(&cfg->scl_gpio)) {
LOG_ERR("%s GPIO device is not ready for SCL GPIO", dev->name);
return -ENODEV;
}
/* Default configuration */
ret = i2c_xec_configure(dev,
I2C_MODE_CONTROLLER |
I2C_SPEED_SET(I2C_SPEED_STANDARD));
if (ret) {
LOG_ERR("%s configure failed %d", dev->name, ret);
return ret;
}
#ifdef CONFIG_I2C_TARGET
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
config->irq_config_func();
#endif
return 0;
}
#define I2C_XEC_DEVICE(n) \
\
PINCTRL_DT_INST_DEFINE(n); \
\
static void i2c_xec_irq_config_func_##n(void); \
\
static struct i2c_xec_data i2c_xec_data_##n; \
static const struct i2c_xec_config i2c_xec_config_##n = { \
.base_addr = \
DT_INST_REG_ADDR(n), \
.port_sel = DT_INST_PROP(n, port_sel), \
.girq_id = DT_INST_PROP(n, girq), \
.girq_bit = DT_INST_PROP(n, girq_bit), \
.pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
.pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
.sda_gpio = GPIO_DT_SPEC_INST_GET(n, sda_gpios), \
.scl_gpio = GPIO_DT_SPEC_INST_GET(n, scl_gpios), \
.irq_config_func = i2c_xec_irq_config_func_##n, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_xec_init, NULL, \
&i2c_xec_data_##n, &i2c_xec_config_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_xec_driver_api); \
\
static void i2c_xec_irq_config_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
i2c_xec_bus_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_XEC_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,685 |
```c
/*
*
* Based on the i2c_mcux_lpi2c.c driver, which is:
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_lpi2c
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_lpi2c.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
LOG_MODULE_REGISTER(rv32m1_lpi2c);
#include "i2c-priv.h"
struct rv32m1_lpi2c_config {
LPI2C_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
clock_ip_name_t clock_ip_name;
uint32_t clock_ip_src;
uint32_t bitrate;
void (*irq_config_func)(const struct device *dev);
const struct pinctrl_dev_config *pincfg;
};
struct rv32m1_lpi2c_data {
lpi2c_master_handle_t handle;
struct k_sem transfer_sync;
struct k_sem completion_sync;
status_t completion_status;
};
static int rv32m1_lpi2c_configure(const struct device *dev,
uint32_t dev_config)
{
const struct rv32m1_lpi2c_config *config = dev->config;
uint32_t baudrate;
uint32_t clk_freq;
int err;
if (!(I2C_MODE_CONTROLLER & dev_config)) {
/* Slave mode not supported - yet */
LOG_ERR("Slave mode not supported");
return -ENOTSUP;
}
if (I2C_ADDR_10_BITS & dev_config) {
/* FSL LPI2C driver only supports 7-bit addressing */
LOG_ERR("10 bit addressing not supported");
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
/* TODO: only if SCL pin implements current source pull-up */
/* case I2C_SPEED_HIGH: */
/* baudrate = KHZ(3400); */
/* break; */
/* TODO: ultra-fast requires pin_config setting */
/* case I2C_SPEED_ULTRA: */
/* baudrate = MHZ(5); */
/* break; */
default:
LOG_ERR("Unsupported speed");
return -ENOTSUP;
}
err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq);
if (err) {
LOG_ERR("Could not get clock frequency (err %d)", err);
return -EINVAL;
}
LPI2C_MasterSetBaudRate(config->base, clk_freq, baudrate);
return 0;
}
static void rv32m1_lpi2c_master_transfer_callback(LPI2C_Type *base,
lpi2c_master_handle_t *handle,
status_t completionStatus,
void *userData)
{
struct rv32m1_lpi2c_data *data = userData;
ARG_UNUSED(base);
ARG_UNUSED(handle);
data->completion_status = completionStatus;
k_sem_give(&data->completion_sync);
}
static uint32_t rv32m1_lpi2c_convert_flags(int msg_flags)
{
uint32_t flags = 0U;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kLPI2C_TransferNoStopFlag;
}
if (msg_flags & I2C_MSG_RESTART) {
flags |= kLPI2C_TransferRepeatedStartFlag;
}
return flags;
}
static int rv32m1_lpi2c_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct rv32m1_lpi2c_config *config = dev->config;
struct rv32m1_lpi2c_data *data = dev->data;
lpi2c_master_transfer_t transfer;
status_t status;
int ret = 0;
k_sem_take(&data->transfer_sync, K_FOREVER);
/* Iterate over all the messages */
for (int i = 0; i < num_msgs; i++) {
if (I2C_MSG_ADDR_10_BITS & msgs->flags) {
ret = -ENOTSUP;
goto out;
}
/* Initialize the transfer descriptor */
transfer.flags = rv32m1_lpi2c_convert_flags(msgs->flags);
/* Prevent the controller to send a start condition between
* messages, except if explicitly requested.
*/
if (i != 0 && !(msgs->flags & I2C_MSG_RESTART)) {
transfer.flags |= kLPI2C_TransferNoStartFlag;
}
transfer.slaveAddress = addr;
transfer.direction = (msgs->flags & I2C_MSG_READ)
? kLPI2C_Read : kLPI2C_Write;
transfer.subaddress = 0;
transfer.subaddressSize = 0;
transfer.data = msgs->buf;
transfer.dataSize = msgs->len;
/* Start the transfer */
status = LPI2C_MasterTransferNonBlocking(config->base,
&data->handle,
&transfer);
/* Return an error if the transfer didn't start successfully
* e.g., if the bus was busy
*/
if (status != kStatus_Success) {
LOG_DBG("Could not start transfer (status %d)", status);
ret = -EIO;
goto out;
}
/* Wait for the transfer to complete */
k_sem_take(&data->completion_sync, K_FOREVER);
/* Return an error if the transfer didn't complete
* successfully. e.g., nak, timeout, lost arbitration
*/
if (data->completion_status != kStatus_Success) {
LOG_DBG("Transfer failed (status %d)",
data->completion_status);
LPI2C_MasterTransferAbort(config->base, &data->handle);
ret = -EIO;
goto out;
}
/* Move to the next message */
msgs++;
}
out:
k_sem_give(&data->transfer_sync);
return ret;
}
static void rv32m1_lpi2c_isr(const struct device *dev)
{
const struct rv32m1_lpi2c_config *config = dev->config;
struct rv32m1_lpi2c_data *data = dev->data;
LPI2C_MasterTransferHandleIRQ(config->base, &data->handle);
}
static int rv32m1_lpi2c_init(const struct device *dev)
{
const struct rv32m1_lpi2c_config *config = dev->config;
struct rv32m1_lpi2c_data *data = dev->data;
lpi2c_master_config_t master_config;
uint32_t clk_freq, dev_cfg;
int err;
CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
err = clock_control_on(config->clock_dev, config->clock_subsys);
if (err) {
LOG_ERR("Could not turn on clock (err %d)", err);
return -EINVAL;
}
err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq);
if (err) {
LOG_ERR("Could not get clock frequency (err %d)", err);
return -EINVAL;
}
LPI2C_MasterGetDefaultConfig(&master_config);
LPI2C_MasterInit(config->base, &master_config, clk_freq);
LPI2C_MasterTransferCreateHandle(config->base, &data->handle,
rv32m1_lpi2c_master_transfer_callback,
data);
dev_cfg = i2c_map_dt_bitrate(config->bitrate);
err = rv32m1_lpi2c_configure(dev, dev_cfg | I2C_MODE_CONTROLLER);
if (err) {
LOG_ERR("Could not configure controller (err %d)", err);
return err;
}
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
return err;
}
config->irq_config_func(dev);
return 0;
}
static const struct i2c_driver_api rv32m1_lpi2c_driver_api = {
.configure = rv32m1_lpi2c_configure,
.transfer = rv32m1_lpi2c_transfer,
};
#define RV32M1_LPI2C_DEVICE(id) \
PINCTRL_DT_INST_DEFINE(id); \
static void rv32m1_lpi2c_irq_config_func_##id(const struct device *dev); \
static const struct rv32m1_lpi2c_config rv32m1_lpi2c_##id##_config = { \
.base = \
(LPI2C_Type *)DT_INST_REG_ADDR(id), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
.clock_subsys = \
(clock_control_subsys_t) DT_INST_CLOCKS_CELL(id, name),\
.clock_ip_name = INST_DT_CLOCK_IP_NAME(id), \
.clock_ip_src = kCLOCK_IpSrcFircAsync, \
.bitrate = DT_INST_PROP(id, clock_frequency), \
.irq_config_func = rv32m1_lpi2c_irq_config_func_##id, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \
}; \
static struct rv32m1_lpi2c_data rv32m1_lpi2c_##id##_data = { \
.transfer_sync = Z_SEM_INITIALIZER( \
rv32m1_lpi2c_##id##_data.transfer_sync, 1, 1), \
.completion_sync = Z_SEM_INITIALIZER( \
rv32m1_lpi2c_##id##_data.completion_sync, 0, 1), \
}; \
I2C_DEVICE_DT_INST_DEFINE(id, \
rv32m1_lpi2c_init, \
NULL, \
&rv32m1_lpi2c_##id##_data, \
&rv32m1_lpi2c_##id##_config, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&rv32m1_lpi2c_driver_api); \
static void rv32m1_lpi2c_irq_config_func_##id(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(id), \
0, \
rv32m1_lpi2c_isr, DEVICE_DT_INST_GET(id), \
0); \
irq_enable(DT_INST_IRQN(id)); \
} \
DT_INST_FOREACH_STATUS_OKAY(RV32M1_LPI2C_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_rv32m1_lpi2c.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,433 |
```unknown
config I2C_SBCON
bool "I2C driver for ARM's SBCon two-wire serial bus interface"
default y
depends on DT_HAS_ARM_VERSATILE_I2C_ENABLED
select I2C_BITBANG
``` | /content/code_sandbox/drivers/i2c/Kconfig.sbcon | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# Ambiq SDK I2C
#
#
#
menuconfig I2C_AMBIQ
bool "AMBIQ I2C driver"
default y
depends on DT_HAS_AMBIQ_I2C_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_I2C
help
Enable driver for Ambiq I2C.
if I2C_AMBIQ
config I2C_AMBIQ_DMA
bool "AMBIQ APOLLO I2C DMA Support"
help
Enable DMA for Ambiq I2C.
config I2C_DMA_TCB_BUFFER_SIZE
int "DMA Transfer Control Buffer size in words."
default 1024
help
DMA Transfer Control Buffer size in words
endif # I2C_AMBIQ
``` | /content/code_sandbox/drivers/i2c/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```unknown
config I2C_LPC11U6X
bool "LPC11U6X I2C driver"
default y
depends on DT_HAS_NXP_LPC11U6X_I2C_ENABLED
help
Enable I2C support on the LPC11U6X SoCs
``` | /content/code_sandbox/drivers/i2c/Kconfig.lpc11u6x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```c
/*
*
*/
/**
* @file
* @brief Software driven 'bit-banging' library for I2C
*
* This code implements the I2C single master protocol in software by directly
* manipulating the levels of the SCL and SDA lines of an I2C bus. It supports
* the Standard-mode and Fast-mode speeds and doesn't support optional
* protocol feature like 10-bit addresses or clock stretching.
*
* Timings and protocol are based Rev. 6 of the I2C specification:
* path_to_url
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include "i2c_bitbang.h"
/*
* Indexes into delay table for each part of I2C timing waveform we are
* interested in. In practice, for Standard and Fast modes, there are only two
* different numerical values (T_LOW and T_HIGH) so we alias the others to
* these. (Actually, we're simplifying a little, T_SU_STA could be T_HIGH on
* Fast mode)
*/
#define T_LOW 0
#define T_HIGH 1
#define T_SU_STA T_LOW
#define T_HD_STA T_HIGH
#define T_SU_STP T_HIGH
#define T_BUF T_LOW
#define NS_TO_SYS_CLOCK_HW_CYCLES(ns) \
((uint64_t)sys_clock_hw_cycles_per_sec() * (ns) / NSEC_PER_SEC + 1)
int i2c_bitbang_configure(struct i2c_bitbang *context, uint32_t dev_config)
{
/* Check for features we don't support */
if (I2C_ADDR_10_BITS & dev_config) {
return -ENOTSUP;
}
/* Setup speed to use */
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700);
context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000);
break;
case I2C_SPEED_FAST:
context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300);
context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600);
break;
default:
return -ENOTSUP;
}
context->dev_config = dev_config;
return 0;
}
int i2c_bitbang_get_config(struct i2c_bitbang *context, uint32_t *config)
{
if (context->dev_config == 0) {
return -EIO;
}
*config = context->dev_config;
return 0;
}
static void i2c_set_scl(struct i2c_bitbang *context, int state)
{
context->io->set_scl(context->io_context, state);
}
static void i2c_set_sda(struct i2c_bitbang *context, int state)
{
context->io->set_sda(context->io_context, state);
}
static int i2c_get_sda(struct i2c_bitbang *context)
{
return context->io->get_sda(context->io_context);
}
static void i2c_delay(unsigned int cycles_to_wait)
{
uint32_t start = k_cycle_get_32();
/* Wait until the given number of cycles have passed */
while (k_cycle_get_32() - start < cycles_to_wait) {
}
}
static void i2c_start(struct i2c_bitbang *context)
{
if (!i2c_get_sda(context)) {
/*
* SDA is already low, so we need to do something to make it
* high. Try pulsing clock low to get slave to release SDA.
*/
i2c_set_scl(context, 0);
i2c_delay(context->delays[T_LOW]);
i2c_set_scl(context, 1);
i2c_delay(context->delays[T_SU_STA]);
}
i2c_set_sda(context, 0);
i2c_delay(context->delays[T_HD_STA]);
i2c_set_scl(context, 0);
i2c_delay(context->delays[T_LOW]);
}
static void i2c_repeated_start(struct i2c_bitbang *context)
{
i2c_set_sda(context, 1);
i2c_set_scl(context, 1);
i2c_delay(context->delays[T_HIGH]);
i2c_delay(context->delays[T_SU_STA]);
i2c_start(context);
}
static void i2c_stop(struct i2c_bitbang *context)
{
i2c_set_sda(context, 0);
i2c_delay(context->delays[T_LOW]);
i2c_set_scl(context, 1);
i2c_delay(context->delays[T_HIGH]);
i2c_delay(context->delays[T_SU_STP]);
i2c_set_sda(context, 1);
i2c_delay(context->delays[T_BUF]); /* In case we start again too soon */
}
static void i2c_write_bit(struct i2c_bitbang *context, int bit)
{
/* SDA hold time is zero, so no need for a delay here */
i2c_set_sda(context, bit);
i2c_set_scl(context, 1);
i2c_delay(context->delays[T_HIGH]);
i2c_set_scl(context, 0);
i2c_delay(context->delays[T_LOW]);
}
static bool i2c_read_bit(struct i2c_bitbang *context)
{
bool bit;
/* SDA hold time is zero, so no need for a delay here */
i2c_set_sda(context, 1); /* Stop driving low, so slave has control */
i2c_set_scl(context, 1);
i2c_delay(context->delays[T_HIGH]);
bit = i2c_get_sda(context);
i2c_set_scl(context, 0);
i2c_delay(context->delays[T_LOW]);
return bit;
}
static bool i2c_write_byte(struct i2c_bitbang *context, uint8_t byte)
{
uint8_t mask = 1 << 7;
do {
i2c_write_bit(context, byte & mask);
} while (mask >>= 1);
/* Return inverted ACK bit, i.e. 'true' for ACK, 'false' for NACK */
return !i2c_read_bit(context);
}
static uint8_t i2c_read_byte(struct i2c_bitbang *context)
{
unsigned int byte = 1U;
do {
byte <<= 1;
byte |= i2c_read_bit(context);
} while (!(byte & (1 << 8)));
return byte;
}
int i2c_bitbang_transfer(struct i2c_bitbang *context,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address)
{
uint8_t *buf, *buf_end;
unsigned int flags;
int result = -EIO;
if (!num_msgs) {
return 0;
}
/* We want an initial Start condition */
flags = I2C_MSG_RESTART;
/* Make sure we're in a good state so slave recognises the Start */
i2c_set_scl(context, 1);
flags |= I2C_MSG_STOP;
do {
/* Stop flag from previous message? */
if (flags & I2C_MSG_STOP) {
i2c_stop(context);
}
/* Forget old flags except start flag */
flags &= I2C_MSG_RESTART;
/* Start condition? */
if (flags & I2C_MSG_RESTART) {
i2c_start(context);
} else if (msgs->flags & I2C_MSG_RESTART) {
i2c_repeated_start(context);
}
/* Get flags for new message */
flags |= msgs->flags;
/* Send address after any Start condition */
if (flags & I2C_MSG_RESTART) {
unsigned int byte0 = slave_address << 1;
byte0 |= (flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
if (!i2c_write_byte(context, byte0)) {
goto finish; /* No ACK received */
}
flags &= ~I2C_MSG_RESTART;
}
/* Transfer data */
buf = msgs->buf;
buf_end = buf + msgs->len;
if ((flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
/* Read */
while (buf < buf_end) {
*buf++ = i2c_read_byte(context);
/* ACK the byte, except for the last one */
i2c_write_bit(context, buf == buf_end);
}
} else {
/* Write */
while (buf < buf_end) {
if (!i2c_write_byte(context, *buf++)) {
goto finish; /* No ACK received */
}
}
}
/* Next message */
msgs++;
num_msgs--;
} while (num_msgs);
/* Complete without error */
result = 0;
finish:
i2c_stop(context);
return result;
}
int i2c_bitbang_recover_bus(struct i2c_bitbang *context)
{
int i;
/*
* The I2C-bus specification and user manual (NXP UM10204
* rev. 6, section 3.1.16) suggests the master emit 9 SCL
* clock pulses to recover the bus.
*
* The Linux kernel I2C bitbang recovery functionality issues
* a START condition followed by 9 STOP conditions.
*
* Other I2C slave devices (e.g. Microchip ATSHA204a) suggest
* issuing a START condition followed by 9 SCL clock pulses
* with SDA held high/floating, a REPEATED START condition,
* and a STOP condition.
*
* The latter is what is implemented here.
*/
/* Start condition */
i2c_start(context);
/* 9 cycles of SCL with SDA held high */
for (i = 0; i < 9; i++) {
i2c_write_bit(context, 1);
}
/* Another start condition followed by a stop condition */
i2c_repeated_start(context);
i2c_stop(context);
/* Check if bus is clear */
if (i2c_get_sda(context)) {
return 0;
} else {
return -EBUSY;
}
}
void i2c_bitbang_init(struct i2c_bitbang *context,
const struct i2c_bitbang_io *io, void *io_context)
{
context->io = io;
context->io_context = io_context;
i2c_bitbang_configure(context, I2C_SPEED_STANDARD << I2C_SPEED_SHIFT);
}
``` | /content/code_sandbox/drivers/i2c/i2c_bitbang.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,339 |
```c
/*
*
*
* I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
*
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <stm32_ll_i2c.h>
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include "i2c_ll_stm32.h"
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_ll_stm32_v1);
#include "i2c-priv.h"
#define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
#define STM32_I2C_TIMEOUT_USEC 1000
#define I2C_REQUEST_WRITE 0x00
#define I2C_REQUEST_READ 0x01
#define HEADER 0xF0
static void stm32_i2c_generate_start_condition(I2C_TypeDef *i2c)
{
uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1);
if (cr1 & I2C_CR1_STOP) {
LOG_DBG("%s: START while STOP active!", __func__);
LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP);
}
LL_I2C_GenerateStartCondition(i2c);
}
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
LL_I2C_DisableIT_TX(i2c);
LL_I2C_DisableIT_RX(i2c);
LL_I2C_DisableIT_EVT(i2c);
LL_I2C_DisableIT_BUF(i2c);
if (!data->smbalert_active) {
LL_I2C_DisableIT_ERR(i2c);
}
}
static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
LL_I2C_EnableIT_ERR(i2c);
LL_I2C_EnableIT_EVT(i2c);
LL_I2C_EnableIT_BUF(i2c);
}
#endif /* CONFIG_I2C_STM32_INTERRUPT */
static void stm32_i2c_reset(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
uint16_t cr1, cr2, oar1, oar2, trise, ccr;
#if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
uint16_t fltr;
#endif
/* disable i2c and disable IRQ's */
LL_I2C_Disable(i2c);
#ifdef CONFIG_I2C_STM32_INTERRUPT
stm32_i2c_disable_transfer_interrupts(dev);
#endif
/* save all important registers before reset */
cr1 = LL_I2C_ReadReg(i2c, CR1);
cr2 = LL_I2C_ReadReg(i2c, CR2);
oar1 = LL_I2C_ReadReg(i2c, OAR1);
oar2 = LL_I2C_ReadReg(i2c, OAR2);
ccr = LL_I2C_ReadReg(i2c, CCR);
trise = LL_I2C_ReadReg(i2c, TRISE);
#if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
fltr = LL_I2C_ReadReg(i2c, FLTR);
#endif
/* reset i2c hardware */
LL_I2C_EnableReset(i2c);
LL_I2C_DisableReset(i2c);
/* restore all important registers after reset */
LL_I2C_WriteReg(i2c, CR1, cr1);
LL_I2C_WriteReg(i2c, CR2, cr2);
/* bit 14 of OAR1 must always be 1 */
oar1 |= (1 << 14);
LL_I2C_WriteReg(i2c, OAR1, oar1);
LL_I2C_WriteReg(i2c, OAR2, oar2);
LL_I2C_WriteReg(i2c, CCR, ccr);
LL_I2C_WriteReg(i2c, TRISE, trise);
#if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
LL_I2C_WriteReg(i2c, FLTR, fltr);
#endif
}
static void stm32_i2c_master_finish(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
#ifdef CONFIG_I2C_STM32_INTERRUPT
stm32_i2c_disable_transfer_interrupts(dev);
#endif
#if defined(CONFIG_I2C_TARGET)
data->master_active = false;
if (!data->slave_attached && !data->smbalert_active) {
LL_I2C_Disable(i2c);
} else {
stm32_i2c_enable_transfer_interrupts(dev);
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
}
#else
if (!data->smbalert_active) {
LL_I2C_Disable(i2c);
}
#endif
}
static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave,
uint32_t transfer)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
ARG_UNUSED(next_msg_flags);
#ifdef CONFIG_I2C_STM32_INTERRUPT
k_sem_reset(&data->device_sync_sem);
#endif
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.flags = msg->flags;
data->current.is_restart = 0U;
data->current.is_write = (transfer == I2C_REQUEST_WRITE);
data->current.is_arlo = 0U;
data->current.is_err = 0U;
data->current.is_nack = 0U;
data->current.msg = msg;
#if defined(CONFIG_I2C_TARGET)
data->master_active = true;
#endif
data->slave_address = slave;
LL_I2C_Enable(i2c);
LL_I2C_DisableBitPOS(i2c);
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
if (msg->flags & I2C_MSG_RESTART) {
stm32_i2c_generate_start_condition(i2c);
}
}
static int32_t msg_end(const struct device *dev, uint8_t *next_msg_flags,
const char *funcname)
{
struct i2c_stm32_data *data = dev->data;
if (data->current.is_nack || data->current.is_err ||
data->current.is_arlo) {
goto error;
}
if (!next_msg_flags) {
stm32_i2c_master_finish(dev);
}
return 0;
error:
if (data->current.is_arlo) {
LOG_DBG("%s: ARLO %d", funcname,
data->current.is_arlo);
data->current.is_arlo = 0U;
}
if (data->current.is_nack) {
LOG_DBG("%s: NACK", funcname);
data->current.is_nack = 0U;
}
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", funcname,
data->current.is_err);
data->current.is_err = 0U;
}
stm32_i2c_master_finish(dev);
return -EIO;
}
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void stm32_i2c_master_mode_end(const struct device *dev)
{
struct i2c_stm32_data *data = dev->data;
k_sem_give(&data->device_sync_sem);
}
static inline void handle_sb(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint16_t saddr = data->slave_address;
uint8_t slave;
if (I2C_ADDR_10_BITS & data->dev_config) {
slave = (((saddr & 0x0300) >> 7) & 0xFF);
uint8_t header = slave | HEADER;
if (data->current.is_restart == 0U) {
data->current.is_restart = 1U;
} else {
header |= I2C_REQUEST_READ;
data->current.is_restart = 0U;
}
LL_I2C_TransmitData8(i2c, header);
return;
}
slave = (saddr << 1) & 0xFF;
if (data->current.is_write) {
LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
} else {
LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
if (data->current.len == 2) {
LL_I2C_EnableBitPOS(i2c);
}
}
}
static inline void handle_addr(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (I2C_ADDR_10_BITS & data->dev_config) {
if (!data->current.is_write && data->current.is_restart) {
data->current.is_restart = 0U;
LL_I2C_ClearFlag_ADDR(i2c);
stm32_i2c_generate_start_condition(i2c);
return;
}
}
if (data->current.is_write) {
LL_I2C_ClearFlag_ADDR(i2c);
return;
}
/* according to STM32F1 errata we need to handle these corner cases in
* specific way.
* Please ref to STM32F10xxC/D/E I2C peripheral Errata sheet 2.14.1
*/
if (data->current.len == 0U && IS_ENABLED(CONFIG_SOC_SERIES_STM32F1X)) {
LL_I2C_GenerateStopCondition(i2c);
} else if (data->current.len == 1U) {
/* Single byte reception: enable NACK and clear POS */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
#ifdef CONFIG_SOC_SERIES_STM32F1X
LL_I2C_ClearFlag_ADDR(i2c);
LL_I2C_GenerateStopCondition(i2c);
#endif
} else if (data->current.len == 2U) {
#ifdef CONFIG_SOC_SERIES_STM32F1X
LL_I2C_ClearFlag_ADDR(i2c);
#endif
/* 2-byte reception: enable NACK and set POS */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
LL_I2C_EnableBitPOS(i2c);
}
LL_I2C_ClearFlag_ADDR(i2c);
}
static inline void handle_txe(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (data->current.len) {
data->current.len--;
if (data->current.len == 0U) {
/*
* This is the last byte to transmit disable Buffer
* interrupt and wait for a BTF interrupt
*/
LL_I2C_DisableIT_BUF(i2c);
}
LL_I2C_TransmitData8(i2c, *data->current.buf);
data->current.buf++;
} else {
if (data->current.flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
if (LL_I2C_IsActiveFlag_BTF(i2c)) {
/* Read DR to clear BTF flag */
LL_I2C_ReceiveData8(i2c);
}
k_sem_give(&data->device_sync_sem);
}
}
static inline void handle_rxne(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (data->current.len > 0) {
switch (data->current.len) {
case 1:
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
LL_I2C_DisableBitPOS(i2c);
/* Single byte reception */
if (data->current.flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
LL_I2C_DisableIT_BUF(i2c);
data->current.len--;
*data->current.buf = LL_I2C_ReceiveData8(i2c);
data->current.buf++;
k_sem_give(&data->device_sync_sem);
break;
case 2:
/*
* 2-byte reception for N > 3 has already set the NACK
* bit, and must not set the POS bit. See pg. 854 in
* the F4 reference manual (RM0090).
*/
if (data->current.msg->len > 2) {
break;
}
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
LL_I2C_EnableBitPOS(i2c);
__fallthrough;
case 3:
/*
* 2-byte, 3-byte reception and for N-2, N-1,
* N when N > 3
*/
LL_I2C_DisableIT_BUF(i2c);
break;
default:
/* N byte reception when N > 3 */
data->current.len--;
*data->current.buf = LL_I2C_ReceiveData8(i2c);
data->current.buf++;
}
} else {
if (data->current.flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
k_sem_give(&data->device_sync_sem);
}
}
static inline void handle_btf(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (data->current.is_write) {
handle_txe(dev);
} else {
uint32_t counter = 0U;
switch (data->current.len) {
case 2:
/*
* Stop condition must be generated before reading the
* last two bytes.
*/
if (data->current.flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
for (counter = 2U; counter > 0; counter--) {
data->current.len--;
*data->current.buf = LL_I2C_ReceiveData8(i2c);
data->current.buf++;
}
k_sem_give(&data->device_sync_sem);
break;
case 3:
/* Set NACK before reading N-2 byte*/
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
data->current.len--;
*data->current.buf = LL_I2C_ReceiveData8(i2c);
data->current.buf++;
break;
default:
handle_rxne(dev);
}
}
}
#if defined(CONFIG_I2C_TARGET)
static void stm32_i2c_slave_event(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
const struct i2c_target_callbacks *slave_cb =
data->slave_cfg->callbacks;
if (LL_I2C_IsActiveFlag_TXE(i2c) && LL_I2C_IsActiveFlag_BTF(i2c)) {
uint8_t val;
slave_cb->read_processed(data->slave_cfg, &val);
LL_I2C_TransmitData8(i2c, val);
return;
}
if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
uint8_t val = LL_I2C_ReceiveData8(i2c);
if (slave_cb->write_received(data->slave_cfg, val)) {
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
}
return;
}
if (LL_I2C_IsActiveFlag_AF(i2c)) {
LL_I2C_ClearFlag_AF(i2c);
}
if (LL_I2C_IsActiveFlag_STOP(i2c)) {
LL_I2C_ClearFlag_STOP(i2c);
slave_cb->stop(data->slave_cfg);
/* Prepare to ACK next transmissions address byte */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
}
if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
uint32_t dir = LL_I2C_GetTransferDirection(i2c);
if (dir == LL_I2C_DIRECTION_READ) {
slave_cb->write_requested(data->slave_cfg);
LL_I2C_EnableIT_RX(i2c);
} else {
uint8_t val;
slave_cb->read_requested(data->slave_cfg, &val);
LL_I2C_TransmitData8(i2c, val);
LL_I2C_EnableIT_TX(i2c);
}
stm32_i2c_enable_transfer_interrupts(dev);
}
}
/* Attach and start I2C as slave */
int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t bitrate_cfg;
int ret;
if (!config) {
return -EINVAL;
}
if (data->slave_attached) {
return -EBUSY;
}
if (data->master_active) {
return -EBUSY;
}
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
if (ret < 0) {
LOG_ERR("i2c: failure initializing");
return ret;
}
data->slave_cfg = config;
LL_I2C_Enable(i2c);
if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -ENOTSUP;
}
LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
data->slave_attached = true;
LOG_DBG("i2c: target registered");
stm32_i2c_enable_transfer_interrupts(dev);
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
return 0;
}
int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (!data->slave_attached) {
return -EINVAL;
}
if (data->master_active) {
return -EBUSY;
}
stm32_i2c_disable_transfer_interrupts(dev);
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_ClearFlag_STOP(i2c);
LL_I2C_ClearFlag_ADDR(i2c);
if (!data->smbalert_active) {
LL_I2C_Disable(i2c);
}
data->slave_attached = false;
LOG_DBG("i2c: slave unregistered");
return 0;
}
#endif /* defined(CONFIG_I2C_TARGET) */
void stm32_i2c_event_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
#if defined(CONFIG_I2C_TARGET)
if (data->slave_attached && !data->master_active) {
stm32_i2c_slave_event(dev);
return;
}
#endif
if (LL_I2C_IsActiveFlag_SB(i2c)) {
handle_sb(dev);
} else if (LL_I2C_IsActiveFlag_ADD10(i2c)) {
LL_I2C_TransmitData8(i2c, data->slave_address);
} else if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
handle_addr(dev);
} else if (LL_I2C_IsActiveFlag_BTF(i2c)) {
handle_btf(dev);
} else if (LL_I2C_IsActiveFlag_TXE(i2c) && data->current.is_write) {
handle_txe(dev);
} else if (LL_I2C_IsActiveFlag_RXNE(i2c) && !data->current.is_write) {
handle_rxne(dev);
}
}
void stm32_i2c_error_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
#if defined(CONFIG_I2C_TARGET)
if (data->slave_attached && !data->master_active) {
/* No need for a slave error function right now. */
return;
}
#endif
if (LL_I2C_IsActiveFlag_AF(i2c)) {
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_GenerateStopCondition(i2c);
data->current.is_nack = 1U;
goto end;
}
if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
LL_I2C_ClearFlag_ARLO(i2c);
data->current.is_arlo = 1U;
goto end;
}
if (LL_I2C_IsActiveFlag_BERR(i2c)) {
LL_I2C_ClearFlag_BERR(i2c);
data->current.is_err = 1U;
goto end;
}
#if defined(CONFIG_SMBUS_STM32_SMBALERT)
if (LL_I2C_IsActiveSMBusFlag_ALERT(i2c)) {
LL_I2C_ClearSMBusFlag_ALERT(i2c);
if (data->smbalert_cb_func != NULL) {
data->smbalert_cb_func(data->smbalert_cb_dev);
}
goto end;
}
#endif
return;
end:
stm32_i2c_master_mode_end(dev);
}
static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t saddr)
{
struct i2c_stm32_data *data = dev->data;
msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
stm32_i2c_enable_transfer_interrupts(dev);
if (k_sem_take(&data->device_sync_sem,
K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
LOG_DBG("%s: WRITE timeout", __func__);
stm32_i2c_reset(dev);
return -EIO;
}
return msg_end(dev, next_msg_flags, __func__);
}
static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t saddr)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
stm32_i2c_enable_transfer_interrupts(dev);
LL_I2C_EnableIT_RX(i2c);
if (k_sem_take(&data->device_sync_sem,
K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
LOG_DBG("%s: READ timeout", __func__);
stm32_i2c_reset(dev);
return -EIO;
}
return msg_end(dev, next_msg_flags, __func__);
}
#else /* CONFIG_I2C_STM32_INTERRUPT */
static inline int check_errors(const struct device *dev, const char *funcname)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (LL_I2C_IsActiveFlag_AF(i2c)) {
LL_I2C_ClearFlag_AF(i2c);
LOG_DBG("%s: NACK", funcname);
data->current.is_nack = 1U;
goto error;
}
if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
LL_I2C_ClearFlag_ARLO(i2c);
LOG_DBG("%s: ARLO", funcname);
data->current.is_arlo = 1U;
goto error;
}
if (LL_I2C_IsActiveFlag_OVR(i2c)) {
LL_I2C_ClearFlag_OVR(i2c);
LOG_DBG("%s: OVR", funcname);
data->current.is_err = 1U;
goto error;
}
if (LL_I2C_IsActiveFlag_BERR(i2c)) {
LL_I2C_ClearFlag_BERR(i2c);
LOG_DBG("%s: BERR", funcname);
data->current.is_err = 1U;
goto error;
}
return 0;
error:
return -EIO;
}
static int stm32_i2c_wait_timeout(uint16_t *timeout)
{
if (*timeout == 0) {
return 1;
} else {
k_busy_wait(1);
(*timeout)--;
return 0;
}
}
static int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t saddr)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t len = msg->len;
uint16_t timeout;
uint8_t *buf = msg->buf;
int32_t res;
msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
if (msg->flags & I2C_MSG_RESTART) {
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_SB(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
if (I2C_ADDR_10_BITS & data->dev_config) {
uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
uint8_t header = slave | HEADER;
LL_I2C_TransmitData8(i2c, header);
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
slave = data->slave_address & 0xFF;
LL_I2C_TransmitData8(i2c, slave);
} else {
uint8_t slave = (saddr << 1) & 0xFF;
LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
}
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_GenerateStopCondition(i2c);
data->current.is_nack = 1U;
goto end;
}
}
LL_I2C_ClearFlag_ADDR(i2c);
}
while (len) {
timeout = STM32_I2C_TIMEOUT_USEC;
while (1) {
if (LL_I2C_IsActiveFlag_TXE(i2c)) {
break;
}
if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_GenerateStopCondition(i2c);
data->current.is_nack = 1U;
goto end;
}
}
LL_I2C_TransmitData8(i2c, *buf);
buf++;
len--;
}
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
if (msg->flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
end:
check_errors(dev, __func__);
res = msg_end(dev, next_msg_flags, __func__);
if (res < 0) {
stm32_i2c_reset(dev);
}
return res;
}
static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t saddr)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t len = msg->len;
uint16_t timeout;
uint8_t *buf = msg->buf;
int32_t res;
msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
if (msg->flags & I2C_MSG_RESTART) {
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_SB(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
if (I2C_ADDR_10_BITS & data->dev_config) {
uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
uint8_t header = slave | HEADER;
LL_I2C_TransmitData8(i2c, header);
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
slave = saddr & 0xFF;
LL_I2C_TransmitData8(i2c, slave);
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
LL_I2C_ClearFlag_ADDR(i2c);
stm32_i2c_generate_start_condition(i2c);
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_SB(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
header |= I2C_REQUEST_READ;
LL_I2C_TransmitData8(i2c, header);
} else {
uint8_t slave = ((saddr) << 1) & 0xFF;
LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
}
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_ClearFlag_AF(i2c);
LL_I2C_GenerateStopCondition(i2c);
data->current.is_nack = 1U;
goto end;
}
}
/* ADDR must be cleared before NACK generation. Either in 2 byte reception
* byte 1 will be NACK'ed and slave won't sent the last byte
*/
LL_I2C_ClearFlag_ADDR(i2c);
if (len == 1U) {
/* Single byte reception: enable NACK and set STOP */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
} else if (len == 2U) {
/* 2-byte reception: enable NACK and set POS */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
LL_I2C_EnableBitPOS(i2c);
}
}
while (len) {
timeout = STM32_I2C_TIMEOUT_USEC;
while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
timeout = STM32_I2C_TIMEOUT_USEC;
switch (len) {
case 1:
if (msg->flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
len--;
*buf = LL_I2C_ReceiveData8(i2c);
buf++;
break;
case 2:
while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
/*
* Stop condition must be generated before reading the
* last two bytes.
*/
if (msg->flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
}
for (uint32_t counter = 2; counter > 0; counter--) {
len--;
*buf = LL_I2C_ReceiveData8(i2c);
buf++;
}
break;
case 3:
while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
if (stm32_i2c_wait_timeout(&timeout)) {
LL_I2C_GenerateStopCondition(i2c);
data->current.is_err = 1U;
goto end;
}
}
/* Set NACK before reading N-2 byte*/
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
__fallthrough;
default:
len--;
*buf = LL_I2C_ReceiveData8(i2c);
buf++;
}
}
end:
check_errors(dev, __func__);
res = msg_end(dev, next_msg_flags, __func__);
if (res < 0) {
stm32_i2c_reset(dev);
}
return res;
}
#endif /* CONFIG_I2C_STM32_INTERRUPT */
int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
switch (I2C_SPEED_GET(data->dev_config)) {
case I2C_SPEED_STANDARD:
LL_I2C_ConfigSpeed(i2c, clock, 100000, LL_I2C_DUTYCYCLE_2);
break;
case I2C_SPEED_FAST:
LL_I2C_ConfigSpeed(i2c, clock, 400000, LL_I2C_DUTYCYCLE_2);
break;
default:
return -EINVAL;
}
return 0;
}
int stm32_i2c_transaction(const struct device *dev,
struct i2c_msg msg, uint8_t *next_msg_flags,
uint16_t periph)
{
int ret;
if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = stm32_i2c_msg_write(dev, &msg, next_msg_flags, periph);
} else {
ret = stm32_i2c_msg_read(dev, &msg, next_msg_flags, periph);
}
return ret;
}
``` | /content/code_sandbox/drivers/i2c/i2c_ll_stm32_v1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,617 |
```unknown
config I2C_LITEX
bool "LiteX I2C driver"
default y
depends on DT_HAS_LITEX_I2C_ENABLED
select I2C_BITBANG
help
Enable support for Litex I2C driver
``` | /content/code_sandbox/drivers/i2c/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_i2c
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_numaker, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#include <soc.h>
#include <NuMicro.h>
/* i2c Master Mode Status */
#define M_START 0x08 /* Start */
#define M_REPEAT_START 0x10 /* Master Repeat Start */
#define M_TRAN_ADDR_ACK 0x18 /* Master Transmit Address ACK */
#define M_TRAN_ADDR_NACK 0x20 /* Master Transmit Address NACK */
#define M_TRAN_DATA_ACK 0x28 /* Master Transmit Data ACK */
#define M_TRAN_DATA_NACK 0x30 /* Master Transmit Data NACK */
#define M_ARB_LOST 0x38 /* Master Arbitration Los */
#define M_RECE_ADDR_ACK 0x40 /* Master Receive Address ACK */
#define M_RECE_ADDR_NACK 0x48 /* Master Receive Address NACK */
#define M_RECE_DATA_ACK 0x50 /* Master Receive Data ACK */
#define M_RECE_DATA_NACK 0x58 /* Master Receive Data NACK */
#define BUS_ERROR 0x00 /* Bus error */
/* i2c Slave Mode Status */
#define S_REPEAT_START_STOP 0xA0 /* Slave Transmit Repeat Start or Stop */
#define S_TRAN_ADDR_ACK 0xA8 /* Slave Transmit Address ACK */
#define S_TRAN_DATA_ACK 0xB8 /* Slave Transmit Data ACK */
#define S_TRAN_DATA_NACK 0xC0 /* Slave Transmit Data NACK */
#define S_TRAN_LAST_DATA_ACK 0xC8 /* Slave Transmit Last Data ACK */
#define S_RECE_ADDR_ACK 0x60 /* Slave Receive Address ACK */
#define S_RECE_ARB_LOST 0x68 /* Slave Receive Arbitration Lost */
#define S_RECE_DATA_ACK 0x80 /* Slave Receive Data ACK */
#define S_RECE_DATA_NACK 0x88 /* Slave Receive Data NACK */
/* i2c GC Mode Status */
#define GC_ADDR_ACK 0x70 /* GC mode Address ACK */
#define GC_ARB_LOST 0x78 /* GC mode Arbitration Lost */
#define GC_DATA_ACK 0x90 /* GC mode Data ACK */
#define GC_DATA_NACK 0x98 /* GC mode Data NACK */
/* i2c Other Status */
#define ADDR_TRAN_ARB_LOST 0xB0 /* Address Transmit Arbitration Lost */
#define BUS_RELEASED 0xF8 /* Bus Released */
struct i2c_numaker_config {
I2C_T *i2c_base;
const struct reset_dt_spec reset;
uint32_t clk_modidx;
uint32_t clk_src;
uint32_t clk_div;
const struct device *clkctrl_dev;
uint32_t irq_n;
void (*irq_config_func)(const struct device *dev);
const struct pinctrl_dev_config *pincfg;
uint32_t bitrate;
};
struct i2c_numaker_data {
struct k_sem lock;
uint32_t dev_config;
/* Master transfer context */
struct {
struct k_sem xfer_sync;
uint16_t addr;
struct i2c_msg *msgs_beg;
struct i2c_msg *msgs_pos;
struct i2c_msg *msgs_end;
uint8_t *buf_beg;
uint8_t *buf_pos;
uint8_t *buf_end;
} master_xfer;
#ifdef CONFIG_I2C_TARGET
/* Slave transfer context */
struct {
struct i2c_target_config *slave_config;
bool slave_addressed;
} slave_xfer;
#endif
};
/* ACK/NACK last data byte, dependent on whether or not message merge is allowed */
static void m_numaker_i2c_master_xfer_msg_read_last_byte(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
/* Shouldn't invoke with message pointer OOB */
__ASSERT_NO_MSG(data->master_xfer.msgs_pos < data->master_xfer.msgs_end);
/* Should invoke with exactly one data byte remaining for read */
__ASSERT_NO_MSG((data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
__ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 1);
/* Flags of previous message */
bool do_stop_prev = data->master_xfer.msgs_pos->flags & I2C_MSG_STOP;
/* Advance to next messages temporarily */
data->master_xfer.msgs_pos++;
/* Has next message? */
if (data->master_xfer.msgs_pos < data->master_xfer.msgs_end) {
/* Flags of next message */
struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
bool is_read_next = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
bool do_restart_next = data->master_xfer.msgs_pos->flags & I2C_MSG_RESTART;
/*
* Different R/W bit so message merge is disallowed.
* Force I2C Repeat Start on I2C Stop/Repeat Start missing
*/
if (!is_read_next) {
if (!do_stop_prev && !do_restart_next) {
do_restart_next = true;
}
}
if (do_stop_prev || do_restart_next) {
/* NACK last data byte (required for Master Receiver) */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
} else {
/* ACK last data byte, so to merge adjacent messages into one transaction */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
} else {
/* NACK last data byte (required for Master Receiver) */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
/* Roll back message pointer */
data->master_xfer.msgs_pos--;
}
/* End the transfer, involving I2C Stop and signal to thread */
static void m_numaker_i2c_master_xfer_end(const struct device *dev, bool do_stop)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
if (do_stop) {
/* Do I2C Stop */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
}
/* Signal master transfer end */
k_sem_give(&data->master_xfer.xfer_sync);
}
static void m_numaker_i2c_master_xfer_msg_end(const struct device *dev);
/* Read next data byte, involving ACK/NACK last data byte and message merge */
static void m_numaker_i2c_master_xfer_msg_read_next_byte(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
switch (data->master_xfer.buf_end - data->master_xfer.buf_pos) {
case 0:
/* Last data byte ACKed, we'll do message merge */
m_numaker_i2c_master_xfer_msg_end(dev);
break;
case 1:
/* Read last data byte for this message */
m_numaker_i2c_master_xfer_msg_read_last_byte(dev);
break;
default:
/* ACK non-last data byte */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
}
/* End one message transfer, involving message merge and transfer end */
static void m_numaker_i2c_master_xfer_msg_end(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
/* Shouldn't invoke with message pointer OOB */
__ASSERT_NO_MSG(data->master_xfer.msgs_pos < data->master_xfer.msgs_end);
/* Should have transferred up */
__ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 0);
/* Flags of previous message */
bool is_read_prev = (data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
bool do_stop_prev = data->master_xfer.msgs_pos->flags & I2C_MSG_STOP;
/* Advance to next messages */
data->master_xfer.msgs_pos++;
/* Has next message? */
if (data->master_xfer.msgs_pos < data->master_xfer.msgs_end) {
/* Flags of next message */
struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
bool is_read_next = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
bool do_restart_next = data->master_xfer.msgs_pos->flags & I2C_MSG_RESTART;
/*
* Different R/W bit so message merge is disallowed.
* Force I2C Repeat Start on I2C Stop/Repeat Start missing
*/
if (!is_read_prev != !is_read_next) { /* Logical XOR idiom */
if (!do_stop_prev && !do_restart_next) {
LOG_WRN("Cannot merge adjacent messages, force I2C Repeat Start");
do_restart_next = true;
}
}
if (do_stop_prev) {
/* Do I2C Stop and then Start */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk |
I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
} else if (do_restart_next) {
/* Do I2C Repeat Start */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
} else {
/* Merge into the same transaction */
/* Prepare buffer for current message */
data->master_xfer.buf_beg = data->master_xfer.msgs_pos->buf;
data->master_xfer.buf_pos = data->master_xfer.msgs_pos->buf;
data->master_xfer.buf_end = data->master_xfer.msgs_pos->buf +
data->master_xfer.msgs_pos->len;
if (is_read_prev) {
m_numaker_i2c_master_xfer_msg_read_next_byte(dev);
} else {
/*
* Interrupt flag not cleared, expect to re-enter ISR with
* context unchanged, except buffer changed for message change.
*/
}
}
} else {
if (!do_stop_prev) {
LOG_WRN("Last message not marked I2C Stop");
}
m_numaker_i2c_master_xfer_end(dev, do_stop_prev);
}
}
static int i2c_numaker_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
uint32_t bitrate;
/* Check address size */
if (dev_config & I2C_ADDR_10_BITS) {
LOG_ERR("10-bits address not supported");
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
bitrate = KHZ(100);
break;
case I2C_SPEED_FAST:
bitrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
bitrate = MHZ(1);
break;
default:
LOG_ERR("Speed code %d not supported", I2C_SPEED_GET(dev_config));
return -ENOTSUP;
}
I2C_T *i2c_base = config->i2c_base;
int err = 0;
k_sem_take(&data->lock, K_FOREVER);
irq_disable(config->irq_n);
#ifdef CONFIG_I2C_TARGET
if (data->slave_xfer.slave_addressed) {
LOG_ERR("Reconfigure with slave being busy");
err = -EBUSY;
goto done;
}
#endif
I2C_Open(i2c_base, bitrate);
/* INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. */
i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk);
data->dev_config = dev_config;
done:
irq_enable(config->irq_n);
k_sem_give(&data->lock);
return err;
}
static int i2c_numaker_get_config(const struct device *dev, uint32_t *dev_config)
{
struct i2c_numaker_data *data = dev->data;
if (!dev_config) {
return -EINVAL;
}
k_sem_take(&data->lock, K_FOREVER);
*dev_config = data->dev_config;
k_sem_give(&data->lock);
return 0;
}
/*
* Master active transfer:
* 1. Do I2C Start to start the transfer (thread)
* 2. I2C FSM (ISR)
* 3. Force I2C Stop to end the transfer (thread)
* Slave passive transfer:
* 1. Prepare callback (thread)
* 2. Do data transfer via above callback (ISR)
*/
static int i2c_numaker_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
int err = 0;
k_sem_take(&data->lock, K_FOREVER);
irq_disable(config->irq_n);
if (data->slave_xfer.slave_addressed) {
LOG_ERR("Master transfer with slave being busy");
err = -EBUSY;
goto cleanup;
}
if (num_msgs == 0) {
goto cleanup;
}
/* Prepare to start transfer */
data->master_xfer.addr = addr;
data->master_xfer.msgs_beg = msgs;
data->master_xfer.msgs_pos = msgs;
data->master_xfer.msgs_end = msgs + num_msgs;
/* Do I2C Start to start the transfer */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
irq_enable(config->irq_n);
k_sem_take(&data->master_xfer.xfer_sync, K_FOREVER);
irq_disable(config->irq_n);
/* Check transfer result */
if (data->master_xfer.msgs_pos != data->master_xfer.msgs_end) {
bool is_read;
bool is_10bit;
is_read = (data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
is_10bit = data->master_xfer.msgs_pos->flags & I2C_MSG_ADDR_10_BITS;
LOG_ERR("Failed message:");
LOG_ERR("MSG IDX: %d", data->master_xfer.msgs_pos - data->master_xfer.msgs_beg);
LOG_ERR("ADDR (%d-bit): 0x%04X", is_10bit ? 10 : 7, addr);
LOG_ERR("DIR: %s", is_read ? "R" : "W");
LOG_ERR("Expected %d bytes transferred, but actual %d",
data->master_xfer.msgs_pos->len,
data->master_xfer.buf_pos - data->master_xfer.buf_beg);
err = -EIO;
goto i2c_stop;
}
i2c_stop:
/* Do I2C Stop to release bus ownership */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
#ifdef CONFIG_I2C_TARGET
/* Enable slave mode if one slave is registered */
if (data->slave_xfer.slave_config) {
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
}
#endif
cleanup:
irq_enable(config->irq_n);
k_sem_give(&data->lock);
return err;
}
#ifdef CONFIG_I2C_TARGET
static int i2c_numaker_slave_register(const struct device *dev,
struct i2c_target_config *slave_config)
{
if (!slave_config || !slave_config->callbacks) {
return -EINVAL;
}
if (slave_config->flags & I2C_ADDR_10_BITS) {
LOG_ERR("10-bits address not supported");
return -ENOTSUP;
}
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
int err = 0;
k_sem_take(&data->lock, K_FOREVER);
irq_disable(config->irq_n);
if (data->slave_xfer.slave_config) {
err = -EBUSY;
goto cleanup;
}
data->slave_xfer.slave_config = slave_config;
/* Slave address */
I2C_SetSlaveAddr(i2c_base,
0,
slave_config->address,
I2C_GCMODE_DISABLE);
/* Slave address state */
data->slave_xfer.slave_addressed = false;
/* Enable slave mode */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
cleanup:
irq_enable(config->irq_n);
k_sem_give(&data->lock);
return err;
}
static int i2c_numaker_slave_unregister(const struct device *dev,
struct i2c_target_config *slave_config)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
int err = 0;
if (!slave_config) {
return -EINVAL;
}
k_sem_take(&data->lock, K_FOREVER);
irq_disable(config->irq_n);
if (data->slave_xfer.slave_config != slave_config) {
err = -EINVAL;
goto cleanup;
}
if (data->slave_xfer.slave_addressed) {
LOG_ERR("Unregister slave driver with slave being busy");
err = -EBUSY;
goto cleanup;
}
/* Slave address: Zero */
I2C_SetSlaveAddr(i2c_base,
0,
0,
I2C_GCMODE_DISABLE);
/* Slave address state */
data->slave_xfer.slave_addressed = false;
/* Disable slave mode */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
data->slave_xfer.slave_config = NULL;
cleanup:
irq_enable(config->irq_n);
k_sem_give(&data->lock);
return err;
}
#endif
static int i2c_numaker_recover_bus(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
k_sem_take(&data->lock, K_FOREVER);
/* Do I2C Stop to release bus ownership */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
k_sem_give(&data->lock);
return 0;
}
static void i2c_numaker_isr(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
I2C_T *i2c_base = config->i2c_base;
#ifdef CONFIG_I2C_TARGET
struct i2c_target_config *slave_config = data->slave_xfer.slave_config;
const struct i2c_target_callbacks *slave_callbacks =
slave_config ? slave_config->callbacks : NULL;
uint8_t data_byte;
#endif
uint32_t status;
if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
I2C_ClearTimeoutFlag(i2c_base);
return;
}
status = I2C_GET_STATUS(i2c_base);
switch (status) {
case M_START: /* Start */
case M_REPEAT_START: /* Master Repeat Start */
/* Prepare buffer for current message */
data->master_xfer.buf_beg = data->master_xfer.msgs_pos->buf;
data->master_xfer.buf_pos = data->master_xfer.msgs_pos->buf;
data->master_xfer.buf_end = data->master_xfer.msgs_pos->buf +
data->master_xfer.msgs_pos->len;
/* Write I2C address */
struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
bool is_read = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
uint16_t addr = data->master_xfer.addr;
int addr_rw = is_read ? ((addr << 1) | 1) : (addr << 1);
I2C_SET_DATA(i2c_base, (uint8_t) (addr_rw & 0xFF));
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
break;
case M_TRAN_ADDR_ACK: /* Master Transmit Address ACK */
case M_TRAN_DATA_ACK: /* Master Transmit Data ACK */
__ASSERT_NO_MSG(data->master_xfer.buf_pos);
if (data->master_xfer.buf_pos < data->master_xfer.buf_end) {
I2C_SET_DATA(i2c_base, *data->master_xfer.buf_pos++);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
} else {
/* End this message */
m_numaker_i2c_master_xfer_msg_end(dev);
}
break;
case M_TRAN_ADDR_NACK: /* Master Transmit Address NACK */
case M_TRAN_DATA_NACK: /* Master Transmit Data NACK */
case M_RECE_ADDR_NACK: /* Master Receive Address NACK */
case M_ARB_LOST: /* Master Arbitration Lost */
m_numaker_i2c_master_xfer_end(dev, true);
break;
case M_RECE_ADDR_ACK: /* Master Receive Address ACK */
case M_RECE_DATA_ACK: /* Master Receive Data ACK */
__ASSERT_NO_MSG(data->master_xfer.buf_pos);
if (status == M_RECE_ADDR_ACK) {
__ASSERT_NO_MSG(data->master_xfer.buf_pos < data->master_xfer.buf_end);
} else if (status == M_RECE_DATA_ACK) {
__ASSERT_NO_MSG((data->master_xfer.buf_end -
data->master_xfer.buf_pos) >= 1);
*data->master_xfer.buf_pos++ = I2C_GET_DATA(i2c_base);
}
m_numaker_i2c_master_xfer_msg_read_next_byte(dev);
break;
case M_RECE_DATA_NACK: /* Master Receive Data NACK */
__ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 1);
*data->master_xfer.buf_pos++ = I2C_GET_DATA(i2c_base);
/* End this message */
m_numaker_i2c_master_xfer_msg_end(dev);
break;
case BUS_ERROR: /* Bus error */
m_numaker_i2c_master_xfer_end(dev, true);
break;
#ifdef CONFIG_I2C_TARGET
/* NOTE: Don't disable interrupt here because slave mode relies on */
/* for passive transfer in ISR. */
/* Slave Transmit */
case S_TRAN_ADDR_ACK: /* Slave Transmit Address ACK */
case ADDR_TRAN_ARB_LOST: /* Slave Transmit Arbitration Lost */
data->slave_xfer.slave_addressed = true;
if (slave_callbacks->read_requested(slave_config, &data_byte) == 0) {
/* Non-last data byte */
I2C_SET_DATA(i2c_base, data_byte);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
} else {
/* Go S_TRAN_LAST_DATA_ACK on error */
I2C_SET_DATA(i2c_base, 0xFF);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
break;
case S_TRAN_DATA_ACK: /* Slave Transmit Data ACK */
if (slave_callbacks->read_processed(slave_config, &data_byte) == 0) {
/* Non-last data byte */
I2C_SET_DATA(i2c_base, data_byte);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
} else {
/* Go S_TRAN_LAST_DATA_ACK on error */
I2C_SET_DATA(i2c_base, 0xFF);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
break;
case S_TRAN_DATA_NACK: /* Slave Transmit Data NACK */
case S_TRAN_LAST_DATA_ACK: /* Slave Transmit Last Data ACK */
/* Go slave end */
data->slave_xfer.slave_addressed = false;
slave_callbacks->stop(slave_config);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
break;
/* Slave Receive */
case S_RECE_DATA_ACK: /* Slave Receive Data ACK */
data_byte = I2C_GET_DATA(i2c_base);
if (slave_callbacks->write_received(slave_config, data_byte) == 0) {
/* Write OK, ACK next data byte */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
} else {
/* Write FAILED, NACK next data byte */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
break;
case S_RECE_DATA_NACK: /* Slave Receive Data NACK */
/* Go slave end */
data->slave_xfer.slave_addressed = false;
slave_callbacks->stop(slave_config);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
break;
case S_RECE_ADDR_ACK: /* Slave Receive Address ACK */
case S_RECE_ARB_LOST: /* Slave Receive Arbitration Lost */
data->slave_xfer.slave_addressed = true;
if (slave_callbacks->write_requested(slave_config) == 0) {
/* Write ready, ACK next byte */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
} else {
/* Write not ready, NACK next byte */
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
}
break;
case S_REPEAT_START_STOP: /* Slave Transmit/Receive Repeat Start or Stop */
/* Go slave end */
data->slave_xfer.slave_addressed = false;
slave_callbacks->stop(slave_config);
I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
break;
#endif /* CONFIG_I2C_TARGET */
case BUS_RELEASED: /* Bus Released */
/* Ignore the interrupt raised by BUS_RELEASED. */
break;
default:
__ASSERT(false, "Uncaught I2C FSM state");
m_numaker_i2c_master_xfer_end(dev, true);
}
}
static int i2c_numaker_init(const struct device *dev)
{
const struct i2c_numaker_config *config = dev->config;
struct i2c_numaker_data *data = dev->data;
int err = 0;
struct numaker_scc_subsys scc_subsys;
/* Validate this module's reset object */
if (!device_is_ready(config->reset.dev)) {
LOG_ERR("reset controller not ready");
return -ENODEV;
}
/* Clean mutable context */
memset(data, 0x00, sizeof(*data));
k_sem_init(&data->lock, 1, 1);
k_sem_init(&data->master_xfer.xfer_sync, 0, 1);
SYS_UnlockReg();
memset(&scc_subsys, 0x00, sizeof(scc_subsys));
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
scc_subsys.pcc.clk_modidx = config->clk_modidx;
scc_subsys.pcc.clk_src = config->clk_src;
scc_subsys.pcc.clk_div = config->clk_div;
/* Equivalent to CLK_EnableModuleClock() */
err = clock_control_on(config->clkctrl_dev, (clock_control_subsys_t) &scc_subsys);
if (err != 0) {
goto cleanup;
}
/* Equivalent to CLK_SetModuleClock() */
err = clock_control_configure(config->clkctrl_dev,
(clock_control_subsys_t) &scc_subsys,
NULL);
if (err != 0) {
goto cleanup;
}
/* Configure pinmux (NuMaker's SYS MFP) */
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
goto cleanup;
}
/* Reset I2C to default state, same as BSP's SYS_ResetModule(id_rst) */
reset_line_toggle_dt(&config->reset);
err = i2c_numaker_configure(dev, I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
if (err != 0) {
goto cleanup;
}
config->irq_config_func(dev);
cleanup:
SYS_LockReg();
return err;
}
static const struct i2c_driver_api i2c_numaker_driver_api = {
.configure = i2c_numaker_configure,
.get_config = i2c_numaker_get_config,
.transfer = i2c_numaker_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_numaker_slave_register,
.target_unregister = i2c_numaker_slave_unregister,
#endif
.recover_bus = i2c_numaker_recover_bus,
};
#define I2C_NUMAKER_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static void i2c_numaker_irq_config_func_##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
i2c_numaker_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
\
irq_enable(DT_INST_IRQN(inst)); \
} \
\
static const struct i2c_numaker_config i2c_numaker_config_##inst = { \
.i2c_base = (I2C_T *) DT_INST_REG_ADDR(inst), \
.reset = RESET_DT_SPEC_INST_GET(inst), \
.clk_modidx = DT_INST_CLOCKS_CELL(inst, clock_module_index), \
.clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
.clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
.clkctrl_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(inst))),\
.irq_n = DT_INST_IRQN(inst), \
.irq_config_func = i2c_numaker_irq_config_func_##inst, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
}; \
\
static struct i2c_numaker_data i2c_numaker_data_##inst; \
\
I2C_DEVICE_DT_INST_DEFINE(inst, \
i2c_numaker_init, \
NULL, \
&i2c_numaker_data_##inst, \
&i2c_numaker_config_##inst, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_numaker_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_NUMAKER_INIT);
``` | /content/code_sandbox/drivers/i2c/i2c_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,348 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_sedi_i2c
#include <stdint.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <sedi_driver_i2c.h>
#include <zephyr/pm/device.h>
#define I2C_SEDI_TIMEOUT_MS (1000)
struct i2c_sedi_context {
DEVICE_MMIO_RAM;
int sedi_device;
struct k_sem *sem;
struct k_mutex *mutex;
int err;
uint16_t addr_10bit;
};
struct i2c_sedi_config {
DEVICE_MMIO_ROM;
sedi_i2c_event_cb_t cb_sedi;
void (*irq_config)(const struct device *dev);
};
static int i2c_sedi_api_configure(const struct device *dev, uint32_t dev_config)
{
int ret;
int speed = I2C_SPEED_GET(dev_config);
int sedi_speed;
struct i2c_sedi_context *const context = dev->data;
context->addr_10bit = (dev_config & I2C_ADDR_10_BITS) ? SEDI_I2C_ADDRESS_10BIT : 0;
if (speed == I2C_SPEED_STANDARD) {
sedi_speed = SEDI_I2C_BUS_SPEED_STANDARD;
} else if (speed == I2C_SPEED_FAST) {
sedi_speed = SEDI_I2C_BUS_SPEED_FAST;
} else if (speed == I2C_SPEED_FAST_PLUS) {
sedi_speed = SEDI_I2C_BUS_SPEED_FAST_PLUS;
} else if (speed == I2C_SPEED_HIGH) {
sedi_speed = SEDI_I2C_BUS_SPEED_HIGH;
} else {
return -EINVAL;
}
k_mutex_lock(context->mutex, K_FOREVER);
ret = sedi_i2c_control(context->sedi_device, SEDI_I2C_BUS_SPEED, sedi_speed);
k_mutex_unlock(context->mutex);
if (ret != 0) {
return -EIO;
} else {
return 0;
}
}
static int i2c_sedi_api_full_io(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
int ret = 0;
struct i2c_sedi_context *context = dev->data;
if (!num_msgs) {
return 0;
}
__ASSERT_NO_MSG(msgs);
k_mutex_lock(context->mutex, K_FOREVER);
pm_device_busy_set(dev);
for (int i = 0; i < num_msgs; i++) {
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = sedi_i2c_master_write_async(
context->sedi_device, addr | context->addr_10bit, msgs[i].buf,
msgs[i].len, (msgs[i].flags & I2C_MSG_STOP) == 0x0);
} else {
ret = sedi_i2c_master_read_async(
context->sedi_device, addr | context->addr_10bit, msgs[i].buf,
msgs[i].len, (msgs[i].flags & I2C_MSG_STOP) == 0x0);
}
if (ret != 0) {
ret = -EIO;
break;
}
ret = k_sem_take(context->sem, K_MSEC(I2C_SEDI_TIMEOUT_MS));
if (ret != 0) {
break;
}
if (context->err != 0) {
ret = -EIO;
break;
}
}
if (ret != 0) {
/* Abort current transfer */
sedi_i2c_control(context->sedi_device, SEDI_I2C_ABORT_TRANSFER, 0);
ret = -EIO;
}
pm_device_busy_clear(dev);
k_mutex_unlock(context->mutex);
return ret;
}
static const struct i2c_driver_api i2c_sedi_apis = {
.configure = i2c_sedi_api_configure,
.transfer = i2c_sedi_api_full_io
};
#ifdef CONFIG_PM_DEVICE
static int i2c_sedi_suspend_device(const struct device *dev)
{
struct i2c_sedi_context *const context = dev->data;
int ret;
if (pm_device_is_busy(dev)) {
return -EBUSY;
}
ret = sedi_i2c_set_power(context->sedi_device, SEDI_POWER_SUSPEND);
if (ret != 0) {
return -EIO;
}
return 0;
}
static int i2c_sedi_resume_device_from_suspend(const struct device *dev)
{
struct i2c_sedi_context *const context = dev->data;
int ret;
ret = sedi_i2c_set_power(context->sedi_device, SEDI_POWER_FULL);
if (ret != 0) {
return -EIO;
}
return 0;
}
static int i2c_sedi_pm_action(const struct device *dev, enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
ret = i2c_sedi_suspend_device(dev);
break;
case PM_DEVICE_ACTION_RESUME:
ret = i2c_sedi_resume_device_from_suspend(dev);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int i2c_sedi_init(const struct device *dev)
{
int ret;
const struct i2c_sedi_config *const config = dev->config;
struct i2c_sedi_context *const context = dev->data;
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
ret = sedi_i2c_init(context->sedi_device, config->cb_sedi, DEVICE_MMIO_GET(dev));
if (ret != 0) {
return -EIO;
}
ret = sedi_i2c_set_power(context->sedi_device, SEDI_POWER_FULL);
if (ret != 0) {
return -EIO;
}
config->irq_config(dev);
return 0;
}
static void i2c_sedi_isr(const struct device *dev)
{
struct i2c_sedi_context *const context = dev->data;
sedi_i2c_isr_handler(context->sedi_device);
}
#define I2C_SEDI_IRQ_FLAGS_SENSE0(n) 0
#define I2C_SEDI_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
#define I2C_SEDI_IRQ_FLAGS(n) _CONCAT(I2C_SEDI_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))(n)
#define I2C_DEVICE_INIT_SEDI(n) \
static K_SEM_DEFINE(i2c_sedi_sem_##n, 0, 1); \
static K_MUTEX_DEFINE(i2c_sedi_mutex_##n); \
static struct i2c_sedi_context i2c_sedi_data_##n = { \
.sedi_device = DT_INST_PROP(n, peripheral_id), \
.sem = &i2c_sedi_sem_##n, \
.mutex = &i2c_sedi_mutex_##n, \
}; \
static void i2c_sedi_callback_##n(const uint32_t event) \
{ \
if (event == SEDI_I2C_EVENT_TRANSFER_DONE) { \
i2c_sedi_data_##n.err = 0; \
} else { \
i2c_sedi_data_##n.err = 1; \
} \
k_sem_give(i2c_sedi_data_##n.sem); \
}; \
static void i2c_sedi_irq_config_##n(const struct device *dev) \
{ \
ARG_UNUSED(dev); \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_sedi_isr, \
DEVICE_DT_INST_GET(n), I2C_SEDI_IRQ_FLAGS(n)); \
irq_enable(DT_INST_IRQN(n)); \
}; \
static const struct i2c_sedi_config i2c_sedi_config_##n = { \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
.cb_sedi = &i2c_sedi_callback_##n, \
.irq_config = &i2c_sedi_irq_config_##n, \
}; \
PM_DEVICE_DT_DEFINE(DT_NODELABEL(i2c##n), i2c_sedi_pm_action); \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_sedi_init, PM_DEVICE_DT_GET(DT_NODELABEL(i2c##n)), \
&i2c_sedi_data_##n, &i2c_sedi_config_##n, PRE_KERNEL_2, \
CONFIG_I2C_INIT_PRIORITY, &i2c_sedi_apis);
DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_SEDI)
``` | /content/code_sandbox/drivers/i2c/i2c_sedi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,938 |
```c
/*
*
*/
#define DT_DRV_COMPAT altr_nios2_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/sys/util.h>
#include <altera_common.h>
#include "altera_avalon_i2c.h"
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_nios2);
#define NIOS2_I2C_TIMEOUT_USEC 1000
struct i2c_nios2_data {
ALT_AVALON_I2C_DEV_t i2c_dev;
IRQ_DATA_t irq_data;
struct k_sem sem_lock;
};
static int
i2c_nios2_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_nios2_data *data = (struct i2c_nios2_data *)dev->data;
int32_t rc = 0;
k_sem_take(&data->sem_lock, K_FOREVER);
if (!(I2C_MODE_CONTROLLER & dev_config)) {
LOG_ERR("i2c config mode error\n");
rc = -EINVAL;
goto i2c_cfg_err;
}
if (I2C_ADDR_10_BITS & dev_config) {
LOG_ERR("i2c config addressing error\n");
rc = -EINVAL;
goto i2c_cfg_err;
}
if (I2C_SPEED_GET(dev_config) != I2C_SPEED_STANDARD) {
LOG_ERR("i2c config speed error\n");
rc = -EINVAL;
goto i2c_cfg_err;
}
alt_avalon_i2c_init(&data->i2c_dev);
i2c_cfg_err:
k_sem_give(&data->sem_lock);
return rc;
}
static int i2c_nios2_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_nios2_data *data = (struct i2c_nios2_data *)dev->data;
ALT_AVALON_I2C_STATUS_CODE status;
uint32_t restart, stop;
int32_t i, timeout, rc = 0;
k_sem_take(&data->sem_lock, K_FOREVER);
/* register the optional interrupt callback */
alt_avalon_i2c_register_optional_irq_handler(
&data->i2c_dev, &data->irq_data);
/* Iterate over all the messages */
for (i = 0; i < num_msgs; i++) {
/* convert restart flag */
if (msgs->flags & I2C_MSG_RESTART) {
restart = ALT_AVALON_I2C_RESTART;
} else {
restart = ALT_AVALON_I2C_NO_RESTART;
}
/* convert stop flag */
if (msgs->flags & I2C_MSG_STOP) {
stop = ALT_AVALON_I2C_STOP;
} else {
stop = ALT_AVALON_I2C_NO_STOP;
}
/* Set the slave device address */
alt_avalon_i2c_master_target_set(&data->i2c_dev, addr);
/* Start the transfer */
if (msgs->flags & I2C_MSG_READ) {
status = alt_avalon_i2c_master_receive_using_interrupts(
&data->i2c_dev,
msgs->buf, msgs->len,
restart, stop);
} else {
status = alt_avalon_i2c_master_transmit_using_interrupts
(&data->i2c_dev,
msgs->buf, msgs->len,
restart, stop);
}
/* Return an error if the transfer didn't
* start successfully e.g., if the bus was busy
*/
if (status != ALT_AVALON_I2C_SUCCESS) {
LOG_ERR("i2c transfer error %lu\n", status);
rc = -EIO;
goto i2c_transfer_err;
}
timeout = NIOS2_I2C_TIMEOUT_USEC;
while (timeout) {
k_busy_wait(1);
status = alt_avalon_i2c_interrupt_transaction_status(
&data->i2c_dev);
if (status == ALT_AVALON_I2C_SUCCESS) {
break;
}
timeout--;
}
if (timeout <= 0) {
LOG_ERR("i2c busy or timeout error %lu\n", status);
rc = -EIO;
goto i2c_transfer_err;
}
/* move to the next message */
msgs++;
}
i2c_transfer_err:
alt_avalon_i2c_disable(&data->i2c_dev);
k_sem_give(&data->sem_lock);
return rc;
}
static void i2c_nios2_isr(const struct device *dev)
{
struct i2c_nios2_data *data = (struct i2c_nios2_data *)dev->data;
/* Call Altera HAL driver ISR */
alt_handle_irq(&data->i2c_dev, DT_INST_IRQN(0));
}
static int i2c_nios2_init(const struct device *dev);
static const struct i2c_driver_api i2c_nios2_driver_api = {
.configure = i2c_nios2_configure,
.transfer = i2c_nios2_transfer,
};
static struct i2c_nios2_data i2c_nios2_dev_data = {
.i2c_dev = {
.i2c_base = (alt_u32 *)DT_INST_REG_ADDR(0),
.irq_controller_ID = I2C_0_IRQ_INTERRUPT_CONTROLLER_ID,
.irq_ID = DT_INST_IRQN(0),
.ip_freq_in_hz = DT_INST_PROP(0, clock_frequency),
},
};
static int i2c_nios2_init(const struct device *dev)
{
struct i2c_nios2_data *data = (struct i2c_nios2_data *)dev->data;
int rc;
/* initialize semaphore */
k_sem_init(&data->sem_lock, 1, 1);
rc = i2c_nios2_configure(dev,
I2C_MODE_CONTROLLER |
I2C_SPEED_SET(I2C_SPEED_STANDARD));
if (rc) {
LOG_ERR("i2c configure failed %d\n", rc);
return rc;
}
/* clear ISR register content */
alt_avalon_i2c_int_clear(&data->i2c_dev,
ALT_AVALON_I2C_ISR_ALL_CLEARABLE_INTS_MSK);
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
i2c_nios2_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
I2C_DEVICE_DT_INST_DEFINE(0, i2c_nios2_init, NULL,
&i2c_nios2_dev_data, NULL,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_nios2_driver_api);
``` | /content/code_sandbox/drivers/i2c/i2c_nios2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,561 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_ra_iic
#include <math.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include "r_iic_master.h"
#include <errno.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(renesas_ra_iic);
typedef void (*init_func_t)(const struct device *dev);
static const double RA_IIC_MASTER_DIV_TIME_NS = 1000000000;
struct i2c_ra_iic_config {
void (*irq_config_func)(const struct device *dev);
const struct pinctrl_dev_config *pcfg;
uint32_t noise_filter_stage;
double rise_time_s;
double fall_time_s;
uint32_t duty_cycle_percent;
};
struct i2c_ra_iic_data {
iic_master_instance_ctrl_t ctrl;
i2c_master_cfg_t fsp_config;
struct k_mutex bus_mutex;
struct k_sem complete_sem;
i2c_master_event_t event;
iic_master_extended_cfg_t iic_master_ext_cfg;
uint32_t dev_config;
};
/* IIC master clock setting calculation function. */
static void calc_iic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
iic_master_clock_settings_t *clk_cfg);
/* FSP interruption handlers. */
void iic_master_rxi_isr(void);
void iic_master_txi_isr(void);
void iic_master_tei_isr(void);
void iic_master_eri_isr(void);
struct ra_iic_master_bitrate {
uint32_t bitrate;
uint32_t duty;
uint32_t divider;
uint32_t brl;
uint32_t brh;
uint32_t duty_error_percent;
};
static int i2c_ra_iic_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
if (!(dev_config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Only I2C Master mode supported.");
return -EIO;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
data->fsp_config.rate = I2C_MASTER_RATE_STANDARD;
break;
case I2C_SPEED_FAST:
data->fsp_config.rate = I2C_MASTER_RATE_FAST;
break;
case I2C_SPEED_FAST_PLUS:
data->fsp_config.rate = I2C_MASTER_RATE_FASTPLUS;
break;
default:
LOG_ERR("%s: Invalid I2C speed rate flag: %d", __func__, I2C_SPEED_GET(dev_config));
return -EIO;
}
/* Recalc clock setting after updating config. */
calc_iic_master_clock_setting(dev, data->fsp_config.rate,
&data->iic_master_ext_cfg.clock_settings);
R_IIC_MASTER_Close(&data->ctrl);
R_IIC_MASTER_Open(&data->ctrl, &data->fsp_config);
/* save current devconfig. */
data->dev_config = dev_config;
return 0;
}
static int i2c_ra_iic_get_config(const struct device *dev, uint32_t *dev_config)
{
struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
*dev_config = data->dev_config;
return 0;
}
#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK)
static int i2c_ra_iic_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *const)dev->data;
struct i2c_msg *current, *next;
fsp_err_t fsp_err = FSP_SUCCESS;
int ret = 0;
if (!num_msgs) {
return 0;
}
/* Check for validity of all messages before transfer */
current = msgs;
/*
* Set I2C_MSG_RESTART flag on first message in order to send start
* condition
*/
current->flags |= I2C_MSG_RESTART;
for (int i = 1; i <= num_msgs; i++) {
if (i < num_msgs) {
next = current + 1;
/*
* Restart condition between messages
* of different directions is required
*/
if (OPERATION(current) != OPERATION(next)) {
if (!(next->flags & I2C_MSG_RESTART)) {
LOG_ERR("%s: Restart condition between messages of "
"different directions is required."
"Current/Total: [%d/%d]",
__func__, i, num_msgs);
ret = -EIO;
break;
}
}
/* Stop condition is only allowed on last message */
if (current->flags & I2C_MSG_STOP) {
LOG_ERR("%s: Invalid stop flag. Stop condition is only allowed on "
"last message. "
"Current/Total: [%d/%d]",
__func__, i, num_msgs);
ret = -EIO;
break;
}
} else {
current->flags |= I2C_MSG_STOP;
}
current++;
}
if (ret) {
return ret;
}
k_mutex_lock(&data->bus_mutex, K_FOREVER);
/* Set destination address with configured address mode before sending msg. */
i2c_master_addr_mode_t addr_mode = 0;
if (I2C_MSG_ADDR_10_BITS & data->dev_config) {
addr_mode = I2C_MASTER_ADDR_MODE_10BIT;
} else {
addr_mode = I2C_MASTER_ADDR_MODE_7BIT;
}
R_IIC_MASTER_SlaveAddressSet(&data->ctrl, addr, addr_mode);
/* Process input `msgs`. */
current = msgs;
while (num_msgs > 0) {
if (num_msgs > 1) {
next = current + 1;
} else {
next = NULL;
}
if (current->flags & I2C_MSG_READ) {
fsp_err =
R_IIC_MASTER_Read(&data->ctrl, current->buf, current->len,
next != NULL && (next->flags & I2C_MSG_RESTART));
} else {
fsp_err =
R_IIC_MASTER_Write(&data->ctrl, current->buf, current->len,
next != NULL && (next->flags & I2C_MSG_RESTART));
}
if (fsp_err != FSP_SUCCESS) {
switch (fsp_err) {
case FSP_ERR_INVALID_SIZE:
LOG_ERR("%s: Provided number of bytes more than uint16_t size "
"(65535) while DTC is used for data transfer.",
__func__);
break;
case FSP_ERR_IN_USE:
LOG_ERR("%s: Bus busy condition. Another transfer was in progress.",
__func__);
break;
default:
/* Should not reach here. */
LOG_ERR("%s: Unknown error. FSP_ERR=%d\n", __func__, fsp_err);
break;
}
ret = -EIO;
goto RELEASE_BUS;
}
/* Wait for callback to return. */
k_sem_take(&data->complete_sem, K_FOREVER);
/* Handle event msg from callback. */
switch (data->event) {
case I2C_MASTER_EVENT_ABORTED:
LOG_ERR("%s: %s failed.", __func__,
(current->flags & I2C_MSG_READ) ? "Read" : "Write");
ret = -EIO;
goto RELEASE_BUS;
case I2C_MASTER_EVENT_RX_COMPLETE:
break;
case I2C_MASTER_EVENT_TX_COMPLETE:
break;
default:
break;
}
current++;
num_msgs--;
}
RELEASE_BUS:
k_mutex_unlock(&data->bus_mutex);
return ret;
}
static void i2c_ra_iic_callback(i2c_master_callback_args_t *p_args)
{
const struct device *dev = p_args->p_context;
struct i2c_ra_iic_data *data = dev->data;
data->event = p_args->event;
k_sem_give(&data->complete_sem);
}
static int i2c_ra_iic_init(const struct device *dev)
{
const struct i2c_ra_iic_config *config = dev->config;
struct i2c_ra_iic_data *data = (struct i2c_ra_iic_data *)dev->data;
fsp_err_t fsp_err = FSP_SUCCESS;
int ret = 0;
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("%s: pinctrl config failed.", __func__);
return ret;
}
k_mutex_init(&data->bus_mutex);
k_sem_init(&data->complete_sem, 0, 1);
switch (data->fsp_config.rate) {
case I2C_MASTER_RATE_STANDARD:
case I2C_MASTER_RATE_FAST:
case I2C_MASTER_RATE_FASTPLUS:
calc_iic_master_clock_setting(dev, data->fsp_config.rate,
&data->iic_master_ext_cfg.clock_settings);
data->iic_master_ext_cfg.timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT;
data->iic_master_ext_cfg.timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED;
data->fsp_config.p_extend = &data->iic_master_ext_cfg;
break;
default:
LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, data->fsp_config.rate);
return -ENOTSUP;
}
fsp_err = R_IIC_MASTER_Open(&data->ctrl, &data->fsp_config);
__ASSERT(fsp_err == FSP_SUCCESS, "%s: Open iic master failed. FSP_ERR=%d", __func__,
fsp_err);
config->irq_config_func(dev);
return 0;
}
static void calc_iic_master_bitrate(const struct i2c_ra_iic_config *config, uint32_t total_brl_brh,
uint32_t brh, uint32_t divider,
struct ra_iic_master_bitrate *result)
{
const uint32_t noise_filter_stage = config->noise_filter_stage;
const double rise_time_s = config->rise_time_s;
const double fall_time_s = config->fall_time_s;
const uint32_t requested_duty = config->duty_cycle_percent;
const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB);
uint32_t constant_add = 0;
/* A constant is added to BRL and BRH in all formulas. This constand is 3 + nf
* when CKS == 0, or 2 + nf when CKS != 0.
*/
if (divider == 0) {
constant_add = 3 + noise_filter_stage;
} else {
/* All dividers other than 0 use an addition of 2 + noise_filter_stages. */
constant_add = 2 + noise_filter_stage;
}
/* Converts all divided numbers to double to avoid data loss. */
uint32_t divided_pclk = (peripheral_clock >> divider);
result->bitrate =
1 / ((total_brl_brh + 2 * constant_add) / divided_pclk + rise_time_s + fall_time_s);
result->duty =
100 *
((rise_time_s + ((brh + constant_add) / divided_pclk)) /
(rise_time_s + fall_time_s + ((total_brl_brh + 2 * constant_add)) / divided_pclk));
result->divider = divider;
result->brh = brh;
result->brl = total_brl_brh - brh;
result->duty_error_percent =
(result->duty > requested_duty ? result->duty - requested_duty
: requested_duty - result->duty) /
requested_duty;
LOG_DBG("%s: [input] total_brl_brh[%d] brh[%d] divider[%d]"
" [output] bitrate[%u] duty[%u] divider[%u] brh[%u] brl[%u] "
"duty_error_percent[%u]\n",
__func__, total_brl_brh, brh, divider, result->bitrate, result->duty,
result->divider, result->brh, result->brl, result->duty_error_percent);
}
static void calc_iic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
iic_master_clock_settings_t *clk_cfg)
{
const struct i2c_ra_iic_config *config = dev->config;
const uint32_t noise_filter_stage = config->noise_filter_stage;
const double rise_time_s = config->rise_time_s;
const double fall_time_s = config->fall_time_s;
const uint32_t requested_duty = config->duty_cycle_percent;
const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB);
uint32_t requested_bitrate = 0;
switch (fsp_i2c_rate) {
case I2C_MASTER_RATE_STANDARD:
case I2C_MASTER_RATE_FAST:
case I2C_MASTER_RATE_FASTPLUS:
requested_bitrate = fsp_i2c_rate;
break;
default:
LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, fsp_i2c_rate);
return;
}
/* Start with maximum possible bitrate. */
uint32_t min_brh = noise_filter_stage + 1;
uint32_t min_brl_brh = 2 * min_brh;
struct ra_iic_master_bitrate bitrate = {};
calc_iic_master_bitrate(config, min_brl_brh, min_brh, 0, &bitrate);
/* Start with the smallest divider because it gives the most resolution. */
uint32_t constant_add = 3 + noise_filter_stage;
for (int temp_divider = 0; temp_divider <= 7; ++temp_divider) {
if (1 == temp_divider) {
/* All dividers other than 0 use an addition of 2 + noise_filter_stages.
*/
constant_add = 2 + noise_filter_stage;
}
/* If the requested bitrate cannot be achieved with this divider, continue.
*/
uint32_t divided_pclk = (peripheral_clock >> temp_divider);
uint32_t total_brl_brh =
ceil(((1 / (double)requested_bitrate) - (rise_time_s + fall_time_s)) *
divided_pclk -
(2 * constant_add));
if ((total_brl_brh > 62) || (total_brl_brh < min_brl_brh)) {
continue;
}
uint32_t temp_brh = total_brl_brh * requested_duty / 100;
if (temp_brh < min_brh) {
temp_brh = min_brh;
}
/* Calculate the actual bitrate and duty cycle. */
struct ra_iic_master_bitrate temp_bitrate = {};
calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
&temp_bitrate);
/* Adjust duty cycle down if it helps. */
struct ra_iic_master_bitrate test_bitrate = temp_bitrate;
while (test_bitrate.duty > requested_duty) {
temp_brh -= 1;
if ((temp_brh < min_brh) || ((total_brl_brh - temp_brh) > 31)) {
break;
}
struct ra_iic_master_bitrate new_bitrate = {};
calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
&new_bitrate);
if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
temp_bitrate = new_bitrate;
} else {
break;
}
}
/* Adjust duty cycle up if it helps. */
while (test_bitrate.duty < requested_duty) {
++temp_brh;
if ((temp_brh > total_brl_brh) || (temp_brh > 31) ||
((total_brl_brh - temp_brh) < min_brh)) {
break;
}
struct ra_iic_master_bitrate new_bitrate = {};
calc_iic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
&new_bitrate);
if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
temp_bitrate = new_bitrate;
} else {
break;
}
}
if ((temp_bitrate.brh < 32) && (temp_bitrate.brl < 32)) {
/* Valid setting found. */
bitrate = temp_bitrate;
break;
}
}
clk_cfg->brl_value = bitrate.brl;
clk_cfg->brh_value = bitrate.brh;
clk_cfg->cks_value = bitrate.divider;
LOG_DBG("%s: [input] rate[%u] [output] brl[%u] brh[%u] cks[%u]\n", __func__, fsp_i2c_rate,
clk_cfg->brl_value, clk_cfg->brh_value, clk_cfg->cks_value);
}
static const struct i2c_driver_api i2c_ra_iic_driver_api = {
.configure = i2c_ra_iic_configure,
.get_config = i2c_ra_iic_get_config,
.transfer = i2c_ra_iic_transfer,
};
#define _ELC_EVENT_IIC_RXI(channel) ELC_EVENT_IIC##channel##_RXI
#define _ELC_EVENT_IIC_TXI(channel) ELC_EVENT_IIC##channel##_TXI
#define _ELC_EVENT_IIC_TEI(channel) ELC_EVENT_IIC##channel##_TEI
#define _ELC_EVENT_IIC_ERI(channel) ELC_EVENT_IIC##channel##_ERI
#define ELC_EVENT_IIC_RXI(channel) _ELC_EVENT_IIC_RXI(channel)
#define ELC_EVENT_IIC_TXI(channel) _ELC_EVENT_IIC_TXI(channel)
#define ELC_EVENT_IIC_TEI(channel) _ELC_EVENT_IIC_TEI(channel)
#define ELC_EVENT_IIC_ERI(channel) _ELC_EVENT_IIC_ERI(channel)
#define I2C_RA_IIC_INIT(index) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static void i2c_ra_iic_irq_config_func##index(const struct device *dev) \
{ \
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] = \
ELC_EVENT_IIC_RXI(DT_INST_PROP(index, channel)); \
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] = \
ELC_EVENT_IIC_TXI(DT_INST_PROP(index, channel)); \
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] = \
ELC_EVENT_IIC_TEI(DT_INST_PROP(index, channel)); \
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] = \
ELC_EVENT_IIC_ERI(DT_INST_PROP(index, channel)); \
\
IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, rxi, irq), \
DT_INST_IRQ_BY_NAME(index, rxi, priority), iic_master_rxi_isr, \
0); \
IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, txi, irq), \
DT_INST_IRQ_BY_NAME(index, txi, priority), iic_master_txi_isr, \
0); \
IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, tei, irq), \
DT_INST_IRQ_BY_NAME(index, tei, priority), iic_master_tei_isr, \
0); \
IRQ_DIRECT_CONNECT(DT_INST_IRQ_BY_NAME(index, eri, irq), \
DT_INST_IRQ_BY_NAME(index, eri, priority), iic_master_eri_isr, \
0); \
\
irq_enable(DT_INST_IRQ_BY_NAME(index, rxi, irq)); \
irq_enable(DT_INST_IRQ_BY_NAME(index, txi, irq)); \
irq_enable(DT_INST_IRQ_BY_NAME(index, tei, irq)); \
irq_enable(DT_INST_IRQ_BY_NAME(index, eri, irq)); \
} \
\
static const struct i2c_ra_iic_config i2c_ra_iic_config_##index = { \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
.irq_config_func = i2c_ra_iic_irq_config_func##index, \
.noise_filter_stage = 1, /* Cannot be configured. */ \
.rise_time_s = DT_INST_PROP(index, rise_time_ns) / RA_IIC_MASTER_DIV_TIME_NS, \
.fall_time_s = DT_INST_PROP(index, fall_time_ns) / RA_IIC_MASTER_DIV_TIME_NS, \
.duty_cycle_percent = DT_INST_PROP(index, duty_cycle_percent), \
}; \
\
static struct i2c_ra_iic_data i2c_ra_iic_data_##index = { \
.fsp_config = \
{ \
.channel = DT_INST_PROP(index, channel), \
.slave = 0, \
.rate = DT_INST_PROP(index, clock_frequency), \
.addr_mode = I2C_MASTER_ADDR_MODE_7BIT, \
.ipl = DT_INST_PROP(index, interrupt_priority_level), \
.rxi_irq = DT_INST_IRQ_BY_NAME(index, rxi, irq), \
.txi_irq = DT_INST_IRQ_BY_NAME(index, txi, irq), \
.tei_irq = DT_INST_IRQ_BY_NAME(index, tei, irq), \
.eri_irq = DT_INST_IRQ_BY_NAME(index, eri, irq), \
.p_callback = i2c_ra_iic_callback, \
.p_context = DEVICE_DT_GET(DT_DRV_INST(index)), \
}, \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(index, i2c_ra_iic_init, NULL, &i2c_ra_iic_data_##index, \
&i2c_ra_iic_config_##index, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_ra_iic_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_RA_IIC_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_renesas_ra_iic.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,062 |
```unknown
config I2C_CC13XX_CC26XX
bool "TI SimpleLink CC13xx / CC26xx I2C driver"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_I2C_ENABLED
help
Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series.
``` | /content/code_sandbox/drivers/i2c/Kconfig.cc13xx_cc26xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
menuconfig I2C_STM32
bool "STM32 I2C driver"
default y
depends on DT_HAS_ST_STM32_I2C_V1_ENABLED || DT_HAS_ST_STM32_I2C_V2_ENABLED
help
Enable I2C support on the STM32 SoCs
if I2C_STM32
config I2C_STM32_V1
bool
default y
depends on DT_HAS_ST_STM32_I2C_V1_ENABLED
select USE_STM32_LL_I2C
select I2C_STM32_INTERRUPT if I2C_TARGET
help
Driver variant matching `st,stm32-i2c-v1` compatible.
config I2C_STM32_V2
bool
default y
depends on DT_HAS_ST_STM32_I2C_V2_ENABLED
select USE_STM32_LL_I2C
select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
select I2C_STM32_INTERRUPT if I2C_TARGET
help
Driver variant matching `st,stm32-i2c-v2` compatible.
If I2C_TARGET is enabled it selects I2C_STM32_INTERRUPT, since target mode
is only supported by this driver with interrupts enabled.
config I2C_STM32_INTERRUPT
bool "STM32 MCU I2C Interrupt Support"
depends on I2C_STM32_V1 || I2C_STM32_V2
default y
help
Enable Interrupt support for the I2C Driver
config I2C_STM32_COMBINED_INTERRUPT
bool
depends on I2C_STM32_INTERRUPT
default y if SOC_SERIES_STM32C0X || SOC_SERIES_STM32F0X || \
SOC_SERIES_STM32G0X || SOC_SERIES_STM32L0X
config I2C_STM32_BUS_RECOVERY
bool "Bus recovery support"
select I2C_BITBANG
help
Enable STM32 driver bus recovery support via GPIO bitbanging.
config I2C_STM32_V2_TIMING
bool "compute the I2C V2 bus timing"
depends on I2C_STM32_V2
help
Enable STM32 driver bus to calculate the Timing.
endif # I2C_STM32
``` | /content/code_sandbox/drivers/i2c/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 510 |
```objective-c
/*
*
* Driver for the Xilinx AXI IIC Bus Interface.
* This is an FPGA logic core as described by Xilinx document PG090.
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_
#define ZEPHYR_DRIVERS_I2C_I2C_XILINX_AXI_H_
#include <zephyr/sys/util_macro.h>
/* Register offsets */
enum xilinx_axi_i2c_register {
REG_GIE = 0x01C, /* Global Interrupt Enable */
REG_ISR = 0x020, /* Interrupt Status */
REG_IER = 0x028, /* Interrupt Enable */
REG_SOFTR = 0x040, /* Soft Reset */
REG_CR = 0x100, /* Control */
REG_SR = 0x104, /* Status */
REG_TX_FIFO = 0x108, /* Transmit FIFO */
REG_RX_FIFO = 0x10C, /* Receive FIFO */
REG_ADR = 0x110, /* Target Address */
REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
REG_RX_FIFO_OCY = 0x118, /* Receive FIFO Occupancy */
REG_TEN_ADR = 0x11C, /* Target Ten Bit Address */
REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
REG_GPO = 0x124, /* General Purpose Output */
REG_TSUSTA = 0x128, /* Timing Parameter */
REG_TSUSTO = 0x12C, /* Timing Parameter */
REG_THDSTA = 0x130, /* Timing Parameter */
REG_TSUDAT = 0x134, /* Timing Parameter */
REG_TBUF = 0x138, /* Timing Parameter */
REG_THIGH = 0x13C, /* Timing Parameter */
REG_TLOW = 0x140, /* Timing Parameter */
REG_THDDAT = 0x144, /* Timing Parameter */
};
/* Register bits */
/* Global Interrupt Enable */
enum xilinx_axi_i2c_gie_bits {
GIE_ENABLE = BIT(31),
};
/* Interrupt Status/Interrupt Enable */
enum xilinx_axi_i2c_isr_bits {
ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
ISR_NOT_ADDR_TARGET = BIT(6), /* Not Addressed As Target */
ISR_ADDR_TARGET = BIT(5), /* Addressed As Target */
ISR_BUS_NOT_BUSY = BIT(4), /* IIC Bus is Not Busy */
ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */
ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
ISR_TX_ERR_TARGET_COMP = BIT(1), /* Transmit Error/Target Transmit Complete */
ISR_ARB_LOST = BIT(0), /* Arbitration Lost */
};
/* Soft Reset */
enum xilinx_axi_i2c_softr_vals {
SOFTR_KEY = 0xA,
};
/* Control */
enum xilinx_axi_i2c_cr_bits {
CR_GC_EN = BIT(6), /* General Call Enable */
CR_RSTA = BIT(5), /* Repeated Start */
CR_TXAK = BIT(4), /* Transmit Acknowledge Enable */
CR_TX = BIT(3), /* Transmit/Receive Mode Select */
CR_MSMS = BIT(2), /* Controller/Target Mode Select */
CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
CR_EN = BIT(0), /* AXI IIC Enable */
};
/* Status */
enum xilinx_axi_i2c_sr_bits {
SR_TX_FIFO_EMPTY = BIT(7), /* Transmit FIFO empty */
SR_RX_FIFO_EMPTY = BIT(6), /* Receive FIFO empty */
SR_RX_FIFO_FULL = BIT(5), /* Receive FIFO full */
SR_TX_FIFO_FULL = BIT(4), /* Transmit FIFO full */
SR_SRW = BIT(3), /* Target Read/Write */
SR_BB = BIT(2), /* Bus Busy */
SR_AAS = BIT(1), /* Addressed As Target */
SR_ABGC = BIT(0), /* Addressed By a General Call */
};
/* TX FIFO */
enum xilinx_axi_i2c_tx_fifo_bits {
TX_FIFO_STOP = BIT(9),
TX_FIFO_START = BIT(8),
};
/* RX FIFO */
enum xilinx_axi_i2c_rx_fifo_bits {
RX_FIFO_DATA_MASK = 0xFF,
};
/* TX_FIFO_OCY */
enum xilinx_axi_i2c_tx_fifo_ocy_bits {
TX_FIFO_OCY_MASK = 0x0F,
};
/* RX_FIFO_OCY */
enum xilinx_axi_i2c_rx_fifo_ocy_bits {
RX_FIFO_OCY_MASK = 0x0F,
};
/* other constants */
enum {
/* Size of RX/TX FIFO */
FIFO_SIZE = 16,
/* Maximum number of bytes that can be read in dynamic mode */
MAX_DYNAMIC_READ_LEN = 255,
};
#endif
``` | /content/code_sandbox/drivers/i2c/i2c_xilinx_axi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,086 |
```unknown
config I2C_GPIO
bool "GPIO bit banging I2C support"
default y
depends on DT_HAS_GPIO_I2C_ENABLED
select I2C_BITBANG
help
Enable software driven (bit banging) I2C support using GPIO pins
``` | /content/code_sandbox/drivers/i2c/Kconfig.gpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <nrfx_twi.h>
#include "i2c_nrfx_twi_common.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(i2c_nrfx_twi);
int i2c_nrfx_twi_init(const struct device *dev)
{
const struct i2c_nrfx_twi_config *config = dev->config;
nrfx_err_t result = nrfx_twi_init(&config->twi, &config->config,
config->event_handler, (void *)dev);
if (result != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize device: %s",
dev->name);
return -EBUSY;
}
return 0;
}
int i2c_nrfx_twi_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_nrfx_twi_config *config = dev->config;
struct i2c_nrfx_twi_common_data *data = dev->data;
nrfx_twi_t const *inst = &config->twi;
if (I2C_ADDR_10_BITS & dev_config) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
nrf_twi_frequency_set(inst->p_twi, NRF_TWI_FREQ_100K);
break;
case I2C_SPEED_FAST:
nrf_twi_frequency_set(inst->p_twi, NRF_TWI_FREQ_400K);
break;
default:
LOG_ERR("unsupported speed");
return -EINVAL;
}
data->dev_config = dev_config;
return 0;
}
int i2c_nrfx_twi_recover_bus(const struct device *dev)
{
const struct i2c_nrfx_twi_config *config = dev->config;
uint32_t scl_pin;
uint32_t sda_pin;
nrfx_err_t err;
scl_pin = nrf_twi_scl_pin_get(config->twi.p_twi);
sda_pin = nrf_twi_sda_pin_get(config->twi.p_twi);
err = nrfx_twi_bus_recover(scl_pin, sda_pin);
return (err == NRFX_SUCCESS ? 0 : -EBUSY);
}
int i2c_nrfx_twi_msg_transfer(const struct device *dev, uint8_t flags,
uint8_t *buf, size_t buf_len,
uint16_t i2c_addr, bool more_msgs)
{
const struct i2c_nrfx_twi_config *config = dev->config;
int ret = 0;
uint32_t xfer_flags = 0;
nrfx_err_t res;
nrfx_twi_xfer_desc_t cur_xfer = {
.p_primary_buf = buf,
.primary_length = buf_len,
.address = i2c_addr,
.type = (flags & I2C_MSG_READ) ?
NRFX_TWI_XFER_RX : NRFX_TWI_XFER_TX,
};
if (flags & I2C_MSG_ADDR_10_BITS) {
LOG_ERR("10-bit I2C Addr devices not supported");
ret = -ENOTSUP;
} else if (!(flags & I2C_MSG_STOP)) {
/* - if the transfer consists of more messages
* and the I2C repeated START is not requested
* to appear before the next message, suspend
* the transfer after the current message,
* so that it can be resumed with the next one,
* resulting in the two messages merged into
* a continuous transfer on the bus
*/
if (more_msgs) {
xfer_flags |= NRFX_TWI_FLAG_SUSPEND;
/* - otherwise, just finish the transfer without
* generating the STOP condition, unless the current
* message is an RX request, for which such feature
* is not supported
*/
} else if (flags & I2C_MSG_READ) {
ret = -ENOTSUP;
} else {
xfer_flags |= NRFX_TWI_FLAG_TX_NO_STOP;
}
}
if (!ret) {
res = nrfx_twi_xfer(&config->twi, &cur_xfer, xfer_flags);
switch (res) {
case NRFX_SUCCESS:
break;
case NRFX_ERROR_BUSY:
ret = -EBUSY;
break;
default:
ret = -EIO;
break;
}
}
return ret;
}
#ifdef CONFIG_PM_DEVICE
int twi_nrfx_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct i2c_nrfx_twi_config *config = dev->config;
struct i2c_nrfx_twi_common_data *data = dev->data;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
i2c_nrfx_twi_init(dev);
if (data->dev_config) {
i2c_nrfx_twi_configure(dev, data->dev_config);
}
break;
case PM_DEVICE_ACTION_SUSPEND:
nrfx_twi_uninit(&config->twi);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
``` | /content/code_sandbox/drivers/i2c/i2c_nrfx_twi_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,250 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <fsl_i2c.h>
#include <fsl_clock.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_mcux);
#include "i2c-priv.h"
#define DEV_BASE(dev) \
((I2C_Type *)((const struct i2c_mcux_config * const)(dev)->config)->base)
struct i2c_mcux_config {
I2C_Type *base;
clock_name_t clock_source;
void (*irq_config_func)(const struct device *dev);
uint32_t bitrate;
const struct pinctrl_dev_config *pincfg;
};
struct i2c_mcux_data {
i2c_master_handle_t handle;
struct k_sem lock;
struct k_sem device_sync_sem;
status_t callback_status;
#ifdef CONFIG_I2C_CALLBACK
uint16_t addr;
uint32_t msg;
struct i2c_msg *msgs;
uint32_t num_msgs;
i2c_callback_t cb;
void *userdata;
#endif /* CONFIG_I2C_CALLBACK */
};
static int i2c_mcux_configure(const struct device *dev,
uint32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_mcux_data *data = dev->data;
const struct i2c_mcux_config *config = dev->config;
uint32_t clock_freq;
uint32_t baudrate;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
clock_freq = CLOCK_GetFreq(config->clock_source);
k_sem_take(&data->lock, K_FOREVER);
I2C_MasterSetBaudRate(base, baudrate, clock_freq);
k_sem_give(&data->lock);
return 0;
}
#ifdef CONFIG_I2C_CALLBACK
static void i2c_mcux_async_done(const struct device *dev, struct i2c_mcux_data *data, int result);
static void i2c_mcux_async_iter(const struct device *dev);
#endif
static void i2c_mcux_master_transfer_callback(I2C_Type *base,
i2c_master_handle_t *handle,
status_t status, void *userdata)
{
ARG_UNUSED(handle);
ARG_UNUSED(base);
struct device *dev = userdata;
struct i2c_mcux_data *data = dev->data;
#ifdef CONFIG_I2C_CALLBACK
if (data->cb != NULL) {
/* Async transfer */
if (status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
i2c_mcux_async_done(dev, data, -EIO);
} else if (data->msg == data->num_msgs - 1) {
i2c_mcux_async_done(dev, data, 0);
} else {
data->msg++;
i2c_mcux_async_iter(dev);
}
return;
}
#endif /* CONFIG_I2C_CALLBACK */
data->callback_status = status;
k_sem_give(&data->device_sync_sem);
}
static uint32_t i2c_mcux_convert_flags(int msg_flags)
{
uint32_t flags = 0U;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kI2C_TransferNoStopFlag;
}
if (msg_flags & I2C_MSG_RESTART) {
flags |= kI2C_TransferRepeatedStartFlag;
}
return flags;
}
static int i2c_mcux_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_mcux_data *data = dev->data;
i2c_master_transfer_t transfer;
status_t status;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
/* Iterate over all the messages */
for (int i = 0; i < num_msgs; i++) {
if (I2C_MSG_ADDR_10_BITS & msgs->flags) {
ret = -ENOTSUP;
break;
}
/* Initialize the transfer descriptor */
transfer.flags = i2c_mcux_convert_flags(msgs->flags);
transfer.slaveAddress = addr;
transfer.direction = (msgs->flags & I2C_MSG_READ)
? kI2C_Read : kI2C_Write;
transfer.subaddress = 0;
transfer.subaddressSize = 0;
transfer.data = msgs->buf;
transfer.dataSize = msgs->len;
/* Prevent the controller to send a start condition between
* messages, except if explicitly requested.
*/
if (i != 0 && !(msgs->flags & I2C_MSG_RESTART)) {
transfer.flags |= kI2C_TransferNoStartFlag;
}
/* Start the transfer */
status = I2C_MasterTransferNonBlocking(base,
&data->handle, &transfer);
/* Return an error if the transfer didn't start successfully
* e.g., if the bus was busy
*/
if (status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
break;
}
/* Wait for the transfer to complete */
k_sem_take(&data->device_sync_sem, K_FOREVER);
/* Return an error if the transfer didn't complete
* successfully. e.g., nak, timeout, lost arbitration
*/
if (data->callback_status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
break;
}
/* Move to the next message */
msgs++;
}
k_sem_give(&data->lock);
return ret;
}
#ifdef CONFIG_I2C_CALLBACK
static void i2c_mcux_async_done(const struct device *dev, struct i2c_mcux_data *data, int result)
{
i2c_callback_t cb = data->cb;
void *userdata = data->userdata;
data->msg = 0;
data->msgs = NULL;
data->num_msgs = 0;
data->cb = NULL;
data->userdata = NULL;
data->addr = 0;
k_sem_give(&data->lock);
/* Callback may wish to start another transfer */
cb(dev, result, userdata);
}
/* Start a transfer asynchronously */
static void i2c_mcux_async_iter(const struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_mcux_data *data = dev->data;
i2c_master_transfer_t transfer;
status_t status;
struct i2c_msg *msg = &data->msgs[data->msg];
if (I2C_MSG_ADDR_10_BITS & msg->flags) {
i2c_mcux_async_done(dev, data, -ENOTSUP);
return;
}
/* Initialize the transfer descriptor */
transfer.flags = i2c_mcux_convert_flags(msg->flags);
transfer.slaveAddress = data->addr;
transfer.direction = (msg->flags & I2C_MSG_READ) ? kI2C_Read : kI2C_Write;
transfer.subaddress = 0;
transfer.subaddressSize = 0;
transfer.data = msg->buf;
transfer.dataSize = msg->len;
/* Prevent the controller to send a start condition between
* messages, except if explicitly requested.
*/
if (data->msg != 0 && !(msg->flags & I2C_MSG_RESTART)) {
transfer.flags |= kI2C_TransferNoStartFlag;
}
/* Start the transfer */
status = I2C_MasterTransferNonBlocking(base, &data->handle, &transfer);
/* Return an error if the transfer didn't start successfully
* e.g., if the bus was busy
*/
if (status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
i2c_mcux_async_done(dev, data, -EIO);
}
}
static int i2c_mcux_transfer_cb(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr, i2c_callback_t cb, void *userdata)
{
struct i2c_mcux_data *data = dev->data;
int res = k_sem_take(&data->lock, K_NO_WAIT);
if (res != 0) {
return -EWOULDBLOCK;
}
data->msg = 0;
data->msgs = msgs;
data->num_msgs = num_msgs;
data->addr = addr;
data->cb = cb;
data->userdata = userdata;
data->addr = addr;
i2c_mcux_async_iter(dev);
return 0;
}
#endif /* CONFIG_I2C_CALLBACK */
static void i2c_mcux_isr(const struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_mcux_data *data = dev->data;
I2C_MasterTransferHandleIRQ(base, &data->handle);
}
static int i2c_mcux_init(const struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
const struct i2c_mcux_config *config = dev->config;
struct i2c_mcux_data *data = dev->data;
uint32_t clock_freq, bitrate_cfg;
i2c_master_config_t master_config;
int error;
k_sem_init(&data->lock, 1, 1);
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
clock_freq = CLOCK_GetFreq(config->clock_source);
I2C_MasterGetDefaultConfig(&master_config);
I2C_MasterInit(base, &master_config, clock_freq);
I2C_MasterTransferCreateHandle(base, &data->handle,
i2c_mcux_master_transfer_callback, (void *)dev);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (error) {
return error;
}
error = i2c_mcux_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
config->irq_config_func(dev);
return 0;
}
static const struct i2c_driver_api i2c_mcux_driver_api = {
.configure = i2c_mcux_configure,
.transfer = i2c_mcux_transfer,
#ifdef CONFIG_I2C_CALLBACK
.transfer_cb = i2c_mcux_transfer_cb,
#endif
};
#define I2C_DEVICE_INIT_MCUX(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static void i2c_mcux_config_func_ ## n(const struct device *dev); \
\
static const struct i2c_mcux_config i2c_mcux_config_ ## n = { \
.base = (I2C_Type *)DT_INST_REG_ADDR(n),\
.clock_source = I2C ## n ## _CLK_SRC, \
.irq_config_func = i2c_mcux_config_func_ ## n, \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct i2c_mcux_data i2c_mcux_data_ ## n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, \
i2c_mcux_init, NULL, \
&i2c_mcux_data_ ## n, \
&i2c_mcux_config_ ## n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_mcux_driver_api); \
\
static void i2c_mcux_config_func_ ## n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
i2c_mcux_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/i2c/i2c_mcux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,829 |
```unknown
menuconfig I2C_TCA954X
bool "I2C addressable switch"
default y
depends on DT_HAS_TI_TCA9546A_ENABLED || DT_HAS_TI_TCA9548A_ENABLED
help
Enable TCA954x series I2C bus switch
if I2C_TCA954X
config I2C_TCA954X_ROOT_INIT_PRIO
int "TCA954x root driver init priority"
default I2C_INIT_PRIORITY
help
Should be lower than `I2C_TCA954X_CHANNEL_INIT_PRIO`
config I2C_TCA954X_CHANNEL_INIT_PRIO
int "TCA954x channel driver init priority"
default I2C_INIT_PRIORITY
help
Should be higher than `I2C_TCA954X_ROOT_INIT_PRIO`
endif
``` | /content/code_sandbox/drivers/i2c/Kconfig.tca954x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 175 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_versatile_i2c
/**
* @file
* @brief Driver for ARM's SBCon 2-wire serial bus interface
*
* SBCon is a simple device which allows directly setting and getting the
* hardware state of two-bit serial interfaces like I2C.
*/
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_sbcon, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#include "i2c_bitbang.h"
/* SBCon hardware registers layout */
struct sbcon {
union {
volatile uint32_t SB_CONTROLS; /* Write to set pins high */
volatile uint32_t SB_CONTROL; /* Read for state of pins */
};
volatile uint32_t SB_CONTROLC; /* Write to set pins low */
};
/* Bits values for SCL and SDA lines in struct sbcon registers */
#define SCL BIT(0)
#define SDA BIT(1)
/* Driver config */
struct i2c_sbcon_config {
struct sbcon *sbcon; /* Address of hardware registers */
uint32_t bitrate; /* I2C bus speed in Hz */
};
/* Driver instance data */
struct i2c_sbcon_context {
struct i2c_bitbang bitbang; /* Bit-bang library data */
};
static void i2c_sbcon_set_scl(void *io_context, int state)
{
struct sbcon *sbcon = io_context;
if (state) {
sbcon->SB_CONTROLS = SCL;
} else {
sbcon->SB_CONTROLC = SCL;
}
}
static void i2c_sbcon_set_sda(void *io_context, int state)
{
struct sbcon *sbcon = io_context;
if (state) {
sbcon->SB_CONTROLS = SDA;
} else {
sbcon->SB_CONTROLC = SDA;
}
}
static int i2c_sbcon_get_sda(void *io_context)
{
struct sbcon *sbcon = io_context;
return sbcon->SB_CONTROL & SDA;
}
static const struct i2c_bitbang_io io_fns = {
.set_scl = &i2c_sbcon_set_scl,
.set_sda = &i2c_sbcon_set_sda,
.get_sda = &i2c_sbcon_get_sda,
};
static int i2c_sbcon_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_sbcon_context *context = dev->data;
return i2c_bitbang_configure(&context->bitbang, dev_config);
}
static int i2c_sbcon_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_sbcon_context *context = dev->data;
return i2c_bitbang_get_config(&context->bitbang, config);
}
static int i2c_sbcon_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t slave_address)
{
struct i2c_sbcon_context *context = dev->data;
return i2c_bitbang_transfer(&context->bitbang, msgs, num_msgs,
slave_address);
}
static int i2c_sbcon_recover_bus(const struct device *dev)
{
struct i2c_sbcon_context *context = dev->data;
return i2c_bitbang_recover_bus(&context->bitbang);
}
static const struct i2c_driver_api api = {
.configure = i2c_sbcon_configure,
.get_config = i2c_sbcon_get_config,
.transfer = i2c_sbcon_transfer,
.recover_bus = i2c_sbcon_recover_bus,
};
static int i2c_sbcon_init(const struct device *dev)
{
struct i2c_sbcon_context *context = dev->data;
const struct i2c_sbcon_config *config = dev->config;
int ret;
i2c_bitbang_init(&context->bitbang, &io_fns, config->sbcon);
ret = i2c_bitbang_configure(&context->bitbang,
I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
if (ret != 0) {
LOG_ERR("failed to configure I2C bitbang: %d", ret);
}
return ret;
}
#define DEFINE_I2C_SBCON(_num) \
\
static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \
\
static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \
.sbcon = (void *)DT_INST_REG_ADDR(_num), \
.bitrate = DT_INST_PROP(_num, clock_frequency), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(_num, \
i2c_sbcon_init, \
NULL, \
&i2c_sbcon_dev_data_##_num, \
&i2c_sbcon_dev_cfg_##_num, \
PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY, &api);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_SBCON)
``` | /content/code_sandbox/drivers/i2c/i2c_sbcon.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,150 |
```unknown
# sam twihs I2C support
config I2C_SAM_TWIHS
bool "Atmel SAM (TWIHS) I2C driver"
default y
depends on DT_HAS_ATMEL_SAM_I2C_TWIHS_ENABLED
select HAS_I2C_RTIO
help
Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.
``` | /content/code_sandbox/drivers/i2c/Kconfig.sam_twihs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
menuconfig I2C_MAX32
bool "Analog Devices MAX32 I2C driver"
default y
depends on DT_HAS_ADI_MAX32_I2C_ENABLED
select PINCTRL
help
i2c driver for max32 family.
if I2C_MAX32
config I2C_MAX32_INTERRUPT
bool "Interrupt support for MAX32 I2C driver"
default y
help
Enable interrupt support for MAX32 I2C controller mode
transfers.
config I2C_MAX32_DMA
bool "DMA support for MAX32 MCU I2C driver"
depends on I2C_MAX32_INTERRUPT
select DMA
help
Use DMA for MAX32 MCU I2C controller mode transfers.
endif # I2C_MAX32
``` | /content/code_sandbox/drivers/i2c/Kconfig.max32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 161 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_NPCX_CONTROLLER_H_
#define ZEPHYR_DRIVERS_I2C_I2C_NPCX_CONTROLLER_H_
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Lock the mutex of npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
*/
void npcx_i2c_ctrl_mutex_lock(const struct device *i2c_dev);
/**
* @brief Unlock the mutex of npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
*/
void npcx_i2c_ctrl_mutex_unlock(const struct device *i2c_dev);
/**
* @brief Configure operation of a npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param dev_config Bit-packed 32-bit value to the device runtime configuration
* for the I2C controller.
*
* @retval 0 If successful.
* @retval -EIO General input / output error, failed to configure device.
* @retval -ERANGE Out of supported i2c frequency.
*/
int npcx_i2c_ctrl_configure(const struct device *i2c_dev, uint32_t dev_config);
/**
* @brief Get I2C controller speed.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param speed Pointer to store the I2C speed.
*
* @retval 0 If successful.
* @retval -ERANGE Stored I2C frequency out of supported range.
* @retval -EIO Controller is not configured.
*/
int npcx_i2c_ctrl_get_speed(const struct device *i2c_dev, uint32_t *speed);
/**
* @brief Perform data transfer to via npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param msgs Array of messages to transfer.
* @param num_msgs Number of messages to transfer.
* @param addr Address of the I2C target device.
* @param port Port index of selected i2c port.
*
* @retval 0 If successful.
* @retval -EIO General input / output error.
* @retval -ENXIO No slave address match.
* @retval -ETIMEDOUT Timeout occurred for a i2c transaction.
*/
int npcx_i2c_ctrl_transfer(const struct device *i2c_dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr, uint8_t port);
/**
* @brief Toggle the SCL to generate maximum 9 clocks until the target release
* the SDA line and send a STOP condition.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
*
* @retval 0 If successful.
* @retval -EBUSY fail to recover the bus.
*/
int npcx_i2c_ctrl_recover_bus(const struct device *dev);
/**
* @brief Registers the provided config as Target device of a npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param target_cfg Config struct used by the i2c target driver
* @param port Port index of selected i2c port.
*
* @retval 0 Is successful
* @retval -EBUSY If i2c transaction is proceeding.
*/
int npcx_i2c_ctrl_target_register(const struct device *i2c_dev,
struct i2c_target_config *target_cfg, uint8_t port);
/**
* @brief Unregisters the provided config as Target device of a npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param target_cfg Config struct used by the i2c target driver
*
* @retval 0 Is successful
* @retval -EBUSY If i2c transaction is proceeding.
* @retval -EINVAL If parameters are invalid
*/
int npcx_i2c_ctrl_target_unregister(const struct device *i2c_dev,
struct i2c_target_config *target_cfg);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_NPCX_CONTROLLER_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_npcx_controller.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 938 |
```c
/*
*
*/
#include <zephyr/drivers/i2c.h>
#include <string.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_i2c_configure(const struct device *dev,
uint32_t dev_config)
{
K_OOPS(K_SYSCALL_DRIVER_I2C(dev, configure));
return z_impl_i2c_configure((const struct device *)dev, dev_config);
}
#include <zephyr/syscalls/i2c_configure_mrsh.c>
static inline int z_vrfy_i2c_get_config(const struct device *dev,
uint32_t *dev_config)
{
K_OOPS(K_SYSCALL_DRIVER_I2C(dev, get_config));
K_OOPS(K_SYSCALL_MEMORY_WRITE(dev_config, sizeof(uint32_t)));
return z_impl_i2c_get_config(dev, dev_config);
}
#include <zephyr/syscalls/i2c_get_config_mrsh.c>
static uint32_t copy_msgs_and_transfer(const struct device *dev,
const struct i2c_msg *msgs,
uint8_t num_msgs,
uint16_t addr)
{
struct i2c_msg copy[num_msgs];
uint8_t i;
/* Use a local copy to avoid switcheroo attacks. */
memcpy(copy, msgs, num_msgs * sizeof(*msgs));
/* Validate the buffers in each message struct. Read options require
* that the target buffer be writable
*/
for (i = 0U; i < num_msgs; i++) {
K_OOPS(K_SYSCALL_MEMORY(copy[i].buf, copy[i].len,
copy[i].flags & I2C_MSG_READ));
}
return z_impl_i2c_transfer(dev, copy, num_msgs, addr);
}
static inline int z_vrfy_i2c_transfer(const struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
/* copy_msgs_and_transfer() will allocate a copy on the stack using
* VLA, so ensure this won't blow the stack. Most functions defined
* in i2c.h use only a handful of messages, so up to 32 messages
* should be more than sufficient.
*/
K_OOPS(K_SYSCALL_VERIFY(num_msgs >= 1 && num_msgs < 32));
/* We need to be able to read the overall array of messages */
K_OOPS(K_SYSCALL_MEMORY_ARRAY_READ(msgs, num_msgs,
sizeof(struct i2c_msg)));
return copy_msgs_and_transfer((const struct device *)dev,
(struct i2c_msg *)msgs,
(uint8_t)num_msgs, (uint16_t)addr);
}
#include <zephyr/syscalls/i2c_transfer_mrsh.c>
static inline int z_vrfy_i2c_target_driver_register(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
return z_impl_i2c_target_driver_register(dev);
}
#include <zephyr/syscalls/i2c_target_driver_register_mrsh.c>
static inline int z_vrfy_i2c_target_driver_unregister(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
return z_impl_i2c_target_driver_unregister(dev);
}
#include <zephyr/syscalls/i2c_target_driver_unregister_mrsh.c>
static inline int z_vrfy_i2c_recover_bus(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
return z_impl_i2c_recover_bus(dev);
}
#include <zephyr/syscalls/i2c_recover_bus_mrsh.c>
``` | /content/code_sandbox/drivers/i2c/i2c_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 786 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <stdint.h>
LOG_MODULE_REGISTER(tca954x, CONFIG_I2C_LOG_LEVEL);
struct tca954x_root_config {
struct i2c_dt_spec i2c;
uint8_t nchans;
const struct gpio_dt_spec reset_gpios;
};
struct tca954x_root_data {
struct k_mutex lock;
uint8_t selected_chan;
};
struct tca954x_channel_config {
const struct device *root;
uint8_t chan_mask;
};
static inline struct tca954x_root_data *
get_root_data_from_channel(const struct device *dev)
{
const struct tca954x_channel_config *channel_config = dev->config;
return channel_config->root->data;
}
static inline const struct tca954x_root_config *
get_root_config_from_channel(const struct device *dev)
{
const struct tca954x_channel_config *channel_config = dev->config;
return channel_config->root->config;
}
static int tca954x_configure(const struct device *dev, uint32_t dev_config)
{
const struct tca954x_root_config *cfg =
get_root_config_from_channel(dev);
return i2c_configure(cfg->i2c.bus, dev_config);
}
static int tca954x_set_channel(const struct device *dev, uint8_t select_mask)
{
int res = 0;
struct tca954x_root_data *data = dev->data;
const struct tca954x_root_config *cfg = dev->config;
/* Only select the channel if its different from the last channel */
if (data->selected_chan != select_mask) {
res = i2c_write_dt(&cfg->i2c, &select_mask, 1);
if (res == 0) {
data->selected_chan = select_mask;
} else {
LOG_DBG("tca954x: failed to set channel");
}
}
return res;
}
static int tca954x_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs,
uint16_t addr)
{
struct tca954x_root_data *data = get_root_data_from_channel(dev);
const struct tca954x_root_config *config =
get_root_config_from_channel(dev);
const struct tca954x_channel_config *down_cfg = dev->config;
int res;
res = k_mutex_lock(&data->lock, K_MSEC(5000));
if (res != 0) {
return res;
}
res = tca954x_set_channel(down_cfg->root, down_cfg->chan_mask);
if (res != 0) {
goto end_trans;
}
res = i2c_transfer(config->i2c.bus, msgs, num_msgs, addr);
end_trans:
k_mutex_unlock(&data->lock);
return res;
}
static int tca954x_root_init(const struct device *dev)
{
struct tca954x_root_data *i2c_tca954x = dev->data;
const struct tca954x_root_config *config = dev->config;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C bus %s not ready", config->i2c.bus->name);
return -ENODEV;
}
/* If the RESET line is available, configure it. */
if (config->reset_gpios.port) {
if (!gpio_is_ready_dt(&config->reset_gpios)) {
LOG_ERR("%s is not ready",
config->reset_gpios.port->name);
return -ENODEV;
}
if (gpio_pin_configure_dt(&config->reset_gpios, GPIO_OUTPUT)) {
LOG_ERR("%s: failed to configure RESET line", dev->name);
return -EIO;
}
/* Deassert reset line */
gpio_pin_set_dt(&config->reset_gpios, 0);
}
i2c_tca954x->selected_chan = 0;
return 0;
}
static int tca954x_channel_init(const struct device *dev)
{
const struct tca954x_channel_config *chan_cfg = dev->config;
const struct tca954x_root_config *root_cfg =
get_root_config_from_channel(dev);
if (!device_is_ready(chan_cfg->root)) {
LOG_ERR("I2C mux root %s not ready", chan_cfg->root->name);
return -ENODEV;
}
if (chan_cfg->chan_mask >= BIT(root_cfg->nchans)) {
LOG_ERR("Wrong DTS address provided for %s", dev->name);
return -EINVAL;
}
return 0;
}
static const struct i2c_driver_api tca954x_api_funcs = {
.configure = tca954x_configure,
.transfer = tca954x_transfer,
};
BUILD_ASSERT(CONFIG_I2C_TCA954X_CHANNEL_INIT_PRIO > CONFIG_I2C_TCA954X_ROOT_INIT_PRIO,
"I2C multiplexer channels must be initialized after their root");
#define TCA954x_CHILD_DEFINE(node_id, n) \
static const struct tca954x_channel_config \
tca##n##a_down_config_##node_id = { \
.chan_mask = BIT(DT_REG_ADDR(node_id)), \
.root = DEVICE_DT_GET(DT_PARENT(node_id)), \
}; \
DEVICE_DT_DEFINE(node_id, \
tca954x_channel_init, \
NULL, \
NULL, \
&tca##n##a_down_config_##node_id, \
POST_KERNEL, CONFIG_I2C_TCA954X_CHANNEL_INIT_PRIO, \
&tca954x_api_funcs);
#define TCA954x_ROOT_DEFINE(n, inst, ch) \
static const struct tca954x_root_config tca##n##a_cfg_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.nchans = ch, \
.reset_gpios = GPIO_DT_SPEC_GET_OR( \
DT_INST(inst, ti_tca##n##a), reset_gpios, {0}), \
}; \
static struct tca954x_root_data tca##n##a_data_##inst = { \
.lock = Z_MUTEX_INITIALIZER(tca##n##a_data_##inst.lock), \
}; \
I2C_DEVICE_DT_DEFINE(DT_INST(inst, ti_tca##n##a), \
tca954x_root_init, NULL, \
&tca##n##a_data_##inst, &tca##n##a_cfg_##inst, \
POST_KERNEL, CONFIG_I2C_TCA954X_ROOT_INIT_PRIO, \
NULL); \
DT_FOREACH_CHILD_VARGS(DT_INST(inst, ti_tca##n##a), TCA954x_CHILD_DEFINE, n);
/*
* TCA9546A: 4 channels
*/
#define TCA9546A_INIT(n) TCA954x_ROOT_DEFINE(9546, n, 4)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_tca9546a
DT_INST_FOREACH_STATUS_OKAY(TCA9546A_INIT)
/*
* TCA9548A: 8 channels
*/
#define TCA9548A_INIT(n) TCA954x_ROOT_DEFINE(9548, n, 8)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_tca9548a
DT_INST_FOREACH_STATUS_OKAY(TCA9548A_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_tca954x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,651 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_SC18IM704_H_
#define ZEPHYR_DRIVERS_I2C_I2C_SC18IM704_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SC18IM704_CMD_STOP 0x50
#define SC18IM704_CMD_I2C_START 0x53
#define SC18IM704_CMD_READ_REG 0x52
#define SC18IM704_CMD_WRITE_REG 0x57
#define SC18IM704_CMD_READ_GPIO 0x49
#define SC18IM704_CMD_WRITE_GPIO 0x4f
#define SC18IM704_CMD_POWER_DOWN 0x5a
#define SC18IM704_REG_BRG0 0x00
#define SC18IM704_REG_BRG1 0x01
#define SC18IM704_REG_GPIO_CONF1 0x02
#define SC18IM704_REG_GPIO_CONF2 0x03
#define SC18IM704_REG_GPIO_STATE 0x04
#define SC18IM704_REG_I2C_ADDR 0x06
#define SC18IM704_REG_I2C_CLK_L 0x07
#define SC18IM704_REG_I2C_CLK_H 0x08
#define SC18IM704_REG_I2C_TIMEOUT 0x09
#define SC18IM704_REG_I2C_STAT 0x0a
#define SC18IM704_I2C_STAT_OK 0xf0
#define SC18IM704_I2C_STAT_NACK_ADDR 0xf1
#define SC18IM704_I2C_STAT_NACK_DATA 0xf2
#define SC18IM704_I2C_STAT_TIMEOUT 0xf8
/**
* @brief Claim the SC18IM704 device.
*
* @warning After calling this routine, the device cannot be used by any other
* thread until the sc18im704_release routine is called.
*
* @param dev SC18IM704 device.
*
* @retval 0 Device claimed.
* @retval -EBUSY The device could not be claimed.
*/
int sc18im704_claim(const struct device *dev);
/**
* @brief Release the SC18IM704 device claim.
*
* @warning This routine must only be used after a sc18im704_claim.
*
* @param dev SC18IM704 device.
*
* @retval 0 Device claim to release.
* @retval -EPERM The current thread hasn't claimed the device.
* @retval -EINVAL The device has no active claims.
*/
int sc18im704_release(const struct device *dev);
/**
* @brief Exchange data with the SC18IM704 device.
*
* @param dev SC18IM704 device.
* @param tx_data The data buffer to write from.
* @param tx_len The length of the tx_data buffer.
* @param rx_data The data buffer to read to.
* @param rx_len The length of the rx_data buffer.
*
* @retval 0 If successful.
* @retval -EAGAIN The device did not respond in time (1 second timeout).
*/
int sc18im704_transfer(const struct device *dev,
const uint8_t *tx_data, uint8_t tx_len,
uint8_t *rx_data, uint8_t rx_len);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_SC18IM704_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_sc18im704.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 739 |
```c
/*
*
* Based on i2c_tca9656a.c
*
*/
#define DT_DRV_COMPAT gpio_i2c_switch
#define GPIO_I2C_TOGGLE_DELAY_US 1
#define GPIO_I2C_LOCK_TIMEOUT_US (GPIO_I2C_TOGGLE_DELAY_US * 2 + 100)
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_i2c_switch, CONFIG_I2C_LOG_LEVEL);
struct gpio_i2c_switch_config {
const struct device *bus;
const struct gpio_dt_spec gpio;
};
struct gpio_i2c_switch_data {
struct k_mutex lock;
};
static int gpio_i2c_switch_configure(const struct device *dev, uint32_t dev_config)
{
const struct gpio_i2c_switch_config *config = dev->config;
return i2c_configure(config->bus, dev_config);
}
static int gpio_i2c_switch_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
int res;
struct gpio_i2c_switch_data *data = dev->data;
const struct gpio_i2c_switch_config *config = dev->config;
res = k_mutex_lock(&data->lock, K_USEC(GPIO_I2C_LOCK_TIMEOUT_US));
if (res != 0) {
return res;
}
/* enable switch */
gpio_pin_set_dt(&config->gpio, 1);
k_busy_wait(GPIO_I2C_TOGGLE_DELAY_US);
res = i2c_transfer(config->bus, msgs, num_msgs, addr);
/* disable switch */
gpio_pin_set_dt(&config->gpio, 0);
k_busy_wait(GPIO_I2C_TOGGLE_DELAY_US);
k_mutex_unlock(&data->lock);
return res;
}
static const struct i2c_driver_api gpio_i2c_switch_api_funcs = {
.configure = gpio_i2c_switch_configure,
.transfer = gpio_i2c_switch_transfer,
};
static int gpio_i2c_switch_init(const struct device *dev)
{
const struct gpio_i2c_switch_config *config = dev->config;
struct gpio_i2c_switch_data *data = dev->data;
k_mutex_init(&data->lock);
return gpio_pin_configure_dt(&config->gpio, GPIO_OUTPUT_INACTIVE);
}
#define DEFINE_GPIO_I2C_SWITCH(inst) \
\
static struct gpio_i2c_switch_data gpio_i2c_switch_dev_data_##inst; \
\
static const struct gpio_i2c_switch_config gpio_i2c_switch_dev_cfg_##inst = { \
.bus = DEVICE_DT_GET(DT_PHANDLE(DT_DRV_INST(inst), controller)), \
.gpio = GPIO_DT_SPEC_GET(DT_DRV_INST(inst), gpios), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, gpio_i2c_switch_init, device_pm_control_nop, \
&gpio_i2c_switch_dev_data_##inst, &gpio_i2c_switch_dev_cfg_##inst, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &gpio_i2c_switch_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_GPIO_I2C_SWITCH)
``` | /content/code_sandbox/drivers/i2c/gpio_i2c_switch.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 703 |
```unknown
config I2C_XILINX_AXI
bool "Xilinx AXI I2C driver"
default y
depends on DT_HAS_XLNX_XPS_IIC_2_00_A_ENABLED || DT_HAS_XLNX_XPS_IIC_2_1_ENABLED
select EVENTS
help
Enable the Xilinx AXI IIC Bus Interface driver.
This is an FPGA logic core as described by Xilinx document PG090.
``` | /content/code_sandbox/drivers/i2c/Kconfig.xilinx_axi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# ESP32 I2C configuration options
config I2C_ESP32
bool "ESP32 I2C driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_I2C_ENABLED
select GPIO_ESP32
help
Enables the ESP32 I2C driver
``` | /content/code_sandbox/drivers/i2c/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_i2c
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <esp32/rom/gpio.h>
#include <soc/gpio_sig_map.h>
#include <hal/i2c_ll.h>
#include <hal/i2c_hal.h>
#include <hal/gpio_hal.h>
#include <clk_ctrl_os.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <string.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_esp32, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#define I2C_FILTER_CYC_NUM_DEF 7 /* Number of apb cycles filtered by default */
#define I2C_CLR_BUS_SCL_NUM 9 /* Number of SCL clocks to restore SDA signal */
#define I2C_CLR_BUS_HALF_PERIOD_US 5 /* Period of SCL clock to restore SDA signal */
#define I2C_TRANSFER_TIMEOUT_MSEC 500 /* Transfer timeout period */
/* Freq limitation when using different clock sources */
#define I2C_CLK_LIMIT_REF_TICK (1 * 1000 * 1000 / 20) /* REF_TICK, no more than REF_TICK/20*/
#define I2C_CLK_LIMIT_APB (80 * 1000 * 1000 / 20) /* Limited by APB, no more than APB/20 */
#define I2C_CLK_LIMIT_RTC (20 * 1000 * 1000 / 20) /* Limited by RTC, no more than RTC/20 */
#define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /* Limited by RTC, no more than XTAL/20 */
#define I2C_CLOCK_INVALID (-1)
enum i2c_status_t {
I2C_STATUS_READ, /* read status for current master command */
I2C_STATUS_WRITE, /* write status for current master command */
I2C_STATUS_IDLE, /* idle status for current master command */
I2C_STATUS_ACK_ERROR, /* ack error status for current master command */
I2C_STATUS_DONE, /* I2C command done */
I2C_STATUS_TIMEOUT, /* I2C bus status error, and operation timeout */
};
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
struct i2c_esp32_pin {
struct gpio_dt_spec gpio;
int sig_out;
int sig_in;
};
#endif
struct i2c_esp32_data {
i2c_hal_context_t hal;
struct k_sem cmd_sem;
struct k_sem transfer_sem;
volatile enum i2c_status_t status;
uint32_t dev_config;
int cmd_idx;
int irq_line;
};
typedef void (*irq_connect_cb)(void);
struct i2c_esp32_config {
int index;
const struct device *clock_dev;
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
const struct i2c_esp32_pin scl;
const struct i2c_esp32_pin sda;
#endif
const struct pinctrl_dev_config *pcfg;
const clock_control_subsys_t clock_subsys;
const struct {
bool tx_lsb_first;
bool rx_lsb_first;
} mode;
int irq_source;
const uint32_t bitrate;
const uint32_t scl_timeout;
};
static uint32_t i2c_get_src_clk_freq(i2c_clock_source_t clk_src)
{
uint32_t periph_src_clk_hz = 0;
switch (clk_src) {
#if SOC_I2C_SUPPORT_APB
case I2C_CLK_SRC_APB:
periph_src_clk_hz = esp_clk_apb_freq();
break;
#endif
#if SOC_I2C_SUPPORT_XTAL
case I2C_CLK_SRC_XTAL:
periph_src_clk_hz = esp_clk_xtal_freq();
break;
#endif
#if SOC_I2C_SUPPORT_RTC
case I2C_CLK_SRC_RC_FAST:
periph_rtc_dig_clk8m_enable();
periph_src_clk_hz = periph_rtc_dig_clk8m_get_freq();
break;
#endif
#if SOC_I2C_SUPPORT_REF_TICK
case RMT_CLK_SRC_REF_TICK:
periph_src_clk_hz = REF_CLK_FREQ;
break;
#endif
default:
LOG_ERR("clock source %d is not supported", clk_src);
break;
}
return periph_src_clk_hz;
}
static i2c_clock_source_t i2c_get_clk_src(uint32_t clk_freq)
{
i2c_clock_source_t clk_srcs[] = SOC_I2C_CLKS;
for (size_t i = 0; i < ARRAY_SIZE(clk_srcs); i++) {
/* I2C SCL clock frequency should not larger than clock source frequency/20 */
if (clk_freq <= (i2c_get_src_clk_freq(clk_srcs[i]) / 20)) {
return clk_srcs[i];
}
}
return I2C_CLOCK_INVALID;
}
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
static int i2c_esp32_config_pin(const struct device *dev)
{
const struct i2c_esp32_config *config = dev->config;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
int ret = 0;
if (config->index >= SOC_I2C_NUM) {
LOG_ERR("Invalid I2C peripheral number");
return -EINVAL;
}
gpio_pin_set_dt(&config->sda.gpio, 1);
ret = gpio_pin_configure_dt(&config->sda.gpio, GPIO_PULL_UP | GPIO_OUTPUT | GPIO_INPUT);
esp_rom_gpio_matrix_out(config->sda.gpio.pin, config->sda.sig_out, 0, 0);
esp_rom_gpio_matrix_in(config->sda.gpio.pin, config->sda.sig_in, 0);
gpio_pin_set_dt(&config->scl.gpio, 1);
ret |= gpio_pin_configure_dt(&config->scl.gpio, GPIO_PULL_UP | GPIO_OUTPUT | GPIO_INPUT);
esp_rom_gpio_matrix_out(config->scl.gpio.pin, config->scl.sig_out, 0, 0);
esp_rom_gpio_matrix_in(config->scl.gpio.pin, config->scl.sig_in, 0);
return ret;
}
#endif
/* Some slave device will die by accident and keep the SDA in low level,
* in this case, master should send several clock to make the slave release the bus.
* Slave mode of ESP32 might also get in wrong state that held the SDA low,
* in this case, master device could send a stop signal to make esp32 slave release the bus.
**/
static void IRAM_ATTR i2c_master_clear_bus(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
const struct i2c_esp32_config *config = dev->config;
const int scl_half_period = I2C_CLR_BUS_HALF_PERIOD_US; /* use standard 100kHz data rate */
int i = 0;
gpio_pin_configure_dt(&config->scl.gpio, GPIO_OUTPUT);
gpio_pin_configure_dt(&config->sda.gpio, GPIO_OUTPUT | GPIO_INPUT);
/* If a SLAVE device was in a read operation when the bus was interrupted, */
/* the SLAVE device is controlling SDA. If the slave is sending a stream of ZERO bytes, */
/* it will only release SDA during the ACK bit period. So, this reset code needs */
/* to synchronize the bit stream with either the ACK bit, or a 1 bit to correctly */
/* generate a STOP condition. */
gpio_pin_set_dt(&config->sda.gpio, 1);
esp_rom_delay_us(scl_half_period);
while (!gpio_pin_get_dt(&config->sda.gpio) && (i++ < I2C_CLR_BUS_SCL_NUM)) {
gpio_pin_set_dt(&config->scl.gpio, 1);
esp_rom_delay_us(scl_half_period);
gpio_pin_set_dt(&config->scl.gpio, 0);
esp_rom_delay_us(scl_half_period);
}
gpio_pin_set_dt(&config->sda.gpio, 0); /* setup for STOP */
gpio_pin_set_dt(&config->scl.gpio, 1);
esp_rom_delay_us(scl_half_period);
gpio_pin_set_dt(&config->sda.gpio, 1); /* STOP, SDA low -> high while SCL is HIGH */
i2c_esp32_config_pin(dev);
#else
i2c_ll_master_clr_bus(data->hal.dev);
#endif
i2c_ll_update(data->hal.dev);
}
static void IRAM_ATTR i2c_hw_fsm_reset(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
#ifndef SOC_I2C_SUPPORT_HW_FSM_RST
const struct i2c_esp32_config *config = dev->config;
int scl_low_period, scl_high_period;
int scl_start_hold, scl_rstart_setup;
int scl_stop_hold, scl_stop_setup;
int sda_hold, sda_sample;
int timeout;
uint8_t filter_cfg;
i2c_ll_get_scl_timing(data->hal.dev, &scl_high_period, &scl_low_period);
i2c_ll_get_start_timing(data->hal.dev, &scl_rstart_setup, &scl_start_hold);
i2c_ll_get_stop_timing(data->hal.dev, &scl_stop_setup, &scl_stop_hold);
i2c_ll_get_sda_timing(data->hal.dev, &sda_sample, &sda_hold);
i2c_ll_get_tout(data->hal.dev, &timeout);
i2c_ll_get_filter(data->hal.dev, &filter_cfg);
/* to reset the I2C hw module, we need re-enable the hw */
clock_control_off(config->clock_dev, config->clock_subsys);
i2c_master_clear_bus(dev);
clock_control_on(config->clock_dev, config->clock_subsys);
i2c_hal_master_init(&data->hal);
i2c_ll_disable_intr_mask(data->hal.dev, I2C_LL_INTR_MASK);
i2c_ll_clear_intr_mask(data->hal.dev, I2C_LL_INTR_MASK);
i2c_ll_set_scl_timing(data->hal.dev, scl_high_period, scl_low_period);
i2c_ll_set_start_timing(data->hal.dev, scl_rstart_setup, scl_start_hold);
i2c_ll_set_stop_timing(data->hal.dev, scl_stop_setup, scl_stop_hold);
i2c_ll_set_sda_timing(data->hal.dev, sda_sample, sda_hold);
i2c_ll_set_tout(data->hal.dev, timeout);
i2c_ll_set_filter(data->hal.dev, filter_cfg);
#else
i2c_ll_master_fsm_rst(data->hal.dev);
i2c_master_clear_bus(dev);
#endif
i2c_ll_update(data->hal.dev);
}
static int i2c_esp32_recover(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
k_sem_take(&data->transfer_sem, K_FOREVER);
i2c_hw_fsm_reset(dev);
k_sem_give(&data->transfer_sem);
return 0;
}
static void IRAM_ATTR i2c_esp32_configure_bitrate(const struct device *dev, uint32_t bitrate)
{
const struct i2c_esp32_config *config = dev->config;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
i2c_clock_source_t sclk = i2c_get_clk_src(bitrate);
uint32_t clk_freq_mhz = i2c_get_src_clk_freq(sclk);
i2c_hal_set_bus_timing(&data->hal, bitrate, sclk, clk_freq_mhz);
if (config->scl_timeout > 0) {
uint32_t timeout_cycles = MIN(I2C_LL_MAX_TIMEOUT,
clk_freq_mhz / MHZ(1) * config->scl_timeout);
i2c_ll_set_tout(data->hal.dev, timeout_cycles);
LOG_DBG("SCL timeout: %d us, value: %d", config->scl_timeout, timeout_cycles);
} else {
/* Disabling the timeout by clearing the I2C_TIME_OUT_EN bit does not seem to work,
* at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the
* timeout to maximum supported value instead.
*/
i2c_ll_set_tout(data->hal.dev, I2C_LL_MAX_TIMEOUT);
}
i2c_ll_update(data->hal.dev);
}
static void i2c_esp32_configure_data_mode(const struct device *dev)
{
const struct i2c_esp32_config *config = dev->config;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
i2c_trans_mode_t tx_mode = I2C_DATA_MODE_MSB_FIRST;
i2c_trans_mode_t rx_mode = I2C_DATA_MODE_MSB_FIRST;
if (config->mode.tx_lsb_first) {
tx_mode = I2C_DATA_MODE_LSB_FIRST;
}
if (config->mode.rx_lsb_first) {
rx_mode = I2C_DATA_MODE_LSB_FIRST;
}
i2c_ll_set_data_mode(data->hal.dev, tx_mode, rx_mode);
i2c_ll_set_filter(data->hal.dev, I2C_FILTER_CYC_NUM_DEF);
i2c_ll_update(data->hal.dev);
}
static int i2c_esp32_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_esp32_config *config = dev->config;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
uint32_t bitrate;
if (!(dev_config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Only I2C Master mode supported.");
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
bitrate = KHZ(100);
break;
case I2C_SPEED_FAST:
bitrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
bitrate = MHZ(1);
break;
default:
LOG_ERR("Error configuring I2C speed.");
return -ENOTSUP;
}
k_sem_take(&data->transfer_sem, K_FOREVER);
data->dev_config = dev_config;
i2c_esp32_configure_bitrate(dev, bitrate);
k_sem_give(&data->transfer_sem);
return 0;
}
static int i2c_esp32_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
if (data->dev_config == 0) {
LOG_ERR("I2C controller not configured");
return -EIO;
}
*config = data->dev_config;
return 0;
}
static void IRAM_ATTR i2c_esp32_reset_fifo(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
/* reset fifo buffers */
i2c_ll_txfifo_rst(data->hal.dev);
i2c_ll_rxfifo_rst(data->hal.dev);
}
static int IRAM_ATTR i2c_esp32_transmit(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
int ret = 0;
/* Start transmission*/
i2c_ll_update(data->hal.dev);
i2c_ll_trans_start(data->hal.dev);
data->cmd_idx = 0;
ret = k_sem_take(&data->cmd_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC));
if (ret != 0) {
/* If the I2C slave is powered off or the SDA/SCL is */
/* connected to ground, for example, I2C hw FSM would get */
/* stuck in wrong state, we have to reset the I2C module in this case. */
i2c_hw_fsm_reset(dev);
return -ETIMEDOUT;
}
if (data->status == I2C_STATUS_TIMEOUT) {
i2c_hw_fsm_reset(dev);
ret = -ETIMEDOUT;
} else if (data->status == I2C_STATUS_ACK_ERROR) {
ret = -EFAULT;
}
return ret;
}
static void IRAM_ATTR i2c_esp32_master_start(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
i2c_ll_hw_cmd_t cmd = {
.op_code = I2C_LL_CMD_RESTART
};
i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++);
}
static void IRAM_ATTR i2c_esp32_master_stop(const struct device *dev)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
i2c_ll_hw_cmd_t cmd = {
.op_code = I2C_LL_CMD_STOP
};
i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++);
}
static int IRAM_ATTR i2c_esp32_write_addr(const struct device *dev, uint16_t addr)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
uint8_t addr_len = 1;
uint8_t addr_byte = addr & 0xFF;
data->status = I2C_STATUS_WRITE;
/* write address value in tx buffer */
i2c_ll_write_txfifo(data->hal.dev, &addr_byte, 1);
if (data->dev_config & I2C_ADDR_10_BITS) {
addr_byte = (addr >> 8) & 0xFF;
i2c_ll_write_txfifo(data->hal.dev, &addr_byte, 1);
addr_len++;
}
const i2c_ll_hw_cmd_t cmd_end = {
.op_code = I2C_LL_CMD_END,
};
i2c_ll_hw_cmd_t cmd = {
.op_code = I2C_LL_CMD_WRITE,
.ack_en = true,
.byte_num = addr_len,
};
i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++);
i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++);
i2c_ll_master_enable_tx_it(data->hal.dev);
return i2c_esp32_transmit(dev);
}
static int IRAM_ATTR i2c_esp32_master_read(const struct device *dev, struct i2c_msg *msg)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
uint32_t msg_len = msg->len;
uint8_t *msg_buf = msg->buf;
uint8_t rd_filled = 0;
int ret = 0;
data->status = I2C_STATUS_READ;
i2c_ll_hw_cmd_t cmd = {
.op_code = I2C_LL_CMD_READ,
};
const i2c_ll_hw_cmd_t cmd_end = {
.op_code = I2C_LL_CMD_END,
};
while (msg_len) {
rd_filled = (msg_len > SOC_I2C_FIFO_LEN) ? SOC_I2C_FIFO_LEN : (msg_len - 1);
/* I2C master won't acknowledge the last byte read from the
* slave device. Divide the read command in two segments as
* recommended by the ESP32 Technical Reference Manual.
*/
if (msg_len == 1) {
rd_filled = 1;
cmd.ack_val = 1;
} else {
cmd.ack_val = 0;
}
cmd.byte_num = rd_filled;
i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++);
i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++);
i2c_ll_master_enable_tx_it(data->hal.dev);
ret = i2c_esp32_transmit(dev);
if (ret < 0) {
return ret;
}
i2c_ll_read_rxfifo(data->hal.dev, msg_buf, rd_filled);
msg_buf += rd_filled;
msg_len -= rd_filled;
}
return 0;
}
static int IRAM_ATTR i2c_esp32_read_msg(const struct device *dev,
struct i2c_msg *msg, uint16_t addr)
{
int ret = 0;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
/* Set the R/W bit to R */
addr |= BIT(0);
if (msg->flags & I2C_MSG_RESTART) {
i2c_esp32_master_start(dev);
ret = i2c_esp32_write_addr(dev, addr);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
}
ret = i2c_esp32_master_read(dev, msg);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
if (msg->flags & I2C_MSG_STOP) {
i2c_esp32_master_stop(dev);
ret = i2c_esp32_transmit(dev);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
}
return 0;
}
static int IRAM_ATTR i2c_esp32_master_write(const struct device *dev, struct i2c_msg *msg)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
uint8_t wr_filled = 0;
uint32_t msg_len = msg->len;
uint8_t *msg_buf = msg->buf;
int ret = 0;
data->status = I2C_STATUS_WRITE;
i2c_ll_hw_cmd_t cmd = {
.op_code = I2C_LL_CMD_WRITE,
.ack_en = true,
};
const i2c_ll_hw_cmd_t cmd_end = {
.op_code = I2C_LL_CMD_END,
};
while (msg_len) {
wr_filled = (msg_len > SOC_I2C_FIFO_LEN) ? SOC_I2C_FIFO_LEN : msg_len;
cmd.byte_num = wr_filled;
if (wr_filled > 0) {
i2c_ll_write_txfifo(data->hal.dev, msg_buf, wr_filled);
i2c_ll_write_cmd_reg(data->hal.dev, cmd, data->cmd_idx++);
i2c_ll_write_cmd_reg(data->hal.dev, cmd_end, data->cmd_idx++);
i2c_ll_master_enable_tx_it(data->hal.dev);
ret = i2c_esp32_transmit(dev);
if (ret < 0) {
return ret;
}
}
msg_buf += wr_filled;
msg_len -= wr_filled;
}
return 0;
}
static int IRAM_ATTR i2c_esp32_write_msg(const struct device *dev,
struct i2c_msg *msg, uint16_t addr)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
int ret = 0;
if (msg->flags & I2C_MSG_RESTART) {
i2c_esp32_master_start(dev);
ret = i2c_esp32_write_addr(dev, addr);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
}
ret = i2c_esp32_master_write(dev, msg);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
if (msg->flags & I2C_MSG_STOP) {
i2c_esp32_master_stop(dev);
ret = i2c_esp32_transmit(dev);
if (ret < 0) {
LOG_ERR("I2C transfer error: %d", ret);
return ret;
}
}
return 0;
}
static int IRAM_ATTR i2c_esp32_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
struct i2c_msg *current, *next;
uint32_t timeout = I2C_TRANSFER_TIMEOUT_MSEC * USEC_PER_MSEC;
int ret = 0;
if (!num_msgs) {
return 0;
}
while (i2c_ll_is_bus_busy(data->hal.dev)) {
k_busy_wait(1);
if (timeout-- == 0) {
return -EBUSY;
}
}
/* Check for validity of all messages before transfer */
current = msgs;
/* Add restart flag on first message to send start event */
current->flags |= I2C_MSG_RESTART;
for (int k = 1; k <= num_msgs; k++) {
if (k < num_msgs) {
next = current + 1;
/* messages of different direction require restart event */
if ((current->flags & I2C_MSG_RW_MASK) != (next->flags & I2C_MSG_RW_MASK)) {
if (!(next->flags & I2C_MSG_RESTART)) {
ret = -EINVAL;
break;
}
}
/* check if there is any stop event in the middle of the transaction */
if (current->flags & I2C_MSG_STOP) {
ret = -EINVAL;
break;
}
}
current++;
}
if (ret) {
return ret;
}
k_sem_take(&data->transfer_sem, K_FOREVER);
/* Mask out unused address bits, and make room for R/W bit */
addr &= BIT_MASK(data->dev_config & I2C_ADDR_10_BITS ? 10 : 7);
addr <<= 1;
for (; num_msgs > 0; num_msgs--, msgs++) {
if (data->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(data->hal.dev)) {
i2c_hw_fsm_reset(dev);
}
/* reset all fifo buffer before start */
i2c_esp32_reset_fifo(dev);
/* These two interrupts some times can not be cleared when the FSM gets stuck. */
/* So we disable them when these two interrupt occurs and re-enable them here. */
i2c_ll_disable_intr_mask(data->hal.dev, I2C_LL_INTR_MASK);
i2c_ll_clear_intr_mask(data->hal.dev, I2C_LL_INTR_MASK);
if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
ret = i2c_esp32_read_msg(dev, msgs, addr);
} else {
ret = i2c_esp32_write_msg(dev, msgs, addr);
}
if (ret < 0) {
break;
}
}
k_sem_give(&data->transfer_sem);
return ret;
}
static void IRAM_ATTR i2c_esp32_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
i2c_intr_event_t evt_type = I2C_INTR_EVENT_ERR;
if (data->status == I2C_STATUS_WRITE) {
i2c_hal_master_handle_tx_event(&data->hal, &evt_type);
} else if (data->status == I2C_STATUS_READ) {
i2c_hal_master_handle_rx_event(&data->hal, &evt_type);
}
if (evt_type == I2C_INTR_EVENT_NACK) {
data->status = I2C_STATUS_ACK_ERROR;
} else if (evt_type == I2C_INTR_EVENT_TOUT) {
data->status = I2C_STATUS_TIMEOUT;
} else if (evt_type == I2C_INTR_EVENT_ARBIT_LOST) {
data->status = I2C_STATUS_TIMEOUT;
} else if (evt_type == I2C_INTR_EVENT_TRANS_DONE) {
data->status = I2C_STATUS_DONE;
}
k_sem_give(&data->cmd_sem);
}
static const struct i2c_driver_api i2c_esp32_driver_api = {
.configure = i2c_esp32_configure,
.get_config = i2c_esp32_get_config,
.transfer = i2c_esp32_transfer,
.recover_bus = i2c_esp32_recover
};
static int IRAM_ATTR i2c_esp32_init(const struct device *dev)
{
const struct i2c_esp32_config *config = dev->config;
struct i2c_esp32_data *data = (struct i2c_esp32_data *const)(dev)->data;
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
if (!gpio_is_ready_dt(&config->scl.gpio)) {
LOG_ERR("SCL GPIO device is not ready");
return -EINVAL;
}
if (!gpio_is_ready_dt(&config->sda.gpio)) {
LOG_ERR("SDA GPIO device is not ready");
return -EINVAL;
}
#endif
int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("Failed to configure I2C pins");
return -EINVAL;
}
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
clock_control_on(config->clock_dev, config->clock_subsys);
esp_intr_alloc(config->irq_source, 0, i2c_esp32_isr, (void *)dev, NULL);
i2c_hal_master_init(&data->hal);
i2c_esp32_configure_data_mode(dev);
return i2c_esp32_configure(dev, I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
}
#define I2C(idx) DT_NODELABEL(i2c##idx)
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
#define I2C_ESP32_GET_PIN_INFO(idx) \
.scl = { \
.gpio = GPIO_DT_SPEC_GET(I2C(idx), scl_gpios), \
.sig_out = I2CEXT##idx##_SCL_OUT_IDX, \
.sig_in = I2CEXT##idx##_SCL_IN_IDX, \
}, \
.sda = { \
.gpio = GPIO_DT_SPEC_GET(I2C(idx), sda_gpios), \
.sig_out = I2CEXT##idx##_SDA_OUT_IDX, \
.sig_in = I2CEXT##idx##_SDA_IN_IDX, \
},
#else
#define I2C_ESP32_GET_PIN_INFO(idx)
#endif /* SOC_I2C_SUPPORT_HW_CLR_BUS */
#define I2C_ESP32_TIMEOUT(inst) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, scl_timeout_us), \
(DT_INST_PROP(inst, scl_timeout_us)), (0))
#define I2C_ESP32_FREQUENCY(bitrate) \
(bitrate == I2C_BITRATE_STANDARD ? KHZ(100) \
: bitrate == I2C_BITRATE_FAST ? KHZ(400) \
: bitrate == I2C_BITRATE_FAST_PLUS ? MHZ(1) : 0)
#define I2C_FREQUENCY(idx) \
I2C_ESP32_FREQUENCY(DT_PROP(I2C(idx), clock_frequency))
#define ESP32_I2C_INIT(idx) \
\
PINCTRL_DT_DEFINE(I2C(idx)); \
\
static struct i2c_esp32_data i2c_esp32_data_##idx = { \
.hal = { \
.dev = (i2c_dev_t *) DT_REG_ADDR(I2C(idx)), \
}, \
.cmd_sem = Z_SEM_INITIALIZER(i2c_esp32_data_##idx.cmd_sem, 0, 1), \
.transfer_sem = Z_SEM_INITIALIZER(i2c_esp32_data_##idx.transfer_sem, 1, 1), \
}; \
\
static const struct i2c_esp32_config i2c_esp32_config_##idx = { \
.index = idx, \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(I2C(idx))), \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
.clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(I2C(idx), offset), \
I2C_ESP32_GET_PIN_INFO(idx) \
.mode = { \
.tx_lsb_first = DT_PROP(I2C(idx), tx_lsb), \
.rx_lsb_first = DT_PROP(I2C(idx), rx_lsb), \
}, \
.irq_source = ETS_I2C_EXT##idx##_INTR_SOURCE, \
.bitrate = I2C_FREQUENCY(idx), \
.scl_timeout = I2C_ESP32_TIMEOUT(idx), \
}; \
I2C_DEVICE_DT_DEFINE(I2C(idx), i2c_esp32_init, NULL, &i2c_esp32_data_##idx, \
&i2c_esp32_config_##idx, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_esp32_driver_api);
#if DT_NODE_HAS_STATUS(I2C(0), okay)
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
#if !DT_NODE_HAS_PROP(I2C(0), sda_gpios) || !DT_NODE_HAS_PROP(I2C(0), scl_gpios)
#error "Missing <sda-gpios> and <scl-gpios> properties to build for this target."
#endif
#else
#if DT_NODE_HAS_PROP(I2C(0), sda_gpios) || DT_NODE_HAS_PROP(I2C(0), scl_gpios)
#error "Properties <sda-gpios> and <scl-gpios> are not required for this target."
#endif
#endif /* !SOC_I2C_SUPPORT_HW_CLR_BUS */
ESP32_I2C_INIT(0);
#endif /* DT_NODE_HAS_STATUS(I2C(0), okay) */
#if DT_NODE_HAS_STATUS(I2C(1), okay)
#ifndef SOC_I2C_SUPPORT_HW_CLR_BUS
#if !DT_NODE_HAS_PROP(I2C(1), sda_gpios) || !DT_NODE_HAS_PROP(I2C(1), scl_gpios)
#error "Missing <sda-gpios> and <scl-gpios> properties to build for this target."
#endif
#else
#if DT_NODE_HAS_PROP(I2C(1), sda_gpios) || DT_NODE_HAS_PROP(I2C(1), scl_gpios)
#error "Properties <sda-gpios> and <scl-gpios> are not required for this target."
#endif
#endif /* !SOC_I2C_SUPPORT_HW_CLR_BUS */
ESP32_I2C_INIT(1);
#endif /* DT_NODE_HAS_STATUS(I2C(1), okay) */
``` | /content/code_sandbox/drivers/i2c/i2c_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,905 |
```unknown
# Renesas RA Family
config RENESAS_RA_I2C_IIC
bool "Renesas RA I2C IIC Master"
default y
depends on DT_HAS_RENESAS_RA_IIC_ENABLED
select USE_RA_FSP_I2C_IIC
help
Enable Renesas RA I2C IIC Driver.
``` | /content/code_sandbox/drivers/i2c/Kconfig.renesas_ra | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*
* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4, STM32WB and
* STM32WL
*
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <stm32_ll_i2c.h>
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include "i2c_ll_stm32.h"
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_ll_stm32_v2);
#include "i2c-priv.h"
#define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
#ifdef CONFIG_I2C_STM32_V2_TIMING
/* Use the algorithm to calcuate the I2C timing */
#ifndef STM32_I2C_VALID_TIMING_NBR
#define STM32_I2C_VALID_TIMING_NBR 128U
#endif
#define STM32_I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */
#define STM32_I2C_SPEED_FREQ_FAST 1U /* 400 kHz */
#define STM32_I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */
#define STM32_I2C_USE_ANALOG_FILTER 1U
#define STM32_I2C_DIGITAL_FILTER_COEF 0U
#define STM32_I2C_PRESC_MAX 16U
#define STM32_I2C_SCLDEL_MAX 16U
#define STM32_I2C_SDADEL_MAX 16U
#define STM32_I2C_SCLH_MAX 256U
#define STM32_I2C_SCLL_MAX 256U
/* I2C_DEVICE_Private_Types */
struct stm32_i2c_charac_t {
uint32_t freq; /* Frequency in Hz */
uint32_t freq_min; /* Minimum frequency in Hz */
uint32_t freq_max; /* Maximum frequency in Hz */
uint32_t hddat_min; /* Minimum data hold time in ns */
uint32_t vddat_max; /* Maximum data valid time in ns */
uint32_t sudat_min; /* Minimum data setup time in ns */
uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */
uint32_t hscl_min; /* Minimum high period of SCL clock in ns */
uint32_t trise; /* Rise time in ns */
uint32_t tfall; /* Fall time in ns */
uint32_t dnf; /* Digital noise filter coefficient */
};
struct stm32_i2c_timings_t {
uint32_t presc; /* Timing prescaler */
uint32_t tscldel; /* SCL delay */
uint32_t tsdadel; /* SDA delay */
uint32_t sclh; /* SCL high period */
uint32_t scll; /* SCL low period */
};
/* I2C_DEVICE Private Constants */
static const struct stm32_i2c_charac_t stm32_i2c_charac[] = {
[STM32_I2C_SPEED_FREQ_STANDARD] = {
.freq = 100000,
.freq_min = 80000,
.freq_max = 120000,
.hddat_min = 0,
.vddat_max = 3450,
.sudat_min = 250,
.lscl_min = 4700,
.hscl_min = 4000,
.trise = 640,
.tfall = 20,
.dnf = STM32_I2C_DIGITAL_FILTER_COEF,
},
[STM32_I2C_SPEED_FREQ_FAST] = {
.freq = 400000,
.freq_min = 320000,
.freq_max = 480000,
.hddat_min = 0,
.vddat_max = 900,
.sudat_min = 100,
.lscl_min = 1300,
.hscl_min = 600,
.trise = 250,
.tfall = 100,
.dnf = STM32_I2C_DIGITAL_FILTER_COEF,
},
[STM32_I2C_SPEED_FREQ_FAST_PLUS] = {
.freq = 1000000,
.freq_min = 800000,
.freq_max = 1200000,
.hddat_min = 0,
.vddat_max = 450,
.sudat_min = 50,
.lscl_min = 500,
.hscl_min = 260,
.trise = 60,
.tfall = 100,
.dnf = STM32_I2C_DIGITAL_FILTER_COEF,
},
};
static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR];
static uint32_t i2c_valid_timing_nbr;
#endif /* CONFIG_I2C_STM32_V2_TIMING */
static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave,
uint32_t transfer)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (LL_I2C_IsEnabledReloadMode(i2c)) {
LL_I2C_SetTransferSize(i2c, msg->len);
} else {
if (I2C_ADDR_10_BITS & data->dev_config) {
LL_I2C_SetMasterAddressingMode(i2c,
LL_I2C_ADDRESSING_MODE_10BIT);
LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave);
} else {
LL_I2C_SetMasterAddressingMode(i2c,
LL_I2C_ADDRESSING_MODE_7BIT);
LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1);
}
if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags &&
!(*next_msg_flags & I2C_MSG_RESTART)) {
LL_I2C_EnableReloadMode(i2c);
} else {
LL_I2C_DisableReloadMode(i2c);
}
LL_I2C_DisableAutoEndMode(i2c);
LL_I2C_SetTransferRequest(i2c, transfer);
LL_I2C_SetTransferSize(i2c, msg->len);
#if defined(CONFIG_I2C_TARGET)
data->master_active = true;
#endif
LL_I2C_Enable(i2c);
LL_I2C_GenerateStartCondition(i2c);
}
}
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
LL_I2C_DisableIT_TX(i2c);
LL_I2C_DisableIT_RX(i2c);
LL_I2C_DisableIT_STOP(i2c);
LL_I2C_DisableIT_NACK(i2c);
LL_I2C_DisableIT_TC(i2c);
if (!data->smbalert_active) {
LL_I2C_DisableIT_ERR(i2c);
}
}
static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
LL_I2C_EnableIT_STOP(i2c);
LL_I2C_EnableIT_NACK(i2c);
LL_I2C_EnableIT_TC(i2c);
LL_I2C_EnableIT_ERR(i2c);
}
static void stm32_i2c_master_mode_end(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
stm32_i2c_disable_transfer_interrupts(dev);
if (LL_I2C_IsEnabledReloadMode(i2c)) {
LL_I2C_DisableReloadMode(i2c);
}
#if defined(CONFIG_I2C_TARGET)
data->master_active = false;
if (!data->slave_attached && !data->smbalert_active) {
LL_I2C_Disable(i2c);
}
#else
if (!data->smbalert_active) {
LL_I2C_Disable(i2c);
}
#endif
k_sem_give(&data->device_sync_sem);
}
#if defined(CONFIG_I2C_TARGET)
static void stm32_i2c_slave_event(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
const struct i2c_target_callbacks *slave_cb;
struct i2c_target_config *slave_cfg;
if (data->slave_cfg->flags != I2C_TARGET_FLAGS_ADDR_10_BITS) {
uint8_t slave_address;
/* Choose the right slave from the address match code */
slave_address = LL_I2C_GetAddressMatchCode(i2c) >> 1;
if (data->slave_cfg != NULL &&
slave_address == data->slave_cfg->address) {
slave_cfg = data->slave_cfg;
} else if (data->slave2_cfg != NULL &&
slave_address == data->slave2_cfg->address) {
slave_cfg = data->slave2_cfg;
} else {
__ASSERT_NO_MSG(0);
return;
}
} else {
/* On STM32 the LL_I2C_GetAddressMatchCode & (ISR register) returns
* only 7bits of address match so 10 bit dual addressing is broken.
* Revert to assuming single address match.
*/
if (data->slave_cfg != NULL) {
slave_cfg = data->slave_cfg;
} else {
__ASSERT_NO_MSG(0);
return;
}
}
slave_cb = slave_cfg->callbacks;
if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
uint8_t val;
slave_cb->read_processed(slave_cfg, &val);
LL_I2C_TransmitData8(i2c, val);
return;
}
if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
uint8_t val = LL_I2C_ReceiveData8(i2c);
if (slave_cb->write_received(slave_cfg, val)) {
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
}
return;
}
if (LL_I2C_IsActiveFlag_NACK(i2c)) {
LL_I2C_ClearFlag_NACK(i2c);
}
if (LL_I2C_IsActiveFlag_STOP(i2c)) {
stm32_i2c_disable_transfer_interrupts(dev);
/* Flush remaining TX byte before clearing Stop Flag */
LL_I2C_ClearFlag_TXE(i2c);
LL_I2C_ClearFlag_STOP(i2c);
slave_cb->stop(slave_cfg);
/* Prepare to ACK next transmissions address byte */
LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
}
if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
uint32_t dir;
LL_I2C_ClearFlag_ADDR(i2c);
dir = LL_I2C_GetTransferDirection(i2c);
if (dir == LL_I2C_DIRECTION_WRITE) {
slave_cb->write_requested(slave_cfg);
LL_I2C_EnableIT_RX(i2c);
} else {
uint8_t val;
slave_cb->read_requested(slave_cfg, &val);
LL_I2C_TransmitData8(i2c, val);
LL_I2C_EnableIT_TX(i2c);
}
stm32_i2c_enable_transfer_interrupts(dev);
}
}
/* Attach and start I2C as target */
int i2c_stm32_target_register(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t bitrate_cfg;
int ret;
if (!config) {
return -EINVAL;
}
if (data->slave_cfg && data->slave2_cfg) {
return -EBUSY;
}
if (data->master_active) {
return -EBUSY;
}
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
if (ret < 0) {
LOG_ERR("i2c: failure initializing");
return ret;
}
#if defined(CONFIG_PM_DEVICE_RUNTIME)
if (pm_device_wakeup_is_capable(dev)) {
/* Mark device as active */
(void)pm_device_runtime_get(dev);
/* Enable wake-up from stop */
LOG_DBG("i2c: enabling wakeup from stop");
LL_I2C_EnableWakeUpFromStop(cfg->i2c);
}
#endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */
LL_I2C_Enable(i2c);
if (!data->slave_cfg) {
data->slave_cfg = config;
if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
LL_I2C_SetOwnAddress1(i2c, config->address, LL_I2C_OWNADDRESS1_10BIT);
LOG_DBG("i2c: target #1 registered with 10-bit address");
} else {
LL_I2C_SetOwnAddress1(i2c, config->address << 1U, LL_I2C_OWNADDRESS1_7BIT);
LOG_DBG("i2c: target #1 registered with 7-bit address");
}
LL_I2C_EnableOwnAddress1(i2c);
LOG_DBG("i2c: target #1 registered");
} else {
data->slave2_cfg = config;
if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -EINVAL;
}
LL_I2C_SetOwnAddress2(i2c, config->address << 1U,
LL_I2C_OWNADDRESS2_NOMASK);
LL_I2C_EnableOwnAddress2(i2c);
LOG_DBG("i2c: target #2 registered");
}
data->slave_attached = true;
LL_I2C_EnableIT_ADDR(i2c);
return 0;
}
int i2c_stm32_target_unregister(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
if (!data->slave_attached) {
return -EINVAL;
}
if (data->master_active) {
return -EBUSY;
}
if (config == data->slave_cfg) {
LL_I2C_DisableOwnAddress1(i2c);
data->slave_cfg = NULL;
LOG_DBG("i2c: slave #1 unregistered");
} else if (config == data->slave2_cfg) {
LL_I2C_DisableOwnAddress2(i2c);
data->slave2_cfg = NULL;
LOG_DBG("i2c: slave #2 unregistered");
} else {
return -EINVAL;
}
/* Return if there is a slave remaining */
if (data->slave_cfg || data->slave2_cfg) {
LOG_DBG("i2c: target#%c still registered", data->slave_cfg?'1':'2');
return 0;
}
/* Otherwise disable I2C */
LL_I2C_DisableIT_ADDR(i2c);
stm32_i2c_disable_transfer_interrupts(dev);
LL_I2C_ClearFlag_NACK(i2c);
LL_I2C_ClearFlag_STOP(i2c);
LL_I2C_ClearFlag_ADDR(i2c);
if (!data->smbalert_active) {
LL_I2C_Disable(i2c);
}
#if defined(CONFIG_PM_DEVICE_RUNTIME)
if (pm_device_wakeup_is_capable(dev)) {
/* Disable wake-up from STOP */
LOG_DBG("i2c: disabling wakeup from stop");
LL_I2C_DisableWakeUpFromStop(i2c);
/* Release the device */
(void)pm_device_runtime_put(dev);
}
#endif /* defined(CONFIG_PM_DEVICE_RUNTIME) */
data->slave_attached = false;
return 0;
}
#endif /* defined(CONFIG_I2C_TARGET) */
static void stm32_i2c_event(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
#if defined(CONFIG_I2C_TARGET)
if (data->slave_attached && !data->master_active) {
stm32_i2c_slave_event(dev);
return;
}
#endif
if (data->current.len) {
/* Send next byte */
if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
LL_I2C_TransmitData8(i2c, *data->current.buf);
}
/* Receive next byte */
if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
*data->current.buf = LL_I2C_ReceiveData8(i2c);
}
data->current.buf++;
data->current.len--;
}
/* NACK received */
if (LL_I2C_IsActiveFlag_NACK(i2c)) {
LL_I2C_ClearFlag_NACK(i2c);
data->current.is_nack = 1U;
/*
* AutoEndMode is always disabled in master mode,
* so send a stop condition manually
*/
LL_I2C_GenerateStopCondition(i2c);
return;
}
/* STOP received */
if (LL_I2C_IsActiveFlag_STOP(i2c)) {
LL_I2C_ClearFlag_STOP(i2c);
LL_I2C_DisableReloadMode(i2c);
goto end;
}
/* Transfer Complete or Transfer Complete Reload */
if (LL_I2C_IsActiveFlag_TC(i2c) ||
LL_I2C_IsActiveFlag_TCR(i2c)) {
/* Issue stop condition if necessary */
if (data->current.msg->flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
} else {
stm32_i2c_disable_transfer_interrupts(dev);
k_sem_give(&data->device_sync_sem);
}
}
return;
end:
stm32_i2c_master_mode_end(dev);
}
static int stm32_i2c_error(const struct device *dev)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
#if defined(CONFIG_I2C_TARGET)
if (data->slave_attached && !data->master_active) {
/* No need for a slave error function right now. */
return 0;
}
#endif
if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
LL_I2C_ClearFlag_ARLO(i2c);
data->current.is_arlo = 1U;
goto end;
}
if (LL_I2C_IsActiveFlag_BERR(i2c)) {
LL_I2C_ClearFlag_BERR(i2c);
data->current.is_err = 1U;
goto end;
}
#if defined(CONFIG_SMBUS_STM32_SMBALERT)
if (LL_I2C_IsActiveSMBusFlag_ALERT(i2c)) {
LL_I2C_ClearSMBusFlag_ALERT(i2c);
if (data->smbalert_cb_func != NULL) {
data->smbalert_cb_func(data->smbalert_cb_dev);
}
goto end;
}
#endif
return 0;
end:
stm32_i2c_master_mode_end(dev);
return -EIO;
}
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
void stm32_i2c_combined_isr(void *arg)
{
const struct device *dev = (const struct device *) arg;
if (stm32_i2c_error(dev)) {
return;
}
stm32_i2c_event(dev);
}
#else
void stm32_i2c_event_isr(void *arg)
{
const struct device *dev = (const struct device *) arg;
stm32_i2c_event(dev);
}
void stm32_i2c_error_isr(void *arg)
{
const struct device *dev = (const struct device *) arg;
stm32_i2c_error(dev);
}
#endif
static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
bool is_timeout = false;
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.is_write = 1U;
data->current.is_nack = 0U;
data->current.is_err = 0U;
data->current.msg = msg;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
stm32_i2c_enable_transfer_interrupts(dev);
LL_I2C_EnableIT_TX(i2c);
if (k_sem_take(&data->device_sync_sem,
K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
stm32_i2c_master_mode_end(dev);
k_sem_take(&data->device_sync_sem, K_FOREVER);
is_timeout = true;
}
if (data->current.is_nack || data->current.is_err ||
data->current.is_arlo || is_timeout) {
goto error;
}
return 0;
error:
if (data->current.is_arlo) {
LOG_DBG("%s: ARLO %d", __func__,
data->current.is_arlo);
data->current.is_arlo = 0U;
}
if (data->current.is_nack) {
LOG_DBG("%s: NACK", __func__);
data->current.is_nack = 0U;
}
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", __func__,
data->current.is_err);
data->current.is_err = 0U;
}
if (is_timeout) {
LOG_DBG("%s: TIMEOUT", __func__);
}
return -EIO;
}
static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
bool is_timeout = false;
data->current.len = msg->len;
data->current.buf = msg->buf;
data->current.is_write = 0U;
data->current.is_arlo = 0U;
data->current.is_err = 0U;
data->current.is_nack = 0U;
data->current.msg = msg;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
stm32_i2c_enable_transfer_interrupts(dev);
LL_I2C_EnableIT_RX(i2c);
if (k_sem_take(&data->device_sync_sem,
K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
stm32_i2c_master_mode_end(dev);
k_sem_take(&data->device_sync_sem, K_FOREVER);
is_timeout = true;
}
if (data->current.is_nack || data->current.is_err ||
data->current.is_arlo || is_timeout) {
goto error;
}
return 0;
error:
if (data->current.is_arlo) {
LOG_DBG("%s: ARLO %d", __func__,
data->current.is_arlo);
data->current.is_arlo = 0U;
}
if (data->current.is_nack) {
LOG_DBG("%s: NACK", __func__);
data->current.is_nack = 0U;
}
if (data->current.is_err) {
LOG_DBG("%s: ERR %d", __func__,
data->current.is_err);
data->current.is_err = 0U;
}
if (is_timeout) {
LOG_DBG("%s: TIMEOUT", __func__);
}
return -EIO;
}
#else /* !CONFIG_I2C_STM32_INTERRUPT */
static inline int check_errors(const struct device *dev, const char *funcname)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
if (LL_I2C_IsActiveFlag_NACK(i2c)) {
LL_I2C_ClearFlag_NACK(i2c);
LOG_DBG("%s: NACK", funcname);
goto error;
}
if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
LL_I2C_ClearFlag_ARLO(i2c);
LOG_DBG("%s: ARLO", funcname);
goto error;
}
if (LL_I2C_IsActiveFlag_OVR(i2c)) {
LL_I2C_ClearFlag_OVR(i2c);
LOG_DBG("%s: OVR", funcname);
goto error;
}
if (LL_I2C_IsActiveFlag_BERR(i2c)) {
LL_I2C_ClearFlag_BERR(i2c);
LOG_DBG("%s: BERR", funcname);
goto error;
}
return 0;
error:
if (LL_I2C_IsEnabledReloadMode(i2c)) {
LL_I2C_DisableReloadMode(i2c);
}
return -EIO;
}
static inline int msg_done(const struct device *dev,
unsigned int current_msg_flags)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
/* Wait for transfer to complete */
while (!LL_I2C_IsActiveFlag_TC(i2c) && !LL_I2C_IsActiveFlag_TCR(i2c)) {
if (check_errors(dev, __func__)) {
return -EIO;
}
}
/* Issue stop condition if necessary */
if (current_msg_flags & I2C_MSG_STOP) {
LL_I2C_GenerateStopCondition(i2c);
while (!LL_I2C_IsActiveFlag_STOP(i2c)) {
}
LL_I2C_ClearFlag_STOP(i2c);
LL_I2C_DisableReloadMode(i2c);
}
return 0;
}
static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
unsigned int len = 0U;
uint8_t *buf = msg->buf;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
len = msg->len;
while (len) {
while (1) {
if (LL_I2C_IsActiveFlag_TXIS(i2c)) {
break;
}
if (check_errors(dev, __func__)) {
return -EIO;
}
}
LL_I2C_TransmitData8(i2c, *buf);
buf++;
len--;
}
return msg_done(dev, msg->flags);
}
static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
uint8_t *next_msg_flags, uint16_t slave)
{
const struct i2c_stm32_config *cfg = dev->config;
I2C_TypeDef *i2c = cfg->i2c;
unsigned int len = 0U;
uint8_t *buf = msg->buf;
msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_READ);
len = msg->len;
while (len) {
while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
if (check_errors(dev, __func__)) {
return -EIO;
}
}
*buf = LL_I2C_ReceiveData8(i2c);
buf++;
len--;
}
return msg_done(dev, msg->flags);
}
#endif
#ifdef CONFIG_I2C_STM32_V2_TIMING
/*
* Macro used to fix the compliance check warning :
* "DEEP_INDENTATION: Too many leading tabs - consider code refactoring
* in the i2c_compute_scll_sclh() function below
*/
#define I2C_LOOP_SCLH(); \
if ((tscl >= clk_min) && \
(tscl <= clk_max) && \
(tscl_h >= stm32_i2c_charac[i2c_speed].hscl_min) && \
(ti2cclk < tscl_h)) { \
\
int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; \
\
if (error < 0) { \
error = -error; \
} \
\
if ((uint32_t)error < prev_error) { \
prev_error = (uint32_t)error; \
i2c_valid_timing[count].scll = scll; \
i2c_valid_timing[count].sclh = sclh; \
ret = count; \
} \
}
/*
* @brief Calculate SCLL and SCLH and find best configuration.
* @param clock_src_freq I2C source clock in Hz.
* @param i2c_speed I2C frequency (index).
* @retval config index (0 to I2C_VALID_TIMING_NBR], 0xFFFFFFFF for no valid config.
*/
uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed)
{
uint32_t ret = 0xFFFFFFFFU;
uint32_t ti2cclk;
uint32_t ti2cspeed;
uint32_t prev_error;
uint32_t dnf_delay;
uint32_t clk_min, clk_max;
uint32_t scll, sclh;
uint32_t tafdel_min;
ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq;
ti2cspeed = (NSEC_PER_SEC + (stm32_i2c_charac[i2c_speed].freq / 2U)) /
stm32_i2c_charac[i2c_speed].freq;
tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
STM32_I2C_ANALOG_FILTER_DELAY_MIN :
0U;
/* tDNF = DNF x tI2CCLK */
dnf_delay = stm32_i2c_charac[i2c_speed].dnf * ti2cclk;
clk_max = NSEC_PER_SEC / stm32_i2c_charac[i2c_speed].freq_min;
clk_min = NSEC_PER_SEC / stm32_i2c_charac[i2c_speed].freq_max;
prev_error = ti2cspeed;
for (uint32_t count = 0; count < STM32_I2C_VALID_TIMING_NBR; count++) {
/* tPRESC = (PRESC+1) x tI2CCLK*/
uint32_t tpresc = (i2c_valid_timing[count].presc + 1U) * ti2cclk;
for (scll = 0; scll < STM32_I2C_SCLL_MAX; scll++) {
/* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */
uint32_t tscl_l = tafdel_min + dnf_delay +
(2U * ti2cclk) + ((scll + 1U) * tpresc);
/*
* The I2CCLK period tI2CCLK must respect the following conditions:
* tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH
*/
if ((tscl_l > stm32_i2c_charac[i2c_speed].lscl_min) &&
(ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) {
for (sclh = 0; sclh < STM32_I2C_SCLH_MAX; sclh++) {
/*
* tHIGH(min) <= tAF(min) + tDNF +
* 2 x tI2CCLK + [(SCLH+1) x tPRESC]
*/
uint32_t tscl_h = tafdel_min + dnf_delay +
(2U * ti2cclk) + ((sclh + 1U) * tpresc);
/* tSCL = tf + tLOW + tr + tHIGH */
uint32_t tscl = tscl_l +
tscl_h + stm32_i2c_charac[i2c_speed].trise +
stm32_i2c_charac[i2c_speed].tfall;
/* get timings with the lowest clock error */
I2C_LOOP_SCLH();
}
}
}
}
return ret;
}
/*
* Macro used to fix the compliance check warning :
* "DEEP_INDENTATION: Too many leading tabs - consider code refactoring
* in the i2c_compute_presc_scldel_sdadel() function below
*/
#define I2C_LOOP_SDADEL(); \
\
if ((tsdadel >= (uint32_t)tsdadel_min) && \
(tsdadel <= (uint32_t)tsdadel_max)) { \
if (presc != prev_presc) { \
i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; \
i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; \
i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; \
prev_presc = presc; \
i2c_valid_timing_nbr++; \
\
if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) { \
break; \
} \
} \
}
/*
* @brief Compute PRESC, SCLDEL and SDADEL.
* @param clock_src_freq I2C source clock in Hz.
* @param i2c_speed I2C frequency (index).
* @retval None.
*/
void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t i2c_speed)
{
uint32_t prev_presc = STM32_I2C_PRESC_MAX;
uint32_t ti2cclk;
int32_t tsdadel_min, tsdadel_max;
int32_t tscldel_min;
uint32_t presc, scldel, sdadel;
uint32_t tafdel_min, tafdel_max;
ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq;
tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0U;
tafdel_max = (STM32_I2C_USE_ANALOG_FILTER == 1U) ?
STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0U;
/*
* tDNF = DNF x tI2CCLK
* tPRESC = (PRESC+1) x tI2CCLK
* SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC}
* SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC}
*/
tsdadel_min = (int32_t)stm32_i2c_charac[i2c_speed].tfall +
(int32_t)stm32_i2c_charac[i2c_speed].hddat_min -
(int32_t)tafdel_min -
(int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 3) *
(int32_t)ti2cclk);
tsdadel_max = (int32_t)stm32_i2c_charac[i2c_speed].vddat_max -
(int32_t)stm32_i2c_charac[i2c_speed].trise -
(int32_t)tafdel_max -
(int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 4) *
(int32_t)ti2cclk);
/* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */
tscldel_min = (int32_t)stm32_i2c_charac[i2c_speed].trise +
(int32_t)stm32_i2c_charac[i2c_speed].sudat_min;
if (tsdadel_min <= 0) {
tsdadel_min = 0;
}
if (tsdadel_max <= 0) {
tsdadel_max = 0;
}
for (presc = 0; presc < STM32_I2C_PRESC_MAX; presc++) {
for (scldel = 0; scldel < STM32_I2C_SCLDEL_MAX; scldel++) {
/* TSCLDEL = (SCLDEL+1) * (PRESC+1) * TI2CCLK */
uint32_t tscldel = (scldel + 1U) * (presc + 1U) * ti2cclk;
if (tscldel >= (uint32_t)tscldel_min) {
for (sdadel = 0; sdadel < STM32_I2C_SDADEL_MAX; sdadel++) {
/* TSDADEL = SDADEL * (PRESC+1) * TI2CCLK */
uint32_t tsdadel = (sdadel * (presc + 1U)) * ti2cclk;
I2C_LOOP_SDADEL();
}
if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) {
return;
}
}
}
}
}
int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t timing = 0U;
uint32_t idx;
uint32_t speed = 0U;
uint32_t i2c_freq = cfg->bitrate;
/* Reset valid timing count at the beginning of each new computation */
i2c_valid_timing_nbr = 0;
if ((clock != 0U) && (i2c_freq != 0U)) {
for (speed = 0 ; speed <= (uint32_t)STM32_I2C_SPEED_FREQ_FAST_PLUS ; speed++) {
if ((i2c_freq >= stm32_i2c_charac[speed].freq_min) &&
(i2c_freq <= stm32_i2c_charac[speed].freq_max)) {
i2c_compute_presc_scldel_sdadel(clock, speed);
idx = i2c_compute_scll_sclh(clock, speed);
if (idx < STM32_I2C_VALID_TIMING_NBR) {
timing = ((i2c_valid_timing[idx].presc &
0x0FU) << 28) |
((i2c_valid_timing[idx].tscldel & 0x0FU) << 20) |
((i2c_valid_timing[idx].tsdadel & 0x0FU) << 16) |
((i2c_valid_timing[idx].sclh & 0xFFU) << 8) |
((i2c_valid_timing[idx].scll & 0xFFU) << 0);
}
break;
}
}
}
/* Fill the current timing value in data structure at runtime */
data->current_timing.periph_clock = clock;
data->current_timing.i2c_speed = i2c_freq;
data->current_timing.timing_setting = timing;
LL_I2C_SetTiming(i2c, timing);
return 0;
}
#else/* CONFIG_I2C_STM32_V2_TIMING */
int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
uint32_t i2c_hold_time_min, i2c_setup_time_min;
uint32_t i2c_h_min_time, i2c_l_min_time;
uint32_t presc = 1U;
uint32_t timing = 0U;
/* Look for an adequate preset timing value */
for (uint32_t i = 0; i < cfg->n_timings; i++) {
const struct i2c_config_timing *preset = &cfg->timings[i];
uint32_t speed = i2c_map_dt_bitrate(preset->i2c_speed);
if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config))
&& (preset->periph_clock == clock)) {
/* Found a matching periph clock and i2c speed */
LL_I2C_SetTiming(i2c, preset->timing_setting);
return 0;
}
}
/* No preset timing was provided, let's dynamically configure */
switch (I2C_SPEED_GET(data->dev_config)) {
case I2C_SPEED_STANDARD:
i2c_h_min_time = 4000U;
i2c_l_min_time = 4700U;
i2c_hold_time_min = 500U;
i2c_setup_time_min = 1250U;
break;
case I2C_SPEED_FAST:
i2c_h_min_time = 600U;
i2c_l_min_time = 1300U;
i2c_hold_time_min = 375U;
i2c_setup_time_min = 500U;
break;
default:
LOG_ERR("i2c: speed above \"fast\" requires manual timing configuration, "
"see \"timings\" property of st,stm32-i2c-v2 devicetree binding");
return -EINVAL;
}
/* Calculate period until prescaler matches */
do {
uint32_t t_presc = clock / presc;
uint32_t ns_presc = NSEC_PER_SEC / t_presc;
uint32_t sclh = i2c_h_min_time / ns_presc;
uint32_t scll = i2c_l_min_time / ns_presc;
uint32_t sdadel = i2c_hold_time_min / ns_presc;
uint32_t scldel = i2c_setup_time_min / ns_presc;
if ((sclh - 1) > 255 || (scll - 1) > 255) {
++presc;
continue;
}
if (sdadel > 15 || (scldel - 1) > 15) {
++presc;
continue;
}
timing = __LL_I2C_CONVERT_TIMINGS(presc - 1,
scldel - 1, sdadel, sclh - 1, scll - 1);
break;
} while (presc < 16);
if (presc >= 16U) {
LOG_ERR("I2C:failed to find prescaler value");
return -EINVAL;
}
LOG_DBG("I2C TIMING = 0x%x", timing);
LL_I2C_SetTiming(i2c, timing);
return 0;
}
#endif /* CONFIG_I2C_STM32_V2_TIMING */
int stm32_i2c_transaction(const struct device *dev,
struct i2c_msg msg, uint8_t *next_msg_flags,
uint16_t periph)
{
/*
* Perform a I2C transaction, while taking into account the STM32 I2C V2
* peripheral has a limited maximum chunk size. Take appropriate action
* if the message to send exceeds that limit.
*
* The last chunk of a transmission uses this function's next_msg_flags
* parameter for its backend calls (_write/_read). Any previous chunks
* use a copy of the current message's flags, with the STOP and RESTART
* bits turned off. This will cause the backend to use reload-mode,
* which will make the combination of all chunks to look like one big
* transaction on the wire.
*/
const uint32_t i2c_stm32_maxchunk = 255U;
const uint8_t saved_flags = msg.flags;
uint8_t combine_flags =
saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART);
uint8_t *flagsp = NULL;
uint32_t rest = msg.len;
int ret = 0;
do { /* do ... while to allow zero-length transactions */
if (msg.len > i2c_stm32_maxchunk) {
msg.len = i2c_stm32_maxchunk;
msg.flags &= ~I2C_MSG_STOP;
flagsp = &combine_flags;
} else {
msg.flags = saved_flags;
flagsp = next_msg_flags;
}
if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = stm32_i2c_msg_write(dev, &msg, flagsp, periph);
} else {
ret = stm32_i2c_msg_read(dev, &msg, flagsp, periph);
}
if (ret < 0) {
break;
}
rest -= msg.len;
msg.buf += msg.len;
msg.len = rest;
} while (rest > 0U);
return ret;
}
``` | /content/code_sandbox/drivers/i2c/i2c_ll_stm32_v2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,647 |
```unknown
config I2C_EMUL
bool "I2C emulator"
default y
depends on DT_HAS_ZEPHYR_I2C_EMUL_CONTROLLER_ENABLED
depends on EMUL
help
Enable the I2C emulator driver. This is a fake driver in that it
does not talk to real hardware. Instead it talks to emulation
drivers that pretend to be devices on the emulated I2C bus. It is
used for testing drivers for I2C devices.
``` | /content/code_sandbox/drivers/i2c/Kconfig.i2c_emul | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```c
/*
*
* Driver for the Xilinx AXI IIC Bus Interface.
* This is an FPGA logic core as described by Xilinx document PG090.
*/
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_xilinx_axi, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#include "i2c_xilinx_axi.h"
struct i2c_xilinx_axi_config {
mem_addr_t base;
void (*irq_config_func)(const struct device *dev);
/* Whether device has working dynamic read (broken prior to core rev. 2.1) */
bool dyn_read_working;
};
struct i2c_xilinx_axi_data {
struct k_event irq_event;
/* Serializes between ISR and other calls */
struct k_spinlock lock;
/* Provides exclusion against multiple concurrent requests */
struct k_mutex mutex;
#if defined(CONFIG_I2C_TARGET)
struct i2c_target_config *target_cfg;
bool target_reading;
bool target_read_aborted;
bool target_writing;
#endif
};
static void i2c_xilinx_axi_reinit(const struct i2c_xilinx_axi_config *config)
{
LOG_DBG("Controller reinit");
sys_write32(SOFTR_KEY, config->base + REG_SOFTR);
sys_write32(CR_TX_FIFO_RST, config->base + REG_CR);
sys_write32(CR_EN, config->base + REG_CR);
sys_write32(GIE_ENABLE, config->base + REG_GIE);
}
#if defined(CONFIG_I2C_TARGET)
#define I2C_XILINX_AXI_TARGET_INTERRUPTS \
(ISR_ADDR_TARGET | ISR_NOT_ADDR_TARGET | ISR_RX_FIFO_FULL | ISR_TX_FIFO_EMPTY | \
ISR_TX_ERR_TARGET_COMP)
static void i2c_xilinx_axi_target_setup(const struct i2c_xilinx_axi_config *config,
struct i2c_target_config *cfg)
{
i2c_xilinx_axi_reinit(config);
sys_write32(ISR_ADDR_TARGET, config->base + REG_IER);
sys_write32(cfg->address << 1, config->base + REG_ADR);
sys_write32(0, config->base + REG_RX_FIFO_PIRQ);
}
static int i2c_xilinx_axi_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
const struct i2c_xilinx_axi_config *config = dev->config;
struct i2c_xilinx_axi_data *data = dev->data;
k_spinlock_key_t key;
int ret;
if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
/* Optionally supported in core, but not implemented in driver yet */
return -EOPNOTSUPP;
}
k_mutex_lock(&data->mutex, K_FOREVER);
key = k_spin_lock(&data->lock);
if (data->target_cfg) {
ret = -EBUSY;
goto out_unlock;
}
data->target_cfg = cfg;
i2c_xilinx_axi_target_setup(config, cfg);
ret = 0;
out_unlock:
k_spin_unlock(&data->lock, key);
LOG_DBG("Target register ret=%d", ret);
k_mutex_unlock(&data->mutex);
return ret;
}
static int i2c_xilinx_axi_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
const struct i2c_xilinx_axi_config *config = dev->config;
struct i2c_xilinx_axi_data *data = dev->data;
k_spinlock_key_t key;
uint32_t int_enable;
int ret;
k_mutex_lock(&data->mutex, K_FOREVER);
key = k_spin_lock(&data->lock);
if (!data->target_cfg) {
ret = -EINVAL;
goto out_unlock;
}
if (data->target_reading || data->target_writing) {
ret = -EBUSY;
goto out_unlock;
}
data->target_cfg = NULL;
sys_write32(0, config->base + REG_ADR);
sys_write32(CR_EN, config->base + REG_CR);
int_enable = sys_read32(config->base + REG_IER);
int_enable &= ~I2C_XILINX_AXI_TARGET_INTERRUPTS;
sys_write32(int_enable, config->base + REG_IER);
ret = 0;
out_unlock:
k_spin_unlock(&data->lock, key);
LOG_DBG("Target unregister ret=%d", ret);
k_mutex_unlock(&data->mutex);
return ret;
}
static void i2c_xilinx_axi_target_isr(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, uint32_t *int_status,
uint32_t *ints_to_clear, uint32_t *int_enable)
{
if (*int_status & ISR_ADDR_TARGET) {
LOG_DBG("Addressed as target");
*int_status &= ~ISR_ADDR_TARGET;
*int_enable &= ~ISR_ADDR_TARGET;
*int_enable |= ISR_NOT_ADDR_TARGET;
*ints_to_clear |= ISR_NOT_ADDR_TARGET;
if (sys_read32(config->base + REG_SR) & SR_SRW) {
uint8_t read_byte;
data->target_reading = true;
*ints_to_clear |= ISR_TX_FIFO_EMPTY | ISR_TX_ERR_TARGET_COMP;
*int_enable |= ISR_TX_FIFO_EMPTY | ISR_TX_ERR_TARGET_COMP;
if ((*data->target_cfg->callbacks->read_requested)(data->target_cfg,
&read_byte)) {
LOG_DBG("target read_requested rejected");
data->target_read_aborted = true;
read_byte = 0xFF;
}
sys_write32(read_byte, config->base + REG_TX_FIFO);
} else {
data->target_writing = true;
*int_enable |= ISR_RX_FIFO_FULL;
if ((*data->target_cfg->callbacks->write_requested)(data->target_cfg)) {
uint32_t cr = sys_read32(config->base + REG_CR);
LOG_DBG("target write_requested rejected");
cr |= CR_TXAK;
sys_write32(cr, config->base + REG_CR);
}
}
} else if (*int_status & ISR_NOT_ADDR_TARGET) {
LOG_DBG("Not addressed as target");
(*data->target_cfg->callbacks->stop)(data->target_cfg);
data->target_reading = false;
data->target_read_aborted = false;
data->target_writing = false;
sys_write32(CR_EN, config->base + REG_CR);
*int_status &= ~ISR_NOT_ADDR_TARGET;
*int_enable &= ~I2C_XILINX_AXI_TARGET_INTERRUPTS;
*int_enable |= ISR_ADDR_TARGET;
*ints_to_clear |= ISR_ADDR_TARGET;
} else if (data->target_writing && (*int_status & ISR_RX_FIFO_FULL)) {
*int_status &= ~ISR_RX_FIFO_FULL;
const uint8_t written_byte =
sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;
if ((*data->target_cfg->callbacks->write_received)(data->target_cfg,
written_byte)) {
uint32_t cr = sys_read32(config->base + REG_CR);
LOG_DBG("target write_received rejected");
cr |= CR_TXAK;
sys_write32(cr, config->base + REG_CR);
}
} else if (data->target_reading && (*int_status & ISR_TX_ERR_TARGET_COMP)) {
/* Controller has NAKed the last byte read, so no more to send.
* Ignore TX FIFO empty so we don't write an extra byte.
*/
LOG_DBG("target read completed");
*int_status &= ~ISR_TX_ERR_TARGET_COMP;
*int_enable &= ~ISR_TX_FIFO_EMPTY;
*ints_to_clear |= ISR_TX_FIFO_EMPTY;
} else if (data->target_reading && (*int_status & ISR_TX_FIFO_EMPTY)) {
*int_status &= ~ISR_TX_FIFO_EMPTY;
uint8_t read_byte = 0xFF;
if (!data->target_read_aborted &&
(*data->target_cfg->callbacks->read_processed)(data->target_cfg,
&read_byte)) {
LOG_DBG("target read_processed rejected");
data->target_read_aborted = true;
}
sys_write32(read_byte, config->base + REG_TX_FIFO);
}
}
#endif
static void i2c_xilinx_axi_isr(const struct device *dev)
{
const struct i2c_xilinx_axi_config *config = dev->config;
struct i2c_xilinx_axi_data *data = dev->data;
const k_spinlock_key_t key = k_spin_lock(&data->lock);
uint32_t int_enable = sys_read32(config->base + REG_IER);
uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable;
uint32_t ints_to_clear = int_status;
LOG_DBG("ISR called for 0x%08" PRIxPTR ", status 0x%02x", config->base, int_status);
if (int_status & ISR_ARB_LOST) {
/* Must clear MSMS before clearing interrupt */
uint32_t cr = sys_read32(config->base + REG_CR);
cr &= ~CR_MSMS;
sys_write32(cr, config->base + REG_CR);
}
#if defined(CONFIG_I2C_TARGET)
if (data->target_cfg && (int_status & I2C_XILINX_AXI_TARGET_INTERRUPTS)) {
/* This clears events from int_status which are already handled */
i2c_xilinx_axi_target_isr(config, data, &int_status, &ints_to_clear, &int_enable);
}
#endif
/* Mask any interrupts which have not already been handled separately */
sys_write32(int_enable & ~int_status, config->base + REG_IER);
/* Be careful, writing 1 to a bit that is not currently set in ISR will SET it! */
sys_write32(ints_to_clear & sys_read32(config->base + REG_ISR), config->base + REG_ISR);
k_spin_unlock(&data->lock, key);
if (int_status) {
k_event_post(&data->irq_event, int_status);
}
}
static int i2c_xilinx_axi_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_xilinx_axi_config *config = dev->config;
LOG_INF("Configuring %s at 0x%08" PRIxPTR, dev->name, config->base);
i2c_xilinx_axi_reinit(config);
return 0;
}
static uint32_t i2c_xilinx_axi_wait_interrupt(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, uint32_t int_mask)
{
const k_spinlock_key_t key = k_spin_lock(&data->lock);
const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask;
uint32_t events;
LOG_DBG("Set IER to 0x%02x", int_enable);
sys_write32(int_enable, config->base + REG_IER);
k_event_clear(&data->irq_event, int_mask);
k_spin_unlock(&data->lock, key);
events = k_event_wait(&data->irq_event, int_mask, false, K_MSEC(100));
LOG_DBG("Got ISR events 0x%02x", events);
if (!events) {
LOG_ERR("Timeout waiting for ISR events 0x%02x, SR 0x%02x, ISR 0x%02x", int_mask,
sys_read32(config->base + REG_SR), sys_read32(config->base + REG_ISR));
}
return events;
}
static void i2c_xilinx_axi_clear_interrupt(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, uint32_t int_mask)
{
const k_spinlock_key_t key = k_spin_lock(&data->lock);
const uint32_t int_status = sys_read32(config->base + REG_ISR);
if (int_status & int_mask) {
sys_write32(int_status & int_mask, config->base + REG_ISR);
}
k_spin_unlock(&data->lock, key);
}
static int i2c_xilinx_axi_wait_rx_full(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, uint32_t read_bytes)
{
uint32_t events;
i2c_xilinx_axi_clear_interrupt(config, data, ISR_RX_FIFO_FULL);
if (!(sys_read32(config->base + REG_SR) & SR_RX_FIFO_EMPTY) &&
(sys_read32(config->base + REG_RX_FIFO_OCY) & RX_FIFO_OCY_MASK) + 1 >= read_bytes) {
LOG_DBG("RX already full on checking, SR 0x%02x RXOCY 0x%02x",
sys_read32(config->base + REG_SR),
sys_read32(config->base + REG_RX_FIFO_OCY));
return 0;
}
events = i2c_xilinx_axi_wait_interrupt(config, data, ISR_RX_FIFO_FULL | ISR_ARB_LOST);
if (!events) {
return -ETIMEDOUT;
}
if (events & ISR_ARB_LOST) {
LOG_ERR("Arbitration lost on RX");
return -ENXIO;
}
return 0;
}
static int i2c_xilinx_axi_read_nondyn(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, struct i2c_msg *msg,
uint16_t addr)
{
uint8_t *read_ptr = msg->buf;
uint32_t bytes_left = msg->len;
uint32_t cr = CR_EN | CR_MSMS;
if (!bytes_left) {
return -EINVAL;
}
if (bytes_left == 1) {
/* Set TXAK bit now, to NAK after the first byte is received */
cr |= CR_TXAK;
}
/**
* The Xilinx core's RX FIFO full logic seems rather broken in that the interrupt
* is triggered, and the I2C receive is throttled, only when the FIFO occupancy
* equals the PIRQ threshold, not when greater or equal. In the non-dynamic mode
* of operation, we need to stop the read prior to the last bytes being received
* from the target in order to set the TXAK bit and clear MSMS to terminate the
* receive properly.
* However, if we previously allowed multiple bytes into the RX FIFO, this requires
* reducing the PIRQ threshold to 0 (single byte) during the receive operation. This
* can cause the receive to unthrottle (since FIFO occupancy now exceeds PIRQ
* threshold) and depending on timing between the driver code and the core,
* this can cause the core to try to receive more data into the FIFO than desired
* and cause various unexpected results.
*
* To avoid this, we only receive one byte at a time in the non-dynamic mode.
* Dynamic mode doesn't have this issue as it provides the RX byte count to the
* controller specifically and the TXAK and MSMS bits are handled automatically.
*/
sys_write32(0, config->base + REG_RX_FIFO_PIRQ);
if (msg->flags & I2C_MSG_RESTART) {
cr |= CR_RSTA;
sys_write32(cr, config->base + REG_CR);
sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO);
} else {
sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO);
sys_write32(cr, config->base + REG_CR);
}
while (bytes_left) {
int ret = i2c_xilinx_axi_wait_rx_full(config, data, 1);
if (ret) {
return ret;
}
if (bytes_left == 2) {
/* Set TXAK so the last byte is NAKed */
cr |= CR_TXAK;
} else if (bytes_left == 1 && (msg->flags & I2C_MSG_STOP)) {
/* Before reading the last byte, clear MSMS to issue a stop if required */
cr &= ~CR_MSMS;
}
cr &= ~CR_RSTA;
sys_write32(cr, config->base + REG_CR);
*read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;
bytes_left--;
}
return 0;
}
static int i2c_xilinx_axi_read_dyn(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, struct i2c_msg *msg,
uint16_t addr)
{
uint8_t *read_ptr = msg->buf;
uint32_t bytes_left = msg->len;
uint32_t bytes_to_read = bytes_left;
uint32_t cr = CR_EN;
uint32_t len_word = bytes_left;
if (!bytes_left || bytes_left > MAX_DYNAMIC_READ_LEN) {
return -EINVAL;
}
if (msg->flags & I2C_MSG_RESTART) {
cr |= CR_MSMS | CR_RSTA;
}
sys_write32(cr, config->base + REG_CR);
if (bytes_to_read > FIFO_SIZE) {
bytes_to_read = FIFO_SIZE;
}
sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ);
sys_write32((addr << 1) | I2C_MSG_READ | TX_FIFO_START, config->base + REG_TX_FIFO);
if (msg->flags & I2C_MSG_STOP) {
len_word |= TX_FIFO_STOP;
}
sys_write32(len_word, config->base + REG_TX_FIFO);
while (bytes_left) {
int ret;
bytes_to_read = bytes_left;
if (bytes_to_read > FIFO_SIZE) {
bytes_to_read = FIFO_SIZE;
}
sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ);
ret = i2c_xilinx_axi_wait_rx_full(config, data, bytes_to_read);
if (ret) {
return ret;
}
while (bytes_to_read) {
*read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK;
bytes_to_read--;
bytes_left--;
}
}
return 0;
}
static int i2c_xilinx_axi_wait_tx_done(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data)
{
const uint32_t finish_bits = ISR_BUS_NOT_BUSY | ISR_TX_FIFO_EMPTY;
uint32_t events = i2c_xilinx_axi_wait_interrupt(
config, data, finish_bits | ISR_TX_ERR_TARGET_COMP | ISR_ARB_LOST);
if (!(events & finish_bits) || (events & ~finish_bits)) {
if (!events) {
return -ETIMEDOUT;
}
if (events & ISR_ARB_LOST) {
LOG_ERR("Arbitration lost on TX");
return -EAGAIN;
}
LOG_ERR("TX received NAK");
return -ENXIO;
}
return 0;
}
static int i2c_xilinx_axi_wait_not_busy(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data)
{
if (sys_read32(config->base + REG_SR) & SR_BB) {
uint32_t events = i2c_xilinx_axi_wait_interrupt(config, data, ISR_BUS_NOT_BUSY);
if (events != ISR_BUS_NOT_BUSY) {
LOG_ERR("Bus stuck busy");
i2c_xilinx_axi_reinit(config);
return -EBUSY;
}
}
return 0;
}
static int i2c_xilinx_axi_write(const struct i2c_xilinx_axi_config *config,
struct i2c_xilinx_axi_data *data, const struct i2c_msg *msg,
uint16_t addr)
{
const uint8_t *write_ptr = msg->buf;
uint32_t bytes_left = msg->len;
uint32_t cr = CR_EN | CR_TX;
uint32_t fifo_space = FIFO_SIZE - 1; /* account for address being written */
if (msg->flags & I2C_MSG_RESTART) {
cr |= CR_MSMS | CR_RSTA;
}
i2c_xilinx_axi_clear_interrupt(config, data, ISR_TX_ERR_TARGET_COMP | ISR_ARB_LOST);
sys_write32(cr, config->base + REG_CR);
sys_write32((addr << 1) | TX_FIFO_START, config->base + REG_TX_FIFO);
/* TX FIFO empty detection is somewhat fragile because the status register
* TX_FIFO_EMPTY bit can be set prior to the transaction actually being
* complete, so we have to rely on the TX empty interrupt.
* However, delays in writing data to the TX FIFO could cause it
* to run empty in the middle of the process, causing us to get a spurious
* completion detection from the interrupt. Therefore we disable interrupts
* while the TX FIFO is being filled up to try to avoid this.
*/
while (bytes_left) {
uint32_t bytes_to_send = bytes_left;
const k_spinlock_key_t key = k_spin_lock(&data->lock);
int ret;
if (bytes_to_send > fifo_space) {
bytes_to_send = fifo_space;
}
while (bytes_to_send) {
uint32_t write_word = *write_ptr++;
if (bytes_left == 1 && (msg->flags & I2C_MSG_STOP)) {
write_word |= TX_FIFO_STOP;
}
sys_write32(write_word, config->base + REG_TX_FIFO);
bytes_to_send--;
bytes_left--;
}
i2c_xilinx_axi_clear_interrupt(config, data, ISR_TX_FIFO_EMPTY | ISR_BUS_NOT_BUSY);
k_spin_unlock(&data->lock, key);
ret = i2c_xilinx_axi_wait_tx_done(config, data);
if (ret) {
return ret;
}
fifo_space = FIFO_SIZE;
}
return 0;
}
static int i2c_xilinx_axi_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
const struct i2c_xilinx_axi_config *config = dev->config;
struct i2c_xilinx_axi_data *data = dev->data;
int ret;
k_mutex_lock(&data->mutex, K_FOREVER);
ret = i2c_xilinx_axi_wait_not_busy(config, data);
if (ret) {
goto out_unlock;
}
if (!num_msgs) {
goto out_unlock;
}
/**
* Reinitializing before each transfer shouldn't technically be needed, but
* seems to improve general reliability. The Linux driver also does this.
*/
i2c_xilinx_axi_reinit(config);
do {
if (msgs->flags & I2C_MSG_ADDR_10_BITS) {
/* Optionally supported in core, but not implemented in driver yet */
ret = -EOPNOTSUPP;
goto out_check_target;
}
if (msgs->flags & I2C_MSG_READ) {
if (config->dyn_read_working && msgs->len <= MAX_DYNAMIC_READ_LEN) {
ret = i2c_xilinx_axi_read_dyn(config, data, msgs, addr);
} else {
ret = i2c_xilinx_axi_read_nondyn(config, data, msgs, addr);
}
} else {
ret = i2c_xilinx_axi_write(config, data, msgs, addr);
}
if (!ret && (msgs->flags & I2C_MSG_STOP)) {
ret = i2c_xilinx_axi_wait_not_busy(config, data);
}
if (ret) {
goto out_check_target;
}
msgs++;
num_msgs--;
} while (num_msgs);
out_check_target:
#if defined(CONFIG_I2C_TARGET)
/* If a target is registered, then ensure the controller gets put back
* into a suitable state to handle target transfers.
*/
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (data->target_cfg) {
i2c_xilinx_axi_target_setup(config, data->target_cfg);
}
k_spin_unlock(&data->lock, key);
#endif
out_unlock:
k_mutex_unlock(&data->mutex);
return ret;
}
static int i2c_xilinx_axi_init(const struct device *dev)
{
const struct i2c_xilinx_axi_config *config = dev->config;
struct i2c_xilinx_axi_data *data = dev->data;
int error;
k_event_init(&data->irq_event);
k_mutex_init(&data->mutex);
error = i2c_xilinx_axi_configure(dev, I2C_MODE_CONTROLLER);
if (error) {
return error;
}
config->irq_config_func(dev);
LOG_INF("initialized");
return 0;
}
static const struct i2c_driver_api i2c_xilinx_axi_driver_api = {
.configure = i2c_xilinx_axi_configure,
.transfer = i2c_xilinx_axi_transfer,
#if defined(CONFIG_I2C_TARGET)
.target_register = i2c_xilinx_axi_target_register,
.target_unregister = i2c_xilinx_axi_target_unregister,
#endif
};
#define I2C_XILINX_AXI_INIT(n, compat) \
static void i2c_xilinx_axi_config_func_##compat##_##n(const struct device *dev); \
\
static const struct i2c_xilinx_axi_config i2c_xilinx_axi_config_##compat##_##n = { \
.base = DT_INST_REG_ADDR(n), \
.irq_config_func = i2c_xilinx_axi_config_func_##compat##_##n, \
.dyn_read_working = DT_INST_NODE_HAS_COMPAT(n, xlnx_xps_iic_2_1)}; \
\
static struct i2c_xilinx_axi_data i2c_xilinx_axi_data_##compat##_##n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, i2c_xilinx_axi_init, NULL, \
&i2c_xilinx_axi_data_##compat##_##n, \
&i2c_xilinx_axi_config_##compat##_##n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_xilinx_axi_driver_api); \
\
static void i2c_xilinx_axi_config_func_##compat##_##n(const struct device *dev) \
{ \
ARG_UNUSED(dev); \
\
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_xilinx_axi_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
#define DT_DRV_COMPAT xlnx_xps_iic_2_1
DT_INST_FOREACH_STATUS_OKAY_VARGS(I2C_XILINX_AXI_INIT, DT_DRV_COMPAT)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT xlnx_xps_iic_2_00_a
DT_INST_FOREACH_STATUS_OKAY_VARGS(I2C_XILINX_AXI_INIT, DT_DRV_COMPAT)
``` | /content/code_sandbox/drivers/i2c/i2c_xilinx_axi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,003 |
```unknown
config I2C_SC18IM704
bool "NXP SC18IM704 I2C controller driver"
default y
depends on DT_HAS_NXP_SC18IM704_I2C_ENABLED
select UART_USE_RUNTIME_CONFIGURE
help
Enables NXP SC18IM704 I2C controller driver
if I2C_SC18IM704
config I2C_SC18IM704_INIT_PRIORITY
int "SC18IM704 I2C init priority"
default 51
help
SC18IM704 I2C controller initialization priority.
Note: Has to be greater than the UART bus initialization priority.
config I2C_SC18IM704_VERIFY
bool "Verify SC18IM704 I2C transfers"
default y
help
Verify the I2C state register after I2C transfers to detect errors.
endif
``` | /content/code_sandbox/drivers/i2c/Kconfig.sc18im704 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 177 |
```c
/*
*
*/
#define DT_DRV_COMPAT adi_max32_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/irq.h>
#if defined(CONFIG_I2C_MAX32_DMA)
#include <zephyr/drivers/dma.h>
#endif /* CONFIG_I2C_MAX32_DMA */
#include <wrap_max32_i2c.h>
#define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
#define ADI_MAX32_I2C_INT_FL1_MASK 0x7
#define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5)
#define I2C_RECOVER_MAX_RETRIES 3
#ifdef CONFIG_I2C_MAX32_DMA
struct max32_i2c_dma_config {
const struct device *dev;
const uint32_t channel;
const uint32_t slot;
};
#endif /* CONFIG_I2C_MAX32_DMA */
/* Driver config */
struct max32_i2c_config {
mxc_i2c_regs_t *regs;
const struct pinctrl_dev_config *pctrl;
const struct device *clock;
struct max32_perclk perclk;
uint32_t bitrate;
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
uint8_t irqn;
void (*irq_config_func)(const struct device *dev);
#endif
#ifdef CONFIG_I2C_MAX32_DMA
struct max32_i2c_dma_config tx_dma;
struct max32_i2c_dma_config rx_dma;
#endif /* CONFIG_I2C_MAX32_DMA */
};
struct max32_i2c_data {
mxc_i2c_req_t req;
const struct device *dev;
struct k_sem lock;
uint8_t target_mode;
uint8_t flags;
#ifdef CONFIG_I2C_TARGET
struct i2c_target_config *target_cfg;
bool first_write;
#endif /* CONFIG_I2C_TARGET */
uint32_t readb;
uint32_t written;
#if defined(CONFIG_I2C_MAX32_INTERRUPT) || defined(CONFIG_I2C_MAX32_DMA)
struct k_sem xfer;
int err;
#endif
};
static int api_configure(const struct device *dev, uint32_t dev_cfg)
{
int ret = 0;
const struct max32_i2c_config *const cfg = dev->config;
mxc_i2c_regs_t *i2c = cfg->regs;
switch (I2C_SPEED_GET(dev_cfg)) {
case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE);
break;
case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
break;
#if defined(MXC_I2C_FASTPLUS_SPEED)
case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
break;
#endif
#if defined(MXC_I2C_HIGH_SPEED)
case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED);
break;
#endif
default:
/* Speed not supported */
return -ENOTSUP;
}
return ret;
}
#ifdef CONFIG_I2C_TARGET
static int api_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
const struct max32_i2c_config *config = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = config->regs;
int ret;
data->target_cfg = cfg;
ret = MXC_I2C_Init(i2c, 0, cfg->address);
if (ret == E_NO_ERROR) {
data->target_mode = 1;
irq_enable(config->irqn);
MXC_I2C_SlaveTransactionAsync(i2c, NULL);
}
return ret == E_NO_ERROR ? 0 : E_FAIL;
}
static int api_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
const struct max32_i2c_config *config = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = config->regs;
data->target_cfg = NULL;
data->target_mode = 0;
#ifndef CONFIG_I2C_MAX32_INTERRUPT
irq_disable(config->irqn);
#endif
return MXC_I2C_Init(i2c, 1, 0);
}
static int i2c_max32_target_callback(const struct device *dev, mxc_i2c_regs_t *i2c,
mxc_i2c_slave_event_t event)
{
struct max32_i2c_data *data = dev->data;
const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
static uint8_t rxval, txval, rxcnt;
switch (event) {
case MXC_I2C_EVT_MASTER_WR:
if (data->first_write && target_cb->write_requested) {
target_cb->write_requested(data->target_cfg);
data->first_write = false;
}
break;
case MXC_I2C_EVT_MASTER_RD:
break;
case MXC_I2C_EVT_RX_THRESH:
case MXC_I2C_EVT_OVERFLOW:
rxcnt = MXC_I2C_GetRXFIFOAvailable(i2c);
if (target_cb->write_received) {
while (rxcnt--) {
MXC_I2C_ReadRXFIFO(i2c, &rxval, 1);
target_cb->write_received(data->target_cfg, rxval);
}
} else {
MXC_I2C_ClearRXFIFO(i2c);
}
break;
case MXC_I2C_EVT_TX_THRESH:
case MXC_I2C_EVT_UNDERFLOW:
if (target_cb->read_requested) {
target_cb->read_requested(data->target_cfg, &txval);
MXC_I2C_WriteTXFIFO(i2c, &txval, 1);
}
if (target_cb->read_processed) {
target_cb->read_processed(data->target_cfg, &txval);
}
break;
case MXC_I2C_EVT_TRANS_COMP:
if (target_cb->stop) {
target_cb->stop(data->target_cfg);
}
data->first_write = true;
break;
}
return 0;
}
#endif /* CONFIG_I2C_TARGET */
static int api_recover_bus(const struct device *dev)
{
int ret;
const struct max32_i2c_config *const cfg = dev->config;
mxc_i2c_regs_t *i2c = cfg->regs;
ret = MXC_I2C_Recover(i2c, I2C_RECOVER_MAX_RETRIES);
return ret;
}
#ifndef CONFIG_I2C_MAX32_INTERRUPT
static int i2c_max32_transfer_sync(mxc_i2c_regs_t *i2c, struct max32_i2c_data *data)
{
uint32_t int_fl0, int_fl1;
uint32_t readb = 0;
mxc_i2c_req_t *req = &data->req;
/* Wait for acknowledge */
if (data->flags & (I2C_MSG_RESTART | I2C_MSG_READ)) {
do {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
} while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) &&
!(int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR));
}
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
return -EIO;
}
while (req->tx_len > data->written) {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
data->written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[data->written],
req->tx_len - data->written);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_TX_THD, 0);
}
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
return -EIO;
}
}
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
while (req->rx_len > readb) {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
if (int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE)) {
readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_RX_THD, 0);
}
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
return -EIO;
}
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) && (req->rx_len > readb) &&
MXC_I2C_GetRXFIFOAvailable(i2c) == 0) {
Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
Wrap_MXC_I2C_Restart(i2c);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
i2c->fifo = (req->addr << 1) | 0x1;
}
}
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
return -EIO;
}
if (data->flags & I2C_MSG_STOP) {
MXC_I2C_Stop(i2c);
do {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
} while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP));
}
if (req->rx_len) {
do {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
} while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE));
} else {
while (Wrap_MXC_I2C_GetTxFIFOLevel(i2c) > 0) {
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
}
}
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
return 0;
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
#if defined(CONFIG_I2C_MAX32_DMA)
static void i2c_max32_dma_callback(const struct device *dev, void *arg, uint32_t channel,
int status)
{
struct max32_i2c_data *data = arg;
const struct device *i2c_dev = data->dev;
const struct max32_i2c_config *const cfg = i2c_dev->config;
if (status < 0) {
data->err = -EIO;
} else {
if (data->req.restart) {
Wrap_MXC_I2C_Restart(cfg->regs);
} else {
Wrap_MXC_I2C_Stop(cfg->regs);
}
}
}
static int i2c_max32_tx_dma_load(const struct device *dev, struct i2c_msg *msg)
{
int ret;
const struct max32_i2c_config *config = dev->config;
struct max32_i2c_data *data = dev->data;
struct dma_config dma_cfg = {0};
struct dma_block_config dma_blk = {0};
dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
dma_cfg.dma_callback = i2c_max32_dma_callback;
dma_cfg.user_data = (void *)data;
dma_cfg.dma_slot = config->tx_dma.slot;
dma_cfg.block_count = 1;
dma_cfg.source_data_size = 1U;
dma_cfg.source_burst_length = 1U;
dma_cfg.dest_data_size = 1U;
dma_cfg.head_block = &dma_blk;
dma_blk.block_size = msg->len;
dma_blk.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
dma_blk.source_address = (uint32_t)msg->buf;
ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg);
if (ret < 0) {
return ret;
}
return dma_start(config->tx_dma.dev, config->tx_dma.channel);
}
static int i2c_max32_rx_dma_load(const struct device *dev, struct i2c_msg *msg)
{
int ret;
const struct max32_i2c_config *config = dev->config;
struct max32_i2c_data *data = dev->data;
struct dma_config dma_cfg = {0};
struct dma_block_config dma_blk = {0};
dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
dma_cfg.dma_callback = i2c_max32_dma_callback;
dma_cfg.user_data = (void *)data;
dma_cfg.dma_slot = config->rx_dma.slot;
dma_cfg.block_count = 1;
dma_cfg.source_data_size = 1U;
dma_cfg.source_burst_length = 1U;
dma_cfg.dest_data_size = 1U;
dma_cfg.head_block = &dma_blk;
dma_blk.block_size = msg->len;
dma_blk.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
dma_blk.dest_address = (uint32_t)msg->buf;
ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg);
if (ret < 0) {
return ret;
}
return dma_start(config->rx_dma.dev, config->rx_dma.channel);
}
static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
{
int ret = 0;
const struct max32_i2c_config *const cfg = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = cfg->regs;
uint8_t target_rw;
unsigned int i = 0;
k_sem_take(&data->lock, K_FOREVER);
MXC_I2C_SetRXThreshold(i2c, 1);
MXC_I2C_SetTXThreshold(i2c, 2);
MXC_I2C_ClearTXFIFO(i2c);
MXC_I2C_ClearRXFIFO(i2c);
for (i = 0; i < num_msgs; i++) {
data->req.restart = !(msgs[i].flags & I2C_MSG_STOP);
if (msgs[i].flags & I2C_MSG_READ) {
target_rw = (target_address << 1) | 0x1;
MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
Wrap_MXC_I2C_SetRxCount(i2c, msgs[i].len);
ret = i2c_max32_rx_dma_load(dev, &msgs[i]);
if (ret < 0) {
break;
}
MXC_I2C_EnableInt(
i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
} else {
target_rw = (target_address << 1) & ~0x1;
MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
ret = i2c_max32_tx_dma_load(dev, &msgs[i]);
if (ret < 0) {
break;
}
MXC_I2C_EnableInt(
i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
}
data->err = 0;
Wrap_MXC_I2C_Start(i2c);
ret = k_sem_take(&data->xfer, K_FOREVER);
Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN);
if (data->err) {
ret = data->err;
}
if (ret) {
MXC_I2C_Stop(i2c);
dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
}
}
k_sem_give(&data->lock);
return ret;
}
#endif /* CONFIG_I2C_MAX32_DMA */
#ifdef CONFIG_I2C_MAX32_INTERRUPT
static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
{
int ret = 0;
const struct max32_i2c_config *const cfg = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = cfg->regs;
mxc_i2c_req_t *req = &data->req;
uint8_t target_rw;
unsigned int i = 0;
req->i2c = i2c;
req->addr = target_address;
k_sem_take(&data->lock, K_FOREVER);
MXC_I2C_ClearRXFIFO(i2c);
MXC_I2C_ClearTXFIFO(i2c);
MXC_I2C_SetRXThreshold(i2c, 1);
/* First message should always begin with a START condition */
msgs[0].flags |= I2C_MSG_RESTART;
for (i = 0; i < num_msgs; i++) {
if (msgs[i].flags & I2C_MSG_READ) {
req->rx_buf = (unsigned char *)msgs[i].buf;
req->rx_len = msgs[i].len;
req->tx_buf = NULL;
req->tx_len = 0;
target_rw = (target_address << 1) | 0x1;
} else {
req->tx_buf = (unsigned char *)msgs[i].buf;
req->tx_len = msgs[i].len;
req->rx_buf = NULL;
req->rx_len = 0;
target_rw = (target_address << 1) & ~0x1;
}
/*
* If previous message ends with a STOP condition, this message
* should begin with a START
*/
if (i > 0) {
if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
msgs[i].flags |= I2C_MSG_RESTART;
}
}
data->flags = msgs[i].flags;
data->readb = 0;
data->written = 0;
data->err = 0;
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
if ((data->flags & I2C_MSG_RESTART)) {
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
MXC_I2C_Start(i2c);
Wrap_MXC_I2C_WaitForRestart(i2c);
MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
} else {
if (req->tx_len) {
data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1);
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
} else {
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
}
}
ret = k_sem_take(&data->xfer, K_FOREVER);
if (data->err) {
MXC_I2C_Stop(i2c);
ret = data->err;
} else {
if (data->flags & I2C_MSG_STOP) {
/* Wait for busy flag to be cleared */
while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) {
}
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
ADI_MAX32_I2C_INT_FL1_MASK);
}
}
if (ret) {
break;
}
}
k_sem_give(&data->lock);
return ret;
}
#else
static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
{
int ret = 0;
const struct max32_i2c_config *const cfg = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = cfg->regs;
mxc_i2c_req_t *req = &data->req;
uint8_t target_rw;
unsigned int i = 0;
req->i2c = i2c;
req->addr = target_address;
k_sem_take(&data->lock, K_FOREVER);
MXC_I2C_ClearRXFIFO(i2c);
/* First message should always begin with a START condition */
msgs[0].flags |= I2C_MSG_RESTART;
for (i = 0; i < num_msgs; i++) {
if (msgs[i].flags & I2C_MSG_READ) {
req->rx_buf = (unsigned char *)msgs[i].buf;
req->rx_len = msgs[i].len;
req->tx_buf = NULL;
req->tx_len = 0;
target_rw = (target_address << 1) | 0x1;
} else {
req->tx_buf = (unsigned char *)msgs[i].buf;
req->tx_len = msgs[i].len;
req->rx_buf = NULL;
req->rx_len = 0;
target_rw = (target_address << 1) & ~0x1;
}
/*
* If previous message ends with a STOP condition, this message
* should begin with a START
*/
if (i > 0) {
if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
msgs[i].flags |= I2C_MSG_RESTART;
}
}
data->flags = msgs[i].flags;
data->readb = 0;
data->written = 0;
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
if (data->flags & I2C_MSG_RESTART) {
MXC_I2C_Start(i2c);
Wrap_MXC_I2C_WaitForRestart(i2c);
MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
}
ret = i2c_max32_transfer_sync(i2c, data);
if (ret) {
MXC_I2C_Stop(i2c);
break;
}
}
k_sem_give(&data->lock);
return ret;
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
static int api_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t target_address)
{
#if CONFIG_I2C_MAX32_DMA
const struct max32_i2c_config *cfg = dev->config;
if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
return i2c_max32_transfer_dma(dev, msgs, num_msgs, target_address);
}
#endif
return i2c_max32_transfer(dev, msgs, num_msgs, target_address);
}
#ifdef CONFIG_I2C_TARGET
static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
{
uint32_t ctrl;
uint32_t int_fl0;
uint32_t int_fl1;
uint32_t int_en0;
uint32_t int_en1;
ctrl = i2c->ctrl;
Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
/* Error occurred, notify callback function and end transaction */
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
MXC_I2C_ClearTXFIFO(i2c);
MXC_I2C_ClearRXFIFO(i2c);
}
/* Check whether data is available if we received an interrupt occurred while receiving */
if (int_en0 & ADI_MAX32_I2C_INT_EN0_RX_THD || int_en1 & ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW) {
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_RX_THD) {
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_RX_THRESH);
}
if (int_fl1 & ADI_MAX32_I2C_INT_FL1_RX_OVERFLOW) {
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_OVERFLOW);
}
}
/* Check whether TX FIFO needs to be refilled if interrupt ocurred while transmitting */
if (int_en0 & (ADI_MAX32_I2C_INT_EN0_TX_THD | ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT) ||
int_en1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TX_THRESH);
}
if (int_fl1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_UNDERFLOW);
}
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_LOCK_OUT) {
int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
int_en1 = 0;
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
}
}
/* Check if transaction completed or restart occurred */
if (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) {
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP) {
/* Stop/NACK condition occurred, transaction complete */
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
} else if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
/* Restart detected, re-arm address match interrupt */
int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
}
int_en1 = 0;
}
/* Check for address match interrupt */
if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) {
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) {
/* Address match occurred, prepare for transaction */
if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
/* Read request received from the master */
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD);
int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD |
ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT |
ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
int_en1 = ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW;
} else {
/* Write request received from the master */
i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_WR);
int_en0 = ADI_MAX32_I2C_INT_EN0_RX_THD |
ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
int_en1 = ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW;
}
}
}
Wrap_MXC_I2C_SetIntEn(i2c, int_en0, int_en1);
}
#endif /* CONFIG_I2C_TARGET */
#ifdef CONFIG_I2C_MAX32_INTERRUPT
static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c)
{
struct max32_i2c_data *data = dev->data;
mxc_i2c_req_t *req = &data->req;
uint32_t written, readb;
uint32_t txfifolevel;
uint32_t int_fl0, int_fl1;
uint32_t int_en0, int_en1;
written = data->written;
readb = data->readb;
Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c);
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
data->err = -EIO;
Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
k_sem_give(&data->xfer);
return;
}
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) {
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
if (written < req->tx_len) {
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
} else if (readb < req->rx_len) {
MXC_I2C_EnableInt(
i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
}
}
if (req->tx_len &&
(int_fl0 & (ADI_MAX32_I2C_INT_FL0_TX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
if (written < req->tx_len) {
written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written],
req->tx_len - written);
} else {
if (!(int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
/* We are done, stop sending more data */
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
if (data->flags & I2C_MSG_STOP) {
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
/* Done flag is not set if stop/restart is not set */
Wrap_MXC_I2C_Stop(i2c);
} else {
k_sem_give(&data->xfer);
}
}
if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
k_sem_give(&data->xfer);
}
}
} else if ((int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
if (readb == req->rx_len) {
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
if (data->flags & I2C_MSG_STOP) {
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
Wrap_MXC_I2C_Stop(i2c);
k_sem_give(&data->xfer);
} else {
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
k_sem_give(&data->xfer);
}
}
} else if ((int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) &&
(int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
MXC_I2C_DisableInt(
i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE),
0);
Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
i2c->fifo = (req->addr << 1) | 0x1;
Wrap_MXC_I2C_Restart(i2c);
}
}
data->written = written;
data->readb = readb;
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
#ifdef CONFIG_I2C_MAX32_DMA
static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c)
{
struct max32_i2c_data *data = dev->data;
uint32_t int_fl0, int_fl1;
uint32_t int_en0, int_en1;
Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
data->err = -EIO;
Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
k_sem_give(&data->xfer);
} else {
if (!data->err && (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
k_sem_give(&data->xfer);
}
}
}
#endif /* CONFIG_I2C_MAX32_DMA */
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
static void i2c_max32_isr(const struct device *dev)
{
const struct max32_i2c_config *cfg = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = cfg->regs;
#ifdef CONFIG_I2C_MAX32_INTERRUPT
if (data->target_mode == 0) {
#ifdef CONFIG_I2C_MAX32_DMA
if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
i2c_max32_isr_controller_dma(dev, i2c);
return;
}
#endif
i2c_max32_isr_controller(dev, i2c);
return;
}
#endif /* CONFIG_I2C_MAX32_INTERRUPT */
#ifdef CONFIG_I2C_TARGET
if (data->target_mode == 1) {
i2c_max32_isr_target(dev, i2c);
}
#endif
}
#endif /* CONFIG_I2C_TARGET || CONFIG_I2C_MAX32_INTERRUPT */
static const struct i2c_driver_api api = {
.configure = api_configure,
.transfer = api_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = api_target_register,
.target_unregister = api_target_unregister,
#endif
.recover_bus = api_recover_bus,
};
static int i2c_max32_init(const struct device *dev)
{
const struct max32_i2c_config *const cfg = dev->config;
struct max32_i2c_data *data = dev->data;
mxc_i2c_regs_t *i2c = cfg->regs;
int ret = 0;
if (!device_is_ready(cfg->clock)) {
return -ENODEV;
}
MXC_I2C_Shutdown(i2c); /* Clear everything out */
ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
if (ret) {
return ret;
}
ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
if (ret) {
return ret;
}
ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */
if (ret) {
return ret;
}
MXC_I2C_SetFrequency(i2c, cfg->bitrate);
k_sem_init(&data->lock, 1, 1);
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
cfg->irq_config_func(dev);
#endif
#ifdef CONFIG_I2C_MAX32_INTERRUPT
irq_enable(cfg->irqn);
k_sem_init(&data->xfer, 0, 1);
#endif
#if defined(CONFIG_I2C_TARGET)
data->first_write = true;
data->target_mode = 0;
#endif
data->dev = dev;
return ret;
}
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
#define I2C_MAX32_CONFIG_IRQ_FUNC(n) \
.irq_config_func = i2c_max32_irq_config_func_##n, .irqn = DT_INST_IRQN(n),
#define I2C_MAX32_IRQ_CONFIG_FUNC(n) \
static void i2c_max32_irq_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_max32_isr, \
DEVICE_DT_INST_GET(n), 0); \
}
#else
#define I2C_MAX32_CONFIG_IRQ_FUNC(n)
#define I2C_MAX32_IRQ_CONFIG_FUNC(n)
#endif
#if CONFIG_I2C_MAX32_DMA
#define MAX32_DT_INST_DMA_CTLR(n, name) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
(DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, name))), (NULL))
#define MAX32_DT_INST_DMA_CELL(n, name, cell) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
(0xff))
#define MAX32_I2C_TX_DMA_INIT(n) \
.tx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, tx), \
.tx_dma.channel = MAX32_DT_INST_DMA_CELL(n, tx, channel), \
.tx_dma.slot = MAX32_DT_INST_DMA_CELL(n, tx, slot),
#define MAX32_I2C_RX_DMA_INIT(n) \
.rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx), \
.rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel), \
.rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
#else
#define MAX32_I2C_TX_DMA_INIT(n)
#define MAX32_I2C_RX_DMA_INIT(n)
#endif
#define DEFINE_I2C_MAX32(_num) \
PINCTRL_DT_INST_DEFINE(_num); \
I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
.regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
.bitrate = DT_INST_PROP(_num, clock_frequency), \
I2C_MAX32_CONFIG_IRQ_FUNC(_num) MAX32_I2C_TX_DMA_INIT(_num) \
MAX32_I2C_RX_DMA_INIT(_num)}; \
static struct max32_i2c_data max32_i2c_data_##_num; \
I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
&max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
CONFIG_I2C_INIT_PRIORITY, &api);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_MAX32)
``` | /content/code_sandbox/drivers/i2c/i2c_max32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,626 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(mcux_flexcomm);
#include "i2c-priv.h"
#define I2C_TRANSFER_TIMEOUT_MSEC \
COND_CODE_0(CONFIG_I2C_NXP_TRANSFER_TIMEOUT, (K_FOREVER), \
(K_MSEC(CONFIG_I2C_NXP_TRANSFER_TIMEOUT)))
#define MCUX_FLEXCOMM_MAX_TARGETS 4
struct mcux_flexcomm_config {
I2C_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
void (*irq_config_func)(const struct device *dev);
uint32_t bitrate;
const struct pinctrl_dev_config *pincfg;
const struct reset_dt_spec reset;
};
#ifdef CONFIG_I2C_TARGET
struct mcux_flexcomm_target_data {
struct i2c_target_config *target_cfg;
bool target_attached;
bool first_read;
bool first_write;
bool is_write;
};
#endif
struct mcux_flexcomm_data {
i2c_master_handle_t handle;
struct k_sem device_sync_sem;
struct k_sem lock;
status_t callback_status;
#ifdef CONFIG_I2C_TARGET
uint8_t nr_targets_attached;
i2c_slave_config_t i2c_cfg;
i2c_slave_handle_t target_handle;
struct mcux_flexcomm_target_data target_data[MCUX_FLEXCOMM_MAX_TARGETS];
#endif
};
static int mcux_flexcomm_configure(const struct device *dev,
uint32_t dev_config_raw)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
I2C_Type *base = config->base;
uint32_t clock_freq;
uint32_t baudrate;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
/* Get the clock frequency */
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
k_sem_take(&data->lock, K_FOREVER);
I2C_MasterSetBaudRate(base, baudrate, clock_freq);
k_sem_give(&data->lock);
return 0;
}
static void mcux_flexcomm_master_transfer_callback(I2C_Type *base,
i2c_master_handle_t *handle,
status_t status,
void *userData)
{
struct mcux_flexcomm_data *data = userData;
ARG_UNUSED(handle);
ARG_UNUSED(base);
data->callback_status = status;
k_sem_give(&data->device_sync_sem);
}
static uint32_t mcux_flexcomm_convert_flags(int msg_flags)
{
uint32_t flags = 0U;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kI2C_TransferNoStopFlag;
}
if (msg_flags & I2C_MSG_RESTART) {
flags |= kI2C_TransferRepeatedStartFlag;
}
return flags;
}
static int mcux_flexcomm_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
I2C_Type *base = config->base;
i2c_master_transfer_t transfer;
status_t status;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
/* Iterate over all the messages */
for (int i = 0; i < num_msgs; i++) {
if (I2C_MSG_ADDR_10_BITS & msgs->flags) {
ret = -ENOTSUP;
break;
}
/* Initialize the transfer descriptor */
transfer.flags = mcux_flexcomm_convert_flags(msgs->flags);
/* Prevent the controller to send a start condition between
* messages, except if explicitly requested.
*/
if (i != 0 && !(msgs->flags & I2C_MSG_RESTART)) {
transfer.flags |= kI2C_TransferNoStartFlag;
}
transfer.slaveAddress = addr;
transfer.direction = (msgs->flags & I2C_MSG_READ)
? kI2C_Read : kI2C_Write;
transfer.subaddress = 0;
transfer.subaddressSize = 0;
transfer.data = msgs->buf;
transfer.dataSize = msgs->len;
/* Start the transfer */
status = I2C_MasterTransferNonBlocking(base,
&data->handle, &transfer);
/* Return an error if the transfer didn't start successfully
* e.g., if the bus was busy
*/
if (status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
break;
}
/* Wait for the transfer to complete */
k_sem_take(&data->device_sync_sem, I2C_TRANSFER_TIMEOUT_MSEC);
/* Return an error if the transfer didn't complete
* successfully. e.g., nak, timeout, lost arbitration
*/
if (data->callback_status != kStatus_Success) {
I2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
break;
}
/* Move to the next message */
msgs++;
}
k_sem_give(&data->lock);
return ret;
}
#if defined(CONFIG_I2C_TARGET)
static struct mcux_flexcomm_target_data *mcux_flexcomm_find_free_target(
struct mcux_flexcomm_data *data)
{
struct mcux_flexcomm_target_data *target;
int i;
for (i = 0; i < ARRAY_SIZE(data->target_data); i++) {
target = &data->target_data[i];
if (!target->target_attached) {
return target;
}
}
return NULL;
}
static struct mcux_flexcomm_target_data *mcux_flexcomm_find_target_by_address(
struct mcux_flexcomm_data *data, uint16_t address)
{
struct mcux_flexcomm_target_data *target;
int i;
for (i = 0; i < ARRAY_SIZE(data->target_data); i++) {
target = &data->target_data[i];
if (target->target_attached && target->target_cfg->address == address) {
return target;
}
}
return NULL;
}
static int mcux_flexcomm_setup_i2c_config_address(struct mcux_flexcomm_data *data,
struct mcux_flexcomm_target_data *target, bool disabled)
{
i2c_slave_address_t *addr;
int idx = -1;
int i;
for (i = 0; i < ARRAY_SIZE(data->target_data); i++) {
if (data->target_data[i].target_attached && &data->target_data[i] == target) {
idx = i;
break;
}
}
if (idx < 0) {
return -ENODEV;
}
/* This could be just shifting a pointer in the i2c_cfg struct */
/* However would be less readable and error prone if the struct changes */
switch (idx) {
case 0:
addr = &data->i2c_cfg.address0;
break;
case 1:
addr = &data->i2c_cfg.address1;
break;
case 2:
addr = &data->i2c_cfg.address2;
break;
case 3:
addr = &data->i2c_cfg.address3;
break;
default:
return -1;
}
addr->address = target->target_cfg->address;
addr->addressDisable = disabled;
return 0;
}
static void i2c_target_transfer_callback(I2C_Type *base,
volatile i2c_slave_transfer_t *transfer, void *userData)
{
/* Convert 8-bit received address to 7-bit address */
uint8_t address = transfer->receivedAddress >> 1;
struct mcux_flexcomm_data *data = userData;
struct mcux_flexcomm_target_data *target;
const struct i2c_target_callbacks *target_cb;
static uint8_t rxVal, txVal;
ARG_UNUSED(base);
target = mcux_flexcomm_find_target_by_address(data, address);
if (!target) {
LOG_ERR("No target found for address: 0x%x", address);
return;
}
target_cb = target->target_cfg->callbacks;
switch (transfer->event) {
case kI2C_SlaveTransmitEvent:
/* request to provide data to transmit */
if (target->first_read && target_cb->read_requested) {
target->first_read = false;
target_cb->read_requested(target->target_cfg, &txVal);
} else if (target_cb->read_processed) {
target_cb->read_processed(target->target_cfg, &txVal);
}
transfer->txData = &txVal;
transfer->txSize = 1;
break;
case kI2C_SlaveReceiveEvent:
/* request to provide a buffer in which to place received data */
if (target->first_write && target_cb->write_requested) {
target_cb->write_requested(target->target_cfg);
target->first_write = false;
}
transfer->rxData = &rxVal;
transfer->rxSize = 1;
target->is_write = true;
break;
case kI2C_SlaveCompletionEvent:
/* called after every transferred byte */
if (target->is_write && target_cb->write_received) {
target_cb->write_received(target->target_cfg, rxVal);
target->is_write = false;
}
break;
case kI2C_SlaveDeselectedEvent:
if (target_cb->stop) {
target_cb->stop(target->target_cfg);
}
target->first_read = true;
target->first_write = true;
break;
default:
LOG_INF("Unhandled event: %d", transfer->event);
break;
}
}
static int mcux_flexcomm_setup_slave_config(const struct device *dev)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
I2C_Type *base = config->base;
uint32_t clock_freq;
/* Get the clock frequency */
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
I2C_SlaveInit(base, &data->i2c_cfg, clock_freq);
I2C_SlaveTransferCreateHandle(base, &data->target_handle,
i2c_target_transfer_callback, data);
I2C_SlaveTransferNonBlocking(base, &data->target_handle,
kI2C_SlaveCompletionEvent | kI2C_SlaveTransmitEvent |
kI2C_SlaveReceiveEvent | kI2C_SlaveDeselectedEvent);
return 0;
}
int mcux_flexcomm_target_register(const struct device *dev,
struct i2c_target_config *target_config)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
struct mcux_flexcomm_target_data *target;
I2C_Type *base = config->base;
I2C_MasterDeinit(base);
if (!target_config) {
return -EINVAL;
}
target = mcux_flexcomm_find_free_target(data);
if (!target) {
return -EBUSY;
}
target->target_cfg = target_config;
target->target_attached = true;
target->first_read = true;
target->first_write = true;
if (data->nr_targets_attached == 0) {
I2C_SlaveGetDefaultConfig(&data->i2c_cfg);
}
if (mcux_flexcomm_setup_i2c_config_address(data, target, false) < 0) {
return -EINVAL;
}
if (mcux_flexcomm_setup_slave_config(dev) < 0) {
return -EINVAL;
}
data->nr_targets_attached++;
return 0;
}
int mcux_flexcomm_target_unregister(const struct device *dev,
struct i2c_target_config *target_config)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
struct mcux_flexcomm_target_data *target;
I2C_Type *base = config->base;
target = mcux_flexcomm_find_target_by_address(data, target_config->address);
if (!target || !target->target_attached) {
return -EINVAL;
}
if (mcux_flexcomm_setup_i2c_config_address(data, target, true) < 0) {
return -EINVAL;
}
target->target_cfg = NULL;
target->target_attached = false;
data->nr_targets_attached--;
if (data->nr_targets_attached > 0) {
/* still slaves attached, reconfigure the I2C peripheral after address removal */
if (mcux_flexcomm_setup_slave_config(dev) < 0) {
return -EINVAL;
}
} else {
I2C_SlaveDeinit(base);
}
return 0;
}
#endif
static void mcux_flexcomm_isr(const struct device *dev)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
I2C_Type *base = config->base;
#if defined(CONFIG_I2C_TARGET)
if (data->nr_targets_attached > 0) {
I2C_SlaveTransferHandleIRQ(base, &data->target_handle);
return;
}
#endif
I2C_MasterTransferHandleIRQ(base, &data->handle);
}
static int mcux_flexcomm_init(const struct device *dev)
{
const struct mcux_flexcomm_config *config = dev->config;
struct mcux_flexcomm_data *data = dev->data;
I2C_Type *base = config->base;
uint32_t clock_freq, bitrate_cfg;
i2c_master_config_t master_config;
int error;
if (!device_is_ready(config->reset.dev)) {
LOG_ERR("Reset device not ready");
return -ENODEV;
}
error = reset_line_toggle(config->reset.dev, config->reset.id);
if (error) {
return error;
}
error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (error) {
return error;
}
k_sem_init(&data->lock, 1, 1);
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Get the clock frequency */
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
I2C_MasterGetDefaultConfig(&master_config);
I2C_MasterInit(base, &master_config, clock_freq);
I2C_MasterTransferCreateHandle(base, &data->handle,
mcux_flexcomm_master_transfer_callback,
data);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = mcux_flexcomm_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
config->irq_config_func(dev);
return 0;
}
static const struct i2c_driver_api mcux_flexcomm_driver_api = {
.configure = mcux_flexcomm_configure,
.transfer = mcux_flexcomm_transfer,
#if defined(CONFIG_I2C_TARGET)
.target_register = mcux_flexcomm_target_register,
.target_unregister = mcux_flexcomm_target_unregister,
#endif
};
#define I2C_MCUX_FLEXCOMM_DEVICE(id) \
PINCTRL_DT_INST_DEFINE(id); \
static void mcux_flexcomm_config_func_##id(const struct device *dev); \
static const struct mcux_flexcomm_config mcux_flexcomm_config_##id = { \
.base = (I2C_Type *) DT_INST_REG_ADDR(id), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(id, name),\
.irq_config_func = mcux_flexcomm_config_func_##id, \
.bitrate = DT_INST_PROP(id, clock_frequency), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \
.reset = RESET_DT_SPEC_INST_GET(id), \
}; \
static struct mcux_flexcomm_data mcux_flexcomm_data_##id; \
I2C_DEVICE_DT_INST_DEFINE(id, \
mcux_flexcomm_init, \
NULL, \
&mcux_flexcomm_data_##id, \
&mcux_flexcomm_config_##id, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&mcux_flexcomm_driver_api); \
static void mcux_flexcomm_config_func_##id(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(id), \
DT_INST_IRQ(id, priority), \
mcux_flexcomm_isr, \
DEVICE_DT_INST_GET(id), \
0); \
irq_enable(DT_INST_IRQN(id)); \
} \
DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_FLEXCOMM_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_mcux_flexcomm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,047 |
```unknown
# NUMAKER I2C driver configuration options
config I2C_NUMAKER
bool "Nuvoton NuMaker I2C driver"
default y
select HAS_NUMAKER_I2C
depends on DT_HAS_NUVOTON_NUMAKER_I2C_ENABLED
help
This option enables I2C driver for Nuvoton NuMaker family of
processors.
Say y if you wish to enable NuMaker I2C.
``` | /content/code_sandbox/drivers/i2c/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```unknown
config I2C_SIFIVE
bool "Sifive I2C driver"
default y
depends on DT_HAS_SIFIVE_I2C0_ENABLED
help
Enable I2C support on SiFive Freedom
``` | /content/code_sandbox/drivers/i2c/Kconfig.sifive | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
# Renesas R-Car Gen3 I2C configuration options
config I2C_RCAR
bool "Renesas R-Car I2C Driver"
default y
depends on DT_HAS_RENESAS_RCAR_I2C_ENABLED
help
Enable Renesas R-Car I2C Driver.
``` | /content/code_sandbox/drivers/i2c/Kconfig.rcar | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
#
#
#
config I2C_SEDI
bool "Intel SEDI I2C Driver"
default y
depends on DT_HAS_INTEL_SEDI_I2C_ENABLED
help
This option enables the Intel SEDI I2C driver.
This driver is simply a shim driver built upon the SEDI
bare metal I2C driver in the hal-intel module
``` | /content/code_sandbox/drivers/i2c/Kconfig.sedi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_
#define ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_
#include <zephyr/drivers/pinctrl.h>
#define PINCTRL_STATE_FAST_PLUS PINCTRL_STATE_PRIV_START
#define LPC11U6X_I2C_CONTROL_AA (1 << 2)
#define LPC11U6X_I2C_CONTROL_SI (1 << 3)
#define LPC11U6X_I2C_CONTROL_STOP (1 << 4)
#define LPC11U6X_I2C_CONTROL_START (1 << 5)
#define LPC11U6X_I2C_CONTROL_I2C_EN (1 << 6)
/* I2C controller states */
#define LPC11U6X_I2C_MASTER_TX_START 0x08
#define LPC11U6X_I2C_MASTER_TX_RESTART 0x10
#define LPC11U6X_I2C_MASTER_TX_ADR_ACK 0x18
#define LPC11U6X_I2C_MASTER_TX_ADR_NACK 0x20
#define LPC11U6X_I2C_MASTER_TX_DAT_ACK 0x28
#define LPC11U6X_I2C_MASTER_TX_DAT_NACK 0x30
#define LPC11U6X_I2C_MASTER_TX_ARB_LOST 0x38
#define LPC11U6X_I2C_MASTER_RX_ADR_ACK 0x40
#define LPC11U6X_I2C_MASTER_RX_ADR_NACK 0x48
#define LPC11U6X_I2C_MASTER_RX_DAT_ACK 0x50
#define LPC11U6X_I2C_MASTER_RX_DAT_NACK 0x58
#define LPC11U6X_I2C_SLAVE_RX_ADR_ACK 0x60
#define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_ADR_ACK 0x68
#define LPC11U6X_I2C_SLAVE_RX_GC_ACK 0x70
#define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_GC_ACK 0x78
#define LPC11U6X_I2C_SLAVE_RX_DAT_ACK 0x80
#define LPC11U6X_I2C_SLAVE_RX_DAT_NACK 0x88
#define LPC11U6X_I2C_SLAVE_RX_GC_DAT_ACK 0x90
#define LPC11U6X_I2C_SLAVE_RX_GC_DAT_NACK 0x98
#define LPC11U6X_I2C_SLAVE_RX_STOP 0xA0
#define LPC11U6X_I2C_SLAVE_TX_ADR_ACK 0xA8
#define LPC11U6X_I2C_SLAVE_TX_ARB_LOST_ADR_ACK 0xB0
#define LPC11U6X_I2C_SLAVE_TX_DAT_ACK 0xB8
#define LPC11U6X_I2C_SLAVE_TX_DAT_NACK 0xC0
#define LPC11U6X_I2C_SLAVE_TX_LAST_BYTE 0xC8
/* Transfer Status */
#define LPC11U6X_I2C_STATUS_BUSY 0x01
#define LPC11U6X_I2C_STATUS_OK 0x02
#define LPC11U6X_I2C_STATUS_FAIL 0x03
#define LPC11U6X_I2C_STATUS_INACTIVE 0x04
struct lpc11u6x_i2c_regs {
volatile uint32_t con_set; /* Control set */
volatile const uint32_t stat; /* Status */
volatile uint32_t dat; /* Data */
volatile uint32_t addr0; /* Slave address 0 */
volatile uint32_t sclh; /* SCL Duty Cycle */
volatile uint32_t scll; /* SCL Duty Cycle */
volatile uint32_t con_clr; /* Control clear */
volatile uint32_t mm_ctrl; /* Monitor mode control */
volatile uint32_t addr[3]; /* Slave address {1,2,3} */
volatile const uint32_t data_buffer; /* Data buffer */
volatile uint32_t mask[4]; /* Slave address mask */
};
struct lpc11u6x_i2c_config {
struct lpc11u6x_i2c_regs *base;
const struct device *clock_dev;
void (*irq_config_func)(const struct device *dev);
uint32_t clkid;
const struct pinctrl_dev_config *pincfg;
};
struct lpc11u6x_i2c_current_transfer {
struct i2c_msg *msgs;
uint8_t *curr_buf;
uint8_t curr_len;
uint8_t nr_msgs;
uint8_t addr;
uint8_t status;
};
struct lpc11u6x_i2c_data {
struct lpc11u6x_i2c_current_transfer transfer;
struct i2c_target_config *slave;
struct k_sem completion;
struct k_mutex mutex;
};
#endif /* ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_lpc11u6x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,085 |
```c
/*
*
*/
#include <zephyr/pm/policy.h>
#define DT_DRV_COMPAT nuvoton_npcx_i2c_ctrl
/**
* @file
* @brief Nuvoton NPCX smb/i2c module (controller) driver
*
* This file contains the driver of SMB module (controller) which provides full
* support for a two-wire SMBus/I2C synchronous serial interface. The following
* is the state diagrams for each Zephyr i2c api functions.
*
* case 1: i2c_write()/i2c_burst_write()
*
* All msg data sent? Is there next msg?
* +<----------------+<----------------------+
* | No | | Yes
* +------+ +------------+ | +------- ----+ | +------- -------+ |
* +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
* | +------+ +------------+ +------------+ Yes +---------------+ |
* | Issue START START completed | No
* | +-----------+ |
* +--------------------------------------------| WAIT_STOP |<------------+
* STOP is completed +-----------+ Issue STOP
*
*
* case 2: i2c_read()
*
* All msg data received? Is there next msg?
* +<-----------------+<---------------------+
* | No | | Yes
* +------+ +------------+ | +------- ---+ | +------- ------+ |
* +->| IDLE |-->| WAIT_START |--->| READ_FIFO |---+--->| READ_SUSPEND |--+
* | +------+ +------------+ +------------+ Yes +--------------+ |
* | Issue START START completed | No
* | +-----------+ |
* +------------------------------------------| WAIT_STOP |<--------------+
* STOP is completed +-----------+ Issue STOP
*
*
* case 3: i2c_write_read()/i2c_burst_read()
*
* All msg data sent? Is there next write msg?
* +<----------------+<----------------------+
* | No | | Yes
* +------+ +------------+ | +------- ----+ | +------- -------+ |
* +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
* | +------+ +------------+ +------------+ Yes +---------------+ |
* | Issue START START completed | No
* | +---------------------------------------------------------------+
* | |
* | | All msg data received? Is there next read msg?
* | | +<-----------------+<-----------------------+
* | | | No | | Yes
* | | +--------------+ | +------- ---+ | +------- ------+ |
* | +--| WAIT_RESTART |--->| READ_FIFO |---+--->| READ_SUSPEND |----+
* | +--------------+ +-----------+ Yes +--------------+ |
* | Issue RESTART RESTART completed | No
* | +-----------+ |
* +-------------------------------------------| WAIT_STOP |<-------------+
* STOP is completed +-----------+ Issue STOP
*
*/
#include <assert.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/atomic.h>
#include <soc.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_npcx, LOG_LEVEL_ERR);
/* I2C controller mode */
#define NPCX_I2C_BANK_NORMAL 0
#define NPCX_I2C_BANK_FIFO 1
/* Timeout for device should be available after reset (SMBus spec. unit:ms) */
#define I2C_MAX_TIMEOUT 35
/* Timeout for SCL held to low by slave device . (SMBus spec. unit:ms). */
#define I2C_MIN_TIMEOUT 25
/* Default maximum time we allow for an I2C transfer (unit:ms) */
#define I2C_TRANS_TIMEOUT K_MSEC(100)
/*
* NPCX I2C module that supports FIFO mode has 32 bytes Tx FIFO and
* 32 bytes Rx FIFO.
*/
#define NPCX_I2C_FIFO_MAX_SIZE 32
/* Valid bit fields in SMBST register */
#define NPCX_VALID_SMBST_MASK ~(BIT(NPCX_SMBST_XMIT) | BIT(NPCX_SMBST_MASTER))
/* The delay for the I2C bus recovery bitbang in ~100K Hz */
#define I2C_RECOVER_BUS_DELAY_US 5
#define I2C_RECOVER_SCL_RETRY 10
#define I2C_RECOVER_SDA_RETRY 3
/* Supported I2C bus frequency */
enum npcx_i2c_freq {
NPCX_I2C_BUS_SPEED_100KHZ,
NPCX_I2C_BUS_SPEED_400KHZ,
NPCX_I2C_BUS_SPEED_1MHZ,
};
enum npcx_i2c_flag {
NPCX_I2C_FLAG_TARGET,
NPCX_I2C_FLAG_COUNT,
};
/*
* Internal SMBus Interface driver states values, which reflect events
* which occurred on the bus
*/
enum npcx_i2c_oper_state {
NPCX_I2C_IDLE,
NPCX_I2C_WAIT_START,
NPCX_I2C_WAIT_RESTART,
NPCX_I2C_WRITE_FIFO,
NPCX_I2C_WRITE_SUSPEND,
NPCX_I2C_READ_FIFO,
NPCX_I2C_READ_SUSPEND,
NPCX_I2C_WAIT_STOP,
NPCX_I2C_ERROR_RECOVERY,
};
/* I2C timing configuration for each i2c speed */
struct npcx_i2c_timing_cfg {
uint8_t HLDT; /* i2c hold-time (Unit: clocks) */
uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */
uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */
};
/* Device config */
struct i2c_ctrl_config {
uintptr_t base; /* i2c controller base address */
struct npcx_clk_cfg clk_cfg; /* clock configuration */
uint8_t irq; /* i2c controller irq */
};
/* Driver data */
struct i2c_ctrl_data {
struct k_sem lock_sem; /* mutex of i2c controller */
struct k_sem sync_sem; /* semaphore used for synchronization */
uint32_t bus_freq; /* operation freq of i2c */
enum npcx_i2c_oper_state oper_state; /* controller operation state */
int trans_err; /* error code during transaction */
struct i2c_msg *msg; /* cache msg for transaction state machine */
int is_write; /* direction of current msg */
uint8_t *ptr_msg; /* current msg pointer for FIFO read/write */
uint16_t addr; /* slave address of transaction */
uint8_t port; /* current port used the controller */
bool is_configured; /* is port configured? */
const struct npcx_i2c_timing_cfg *ptr_speed_confs;
#ifdef CONFIG_I2C_TARGET
struct i2c_target_config *target_cfg;
atomic_t flags;
#endif
};
/* Driver convenience defines */
#define HAL_I2C_INSTANCE(dev) \
((struct smb_reg *)((const struct i2c_ctrl_config *)(dev)->config)->base)
/* Recommended I2C timing values are based on 15 MHz */
static const struct npcx_i2c_timing_cfg npcx_15m_speed_confs[] = {
[NPCX_I2C_BUS_SPEED_100KHZ] = {.HLDT = 15, .k1 = 76, .k2 = 0},
[NPCX_I2C_BUS_SPEED_400KHZ] = {.HLDT = 7, .k1 = 24, .k2 = 18,},
[NPCX_I2C_BUS_SPEED_1MHZ] = {.HLDT = 7, .k1 = 14, .k2 = 10,},
};
static const struct npcx_i2c_timing_cfg npcx_20m_speed_confs[] = {
[NPCX_I2C_BUS_SPEED_100KHZ] = {.HLDT = 15, .k1 = 102, .k2 = 0},
[NPCX_I2C_BUS_SPEED_400KHZ] = {.HLDT = 7, .k1 = 32, .k2 = 22},
[NPCX_I2C_BUS_SPEED_1MHZ] = {.HLDT = 7, .k1 = 16, .k2 = 10},
};
/* I2C controller inline functions access shared registers */
static inline void i2c_ctrl_start(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_START);
}
static inline void i2c_ctrl_stop(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_STOP);
}
static inline int i2c_ctrl_bus_busy(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
return IS_BIT_SET(inst->SMBCST, NPCX_SMBCST_BB);
}
static inline void i2c_ctrl_bank_sel(const struct device *dev, int bank)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
if (bank) {
inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_BNK_SEL);
} else {
inst->SMBCTL3 &= ~BIT(NPCX_SMBCTL3_BNK_SEL);
}
}
static inline void i2c_ctrl_irq_enable(const struct device *dev, int enable)
{
const struct i2c_ctrl_config *const config = dev->config;
if (enable) {
irq_enable(config->irq);
} else {
irq_disable(config->irq);
}
}
/* I2C controller inline functions access registers in 'Normal' bank */
static inline void i2c_ctrl_norm_stall_scl(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
/* Enable writing to SCL_LVL/SDA_LVL bit in SMBnCTL3 */
inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE);
/* Force SCL bus to low and keep SDA floating */
inst->SMBCTL3 = (inst->SMBCTL3 & ~BIT(NPCX_SMBCTL3_SCL_LVL))
| BIT(NPCX_SMBCTL3_SDA_LVL);
/* Disable writing to them */
inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE);
}
static inline void i2c_ctrl_norm_free_scl(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
/* Enable writing to SCL_LVL/SDA_LVL bit in SMBnCTL3 */
inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE);
/*
* Release SCL bus. Then it might be still driven by module itself or
* slave device.
*/
inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_SCL_LVL) | BIT(NPCX_SMBCTL3_SDA_LVL);
/* Disable writing to them */
inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE);
}
/* I2C controller inline functions access registers in 'Normal' bank */
static inline void i2c_ctrl_norm_stall_sda(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
/* Enable writing to SCL_LVL/SDA_LVL bit in SMBnCTL3 */
inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE);
/* Force SDA bus to low and keep SCL floating */
inst->SMBCTL3 = (inst->SMBCTL3 & ~BIT(NPCX_SMBCTL3_SDA_LVL))
| BIT(NPCX_SMBCTL3_SCL_LVL);
/* Disable writing to them */
inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE);
}
static inline void i2c_ctrl_norm_free_sda(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
/* Enable writing to SCL_LVL/SDA_LVL bit in SMBnCTL3 */
inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE);
/*
* Release SDA bus. Then it might be still driven by module itself or
* slave device.
*/
inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_SDA_LVL) | BIT(NPCX_SMBCTL3_SCL_LVL);
/* Disable writing to them */
inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE);
}
/* I2C controller inline functions access registers in 'FIFO' bank */
static inline void i2c_ctrl_fifo_write(const struct device *dev, uint8_t data)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
inst->SMBSDA = data;
}
static inline uint8_t i2c_ctrl_fifo_read(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
return inst->SMBSDA;
}
static inline int i2c_ctrl_fifo_tx_avail(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
return NPCX_I2C_FIFO_MAX_SIZE - (inst->SMBTXF_STS & 0x3f);
}
static inline int i2c_ctrl_fifo_rx_occupied(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
return inst->SMBRXF_STS & 0x3f;
}
static inline void i2c_ctrl_fifo_rx_setup_threshold_nack(
const struct device *dev, int threshold, int last)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
uint8_t value = MIN(threshold, NPCX_I2C_FIFO_MAX_SIZE);
SET_FIELD(inst->SMBRXF_CTL, NPCX_SMBRXF_CTL_RX_THR, value);
/*
* Is it last received transaction? If so, set LAST bit. Then the
* hardware will generate NACK automatically when receiving last byte.
*/
if (last && (value == threshold)) {
inst->SMBRXF_CTL |= BIT(NPCX_SMBRXF_CTL_LAST);
}
}
static inline void i2c_ctrl_fifo_clear_status(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
inst->SMBFIF_CTS |= BIT(NPCX_SMBFIF_CTS_CLR_FIFO);
}
/*
* I2C local functions which touch the registers in 'Normal' bank. These
* utilities will change bank back to FIFO mode when leaving themselves in case
* the other utilities access the registers in 'FIFO' bank.
*/
static void i2c_ctrl_hold_bus(const struct device *dev, int stall)
{
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_NORMAL);
if (stall) {
i2c_ctrl_norm_stall_scl(dev);
} else {
i2c_ctrl_norm_free_scl(dev);
}
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_FIFO);
}
static void i2c_ctrl_init_module(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_NORMAL);
/* Enable FIFO mode first */
inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN);
/* Enable module - before configuring CTL1 */
inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
/* Enable SMB interrupt and 'New Address Match' interrupt source */
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_FIFO);
}
static void i2c_ctrl_config_bus_freq(const struct device *dev,
enum npcx_i2c_freq bus_freq)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
struct i2c_ctrl_data *const data = dev->data;
const struct npcx_i2c_timing_cfg bus_cfg =
data->ptr_speed_confs[bus_freq];
/* Switch to bank 0 to configure bus speed */
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_NORMAL);
/* Configure bus speed */
if (bus_freq == NPCX_I2C_BUS_SPEED_100KHZ) {
/* Enable 'Normal' Mode */
inst->SMBCTL3 &= ~(BIT(NPCX_SMBCTL3_400K));
/* Set freq of SCL. For 100KHz, only k1 is used. */
SET_FIELD(inst->SMBCTL2, NPCX_SMBCTL2_SCLFRQ0_6_FIELD,
bus_cfg.k1/2 & 0x7f);
SET_FIELD(inst->SMBCTL3, NPCX_SMBCTL3_SCLFRQ7_8_FIELD,
bus_cfg.k1/2 >> 7);
SET_FIELD(inst->SMBCTL4, NPCX_SMBCTL4_HLDT_FIELD,
bus_cfg.HLDT);
} else {
/* Enable 'Fast' Mode for 400K or higher freq. */
inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_400K);
/* Set high/low time of SCL and hold-time */
inst->SMBSCLLT = bus_cfg.k1/2;
inst->SMBSCLHT = bus_cfg.k2/2;
SET_FIELD(inst->SMBCTL4, NPCX_SMBCTL4_HLDT_FIELD,
bus_cfg.HLDT);
}
/* Switch to bank 1 to access I2C FIFO registers */
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_FIFO);
}
/* I2C controller local functions */
static int i2c_ctrl_wait_stop_completed(const struct device *dev, int timeout)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
if (timeout <= 0) {
return -EINVAL;
}
do {
/*
* Wait till i2c bus is idle. This bit is cleared to 0
* automatically after the STOP condition is generated.
*/
if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP)) {
break;
}
k_msleep(1);
} while (--timeout);
if (timeout > 0) {
return 0;
} else {
return -ETIMEDOUT;
}
}
static bool i2c_ctrl_is_scl_sda_both_high(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL) &&
IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) {
return true;
}
return false;
}
static int i2c_ctrl_wait_idle_completed(const struct device *dev, int timeout)
{
if (timeout <= 0) {
return -EINVAL;
}
do {
/* Wait for both SCL & SDA lines are high */
if (i2c_ctrl_is_scl_sda_both_high(dev)) {
break;
}
k_msleep(1);
} while (--timeout);
if (timeout > 0) {
return 0;
} else {
return -ETIMEDOUT;
}
}
static int i2c_ctrl_recovery(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
struct i2c_ctrl_data *const data = dev->data;
int ret;
if (data->oper_state != NPCX_I2C_ERROR_RECOVERY) {
data->oper_state = NPCX_I2C_ERROR_RECOVERY;
}
/* Step 1: Make sure the bus is not stalled before exit. */
i2c_ctrl_hold_bus(dev, 0);
/*
* Step 2: Abort data, wait for STOP condition completed.
* - Clearing NEGACK and BER bits first
* - Wait for STOP condition completed
* - Then clear BB (BUS BUSY) bit
*/
inst->SMBST = BIT(NPCX_SMBST_BER) | BIT(NPCX_SMBST_NEGACK);
ret = i2c_ctrl_wait_stop_completed(dev, I2C_MAX_TIMEOUT);
inst->SMBCST |= BIT(NPCX_SMBCST_BB);
if (ret != 0) {
LOG_ERR("Abort i2c port%02x fail! Bus might be stalled.",
data->port);
}
/*
* Step 3: Reset i2c module to clear all internal state machine of it
* - Disable the SMB module first
* - Wait both SCL/SDA line are high
* - Enable i2c module again
*/
inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
ret = i2c_ctrl_wait_idle_completed(dev, I2C_MAX_TIMEOUT);
if (ret != 0) {
LOG_ERR("Reset i2c port%02x fail! Bus might be stalled.",
data->port);
return -EIO;
}
/* Reset module and internal state machine */
i2c_ctrl_init_module(dev);
/* Recovery is completed */
data->oper_state = NPCX_I2C_IDLE;
return 0;
}
static void i2c_ctrl_notify(const struct device *dev, int error)
{
struct i2c_ctrl_data *const data = dev->data;
data->trans_err = error;
k_sem_give(&data->sync_sem);
}
static int i2c_ctrl_wait_completion(const struct device *dev)
{
struct i2c_ctrl_data *const data = dev->data;
if (k_sem_take(&data->sync_sem, I2C_TRANS_TIMEOUT) == 0) {
return data->trans_err;
} else {
return -ETIMEDOUT;
}
}
size_t i2c_ctrl_calculate_msg_remains(const struct device *dev)
{
struct i2c_ctrl_data *const data = dev->data;
uint8_t *buf_end = data->msg->buf + data->msg->len;
return (buf_end > data->ptr_msg) ? (buf_end - data->ptr_msg) : 0;
}
static void i2c_ctrl_handle_write_int_event(const struct device *dev)
{
struct i2c_ctrl_data *const data = dev->data;
/* START condition is issued */
if (data->oper_state == NPCX_I2C_WAIT_START) {
/* Write slave address with W bit */
i2c_ctrl_fifo_write(dev, ((data->addr << 1) & ~BIT(0)));
/* Start to proceed write process */
data->oper_state = NPCX_I2C_WRITE_FIFO;
return;
}
/* Write message data bytes to FIFO */
if (data->oper_state == NPCX_I2C_WRITE_FIFO) {
/* Calculate how many remaining bytes need to transmit */
size_t tx_remain = i2c_ctrl_calculate_msg_remains(dev);
size_t tx_avail = MIN(tx_remain, i2c_ctrl_fifo_tx_avail(dev));
LOG_DBG("tx remains %d, avail %d", tx_remain, tx_avail);
for (int i = 0U; i < tx_avail; i++) {
i2c_ctrl_fifo_write(dev, *(data->ptr_msg++));
}
/* Is there any remaining bytes? */
if (data->ptr_msg == data->msg->buf + data->msg->len) {
data->oper_state = NPCX_I2C_WRITE_SUSPEND;
}
return;
}
/* Issue STOP after sending message? */
if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) {
if (data->msg->flags & I2C_MSG_STOP) {
/* Generate a STOP condition immediately */
i2c_ctrl_stop(dev);
/* Clear rx FIFO threshold and status bits */
i2c_ctrl_fifo_clear_status(dev);
/* Wait for STOP completed */
data->oper_state = NPCX_I2C_WAIT_STOP;
} else {
/* Disable interrupt and handle next message */
i2c_ctrl_irq_enable(dev, 0);
}
}
return i2c_ctrl_notify(dev, 0);
}
static void i2c_ctrl_handle_read_int_event(const struct device *dev)
{
struct i2c_ctrl_data *const data = dev->data;
/* START or RESTART condition is issued */
if (data->oper_state == NPCX_I2C_WAIT_START ||
data->oper_state == NPCX_I2C_WAIT_RESTART) {
/* Setup threshold of rx FIFO before sending address byte */
i2c_ctrl_fifo_rx_setup_threshold_nack(dev, data->msg->len,
(data->msg->flags & I2C_MSG_STOP) != 0);
/* Write slave address with R bit */
i2c_ctrl_fifo_write(dev, ((data->addr << 1) | BIT(0)));
/* Start to proceed read process */
data->oper_state = NPCX_I2C_READ_FIFO;
return;
}
/* Read message data bytes from FIFO */
if (data->oper_state == NPCX_I2C_READ_FIFO) {
/* Calculate how many remaining bytes need to receive */
size_t rx_remain = i2c_ctrl_calculate_msg_remains(dev);
size_t rx_occupied = i2c_ctrl_fifo_rx_occupied(dev);
LOG_DBG("rx remains %d, occupied %d", rx_remain, rx_occupied);
/* Is it the last read transaction with STOP condition? */
if (rx_occupied >= rx_remain &&
(data->msg->flags & I2C_MSG_STOP) != 0) {
/*
* Generate a STOP condition before reading data bytes
* from FIFO. It prevents a glitch on SCL.
*/
i2c_ctrl_stop(dev);
} else {
/*
* Hold SCL line here in case the hardware releases bus
* immediately after the driver start to read data from
* FIFO. Then we might lose incoming data from device.
*/
i2c_ctrl_hold_bus(dev, 1);
}
/* Read data bytes from FIFO */
for (int i = 0; i < rx_occupied; i++) {
*(data->ptr_msg++) = i2c_ctrl_fifo_read(dev);
}
rx_remain = i2c_ctrl_calculate_msg_remains(dev);
/* Setup threshold of RX FIFO if needed */
if (rx_remain > 0) {
i2c_ctrl_fifo_rx_setup_threshold_nack(dev, rx_remain,
(data->msg->flags & I2C_MSG_STOP) != 0);
/* Release bus */
i2c_ctrl_hold_bus(dev, 0);
return;
}
}
/* Is the STOP condition issued? */
if ((data->msg->flags & I2C_MSG_STOP) != 0) {
/* Clear rx FIFO threshold and status bits */
i2c_ctrl_fifo_clear_status(dev);
/* Wait for STOP completed */
data->oper_state = NPCX_I2C_WAIT_STOP;
} else {
/* Disable i2c interrupt first */
i2c_ctrl_irq_enable(dev, 0);
data->oper_state = NPCX_I2C_READ_SUSPEND;
}
return i2c_ctrl_notify(dev, 0);
}
static int i2c_ctrl_proc_write_msg(const struct device *dev,
struct i2c_msg *msg)
{
struct i2c_ctrl_data *const data = dev->data;
data->is_write = 1;
data->ptr_msg = msg->buf;
data->msg = msg;
if (data->oper_state == NPCX_I2C_IDLE) {
data->oper_state = NPCX_I2C_WAIT_START;
/* Clear FIFO status before starting a new transaction */
i2c_ctrl_fifo_clear_status(dev);
/* Issue a START, wait for transaction completed */
i2c_ctrl_start(dev);
return i2c_ctrl_wait_completion(dev);
} else if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) {
data->oper_state = NPCX_I2C_WRITE_FIFO;
i2c_ctrl_irq_enable(dev, 1);
return i2c_ctrl_wait_completion(dev);
}
LOG_ERR("Unexpected state %d during writing i2c port%02x!",
data->oper_state, data->port);
data->trans_err = -EIO;
return data->trans_err;
}
static int i2c_ctrl_proc_read_msg(const struct device *dev, struct i2c_msg *msg)
{
struct i2c_ctrl_data *const data = dev->data;
data->is_write = 0;
data->ptr_msg = msg->buf;
data->msg = msg;
if (data->oper_state == NPCX_I2C_IDLE) {
data->oper_state = NPCX_I2C_WAIT_START;
/* Clear FIFO status before starting a new transaction */
i2c_ctrl_fifo_clear_status(dev);
/* Issue a START, wait for transaction completed */
i2c_ctrl_start(dev);
return i2c_ctrl_wait_completion(dev);
} else if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) {
data->oper_state = NPCX_I2C_WAIT_RESTART;
/* Issue a RESTART, wait for transaction completed */
i2c_ctrl_start(dev);
i2c_ctrl_irq_enable(dev, 1);
return i2c_ctrl_wait_completion(dev);
} else if (data->oper_state == NPCX_I2C_READ_SUSPEND) {
data->oper_state = NPCX_I2C_READ_FIFO;
/* Setup threshold of RX FIFO first */
i2c_ctrl_fifo_rx_setup_threshold_nack(dev, msg->len,
(msg->flags & I2C_MSG_STOP) != 0);
/* Release bus */
i2c_ctrl_hold_bus(dev, 0);
/* Enable i2c interrupt first */
i2c_ctrl_irq_enable(dev, 1);
return i2c_ctrl_wait_completion(dev);
}
LOG_ERR("Unexpected state %d during reading i2c port%02x!",
data->oper_state, data->port);
data->trans_err = -EIO;
return data->trans_err;
}
/* I2C controller isr function */
#ifdef CONFIG_I2C_TARGET
static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
struct i2c_ctrl_data *const data = dev->data;
const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
uint8_t val = 0;
/* A 'Bus Error' has been identified */
if (IS_BIT_SET(status, NPCX_SMBST_BER)) {
/* Clear BER Bit */
inst->SMBST = BIT(NPCX_SMBST_BER);
/* Notify upper layer the end of transaction */
if (target_cb->stop) {
target_cb->stop(data->target_cfg);
}
/* Reset i2c module in target mode */
inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
/*
* Re-enable interrupts because they are turned off after the SMBus module
* is reset above.
*/
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
/* End of transaction */
data->oper_state = NPCX_I2C_IDLE;
LOG_DBG("target: Bus error on port%02x!", data->port);
return;
}
/* A 'Slave Stop' Condition has been identified */
if (IS_BIT_SET(status, NPCX_SMBST_SLVSTP)) {
/* Clear SLVSTP Bit */
inst->SMBST = BIT(NPCX_SMBST_SLVSTP);
/* End of transaction */
data->oper_state = NPCX_I2C_IDLE;
/* Notify upper layer a STOP condition received */
if (target_cb->stop) {
target_cb->stop(data->target_cfg);
}
return;
}
/* A negative acknowledge has occurred */
if (IS_BIT_SET(status, NPCX_SMBST_NEGACK)) {
/* Clear NEGACK Bit */
inst->SMBST = BIT(NPCX_SMBST_NEGACK);
/* Do nothing in i2c target mode */
return;
}
/* A 'Target Address Match' has been identified */
if (IS_BIT_SET(status, NPCX_SMBST_NMATCH)) {
/* Clear NMATCH Bit */
inst->SMBST = BIT(NPCX_SMBST_NMATCH);
/* Distinguish the direction of i2c target mode by reading XMIT bit */
if (IS_BIT_SET(inst->SMBST, NPCX_SMBST_XMIT)) {
/* Start transmitting data in i2c target mode */
data->oper_state = NPCX_I2C_WRITE_FIFO;
/* Write first requested byte after repeated start */
if (target_cb->read_requested) {
target_cb->read_requested(data->target_cfg, &val);
}
inst->SMBSDA = val;
} else {
/* Start receiving data in i2c target mode */
data->oper_state = NPCX_I2C_READ_FIFO;
if (target_cb->write_requested) {
target_cb->write_requested(data->target_cfg);
}
}
return;
}
/* Tx byte empty or Rx byte full has occurred */
if (IS_BIT_SET(status, NPCX_SMBST_SDAST)) {
if (data->oper_state == NPCX_I2C_WRITE_FIFO) {
/* Notify upper layer one byte will be transmitted */
if (target_cb->read_processed) {
target_cb->read_processed(data->target_cfg, &val);
}
inst->SMBSDA = val;
} else if (data->oper_state == NPCX_I2C_READ_FIFO) {
if (target_cb->write_received) {
val = inst->SMBSDA;
/* Notify upper layer one byte received */
target_cb->write_received(data->target_cfg, val);
}
} else {
LOG_ERR("Unexpected oper state %d on i2c target port%02x!",
data->oper_state, data->port);
}
return;
}
/* Clear unexpected status bits */
if (status != 0) {
inst->SMBST = status;
LOG_ERR("Unexpected SMBST 0x%02x occurred on i2c target port%02x!",
status, data->port);
}
}
#endif
/* I2C controller isr function */
static void i2c_ctrl_isr(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
struct i2c_ctrl_data *const data = dev->data;
uint8_t status, tmp;
status = inst->SMBST & NPCX_VALID_SMBST_MASK;
LOG_DBG("status: %02x, %d", status, data->oper_state);
#ifdef CONFIG_I2C_TARGET
if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
return i2c_ctrl_target_isr(dev, status);
}
#endif
/* A 'Bus Error' has been identified */
if (IS_BIT_SET(status, NPCX_SMBST_BER)) {
/* Generate a STOP condition immediately */
i2c_ctrl_stop(dev);
/* Clear BER Bit */
inst->SMBST = BIT(NPCX_SMBST_BER);
/* Make sure slave doesn't hold bus by reading FIFO again */
tmp = i2c_ctrl_fifo_read(dev);
LOG_ERR("Bus error occurred on i2c port%02x!", data->port);
data->oper_state = NPCX_I2C_ERROR_RECOVERY;
/* I/O error occurred */
i2c_ctrl_notify(dev, -EIO);
return;
}
/* A negative acknowledge has occurred */
if (IS_BIT_SET(status, NPCX_SMBST_NEGACK)) {
/* Generate a STOP condition immediately */
i2c_ctrl_stop(dev);
/* Clear NEGACK Bit */
inst->SMBST = BIT(NPCX_SMBST_NEGACK);
/* End transaction */
data->oper_state = NPCX_I2C_WAIT_STOP;
/* No such device or address */
return i2c_ctrl_notify(dev, -ENXIO);
}
/* START, tx FIFO empty or rx FIFO full has occurred */
if (IS_BIT_SET(status, NPCX_SMBST_SDAST)) {
if (data->is_write) {
return i2c_ctrl_handle_write_int_event(dev);
} else {
return i2c_ctrl_handle_read_int_event(dev);
}
}
/* Clear unexpected status bits */
if (status != 0) {
inst->SMBST = status;
LOG_ERR("Unexpected SMBST 0x%02x occurred on i2c port%02x!",
status, data->port);
}
}
/* NPCX specific I2C controller functions */
void npcx_i2c_ctrl_mutex_lock(const struct device *i2c_dev)
{
struct i2c_ctrl_data *const data = i2c_dev->data;
k_sem_take(&data->lock_sem, K_FOREVER);
}
void npcx_i2c_ctrl_mutex_unlock(const struct device *i2c_dev)
{
struct i2c_ctrl_data *const data = i2c_dev->data;
k_sem_give(&data->lock_sem);
}
int npcx_i2c_ctrl_configure(const struct device *i2c_dev, uint32_t dev_config)
{
struct i2c_ctrl_data *const data = i2c_dev->data;
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
data->bus_freq = NPCX_I2C_BUS_SPEED_100KHZ;
break;
case I2C_SPEED_FAST:
data->bus_freq = NPCX_I2C_BUS_SPEED_400KHZ;
break;
case I2C_SPEED_FAST_PLUS:
data->bus_freq = NPCX_I2C_BUS_SPEED_1MHZ;
break;
default:
return -ERANGE;
}
i2c_ctrl_config_bus_freq(i2c_dev, data->bus_freq);
data->is_configured = true;
return 0;
}
int npcx_i2c_ctrl_get_speed(const struct device *i2c_dev, uint32_t *speed)
{
struct i2c_ctrl_data *const data = i2c_dev->data;
if (!data->is_configured) {
return -EIO;
}
switch (data->bus_freq) {
case NPCX_I2C_BUS_SPEED_100KHZ:
*speed = I2C_SPEED_SET(I2C_SPEED_STANDARD);
break;
case NPCX_I2C_BUS_SPEED_400KHZ:
*speed = I2C_SPEED_SET(I2C_SPEED_FAST);
break;
case NPCX_I2C_BUS_SPEED_1MHZ:
*speed = I2C_SPEED_SET(I2C_SPEED_FAST_PLUS);
break;
default:
return -ERANGE;
}
return 0;
}
int npcx_i2c_ctrl_recover_bus(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
int ret = 0;
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_NORMAL);
/*
* When the SCL is low, wait for a while in case of the clock is stalled
* by a I2C target.
*/
if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) {
for (int i = 0;; i++) {
if (i >= I2C_RECOVER_SCL_RETRY) {
ret = -EBUSY;
goto recover_exit;
}
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) {
break;
}
}
}
if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) {
goto recover_exit;
}
for (int i = 0; i < I2C_RECOVER_SDA_RETRY; i++) {
/* Drive the clock high. */
i2c_ctrl_norm_free_scl(dev);
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
/*
* Toggle SCL to generate 9 clocks. If the I2C target releases the SDA, we can stop
* toggle the SCL and issue a STOP.
*/
for (int j = 0; j < 9; j++) {
if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) {
break;
}
i2c_ctrl_norm_stall_scl(dev);
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
i2c_ctrl_norm_free_scl(dev);
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
}
/* Drive the SDA line to issue STOP. */
i2c_ctrl_norm_stall_sda(dev);
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
i2c_ctrl_norm_free_sda(dev);
k_busy_wait(I2C_RECOVER_BUS_DELAY_US);
if (i2c_ctrl_is_scl_sda_both_high(dev)) {
ret = 0;
goto recover_exit;
}
}
if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) {
LOG_ERR("Recover SDA fail");
ret = -EBUSY;
}
if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) {
LOG_ERR("Recover SCL fail");
ret = -EBUSY;
}
recover_exit:
i2c_ctrl_bank_sel(dev, NPCX_I2C_BANK_FIFO);
return ret;
}
#ifdef CONFIG_I2C_TARGET
int npcx_i2c_ctrl_target_register(const struct device *i2c_dev,
struct i2c_target_config *target_cfg, uint8_t port)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(i2c_dev);
struct i2c_ctrl_data *const data = i2c_dev->data;
int idx_ctrl = (port & 0xF0) >> 4;
int idx_port = (port & 0x0F);
uint8_t addr = BIT(NPCX_SMBADDR1_SAEN) | target_cfg->address;
/* I2c module has been configured to target mode */
if (atomic_test_and_set_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
return -EBUSY;
}
/* A transiaction is ongoing */
if (data->oper_state != NPCX_I2C_IDLE) {
atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET);
return -EBUSY;
}
data->target_cfg = target_cfg;
i2c_ctrl_irq_enable(i2c_dev, 0);
/* Switch correct port for i2c controller first */
npcx_pinctrl_i2c_port_sel(idx_ctrl, idx_port);
/* Reset I2C module */
inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
/* Select normal bank and single byte mode for i2c target mode */
i2c_ctrl_bank_sel(i2c_dev, NPCX_I2C_BANK_NORMAL);
inst->SMBFIF_CTL &= ~BIT(NPCX_SMBFIF_CTL_FIFO_EN);
inst->SMBADDR1 = addr; /* Enable target mode and configure its address */
/* Reconfigure SMBCTL1 */
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
i2c_ctrl_irq_enable(i2c_dev, 1);
return 0;
}
int npcx_i2c_ctrl_target_unregister(const struct device *i2c_dev,
struct i2c_target_config *target_cfg)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(i2c_dev);
struct i2c_ctrl_data *const data = i2c_dev->data;
/* No I2c module has been configured to target mode */
if (!atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
return -EINVAL;
}
/* A transiaction is ongoing */
if (data->oper_state != NPCX_I2C_IDLE) {
return -EBUSY;
}
data->target_cfg = NULL;
i2c_ctrl_irq_enable(i2c_dev, 0);
/* Reset I2C module */
inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
inst->SMBADDR1 = 0; /* Disable target mode and clear address setting */
/* Enable FIFO mode and select to FIFO bank for i2c controller mode */
inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN);
i2c_ctrl_bank_sel(i2c_dev, NPCX_I2C_BANK_FIFO);
/* Reconfigure SMBCTL1 */
inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
i2c_ctrl_irq_enable(i2c_dev, 1);
/* Mark it as controller mode */
atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET);
return 0;
}
#endif
int npcx_i2c_ctrl_transfer(const struct device *i2c_dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr, int port)
{
struct i2c_ctrl_data *const data = i2c_dev->data;
int ret = 0;
uint8_t i;
#ifdef CONFIG_I2C_TARGET
/* I2c module has been configured to target mode */
if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
return -EBUSY;
}
#endif
/*
* suspend-to-idle stops SMB module clocks (derived from APB2/APB3), which must remain
* active during a transaction
*/
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
/* Does bus need recovery? */
if (data->oper_state != NPCX_I2C_WRITE_SUSPEND &&
data->oper_state != NPCX_I2C_READ_SUSPEND) {
if (i2c_ctrl_bus_busy(i2c_dev) || !i2c_ctrl_is_scl_sda_both_high(i2c_dev) ||
data->oper_state == NPCX_I2C_ERROR_RECOVERY) {
ret = npcx_i2c_ctrl_recover_bus(i2c_dev);
if (ret != 0) {
LOG_ERR("Recover Bus failed");
goto out;
}
ret = i2c_ctrl_recovery(i2c_dev);
/* Recovery failed, return it immediately */
if (ret) {
goto out;
}
}
}
/* Start i2c transaction */
data->port = port;
data->trans_err = 0;
data->addr = addr;
/*
* Reset i2c event-completed semaphore before starting transactions.
* Some interrupt events such as BUS_ERROR might change its counter
* when bus is idle.
*/
k_sem_reset(&data->sync_sem);
for (i = 0U; i < num_msgs; i++) {
struct i2c_msg *msg = msgs + i;
/* Handle write transaction */
if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = i2c_ctrl_proc_write_msg(i2c_dev, msg);
} else {/* Handle read transaction */
ret = i2c_ctrl_proc_read_msg(i2c_dev, msg);
}
if (ret < 0) {
break;
}
}
/* Check STOP completed? */
if (data->oper_state == NPCX_I2C_WAIT_STOP) {
data->trans_err = i2c_ctrl_wait_stop_completed(i2c_dev,
I2C_MIN_TIMEOUT);
if (data->trans_err == 0) {
data->oper_state = NPCX_I2C_IDLE;
} else {
LOG_ERR("STOP fail! bus is held on i2c port%02x!",
data->port);
data->oper_state = NPCX_I2C_ERROR_RECOVERY;
}
}
if (data->oper_state == NPCX_I2C_ERROR_RECOVERY || ret == -ETIMEDOUT) {
int recovery_error = i2c_ctrl_recovery(i2c_dev);
/*
* Recovery failed, return it immediately. Otherwise, the upper
* layer still needs to know why the transaction failed.
*/
if (recovery_error != 0) {
ret = recovery_error;
}
}
out:
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
return ret;
}
/* I2C controller driver registration */
static int i2c_ctrl_init(const struct device *dev)
{
const struct i2c_ctrl_config *const config = dev->config;
struct i2c_ctrl_data *const data = dev->data;
const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
uint32_t i2c_rate;
if (!device_is_ready(clk_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Turn on device clock first and get source clock freq. */
if (clock_control_on(clk_dev,
(clock_control_subsys_t) &config->clk_cfg) != 0) {
LOG_ERR("Turn on %s clock fail.", dev->name);
return -EIO;
}
/*
* If apb2/3's clock is not 15MHz, we need to add the other timing
* configuration of the device to meet SMBus timing spec. Please refer
* Table 21/22/23 and section 7.5.9 SMBus Timing for more detail.
*/
if (clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &i2c_rate) != 0) {
LOG_ERR("Get %s clock rate error.", dev->name);
return -EIO;
}
if (i2c_rate == 15000000) {
data->ptr_speed_confs = npcx_15m_speed_confs;
} else if (i2c_rate == 20000000) {
data->ptr_speed_confs = npcx_20m_speed_confs;
} else {
LOG_ERR("Unsupported apb2/3 freq for %s.", dev->name);
return -EIO;
}
/* Initialize i2c module */
i2c_ctrl_init_module(dev);
/* initialize mutex and semaphore for i2c/smb controller */
k_sem_init(&data->lock_sem, 1, 1);
k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
/* Initialize driver status machine */
data->oper_state = NPCX_I2C_IDLE;
return 0;
}
/* I2C controller init macro functions */
#define NPCX_I2C_CTRL_INIT_FUNC(inst) _CONCAT(i2c_ctrl_init_, inst)
#define NPCX_I2C_CTRL_INIT_FUNC_DECL(inst) \
static int i2c_ctrl_init_##inst(const struct device *dev)
#define NPCX_I2C_CTRL_INIT_FUNC_IMPL(inst) \
static int i2c_ctrl_init_##inst(const struct device *dev) \
{ \
int ret; \
\
ret = i2c_ctrl_init(dev); \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
i2c_ctrl_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
\
return ret; \
}
#define NPCX_I2C_CTRL_INIT(inst) \
NPCX_I2C_CTRL_INIT_FUNC_DECL(inst); \
\
static const struct i2c_ctrl_config i2c_ctrl_cfg_##inst = { \
.base = DT_INST_REG_ADDR(inst), \
.irq = DT_INST_IRQN(inst), \
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst), \
}; \
\
static struct i2c_ctrl_data i2c_ctrl_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, \
NPCX_I2C_CTRL_INIT_FUNC(inst), \
NULL, \
&i2c_ctrl_data_##inst, &i2c_ctrl_cfg_##inst, \
PRE_KERNEL_1, CONFIG_I2C_INIT_PRIORITY, \
NULL); \
\
NPCX_I2C_CTRL_INIT_FUNC_IMPL(inst)
DT_INST_FOREACH_STATUS_OKAY(NPCX_I2C_CTRL_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_npcx_controller.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11,838 |
```c
/*
*
*/
/*
* This is not a real I2C driver. It is used to instantiate struct
* devices for the "vnd,i2c" devicetree compatible used in test code.
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#define DT_DRV_COMPAT vnd_i2c
static int vnd_i2c_configure(const struct device *dev,
uint32_t dev_config)
{
return -ENOTSUP;
}
static int vnd_i2c_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
return -ENOTSUP;
}
static const struct i2c_driver_api vnd_i2c_api = {
.configure = vnd_i2c_configure,
.transfer = vnd_i2c_transfer,
};
#define VND_I2C_INIT(n) \
I2C_DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, NULL, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &vnd_i2c_api);
DT_INST_FOREACH_STATUS_OKAY(VND_I2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_test.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 247 |
```c
/*
*
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <nrfx_twim.h>
#include <zephyr/sys/util.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_nrfx_twim, CONFIG_I2C_LOG_LEVEL);
#if CONFIG_I2C_NRFX_TRANSFER_TIMEOUT
#define I2C_TRANSFER_TIMEOUT_MSEC K_MSEC(CONFIG_I2C_NRFX_TRANSFER_TIMEOUT)
#else
#define I2C_TRANSFER_TIMEOUT_MSEC K_FOREVER
#endif
struct i2c_nrfx_twim_data {
struct k_sem transfer_sync;
struct k_sem completion_sync;
volatile nrfx_err_t res;
uint8_t *msg_buf;
};
struct i2c_nrfx_twim_config {
nrfx_twim_t twim;
nrfx_twim_config_t twim_config;
uint16_t msg_buf_size;
void (*irq_connect)(void);
const struct pinctrl_dev_config *pcfg;
uint16_t max_transfer_size;
};
static int i2c_nrfx_twim_recover_bus(const struct device *dev);
static int i2c_nrfx_twim_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_nrfx_twim_data *dev_data = dev->data;
const struct i2c_nrfx_twim_config *dev_config = dev->config;
int ret = 0;
uint8_t *msg_buf = dev_data->msg_buf;
uint16_t msg_buf_used = 0;
uint16_t msg_buf_size = dev_config->msg_buf_size;
nrfx_twim_xfer_desc_t cur_xfer = {
.address = addr
};
k_sem_take(&dev_data->transfer_sync, K_FOREVER);
/* Dummy take on completion_sync sem to be sure that it is empty */
k_sem_take(&dev_data->completion_sync, K_NO_WAIT);
(void)pm_device_runtime_get(dev);
for (size_t i = 0; i < num_msgs; i++) {
if (I2C_MSG_ADDR_10_BITS & msgs[i].flags) {
ret = -ENOTSUP;
break;
}
bool dma_accessible = nrf_dma_accessible_check(&dev_config->twim, msgs[i].buf);
/* This fragment needs to be merged with the next one if:
* - it is not the last fragment
* - it does not end a bus transaction
* - the next fragment does not start a bus transaction
* - the direction of the next fragment is the same as this one
*/
bool concat_next = ((i + 1) < num_msgs)
&& !(msgs[i].flags & I2C_MSG_STOP)
&& !(msgs[i + 1].flags & I2C_MSG_RESTART)
&& ((msgs[i].flags & I2C_MSG_READ)
== (msgs[i + 1].flags & I2C_MSG_READ));
/* If we need to concatenate the next message, or we've
* already committed to concatenate this message, or its buffer
* is not accessible by DMA, add it to the internal driver
* buffer after verifying there's room.
*/
if (concat_next || (msg_buf_used != 0) || !dma_accessible) {
if ((msg_buf_used + msgs[i].len) > msg_buf_size) {
LOG_ERR("Need to use the internal driver "
"buffer but its size is insufficient "
"(%u + %u > %u). "
"Adjust the zephyr,concat-buf-size or "
"zephyr,flash-buf-max-size property "
"(the one with greater value) in the "
"\"%s\" node.",
msg_buf_used, msgs[i].len,
msg_buf_size, dev->name);
ret = -ENOSPC;
break;
}
if (!(msgs[i].flags & I2C_MSG_READ)) {
memcpy(msg_buf + msg_buf_used,
msgs[i].buf,
msgs[i].len);
}
msg_buf_used += msgs[i].len;
}
if (concat_next) {
continue;
}
if (msg_buf_used == 0) {
cur_xfer.p_primary_buf = msgs[i].buf;
cur_xfer.primary_length = msgs[i].len;
} else {
cur_xfer.p_primary_buf = msg_buf;
cur_xfer.primary_length = msg_buf_used;
}
cur_xfer.type = (msgs[i].flags & I2C_MSG_READ) ?
NRFX_TWIM_XFER_RX : NRFX_TWIM_XFER_TX;
if (cur_xfer.primary_length > dev_config->max_transfer_size) {
LOG_ERR("Trying to transfer more than the maximum size "
"for this device: %d > %d",
cur_xfer.primary_length,
dev_config->max_transfer_size);
return -ENOSPC;
}
nrfx_err_t res = nrfx_twim_xfer(&dev_config->twim,
&cur_xfer,
(msgs[i].flags & I2C_MSG_STOP) ?
0 : NRFX_TWIM_FLAG_TX_NO_STOP);
if (res != NRFX_SUCCESS) {
if (res == NRFX_ERROR_BUSY) {
ret = -EBUSY;
break;
} else {
ret = -EIO;
break;
}
}
ret = k_sem_take(&dev_data->completion_sync,
I2C_TRANSFER_TIMEOUT_MSEC);
if (ret != 0) {
/* Whatever the frequency, completion_sync should have
* been given by the event handler.
*
* If it hasn't, it's probably due to an hardware issue
* on the I2C line, for example a short between SDA and
* GND.
* This is issue has also been when trying to use the
* I2C bus during MCU internal flash erase.
*
* In many situation, a retry is sufficient.
* However, some time the I2C device get stuck and need
* help to recover.
* Therefore we always call i2c_nrfx_twim_recover_bus()
* to make sure everything has been done to restore the
* bus from this error.
*/
(void)i2c_nrfx_twim_recover_bus(dev);
ret = -EIO;
break;
}
res = dev_data->res;
if (res != NRFX_SUCCESS) {
ret = -EIO;
break;
}
/* If concatenated messages were I2C_MSG_READ type, then
* content of concatenation buffer has to be copied back into
* buffers provided by user. */
if ((msgs[i].flags & I2C_MSG_READ)
&& cur_xfer.p_primary_buf == msg_buf) {
int j = i;
while (msg_buf_used >= msgs[j].len) {
msg_buf_used -= msgs[j].len;
memcpy(msgs[j].buf,
msg_buf + msg_buf_used,
msgs[j].len);
j--;
}
}
msg_buf_used = 0;
}
(void)pm_device_runtime_put(dev);
k_sem_give(&dev_data->transfer_sync);
return ret;
}
static void event_handler(nrfx_twim_evt_t const *p_event, void *p_context)
{
struct i2c_nrfx_twim_data *dev_data = p_context;
switch (p_event->type) {
case NRFX_TWIM_EVT_DONE:
dev_data->res = NRFX_SUCCESS;
break;
case NRFX_TWIM_EVT_ADDRESS_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_ANACK;
break;
case NRFX_TWIM_EVT_DATA_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
break;
default:
dev_data->res = NRFX_ERROR_INTERNAL;
break;
}
k_sem_give(&dev_data->completion_sync);
}
static int i2c_nrfx_twim_configure(const struct device *dev,
uint32_t i2c_config)
{
const struct i2c_nrfx_twim_config *dev_config = dev->config;
if (I2C_ADDR_10_BITS & i2c_config) {
return -EINVAL;
}
switch (I2C_SPEED_GET(i2c_config)) {
case I2C_SPEED_STANDARD:
nrf_twim_frequency_set(dev_config->twim.p_twim,
NRF_TWIM_FREQ_100K);
break;
case I2C_SPEED_FAST:
nrf_twim_frequency_set(dev_config->twim.p_twim,
NRF_TWIM_FREQ_400K);
break;
#if NRF_TWIM_HAS_1000_KHZ_FREQ
case I2C_SPEED_FAST_PLUS:
nrf_twim_frequency_set(dev_config->twim.p_twim,
NRF_TWIM_FREQ_1000K);
break;
#endif
default:
LOG_ERR("unsupported speed");
return -EINVAL;
}
return 0;
}
static int i2c_nrfx_twim_recover_bus(const struct device *dev)
{
const struct i2c_nrfx_twim_config *dev_config = dev->config;
enum pm_device_state state;
uint32_t scl_pin;
uint32_t sda_pin;
nrfx_err_t err;
scl_pin = nrf_twim_scl_pin_get(dev_config->twim.p_twim);
sda_pin = nrf_twim_sda_pin_get(dev_config->twim.p_twim);
/* disable peripheral if active (required to release SCL/SDA lines) */
(void)pm_device_state_get(dev, &state);
if (state == PM_DEVICE_STATE_ACTIVE) {
nrfx_twim_disable(&dev_config->twim);
}
err = nrfx_twim_bus_recover(scl_pin, sda_pin);
/* restore peripheral if it was active before */
if (state == PM_DEVICE_STATE_ACTIVE) {
(void)pinctrl_apply_state(dev_config->pcfg,
PINCTRL_STATE_DEFAULT);
nrfx_twim_enable(&dev_config->twim);
}
return (err == NRFX_SUCCESS ? 0 : -EBUSY);
}
static const struct i2c_driver_api i2c_nrfx_twim_driver_api = {
.configure = i2c_nrfx_twim_configure,
.transfer = i2c_nrfx_twim_transfer,
.recover_bus = i2c_nrfx_twim_recover_bus,
};
#ifdef CONFIG_PM_DEVICE
static int twim_nrfx_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct i2c_nrfx_twim_config *dev_config = dev->config;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(dev_config->pcfg,
PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
nrfx_twim_enable(&dev_config->twim);
break;
case PM_DEVICE_ACTION_SUSPEND:
nrfx_twim_disable(&dev_config->twim);
ret = pinctrl_apply_state(dev_config->pcfg,
PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int i2c_nrfx_twim_init(const struct device *dev)
{
const struct i2c_nrfx_twim_config *dev_config = dev->config;
struct i2c_nrfx_twim_data *dev_data = dev->data;
dev_config->irq_connect();
int err = pinctrl_apply_state(dev_config->pcfg,
COND_CODE_1(CONFIG_PM_DEVICE_RUNTIME,
(PINCTRL_STATE_SLEEP),
(PINCTRL_STATE_DEFAULT)));
if (err < 0) {
return err;
}
if (nrfx_twim_init(&dev_config->twim, &dev_config->twim_config,
event_handler, dev_data) != NRFX_SUCCESS) {
LOG_ERR("Failed to initialize device: %s", dev->name);
return -EIO;
}
#ifdef CONFIG_PM_DEVICE_RUNTIME
pm_device_init_suspended(dev);
pm_device_runtime_enable(dev);
#else
nrfx_twim_enable(&dev_config->twim);
#endif
return 0;
}
#define I2C_NRFX_TWIM_INVALID_FREQUENCY ((nrf_twim_frequency_t)-1)
#define I2C_NRFX_TWIM_FREQUENCY(bitrate) \
(bitrate == I2C_BITRATE_STANDARD ? NRF_TWIM_FREQ_100K : \
bitrate == 250000 ? NRF_TWIM_FREQ_250K : \
bitrate == I2C_BITRATE_FAST ? NRF_TWIM_FREQ_400K : \
IF_ENABLED(NRF_TWIM_HAS_1000_KHZ_FREQ, \
(bitrate == I2C_BITRATE_FAST_PLUS ? NRF_TWIM_FREQ_1000K :)) \
I2C_NRFX_TWIM_INVALID_FREQUENCY)
#define I2C(idx) DT_NODELABEL(i2c##idx)
#define I2C_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(I2C(idx), prop)
#define I2C_FREQUENCY(idx) \
I2C_NRFX_TWIM_FREQUENCY(DT_PROP(I2C(idx), clock_frequency))
#define CONCAT_BUF_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_concat_buf_size), \
(DT_PROP(I2C(idx), zephyr_concat_buf_size)), (0))
#define FLASH_BUF_MAX_SIZE(idx) \
COND_CODE_1(DT_NODE_HAS_PROP(I2C(idx), zephyr_flash_buf_max_size), \
(DT_PROP(I2C(idx), zephyr_flash_buf_max_size)), (0))
#define USES_MSG_BUF(idx) \
COND_CODE_0(CONCAT_BUF_SIZE(idx), \
(COND_CODE_0(FLASH_BUF_MAX_SIZE(idx), (0), (1))), \
(1))
#define MSG_BUF_SIZE(idx) MAX(CONCAT_BUF_SIZE(idx), FLASH_BUF_MAX_SIZE(idx))
#define I2C_NRFX_TWIM_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(idx) != \
I2C_NRFX_TWIM_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static void irq_connect##idx(void) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), \
nrfx_isr, nrfx_twim_##idx##_irq_handler, 0); \
} \
IF_ENABLED(USES_MSG_BUF(idx), \
(static uint8_t twim_##idx##_msg_buf[MSG_BUF_SIZE(idx)] \
I2C_MEMORY_SECTION(idx);)) \
static struct i2c_nrfx_twim_data twim_##idx##_data = { \
.transfer_sync = Z_SEM_INITIALIZER( \
twim_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = Z_SEM_INITIALIZER( \
twim_##idx##_data.completion_sync, 0, 1), \
IF_ENABLED(USES_MSG_BUF(idx), \
(.msg_buf = twim_##idx##_msg_buf,)) \
}; \
PINCTRL_DT_DEFINE(I2C(idx)); \
static const struct i2c_nrfx_twim_config twim_##idx##z_config = { \
.twim = NRFX_TWIM_INSTANCE(idx), \
.twim_config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(idx), \
}, \
.msg_buf_size = MSG_BUF_SIZE(idx), \
.irq_connect = irq_connect##idx, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
.max_transfer_size = BIT_MASK( \
DT_PROP(I2C(idx), easydma_maxcnt_bits)), \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twim_nrfx_pm_action); \
I2C_DEVICE_DT_DEFINE(I2C(idx), \
i2c_nrfx_twim_init, \
PM_DEVICE_DT_GET(I2C(idx)), \
&twim_##idx##_data, \
&twim_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twim_driver_api)
#define I2C_MEMORY_SECTION(idx) \
COND_CODE_1(I2C_HAS_PROP(idx, memory_regions), \
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
DT_PHANDLE(I2C(idx), memory_regions)))))), \
())
#ifdef CONFIG_HAS_HW_NRF_TWIM0
I2C_NRFX_TWIM_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM1
I2C_NRFX_TWIM_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM2
I2C_NRFX_TWIM_DEVICE(2);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM3
I2C_NRFX_TWIM_DEVICE(3);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM20
I2C_NRFX_TWIM_DEVICE(20);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM21
I2C_NRFX_TWIM_DEVICE(21);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM22
I2C_NRFX_TWIM_DEVICE(22);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM30
I2C_NRFX_TWIM_DEVICE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM120
I2C_NRFX_TWIM_DEVICE(120);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM130
I2C_NRFX_TWIM_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM131
I2C_NRFX_TWIM_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM132
I2C_NRFX_TWIM_DEVICE(132);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM133
I2C_NRFX_TWIM_DEVICE(133);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM134
I2C_NRFX_TWIM_DEVICE(134);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM135
I2C_NRFX_TWIM_DEVICE(135);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM136
I2C_NRFX_TWIM_DEVICE(136);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWIM137
I2C_NRFX_TWIM_DEVICE(137);
#endif
``` | /content/code_sandbox/drivers/i2c/i2c_nrfx_twim.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,232 |
```unknown
config I2C_ITE_IT8XXX2
bool "ITE IT8XXX2 I2C driver"
default y
depends on DT_HAS_ITE_IT8XXX2_I2C_ENABLED
help
Enable I2C support on it8xxx2_evb.
Supported Speeds: 100kHz, 400kHz and 1MHz.
This driver supports repeated start.
if I2C_ITE_IT8XXX2
config I2C_IT8XXX2_FIFO_MODE
bool "IT8XXX2 I2C FIFO mode"
default y
help
This is an option to enable FIFO mode which can reduce
the time between each byte to improve the I2C bus clock
stretching during I2C transaction.
The I2C controller supports two 32-bytes FIFOs,
FIFO1 supports channel A. FIFO2 supports channel B.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
endif # I2C_ITE_IT8XXX2
config I2C_ITE_ENHANCE
bool "ITE IT8XXX2 I2C enhance driver"
default y
depends on DT_HAS_ITE_ENHANCE_I2C_ENABLED
help
This option can enable the enhance I2C
of IT8XXX2 and support three channels.
if I2C_ITE_ENHANCE
config I2C_IT8XXX2_CQ_MODE
bool "IT8XXX2 I2C command queue mode"
default y
select SOC_IT8XXX2_CPU_IDLE_GATING
help
This is an option to enable command queue mode which can
reduce the time between each byte to improve the I2C bus
clock stretching during I2C transaction.
I2C command queue mode of it8xxx2 can support I2C APIs
including: i2c_write(), i2c_read(), i2c_burst_read.
config I2C_CQ_MODE_MAX_PAYLOAD_SIZE
int "It is allowed to configure the size up to 2K bytes."
range 32 2048
default 64
help
This is the command queue mode payload size which size
up to 2k bytes.
endif # I2C_ITE_ENHANCE
if I2C_TARGET
config I2C_TARGET_IT8XXX2_MAX_BUF_SIZE
int "It is allowed to configure the size up to 2044 bytes."
range 4 2044
default 256
config I2C_TARGET_BUFFER_MODE
default y
endif # I2C_TARGET
``` | /content/code_sandbox/drivers/i2c/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 563 |
```unknown
# Kconfig Andes ATCIIC100 configuration option
#
#
#
config I2C_ANDES_ATCIIC100
bool "Andes ATCIIC100 I2C driver"
default y
depends on DT_HAS_ANDESTECH_ATCIIC100_ENABLED
help
Enable driver for the Andes ATCIIC100 I2C controller.
``` | /content/code_sandbox/drivers/i2c/Kconfig.andes_atciic100 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_i2c
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/i2c.h>
#include <gd32_i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_gd32, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
/* Bus error */
#define I2C_GD32_ERR_BERR BIT(0)
/* Arbitration lost */
#define I2C_GD32_ERR_LARB BIT(1)
/* No ACK received */
#define I2C_GD32_ERR_AERR BIT(2)
/* I2C bus busy */
#define I2C_GD32_ERR_BUSY BIT(4)
struct i2c_gd32_config {
uint32_t reg;
uint32_t bitrate;
uint16_t clkid;
struct reset_dt_spec reset;
const struct pinctrl_dev_config *pcfg;
void (*irq_cfg_func)(void);
};
struct i2c_gd32_data {
struct k_sem bus_mutex;
struct k_sem sync_sem;
uint32_t dev_config;
uint16_t addr1;
uint16_t addr2;
uint32_t xfer_len;
struct i2c_msg *current;
uint8_t errs;
bool is_restart;
};
static inline void i2c_gd32_enable_interrupts(const struct i2c_gd32_config *cfg)
{
I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE;
I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE;
I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE;
}
static inline void i2c_gd32_disable_interrupts(const struct i2c_gd32_config *cfg)
{
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE;
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE;
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
}
static inline void i2c_gd32_xfer_read(struct i2c_gd32_data *data,
const struct i2c_gd32_config *cfg)
{
data->current->len--;
*data->current->buf = I2C_DATA(cfg->reg);
data->current->buf++;
if ((data->xfer_len > 0U) &&
(data->current->len == 0U)) {
data->current++;
}
}
static inline void i2c_gd32_xfer_write(struct i2c_gd32_data *data,
const struct i2c_gd32_config *cfg)
{
data->current->len--;
I2C_DATA(cfg->reg) = *data->current->buf;
data->current->buf++;
if ((data->xfer_len > 0U) &&
(data->current->len == 0U)) {
data->current++;
}
}
static void i2c_gd32_handle_rbne(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
switch (data->xfer_len) {
case 0:
/* Unwanted data received, ignore it. */
k_sem_give(&data->sync_sem);
break;
case 1:
/* If total_read_length == 1, read the data directly. */
data->xfer_len--;
i2c_gd32_xfer_read(data, cfg);
k_sem_give(&data->sync_sem);
break;
case 2:
__fallthrough;
case 3:
/*
* If total_read_length == 2, or total_read_length > 3
* and remaining_read_length == 3, disable the RBNE
* interrupt.
* Remaining data will be read from BTC interrupt.
*/
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
break;
default:
/*
* If total_read_length > 3 and remaining_read_length > 3,
* read the data directly.
*/
data->xfer_len--;
i2c_gd32_xfer_read(data, cfg);
break;
}
}
static void i2c_gd32_handle_tbe(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
if (data->xfer_len > 0U) {
data->xfer_len--;
if (data->xfer_len == 0U) {
/*
* This is the last data to transmit, disable the TBE interrupt.
* Use the BTC interrupt to indicate the write data complete state.
*/
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
}
i2c_gd32_xfer_write(data, cfg);
} else {
/* Enter stop condition */
I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
k_sem_give(&data->sync_sem);
}
}
static void i2c_gd32_handle_btc(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
if (data->current->flags & I2C_MSG_READ) {
uint32_t counter = 0U;
switch (data->xfer_len) {
case 2:
/* Stop condition must be generated before reading the last two bytes. */
I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
for (counter = 2U; counter > 0; counter--) {
data->xfer_len--;
i2c_gd32_xfer_read(data, cfg);
}
k_sem_give(&data->sync_sem);
break;
case 3:
/* Clear ACKEN bit */
I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
data->xfer_len--;
i2c_gd32_xfer_read(data, cfg);
break;
default:
i2c_gd32_handle_rbne(dev);
break;
}
} else {
i2c_gd32_handle_tbe(dev);
}
}
static void i2c_gd32_handle_addsend(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len <= 2U)) {
I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
}
/* Clear ADDSEND bit */
I2C_STAT0(cfg->reg);
I2C_STAT1(cfg->reg);
if (data->is_restart) {
data->is_restart = false;
data->current->flags &= ~I2C_MSG_RW_MASK;
data->current->flags |= I2C_MSG_READ;
/* Enter repeated start condition */
I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
return;
}
if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len == 1U)) {
/* Enter stop condition */
I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
}
}
static void i2c_gd32_event_isr(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
uint32_t stat;
stat = I2C_STAT0(cfg->reg);
if (stat & I2C_STAT0_SBSEND) {
if (data->current->flags & I2C_MSG_READ) {
I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 1U;
} else {
I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 0U;
}
} else if (stat & I2C_STAT0_ADD10SEND) {
I2C_DATA(cfg->reg) = data->addr2;
} else if (stat & I2C_STAT0_ADDSEND) {
i2c_gd32_handle_addsend(dev);
/*
* Must handle BTC first.
* For I2C_STAT0, BTC is the superset of RBNE and TBE.
*/
} else if (stat & I2C_STAT0_BTC) {
i2c_gd32_handle_btc(dev);
} else if (stat & I2C_STAT0_RBNE) {
i2c_gd32_handle_rbne(dev);
} else if (stat & I2C_STAT0_TBE) {
i2c_gd32_handle_tbe(dev);
}
}
static void i2c_gd32_error_isr(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
uint32_t stat;
stat = I2C_STAT0(cfg->reg);
if (stat & I2C_STAT0_BERR) {
I2C_STAT0(cfg->reg) &= ~I2C_STAT0_BERR;
data->errs |= I2C_GD32_ERR_BERR;
}
if (stat & I2C_STAT0_LOSTARB) {
I2C_STAT0(cfg->reg) &= ~I2C_STAT0_LOSTARB;
data->errs |= I2C_GD32_ERR_LARB;
}
if (stat & I2C_STAT0_AERR) {
I2C_STAT0(cfg->reg) &= ~I2C_STAT0_AERR;
data->errs |= I2C_GD32_ERR_AERR;
}
if (data->errs != 0U) {
/* Enter stop condition */
I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
k_sem_give(&data->sync_sem);
}
}
static void i2c_gd32_log_err(struct i2c_gd32_data *data)
{
if (data->errs & I2C_GD32_ERR_BERR) {
LOG_ERR("Bus error");
}
if (data->errs & I2C_GD32_ERR_LARB) {
LOG_ERR("Arbitration lost");
}
if (data->errs & I2C_GD32_ERR_AERR) {
LOG_ERR("No ACK received");
}
if (data->errs & I2C_GD32_ERR_BUSY) {
LOG_ERR("I2C bus busy");
}
}
static void i2c_gd32_xfer_begin(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
k_sem_reset(&data->sync_sem);
data->errs = 0U;
data->is_restart = false;
/* Default to set ACKEN bit. */
I2C_CTL0(cfg->reg) |= I2C_CTL0_ACKEN;
if (data->current->flags & I2C_MSG_READ) {
/* For 2 bytes read, use POAP bit to give NACK for the last data receiving. */
if (data->xfer_len == 2U) {
I2C_CTL0(cfg->reg) |= I2C_CTL0_POAP;
}
/*
* For read on 10 bits address mode, start condition will happen twice.
* Transfer sequence as below:
* S addr1+W addr2 S addr1+R
* Use a is_restart flag to cover this case.
*/
if (data->dev_config & I2C_ADDR_10_BITS) {
data->is_restart = true;
data->current->flags &= ~I2C_MSG_RW_MASK;
}
}
i2c_gd32_enable_interrupts(cfg);
/* Enter repeated start condition */
I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
}
static int i2c_gd32_xfer_end(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
i2c_gd32_disable_interrupts(cfg);
/* Wait for stop condition is done. */
while (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
/* NOP */
}
if (data->errs) {
return -EIO;
}
return 0;
}
static int i2c_gd32_msg_read(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
data->errs = I2C_GD32_ERR_BUSY;
return -EBUSY;
}
i2c_gd32_xfer_begin(dev);
k_sem_take(&data->sync_sem, K_FOREVER);
return i2c_gd32_xfer_end(dev);
}
static int i2c_gd32_msg_write(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
data->errs = I2C_GD32_ERR_BUSY;
return -EBUSY;
}
i2c_gd32_xfer_begin(dev);
k_sem_take(&data->sync_sem, K_FOREVER);
return i2c_gd32_xfer_end(dev);
}
static int i2c_gd32_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs,
uint16_t addr)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
struct i2c_msg *current, *next;
uint8_t itr;
int err = 0;
current = msgs;
/* First message flags implicitly contain I2C_MSG_RESTART flag. */
current->flags |= I2C_MSG_RESTART;
for (uint8_t i = 1; i <= num_msgs; i++) {
if (i < num_msgs) {
next = current + 1;
/*
* If there have a R/W transfer state change between messages,
* An explicit I2C_MSG_RESTART flag is needed for the second message.
*/
if ((current->flags & I2C_MSG_RW_MASK) !=
(next->flags & I2C_MSG_RW_MASK)) {
if ((next->flags & I2C_MSG_RESTART) == 0U) {
return -EINVAL;
}
}
/* Only the last message need I2C_MSG_STOP flag to free the Bus. */
if (current->flags & I2C_MSG_STOP) {
return -EINVAL;
}
}
if ((current->buf == NULL) ||
(current->len == 0U)) {
return -EINVAL;
}
current++;
}
k_sem_take(&data->bus_mutex, K_FOREVER);
/* Enable i2c device */
I2C_CTL0(cfg->reg) |= I2C_CTL0_I2CEN;
if (data->dev_config & I2C_ADDR_10_BITS) {
data->addr1 = 0xF0 | ((addr & BITS(8, 9)) >> 8U);
data->addr2 = addr & BITS(0, 7);
} else {
data->addr1 = addr & BITS(0, 6);
}
for (uint8_t i = 0; i < num_msgs; i = itr) {
data->current = &msgs[i];
data->xfer_len = msgs[i].len;
for (itr = i + 1; itr < num_msgs; itr++) {
if ((data->current->flags & I2C_MSG_RW_MASK) !=
(msgs[itr].flags & I2C_MSG_RW_MASK)) {
break;
}
data->xfer_len += msgs[itr].len;
}
if (data->current->flags & I2C_MSG_READ) {
err = i2c_gd32_msg_read(dev);
} else {
err = i2c_gd32_msg_write(dev);
}
if (err < 0) {
i2c_gd32_log_err(data);
break;
}
}
/* Disable I2C device */
I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
k_sem_give(&data->bus_mutex);
return err;
}
static int i2c_gd32_configure(const struct device *dev,
uint32_t dev_config)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
uint32_t pclk1, freq, clkc;
int err = 0;
k_sem_take(&data->bus_mutex, K_FOREVER);
/* Disable I2C device */
I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&cfg->clkid,
&pclk1);
/* i2c clock frequency, us */
freq = pclk1 / 1000000U;
if (freq > I2CCLK_MAX) {
LOG_ERR("I2C max clock freq %u, current is %u\n",
I2CCLK_MAX, freq);
err = -ENOTSUP;
goto error;
}
/*
* Refer from SoC user manual.
* In standard mode:
* T_high = CLKC * T_pclk1
* T_low = CLKC * T_pclk1
*
* In fast mode and fast mode plus with DTCY=1:
* T_high = 9 * CLKC * T_pclk1
* T_low = 16 * CLKC * T_pclk1
*
* T_pclk1 is reciprocal of pclk1:
* T_pclk1 = 1 / pclk1
*
* T_high and T_low construct the bit transfer:
* T_high + T_low = 1 / bitrate
*
* And then, we can get the CLKC equation.
* Standard mode:
* CLKC = pclk1 / (bitrate * 2)
* Fast mode and fast mode plus:
* CLKC = pclk1 / (bitrate * 25)
*
* Variable list:
* T_high: high period of the SCL clock
* T_low: low period of the SCL clock
* T_pclk1: duration of single pclk1 pulse
* pclk1: i2c device clock frequency
* bitrate: 100 Kbits for standard mode
*/
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
if (freq < I2CCLK_MIN) {
LOG_ERR("I2C standard-mode min clock freq %u, current is %u\n",
I2CCLK_MIN, freq);
err = -ENOTSUP;
goto error;
}
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_I2CCLK;
I2C_CTL1(cfg->reg) |= freq;
/* Standard-mode risetime maximum value: 1000ns */
if (freq == I2CCLK_MAX) {
I2C_RT(cfg->reg) = I2CCLK_MAX;
} else {
I2C_RT(cfg->reg) = freq + 1U;
}
/* CLKC = pclk1 / (bitrate * 2) */
clkc = pclk1 / (I2C_BITRATE_STANDARD * 2U);
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
I2C_CKCFG(cfg->reg) |= clkc;
/* standard-mode */
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_FAST;
break;
case I2C_SPEED_FAST:
if (freq < I2CCLK_FM_MIN) {
LOG_ERR("I2C fast-mode min clock freq %u, current is %u\n",
I2CCLK_FM_MIN, freq);
err = -ENOTSUP;
goto error;
}
/* Fast-mode risetime maximum value: 300ns */
I2C_RT(cfg->reg) = freq * 300U / 1000U + 1U;
/* CLKC = pclk1 / (bitrate * 25) */
clkc = pclk1 / (I2C_BITRATE_FAST * 25U);
if (clkc == 0U) {
clkc = 1U;
}
/* Default DCTY to 1 */
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
I2C_CKCFG(cfg->reg) |= clkc;
/* Transfer mode: fast-mode */
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
#ifdef I2C_FMPCFG
/* Disable transfer mode: fast-mode plus */
I2C_FMPCFG(cfg->reg) &= ~I2C_FMPCFG_FMPEN;
#endif /* I2C_FMPCFG */
break;
#ifdef I2C_FMPCFG
case I2C_SPEED_FAST_PLUS:
if (freq < I2CCLK_FM_PLUS_MIN) {
LOG_ERR("I2C fast-mode plus min clock freq %u, current is %u\n",
I2CCLK_FM_PLUS_MIN, freq);
err = -ENOTSUP;
goto error;
}
/* Fast-mode plus risetime maximum value: 120ns */
I2C_RT(cfg->reg) = freq * 120U / 1000U + 1U;
/* CLKC = pclk1 / (bitrate * 25) */
clkc = pclk1 / (I2C_BITRATE_FAST_PLUS * 25U);
if (clkc == 0U) {
clkc = 1U;
}
/* Default DCTY to 1 */
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
I2C_CKCFG(cfg->reg) |= clkc;
/* Transfer mode: fast-mode */
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
/* Enable transfer mode: fast-mode plus */
I2C_FMPCFG(cfg->reg) |= I2C_FMPCFG_FMPEN;
break;
#endif /* I2C_FMPCFG */
default:
err = -EINVAL;
goto error;
}
data->dev_config = dev_config;
error:
k_sem_give(&data->bus_mutex);
return err;
}
static const struct i2c_driver_api i2c_gd32_driver_api = {
.configure = i2c_gd32_configure,
.transfer = i2c_gd32_transfer,
};
static int i2c_gd32_init(const struct device *dev)
{
struct i2c_gd32_data *data = dev->data;
const struct i2c_gd32_config *cfg = dev->config;
uint32_t bitrate_cfg;
int err;
err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
return err;
}
/* Mutex semaphore to protect the i2c api in multi-thread env. */
k_sem_init(&data->bus_mutex, 1, 1);
/* Sync semaphore to sync i2c state between isr and transfer api. */
k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);
cfg->irq_cfg_func();
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
i2c_gd32_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
return 0;
}
#define I2C_GD32_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
static void i2c_gd32_irq_cfg_func_##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, event, irq), \
DT_INST_IRQ_BY_NAME(inst, event, priority), \
i2c_gd32_event_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQ_BY_NAME(inst, event, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, error, irq), \
DT_INST_IRQ_BY_NAME(inst, error, priority), \
i2c_gd32_error_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQ_BY_NAME(inst, error, irq)); \
} \
static struct i2c_gd32_data i2c_gd32_data_##inst; \
const static struct i2c_gd32_config i2c_gd32_cfg_##inst = { \
.reg = DT_INST_REG_ADDR(inst), \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
.clkid = DT_INST_CLOCKS_CELL(inst, id), \
.reset = RESET_DT_SPEC_INST_GET(inst), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.irq_cfg_func = i2c_gd32_irq_cfg_func_##inst, \
}; \
I2C_DEVICE_DT_INST_DEFINE(inst, \
i2c_gd32_init, NULL, \
&i2c_gd32_data_##inst, &i2c_gd32_cfg_##inst, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_gd32_driver_api); \
DT_INST_FOREACH_STATUS_OKAY(I2C_GD32_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,056 |
```objective-c
/* dw_i2c.h - header for Design Ware I2C operations */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_H_
#define ZEPHYR_DRIVERS_I2C_I2C_DW_H_
#include <zephyr/drivers/i2c.h>
#include <stdbool.h>
#define DT_DRV_COMPAT snps_designware_i2c
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE");
#include <zephyr/drivers/pcie/pcie.h>
#endif
#if defined(CONFIG_RESET)
#include <zephyr/drivers/reset.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_DW_MAGIC_KEY 0x44570140
typedef void (*i2c_isr_cb_t)(const struct device *port);
#define IC_ACTIVITY (1 << 0)
#define IC_ENABLE_BIT (1 << 0)
/* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */
#define I2C_DW_STATE_READY (0)
#define I2C_DW_CMD_SEND (1 << 0)
#define I2C_DW_CMD_RECV (1 << 1)
#define I2C_DW_CMD_ERROR (1 << 2)
#define I2C_DW_BUSY (1 << 3)
#define DW_ENABLE_TX_INT_I2C_MASTER (DW_INTR_STAT_TX_OVER | \
DW_INTR_STAT_TX_EMPTY | \
DW_INTR_STAT_TX_ABRT | \
DW_INTR_STAT_STOP_DET)
#define DW_ENABLE_RX_INT_I2C_MASTER (DW_INTR_STAT_RX_UNDER | \
DW_INTR_STAT_RX_OVER | \
DW_INTR_STAT_RX_FULL | \
DW_INTR_STAT_STOP_DET)
#define DW_ENABLE_TX_INT_I2C_SLAVE (DW_INTR_STAT_RD_REQ | \
DW_INTR_STAT_TX_ABRT | \
DW_INTR_STAT_STOP_DET)
#define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | \
DW_INTR_STAT_STOP_DET)
#define DW_DISABLE_ALL_I2C_INT 0x00000000
/* IC_CON Low count and high count default values */
/* TODO verify values for high and fast speed */
#define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4)
#define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5)
#define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8)
#define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8)
#define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8)
#define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8)
/*
* DesignWare speed values don't directly translate from the Zephyr speed
* selections in include/i2c.h so here we do a little translation
*/
#define I2C_DW_SPEED_STANDARD 0x1
#define I2C_DW_SPEED_FAST 0x2
#define I2C_DW_SPEED_FAST_PLUS 0x2
#define I2C_DW_SPEED_HIGH 0x3
/*
* These values have been randomly selected. It would be good to test different
* watermark levels for performance capabilities
*/
#define I2C_DW_TX_WATERMARK 2
#define I2C_DW_RX_WATERMARK 7
struct i2c_dw_rom_config {
DEVICE_MMIO_ROM;
i2c_isr_cb_t config_func;
uint32_t bitrate;
#if defined(CONFIG_PINCTRL)
const struct pinctrl_dev_config *pcfg;
#endif
#if defined(CONFIG_RESET)
const struct reset_dt_spec reset;
#endif
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
struct pcie_dev *pcie;
#endif /* I2C_DW_PCIE_ENABLED */
#ifdef CONFIG_I2C_DW_LPSS_DMA
const struct device *dma_dev;
#endif
};
struct i2c_dw_dev_config {
DEVICE_MMIO_RAM;
struct k_sem device_sync_sem;
struct k_mutex bus_mutex;
uint32_t app_config;
uint8_t *xfr_buf;
uint32_t xfr_len;
uint32_t rx_pending;
uint16_t hcnt;
uint16_t lcnt;
volatile uint8_t state; /* last direction of transfer */
uint8_t request_bytes;
uint8_t xfr_flags;
bool support_hs_mode;
#ifdef CONFIG_I2C_DW_LPSS_DMA
uintptr_t phy_addr;
uintptr_t base_addr;
/* For dma transfer */
bool xfr_status;
#endif
struct i2c_target_config *slave_cfg;
};
#define Z_REG_READ(__sz) sys_read##__sz
#define Z_REG_WRITE(__sz) sys_write##__sz
#define Z_REG_SET_BIT sys_set_bit
#define Z_REG_CLEAR_BIT sys_clear_bit
#define Z_REG_TEST_BIT sys_test_bit
#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
static inline uint32_t read_##__reg(uint32_t addr) \
{ \
return Z_REG_READ(__sz)(addr + __off); \
}
#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
static inline void write_##__reg(uint32_t data, uint32_t addr) \
{ \
Z_REG_WRITE(__sz)(data, addr + __off); \
}
#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void set_bit_##__reg_bit(uint32_t addr) \
{ \
Z_REG_SET_BIT(addr + __reg_off, __bit); \
}
#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void clear_bit_##__reg_bit(uint32_t addr) \
{ \
Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \
}
#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline int test_bit_##__reg_bit(uint32_t addr) \
{ \
return Z_REG_TEST_BIT(addr + __reg_off, __bit); \
}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_dw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,420 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_i2c
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_cc13xx_cc26xx);
#include <driverlib/i2c.h>
#include <driverlib/prcm.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26X2.h>
#include <zephyr/irq.h>
#include "i2c-priv.h"
struct i2c_cc13xx_cc26xx_data {
struct k_sem lock;
struct k_sem complete;
volatile uint32_t error;
#ifdef CONFIG_PM
Power_NotifyObj postNotify;
uint32_t dev_config;
#endif
};
struct i2c_cc13xx_cc26xx_config {
uint32_t base;
const struct pinctrl_dev_config *pcfg;
};
static int i2c_cc13xx_cc26xx_transmit(const struct device *dev,
const uint8_t *buf,
uint32_t len, uint16_t addr)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
const uint32_t base = config->base;
struct i2c_cc13xx_cc26xx_data *data = dev->data;
/* Sending address without data is not supported */
if (len == 0) {
return -EIO;
}
I2CMasterSlaveAddrSet(base, addr, false);
/* The following assumes a single master. Use I2CMasterBusBusy() if
* wanting to implement multiple master support.
*/
/* Single transmission */
if (len == 1) {
I2CMasterDataPut(base, *buf);
I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_SEND);
k_sem_take(&data->complete, K_FOREVER);
return data->error == I2C_MASTER_ERR_NONE ? 0 : -EIO;
}
/* Burst transmission */
I2CMasterDataPut(base, buf[0]);
I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
goto send_error_stop;
}
for (int i = 1; i < len - 1; i++) {
I2CMasterDataPut(base, buf[i]);
I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_CONT);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
goto send_error_stop;
}
}
I2CMasterDataPut(base, buf[len - 1]);
I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_FINISH);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
return -EIO;
}
return 0;
send_error_stop:
I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
return -EIO;
}
static int i2c_cc13xx_cc26xx_receive(const struct device *dev, uint8_t *buf,
uint32_t len,
uint16_t addr)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
const uint32_t base = config->base;
struct i2c_cc13xx_cc26xx_data *data = dev->data;
/* Sending address without data is not supported */
if (len == 0) {
return -EIO;
}
I2CMasterSlaveAddrSet(base, addr, true);
/* The following assumes a single master. Use I2CMasterBusBusy() if
* wanting to implement multiple master support.
*/
/* Single receive */
if (len == 1) {
I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_RECEIVE);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
return -EIO;
}
*buf = I2CMasterDataGet(base);
return 0;
}
/* Burst receive */
I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_START);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
goto recv_error_stop;
}
buf[0] = I2CMasterDataGet(base);
for (int i = 1; i < len - 1; i++) {
I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
goto recv_error_stop;
}
buf[i] = I2CMasterDataGet(base);
}
I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
k_sem_take(&data->complete, K_FOREVER);
if (data->error != I2C_MASTER_ERR_NONE) {
return -EIO;
}
buf[len - 1] = I2CMasterDataGet(base);
return 0;
recv_error_stop:
I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP);
return -EIO;
}
static int i2c_cc13xx_cc26xx_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_cc13xx_cc26xx_data *data = dev->data;
int ret = 0;
if (num_msgs == 0) {
return 0;
}
k_sem_take(&data->lock, K_FOREVER);
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
for (int i = 0; i < num_msgs; i++) {
/* Not supported by hardware */
if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
ret = -EIO;
break;
}
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = i2c_cc13xx_cc26xx_transmit(dev, msgs[i].buf,
msgs[i].len, addr);
} else {
ret = i2c_cc13xx_cc26xx_receive(dev, msgs[i].buf,
msgs[i].len, addr);
}
if (ret) {
break;
}
}
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
k_sem_give(&data->lock);
return ret;
}
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
static int i2c_cc13xx_cc26xx_configure(const struct device *dev,
uint32_t dev_config)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
bool fast;
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
fast = false;
break;
case I2C_SPEED_FAST:
fast = true;
break;
default:
LOG_ERR("Unsupported speed");
return -EIO;
}
/* Support for slave mode has not been implemented */
if (!(dev_config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Slave mode is not supported");
return -EIO;
}
/* This is deprecated and could be ignored in the future */
if (dev_config & I2C_ADDR_10_BITS) {
LOG_ERR("10-bit addressing mode is not supported");
return -EIO;
}
/* Enables and configures I2C master */
I2CMasterInitExpClk(config->base, CPU_FREQ, fast);
#ifdef CONFIG_PM
struct i2c_cc13xx_cc26xx_data *data = dev->data;
data->dev_config = dev_config;
#endif
return 0;
}
static void i2c_cc13xx_cc26xx_isr(const struct device *dev)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
struct i2c_cc13xx_cc26xx_data *data = dev->data;
const uint32_t base = config->base;
if (I2CMasterIntStatus(base, true)) {
I2CMasterIntClear(base);
data->error = I2CMasterErr(base);
k_sem_give(&data->complete);
}
}
#ifdef CONFIG_PM
/*
* ======== postNotifyFxn ========
* Called by Power module when waking up the CPU from Standby. The i2c needs
* to be reconfigured afterwards, unless Zephyr's device PM turned it off, in
* which case it'd be responsible for turning it back on and reconfigure it.
*/
static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg,
uintptr_t clientArg)
{
const struct device *dev = (const struct device *)clientArg;
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
struct i2c_cc13xx_cc26xx_data *data = dev->data;
int ret = Power_NOTIFYDONE;
int16_t res_id;
/* Reconfigure the hardware if returning from sleep */
if (eventType == PowerCC26XX_AWAKE_STANDBY) {
res_id = PowerCC26XX_PERIPH_I2C0;
if (Power_getDependencyCount(res_id) != 0) {
/* Reconfigure and enable I2C only if powered */
if (i2c_cc13xx_cc26xx_configure(dev,
data->dev_config) != 0) {
ret = Power_NOTIFYERROR;
}
I2CMasterIntEnable(config->base);
}
}
return (ret);
}
#endif
#ifdef CONFIG_PM_DEVICE
static int i2c_cc13xx_cc26xx_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
struct i2c_cc13xx_cc26xx_data *data = dev->data;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
Power_setDependency(PowerCC26XX_PERIPH_I2C0);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
ret = i2c_cc13xx_cc26xx_configure(dev, data->dev_config);
if (ret == 0) {
I2CMasterIntEnable(config->base);
}
break;
case PM_DEVICE_ACTION_SUSPEND:
I2CMasterIntDisable(config->base);
I2CMasterDisable(config->base);
/* Reset pin type to default GPIO configuration */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
Power_releaseDependency(PowerCC26XX_PERIPH_I2C0);
break;
default:
return -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int i2c_cc13xx_cc26xx_init(const struct device *dev)
{
const struct i2c_cc13xx_cc26xx_config *config = dev->config;
uint32_t cfg;
int err;
#ifdef CONFIG_PM
struct i2c_cc13xx_cc26xx_data *data = dev->data;
/* Set Power dependencies & constraints */
Power_setDependency(PowerCC26XX_PERIPH_I2C0);
/* Register notification function */
Power_registerNotify(&data->postNotify,
PowerCC26XX_AWAKE_STANDBY,
postNotifyFxn, (uintptr_t)dev);
#else
/* Enable I2C power domain */
PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL);
/* Enable I2C peripheral clock */
PRCMPeripheralRunEnable(PRCM_PERIPH_I2C0);
/* Enable in sleep mode until proper power management is added */
PRCMPeripheralSleepEnable(PRCM_PERIPH_I2C0);
PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_I2C0);
/* Load PRCM settings */
PRCMLoadSet();
while (!PRCMLoadGet()) {
continue;
}
/* I2C should not be accessed until power domain is on. */
while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_SERIAL) !=
PRCM_DOMAIN_POWER_ON) {
continue;
}
#endif
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
i2c_cc13xx_cc26xx_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
LOG_ERR("Failed to configure pinctrl state");
return err;
}
cfg = i2c_map_dt_bitrate(DT_INST_PROP(0, clock_frequency));
err = i2c_cc13xx_cc26xx_configure(dev, cfg | I2C_MODE_CONTROLLER);
if (err) {
LOG_ERR("Failed to configure");
return err;
}
I2CMasterIntEnable(config->base);
return 0;
}
static const struct i2c_driver_api i2c_cc13xx_cc26xx_driver_api = {
.configure = i2c_cc13xx_cc26xx_configure,
.transfer = i2c_cc13xx_cc26xx_transfer
};
PINCTRL_DT_INST_DEFINE(0);
static const struct i2c_cc13xx_cc26xx_config i2c_cc13xx_cc26xx_config = {
.base = DT_INST_REG_ADDR(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct i2c_cc13xx_cc26xx_data i2c_cc13xx_cc26xx_data = {
.lock = Z_SEM_INITIALIZER(i2c_cc13xx_cc26xx_data.lock, 1, 1),
.complete = Z_SEM_INITIALIZER(i2c_cc13xx_cc26xx_data.complete, 0, 1),
.error = I2C_MASTER_ERR_NONE
};
PM_DEVICE_DT_INST_DEFINE(0, i2c_cc13xx_cc26xx_pm_action);
I2C_DEVICE_DT_INST_DEFINE(0,
i2c_cc13xx_cc26xx_init,
PM_DEVICE_DT_INST_GET(0),
&i2c_cc13xx_cc26xx_data, &i2c_cc13xx_cc26xx_config,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_cc13xx_cc26xx_driver_api);
``` | /content/code_sandbox/drivers/i2c/i2c_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,281 |
```c
/* dw_i2c.c - I2C file for Design Ware */
/*
*
*/
#include <stddef.h>
#include <zephyr/types.h>
#include <stdlib.h>
#include <stdbool.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/pm/device.h>
#include <zephyr/arch/cpu.h>
#include <string.h>
#if defined(CONFIG_PINCTRL)
#include <zephyr/drivers/pinctrl.h>
#endif
#if defined(CONFIG_RESET)
#include <zephyr/drivers/reset.h>
#endif
#include <errno.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/util.h>
#if defined(CONFIG_I2C_DW_LPSS_DMA)
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_intel_lpss.h>
#endif
#ifdef CONFIG_IOAPIC
#include <zephyr/drivers/interrupt_controller/ioapic.h>
#endif
#include "i2c_dw.h"
#include "i2c_dw_registers.h"
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_dw);
#include "i2c-priv.h"
static inline uint32_t get_regs(const struct device *dev)
{
return (uint32_t)DEVICE_MMIO_GET(dev);
}
#ifdef CONFIG_I2C_DW_LPSS_DMA
void i2c_dw_enable_idma(const struct device *dev, bool enable)
{
uint32_t reg;
uint32_t reg_base = get_regs(dev);
if (enable) {
write_dma_cr(DW_IC_DMA_ENABLE, reg_base);
reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
} else {
reg = read_dma_cr(reg_base);
reg &= ~DW_IC_DMA_ENABLE;
write_dma_cr(reg, reg_base);
reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
}
}
void cb_i2c_idma_transfer(const struct device *dma, void *user_data,
uint32_t channel, int status)
{
const struct device *dev = (const struct device *)user_data;
const struct i2c_dw_rom_config * const rom = dev->config;
struct i2c_dw_dev_config *const dw = dev->data;
dma_stop(rom->dma_dev, channel);
i2c_dw_enable_idma(dev, false);
if (status) {
dw->xfr_status = true;
} else {
dw->xfr_status = false;
}
}
void i2c_dw_set_fifo_th(const struct device *dev, uint8_t fifo_depth)
{
uint32_t reg_base = get_regs(dev);
write_tdlr(fifo_depth, reg_base);
write_rdlr(fifo_depth - 1, reg_base);
}
inline void *i2c_dw_dr_phy_addr(const struct device *dev)
{
struct i2c_dw_dev_config *const dw = dev->data;
return (void *) (dw->phy_addr + DW_IC_REG_DATA_CMD);
}
int32_t i2c_dw_idma_rx_transfer(const struct device *dev)
{
struct i2c_dw_dev_config *const dw = dev->data;
const struct i2c_dw_rom_config * const rom = dev->config;
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_block_cfg = { 0 };
if (!device_is_ready(rom->dma_dev)) {
LOG_DBG("DMA device is not ready");
return -ENODEV;
}
dma_cfg.dma_slot = 1U;
dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
dma_cfg.source_data_size = 1U;
dma_cfg.dest_data_size = 1U;
dma_cfg.source_burst_length = 1U;
dma_cfg.dest_burst_length = 1U;
dma_cfg.dma_callback = cb_i2c_idma_transfer;
dma_cfg.user_data = (void *)dev;
dma_cfg.complete_callback_en = 0U;
dma_cfg.error_callback_dis = 0U;
dma_cfg.block_count = 1U;
dma_cfg.head_block = &dma_block_cfg;
dma_block_cfg.block_size = dw->xfr_len;
dma_block_cfg.dest_address = (uint64_t)&dw->xfr_buf[0];
dma_block_cfg.source_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
dw->xfr_status = false;
if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN, &dma_cfg)) {
LOG_DBG("Error transfer");
return -EIO;
}
if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN)) {
LOG_DBG("Error transfer");
return -EIO;
}
i2c_dw_enable_idma(dev, true);
i2c_dw_set_fifo_th(dev, 1);
return 0;
}
int32_t i2c_dw_idma_tx_transfer(const struct device *dev,
uint64_t data)
{
const struct i2c_dw_rom_config * const rom = dev->config;
struct i2c_dw_dev_config *const dw = dev->data;
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_block_cfg = { 0 };
if (!device_is_ready(rom->dma_dev)) {
LOG_DBG("DMA device is not ready");
return -ENODEV;
}
dma_cfg.dma_slot = 0U;
dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
dma_cfg.source_data_size = 1U;
dma_cfg.dest_data_size = 1U;
dma_cfg.source_burst_length = 1U;
dma_cfg.dest_burst_length = 1U;
dma_cfg.dma_callback = cb_i2c_idma_transfer;
dma_cfg.user_data = (void *)dev;
dma_cfg.complete_callback_en = 0U;
dma_cfg.error_callback_dis = 0U;
dma_cfg.block_count = 1U;
dma_cfg.head_block = &dma_block_cfg;
dma_block_cfg.block_size = 1;
dma_block_cfg.source_address = (uint64_t)&data;
dma_block_cfg.dest_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
dw->xfr_status = false;
if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN, &dma_cfg)) {
LOG_DBG("Error transfer");
return -EIO;
}
if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN)) {
LOG_DBG("Error transfer");
return -EIO;
}
i2c_dw_enable_idma(dev, true);
i2c_dw_set_fifo_th(dev, 1);
return 0;
}
#endif
static inline void i2c_dw_data_ask(const struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t data;
int tx_empty;
int rx_empty;
int cnt;
int rx_buffer_depth, tx_buffer_depth;
union ic_comp_param_1_register ic_comp_param_1;
uint32_t reg_base = get_regs(dev);
/* No more bytes to request, so command queue is no longer needed */
if (dw->request_bytes == 0U) {
clear_bit_intr_mask_tx_empty(reg_base);
return;
}
/* Get the FIFO depth that could be from 2 to 256 from HW spec */
ic_comp_param_1.raw = read_comp_param_1(reg_base);
rx_buffer_depth = ic_comp_param_1.bits.rx_buffer_depth + 1;
tx_buffer_depth = ic_comp_param_1.bits.tx_buffer_depth + 1;
/* How many bytes we can actually ask */
rx_empty = (rx_buffer_depth - read_rxflr(reg_base)) - dw->rx_pending;
if (rx_empty < 0) {
/* RX FIFO expected to be full.
* So don't request any bytes, yet.
*/
return;
}
/* How many empty slots in TX FIFO (as command queue) */
tx_empty = tx_buffer_depth - read_txflr(reg_base);
/* Figure out how many bytes we can request */
cnt = MIN(rx_buffer_depth, dw->request_bytes);
cnt = MIN(MIN(tx_empty, rx_empty), cnt);
while (cnt > 0) {
/* Tell controller to get another byte */
data = IC_DATA_CMD_CMD;
/* Send RESTART if needed */
if (dw->xfr_flags & I2C_MSG_RESTART) {
data |= IC_DATA_CMD_RESTART;
dw->xfr_flags &= ~(I2C_MSG_RESTART);
}
/* After receiving the last byte, send STOP if needed */
if ((dw->xfr_flags & I2C_MSG_STOP)
&& (dw->request_bytes == 1U)) {
data |= IC_DATA_CMD_STOP;
}
#ifdef CONFIG_I2C_TARGET
clear_bit_intr_mask_tx_empty(reg_base);
#endif /* CONFIG_I2C_TARGET */
write_cmd_data(data, reg_base);
dw->rx_pending++;
dw->request_bytes--;
cnt--;
}
}
static void i2c_dw_data_read(const struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t reg_base = get_regs(dev);
#ifdef CONFIG_I2C_DW_LPSS_DMA
if (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
i2c_dw_idma_rx_transfer(dev);
dw->xfr_len = 0;
dw->rx_pending = 0;
}
#else
while (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
dw->xfr_buf[0] = (uint8_t)read_cmd_data(reg_base);
dw->xfr_buf++;
dw->xfr_len--;
dw->rx_pending--;
if (dw->xfr_len == 0U) {
break;
}
}
#endif
/* Nothing to receive anymore */
if (dw->xfr_len == 0U) {
dw->state &= ~I2C_DW_CMD_RECV;
return;
}
}
static int i2c_dw_data_send(const struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t data = 0U;
uint32_t reg_base = get_regs(dev);
/* Nothing to send anymore, mask the interrupt */
if (dw->xfr_len == 0U) {
clear_bit_intr_mask_tx_empty(reg_base);
dw->state &= ~I2C_DW_CMD_SEND;
return 0;
}
while (test_bit_status_tfnt(reg_base) && (dw->xfr_len > 0)) {
/* We have something to transmit to a specific host */
data = dw->xfr_buf[0];
/* Send RESTART if needed */
if (dw->xfr_flags & I2C_MSG_RESTART) {
data |= IC_DATA_CMD_RESTART;
dw->xfr_flags &= ~(I2C_MSG_RESTART);
}
/* Send STOP if needed */
if ((dw->xfr_len == 1U) && (dw->xfr_flags & I2C_MSG_STOP)) {
data |= IC_DATA_CMD_STOP;
}
#ifdef CONFIG_I2C_DW_LPSS_DMA
i2c_dw_idma_tx_transfer(dev, data);
#else
write_cmd_data(data, reg_base);
#endif
dw->xfr_len--;
dw->xfr_buf++;
if (test_bit_intr_stat_tx_abrt(reg_base)) {
return -EIO;
}
}
return 0;
}
static inline void i2c_dw_transfer_complete(const struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t value;
uint32_t reg_base = get_regs(dev);
write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
value = read_clr_intr(reg_base);
k_sem_give(&dw->device_sync_sem);
}
#ifdef CONFIG_I2C_TARGET
static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev);
static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data);
static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev);
#endif
static void i2c_dw_isr(const struct device *port)
{
struct i2c_dw_dev_config * const dw = port->data;
union ic_interrupt_register intr_stat;
uint32_t value;
int ret = 0;
uint32_t reg_base = get_regs(port);
/* Cache ic_intr_stat for processing, so there is no need to read
* the register multiple times.
*/
intr_stat.raw = read_intr_stat(reg_base);
/*
* Causes of an interrupt:
* - STOP condition is detected
* - Transfer is aborted
* - Transmit FIFO is empty
* - Transmit FIFO has overflowed
* - Receive FIFO is full
* - Receive FIFO has overflowed
* - Received FIFO has underrun
* - Transmit data is required (tx_req)
* - Receive data is available (rx_avail)
*/
LOG_DBG("I2C: interrupt received");
/* Check if we are configured as a master device */
if (test_bit_con_master_mode(reg_base)) {
#ifdef CONFIG_I2C_DW_LPSS_DMA
uint32_t stat = sys_read32(reg_base + IDMA_REG_INTR_STS);
if (stat & IDMA_TX_RX_CHAN_MASK) {
const struct i2c_dw_rom_config * const rom = port->config;
/* Handle the DMA interrupt */
dma_intel_lpss_isr(rom->dma_dev);
}
#endif
/* Bail early if there is any error. */
if ((DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_TX_OVER |
DW_INTR_STAT_RX_OVER | DW_INTR_STAT_RX_UNDER) &
intr_stat.raw) {
dw->state = I2C_DW_CMD_ERROR;
goto done;
}
/* Check if the RX FIFO reached threshold */
if (intr_stat.bits.rx_full) {
i2c_dw_data_read(port);
}
#ifdef CONFIG_I2C_TARGET
/* Check if the TX FIFO is ready for commands.
* TX FIFO also serves as command queue where read requests
* are written to TX FIFO.
*/
if ((dw->xfr_flags & I2C_MSG_RW_MASK)
== I2C_MSG_READ) {
set_bit_intr_mask_tx_empty(reg_base);
}
#endif /* CONFIG_I2C_TARGET */
if (intr_stat.bits.tx_empty) {
if ((dw->xfr_flags & I2C_MSG_RW_MASK)
== I2C_MSG_WRITE) {
ret = i2c_dw_data_send(port);
} else {
i2c_dw_data_ask(port);
}
/* If STOP is not expected, finish processing this
* message if there is nothing left to do anymore.
*/
if (((dw->xfr_len == 0U)
&& !(dw->xfr_flags & I2C_MSG_STOP))
|| (ret != 0)) {
goto done;
}
}
/* STOP detected: finish processing this message */
if (intr_stat.bits.stop_det) {
value = read_clr_stop_det(reg_base);
goto done;
}
} else {
#ifdef CONFIG_I2C_TARGET
const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
uint32_t slave_activity = test_bit_status_activity(reg_base);
uint8_t data;
i2c_dw_slave_read_clear_intr_bits(port);
if (intr_stat.bits.rx_full) {
if (dw->state != I2C_DW_CMD_SEND) {
dw->state = I2C_DW_CMD_SEND;
if (slave_cb->write_requested) {
slave_cb->write_requested(dw->slave_cfg);
}
}
/* FIFO needs to be drained here so we don't miss the next interrupt */
do {
data = i2c_dw_read_byte_non_blocking(port);
if (slave_cb->write_received) {
slave_cb->write_received(dw->slave_cfg, data);
}
} while (test_bit_status_rfne(reg_base));
}
if (intr_stat.bits.rd_req) {
if (slave_activity) {
read_clr_rd_req(reg_base);
dw->state = I2C_DW_CMD_RECV;
if (slave_cb->read_requested) {
slave_cb->read_requested(dw->slave_cfg, &data);
i2c_dw_write_byte_non_blocking(port, data);
}
if (slave_cb->read_processed) {
slave_cb->read_processed(dw->slave_cfg, &data);
}
}
}
#endif
}
return;
done:
i2c_dw_transfer_complete(port);
}
static int i2c_dw_setup(const struct device *dev, uint16_t slave_address)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t value;
union ic_con_register ic_con;
union ic_tar_register ic_tar;
uint32_t reg_base = get_regs(dev);
ic_con.raw = 0U;
/* Disable the device controller to be able set TAR */
clear_bit_enable_en(reg_base);
/* Disable interrupts */
write_intr_mask(0, reg_base);
/* Clear interrupts */
value = read_clr_intr(reg_base);
/* Set master or slave mode - (initialization = slave) */
if (I2C_MODE_CONTROLLER & dw->app_config) {
/*
* Make sure to set both the master_mode and slave_disable_bit
* to both 0 or both 1
*/
LOG_DBG("I2C: host configured as Master Device");
ic_con.bits.master_mode = 1U;
ic_con.bits.slave_disable = 1U;
} else {
return -EINVAL;
}
ic_con.bits.restart_en = 1U;
/* Set addressing mode - (initialization = 7 bit) */
if (I2C_ADDR_10_BITS & dw->app_config) {
LOG_DBG("I2C: using 10-bit address");
ic_con.bits.addr_master_10bit = 1U;
ic_con.bits.addr_slave_10bit = 1U;
}
/* Setup the clock frequency and speed mode */
switch (I2C_SPEED_GET(dw->app_config)) {
case I2C_SPEED_STANDARD:
LOG_DBG("I2C: speed set to STANDARD");
write_ss_scl_lcnt(dw->lcnt, reg_base);
write_ss_scl_hcnt(dw->hcnt, reg_base);
ic_con.bits.speed = I2C_DW_SPEED_STANDARD;
break;
case I2C_SPEED_FAST:
__fallthrough;
case I2C_SPEED_FAST_PLUS:
LOG_DBG("I2C: speed set to FAST or FAST_PLUS");
write_fs_scl_lcnt(dw->lcnt, reg_base);
write_fs_scl_hcnt(dw->hcnt, reg_base);
ic_con.bits.speed = I2C_DW_SPEED_FAST;
break;
case I2C_SPEED_HIGH:
if (!dw->support_hs_mode) {
return -EINVAL;
}
LOG_DBG("I2C: speed set to HIGH");
write_hs_scl_lcnt(dw->lcnt, reg_base);
write_hs_scl_hcnt(dw->hcnt, reg_base);
ic_con.bits.speed = I2C_DW_SPEED_HIGH;
break;
default:
LOG_DBG("I2C: invalid speed requested");
return -EINVAL;
}
LOG_DBG("I2C: lcnt = %d", dw->lcnt);
LOG_DBG("I2C: hcnt = %d", dw->hcnt);
/* Set the IC_CON register */
write_con(ic_con.raw, reg_base);
/* Set RX fifo threshold level.
* Setting it to zero automatically triggers interrupt
* RX_FULL whenever there is data received.
*
* TODO: extend the threshold for multi-byte RX.
*/
write_rx_tl(0, reg_base);
/* Set TX fifo threshold level.
* TX_EMPTY interrupt is triggered only when the
* TX FIFO is truly empty. So that we can let
* the controller do the transfers for longer period
* before we need to fill the FIFO again. This may
* cause some pauses during transfers, but this keeps
* the device from interrupting often.
*/
write_tx_tl(0, reg_base);
ic_tar.raw = read_tar(reg_base);
if (test_bit_con_master_mode(reg_base)) {
/* Set address of target slave */
ic_tar.bits.ic_tar = slave_address;
} else {
/* Set slave address for device */
write_sar(slave_address, reg_base);
}
/* If I2C is being operated in master mode and I2C_DYNAMIC_TAR_UPDATE
* configuration parameter is set to Yes (1), the ic_10bitaddr_master
* bit in ic_tar register would control whether the DW_apb_i2c starts
* its transfers in 7-bit or 10-bit addressing mode.
*/
if (I2C_MODE_CONTROLLER & dw->app_config) {
if (I2C_ADDR_10_BITS & dw->app_config) {
ic_tar.bits.ic_10bitaddr_master = 1U;
} else {
ic_tar.bits.ic_10bitaddr_master = 0U;
}
}
write_tar(ic_tar.raw, reg_base);
return 0;
}
static int i2c_dw_transfer(const struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address)
{
struct i2c_dw_dev_config * const dw = dev->data;
struct i2c_msg *cur_msg = msgs;
uint8_t msg_left = num_msgs;
uint8_t pflags;
int ret;
uint32_t reg_base = get_regs(dev);
uint32_t value = 0;
__ASSERT_NO_MSG(msgs);
if (!num_msgs) {
return 0;
}
ret = k_mutex_lock(&dw->bus_mutex, K_FOREVER);
if (ret != 0) {
return ret;
}
/* First step, check if there is current activity */
if (test_bit_status_activity(reg_base) || (dw->state & I2C_DW_BUSY)) {
ret = -EBUSY;
goto error;
}
dw->state |= I2C_DW_BUSY;
ret = i2c_dw_setup(dev, slave_address);
if (ret) {
goto error;
}
/* Enable controller */
set_bit_enable_en(reg_base);
/*
* While waiting at device_sync_sem, kernel can switch to idle
* task which in turn can call pm_system_suspend() hook of Power
* Management App (PMA).
* pm_device_busy_set() call here, would indicate to PMA that it should
* not execute PM policies that would turn off this ip block, causing an
* ongoing hw transaction to be left in an inconsistent state.
* Note : This is just a sample to show a possible use of the API, it is
* upto the driver expert to see, if he actually needs it here, or
* somewhere else, or not needed as the driver's suspend()/resume()
* can handle everything
*/
pm_device_busy_set(dev);
/* Process all the messages */
while (msg_left > 0) {
/* Workaround for I2C scanner as DW HW does not support 0 byte transfers.*/
if ((cur_msg->len == 0) && (cur_msg->buf != NULL)) {
cur_msg->len = 1;
}
pflags = dw->xfr_flags;
dw->xfr_buf = cur_msg->buf;
dw->xfr_len = cur_msg->len;
dw->xfr_flags = cur_msg->flags;
dw->rx_pending = 0U;
/* Need to RESTART if changing transfer direction */
if ((pflags & I2C_MSG_RW_MASK)
!= (dw->xfr_flags & I2C_MSG_RW_MASK)) {
dw->xfr_flags |= I2C_MSG_RESTART;
}
dw->state &= ~(I2C_DW_CMD_SEND | I2C_DW_CMD_RECV);
if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
dw->state |= I2C_DW_CMD_SEND;
dw->request_bytes = 0U;
} else {
dw->state |= I2C_DW_CMD_RECV;
dw->request_bytes = dw->xfr_len;
}
/* Enable interrupts to trigger ISR */
if (test_bit_con_master_mode(reg_base)) {
/* Enable necessary interrupts */
write_intr_mask((DW_ENABLE_TX_INT_I2C_MASTER |
DW_ENABLE_RX_INT_I2C_MASTER), reg_base);
} else {
/* Enable necessary interrupts */
write_intr_mask(DW_ENABLE_TX_INT_I2C_SLAVE, reg_base);
}
/* Wait for transfer to be done */
ret = k_sem_take(&dw->device_sync_sem, K_MSEC(CONFIG_I2C_DW_RW_TIMEOUT_MS));
if (ret != 0) {
write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
value = read_clr_intr(reg_base);
break;
}
if (dw->state & I2C_DW_CMD_ERROR) {
ret = -EIO;
break;
}
/* Something wrong if there is something left to do */
if (dw->xfr_len > 0) {
ret = -EIO;
break;
}
cur_msg++;
msg_left--;
}
pm_device_busy_clear(dev);
error:
dw->state = I2C_DW_STATE_READY;
k_mutex_unlock(&dw->bus_mutex);
return ret;
}
static int i2c_dw_runtime_configure(const struct device *dev, uint32_t config)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t value = 0U;
uint32_t rc = 0U;
uint32_t reg_base = get_regs(dev);
dw->app_config = config;
/* Make sure we have a supported speed for the DesignWare model */
/* and have setup the clock frequency and speed mode */
switch (I2C_SPEED_GET(dw->app_config)) {
case I2C_SPEED_STANDARD:
/* Following the directions on DW spec page 59, IC_SS_SCL_LCNT
* must have register values larger than IC_FS_SPKLEN + 7
*/
if (I2C_STD_LCNT <= (read_fs_spklen(reg_base) + 7)) {
value = read_fs_spklen(reg_base) + 8;
} else {
value = I2C_STD_LCNT;
}
dw->lcnt = value;
/* Following the directions on DW spec page 59, IC_SS_SCL_HCNT
* must have register values larger than IC_FS_SPKLEN + 5
*/
if (I2C_STD_HCNT <= (read_fs_spklen(reg_base) + 5)) {
value = read_fs_spklen(reg_base) + 6;
} else {
value = I2C_STD_HCNT;
}
dw->hcnt = value;
break;
case I2C_SPEED_FAST:
__fallthrough;
case I2C_SPEED_FAST_PLUS:
/*
* Following the directions on DW spec page 59, IC_FS_SCL_LCNT
* must have register values larger than IC_FS_SPKLEN + 7
*/
if (I2C_FS_LCNT <= (read_fs_spklen(reg_base) + 7)) {
value = read_fs_spklen(reg_base) + 8;
} else {
value = I2C_FS_LCNT;
}
dw->lcnt = value;
/*
* Following the directions on DW spec page 59, IC_FS_SCL_HCNT
* must have register values larger than IC_FS_SPKLEN + 5
*/
if (I2C_FS_HCNT <= (read_fs_spklen(reg_base) + 5)) {
value = read_fs_spklen(reg_base) + 6;
} else {
value = I2C_FS_HCNT;
}
dw->hcnt = value;
break;
case I2C_SPEED_HIGH:
if (dw->support_hs_mode) {
if (I2C_HS_LCNT <= (read_hs_spklen(reg_base) + 7)) {
value = read_hs_spklen(reg_base) + 8;
} else {
value = I2C_HS_LCNT;
}
dw->lcnt = value;
if (I2C_HS_HCNT <= (read_hs_spklen(reg_base) + 5)) {
value = read_hs_spklen(reg_base) + 6;
} else {
value = I2C_HS_HCNT;
}
dw->hcnt = value;
} else {
rc = -EINVAL;
}
break;
default:
/* TODO change */
rc = -EINVAL;
}
/*
* Clear any interrupts currently waiting in the controller
*/
value = read_clr_intr(reg_base);
/*
* TEMPORARY HACK - The I2C does not work in any mode other than Master
* currently. This "hack" forces us to always be configured for master
* mode, until we can verify that Slave mode works correctly.
*/
dw->app_config |= I2C_MODE_CONTROLLER;
return rc;
}
#ifdef CONFIG_I2C_TARGET
static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev)
{
uint32_t reg_base = get_regs(dev);
if (!test_bit_status_rfne(reg_base)) { /* Rx FIFO must not be empty */
return -EIO;
}
return (uint8_t)read_cmd_data(reg_base);
}
static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data)
{
uint32_t reg_base = get_regs(dev);
if (!test_bit_status_tfnt(reg_base)) { /* Tx FIFO must not be full */
return;
}
write_cmd_data(data, reg_base);
}
static int i2c_dw_set_master_mode(const struct device *dev)
{
union ic_comp_param_1_register ic_comp_param_1;
uint32_t reg_base = get_regs(dev);
union ic_con_register ic_con;
clear_bit_enable_en(reg_base);
ic_con.bits.master_mode = 1U;
ic_con.bits.slave_disable = 1U;
ic_con.bits.rx_fifo_full = 0U;
write_con(ic_con.raw, reg_base);
set_bit_enable_en(reg_base);
ic_comp_param_1.raw = read_comp_param_1(reg_base);
write_tx_tl(ic_comp_param_1.bits.tx_buffer_depth + 1, reg_base);
write_rx_tl(ic_comp_param_1.bits.rx_buffer_depth + 1, reg_base);
return 0;
}
static int i2c_dw_set_slave_mode(const struct device *dev, uint8_t addr)
{
uint32_t reg_base = get_regs(dev);
union ic_con_register ic_con;
ic_con.raw = read_con(reg_base);
clear_bit_enable_en(reg_base);
ic_con.bits.master_mode = 0U;
ic_con.bits.slave_disable = 0U;
ic_con.bits.rx_fifo_full = 1U;
ic_con.bits.restart_en = 1U;
ic_con.bits.stop_det = 1U;
write_con(ic_con.raw, reg_base);
write_sar(addr, reg_base);
write_intr_mask(~DW_INTR_MASK_RESET, reg_base);
set_bit_enable_en(reg_base);
write_tx_tl(0, reg_base);
write_rx_tl(0, reg_base);
LOG_DBG("I2C: Host registered as Slave Device");
return 0;
}
static int i2c_dw_slave_register(const struct device *dev,
struct i2c_target_config *cfg)
{
struct i2c_dw_dev_config * const dw = dev->data;
uint32_t reg_base = get_regs(dev);
int ret;
dw->slave_cfg = cfg;
ret = i2c_dw_set_slave_mode(dev, cfg->address);
write_intr_mask(DW_INTR_MASK_RX_FULL |
DW_INTR_MASK_RD_REQ |
DW_INTR_MASK_TX_ABRT |
DW_INTR_MASK_STOP_DET, reg_base);
return ret;
}
static int i2c_dw_slave_unregister(const struct device *dev,
struct i2c_target_config *cfg)
{
struct i2c_dw_dev_config * const dw = dev->data;
int ret;
dw->state = I2C_DW_STATE_READY;
ret = i2c_dw_set_master_mode(dev);
return ret;
}
static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev)
{
struct i2c_dw_dev_config * const dw = dev->data;
union ic_interrupt_register intr_stat;
uint32_t reg_base = get_regs(dev);
const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
intr_stat.raw = read_intr_stat(reg_base);
if (intr_stat.bits.tx_abrt) {
read_clr_tx_abrt(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.rx_under) {
read_clr_rx_under(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.rx_over) {
read_clr_rx_over(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.tx_over) {
read_clr_tx_over(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.rx_done) {
read_clr_rx_done(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.activity) {
read_clr_activity(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.stop_det) {
read_clr_stop_det(reg_base);
dw->state = I2C_DW_STATE_READY;
if (slave_cb->stop) {
slave_cb->stop(dw->slave_cfg);
}
}
if (intr_stat.bits.start_det) {
read_clr_start_det(reg_base);
dw->state = I2C_DW_STATE_READY;
}
if (intr_stat.bits.gen_call) {
read_clr_gen_call(reg_base);
dw->state = I2C_DW_STATE_READY;
}
}
#endif /* CONFIG_I2C_TARGET */
static const struct i2c_driver_api funcs = {
.configure = i2c_dw_runtime_configure,
.transfer = i2c_dw_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_dw_slave_register,
.target_unregister = i2c_dw_slave_unregister,
#endif /* CONFIG_I2C_TARGET */
};
static int i2c_dw_initialize(const struct device *dev)
{
const struct i2c_dw_rom_config * const rom = dev->config;
struct i2c_dw_dev_config * const dw = dev->data;
union ic_con_register ic_con;
int ret = 0;
#if defined(CONFIG_RESET)
if (rom->reset.dev) {
ret = reset_line_toggle_dt(&rom->reset);
if (ret) {
return ret;
}
}
#endif
#if defined(CONFIG_PINCTRL)
ret = pinctrl_apply_state(rom->pcfg, PINCTRL_STATE_DEFAULT);
if (ret) {
return ret;
}
#endif
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
if (rom->pcie) {
struct pcie_bar mbar;
if (rom->pcie->bdf == PCIE_BDF_NONE) {
return -EINVAL;
}
pcie_probe_mbar(rom->pcie->bdf, 0, &mbar);
pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr,
mbar.size, K_MEM_CACHE_NONE);
pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
#ifdef CONFIG_I2C_DW_LPSS_DMA
uintptr_t base;
base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET;
dma_intel_lpss_set_base(rom->dma_dev, base);
dma_intel_lpss_setup(rom->dma_dev);
/* Assign physical & virtual address to dma instance */
dw->phy_addr = mbar.phys_addr;
dw->base_addr = (uint32_t)(DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET);
sys_write32((uint32_t)dw->phy_addr,
DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]",
dw->phy_addr, dw->base_addr);
#endif
} else
#endif
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
}
k_sem_init(&dw->device_sync_sem, 0, K_SEM_MAX_LIMIT);
k_mutex_init(&dw->bus_mutex);
uint32_t reg_base = get_regs(dev);
clear_bit_enable_en(reg_base);
/* verify that we have a valid DesignWare register first */
if (read_comp_type(reg_base) != I2C_DW_MAGIC_KEY) {
LOG_DBG("I2C: DesignWare magic key not found, check base "
"address. Stopping initialization");
return -EIO;
}
/*
* grab the default value on initialization. This should be set to the
* IC_MAX_SPEED_MODE in the hardware. If it does support high speed we
* can move provide support for it
*/
ic_con.raw = read_con(reg_base);
if (ic_con.bits.speed == I2C_DW_SPEED_HIGH) {
LOG_DBG("I2C: high speed supported");
dw->support_hs_mode = true;
} else {
LOG_DBG("I2C: high speed NOT supported");
dw->support_hs_mode = false;
}
rom->config_func(dev);
dw->app_config = I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(rom->bitrate);
if (i2c_dw_runtime_configure(dev, dw->app_config) != 0) {
LOG_DBG("I2C: Cannot set default configuration");
return -EIO;
}
dw->state = I2C_DW_STATE_READY;
return ret;
}
#if defined(CONFIG_PINCTRL)
#define PINCTRL_DW_DEFINE(n) PINCTRL_DT_INST_DEFINE(n)
#define PINCTRL_DW_CONFIG(n) .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
#else
#define PINCTRL_DW_DEFINE(n)
#define PINCTRL_DW_CONFIG(n)
#endif
#if defined(CONFIG_RESET)
#define RESET_DW_CONFIG(n) \
IF_ENABLED(DT_INST_NODE_HAS_PROP(0, resets), \
(.reset = RESET_DT_SPEC_INST_GET(n),))
#else
#define RESET_DW_CONFIG(n)
#endif
#define I2C_DW_INIT_PCIE0(n)
#define I2C_DW_INIT_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie),
#define I2C_DW_INIT_PCIE(n) \
_CONCAT(I2C_DW_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define I2C_DEFINE_PCIE0(n)
#define I2C_DEFINE_PCIE1(n) DEVICE_PCIE_INST_DECLARE(n)
#define I2C_PCIE_DEFINE(n) \
_CONCAT(I2C_DEFINE_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define I2C_DW_IRQ_FLAGS_SENSE0(n) 0
#define I2C_DW_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
#define I2C_DW_IRQ_FLAGS(n) \
_CONCAT(I2C_DW_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))(n)
/* not PCI(e) */
#define I2C_DW_IRQ_CONFIG_PCIE0(n) \
static void i2c_config_##n(const struct device *port) \
{ \
ARG_UNUSED(port); \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
i2c_dw_isr, DEVICE_DT_INST_GET(n), \
I2C_DW_IRQ_FLAGS(n)); \
irq_enable(DT_INST_IRQN(n)); \
}
/* PCI(e) with auto IRQ detection */
#define I2C_DW_IRQ_CONFIG_PCIE1(n) \
static void i2c_config_##n(const struct device *port) \
{ \
BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
"Only runtime IRQ configuration is supported"); \
BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
"DW I2C PCI needs CONFIG_DYNAMIC_INTERRUPTS"); \
const struct i2c_dw_rom_config * const dev_cfg = port->config;\
unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
return; \
} \
pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
DT_INST_IRQ(n, priority), \
(void (*)(const void *))i2c_dw_isr, \
DEVICE_DT_INST_GET(n), \
I2C_DW_IRQ_FLAGS(n)); \
pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
}
#define I2C_DW_IRQ_CONFIG(n) \
_CONCAT(I2C_DW_IRQ_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define I2C_CONFIG_REG_INIT_PCIE0(n) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),
#define I2C_CONFIG_REG_INIT_PCIE1(n)
#define I2C_CONFIG_REG_INIT(n) \
_CONCAT(I2C_CONFIG_REG_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
#define I2C_CONFIG_DMA_INIT(n) \
COND_CODE_1(CONFIG_I2C_DW_LPSS_DMA, \
(COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
(.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0)),), \
())), ())
#define I2C_DEVICE_INIT_DW(n) \
PINCTRL_DW_DEFINE(n); \
I2C_PCIE_DEFINE(n); \
static void i2c_config_##n(const struct device *port); \
static const struct i2c_dw_rom_config i2c_config_dw_##n = { \
I2C_CONFIG_REG_INIT(n) \
.config_func = i2c_config_##n, \
.bitrate = DT_INST_PROP(n, clock_frequency), \
RESET_DW_CONFIG(n) \
PINCTRL_DW_CONFIG(n) \
I2C_DW_INIT_PCIE(n) \
I2C_CONFIG_DMA_INIT(n) \
}; \
static struct i2c_dw_dev_config i2c_##n##_runtime; \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_dw_initialize, NULL, \
&i2c_##n##_runtime, &i2c_config_dw_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&funcs); \
I2C_DW_IRQ_CONFIG(n)
DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_DW)
``` | /content/code_sandbox/drivers/i2c/i2c_dw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,680 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_lpi2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/rtio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <fsl_lpi2c.h>
#include <zephyr/drivers/pinctrl.h>
#ifdef CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY
#include "i2c_bitbang.h"
#include <zephyr/drivers/gpio.h>
#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mcux_lpi2c);
#include "i2c-priv.h"
/* Wait for the duration of 12 bits to detect a NAK after a bus
* address scan. (10 appears sufficient, 20% safety factor.)
*/
#define SCAN_DELAY_US(baudrate) (12 * USEC_PER_SEC / baudrate)
/* Required by DEVICE_MMIO_NAMED_* macros */
#define DEV_CFG(_dev) \
((const struct mcux_lpi2c_config *)(_dev)->config)
#define DEV_DATA(_dev) ((struct mcux_lpi2c_data *)(_dev)->data)
struct mcux_lpi2c_config {
DEVICE_MMIO_NAMED_ROM(reg_base);
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
void (*irq_config_func)(const struct device *dev);
uint32_t bitrate;
uint32_t bus_idle_timeout_ns;
const struct pinctrl_dev_config *pincfg;
#ifdef CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY
struct gpio_dt_spec scl;
struct gpio_dt_spec sda;
#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */
};
struct mcux_lpi2c_data {
DEVICE_MMIO_NAMED_RAM(reg_base);
lpi2c_master_handle_t handle;
struct i2c_rtio *ctx;
lpi2c_master_transfer_t transfer;
#ifdef CONFIG_I2C_TARGET
lpi2c_slave_handle_t target_handle;
struct i2c_target_config *target_cfg;
bool target_attached;
bool first_tx;
bool read_active;
bool send_ack;
#endif
};
static int mcux_lpi2c_configure(const struct device *dev,
uint32_t dev_config_raw)
{
struct i2c_rtio *const ctx = ((struct mcux_lpi2c_data *)
dev->data)->ctx;
return i2c_rtio_configure(ctx, dev_config_raw);
}
static int mcux_lpi2c_do_configure(const struct device *dev, uint32_t dev_config_raw)
{
const struct mcux_lpi2c_config *config = dev->config;
LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
uint32_t clock_freq;
uint32_t baudrate;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
LPI2C_MasterSetBaudRate(base, clock_freq, baudrate);
return 0;
}
static uint32_t mcux_lpi2c_convert_flags(int msg_flags)
{
uint32_t flags = 0U;
if (!(msg_flags & I2C_MSG_STOP)) {
flags |= kLPI2C_TransferNoStopFlag;
}
if (msg_flags & I2C_MSG_RESTART) {
flags |= kLPI2C_TransferRepeatedStartFlag;
}
return flags;
}
static bool mcux_lpi2c_msg_start(const struct device *dev, uint8_t flags,
uint8_t *buf, size_t buf_len, uint16_t i2c_addr)
{
struct mcux_lpi2c_data *data = dev->data;
struct i2c_rtio *ctx = data->ctx;
LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
lpi2c_master_transfer_t *transfer = &data->transfer;
status_t status;
if (I2C_MSG_ADDR_10_BITS & flags) {
return i2c_rtio_complete(ctx, -ENOTSUP);
}
/* Initialize the transfer descriptor */
transfer->flags = mcux_lpi2c_convert_flags(flags);
/* Prevent the controller to send a start condition between
* messages, except if explicitly requested.
*/
if (ctx->txn_curr != ctx->txn_head && !(flags & I2C_MSG_RESTART)) {
transfer->flags |= kLPI2C_TransferNoStartFlag;
}
transfer->slaveAddress = i2c_addr;
transfer->direction = (flags & I2C_MSG_READ)
? kLPI2C_Read : kLPI2C_Write;
transfer->subaddress = 0;
transfer->subaddressSize = 0;
transfer->data = buf;
transfer->dataSize = buf_len;
/* Start the transfer */
status = LPI2C_MasterTransferNonBlocking(base,
&data->handle, transfer);
/* Return an error if the transfer didn't start successfully
* e.g., if the bus was busy
*/
if (status != kStatus_Success) {
LPI2C_MasterTransferAbort(base, &data->handle);
return i2c_rtio_complete(ctx, -EIO);
}
return false;
}
static void mcux_lpi2c_complete(const struct device *dev, int status);
static bool mcux_lpi2c_start(const struct device *dev)
{
struct mcux_lpi2c_data *data = dev->data;
struct i2c_rtio *ctx = data->ctx;
struct rtio_sqe *sqe = &ctx->txn_curr->sqe;
struct i2c_dt_spec *dt_spec = sqe->iodev->data;
int res = 0;
switch (sqe->op) {
case RTIO_OP_RX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags,
sqe->rx.buf, sqe->rx.buf_len, dt_spec->addr);
case RTIO_OP_TINY_TX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
sqe->tiny_tx.buf, sqe->tiny_tx.buf_len, dt_spec->addr);
case RTIO_OP_TX:
return mcux_lpi2c_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
sqe->tx.buf, sqe->tx.buf_len, dt_spec->addr);
case RTIO_OP_I2C_CONFIGURE:
res = mcux_lpi2c_do_configure(dev, sqe->i2c_config);
return i2c_rtio_complete(data->ctx, res);
default:
LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
return i2c_rtio_complete(data->ctx, -EINVAL);
}
}
static void mcux_lpi2c_complete(const struct device *dev, status_t status)
{
const struct mcux_lpi2c_config *config = dev->config;
struct mcux_lpi2c_data *data = dev->data;
LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct i2c_rtio *const ctx = data->ctx;
int ret = 0;
/* Return an error if the transfer didn't complete
* successfully. e.g., nak, timeout, lost arbitration
*/
if (status != kStatus_Success) {
LPI2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
goto out;
}
if (data->transfer.dataSize == 0) {
k_busy_wait(SCAN_DELAY_US(config->bitrate));
if (0 != (base->MSR & LPI2C_MSR_NDF_MASK)) {
LPI2C_MasterTransferAbort(base, &data->handle);
ret = -EIO;
goto out;
}
}
out:
if (i2c_rtio_complete(ctx, ret)) {
mcux_lpi2c_start(dev);
}
}
static void mcux_lpi2c_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
{
struct mcux_lpi2c_data *data = dev->data;
struct i2c_rtio *const ctx = data->ctx;
if (i2c_rtio_submit(ctx, iodev_sqe)) {
mcux_lpi2c_start(dev);
}
}
static void mcux_lpi2c_master_transfer_callback(LPI2C_Type *base,
lpi2c_master_handle_t *handle,
status_t status, void *userData)
{
ARG_UNUSED(handle);
ARG_UNUSED(base);
const struct device *dev = userData;
mcux_lpi2c_complete(dev, status);
}
static int mcux_lpi2c_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_rtio *const ctx = ((struct mcux_lpi2c_data *)
dev->data)->ctx;
return i2c_rtio_transfer(ctx, msgs, num_msgs, addr);
}
static void mcux_lpi2c_isr(const struct device *dev)
{
struct mcux_lpi2c_data *data = dev->data;
LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
LPI2C_MasterTransferHandleIRQ(base, &data->handle);
}
static int mcux_lpi2c_init(const struct device *dev)
{
const struct mcux_lpi2c_config *config = dev->config;
struct mcux_lpi2c_data *data = dev->data;
LPI2C_Type *base;
uint32_t clock_freq, bitrate_cfg;
lpi2c_master_config_t master_config;
int error;
DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (error) {
return error;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
LPI2C_MasterGetDefaultConfig(&master_config);
master_config.busIdleTimeout_ns = config->bus_idle_timeout_ns;
LPI2C_MasterInit(base, &master_config, clock_freq);
LPI2C_MasterTransferCreateHandle(base, &data->handle,
mcux_lpi2c_master_transfer_callback,
(void *)dev);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = mcux_lpi2c_do_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
config->irq_config_func(dev);
i2c_rtio_init(data->ctx, dev);
return 0;
}
static const struct i2c_driver_api mcux_lpi2c_driver_api = {
.configure = mcux_lpi2c_configure,
.transfer = mcux_lpi2c_transfer,
.iodev_submit = mcux_lpi2c_submit,
};
#if CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY
#define I2C_MCUX_LPI2C_SCL_INIT(n) .scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}),
#define I2C_MCUX_LPI2C_SDA_INIT(n) .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),
#else
#define I2C_MCUX_LPI2C_SCL_INIT(n)
#define I2C_MCUX_LPI2C_SDA_INIT(n)
#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */
#define I2C_MCUX_LPI2C_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static void mcux_lpi2c_config_func_##n(const struct device *dev); \
\
static const struct mcux_lpi2c_config mcux_lpi2c_config_##n = { \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
.irq_config_func = mcux_lpi2c_config_func_##n, \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
I2C_MCUX_LPI2C_SCL_INIT(n) \
I2C_MCUX_LPI2C_SDA_INIT(n) \
.bus_idle_timeout_ns = \
UTIL_AND(DT_INST_NODE_HAS_PROP(n, bus_idle_timeout),\
DT_INST_PROP(n, bus_idle_timeout)), \
}; \
\
I2C_RTIO_DEFINE(_i2c##n##_lpi2c_rtio, \
DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \
DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \
\
static struct mcux_lpi2c_data mcux_lpi2c_data_##n = { \
.ctx = &CONCAT(_i2c, n, _lpi2c_rtio), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(n, mcux_lpi2c_init, NULL, \
&mcux_lpi2c_data_##n, \
&mcux_lpi2c_config_##n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&mcux_lpi2c_driver_api); \
\
static void mcux_lpi2c_config_func_##n(const struct device *dev)\
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mcux_lpi2c_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_LPI2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_mcux_lpi2c_rtio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,383 |
```objective-c
/* i2c_dw_registers.h - array access for I2C Design Ware registers */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_
#define ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* IC_CON bits */
union ic_con_register {
uint32_t raw;
struct {
uint32_t master_mode : 1 __packed;
uint32_t speed : 2 __packed;
uint32_t addr_slave_10bit : 1 __packed;
uint32_t addr_master_10bit : 1 __packed;
uint32_t restart_en : 1 __packed;
uint32_t slave_disable : 1 __packed;
uint32_t stop_det : 1 __packed;
uint32_t tx_empty_ctl : 1 __packed;
uint32_t rx_fifo_full : 1 __packed;
} bits;
};
/* IC_DATA_CMD bits */
#define IC_DATA_CMD_DAT_MASK 0xFF
#define IC_DATA_CMD_CMD BIT(8)
#define IC_DATA_CMD_STOP BIT(9)
#define IC_DATA_CMD_RESTART BIT(10)
/* DesignWare Interrupt bits positions */
#define DW_INTR_STAT_RX_UNDER BIT(0)
#define DW_INTR_STAT_RX_OVER BIT(1)
#define DW_INTR_STAT_RX_FULL BIT(2)
#define DW_INTR_STAT_TX_OVER BIT(3)
#define DW_INTR_STAT_TX_EMPTY BIT(4)
#define DW_INTR_STAT_RD_REQ BIT(5)
#define DW_INTR_STAT_TX_ABRT BIT(6)
#define DW_INTR_STAT_RX_DONE BIT(7)
#define DW_INTR_STAT_ACTIVITY BIT(8)
#define DW_INTR_STAT_STOP_DET BIT(9)
#define DW_INTR_STAT_START_DET BIT(10)
#define DW_INTR_STAT_GEN_CALL BIT(11)
#define DW_INTR_STAT_RESTART_DET BIT(12)
#define DW_INTR_STAT_MST_ON_HOLD BIT(13)
#define DW_INTR_MASK_RX_UNDER BIT(0)
#define DW_INTR_MASK_RX_OVER BIT(1)
#define DW_INTR_MASK_RX_FULL BIT(2)
#define DW_INTR_MASK_TX_OVER BIT(3)
#define DW_INTR_MASK_TX_EMPTY BIT(4)
#define DW_INTR_MASK_RD_REQ BIT(5)
#define DW_INTR_MASK_TX_ABRT BIT(6)
#define DW_INTR_MASK_RX_DONE BIT(7)
#define DW_INTR_MASK_ACTIVITY BIT(8)
#define DW_INTR_MASK_STOP_DET BIT(9)
#define DW_INTR_MASK_START_DET BIT(10)
#define DW_INTR_MASK_GEN_CALL BIT(11)
#define DW_INTR_MASK_RESTART_DET BIT(12)
#define DW_INTR_MASK_MST_ON_HOLD BIT(13)
#define DW_INTR_MASK_RESET 0x000008ff
union ic_interrupt_register {
uint32_t raw;
struct {
uint32_t rx_under : 1 __packed;
uint32_t rx_over : 1 __packed;
uint32_t rx_full : 1 __packed;
uint32_t tx_over : 1 __packed;
uint32_t tx_empty : 1 __packed;
uint32_t rd_req : 1 __packed;
uint32_t tx_abrt : 1 __packed;
uint32_t rx_done : 1 __packed;
uint32_t activity : 1 __packed;
uint32_t stop_det : 1 __packed;
uint32_t start_det : 1 __packed;
uint32_t gen_call : 1 __packed;
uint32_t restart_det : 1 __packed;
uint32_t mst_on_hold : 1 __packed;
uint32_t reserved : 2 __packed;
} bits;
};
/* IC_TAR */
union ic_tar_register {
uint32_t raw;
struct {
uint32_t ic_tar : 10 __packed;
uint32_t gc_or_start : 1 __packed;
uint32_t special : 1 __packed;
uint32_t ic_10bitaddr_master : 1 __packed;
uint32_t reserved : 3 __packed;
} bits;
};
/* IC_COMP_PARAM_1 */
union ic_comp_param_1_register {
uint32_t raw;
struct {
uint32_t apb_data_width : 2 __packed;
uint32_t max_speed_mode : 2 __packed;
uint32_t hc_count_values : 1 __packed;
uint32_t intr_io : 1 __packed;
uint32_t has_dma : 1 __packed;
uint32_t add_encoded_params : 1 __packed;
uint32_t rx_buffer_depth : 8 __packed;
uint32_t tx_buffer_depth : 8 __packed;
uint32_t reserved : 7 __packed;
} bits;
};
#define DW_IC_REG_CON (0x00)
#define DW_IC_REG_TAR (0x04)
#define DW_IC_REG_SAR (0x08)
#define DW_IC_REG_DATA_CMD (0x10)
#define DW_IC_REG_SS_SCL_HCNT (0x14)
#define DW_IC_REG_SS_SCL_LCNT (0x18)
#define DW_IC_REG_FS_SCL_HCNT (0x1C)
#define DW_IC_REG_FS_SCL_LCNT (0x20)
#define DW_IC_REG_HS_SCL_HCNT (0x24)
#define DW_IC_REG_HS_SCL_LCNT (0x28)
#define DW_IC_REG_INTR_STAT (0x2C)
#define DW_IC_REG_INTR_MASK (0x30)
#define DW_IC_REG_RX_TL (0x38)
#define DW_IC_REG_TX_TL (0x3C)
#define DW_IC_REG_CLR_INTR (0x40)
#define DW_IC_REG_CLR_RX_UNDER (0x44)
#define DW_IC_REG_CLR_RX_OVER (0x48)
#define DW_IC_REG_CLR_TX_OVER (0x4c)
#define DW_IC_REG_CLR_RD_REQ (0x50)
#define DW_IC_REG_CLR_TX_ABRT (0x54)
#define DW_IC_REG_CLR_RX_DONE (0x58)
#define DW_IC_REG_CLR_ACTIVITY (0x5c)
#define DW_IC_REG_CLR_STOP_DET (0x60)
#define DW_IC_REG_CLR_START_DET (0x64)
#define DW_IC_REG_CLR_GEN_CALL (0x68)
#define DW_IC_REG_ENABLE (0x6C)
#define DW_IC_REG_STATUS (0x70)
#define DW_IC_REG_TXFLR (0x74)
#define DW_IC_REG_RXFLR (0x78)
#define DW_IC_REG_DMA_CR (0x88)
#define DW_IC_REG_TDLR (0x8C)
#define DW_IC_REG_RDLR (0x90)
#define DW_IC_REG_FS_SPKLEN (0xA0)
#define DW_IC_REG_HS_SPKLEN (0xA4)
#define DW_IC_REG_COMP_PARAM_1 (0xF4)
#define DW_IC_REG_COMP_TYPE (0xFC)
#define IDMA_REG_INTR_STS 0xAE8
#define IDMA_TX_RX_CHAN_MASK 0x3
/* CON Bit */
#define DW_IC_CON_MASTER_MODE_BIT (0)
/* DMA control bits */
#define DW_IC_DMA_RX_ENABLE BIT(0)
#define DW_IC_DMA_TX_ENABLE BIT(1)
#define DW_IC_DMA_ENABLE (BIT(0) | BIT(1))
DEFINE_TEST_BIT_OP(con_master_mode, DW_IC_REG_CON, DW_IC_CON_MASTER_MODE_BIT)
DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32)
DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32)
#define DW_IC_INTR_STAT_TX_ABRT_BIT (6)
DEFINE_TEST_BIT_OP(intr_stat_tx_abrt, DW_IC_REG_INTR_STAT, DW_IC_INTR_STAT_TX_ABRT_BIT)
DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32)
#define DW_IC_INTR_MASK_TX_EMPTY_BIT (4)
DEFINE_CLEAR_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT)
DEFINE_SET_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT)
DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32)
DEFINE_MM_REG_WRITE(tx_tl, DW_IC_REG_TX_TL, 32)
DEFINE_MM_REG_READ(clr_intr, DW_IC_REG_CLR_INTR, 32)
DEFINE_MM_REG_READ(clr_stop_det, DW_IC_REG_CLR_STOP_DET, 32)
DEFINE_MM_REG_READ(clr_start_det, DW_IC_REG_CLR_START_DET, 32)
DEFINE_MM_REG_READ(clr_gen_call, DW_IC_REG_CLR_GEN_CALL, 32)
DEFINE_MM_REG_READ(clr_tx_abrt, DW_IC_REG_CLR_TX_ABRT, 32)
DEFINE_MM_REG_READ(clr_rx_under, DW_IC_REG_CLR_RX_UNDER, 32)
DEFINE_MM_REG_READ(clr_rx_over, DW_IC_REG_CLR_RX_OVER, 32)
DEFINE_MM_REG_READ(clr_tx_over, DW_IC_REG_CLR_TX_OVER, 32)
DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32)
DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32)
DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32)
#define DW_IC_ENABLE_EN_BIT (0)
DEFINE_CLEAR_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT)
DEFINE_SET_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT)
#define DW_IC_STATUS_ACTIVITY_BIT (0)
#define DW_IC_STATUS_TFNT_BIT (1)
#define DW_IC_STATUS_RFNE_BIT (3)
DEFINE_TEST_BIT_OP(status_activity, DW_IC_REG_STATUS, DW_IC_STATUS_ACTIVITY_BIT)
DEFINE_TEST_BIT_OP(status_tfnt, DW_IC_REG_STATUS, DW_IC_STATUS_TFNT_BIT)
DEFINE_TEST_BIT_OP(status_rfne, DW_IC_REG_STATUS, DW_IC_STATUS_RFNE_BIT)
DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32)
DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32)
DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32)
DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32)
DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32)
DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32)
DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32)
DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32)
DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32)
DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32)
DEFINE_MM_REG_READ(comp_param_1, DW_IC_REG_COMP_PARAM_1, 32)
DEFINE_MM_REG_READ(comp_type, DW_IC_REG_COMP_TYPE, 32)
DEFINE_MM_REG_READ(tar, DW_IC_REG_TAR, 32)
DEFINE_MM_REG_WRITE(tar, DW_IC_REG_TAR, 32)
DEFINE_MM_REG_WRITE(sar, DW_IC_REG_SAR, 32)
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_dw_registers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,647 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_i2c
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_sam0, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER SERCOM_I2CM_CTRLA_MODE(5)
#endif
struct i2c_sam0_dev_config {
SercomI2cm *regs;
const struct pinctrl_dev_config *pcfg;
uint32_t bitrate;
#ifdef MCLK
volatile uint32_t *mclk;
uint32_t mclk_mask;
uint16_t gclk_core_id;
#else
uint32_t pm_apbcmask;
uint16_t gclk_clkctrl_id;
#endif
void (*irq_config_func)(const struct device *dev);
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
const struct device *dma_dev;
uint8_t write_dma_request;
uint8_t read_dma_request;
uint8_t dma_channel;
#endif
};
struct i2c_sam0_msg {
uint8_t *buffer;
uint32_t size;
uint32_t status;
};
struct i2c_sam0_dev_data {
struct k_sem lock;
struct k_sem sem;
struct i2c_sam0_msg msg;
struct i2c_msg *msgs;
uint8_t num_msgs;
};
static void wait_synchronization(SercomI2cm *regs)
{
#if defined(SERCOM_I2CM_SYNCBUSY_MASK)
/* SYNCBUSY is a register */
while ((regs->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) != 0) {
}
#elif defined(SERCOM_I2CM_STATUS_SYNCBUSY)
/* SYNCBUSY is a bit */
while ((regs->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY) != 0) {
}
#else
#error Unsupported device
#endif
}
static bool i2c_sam0_terminate_on_error(const struct device *dev)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
if (!(i2c->STATUS.reg & (SERCOM_I2CM_STATUS_ARBLOST |
SERCOM_I2CM_STATUS_RXNACK |
#ifdef SERCOM_I2CM_STATUS_LENERR
SERCOM_I2CM_STATUS_LENERR |
#endif
#ifdef SERCOM_I2CM_STATUS_SEXTTOUT
SERCOM_I2CM_STATUS_SEXTTOUT |
#endif
#ifdef SERCOM_I2CM_STATUS_MEXTTOUT
SERCOM_I2CM_STATUS_MEXTTOUT |
#endif
SERCOM_I2CM_STATUS_LOWTOUT |
SERCOM_I2CM_STATUS_BUSERR))) {
return false;
}
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
if (cfg->dma_channel != 0xFF) {
dma_stop(cfg->dma_dev, cfg->dma_channel);
}
#endif
data->msg.status = i2c->STATUS.reg;
/*
* Clear all the flags that require an explicit clear
* (as opposed to being cleared by ADDR writes, etc)
*/
i2c->STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST |
#ifdef SERCOM_I2CM_STATUS_LENERR
SERCOM_I2CM_STATUS_LENERR |
#endif
SERCOM_I2CM_STATUS_LOWTOUT |
SERCOM_I2CM_STATUS_BUSERR;
wait_synchronization(i2c);
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
if (i2c->INTFLAG.reg & (SERCOM_I2CM_INTFLAG_MB | SERCOM_I2CM_INTFLAG_SB)) {
i2c->CTRLB.bit.CMD = 3;
}
k_sem_give(&data->sem);
return true;
}
static void i2c_sam0_isr(const struct device *dev)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
/* Get present interrupts and clear them */
uint32_t status = i2c->INTFLAG.reg;
i2c->INTFLAG.reg = status;
if (i2c_sam0_terminate_on_error(dev)) {
return;
}
/*
* Directly send/receive next message if it is in the same direction and
* the current message has no stop flag and the next message has no
* restart flag.
*/
const bool continue_next = (data->msg.size == 1) && (data->num_msgs > 1) &&
((data->msgs[0].flags & I2C_MSG_RW_MASK) ==
(data->msgs[1].flags & I2C_MSG_RW_MASK)) &&
!(data->msgs[0].flags & I2C_MSG_STOP) &&
!(data->msgs[1].flags & I2C_MSG_RESTART) &&
((status & (SERCOM_I2CM_INTFLAG_MB | SERCOM_I2CM_INTFLAG_SB)));
if (status & SERCOM_I2CM_INTFLAG_MB) {
if (!data->msg.size) {
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
/*
* Decide whether to issue a repeated start, or a stop condition...
* - A repeated start can either be accomplished by writing a 0x1
* to the CMD field, or by writing to ADDR - which is what this
* driver does in i2c_sam0_transfer().
* - A stop is accomplished by writing a 0x3 to CMD (below).
*
* This decision is not the same as continue_next, as the value of
* data->msg.size is already zero (not one), and i2c_sam0_transfer()
* is responsible for advancing to the next message, not the ISR.
*/
if ((data->num_msgs <= 1)
|| (data->msgs[0].flags & I2C_MSG_STOP)
|| !(data->msgs[1].flags & I2C_MSG_RESTART)) {
i2c->CTRLB.bit.CMD = 3;
}
k_sem_give(&data->sem);
return;
}
i2c->DATA.reg = *data->msg.buffer;
data->msg.buffer++;
data->msg.size--;
} else if (status & SERCOM_I2CM_INTFLAG_SB) {
if (!continue_next && (data->msg.size == 1)) {
/*
* If this is the last byte, then prepare for an auto
* NACK before doing the actual read. This does not
* require write synchronization.
*/
i2c->CTRLB.bit.ACKACT = 1;
i2c->CTRLB.bit.CMD = 3;
}
*data->msg.buffer = i2c->DATA.reg;
data->msg.buffer++;
data->msg.size--;
if (!continue_next && !data->msg.size) {
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
k_sem_give(&data->sem);
return;
}
}
if (continue_next) {
data->msgs++;
data->num_msgs--;
data->msg.buffer = data->msgs->buf;
data->msg.size = data->msgs->len;
data->msg.status = 0;
}
}
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
static void i2c_sam0_dma_write_done(const struct device *dma_dev, void *arg,
uint32_t id, int error_code)
{
const struct device *dev = arg;
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
ARG_UNUSED(dma_dev);
ARG_UNUSED(id);
unsigned int key = irq_lock();
if (i2c_sam0_terminate_on_error(dev)) {
irq_unlock(key);
return;
}
if (error_code < 0) {
LOG_ERR("DMA write error on %s: %d", dev->name, error_code);
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
irq_unlock(key);
data->msg.status = error_code;
k_sem_give(&data->sem);
return;
}
irq_unlock(key);
/*
* DMA has written the whole message now, so just wait for the
* final I2C IRQ to indicate that it's finished transmitting.
*/
data->msg.size = 0;
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
}
static bool i2c_sam0_dma_write_start(const struct device *dev)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
int retval;
if (cfg->dma_channel == 0xFF) {
return false;
}
if (data->msg.size <= 1) {
/*
* Catch empty writes and skip DMA on single byte transfers.
*/
return false;
}
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_blk = { 0 };
dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
dma_cfg.source_data_size = 1;
dma_cfg.dest_data_size = 1;
dma_cfg.user_data = (void *)dev;
dma_cfg.dma_callback = i2c_sam0_dma_write_done;
dma_cfg.block_count = 1;
dma_cfg.head_block = &dma_blk;
dma_cfg.dma_slot = cfg->write_dma_request;
dma_blk.block_size = data->msg.size;
dma_blk.source_address = (uint32_t)data->msg.buffer;
dma_blk.dest_address = (uint32_t)(&(i2c->DATA.reg));
dma_blk.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg);
if (retval != 0) {
LOG_ERR("Write DMA configure on %s failed: %d",
dev->name, retval);
return false;
}
retval = dma_start(cfg->dma_dev, cfg->dma_channel);
if (retval != 0) {
LOG_ERR("Write DMA start on %s failed: %d",
dev->name, retval);
return false;
}
return true;
}
static void i2c_sam0_dma_read_done(const struct device *dma_dev, void *arg,
uint32_t id, int error_code)
{
const struct device *dev = arg;
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
ARG_UNUSED(dma_dev);
ARG_UNUSED(id);
unsigned int key = irq_lock();
if (i2c_sam0_terminate_on_error(dev)) {
irq_unlock(key);
return;
}
if (error_code < 0) {
LOG_ERR("DMA read error on %s: %d", dev->name, error_code);
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
irq_unlock(key);
data->msg.status = error_code;
k_sem_give(&data->sem);
return;
}
irq_unlock(key);
/*
* DMA has read all but the last byte now, so let the ISR handle
* that and the terminating NACK.
*/
data->msg.buffer += data->msg.size - 1;
data->msg.size = 1;
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
}
static bool i2c_sam0_dma_read_start(const struct device *dev)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
int retval;
if (cfg->dma_channel == 0xFF) {
return false;
}
if (data->msg.size <= 2) {
/*
* The last byte is always handled by the I2C ISR so
* just skip a two length read as well.
*/
return false;
}
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_blk = { 0 };
dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
dma_cfg.source_data_size = 1;
dma_cfg.dest_data_size = 1;
dma_cfg.user_data = (void *)dev;
dma_cfg.dma_callback = i2c_sam0_dma_read_done;
dma_cfg.block_count = 1;
dma_cfg.head_block = &dma_blk;
dma_cfg.dma_slot = cfg->read_dma_request;
dma_blk.block_size = data->msg.size - 1;
dma_blk.dest_address = (uint32_t)data->msg.buffer;
dma_blk.source_address = (uint32_t)(&(i2c->DATA.reg));
dma_blk.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
retval = dma_config(cfg->dma_dev, cfg->dma_channel, &dma_cfg);
if (retval != 0) {
LOG_ERR("Read DMA configure on %s failed: %d",
dev->name, retval);
return false;
}
retval = dma_start(cfg->dma_dev, cfg->dma_channel);
if (retval != 0) {
LOG_ERR("Read DMA start on %s failed: %d",
dev->name, retval);
return false;
}
return true;
}
#endif
static int i2c_sam0_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
uint32_t addr_reg;
int ret;
if (!num_msgs) {
return 0;
}
k_sem_take(&data->lock, K_FOREVER);
data->num_msgs = num_msgs;
data->msgs = msgs;
for (; data->num_msgs > 0;) {
if (!data->msgs->len) {
if ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
ret = -EINVAL;
goto unlock;
}
}
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
i2c->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
i2c->STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST |
#ifdef SERCOM_I2CM_STATUS_LENERR
SERCOM_I2CM_STATUS_LENERR |
#endif
SERCOM_I2CM_STATUS_LOWTOUT |
SERCOM_I2CM_STATUS_BUSERR;
wait_synchronization(i2c);
data->msg.buffer = data->msgs->buf;
data->msg.size = data->msgs->len;
data->msg.status = 0;
addr_reg = addr << 1U;
if ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
addr_reg |= 1U;
/* Set to auto ACK */
i2c->CTRLB.bit.ACKACT = 0;
wait_synchronization(i2c);
}
if (data->msgs->flags & I2C_MSG_ADDR_10_BITS) {
#ifdef SERCOM_I2CM_ADDR_TENBITEN
addr_reg |= SERCOM_I2CM_ADDR_TENBITEN;
#else
ret = -ENOTSUP;
goto unlock;
#endif
}
unsigned int key = irq_lock();
/*
* Writing the address starts the transaction, issuing
* a start/repeated start as required.
*/
i2c->ADDR.reg = addr_reg;
/*
* Have to wait here to make sure the address write
* clears any pending requests or errors before DMA or
* ISR tries to handle it.
*/
wait_synchronization(i2c);
#ifdef SERCOM_I2CM_INTENSET_ERROR
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
#endif
if ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
/*
* Always set MB even when reading, since that's how
* some errors are indicated.
*/
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
if (!i2c_sam0_dma_read_start(dev))
#endif
{
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
}
} else {
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
if (!i2c_sam0_dma_write_start(dev))
#endif
{
i2c->INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
}
}
irq_unlock(key);
/* Now wait for the ISR to handle everything */
k_sem_take(&data->sem, K_FOREVER);
if (data->msg.status) {
if (data->msg.status & SERCOM_I2CM_STATUS_ARBLOST) {
LOG_DBG("Arbitration lost on %s",
dev->name);
ret = -EAGAIN;
goto unlock;
}
LOG_ERR("Transaction error on %s: %08X",
dev->name, data->msg.status);
ret = -EIO;
goto unlock;
}
data->num_msgs--;
data->msgs++;
}
ret = 0;
unlock:
k_sem_give(&data->lock);
return ret;
}
static int i2c_sam0_set_apply_bitrate(const struct device *dev,
uint32_t config)
{
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
uint32_t baud;
uint32_t baud_low;
uint32_t baud_high;
uint32_t CTRLA = i2c->CTRLA.reg;
#ifdef SERCOM_I2CM_CTRLA_SPEED_Msk
CTRLA &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
#endif
CTRLA &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
#ifdef SERCOM_I2CM_CTRLA_SPEED
CTRLA |= SERCOM_I2CM_CTRLA_SPEED(0);
#endif
CTRLA |= SERCOM_I2CM_CTRLA_SDAHOLD(0x0);
i2c->CTRLA.reg = CTRLA;
wait_synchronization(i2c);
/* 5 is the nominal 100ns rise time from the app notes */
baud = (SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / 100000U - 5U - 10U) / 2U;
if (baud > 255U || baud < 1U) {
return -ERANGE;
}
LOG_DBG("Setting %s to standard mode with divisor %u",
dev->name, baud);
i2c->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(baud);
break;
case I2C_SPEED_FAST:
CTRLA |= SERCOM_I2CM_CTRLA_SDAHOLD(0x0);
i2c->CTRLA.reg = CTRLA;
wait_synchronization(i2c);
/* 5 is the nominal 100ns rise time from the app notes */
baud = (SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / 400000U - 5U - 10U) / 2U;
if (baud > 255U || baud < 1U) {
return -ERANGE;
}
LOG_DBG("Setting %s to fast mode with divisor %u",
dev->name, baud);
i2c->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(baud);
break;
case I2C_SPEED_FAST_PLUS:
#ifdef SERCOM_I2CM_CTRLA_SPEED
CTRLA |= SERCOM_I2CM_CTRLA_SPEED(1);
#endif
CTRLA |= SERCOM_I2CM_CTRLA_SDAHOLD(0x2);
i2c->CTRLA.reg = CTRLA;
wait_synchronization(i2c);
/* 5 is the nominal 100ns rise time from the app notes */
baud = (SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / 1000000U - 5U - 10U);
/* 2:1 low:high ratio */
baud_high = baud;
baud_high /= 3U;
baud_high = CLAMP(baud_high, 1U, 255U);
baud_low = baud - baud_high;
if (baud_low < 1U && baud_high > 1U) {
--baud_high;
++baud_low;
}
if (baud_low < 1U || baud_low > 255U) {
return -ERANGE;
}
LOG_DBG("Setting %s to fast mode plus with divisors %u/%u",
dev->name, baud_high, baud_low);
i2c->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(baud_high) |
SERCOM_I2CM_BAUD_BAUDLOW(baud_low);
break;
case I2C_SPEED_HIGH:
#ifdef SERCOM_I2CM_CTRLA_SPEED
CTRLA |= SERCOM_I2CM_CTRLA_SPEED(2);
#endif
CTRLA |= SERCOM_I2CM_CTRLA_SDAHOLD(0x2);
i2c->CTRLA.reg = CTRLA;
wait_synchronization(i2c);
baud = (SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / 3400000U) - 2U;
/* 2:1 low:high ratio */
baud_high = baud;
baud_high /= 3U;
baud_high = CLAMP(baud_high, 1U, 255U);
baud_low = baud - baud_high;
if (baud_low < 1U && baud_high > 1U) {
--baud_high;
++baud_low;
}
if (baud_low < 1U || baud_low > 255U) {
return -ERANGE;
}
#ifdef SERCOM_I2CM_BAUD_HSBAUD
LOG_DBG("Setting %s to high speed with divisors %u/%u",
dev->name, baud_high, baud_low);
/*
* 48 is just from the app notes, but the datasheet says
* it's ignored
*/
i2c->BAUD.reg = SERCOM_I2CM_BAUD_HSBAUD(baud_high) |
SERCOM_I2CM_BAUD_HSBAUDLOW(baud_low) |
SERCOM_I2CM_BAUD_BAUD(48) |
SERCOM_I2CM_BAUD_BAUDLOW(48);
#else
return -ENOTSUP;
#endif
break;
default:
return -ENOTSUP;
}
wait_synchronization(i2c);
return 0;
}
static int i2c_sam0_configure(const struct device *dev, uint32_t config)
{
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
int retval;
if (!(config & I2C_MODE_CONTROLLER)) {
return -EINVAL;
}
if (config & I2C_SPEED_MASK) {
i2c->CTRLA.bit.ENABLE = 0;
wait_synchronization(i2c);
retval = i2c_sam0_set_apply_bitrate(dev, config);
i2c->CTRLA.bit.ENABLE = 1;
wait_synchronization(i2c);
if (retval != 0) {
return retval;
}
}
return 0;
}
static int i2c_sam0_initialize(const struct device *dev)
{
struct i2c_sam0_dev_data *data = dev->data;
const struct i2c_sam0_dev_config *const cfg = dev->config;
SercomI2cm *i2c = cfg->regs;
int retval;
#ifdef MCLK
/* Enable the GCLK */
GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
GCLK_PCHCTRL_CHEN;
/* Enable SERCOM clock in MCLK */
*cfg->mclk |= cfg->mclk_mask;
#else
/* Enable the GCLK */
GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
/* Enable SERCOM clock in PM */
PM->APBCMASK.reg |= cfg->pm_apbcmask;
#endif
/* Disable all I2C interrupts */
i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
/* I2C mode, enable timeouts */
i2c->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER |
#ifdef SERCOM_I2CM_CTRLA_LOWTOUTEN
SERCOM_I2CM_CTRLA_LOWTOUTEN |
#endif
SERCOM_I2CM_CTRLA_INACTOUT(0x3);
wait_synchronization(i2c);
/* Enable smart mode (auto ACK) */
i2c->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
wait_synchronization(i2c);
retval = i2c_sam0_set_apply_bitrate(dev,
i2c_map_dt_bitrate(cfg->bitrate));
if (retval != 0) {
return retval;
}
k_sem_init(&data->lock, 1, 1);
k_sem_init(&data->sem, 0, 1);
cfg->irq_config_func(dev);
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
if (!device_is_ready(cfg->dma_dev)) {
return -ENODEV;
}
#endif
i2c->CTRLA.bit.ENABLE = 1;
wait_synchronization(i2c);
/* Force bus idle */
i2c->STATUS.bit.BUSSTATE = 1;
wait_synchronization(i2c);
return 0;
}
static const struct i2c_driver_api i2c_sam0_driver_api = {
.configure = i2c_sam0_configure,
.transfer = i2c_sam0_transfer,
};
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
#define I2C_SAM0_DMA_CHANNELS(n) \
.dma_dev = DEVICE_DT_GET(ATMEL_SAM0_DT_INST_DMA_CTLR(n, tx)), \
.write_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
.read_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
.dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
#else
#define I2C_SAM0_DMA_CHANNELS(n)
#endif
#define SAM0_I2C_IRQ_CONNECT(n, m) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
DT_INST_IRQ_BY_IDX(n, m, priority), \
i2c_sam0_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
} while (false)
#if DT_INST_IRQ_HAS_IDX(0, 3)
#define I2C_SAM0_IRQ_HANDLER(n) \
static void i2c_sam0_irq_config_##n(const struct device *dev) \
{ \
SAM0_I2C_IRQ_CONNECT(n, 0); \
SAM0_I2C_IRQ_CONNECT(n, 1); \
SAM0_I2C_IRQ_CONNECT(n, 2); \
SAM0_I2C_IRQ_CONNECT(n, 3); \
}
#else
#define I2C_SAM0_IRQ_HANDLER(n) \
static void i2c_sam0_irq_config_##n(const struct device *dev) \
{ \
SAM0_I2C_IRQ_CONNECT(n, 0); \
}
#endif
#ifdef MCLK
#define I2C_SAM0_CONFIG(n) \
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
.irq_config_func = &i2c_sam0_irq_config_##n, \
I2C_SAM0_DMA_CHANNELS(n) \
}
#else /* !MCLK */
#define I2C_SAM0_CONFIG(n) \
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
.irq_config_func = &i2c_sam0_irq_config_##n, \
I2C_SAM0_DMA_CHANNELS(n) \
}
#endif
#define I2C_SAM0_DEVICE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void i2c_sam0_irq_config_##n(const struct device *dev); \
I2C_SAM0_CONFIG(n); \
static struct i2c_sam0_dev_data i2c_sam0_dev_data_##n; \
I2C_DEVICE_DT_INST_DEFINE(n, \
i2c_sam0_initialize, \
NULL, \
&i2c_sam0_dev_data_##n, \
&i2c_sam0_dev_config_##n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_sam0_driver_api); \
I2C_SAM0_IRQ_HANDLER(n)
DT_INST_FOREACH_STATUS_OKAY(I2C_SAM0_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,061 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_i2c_twi
/** @file
* @brief I2C bus (TWI) driver for Atmel SAM MCU family.
*
* Limitations:
* - Only I2C Master Mode with 7 bit addressing is currently supported.
* - No reentrancy support.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <stdbool.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_sam_twi);
#include "i2c-priv.h"
/** I2C bus speed [Hz] in Standard Mode */
#define BUS_SPEED_STANDARD_HZ 100000U
/** I2C bus speed [Hz] in Fast Mode */
#define BUS_SPEED_FAST_HZ 400000U
/* Maximum value of Clock Divider (CKDIV) */
#define CKDIV_MAX 7
/* Device constant configuration parameters */
struct i2c_sam_twi_dev_cfg {
Twi *regs;
void (*irq_config)(void);
uint32_t bitrate;
const struct atmel_sam_pmc_config clock_cfg;
const struct pinctrl_dev_config *pcfg;
uint8_t irq_id;
};
struct twi_msg {
/* Buffer containing data to read or write */
uint8_t *buf;
/* Length of the buffer */
uint32_t len;
/* Index of the next byte to be read/written from/to the buffer */
uint32_t idx;
/* Value of TWI_SR at the end of the message */
uint32_t twi_sr;
/* Transfer flags as defined in the i2c.h file */
uint8_t flags;
};
/* Device run time data */
struct i2c_sam_twi_dev_data {
struct k_sem lock;
struct k_sem sem;
struct twi_msg msg;
};
static int i2c_clk_set(Twi *const twi, uint32_t speed)
{
uint32_t ck_div = 0U;
uint32_t cl_div;
bool div_completed = false;
/* From the datasheet "TWI Clock Waveform Generator Register"
* T_low = ( ( CLDIV 2^CKDIV ) + 4 ) T_MCK
*/
while (!div_completed) {
cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 4)
/ (1 << ck_div);
if (cl_div <= 255U) {
div_completed = true;
} else {
ck_div++;
}
}
if (ck_div > CKDIV_MAX) {
LOG_ERR("Failed to configure I2C clock");
return -EIO;
}
/* Set TWI clock duty cycle to 50% */
twi->TWI_CWGR = TWI_CWGR_CLDIV(cl_div) | TWI_CWGR_CHDIV(cl_div)
| TWI_CWGR_CKDIV(ck_div);
return 0;
}
static int i2c_sam_twi_configure(const struct device *dev, uint32_t config)
{
const struct i2c_sam_twi_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twi_dev_data *const dev_data = dev->data;
Twi *const twi = dev_cfg->regs;
uint32_t bitrate;
int ret;
if (!(config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Master Mode is not enabled");
return -EIO;
}
if (config & I2C_ADDR_10_BITS) {
LOG_ERR("I2C 10-bit addressing is currently not supported");
LOG_ERR("Please submit a patch");
return -EIO;
}
/* Configure clock */
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
bitrate = BUS_SPEED_STANDARD_HZ;
break;
case I2C_SPEED_FAST:
bitrate = BUS_SPEED_FAST_HZ;
break;
default:
LOG_ERR("Unsupported I2C speed value");
return -EIO;
}
k_sem_take(&dev_data->lock, K_FOREVER);
/* Setup clock waveform */
ret = i2c_clk_set(twi, bitrate);
if (ret < 0) {
goto unlock;
}
/* Disable Slave Mode */
twi->TWI_CR = TWI_CR_SVDIS;
/* Enable Master Mode */
twi->TWI_CR = TWI_CR_MSEN;
ret = 0;
unlock:
k_sem_give(&dev_data->lock);
return ret;
}
static void write_msg_start(Twi *const twi, struct twi_msg *msg, uint8_t daddr)
{
/* Set slave address and number of internal address bytes. */
twi->TWI_MMR = TWI_MMR_DADR(daddr);
/* Write first data byte on I2C bus */
twi->TWI_THR = msg->buf[msg->idx++];
/* Enable Transmit Ready and Transmission Completed interrupts */
twi->TWI_IER = TWI_IER_TXRDY | TWI_IER_TXCOMP | TWI_IER_NACK;
}
static void read_msg_start(Twi *const twi, struct twi_msg *msg, uint8_t daddr)
{
uint32_t twi_cr_stop;
/* Set slave address and number of internal address bytes */
twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(daddr);
/* In single data byte read the START and STOP must both be set */
twi_cr_stop = (msg->len == 1U) ? TWI_CR_STOP : 0;
/* Start the transfer by sending START condition */
twi->TWI_CR = TWI_CR_START | twi_cr_stop;
/* Enable Receive Ready and Transmission Completed interrupts */
twi->TWI_IER = TWI_IER_RXRDY | TWI_IER_TXCOMP | TWI_IER_NACK;
}
static int i2c_sam_twi_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct i2c_sam_twi_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twi_dev_data *const dev_data = dev->data;
Twi *const twi = dev_cfg->regs;
int ret;
__ASSERT_NO_MSG(msgs);
if (!num_msgs) {
return 0;
}
k_sem_take(&dev_data->lock, K_FOREVER);
/* Clear pending interrupts, such as NACK. */
(void)twi->TWI_SR;
/* Set number of internal address bytes to 0, not used. */
twi->TWI_IADR = 0;
for (; num_msgs > 0; num_msgs--, msgs++) {
dev_data->msg.buf = msgs->buf;
dev_data->msg.len = msgs->len;
dev_data->msg.idx = 0U;
dev_data->msg.twi_sr = 0U;
dev_data->msg.flags = msgs->flags;
/*
* REMARK: Dirty workaround:
*
* The controller does not have a documented, generic way to
* issue RESTART when changing transfer direction as master.
* Send a stop condition in such a case.
*/
if (num_msgs > 1) {
if ((msgs[0].flags & I2C_MSG_RW_MASK) !=
(msgs[1].flags & I2C_MSG_RW_MASK)) {
dev_data->msg.flags |= I2C_MSG_STOP;
}
}
if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
read_msg_start(twi, &dev_data->msg, addr);
} else {
write_msg_start(twi, &dev_data->msg, addr);
}
/* Wait for the transfer to complete */
k_sem_take(&dev_data->sem, K_FOREVER);
if (dev_data->msg.twi_sr > 0) {
/* Something went wrong */
ret = -EIO;
goto unlock;
}
}
ret = 0;
unlock:
k_sem_give(&dev_data->lock);
return ret;
}
static void i2c_sam_twi_isr(const struct device *dev)
{
const struct i2c_sam_twi_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twi_dev_data *const dev_data = dev->data;
Twi *const twi = dev_cfg->regs;
struct twi_msg *msg = &dev_data->msg;
uint32_t isr_status;
/* Retrieve interrupt status */
isr_status = twi->TWI_SR & twi->TWI_IMR;
/* Not Acknowledged */
if (isr_status & TWI_SR_NACK) {
msg->twi_sr = isr_status;
goto tx_comp;
}
/* Byte received */
if (isr_status & TWI_SR_RXRDY) {
msg->buf[msg->idx++] = twi->TWI_RHR;
if (msg->idx == msg->len - 1U) {
/* Send a STOP condition on the TWI */
twi->TWI_CR = TWI_CR_STOP;
}
}
/* Byte sent */
if (isr_status & TWI_SR_TXRDY) {
if (msg->idx == msg->len) {
if (msg->flags & I2C_MSG_STOP) {
/* Send a STOP condition on the TWI */
twi->TWI_CR = TWI_CR_STOP;
/* Disable Transmit Ready interrupt */
twi->TWI_IDR = TWI_IDR_TXRDY;
} else {
/* Transmission completed */
goto tx_comp;
}
} else {
twi->TWI_THR = msg->buf[msg->idx++];
}
}
/* Transmission completed */
if (isr_status & TWI_SR_TXCOMP) {
goto tx_comp;
}
return;
tx_comp:
/* Disable all enabled interrupts */
twi->TWI_IDR = twi->TWI_IMR;
/* We are done */
k_sem_give(&dev_data->sem);
}
static int i2c_sam_twi_initialize(const struct device *dev)
{
const struct i2c_sam_twi_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twi_dev_data *const dev_data = dev->data;
Twi *const twi = dev_cfg->regs;
uint32_t bitrate_cfg;
int ret;
/* Configure interrupts */
dev_cfg->irq_config();
/* Initialize semaphores */
k_sem_init(&dev_data->lock, 1, 1);
k_sem_init(&dev_data->sem, 0, 1);
/* Connect pins to the peripheral */
ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Enable TWI clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Reset TWI module */
twi->TWI_CR = TWI_CR_SWRST;
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
ret = i2c_sam_twi_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret < 0) {
LOG_ERR("Failed to initialize %s device", dev->name);
return ret;
}
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct i2c_driver_api i2c_sam_twi_driver_api = {
.configure = i2c_sam_twi_configure,
.transfer = i2c_sam_twi_transfer,
};
#define I2C_TWI_SAM_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void i2c##n##_sam_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
i2c_sam_twi_isr, \
DEVICE_DT_INST_GET(n), 0); \
} \
\
static const struct i2c_sam_twi_dev_cfg i2c##n##_sam_config = { \
.regs = (Twi *)DT_INST_REG_ADDR(n), \
.irq_config = i2c##n##_sam_irq_config, \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
.irq_id = DT_INST_IRQN(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct i2c_sam_twi_dev_data i2c##n##_sam_data; \
\
I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twi_initialize, \
NULL, \
&i2c##n##_sam_data, &i2c##n##_sam_config, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_sam_twi_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_TWI_SAM_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_sam_twi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,024 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/pm/policy.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <stm32_ll_i2c.h>
#include <stm32_ll_rcc.h>
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include "i2c_ll_stm32.h"
#ifdef CONFIG_I2C_STM32_BUS_RECOVERY
#include "i2c_bitbang.h"
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_ll_stm32);
#include "i2c-priv.h"
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
#define DT_DRV_COMPAT st_stm32_i2c_v2
#else
#define DT_DRV_COMPAT st_stm32_i2c_v1
#endif
/* This symbol takes the value 1 if one of the device instances */
/* is configured in dts with a domain clock */
#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
#else
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
#endif
int i2c_stm32_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_stm32_data *data = dev->data;
if (!data->is_configured) {
LOG_ERR("I2C controller not configured");
return -EIO;
}
*config = data->dev_config;
#if CONFIG_I2C_STM32_V2_TIMING
/* Print the timing parameter of device data */
LOG_INF("I2C timing value, report to the DTS :");
/* I2C BIT RATE */
if (data->current_timing.i2c_speed == 100000) {
LOG_INF("timings = <%d I2C_BITRATE_STANDARD 0x%X>;",
data->current_timing.periph_clock,
data->current_timing.timing_setting);
} else if (data->current_timing.i2c_speed == 400000) {
LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;",
data->current_timing.periph_clock,
data->current_timing.timing_setting);
} else if (data->current_timing.i2c_speed == 1000000) {
LOG_INF("timings = <%d I2C_SPEED_FAST_PLUS 0x%X>;",
data->current_timing.periph_clock,
data->current_timing.timing_setting);
}
#endif /* CONFIG_I2C_STM32_V2_TIMING */
return 0;
}
int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
I2C_TypeDef *i2c = cfg->i2c;
uint32_t i2c_clock = 0U;
int ret;
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[1],
&i2c_clock) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
return -EIO;
}
} else {
if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0],
&i2c_clock) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
return -EIO;
}
}
data->dev_config = config;
k_sem_take(&data->bus_mutex, K_FOREVER);
#ifdef CONFIG_PM_DEVICE_RUNTIME
ret = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]);
if (ret < 0) {
LOG_ERR("failure Enabling I2C clock");
return ret;
}
#endif
LL_I2C_Disable(i2c);
i2c_stm32_set_smbus_mode(dev, data->mode);
ret = stm32_i2c_configure_timing(dev, i2c_clock);
if (data->smbalert_active) {
LL_I2C_Enable(i2c);
}
#ifdef CONFIG_PM_DEVICE_RUNTIME
ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
if (ret < 0) {
LOG_ERR("failure disabling I2C clock");
return ret;
}
#endif
k_sem_give(&data->bus_mutex);
return ret;
}
#define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
uint8_t num_msgs, uint16_t slave)
{
struct i2c_stm32_data *data = dev->data;
struct i2c_msg *current, *next;
int ret = 0;
/* Check for validity of all messages, to prevent having to abort
* in the middle of a transfer
*/
current = msg;
/*
* Set I2C_MSG_RESTART flag on first message in order to send start
* condition
*/
current->flags |= I2C_MSG_RESTART;
for (uint8_t i = 1; i <= num_msgs; i++) {
if (i < num_msgs) {
next = current + 1;
/*
* Restart condition between messages
* of different directions is required
*/
if (OPERATION(current) != OPERATION(next)) {
if (!(next->flags & I2C_MSG_RESTART)) {
ret = -EINVAL;
break;
}
}
/* Stop condition is only allowed on last message */
if (current->flags & I2C_MSG_STOP) {
ret = -EINVAL;
break;
}
}
current++;
}
if (ret) {
return ret;
}
/* Send out messages */
k_sem_take(&data->bus_mutex, K_FOREVER);
/* Prevent driver from being suspended by PM until I2C transaction is complete */
#ifdef CONFIG_PM_DEVICE_RUNTIME
(void)pm_device_runtime_get(dev);
#endif
/* Prevent the clocks to be stopped during the i2c transaction */
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
current = msg;
while (num_msgs > 0) {
uint8_t *next_msg_flags = NULL;
if (num_msgs > 1) {
next = current + 1;
next_msg_flags = &(next->flags);
}
ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
if (ret < 0) {
break;
}
current++;
num_msgs--;
}
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
#ifdef CONFIG_PM_DEVICE_RUNTIME
(void)pm_device_runtime_put(dev);
#endif
k_sem_give(&data->bus_mutex);
return ret;
}
#if CONFIG_I2C_STM32_BUS_RECOVERY
static void i2c_stm32_bitbang_set_scl(void *io_context, int state)
{
const struct i2c_stm32_config *config = io_context;
gpio_pin_set_dt(&config->scl, state);
}
static void i2c_stm32_bitbang_set_sda(void *io_context, int state)
{
const struct i2c_stm32_config *config = io_context;
gpio_pin_set_dt(&config->sda, state);
}
static int i2c_stm32_bitbang_get_sda(void *io_context)
{
const struct i2c_stm32_config *config = io_context;
return gpio_pin_get_dt(&config->sda) == 0 ? 0 : 1;
}
static int i2c_stm32_recover_bus(const struct device *dev)
{
const struct i2c_stm32_config *config = dev->config;
struct i2c_stm32_data *data = dev->data;
struct i2c_bitbang bitbang_ctx;
struct i2c_bitbang_io bitbang_io = {
.set_scl = i2c_stm32_bitbang_set_scl,
.set_sda = i2c_stm32_bitbang_set_sda,
.get_sda = i2c_stm32_bitbang_get_sda,
};
uint32_t bitrate_cfg;
int error = 0;
LOG_ERR("attempting to recover bus");
if (!gpio_is_ready_dt(&config->scl)) {
LOG_ERR("SCL GPIO device not ready");
return -EIO;
}
if (!gpio_is_ready_dt(&config->sda)) {
LOG_ERR("SDA GPIO device not ready");
return -EIO;
}
k_sem_take(&data->bus_mutex, K_FOREVER);
error = gpio_pin_configure_dt(&config->scl, GPIO_OUTPUT_HIGH);
if (error != 0) {
LOG_ERR("failed to configure SCL GPIO (err %d)", error);
goto restore;
}
error = gpio_pin_configure_dt(&config->sda, GPIO_OUTPUT_HIGH);
if (error != 0) {
LOG_ERR("failed to configure SDA GPIO (err %d)", error);
goto restore;
}
i2c_bitbang_init(&bitbang_ctx, &bitbang_io, (void *)config);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate) | I2C_MODE_CONTROLLER;
error = i2c_bitbang_configure(&bitbang_ctx, bitrate_cfg);
if (error != 0) {
LOG_ERR("failed to configure I2C bitbang (err %d)", error);
goto restore;
}
error = i2c_bitbang_recover_bus(&bitbang_ctx);
if (error != 0) {
LOG_ERR("failed to recover bus (err %d)", error);
}
restore:
(void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
k_sem_give(&data->bus_mutex);
return error;
}
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
static const struct i2c_driver_api api_funcs = {
.configure = i2c_stm32_runtime_configure,
.transfer = i2c_stm32_transfer,
.get_config = i2c_stm32_get_config,
#if CONFIG_I2C_STM32_BUS_RECOVERY
.recover_bus = i2c_stm32_recover_bus,
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
#if defined(CONFIG_I2C_TARGET)
.target_register = i2c_stm32_target_register,
.target_unregister = i2c_stm32_target_unregister,
#endif
};
#ifdef CONFIG_PM_DEVICE
static int i2c_stm32_suspend(const struct device *dev)
{
int ret;
const struct i2c_stm32_config *cfg = dev->config;
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
/* Disable device clock. */
ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
if (ret < 0) {
LOG_ERR("failure disabling I2C clock");
return ret;
}
/* Move pins to sleep state */
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
if (ret == -ENOENT) {
/* Warn but don't block suspend */
LOG_WRN("I2C pinctrl sleep state not available ");
} else if (ret < 0) {
return ret;
}
return 0;
}
#endif
static int i2c_stm32_activate(const struct device *dev)
{
int ret;
const struct i2c_stm32_config *cfg = dev->config;
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
/* Move pins to active/default state */
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("I2C pinctrl setup failed (%d)", ret);
return ret;
}
/* Enable device clock. */
if (clock_control_on(clk,
(clock_control_subsys_t) &cfg->pclken[0]) != 0) {
LOG_ERR("i2c: failure enabling clock");
return -EIO;
}
return 0;
}
static int i2c_stm32_init(const struct device *dev)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
const struct i2c_stm32_config *cfg = dev->config;
uint32_t bitrate_cfg;
int ret;
struct i2c_stm32_data *data = dev->data;
#ifdef CONFIG_I2C_STM32_INTERRUPT
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
cfg->irq_config_func(dev);
#endif
data->is_configured = false;
data->mode = I2CSTM32MODE_I2C;
/*
* initialize mutex used when multiple transfers
* are taking place to guarantee that each one is
* atomic and has exclusive access to the I2C bus.
*/
k_sem_init(&data->bus_mutex, 1, 1);
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
i2c_stm32_activate(dev);
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
/* Enable I2C clock source */
ret = clock_control_configure(clk,
(clock_control_subsys_t) &cfg->pclken[1],
NULL);
if (ret < 0) {
return -EIO;
}
}
#if defined(CONFIG_SOC_SERIES_STM32F1X)
/*
* Force i2c reset for STM32F1 series.
* So that they can enter master mode properly.
* Issue described in ES096 2.14.7
*/
I2C_TypeDef *i2c = cfg->i2c;
LL_I2C_EnableReset(i2c);
LL_I2C_DisableReset(i2c);
#endif
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
ret = i2c_stm32_runtime_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret < 0) {
LOG_ERR("i2c: failure initializing");
return ret;
}
#ifdef CONFIG_PM_DEVICE_RUNTIME
(void)pm_device_runtime_enable(dev);
#endif
data->is_configured = true;
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int i2c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
{
int err;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
err = i2c_stm32_activate(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
err = i2c_stm32_suspend(dev);
break;
default:
return -ENOTSUP;
}
return err;
}
#endif
#ifdef CONFIG_SMBUS_STM32_SMBALERT
void i2c_stm32_smbalert_set_callback(const struct device *dev, i2c_stm32_smbalert_cb_func_t func,
const struct device *cb_dev)
{
struct i2c_stm32_data *data = dev->data;
data->smbalert_cb_func = func;
data->smbalert_cb_dev = cb_dev;
}
#endif /* CONFIG_SMBUS_STM32_SMBALERT */
void i2c_stm32_set_smbus_mode(const struct device *dev, enum i2c_stm32_mode mode)
{
const struct i2c_stm32_config *cfg = dev->config;
struct i2c_stm32_data *data = dev->data;
I2C_TypeDef *i2c = cfg->i2c;
data->mode = mode;
switch (mode) {
case I2CSTM32MODE_I2C:
LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
return;
#ifdef CONFIG_SMBUS_STM32
case I2CSTM32MODE_SMBUSHOST:
LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_HOST);
return;
case I2CSTM32MODE_SMBUSDEVICE:
LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE);
return;
case I2CSTM32MODE_SMBUSDEVICEARP:
LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE_ARP);
return;
#endif
default:
LOG_ERR("%s: invalid mode %i", dev->name, mode);
return;
}
}
#ifdef CONFIG_SMBUS_STM32
void i2c_stm32_smbalert_enable(const struct device *dev)
{
struct i2c_stm32_data *data = dev->data;
const struct i2c_stm32_config *cfg = dev->config;
data->smbalert_active = true;
LL_I2C_EnableSMBusAlert(cfg->i2c);
LL_I2C_EnableIT_ERR(cfg->i2c);
LL_I2C_Enable(cfg->i2c);
}
void i2c_stm32_smbalert_disable(const struct device *dev)
{
struct i2c_stm32_data *data = dev->data;
const struct i2c_stm32_config *cfg = dev->config;
data->smbalert_active = false;
LL_I2C_DisableSMBusAlert(cfg->i2c);
LL_I2C_DisableIT_ERR(cfg->i2c);
LL_I2C_Disable(cfg->i2c);
}
#endif /* CONFIG_SMBUS_STM32 */
/* Macros for I2C instance declaration */
#ifdef CONFIG_I2C_STM32_INTERRUPT
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQN(index), \
DT_INST_IRQ(index, priority), \
stm32_i2c_combined_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
} while (false)
#else
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
DT_INST_IRQ_BY_NAME(index, event, priority),\
stm32_i2c_event_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
DT_INST_IRQ_BY_NAME(index, error, priority),\
stm32_i2c_error_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
} while (false)
#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
#define STM32_I2C_IRQ_HANDLER_DECL(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev)
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
.irq_config_func = i2c_stm32_irq_config_func_##index,
#define STM32_I2C_IRQ_HANDLER(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
{ \
STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
}
#else
#define STM32_I2C_IRQ_HANDLER_DECL(index)
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
#define STM32_I2C_IRQ_HANDLER(index)
#endif /* CONFIG_I2C_STM32_INTERRUPT */
#define STM32_I2C_INIT(index) \
STM32_I2C_IRQ_HANDLER_DECL(index); \
\
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
(static const uint32_t i2c_timings_##index[] = \
DT_INST_PROP_OR(index, timings, {});)) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static const struct stm32_pclken pclken_##index[] = \
STM32_DT_INST_CLOCKS(index); \
\
static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
.i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
.pclken = pclken_##index, \
.pclk_len = DT_INST_NUM_CLOCKS(index), \
STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
.bitrate = DT_INST_PROP(index, clock_frequency), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
(.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\
.sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
(.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
.n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
}; \
\
static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
\
PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
\
I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
PM_DEVICE_DT_INST_GET(index), \
&i2c_stm32_dev_data_##index, \
&i2c_stm32_cfg_##index, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&api_funcs); \
\
STM32_I2C_IRQ_HANDLER(index)
DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_ll_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,013 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_PRIV_H_
#define ZEPHYR_DRIVERS_I2C_I2C_PRIV_H_
#include <zephyr/drivers/i2c.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/logging/log.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t i2c_map_dt_bitrate(uint32_t bitrate)
{
switch (bitrate) {
case I2C_BITRATE_STANDARD:
return I2C_SPEED_STANDARD << I2C_SPEED_SHIFT;
case I2C_BITRATE_FAST:
return I2C_SPEED_FAST << I2C_SPEED_SHIFT;
case I2C_BITRATE_FAST_PLUS:
return I2C_SPEED_FAST_PLUS << I2C_SPEED_SHIFT;
case I2C_BITRATE_HIGH:
return I2C_SPEED_HIGH << I2C_SPEED_SHIFT;
case I2C_BITRATE_ULTRA:
return I2C_SPEED_ULTRA << I2C_SPEED_SHIFT;
}
LOG_ERR("Invalid I2C bit rate value");
return 0;
}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_PRIV_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c-priv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 265 |
```unknown
config I2C_SMARTBOND
bool "Renesas SmartBond(tm) I2C driver"
default y
depends on DT_HAS_RENESAS_SMARTBOND_I2C_ENABLED
help
Enable I2C driver for Renesas SmartBond(tm) DA1469x series MCU.
``` | /content/code_sandbox/drivers/i2c/Kconfig.smartbond | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```unknown
# Microchip PolarFire SoC Icicle Kit I2C configuration options
config I2C_MCHP_MSS
bool "Microchip PolarFire SoC I2C driver"
default y
depends on DT_HAS_MICROCHIP_MPFS_I2C_ENABLED
help
Enable PolarFire SoC Icicle Kit I2C driver.
``` | /content/code_sandbox/drivers/i2c/Kconfig.mchp_mss | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_rcar_i2c
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_rcar);
#include "i2c-priv.h"
typedef void (*init_func_t)(const struct device *dev);
struct i2c_rcar_cfg {
uint32_t reg_addr;
init_func_t init_func;
const struct device *clock_dev;
struct rcar_cpg_clk mod_clk;
uint32_t bitrate;
};
struct i2c_rcar_data {
uint8_t status_mask;
struct k_sem int_sem;
};
/* Registers */
#define RCAR_I2C_ICSCR 0x00 /* Slave Control Register */
#define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
#define RCAR_I2C_ICSIER 0x10 /* Slave IRQ Enable */
#define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
#define RCAR_I2C_ICSSR 0x08 /* Slave Status */
#define RCAR_I2C_ICMSR 0x0c /* Master Status */
#define RCAR_I2C_ICCCR 0x18 /* Clock Control Register */
#define RCAR_I2C_ICSAR 0x1c /* Slave Address Register */
#define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
#define RCAR_I2C_ICRXD_ICTXD 0x24 /* Receive Transmit Data Register */
#define RCAR_I2C_ICFBSCR 0x38 /* First Bit Setup Cycle (Gen3).*/
#define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
#define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
#define RCAR_I2C_ICMCR_FSCL BIT(6) /* Forced SCL */
#define RCAR_I2C_ICMCR_FSDA BIT(5) /* Forced SDA */
#define RCAR_I2C_ICMCR_OBPC BIT(4) /* Override Bus Pin Control */
#define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
#define RCAR_I2C_ICMCR_TSBE BIT(2) /* Start Byte Transmission Enable */
#define RCAR_I2C_ICMCR_FSB BIT(1) /* Forced Stop onto the Bus */
#define RCAR_I2C_ICMCR_ESG BIT(0) /* Enable Start Generation */
#define RCAR_I2C_ICMCR_MASTER (RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE)
/* Bits to manage ICMIER and ICMSR registers */
#define RCAR_I2C_MNR BIT(6) /* Master Nack Received */
#define RCAR_I2C_MAL BIT(5) /* Master Arbitration lost */
#define RCAR_I2C_MST BIT(4) /* Master Stop Transmitted */
#define RCAR_I2C_MDE BIT(3) /* Master Data Empty */
#define RCAR_I2C_MDT BIT(2) /* Master Data Transmitted */
#define RCAR_I2C_MDR BIT(1) /* Master Data Received */
#define RCAR_I2C_MAT BIT(0) /* Master Address Transmitted */
/* Recommended bitrate settings from official documentation */
#define RCAR_I2C_ICCCR_CDF_100_KHZ 6
#define RCAR_I2C_ICCCR_CDF_400_KHZ 6
#define RCAR_I2C_ICCCR_SCGD_100_KHZ 21
#define RCAR_I2C_ICCCR_SCGD_400_KHZ 3
#define MAX_WAIT_US 100
static uint32_t i2c_rcar_read(const struct i2c_rcar_cfg *config,
uint32_t offs)
{
return sys_read32(config->reg_addr + offs);
}
static void i2c_rcar_write(const struct i2c_rcar_cfg *config,
uint32_t offs, uint32_t value)
{
sys_write32(value, config->reg_addr + offs);
}
static void i2c_rcar_isr(const struct device *dev)
{
const struct i2c_rcar_cfg *config = dev->config;
struct i2c_rcar_data *data = dev->data;
if (((i2c_rcar_read(config, RCAR_I2C_ICMSR)) & data->status_mask) ==
data->status_mask) {
k_sem_give(&data->int_sem);
i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
}
}
static int i2c_rcar_wait_for_state(const struct device *dev, uint8_t mask)
{
const struct i2c_rcar_cfg *config = dev->config;
struct i2c_rcar_data *data = dev->data;
data->status_mask = mask;
/* Reset interrupts semaphore */
k_sem_reset(&data->int_sem);
/* Enable interrupts */
i2c_rcar_write(config, RCAR_I2C_ICMIER, mask);
/* Wait for the interrupts */
return k_sem_take(&data->int_sem, K_USEC(MAX_WAIT_US));
}
static int i2c_rcar_finish(const struct device *dev)
{
const struct i2c_rcar_cfg *config = dev->config;
int ret;
/* Enable STOP generation */
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_FSB);
i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
/* Wait for STOP to be transmitted */
ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MST);
i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
/* Disable STOP generation */
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
return ret;
}
static int i2c_rcar_set_addr(const struct device *dev,
uint8_t chip, uint8_t read)
{
const struct i2c_rcar_cfg *config = dev->config;
/* Set slave address & transfer mode */
i2c_rcar_write(config, RCAR_I2C_ICMAR, (chip << 1) | read);
/* Reset */
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_ESG);
/* Clear Status */
i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
/* Wait for address & transfer mode to be transmitted */
if (read != 0) {
return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDR);
} else {
return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDE);
}
}
static int i2c_rcar_transfer_msg(const struct device *dev, struct i2c_msg *msg)
{
const struct i2c_rcar_cfg *config = dev->config;
uint32_t i, reg;
int ret = 0;
if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
/* Reading as master */
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
for (i = 0; i < msg->len; i++) {
if (msg->len - 1 == i) {
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER |
RCAR_I2C_ICMCR_FSB);
}
/* Start data reception */
reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
reg &= ~RCAR_I2C_MDR;
i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
/* Wait for data to be received */
ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDR);
if (ret != 0) {
return ret;
}
msg->buf[i] = i2c_rcar_read(config, RCAR_I2C_ICRXD_ICTXD) & 0xff;
}
} else {
/* Writing as master */
for (i = 0; i < msg->len; i++) {
i2c_rcar_write(config, RCAR_I2C_ICRXD_ICTXD, msg->buf[i]);
i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
/* Start data transmission */
reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
reg &= ~RCAR_I2C_MDE;
i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
/* Wait for all data to be transmitted */
ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDE);
if (ret != 0) {
return ret;
}
}
}
return ret;
}
static int i2c_rcar_transfer(const struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
const struct i2c_rcar_cfg *config = dev->config;
uint16_t timeout = 0;
int ret;
if (!num_msgs) {
return 0;
}
/* Wait for the bus to be available */
while ((i2c_rcar_read(config, RCAR_I2C_ICMCR) & RCAR_I2C_ICMCR_FSDA) && (timeout < 10)) {
k_busy_wait(USEC_PER_MSEC);
timeout++;
}
if (timeout == 10) {
return -EIO;
}
do {
/* We are not supporting 10-bit addressing */
if ((msgs->flags & I2C_MSG_ADDR_10_BITS) == I2C_MSG_ADDR_10_BITS) {
return -ENOTSUP;
}
/* Send slave address */
if (i2c_rcar_set_addr(dev, addr, !!(msgs->flags & I2C_MSG_READ))) {
return -EIO; /* No ACK received */
}
/* Transfer data */
if (msgs->len) {
ret = i2c_rcar_transfer_msg(dev, msgs);
if (ret != 0) {
return ret;
}
}
/* Finish the transfer */
if ((msgs->flags & I2C_MSG_STOP) == I2C_MSG_STOP) {
ret = i2c_rcar_finish(dev);
if (ret != 0) {
return ret;
}
}
/* Next message */
msgs++;
num_msgs--;
} while (num_msgs);
/* Complete without error */
return 0;
}
static int i2c_rcar_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_rcar_cfg *config = dev->config;
uint8_t cdf, scgd;
/* We only support Master mode */
if ((dev_config & I2C_MODE_CONTROLLER) != I2C_MODE_CONTROLLER) {
return -ENOTSUP;
}
/* We are not supporting 10-bit addressing */
if ((dev_config & I2C_ADDR_10_BITS) == I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
/* Use recommended value for 100 kHz bus */
cdf = RCAR_I2C_ICCCR_CDF_100_KHZ;
scgd = RCAR_I2C_ICCCR_SCGD_100_KHZ;
break;
case I2C_SPEED_FAST:
/* Use recommended value for 400 kHz bus */
cdf = RCAR_I2C_ICCCR_CDF_400_KHZ;
scgd = RCAR_I2C_ICCCR_SCGD_400_KHZ;
break;
default:
return -ENOTSUP;
}
/* Setting ICCCR to recommended value */
i2c_rcar_write(config, RCAR_I2C_ICCCR, (scgd << 3) | cdf);
/* Reset slave mode */
i2c_rcar_write(config, RCAR_I2C_ICSIER, 0);
i2c_rcar_write(config, RCAR_I2C_ICSAR, 0);
i2c_rcar_write(config, RCAR_I2C_ICSCR, 0);
i2c_rcar_write(config, RCAR_I2C_ICSSR, 0);
/* Reset master mode */
i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
i2c_rcar_write(config, RCAR_I2C_ICMCR, 0);
i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
i2c_rcar_write(config, RCAR_I2C_ICMAR, 0);
return 0;
}
static int i2c_rcar_init(const struct device *dev)
{
const struct i2c_rcar_cfg *config = dev->config;
struct i2c_rcar_data *data = dev->data;
uint32_t bitrate_cfg;
int ret;
k_sem_init(&data->int_sem, 0, 1);
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t)&config->mod_clk);
if (ret != 0) {
return ret;
}
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
ret = i2c_rcar_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret != 0) {
return ret;
}
config->init_func(dev);
return 0;
}
static const struct i2c_driver_api i2c_rcar_driver_api = {
.configure = i2c_rcar_configure,
.transfer = i2c_rcar_transfer,
};
/* Device Instantiation */
#define I2C_RCAR_INIT(n) \
static void i2c_rcar_##n##_init(const struct device *dev); \
static const struct i2c_rcar_cfg i2c_rcar_cfg_##n = { \
.reg_addr = DT_INST_REG_ADDR(n), \
.init_func = i2c_rcar_##n##_init, \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.mod_clk.module = \
DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
.mod_clk.domain = \
DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
}; \
\
static struct i2c_rcar_data i2c_rcar_data_##n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, \
i2c_rcar_init, \
NULL, \
&i2c_rcar_data_##n, \
&i2c_rcar_cfg_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_rcar_driver_api \
); \
static void i2c_rcar_##n##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
0, \
i2c_rcar_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_RCAR_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_rcar.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,622 |
```unknown
config I2C_GD32
bool "GigaDevice GD32 I2C driver"
default y
depends on DT_HAS_GD_GD32_I2C_ENABLED
help
Enables GigaDevice GD32 I2C driver
``` | /content/code_sandbox/drivers/i2c/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_sc18im704_i2c
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_sc18im, CONFIG_I2C_LOG_LEVEL);
#include "i2c_sc18im704.h"
struct i2c_sc18im_config {
const struct device *bus;
uint32_t bus_speed;
const struct gpio_dt_spec reset_gpios;
};
struct i2c_sc18im_data {
struct k_mutex lock;
uint32_t i2c_config;
};
int sc18im704_claim(const struct device *dev)
{
struct i2c_sc18im_data *data = dev->data;
return k_mutex_lock(&data->lock, K_FOREVER);
}
int sc18im704_release(const struct device *dev)
{
struct i2c_sc18im_data *data = dev->data;
return k_mutex_unlock(&data->lock);
}
int sc18im704_transfer(const struct device *dev,
const uint8_t *tx_data, uint8_t tx_len,
uint8_t *rx_data, uint8_t rx_len)
{
const struct i2c_sc18im_config *cfg = dev->config;
struct i2c_sc18im_data *data = dev->data;
int ret = 0;
ret = k_mutex_lock(&data->lock, K_FOREVER);
if (ret < 0) {
return ret;
}
if (tx_data != NULL) {
for (uint8_t i = 0; i < tx_len; ++i) {
uart_poll_out(cfg->bus, tx_data[i]);
}
}
if (rx_data != NULL) {
k_timepoint_t end;
for (uint8_t i = 0; i < rx_len && ret == 0; ++i) {
/* Make sure we don't wait forever */
end = sys_timepoint_calc(K_SECONDS(1));
do {
ret = uart_poll_in(cfg->bus, &rx_data[i]);
} while (ret == -1 && !sys_timepoint_expired(end));
}
/* -1 indicates we timed out */
ret = ret == -1 ? -EAGAIN : ret;
if (ret < 0) {
LOG_ERR("Failed to read data (%d)", ret);
}
}
k_mutex_unlock(&data->lock);
return ret;
}
static int i2c_sc18im_configure(const struct device *dev, uint32_t config)
{
struct i2c_sc18im_data *data = dev->data;
if (!(I2C_MODE_CONTROLLER & config)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & config) {
return -EINVAL;
}
if (I2C_SPEED_GET(config) != I2C_SPEED_GET(data->i2c_config)) {
uint8_t buf[] = {
SC18IM704_CMD_WRITE_REG,
SC18IM704_REG_I2C_CLK_L,
0,
SC18IM704_CMD_STOP,
};
int ret;
/* CLK value is calculated as 15000000 / (8 * freq), see datasheet */
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
buf[2] = 0x13; /* 99 kHz */
break;
case I2C_SPEED_FAST:
buf[2] = 0x05; /* 375 kHz */
break;
default:
return -EINVAL;
}
ret = sc18im704_transfer(dev, buf, sizeof(buf), NULL, 0);
if (ret < 0) {
LOG_ERR("Failed to set I2C speed (%d)", ret);
return -EIO;
}
}
data->i2c_config = config;
return 0;
}
static int i2c_sc18im_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_sc18im_data *data = dev->data;
*config = data->i2c_config;
return 0;
}
static int i2c_sc18im_transfer_msg(const struct device *dev,
struct i2c_msg *msg,
uint16_t addr)
{
uint8_t start[] = {
SC18IM704_CMD_I2C_START,
0x00,
0x00,
};
uint8_t stop = SC18IM704_CMD_STOP;
int ret;
if (msg->flags & I2C_MSG_ADDR_10_BITS || msg->len > UINT8_MAX) {
return -EINVAL;
}
start[1] = addr | (msg->flags & I2C_MSG_RW_MASK);
start[2] = msg->len;
ret = sc18im704_transfer(dev, start, sizeof(start), NULL, 0);
if (ret < 0) {
return ret;
}
if (msg->flags & I2C_MSG_READ) {
/* Send the stop character before reading */
ret = sc18im704_transfer(dev, &stop, 1, msg->buf, msg->len);
if (ret < 0) {
return ret;
}
} else {
ret = sc18im704_transfer(dev, msg->buf, msg->len, NULL, 0);
if (ret < 0) {
return ret;
}
if (msg->flags & I2C_MSG_STOP) {
ret = sc18im704_transfer(dev, &stop, 1, NULL, 0);
if (ret < 0) {
return ret;
}
}
}
return 0;
}
static int i2c_sc18im_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
int ret;
if (num_msgs == 0) {
return 0;
}
ret = sc18im704_claim(dev);
if (ret < 0) {
LOG_ERR("Failed to claim I2C bridge (%d)", ret);
return ret;
}
for (uint8_t i = 0; i < num_msgs && ret == 0; ++i) {
ret = i2c_sc18im_transfer_msg(dev, &msgs[i], addr);
}
#ifdef CONFIG_I2C_SC18IM704_VERIFY
if (ret == 0) {
uint8_t buf[] = {
SC18IM704_CMD_READ_REG,
SC18IM704_REG_I2C_STAT,
SC18IM704_CMD_STOP,
};
uint8_t data;
ret = sc18im704_transfer(dev, buf, sizeof(buf), &data, 1);
if (ret == 0 && data != SC18IM704_I2C_STAT_OK) {
ret = -EIO;
}
}
#endif /* CONFIG_I2C_SC18IM704_VERIFY */
sc18im704_release(dev);
return ret;
}
static int i2c_sc18im_init(const struct device *dev)
{
const struct i2c_sc18im_config *cfg = dev->config;
struct i2c_sc18im_data *data = dev->data;
int ret;
/* The device baudrate after reset is 9600 */
struct uart_config uart_cfg = {
.baudrate = 9600,
.parity = UART_CFG_PARITY_NONE,
.stop_bits = UART_CFG_STOP_BITS_1,
.data_bits = UART_CFG_DATA_BITS_8,
.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,
};
k_mutex_init(&data->lock);
if (!device_is_ready(cfg->bus)) {
LOG_ERR("UART bus not ready");
return -ENODEV;
}
ret = uart_configure(cfg->bus, &uart_cfg);
if (ret < 0) {
LOG_ERR("Failed to configure UART (%d)", ret);
return ret;
}
if (cfg->reset_gpios.port) {
uint8_t buf[2];
if (!gpio_is_ready_dt(&cfg->reset_gpios)) {
LOG_ERR("Reset GPIO device not ready");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->reset_gpios, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Failed to configure reset GPIO (%d)", ret);
return ret;
}
ret = gpio_pin_set_dt(&cfg->reset_gpios, 0);
if (ret < 0) {
LOG_ERR("Failed to set reset GPIO (%d)", ret);
return ret;
}
/* The device sends "OK" */
ret = sc18im704_transfer(dev, NULL, 0, buf, sizeof(buf));
if (ret < 0) {
LOG_ERR("Failed to get OK (%d)", ret);
return ret;
}
}
if (cfg->bus_speed != 9600) {
uint16_t brg = (7372800 / cfg->bus_speed) - 16;
uint8_t buf[] = {
SC18IM704_CMD_WRITE_REG,
SC18IM704_REG_BRG0,
brg & 0xff,
SC18IM704_REG_BRG1,
brg >> 8,
SC18IM704_CMD_STOP,
};
ret = sc18im704_transfer(dev, buf, sizeof(buf), NULL, 0);
if (ret < 0) {
LOG_ERR("Failed to set baudrate (%d)", ret);
return ret;
}
/* Make sure UART buffer is sent */
k_msleep(1);
/* Re-configure the UART controller with the new baudrate */
uart_cfg.baudrate = cfg->bus_speed;
ret = uart_configure(cfg->bus, &uart_cfg);
if (ret < 0) {
LOG_ERR("Failed to re-configure UART (%d)", ret);
return ret;
}
}
return 0;
}
static const struct i2c_driver_api i2c_sc18im_driver_api = {
.configure = i2c_sc18im_configure,
.get_config = i2c_sc18im_get_config,
.transfer = i2c_sc18im_transfer,
};
#define I2C_SC18IM_DEFINE(n) \
\
static const struct i2c_sc18im_config i2c_sc18im_config_##n = { \
.bus = DEVICE_DT_GET(DT_BUS(DT_INST_PARENT(n))), \
.bus_speed = DT_PROP_OR(DT_INST_PARENT(n), target_speed, 9600), \
.reset_gpios = GPIO_DT_SPEC_GET_OR(DT_INST_PARENT(n), reset_gpios, {0}), \
}; \
static struct i2c_sc18im_data i2c_sc18im_data_##n = { \
.i2c_config = I2C_MODE_CONTROLLER | (I2C_SPEED_STANDARD << I2C_SPEED_SHIFT), \
}; \
\
DEVICE_DT_INST_DEFINE(n, i2c_sc18im_init, NULL, \
&i2c_sc18im_data_##n, &i2c_sc18im_config_##n, \
POST_KERNEL, CONFIG_I2C_SC18IM704_INIT_PRIORITY, \
&i2c_sc18im_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_SC18IM_DEFINE)
``` | /content/code_sandbox/drivers/i2c/i2c_sc18im704.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,521 |
```c
/*
*
*/
#define DT_DRV_COMPAT ene_kb1200_i2c
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <errno.h>
#include <reg/fsmbm.h>
struct i2c_kb1200_config {
struct fsmbm_regs *fsmbm;
const struct pinctrl_dev_config *pcfg;
};
struct i2c_kb1200_data {
struct k_sem mutex;
volatile uint8_t *msg_buf;
volatile uint32_t msg_len;
volatile uint8_t msg_flags;
volatile int state;
volatile uint32_t index;
volatile int err_code;
};
/* I2C Master local functions */
static void i2c_kb1200_isr(const struct device *dev)
{
const struct i2c_kb1200_config *config = dev->config;
struct i2c_kb1200_data *data = dev->data;
if (data->state == STATE_SENDING) {
if (config->fsmbm->FSMBMPF & FSMBM_BLOCK_FINISH_EVENT) {
/* continue block */
uint32_t remain = data->msg_len - data->index;
uint32_t send_bytes =
remain > FSMBM_BUFFER_SIZE ? FSMBM_BUFFER_SIZE : remain;
memcpy((void *)&config->fsmbm->FSMBMDAT[0],
(void *)&data->msg_buf[data->index], send_bytes);
data->index += send_bytes;
/* Increase CNT setting let hw can't match counter */
config->fsmbm->FSMBMPRTC_C += send_bytes;
/* If it was the last protocol recover the correct length value*/
if (data->msg_len == data->index) {
config->fsmbm->FSMBMPRTC_C -= 1;
}
config->fsmbm->FSMBMPF = FSMBM_BLOCK_FINISH_EVENT;
} else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) {
/* complete */
if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) &&
((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) {
/* while packet finish without STOP, the error message is
* FSMBM_SMBUS_BUSY
*/
data->err_code = 0;
} else {
data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
}
data->state = STATE_COMPLETE;
config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT;
} else {
data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
data->state = STATE_COMPLETE;
}
} else if (data->state == STATE_RECEIVING) {
uint32_t remain = data->msg_len - data->index;
uint32_t receive_bytes = (remain > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : remain;
memcpy((void *)&data->msg_buf[data->index], (void *)&config->fsmbm->FSMBMDAT[0],
receive_bytes);
data->index += receive_bytes;
if (config->fsmbm->FSMBMPF & FSMBM_BLOCK_FINISH_EVENT) {
/* continue block */
/* Check next protocl information */
remain = data->msg_len - data->index;
uint32_t NextLen =
(remain > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : remain;
/* Increase CNT setting let hw can't match counter */
config->fsmbm->FSMBMPRTC_C += NextLen;
/* If it was the last protocol recover the correct length value */
if (data->msg_len == (data->index + NextLen)) {
config->fsmbm->FSMBMPRTC_C -= 1;
}
config->fsmbm->FSMBMPF = FSMBM_BLOCK_FINISH_EVENT;
} else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) {
/* complete */
if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) &&
((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) {
/* while packet finish without STOP, the error message is
* FSMBM_SMBUS_BUSY
*/
data->err_code = 0;
} else {
data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
}
data->state = STATE_COMPLETE;
config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT;
} else {
data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
data->state = STATE_COMPLETE;
}
} else if (data->state == STATE_COMPLETE) {
config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
}
}
static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, uint16_t addr)
{
const struct i2c_kb1200_config *config = dev->config;
struct i2c_kb1200_data *data = dev->data;
uint8_t send_bytes;
if (msg.flags & I2C_MSG_STOP) {
/* No CMD, No CNT, No PEC, with STOP*/
config->fsmbm->FSMBMFRT = ___STOP;
} else {
/* No CMD, No CNT, No PEC, no STOP*/
config->fsmbm->FSMBMFRT = ___NONE;
}
data->msg_len = msg.len;
data->msg_buf = msg.buf;
data->msg_flags = msg.flags;
data->state = STATE_IDLE;
data->index = 0;
data->err_code = 0;
send_bytes = (msg.len > FSMBM_BUFFER_SIZE) ? FSMBM_BUFFER_SIZE : msg.len;
memcpy((void *)&config->fsmbm->FSMBMDAT[0], (void *)&data->msg_buf[data->index],
send_bytes);
data->index += send_bytes;
data->state = STATE_SENDING;
config->fsmbm->FSMBMCMD = 0;
config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_WRITE;
config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
/* If data over bufferSize increase 1 to force continue transmit */
if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) {
config->fsmbm->FSMBMPRTC_C = FSMBM_BUFFER_SIZE + 1;
} else {
config->fsmbm->FSMBMPRTC_C = send_bytes;
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
while (data->state != STATE_COMPLETE) {
;
}
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */
config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET;
return data->err_code;
}
return 0;
}
static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, uint16_t addr)
{
const struct i2c_kb1200_config *config = dev->config;
struct i2c_kb1200_data *data = dev->data;
if (msg.flags & I2C_MSG_STOP) {
/* No CMD, No CNT, No PEC, with STOP*/
config->fsmbm->FSMBMFRT = ___STOP;
} else {
/* No CMD, No CNT, No PEC, no STOP*/
config->fsmbm->FSMBMFRT = ___NONE;
}
data->msg_len = msg.len;
data->msg_buf = msg.buf;
data->msg_flags = msg.flags;
data->state = STATE_IDLE;
data->index = 0;
data->err_code = 0;
data->state = STATE_RECEIVING;
config->fsmbm->FSMBMCMD = 0;
config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_READ;
config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
/* If data over bufferSize increase 1 to force continue receive */
if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) {
config->fsmbm->FSMBMPRTC_C = FSMBM_BUFFER_SIZE + 1;
} else {
config->fsmbm->FSMBMPRTC_C = msg.len;
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
while (data->state != STATE_COMPLETE) {
;
}
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */
config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET;
return data->err_code;
}
return 0;
}
/* I2C Master api functions */
static int i2c_kb1200_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_kb1200_config *config = dev->config;
if (!(dev_config & I2C_MODE_CONTROLLER)) {
return -ENOTSUP;
}
if (dev_config & I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
uint32_t speed = I2C_SPEED_GET(dev_config);
switch (speed) {
case I2C_SPEED_STANDARD:
config->fsmbm->FSMBMCFG = (FSMBM_CLK_100K << FSMBM_CLK_POS);
break;
case I2C_SPEED_FAST:
config->fsmbm->FSMBMCFG = (FSMBM_CLK_400K << FSMBM_CLK_POS);
break;
case I2C_SPEED_FAST_PLUS:
config->fsmbm->FSMBMCFG = (FSMBM_CLK_1M << FSMBM_CLK_POS);
break;
default:
return -EINVAL;
}
config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
/* HW reset, Enable FSMBM function, Timeout function*/
config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET | FSMBM_TIMEOUT_ENABLE | FSMBM_FUNCTION_ENABLE;
return 0;
}
static int i2c_kb1200_get_config(const struct device *dev, uint32_t *dev_config)
{
const struct i2c_kb1200_config *config = dev->config;
if ((config->fsmbm->FSMBMCFG & FSMBM_FUNCTION_ENABLE) == 0x00) {
printk("Cannot find i2c controller on 0x%p!\n", config->fsmbm);
return -EIO;
}
switch ((config->fsmbm->FSMBMCFG >> FSMBM_CLK_POS) & FSMBM_CLK_MASK) {
case FSMBM_CLK_100K:
*dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_STANDARD);
break;
case FSMBM_CLK_400K:
*dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_FAST);
break;
case FSMBM_CLK_1M:
*dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_FAST_PLUS);
break;
default:
return -ERANGE;
}
return 0;
}
static int i2c_kb1200_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
struct i2c_kb1200_data *data = dev->data;
int ret;
/* get the mutex */
k_sem_take(&data->mutex, K_FOREVER);
for (int i = 0U; i < num_msgs; i++) {
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = i2c_kb1200_poll_write(dev, msgs[i], addr);
if (ret) {
printk("%s Write error: 0x%X\n", dev->name, ret);
break;
}
} else {
ret = i2c_kb1200_poll_read(dev, msgs[i], addr);
if (ret) {
printk("%s Read error: 0x%X\n", dev->name, ret);
break;
}
}
}
/* release the mutex */
k_sem_give(&data->mutex);
return ret;
}
/* I2C Master driver registration */
static const struct i2c_driver_api i2c_kb1200_api = {
.configure = i2c_kb1200_configure,
.get_config = i2c_kb1200_get_config,
.transfer = i2c_kb1200_transfer,
};
#define KB1200_FSMBM_DEV(inst) DEVICE_DT_INST_GET(inst),
static const struct device *const fsmbm_devices[] = {DT_INST_FOREACH_STATUS_OKAY(KB1200_FSMBM_DEV)};
static void i2c_kb1200_isr_wrap(void)
{
for (size_t i = 0; i < ARRAY_SIZE(fsmbm_devices); i++) {
const struct device *dev_ = fsmbm_devices[i];
const struct i2c_kb1200_config *config = dev_->config;
if (config->fsmbm->FSMBMIE & config->fsmbm->FSMBMPF) {
i2c_kb1200_isr(dev_);
}
}
}
static bool init_irq = true;
static void kb1200_fsmbm_irq_init(void)
{
if (init_irq) {
init_irq = false;
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), i2c_kb1200_isr_wrap, NULL,
0);
irq_enable(DT_INST_IRQN(0));
}
}
static int i2c_kb1200_init(const struct device *dev)
{
int ret;
const struct i2c_kb1200_config *config = dev->config;
struct i2c_kb1200_data *data = dev->data;
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
return ret;
}
/* init mutex */
k_sem_init(&data->mutex, 1, 1);
kb1200_fsmbm_irq_init();
return 0;
}
#define I2C_KB1200_DEVICE(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
static struct i2c_kb1200_data i2c_kb1200_data_##inst; \
static const struct i2c_kb1200_config i2c_kb1200_config_##inst = { \
.fsmbm = (struct fsmbm_regs *)DT_INST_REG_ADDR(inst), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, &i2c_kb1200_init, NULL, &i2c_kb1200_data_##inst, \
&i2c_kb1200_config_##inst, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_kb1200_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_KB1200_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_ene_kb1200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,524 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_i2c
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_litex, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#include "i2c_bitbang.h"
#include <soc.h>
#define SCL_BIT_POS 0
#define SDA_DIR_BIT_POS 1
#define SDA_BIT_W_POS 2
#define SDA_BIT_R_POS 0
#define SDA_DIR_OUTPUT 1
#define SDA_DIR_INPUT 0
#define HIGH_STATE_ON_I2C_LINES 0x7
struct i2c_litex_cfg {
uint32_t write_addr;
uint32_t read_addr;
uint32_t bitrate;
};
#define GET_I2C_CFG(dev) \
((const struct i2c_litex_cfg *) dev->config)
#define GET_I2C_BITBANG(dev) \
((struct i2c_bitbang *) dev->data)
static inline void set_bit(uint32_t addr, uint32_t bit, uint32_t val)
{
uint32_t mask = BIT(bit);
if (val) {
litex_write8(litex_read8(addr) | mask, addr);
} else {
litex_write8(litex_read8(addr) & ~mask, addr);
}
}
static inline int get_bit(uint32_t addr, uint32_t bit)
{
uint32_t mask = BIT(bit);
return !!(litex_read8(addr) & mask);
}
static void i2c_litex_bitbang_set_scl(void *context, int state)
{
const struct i2c_litex_cfg *config =
(const struct i2c_litex_cfg *) context;
set_bit(config->write_addr, SCL_BIT_POS, state);
}
static void i2c_litex_bitbang_set_sda(void *context, int state)
{
const struct i2c_litex_cfg *config =
(const struct i2c_litex_cfg *) context;
set_bit(config->write_addr, SDA_DIR_BIT_POS, SDA_DIR_OUTPUT);
set_bit(config->write_addr, SDA_BIT_W_POS, state);
}
static int i2c_litex_bitbang_get_sda(void *context)
{
const struct i2c_litex_cfg *config =
(const struct i2c_litex_cfg *) context;
set_bit(config->write_addr, SDA_DIR_BIT_POS, SDA_DIR_INPUT);
return get_bit(config->read_addr, SDA_BIT_R_POS);
}
static const struct i2c_bitbang_io i2c_litex_bitbang_io = {
.set_scl = i2c_litex_bitbang_set_scl,
.set_sda = i2c_litex_bitbang_set_sda,
.get_sda = i2c_litex_bitbang_get_sda,
};
static int i2c_litex_init(const struct device *dev)
{
const struct i2c_litex_cfg *config = GET_I2C_CFG(dev);
struct i2c_bitbang *bitbang = GET_I2C_BITBANG(dev);
int ret;
litex_write8(litex_read8(config->write_addr) | HIGH_STATE_ON_I2C_LINES, config->write_addr);
i2c_bitbang_init(bitbang, &i2c_litex_bitbang_io, (void *)config);
ret = i2c_bitbang_configure(bitbang,
I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
if (ret != 0) {
LOG_ERR("failed to configure I2C bitbang: %d", ret);
}
return ret;
}
static int i2c_litex_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_bitbang *bitbang = GET_I2C_BITBANG(dev);
return i2c_bitbang_configure(bitbang, dev_config);
}
static int i2c_litex_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_bitbang *bitbang = GET_I2C_BITBANG(dev);
return i2c_bitbang_get_config(bitbang, config);
}
static int i2c_litex_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_bitbang *bitbang = GET_I2C_BITBANG(dev);
return i2c_bitbang_transfer(bitbang, msgs, num_msgs, addr);
}
static int i2c_litex_recover_bus(const struct device *dev)
{
struct i2c_bitbang *bitbang = GET_I2C_BITBANG(dev);
return i2c_bitbang_recover_bus(bitbang);
}
static const struct i2c_driver_api i2c_litex_driver_api = {
.configure = i2c_litex_configure,
.get_config = i2c_litex_get_config,
.transfer = i2c_litex_transfer,
.recover_bus = i2c_litex_recover_bus,
};
/* Device Instantiation */
#define I2C_LITEX_INIT(n) \
static const struct i2c_litex_cfg i2c_litex_cfg_##n = { \
.write_addr = DT_INST_REG_ADDR_BY_NAME(n, write), \
.read_addr = DT_INST_REG_ADDR_BY_NAME(n, read), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct i2c_bitbang i2c_bitbang_##n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, \
i2c_litex_init, \
NULL, \
&i2c_bitbang_##n, \
&i2c_litex_cfg_##n, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_litex_driver_api \
);
DT_INST_FOREACH_STATUS_OKAY(I2C_LITEX_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,298 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_i2c
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include "i2c_lpc11u6x.h"
#define DEV_BASE(dev) (((struct lpc11u6x_i2c_config *)(dev->config))->base)
static void lpc11u6x_i2c_set_bus_speed(const struct lpc11u6x_i2c_config *cfg,
const struct device *clk_dev,
uint32_t speed)
{
uint32_t clk, div;
clock_control_get_rate(clk_dev, (clock_control_subsys_t) cfg->clkid,
&clk);
div = clk / speed;
cfg->base->sclh = div / 2;
cfg->base->scll = div - (div / 2);
}
static int lpc11u6x_i2c_configure(const struct device *dev,
uint32_t dev_config)
{
const struct lpc11u6x_i2c_config *cfg = dev->config;
struct lpc11u6x_i2c_data *data = dev->data;
uint32_t speed;
int ret;
uint8_t mux_selection = PINCTRL_STATE_DEFAULT;
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
speed = 100000;
break;
case I2C_SPEED_FAST:
speed = 400000;
break;
case I2C_SPEED_FAST_PLUS:
mux_selection = PINCTRL_STATE_FAST_PLUS;
speed = 1000000;
break;
case I2C_SPEED_HIGH:
case I2C_SPEED_ULTRA:
return -ENOTSUP;
default:
return -EINVAL;
}
if (dev_config & I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
k_mutex_lock(&data->mutex, K_FOREVER);
lpc11u6x_i2c_set_bus_speed(cfg, cfg->clock_dev, speed);
ret = pinctrl_apply_state(cfg->pincfg, mux_selection);
if (ret) {
k_mutex_unlock(&data->mutex);
return ret;
}
k_mutex_unlock(&data->mutex);
return 0;
}
static int lpc11u6x_i2c_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct lpc11u6x_i2c_config *cfg = dev->config;
struct lpc11u6x_i2c_data *data = dev->data;
int ret = 0;
if (!num_msgs) {
return 0;
}
k_mutex_lock(&data->mutex, K_FOREVER);
data->transfer.msgs = msgs;
data->transfer.curr_buf = msgs->buf;
data->transfer.curr_len = msgs->len;
data->transfer.nr_msgs = num_msgs;
data->transfer.addr = addr;
/* Reset all control bits */
cfg->base->con_clr = LPC11U6X_I2C_CONTROL_SI |
LPC11U6X_I2C_CONTROL_STOP | LPC11U6X_I2C_CONTROL_START;
/* Send start and wait for completion */
data->transfer.status = LPC11U6X_I2C_STATUS_BUSY;
cfg->base->con_set = LPC11U6X_I2C_CONTROL_START;
k_sem_take(&data->completion, K_FOREVER);
if (data->transfer.status != LPC11U6X_I2C_STATUS_OK) {
ret = -EIO;
}
data->transfer.status = LPC11U6X_I2C_STATUS_INACTIVE;
/* If a slave is registered, put the controller in slave mode */
if (data->slave) {
cfg->base->con_set = LPC11U6X_I2C_CONTROL_AA;
}
k_mutex_unlock(&data->mutex);
return ret;
}
static int lpc11u6x_i2c_slave_register(const struct device *dev,
struct i2c_target_config *cfg)
{
const struct lpc11u6x_i2c_config *dev_cfg = dev->config;
struct lpc11u6x_i2c_data *data = dev->data;
int ret = 0;
if (!cfg) {
return -EINVAL;
}
if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -ENOTSUP;
}
k_mutex_lock(&data->mutex, K_FOREVER);
if (data->slave) {
ret = -EBUSY;
goto exit;
}
data->slave = cfg;
/* Configure controller to act as slave */
dev_cfg->base->addr0 = (cfg->address << 1);
dev_cfg->base->con_clr = LPC11U6X_I2C_CONTROL_START |
LPC11U6X_I2C_CONTROL_STOP | LPC11U6X_I2C_CONTROL_SI;
dev_cfg->base->con_set = LPC11U6X_I2C_CONTROL_AA;
exit:
k_mutex_unlock(&data->mutex);
return ret;
}
static int lpc11u6x_i2c_slave_unregister(const struct device *dev,
struct i2c_target_config *cfg)
{
const struct lpc11u6x_i2c_config *dev_cfg = dev->config;
struct lpc11u6x_i2c_data *data = dev->data;
if (!cfg) {
return -EINVAL;
}
if (data->slave != cfg) {
return -EINVAL;
}
k_mutex_lock(&data->mutex, K_FOREVER);
data->slave = NULL;
dev_cfg->base->con_clr = LPC11U6X_I2C_CONTROL_AA;
k_mutex_unlock(&data->mutex);
return 0;
}
static void lpc11u6x_i2c_isr(const struct device *dev)
{
struct lpc11u6x_i2c_data *data = dev->data;
struct lpc11u6x_i2c_regs *i2c = DEV_BASE(dev);
struct lpc11u6x_i2c_current_transfer *transfer = &data->transfer;
uint32_t clear = LPC11U6X_I2C_CONTROL_SI;
uint32_t set = 0;
uint8_t val;
switch (i2c->stat) {
/* Master TX states */
case LPC11U6X_I2C_MASTER_TX_START:
case LPC11U6X_I2C_MASTER_TX_RESTART:
i2c->dat = (transfer->addr << 1) |
(transfer->msgs->flags & I2C_MSG_READ);
clear |= LPC11U6X_I2C_CONTROL_START;
transfer->curr_buf = transfer->msgs->buf;
transfer->curr_len = transfer->msgs->len;
break;
case LPC11U6X_I2C_MASTER_TX_ADR_ACK:
case LPC11U6X_I2C_MASTER_TX_DAT_ACK:
if (!transfer->curr_len) {
transfer->msgs++;
transfer->nr_msgs--;
if (!transfer->nr_msgs) {
transfer->status = LPC11U6X_I2C_STATUS_OK;
set |= LPC11U6X_I2C_CONTROL_STOP;
} else {
set |= LPC11U6X_I2C_CONTROL_START;
}
} else {
i2c->dat = transfer->curr_buf[0];
transfer->curr_buf++;
transfer->curr_len--;
}
break;
/* Master RX states */
case LPC11U6X_I2C_MASTER_RX_DAT_NACK:
transfer->msgs++;
transfer->nr_msgs--;
set |= (transfer->nr_msgs ? LPC11U6X_I2C_CONTROL_START :
LPC11U6X_I2C_CONTROL_STOP);
if (!transfer->nr_msgs) {
transfer->status = LPC11U6X_I2C_STATUS_OK;
}
__fallthrough;
case LPC11U6X_I2C_MASTER_RX_DAT_ACK:
transfer->curr_buf[0] = i2c->dat;
transfer->curr_buf++;
transfer->curr_len--;
__fallthrough;
case LPC11U6X_I2C_MASTER_RX_ADR_ACK:
if (transfer->curr_len <= 1) {
clear |= LPC11U6X_I2C_CONTROL_AA;
} else {
set |= LPC11U6X_I2C_CONTROL_AA;
}
break;
/* Slave States */
case LPC11U6X_I2C_SLAVE_RX_ADR_ACK:
case LPC11U6X_I2C_SLAVE_RX_ARB_LOST_ADR_ACK:
case LPC11U6X_I2C_SLAVE_RX_GC_ACK:
case LPC11U6X_I2C_SLAVE_RX_ARB_LOST_GC_ACK:
if (data->slave->callbacks->write_requested(data->slave)) {
clear |= LPC11U6X_I2C_CONTROL_AA;
}
break;
case LPC11U6X_I2C_SLAVE_RX_DAT_ACK:
case LPC11U6X_I2C_SLAVE_RX_GC_DAT_ACK:
val = i2c->dat;
if (data->slave->callbacks->write_received(data->slave, val)) {
clear |= LPC11U6X_I2C_CONTROL_AA;
}
break;
case LPC11U6X_I2C_SLAVE_RX_DAT_NACK:
case LPC11U6X_I2C_SLAVE_RX_GC_DAT_NACK:
val = i2c->dat;
data->slave->callbacks->write_received(data->slave, val);
data->slave->callbacks->stop(data->slave);
set |= LPC11U6X_I2C_CONTROL_AA;
break;
case LPC11U6X_I2C_SLAVE_RX_STOP:
data->slave->callbacks->stop(data->slave);
set |= LPC11U6X_I2C_CONTROL_AA;
break;
case LPC11U6X_I2C_SLAVE_TX_ADR_ACK:
case LPC11U6X_I2C_SLAVE_TX_ARB_LOST_ADR_ACK:
if (data->slave->callbacks->read_requested(data->slave, &val)) {
clear |= LPC11U6X_I2C_CONTROL_AA;
}
i2c->dat = val;
break;
case LPC11U6X_I2C_SLAVE_TX_DAT_ACK:
if (data->slave->callbacks->read_processed(data->slave, &val)) {
clear |= LPC11U6X_I2C_CONTROL_AA;
}
i2c->dat = val;
break;
case LPC11U6X_I2C_SLAVE_TX_DAT_NACK:
case LPC11U6X_I2C_SLAVE_TX_LAST_BYTE:
data->slave->callbacks->stop(data->slave);
set |= LPC11U6X_I2C_CONTROL_AA;
break;
/* Error cases */
case LPC11U6X_I2C_MASTER_TX_ADR_NACK:
case LPC11U6X_I2C_MASTER_RX_ADR_NACK:
case LPC11U6X_I2C_MASTER_TX_DAT_NACK:
case LPC11U6X_I2C_MASTER_TX_ARB_LOST:
transfer->status = LPC11U6X_I2C_STATUS_FAIL;
set = LPC11U6X_I2C_CONTROL_STOP;
break;
default:
set = LPC11U6X_I2C_CONTROL_STOP;
break;
}
i2c->con_clr = clear;
i2c->con_set = set;
if ((transfer->status != LPC11U6X_I2C_STATUS_BUSY) &&
(transfer->status != LPC11U6X_I2C_STATUS_INACTIVE)) {
k_sem_give(&data->completion);
}
}
static int lpc11u6x_i2c_init(const struct device *dev)
{
const struct lpc11u6x_i2c_config *cfg = dev->config;
struct lpc11u6x_i2c_data *data = dev->data;
int err;
err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
if (!device_is_ready(cfg->clock_dev)) {
return -ENODEV;
}
/* Configure clock and de-assert reset for I2Cx */
clock_control_on(cfg->clock_dev, (clock_control_subsys_t) cfg->clkid);
/* Configure bus speed. Default is 100KHz */
lpc11u6x_i2c_set_bus_speed(cfg, cfg->clock_dev, 100000);
/* Clear all control bytes and enable I2C interface */
cfg->base->con_clr = LPC11U6X_I2C_CONTROL_AA | LPC11U6X_I2C_CONTROL_SI |
LPC11U6X_I2C_CONTROL_START | LPC11U6X_I2C_CONTROL_I2C_EN;
cfg->base->con_set = LPC11U6X_I2C_CONTROL_I2C_EN;
/* Initialize mutex and semaphore */
k_mutex_init(&data->mutex);
k_sem_init(&data->completion, 0, 1);
data->transfer.status = LPC11U6X_I2C_STATUS_INACTIVE;
/* Configure IRQ */
cfg->irq_config_func(dev);
return 0;
}
static const struct i2c_driver_api i2c_api = {
.configure = lpc11u6x_i2c_configure,
.transfer = lpc11u6x_i2c_transfer,
.target_register = lpc11u6x_i2c_slave_register,
.target_unregister = lpc11u6x_i2c_slave_unregister,
};
#define LPC11U6X_I2C_INIT(idx) \
\
static void lpc11u6x_i2c_isr_config_##idx(const struct device *dev); \
\
PINCTRL_DT_INST_DEFINE(idx); \
\
static const struct lpc11u6x_i2c_config i2c_cfg_##idx = { \
.base = \
(struct lpc11u6x_i2c_regs *) DT_INST_REG_ADDR(idx), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.irq_config_func = lpc11u6x_i2c_isr_config_##idx, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
.clkid = DT_INST_PHA_BY_IDX(idx, clocks, 0, clkid), \
}; \
\
static struct lpc11u6x_i2c_data i2c_data_##idx; \
\
I2C_DEVICE_DT_INST_DEFINE(idx, \
lpc11u6x_i2c_init, \
NULL, \
&i2c_data_##idx, &i2c_cfg_##idx, \
PRE_KERNEL_1, CONFIG_I2C_INIT_PRIORITY, \
&i2c_api); \
\
static void lpc11u6x_i2c_isr_config_##idx(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(idx), \
DT_INST_IRQ(idx, priority), \
lpc11u6x_i2c_isr, DEVICE_DT_INST_GET(idx), 0); \
\
irq_enable(DT_INST_IRQN(idx)); \
}
DT_INST_FOREACH_STATUS_OKAY(LPC11U6X_I2C_INIT);
``` | /content/code_sandbox/drivers/i2c/i2c_lpc11u6x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,353 |
```unknown
# Microchip XEC I2C configuration options
config I2C_XEC
bool "XEC Microchip I2C driver"
default y
depends on DT_HAS_MICROCHIP_XEC_I2C_ENABLED
help
Enable the Microchip XEC I2C driver.
config I2C_XEC_V2
bool "XEC Microchip I2C driver"
default y
depends on DT_HAS_MICROCHIP_XEC_I2C_V2_ENABLED
help
Enable the Microchip XEC I2C V2 driver.
``` | /content/code_sandbox/drivers/i2c/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```unknown
config I2C_IPROC
bool "Broadcom iProc I2C controller"
default y
depends on DT_HAS_BRCM_IPROC_I2C_ENABLED
help
Enable support for Broadcom iProc I2C controller.
``` | /content/code_sandbox/drivers/i2c/Kconfig.bcm_iproc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_
#define ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_
#include <zephyr/drivers/i2c/stm32.h>
#ifdef CONFIG_I2C_STM32_BUS_RECOVERY
#include <zephyr/drivers/gpio.h>
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
typedef void (*irq_config_func_t)(const struct device *port);
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
/**
* @brief structure to convey optional i2c timings settings
*/
struct i2c_config_timing {
/* i2c peripheral clock in Hz */
uint32_t periph_clock;
/* i2c bus speed in Hz */
uint32_t i2c_speed;
/* I2C_TIMINGR register value of i2c v2 peripheral */
uint32_t timing_setting;
};
#endif
struct i2c_stm32_config {
#ifdef CONFIG_I2C_STM32_INTERRUPT
irq_config_func_t irq_config_func;
#endif
#ifdef CONFIG_I2C_STM32_BUS_RECOVERY
struct gpio_dt_spec scl;
struct gpio_dt_spec sda;
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
const struct stm32_pclken *pclken;
size_t pclk_len;
I2C_TypeDef *i2c;
uint32_t bitrate;
const struct pinctrl_dev_config *pcfg;
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
const struct i2c_config_timing *timings;
size_t n_timings;
#endif
};
struct i2c_stm32_data {
#ifdef CONFIG_I2C_STM32_INTERRUPT
struct k_sem device_sync_sem;
#endif
struct k_sem bus_mutex;
uint32_t dev_config;
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
/* Store the current timing structure set by runtime config */
struct i2c_config_timing current_timing;
#endif
#ifdef CONFIG_I2C_STM32_V1
uint16_t slave_address;
#endif
struct {
#ifdef CONFIG_I2C_STM32_V1
unsigned int is_restart;
unsigned int flags;
#endif
unsigned int is_write;
unsigned int is_arlo;
unsigned int is_nack;
unsigned int is_err;
struct i2c_msg *msg;
unsigned int len;
uint8_t *buf;
} current;
#ifdef CONFIG_I2C_TARGET
bool master_active;
struct i2c_target_config *slave_cfg;
#ifdef CONFIG_I2C_STM32_V2
struct i2c_target_config *slave2_cfg;
#endif
bool slave_attached;
#endif
bool is_configured;
bool smbalert_active;
enum i2c_stm32_mode mode;
#ifdef CONFIG_SMBUS_STM32_SMBALERT
i2c_stm32_smbalert_cb_func_t smbalert_cb_func;
const struct device *smbalert_cb_dev;
#endif
};
int32_t stm32_i2c_transaction(const struct device *dev,
struct i2c_msg msg, uint8_t *next_msg_flags,
uint16_t periph);
int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clk);
int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config);
int i2c_stm32_get_config(const struct device *dev, uint32_t *config);
void stm32_i2c_event_isr(void *arg);
void stm32_i2c_error_isr(void *arg);
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
void stm32_i2c_combined_isr(void *arg);
#endif
#ifdef CONFIG_I2C_TARGET
int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config);
int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config);
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_ */
``` | /content/code_sandbox/drivers/i2c/i2c_ll_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 873 |
```unknown
# NPCX I2C driver configuration options
config I2C_NPCX
bool "Nuvoton NPCX embedded controller (EC) I2C driver"
default y
depends on DT_HAS_NUVOTON_NPCX_I2C_PORT_ENABLED
help
This option enables the I2C driver for NPCX family of
processors.
Say y if you wish to use I2C modules on NPCX MCU.
config I2C_NPCX_PORT_INIT_PRIORITY
int "NPCX I2C port init priority"
default 51
depends on I2C_NPCX
help
Initialization priority for the I2C port on an NPCX device, must be
set to a lower priority than the controller one (I2C_INIT_PRIORITY).
``` | /content/code_sandbox/drivers/i2c/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 163 |
```unknown
menuconfig I2C_DW
bool "Design Ware I2C support"
default y
depends on DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED
help
Enable the Design Ware I2C driver
config I2C_DW_CLOCK_SPEED
int "Set the clock speed for I2C"
depends on I2C_DW
default 32
config I2C_DW_LPSS_DMA
bool "Use I2C integrated DMA for asynchronous transfer"
depends on I2C_DW
select DMA
select DMA_INTEL_LPSS
help
This option enables I2C DMA feature to be used for asynchronous
data transfers. All Tx operations are done using dma channel 0 and
all Rx operations are done using dma channel 1.
config I2C_DW_RW_TIMEOUT_MS
int "Set the Read/Write timeout in milliseconds"
depends on I2C_DW
default 100
``` | /content/code_sandbox/drivers/i2c/Kconfig.dw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```c
/*
*
*/
#define DT_DRV_COMPAT ambiq_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/pm/device_runtime.h>
#include <am_mcu_apollo.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/pinctrl.h>
LOG_MODULE_REGISTER(ambiq_i2c, CONFIG_I2C_LOG_LEVEL);
typedef int (*ambiq_i2c_pwr_func_t)(void);
#define PWRCTRL_MAX_WAIT_US 5
#define I2C_TRANSFER_TIMEOUT_MSEC 500 /* Transfer timeout period */
#include "i2c-priv.h"
struct i2c_ambiq_config {
uint32_t base;
int size;
uint32_t bitrate;
const struct pinctrl_dev_config *pcfg;
ambiq_i2c_pwr_func_t pwr_func;
void (*irq_config_func)(void);
};
typedef void (*i2c_ambiq_callback_t)(const struct device *dev, int result, void *data);
struct i2c_ambiq_data {
am_hal_iom_config_t iom_cfg;
void *iom_handler;
struct k_sem bus_sem;
struct k_sem transfer_sem;
i2c_ambiq_callback_t callback;
void *callback_data;
int inst_idx;
uint32_t transfer_status;
};
#ifdef CONFIG_I2C_AMBIQ_DMA
static __aligned(32) struct {
__aligned(32) uint32_t buf[CONFIG_I2C_DMA_TCB_BUFFER_SIZE];
} i2c_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __attribute__((__section__(".nocache")));
static void i2c_ambiq_callback(void *callback_ctxt, uint32_t status)
{
const struct device *dev = callback_ctxt;
struct i2c_ambiq_data *data = dev->data;
if (data->callback) {
data->callback(dev, status, data->callback_data);
}
data->transfer_status = status;
}
#endif
static void i2c_ambiq_isr(const struct device *dev)
{
uint32_t ui32Status;
struct i2c_ambiq_data *data = dev->data;
am_hal_iom_interrupt_status_get(data->iom_handler, false, &ui32Status);
am_hal_iom_interrupt_clear(data->iom_handler, ui32Status);
am_hal_iom_interrupt_service(data->iom_handler, ui32Status);
k_sem_give(&data->transfer_sem);
}
static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
{
struct i2c_ambiq_data *data = dev->data;
int ret = 0;
am_hal_iom_transfer_t trans = {0};
trans.ui8Priority = 1;
trans.eDirection = AM_HAL_IOM_RX;
trans.uPeerInfo.ui32I2CDevAddr = addr;
trans.ui32NumBytes = msg->len;
trans.pui32RxBuffer = (uint32_t *)msg->buf;
#ifdef CONFIG_I2C_AMBIQ_DMA
data->transfer_status = -EFAULT;
ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback,
(void *)dev);
if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) {
LOG_ERR("Timeout waiting for transfer complete");
/* cancel timed out transaction */
am_hal_iom_disable(data->iom_handler);
/* clean up for next xfer */
k_sem_reset(&data->transfer_sem);
am_hal_iom_enable(data->iom_handler);
return -ETIMEDOUT;
}
ret = data->transfer_status;
#else
ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
#endif
return (ret != AM_HAL_STATUS_SUCCESS) ? -EIO : 0;
}
static int i2c_ambiq_write(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
{
struct i2c_ambiq_data *data = dev->data;
int ret = 0;
am_hal_iom_transfer_t trans = {0};
trans.ui8Priority = 1;
trans.eDirection = AM_HAL_IOM_TX;
trans.uPeerInfo.ui32I2CDevAddr = addr;
trans.ui32NumBytes = msg->len;
trans.pui32TxBuffer = (uint32_t *)msg->buf;
#ifdef CONFIG_I2C_AMBIQ_DMA
data->transfer_status = -EFAULT;
ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback,
(void *)dev);
if (k_sem_take(&data->transfer_sem, K_MSEC(I2C_TRANSFER_TIMEOUT_MSEC))) {
LOG_ERR("Timeout waiting for transfer complete");
/* cancel timed out transaction */
am_hal_iom_disable(data->iom_handler);
/* clean up for next xfer */
k_sem_reset(&data->transfer_sem);
am_hal_iom_enable(data->iom_handler);
return -ETIMEDOUT;
}
ret = data->transfer_status;
#else
ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
#endif
return (ret != AM_HAL_STATUS_SUCCESS) ? -EIO : 0;
}
static int i2c_ambiq_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_ambiq_data *data = dev->data;
if (!(I2C_MODE_CONTROLLER & dev_config)) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
data->iom_cfg.ui32ClockFreq = AM_HAL_IOM_100KHZ;
break;
case I2C_SPEED_FAST:
data->iom_cfg.ui32ClockFreq = AM_HAL_IOM_400KHZ;
break;
case I2C_SPEED_FAST_PLUS:
data->iom_cfg.ui32ClockFreq = AM_HAL_IOM_1MHZ;
break;
default:
return -EINVAL;
}
#ifdef CONFIG_I2C_AMBIQ_DMA
data->iom_cfg.pNBTxnBuf = i2c_dma_tcb_buf[data->inst_idx].buf;
data->iom_cfg.ui32NBTxnBufLength = CONFIG_I2C_DMA_TCB_BUFFER_SIZE;
#endif
am_hal_iom_configure(data->iom_handler, &data->iom_cfg);
return 0;
}
static int i2c_ambiq_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
struct i2c_ambiq_data *data = dev->data;
int ret = 0;
if (!num_msgs) {
return 0;
}
ret = pm_device_runtime_get(dev);
if (ret < 0) {
LOG_ERR("pm_device_runtime_get failed: %d", ret);
}
/* Send out messages */
k_sem_take(&data->bus_sem, K_FOREVER);
for (int i = 0; i < num_msgs; i++) {
if (msgs[i].flags & I2C_MSG_READ) {
ret = i2c_ambiq_read(dev, &(msgs[i]), addr);
} else {
ret = i2c_ambiq_write(dev, &(msgs[i]), addr);
}
if (ret != 0) {
k_sem_give(&data->bus_sem);
return ret;
}
}
k_sem_give(&data->bus_sem);
/* Use async put to avoid useless device suspension/resumption
* when doing consecutive transmission.
*/
ret = pm_device_runtime_put_async(dev, K_MSEC(2));
if (ret < 0) {
LOG_ERR("pm_device_runtime_put failed: %d", ret);
}
return 0;
}
static int i2c_ambiq_init(const struct device *dev)
{
struct i2c_ambiq_data *data = dev->data;
const struct i2c_ambiq_config *config = dev->config;
uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
int ret = 0;
data->iom_cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE;
if (AM_HAL_STATUS_SUCCESS !=
am_hal_iom_initialize((config->base - IOM0_BASE) / config->size,
&data->iom_handler)) {
LOG_ERR("Fail to initialize I2C\n");
return -ENXIO;
}
ret = config->pwr_func();
ret |= i2c_ambiq_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret < 0) {
LOG_ERR("Fail to config I2C\n");
goto end;
}
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("Fail to config I2C pins\n");
goto end;
}
#ifdef CONFIG_I2C_AMBIQ_DMA
am_hal_iom_interrupt_clear(data->iom_handler, AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP);
am_hal_iom_interrupt_enable(data->iom_handler, AM_HAL_IOM_INT_DCMP | AM_HAL_IOM_INT_CMDCMP);
config->irq_config_func();
#endif
if (AM_HAL_STATUS_SUCCESS != am_hal_iom_enable(data->iom_handler)) {
LOG_ERR("Fail to enable I2C\n");
ret = -EIO;
}
end:
if (ret < 0) {
am_hal_iom_uninitialize(data->iom_handler);
}
return ret;
}
static const struct i2c_driver_api i2c_ambiq_driver_api = {
.configure = i2c_ambiq_configure,
.transfer = i2c_ambiq_transfer,
};
#ifdef CONFIG_PM_DEVICE
static int i2c_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
{
struct i2c_ambiq_data *data = dev->data;
uint32_t ret;
am_hal_sysctrl_power_state_e status;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
status = AM_HAL_SYSCTRL_WAKE;
break;
case PM_DEVICE_ACTION_SUSPEND:
status = AM_HAL_SYSCTRL_DEEPSLEEP;
break;
default:
return -ENOTSUP;
}
ret = am_hal_iom_power_ctrl(data->iom_handler, status, true);
if (ret != AM_HAL_STATUS_SUCCESS) {
return -EPERM;
} else {
return 0;
}
}
#endif /* CONFIG_PM_DEVICE */
#define AMBIQ_I2C_DEFINE(n) \
PINCTRL_DT_INST_DEFINE(n); \
static int pwr_on_ambiq_i2c_##n(void) \
{ \
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
k_busy_wait(PWRCTRL_MAX_WAIT_US); \
return 0; \
} \
static void i2c_irq_config_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_ambiq_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}; \
static struct i2c_ambiq_data i2c_ambiq_data##n = { \
.bus_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.bus_sem, 1, 1), \
.transfer_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.transfer_sem, 0, 1), \
.inst_idx = n, \
}; \
static const struct i2c_ambiq_config i2c_ambiq_config##n = { \
.base = DT_INST_REG_ADDR(n), \
.size = DT_INST_REG_SIZE(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.irq_config_func = i2c_irq_config_func_##n, \
.pwr_func = pwr_on_ambiq_i2c_##n}; \
PM_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_pm_action); \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_init, PM_DEVICE_DT_INST_GET(n), &i2c_ambiq_data##n, \
&i2c_ambiq_config##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_ambiq_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_I2C_DEFINE)
``` | /content/code_sandbox/drivers/i2c/i2c_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,846 |
```c
/*
*
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <nrfx_twi.h>
#include "i2c_nrfx_twi_common.h"
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_nrfx_twi, CONFIG_I2C_LOG_LEVEL);
#if CONFIG_I2C_NRFX_TRANSFER_TIMEOUT
#define I2C_TRANSFER_TIMEOUT_MSEC K_MSEC(CONFIG_I2C_NRFX_TRANSFER_TIMEOUT)
#else
#define I2C_TRANSFER_TIMEOUT_MSEC K_FOREVER
#endif
struct i2c_nrfx_twi_data {
uint32_t dev_config;
struct k_sem transfer_sync;
struct k_sem completion_sync;
volatile nrfx_err_t res;
};
/* Enforce dev_config matches the same offset as the common structure,
* otherwise common API won't be compatible with i2c_nrfx_twi.
*/
BUILD_ASSERT(
offsetof(struct i2c_nrfx_twi_data, dev_config) ==
offsetof(struct i2c_nrfx_twi_common_data, dev_config)
);
static int i2c_nrfx_twi_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct i2c_nrfx_twi_config *config = dev->config;
struct i2c_nrfx_twi_data *data = dev->data;
int ret = 0;
k_sem_take(&data->transfer_sync, K_FOREVER);
/* Dummy take on completion_sync sem to be sure that it is empty */
k_sem_take(&data->completion_sync, K_NO_WAIT);
nrfx_twi_enable(&config->twi);
for (size_t i = 0; i < num_msgs; i++) {
bool more_msgs = ((i < (num_msgs - 1)) &&
!(msgs[i + 1].flags & I2C_MSG_RESTART));
ret = i2c_nrfx_twi_msg_transfer(dev, msgs[i].flags,
msgs[i].buf,
msgs[i].len, addr,
more_msgs);
if (ret) {
break;
}
ret = k_sem_take(&data->completion_sync,
I2C_TRANSFER_TIMEOUT_MSEC);
if (ret != 0) {
/* Whatever the frequency, completion_sync should have
* been given by the event handler.
*
* If it hasn't, it's probably due to an hardware issue
* on the I2C line, for example a short between SDA and
* GND.
* This is issue has also been when trying to use the
* I2C bus during MCU internal flash erase.
*
* In many situation, a retry is sufficient.
* However, some time the I2C device get stuck and need
* help to recover.
* Therefore we always call i2c_nrfx_twi_recover_bus()
* to make sure everything has been done to restore the
* bus from this error.
*/
nrfx_twi_disable(&config->twi);
(void)i2c_nrfx_twi_recover_bus(dev);
ret = -EIO;
break;
}
if (data->res != NRFX_SUCCESS) {
ret = -EIO;
break;
}
}
nrfx_twi_disable(&config->twi);
k_sem_give(&data->transfer_sync);
return ret;
}
static void event_handler(nrfx_twi_evt_t const *p_event, void *p_context)
{
const struct device *dev = p_context;
struct i2c_nrfx_twi_data *dev_data = (struct i2c_nrfx_twi_data *)dev->data;
switch (p_event->type) {
case NRFX_TWI_EVT_DONE:
dev_data->res = NRFX_SUCCESS;
break;
case NRFX_TWI_EVT_ADDRESS_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_ANACK;
break;
case NRFX_TWI_EVT_DATA_NACK:
dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
break;
default:
dev_data->res = NRFX_ERROR_INTERNAL;
break;
}
k_sem_give(&dev_data->completion_sync);
}
static const struct i2c_driver_api i2c_nrfx_twi_driver_api = {
.configure = i2c_nrfx_twi_configure,
.transfer = i2c_nrfx_twi_transfer,
.recover_bus = i2c_nrfx_twi_recover_bus,
};
#define I2C_NRFX_TWI_DEVICE(idx) \
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(I2C(idx)); \
BUILD_ASSERT(I2C_FREQUENCY(idx) != \
I2C_NRFX_TWI_INVALID_FREQUENCY, \
"Wrong I2C " #idx " frequency setting in dts"); \
static int twi_##idx##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQN(I2C(idx)), DT_IRQ(I2C(idx), priority), \
nrfx_isr, nrfx_twi_##idx##_irq_handler, 0); \
const struct i2c_nrfx_twi_config *config = dev->config; \
int err = pinctrl_apply_state(config->pcfg, \
PINCTRL_STATE_DEFAULT); \
if (err < 0) { \
return err; \
} \
return i2c_nrfx_twi_init(dev); \
} \
static struct i2c_nrfx_twi_data twi_##idx##_data = { \
.transfer_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.transfer_sync, 1, 1), \
.completion_sync = Z_SEM_INITIALIZER( \
twi_##idx##_data.completion_sync, 0, 1) \
}; \
PINCTRL_DT_DEFINE(I2C(idx)); \
static const struct i2c_nrfx_twi_config twi_##idx##z_config = { \
.twi = NRFX_TWI_INSTANCE(idx), \
.config = { \
.skip_gpio_cfg = true, \
.skip_psel_cfg = true, \
.frequency = I2C_FREQUENCY(idx), \
}, \
.event_handler = event_handler, \
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(I2C(idx)), \
}; \
PM_DEVICE_DT_DEFINE(I2C(idx), twi_nrfx_pm_action); \
I2C_DEVICE_DT_DEFINE(I2C(idx), \
twi_##idx##_init, \
PM_DEVICE_DT_GET(I2C(idx)), \
&twi_##idx##_data, \
&twi_##idx##z_config, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_nrfx_twi_driver_api)
#ifdef CONFIG_HAS_HW_NRF_TWI0
I2C_NRFX_TWI_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_TWI1
I2C_NRFX_TWI_DEVICE(1);
#endif
``` | /content/code_sandbox/drivers/i2c/i2c_nrfx_twi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,640 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_enhance_i2c
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/policy.h>
#include <errno.h>
#include <soc.h>
#include <soc_dt.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_ite_enhance, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
/* Start smbus session from idle state */
#define I2C_MSG_START BIT(5)
#define I2C_LINE_SCL_HIGH BIT(0)
#define I2C_LINE_SDA_HIGH BIT(1)
#define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
/* Reserved 5 bytes for ID and CMD_x. */
#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
/* Repeat Start. */
#define I2C_CQ_CMD_L_RS BIT(7)
/*
* R/W (Read/ Write) decides the I2C read or write direction.
* 1: read, 0: write
*/
#define I2C_CQ_CMD_L_RW BIT(6)
/* P (STOP) is the I2C STOP condition. */
#define I2C_CQ_CMD_L_P BIT(5)
/* E (End) is this device end flag. */
#define I2C_CQ_CMD_L_E BIT(4)
/* LA (Last ACK) is Last ACK in master receiver. */
#define I2C_CQ_CMD_L_LA BIT(3)
/* bit[2:0] are number of transfer out or receive data which depends on R/W. */
#define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0)
struct i2c_cq_packet {
uint8_t id;
uint8_t cmd_l;
uint8_t cmd_h;
FLEXIBLE_ARRAY_DECLARE(uint8_t, wdata);
};
#endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
struct i2c_enhance_config {
void (*irq_config_func)(void);
uint32_t bitrate;
uint8_t *base;
uint8_t i2c_irq_base;
uint8_t port;
uint8_t channel_switch_sel;
/* SCL GPIO cells */
struct gpio_dt_spec scl_gpios;
/* SDA GPIO cells */
struct gpio_dt_spec sda_gpios;
/* I2C alternate configuration */
const struct pinctrl_dev_config *pcfg;
uint8_t prescale_scl_low;
uint8_t data_hold_time;
uint32_t clock_gate_offset;
bool target_enable;
bool target_pio_mode;
bool push_pull_recovery;
};
enum i2c_pin_fun {
SCL = 0,
SDA,
};
enum i2c_ch_status {
I2C_CH_NORMAL = 0,
I2C_CH_REPEAT_START,
I2C_CH_WAIT_READ,
I2C_CH_WAIT_NEXT_XFER,
};
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
struct i2c_host_cq_buffer {
/* Command queue tx payload. */
uint8_t i2c_cq_mode_tx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
/* Command queue rx payload. */
uint8_t i2c_cq_mode_rx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
};
#endif
#ifdef CONFIG_I2C_TARGET
/*
* When accessing data exceeds the maximum buffer, the actual reload address
* is one byte more than the maximum buffer size. Therefore, it is necessary to
* have a buffer in place to prevent overwriting other memory.
*/
#define PROTECT_MEM_BUF 4
struct i2c_target_dma_buffer {
/* Target mode DMA output buffer. */
uint8_t __aligned(4)
out_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
/* Target mode DMA input buffer. */
uint8_t __aligned(4)
in_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
};
#endif
struct i2c_enhance_data {
enum i2c_ch_status i2ccs;
struct i2c_msg *active_msg;
struct k_mutex mutex;
struct k_sem device_sync_sem;
/* Index into output data */
size_t widx;
/* Index into input data */
size_t ridx;
/* operation freq of i2c */
uint32_t bus_freq;
/* Error code, if any */
uint32_t err;
/* address of device */
uint16_t addr_16bit;
/* wait for stop bit interrupt */
uint8_t stop;
/* Number of messages. */
uint8_t num_msgs;
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
/* Store command queue mode messages. */
struct i2c_msg *cq_msgs;
#endif
#ifdef CONFIG_I2C_TARGET
struct i2c_target_config *target_cfg;
uint32_t buffer_size;
int target_nack;
bool target_attached;
#endif
union {
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
struct i2c_host_cq_buffer host_buffer;
#endif
#ifdef CONFIG_I2C_TARGET
struct i2c_target_dma_buffer target_buffer;
#endif
};
};
enum enhanced_i2c_transfer_direct {
TX_DIRECT,
RX_DIRECT,
};
enum enhanced_i2c_ctl {
/* Hardware reset */
E_HW_RST = 0x01,
/* Stop */
E_STOP = 0x02,
/* Start & Repeat start */
E_START = 0x04,
/* Acknowledge */
E_ACK = 0x08,
/* State reset */
E_STS_RST = 0x10,
/* Mode select */
E_MODE_SEL = 0x20,
/* I2C interrupt enable */
E_INT_EN = 0x40,
/* 0 : Standard mode , 1 : Receive mode */
E_RX_MODE = 0x80,
/* State reset and hardware reset */
E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
/* Generate start condition and transmit slave address */
E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
/* Generate stop condition */
E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
/* Start with command queue mode */
E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START),
};
enum enhanced_i2c_host_status {
/* ACK receive */
E_HOSTA_ACK = 0x01,
/* Interrupt pending */
E_HOSTA_INTP = 0x02,
/* Read/Write */
E_HOSTA_RW = 0x04,
/* Time out error */
E_HOSTA_TMOE = 0x08,
/* Arbitration lost */
E_HOSTA_ARB = 0x10,
/* Bus busy */
E_HOSTA_BB = 0x20,
/* Address match */
E_HOSTA_AM = 0x40,
/* Byte done status */
E_HOSTA_BDS = 0x80,
/* time out or lost arbitration */
E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
/* Byte transfer done and ACK receive */
E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
};
enum i2c_reset_cause {
I2C_RC_NO_IDLE_FOR_START = 1,
I2C_RC_TIMEOUT,
};
#ifdef CONFIG_I2C_TARGET
enum enhanced_i2c_target_status {
/* Time out error */
E_TARGET_TMOE = 0x08,
/* Arbitration lost */
E_TARGET_ARB = 0x10,
/* Time out or lost arbitration */
E_TARGET_ANY_ERROR = (E_TARGET_TMOE | E_TARGET_ARB),
};
#endif
static int i2c_parsing_return_value(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
if (!data->err) {
return 0;
}
/* Connection timed out */
if (data->err == ETIMEDOUT) {
return -ETIMEDOUT;
}
/* The device does not respond ACK */
if (data->err == E_HOSTA_ACK) {
return -ENXIO;
} else {
return -EIO;
}
}
static int i2c_get_line_levels(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
int pin_sts = 0;
if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) {
pin_sts |= I2C_LINE_SCL_HIGH;
}
if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) {
pin_sts |= I2C_LINE_SDA_HIGH;
}
return pin_sts;
}
static int i2c_is_busy(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
return (IT8XXX2_I2C_STR(base) & E_HOSTA_BB);
}
static int i2c_bus_not_available(const struct device *dev)
{
if (i2c_is_busy(dev) ||
(i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
return -EIO;
}
return 0;
}
static void i2c_reset(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
/* State reset and hardware reset */
IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
}
/* Set clock frequency for i2c port D, E , or F */
static void i2c_enhanced_port_set_frequency(const struct device *dev,
int freq_hz)
{
const struct i2c_enhance_config *config = dev->config;
uint32_t clk_div, psr, pll_clock, psr_h, psr_l;
uint8_t *base = config->base;
uint8_t prescale_scl = config->prescale_scl_low;
pll_clock = chip_get_pll_freq();
/*
* Let psr(Prescale) = IT8XXX2_I2C_PSR(p_ch)
* Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
* SMBus clock = pll_clock / clk_div
* SMBus clock cycle = 1 / SMBus clock
* 1 SCL cycle = 1 / freq
* 1 / freq = 2 x (psr + 2) x (1 / (pll_clock / clk_div))
* psr = ((pll_clock / clk_div) x (1 / freq) x (1 / 2)) - 2
*/
if (freq_hz) {
/* Get SMBus clock divide value */
clk_div = (IT8XXX2_ECPM_SCDCR2 & 0x0F) + 1U;
/* Calculate PSR value */
psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U;
/* Set psr value under 0xFD */
if (psr > 0xFD) {
psr = 0xFD;
}
/* Adjust SCL low period prescale */
psr_l = psr + prescale_scl;
if (psr_l > 0xFD) {
psr_l = 0xFD;
LOG_WRN("(psr + prescale_scl) can not be greater than 0xfd.");
}
/*
* Adjust SCL high period prescale
* The property setting prescale_scl must be less than psr and
* the minimum value of psr_h is 2.
*/
if (psr > (prescale_scl + 2)) {
psr_h = psr - prescale_scl;
} else {
psr_h = 2;
LOG_WRN("prescale_scl_low should be less than (psr - 2).");
}
/* Set I2C Speed for SCL low period. */
IT8XXX2_I2C_PSR(base) = psr_l & 0xFF;
/* Set I2C Speed for SCL high period. */
IT8XXX2_I2C_HSPR(base) = psr_h & 0xFF;
}
}
static int i2c_enhance_configure(const struct device *dev,
uint32_t dev_config_raw)
{
const struct i2c_enhance_config *config = dev->config;
struct i2c_enhance_data *const data = dev->data;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
data->bus_freq = I2C_SPEED_GET(dev_config_raw);
i2c_enhanced_port_set_frequency(dev, config->bitrate);
return 0;
}
static int i2c_enhance_get_config(const struct device *dev, uint32_t *dev_config)
{
struct i2c_enhance_data *const data = dev->data;
uint32_t speed;
if (!data->bus_freq) {
LOG_ERR("The bus frequency is not initially configured.");
return -EIO;
}
switch (data->bus_freq) {
case I2C_SPEED_DT:
case I2C_SPEED_STANDARD:
case I2C_SPEED_FAST:
case I2C_SPEED_FAST_PLUS:
speed = I2C_SPEED_SET(data->bus_freq);
break;
default:
return -ERANGE;
}
*dev_config = (I2C_MODE_CONTROLLER | speed);
return 0;
}
static int enhanced_i2c_error(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
uint32_t i2c_str = IT8XXX2_I2C_STR(base);
if (i2c_str & E_HOSTA_ANY_ERROR) {
data->err = i2c_str & E_HOSTA_ANY_ERROR;
/* device does not respond ACK */
} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
if (IT8XXX2_I2C_CTR(base) & E_ACK) {
data->err = E_HOSTA_ACK;
/* STOP */
IT8XXX2_I2C_CTR(base) = E_FINISH;
}
}
return data->err;
}
static void enhanced_i2c_start(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
/* reset i2c port */
i2c_reset(dev);
/* Set i2c frequency */
i2c_enhanced_port_set_frequency(dev, config->bitrate);
/*
* Set time out register.
* I2C D/E/F clock/data low timeout.
*/
IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
/* bit1: Enable enhanced i2c module */
IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
}
static void i2c_pio_trans_data(const struct device *dev,
enum enhanced_i2c_transfer_direct direct,
uint16_t trans_data, int first_byte)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
uint32_t nack = 0;
if (first_byte) {
/* First byte must be slave address. */
IT8XXX2_I2C_DTR(base) = trans_data |
(direct == RX_DIRECT ? BIT(0) : 0);
/* start or repeat start signal. */
IT8XXX2_I2C_CTR(base) = E_START_ID;
} else {
if (direct == TX_DIRECT) {
/* Transmit data */
IT8XXX2_I2C_DTR(base) = (uint8_t)trans_data;
} else {
/*
* Receive data.
* Last byte should be NACK in the end of read cycle
*/
if (((data->ridx + 1) == data->active_msg->len) &&
(data->active_msg->flags & I2C_MSG_STOP)) {
nack = 1;
}
}
/* Set hardware reset to start next transmission */
IT8XXX2_I2C_CTR(base) = E_INT_EN | E_MODE_SEL |
E_HW_RST | (nack ? 0 : E_ACK);
}
}
static int enhanced_i2c_tran_read(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
uint8_t in_data = 0;
if (data->active_msg->flags & I2C_MSG_START) {
/* clear start flag */
data->active_msg->flags &= ~I2C_MSG_START;
enhanced_i2c_start(dev);
/* Direct read */
data->i2ccs = I2C_CH_WAIT_READ;
/* Send ID */
i2c_pio_trans_data(dev, RX_DIRECT, data->addr_16bit << 1, 1);
} else {
if (data->i2ccs) {
if (data->i2ccs == I2C_CH_WAIT_READ) {
data->i2ccs = I2C_CH_NORMAL;
/* Receive data */
i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
/* data->active_msg->flags == I2C_MSG_RESTART */
} else {
/* Write to read */
data->i2ccs = I2C_CH_WAIT_READ;
/* Send ID */
i2c_pio_trans_data(dev, RX_DIRECT,
data->addr_16bit << 1, 1);
}
} else {
if (data->ridx < data->active_msg->len) {
/* read data */
*(data->active_msg->buf++) = IT8XXX2_I2C_DRR(base);
data->ridx++;
/* done */
if (data->ridx == data->active_msg->len) {
data->active_msg->len = 0;
if (data->active_msg->flags & I2C_MSG_STOP) {
data->i2ccs = I2C_CH_NORMAL;
IT8XXX2_I2C_CTR(base) = E_FINISH;
/* wait for stop bit interrupt */
data->stop = 1;
return 1;
}
/* End the transaction */
data->i2ccs = I2C_CH_WAIT_READ;
return 0;
}
/* read next byte */
i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
}
}
}
return 1;
}
static int enhanced_i2c_tran_write(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
uint8_t out_data;
if (data->active_msg->flags & I2C_MSG_START) {
/* Clear start bit */
data->active_msg->flags &= ~I2C_MSG_START;
enhanced_i2c_start(dev);
/* Send ID */
i2c_pio_trans_data(dev, TX_DIRECT, data->addr_16bit << 1, 1);
} else {
/* Host has completed the transmission of a byte */
if (data->widx < data->active_msg->len) {
out_data = *(data->active_msg->buf++);
data->widx++;
/* Send Byte */
i2c_pio_trans_data(dev, TX_DIRECT, out_data, 0);
if (data->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
data->i2ccs = I2C_CH_NORMAL;
}
} else {
/* done */
data->active_msg->len = 0;
if (data->active_msg->flags & I2C_MSG_STOP) {
IT8XXX2_I2C_CTR(base) = E_FINISH;
/* wait for stop bit interrupt */
data->stop = 1;
} else {
/* Direct write with direct read */
data->i2ccs = I2C_CH_WAIT_NEXT_XFER;
return 0;
}
}
}
return 1;
}
static int i2c_transaction(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
/* no error */
if (!(enhanced_i2c_error(dev))) {
if (!data->stop) {
/*
* The return value indicates if there is more data
* to be read or written. If the return value = 1,
* it means that the interrupt cannot be disable and
* continue to transmit data.
*/
if (data->active_msg->flags & I2C_MSG_READ) {
return enhanced_i2c_tran_read(dev);
} else {
return enhanced_i2c_tran_write(dev);
}
}
}
/* reset i2c port */
i2c_reset(dev);
IT8XXX2_I2C_CTR1(base) = 0;
data->stop = 0;
/* done doing work */
return 0;
}
static int i2c_enhance_pio_transfer(const struct device *dev,
struct i2c_msg *msgs)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
int res;
if (data->i2ccs == I2C_CH_NORMAL) {
struct i2c_msg *start_msg = &msgs[0];
start_msg->flags |= I2C_MSG_START;
}
for (int i = 0; i < data->num_msgs; i++) {
data->widx = 0;
data->ridx = 0;
data->err = 0;
data->active_msg = &msgs[i];
/*
* Start transaction.
* The return value indicates if the initial configuration
* of I2C transaction for read or write has been completed.
*/
if (i2c_transaction(dev)) {
/* Enable I2C interrupt. */
irq_enable(config->i2c_irq_base);
}
/* Wait for the transfer to complete */
/* TODO: the timeout should be adjustable */
res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
/*
* The irq will be enabled at the condition of start or
* repeat start of I2C. If timeout occurs without being
* wake up during suspend(ex: interrupt is not fired),
* the irq should be disabled immediately.
*/
irq_disable(config->i2c_irq_base);
/*
* The transaction is dropped on any error(timeout, NACK, fail,
* bus error, device error).
*/
if (data->err) {
break;
}
if (res != 0) {
data->err = ETIMEDOUT;
/* reset i2c port */
i2c_reset(dev);
LOG_ERR("I2C ch%d:0x%X reset cause %d",
config->port, data->addr_16bit, I2C_RC_TIMEOUT);
/* If this message is sent fail, drop the transaction. */
break;
}
}
/* reset i2c channel status */
if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
data->i2ccs = I2C_CH_NORMAL;
}
return data->err;
}
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
static void enhanced_i2c_set_cmd_addr_regs(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
struct i2c_enhance_data *data = dev->data;
struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
uint32_t dlm_base;
uint8_t *base = config->base;
/* Set "Address Register" to store the I2C data. */
dlm_base = (uint32_t)host_buffer->i2c_cq_mode_rx_dlm & 0xffffff;
IT8XXX2_I2C_RAMH2A(base) = (dlm_base >> 16) & 0xff;
IT8XXX2_I2C_RAMHA(base) = (dlm_base >> 8) & 0xff;
IT8XXX2_I2C_RAMLA(base) = dlm_base & 0xff;
/* Set "Command Address Register" to get commands. */
dlm_base = (uint32_t)host_buffer->i2c_cq_mode_tx_dlm & 0xffffff;
IT8XXX2_I2C_CMD_ADDH2(base) = (dlm_base >> 16) & 0xff;
IT8XXX2_I2C_CMD_ADDH(base) = (dlm_base >> 8) & 0xff;
IT8XXX2_I2C_CMD_ADDL(base) = dlm_base & 0xff;
}
static void enhanced_i2c_cq_write(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
struct i2c_cq_packet *i2c_cq_pckt;
uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
/* Set commands in RAM. */
i2c_cq_pckt->id = data->addr_16bit << 1;
i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
i2c_cq_pckt->cmd_h = num_bit_10_3;
for (int i = 0; i < data->cq_msgs[0].len; i++) {
i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
}
}
static void enhanced_i2c_cq_read(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
struct i2c_cq_packet *i2c_cq_pckt;
uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
/* Set commands in RAM. */
i2c_cq_pckt->id = data->addr_16bit << 1;
i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P |
I2C_CQ_CMD_L_E | num_bit_2_0;
i2c_cq_pckt->cmd_h = num_bit_10_3;
}
static void enhanced_i2c_cq_write_to_read(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
struct i2c_cq_packet *i2c_cq_pckt;
uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
int i;
i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
/* Set commands in RAM. (command byte for write) */
i2c_cq_pckt->id = data->addr_16bit << 1;
i2c_cq_pckt->cmd_l = num_bit_2_0;
i2c_cq_pckt->cmd_h = num_bit_10_3;
for (i = 0; i < data->cq_msgs[0].len; i++) {
i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
}
/* Set commands in RAM. (command byte for read) */
num_bit_2_0 = (data->cq_msgs[1].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
num_bit_10_3 = ((data->cq_msgs[1].len - 1) >> 3) & 0xff;
i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
i2c_cq_pckt->wdata[i] = num_bit_10_3;
}
static int enhanced_i2c_cq_isr(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
/* Device 1 finish IRQ. */
if (IT8XXX2_I2C_FST(base) & IT8XXX2_I2C_FST_DEV1_IRQ) {
uint8_t msgs_idx = data->num_msgs - 1;
/* Get data if this is a read transaction. */
if (data->cq_msgs[msgs_idx].flags & I2C_MSG_READ) {
for (int i = 0; i < data->cq_msgs[msgs_idx].len; i++) {
data->cq_msgs[msgs_idx].buf[i] =
host_buffer->i2c_cq_mode_rx_dlm[i];
}
}
} else {
/* Device 1 error have occurred. eg. nack, timeout... */
if (IT8XXX2_I2C_NST(base) & IT8XXX2_I2C_NST_ID_NACK) {
data->err = E_HOSTA_ACK;
} else {
data->err = IT8XXX2_I2C_STR(base) &
E_HOSTA_ANY_ERROR;
}
}
/* Reset bus. */
IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
IT8XXX2_I2C_CTR1(base) = 0;
return 0;
}
static int enhanced_i2c_cmd_queue_trans(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
/* State reset and hardware reset. */
IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
/* Set "PSR" registers to decide the i2c speed. */
i2c_enhanced_port_set_frequency(dev, config->bitrate);
/* Set time out register. port D, E, or F clock/data low timeout. */
IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
if (data->num_msgs == 2) {
/* I2C write to read of command queue mode. */
enhanced_i2c_cq_write_to_read(dev);
} else {
/* I2C read of command queue mode. */
if (data->cq_msgs[0].flags & I2C_MSG_READ) {
enhanced_i2c_cq_read(dev);
/* I2C write of command queue mode. */
} else {
enhanced_i2c_cq_write(dev);
}
}
/* Enable i2c module with command queue mode. */
IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN | IT8XXX2_I2C_COMQ_EN;
/* One shot on device 1. */
IT8XXX2_I2C_MODE_SEL(base) = 0;
IT8XXX2_I2C_CTR2(base) = 1;
/*
* The EC processor(CPU) cannot be in the k_cpu_idle() and power
* policy during the transactions with the CQ mode(DMA mode).
* Otherwise, the EC processor would be clock gated.
*/
chip_block_idle();
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
/* Start */
IT8XXX2_I2C_CTR(base) = E_START_CQ;
return 1;
}
static int i2c_enhance_cq_transfer(const struct device *dev,
struct i2c_msg *msgs)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
int res = 0;
data->err = 0;
data->cq_msgs = msgs;
/* Start transaction */
if (enhanced_i2c_cmd_queue_trans(dev)) {
/* Enable i2c interrupt */
irq_enable(config->i2c_irq_base);
}
/* Wait for the transfer to complete */
res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
irq_disable(config->i2c_irq_base);
if (res != 0) {
data->err = ETIMEDOUT;
/* Reset i2c port. */
i2c_reset(dev);
LOG_ERR("I2C ch%d:0x%X reset cause %d",
config->port, data->addr_16bit, I2C_RC_TIMEOUT);
}
/* Permit to enter power policy and idle mode. */
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
chip_permit_idle();
return data->err;
}
static bool cq_mode_allowed(const struct device *dev, struct i2c_msg *msgs)
{
struct i2c_enhance_data *data = dev->data;
/*
* If the transaction of write or read is divided into two
* transfers(not two messages), the command queue mode does
* not support.
*/
if (data->i2ccs != I2C_CH_NORMAL) {
return false;
}
/*
* When there is only one message, use the command queue transfer
* directly.
*/
if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP)) {
/* Read transfer payload too long, use PIO mode */
if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
(msgs[0].len > CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
return false;
}
/* Write transfer payload too long, use PIO mode */
if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
(msgs[0].len > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
return false;
}
/*
* Write of I2C target address without writing data, used by
* cmd_i2c_scan. Use PIO mode.
*/
if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
(msgs[0].len == 0)) {
return false;
}
return true;
}
/*
* When there are two messages, we need to judge whether or not there
* is I2C_MSG_RESTART flag from the second message, and then decide to
* do the command queue or PIO mode transfer.
*/
if (data->num_msgs == 2) {
/*
* The first of two messages must be write.
* If the length of write to read transfer is greater than
* command queue payload size, there will execute PIO mode.
*/
if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
(msgs[0].len <= I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
/*
* The transfer is i2c_burst_read().
*
* e.g. msg[0].flags = I2C_MSG_WRITE;
* msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
* I2C_MSG_STOP;
*/
if ((msgs[1].flags & I2C_MSG_RESTART) &&
((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
(msgs[1].flags & I2C_MSG_STOP) &&
(msgs[1].len <= CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
return true;
}
}
}
return false;
}
#endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
static int i2c_enhance_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_enhance_data *data = dev->data;
int ret;
#ifdef CONFIG_I2C_TARGET
if (data->target_attached) {
LOG_ERR("Device is registered as target");
return -EBUSY;
}
#endif
/* Lock mutex of i2c controller */
k_mutex_lock(&data->mutex, K_FOREVER);
data->num_msgs = num_msgs;
data->addr_16bit = addr;
/*
* If the transaction of write to read is divided into two
* transfers, the repeat start transfer uses this flag to
* exclude checking bus busy.
*/
if (data->i2ccs == I2C_CH_NORMAL) {
/* Make sure we're in a good state to start */
if (i2c_bus_not_available(dev)) {
/* Recovery I2C bus */
i2c_recover_bus(dev);
/*
* After resetting I2C bus, if I2C bus is not available
* (No external pull-up), drop the transaction.
*/
if (i2c_bus_not_available(dev)) {
/* Unlock mutex of i2c controller */
k_mutex_unlock(&data->mutex);
return -EIO;
}
}
}
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
if (cq_mode_allowed(dev, msgs)) {
data->err = i2c_enhance_cq_transfer(dev, msgs);
} else
#endif
{
data->err = i2c_enhance_pio_transfer(dev, msgs);
}
/* Save return value. */
ret = i2c_parsing_return_value(dev);
/* Unlock mutex of i2c controller */
k_mutex_unlock(&data->mutex);
return ret;
}
#ifdef CONFIG_I2C_TARGET
static void target_i2c_isr_dma(const struct device *dev,
uint8_t interrupt_status)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
uint8_t *base = config->base;
/* Byte counter enable */
if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
IT8XXX2_I2C_BYTE_CNT_L(base) |=
(IT8XXX2_I2C_DMA_ADDR_RELOAD |
IT8XXX2_I2C_BYTE_CNT_ENABLE);
}
/* The number of received data exceeds the byte counter setting */
if (interrupt_status & IT8XXX2_I2C_CNT_HOLD) {
LOG_ERR("The excess data written starts "
"from the memory address:%p",
target_buffer->in_buffer +
CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE);
}
/* Controller to write data */
if (interrupt_status & IT8XXX2_I2C_SLVDATAFLG) {
/* Number of receive data in target mode */
data->buffer_size =
((IT8XXX2_I2C_SLV_NUM_H(base) << 8) |
IT8XXX2_I2C_SLV_NUM_L(base)) + 1;
/* Write data done callback function */
target_cb->buf_write_received(data->target_cfg,
target_buffer->in_buffer, data->buffer_size);
}
/* Peripheral finish */
if (interrupt_status & IT8XXX2_I2C_P_CLR) {
/* Transfer done callback function */
target_cb->stop(data->target_cfg);
}
/* Controller to read data */
if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
uint32_t len;
uint8_t *rdata = NULL;
/* Clear byte counter setting */
IT8XXX2_I2C_BYTE_CNT_L(base) &=
~(IT8XXX2_I2C_DMA_ADDR_RELOAD |
IT8XXX2_I2C_BYTE_CNT_ENABLE);
/* Read data callback function */
target_cb->buf_read_requested(data->target_cfg,
&rdata, &len);
if (len > CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE) {
LOG_ERR("The buffer size exceeds "
"I2C_TARGET_IT8XXX2_MAX_BUF_SIZE: len=%d",
len);
} else {
memcpy(target_buffer->out_buffer, rdata, len);
}
}
/* Write clear the peripheral status */
IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
}
static int target_i2c_isr_pio(const struct device *dev,
uint8_t interrupt_status,
uint8_t target_status)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
int ret = 0;
uint8_t *base = config->base;
uint8_t val;
/* Target ID write flag */
if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
ret = target_cb->write_requested(data->target_cfg);
}
/* Target ID read flag */
else if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
if (!target_cb->read_requested(data->target_cfg, &val)) {
IT8XXX2_I2C_DTR(base) = val;
}
}
/* Byte transfer done */
else if (target_status & IT8XXX2_I2C_BYTE_DONE) {
/* Read of write */
if (target_status & IT8XXX2_I2C_RW) {
/* Host receiving, target transmitting */
if (!target_cb->read_processed(data->target_cfg, &val)) {
IT8XXX2_I2C_DTR(base) = val;
}
} else {
/* Host transmitting, target receiving */
val = IT8XXX2_I2C_DRR(base);
ret = target_cb->write_received(data->target_cfg, val);
}
}
return ret;
}
static void target_i2c_isr(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
uint8_t *base = config->base;
uint8_t target_status = IT8XXX2_I2C_STR(base);
/* Any error */
if (target_status & E_TARGET_ANY_ERROR) {
/* Hardware reset */
IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
return;
}
/* Interrupt pending */
if (target_status & IT8XXX2_I2C_INT_PEND) {
uint8_t interrupt_status = IT8XXX2_I2C_IRQ_ST(base);
/* Determine whether the transaction uses PIO or DMA mode */
if (config->target_pio_mode) {
if (target_i2c_isr_pio(dev, interrupt_status, target_status) < 0) {
/* NACK */
IT8XXX2_I2C_CTR(base) &= ~IT8XXX2_I2C_ACK;
IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
data->target_nack = 1;
}
/* Peripheral finish */
if (interrupt_status & IT8XXX2_I2C_P_CLR) {
/* Transfer done callback function */
target_cb->stop(data->target_cfg);
if (data->target_nack) {
/* Set acknowledge */
IT8XXX2_I2C_CTR(base) |=
IT8XXX2_I2C_ACK;
data->target_nack = 0;
}
}
/* Write clear the peripheral status */
IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
/* Hardware reset */
IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
} else {
target_i2c_isr_dma(dev, interrupt_status);
}
}
}
#endif
static void i2c_enhance_isr(void *arg)
{
struct device *dev = (struct device *)arg;
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
#ifdef CONFIG_I2C_TARGET
if (data->target_attached) {
target_i2c_isr(dev);
} else {
#endif
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
uint8_t *base = config->base;
/* If done doing work, wake up the task waiting for the transfer */
if (IT8XXX2_I2C_CTR1(base) & IT8XXX2_I2C_COMQ_EN) {
if (enhanced_i2c_cq_isr(dev)) {
return;
}
} else
#endif
{
if (i2c_transaction(dev)) {
return;
}
}
irq_disable(config->i2c_irq_base);
k_sem_give(&data->device_sync_sem);
#ifdef CONFIG_I2C_TARGET
}
#endif
}
static int i2c_enhance_init(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config->base;
uint8_t data_hold_time = config->data_hold_time;
uint32_t bitrate_cfg;
int error, status;
#ifdef CONFIG_I2C_TARGET
if (!config->target_enable) {
#endif
/* Initialize mutex and semaphore */
k_mutex_init(&data->mutex);
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
/* Enable clock to specified peripheral */
volatile uint8_t *reg = (volatile uint8_t *)
(IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
uint8_t reg_mask = config->clock_gate_offset & 0xff;
*reg &= ~reg_mask;
/* Enable I2C function */
/* Software reset */
IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
/* reset i2c port */
i2c_reset(dev);
/* bit1, Module enable */
IT8XXX2_I2C_CTR1(base) = 0;
#ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
/* Set command address registers. */
enhanced_i2c_set_cmd_addr_regs(dev);
#endif
/* ChannelA-F switch selection of I2C pin */
if (config->port == SMB_CHANNEL_A) {
IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
config->channel_switch_sel;
} else if (config->port == SMB_CHANNEL_B) {
IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
(IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
} else if (config->port == SMB_CHANNEL_C) {
IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
config->channel_switch_sel;
} else if (config->port == I2C_CHANNEL_D) {
IT8XXX2_SMB_SMB23CHS = (config->channel_switch_sel << 4) |
(IT8XXX2_SMB_SMB23CHS &= ~GENMASK(6, 4));
} else if (config->port == I2C_CHANNEL_E) {
IT8XXX2_SMB_SMB45CHS = (IT8XXX2_SMB_SMB45CHS &= ~GENMASK(2, 0)) |
config->channel_switch_sel;
} else if (config->port == I2C_CHANNEL_F) {
IT8XXX2_SMB_SMB45CHS = (config->channel_switch_sel << 4) |
(IT8XXX2_SMB_SMB45CHS &= ~GENMASK(6, 4));
}
/* Set I2C data hold time. */
IT8XXX2_I2C_DHTR(base) = (IT8XXX2_I2C_DHTR(base) & ~GENMASK(2, 0)) |
(data_hold_time - 3);
/* Set clock frequency for I2C ports */
if (config->bitrate == I2C_BITRATE_STANDARD ||
config->bitrate == I2C_BITRATE_FAST ||
config->bitrate == I2C_BITRATE_FAST_PLUS) {
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
} else {
/* Device tree specified speed */
bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
}
error = i2c_enhance_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
data->i2ccs = I2C_CH_NORMAL;
if (error) {
LOG_ERR("i2c: failure initializing");
return error;
}
#ifdef CONFIG_I2C_TARGET
}
#endif
/* Set the pin to I2C alternate function. */
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure I2C pins");
return status;
}
return 0;
}
static int i2c_enhance_recover_bus(const struct device *dev)
{
const struct i2c_enhance_config *config = dev->config;
int i, status;
/* Output type selection */
gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
/* Set SCL of I2C as GPIO pin */
gpio_pin_configure_dt(&config->scl_gpios, flags);
/* Set SDA of I2C as GPIO pin */
gpio_pin_configure_dt(&config->sda_gpios, flags);
/*
* In I2C recovery bus, 1ms sleep interval for bitbanging i2c
* is mainly to ensure that gpio has enough time to go from
* low to high or high to low.
*/
/* Pull SCL and SDA pin to high */
gpio_pin_set_dt(&config->scl_gpios, 1);
gpio_pin_set_dt(&config->sda_gpios, 1);
k_msleep(1);
/* Start condition */
gpio_pin_set_dt(&config->sda_gpios, 0);
k_msleep(1);
gpio_pin_set_dt(&config->scl_gpios, 0);
k_msleep(1);
/* 9 cycles of SCL with SDA held high */
for (i = 0; i < 9; i++) {
/* SDA */
gpio_pin_set_dt(&config->sda_gpios, 1);
/* SCL */
gpio_pin_set_dt(&config->scl_gpios, 1);
k_msleep(1);
/* SCL */
gpio_pin_set_dt(&config->scl_gpios, 0);
k_msleep(1);
}
/* SDA */
gpio_pin_set_dt(&config->sda_gpios, 0);
k_msleep(1);
/* Stop condition */
gpio_pin_set_dt(&config->scl_gpios, 1);
k_msleep(1);
gpio_pin_set_dt(&config->sda_gpios, 1);
k_msleep(1);
/* Set GPIO back to I2C alternate function */
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure I2C pins");
return status;
}
/* reset i2c port */
i2c_reset(dev);
LOG_ERR("I2C ch%d reset cause %d", config->port,
I2C_RC_NO_IDLE_FOR_START);
return 0;
}
#ifdef CONFIG_I2C_TARGET
static int i2c_enhance_target_register(const struct device *dev,
struct i2c_target_config *target_cfg)
{
const struct i2c_enhance_config *config = dev->config;
struct i2c_enhance_data *data = dev->data;
uint8_t *base = config->base;
if (!target_cfg) {
return -EINVAL;
}
if (target_cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -ENOTSUP;
}
if (data->target_attached) {
return -EBUSY;
}
data->target_cfg = target_cfg;
data->target_attached = true;
/* Software reset */
IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
/* Disable the timeout setting when clock/data are in a low state */
IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |
IT8XXX2_I2C_SDA_TIMEOUT_EN);
/* Bit stretching */
IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;
/* Peripheral address(8-bit) */
IT8XXX2_I2C_IDR(base) = target_cfg->address << 1;
/* I2C interrupt enable and set acknowledge */
IT8XXX2_I2C_CTR(base) = IT8XXX2_I2C_INT_EN | IT8XXX2_I2C_HALT |
IT8XXX2_I2C_ACK;
/* Interrupt status write clear */
IT8XXX2_I2C_IRQ_ST(base) = 0xff;
/* I2C target initial configuration of PIO mode */
if (config->target_pio_mode) {
/* Block to enter power policy. */
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
/* I2C module enable */
IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
/* I2C target initial configuration of DMA mode */
} else {
struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
uint32_t in_data_addr, out_data_addr;
int buf_size = CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE;
/* Clear read and write data buffer of DMA */
memset(target_buffer->in_buffer, 0, buf_size);
memset(target_buffer->out_buffer, 0, buf_size);
in_data_addr = (uint32_t)target_buffer->in_buffer & 0xffffff;
out_data_addr = (uint32_t)target_buffer->out_buffer & 0xffffff;
/*
* DMA write target address register
* for high order byte
*/
IT8XXX2_I2C_RAMH2A(base) = in_data_addr >> 16;
IT8XXX2_I2C_RAMHA(base) = in_data_addr >> 8;
IT8XXX2_I2C_RAMLA(base) = in_data_addr;
/*
* DMA read target address register
* for high order byte
*/
IT8XXX2_I2C_CMD_ADDH2(base) = out_data_addr >> 16;
IT8XXX2_I2C_RAMHA2(base) = out_data_addr >> 8;
IT8XXX2_I2C_RAMLA2(base) = out_data_addr;
/* Byte counter setting */
/* This register indicates byte count[10:3]. */
IT8XXX2_I2C_BYTE_CNT_H(base) =
CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE >> 3;
/* This register indicates byte count[2:0]. */
IT8XXX2_I2C_BYTE_CNT_L(base) =
CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE & GENMASK(2, 0);
/*
* The EC processor(CPU) cannot be in the k_cpu_idle() and power
* policy during the transactions with the CQ mode(DMA mode).
* Otherwise, the EC processor would be clock gated.
*/
chip_block_idle();
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
/* I2C module enable and command queue mode */
IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_COMQ_EN | IT8XXX2_I2C_MDL_EN;
}
ite_intc_isr_clear(config->i2c_irq_base);
irq_enable(config->i2c_irq_base);
return 0;
}
static int i2c_enhance_target_unregister(const struct device *dev,
struct i2c_target_config *cfg)
{
const struct i2c_enhance_config *config = dev->config;
struct i2c_enhance_data *data = dev->data;
if (!data->target_attached) {
return -EINVAL;
}
irq_disable(config->i2c_irq_base);
/* Permit to enter power policy and idle mode. */
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
if (!config->target_pio_mode) {
chip_permit_idle();
}
data->target_cfg = NULL;
data->target_attached = false;
data->target_nack = 0;
return 0;
}
#endif
static const struct i2c_driver_api i2c_enhance_driver_api = {
.configure = i2c_enhance_configure,
.get_config = i2c_enhance_get_config,
.transfer = i2c_enhance_transfer,
.recover_bus = i2c_enhance_recover_bus,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_enhance_target_register,
.target_unregister = i2c_enhance_target_unregister,
#endif
};
#ifdef CONFIG_I2C_TARGET
BUILD_ASSERT(IS_ENABLED(CONFIG_I2C_TARGET_BUFFER_MODE),
"When I2C target config is enabled, the buffer mode must be used.");
#endif
#define I2C_ITE_ENHANCE_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
50000) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_STANDARD) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_FAST) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
static void i2c_enhance_config_func_##inst(void); \
\
static const struct i2c_enhance_config i2c_enhance_cfg_##inst = { \
.base = (uint8_t *)(DT_INST_REG_ADDR(inst)), \
.irq_config_func = i2c_enhance_config_func_##inst, \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
.i2c_irq_base = DT_INST_IRQN(inst), \
.port = DT_INST_PROP(inst, port_num), \
.channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
.scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
.sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
.prescale_scl_low = DT_INST_PROP_OR(inst, prescale_scl_low, 0), \
.data_hold_time = DT_INST_PROP_OR(inst, data_hold_time, 0), \
.clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.target_enable = DT_INST_PROP(inst, target_enable), \
.target_pio_mode = DT_INST_PROP(inst, target_pio_mode), \
.push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \
}; \
\
static struct i2c_enhance_data i2c_enhance_data_##inst; \
\
I2C_DEVICE_DT_INST_DEFINE(inst, i2c_enhance_init, \
NULL, \
&i2c_enhance_data_##inst, \
&i2c_enhance_cfg_##inst, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_enhance_driver_api); \
\
static void i2c_enhance_config_func_##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
0, \
i2c_enhance_isr, \
DEVICE_DT_INST_GET(inst), 0); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_ENHANCE_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_ite_enhance.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14,245 |
```objective-c
/*
*
*/
/**
* @brief Functions for setting and getting the state of the I2C lines.
*
* These need to be implemented by the user of this library.
*/
struct i2c_bitbang_io {
/* Set the state of the SCL line (zero/non-zero value) */
void (*set_scl)(void *io_context, int state);
/* Set the state of the SDA line (zero/non-zero value) */
void (*set_sda)(void *io_context, int state);
/* Return the state of the SDA line (zero/non-zero value) */
int (*get_sda)(void *io_context);
};
/**
* @brief Instance data for i2c_bitbang
*
* A driver or other code wishing to use the i2c_bitbang library should
* create one of these structures then use it via the library APIs.
* Structure members are private, and shouldn't be accessed directly.
*/
struct i2c_bitbang {
const struct i2c_bitbang_io *io;
void *io_context;
uint32_t delays[2];
uint32_t dev_config;
};
/**
* @brief Initialize an i2c_bitbang instance
*
* @param bitbang The instance to initialize
* @param io Functions to use for controlling I2C bus lines
* @param io_context Context pointer to pass to i/o functions when then are
* called.
*/
void i2c_bitbang_init(struct i2c_bitbang *bitbang,
const struct i2c_bitbang_io *io, void *io_context);
/**
* Implementation of the functionality required by the 'configure' function
* in struct i2c_driver_api.
*/
int i2c_bitbang_configure(struct i2c_bitbang *bitbang, uint32_t dev_config);
/**
* Implementation of the functionality required by the 'get_config' function
* in struct i2c_driver_api.
*/
int i2c_bitbang_get_config(struct i2c_bitbang *context, uint32_t *config);
/**
* Implementation of the functionality required by the 'recover_bus'
* function in struct i2c_driver_api.
*/
int i2c_bitbang_recover_bus(struct i2c_bitbang *bitbang);
/**
* Implementation of the functionality required by the 'transfer' function
* in struct i2c_driver_api.
*/
int i2c_bitbang_transfer(struct i2c_bitbang *bitbang,
struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t slave_address);
``` | /content/code_sandbox/drivers/i2c/i2c_bitbang.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 538 |
```c
/*
* Logging of I2C messages
*
*
*/
#include <stdio.h>
#include <zephyr/drivers/i2c.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c);
#if defined(CONFIG_I2C_CALLBACK) && defined(CONFIG_POLL)
void z_i2c_transfer_signal_cb(const struct device *dev,
int result,
void *data)
{
struct k_poll_signal *sig = (struct k_poll_signal *)data;
k_poll_signal_raise(sig, result);
}
#endif
#ifdef CONFIG_I2C_DUMP_MESSAGES_ALLOWLIST
#define DEF_BUS_WITH_ADDR(node, prop, idx) I2C_DT_SPEC_GET(DT_PHANDLE_BY_IDX(node, prop, idx)),
#define DEF_ALLOWLIST_DEV(node) DT_FOREACH_PROP_ELEM(node, devices, DEF_BUS_WITH_ADDR)
struct i2c_dt_spec messages_allowlist[] = {
DT_FOREACH_STATUS_OKAY(zephyr_i2c_dump_allowlist, DEF_ALLOWLIST_DEV)};
#undef DEF_ALLOWLIST_DEV
#undef DEF_BUS_WITH_ADDR
#endif
void i2c_dump_msgs_rw(const struct device *dev, const struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr, bool dump_read)
{
#ifdef CONFIG_I2C_DUMP_MESSAGES_ALLOWLIST
bool found_dev = 0;
for (int a = 0; a < ARRAY_SIZE(messages_allowlist); a++) {
struct i2c_dt_spec *allowed = &messages_allowlist[a];
if (dev != allowed->bus || addr != allowed->addr) {
continue;
} else {
found_dev = 1;
break;
}
}
if (!found_dev) {
return;
}
#endif
LOG_DBG("I2C msg: %s, addr=%x", dev->name, addr);
for (unsigned int i = 0; i < num_msgs; i++) {
const struct i2c_msg *msg = &msgs[i];
const bool is_read = msg->flags & I2C_MSG_READ;
const bool dump_data = dump_read || !is_read;
if (msg->len == 1 && dump_data) {
LOG_DBG(" %c %2s %1s len=01: %02x", is_read ? 'R' : 'W',
msg->flags & I2C_MSG_RESTART ? "Sr" : "",
msg->flags & I2C_MSG_STOP ? "P" : "", msg->buf[0]);
} else {
LOG_DBG(" %c %2s %1s len=%02x: ", is_read ? 'R' : 'W',
msg->flags & I2C_MSG_RESTART ? "Sr" : "",
msg->flags & I2C_MSG_STOP ? "P" : "", msg->len);
if (dump_data) {
LOG_HEXDUMP_DBG(msg->buf, msg->len, "contents:");
}
}
}
}
``` | /content/code_sandbox/drivers/i2c/i2c_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 636 |
```c
/*
*
*/
#define DT_DRV_COMPAT telink_b91_i2c
#include "i2c.h"
#include "clock.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_telink);
#include <zephyr/drivers/i2c.h>
#include "i2c-priv.h"
#include <zephyr/drivers/pinctrl.h>
/* I2C configuration structure */
struct i2c_b91_cfg {
uint32_t bitrate;
const struct pinctrl_dev_config *pcfg;
};
/* I2C data structure */
struct i2c_b91_data {
struct k_sem mutex;
};
/* API implementation: configure */
static int i2c_b91_configure(const struct device *dev, uint32_t dev_config)
{
ARG_UNUSED(dev);
uint32_t i2c_speed = 0u;
/* check address size */
if (dev_config & I2C_ADDR_10_BITS) {
LOG_ERR("10-bits address is not supported");
return -ENOTSUP;
}
/* check I2C Master/Slave configuration */
if (!(dev_config & I2C_MODE_CONTROLLER)) {
LOG_ERR("I2C slave is not implemented");
return -ENOTSUP;
}
/* check i2c speed */
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
i2c_speed = 100000u;
break;
case I2C_SPEED_FAST:
i2c_speed = 400000U;
break;
case I2C_SPEED_FAST_PLUS:
case I2C_SPEED_HIGH:
case I2C_SPEED_ULTRA:
default:
LOG_ERR("Unsupported I2C speed requested");
return -ENOTSUP;
}
/* init i2c */
i2c_master_init();
i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * i2c_speed)));
return 0;
}
/* API implementation: transfer */
static int i2c_b91_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs,
uint16_t addr)
{
int status = 0;
uint8_t send_stop = 0;
struct i2c_b91_data *data = dev->data;
/* get the mutex */
k_sem_take(&data->mutex, K_FOREVER);
/* loop through all messages */
for (int i = 0; i < num_msgs; i++) {
/* check addr size */
if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
LOG_ERR("10-bits address is not supported");
k_sem_give(&data->mutex);
return -ENOTSUP;
}
/* config stop bit */
send_stop = msgs[i].flags & I2C_MSG_STOP ? 1 : 0;
i2c_master_send_stop(send_stop);
/* transfer data */
if (msgs[i].flags & I2C_MSG_READ) {
status = i2c_master_read(addr, msgs[i].buf, msgs[i].len);
} else {
status = i2c_master_write(addr, msgs[i].buf, msgs[i].len);
}
/* check status */
if (!status) {
LOG_ERR("Failed to transfer I2C messages\n");
k_sem_give(&data->mutex);
return -EIO;
}
}
/* release the mutex */
k_sem_give(&data->mutex);
return 0;
};
/* API implementation: init */
static int i2c_b91_init(const struct device *dev)
{
int status = 0;
const struct i2c_b91_cfg *cfg = dev->config;
struct i2c_b91_data *data = dev->data;
uint32_t dev_config = (I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(cfg->bitrate));
/* init mutex */
k_sem_init(&data->mutex, 1, 1);
/* config i2c on startup */
status = i2c_b91_configure(dev, dev_config);
if (status != 0) {
LOG_ERR("Failed to configure I2C on init");
return status;
}
/* configure pins */
status = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure I2C pins");
return status;
}
return 0;
}
/* I2C driver APIs structure */
static const struct i2c_driver_api i2c_b91_api = {
.configure = i2c_b91_configure,
.transfer = i2c_b91_transfer,
};
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
"unsupported I2C instance");
/* I2C driver registration */
#define I2C_B91_INIT(inst) \
\
PINCTRL_DT_INST_DEFINE(inst); \
\
static struct i2c_b91_data i2c_b91_data_##inst; \
\
static struct i2c_b91_cfg i2c_b91_cfg_##inst = { \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(inst, i2c_b91_init, \
NULL, \
&i2c_b91_data_##inst, \
&i2c_b91_cfg_##inst, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_b91_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_B91_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_b91.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,232 |
```unknown
# nrfx I2C support
menuconfig I2C_NRFX
bool "nRF TWI nrfx drivers"
default y
depends on SOC_FAMILY_NORDIC_NRF
depends on MULTITHREADING
select PINCTRL
help
Enable support for nrfx TWI drivers for nRF MCU series.
if I2C_NRFX
config I2C_NRFX_TWI
def_bool y
depends on DT_HAS_NORDIC_NRF_TWI_ENABLED
select HAS_I2C_RTIO
select NRFX_TWI0 if HAS_HW_NRF_TWI0
select NRFX_TWI1 if HAS_HW_NRF_TWI1
config I2C_NRFX_TWIM
def_bool y
depends on DT_HAS_NORDIC_NRF_TWIM_ENABLED
select NRFX_TWIM0 if HAS_HW_NRF_TWIM0
select NRFX_TWIM1 if HAS_HW_NRF_TWIM1
select NRFX_TWIM2 if HAS_HW_NRF_TWIM2
select NRFX_TWIM3 if HAS_HW_NRF_TWIM3
select NRFX_TWIM20 if HAS_HW_NRF_TWIM20
select NRFX_TWIM21 if HAS_HW_NRF_TWIM21
select NRFX_TWIM22 if HAS_HW_NRF_TWIM22
select NRFX_TWIM30 if HAS_HW_NRF_TWIM30
select NRFX_TWIM120 if HAS_HW_NRF_TWIM120
select NRFX_TWIM130 if HAS_HW_NRF_TWIM130
select NRFX_TWIM131 if HAS_HW_NRF_TWIM131
select NRFX_TWIM132 if HAS_HW_NRF_TWIM132
select NRFX_TWIM133 if HAS_HW_NRF_TWIM133
select NRFX_TWIM134 if HAS_HW_NRF_TWIM134
select NRFX_TWIM135 if HAS_HW_NRF_TWIM135
select NRFX_TWIM136 if HAS_HW_NRF_TWIM136
select NRFX_TWIM137 if HAS_HW_NRF_TWIM137
config I2C_NRFX_TRANSFER_TIMEOUT
int "Transfer timeout [ms]"
default 500
help
Timeout in milliseconds used for each I2C transfer.
0 means that the driver should use the K_FOREVER value,
i.e. it should wait as long as necessary.
endif # I2C_NRFX
``` | /content/code_sandbox/drivers/i2c/Kconfig.nrfx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 495 |
```c
/*
*
*/
/* The logic here is adapted from SimpleLink SDK's I2CCC32XX.c module. */
#define DT_DRV_COMPAT ti_cc32xx_i2c
#include <zephyr/kernel.h>
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/* Driverlib includes */
#include <inc/hw_memmap.h>
#include <inc/hw_common_reg.h>
#include <driverlib/rom.h>
#include <driverlib/rom_map.h>
#include <driverlib/i2c.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_cc32xx);
#include "i2c-priv.h"
#define I2C_MASTER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START
#define I2C_MASTER_CMD_BURST_RECEIVE_STOP \
I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT
#define I2C_SEM_MASK \
COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M
#define I2C_SEM_TAKE \
COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S
#define IS_I2C_MSG_WRITE(flags) ((flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
#define DEV_BASE(dev) \
(((const struct i2c_cc32xx_config *const)(dev)->config)->base)
/* Since this driver does not explicitly enable the TX/RX FIFOs, there
* are no interrupts received which can distinguish between read and write
* completion.
* So, we need the READ and WRITE state flags to determine whether the
* completed transmission was started as a write or a read.
* The ERROR flag is used to convey error status from the ISR back to the
* I2C API without having to re-read I2C registers.
*/
enum i2c_cc32xx_state {
/* I2C was primed for a write operation */
I2C_CC32XX_WRITE_MODE,
/* I2C was primed for a read operation */
I2C_CC32XX_READ_MODE,
/* I2C error occurred */
I2C_CC32XX_ERROR = 0xFF
};
struct i2c_cc32xx_config {
uint32_t base;
uint32_t bitrate;
unsigned int irq_no;
const struct pinctrl_dev_config *pcfg;
};
struct i2c_cc32xx_data {
struct k_sem mutex;
struct k_sem transfer_complete;
volatile enum i2c_cc32xx_state state;
struct i2c_msg msg; /* Cache msg for transfer state machine */
uint16_t slave_addr; /* Cache slave address for ISR use */
};
static void configure_i2c_irq(const struct i2c_cc32xx_config *config);
#define I2C_CLK_FREQ(n) DT_PROP(DT_INST_PHANDLE(n, clocks), clock_frequency)
static int i2c_cc32xx_configure(const struct device *dev,
uint32_t dev_config_raw)
{
uint32_t base = DEV_BASE(dev);
uint32_t bitrate_id;
if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
return -EINVAL;
}
if (dev_config_raw & I2C_ADDR_10_BITS) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
bitrate_id = 0U;
break;
case I2C_SPEED_FAST:
bitrate_id = 1U;
break;
default:
return -EINVAL;
}
MAP_I2CMasterInitExpClk(base, I2C_CLK_FREQ(0), bitrate_id);
return 0;
}
static void i2c_cc32xx_prime_transfer(const struct device *dev,
struct i2c_msg *msg,
uint16_t addr)
{
struct i2c_cc32xx_data *data = dev->data;
uint32_t base = DEV_BASE(dev);
/* Initialize internal counters and buf pointers: */
data->msg = *msg;
data->slave_addr = addr;
/* Start transfer in Transmit mode */
if (IS_I2C_MSG_WRITE(data->msg.flags)) {
/* Specify the I2C slave address */
MAP_I2CMasterSlaveAddrSet(base, addr, false);
/* Update the I2C state */
data->state = I2C_CC32XX_WRITE_MODE;
/* Write data contents into data register */
MAP_I2CMasterDataPut(base, *((data->msg.buf)++));
/* Start the I2C transfer in master transmit mode */
MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
} else {
/* Start transfer in Receive mode */
/* Specify the I2C slave address */
MAP_I2CMasterSlaveAddrSet(base, addr, true);
/* Update the I2C mode */
data->state = I2C_CC32XX_READ_MODE;
if (data->msg.len < 2) {
/* Start the I2C transfer in master receive mode */
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_START_NACK);
} else {
/* Start the I2C transfer in burst receive mode */
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_START);
}
}
}
static int i2c_cc32xx_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_cc32xx_data *data = dev->data;
int retval = 0;
/* Acquire the driver mutex */
k_sem_take(&data->mutex, K_FOREVER);
/* Iterate over all the messages */
for (int i = 0; i < num_msgs; i++) {
/* Begin the transfer */
i2c_cc32xx_prime_transfer(dev, msgs, addr);
/* Wait for the transfer to complete */
k_sem_take(&data->transfer_complete, K_FOREVER);
/* Return an error if the transfer didn't complete */
if (data->state == I2C_CC32XX_ERROR) {
retval = -EIO;
break;
}
/* Move to the next message */
msgs++;
}
/* Release the mutex */
k_sem_give(&data->mutex);
return retval;
}
static void i2c_cc32xx_isr_handle_write(uint32_t base,
struct i2c_cc32xx_data *data)
{
/* Decrement write Counter */
data->msg.len--;
/* Check if more data needs to be sent */
if (data->msg.len) {
/* Write data contents into data register */
MAP_I2CMasterDataPut(base, *(data->msg.buf));
data->msg.buf++;
if (data->msg.len < 2) {
/* Everything has been sent, nothing to receive */
/* Send last byte with STOP bit */
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_SEND_FINISH);
} else {
/*
* Either there is more data to be transmitted or some
* data needs to be received next
*/
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_SEND_CONT);
}
} else {
/*
* No more data needs to be sent, so follow up with
* a STOP bit.
*/
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_STOP);
}
}
static void i2c_cc32xx_isr_handle_read(uint32_t base,
struct i2c_cc32xx_data *data)
{
/* Save the received data */
*(data->msg.buf) = MAP_I2CMasterDataGet(base);
data->msg.buf++;
/* Check if any data needs to be received */
data->msg.len--;
if (data->msg.len) {
if (data->msg.len > 1) {
/* More data to be received */
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_CONT);
} else {
/*
* Send NACK because it's the last byte to be received
*/
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK);
}
} else {
/*
* No more data needs to be received, so follow up with a
* STOP bit
*/
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_RECEIVE_STOP);
}
}
static void i2c_cc32xx_isr(const struct device *dev)
{
uint32_t base = DEV_BASE(dev);
struct i2c_cc32xx_data *data = dev->data;
uint32_t err_status;
uint32_t int_status;
/* Get the error status of the I2C controller */
err_status = MAP_I2CMasterErr(base);
/* Get interrupt cause (from I2CMRIS (raw interrupt) reg): */
int_status = MAP_I2CMasterIntStatusEx(base, 0);
/* Clear interrupt source to avoid additional interrupts */
MAP_I2CMasterIntClearEx(base, int_status);
LOG_DBG("primed state: %d; err_status: 0x%x; int_status: 0x%x",
data->state, err_status, int_status);
/* Handle errors: */
if ((err_status != I2C_MASTER_ERR_NONE) ||
(int_status &
(I2C_MASTER_INT_ARB_LOST | I2C_MASTER_INT_TIMEOUT))) {
/* Set so API can report I/O error: */
data->state = I2C_CC32XX_ERROR;
if (!(err_status & (I2C_MASTER_ERR_ARB_LOST |
I2C_MASTER_ERR_ADDR_ACK))) {
/* Send a STOP bit to end I2C communications */
/*
* I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -and-
* I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
* have the same values
*/
MAP_I2CMasterControl(base,
I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
}
/* Indicate transfer complete */
k_sem_give(&data->transfer_complete);
/* Handle Stop: */
} else if (int_status & I2C_MASTER_INT_STOP) {
/* Indicate transfer complete */
k_sem_give(&data->transfer_complete);
/* Handle (read or write) transmit complete: */
} else if (int_status & (I2C_MASTER_INT_DATA | I2C_MASTER_INT_START)) {
if (data->state == I2C_CC32XX_WRITE_MODE) {
i2c_cc32xx_isr_handle_write(base, data);
}
if (data->state == I2C_CC32XX_READ_MODE) {
i2c_cc32xx_isr_handle_read(base, data);
}
/* Some unanticipated H/W state: */
} else {
__ASSERT(1, "Unanticipated I2C Interrupt!");
data->state = I2C_CC32XX_ERROR;
k_sem_give(&data->transfer_complete);
}
}
static int i2c_cc32xx_init(const struct device *dev)
{
uint32_t base = DEV_BASE(dev);
const struct i2c_cc32xx_config *config = dev->config;
struct i2c_cc32xx_data *data = dev->data;
uint32_t bitrate_cfg;
int error;
uint32_t regval;
/* Enable the I2C module clocks and wait for completion:*/
MAP_PRCMPeripheralClkEnable(PRCM_I2CA0,
PRCM_RUN_MODE_CLK |
PRCM_SLP_MODE_CLK);
while (!MAP_PRCMPeripheralStatusGet(PRCM_I2CA0)) {
}
error = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (error < 0) {
return error;
}
k_sem_init(&data->mutex, 1, K_SEM_MAX_LIMIT);
k_sem_init(&data->transfer_complete, 0, K_SEM_MAX_LIMIT);
/* In case of app restart: disable I2C module, clear NVIC interrupt */
/* Note: this was done *during* pinmux setup in SimpleLink SDK. */
MAP_I2CMasterDisable(base);
/* Clear exception INT_I2CA0 */
MAP_IntPendClear((unsigned long)(config->irq_no + 16));
configure_i2c_irq(config);
/* Take I2C hardware semaphore. */
regval = HWREG(COMMON_REG_BASE);
regval = (regval & ~I2C_SEM_MASK) | (0x01 << I2C_SEM_TAKE);
HWREG(COMMON_REG_BASE) = regval;
/* Set to default configuration: */
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_cc32xx_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
/* Clear any pending interrupts */
MAP_I2CMasterIntClear(base);
/* Enable the I2C Master for operation */
MAP_I2CMasterEnable(base);
/* Unmask I2C interrupts */
MAP_I2CMasterIntEnable(base);
return 0;
}
static const struct i2c_driver_api i2c_cc32xx_driver_api = {
.configure = i2c_cc32xx_configure,
.transfer = i2c_cc32xx_transfer,
};
PINCTRL_DT_INST_DEFINE(0);
static const struct i2c_cc32xx_config i2c_cc32xx_config = {
.base = DT_INST_REG_ADDR(0),
.bitrate = DT_INST_PROP(0, clock_frequency),
.irq_no = DT_INST_IRQN(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct i2c_cc32xx_data i2c_cc32xx_data;
I2C_DEVICE_DT_INST_DEFINE(0, i2c_cc32xx_init, NULL,
&i2c_cc32xx_data, &i2c_cc32xx_config,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_cc32xx_driver_api);
static void configure_i2c_irq(const struct i2c_cc32xx_config *config)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
i2c_cc32xx_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(config->irq_no);
}
``` | /content/code_sandbox/drivers/i2c/i2c_cc32xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,230 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_i2c
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <errno.h>
#include <ilm.h>
#include <soc.h>
#include <soc_dt.h>
#include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
#include <zephyr/pm/policy.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
/* Start smbus session from idle state */
#define I2C_MSG_START BIT(5)
#define I2C_LINE_SCL_HIGH BIT(0)
#define I2C_LINE_SDA_HIGH BIT(1)
#define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
#define I2C_FIFO_MODE_MAX_SIZE 32
#define I2C_FIFO_MODE_TOTAL_LEN 255
#define I2C_MSG_BURST_READ_MASK (I2C_MSG_RESTART | I2C_MSG_STOP | I2C_MSG_READ)
#endif
struct i2c_it8xxx2_config {
void (*irq_config_func)(void);
uint32_t bitrate;
uint8_t *base;
uint8_t *reg_mstfctrl;
uint8_t i2c_irq_base;
uint8_t port;
uint8_t channel_switch_sel;
/* SCL GPIO cells */
struct gpio_dt_spec scl_gpios;
/* SDA GPIO cells */
struct gpio_dt_spec sda_gpios;
/* I2C alternate configuration */
const struct pinctrl_dev_config *pcfg;
uint32_t clock_gate_offset;
bool fifo_enable;
bool push_pull_recovery;
};
enum i2c_pin_fun {
SCL = 0,
SDA,
};
enum i2c_ch_status {
I2C_CH_NORMAL = 0,
I2C_CH_REPEAT_START,
I2C_CH_WAIT_READ,
I2C_CH_WAIT_NEXT_XFER,
};
struct i2c_it8xxx2_data {
enum i2c_ch_status i2ccs;
struct i2c_msg *active_msg;
struct k_mutex mutex;
struct k_sem device_sync_sem;
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
struct i2c_msg *msgs_list;
/* Read or write byte counts. */
uint32_t bytecnt;
/* Number of messages. */
uint8_t num_msgs;
uint8_t active_msg_index;
#endif
/* Index into output data */
size_t widx;
/* Index into input data */
size_t ridx;
/* operation freq of i2c */
uint32_t bus_freq;
/* Error code, if any */
uint32_t err;
/* address of device */
uint16_t addr_16bit;
/* Frequency setting */
uint8_t freq;
/* wait for stop bit interrupt */
uint8_t stop;
};
enum i2c_host_status {
/* Host busy */
HOSTA_HOBY = 0x01,
/* Finish Interrupt */
HOSTA_FINTR = 0x02,
/* Device error */
HOSTA_DVER = 0x04,
/* Bus error */
HOSTA_BSER = 0x08,
/* Fail */
HOSTA_FAIL = 0x10,
/* Not response ACK */
HOSTA_NACK = 0x20,
/* Time-out error */
HOSTA_TMOE = 0x40,
/* Byte done status */
HOSTA_BDS = 0x80,
/* Error bit is set */
HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL |
HOSTA_NACK | HOSTA_TMOE),
/* W/C for next byte */
HOSTA_NEXT_BYTE = HOSTA_BDS,
/* W/C host status register */
HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
};
enum i2c_reset_cause {
I2C_RC_NO_IDLE_FOR_START = 1,
I2C_RC_TIMEOUT,
};
static int i2c_parsing_return_value(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
struct i2c_it8xxx2_data *data = dev->data;
if (!data->err) {
return 0;
}
if (data->err == ETIMEDOUT) {
/* Connection timed out */
LOG_ERR("I2C ch%d Address:0x%X Transaction time out.",
config->port, data->addr_16bit);
} else {
LOG_DBG("I2C ch%d Address:0x%X Host error bits message:",
config->port, data->addr_16bit);
/* Host error bits message*/
if (data->err & HOSTA_TMOE) {
LOG_ERR("Time-out error: hardware time-out error.");
}
if (data->err & HOSTA_NACK) {
LOG_DBG("NACK error: device does not response ACK.");
}
if (data->err & HOSTA_FAIL) {
LOG_ERR("Fail: a processing transmission is killed.");
}
if (data->err & HOSTA_BSER) {
LOG_ERR("BUS error: SMBus has lost arbitration.");
}
}
return -EIO;
}
static int i2c_get_line_levels(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
return (IT8XXX2_SMB_SMBPCTL(base) &
(IT8XXX2_SMB_SMBDCS | IT8XXX2_SMB_SMBCS));
}
static int i2c_is_busy(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
return (IT8XXX2_SMB_HOSTA(base) &
(HOSTA_HOBY | HOSTA_ALL_WC_BIT));
}
static int i2c_bus_not_available(const struct device *dev)
{
if (i2c_is_busy(dev) ||
(i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
return -EIO;
}
return 0;
}
static void i2c_reset(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/* bit1, kill current transaction. */
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL;
IT8XXX2_SMB_HOCTL(base) = 0;
/* W/C host status register */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
}
/*
* Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
* (offset 0h ~ 7h).
*/
static void i2c_standard_port_timing_regs_400khz(uint8_t port)
{
/* Port clock frequency depends on setting of timing registers. */
IT8XXX2_SMB_SCLKTS(port) = 0;
/* Suggested setting of timing registers of 400kHz. */
#ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
IT8XXX2_SMB_4P7USL = 0x16;
IT8XXX2_SMB_4P0USL = 0x11;
IT8XXX2_SMB_300NS = 0x8;
IT8XXX2_SMB_250NS = 0x8;
IT8XXX2_SMB_45P3USL = 0xff;
IT8XXX2_SMB_45P3USH = 0x3;
IT8XXX2_SMB_4P7A4P0H = 0;
#else
IT8XXX2_SMB_4P7USL = 0x3;
IT8XXX2_SMB_4P0USL = 0;
IT8XXX2_SMB_300NS = 0x1;
IT8XXX2_SMB_250NS = 0x5;
IT8XXX2_SMB_45P3USL = 0x6a;
IT8XXX2_SMB_45P3USH = 0x1;
IT8XXX2_SMB_4P7A4P0H = 0;
#endif
}
/* Set clock frequency for i2c port A, B , or C */
static void i2c_standard_port_set_frequency(const struct device *dev,
int freq_hz, int freq_set)
{
const struct i2c_it8xxx2_config *config = dev->config;
/*
* If port's clock frequency is 400kHz, we use timing registers
* for setting. So we can adjust tlow to meet timing.
* The others use basic 50/100/1000 KHz setting.
*/
if (freq_hz == I2C_BITRATE_FAST) {
i2c_standard_port_timing_regs_400khz(config->port);
} else {
IT8XXX2_SMB_SCLKTS(config->port) = freq_set;
}
/* This field defines the SMCLK0/1/2 clock/data low timeout. */
IT8XXX2_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
}
static int i2c_it8xxx2_configure(const struct device *dev,
uint32_t dev_config_raw)
{
const struct i2c_it8xxx2_config *config = dev->config;
struct i2c_it8xxx2_data *const data = dev->data;
uint32_t freq_set;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
data->bus_freq = I2C_SPEED_GET(dev_config_raw);
switch (data->bus_freq) {
case I2C_SPEED_DT:
freq_set = IT8XXX2_SMB_SMCLKS_50K;
break;
case I2C_SPEED_STANDARD:
freq_set = IT8XXX2_SMB_SMCLKS_100K;
break;
case I2C_SPEED_FAST:
freq_set = IT8XXX2_SMB_SMCLKS_400K;
break;
case I2C_SPEED_FAST_PLUS:
freq_set = IT8XXX2_SMB_SMCLKS_1M;
break;
default:
return -EINVAL;
}
i2c_standard_port_set_frequency(dev, config->bitrate, freq_set);
return 0;
}
static int i2c_it8xxx2_get_config(const struct device *dev,
uint32_t *dev_config)
{
struct i2c_it8xxx2_data *const data = dev->data;
uint32_t speed;
if (!data->bus_freq) {
LOG_ERR("The bus frequency is not initially configured.");
return -EIO;
}
switch (data->bus_freq) {
case I2C_SPEED_DT:
case I2C_SPEED_STANDARD:
case I2C_SPEED_FAST:
case I2C_SPEED_FAST_PLUS:
speed = I2C_SPEED_SET(data->bus_freq);
break;
default:
return -ERANGE;
}
*dev_config = (I2C_MODE_CONTROLLER | speed);
return 0;
}
void __soc_ram_code i2c_r_last_byte(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/*
* bit5, The firmware shall write 1 to this bit
* when the next byte will be the last byte for i2c read.
*/
if ((data->active_msg->flags & I2C_MSG_STOP) &&
(data->ridx == data->active_msg->len - 1)) {
IT8XXX2_SMB_HOCTL(base) |= IT8XXX2_SMB_LABY;
}
}
void __soc_ram_code i2c_w2r_change_direction(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/* I2C switch direction */
if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
i2c_r_last_byte(dev);
IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
} else {
/*
* bit2, I2C switch direction wait.
* bit3, I2C switch direction enable.
*/
IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
IT8XXX2_SMB_I2C_SW_WAIT;
IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
i2c_r_last_byte(dev);
IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
}
}
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
void __soc_ram_code i2c_fifo_en_w2r(const struct device *dev, bool enable)
{
const struct i2c_it8xxx2_config *config = dev->config;
unsigned int key = irq_lock();
if (enable) {
if (config->port == SMB_CHANNEL_A) {
IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MAIF |
IT8XXX2_SMB_MAIFI;
} else if (config->port == SMB_CHANNEL_B) {
IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
IT8XXX2_SMB_MBIFI;
} else if (config->port == SMB_CHANNEL_C) {
IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
IT8XXX2_SMB_MCIFI;
}
} else {
if (config->port == SMB_CHANNEL_A) {
IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MAIF |
IT8XXX2_SMB_MAIFI);
} else if (config->port == SMB_CHANNEL_B) {
IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
IT8XXX2_SMB_MBIFI);
} else if (config->port == SMB_CHANNEL_C) {
IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
IT8XXX2_SMB_MCIFI);
}
}
irq_unlock(key);
}
void __soc_ram_code i2c_tran_fifo_write_start(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint32_t i;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
/* Clear start flag. */
data->active_msg->flags &= ~I2C_MSG_START;
/* Enable SMB channel in FIFO mode. */
*reg_mstfctrl |= IT8XXX2_SMB_FFEN;
/* I2C enable. */
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
IT8XXX2_SMB_I2C_EN |
IT8XXX2_SMB_SMHEN;
/* Set write byte counts. */
IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
/*
* bit[7:1]: Address of the target.
* bit[0]: Direction of the host transfer.
*/
IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
/* The maximum fifo size is 32 bytes. */
data->bytecnt = MIN(data->active_msg->len, I2C_FIFO_MODE_MAX_SIZE);
for (i = 0; i < data->bytecnt; i++) {
/* Set host block data byte. */
IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
}
/* Calculate the remaining byte counts. */
data->bytecnt = data->active_msg->len - data->bytecnt;
/*
* bit[6] = 1b: Start.
* bit[4:2] = 111b: Extend command.
* bit[0] = 1b: Host interrupt enable.
*/
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
IT8XXX2_SMB_SMCD_EXTND |
IT8XXX2_SMB_INTREN;
}
void __soc_ram_code i2c_tran_fifo_write_next_block(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint32_t i, _bytecnt;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
/* The maximum fifo size is 32 bytes. */
_bytecnt = MIN(data->bytecnt, I2C_FIFO_MODE_MAX_SIZE);
for (i = 0; i < _bytecnt; i++) {
/* Set host block data byte. */
IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
}
/* Clear FIFO block done status. */
*reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
/* Calculate the remaining byte counts. */
data->bytecnt -= _bytecnt;
}
void __soc_ram_code i2c_tran_fifo_write_finish(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/* Clear byte count register. */
IT8XXX2_SMB_D0REG(base) = 0;
/* W/C */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
/* Disable the SMBus host interface. */
IT8XXX2_SMB_HOCTL2(base) = 0x00;
}
int __soc_ram_code i2c_tran_fifo_w2r_change_direction(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
if (++data->active_msg_index >= data->num_msgs) {
LOG_ERR("Current message index is error.");
data->err = EINVAL;
/* W/C */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
/* Disable the SMBus host interface. */
IT8XXX2_SMB_HOCTL2(base) = 0x00;
return 0;
}
/* Set I2C_SW_EN = 1 */
IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
IT8XXX2_SMB_I2C_SW_WAIT;
IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
/* Point to the next msg for the read location. */
data->active_msg = &data->msgs_list[data->active_msg_index];
/* Set read byte counts. */
IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
data->bytecnt = data->active_msg->len;
/* W/C I2C W2R FIFO interrupt status. */
IT8XXX2_SMB_IWRFISTA = BIT(config->port);
return 1;
}
void __soc_ram_code i2c_tran_fifo_read_start(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
/* Clear start flag. */
data->active_msg->flags &= ~I2C_MSG_START;
/* Enable SMB channel in FIFO mode. */
*reg_mstfctrl |= IT8XXX2_SMB_FFEN;
/* I2C enable. */
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
IT8XXX2_SMB_I2C_EN |
IT8XXX2_SMB_SMHEN;
/* Set read byte counts. */
IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
/*
* bit[7:1]: Address of the target.
* bit[0]: Direction of the host transfer.
*/
IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
IT8XXX2_SMB_DIR;
data->bytecnt = data->active_msg->len;
/*
* bit[6] = 1b: Start.
* bit[4:2] = 111b: Extend command.
* bit[0] = 1b: Host interrupt enable.
*/
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
IT8XXX2_SMB_SMCD_EXTND |
IT8XXX2_SMB_INTREN;
}
void __soc_ram_code i2c_tran_fifo_read_next_block(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint32_t i;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
for (i = 0; i < I2C_FIFO_MODE_MAX_SIZE; i++) {
/* To get received data. */
*(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
}
/* Clear FIFO block done status. */
*reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
/* Calculate the remaining byte counts. */
data->bytecnt -= I2C_FIFO_MODE_MAX_SIZE;
}
void __soc_ram_code i2c_tran_fifo_read_finish(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint32_t i;
uint8_t *base = config->base;
for (i = 0; i < data->bytecnt; i++) {
/* To get received data. */
*(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
}
/* Clear byte count register. */
IT8XXX2_SMB_D0REG(base) = 0;
/* W/C */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
/* Disable the SMBus host interface. */
IT8XXX2_SMB_HOCTL2(base) = 0x00;
}
int __soc_ram_code i2c_tran_fifo_write_to_read(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
int ret = 1;
if (data->active_msg->flags & I2C_MSG_START) {
/* Enable I2C write to read FIFO mode. */
i2c_fifo_en_w2r(dev, 1);
i2c_tran_fifo_write_start(dev);
} else {
/* Check block done status. */
if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
i2c_tran_fifo_read_next_block(dev);
} else {
i2c_tran_fifo_write_next_block(dev);
}
} else if (IT8XXX2_SMB_IWRFISTA & BIT(config->port)) {
/*
* This function returns 0 on a failure to indicate
* that the current transaction is completed and
* returned the data->err.
*/
ret = i2c_tran_fifo_w2r_change_direction(dev);
} else {
/* Wait finish. */
if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
i2c_tran_fifo_read_finish(dev);
/* Done doing work. */
ret = 0;
}
}
}
return ret;
}
int __soc_ram_code i2c_tran_fifo_read(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
if (data->active_msg->flags & I2C_MSG_START) {
i2c_tran_fifo_read_start(dev);
} else {
/* Check block done status. */
if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
i2c_tran_fifo_read_next_block(dev);
} else {
/* Wait finish. */
if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
i2c_tran_fifo_read_finish(dev);
/* Done doing work. */
return 0;
}
}
}
return 1;
}
int __soc_ram_code i2c_tran_fifo_write(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
if (data->active_msg->flags & I2C_MSG_START) {
i2c_tran_fifo_write_start(dev);
} else {
/* Check block done status. */
if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
i2c_tran_fifo_write_next_block(dev);
} else {
/* Wait finish. */
if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
i2c_tran_fifo_write_finish(dev);
/* Done doing work. */
return 0;
}
}
}
return 1;
}
int __soc_ram_code i2c_fifo_transaction(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/* Any error. */
if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
} else {
if (data->num_msgs == 2) {
return i2c_tran_fifo_write_to_read(dev);
} else if (data->active_msg->flags & I2C_MSG_READ) {
return i2c_tran_fifo_read(dev);
} else {
return i2c_tran_fifo_write(dev);
}
}
/* W/C */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
/* Disable the SMBus host interface. */
IT8XXX2_SMB_HOCTL2(base) = 0x00;
return 0;
}
bool __soc_ram_code fifo_mode_allowed(const struct device *dev,
struct i2c_msg *msgs)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
/*
* If the transaction of write or read is divided into two
* transfers(not two messages), the FIFO mode does not support.
*/
if (data->i2ccs != I2C_CH_NORMAL) {
return false;
}
/*
* FIFO2 only supports one channel of B or C. If the FIFO of
* channel is not enabled, it will select PIO mode.
*/
if (!config->fifo_enable) {
return false;
}
/*
* When there is only one message, use the FIFO mode transfer
* directly.
* Transfer payload too long (>255 bytes), use PIO mode.
* Write or read of I2C target address without data, used by
* cmd_i2c_scan. Use PIO mode.
*/
if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP) &&
(msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN) && (msgs[0].len != 0)) {
return true;
}
/*
* When there are two messages, we need to judge whether or not there
* is I2C_MSG_RESTART flag from the second message, and then decide to
* do the FIFO mode or PIO mode transfer.
*/
if (data->num_msgs == 2) {
/*
* The first of two messages must be write.
* Transfer payload too long (>255 bytes), use PIO mode.
*/
if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
(msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
/*
* The transfer is i2c_burst_read().
*
* e.g. msg[0].flags = I2C_MSG_WRITE;
* msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
* I2C_MSG_STOP;
*/
if ((msgs[1].flags == I2C_MSG_BURST_READ_MASK) &&
(msgs[1].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
return true;
}
}
}
return false;
}
#endif
int __soc_ram_code i2c_tran_read(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
if (data->active_msg->flags & I2C_MSG_START) {
/* i2c enable */
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
IT8XXX2_SMB_I2C_EN |
IT8XXX2_SMB_SMHEN;
/*
* bit0, Direction of the host transfer.
* bit[1:7}, Address of the targeted slave.
*/
IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
IT8XXX2_SMB_DIR;
/* clear start flag */
data->active_msg->flags &= ~I2C_MSG_START;
/*
* bit0, Host interrupt enable.
* bit[2:4}, Extend command.
* bit5, The firmware shall write 1 to this bit
* when the next byte will be the last byte.
* bit6, start.
*/
if ((data->active_msg->len == 1) &&
(data->active_msg->flags & I2C_MSG_STOP)) {
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
IT8XXX2_SMB_LABY |
IT8XXX2_SMB_SMCD_EXTND |
IT8XXX2_SMB_INTREN;
} else {
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
IT8XXX2_SMB_SMCD_EXTND |
IT8XXX2_SMB_INTREN;
}
} else {
if ((data->i2ccs == I2C_CH_REPEAT_START) ||
(data->i2ccs == I2C_CH_WAIT_READ)) {
if (data->i2ccs == I2C_CH_REPEAT_START) {
/* write to read */
i2c_w2r_change_direction(dev);
} else {
/* For last byte */
i2c_r_last_byte(dev);
/* W/C for next byte */
IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
}
data->i2ccs = I2C_CH_NORMAL;
} else if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
if (data->ridx < data->active_msg->len) {
/* To get received data. */
*(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
data->ridx++;
/* For last byte */
i2c_r_last_byte(dev);
/* done */
if (data->ridx == data->active_msg->len) {
data->active_msg->len = 0;
if (data->active_msg->flags & I2C_MSG_STOP) {
/* W/C for finish */
IT8XXX2_SMB_HOSTA(base) =
HOSTA_NEXT_BYTE;
data->stop = 1;
} else {
data->i2ccs = I2C_CH_WAIT_READ;
return 0;
}
} else {
/* W/C for next byte */
IT8XXX2_SMB_HOSTA(base) =
HOSTA_NEXT_BYTE;
}
}
}
}
return 1;
}
int __soc_ram_code i2c_tran_write(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
if (data->active_msg->flags & I2C_MSG_START) {
/* i2c enable */
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
IT8XXX2_SMB_I2C_EN |
IT8XXX2_SMB_SMHEN;
/*
* bit0, Direction of the host transfer.
* bit[1:7}, Address of the targeted slave.
*/
IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
/* Send first byte */
IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
data->widx++;
/* clear start flag */
data->active_msg->flags &= ~I2C_MSG_START;
/*
* bit0, Host interrupt enable.
* bit[2:4}, Extend command.
* bit6, start.
*/
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
IT8XXX2_SMB_SMCD_EXTND |
IT8XXX2_SMB_INTREN;
} else {
/* Host has completed the transmission of a byte */
if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
if (data->widx < data->active_msg->len) {
/* Send next byte */
IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
data->widx++;
/* W/C byte done for next byte */
IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
if (data->i2ccs == I2C_CH_REPEAT_START) {
data->i2ccs = I2C_CH_NORMAL;
}
} else {
/* done */
data->active_msg->len = 0;
if (data->active_msg->flags & I2C_MSG_STOP) {
/* set I2C_EN = 0 */
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
IT8XXX2_SMB_SMHEN;
/* W/C byte done for finish */
IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
data->stop = 1;
} else {
data->i2ccs = I2C_CH_REPEAT_START;
return 0;
}
}
}
}
return 1;
}
int __soc_ram_code i2c_pio_transaction(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
/* any error */
if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
} else {
if (!data->stop) {
/*
* The return value indicates if there is more data
* to be read or written. If the return value = 1,
* it means that the interrupt cannot be disable and
* continue to transmit data.
*/
if (data->active_msg->flags & I2C_MSG_READ) {
return i2c_tran_read(dev);
} else {
return i2c_tran_write(dev);
}
}
/* wait finish */
if (!(IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
return 1;
}
}
/* W/C */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
/* disable the SMBus host interface */
IT8XXX2_SMB_HOCTL2(base) = 0x00;
data->stop = 0;
/* done doing work */
return 0;
}
static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
int res, ret;
/* Lock mutex of i2c controller */
k_mutex_lock(&data->mutex, K_FOREVER);
/*
* If the transaction of write to read is divided into two
* transfers, the repeat start transfer uses this flag to
* exclude checking bus busy.
*/
if (data->i2ccs == I2C_CH_NORMAL) {
struct i2c_msg *start_msg = &msgs[0];
/* Make sure we're in a good state to start */
if (i2c_bus_not_available(dev)) {
/* Recovery I2C bus */
i2c_recover_bus(dev);
/*
* After resetting I2C bus, if I2C bus is not available
* (No external pull-up), drop the transaction.
*/
if (i2c_bus_not_available(dev)) {
/* Unlock mutex of i2c controller */
k_mutex_unlock(&data->mutex);
return -EIO;
}
}
start_msg->flags |= I2C_MSG_START;
}
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
/* Store num_msgs to data struct. */
data->num_msgs = num_msgs;
/* Store msgs to data struct. */
data->msgs_list = msgs;
bool fifo_mode_enable = fifo_mode_allowed(dev, msgs);
if (fifo_mode_enable) {
/* Block to enter power policy. */
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
#endif
for (int i = 0; i < num_msgs; i++) {
data->widx = 0;
data->ridx = 0;
data->err = 0;
data->active_msg = &msgs[i];
data->addr_16bit = addr;
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
data->active_msg_index = 0;
/*
* Start transaction.
* The return value indicates if the initial configuration
* of I2C transaction for read or write has been completed.
*/
if (fifo_mode_enable) {
if (i2c_fifo_transaction(dev)) {
/* Enable i2c interrupt */
irq_enable(config->i2c_irq_base);
}
} else
#endif
{
if (i2c_pio_transaction(dev)) {
/* Enable i2c interrupt */
irq_enable(config->i2c_irq_base);
}
}
/* Wait for the transfer to complete */
/* TODO: the timeout should be adjustable */
res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
/*
* The irq will be enabled at the condition of start or
* repeat start of I2C. If timeout occurs without being
* wake up during suspend(ex: interrupt is not fired),
* the irq should be disabled immediately.
*/
irq_disable(config->i2c_irq_base);
/*
* The transaction is dropped on any error(timeout, NACK, fail,
* bus error, device error).
*/
if (data->err) {
break;
}
if (res != 0) {
data->err = ETIMEDOUT;
/* reset i2c port */
i2c_reset(dev);
LOG_ERR("I2C ch%d:0x%X reset cause %d",
config->port, data->addr_16bit, I2C_RC_TIMEOUT);
/* If this message is sent fail, drop the transaction. */
break;
}
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
/*
* In FIFO mode, messages are compressed into a single
* transaction.
*/
if (fifo_mode_enable) {
break;
}
#endif
}
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
if (fifo_mode_enable) {
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
/* Disable SMB channels in FIFO mode. */
*reg_mstfctrl &= ~IT8XXX2_SMB_FFEN;
/* Disable I2C write to read FIFO mode. */
if (data->num_msgs == 2) {
i2c_fifo_en_w2r(dev, 0);
}
/* Permit to enter power policy. */
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
#endif
/* reset i2c channel status */
if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
data->i2ccs = I2C_CH_NORMAL;
}
/* Save return value. */
ret = i2c_parsing_return_value(dev);
/* Unlock mutex of i2c controller */
k_mutex_unlock(&data->mutex);
return ret;
}
static void i2c_it8xxx2_isr(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
/* If done doing work, wake up the task waiting for the transfer. */
if (config->fifo_enable && (*reg_mstfctrl & IT8XXX2_SMB_FFEN)) {
if (i2c_fifo_transaction(dev)) {
return;
}
} else
#endif
{
if (i2c_pio_transaction(dev)) {
return;
}
}
irq_disable(config->i2c_irq_base);
k_sem_give(&data->device_sync_sem);
}
static int i2c_it8xxx2_init(const struct device *dev)
{
struct i2c_it8xxx2_data *data = dev->data;
const struct i2c_it8xxx2_config *config = dev->config;
uint8_t *base = config->base;
uint32_t bitrate_cfg;
int error, status;
/* Initialize mutex and semaphore */
k_mutex_init(&data->mutex);
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
/* Enable clock to specified peripheral */
volatile uint8_t *reg = (volatile uint8_t *)
(IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
uint8_t reg_mask = config->clock_gate_offset & 0xff;
*reg &= ~reg_mask;
/* Enable SMBus function */
/*
* bit0, The SMBus host interface is enabled.
* bit1, Enable to communicate with I2C device
* and support I2C-compatible cycles.
* bit4, This bit controls the reset mechanism
* of SMBus master to handle the SMDAT
* line low if 25ms reg timeout.
*/
IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN | IT8XXX2_SMB_SMHEN;
/*
* bit1, Kill SMBus host transaction.
* bit0, Enable the interrupt for the master interface.
*/
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL | IT8XXX2_SMB_SMHEN;
IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SMHEN;
/* W/C host status register */
IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
IT8XXX2_SMB_HOCTL2(base) = 0x00;
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
if (config->port == SMB_CHANNEL_B && config->fifo_enable) {
/* Select channel B in FIFO2. */
*reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_B;
} else if (config->port == SMB_CHANNEL_C && config->fifo_enable) {
/* Select channel C in FIFO2. */
*reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_C;
}
#endif
/* ChannelA-C switch selection of I2C pin */
if (config->port == SMB_CHANNEL_A) {
IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
config->channel_switch_sel;
} else if (config->port == SMB_CHANNEL_B) {
IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
(IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
} else if (config->port == SMB_CHANNEL_C) {
IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
config->channel_switch_sel;
}
/* Set clock frequency for I2C ports */
if (config->bitrate == I2C_BITRATE_STANDARD ||
config->bitrate == I2C_BITRATE_FAST ||
config->bitrate == I2C_BITRATE_FAST_PLUS) {
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
} else {
/* Device tree specified speed */
bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
}
error = i2c_it8xxx2_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
data->i2ccs = I2C_CH_NORMAL;
if (error) {
LOG_ERR("i2c: failure initializing");
return error;
}
/* Set the pin to I2C alternate function. */
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure I2C pins");
return status;
}
return 0;
}
static int i2c_it8xxx2_recover_bus(const struct device *dev)
{
const struct i2c_it8xxx2_config *config = dev->config;
int i, status;
/* Output type selection */
gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
/* Set SCL of I2C as GPIO pin */
gpio_pin_configure_dt(&config->scl_gpios, flags);
/* Set SDA of I2C as GPIO pin */
gpio_pin_configure_dt(&config->sda_gpios, flags);
/*
* In I2C recovery bus, 1ms sleep interval for bitbanging i2c
* is mainly to ensure that gpio has enough time to go from
* low to high or high to low.
*/
/* Pull SCL and SDA pin to high */
gpio_pin_set_dt(&config->scl_gpios, 1);
gpio_pin_set_dt(&config->sda_gpios, 1);
k_msleep(1);
/* Start condition */
gpio_pin_set_dt(&config->sda_gpios, 0);
k_msleep(1);
gpio_pin_set_dt(&config->scl_gpios, 0);
k_msleep(1);
/* 9 cycles of SCL with SDA held high */
for (i = 0; i < 9; i++) {
/* SDA */
gpio_pin_set_dt(&config->sda_gpios, 1);
/* SCL */
gpio_pin_set_dt(&config->scl_gpios, 1);
k_msleep(1);
/* SCL */
gpio_pin_set_dt(&config->scl_gpios, 0);
k_msleep(1);
}
/* SDA */
gpio_pin_set_dt(&config->sda_gpios, 0);
k_msleep(1);
/* Stop condition */
gpio_pin_set_dt(&config->scl_gpios, 1);
k_msleep(1);
gpio_pin_set_dt(&config->sda_gpios, 1);
k_msleep(1);
/* Set GPIO back to I2C alternate function of SCL */
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure I2C pins");
return status;
}
/* reset i2c port */
i2c_reset(dev);
LOG_ERR("I2C ch%d reset cause %d", config->port,
I2C_RC_NO_IDLE_FOR_START);
return 0;
}
static const struct i2c_driver_api i2c_it8xxx2_driver_api = {
.configure = i2c_it8xxx2_configure,
.get_config = i2c_it8xxx2_get_config,
.transfer = i2c_it8xxx2_transfer,
.recover_bus = i2c_it8xxx2_recover_bus,
};
#ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
/*
* Sometimes, channel C may write wrong register to the target device.
* This issue occurs when FIFO2 is enabled on channel C. The problem
* arises because FIFO2 is shared between channel B and channel C.
* FIFO2 will be disabled when data access is completed, at which point
* FIFO2 is set to the default configuration for channel B.
* The byte counter of FIFO2 may be affected by channel B. There is a chance
* that channel C may encounter wrong register being written due to FIFO2
* byte counter wrong write after channel B's write operation.
*/
BUILD_ASSERT((DT_PROP(DT_NODELABEL(i2c2), fifo_enable) == false),
"Channel C cannot use FIFO mode.");
#endif
#ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
#define I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK(inst) \
BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_FAST), "Only supports 400 KHz");
DT_INST_FOREACH_STATUS_OKAY(I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK)
#endif
#define I2C_ITE_IT8XXX2_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
50000) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_STANDARD) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_FAST) || \
(DT_INST_PROP(inst, clock_frequency) == \
I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
static void i2c_it8xxx2_config_func_##inst(void); \
\
static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##inst = { \
.base = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 0)), \
.reg_mstfctrl = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 1)), \
.irq_config_func = i2c_it8xxx2_config_func_##inst, \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
.i2c_irq_base = DT_INST_IRQN(inst), \
.port = DT_INST_PROP(inst, port_num), \
.channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
.scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
.sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
.clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.fifo_enable = DT_INST_PROP(inst, fifo_enable), \
.push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \
}; \
\
static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \
\
I2C_DEVICE_DT_INST_DEFINE(inst, i2c_it8xxx2_init, \
NULL, \
&i2c_it8xxx2_data_##inst, \
&i2c_it8xxx2_cfg_##inst, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_it8xxx2_driver_api); \
\
static void i2c_it8xxx2_config_func_##inst(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
0, \
i2c_it8xxx2_isr, \
DEVICE_DT_INST_GET(inst), 0); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 12,388 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_i2c_port
/**
* @file
* @brief Nuvoton NPCX smb/i2c port driver
*
* This file contains the driver of SMBus/I2C buses (ports) which provides
* pin-muxing for each i2c io-pads. In order to support "SMBus Multi-Bus"
* feature, please refer the diagram below, the driver also provides connection
* between Zephyr i2c api functions and i2c controller driver which provides
* full support for SMBus/I2C transactions.
*
* Port SEL
* |
* |\|
* SCL_N Port 0----| \ +--------------+
* SDA_N Port 0----| |----| SMB/I2C |
* | |----| Controller N |
* SCL_N Port 1----| | +--------------+
* SDA_N Port 1----| /
* |/
*
*/
#include <assert.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_npcx_port, LOG_LEVEL_ERR);
#include "i2c_npcx_controller.h"
#include "i2c-priv.h"
/* Device config */
struct i2c_npcx_port_config {
uint32_t bitrate;
uint8_t port;
const struct device *i2c_ctrl;
/* pinmux configuration */
const struct pinctrl_dev_config *pcfg;
};
/* I2C api functions */
static int i2c_npcx_port_configure(const struct device *dev,
uint32_t dev_config)
{
const struct i2c_npcx_port_config *const config = dev->config;
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!",
config->port);
return -EIO;
}
if (!(dev_config & I2C_MODE_CONTROLLER)) {
return -ENOTSUP;
}
if (dev_config & I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
/* Configure i2c controller */
return npcx_i2c_ctrl_configure(config->i2c_ctrl, dev_config);
}
static int i2c_npcx_port_get_config(const struct device *dev, uint32_t *dev_config)
{
const struct i2c_npcx_port_config *const config = dev->config;
uint32_t speed;
int ret;
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!", config->port);
return -EIO;
}
ret = npcx_i2c_ctrl_get_speed(config->i2c_ctrl, &speed);
if (!ret) {
*dev_config = (I2C_MODE_CONTROLLER | speed);
}
return ret;
}
static int i2c_npcx_port_transfer(const struct device *dev,
struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr)
{
const struct i2c_npcx_port_config *const config = dev->config;
int ret = 0;
int idx_ctrl = (config->port & 0xF0) >> 4;
int idx_port = (config->port & 0x0F);
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!",
config->port);
return -EIO;
}
/* Lock mutex of i2c/smb controller */
npcx_i2c_ctrl_mutex_lock(config->i2c_ctrl);
/* Switch correct port for i2c controller first */
npcx_pinctrl_i2c_port_sel(idx_ctrl, idx_port);
/* Start transaction with i2c controller */
ret = npcx_i2c_ctrl_transfer(config->i2c_ctrl, msgs, num_msgs, addr,
config->port);
/* Unlock mutex of i2c/smb controller */
npcx_i2c_ctrl_mutex_unlock(config->i2c_ctrl);
return ret;
}
static int i2c_npcx_port_recover_bus(const struct device *dev)
{
const struct i2c_npcx_port_config *const config = dev->config;
int ret;
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!", config->port);
return -EIO;
}
/* Lock mutex of i2c/smb controller */
npcx_i2c_ctrl_mutex_lock(config->i2c_ctrl);
ret = npcx_i2c_ctrl_recover_bus(config->i2c_ctrl);
/* Unlock mutex of i2c/smb controller */
npcx_i2c_ctrl_mutex_unlock(config->i2c_ctrl);
return ret;
}
#ifdef CONFIG_I2C_TARGET
static int i2c_npcx_target_register(const struct device *dev,
struct i2c_target_config *target_cfg)
{
const struct i2c_npcx_port_config *const config = dev->config;
if (!target_cfg) {
return -EINVAL;
}
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!", config->port);
return -EIO;
}
return npcx_i2c_ctrl_target_register(config->i2c_ctrl, target_cfg, config->port);
}
static int i2c_npcx_target_unregister(const struct device *dev,
struct i2c_target_config *target_cfg)
{
const struct i2c_npcx_port_config *const config = dev->config;
if (config->i2c_ctrl == NULL) {
LOG_ERR("Cannot find i2c controller on port%02x!", config->port);
return -EIO;
}
return npcx_i2c_ctrl_target_unregister(config->i2c_ctrl, target_cfg);
}
#endif
/* I2C driver registration */
static int i2c_npcx_port_init(const struct device *dev)
{
const struct i2c_npcx_port_config *const config = dev->config;
uint32_t i2c_config;
int ret;
/* Configure pin-mux for I2C device */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("I2C pinctrl setup failed (%d)", ret);
return ret;
}
/* Setup initial i2c configuration */
i2c_config = (I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
ret = i2c_npcx_port_configure(dev, i2c_config);
if (ret != 0) {
return ret;
}
return 0;
}
static const struct i2c_driver_api i2c_port_npcx_driver_api = {
.configure = i2c_npcx_port_configure,
.get_config = i2c_npcx_port_get_config,
.transfer = i2c_npcx_port_transfer,
.recover_bus = i2c_npcx_port_recover_bus,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_npcx_target_register,
.target_unregister = i2c_npcx_target_unregister,
#endif
};
/* I2C port init macro functions */
#define NPCX_I2C_PORT_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
static const struct i2c_npcx_port_config i2c_npcx_port_cfg_##inst = { \
.port = DT_INST_PROP(inst, port), \
.bitrate = DT_INST_PROP(inst, clock_frequency), \
.i2c_ctrl = DEVICE_DT_GET(DT_INST_PHANDLE(inst, controller)), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(inst, \
i2c_npcx_port_init, \
NULL, NULL, \
&i2c_npcx_port_cfg_##inst, \
PRE_KERNEL_1, CONFIG_I2C_NPCX_PORT_INIT_PRIORITY, \
&i2c_port_npcx_driver_api);
DT_INST_FOREACH_STATUS_OKAY(NPCX_I2C_PORT_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_npcx_port.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,814 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_i2c_v2
#include <zephyr/kernel.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/sys/printk.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#define SPEED_100KHZ_BUS 0
#define SPEED_400KHZ_BUS 1
#define SPEED_1MHZ_BUS 2
#define EC_OWN_I2C_ADDR 0x7F
#define RESET_WAIT_US 20
/* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
#define WAIT_INTERVAL 50
#define WAIT_COUNT 200
#define STOP_WAIT_COUNT 500
#define PIN_CFG_WAIT 50
/* I2C Read/Write bit pos */
#define I2C_READ_WRITE_POS 0
/* I2C recover SCL low retries */
#define I2C_RECOVER_SCL_LOW_RETRIES 10
/* I2C recover SDA low retries */
#define I2C_RECOVER_SDA_LOW_RETRIES 3
/* I2C recovery bit bang delay */
#define I2C_RECOVER_BB_DELAY_US 5
/* I2C recovery SCL sample delay */
#define I2C_RECOVER_SCL_DELAY_US 50
/* I2C SCL and SDA lines(signals) */
#define I2C_LINES_SCL_HI BIT(SOC_I2C_SCL_POS)
#define I2C_LINES_SDA_HI BIT(SOC_I2C_SDA_POS)
#define I2C_LINES_BOTH_HI (I2C_LINES_SCL_HI | I2C_LINES_SDA_HI)
#define I2C_START 0U
#define I2C_RPT_START 1U
#define I2C_ENI_DIS 0U
#define I2C_ENI_EN 1U
#define I2C_WAIT_PIN_DEASSERT 0U
#define I2C_WAIT_PIN_ASSERT 1U
#define I2C_XEC_CTRL_WR_DLY 8
#define I2C_XEC_STATE_STOPPED 1U
#define I2C_XEC_STATE_OPEN 2U
#define I2C_XEC_OK 0
#define I2C_XEC_ERR_LAB 1
#define I2C_XEC_ERR_BUS 2
#define I2C_XEC_ERR_TMOUT 3
#define XEC_GPIO_CTRL_BASE DT_REG_ADDR(DT_NODELABEL(gpio_000_036))
struct xec_speed_cfg {
uint32_t bus_clk;
uint32_t data_timing;
uint32_t start_hold_time;
uint32_t idle_scale;
uint32_t timeout_scale;
};
struct i2c_xec_config {
uint32_t port_sel;
uint32_t base_addr;
uint32_t clock_freq;
uint8_t girq;
uint8_t girq_pos;
uint8_t pcr_idx;
uint8_t pcr_bitpos;
const struct pinctrl_dev_config *pcfg;
void (*irq_config_func)(void);
};
struct i2c_xec_data {
uint8_t state;
uint8_t read_discard;
uint8_t speed_id;
struct i2c_target_config *target_cfg;
bool target_attached;
bool target_read;
uint32_t i2c_compl;
uint8_t i2c_ctrl;
uint8_t i2c_addr;
uint8_t i2c_status;
};
/* Recommended programming values based on 16MHz
* i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
* bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
* (16MHz/400KHz -2) = 0x0F + 0x17
* (16MHz/1MHz -2) = 0x05 + 0x09
*/
static const struct xec_speed_cfg xec_cfg_params[] = {
[SPEED_100KHZ_BUS] = {
.bus_clk = 0x00004F4F,
.data_timing = 0x0C4D5006,
.start_hold_time = 0x0000004D,
.idle_scale = 0x01FC01ED,
.timeout_scale = 0x4B9CC2C7,
},
[SPEED_400KHZ_BUS] = {
.bus_clk = 0x00000F17,
.data_timing = 0x040A0A06,
.start_hold_time = 0x0000000A,
.idle_scale = 0x01000050,
.timeout_scale = 0x159CC2C7,
},
[SPEED_1MHZ_BUS] = {
.bus_clk = 0x00000509,
.data_timing = 0x04060601,
.start_hold_time = 0x00000006,
.idle_scale = 0x10000050,
.timeout_scale = 0x089CC2C7,
},
};
static void i2c_ctl_wr(const struct device *dev, uint8_t ctrl)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
data->i2c_ctrl = ctrl;
regs->CTRLSTS = ctrl;
for (int i = 0; i < I2C_XEC_CTRL_WR_DLY; i++) {
regs->BLKID = ctrl;
}
}
static int i2c_xec_reset_config(const struct device *dev);
static int wait_bus_free(const struct device *dev, uint32_t nwait)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
uint32_t count = nwait;
uint8_t sts = 0;
while (count--) {
sts = regs->CTRLSTS;
data->i2c_status = sts;
if (sts & MCHP_I2C_SMB_STS_NBB) {
break; /* bus is free */
}
k_busy_wait(WAIT_INTERVAL);
}
/* NBB -> 1 not busy can occur for STOP, BER, or LAB */
if (sts == (MCHP_I2C_SMB_STS_PIN | MCHP_I2C_SMB_STS_NBB)) {
/* No service requested(PIN=1), NotBusy(NBB=1), and no errors */
return 0;
}
if (sts & MCHP_I2C_SMB_STS_BER) {
return I2C_XEC_ERR_BUS;
}
if (sts & MCHP_I2C_SMB_STS_LAB) {
return I2C_XEC_ERR_LAB;
}
return I2C_XEC_ERR_TMOUT;
}
/*
* returns state of I2C SCL and SDA lines.
* b[0] = SCL, b[1] = SDA
* Call soc specific routine to read GPIO pad input.
* Why? We can get the pins from our PINCTRL info but
* we do not know which pin is I2C clock and which pin
* is I2C data. There's no ordering in PINCTRL DT unless
* we impose an order.
*/
static uint32_t get_lines(const struct device *dev)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
uint8_t port = regs->CFG & MCHP_I2C_SMB_CFG_PORT_SEL_MASK;
uint32_t lines = 0u;
soc_i2c_port_lines_get(port, &lines);
return lines;
}
static int i2c_xec_reset_config(const struct device *dev)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
data->state = I2C_XEC_STATE_STOPPED;
data->read_discard = 0;
/* Assert RESET */
z_mchp_xec_pcr_periph_reset(cfg->pcr_idx, cfg->pcr_bitpos);
regs->CFG = MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
/* PIN=1 to clear all status except NBB and synchronize */
i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN);
/*
* Controller implements two peripheral addresses for itself.
* It always monitors whether an external controller issues START
* plus target address. We should write valid peripheral addresses
* that do not match any peripheral on the bus.
* An alternative is to use the default 0 value which is the
* general call address and disable the general call match
* enable in the configuration register.
*/
regs->OWN_ADDR = EC_OWN_I2C_ADDR | (EC_OWN_I2C_ADDR << 8);
#ifdef CONFIG_I2C_TARGET
if (data->target_cfg) {
regs->OWN_ADDR = data->target_cfg->address;
}
#endif
/* Port number and filter enable MUST be written before enabling */
regs->CFG |= BIT(14); /* disable general call */
regs->CFG |= MCHP_I2C_SMB_CFG_FEN;
regs->CFG |= (cfg->port_sel & MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
/*
* Before enabling the controller program the desired bus clock,
* repeated start hold time, data timing, and timeout scaling
* registers.
*/
regs->BUSCLK = xec_cfg_params[data->speed_id].bus_clk;
regs->RSHTM = xec_cfg_params[data->speed_id].start_hold_time;
regs->DATATM = xec_cfg_params[data->speed_id].data_timing;
regs->TMOUTSC = xec_cfg_params[data->speed_id].timeout_scale;
regs->IDLSC = xec_cfg_params[data->speed_id].idle_scale;
/*
* PIN=1 clears all status except NBB
* ESO=1 enables output drivers
* ACK=1 enable ACK generation when data/address is clocked in.
*/
i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN |
MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ACK);
/* Enable controller */
regs->CFG |= MCHP_I2C_SMB_CFG_ENAB;
k_busy_wait(RESET_WAIT_US);
/* wait for NBB=1, BER, LAB, or timeout */
int rc = wait_bus_free(dev, WAIT_COUNT);
return rc;
}
/*
* If SCL is low sample I2C_RECOVER_SCL_LOW_RETRIES times with a 5 us delay
* between samples. If SCL remains low then return -EBUSY
* If SCL is High and SDA is low then loop up to I2C_RECOVER_SDA_LOW_RETRIES
* times driving the pins:
* Drive SCL high
* delay I2C_RECOVER_BB_DELAY_US
* Generate 9 clock pulses on SCL checking SDA before each falling edge of SCL
* If SDA goes high exit clock loop else to all 9 clocks
* Drive SDA low, delay 5 us, release SDA, delay 5 us
* Both lines are high then exit SDA recovery loop
* Both lines should not be driven
* Check both lines: if any bad return error else return success
* NOTE 1: Bit-bang mode uses a HW MUX to switch the lines away from the I2C
* controller logic to BB logic.
* NOTE 2: Bit-bang mode requires HW timeouts to be disabled.
* NOTE 3: Bit-bang mode requires the controller's configuration enable bit
* to be set.
* NOTE 4: The controller must be reset after using bit-bang mode.
*/
static int i2c_xec_recover_bus(const struct device *dev)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
int i, j, ret;
LOG_ERR("I2C attempt bus recovery\n");
/* reset controller to a known state */
z_mchp_xec_pcr_periph_reset(cfg->pcr_idx, cfg->pcr_bitpos);
regs->CFG = BIT(14) | MCHP_I2C_SMB_CFG_FEN |
(cfg->port_sel & MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
regs->CFG |= MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO |
MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN;
regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
MCHP_I2C_SMB_BB_DAT;
regs->CFG |= MCHP_I2C_SMB_CFG_ENAB;
if (!(regs->BBCTRL & MCHP_I2C_SMB_BB_CLKI_RO)) {
for (i = 0;; i++) {
if (i >= I2C_RECOVER_SCL_LOW_RETRIES) {
ret = -EBUSY;
goto recov_exit;
}
k_busy_wait(I2C_RECOVER_SCL_DELAY_US);
if (regs->BBCTRL & MCHP_I2C_SMB_BB_CLKI_RO) {
break; /* SCL went High */
}
}
}
if (regs->BBCTRL & MCHP_I2C_SMB_BB_DATI_RO) {
ret = 0;
goto recov_exit;
}
ret = -EBUSY;
/* SDA recovery */
for (i = 0; i < I2C_RECOVER_SDA_LOW_RETRIES; i++) {
/* SCL output mode and tri-stated */
regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
MCHP_I2C_SMB_BB_SCL_DIR_OUT |
MCHP_I2C_SMB_BB_CL |
MCHP_I2C_SMB_BB_DAT;
k_busy_wait(I2C_RECOVER_BB_DELAY_US);
for (j = 0; j < 9; j++) {
if (regs->BBCTRL & MCHP_I2C_SMB_BB_DATI_RO) {
break;
}
/* drive SCL low */
regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
MCHP_I2C_SMB_BB_SCL_DIR_OUT |
MCHP_I2C_SMB_BB_DAT;
k_busy_wait(I2C_RECOVER_BB_DELAY_US);
/* release SCL: pulled high by external pull-up */
regs->BBCTRL = MCHP_I2C_SMB_BB_EN |
MCHP_I2C_SMB_BB_SCL_DIR_OUT |
MCHP_I2C_SMB_BB_CL |
MCHP_I2C_SMB_BB_DAT;
k_busy_wait(I2C_RECOVER_BB_DELAY_US);
}
/* SCL is High. Produce rising edge on SCL for STOP */
regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
MCHP_I2C_SMB_BB_SDA_DIR_OUT; /* drive low */
k_busy_wait(I2C_RECOVER_BB_DELAY_US);
regs->BBCTRL = MCHP_I2C_SMB_BB_EN | MCHP_I2C_SMB_BB_CL |
MCHP_I2C_SMB_BB_DAT; /* release SCL */
k_busy_wait(I2C_RECOVER_BB_DELAY_US);
/* check if SCL and SDA are both high */
uint8_t bb = regs->BBCTRL &
(MCHP_I2C_SMB_BB_CLKI_RO | MCHP_I2C_SMB_BB_DATI_RO);
if (bb == (MCHP_I2C_SMB_BB_CLKI_RO | MCHP_I2C_SMB_BB_DATI_RO)) {
ret = 0; /* successful recovery */
goto recov_exit;
}
}
recov_exit:
/* BB mode disable reconnects SCL and SDA to I2C logic. */
regs->BBCTRL = 0;
regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN; /* clear status */
i2c_xec_reset_config(dev); /* reset controller */
return ret;
}
#ifdef CONFIG_I2C_TARGET
/*
* Restart I2C controller as target for ACK of address match.
* Setting PIN clears all status in I2C.Status register except NBB.
*/
static void restart_target(const struct device *dev)
{
i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ACK | MCHP_I2C_SMB_CTRL_ENI);
}
/*
* Configure I2C controller acting as target to NACK the next received byte.
* NOTE: Firmware must re-enable ACK generation before the start of the next
* transaction otherwise the controller will NACK its target addresses.
*/
static void target_config_for_nack(const struct device *dev)
{
i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ENI);
}
#endif
static int wait_pin(const struct device *dev, bool pin_assert, uint32_t nwait)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
for (;;) {
k_busy_wait(WAIT_INTERVAL);
data->i2c_compl = regs->COMPL;
data->i2c_status = regs->CTRLSTS;
if (data->i2c_status & MCHP_I2C_SMB_STS_BER) {
return I2C_XEC_ERR_BUS;
}
if (data->i2c_status & MCHP_I2C_SMB_STS_LAB) {
return I2C_XEC_ERR_LAB;
}
if (!(data->i2c_status & MCHP_I2C_SMB_STS_PIN)) {
if (pin_assert) {
return 0;
}
} else if (!pin_assert) {
return 0;
}
if (nwait) {
--nwait;
} else {
break;
}
}
return I2C_XEC_ERR_TMOUT;
}
static int gen_start(const struct device *dev, uint8_t addr8,
bool is_repeated)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
uint8_t ctrl = MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
MCHP_I2C_SMB_CTRL_ACK;
data->i2c_addr = addr8;
if (is_repeated) {
i2c_ctl_wr(dev, ctrl);
regs->I2CDATA = addr8;
} else {
ctrl |= MCHP_I2C_SMB_CTRL_PIN;
regs->I2CDATA = addr8;
i2c_ctl_wr(dev, ctrl);
}
return 0;
}
static int gen_stop(const struct device *dev)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
uint8_t ctrl = MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_STO | MCHP_I2C_SMB_CTRL_ACK;
data->i2c_ctrl = ctrl;
regs->CTRLSTS = ctrl;
return 0;
}
static int do_stop(const struct device *dev, uint32_t nwait)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
int ret;
data->state = I2C_XEC_STATE_STOPPED;
data->read_discard = 0;
gen_stop(dev);
ret = wait_bus_free(dev, nwait);
if (ret) {
uint32_t lines = get_lines(dev);
if (lines != I2C_LINES_BOTH_HI) {
i2c_xec_recover_bus(dev);
} else {
ret = i2c_xec_reset_config(dev);
}
}
if (ret == 0) {
/* stop success: prepare for next transaction */
regs->CTRLSTS = MCHP_I2C_SMB_CTRL_PIN | MCHP_I2C_SMB_CTRL_ESO |
MCHP_I2C_SMB_CTRL_ACK;
}
return ret;
}
static int do_start(const struct device *dev, uint8_t addr8, bool is_repeated)
{
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
int ret;
gen_start(dev, addr8, is_repeated);
ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
if (ret) {
i2c_xec_reset_config(dev);
return ret;
}
/* PIN 1->0: check for NACK */
if (data->i2c_status & MCHP_I2C_SMB_STS_LRB_AD0) {
gen_stop(dev);
ret = wait_bus_free(dev, WAIT_COUNT);
if (ret) {
i2c_xec_reset_config(dev);
}
return -EIO;
}
return 0;
}
static int i2c_xec_configure(const struct device *dev,
uint32_t dev_config_raw)
{
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
return -ENOTSUP;
}
if (dev_config_raw & I2C_ADDR_10_BITS) {
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
data->speed_id = SPEED_100KHZ_BUS;
break;
case I2C_SPEED_FAST:
data->speed_id = SPEED_400KHZ_BUS;
break;
case I2C_SPEED_FAST_PLUS:
data->speed_id = SPEED_1MHZ_BUS;
break;
default:
return -EINVAL;
}
int ret = i2c_xec_reset_config(dev);
return ret;
}
/* I2C Controller transmit: polling implementation */
static int ctrl_tx(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
int ret = 0;
uint8_t mflags = msg->flags;
uint8_t addr8 = (uint8_t)((addr & 0x7FU) << 1);
if (data->state == I2C_XEC_STATE_STOPPED) {
data->i2c_addr = addr8;
/* Is bus free and controller ready? */
ret = wait_bus_free(dev, WAIT_COUNT);
if (ret) {
ret = i2c_xec_recover_bus(dev);
if (ret) {
return ret;
}
}
ret = do_start(dev, addr8, I2C_START);
if (ret) {
return ret;
}
data->state = I2C_XEC_STATE_OPEN;
} else if (mflags & I2C_MSG_RESTART) {
data->i2c_addr = addr8;
ret = do_start(dev, addr8, I2C_RPT_START);
if (ret) {
return ret;
}
}
for (size_t n = 0; n < msg->len; n++) {
regs->I2CDATA = msg->buf[n];
ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
if (ret) {
i2c_xec_reset_config(dev);
return ret;
}
if (data->i2c_status & MCHP_I2C_SMB_STS_LRB_AD0) { /* NACK? */
do_stop(dev, STOP_WAIT_COUNT);
return -EIO;
}
}
if (mflags & I2C_MSG_STOP) {
ret = do_stop(dev, STOP_WAIT_COUNT);
}
return ret;
}
/*
* I2C Controller receive: polling implementation
* Transmitting a target address with BIT[0] == 1 causes the controller
* to enter controller-read mode where every read of I2CDATA generates
* clocks for the next byte. When we generate START or Repeated-START
* and transmit an address the address is also clocked in during
* address transmission. The address must read and discarded.
* Read of I2CDATA returns data currently in I2C read buffer, sets
* I2CSTATUS.PIN = 1, and !!generates clocks for the next
* byte!!
* For this controller to NACK the last byte we must clear the
* I2C CTRL register ACK bit BEFORE reading the next to last
* byte. Before reading the last byte we configure I2C CTRL to generate a STOP
* and then read the last byte from I2 DATA.
* When controller is in STOP mode it will not generate clocks when I2CDATA is
* read. UGLY HW DESIGN.
* We will NOT attempt to follow this HW design for Controller read except
* when all information is available: STOP message flag set AND number of
* bytes to read including dummy is >= 2. General usage can result in the
* controller not NACK'ing the last byte.
*/
static int ctrl_rx(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
{
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
int ret = 0;
size_t data_len = msg->len;
uint8_t mflags = msg->flags;
uint8_t addr8 = (uint8_t)(((addr & 0x7FU) << 1) | BIT(0));
uint8_t temp = 0;
if (data->state == I2C_XEC_STATE_STOPPED) {
data->i2c_addr = addr8;
/* Is bus free and controller ready? */
ret = wait_bus_free(dev, WAIT_COUNT);
if (ret) {
i2c_xec_reset_config(dev);
return ret;
}
ret = do_start(dev, addr8, I2C_START);
if (ret) {
return ret;
}
data->state = I2C_XEC_STATE_OPEN;
/* controller clocked address into I2CDATA */
data->read_discard = 1U;
} else if (mflags & I2C_MSG_RESTART) {
data->i2c_addr = addr8;
ret = do_start(dev, addr8, I2C_RPT_START);
if (ret) {
return ret;
}
/* controller clocked address into I2CDATA */
data->read_discard = 1U;
}
if (!data_len) { /* requested message length is 0 */
ret = 0;
if (mflags & I2C_MSG_STOP) {
data->state = I2C_XEC_STATE_STOPPED;
data->read_discard = 0;
ret = do_stop(dev, STOP_WAIT_COUNT);
}
return ret;
}
if (data->read_discard) {
data_len++;
}
uint8_t *p8 = &msg->buf[0];
while (data_len) {
if (mflags & I2C_MSG_STOP) {
if (data_len == 2) {
i2c_ctl_wr(dev, MCHP_I2C_SMB_CTRL_ESO);
} else if (data_len == 1) {
break;
}
}
temp = regs->I2CDATA; /* generates clocks */
if (data->read_discard) {
data->read_discard = 0;
} else {
*p8++ = temp;
}
ret = wait_pin(dev, I2C_WAIT_PIN_ASSERT, WAIT_COUNT);
if (ret) {
i2c_xec_reset_config(dev);
return ret;
}
data_len--;
}
if (mflags & I2C_MSG_STOP) {
data->state = I2C_XEC_STATE_STOPPED;
data->read_discard = 0;
ret = do_stop(dev, STOP_WAIT_COUNT);
if (ret == 0) {
*p8 = regs->I2CDATA;
}
}
return ret;
}
static int i2c_xec_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
struct i2c_xec_data *data = dev->data;
int ret = 0;
#ifdef CONFIG_I2C_TARGET
if (data->target_attached) {
LOG_ERR("Device is registered as target");
return -EBUSY;
}
#endif
for (uint8_t i = 0; i < num_msgs; i++) {
struct i2c_msg *m = &msgs[i];
if ((m->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
ret = ctrl_tx(dev, m, addr);
} else {
ret = ctrl_rx(dev, m, addr);
}
if (ret) {
data->state = I2C_XEC_STATE_STOPPED;
data->read_discard = 0;
LOG_ERR("i2x_xfr: flags: %x error: %d", m->flags, ret);
break;
}
}
return ret;
}
static void i2c_xec_bus_isr(const struct device *dev)
{
#ifdef CONFIG_I2C_TARGET
const struct i2c_xec_config *cfg =
(const struct i2c_xec_config *const) (dev->config);
struct i2c_xec_data *data = dev->data;
const struct i2c_target_callbacks *target_cb =
data->target_cfg->callbacks;
struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr;
int ret;
uint32_t status;
uint32_t compl_status;
uint8_t val;
uint8_t dummy = 0U;
/* Get current status */
status = regs->CTRLSTS;
compl_status = regs->COMPL & MCHP_I2C_SMB_CMPL_RW1C_MASK;
/* Idle interrupt enabled and active? */
if ((regs->CFG & MCHP_I2C_SMB_CFG_ENIDI) &&
(compl_status & MCHP_I2C_SMB_CMPL_IDLE_RWC)) {
regs->CFG &= ~MCHP_I2C_SMB_CFG_ENIDI;
if (status & MCHP_I2C_SMB_STS_NBB) {
restart_target(dev);
goto clear_iag;
}
}
if (!data->target_attached) {
goto clear_iag;
}
/* Bus Error */
if (status & MCHP_I2C_SMB_STS_BER) {
if (target_cb->stop) {
target_cb->stop(data->target_cfg);
}
restart_target(dev);
goto clear_iag;
}
/* External stop */
if (status & MCHP_I2C_SMB_STS_EXT_STOP) {
if (target_cb->stop) {
target_cb->stop(data->target_cfg);
}
restart_target(dev);
goto clear_iag;
}
/* Address byte handling */
if (status & MCHP_I2C_SMB_STS_AAS) {
if (status & MCHP_I2C_SMB_STS_PIN) {
goto clear_iag;
}
uint8_t rx_data = regs->I2CDATA;
if (rx_data & BIT(I2C_READ_WRITE_POS)) {
/* target transmitter mode */
data->target_read = true;
val = dummy;
if (target_cb->read_requested) {
target_cb->read_requested(
data->target_cfg, &val);
/* Application target transmit handler
* does not have data to send. In
* target transmit mode the external
* Controller is ACK's data we send.
* All we can do is keep sending dummy
* data. We assume read_requested does
* not modify the value pointed to by val
* if it has not data(returns error).
*/
}
/*
* Writing I2CData causes this HW to release SCL
* ending clock stretching. The external Controller
* senses SCL released and begins generating clocks
* and capturing data driven by this controller
* on SDA. External Controller ACK's data until it
* wants no more then it will NACK.
*/
regs->I2CDATA = val;
goto clear_iag; /* Exit ISR */
} else {
/* target receiver mode */
data->target_read = false;
if (target_cb->write_requested) {
ret = target_cb->write_requested(
data->target_cfg);
if (ret) {
/*
* Application handler can't accept
* data. Configure HW to NACK next
* data transmitted by external
* Controller.
* !!! TODO We must re-program our HW
* for address ACK before next
* transaction is begun !!!
*/
target_config_for_nack(dev);
}
}
goto clear_iag; /* Exit ISR */
}
}
if (data->target_read) { /* Target transmitter mode */
/* Master has Nacked, then just write a dummy byte */
status = regs->CTRLSTS;
if (status & MCHP_I2C_SMB_STS_LRB_AD0) {
/*
* ISSUE: HW will not detect external STOP in
* target transmit mode. Enable IDLE interrupt
* to catch PIN 0 -> 1 and NBB 0 -> 1.
*/
regs->CFG |= MCHP_I2C_SMB_CFG_ENIDI;
/*
* dummy write causes this controller's PIN status
* to de-assert 0 -> 1. Data is not transmitted.
* SCL is not driven low by this controller.
*/
regs->I2CDATA = dummy;
status = regs->CTRLSTS;
} else {
val = dummy;
if (target_cb->read_processed) {
target_cb->read_processed(
data->target_cfg, &val);
}
regs->I2CDATA = val;
}
} else { /* target receiver mode */
/*
* Reading the I2CData register causes this target to release
* SCL. The external Controller senses SCL released generates
* clocks for transmitting the next data byte.
* Reading I2C Data register causes PIN status 0 -> 1.
*/
val = regs->I2CDATA;
if (target_cb->write_received) {
/*
* Call back returns error if we should NACK
* next byte.
*/
ret = target_cb->write_received(data->target_cfg, val);
if (ret) {
/*
* Configure HW to NACK next byte. It will not
* generate clocks for another byte of data
*/
target_config_for_nack(dev);
}
}
}
clear_iag:
regs->COMPL = compl_status;
mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
#endif
}
#ifdef CONFIG_I2C_TARGET
static int i2c_xec_target_register(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data = dev->data;
int ret;
if (!config) {
return -EINVAL;
}
if (data->target_attached) {
return -EBUSY;
}
/* Wait for any outstanding transactions to complete so that
* the bus is free
*/
ret = wait_bus_free(dev, WAIT_COUNT);
if (ret) {
return ret;
}
data->target_cfg = config;
ret = i2c_xec_reset_config(dev);
if (ret) {
return ret;
}
restart_target(dev);
data->target_attached = true;
/* Clear before enabling girq bit */
mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
mchp_xec_ecia_girq_src_en(cfg->girq, cfg->girq_pos);
return 0;
}
static int i2c_xec_target_unregister(const struct device *dev,
struct i2c_target_config *config)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data = dev->data;
if (!data->target_attached) {
return -EINVAL;
}
data->target_cfg = NULL;
data->target_attached = false;
mchp_xec_ecia_girq_src_dis(cfg->girq, cfg->girq_pos);
return 0;
}
#endif
static const struct i2c_driver_api i2c_xec_driver_api = {
.configure = i2c_xec_configure,
.transfer = i2c_xec_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_xec_target_register,
.target_unregister = i2c_xec_target_unregister,
#endif
};
static int i2c_xec_init(const struct device *dev)
{
const struct i2c_xec_config *cfg = dev->config;
struct i2c_xec_data *data =
(struct i2c_xec_data *const) (dev->data);
int ret;
uint32_t bitrate_cfg;
data->state = I2C_XEC_STATE_STOPPED;
data->target_cfg = NULL;
data->target_attached = false;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC I2C pinctrl setup failed (%d)", ret);
return ret;
}
bitrate_cfg = i2c_map_dt_bitrate(cfg->clock_freq);
if (!bitrate_cfg) {
return -EINVAL;
}
/* Default configuration */
ret = i2c_xec_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret) {
return ret;
}
#ifdef CONFIG_I2C_TARGET
const struct i2c_xec_config *config =
(const struct i2c_xec_config *const) (dev->config);
config->irq_config_func();
#endif
return 0;
}
#define I2C_XEC_DEVICE(n) \
\
PINCTRL_DT_INST_DEFINE(n); \
\
static void i2c_xec_irq_config_func_##n(void); \
\
static struct i2c_xec_data i2c_xec_data_##n; \
static const struct i2c_xec_config i2c_xec_config_##n = { \
.base_addr = \
DT_INST_REG_ADDR(n), \
.port_sel = DT_INST_PROP(n, port_sel), \
.clock_freq = DT_INST_PROP(n, clock_frequency), \
.girq = DT_INST_PROP_BY_IDX(n, girqs, 0), \
.girq_pos = DT_INST_PROP_BY_IDX(n, girqs, 1), \
.pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
.pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
.irq_config_func = i2c_xec_irq_config_func_##n, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_xec_init, NULL, \
&i2c_xec_data_##n, &i2c_xec_config_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_xec_driver_api); \
\
static void i2c_xec_irq_config_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
i2c_xec_bus_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_XEC_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_mchp_xec_v2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,756 |
```c
/*
*
*/
#define DT_DRV_COMPAT fsl_imx21_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <soc.h>
#include <i2c_imx.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_imx);
#include "i2c-priv.h"
#define DEV_BASE(dev) \
((I2C_Type *)((const struct i2c_imx_config * const)(dev)->config)->base)
struct i2c_imx_config {
I2C_Type *base;
void (*irq_config_func)(const struct device *dev);
uint32_t bitrate;
const struct pinctrl_dev_config *pincfg;
};
struct i2c_master_transfer {
const uint8_t *txBuff;
volatile uint8_t *rxBuff;
volatile uint32_t cmdSize;
volatile uint32_t txSize;
volatile uint32_t rxSize;
volatile bool isBusy;
volatile uint32_t currentDir;
volatile uint32_t currentMode;
volatile bool ack;
};
struct i2c_imx_data {
struct i2c_master_transfer transfer;
struct k_sem device_sync_sem;
};
static bool i2c_imx_write(const struct device *dev, uint8_t *txBuffer,
uint32_t txSize)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
transfer->isBusy = true;
/* Clear I2C interrupt flag to avoid spurious interrupt */
I2C_ClearStatusFlag(base, i2cStatusInterrupt);
/* Set I2C work under Tx mode */
I2C_SetDirMode(base, i2cDirectionTransmit);
transfer->currentDir = i2cDirectionTransmit;
transfer->txBuff = txBuffer;
transfer->txSize = txSize;
I2C_WriteByte(base, *transfer->txBuff);
transfer->txBuff++;
transfer->txSize--;
/* Enable I2C interrupt, subsequent data transfer will be handled
* in ISR.
*/
I2C_SetIntCmd(base, true);
/* Wait for the transfer to complete */
k_sem_take(&data->device_sync_sem, K_FOREVER);
return transfer->ack;
}
static void i2c_imx_read(const struct device *dev, uint8_t *rxBuffer,
uint32_t rxSize)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
transfer->isBusy = true;
/* Clear I2C interrupt flag to avoid spurious interrupt */
I2C_ClearStatusFlag(base, i2cStatusInterrupt);
/* Change to receive state. */
I2C_SetDirMode(base, i2cDirectionReceive);
transfer->currentDir = i2cDirectionReceive;
transfer->rxBuff = rxBuffer;
transfer->rxSize = rxSize;
if (transfer->rxSize == 1U) {
/* Send Nack */
I2C_SetAckBit(base, false);
} else {
/* Send Ack */
I2C_SetAckBit(base, true);
}
/* dummy read to clock in 1st byte */
I2C_ReadByte(base);
/* Enable I2C interrupt, subsequent data transfer will be handled
* in ISR.
*/
I2C_SetIntCmd(base, true);
/* Wait for the transfer to complete */
k_sem_take(&data->device_sync_sem, K_FOREVER);
}
static int i2c_imx_configure(const struct device *dev,
uint32_t dev_config_raw)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
uint32_t baudrate;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
if (I2C_ADDR_10_BITS & dev_config_raw) {
return -EINVAL;
}
/* Initialize I2C state structure content. */
transfer->txBuff = 0;
transfer->rxBuff = 0;
transfer->cmdSize = 0U;
transfer->txSize = 0U;
transfer->rxSize = 0U;
transfer->isBusy = false;
transfer->currentDir = i2cDirectionReceive;
transfer->currentMode = i2cModeSlave;
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
/* Setup I2C init structure. */
i2c_init_config_t i2cInitConfig = {
.baudRate = baudrate,
.slaveAddress = 0x00
};
i2cInitConfig.clockRate = get_i2c_clock_freq(base);
I2C_Init(base, &i2cInitConfig);
I2C_Enable(base);
return 0;
}
static int i2c_imx_send_addr(const struct device *dev, uint16_t addr,
uint8_t flags)
{
uint8_t byte0 = addr << 1;
byte0 |= (flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
return i2c_imx_write(dev, &byte0, 1);
}
static int i2c_imx_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
uint16_t timeout = UINT16_MAX;
int result = -EIO;
if (!num_msgs) {
return 0;
}
/* Wait until bus not busy */
while ((I2C_I2SR_REG(base) & i2cStatusBusBusy) && (--timeout)) {
}
if (timeout == 0U) {
return result;
}
/* Make sure we're in a good state so slave recognises the Start */
I2C_SetWorkMode(base, i2cModeSlave);
transfer->currentMode = i2cModeSlave;
/* Switch back to Rx direction. */
I2C_SetDirMode(base, i2cDirectionReceive);
transfer->currentDir = i2cDirectionReceive;
/* Start condition */
I2C_SetDirMode(base, i2cDirectionTransmit);
transfer->currentDir = i2cDirectionTransmit;
I2C_SetWorkMode(base, i2cModeMaster);
transfer->currentMode = i2cModeMaster;
/* Send address after any Start condition */
if (!i2c_imx_send_addr(dev, addr, msgs->flags)) {
goto finish; /* No ACK received */
}
do {
if (msgs->flags & I2C_MSG_RESTART) {
I2C_SendRepeatStart(base);
if (!i2c_imx_send_addr(dev, addr, msgs->flags)) {
goto finish; /* No ACK received */
}
}
/* Transfer data */
if (msgs->len) {
if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
i2c_imx_read(dev, msgs->buf, msgs->len);
} else {
if (!i2c_imx_write(dev, msgs->buf, msgs->len)) {
goto finish; /* No ACK received */
}
}
}
if (msgs->flags & I2C_MSG_STOP) {
I2C_SetWorkMode(base, i2cModeSlave);
transfer->currentMode = i2cModeSlave;
I2C_SetDirMode(base, i2cDirectionReceive);
transfer->currentDir = i2cDirectionReceive;
}
/* Next message */
msgs++;
num_msgs--;
} while (num_msgs);
/* Complete without error */
result = 0;
return result;
finish:
I2C_SetWorkMode(base, i2cModeSlave);
transfer->currentMode = i2cModeSlave;
I2C_SetDirMode(base, i2cDirectionReceive);
transfer->currentDir = i2cDirectionReceive;
return result;
}
static void i2c_imx_isr(const struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
/* Clear interrupt flag. */
I2C_ClearStatusFlag(base, i2cStatusInterrupt);
/* Exit the ISR if no transfer is happening for this instance. */
if (!transfer->isBusy) {
return;
}
if (i2cModeMaster == transfer->currentMode) {
if (i2cDirectionTransmit == transfer->currentDir) {
/* Normal write operation. */
transfer->ack =
!(I2C_GetStatusFlag(base, i2cStatusReceivedAck));
if (transfer->txSize == 0U) {
/* Close I2C interrupt. */
I2C_SetIntCmd(base, false);
/* Release I2C Bus. */
transfer->isBusy = false;
k_sem_give(&data->device_sync_sem);
} else {
I2C_WriteByte(base, *transfer->txBuff);
transfer->txBuff++;
transfer->txSize--;
}
} else {
/* Normal read operation. */
if (transfer->rxSize == 2U) {
/* Send Nack */
I2C_SetAckBit(base, false);
} else {
/* Send Ack */
I2C_SetAckBit(base, true);
}
if (transfer->rxSize == 1U) {
/* Switch back to Tx direction to avoid
* additional I2C bus read.
*/
I2C_SetDirMode(base, i2cDirectionTransmit);
transfer->currentDir = i2cDirectionTransmit;
}
*transfer->rxBuff = I2C_ReadByte(base);
transfer->rxBuff++;
transfer->rxSize--;
/* receive finished. */
if (transfer->rxSize == 0U) {
/* Close I2C interrupt. */
I2C_SetIntCmd(base, false);
/* Release I2C Bus. */
transfer->isBusy = false;
k_sem_give(&data->device_sync_sem);
}
}
}
}
static int i2c_imx_init(const struct device *dev)
{
const struct i2c_imx_config *config = dev->config;
struct i2c_imx_data *data = dev->data;
uint32_t bitrate_cfg;
int error;
k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (error) {
return error;
}
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_imx_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
config->irq_config_func(dev);
return 0;
}
static const struct i2c_driver_api i2c_imx_driver_api = {
.configure = i2c_imx_configure,
.transfer = i2c_imx_transfer,
};
#define I2C_IMX_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void i2c_imx_config_func_##n(const struct device *dev); \
\
static const struct i2c_imx_config i2c_imx_config_##n = { \
.base = (I2C_Type *)DT_INST_REG_ADDR(n), \
.irq_config_func = i2c_imx_config_func_##n, \
.bitrate = DT_INST_PROP(n, clock_frequency), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct i2c_imx_data i2c_imx_data_##n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, \
i2c_imx_init, \
NULL, \
&i2c_imx_data_##n, &i2c_imx_config_##n, \
POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, \
&i2c_imx_driver_api); \
\
static void i2c_imx_config_func_##n(const struct device *dev) \
{ \
ARG_UNUSED(dev); \
\
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
i2c_imx_isr, DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(I2C_IMX_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_imx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,978 |
```c
/*
* This driver creates fake I2C buses which can contain emulated devices,
* implemented by a separate emulation driver. The API between this driver and
* its emulators is defined by struct i2c_emul_driver_api.
*
*
*/
#define DT_DRV_COMPAT zephyr_i2c_emul_controller
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_emul_ctlr);
#include <zephyr/device.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c_emul.h>
#include "i2c-priv.h"
/** Working data for the device */
struct i2c_emul_data {
/* List of struct i2c_emul associated with the device */
sys_slist_t emuls;
/* I2C host configuration */
uint32_t config;
uint32_t bitrate;
#ifdef CONFIG_I2C_TARGET
struct i2c_target_config *target_cfg;
#endif
};
struct i2c_emul_config {
struct emul_list_for_bus emul_list;
bool target_buffered_mode;
const struct i2c_dt_spec *forward_list;
uint16_t forward_list_size;
};
/**
* Find an emulator by its I2C address
*
* @param dev I2C emulation controller device
* @param addr I2C address of that device
* @return emulator ro use
* @return NULL if not found
*/
static struct i2c_emul *i2c_emul_find(const struct device *dev, int addr)
{
struct i2c_emul_data *data = dev->data;
sys_snode_t *node;
SYS_SLIST_FOR_EACH_NODE(&data->emuls, node) {
struct i2c_emul *emul = NULL;
emul = CONTAINER_OF(node, struct i2c_emul, node);
if (emul->addr == addr) {
return emul;
}
}
return NULL;
}
static int i2c_emul_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_emul_data *data = dev->data;
data->config = dev_config;
return 0;
}
static int i2c_emul_get_config(const struct device *dev, uint32_t *dev_config)
{
struct i2c_emul_data *data = dev->data;
*dev_config = data->config;
return 0;
}
#ifdef CONFIG_I2C_TARGET
static int i2c_emul_send_to_target(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs)
{
struct i2c_emul_data *data = dev->data;
const struct i2c_target_callbacks *callbacks = data->target_cfg->callbacks;
#ifdef CONFIG_I2C_TARGET_BUFFER_MODE
const struct i2c_emul_config *config = dev->config;
if (config->target_buffered_mode) {
for (uint8_t i = 0; i < num_msgs; ++i) {
if (i2c_is_read_op(&msgs[i])) {
uint8_t *ptr = NULL;
uint32_t len;
int rc =
callbacks->buf_read_requested(data->target_cfg, &ptr, &len);
if (rc != 0) {
return rc;
}
if (len > msgs[i].len) {
LOG_ERR("buf_read_requested returned too many bytes");
return -ENOMEM;
}
memcpy(msgs[i].buf, ptr, len);
} else {
callbacks->buf_write_received(data->target_cfg, msgs[i].buf,
msgs[i].len);
}
if (i2c_is_stop_op(&msgs[i])) {
int rc = callbacks->stop(data->target_cfg);
if (rc != 0) {
return rc;
}
}
}
return 0;
}
#endif /* CONFIG_I2C_TARGET_BUFFER_MODE */
for (uint8_t i = 0; i < num_msgs; ++i) {
LOG_DBG(" msgs[%u].flags? 0x%02x", i, msgs[i].flags);
if (i2c_is_read_op(&msgs[i])) {
for (uint32_t j = 0; j < msgs[i].len; ++j) {
int rc = 0;
if (j == 0) {
LOG_DBG(" Calling read_requested with data %p",
(void *)&msgs[i].buf[j]);
rc = callbacks->read_requested(data->target_cfg,
&msgs[i].buf[j]);
} else {
LOG_DBG(" Calling read_processed with data %p",
(void *)&msgs[i].buf[j]);
rc = callbacks->read_processed(data->target_cfg,
&msgs[i].buf[j]);
}
if (rc != 0) {
return rc;
}
}
} else {
for (uint32_t j = 0; j < msgs[i].len; ++j) {
int rc = 0;
if (j == 0) {
LOG_DBG(" Calling write_requested");
rc = callbacks->write_requested(data->target_cfg);
}
if (rc != 0) {
return rc;
}
LOG_DBG(" Calling write_received with data 0x%02x",
msgs[i].buf[j]);
rc = callbacks->write_received(data->target_cfg, msgs[i].buf[j]);
if (rc != 0) {
return rc;
}
}
}
if (i2c_is_stop_op(&msgs[i])) {
int rc = callbacks->stop(data->target_cfg);
if (rc != 0) {
return rc;
}
}
}
return 0;
}
#endif /* CONFIG_I2C_TARGET*/
static int i2c_emul_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
const struct i2c_emul_config *conf = dev->config;
struct i2c_emul *emul;
const struct i2c_emul_api *api;
int ret;
LOG_DBG("%s(dev=%p, addr=0x%02x)", __func__, (void *)dev, addr);
#ifdef CONFIG_I2C_TARGET
struct i2c_emul_data *data = dev->data;
/*
* First check if the bus is configured as a target, targets either listen to the address or
* ignore the messages. So if the address doesn't match, we're just going to bail.
*/
LOG_DBG(" has_target_cfg? %d", data->target_cfg != NULL);
if (data->target_cfg != NULL) {
LOG_DBG(" target_cfg->address? 0x%02x", data->target_cfg->address);
if (data->target_cfg->address != addr) {
return -EINVAL;
}
LOG_DBG(" forwarding to target");
return i2c_emul_send_to_target(dev, msgs, num_msgs);
}
#endif /* CONFIG_I2C_TARGET */
/*
* We're not a target, but lets check if we need to forward this request before we start
* looking for a peripheral.
*/
for (uint16_t i = 0; i < conf->forward_list_size; ++i) {
LOG_DBG(" Checking forward list [%u].addr? 0x%02x", i,
conf->forward_list[i].addr);
if (conf->forward_list[i].addr == addr) {
/* We need to forward this request */
return i2c_transfer(conf->forward_list[i].bus, msgs, num_msgs, addr);
}
}
emul = i2c_emul_find(dev, addr);
if (!emul) {
return -EIO;
}
api = emul->api;
__ASSERT_NO_MSG(emul->api);
__ASSERT_NO_MSG(emul->api->transfer);
if (emul->mock_api != NULL && emul->mock_api->transfer != NULL) {
ret = emul->mock_api->transfer(emul->target, msgs, num_msgs, addr);
if (ret != -ENOSYS) {
return ret;
}
}
return api->transfer(emul->target, msgs, num_msgs, addr);
}
/**
* Set up a new emulator and add it to the list
*
* @param dev I2C emulation controller device
*/
static int i2c_emul_init(const struct device *dev)
{
struct i2c_emul_data *data = dev->data;
int rc;
sys_slist_init(&data->emuls);
rc = emul_init_for_bus(dev);
/* Set config to an uninitialized state */
data->config = (I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(data->bitrate));
return rc;
}
int i2c_emul_register(const struct device *dev, struct i2c_emul *emul)
{
struct i2c_emul_data *data = dev->data;
const char *name = emul->target->dev->name;
sys_slist_append(&data->emuls, &emul->node);
LOG_INF("Register emulator '%s' at I2C addr %02x", name, emul->addr);
return 0;
}
#ifdef CONFIG_I2C_TARGET
static int i2c_emul_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
struct i2c_emul_data *data = dev->data;
data->target_cfg = cfg;
return 0;
}
static int i2c_emul_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
struct i2c_emul_data *data = dev->data;
if (data->target_cfg != cfg) {
return -EINVAL;
}
data->target_cfg = NULL;
return 0;
}
#endif /* CONFIG_I2C_TARGET */
/* Device instantiation */
static const struct i2c_driver_api i2c_emul_api = {
.configure = i2c_emul_configure,
.get_config = i2c_emul_get_config,
.transfer = i2c_emul_transfer,
#ifdef CONFIG_I2C_TARGET
.target_register = i2c_emul_target_register,
.target_unregister = i2c_emul_target_unregister,
#endif
};
#define EMUL_LINK_AND_COMMA(node_id) \
{ \
.dev = DEVICE_DT_GET(node_id), \
},
#define EMUL_FORWARD_ITEM(node_id, prop, idx) \
{ \
.bus = DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)), \
.addr = DT_PHA_BY_IDX(node_id, prop, idx, addr), \
},
#define I2C_EMUL_INIT(n) \
static const struct emul_link_for_bus emuls_##n[] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(n), EMUL_LINK_AND_COMMA)}; \
static const struct i2c_dt_spec emul_forward_list_##n[] = { \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, forwards), \
(DT_INST_FOREACH_PROP_ELEM(n, forwards, EMUL_FORWARD_ITEM)), ())}; \
static struct i2c_emul_config i2c_emul_cfg_##n = { \
.emul_list = \
{ \
.children = emuls_##n, \
.num_children = ARRAY_SIZE(emuls_##n), \
}, \
.target_buffered_mode = DT_INST_PROP(n, target_buffered_mode), \
.forward_list = emul_forward_list_##n, \
.forward_list_size = ARRAY_SIZE(emul_forward_list_##n), \
}; \
static struct i2c_emul_data i2c_emul_data_##n = { \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
I2C_DEVICE_DT_INST_DEFINE(n, i2c_emul_init, NULL, &i2c_emul_data_##n, &i2c_emul_cfg_##n, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &i2c_emul_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_EMUL_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_emul.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,694 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief I2C driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_cat1_i2c
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <cyhal_i2c.h>
#include <cyhal_utils_impl.h>
#include <cyhal_utils_impl.h>
#include <cyhal_scb_common.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_infineon_cat1, CONFIG_I2C_LOG_LEVEL);
#define I2C_CAT1_EVENTS_MASK (CYHAL_I2C_MASTER_WR_CMPLT_EVENT | CYHAL_I2C_MASTER_RD_CMPLT_EVENT | \
CYHAL_I2C_MASTER_ERR_EVENT)
#define I2C_CAT1_SLAVE_EVENTS_MASK \
(CYHAL_I2C_SLAVE_READ_EVENT | CYHAL_I2C_SLAVE_WRITE_EVENT | \
CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT | CYHAL_I2C_SLAVE_RD_CMPLT_EVENT | \
CYHAL_I2C_SLAVE_WR_CMPLT_EVENT | CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT | \
CYHAL_I2C_SLAVE_ERR_EVENT)
/* States for ASYNC operations */
#define CAT1_I2C_PENDING_NONE (0U)
#define CAT1_I2C_PENDING_RX (1U)
#define CAT1_I2C_PENDING_TX (2U)
#define CAT1_I2C_PENDING_TX_RX (3U)
/* I2C speed */
#define CAT1_I2C_SPEED_STANDARD_HZ (100000UL)
#define CAT1_I2C_SPEED_FAST_HZ (400000UL)
#define CAT1_I2C_SPEED_FAST_PLUS_HZ (1000000UL)
/* Data structure */
struct ifx_cat1_i2c_data {
cyhal_i2c_t obj;
cyhal_i2c_cfg_t cfg;
struct k_sem operation_sem;
struct k_sem transfer_sem;
uint32_t error_status;
uint32_t async_pending;
cyhal_resource_inst_t hw_resource;
cyhal_clock_t clock;
struct i2c_target_config *p_target_config;
uint8_t i2c_target_wr_byte;
uint8_t target_wr_buffer[CONFIG_I2C_INFINEON_CAT1_TARGET_BUF];
};
/* Device config structure */
struct ifx_cat1_i2c_config {
uint32_t master_frequency;
CySCB_Type *reg_addr;
const struct pinctrl_dev_config *pcfg;
uint8_t irq_priority;
};
/* Default SCB/I2C configuration structure */
static const cy_stc_scb_i2c_config_t _cyhal_i2c_default_config = {
.i2cMode = CY_SCB_I2C_MASTER,
.useRxFifo = false,
.useTxFifo = true,
.slaveAddress = 0U,
.slaveAddressMask = 0U,
.acceptAddrInFifo = false,
.ackGeneralAddr = false,
.enableWakeFromSleep = false,
.enableDigitalFilter = false,
.lowPhaseDutyCycle = 8U,
.highPhaseDutyCycle = 8U,
};
static int32_t _get_hw_block_num(CySCB_Type *reg_addr)
{
uint32_t i;
for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
return i;
}
}
return -ENOMEM;
}
#ifdef CONFIG_I2C_INFINEON_CAT1_ASYNC
static void ifx_master_event_handler(void *callback_arg, cyhal_i2c_event_t event)
{
const struct device *dev = (const struct device *) callback_arg;
struct ifx_cat1_i2c_data *data = dev->data;
if (((CYHAL_I2C_MASTER_ERR_EVENT | CYHAL_I2C_SLAVE_ERR_EVENT) & event) != 0U) {
/* In case of error abort transfer */
(void)cyhal_i2c_abort_async(&data->obj);
data->error_status = 1;
}
/* Release semaphore if operation complete
* When we have pending TX, RX operations, the semaphore will be released
* after TX, RX complete.
*/
if (((data->async_pending == CAT1_I2C_PENDING_TX_RX) &&
((CYHAL_I2C_MASTER_RD_CMPLT_EVENT & event) != 0U)) ||
(data->async_pending != CAT1_I2C_PENDING_TX_RX)) {
/* Release semaphore (After I2C async transfer is complete) */
k_sem_give(&data->transfer_sem);
}
if (0 != (CYHAL_I2C_SLAVE_READ_EVENT & event)) {
if (data->p_target_config->callbacks->read_requested) {
data->p_target_config->callbacks->read_requested(data->p_target_config,
&data->i2c_target_wr_byte);
data->obj.context.slaveTxBufferIdx = 0;
data->obj.context.slaveTxBufferCnt = 0;
data->obj.context.slaveTxBufferSize = 1;
data->obj.context.slaveTxBuffer = &data->i2c_target_wr_byte;
}
}
if (0 != (CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT & event)) {
if (data->p_target_config->callbacks->read_processed) {
data->p_target_config->callbacks->read_processed(data->p_target_config,
&data->i2c_target_wr_byte);
data->obj.context.slaveTxBufferIdx = 0;
data->obj.context.slaveTxBufferCnt = 0;
data->obj.context.slaveTxBufferSize = 1;
data->obj.context.slaveTxBuffer = &data->i2c_target_wr_byte;
}
}
if (0 != (CYHAL_I2C_SLAVE_WRITE_EVENT & event)) {
cyhal_i2c_slave_config_write_buffer(&data->obj, data->target_wr_buffer,
CONFIG_I2C_INFINEON_CAT1_TARGET_BUF);
if (data->p_target_config->callbacks->write_requested) {
data->p_target_config->callbacks->write_requested(data->p_target_config);
}
}
if (0 != (CYHAL_I2C_SLAVE_WR_CMPLT_EVENT & event)) {
if (data->p_target_config->callbacks->write_received) {
for (int i = 0; i < data->obj.context.slaveRxBufferIdx; i++) {
data->p_target_config->callbacks->write_received(
data->p_target_config, data->target_wr_buffer[i]);
}
}
if (data->p_target_config->callbacks->stop) {
data->p_target_config->callbacks->stop(data->p_target_config);
}
}
if (0 != (CYHAL_I2C_SLAVE_RD_CMPLT_EVENT & event)) {
if (data->p_target_config->callbacks->stop) {
data->p_target_config->callbacks->stop(data->p_target_config);
}
}
}
#endif
static int ifx_cat1_i2c_configure(const struct device *dev, uint32_t dev_config)
{
struct ifx_cat1_i2c_data *data = dev->data;
cy_rslt_t rslt;
int ret;
if (dev_config != 0) {
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
data->cfg.frequencyhal_hz = CAT1_I2C_SPEED_STANDARD_HZ;
break;
case I2C_SPEED_FAST:
data->cfg.frequencyhal_hz = CAT1_I2C_SPEED_FAST_HZ;
break;
case I2C_SPEED_FAST_PLUS:
data->cfg.frequencyhal_hz = CAT1_I2C_SPEED_FAST_PLUS_HZ;
break;
default:
LOG_ERR("Unsupported speed");
return -ERANGE;
}
/* This is deprecated and could be ignored in the future */
if (dev_config & I2C_ADDR_10_BITS) {
LOG_ERR("10-bit addressing mode is not supported");
return -EIO;
}
}
/* Acquire semaphore (block I2C operation for another thread) */
ret = k_sem_take(&data->operation_sem, K_FOREVER);
if (ret) {
return -EIO;
}
/* Configure the I2C resource to be master */
rslt = cyhal_i2c_configure(&data->obj, &data->cfg);
if (rslt != CY_RSLT_SUCCESS) {
LOG_ERR("cyhal_i2c_configure failed with err 0x%x", rslt);
k_sem_give(&data->operation_sem);
return -EIO;
}
#ifdef CONFIG_I2C_INFINEON_CAT1_ASYNC
/* Register an I2C event callback handler */
cyhal_i2c_register_callback(&data->obj, ifx_master_event_handler, (void *)dev);
#endif
/* Release semaphore */
k_sem_give(&data->operation_sem);
return 0;
}
static int ifx_cat1_i2c_get_config(const struct device *dev, uint32_t *dev_config)
{
struct ifx_cat1_i2c_data *data = dev->data;
uint32_t config;
switch (data->cfg.frequencyhal_hz) {
case CAT1_I2C_SPEED_STANDARD_HZ:
config = I2C_SPEED_SET(I2C_SPEED_STANDARD);
break;
case CAT1_I2C_SPEED_FAST_HZ:
config = I2C_SPEED_SET(I2C_SPEED_FAST);
break;
case CAT1_I2C_SPEED_FAST_PLUS_HZ:
config = I2C_SPEED_SET(I2C_SPEED_FAST_PLUS);
break;
default:
LOG_ERR("Unsupported speed");
return -ERANGE;
}
/* Return current configuration */
*dev_config = config | I2C_MODE_CONTROLLER;
return 0;
}
static int ifx_cat1_i2c_msg_validate(struct i2c_msg *msg, uint8_t num_msgs)
{
for (uint32_t i = 0u; i < num_msgs; i++) {
if ((I2C_MSG_ADDR_10_BITS & msg[i].flags) || (msg[i].buf == NULL)) {
return -EINVAL;
}
}
return 0;
}
static int ifx_cat1_i2c_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs,
uint16_t addr)
{
struct ifx_cat1_i2c_data *data = dev->data;
cy_rslt_t rslt = CY_RSLT_SUCCESS;
int ret;
if (!num_msgs) {
return 0;
}
/* Acquire semaphore (block I2C transfer for another thread) */
ret = k_sem_take(&data->operation_sem, K_FOREVER);
if (ret) {
return -EIO;
}
/* This function checks if msg.buf is not NULL and if
* target address is not 10 bit.
*/
if (ifx_cat1_i2c_msg_validate(msg, num_msgs) != 0) {
k_sem_give(&data->operation_sem);
return -EINVAL;
}
#ifdef CONFIG_I2C_INFINEON_CAT1_ASYNC
const struct ifx_cat1_i2c_config *const config = dev->config;
struct i2c_msg *tx_msg;
struct i2c_msg *rx_msg;
data->error_status = 0;
data->async_pending = CAT1_I2C_PENDING_NONE;
/* Enable I2C Interrupt */
cyhal_i2c_enable_event(&data->obj, (cyhal_i2c_event_t)I2C_CAT1_EVENTS_MASK,
config->irq_priority, true);
for (uint32_t i = 0u; i < num_msgs; i++) {
tx_msg = NULL;
rx_msg = NULL;
if ((msg[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
tx_msg = &msg[i];
data->async_pending = CAT1_I2C_PENDING_TX;
}
if ((msg[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
rx_msg = &msg[i];
data->async_pending = CAT1_I2C_PENDING_TX;
}
if ((tx_msg != NULL) && ((i + 1U) < num_msgs) &&
((msg[i + 1U].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)) {
rx_msg = &msg[i + 1U];
i++;
data->async_pending = CAT1_I2C_PENDING_TX_RX;
}
/* Initiate master write and read transfer
* using tx_buff and rx_buff respectively
*/
rslt = cyhal_i2c_master_transfer_async(&data->obj, addr,
(tx_msg == NULL) ? NULL : tx_msg->buf,
(tx_msg == NULL) ? 0u : tx_msg->len,
(rx_msg == NULL) ? NULL : rx_msg->buf,
(rx_msg == NULL) ? 0u : rx_msg->len);
if (rslt != CY_RSLT_SUCCESS) {
k_sem_give(&data->operation_sem);
return -EIO;
}
/* Acquire semaphore (block I2C async transfer for another thread) */
ret = k_sem_take(&data->transfer_sem, K_FOREVER);
if (ret) {
k_sem_give(&data->operation_sem);
return -EIO;
}
/* If error_status != 1 we have error during transfer async.
* error_status is handling in master_event_handler function.
*/
if (data->error_status != 0) {
/* Release semaphore */
k_sem_give(&data->operation_sem);
return -EIO;
}
}
/* Disable I2C Interrupt */
cyhal_i2c_enable_event(&data->obj, (cyhal_i2c_event_t)
I2C_CAT1_EVENTS_MASK, config->irq_priority, false);
#else
for (uint32_t i = 0u; i < num_msgs; i++) {
bool stop_flag = ((msg[i].flags & I2C_MSG_STOP) != 0u) ? true : false;
if ((msg[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
rslt = cyhal_i2c_master_write(&data->obj,
addr, msg[i].buf, msg[i].len, 0, stop_flag);
}
if ((msg[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
rslt = cyhal_i2c_master_read(&data->obj,
addr, msg[i].buf, msg[i].len, 0, stop_flag);
}
if (rslt != CY_RSLT_SUCCESS) {
/* Release semaphore */
k_sem_give(&data->operation_sem);
return -EIO;
}
}
#endif
/* Release semaphore (After I2C transfer is complete) */
k_sem_give(&data->operation_sem);
return 0;
}
static int ifx_cat1_i2c_init(const struct device *dev)
{
struct ifx_cat1_i2c_data *data = dev->data;
const struct ifx_cat1_i2c_config *config = dev->config;
cy_rslt_t result;
int ret;
/* Configuration structure to initialisation I2C */
cyhal_i2c_configurator_t i2c_init_cfg = {
.resource = &data->hw_resource,
.config = &_cyhal_i2c_default_config,
.clock = &data->clock,
};
/* Dedicate SCB HW resource */
data->hw_resource.type = CYHAL_RSC_SCB;
data->hw_resource.block_num = _get_hw_block_num(config->reg_addr);
/* Configure semaphores */
ret = k_sem_init(&data->transfer_sem, 0, 1);
if (ret) {
return ret;
}
ret = k_sem_init(&data->operation_sem, 1, 1);
if (ret) {
return ret;
}
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Allocating clock for I2C driver */
result = _cyhal_utils_allocate_clock(&data->clock, &data->hw_resource,
CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT, true);
if (result != CY_RSLT_SUCCESS) {
return -ENOTSUP;
}
/* Assigns a programmable divider to a selected IP block */
en_clk_dst_t clk_idx = _cyhal_scb_get_clock_index(i2c_init_cfg.resource->block_num);
result = _cyhal_utils_peri_pclk_assign_divider(clk_idx, i2c_init_cfg.clock);
if (result != CY_RSLT_SUCCESS) {
return -ENOTSUP;
}
/* Initialize the I2C peripheral */
result = cyhal_i2c_init_cfg(&data->obj, &i2c_init_cfg);
if (result != CY_RSLT_SUCCESS) {
return -ENOTSUP;
}
data->obj.is_clock_owned = true;
/* Store Master initial configuration */
data->cfg.is_slave = false;
data->cfg.address = 0;
data->cfg.frequencyhal_hz = config->master_frequency;
if (ifx_cat1_i2c_configure(dev, 0) != 0) {
/* Free I2C resource */
cyhal_i2c_free(&data->obj);
}
return 0;
}
static int ifx_cat1_i2c_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
struct ifx_cat1_i2c_data *data = (struct ifx_cat1_i2c_data *)dev->data;
const struct ifx_cat1_i2c_config *config = dev->config;
if (!cfg) {
return -EINVAL;
}
if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
return -ENOTSUP;
}
data->p_target_config = cfg;
data->cfg.is_slave = true;
data->cfg.address = data->p_target_config->address;
data->cfg.frequencyhal_hz = 100000;
if (ifx_cat1_i2c_configure(dev, I2C_SPEED_SET(I2C_SPEED_FAST)) != 0) {
/* Free I2C resource */
cyhal_i2c_free(&data->obj);
/* Release semaphore */
k_sem_give(&data->operation_sem);
return -EIO;
}
cyhal_i2c_enable_event(&data->obj, (cyhal_i2c_event_t)I2C_CAT1_SLAVE_EVENTS_MASK,
config->irq_priority, true);
return 0;
}
static int ifx_cat1_i2c_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
struct ifx_cat1_i2c_data *data = (struct ifx_cat1_i2c_data *)dev->data;
const struct ifx_cat1_i2c_config *config = dev->config;
/* Acquire semaphore (block I2C operation for another thread) */
k_sem_take(&data->operation_sem, K_FOREVER);
cyhal_i2c_free(&data->obj);
data->p_target_config = NULL;
cyhal_i2c_enable_event(&data->obj, (cyhal_i2c_event_t)I2C_CAT1_SLAVE_EVENTS_MASK,
config->irq_priority, false);
/* Release semaphore */
k_sem_give(&data->operation_sem);
return 0;
}
/* I2C API structure */
static const struct i2c_driver_api i2c_cat1_driver_api = {
.configure = ifx_cat1_i2c_configure,
.transfer = ifx_cat1_i2c_transfer,
.get_config = ifx_cat1_i2c_get_config,
.target_register = ifx_cat1_i2c_target_register,
.target_unregister = ifx_cat1_i2c_target_unregister};
/* Macros for I2C instance declaration */
#define INFINEON_CAT1_I2C_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static struct ifx_cat1_i2c_data ifx_cat1_i2c_data##n; \
\
static const struct ifx_cat1_i2c_config i2c_cat1_cfg_##n = { \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.master_frequency = DT_INST_PROP_OR(n, clock_frequency, 100000), \
.reg_addr = (CySCB_Type *)DT_INST_REG_ADDR(n), \
.irq_priority = DT_INST_IRQ(n, priority), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(n, ifx_cat1_i2c_init, NULL, &ifx_cat1_i2c_data##n, \
&i2c_cat1_cfg_##n, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_cat1_driver_api);
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_I2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,646 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_i2c_twihs
/** @file
* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
*
* Only I2C Master Mode with 7 bit addressing is currently supported.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_sam_twihs);
#include "i2c-priv.h"
/** I2C bus speed [Hz] in Standard Mode */
#define BUS_SPEED_STANDARD_HZ 100000U
/** I2C bus speed [Hz] in Fast Mode */
#define BUS_SPEED_FAST_HZ 400000U
/** I2C bus speed [Hz] in High Speed Mode */
#define BUS_SPEED_HIGH_HZ 3400000U
/* Maximum value of Clock Divider (CKDIV) */
#define CKDIV_MAX 7
/* Device constant configuration parameters */
struct i2c_sam_twihs_dev_cfg {
Twihs *regs;
void (*irq_config)(void);
uint32_t bitrate;
const struct atmel_sam_pmc_config clock_cfg;
const struct pinctrl_dev_config *pcfg;
uint8_t irq_id;
};
struct twihs_msg {
/* Buffer containing data to read or write */
uint8_t *buf;
/* Length of the buffer */
uint32_t len;
/* Index of the next byte to be read/written from/to the buffer */
uint32_t idx;
/* Value of TWIHS_SR at the end of the message */
uint32_t twihs_sr;
/* Transfer flags as defined in the i2c.h file */
uint8_t flags;
};
/* Device run time data */
struct i2c_sam_twihs_dev_data {
struct k_sem sem;
struct twihs_msg msg;
};
static int i2c_clk_set(Twihs *const twihs, uint32_t speed)
{
uint32_t ck_div = 0U;
uint32_t cl_div;
bool div_completed = false;
/* From the datasheet "TWIHS Clock Waveform Generator Register"
* T_low = ( ( CLDIV 2^CKDIV ) + 3 ) T_MCK
*/
while (!div_completed) {
cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3)
/ (1 << ck_div);
if (cl_div <= 255U) {
div_completed = true;
} else {
ck_div++;
}
}
if (ck_div > CKDIV_MAX) {
LOG_ERR("Failed to configure I2C clock");
return -EIO;
}
/* Set I2C bus clock duty cycle to 50% */
twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div)
| TWIHS_CWGR_CKDIV(ck_div);
return 0;
}
static int i2c_sam_twihs_configure(const struct device *dev, uint32_t config)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
Twihs *const twihs = dev_cfg->regs;
uint32_t bitrate;
int ret;
if (!(config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Master Mode is not enabled");
return -EIO;
}
if (config & I2C_ADDR_10_BITS) {
LOG_ERR("I2C 10-bit addressing is currently not supported");
LOG_ERR("Please submit a patch");
return -EIO;
}
/* Configure clock */
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
bitrate = BUS_SPEED_STANDARD_HZ;
break;
case I2C_SPEED_FAST:
bitrate = BUS_SPEED_FAST_HZ;
break;
default:
LOG_ERR("Unsupported I2C speed value");
return -EIO;
}
/* Setup clock waveform */
ret = i2c_clk_set(twihs, bitrate);
if (ret < 0) {
return ret;
}
/* Disable Slave Mode */
twihs->TWIHS_CR = TWIHS_CR_SVDIS;
/* Enable Master Mode */
twihs->TWIHS_CR = TWIHS_CR_MSEN;
return 0;
}
static void write_msg_start(Twihs *const twihs, struct twihs_msg *msg,
uint8_t daddr)
{
/* Set slave address. */
twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
/* Write first data byte on I2C bus */
twihs->TWIHS_THR = msg->buf[msg->idx++];
/* Enable Transmit Ready and Transmission Completed interrupts */
twihs->TWIHS_IER = TWIHS_IER_TXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
}
static void read_msg_start(Twihs *const twihs, struct twihs_msg *msg,
uint8_t daddr)
{
uint32_t twihs_cr_stop;
/* Set slave address and number of internal address bytes */
twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
/* Enable Receive Ready and Transmission Completed interrupts */
twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
/* In single data byte read the START and STOP must both be set */
twihs_cr_stop = (msg->len == 1U) ? TWIHS_CR_STOP : 0;
/* Start the transfer by sending START condition */
twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
}
static int i2c_sam_twihs_transfer(const struct device *dev,
struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
Twihs *const twihs = dev_cfg->regs;
__ASSERT_NO_MSG(msgs);
if (!num_msgs) {
return 0;
}
/* Clear pending interrupts, such as NACK. */
(void)twihs->TWIHS_SR;
/* Set number of internal address bytes to 0, not used. */
twihs->TWIHS_IADR = 0;
for (int i = 0; i < num_msgs; i++) {
dev_data->msg.buf = msgs[i].buf;
dev_data->msg.len = msgs[i].len;
dev_data->msg.idx = 0U;
dev_data->msg.twihs_sr = 0U;
dev_data->msg.flags = msgs[i].flags;
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
read_msg_start(twihs, &dev_data->msg, addr);
} else {
write_msg_start(twihs, &dev_data->msg, addr);
}
/* Wait for the transfer to complete */
k_sem_take(&dev_data->sem, K_FOREVER);
if (dev_data->msg.twihs_sr > 0) {
/* Something went wrong */
return -EIO;
}
}
return 0;
}
static void i2c_sam_twihs_isr(const struct device *dev)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
Twihs *const twihs = dev_cfg->regs;
struct twihs_msg *msg = &dev_data->msg;
uint32_t isr_status;
/* Retrieve interrupt status */
isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;
/* Not Acknowledged */
if (isr_status & TWIHS_SR_NACK) {
msg->twihs_sr = isr_status;
goto tx_comp;
}
/* Byte received */
if (isr_status & TWIHS_SR_RXRDY) {
msg->buf[msg->idx++] = twihs->TWIHS_RHR;
if (msg->idx == msg->len - 1U) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
}
}
/* Byte sent */
if (isr_status & TWIHS_SR_TXRDY) {
if (msg->idx == msg->len) {
if (msg->flags & I2C_MSG_STOP) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
/* Disable Transmit Ready interrupt */
twihs->TWIHS_IDR = TWIHS_IDR_TXRDY;
} else {
/* Transmission completed */
goto tx_comp;
}
} else {
twihs->TWIHS_THR = msg->buf[msg->idx++];
}
}
/* Transmission completed */
if (isr_status & TWIHS_SR_TXCOMP) {
goto tx_comp;
}
return;
tx_comp:
/* Disable all enabled interrupts */
twihs->TWIHS_IDR = twihs->TWIHS_IMR;
/* We are done */
k_sem_give(&dev_data->sem);
}
static int i2c_sam_twihs_initialize(const struct device *dev)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
Twihs *const twihs = dev_cfg->regs;
uint32_t bitrate_cfg;
int ret;
/* Configure interrupts */
dev_cfg->irq_config();
/* Initialize semaphore */
k_sem_init(&dev_data->sem, 0, 1);
/* Connect pins to the peripheral */
ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Enable TWIHS clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Reset the module */
twihs->TWIHS_CR = TWIHS_CR_SWRST;
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
ret = i2c_sam_twihs_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret < 0) {
LOG_ERR("Failed to initialize %s device", dev->name);
return ret;
}
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct i2c_driver_api i2c_sam_twihs_driver_api = {
.configure = i2c_sam_twihs_configure,
.transfer = i2c_sam_twihs_transfer,
};
#define I2C_TWIHS_SAM_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void i2c##n##_sam_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
i2c_sam_twihs_isr, \
DEVICE_DT_INST_GET(n), 0); \
} \
\
static const struct i2c_sam_twihs_dev_cfg i2c##n##_sam_config = {\
.regs = (Twihs *)DT_INST_REG_ADDR(n), \
.irq_config = i2c##n##_sam_irq_config, \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
.irq_id = DT_INST_IRQN(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct i2c_sam_twihs_dev_data i2c##n##_sam_data; \
\
I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twihs_initialize, \
NULL, \
&i2c##n##_sam_data, &i2c##n##_sam_config, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_sam_twihs_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_TWIHS_SAM_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_sam_twihs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,928 |
```c
/*
*
*/
#define DT_DRV_COMPAT brcm_iproc_i2c
#include <errno.h>
#include <stdint.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
LOG_MODULE_REGISTER(iproc_i2c);
#include "i2c-priv.h"
/* Registers */
#define CFG_OFFSET 0x00
#define CFG_RESET_SHIFT 31
#define CFG_EN_SHIFT 30
#define CFG_M_RETRY_CNT_SHIFT 16
#define CFG_M_RETRY_CNT_MASK 0x0f
#define TIM_CFG_OFFSET 0x04
#define TIM_CFG_MODE_400_SHIFT 31
#define TIM_RAND_TARGET_STRETCH_SHIFT 24
#define TIM_RAND_TARGET_STRETCH_MASK 0x7f
#define S_ADDR_OFFSET 0x08
#define S_ADDR_OFFSET_ADDR0_MASK 0x7f
#define S_ADDR_OFFSET_ADDR0_SHIFT 0
#define S_ADDR_OFFSET_ADDR0_EN_BIT 7
#define M_FIFO_CTRL_OFFSET 0x0c
#define M_FIFO_RX_FLUSH_SHIFT 31
#define M_FIFO_TX_FLUSH_SHIFT 30
#define M_FIFO_RX_CNT_SHIFT 16
#define M_FIFO_RX_CNT_MASK 0x7f
#define M_FIFO_RX_THLD_SHIFT 8
#define M_FIFO_RX_THLD_MASK 0x3f
#define S_FIFO_CTRL_OFFSET 0x10
#define S_FIFO_RX_FLUSH_SHIFT 31
#define S_FIFO_TX_FLUSH_SHIFT 30
#define M_CMD_OFFSET 0x30
#define M_CMD_START_BUSY_SHIFT 31
#define M_CMD_STATUS_SHIFT 25
#define M_CMD_STATUS_MASK 0x07
#define M_CMD_STATUS_SUCCESS 0x0
#define M_CMD_STATUS_LOST_ARB 0x1
#define M_CMD_STATUS_NACK_ADDR 0x2
#define M_CMD_STATUS_NACK_DATA 0x3
#define M_CMD_STATUS_TIMEOUT 0x4
#define M_CMD_STATUS_FIFO_UNDERRUN 0x5
#define M_CMD_STATUS_RX_FIFO_FULL 0x6
#define M_CMD_SMB_PROT_SHIFT 9
#define M_CMD_SMB_PROT_QUICK 0x0
#define M_CMD_SMB_PROT_MASK 0xf
#define M_CMD_SMB_PROT_BLK_WR 0x7
#define M_CMD_SMB_PROT_BLK_RD 0x8
#define M_CMD_PEC_SHIFT 8
#define M_CMD_RD_CNT_MASK 0xff
#define S_CMD_OFFSET 0x34
#define S_CMD_START_BUSY_SHIFT 31
#define S_CMD_STATUS_SHIFT 23
#define S_CMD_STATUS_MASK 0x07
#define S_CMD_STATUS_TIMEOUT 0x5
#define S_CMD_STATUS_MASTER_ABORT 0x7
#define IE_OFFSET 0x38
#define IE_M_RX_FIFO_FULL_SHIFT 31
#define IE_M_RX_THLD_SHIFT 30
#define IE_M_START_BUSY_SHIFT 28
#define IE_M_TX_UNDERRUN_SHIFT 27
#define IE_S_RX_FIFO_FULL_SHIFT 26
#define IE_S_RX_THLD_SHIFT 25
#define IE_S_RX_EVENT_SHIFT 24
#define IE_S_START_BUSY_SHIFT 23
#define IE_S_TX_UNDERRUN_SHIFT 22
#define IE_S_RD_EN_SHIFT 21
#define IS_OFFSET 0x3c
#define IS_M_RX_FIFO_FULL_SHIFT 31
#define IS_M_RX_THLD_SHIFT 30
#define IS_M_START_BUSY_SHIFT 28
#define IS_M_TX_UNDERRUN_SHIFT 27
#define IS_S_RX_FIFO_FULL_SHIFT 26
#define IS_S_RX_THLD_SHIFT 25
#define IS_S_RX_EVENT_SHIFT 24
#define IS_S_START_BUSY_SHIFT 23
#define IS_S_TX_UNDERRUN_SHIFT 22
#define IS_S_RD_EN_SHIFT 21
#define M_TX_OFFSET 0x40
#define M_TX_WR_STATUS_SHIFT 31
#define M_TX_DATA_MASK 0xff
#define M_RX_OFFSET 0x44
#define M_RX_STATUS_SHIFT 30
#define M_RX_STATUS_MASK 0x03
#define M_RX_PEC_ERR_SHIFT 29
#define M_RX_DATA_SHIFT 0
#define M_RX_DATA_MASK 0xff
#define S_TX_OFFSET 0x48
#define S_TX_WR_STATUS_SHIFT 31
#define S_RX_OFFSET 0x4c
#define S_RX_STATUS_SHIFT 30
#define S_RX_STATUS_MASK 0x03
#define S_RX_DATA_SHIFT 0x0
#define S_RX_DATA_MASK 0xff
#define I2C_TIMEOUT_MSEC 100
#define TX_RX_FIFO_SIZE 64
#define M_RX_FIFO_MAX_THLD_VALUE (TX_RX_FIFO_SIZE - 1)
#define M_RX_FIFO_THLD_VALUE 50
#define I2C_MAX_TARGET_ADDR 0x7f
#define I2C_TARGET_RX_FIFO_EMPTY 0x0
#define I2C_TARGET_RX_START 0x1
#define I2C_TARGET_RX_DATA 0x2
#define I2C_TARGET_RX_END 0x3
#define IE_S_ALL_INTERRUPT_SHIFT 21
#define IE_S_ALL_INTERRUPT_MASK 0x3f
#define TARGET_CLOCK_STRETCH_TIME 25
/*
* To keep running in ISR for less time,
* max target read per interrupt is set to 10 bytes.
*/
#define MAX_TARGET_RX_PER_INT 10
#define ISR_MASK_TARGET \
(BIT(IS_S_START_BUSY_SHIFT) | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EN_SHIFT) | \
BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT) | BIT(IS_S_RX_THLD_SHIFT))
#define ISR_MASK \
(BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT) | BIT(IS_M_RX_THLD_SHIFT))
#define DEV_CFG(dev) ((struct iproc_i2c_config *)(dev)->config)
#define DEV_DATA(dev) ((struct iproc_i2c_data *)(dev)->data)
#define DEV_BASE(dev) ((DEV_CFG(dev))->base)
struct iproc_i2c_config {
mem_addr_t base;
uint32_t bitrate;
void (*irq_config_func)(const struct device *dev);
};
struct iproc_i2c_data {
struct i2c_target_config *target_cfg;
struct i2c_msg *msg;
uint32_t tx_bytes;
uint32_t rx_bytes;
uint32_t thld_bytes;
uint32_t tx_underrun;
struct k_sem device_sync_sem;
uint32_t target_int_mask;
bool rx_start_rcvd;
bool target_read_complete;
bool target_rx_only;
};
static void iproc_i2c_enable_disable(const struct device *dev, bool enable)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
val = sys_read32(base + CFG_OFFSET);
if (enable) {
val |= BIT(CFG_EN_SHIFT);
} else {
val &= ~BIT(CFG_EN_SHIFT);
}
sys_write32(val, base + CFG_OFFSET);
}
static void iproc_i2c_reset_controller(const struct device *dev)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
/* put controller in reset */
val = sys_read32(base + CFG_OFFSET);
val |= BIT(CFG_RESET_SHIFT);
val &= ~BIT(CFG_EN_SHIFT);
sys_write32(val, base + CFG_OFFSET);
k_busy_wait(100);
/* bring controller out of reset */
sys_clear_bit(base + CFG_OFFSET, CFG_RESET_SHIFT);
}
#ifdef CONFIG_I2C_TARGET
/* Set target addr */
static int iproc_i2c_target_set_address(const struct device *dev, uint16_t addr)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
if ((addr == 0) && (addr > I2C_MAX_TARGET_ADDR)) {
LOG_ERR("Invalid target address(0x%x) received", addr);
return -EINVAL;
}
addr = ((addr & S_ADDR_OFFSET_ADDR0_MASK) | BIT(S_ADDR_OFFSET_ADDR0_EN_BIT));
val = sys_read32(base + S_ADDR_OFFSET);
val &= ~(S_ADDR_OFFSET_ADDR0_MASK | BIT(S_ADDR_OFFSET_ADDR0_EN_BIT));
val |= addr;
sys_write32(val, base + S_ADDR_OFFSET);
return 0;
}
static int iproc_i2c_target_init(const struct device *dev, bool need_reset)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
mem_addr_t base = DEV_BASE(dev);
struct i2c_target_config *target_config = dd->target_cfg;
uint32_t val;
int ret;
if (need_reset) {
iproc_i2c_reset_controller(dev);
}
/* flush target TX/RX FIFOs */
val = BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT);
sys_write32(val, base + S_FIFO_CTRL_OFFSET);
/* Maximum target stretch time */
val = sys_read32(base + TIM_CFG_OFFSET);
val &= ~(TIM_RAND_TARGET_STRETCH_MASK << TIM_RAND_TARGET_STRETCH_SHIFT);
val |= (TARGET_CLOCK_STRETCH_TIME << TIM_RAND_TARGET_STRETCH_SHIFT);
sys_write32(val, base + TIM_CFG_OFFSET);
/* Set target address */
ret = iproc_i2c_target_set_address(dev, target_config->address);
if (ret) {
return ret;
}
/* clear all pending target interrupts */
sys_write32(ISR_MASK_TARGET, base + IS_OFFSET);
/* Enable interrupt register to indicate a valid byte in receive fifo */
val = BIT(IE_S_RX_EVENT_SHIFT);
/* Enable interrupt register to indicate target Rx FIFO Full */
val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
/* Enable interrupt register to indicate a Master read transaction */
val |= BIT(IE_S_RD_EN_SHIFT);
/* Enable interrupt register for the target BUSY command */
val |= BIT(IE_S_START_BUSY_SHIFT);
dd->target_int_mask = val;
sys_write32(val, base + IE_OFFSET);
return ret;
}
static int iproc_i2c_check_target_status(const struct device *dev)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
val = sys_read32(base + S_CMD_OFFSET);
/* status is valid only when START_BUSY is cleared after it was set */
if (val & BIT(S_CMD_START_BUSY_SHIFT)) {
return -EBUSY;
}
val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
if ((val == S_CMD_STATUS_TIMEOUT) || (val == S_CMD_STATUS_MASTER_ABORT)) {
if (val == S_CMD_STATUS_TIMEOUT) {
LOG_ERR("target random stretch time timeout");
} else if (val == S_CMD_STATUS_MASTER_ABORT) {
LOG_ERR("Master aborted read transaction");
}
/* re-initialize i2c for recovery */
iproc_i2c_enable_disable(dev, false);
iproc_i2c_target_init(dev, true);
iproc_i2c_enable_disable(dev, true);
return -ETIMEDOUT;
}
return 0;
}
static void iproc_i2c_target_read(const struct device *dev)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
struct i2c_target_config *target_cfg = dd->target_cfg;
mem_addr_t base = DEV_BASE(dev);
uint8_t rx_data, rx_status;
uint32_t rx_bytes = 0;
uint32_t val;
while (rx_bytes < MAX_TARGET_RX_PER_INT) {
val = sys_read32(base + S_RX_OFFSET);
rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
if (rx_status == I2C_TARGET_RX_START) {
/* Start of SMBUS Master write */
target_cfg->callbacks->write_requested(target_cfg);
dd->rx_start_rcvd = true;
dd->target_read_complete = false;
} else if ((rx_status == I2C_TARGET_RX_DATA) && dd->rx_start_rcvd) {
/* Middle of SMBUS Master write */
target_cfg->callbacks->write_received(target_cfg, rx_data);
} else if ((rx_status == I2C_TARGET_RX_END) && dd->rx_start_rcvd) {
/* End of SMBUS Master write */
if (dd->target_rx_only) {
target_cfg->callbacks->write_received(target_cfg, rx_data);
}
target_cfg->callbacks->stop(target_cfg);
} else if (rx_status == I2C_TARGET_RX_FIFO_EMPTY) {
dd->rx_start_rcvd = false;
dd->target_read_complete = true;
break;
}
rx_bytes++;
}
}
static void iproc_i2c_target_rx(const struct device *dev)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
mem_addr_t base = DEV_BASE(dev);
iproc_i2c_target_read(dev);
if (!dd->target_rx_only && dd->target_read_complete) {
/*
* In case of single byte master-read request,
* IS_S_TX_UNDERRUN_SHIFT event is generated before
* IS_S_START_BUSY_SHIFT event. Hence start target data send
* from first IS_S_TX_UNDERRUN_SHIFT event.
*
* This means don't send any data from target when
* IS_S_RD_EN_SHIFT event is generated else it will increment
* eeprom or other backend target driver read pointer twice.
*/
dd->tx_underrun = 0;
dd->target_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
/* clear IS_S_RD_EN_SHIFT interrupt */
sys_write32(BIT(IS_S_RD_EN_SHIFT), base + IS_OFFSET);
}
/* enable target interrupts */
sys_write32(dd->target_int_mask, base + IE_OFFSET);
}
static void iproc_i2c_target_isr(const struct device *dev, uint32_t status)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
struct i2c_target_config *target_cfg = dd->target_cfg;
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
uint8_t data;
LOG_DBG("iproc_i2c(0x%x): %s: sl_sts 0x%x", (uint32_t)base, __func__, status);
if (status & BIT(IS_S_RX_EVENT_SHIFT) || status & BIT(IS_S_RD_EN_SHIFT) ||
status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
/* disable target interrupts */
val = sys_read32(base + IE_OFFSET);
val &= ~dd->target_int_mask;
sys_write32(val, base + IE_OFFSET);
if (status & BIT(IS_S_RD_EN_SHIFT)) {
/* Master-write-read request */
dd->target_rx_only = false;
} else {
/* Master-write request only */
dd->target_rx_only = true;
}
/*
* Clear IS_S_RX_EVENT_SHIFT &
* IS_S_RX_FIFO_FULL_SHIFT interrupt
*/
val = BIT(IS_S_RX_EVENT_SHIFT);
if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
val |= BIT(IS_S_RX_FIFO_FULL_SHIFT);
}
sys_write32(val, base + IS_OFFSET);
iproc_i2c_target_rx(dev);
}
if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
dd->tx_underrun++;
if (dd->tx_underrun == 1) {
/* Start of SMBUS for Master Read */
target_cfg->callbacks->read_requested(target_cfg, &data);
} else {
/* Master read other than start */
target_cfg->callbacks->read_processed(target_cfg, &data);
}
sys_write32(data, base + S_TX_OFFSET);
/* start transfer */
val = BIT(S_CMD_START_BUSY_SHIFT);
sys_write32(val, base + S_CMD_OFFSET);
sys_write32(BIT(IS_S_TX_UNDERRUN_SHIFT), base + IS_OFFSET);
}
/* Stop received from master in case of master read transaction */
if (status & BIT(IS_S_START_BUSY_SHIFT)) {
/*
* Disable interrupt for TX FIFO becomes empty and
* less than PKT_LENGTH bytes were output on the SMBUS
*/
dd->target_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
sys_write32(dd->target_int_mask, base + IE_OFFSET);
/* End of SMBUS for Master Read */
val = BIT(S_TX_WR_STATUS_SHIFT);
sys_write32(val, base + S_TX_OFFSET);
val = BIT(S_CMD_START_BUSY_SHIFT);
sys_write32(val, base + S_CMD_OFFSET);
/* flush TX FIFOs */
val = sys_read32(base + S_FIFO_CTRL_OFFSET);
val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
sys_write32(val, base + S_FIFO_CTRL_OFFSET);
target_cfg->callbacks->stop(target_cfg);
sys_write32(BIT(IS_S_START_BUSY_SHIFT), base + IS_OFFSET);
}
/* check target transmit status only if target is transmitting */
if (!dd->target_rx_only) {
iproc_i2c_check_target_status(dev);
}
}
static int iproc_i2c_target_register(const struct device *dev,
struct i2c_target_config *target_config)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
mem_addr_t base = DEV_BASE(dev);
int ret = 0;
if (dd->target_cfg) {
LOG_ERR("Target already registered");
return -EBUSY;
}
/* Save pointer to received target config */
dd->target_cfg = target_config;
ret = iproc_i2c_target_init(dev, false);
if (ret < 0) {
LOG_ERR("Failed to register iproc_i2c(0x%x) as target, ret %d", (uint32_t)base,
ret);
return ret;
}
return 0;
}
static int iproc_i2c_target_unregister(const struct device *dev, struct i2c_target_config *config)
{
uint32_t val;
mem_addr_t base = DEV_BASE(dev);
struct iproc_i2c_data *dd = DEV_DATA(dev);
if (!dd->target_cfg) {
return -EINVAL;
}
/* Erase the target address programmed */
sys_write32(0x0, base + S_ADDR_OFFSET);
/* disable all target interrupts */
val = sys_read32(base + IE_OFFSET);
val &= ~(IE_S_ALL_INTERRUPT_MASK << IE_S_ALL_INTERRUPT_SHIFT);
sys_write32(val, base + IE_OFFSET);
dd->target_cfg = NULL;
return 0;
}
#endif /* CONFIG_I2C_TARGET */
static void iproc_i2c_common_init(const struct device *dev)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
iproc_i2c_reset_controller(dev);
/* flush TX/RX FIFOs and set RX FIFO threshold to zero */
val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
sys_write32(val, base + M_FIFO_CTRL_OFFSET);
/* disable all interrupts */
sys_write32(0, base + IE_OFFSET);
/* clear all pending interrupts */
sys_write32(~0, base + IS_OFFSET);
}
static int iproc_i2c_check_status(const struct device *dev, uint16_t dev_addr, struct i2c_msg *msg)
{
mem_addr_t base = DEV_BASE(dev);
uint32_t val;
int rc;
val = sys_read32(base + M_CMD_OFFSET);
val >>= M_CMD_STATUS_SHIFT;
val &= M_CMD_STATUS_MASK;
switch (val) {
case M_CMD_STATUS_SUCCESS:
rc = 0;
break;
case M_CMD_STATUS_LOST_ARB:
LOG_ERR("lost bus arbitration");
rc = -EAGAIN;
break;
case M_CMD_STATUS_NACK_ADDR:
LOG_ERR("NAK addr:0x%02x", dev_addr);
rc = -ENXIO;
break;
case M_CMD_STATUS_NACK_DATA:
LOG_ERR("NAK data");
rc = -ENXIO;
break;
case M_CMD_STATUS_TIMEOUT:
LOG_ERR("bus timeout");
rc = -ETIMEDOUT;
break;
case M_CMD_STATUS_FIFO_UNDERRUN:
LOG_ERR("FIFO Under-run");
rc = -ENXIO;
break;
case M_CMD_STATUS_RX_FIFO_FULL:
LOG_ERR("RX FIFO full");
rc = -ETIMEDOUT;
break;
default:
LOG_ERR("Unknown Error : 0x%x", val);
iproc_i2c_enable_disable(dev, false);
iproc_i2c_common_init(dev);
iproc_i2c_enable_disable(dev, true);
rc = -EIO;
break;
}
if (rc < 0) {
/* flush both Master TX/RX FIFOs */
val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
sys_write32(val, base + M_FIFO_CTRL_OFFSET);
}
return rc;
}
static int iproc_i2c_configure(const struct device *dev, uint32_t dev_cfg_raw)
{
mem_addr_t base = DEV_BASE(dev);
if (I2C_ADDR_10_BITS & dev_cfg_raw) {
LOG_ERR("10-bit addressing not supported");
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_cfg_raw)) {
case I2C_SPEED_STANDARD:
sys_clear_bit(base + TIM_CFG_OFFSET, TIM_CFG_MODE_400_SHIFT);
break;
case I2C_SPEED_FAST:
sys_set_bit(base + TIM_CFG_OFFSET, TIM_CFG_MODE_400_SHIFT);
break;
default:
LOG_ERR("Only standard or Fast speed modes are supported");
return -ENOTSUP;
}
return 0;
}
static void iproc_i2c_read_valid_bytes(const struct device *dev)
{
mem_addr_t base = DEV_BASE(dev);
struct iproc_i2c_data *dd = DEV_DATA(dev);
struct i2c_msg *msg = dd->msg;
uint32_t val;
/* Read valid data from RX FIFO */
while (dd->rx_bytes < msg->len) {
val = sys_read32(base + M_RX_OFFSET);
/* rx fifo empty */
if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) {
break;
}
msg->buf[dd->rx_bytes] = (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
dd->rx_bytes++;
}
}
static int iproc_i2c_data_recv(const struct device *dev)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
mem_addr_t base = DEV_BASE(dev);
struct i2c_msg *msg = dd->msg;
uint32_t bytes_left, val;
iproc_i2c_read_valid_bytes(dev);
bytes_left = msg->len - dd->rx_bytes;
if (bytes_left == 0) {
/* finished reading all data, disable rx thld event */
sys_clear_bit(base + IE_OFFSET, IS_M_RX_THLD_SHIFT);
} else if (bytes_left < dd->thld_bytes) {
/* set bytes left as threshold */
val = sys_read32(base + M_FIFO_CTRL_OFFSET);
val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
sys_write32(val, base + M_FIFO_CTRL_OFFSET);
dd->thld_bytes = bytes_left;
}
/*
* if bytes_left >= dd->thld_bytes, no need to change the THRESHOLD.
* It will remain as dd->thld_bytes itself
*/
return 0;
}
static int iproc_i2c_transfer_one(const struct device *dev, struct i2c_msg *msg, uint16_t dev_addr)
{
mem_addr_t base = DEV_BASE(dev);
struct iproc_i2c_data *dd = DEV_DATA(dev);
uint32_t val, addr, tx_bytes, val_intr_en;
int rc;
if (!!(sys_read32(base + M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
LOG_ERR("Bus busy, prev xfer ongoing");
return -EBUSY;
}
LOG_DBG("%s: msg dev_addr 0x%x flags 0x%x len 0x%x val 0x%x\n", __func__, dev_addr,
msg->flags, msg->len, msg->buf[0]);
/* Save current i2c_msg */
dd->msg = msg;
addr = dev_addr << 1 | (msg->flags & I2C_MSG_READ ? 1 : 0);
sys_write32(addr, base + M_TX_OFFSET);
tx_bytes = MIN(msg->len, (TX_RX_FIFO_SIZE - 1));
if (!(msg->flags & I2C_MSG_READ)) {
/* Fill master TX fifo */
for (uint32_t i = 0; i < tx_bytes; i++) {
val = msg->buf[i];
/* For the last byte, set MASTER_WR_STATUS bit */
if (i == msg->len - 1) {
val |= BIT(M_TX_WR_STATUS_SHIFT);
}
sys_write32(val, base + M_TX_OFFSET);
}
dd->tx_bytes = tx_bytes;
}
/*
* Enable the "start busy" interrupt, which will be triggered after the
* transaction is done, i.e., the internal start_busy bit, transitions
* from 1 to 0.
*/
val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
if (!(msg->flags & I2C_MSG_READ) && (msg->len > dd->tx_bytes)) {
val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
}
/*
* Program master command register (0x30) with protocol type and set
* start_busy_command bit to initiate the write transaction
*/
val = BIT(M_CMD_START_BUSY_SHIFT);
if (msg->len == 0) {
/* SMBUS QUICK Command (Read/Write) */
val |= (M_CMD_SMB_PROT_QUICK << M_CMD_SMB_PROT_SHIFT);
} else if (msg->flags & I2C_MSG_READ) {
uint32_t tmp;
dd->rx_bytes = 0;
/* SMBUS Block Read Command */
val |= M_CMD_SMB_PROT_BLK_RD << M_CMD_SMB_PROT_SHIFT;
val |= msg->len;
if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) {
dd->thld_bytes = M_RX_FIFO_THLD_VALUE;
} else {
dd->thld_bytes = msg->len;
}
/* set threshold value */
tmp = sys_read32(base + M_FIFO_CTRL_OFFSET);
tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
tmp |= dd->thld_bytes << M_FIFO_RX_THLD_SHIFT;
sys_write32(tmp, base + M_FIFO_CTRL_OFFSET);
/* enable the RX threshold interrupt */
val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
} else {
/* SMBUS Block Write Command */
val |= M_CMD_SMB_PROT_BLK_WR << M_CMD_SMB_PROT_SHIFT;
}
sys_write32(val_intr_en, base + IE_OFFSET);
sys_write32(val, base + M_CMD_OFFSET);
/* Wait for the transfer to complete or timeout */
rc = k_sem_take(&dd->device_sync_sem, K_MSEC(I2C_TIMEOUT_MSEC));
/* disable all interrupts */
sys_write32(0, base + IE_OFFSET);
if (rc != 0) {
/* flush both Master TX/RX FIFOs */
val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
sys_write32(val, base + M_FIFO_CTRL_OFFSET);
return rc;
}
/* Check for Master Xfer status */
rc = iproc_i2c_check_status(dev, dev_addr, msg);
return rc;
}
static int iproc_i2c_transfer_multi(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
int rc;
struct i2c_msg *msgs_chk = msgs;
if (!msgs_chk) {
return -EINVAL;
}
/* pre-check all msgs */
for (uint8_t i = 0; i < num_msgs; i++, msgs_chk++) {
if (!msgs_chk->buf) {
LOG_ERR("Invalid msg buffer");
return -EINVAL;
}
if (I2C_MSG_ADDR_10_BITS & msgs_chk->flags) {
LOG_ERR("10-bit addressing not supported");
return -ENOTSUP;
}
}
for (uint8_t i = 0; i < num_msgs; i++, msgs++) {
rc = iproc_i2c_transfer_one(dev, msgs, addr);
if (rc < 0) {
return rc;
}
}
return 0;
}
static void iproc_i2c_send_data(const struct device *dev)
{
mem_addr_t base = DEV_BASE(dev);
struct iproc_i2c_data *dd = DEV_DATA(dev);
struct i2c_msg *msg = dd->msg;
uint32_t tx_bytes = msg->len - dd->tx_bytes;
/* can only fill up to the FIFO size */
tx_bytes = MIN(tx_bytes, TX_RX_FIFO_SIZE);
for (uint32_t i = 0; i < tx_bytes; i++) {
/* start from where we left over */
uint32_t idx = dd->tx_bytes + i;
uint32_t val = msg->buf[idx];
/* mark the last byte */
if (idx == (msg->len - 1)) {
uint32_t tmp;
val |= BIT(M_TX_WR_STATUS_SHIFT);
/*
* Since this is the last byte, we should now
* disable TX FIFO underrun interrupt
*/
tmp = sys_read32(base + IE_OFFSET);
tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
sys_write32(tmp, base + IE_OFFSET);
}
/* load data into TX FIFO */
sys_write32(val, base + M_TX_OFFSET);
}
/* update number of transferred bytes */
dd->tx_bytes += tx_bytes;
}
static void iproc_i2c_master_isr(const struct device *dev, uint32_t status)
{
struct iproc_i2c_data *dd = DEV_DATA(dev);
/* TX FIFO is empty and we have more data to send */
if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) {
iproc_i2c_send_data(dev);
}
/* RX FIFO threshold is reached and data needs to be read out */
if (status & BIT(IS_M_RX_THLD_SHIFT)) {
iproc_i2c_data_recv(dev);
}
/* transfer is done */
if (status & BIT(IS_M_START_BUSY_SHIFT)) {
k_sem_give(&dd->device_sync_sem);
}
}
static void iproc_i2c_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
mem_addr_t base = DEV_BASE(dev);
uint32_t status;
uint32_t sl_status, curr_irqs;
curr_irqs = sys_read32(base + IE_OFFSET);
status = sys_read32(base + IS_OFFSET);
/* process only target interrupt which are enabled */
sl_status = status & curr_irqs & ISR_MASK_TARGET;
LOG_DBG("iproc_i2c(0x%x): sts 0x%x, sl_sts 0x%x, curr_ints 0x%x", (uint32_t)base, status,
sl_status, curr_irqs);
#ifdef CONFIG_I2C_TARGET
/* target events */
if (sl_status) {
iproc_i2c_target_isr(dev, sl_status);
return;
}
#endif
status &= ISR_MASK;
/* master events */
if (status) {
iproc_i2c_master_isr(dev, status);
sys_write32(status, base + IS_OFFSET);
}
}
static int iproc_i2c_init(const struct device *dev)
{
const struct iproc_i2c_config *config = DEV_CFG(dev);
struct iproc_i2c_data *dd = DEV_DATA(dev);
uint32_t bitrate = config->bitrate;
int error;
k_sem_init(&dd->device_sync_sem, 0, 1);
iproc_i2c_common_init(dev);
/* Set default clock frequency */
bitrate = i2c_map_dt_bitrate(bitrate);
if (dd->target_cfg == NULL) {
bitrate |= I2C_MODE_CONTROLLER;
}
error = iproc_i2c_configure(dev, bitrate);
if (error) {
return error;
}
config->irq_config_func(dev);
iproc_i2c_enable_disable(dev, true);
return 0;
}
static const struct i2c_driver_api iproc_i2c_driver_api = {
.configure = iproc_i2c_configure,
.transfer = iproc_i2c_transfer_multi,
#ifdef CONFIG_I2C_TARGET
.target_register = iproc_i2c_target_register,
.target_unregister = iproc_i2c_target_unregister,
#endif
};
#define IPROC_I2C_DEVICE_INIT(n) \
static void iproc_i2c_irq_config_func_##n(const struct device *dev) \
{ \
ARG_UNUSED(dev); \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), iproc_i2c_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
} \
\
static const struct iproc_i2c_config iproc_i2c_config_##n = { \
.base = DT_INST_REG_ADDR(n), \
.irq_config_func = iproc_i2c_irq_config_func_##n, \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct iproc_i2c_data iproc_i2c_data_##n; \
\
I2C_DEVICE_DT_INST_DEFINE(n, &iproc_i2c_init, NULL, &iproc_i2c_data_##n, \
&iproc_i2c_config_##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&iproc_i2c_driver_api);
DT_INST_FOREACH_STATUS_OKAY(IPROC_I2C_DEVICE_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_bcm_iproc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,451 |
```unknown
# I2C configuration options
#
# I2C options
#
menuconfig I2C
bool "Inter-Integrated Circuit (I2C) bus drivers"
help
Enable I2C Driver Configuration
if I2C
config I2C_SHELL
bool "I2C Shell"
depends on SHELL
help
Enable I2C Shell.
The I2C shell supports scanning, bus recovery, I2C read and write
operations.
config I2C_STATS
bool "I2C device Stats"
depends on STATS
help
Enable I2C Stats.
config I2C_DUMP_MESSAGES
bool "Log I2C transactions"
depends on LOG
depends on I2C_LOG_LEVEL_DBG
help
Dump every I2C transaction to the system log as debug level log messages.
config I2C_DUMP_MESSAGES_ALLOWLIST
bool "Use allowlist for logging of I2C transactions"
depends on I2C_DUMP_MESSAGES
depends on DT_HAS_ZEPHYR_I2C_DUMP_ALLOWLIST_ENABLED
help
Use allowlist to specify which devices transactions should be logged.
The allowlist is defined in the devicetree using the compatible string of
"zephyr,i2c-dump-allowlist" and phandles to the devices that need to be traced.
Example of devicetree node:
i2c-dump-allowlist {
compatible = "zephyr,i2c-dump-allowlist";
devices = < &display0 >, < &sensor3 >;
};
config I2C_CALLBACK
bool "I2C asynchronous callback API"
help
API and implementations of i2c_transfer_cb.
config HAS_I2C_RTIO
bool
help
This option must be selected by I2C controller drivers that optionally implement the RTIO
interface.
config I2C_RTIO
bool "I2C RTIO API"
depends on HAS_I2C_RTIO
select RTIO
help
API and implementations of I2C for RTIO
if I2C_RTIO
config I2C_RTIO_SQ_SIZE
int "Submission queue size for blocking calls"
default 4
help
Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver
submission queue. The queue depth determines the number of possible i2c_msg
structs that may be in the array given to i2c_transfer. A sensible default
is going to be 4 given the device address, register address, and a value
to be read or written.
config I2C_RTIO_CQ_SIZE
int "Completion queue size for blocking calls"
default 4
help
Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver
submission queue. The queue depth determines the number of possible i2c_msg
structs that may be in the array given to i2c_transfer. A sensible default
is going to be 4 given the device address, register address, and a value
to be read or written.
endif # I2C_RTIO
# Include these first so that any properties (e.g. defaults) below can be
# overridden (by defining symbols in multiple locations)
source "drivers/i2c/Kconfig.b91"
source "drivers/i2c/Kconfig.bcm_iproc"
source "drivers/i2c/Kconfig.cc13xx_cc26xx"
source "drivers/i2c/Kconfig.dw"
source "drivers/i2c/Kconfig.esp32"
source "drivers/i2c/target/Kconfig"
source "drivers/i2c/Kconfig.gpio"
source "drivers/i2c/Kconfig.xec"
source "drivers/i2c/Kconfig.nrfx"
source "drivers/i2c/Kconfig.i2c_emul"
source "drivers/i2c/Kconfig.it8xxx2"
source "drivers/i2c/Kconfig.sbcon"
source "drivers/i2c/Kconfig.sifive"
source "drivers/i2c/Kconfig.stm32"
source "drivers/i2c/Kconfig.sam0"
source "drivers/i2c/Kconfig.sam_twihs"
source "drivers/i2c/Kconfig.litex"
source "drivers/i2c/Kconfig.lpc11u6x"
source "drivers/i2c/Kconfig.npcx"
source "drivers/i2c/Kconfig.test"
source "drivers/i2c/Kconfig.rcar"
source "drivers/i2c/Kconfig.renesas_ra"
source "drivers/i2c/Kconfig.tca954x"
source "drivers/i2c/Kconfig.gd32"
source "drivers/i2c/Kconfig.ifx_cat1"
source "drivers/i2c/Kconfig.ifx_xmc4"
source "drivers/i2c/Kconfig.andes_atciic100"
source "drivers/i2c/Kconfig.sc18im704"
source "drivers/i2c/Kconfig.smartbond"
source "drivers/i2c/Kconfig.xilinx_axi"
source "drivers/i2c/Kconfig.mchp_mss"
source "drivers/i2c/Kconfig.sedi"
source "drivers/i2c/Kconfig.ambiq"
source "drivers/i2c/Kconfig.numaker"
source "drivers/i2c/Kconfig.mcux"
source "drivers/i2c/Kconfig.ene"
source "drivers/i2c/Kconfig.max32"
config I2C_INIT_PRIORITY
int "Init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
I2C device driver initialization priority.
module = I2C
module-str = i2c
source "subsys/logging/Kconfig.template.log_config"
config I2C_GECKO
bool "Gecko I2C driver"
default y
depends on DT_HAS_SILABS_GECKO_I2C_ENABLED
select SOC_GECKO_I2C
help
Enable the SiLabs Gecko I2C bus driver.
config I2C_SAM_TWIM
bool "Atmel SAM (TWIM) I2C driver"
default y
depends on DT_HAS_ATMEL_SAM_I2C_TWIM_ENABLED
help
Enable Atmel SAM MCU Family (TWIM) I2C bus driver.
config I2C_SAM_TWI
bool "Atmel SAM (TWI) I2C driver"
default y
depends on DT_HAS_ATMEL_SAM_I2C_TWI_ENABLED
help
Enable Atmel SAM MCU Family (TWI) I2C bus driver.
config I2C_MCUX
bool "MCUX I2C driver"
default y
depends on DT_HAS_NXP_KINETIS_I2C_ENABLED
select PINCTRL
help
Enable the mcux I2C driver.
config I2C_MCUX_LPI2C
bool "MCUX LPI2C driver"
default y
depends on DT_HAS_NXP_IMX_LPI2C_ENABLED
depends on CLOCK_CONTROL
select HAS_I2C_RTIO
select PINCTRL
help
Enable the mcux LPI2C driver.
config I2C_MCUX_LPI2C_BUS_RECOVERY
bool "Bus recovery support"
depends on I2C_MCUX_LPI2C && PINCTRL
select I2C_BITBANG
help
Enable LPI2C driver bus recovery support via GPIO bitbanging.
config I2C_IMX
bool "i.MX I2C driver"
default y
depends on DT_HAS_FSL_IMX21_I2C_ENABLED
help
Enable the i.MX I2C driver.
config I2C_CC32XX
bool "CC32XX I2C driver"
default y
depends on DT_HAS_TI_CC32XX_I2C_ENABLED
select PINCTRL
help
Enable the CC32XX I2C driver.
config I2C_BITBANG
bool
help
Enable library used for software driven (bit banging) I2C support
config I2C_NIOS2
bool "Nios-II I2C driver"
default y
depends on DT_HAS_ALTR_NIOS2_I2C_ENABLED
help
Enable the Nios-II I2C driver.
config I2C_RV32M1_LPI2C
bool "RV32M1 LPI2C driver"
default y
depends on DT_HAS_OPENISA_RV32M1_LPI2C_ENABLED
depends on CLOCK_CONTROL
select PINCTRL
help
Enable the RV32M1 LPI2C driver.
config GPIO_I2C_SWITCH
bool "GPIO controlled I2C bus switch"
default y
depends on DT_HAS_GPIO_I2C_SWITCH_ENABLED
help
Enable GPIO controlled I2C bus switch driver.
endif # I2C
``` | /content/code_sandbox/drivers/i2c/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,870 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_smartbond_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <DA1469xAB.h>
#include <da1469x_pd.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_smartbond);
#include "i2c-priv.h"
struct i2c_smartbond_cfg {
I2C_Type *regs;
int periph_clock_config;
const struct pinctrl_dev_config *pcfg;
uint32_t bitrate;
};
struct i2c_smartbond_data {
struct k_spinlock lock;
struct i2c_msg *msgs;
uint8_t num_msgs;
uint32_t transmit_cnt, receive_cnt;
i2c_callback_t cb;
void *userdata;
#ifdef CONFIG_I2C_CALLBACK
k_spinlock_key_t spinlock_key;
#endif
};
#if defined(CONFIG_PM_DEVICE)
static inline void i2c_smartbond_pm_prevent_system_sleep(void)
{
/*
* Prevent the SoC from etering the normal sleep state as PDC does not support
* waking up the application core following I2C events.
*/
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
static inline void i2c_smartbond_pm_allow_system_sleep(void)
{
/*
* Allow the SoC to enter the nornmal sleep state once I2C transactions are done.
*/
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
#endif
static inline void i2c_smartbond_pm_policy_state_lock_get(const struct device *dev)
{
#ifdef CONFIG_PM_DEVICE
#ifdef CONFIG_PM_DEVICE_RUNTIME
pm_device_runtime_get(dev);
#else
ARG_UNUSED(dev);
i2c_smartbond_pm_prevent_system_sleep();
#endif
#endif
}
static inline void i2c_smartbond_pm_policy_state_lock_put(const struct device *dev)
{
#ifdef CONFIG_PM_DEVICE
#ifdef CONFIG_PM_DEVICE_RUNTIME
pm_device_runtime_put(dev);
#else
ARG_UNUSED(dev);
i2c_smartbond_pm_allow_system_sleep();
#endif
#endif
}
static inline bool i2c_smartbond_is_idle(const struct device *dev)
{
const struct i2c_smartbond_cfg *config = dev->config;
uint32_t mask = I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk |
I2C_I2C_STATUS_REG_RFNE_Msk |
I2C_I2C_STATUS_REG_TFE_Msk;
return ((config->regs->I2C_STATUS_REG & mask) == I2C_I2C_STATUS_REG_TFE_Msk);
}
static void i2c_smartbond_disable_when_inactive(const struct device *dev)
{
const struct i2c_smartbond_cfg *config = dev->config;
if ((config->regs->I2C_ENABLE_REG & I2C_I2C_ENABLE_REG_I2C_EN_Msk)) {
while (!i2c_smartbond_is_idle(dev)) {
};
config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk;
}
}
static int i2c_smartbond_apply_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
uint32_t con_reg = 0x0UL;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Configure Speed (SCL frequency) */
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
con_reg |= 1UL << I2C_I2C_CON_REG_I2C_SPEED_Pos;
break;
case I2C_SPEED_FAST:
con_reg |= 2UL << I2C_I2C_CON_REG_I2C_SPEED_Pos;
break;
/* TODO: Currently 1 MHz, add switching to 96 MHz PLL sys_clk to support 3.4 Mbit/s */
/*
* case I2C_SPEED_HIGH:
* con_reg |= 3UL << I2C_I2C_CON_REG_I2C_SPEED_Pos;
* break;
*/
default:
LOG_ERR("Speed not supported");
return -ENOTSUP;
}
/* Configure Mode */
if ((dev_config & I2C_MODE_CONTROLLER) == I2C_MODE_CONTROLLER) {
con_reg |=
I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk | I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk;
} else {
LOG_ERR("Only I2C Controller mode supported");
return -ENOTSUP;
}
/* Enable sending RESTART as master */
con_reg |= I2C_I2C_CON_REG_I2C_RESTART_EN_Msk;
i2c_smartbond_disable_when_inactive(dev);
/* Write control register*/
config->regs->I2C_CON_REG = con_reg;
/* Reset interrupt mask */
config->regs->I2C_INTR_MASK_REG = 0x0000U;
config->regs->I2C_ENABLE_REG |= I2C_I2C_ENABLE_REG_I2C_EN_Msk;
k_spin_unlock(&data->lock, key);
return 0;
}
static int i2c_smartbond_configure(const struct device *dev, uint32_t dev_config)
{
int ret = 0;
pm_device_runtime_get(dev);
ret = i2c_smartbond_apply_configure(dev, dev_config);
pm_device_runtime_put(dev);
return ret;
}
static int i2c_smartbond_get_config(const struct device *dev, uint32_t *dev_config)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = data = dev->data;
uint32_t reg;
k_spinlock_key_t key = k_spin_lock(&data->lock);
pm_device_runtime_get(dev);
/* Read the value of the control register */
reg = config->regs->I2C_CON_REG;
pm_device_runtime_put(dev);
k_spin_unlock(&data->lock, key);
*dev_config = 0UL;
/* Check if I2C is in controller or target mode */
if ((reg & I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk) &&
(reg & I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk)) {
*dev_config |= I2C_MODE_CONTROLLER;
} else if (!(reg & I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk) &&
!(reg & I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk)) {
*dev_config &= ~I2C_MODE_CONTROLLER;
} else {
return -EIO;
}
/* Get the operating speed */
switch ((reg & I2C_I2C_CON_REG_I2C_SPEED_Msk) >> I2C_I2C_CON_REG_I2C_SPEED_Pos) {
case 1UL:
*dev_config |= I2C_SPEED_SET(I2C_SPEED_STANDARD);
break;
case 2UL:
*dev_config |= I2C_SPEED_SET(I2C_SPEED_FAST);
break;
case 3UL:
*dev_config |= I2C_SPEED_SET(I2C_SPEED_HIGH);
break;
default:
return -ERANGE;
}
return 0;
}
static inline void i2c_smartbond_set_target_address(const struct i2c_smartbond_cfg *const config,
struct i2c_smartbond_data *data,
const struct i2c_msg *const msg, uint16_t addr)
{
/* Disable I2C Controller */
config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk;
/* Configure addressing mode*/
if (msg->flags & I2C_MSG_ADDR_10_BITS) {
config->regs->I2C_CON_REG |= I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk;
} else {
config->regs->I2C_CON_REG &= ~(I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk);
}
/* Change the Target Address */
config->regs->I2C_TAR_REG = ((config->regs->I2C_TAR_REG & ~I2C_I2C_TAR_REG_IC_TAR_Msk) |
(addr & I2C_I2C_TAR_REG_IC_TAR_Msk));
/* Enable again the I2C to use the new address */
config->regs->I2C_ENABLE_REG |= I2C_I2C_ENABLE_REG_I2C_EN_Msk;
}
static inline int i2c_smartbond_set_msg_flags(struct i2c_msg *msgs, uint8_t num_msgs)
{
struct i2c_msg *current, *next;
current = msgs;
for (uint8_t i = 1; i <= num_msgs; i++) {
if (i < num_msgs) {
next = current + 1;
if ((current->flags & I2C_MSG_RW_MASK) != (next->flags & I2C_MSG_RW_MASK)) {
next->flags |= I2C_MSG_RESTART;
}
if (current->flags & I2C_MSG_STOP) {
return -EINVAL;
}
} else {
current->flags |= I2C_MSG_STOP;
}
current++;
}
return 0;
}
static inline int i2c_smartbond_prep_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
int ret = 0;
ret = i2c_smartbond_set_msg_flags(msgs, num_msgs);
if (ret != 0) {
return ret;
}
i2c_smartbond_set_target_address(config, data, msgs, addr);
data->msgs = msgs;
data->num_msgs = num_msgs;
data->transmit_cnt = 0;
data->receive_cnt = 0;
return 0;
}
static inline int i2c_smartbond_tx(const struct i2c_smartbond_cfg *const config,
struct i2c_smartbond_data *data)
{
const bool rw = ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
int ret = 0;
if (!data->msgs->buf || data->msgs->len == 0) {
return -EINVAL;
}
/* Transmits data or read commands with correct flags */
while ((data->transmit_cnt < data->msgs->len) &&
(config->regs->I2C_STATUS_REG & I2C_I2C_STATUS_REG_TFNF_Msk)) {
config->regs->I2C_DATA_CMD_REG =
(rw ? I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk
: (data->msgs->buf[data->transmit_cnt] &
I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk)) |
((data->transmit_cnt == 0) && (data->msgs->flags & I2C_MSG_RESTART)
? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk
: 0) |
((data->transmit_cnt == (data->msgs->len - 1)) &&
(data->msgs->flags & I2C_MSG_STOP)
? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk
: 0);
data->transmit_cnt++;
/* Return IO error if any of the abort flags are set */
if (config->regs->I2C_TX_ABRT_SOURCE_REG & 0x1FFFF) {
ret = -EIO;
}
}
if (config->regs->I2C_TX_ABRT_SOURCE_REG & 0x1FFFF) {
ret = -EIO;
}
if (ret) {
(void)config->regs->I2C_CLR_TX_ABRT_REG;
}
return ret;
}
static inline int i2c_smartbond_rx(const struct i2c_smartbond_cfg *const config,
struct i2c_smartbond_data *data)
{
int ret = 0;
if (!data->msgs->buf || data->msgs->len == 0) {
return -EINVAL;
}
/* Reads the data register until fifo is empty */
while ((data->receive_cnt < data->transmit_cnt) &&
(config->regs->I2C_STATUS_REG & I2C2_I2C2_STATUS_REG_RFNE_Msk)) {
data->msgs->buf[data->receive_cnt] =
config->regs->I2C_DATA_CMD_REG & I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk;
data->receive_cnt++;
}
return ret;
}
static int i2c_smartbond_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
int ret = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
i2c_smartbond_pm_policy_state_lock_get(dev);
ret = i2c_smartbond_prep_transfer(dev, msgs, num_msgs, addr);
if (ret != 0) {
goto finish;
}
for (; data->num_msgs > 0; data->num_msgs--, data->msgs++) {
data->transmit_cnt = 0;
data->receive_cnt = 0;
if ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
/* Repeating transmit and receives until all data has been read */
while (data->receive_cnt < data->msgs->len) {
/* Transmit read commands */
ret = i2c_smartbond_tx(config, data);
if (ret < 0) {
goto finish;
}
/* Read received data */
ret = i2c_smartbond_rx(config, data);
if (ret < 0) {
goto finish;
}
}
} else {
while (data->transmit_cnt < data->msgs->len) {
/* Transmit data */
ret = i2c_smartbond_tx(config, data);
if (ret < 0) {
goto finish;
}
}
}
}
finish:
while (!i2c_smartbond_is_idle(dev)) {
};
i2c_smartbond_pm_policy_state_lock_put(dev);
k_spin_unlock(&data->lock, key);
return ret;
}
#ifdef CONFIG_I2C_CALLBACK
#define TX_FIFO_DEPTH 32
static int i2c_smartbond_enable_msg_interrupts(const struct i2c_smartbond_cfg *const config,
struct i2c_smartbond_data *data)
{
if ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
uint32_t remaining = data->msgs->len - data->receive_cnt;
uint32_t tx_space = TX_FIFO_DEPTH - config->regs->I2C_TXFLR_REG;
uint32_t rx_tl = ((remaining < tx_space) ? remaining : tx_space) - 1;
config->regs->I2C_RX_TL_REG = rx_tl & I2C_I2C_RX_TL_REG_RX_TL_Msk;
config->regs->I2C_INTR_MASK_REG |= I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk;
} else {
config->regs->I2C_INTR_MASK_REG &= ~I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk;
}
config->regs->I2C_TX_TL_REG = 0UL;
config->regs->I2C_INTR_MASK_REG |= I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk;
return 0;
}
static int i2c_smartbond_transfer_cb(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t addr, i2c_callback_t cb,
void *userdata)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
int ret = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (cb == NULL) {
return -EINVAL;
}
if (data->cb != NULL) {
return -EWOULDBLOCK;
}
data->spinlock_key = key;
data->cb = cb;
data->userdata = userdata;
i2c_smartbond_pm_policy_state_lock_get(dev);
ret = i2c_smartbond_prep_transfer(dev, msgs, num_msgs, addr);
if (ret != 0) {
i2c_smartbond_pm_policy_state_lock_put(dev);
k_spin_unlock(&data->lock, key);
return ret;
}
i2c_smartbond_enable_msg_interrupts(config, data);
LOG_INF("async transfer started");
return 0;
}
static inline void isr_tx(const struct i2c_smartbond_cfg *config, struct i2c_smartbond_data *data)
{
const bool rw = ((data->msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
while ((data->transmit_cnt < data->msgs->len) &&
(config->regs->I2C_STATUS_REG & I2C_I2C_STATUS_REG_TFNF_Msk)) {
config->regs->I2C_DATA_CMD_REG =
(rw ? I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk
: (data->msgs->buf[data->transmit_cnt] &
I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk)) |
((data->transmit_cnt == 0) && (data->msgs->flags & I2C_MSG_RESTART)
? I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk
: 0) |
((data->transmit_cnt == (data->msgs->len - 1)) &&
(data->msgs->flags & I2C_MSG_STOP)
? I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk
: 0);
data->transmit_cnt++;
}
}
static inline void isr_rx(const struct i2c_smartbond_cfg *config, struct i2c_smartbond_data *data)
{
while ((data->receive_cnt < data->transmit_cnt) &&
(config->regs->I2C_STATUS_REG & I2C2_I2C2_STATUS_REG_RFNE_Msk)) {
data->msgs->buf[data->receive_cnt] =
config->regs->I2C_DATA_CMD_REG & I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk;
data->receive_cnt++;
}
}
static inline void i2c_smartbond_async_msg_done(const struct device *dev)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
data->num_msgs--;
if (data->num_msgs > 0) {
data->msgs++;
data->transmit_cnt = 0;
data->receive_cnt = 0;
i2c_smartbond_enable_msg_interrupts(config, data);
} else {
i2c_callback_t cb = data->cb;
data->msgs = NULL;
data->cb = NULL;
LOG_INF("async transfer finished");
cb(dev, 0, data->userdata);
while (!i2c_smartbond_is_idle(dev)) {
};
i2c_smartbond_pm_policy_state_lock_put(dev);
k_spin_unlock(&data->lock, data->spinlock_key);
}
}
static void i2c_smartbond_isr(const struct device *dev)
{
const struct i2c_smartbond_cfg *config = dev->config;
struct i2c_smartbond_data *data = dev->data;
uint32_t flags = config->regs->I2C_INTR_STAT_REG;
if (flags & I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk) {
isr_tx(config, data);
if (data->transmit_cnt == data->msgs->len) {
config->regs->I2C_INTR_MASK_REG &= ~I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk;
if ((data->msgs->flags & I2C_MSG_RW_MASK) != I2C_MSG_READ) {
i2c_smartbond_async_msg_done(dev);
}
}
}
if (flags & I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk) {
isr_rx(config, data);
if (data->receive_cnt == data->msgs->len) {
config->regs->I2C_INTR_MASK_REG &= ~I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk;
i2c_smartbond_async_msg_done(dev);
} else {
uint32_t remaining = data->msgs->len - data->receive_cnt;
uint32_t tx_space = 32 - config->regs->I2C_TXFLR_REG;
uint32_t rx_tl = ((remaining < tx_space) ? remaining : tx_space) - 1;
config->regs->I2C_RX_TL_REG = rx_tl & I2C_I2C_RX_TL_REG_RX_TL_Msk;
config->regs->I2C_INTR_MASK_REG |= I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk;
}
}
}
#define I2C_SMARTBOND_CONFIGURE(id) \
IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), i2c_smartbond_isr, \
DEVICE_DT_INST_GET(id), 0); \
irq_enable(DT_INST_IRQN(id));
#else
#define I2C_SMARTBOND_CONFIGURE(id)
#endif
static const struct i2c_driver_api i2c_smartbond_driver_api = {
.configure = i2c_smartbond_configure,
.get_config = i2c_smartbond_get_config,
.transfer = i2c_smartbond_transfer,
#ifdef CONFIG_I2C_CALLBACK
.transfer_cb = i2c_smartbond_transfer_cb,
#endif
};
static int i2c_smartbond_resume(const struct device *dev)
{
const struct i2c_smartbond_cfg *config = dev->config;
int err;
config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk;
/* Reset I2C CLK_SEL */
CRG_COM->RESET_CLK_COM_REG = (config->periph_clock_config << 1);
/* Set I2C CLK ENABLE */
CRG_COM->SET_CLK_COM_REG = config->periph_clock_config;
err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {
LOG_ERR("Failed to configure I2C pins");
return err;
}
return i2c_smartbond_apply_configure(dev,
I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
}
#if defined(CONFIG_PM_DEVICE)
static int i2c_smartbond_suspend(const struct device *dev)
{
int ret;
const struct i2c_smartbond_cfg *config = dev->config;
/* Disable the I2C digital block */
config->regs->I2C_ENABLE_REG &= ~I2C_I2C_ENABLE_REG_I2C_EN_Msk;
/* Gate I2C clocking */
CRG_COM->RESET_CLK_COM_REG = config->periph_clock_config;
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
LOG_WRN("Fialid to configure the I2C pins to inactive state");
}
return ret;
}
static int i2c_smartbond_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
#ifdef CONFIG_PM_DEVICE_RUNTIME
i2c_smartbond_pm_prevent_system_sleep();
#endif
/*
* Although the GPIO driver should already be initialized, make sure PD_COM
* is up and running before accessing the I2C block.
*/
da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
ret = i2c_smartbond_resume(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
ret = i2c_smartbond_suspend(dev);
/*
* Once the I2C block is turned off its power domain can
* be released, as well.
*/
da1469x_pd_release(MCU_PD_DOMAIN_COM);
#ifdef CONFIG_PM_DEVICE_RUNTIME
i2c_smartbond_pm_allow_system_sleep();
#endif
break;
default:
return -ENOTSUP;
}
return ret;
}
#endif
static int i2c_smartbond_init(const struct device *dev)
{
int ret;
#ifdef CONFIG_PM_DEVICE_RUNTIME
/* Make sure device state is marked as suspended */
pm_device_init_suspended(dev);
ret = pm_device_runtime_enable(dev);
#else
da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
ret = i2c_smartbond_resume(dev);
#endif
return ret;
}
#define I2C_SMARTBOND_DEVICE(id) \
PM_DEVICE_DT_INST_DEFINE(id, i2c_smartbond_pm_action); \
PINCTRL_DT_INST_DEFINE(id); \
static const struct i2c_smartbond_cfg i2c_smartbond_##id##_cfg = { \
.regs = (I2C_Type *)DT_INST_REG_ADDR(id), \
.periph_clock_config = DT_INST_PROP(id, periph_clock_config), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \
.bitrate = DT_INST_PROP_OR(id, clock_frequency, 100000)}; \
static struct i2c_smartbond_data i2c_smartbond_##id##_data = {.msgs = NULL, .cb = NULL}; \
static int i2c_smartbond_##id##_init(const struct device *dev) \
{ \
int ret = i2c_smartbond_init(dev); \
I2C_SMARTBOND_CONFIGURE(id); \
return ret; \
} \
I2C_DEVICE_DT_INST_DEFINE(id, i2c_smartbond_##id##_init, PM_DEVICE_DT_INST_GET(id), \
&i2c_smartbond_##id##_data, \
&i2c_smartbond_##id##_cfg, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_smartbond_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_SMARTBOND_DEVICE)
``` | /content/code_sandbox/drivers/i2c/i2c_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,790 |
```objective-c
/*
*
*/
/**
* @file I2C driver for AndesTech atciic100 IP
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/sys_io.h>
#define I2C_MAX_COUNT 256
#define BURST_CMD_COUNT 1
#define RED_IDR 0x00
#define REG_CFG 0x10
#define REG_INTE 0x14
#define REG_STAT 0x18
#define REG_ADDR 0x1C
#define REG_DATA 0x20
#define REG_CTRL 0x24
#define REG_CMD 0x28
#define REG_SET 0x2C
#define I2C_BASE(dev) \
((const struct i2c_atciic100_config * const)(dev)->config)->base
#define I2C_CFG(dev) (I2C_BASE(dev) + REG_CFG)
#define I2C_INTE(dev) (I2C_BASE(dev) + REG_INTE)
#define I2C_STAT(dev) (I2C_BASE(dev) + REG_STAT)
#define I2C_ADDR(dev) (I2C_BASE(dev) + REG_ADDR)
#define I2C_CMD(dev) (I2C_BASE(dev) + REG_CMD)
#define I2C_SET(dev) (I2C_BASE(dev) + REG_SET)
#define I2C_DATA(dev) (I2C_BASE(dev) + REG_DATA)
#define I2C_CTRL(dev) (I2C_BASE(dev) + REG_CTRL)
#define TARGET_ADDR_MSK BIT_MASK(10)
#define DATA_MSK BIT_MASK(8)
/* Interrupt Enable Register(RW) */
#define IEN_ALL BIT_MASK(10)
#define IEN_CMPL BIT(9)
#define IEN_BYTE_RECV BIT(8)
#define IEN_BYTE_TRANS BIT(7)
#define IEN_START BIT(6)
#define IEN_STOP BIT(5)
#define IEN_ARB_LOSE BIT(4)
#define IEN_ADDR_HIT BIT(3)
#define IEN_FIFO_HALF BIT(2)
#define IEN_FIFO_FULL BIT(1)
#define IEN_FIFO_EMPTY BIT(0)
/* Status Register(RW) */
#define STATUS_W1C_ALL (BIT_MASK(7) << 3)
#define STATUS_LINE_SDA BIT(14)
#define STATUS_LINE_SCL BIT(13)
#define STATUS_GEN_CALL BIT(12)
#define STATUS_BUS_BUSY BIT(11)
#define STATUS_ACK BIT(10)
#define STATUS_CMPL BIT(9)
#define STATUS_BYTE_RECV BIT(8)
#define STATUS_BYTE_TRANS BIT(7)
#define STATUS_START BIT(6)
#define STATUS_STOP BIT(5)
#define STATUS_ARB_LOSE BIT(4)
#define STATUS_ADDR_HIT BIT(3)
#define STATUS_FIFO_HALF BIT(2)
#define STATUS_FIFO_FULL BIT(1)
#define STATUS_FIFO_EMPTY BIT(0)
/* Control Register(RW) */
#define CTRL_PHASE_START BIT(12)
#define CTRL_PHASE_ADDR BIT(11)
#define CTRL_PHASE_DATA BIT(10)
#define CTRL_PHASE_STOP BIT(9)
#define CTRL_DIR BIT(8)
#define CTRL_DATA_COUNT BIT_MASK(8)
/* Command Register(RW) */
#define CMD_MSK BIT_MASK(3)
#define CMD_NO_ACT (0x0)
#define CMD_ISSUE_TRANSACTION (0x1)
#define CMD_ACK (0x2)
#define CMD_NACK (0x3)
#define CMD_CLEAR_FIFO (0x4)
#define CMD_RESET_I2C (0x5)
/* Setup Register(RW) */
#define SETUP_T_SUDAT (BIT_MASK(5) << 24)
#define SETUP_T_SP (BIT_MASK(3) << 21)
#define SETUP_T_HDDAT (BIT_MASK(5) << 16)
#define SETUP_T_SCL_RATIO BIT(13)
#define SETUP_T_SCLHI (BIT_MASK(9) << 4)
#define SETUP_DMA_EN BIT(3)
#define SETUP_CONTROLLER BIT(2)
#define SETUP_ADDRESSING BIT(1)
#define SETUP_I2C_EN BIT(0)
#if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 30000000
#define SETUP_T_SUDAT_STD (0x3)
#define SETUP_T_SP_STD (0x1)
#define SETUP_T_HDDAT_STD (5)
#define SETUP_T_SCL_RATIO_STD (0x0)
#define SETUP_T_SCLHI_STD (138)
#define SETUP_T_SUDAT_FAST (0x0)
#define SETUP_T_SP_FAST (0x1)
#define SETUP_T_HDDAT_FAST (5)
#define SETUP_T_SCL_RATIO_FAST (0x1)
#define SETUP_T_SCLHI_FAST (18)
#define SETUP_T_SUDAT_FAST_P (0x0)
#define SETUP_T_SP_FAST_P (0x1)
#define SETUP_T_HDDAT_FAST_P (0x0)
#define SETUP_T_SCL_RATIO_FAST_P (0x1)
#define SETUP_T_SCLHI_FAST_P (6)
#elif CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 40000000
#define SETUP_T_SUDAT_STD (0x4)
#define SETUP_T_SP_STD (0x2)
#define SETUP_T_HDDAT_STD (0x6)
#define SETUP_T_SCL_RATIO_STD (0x0)
#define SETUP_T_SCLHI_STD (182)
#define SETUP_T_SUDAT_FAST (0x0)
#define SETUP_T_SP_FAST (0x2)
#define SETUP_T_HDDAT_FAST (0x6)
#define SETUP_T_SCL_RATIO_FAST (0x1)
#define SETUP_T_SCLHI_FAST (23)
#define SETUP_T_SUDAT_FAST_P (0x0)
#define SETUP_T_SP_FAST_P (0x2)
#define SETUP_T_HDDAT_FAST_P (0x0)
#define SETUP_T_SCL_RATIO_FAST_P (0x1)
#define SETUP_T_SCLHI_FAST_P (7)
#else
#define SETUP_T_SUDAT_STD (0x9)
#define SETUP_T_SP_STD (0x3)
#define SETUP_T_HDDAT_STD (12)
#define SETUP_T_SCL_RATIO_STD (0x0)
#define SETUP_T_SCLHI_STD (287)
#define SETUP_T_SUDAT_FAST (0x0)
#define SETUP_T_SP_FAST (0x3)
#define SETUP_T_HDDAT_FAST (12)
#define SETUP_T_SCL_RATIO_FAST (0x1)
#define SETUP_T_SCLHI_FAST (38)
#define SETUP_T_SUDAT_FAST_P (0x0)
#define SETUP_T_SP_FAST_P (0x3)
#define SETUP_T_HDDAT_FAST_P (0x0)
#define SETUP_T_SCL_RATIO_FAST_P (0x1)
#define SETUP_T_SCLHI_FAST_P (13)
#endif
#define SETUP_SPEED_MSK (SETUP_T_SUDAT | \
SETUP_T_SP | \
SETUP_T_HDDAT | \
SETUP_T_SCL_RATIO | \
SETUP_T_SCLHI)
#define SETUP_SPEED_STD ((SETUP_T_SUDAT_STD << 24) | \
(SETUP_T_SP_STD << 21) | \
(SETUP_T_HDDAT_STD << 16) | \
(SETUP_T_SCL_RATIO_STD << 13) | \
(SETUP_T_SCLHI_STD << 4))
#define SETUP_SPEED_FAST ((SETUP_T_SUDAT_FAST << 24) | \
(SETUP_T_SP_FAST << 21) | \
(SETUP_T_HDDAT_FAST << 16) | \
(SETUP_T_SCL_RATIO_FAST << 13) | \
(SETUP_T_SCLHI_FAST << 4))
#define SETUP_SPEED_FAST_PLUS ((SETUP_T_SUDAT_FAST_P << 24) | \
(SETUP_T_SP_FAST_P << 21) | \
(SETUP_T_HDDAT_FAST_P << 16) | \
(SETUP_T_SCL_RATIO_FAST_P << 13)| \
(SETUP_T_SCLHI_FAST_P << 4))
#define MAX_XFER_SZ (256)
enum _i2c_ctrl_reg_item_dir {
I2C_CONTROLLER_TX = 0x0,
I2C_CONTROLLER_RX = 0x1,
I2C_TARGET_TX = 0x1,
I2C_TARGET_RX = 0x0,
};
/* I2C driver running state */
enum _i2c_driver_state {
I2C_DRV_NONE = 0x0,
I2C_DRV_INIT = BIT(0),
I2C_DRV_POWER = BIT(1),
I2C_DRV_CFG_PARAM = BIT(2),
I2C_DRV_CONTROLLER_TX = BIT(3),
I2C_DRV_CONTROLLER_RX = BIT(4),
I2C_DRV_TARGET_TX = BIT(5),
I2C_DRV_TARGET_RX = BIT(6),
I2C_DRV_CONTROLLER_TX_CMPL = BIT(7),
I2C_DRV_CONTROLLER_RX_CMPL = BIT(8),
I2C_DRV_TARGET_TX_CMPL = BIT(9),
I2C_DRV_TARGET_RX_CMPL = BIT(10),
};
/* brief I2C Status */
struct _i2c_status {
/* /< Mode: 0=Slave, 1=Master */
uint32_t mode:1;
uint32_t general_call: 1;
uint32_t arbitration_lost : 1;
uint32_t target_ack : 1;
};
struct i2c_atciic100_dev_data_t {
struct k_sem bus_lock;
struct k_sem device_sync_sem;
volatile uint32_t driver_state;
uint8_t *middleware_rx_buf;
uint8_t *middleware_tx_buf;
uint32_t fifo_depth;
uint32_t target_addr;
uint32_t xfer_wt_num;
uint32_t xfer_rd_num;
uint32_t xfered_data_wt_ptr; /* write pointer */
uint32_t xfered_data_rd_ptr; /* read pointer */
volatile struct _i2c_status status;
const struct i2c_target_callbacks *target_callbacks;
struct i2c_target_config *target_config;
};
``` | /content/code_sandbox/drivers/i2c/i2c_andes_atciic100.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,280 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <em_cmu.h>
#include <em_i2c.h>
#include <em_gpio.h>
#include <soc.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_gecko);
#include "i2c-priv.h"
#define DEV_BASE(dev) ((I2C_TypeDef *)((const struct i2c_gecko_config *const)(dev)->config)->base)
struct i2c_gecko_config {
const struct pinctrl_dev_config *pcfg;
I2C_TypeDef *base;
CMU_Clock_TypeDef clock;
uint32_t bitrate;
#if defined(CONFIG_I2C_TARGET)
void (*irq_config_func)(const struct device *dev);
#endif
};
struct i2c_gecko_data {
struct k_sem device_sync_sem;
uint32_t dev_config;
#if defined(CONFIG_I2C_TARGET)
struct i2c_target_config *target_cfg;
#endif
};
static int i2c_gecko_configure(const struct device *dev, uint32_t dev_config_raw)
{
I2C_TypeDef *base = DEV_BASE(dev);
struct i2c_gecko_data *data = dev->data;
I2C_Init_TypeDef i2cInit = I2C_INIT_DEFAULT;
uint32_t baudrate;
if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
data->dev_config = dev_config_raw;
i2cInit.freq = baudrate;
#if defined(CONFIG_I2C_TARGET)
i2cInit.master = 0;
#endif
I2C_Init(base, &i2cInit);
return 0;
}
static int i2c_gecko_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
I2C_TypeDef *base = DEV_BASE(dev);
struct i2c_gecko_data *data = dev->data;
I2C_TransferSeq_TypeDef seq;
I2C_TransferReturn_TypeDef ret = -EIO;
uint32_t timeout = 300000U;
if (!num_msgs) {
return 0;
}
seq.addr = addr << 1;
do {
seq.buf[0].data = msgs->buf;
seq.buf[0].len = msgs->len;
if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
seq.flags = I2C_FLAG_READ;
} else {
seq.flags = I2C_FLAG_WRITE;
if (num_msgs > 1) {
/* Next message */
msgs++;
num_msgs--;
if ((msgs->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
seq.flags = I2C_FLAG_WRITE_READ;
} else {
seq.flags = I2C_FLAG_WRITE_WRITE;
}
seq.buf[1].data = msgs->buf;
seq.buf[1].len = msgs->len;
}
}
if (data->dev_config & I2C_ADDR_10_BITS) {
seq.flags |= I2C_FLAG_10BIT_ADDR;
}
/* Do a polled transfer */
ret = I2C_TransferInit(base, &seq);
while (ret == i2cTransferInProgress && timeout--) {
ret = I2C_Transfer(base);
}
if (ret != i2cTransferDone) {
goto finish;
}
/* Next message */
msgs++;
num_msgs--;
} while (num_msgs);
finish:
if (ret != i2cTransferDone) {
ret = -EIO;
}
return ret;
}
static int i2c_gecko_init(const struct device *dev)
{
const struct i2c_gecko_config *config = dev->config;
uint32_t bitrate_cfg;
int error;
CMU_ClockEnable(config->clock, true);
error = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (error < 0) {
LOG_ERR("Failed to configure I2C pins err[%d]", error);
return error;
}
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
error = i2c_gecko_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (error) {
return error;
}
return 0;
}
#if defined(CONFIG_I2C_TARGET)
static int i2c_gecko_target_register(const struct device *dev, struct i2c_target_config *cfg)
{
const struct i2c_gecko_config *config = dev->config;
struct i2c_gecko_data *data = dev->data;
data->target_cfg = cfg;
I2C_SlaveAddressSet(config->base, cfg->address << _I2C_SADDR_ADDR_SHIFT);
/* Match with specified address, no wildcards in address */
I2C_SlaveAddressMaskSet(config->base, _I2C_SADDRMASK_SADDRMASK_MASK);
I2C_IntDisable(config->base, _I2C_IEN_MASK);
I2C_IntEnable(config->base, I2C_IEN_ADDR | I2C_IEN_RXDATAV | I2C_IEN_ACK | I2C_IEN_SSTOP |
I2C_IEN_BUSERR | I2C_IEN_ARBLOST);
config->irq_config_func(dev);
return 0;
}
static int i2c_gecko_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
{
const struct i2c_gecko_config *config = dev->config;
struct i2c_gecko_data *data = dev->data;
data->target_cfg = NULL;
I2C_IntDisable(config->base, _I2C_IEN_MASK);
return 0;
}
#endif
static const struct i2c_driver_api i2c_gecko_driver_api = {
.configure = i2c_gecko_configure,
.transfer = i2c_gecko_transfer,
#if defined(CONFIG_I2C_TARGET)
.target_register = i2c_gecko_target_register,
.target_unregister = i2c_gecko_target_unregister,
#endif
};
#if defined(CONFIG_I2C_TARGET)
void i2c_gecko_isr(const struct device *dev)
{
const struct i2c_gecko_config *config = dev->config;
struct i2c_gecko_data *data = dev->data;
uint32_t pending;
uint32_t rx_byte;
uint8_t tx_byte;
pending = config->base->IF;
/* If some sort of fault, abort transfer. */
if (pending & (I2C_IF_BUSERR | I2C_IF_ARBLOST)) {
LOG_ERR("I2C Bus Error");
I2C_IntClear(config->base, I2C_IF_BUSERR);
I2C_IntClear(config->base, I2C_IF_ARBLOST);
} else {
if (pending & I2C_IF_ADDR) {
/* Address Match, indicating that reception is started */
rx_byte = config->base->RXDATA;
config->base->CMD = I2C_CMD_ACK;
/* Check if read bit set */
if (rx_byte & 0x1) {
data->target_cfg->callbacks->read_requested(data->target_cfg,
&tx_byte);
config->base->TXDATA = tx_byte;
} else {
data->target_cfg->callbacks->write_requested(data->target_cfg);
}
I2C_IntClear(config->base, I2C_IF_ADDR | I2C_IF_RXDATAV);
} else if (pending & I2C_IF_RXDATAV) {
rx_byte = config->base->RXDATA;
/* Read new data and write to target address */
data->target_cfg->callbacks->write_received(data->target_cfg, rx_byte);
config->base->CMD = I2C_CMD_ACK;
I2C_IntClear(config->base, I2C_IF_RXDATAV);
}
if (pending & I2C_IF_ACK) {
/* Leader ACK'ed, so requesting more data */
data->target_cfg->callbacks->read_processed(data->target_cfg, &tx_byte);
config->base->TXDATA = tx_byte;
I2C_IntClear(config->base, I2C_IF_ACK);
}
if (pending & I2C_IF_SSTOP) {
/* End of transaction */
data->target_cfg->callbacks->stop(data->target_cfg);
I2C_IntClear(config->base, I2C_IF_SSTOP);
}
}
}
#endif
#if defined(CONFIG_I2C_TARGET)
#define GECKO_I2C_IRQ_DEF(idx) static void i2c_gecko_config_func_##idx(const struct device *dev);
#define GECKO_I2C_IRQ_DATA(idx) .irq_config_func = i2c_gecko_config_func_##idx,
#define GECKO_I2C_IRQ_HANDLER(idx) \
static void i2c_gecko_config_func_##idx(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQ(idx, irq), DT_INST_IRQ(idx, priority), i2c_gecko_isr, \
DEVICE_DT_INST_GET(idx), 0); \
irq_enable(DT_INST_IRQ(idx, irq)); \
}
#else
#define GECKO_I2C_IRQ_HANDLER(idx)
#define GECKO_I2C_IRQ_DEF(idx)
#define GECKO_I2C_IRQ_DATA(idx)
#endif
#define I2C_INIT(idx) \
PINCTRL_DT_INST_DEFINE(idx); \
GECKO_I2C_IRQ_DEF(idx); \
\
static const struct i2c_gecko_config i2c_gecko_config_##idx = { \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
.base = (I2C_TypeDef *)DT_INST_REG_ADDR(idx), \
.clock = cmuClock_I2C##idx, \
.bitrate = DT_INST_PROP(idx, clock_frequency), \
GECKO_I2C_IRQ_DATA(idx)}; \
\
static struct i2c_gecko_data i2c_gecko_data_##idx; \
\
I2C_DEVICE_DT_INST_DEFINE(idx, i2c_gecko_init, NULL, &i2c_gecko_data_##idx, \
&i2c_gecko_config_##idx, POST_KERNEL, \
CONFIG_I2C_INIT_PRIORITY, &i2c_gecko_driver_api); \
\
GECKO_I2C_IRQ_HANDLER(idx)
DT_INST_FOREACH_STATUS_OKAY(I2C_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,434 |
```c
/*
*
*/
#define DT_DRV_COMPAT gpio_i2c
/**
* @file
* @brief Driver for software driven I2C using GPIO lines
*
* This driver implements an I2C interface by driving two GPIO lines under
* software control.
*
* The GPIO pins used must be configured (through devicetree and pinmux) with
* suitable flags, i.e. the SDA pin as open-collector/open-drain with a pull-up
* resistor (possibly as an external component attached to the pin).
*
* When the SDA pin is read it must return the state of the physical hardware
* line, not just the last state written to it for output.
*
* The SCL pin should be configured in the same manner as SDA, or, if it is
* known that the hardware attached to pin doesn't attempt clock stretching,
* then the SCL pin may be a push/pull output.
*/
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_gpio);
#include "i2c-priv.h"
#include "i2c_bitbang.h"
/* Driver config */
struct i2c_gpio_config {
struct gpio_dt_spec scl_gpio;
struct gpio_dt_spec sda_gpio;
uint32_t bitrate;
};
/* Driver instance data */
struct i2c_gpio_context {
struct i2c_bitbang bitbang; /* Bit-bang library data */
struct k_mutex mutex;
};
static void i2c_gpio_set_scl(void *io_context, int state)
{
const struct i2c_gpio_config *config = io_context;
gpio_pin_set_dt(&config->scl_gpio, state);
}
static void i2c_gpio_set_sda(void *io_context, int state)
{
const struct i2c_gpio_config *config = io_context;
gpio_pin_set_dt(&config->sda_gpio, state);
}
static int i2c_gpio_get_sda(void *io_context)
{
const struct i2c_gpio_config *config = io_context;
int rc = gpio_pin_get_dt(&config->sda_gpio);
/* Default high as that would be a NACK */
return rc != 0;
}
static const struct i2c_bitbang_io io_fns = {
.set_scl = &i2c_gpio_set_scl,
.set_sda = &i2c_gpio_set_sda,
.get_sda = &i2c_gpio_get_sda,
};
static int i2c_gpio_configure(const struct device *dev, uint32_t dev_config)
{
struct i2c_gpio_context *context = dev->data;
int rc;
k_mutex_lock(&context->mutex, K_FOREVER);
rc = i2c_bitbang_configure(&context->bitbang, dev_config);
k_mutex_unlock(&context->mutex);
return rc;
}
static int i2c_gpio_get_config(const struct device *dev, uint32_t *config)
{
struct i2c_gpio_context *context = dev->data;
int rc;
k_mutex_lock(&context->mutex, K_FOREVER);
rc = i2c_bitbang_get_config(&context->bitbang, config);
if (rc < 0) {
LOG_ERR("I2C controller not configured: %d", rc);
}
k_mutex_unlock(&context->mutex);
return rc;
}
static int i2c_gpio_transfer(const struct device *dev, struct i2c_msg *msgs,
uint8_t num_msgs, uint16_t slave_address)
{
struct i2c_gpio_context *context = dev->data;
int rc;
k_mutex_lock(&context->mutex, K_FOREVER);
rc = i2c_bitbang_transfer(&context->bitbang, msgs, num_msgs,
slave_address);
k_mutex_unlock(&context->mutex);
return rc;
}
static int i2c_gpio_recover_bus(const struct device *dev)
{
struct i2c_gpio_context *context = dev->data;
int rc;
k_mutex_lock(&context->mutex, K_FOREVER);
rc = i2c_bitbang_recover_bus(&context->bitbang);
k_mutex_unlock(&context->mutex);
return rc;
}
static const struct i2c_driver_api api = {
.configure = i2c_gpio_configure,
.get_config = i2c_gpio_get_config,
.transfer = i2c_gpio_transfer,
.recover_bus = i2c_gpio_recover_bus,
};
static int i2c_gpio_init(const struct device *dev)
{
struct i2c_gpio_context *context = dev->data;
const struct i2c_gpio_config *config = dev->config;
uint32_t bitrate_cfg;
int err;
if (!gpio_is_ready_dt(&config->scl_gpio)) {
LOG_ERR("SCL GPIO device not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->scl_gpio, GPIO_OUTPUT_HIGH);
if (err) {
LOG_ERR("failed to configure SCL GPIO pin (err %d)", err);
return err;
}
if (!gpio_is_ready_dt(&config->sda_gpio)) {
LOG_ERR("SDA GPIO device not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->sda_gpio,
GPIO_INPUT | GPIO_OUTPUT_HIGH);
if (err == -ENOTSUP) {
err = gpio_pin_configure_dt(&config->sda_gpio,
GPIO_OUTPUT_HIGH);
}
if (err) {
LOG_ERR("failed to configure SDA GPIO pin (err %d)", err);
return err;
}
i2c_bitbang_init(&context->bitbang, &io_fns, (void *)config);
bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
err = i2c_bitbang_configure(&context->bitbang,
I2C_MODE_CONTROLLER | bitrate_cfg);
if (err) {
LOG_ERR("failed to configure I2C bitbang (err %d)", err);
return err;
}
err = k_mutex_init(&context->mutex);
if (err) {
LOG_ERR("Failed to create the i2c lock mutex : %d", err);
return err;
}
return 0;
}
#define DEFINE_I2C_GPIO(_num) \
\
static struct i2c_gpio_context i2c_gpio_dev_data_##_num; \
\
static const struct i2c_gpio_config i2c_gpio_dev_cfg_##_num = { \
.scl_gpio = GPIO_DT_SPEC_INST_GET(_num, scl_gpios), \
.sda_gpio = GPIO_DT_SPEC_INST_GET(_num, sda_gpios), \
.bitrate = DT_INST_PROP(_num, clock_frequency), \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(_num, \
i2c_gpio_init, \
NULL, \
&i2c_gpio_dev_data_##_num, \
&i2c_gpio_dev_cfg_##_num, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &api);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_GPIO)
``` | /content/code_sandbox/drivers/i2c/i2c_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,535 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_i2c_twihs
/** @file
* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
*
* Only I2C Controller Mode with 7 bit addressing is currently supported.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/rtio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(i2c_sam_twihs_rtio);
#include "i2c-priv.h"
/** I2C bus speed [Hz] in Standard Mode */
#define BUS_SPEED_STANDARD_HZ 100000U
/** I2C bus speed [Hz] in Fast Mode */
#define BUS_SPEED_FAST_HZ 400000U
/** I2C bus speed [Hz] in High Speed Mode */
#define BUS_SPEED_HIGH_HZ 3400000U
/* Maximum value of Clock Divider (CKDIV) */
#define CKDIV_MAX 7
/* Device constant configuration parameters */
struct i2c_sam_twihs_dev_cfg {
Twihs *regs;
void (*irq_config)(void);
uint32_t bitrate;
const struct atmel_sam_pmc_config clock_cfg;
const struct pinctrl_dev_config *pcfg;
uint8_t irq_id;
};
/* Device run time data */
struct i2c_sam_twihs_dev_data {
struct i2c_rtio *ctx;
uint32_t buf_idx;
};
static int i2c_clk_set(Twihs *const twihs, uint32_t speed)
{
uint32_t ck_div = 0U;
uint32_t cl_div;
bool div_completed = false;
/* From the datasheet "TWIHS Clock Waveform Generator Register"
* T_low = ( ( CLDIV 2^CKDIV ) + 3 ) T_MCK
*/
while (!div_completed) {
cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3)
/ (1 << ck_div);
if (cl_div <= 255U) {
div_completed = true;
} else {
ck_div++;
}
}
if (ck_div > CKDIV_MAX) {
LOG_ERR("Failed to configure I2C clock");
return -EIO;
}
/* Set I2C bus clock duty cycle to 50% */
twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div)
| TWIHS_CWGR_CKDIV(ck_div);
return 0;
}
static int i2c_sam_twihs_configure(const struct device *dev, uint32_t config)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
Twihs *const twihs = dev_cfg->regs;
uint32_t bitrate;
int ret;
if (!(config & I2C_MODE_CONTROLLER)) {
LOG_ERR("Master Mode is not enabled");
return -EIO;
}
if (config & I2C_ADDR_10_BITS) {
LOG_ERR("I2C 10-bit addressing is currently not supported");
LOG_ERR("Please submit a patch");
return -EIO;
}
/* Configure clock */
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
bitrate = BUS_SPEED_STANDARD_HZ;
break;
case I2C_SPEED_FAST:
bitrate = BUS_SPEED_FAST_HZ;
break;
default:
LOG_ERR("Unsupported I2C speed value");
return -EIO;
}
/* Setup clock waveform */
ret = i2c_clk_set(twihs, bitrate);
if (ret < 0) {
return ret;
}
/* Disable Target Mode */
twihs->TWIHS_CR = TWIHS_CR_SVDIS;
/* Enable Controller Mode */
twihs->TWIHS_CR = TWIHS_CR_MSEN;
return 0;
}
static void write_msg_start(Twihs *const twihs, const uint8_t *buf, const uint32_t idx,
const uint8_t daddr)
{
/* Set target address. */
twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
/* Write first data byte on I2C bus */
twihs->TWIHS_THR = buf[idx];
/* Enable Transmit Ready and Transmission Completed interrupts */
twihs->TWIHS_IER = TWIHS_IER_TXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
}
static void read_msg_start(Twihs *const twihs, const uint32_t len, const uint8_t daddr)
{
uint32_t twihs_cr_stop;
/* Set target address and number of internal address bytes */
twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
/* In single data byte read the START and STOP must both be set */
twihs_cr_stop = (len == 1U) ? TWIHS_CR_STOP : 0;
/* Enable Receive Ready and Transmission Completed interrupts */
twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
/* Start the transfer by sending START condition */
twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
}
static void i2c_sam_twihs_complete(const struct device *dev, int status);
static void i2c_sam_twihs_start(const struct device *dev)
{
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
Twihs *const twihs = dev_cfg->regs;
struct rtio_sqe *sqe = &dev_data->ctx->txn_curr->sqe;
struct i2c_dt_spec *dt_spec = sqe->iodev->data;
/* Clear pending interrupts, such as NACK. */
(void)twihs->TWIHS_SR;
/* Set number of internal address bytes to 0, not used. */
twihs->TWIHS_IADR = 0;
/* Set the current index to 0 */
dev_data->buf_idx = 0;
switch (sqe->op) {
case RTIO_OP_RX:
read_msg_start(twihs, sqe->rx.buf_len, dt_spec->addr);
break;
case RTIO_OP_TX:
dev_data->buf_idx = 1;
write_msg_start(twihs, sqe->tx.buf, 0, dt_spec->addr);
break;
default:
LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
i2c_sam_twihs_complete(dev, -EINVAL);
}
}
static void i2c_sam_twihs_complete(const struct device *dev, int status)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
Twihs *const twihs = dev_cfg->regs;
struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *)
dev->data)->ctx;
/* Disable all enabled interrupts */
twihs->TWIHS_IDR = twihs->TWIHS_IMR;
if (i2c_rtio_complete(ctx, status)) {
i2c_sam_twihs_start(dev);
}
}
static void i2c_sam_twihs_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
{
struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *)
dev->data)->ctx;
if (i2c_rtio_submit(ctx, iodev_sqe)) {
i2c_sam_twihs_start(dev);
}
}
static void i2c_sam_twihs_isr(const struct device *dev)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
Twihs *const twihs = dev_cfg->regs;
struct rtio_sqe *sqe = &dev_data->ctx->txn_curr->sqe;
uint32_t isr_status;
/* Retrieve interrupt status */
isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;
/* Not Acknowledged */
if (isr_status & TWIHS_SR_NACK) {
i2c_sam_twihs_complete(dev, -EIO);
return;
}
/* Byte received */
if (isr_status & TWIHS_SR_RXRDY) {
sqe->rx.buf[dev_data->buf_idx] = twihs->TWIHS_RHR;
dev_data->buf_idx += 1;
if (dev_data->buf_idx == sqe->rx.buf_len - 1U) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
}
}
/* Byte sent */
if (isr_status & TWIHS_SR_TXRDY) {
if (dev_data->buf_idx == sqe->tx.buf_len) {
if (sqe->iodev_flags & RTIO_IODEV_I2C_STOP) {
/* Send STOP condition */
twihs->TWIHS_CR = TWIHS_CR_STOP;
/* Disable Transmit Ready interrupt */
twihs->TWIHS_IDR = TWIHS_IDR_TXRDY;
} else {
/* Transmission completed */
i2c_sam_twihs_complete(dev, 0);
return;
}
} else {
twihs->TWIHS_THR = sqe->tx.buf[dev_data->buf_idx++];
}
}
/* Transmission completed */
if (isr_status & TWIHS_SR_TXCOMP) {
i2c_sam_twihs_complete(dev, 0);
}
}
static int i2c_sam_twihs_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
uint16_t addr)
{
struct i2c_rtio *const ctx = ((struct i2c_sam_twihs_dev_data *)
dev->data)->ctx;
return i2c_rtio_transfer(ctx, msgs, num_msgs, addr);
}
static int i2c_sam_twihs_initialize(const struct device *dev)
{
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
Twihs *const twihs = dev_cfg->regs;
uint32_t bitrate_cfg;
int ret;
/* Configure interrupts */
dev_cfg->irq_config();
/* Connect pins to the peripheral */
ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Enable TWIHS clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
/* Reset the module */
twihs->TWIHS_CR = TWIHS_CR_SWRST;
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
ret = i2c_sam_twihs_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
if (ret < 0) {
LOG_ERR("Failed to initialize %s device", dev->name);
return ret;
}
i2c_rtio_init(dev_data->ctx, dev);
/* Enable module's IRQ */
irq_enable(dev_cfg->irq_id);
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct i2c_driver_api i2c_sam_twihs_driver_api = {
.configure = i2c_sam_twihs_configure,
.transfer = i2c_sam_twihs_transfer,
.iodev_submit = i2c_sam_twihs_submit,
};
#define I2C_TWIHS_SAM_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static void i2c##n##_sam_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
i2c_sam_twihs_isr, \
DEVICE_DT_INST_GET(n), 0); \
} \
\
I2C_RTIO_DEFINE(_i2c##n##_sam_rtio, \
DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \
DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \
\
static const struct i2c_sam_twihs_dev_cfg i2c##n##_sam_config = { \
.regs = (Twihs *)DT_INST_REG_ADDR(n), \
.irq_config = i2c##n##_sam_irq_config, \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
.irq_id = DT_INST_IRQN(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.bitrate = DT_INST_PROP(n, clock_frequency), \
}; \
\
static struct i2c_sam_twihs_dev_data i2c##n##_sam_data = { \
.ctx = &_i2c##n##_sam_rtio, \
}; \
\
I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twihs_initialize, \
NULL, \
&i2c##n##_sam_data, &i2c##n##_sam_config, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&i2c_sam_twihs_driver_api);
DT_INST_FOREACH_STATUS_OKAY(I2C_TWIHS_SAM_INIT)
``` | /content/code_sandbox/drivers/i2c/i2c_sam_twihs_rtio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,252 |
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