text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#define DT_DRV_COMPAT litex_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/types.h>
#include <zephyr/sys/util.h>
#include <string.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define SUPPORTED_FLAGS (GPIO_INPUT | GPIO_OUTPUT | \
GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \
GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH)
#define GPIO_LOW 0
#define GPIO_HIGH 1
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
LOG_MODULE_REGISTER(gpio_litex);
static const char *LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH =
"Cannot handle all of the gpios with the register of given size\n";
static const char *LITEX_LOG_CANNOT_CHANGE_DIR =
"Cannot change port direction selected in device tree\n";
struct gpio_litex_cfg {
uint32_t reg_addr;
int reg_size;
uint32_t ev_pending_addr;
uint32_t ev_enable_addr;
uint32_t ev_mode_addr;
uint32_t ev_edge_addr;
int nr_gpios;
bool port_is_output;
};
struct gpio_litex_data {
struct gpio_driver_data common;
const struct device *dev;
sys_slist_t cb;
};
/* Helper macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct gpio_litex_cfg *)(dev)->config)
/* Helper functions for bit / port access */
static inline void set_bit(const struct gpio_litex_cfg *config,
uint32_t bit, bool val)
{
int regv, new_regv;
regv = litex_read(config->reg_addr, config->reg_size);
new_regv = (regv & ~BIT(bit)) | (val << bit);
litex_write(config->reg_addr, config->reg_size, new_regv);
}
static inline uint32_t get_bit(const struct gpio_litex_cfg *config, uint32_t bit)
{
int regv = litex_read(config->reg_addr, config->reg_size);
return !!(regv & BIT(bit));
}
static inline void set_port(const struct gpio_litex_cfg *config, uint32_t value)
{
litex_write(config->reg_addr, config->reg_size, value);
}
static inline uint32_t get_port(const struct gpio_litex_cfg *config)
{
int regv = litex_read(config->reg_addr, config->reg_size);
return (regv & BIT_MASK(config->nr_gpios));
}
/* Driver functions */
static int gpio_litex_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
if (flags & ~SUPPORTED_FLAGS) {
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
/* Pin cannot be configured as input and output */
return -ENOTSUP;
} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
/* Pin has to be configured as input or output */
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
if (!gpio_config->port_is_output) {
LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR);
return -EINVAL;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
set_bit(gpio_config, pin, GPIO_HIGH);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
set_bit(gpio_config, pin, GPIO_LOW);
}
} else {
if (gpio_config->port_is_output) {
LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR);
return -EINVAL;
}
}
return 0;
}
static int gpio_litex_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
*value = get_port(gpio_config);
return 0;
}
static int gpio_litex_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
uint32_t port_val;
port_val = get_port(gpio_config);
port_val = (port_val & ~mask) | (value & mask);
set_port(gpio_config, port_val);
return 0;
}
static int gpio_litex_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
uint32_t port_val;
port_val = get_port(gpio_config);
port_val |= pins;
set_port(gpio_config, port_val);
return 0;
}
static int gpio_litex_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
uint32_t port_val;
port_val = get_port(gpio_config);
port_val &= ~pins;
set_port(gpio_config, port_val);
return 0;
}
static int gpio_litex_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
uint32_t port_val;
port_val = get_port(gpio_config);
port_val ^= pins;
set_port(gpio_config, port_val);
return 0;
}
static void gpio_litex_irq_handler(const struct device *dev)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
struct gpio_litex_data *data = dev->data;
uint8_t int_status =
litex_read(gpio_config->ev_pending_addr, gpio_config->reg_size);
uint8_t ev_enabled =
litex_read(gpio_config->ev_enable_addr, gpio_config->reg_size);
/* clear events */
litex_write(gpio_config->ev_pending_addr, gpio_config->reg_size,
int_status);
gpio_fire_callbacks(&data->cb, dev, int_status & ev_enabled);
}
static int gpio_litex_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_litex_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static int gpio_litex_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
if (gpio_config->port_is_output == true) {
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_EDGE) {
uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr,
gpio_config->reg_size);
uint8_t ev_mode = litex_read(gpio_config->ev_mode_addr,
gpio_config->reg_size);
uint8_t ev_edge = litex_read(gpio_config->ev_edge_addr,
gpio_config->reg_size);
litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size,
ev_enabled | BIT(pin));
if (trig == GPIO_INT_TRIG_HIGH) {
/* Change mode to 'edge' and edge to 'rising' */
litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size,
ev_mode & ~BIT(pin));
litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size,
ev_edge & ~BIT(pin));
} else if (trig == GPIO_INT_TRIG_LOW) {
/* Change mode to 'edge' and edge to 'falling' */
litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size,
ev_mode & ~BIT(pin));
litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size,
ev_edge | BIT(pin));
} else if (trig == GPIO_INT_TRIG_BOTH) {
/* Change mode to 'change' */
litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size,
ev_mode | BIT(pin));
}
return 0;
}
if (mode == GPIO_INT_DISABLE) {
uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr,
gpio_config->reg_size);
litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size,
ev_enabled & ~BIT(pin));
return 0;
}
return -ENOTSUP;
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_litex_port_get_direction(const struct device *dev, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
map &= gpio_config->port_pin_mask;
if (inputs != NULL) {
*inputs = map & (!gpio_config->port_is_output);
}
if (outputs != NULL) {
*outputs = map & (gpio_config->port_is_output);
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_litex_driver_api = {
.pin_configure = gpio_litex_configure,
.port_get_raw = gpio_litex_port_get_raw,
.port_set_masked_raw = gpio_litex_port_set_masked_raw,
.port_set_bits_raw = gpio_litex_port_set_bits_raw,
.port_clear_bits_raw = gpio_litex_port_clear_bits_raw,
.port_toggle_bits = gpio_litex_port_toggle_bits,
.pin_interrupt_configure = gpio_litex_pin_interrupt_configure,
.manage_callback = gpio_litex_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_litex_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
/* Device Instantiation */
#define GPIO_LITEX_IRQ_INIT(n) \
do { \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
gpio_litex_irq_handler, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
} while (false)
#define GPIO_LITEX_INIT(n) \
static int gpio_litex_port_init_##n(const struct device *dev); \
\
static const struct gpio_litex_cfg gpio_litex_cfg_##n = { \
.reg_addr = DT_INST_REG_ADDR(n), \
.reg_size = DT_INST_REG_SIZE(n), \
.nr_gpios = DT_INST_PROP(n, ngpios), \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), ( \
.ev_mode_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_mode), \
.ev_edge_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_edge), \
.ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_pend), \
.ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_en), \
)) \
.port_is_output = DT_INST_PROP(n, port_is_output), \
}; \
static struct gpio_litex_data gpio_litex_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_litex_port_init_##n, \
NULL, \
&gpio_litex_data_##n, \
&gpio_litex_cfg_##n, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_litex_driver_api \
); \
\
static int gpio_litex_port_init_##n(const struct device *dev) \
{ \
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); \
\
/* Check if gpios fit in declared register space */ \
/* Number of subregisters times size in bits */ \
const int max_gpios_can_fit = DT_INST_REG_SIZE(n) / 4 \
* CONFIG_LITEX_CSR_DATA_WIDTH; \
if (gpio_config->nr_gpios > max_gpios_can_fit) { \
LOG_ERR("%s", LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH); \
return -EINVAL; \
} \
\
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
(GPIO_LITEX_IRQ_INIT(n);)) \
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_LITEX_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,660 |
```unknown
# PCA95XX GPIO configuration options
menuconfig GPIO_PCA95XX
bool "PCA95XX I2C-based GPIO chip"
default y
depends on DT_HAS_NXP_PCA95XX_ENABLED
depends on I2C
help
Enable driver for PCA95XX I2C-based GPIO chip.
config GPIO_PCA95XX_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_PCA95XX
help
Device driver initialization priority.
config GPIO_PCA95XX_INTERRUPT
bool "Interrupt enable"
depends on GPIO_PCA95XX
help
Enable interrupt support in PCA95XX driver.
Note that the PCA95XX cannot reliably detect
short-pulse interrupts due to its design.
``` | /content/code_sandbox/drivers/gpio/Kconfig.pca95xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 158 |
```unknown
# Litex VexRiscV GPIO configuration options
config GPIO_LITEX
bool "Litex GPIO driver"
default y
depends on DT_HAS_LITEX_GPIO_ENABLED
help
Enable Litex GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```c
/*
*
*/
/**
* @file
* @brief GPIO driver for the ADS114S0x AFE.
*/
#define DT_DRV_COMPAT ti_ads114s0x_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_ads114s0x);
#include <zephyr/drivers/adc/ads114s0x.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_ads114s0x_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *parent;
};
struct gpio_ads114s0x_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
};
static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_ads114s0x_config *config = dev->config;
int err = 0;
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
return ads114s0x_gpio_deconfigure(config->parent, pin);
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if (flags & GPIO_INT_ENABLE) {
/* ads114s0x GPIOs do not support interrupts */
return -ENOTSUP;
}
switch (flags & GPIO_DIR_MASK) {
case GPIO_INPUT:
err = ads114s0x_gpio_set_input(config->parent, pin);
break;
case GPIO_OUTPUT:
err = ads114s0x_gpio_set_output(config->parent, pin,
(flags & GPIO_OUTPUT_INIT_HIGH) != 0);
break;
default:
return -ENOTSUP;
}
return err;
}
static int gpio_ads114s0x_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct gpio_ads114s0x_config *config = dev->config;
return ads114s0x_gpio_port_get_raw(config->parent, value);
}
static int gpio_ads114s0x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_ads114s0x_config *config = dev->config;
return ads114s0x_gpio_port_set_masked_raw(config->parent, mask, value);
}
static int gpio_ads114s0x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ads114s0x_config *config = dev->config;
return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, pins);
}
static int gpio_ads114s0x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ads114s0x_config *config = dev->config;
return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, 0);
}
static int gpio_ads114s0x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ads114s0x_config *config = dev->config;
return ads114s0x_gpio_port_toggle_bits(config->parent, pins);
}
static int gpio_ads114s0x_init(const struct device *dev)
{
const struct gpio_ads114s0x_config *config = dev->config;
if (!device_is_ready(config->parent)) {
LOG_ERR("parent ads114s0x device '%s' not ready", config->parent->name);
return -EINVAL;
}
return 0;
}
static const struct gpio_driver_api gpio_ads114s0x_api = {
.pin_configure = gpio_ads114s0x_config,
.port_set_masked_raw = gpio_ads114s0x_port_set_masked_raw,
.port_set_bits_raw = gpio_ads114s0x_port_set_bits_raw,
.port_clear_bits_raw = gpio_ads114s0x_port_clear_bits_raw,
.port_toggle_bits = gpio_ads114s0x_port_toggle_bits,
.port_get_raw = gpio_ads114s0x_port_get_raw,
};
BUILD_ASSERT(CONFIG_GPIO_ADS114S0X_INIT_PRIORITY > CONFIG_ADC_INIT_PRIORITY,
"ADS114S0X GPIO driver must be initialized after ADS114S0X ADC driver");
#define GPIO_ADS114S0X_DEVICE(id) \
static const struct gpio_ads114s0x_config gpio_ads114s0x_##id##_cfg = { \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id)}, \
.parent = DEVICE_DT_GET(DT_INST_BUS(id)), \
}; \
\
static struct gpio_ads114s0x_data gpio_ads114s0x_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, gpio_ads114s0x_init, NULL, &gpio_ads114s0x_##id##_data, \
&gpio_ads114s0x_##id##_cfg, POST_KERNEL, \
CONFIG_GPIO_ADS114S0X_INIT_PRIORITY, &gpio_ads114s0x_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_ADS114S0X_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_ads114s0x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,145 |
```unknown
config GPIO_IPROC
bool "Broadcom iProc GPIO controller driver"
default y
depends on DT_HAS_BRCM_IPROC_GPIO_ENABLED
help
This option enables the GPIO driver for iProc family
of GPIO controller.
``` | /content/code_sandbox/drivers/gpio/Kconfig.iproc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
config GPIO_NPM6001
bool "nPM6001 GPIO driver"
default y
depends on DT_HAS_NORDIC_NPM6001_GPIO_ENABLED
select I2C
select MFD
help
Enable the nPM6001 GPIO driver.
config GPIO_NPM6001_INIT_PRIORITY
int "nPM6001 GPIO driver initialization priority"
depends on GPIO_NPM6001
default 85
help
Initialization priority for the nPM6001 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.npm6001 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_NCT38XX_H_
#define ZEPHYR_DRIVERS_GPIO_GPIO_NCT38XX_H_
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
/* NCT38XX controller register */
#define NCT38XX_REG_ALERT 0x10
#define NCT38XX_REG_ALERT_MASK 0x12
#define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8))
#define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8))
#define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8))
#define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8))
#define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8))
#define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8))
#define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8))
#define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8))
#define NCT38XX_REG_MUX_CONTROL 0xD0
#define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n))
/* NCT38XX controller register field */
#define NCT38XX_REG_ALERT_VENDOR_DEFINDED_ALERT 15
#define NCT38XX_REG_ALERT_MASK_VENDOR_DEFINDED_ALERT 15
/**
* @brief Dispatch GPIO port ISR
*
* @param dev GPIO port device
* @return 0 if successful, otherwise failed.
*/
int gpio_nct38xx_dispatch_port_isr(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_NCT38XX_H_*/
``` | /content/code_sandbox/drivers/gpio/gpio_nct38xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 430 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_H_
#define ZEPHYR_DRIVERS_GPIO_GPIO_DW_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio.h>
#include "gpio_dw_registers.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*gpio_config_irq_t)(const struct device *port);
struct gpio_dw_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uint32_t ngpios;
uint32_t irq_num; /* set to 0 if GPIO port cannot interrupt */
gpio_config_irq_t config_func;
};
struct gpio_dw_runtime {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
uint32_t base_addr;
sys_slist_t callbacks;
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_DW_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_dw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 187 |
```unknown
# PCF857x GPIO configuration options
menuconfig GPIO_PCF857X
bool "PCF857X I2C GPIO chip"
default y
depends on DT_HAS_NXP_PCF857X_ENABLED
select I2C
help
Enable driver for PCF857X I2C GPIO chip.
config GPIO_PCF857X_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_PCF857X
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.pcf857x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```c
/*
*
*/
#include <SDL.h>
#include "gpio_emul_sdl_bottom.h"
static int sdl_filter_bottom(void *arg, SDL_Event *event)
{
struct gpio_sdl_data *data = arg;
/* Only handle keyboard events */
switch (event->type) {
case SDL_KEYDOWN:
case SDL_KEYUP:
break;
default:
return 1;
}
data->event_scan_code = event->key.keysym.scancode;
data->key_down = event->type == SDL_KEYDOWN;
return data->callback(arg);
}
void gpio_sdl_init_bottom(struct gpio_sdl_data *data)
{
SDL_AddEventWatch(sdl_filter_bottom, (void *)data);
}
``` | /content/code_sandbox/drivers/gpio/gpio_emul_sdl_bottom.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
#include <gpio.h>
#define DT_DRV_COMPAT adi_max32_gpio
LOG_MODULE_REGISTER(gpio_max32, CONFIG_GPIO_LOG_LEVEL);
struct max32_gpio_config {
struct gpio_driver_config common;
mxc_gpio_regs_t *regs;
const struct device *clock;
void (*irq_func)(void);
struct max32_perclk perclk;
};
struct max32_gpio_data {
struct gpio_driver_data common;
sys_slist_t cb_list;
};
static int api_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct max32_gpio_config *cfg = dev->config;
*value = MXC_GPIO_InGet(cfg->regs, (unsigned int)-1);
return 0;
}
static int api_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct max32_gpio_config *cfg = dev->config;
MXC_GPIO_OutPut(cfg->regs, mask, value);
return 0;
}
static int api_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct max32_gpio_config *cfg = dev->config;
MXC_GPIO_OutSet(cfg->regs, pins);
return 0;
}
static int api_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct max32_gpio_config *cfg = dev->config;
MXC_GPIO_OutClr(cfg->regs, pins);
return 0;
}
static int api_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct max32_gpio_config *cfg = dev->config;
MXC_GPIO_OutToggle(cfg->regs, pins);
return 0;
}
static int api_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct max32_gpio_config *cfg = dev->config;
mxc_gpio_cfg_t gpio_cfg;
int ret;
/* MAX32xxx MCUs does not support SINGLE_ENDED, open drain, mode */
if (flags & GPIO_SINGLE_ENDED) {
return -ENOTSUP;
}
gpio_cfg.port = cfg->regs;
gpio_cfg.mask = BIT(pin);
if (flags & GPIO_PULL_UP) {
gpio_cfg.pad = MXC_GPIO_PAD_PULL_UP;
} else if (flags & GPIO_PULL_DOWN) {
gpio_cfg.pad = MXC_GPIO_PAD_PULL_DOWN;
} else if (flags & MAX32_GPIO_WEAK_PULL_UP) {
gpio_cfg.pad = MXC_GPIO_PAD_WEAK_PULL_UP;
} else if (flags & MAX32_GPIO_WEAK_PULL_DOWN) {
gpio_cfg.pad = MXC_GPIO_PAD_WEAK_PULL_DOWN;
} else {
gpio_cfg.pad = MXC_GPIO_PAD_NONE;
}
if (flags & GPIO_OUTPUT) {
gpio_cfg.func = MXC_GPIO_FUNC_OUT;
} else if (flags & GPIO_INPUT) {
gpio_cfg.func = MXC_GPIO_FUNC_IN;
} else {
gpio_cfg.func = MXC_GPIO_FUNC_IN;
gpio_cfg.pad = MXC_GPIO_PAD_NONE;
}
if (flags & MAX32_GPIO_VSEL_VDDIOH) {
gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIOH;
} else {
gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIO;
}
switch (flags & MAX32_GPIO_DRV_STRENGTH_MASK) {
case MAX32_GPIO_DRV_STRENGTH_1:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_1;
break;
case MAX32_GPIO_DRV_STRENGTH_2:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_2;
break;
case MAX32_GPIO_DRV_STRENGTH_3:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_3;
break;
default:
gpio_cfg.drvstr = MXC_GPIO_DRVSTR_0;
break;
}
ret = MXC_GPIO_Config(&gpio_cfg);
if (ret != 0) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_LOW) {
MXC_GPIO_OutClr(cfg->regs, BIT(pin));
} else if (flags & GPIO_OUTPUT_INIT_HIGH) {
MXC_GPIO_OutSet(cfg->regs, BIT(pin));
}
}
return 0;
}
static int api_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct max32_gpio_config *cfg = dev->config;
mxc_gpio_cfg_t gpio_cfg;
gpio_cfg.port = cfg->regs;
gpio_cfg.mask = BIT(pin);
/* rest of the parameters not necessary */
if (mode == GPIO_INT_MODE_DISABLED) {
MXC_GPIO_DisableInt(cfg->regs, gpio_cfg.mask);
/* clear interrupt flags */
MXC_GPIO_ClearFlags(cfg->regs, (MXC_GPIO_GetFlags(cfg->regs) & gpio_cfg.mask));
return 0;
}
switch (mode) {
case GPIO_INT_MODE_LEVEL:
if (trig == GPIO_INT_TRIG_LOW) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_LOW);
} else if (trig == GPIO_INT_TRIG_HIGH) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_HIGH);
} else if (trig == GPIO_INT_TRIG_BOTH) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_BOTH);
} else {
return -EINVAL;
}
break;
case GPIO_INT_MODE_EDGE:
if (trig == GPIO_INT_TRIG_LOW) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_FALLING);
} else if (trig == GPIO_INT_TRIG_HIGH) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_RISING);
} else if (trig == GPIO_INT_TRIG_BOTH) {
MXC_GPIO_IntConfig(&gpio_cfg, MXC_GPIO_INT_BOTH);
} else {
return -EINVAL;
}
break;
default:
return -EINVAL;
}
cfg->irq_func();
MXC_GPIO_EnableInt(cfg->regs, gpio_cfg.mask);
return 0;
}
static int api_manage_callback(const struct device *dev, struct gpio_callback *callback, bool set)
{
struct max32_gpio_data *data = dev->data;
return gpio_manage_callback(&(data->cb_list), callback, set);
}
static const struct gpio_driver_api gpio_max32_driver = {
.pin_configure = api_pin_configure,
.port_get_raw = api_port_get_raw,
.port_set_masked_raw = api_port_set_masked_raw,
.port_set_bits_raw = api_port_set_bits_raw,
.port_clear_bits_raw = api_port_clear_bits_raw,
.port_toggle_bits = api_port_toggle_bits,
.pin_interrupt_configure = api_pin_interrupt_configure,
.manage_callback = api_manage_callback,
};
static void gpio_max32_isr(const void *param)
{
const struct device *dev = param;
const struct max32_gpio_config *cfg = dev->config;
struct max32_gpio_data *data = dev->data;
unsigned int flags = MXC_GPIO_GetFlags(cfg->regs);
/* clear interrupt flags */
MXC_GPIO_ClearFlags(cfg->regs, flags);
gpio_fire_callbacks(&(data->cb_list), dev, flags);
}
static int gpio_max32_init(const struct device *dev)
{
int ret = 0;
const struct max32_gpio_config *cfg = dev->config;
if (cfg->clock != NULL) {
/* enable clock */
ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
if (ret != 0) {
LOG_ERR("cannot enable GPIO clock");
return ret;
}
}
return ret;
}
#define MAX32_GPIO_INIT(_num) \
static void gpio_max32_irq_init_##_num(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), gpio_max32_isr, \
DEVICE_DT_INST_GET(_num), 0); \
irq_enable(DT_INST_IRQN(_num)); \
} \
static struct max32_gpio_data max32_gpio_data_##_num; \
static const struct max32_gpio_config max32_gpio_config_##_num = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_num), \
}, \
.regs = (mxc_gpio_regs_t *)DT_INST_REG_ADDR(_num), \
.irq_func = &gpio_max32_irq_init_##_num, \
.clock = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR(_num)), \
.perclk.bus = DT_INST_PHA_BY_IDX_OR(_num, clocks, 0, offset, 0), \
.perclk.bit = DT_INST_PHA_BY_IDX_OR(_num, clocks, 1, bit, 0), \
}; \
DEVICE_DT_INST_DEFINE(_num, gpio_max32_init, NULL, &max32_gpio_data_##_num, \
&max32_gpio_config_##_num, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
(void *)&gpio_max32_driver);
DT_INST_FOREACH_STATUS_OKAY(MAX32_GPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_max32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,081 |
```c
/*
*
*/
#include "analog.h"
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
/* Driver dts compatibility: telink,b91_gpio */
#define DT_DRV_COMPAT telink_b91_gpio
/* Get GPIO instance */
#define GET_GPIO(dev) ((volatile struct gpio_b91_t *) \
((const struct gpio_b91_config *)dev->config)->gpio_base)
/* Get GPIO IRQ number defined in dts */
#define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
/* Get GPIO IRQ priority defined in dts */
#define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
/* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
#define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
DT_REG_SIZE(DT_NODELABEL(gpioa))))
/* Check that gpio is port C */
#define IS_PORT_C(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpioc)))
/* Check that gpio is port D */
#define IS_PORT_D(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpiod)))
/* Check that 'inst' has only 1 interrupt selected in dts */
#define IS_INST_IRQ_EN(inst) (DT_NUM_IRQS(DT_DRV_INST(inst)) == 1)
/* Max pin number per port (pin 0..7) */
#define PIN_NUM_MAX ((uint8_t)7u)
/* IRQ Enable registers */
#define reg_irq_risc0_en(i) REG_ADDR8(0x140338 + i)
#define reg_irq_risc1_en(i) REG_ADDR8(0x140340 + i)
/* Pull-up/down resistors */
#define GPIO_PIN_UP_DOWN_FLOAT ((uint8_t)0u)
#define GPIO_PIN_PULLDOWN_100K ((uint8_t)2u)
#define GPIO_PIN_PULLUP_10K ((uint8_t)3u)
/* GPIO interrupt types */
#define INTR_RISING_EDGE ((uint8_t)0u)
#define INTR_FALLING_EDGE ((uint8_t)1u)
#define INTR_HIGH_LEVEL ((uint8_t)2u)
#define INTR_LOW_LEVEL ((uint8_t)3u)
/* Supported IRQ numbers */
#define IRQ_GPIO ((uint8_t)25u)
#define IRQ_GPIO2_RISC0 ((uint8_t)26u)
#define IRQ_GPIO2_RISC1 ((uint8_t)27u)
/* B91 GPIO registers structure */
struct gpio_b91_t {
uint8_t input; /* Input: read GPI input */
uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
uint8_t oen; /* OEN: output enable, low active. 0: enable, 1: disable */
uint8_t output; /* Output: configure GPIO output */
uint8_t polarity; /* Polarity: interrupt polarity: rising, falling */
uint8_t ds; /* DS: drive strength. 1: maximum (default), 0: minimal */
uint8_t actas_gpio; /* Act as GPIO: enable (1) or disable (0) GPIO function */
uint8_t irq_en; /* Act as GPIO: enable (1) or disable (0) GPIO function */
};
/* GPIO driver configuration structure */
struct gpio_b91_config {
struct gpio_driver_config common;
uint32_t gpio_base;
uint32_t irq_num;
uint8_t irq_priority;
void (*pirq_connect)(void);
};
/* GPIO driver data structure */
struct gpio_b91_data {
struct gpio_driver_data common; /* driver data */
sys_slist_t callbacks; /* list of callbacks */
};
/* Set IRQ Enable bit based on IRQ number */
static inline void gpiob_b91_irq_en_set(const struct device *dev, gpio_pin_t pin)
{
uint8_t irq = GET_IRQ_NUM(dev);
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
if (irq == IRQ_GPIO) {
BM_SET(gpio->irq_en, BIT(pin));
} else if (irq == IRQ_GPIO2_RISC0) {
BM_SET(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
} else if (irq == IRQ_GPIO2_RISC1) {
BM_SET(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
} else {
__ASSERT(false, "Not supported GPIO IRQ number.");
}
}
/* Clear IRQ Enable bit based on IRQ number */
static inline void gpiob_b91_irq_en_clr(const struct device *dev, gpio_pin_t pin)
{
uint8_t irq = GET_IRQ_NUM(dev);
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
if (irq == IRQ_GPIO) {
BM_CLR(gpio->irq_en, BIT(pin));
} else if (irq == IRQ_GPIO2_RISC0) {
BM_CLR(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
} else if (irq == IRQ_GPIO2_RISC1) {
BM_CLR(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
}
}
/* Get IRQ Enable register value */
static inline uint8_t gpio_b91_irq_en_get(const struct device *dev)
{
uint8_t status = 0;
uint8_t irq = GET_IRQ_NUM(dev);
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
if (irq == IRQ_GPIO) {
status = gpio->irq_en;
} else if (irq == IRQ_GPIO2_RISC0) {
status = reg_irq_risc0_en(GET_PORT_NUM(gpio));
} else if (irq == IRQ_GPIO2_RISC1) {
status = reg_irq_risc1_en(GET_PORT_NUM(gpio));
}
return status;
}
/* Clear IRQ Status bit */
static inline void gpio_b91_irq_status_clr(uint8_t irq)
{
gpio_irq_status_e status = 0;
if (irq == IRQ_GPIO) {
status = FLD_GPIO_IRQ_CLR;
} else if (irq == IRQ_GPIO2_RISC0) {
status = FLD_GPIO_IRQ_GPIO2RISC0_CLR;
} else if (irq == IRQ_GPIO2_RISC1) {
status = FLD_GPIO_IRQ_GPIO2RISC1_CLR;
}
reg_gpio_irq_clr = status;
}
/* Set pin's irq type */
void gpio_b91_irq_set(const struct device *dev, gpio_pin_t pin,
uint8_t trigger_type)
{
uint8_t irq_lvl = 0;
uint8_t irq_mask = 0;
uint8_t irq_num = GET_IRQ_NUM(dev);
uint8_t irq_prioriy = GET_IRQ_PRIORITY(dev);
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
/* Get level and mask based on IRQ number */
if (irq_num == IRQ_GPIO) {
irq_lvl = FLD_GPIO_IRQ_LVL_GPIO;
irq_mask = FLD_GPIO_IRQ_MASK_GPIO;
} else if (irq_num == IRQ_GPIO2_RISC0) {
irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC0;
irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC0;
} else if (irq_num == IRQ_GPIO2_RISC1) {
irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC1;
irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC1;
}
/* Set polarity and level */
switch (trigger_type) {
case INTR_RISING_EDGE:
BM_CLR(gpio->polarity, BIT(pin));
BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
break;
case INTR_FALLING_EDGE:
BM_SET(gpio->polarity, BIT(pin));
BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
break;
case INTR_HIGH_LEVEL:
BM_CLR(gpio->polarity, BIT(pin));
BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
break;
case INTR_LOW_LEVEL:
BM_SET(gpio->polarity, BIT(pin));
BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
break;
}
if (irq_num == IRQ_GPIO) {
reg_gpio_irq_ctrl |= FLD_GPIO_CORE_INTERRUPT_EN;
}
gpio_b91_irq_status_clr(irq_num);
BM_SET(reg_gpio_irq_risc_mask, irq_mask);
/* Enable peripheral interrupt */
gpiob_b91_irq_en_set(dev, pin);
/* Enable PLIC interrupt */
riscv_plic_irq_enable(irq_num);
riscv_plic_set_priority(irq_num, irq_prioriy);
}
/* Set pin's pull-up/down resistor */
static void gpio_b91_up_down_res_set(volatile struct gpio_b91_t *gpio,
gpio_pin_t pin,
uint8_t up_down_res)
{
uint8_t val;
uint8_t mask;
uint8_t analog_reg;
pin = BIT(pin);
val = up_down_res & 0x03;
analog_reg = 0x0e + (GET_PORT_NUM(gpio) << 1) + ((pin & 0xf0) ? 1 : 0);
if (pin & 0x11) {
val = val << 0;
mask = 0xfc;
} else if (pin & 0x22) {
val = val << 2;
mask = 0xf3;
} else if (pin & 0x44) {
val = val << 4;
mask = 0xcf;
} else if (pin & 0x88) {
val = val << 6;
mask = 0x3f;
} else {
return;
}
analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val);
}
/* Config Pin pull-up / pull-down resistors */
static void gpio_b91_config_up_down_res(volatile struct gpio_b91_t *gpio,
gpio_pin_t pin,
gpio_flags_t flags)
{
if ((flags & GPIO_PULL_UP) != 0) {
gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLUP_10K);
} else if ((flags & GPIO_PULL_DOWN) != 0) {
gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLDOWN_100K);
} else {
gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_UP_DOWN_FLOAT);
}
}
/* Config Pin In/Out direction */
static void gpio_b91_config_in_out(volatile struct gpio_b91_t *gpio,
gpio_pin_t pin,
gpio_flags_t flags)
{
uint8_t ie_addr = 0;
/* Port C and D Input Enable registers are located in another place: analog */
if (IS_PORT_C(gpio)) {
ie_addr = areg_gpio_pc_ie;
} else if (IS_PORT_D(gpio)) {
ie_addr = areg_gpio_pd_ie;
}
/* Enable/disable output */
WRITE_BIT(gpio->oen, pin, ~flags & GPIO_OUTPUT);
/* Enable/disable input */
if (ie_addr != 0) {
/* Port C and D are located in analog space */
if (flags & GPIO_INPUT) {
analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) | BIT(pin));
} else {
analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) & (~BIT(pin)));
}
} else {
/* Input Enable registers of all other ports are located in common GPIO space */
WRITE_BIT(gpio->ie, pin, flags & GPIO_INPUT);
}
}
/* GPIO driver initialization */
static int gpio_b91_init(const struct device *dev)
{
const struct gpio_b91_config *cfg = dev->config;
cfg->pirq_connect();
return 0;
}
/* API implementation: pin_configure */
static int gpio_b91_pin_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
/* Check input parameters: pin number */
if (pin > PIN_NUM_MAX) {
return -ENOTSUP;
}
/* Check input parameters: open-source and open-drain */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* Check input parameters: simultaneous in/out mode */
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
return -ENOTSUP;
}
/* Set GPIO init state if defined to avoid glitches */
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio->output |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio->output &= ~BIT(pin);
}
/* GPIO function enable */
WRITE_BIT(gpio->actas_gpio, BIT(pin), 1);
/* Set GPIO pull-up / pull-down resistors */
gpio_b91_config_up_down_res(gpio, pin, flags);
/* Enable/disable input/output */
gpio_b91_config_in_out(gpio, pin, flags);
return 0;
}
/* API implementation: port_get_raw */
static int gpio_b91_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
*value = gpio->input;
return 0;
}
/* API implementation: port_set_masked_raw */
static int gpio_b91_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
gpio->output = (gpio->output & ~mask) | (value & mask);
return 0;
}
/* API implementation: port_set_bits_raw */
static int gpio_b91_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
gpio->output |= mask;
return 0;
}
/* API implementation: port_clear_bits_raw */
static int gpio_b91_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
gpio->output &= ~mask;
return 0;
}
/* API implementation: port_toggle_bits */
static int gpio_b91_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
gpio->output ^= mask;
return 0;
}
/* API implementation: interrupts handler */
#if IS_INST_IRQ_EN(0) || IS_INST_IRQ_EN(1) || IS_INST_IRQ_EN(2) || \
IS_INST_IRQ_EN(3) || IS_INST_IRQ_EN(4)
static void gpio_b91_irq_handler(const struct device *dev)
{
struct gpio_b91_data *data = dev->data;
uint8_t irq = GET_IRQ_NUM(dev);
uint8_t status = gpio_b91_irq_en_get(dev);
gpio_b91_irq_status_clr(irq);
gpio_fire_callbacks(&data->callbacks, dev, status);
}
#endif
/* API implementation: pin_interrupt_configure */
static int gpio_b91_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
int ret_status = 0;
switch (mode) {
case GPIO_INT_MODE_DISABLED: /* GPIO interrupt disable */
gpiob_b91_irq_en_clr(dev, pin);
break;
case GPIO_INT_MODE_LEVEL:
if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt High level */
gpio_b91_irq_set(dev, pin, INTR_HIGH_LEVEL);
} else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Low level */
gpio_b91_irq_set(dev, pin, INTR_LOW_LEVEL);
} else {
ret_status = -ENOTSUP;
}
break;
case GPIO_INT_MODE_EDGE:
if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt Rising edge */
gpio_b91_irq_set(dev, pin, INTR_RISING_EDGE);
} else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Falling edge */
gpio_b91_irq_set(dev, pin, INTR_FALLING_EDGE);
} else {
ret_status = -ENOTSUP;
}
break;
default:
ret_status = -ENOTSUP;
break;
}
return ret_status;
}
/* API implementation: manage_callback */
static int gpio_b91_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_b91_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
/* GPIO driver APIs structure */
static const struct gpio_driver_api gpio_b91_driver_api = {
.pin_configure = gpio_b91_pin_configure,
.port_get_raw = gpio_b91_port_get_raw,
.port_set_masked_raw = gpio_b91_port_set_masked_raw,
.port_set_bits_raw = gpio_b91_port_set_bits_raw,
.port_clear_bits_raw = gpio_b91_port_clear_bits_raw,
.port_toggle_bits = gpio_b91_port_toggle_bits,
.pin_interrupt_configure = gpio_b91_pin_interrupt_configure,
.manage_callback = gpio_b91_manage_callback
};
/* If instance 0 is present and has interrupt enabled, connect IRQ */
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0
static void gpio_b91_irq_connect_0(void)
{
#if IS_INST_IRQ_EN(0)
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
gpio_b91_irq_handler,
DEVICE_DT_INST_GET(0), 0);
#endif
}
#endif
/* If instance 1 is present and has interrupt enabled, connect IRQ */
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
static void gpio_b91_irq_connect_1(void)
{
#if IS_INST_IRQ_EN(1)
IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
gpio_b91_irq_handler,
DEVICE_DT_INST_GET(1), 0);
#endif
}
#endif
/* If instance 2 is present and has interrupt enabled, connect IRQ */
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
static void gpio_b91_irq_connect_2(void)
{
#if IS_INST_IRQ_EN(2)
IRQ_CONNECT(DT_INST_IRQN(2), DT_INST_IRQ(2, priority),
gpio_b91_irq_handler,
DEVICE_DT_INST_GET(2), 0);
#endif
}
#endif
/* If instance 3 is present and has interrupt enabled, connect IRQ */
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
static void gpio_b91_irq_connect_3(void)
{
#if IS_INST_IRQ_EN(3)
IRQ_CONNECT(DT_INST_IRQN(3), DT_INST_IRQ(3, priority),
gpio_b91_irq_handler,
DEVICE_DT_INST_GET(3), 0);
#endif
}
#endif
/* If instance 4 is present and has interrupt enabled, connect IRQ */
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
static void gpio_b91_irq_connect_4(void)
{
#if IS_INST_IRQ_EN(4)
IRQ_CONNECT(DT_INST_IRQN(4), DT_INST_IRQ(4, priority),
gpio_b91_irq_handler,
DEVICE_DT_INST_GET(4), 0);
#endif
}
#endif
/* GPIO driver registration */
#define GPIO_B91_INIT(n) \
static const struct gpio_b91_config gpio_b91_config_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
}, \
.gpio_base = DT_INST_REG_ADDR(n), \
.irq_num = DT_INST_IRQN(n), \
.irq_priority = DT_INST_IRQ(n, priority), \
.pirq_connect = gpio_b91_irq_connect_##n \
}; \
static struct gpio_b91_data gpio_b91_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_b91_init, \
NULL, \
&gpio_b91_data_##n, \
&gpio_b91_config_##n, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_b91_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_B91_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_b91.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,498 |
```unknown
config GPIO_PSOC6
bool "Cypress PSoC-6 GPIO driver"
default y
depends on DT_HAS_CYPRESS_PSOC6_GPIO_ENABLED
help
Enable support for the Cypress PSoC-6 GPIO controllers.
``` | /content/code_sandbox/drivers/gpio/Kconfig.psoc6 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# RT1718S driver configuration options
menuconfig GPIO_RT1718S
bool "RT1718S I2C-based TCPC chip with GPIOs"
default y
depends on DT_HAS_RICHTEK_RT1718S_GPIO_PORT_ENABLED
help
Enable driver GPIO for RT1718S I2C-based TCPC chip.
if GPIO_RT1718S
config RT1718S_INIT_PRIORITY
int "RT1718S GPIO init priority"
default 60
help
RT1718S device driver initialization priority. The priority should be
lower than I2C device.
config GPIO_RT1718S_PORT_INIT_PRIORITY
int "RT1718S GPIO port init priority"
default 61
help
RT1718S GPIO driver initialization priority. The priority should be lower
than I2C & RT1718S_INIT_PRIORITY device.
config GPIO_RT1718S_INTERRUPT
bool "RT1718S alert handler"
help
Enable support for handling RT1718S Alert with a GPIO interrupt connected
from the chip.
endif # GPIO_RT1718S
``` | /content/code_sandbox/drivers/gpio/Kconfig.rt1718s | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 233 |
```c
/*
*/
#define DT_DRV_COMPAT adi_ad559x_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mfd/ad559x.h>
#define AD559X_GPIO_RD_POINTER 0x60
struct gpio_ad559x_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *mfd_dev;
};
struct gpio_ad559x_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
uint8_t gpio_val;
uint8_t gpio_out;
uint8_t gpio_in;
uint8_t gpio_pull_down;
};
static int gpio_ad559x_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_ad559x_config *config = dev->config;
struct gpio_ad559x_data *drv_data = dev->data;
uint16_t data;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (mfd_ad559x_has_pointer_byte_map(config->mfd_dev)) {
ret = mfd_ad559x_read_reg(config->mfd_dev, AD559X_GPIO_RD_POINTER, 0, &data);
/* LSB contains port information. Clear the MSB. */
data &= BIT_MASK(AD559X_PIN_MAX);
} else {
ret = mfd_ad559x_read_reg(config->mfd_dev, AD559X_REG_GPIO_INPUT_EN,
drv_data->gpio_in, &data);
}
if (ret < 0) {
return ret;
}
*value = (uint32_t)data;
return 0;
}
static int gpio_ad559x_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
struct gpio_ad559x_data *data = dev->data;
const struct gpio_ad559x_config *config = dev->config;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
data->gpio_val |= (uint8_t)pins;
return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_GPIO_SET, data->gpio_val);
}
static int gpio_ad559x_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
struct gpio_ad559x_data *data = dev->data;
const struct gpio_ad559x_config *config = dev->config;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
data->gpio_val &= ~(uint8_t)pins;
return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_GPIO_SET, data->gpio_val);
}
static inline int gpio_ad559x_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
struct gpio_ad559x_data *data = dev->data;
const struct gpio_ad559x_config *config = dev->config;
uint8_t val;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin >= AD559X_PIN_MAX) {
return -EINVAL;
}
val = BIT(pin);
if ((flags & GPIO_OUTPUT) != 0U) {
data->gpio_in &= ~val;
data->gpio_out |= val;
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
ret = gpio_ad559x_port_set_bits_raw(
dev, (gpio_port_pins_t)BIT(pin));
if (ret < 0) {
return ret;
}
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
ret = gpio_ad559x_port_clear_bits_raw(
dev, (gpio_port_pins_t)BIT(pin));
if (ret < 0) {
return ret;
}
}
ret = mfd_ad559x_write_reg(config->mfd_dev,
AD559X_REG_GPIO_OUTPUT_EN, data->gpio_out);
if (ret < 0) {
return ret;
}
ret = mfd_ad559x_write_reg(config->mfd_dev,
AD559X_REG_GPIO_INPUT_EN, data->gpio_in);
} else if ((flags & GPIO_INPUT) != 0U) {
data->gpio_in |= val;
data->gpio_out &= ~val;
if ((flags & GPIO_PULL_DOWN) != 0U) {
data->gpio_pull_down |= val;
ret = mfd_ad559x_write_reg(config->mfd_dev,
AD559X_REG_GPIO_PULLDOWN,
data->gpio_pull_down);
if (ret < 0) {
return ret;
}
} else if ((flags & GPIO_PULL_UP) != 0U) {
return -ENOTSUP;
}
ret = mfd_ad559x_write_reg(config->mfd_dev,
AD559X_REG_GPIO_OUTPUT_EN, data->gpio_out);
if (ret < 0) {
return ret;
}
ret = mfd_ad559x_write_reg(config->mfd_dev,
AD559X_REG_GPIO_INPUT_EN, data->gpio_in);
} else {
return -ENOTSUP;
}
return ret;
}
static int gpio_ad559x_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
ARG_UNUSED(dev);
ARG_UNUSED(mask);
ARG_UNUSED(value);
return -ENOTSUP;
}
static int gpio_ad559x_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
ARG_UNUSED(dev);
ARG_UNUSED(pins);
return -ENOTSUP;
}
static int gpio_ad559x_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(mode);
ARG_UNUSED(trig);
return -ENOTSUP;
}
static const struct gpio_driver_api gpio_ad559x_api = {
.pin_configure = gpio_ad559x_configure,
.port_get_raw = gpio_ad559x_port_get_raw,
.port_set_masked_raw = gpio_ad559x_port_set_masked_raw,
.port_set_bits_raw = gpio_ad559x_port_set_bits_raw,
.port_clear_bits_raw = gpio_ad559x_port_clear_bits_raw,
.port_toggle_bits = gpio_ad559x_port_toggle_bits,
.pin_interrupt_configure = gpio_ad559x_pin_interrupt_configure,
};
static int gpio_ad559x_init(const struct device *dev)
{
const struct gpio_ad559x_config *config = dev->config;
if (!device_is_ready(config->mfd_dev)) {
return -ENODEV;
}
return 0;
}
#define GPIO_AD559X_DEFINE(inst) \
static const struct gpio_ad559x_config gpio_ad559x_config##inst = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
\
static struct gpio_ad559x_data gpio_ad559x_data##inst; \
\
DEVICE_DT_INST_DEFINE(inst, gpio_ad559x_init, NULL, \
&gpio_ad559x_data##inst, &gpio_ad559x_config##inst, \
POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
&gpio_ad559x_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_AD559X_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_ad559x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,658 |
```unknown
# Gecko GPIO configuration options
menuconfig GPIO_GECKO
bool "Gecko GPIO driver"
default y
depends on DT_HAS_SILABS_GECKO_GPIO_PORT_ENABLED
select SOC_GECKO_GPIO
help
Enable the Gecko gpio driver.
config GPIO_GECKO_COMMON_INIT_PRIORITY
int "Common initialization priority"
depends on GPIO_GECKO
default 39
``` | /content/code_sandbox/drivers/gpio/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_common.h>
#include <fsl_gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_pin_gaps {
uint8_t start;
uint8_t len;
};
struct mcux_igpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Type *base;
const struct pinctrl_soc_pinmux *pin_muxes;
const struct gpio_pin_gaps *pin_gaps;
uint8_t mux_count;
uint8_t gap_count;
};
struct mcux_igpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data general;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static int mcux_igpio_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
struct pinctrl_soc_pin pin_cfg;
int cfg_idx = pin, i;
/* Some SOCs have non-contiguous gpio pin layouts, account for this */
for (i = 0; i < config->gap_count; i++) {
if (pin >= config->pin_gaps[i].start) {
if (pin < (config->pin_gaps[i].start +
config->pin_gaps[i].len)) {
/* Pin is not connected to a mux */
return -ENOTSUP;
}
cfg_idx -= config->pin_gaps[i].len;
}
}
/* Init pin configuration struct, and use pinctrl api to apply settings */
if (cfg_idx >= config->mux_count) {
/* Pin is not connected to a mux */
return -ENOTSUP;
}
/* Set appropriate bits in pin configuration register */
volatile uint32_t *gpio_cfg_reg =
(volatile uint32_t *)config->pin_muxes[cfg_idx].config_register;
uint32_t reg = *gpio_cfg_reg;
#ifdef CONFIG_SOC_SERIES_IMXRT10XX
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
} else {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
}
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
if (((flags & GPIO_PULL_UP) != 0)) {
/* Use 100K pullup */
reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
} else {
/* 100K pulldown */
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
}
} else {
/* Set pin to keeper */
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
}
#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
if (config->pin_muxes[pin].pue_mux) {
/* PUE type register layout (GPIO_AD pins) */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
} else {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
}
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
if (((flags & GPIO_PULL_UP) != 0)) {
reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
} else {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
}
} else {
/* Set pin to highz */
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
}
} else {
/* PDRV/SNVS/LPSR type register layout */
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
if (((flags & GPIO_PULL_UP) != 0)) {
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
} else {
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
}
} else {
/* Set pin to no pull */
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
}
/* PDRV/SNVS/LPSR reg have different ODE bits */
if (config->pin_muxes[cfg_idx].pdrv_mux) {
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
} else {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
}
} else if (config->pin_muxes[cfg_idx].lpsr_mux) {
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
} else {
reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
}
} else if (config->pin_muxes[cfg_idx].snvs_mux) {
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
} else {
reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
}
}
}
#elif defined(CONFIG_SOC_MIMX8MQ6_M4)
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
} else {
reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
}
if ((flags & GPIO_PULL_UP) != 0) {
reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
}
if ((flag & GPIO_PULL_DOWN) != 0) {
return -ENOTSUP;
}
#else
/* Default flags, should work for most SOCs */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
} else {
reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
}
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
reg |= (0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
if (((flags & GPIO_PULL_UP) != 0)) {
reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
} else {
reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
}
} else {
/* Set pin to highz */
reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
}
#endif /* CONFIG_SOC_SERIES_IMXRT10XX */
memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux));
/* cfg register will be set by pinctrl_configure_pins */
pin_cfg.pin_ctrl_flags = reg;
pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
GPIO_WritePinOutput(base, pin, 1);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
GPIO_WritePinOutput(base, pin, 0);
}
WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT);
return 0;
}
static int mcux_igpio_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
*value = base->DR;
return 0;
}
static int mcux_igpio_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
base->DR = (base->DR & ~mask) | (mask & value);
return 0;
}
static int mcux_igpio_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
GPIO_PortSet(base, mask);
return 0;
}
static int mcux_igpio_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
GPIO_PortClear(base, mask);
return 0;
}
static int mcux_igpio_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
GPIO_PortToggle(base, mask);
return 0;
}
static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct mcux_igpio_config *config = dev->config;
GPIO_Type *base = config->base;
unsigned int key;
uint8_t icr;
int shift;
if (mode == GPIO_INT_MODE_DISABLED) {
key = irq_lock();
WRITE_BIT(base->IMR, pin, 0);
irq_unlock(key);
return 0;
}
if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
icr = 3;
} else if ((mode == GPIO_INT_MODE_EDGE) &&
(trig == GPIO_INT_TRIG_HIGH)) {
icr = 2;
} else if ((mode == GPIO_INT_MODE_LEVEL) &&
(trig == GPIO_INT_TRIG_HIGH)) {
icr = 1;
} else {
icr = 0;
}
if (pin < 16) {
shift = 2 * pin;
base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift);
} else if (pin < 32) {
shift = 2 * (pin - 16);
base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift);
} else {
return -EINVAL;
}
key = irq_lock();
WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
WRITE_BIT(base->ISR, pin, 1);
WRITE_BIT(base->IMR, pin, 1);
irq_unlock(key);
return 0;
}
static int mcux_igpio_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct mcux_igpio_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void mcux_igpio_port_isr(const struct device *dev)
{
const struct mcux_igpio_config *config = dev->config;
struct mcux_igpio_data *data = dev->data;
GPIO_Type *base = config->base;
uint32_t int_flags;
int_flags = base->ISR;
base->ISR = int_flags;
gpio_fire_callbacks(&data->callbacks, dev, int_flags);
}
static const struct gpio_driver_api mcux_igpio_driver_api = {
.pin_configure = mcux_igpio_configure,
.port_get_raw = mcux_igpio_port_get_raw,
.port_set_masked_raw = mcux_igpio_port_set_masked_raw,
.port_set_bits_raw = mcux_igpio_port_set_bits_raw,
.port_clear_bits_raw = mcux_igpio_port_clear_bits_raw,
.port_toggle_bits = mcux_igpio_port_toggle_bits,
.pin_interrupt_configure = mcux_igpio_pin_interrupt_configure,
.manage_callback = mcux_igpio_manage_callback,
};
/* These macros will declare an array of pinctrl_soc_pinmux types */
#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
#define MCUX_IGPIO_PIN_DECLARE(n) \
const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
}; \
const uint8_t mcux_igpio_pin_gaps_##n[] = \
DT_INST_PROP_OR(n, gpio_reserved_ranges, {});
#define MCUX_IGPIO_PIN_INIT(n) \
.pin_muxes = mcux_igpio_pinmux_##n, \
.pin_gaps = (const struct gpio_pin_gaps *)mcux_igpio_pin_gaps_##n, \
.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux), \
.gap_count = (ARRAY_SIZE(mcux_igpio_pin_gaps_##n) / 2)
#define MCUX_IGPIO_IRQ_INIT(n, i) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
DT_INST_IRQ_BY_IDX(n, i, priority), \
mcux_igpio_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
} while (false)
#define MCUX_IGPIO_INIT(n) \
MCUX_IGPIO_PIN_DECLARE(n) \
static int mcux_igpio_##n##_init(const struct device *dev); \
\
static const struct mcux_igpio_config mcux_igpio_##n##_config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.base = (GPIO_Type *)DT_INST_REG_ADDR(n), \
MCUX_IGPIO_PIN_INIT(n) \
}; \
\
static struct mcux_igpio_data mcux_igpio_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
mcux_igpio_##n##_init, \
NULL, \
&mcux_igpio_##n##_data, \
&mcux_igpio_##n##_config, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&mcux_igpio_driver_api); \
\
static int mcux_igpio_##n##_init(const struct device *dev) \
{ \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
(MCUX_IGPIO_IRQ_INIT(n, 0);)) \
\
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
(MCUX_IGPIO_IRQ_INIT(n, 1);)) \
\
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(MCUX_IGPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_mcux_igpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,555 |
```unknown
# TI CC13xx / CC26xx GPIO configuration options
config GPIO_CC13XX_CC26XX
bool "TI SimpleLink CC13xx / CC26xx GPIO driver"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_GPIO_ENABLED
help
Enable the TI SimpleLink CC13xx / CC26xx GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.cc13xx_cc26xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
# STM32 GPIO configuration
config GPIO_STM32
bool "GPIO Driver for STM32 family of MCUs"
default y
depends on DT_HAS_ST_STM32_GPIO_ENABLED
help
Enable GPIO driver for STM32 line of MCUs
``` | /content/code_sandbox/drivers/gpio/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# BD8LB600FS GPIO configuration options
menuconfig GPIO_BD8LB600FS
bool "BD8LB600FS SPI-based GPIO chip"
default y
depends on DT_HAS_ROHM_BD8LB600FS_GPIO_ENABLED
select MFD
help
Enable driver for BD8LB600FS SPI-based GPIO chip.
if GPIO_BD8LB600FS
config GPIO_BD8LB600FS_INIT_PRIORITY
int "Init priority"
default 75
help
Device driver initialization priority.
endif #GPIO_BD8LB600FS
``` | /content/code_sandbox/drivers/gpio/Kconfig.bd8lb600fs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```c
/*
*
*/
#define DT_DRV_COMPAT altr_pio_1_0
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define ALTERA_AVALON_PIO_DATA_OFFSET 0x00
#define ALTERA_AVALON_PIO_DIRECTION_OFFSET 0x04
#define ALTERA_AVALON_PIO_IRQ_OFFSET 0x08
#define ALTERA_AVALON_PIO_SET_BITS 0x10
#define ALTERA_AVALON_PIO_CLEAR_BITS 0x14
typedef void (*altera_cfg_func_t)(void);
struct gpio_altera_config {
struct gpio_driver_config common;
uintptr_t reg_base;
uint32_t irq_num;
uint8_t direction;
uint8_t outset;
uint8_t outclear;
altera_cfg_func_t cfg_func;
};
struct gpio_altera_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of callbacks */
sys_slist_t cb;
struct k_spinlock lock;
};
static bool gpio_pin_direction(const struct device *dev, uint32_t pin_mask)
{
const struct gpio_altera_config *cfg = dev->config;
const int direction = cfg->direction;
uintptr_t reg_base = cfg->reg_base;
uint32_t addr;
uint32_t pin_direction;
if (pin_mask == 0) {
return -EINVAL;
}
/* Check if the direction is Bidirectional */
if (direction != 0) {
return -EINVAL;
}
addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET;
pin_direction = sys_read32(addr);
if (!(pin_direction & pin_mask)) {
return false;
}
return true;
}
static int gpio_altera_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_altera_config *cfg = dev->config;
struct gpio_altera_data * const data = dev->data;
const int port_pin_mask = cfg->common.port_pin_mask;
const int direction = cfg->direction;
uintptr_t reg_base = cfg->reg_base;
k_spinlock_key_t key;
uint32_t addr;
/* Check if pin number is within range */
if ((port_pin_mask & BIT(pin)) == 0) {
return -EINVAL;
}
/* Check if the direction is Bidirectional */
if (direction != 0) {
return -EINVAL;
}
addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET;
key = k_spin_lock(&data->lock);
if (flags == GPIO_INPUT) {
sys_clear_bits(addr, BIT(pin));
} else if (flags == GPIO_OUTPUT) {
sys_set_bits(addr, BIT(pin));
} else {
return -EINVAL;
}
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_altera_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_altera_config *cfg = dev->config;
uintptr_t reg_base = cfg->reg_base;
uint32_t addr;
addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
if (value == NULL) {
return -EINVAL;
}
*value = sys_read32((addr));
return 0;
}
static int gpio_altera_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_altera_config *cfg = dev->config;
struct gpio_altera_data * const data = dev->data;
const uint8_t outset = cfg->outset;
const int port_pin_mask = cfg->common.port_pin_mask;
uintptr_t reg_base = cfg->reg_base;
uint32_t addr;
k_spinlock_key_t key;
if ((port_pin_mask & mask) == 0) {
return -EINVAL;
}
if (!gpio_pin_direction(dev, mask)) {
return -EINVAL;
}
key = k_spin_lock(&data->lock);
if (outset) {
addr = reg_base + ALTERA_AVALON_PIO_SET_BITS;
sys_write32(mask, addr);
} else {
addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
sys_set_bits(addr, mask);
}
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_altera_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_altera_config *cfg = dev->config;
struct gpio_altera_data * const data = dev->data;
const uint8_t outclear = cfg->outclear;
const int port_pin_mask = cfg->common.port_pin_mask;
uintptr_t reg_base = cfg->reg_base;
uint32_t addr;
k_spinlock_key_t key;
/* Check if mask range within 32 */
if ((port_pin_mask & mask) == 0) {
return -EINVAL;
}
if (!gpio_pin_direction(dev, mask)) {
return -EINVAL;
}
key = k_spin_lock(&data->lock);
if (outclear) {
addr = reg_base + ALTERA_AVALON_PIO_CLEAR_BITS;
sys_write32(mask, addr);
} else {
addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET;
sys_clear_bits(addr, mask);
}
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_init(const struct device *dev)
{
const struct gpio_altera_config *cfg = dev->config;
/* Configure GPIO device */
cfg->cfg_func();
return 0;
}
static int gpio_altera_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
ARG_UNUSED(trig);
const struct gpio_altera_config *cfg = dev->config;
struct gpio_altera_data * const data = dev->data;
uintptr_t reg_base = cfg->reg_base;
const int port_pin_mask = cfg->common.port_pin_mask;
uint32_t addr;
k_spinlock_key_t key;
/* Check if pin number is within range */
if ((port_pin_mask & BIT(pin)) == 0) {
return -EINVAL;
}
if (!gpio_pin_direction(dev, BIT(pin))) {
return -EINVAL;
}
addr = reg_base + ALTERA_AVALON_PIO_IRQ_OFFSET;
key = k_spin_lock(&data->lock);
switch (mode) {
case GPIO_INT_MODE_DISABLED:
/* Disable interrupt of pin */
sys_clear_bits(addr, BIT(pin));
irq_disable(cfg->irq_num);
break;
case GPIO_INT_MODE_LEVEL:
case GPIO_INT_MODE_EDGE:
/* Enable interrupt of pin */
sys_set_bits(addr, BIT(pin));
irq_enable(cfg->irq_num);
break;
default:
return -EINVAL;
}
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_altera_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_altera_data * const data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static void gpio_altera_irq_handler(const struct device *dev)
{
const struct gpio_altera_config *cfg = dev->config;
struct gpio_altera_data *data = dev->data;
uintptr_t reg_base = cfg->reg_base;
uint32_t port_value;
uint32_t addr;
k_spinlock_key_t key;
addr = reg_base + ALTERA_AVALON_PIO_IRQ_OFFSET;
key = k_spin_lock(&data->lock);
port_value = sys_read32(addr);
sys_clear_bits(addr, port_value);
k_spin_unlock(&data->lock, key);
/* Call the corresponding callback registered for the pin */
gpio_fire_callbacks(&data->cb, dev, port_value);
}
static const struct gpio_driver_api gpio_altera_driver_api = {
.pin_configure = gpio_altera_configure,
.port_get_raw = gpio_altera_port_get_raw,
.port_set_masked_raw = NULL,
.port_set_bits_raw = gpio_altera_port_set_bits_raw,
.port_clear_bits_raw = gpio_altera_port_clear_bits_raw,
.port_toggle_bits = NULL,
.pin_interrupt_configure = gpio_altera_pin_interrupt_configure,
.manage_callback = gpio_altera_manage_callback
};
#define GPIO_CFG_IRQ(idx, n) \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \
COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, priority), \
DT_INST_IRQ(n, priority), (0)), gpio_altera_irq_handler, \
DEVICE_DT_INST_GET(n), 0); \
#define CREATE_GPIO_DEVICE(n) \
static void gpio_altera_cfg_func_##n(void); \
static struct gpio_altera_data gpio_altera_data_##n; \
static struct gpio_altera_config gpio_config_##n = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.reg_base = DT_INST_REG_ADDR(n), \
.direction = DT_INST_ENUM_IDX(n, direction), \
.irq_num = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), (DT_INST_IRQN(n)), (0)),\
.cfg_func = gpio_altera_cfg_func_##n, \
.outset = DT_INST_PROP(n, outset), \
.outclear = DT_INST_PROP(n, outclear), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_init, \
NULL, \
&gpio_altera_data_##n, \
&gpio_config_##n, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_altera_driver_api); \
\
static void gpio_altera_cfg_func_##n(void) \
{ \
LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), GPIO_CFG_IRQ, (), n)\
}
DT_INST_FOREACH_STATUS_OKAY(CREATE_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_altera_pio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,211 |
```unknown
# TCA6424A configuration options
menuconfig GPIO_TCA6424A
bool "TCA6424A driver"
default y
depends on DT_HAS_TI_TCA6424A_ENABLED
depends on I2C
help
Enable driver for TCA6424A IO expander chip.
config GPIO_TCA6424A_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_TCA6424A
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.tca6424a | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```c
/*
*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_gpio_v2
#include <chip_chipregs.h>
#include <errno.h>
#include <soc.h>
#include <soc_dt.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
/*
* Structure gpio_ite_cfg is about the setting of GPIO
* this config will be used at initial time
*/
struct gpio_ite_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* GPIO port data register (bit mapping to pin) */
uintptr_t reg_gpdr;
/* GPIO port data mirror register (bit mapping to pin) */
uintptr_t reg_gpdmr;
/* GPIO port output type register (bit mapping to pin) */
uintptr_t reg_gpotr;
/* GPIO port 1.8V select register (bit mapping to pin) */
uintptr_t reg_p18scr;
/* GPIO port control register (byte mapping to pin) */
uintptr_t reg_gpcr;
/* Wake up control base register */
uintptr_t wuc_base[8];
/* Wake up control mask */
uint8_t wuc_mask[8];
/* GPIO's irq */
uint8_t gpio_irq[8];
/* Support input voltage selection */
uint8_t has_volt_sel[8];
/* Number of pins per group of GPIO */
uint8_t num_pins;
/* gpioksi, gpioksoh and gpioksol extended setting */
bool kbs_ctrl;
};
/* Structure gpio_ite_data is about callback function */
struct gpio_ite_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
uint8_t volt_default_set;
struct k_spinlock lock;
uint8_t level_isr_high;
uint8_t level_isr_low;
const struct device *instance;
struct k_work interrupt_worker;
};
/**
* Driver functions
*/
static int gpio_ite_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
struct gpio_ite_data *data = dev->data;
uint8_t mask = BIT(pin);
int rc = 0;
/* Don't support "open source" mode */
if (((flags & GPIO_SINGLE_ENDED) != 0) &&
((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
return -ENOTSUP;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (flags == GPIO_DISCONNECTED) {
ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_TRISTATE;
/*
* Since not all GPIOs can be to configured as tri-state,
* prompt error if pin doesn't support the flag.
*/
if (ECREG(reg_gpcr) != GPCR_PORT_PIN_MODE_TRISTATE) {
/* Go back to default setting (input) */
ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_INPUT;
LOG_ERR("Cannot config the node-gpio@%x, pin=%d as tri-state",
(uint32_t)reg_gpdr, pin);
rc = -ENOTSUP;
goto unlock_and_return;
}
/*
* The following configuration isn't necessary because the pin
* was configured as disconnected.
*/
rc = 0;
goto unlock_and_return;
}
/*
* Select open drain first, so that we don't glitch the signal
* when changing the line to an output.
*/
if (flags & GPIO_OPEN_DRAIN) {
ECREG(reg_gpotr) |= mask;
} else {
ECREG(reg_gpotr) &= ~mask;
}
/* 1.8V or 3.3V */
if (gpio_config->has_volt_sel[pin]) {
gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
__ASSERT(!(flags & GPIO_PULL_UP),
"Don't enable internal pullup if 1.8V voltage is used");
ECREG(reg_p18scr) |= mask;
data->volt_default_set &= ~mask;
} else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) {
ECREG(reg_p18scr) &= ~mask;
/*
* A variable is needed to store the difference between
* 3.3V and default so that the flag can be distinguished
* between the two in gpio_ite_get_config.
*/
data->volt_default_set &= ~mask;
} else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
ECREG(reg_p18scr) &= ~mask;
data->volt_default_set |= mask;
} else {
rc = -EINVAL;
goto unlock_and_return;
}
}
/* If output, set level before changing type to an output. */
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
ECREG(reg_gpdr) |= mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
ECREG(reg_gpdr) &= ~mask;
}
}
/* Set input or output. */
if (gpio_config->kbs_ctrl) {
/* Handle keyboard scan controller */
uint8_t ksxgctrlr = ECREG(reg_gpcr);
ksxgctrlr |= KSIX_KSOX_KBS_GPIO_MODE;
if (flags & GPIO_OUTPUT) {
ksxgctrlr |= KSIX_KSOX_GPIO_OUTPUT;
} else {
ksxgctrlr &= ~KSIX_KSOX_GPIO_OUTPUT;
}
ECREG(reg_gpcr) = ksxgctrlr;
} else {
/* Handle regular GPIO controller */
if (flags & GPIO_OUTPUT) {
ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_OUTPUT) &
~GPCR_PORT_PIN_MODE_INPUT;
} else {
ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
}
}
/* Handle pullup / pulldown */
if (gpio_config->kbs_ctrl) {
/* Handle keyboard scan controller */
uint8_t ksxgctrlr = ECREG(reg_gpcr);
if (flags & GPIO_PULL_UP) {
ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLUP) &
~KSIX_KSOX_GPIO_PULLDOWN;
} else if (flags & GPIO_PULL_DOWN) {
ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLDOWN) &
~KSIX_KSOX_GPIO_PULLUP;
} else {
/* No pull up/down */
ksxgctrlr &= ~(KSIX_KSOX_GPIO_PULLUP | KSIX_KSOX_GPIO_PULLDOWN);
}
ECREG(reg_gpcr) = ksxgctrlr;
} else {
/* Handle regular GPIO controller */
if (flags & GPIO_PULL_UP) {
ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLUP) &
~GPCR_PORT_PIN_MODE_PULLDOWN;
} else if (flags & GPIO_PULL_DOWN) {
ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLDOWN) &
~GPCR_PORT_PIN_MODE_PULLUP;
} else {
/* No pull up/down */
ECREG(reg_gpcr) &= ~(GPCR_PORT_PIN_MODE_PULLUP |
GPCR_PORT_PIN_MODE_PULLDOWN);
}
}
unlock_and_return:
k_spin_unlock(&data->lock, key);
return rc;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_ite_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
struct gpio_ite_data *data = dev->data;
uint8_t mask = BIT(pin);
gpio_flags_t flags = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* push-pull or open-drain */
if (ECREG(reg_gpotr) & mask) {
flags |= GPIO_OPEN_DRAIN;
}
/* 1.8V or 3.3V */
if (gpio_config->has_volt_sel[pin]) {
if (data->volt_default_set & mask) {
flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT;
} else {
if (ECREG(reg_p18scr) & mask) {
flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
} else {
flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
}
}
}
/* set input or output. */
if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_OUTPUT) {
flags |= GPIO_OUTPUT;
/* set level */
if (ECREG(reg_gpdr) & mask) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
}
if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_INPUT) {
flags |= GPIO_INPUT;
/* pullup / pulldown */
if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLUP) {
flags |= GPIO_PULL_UP;
}
if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLDOWN) {
flags |= GPIO_PULL_DOWN;
}
}
*out_flags = flags;
k_spin_unlock(&data->lock, key);
return 0;
}
#endif
static int gpio_ite_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
/* Get raw bits of GPIO mirror register */
*value = ECREG(reg_gpdmr);
return 0;
}
static int gpio_ite_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
uint8_t masked_value = value & mask;
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
uint8_t out = ECREG(reg_gpdr);
ECREG(reg_gpdr) = ((out & ~mask) | masked_value);
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_ite_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Set raw bits of GPIO data register */
ECREG(reg_gpdr) |= pins;
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_ite_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Clear raw bits of GPIO data register */
ECREG(reg_gpdr) &= ~pins;
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_ite_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Toggle raw bits of GPIO data register */
ECREG(reg_gpdr) ^= pins;
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_ite_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
int rc = gpio_manage_callback(&data->callbacks, callback, set);
k_spin_unlock(&data->lock, key);
return rc;
}
static void gpio_ite_isr(const void *arg)
{
const struct device *dev = arg;
const struct gpio_ite_cfg *gpio_config = dev->config;
struct gpio_ite_data *data = dev->data;
uint8_t irq = ite_intc_get_irq_num();
uint8_t num_pins = gpio_config->num_pins;
uint8_t pin;
for (pin = 0; pin < num_pins; pin++) {
if (irq == gpio_config->gpio_irq[pin]) {
volatile uint8_t *reg_base =
(uint8_t *)gpio_config->wuc_base[pin];
volatile uint8_t *reg_wuesr = reg_base + 1;
uint8_t wuc_mask = gpio_config->wuc_mask[pin];
/* Should be safe even without spinlock. */
/* Clear the WUC status register. */
ECREG(reg_wuesr) = wuc_mask;
/* The callbacks are user code, and therefore should
* not hold the lock.
*/
gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
break;
}
}
/* Reschedule worker */
k_work_submit(&data->interrupt_worker);
}
static void gpio_ite_interrupt_worker(struct k_work *work)
{
struct gpio_ite_data * const data = CONTAINER_OF(
work, struct gpio_ite_data, interrupt_worker);
gpio_port_value_t value;
gpio_port_value_t triggered_int;
gpio_ite_port_get_raw(data->instance, &value);
k_spinlock_key_t key = k_spin_lock(&data->lock);
triggered_int = (value & data->level_isr_high) | (~value & data->level_isr_low);
k_spin_unlock(&data->lock, key);
if (triggered_int != 0) {
gpio_fire_callbacks(&data->callbacks, data->instance,
triggered_int);
/* Reschedule worker */
k_work_submit(&data->interrupt_worker);
}
}
static int gpio_ite_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_ite_cfg *gpio_config = dev->config;
uint8_t gpio_irq = gpio_config->gpio_irq[pin];
struct gpio_ite_data *data = dev->data;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
#else
if (mode == GPIO_INT_MODE_DISABLED) {
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
/* Disable GPIO interrupt */
irq_disable(gpio_irq);
return 0;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
/* Only enable GPIO interrupt */
irq_enable(gpio_irq);
return 0;
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
}
/* Disable irq before configuring it */
irq_disable(gpio_irq);
if (trig & GPIO_INT_TRIG_BOTH) {
volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin];
volatile uint8_t *reg_wuemr = reg_base;
volatile uint8_t *reg_wuesr = reg_base + 1;
volatile uint8_t *reg_wubemr = reg_base + 3;
uint8_t wuc_mask = gpio_config->wuc_mask[pin];
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Set both edges interrupt. */
if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
ECREG(reg_wubemr) |= wuc_mask;
} else {
ECREG(reg_wubemr) &= ~wuc_mask;
}
if (trig & GPIO_INT_TRIG_LOW) {
ECREG(reg_wuemr) |= wuc_mask;
} else {
ECREG(reg_wuemr) &= ~wuc_mask;
}
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig & GPIO_INT_TRIG_LOW) {
data->level_isr_low |= BIT(pin);
data->level_isr_high &= ~BIT(pin);
} else {
data->level_isr_low &= ~BIT(pin);
data->level_isr_high |= BIT(pin);
}
} else {
data->level_isr_low &= ~BIT(pin);
data->level_isr_high &= ~BIT(pin);
}
/*
* Always write 1 to clear the WUC status register after
* modifying edge mode selection register (WUBEMR and WUEMR).
*/
ECREG(reg_wuesr) = wuc_mask;
k_spin_unlock(&data->lock, key);
}
/* Enable GPIO interrupt */
irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
irq_enable(gpio_irq);
k_work_submit(&data->interrupt_worker);
return 0;
}
static const struct gpio_driver_api gpio_ite_driver_api = {
.pin_configure = gpio_ite_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_ite_get_config,
#endif
.port_get_raw = gpio_ite_port_get_raw,
.port_set_masked_raw = gpio_ite_port_set_masked_raw,
.port_set_bits_raw = gpio_ite_port_set_bits_raw,
.port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
.port_toggle_bits = gpio_ite_port_toggle_bits,
.pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
.manage_callback = gpio_ite_manage_callback,
};
static int gpio_ite_init(const struct device *dev)
{
struct gpio_ite_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->instance = dev;
k_work_init(&data->interrupt_worker,
gpio_ite_interrupt_worker);
k_spin_unlock(&data->lock, key);
return 0;
}
#define GPIO_ITE_DEV_CFG_DATA(inst) \
static struct gpio_ite_data gpio_ite_data_##inst; \
static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
}, \
.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
.reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
.wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}), \
.wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}), \
.gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst), \
.has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}), \
.num_pins = DT_INST_PROP(inst, ngpios), \
.kbs_ctrl = DT_INST_PROP_OR(inst, keyboard_controller, 0), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
gpio_ite_init, \
NULL, \
&gpio_ite_data_##inst, \
&gpio_ite_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_ite_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
#ifdef CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
static int gpio_it8xxx2_init_set(void)
{
const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
for (int i = 0; i < 8; i++) {
gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
}
return 0;
}
SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
#endif /* CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN */
``` | /content/code_sandbox/drivers/gpio/gpio_ite_it8xxx2_v2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,980 |
```unknown
config GPIO_GRGPIO2
bool "GRLIB GRGPIO revision 2"
default y
depends on DT_HAS_GAISLER_GRGPIO_ENABLED
help
Enable driver for GRLIB GRGPIO revision 2.
``` | /content/code_sandbox/drivers/gpio/Kconfig.grgpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```c
/*
*
*/
#define DT_DRV_COMPAT snps_creg_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(creg_gpio, CONFIG_GPIO_LOG_LEVEL);
#include <zephyr/drivers/gpio/gpio_utils.h>
/** Runtime driver data */
struct creg_gpio_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
uint32_t pin_val;
uint32_t base_addr;
};
/** Configuration data */
struct creg_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uint32_t ngpios;
uint8_t bit_per_gpio;
uint8_t off_val;
uint8_t on_val;
};
static int port_get(const struct device *dev,
gpio_port_value_t *value)
{
const struct creg_gpio_config *cfg = dev->config;
struct creg_gpio_drv_data *drv_data = dev->data;
uint32_t in = sys_read32(drv_data->base_addr);
uint32_t tmp = 0;
uint32_t val = 0;
for (uint8_t i = 0; i < cfg->ngpios; i++) {
tmp = (in & cfg->on_val << i * cfg->bit_per_gpio) ? 1 : 0;
val |= tmp << i;
}
*value = drv_data->pin_val = val;
return 0;
}
static int port_write(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value,
gpio_port_value_t toggle)
{
const struct creg_gpio_config *cfg = dev->config;
struct creg_gpio_drv_data *drv_data = dev->data;
uint32_t *pin_val = &drv_data->pin_val;
uint32_t out = 0;
uint32_t tmp = 0;
*pin_val = ((*pin_val & ~mask) | (value & mask)) ^ toggle;
for (uint8_t i = 0; i < cfg->ngpios; i++) {
tmp = (*pin_val & 1 << i) ? cfg->on_val : cfg->off_val;
out |= tmp << i * cfg->bit_per_gpio;
}
sys_write32(out, drv_data->base_addr);
return 0;
}
static int port_set_masked(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return port_write(dev, mask, value, 0);
}
static int port_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, pins, 0);
}
static int port_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, 0, 0);
}
static int port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, 0, 0, pins);
}
static int pin_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct creg_gpio_config *cfg = dev->config;
uint32_t io_flags;
bool pin_is_output;
/* Check for invalid pin number */
if (pin >= cfg->ngpios) {
return -EINVAL;
}
/* Does not support disconnected pin, and
* not supporting both input/output at same time.
*/
io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
if ((io_flags == GPIO_DISCONNECTED)
|| (io_flags == (GPIO_INPUT | GPIO_OUTPUT))) {
return -ENOTSUP;
}
/* No open-drain support */
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP;
}
/* Does not support pull-up/pull-down */
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
return -ENOTSUP;
}
pin_is_output = (flags & GPIO_OUTPUT) != 0U;
if (pin_is_output) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
return port_set_bits(dev, BIT(pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
return port_clear_bits(dev, BIT(pin));
}
}
return -ENOTSUP;
}
static const struct gpio_driver_api api_table = {
.pin_configure = pin_config,
.port_get_raw = port_get,
.port_set_masked_raw = port_set_masked,
.port_set_bits_raw = port_set_bits,
.port_clear_bits_raw = port_clear_bits,
.port_toggle_bits = port_toggle_bits,
};
static const struct creg_gpio_config creg_gpio_cfg = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
},
.ngpios = DT_INST_PROP(0, ngpios),
.bit_per_gpio = DT_INST_PROP(0, bit_per_gpio),
.off_val = DT_INST_PROP(0, off_val),
.on_val = DT_INST_PROP(0, on_val),
};
static struct creg_gpio_drv_data creg_gpio_drvdata = {
.base_addr = DT_INST_REG_ADDR(0),
};
DEVICE_DT_INST_DEFINE(0, NULL, NULL, &creg_gpio_drvdata, &creg_gpio_cfg,
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,
&api_table);
``` | /content/code_sandbox/drivers/gpio/gpio_creg_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,199 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_STM32_H_
#define ZEPHYR_DRIVERS_GPIO_GPIO_STM32_H_
/**
* @file header for STM32 GPIO
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/gpio.h>
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
#include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h>
#else
#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
/* GPIO buses definitions */
#define STM32_PORT_NOT_AVAILABLE 0xFFFFFFFF
#ifdef CONFIG_SOC_SERIES_STM32F0X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#elif CONFIG_SOC_SERIES_STM32F1X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_APB2
#define STM32_PERIPH_GPIOA LL_APB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_APB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_APB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_APB2_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_APB2_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_APB2_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_APB2_GRP1_PERIPH_GPIOG
#elif CONFIG_SOC_SERIES_STM32F2X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
#elif CONFIG_SOC_SERIES_STM32F3X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
#elif CONFIG_SOC_SERIES_STM32F4X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
#define STM32_PERIPH_GPIOJ LL_AHB1_GRP1_PERIPH_GPIOJ
#define STM32_PERIPH_GPIOK LL_AHB1_GRP1_PERIPH_GPIOK
#elif CONFIG_SOC_SERIES_STM32F7X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
#define STM32_PERIPH_GPIOJ LL_AHB1_GRP1_PERIPH_GPIOJ
#define STM32_PERIPH_GPIOK LL_AHB1_GRP1_PERIPH_GPIOK
#elif CONFIG_SOC_SERIES_STM32H7X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
#elif CONFIG_SOC_SERIES_STM32H7RSX
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOM LL_AHB4_GRP1_PERIPH_GPIOM
#define STM32_PERIPH_GPION LL_AHB4_GRP1_PERIPH_GPION
#define STM32_PERIPH_GPIOO LL_AHB4_GRP1_PERIPH_GPIOO
#define STM32_PERIPH_GPIOP LL_AHB4_GRP1_PERIPH_GPIOP
#elif CONFIG_SOC_SERIES_STM32G0X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_GPIOA LL_IOP_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_IOP_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_IOP_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_IOP_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_IOP_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_IOP_GRP1_PERIPH_GPIOF
#elif CONFIG_SOC_SERIES_STM32L0X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_GPIOA LL_IOP_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_IOP_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_IOP_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_IOP_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_IOP_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOH LL_IOP_GRP1_PERIPH_GPIOH
#elif CONFIG_SOC_SERIES_STM32L1X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
#elif CONFIG_SOC_SERIES_STM32L4X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
#elif CONFIG_SOC_SERIES_STM32L5X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#elif CONFIG_SOC_SERIES_STM32MP1X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
#elif CONFIG_SOC_SERIES_STM32WBX
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#elif CONFIG_SOC_SERIES_STM32G4X
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
#elif CONFIG_SOC_SERIES_STM32WLX
#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
#endif /* CONFIG_SOC_SERIES_* */
#ifdef CONFIG_SOC_SERIES_STM32F1X
#define STM32_PINCFG_MODE_OUTPUT (STM32_MODE_OUTPUT \
| STM32_CNF_GP_OUTPUT \
| STM32_CNF_PUSH_PULL)
#define STM32_PINCFG_MODE_INPUT STM32_MODE_INPUT
#define STM32_PINCFG_MODE_ANALOG (STM32_MODE_INPUT \
| STM32_CNF_IN_ANALOG)
#define STM32_PINCFG_PUSH_PULL STM32_CNF_PUSH_PULL
#define STM32_PINCFG_OPEN_DRAIN STM32_CNF_OPEN_DRAIN
#define STM32_PINCFG_PULL_UP (STM32_CNF_IN_PUPD | STM32_PUPD_PULL_UP)
#define STM32_PINCFG_PULL_DOWN (STM32_CNF_IN_PUPD | \
STM32_PUPD_PULL_DOWN)
#define STM32_PINCFG_FLOATING (STM32_CNF_IN_FLOAT | \
STM32_PUPD_NO_PULL)
#else
#define STM32_PINCFG_MODE_OUTPUT STM32_MODER_OUTPUT_MODE
#define STM32_PINCFG_MODE_INPUT STM32_MODER_INPUT_MODE
#define STM32_PINCFG_MODE_ANALOG STM32_MODER_ANALOG_MODE
#define STM32_PINCFG_PUSH_PULL STM32_OTYPER_PUSH_PULL
#define STM32_PINCFG_OPEN_DRAIN STM32_OTYPER_OPEN_DRAIN
#define STM32_PINCFG_PULL_UP STM32_PUPDR_PULL_UP
#define STM32_PINCFG_PULL_DOWN STM32_PUPDR_PULL_DOWN
#define STM32_PINCFG_FLOATING STM32_PUPDR_NO_PULL
#endif /* CONFIG_SOC_SERIES_STM32F1X */
#if defined(CONFIG_GPIO_GET_CONFIG) && !defined(CONFIG_SOC_SERIES_STM32F1X)
/**
* @brief structure of a GPIO pin (stm32 LL values) use to get the configuration
*/
struct gpio_stm32_pin {
unsigned int type; /* LL_GPIO_OUTPUT_PUSHPULL or LL_GPIO_OUTPUT_OPENDRAIN */
unsigned int pupd; /* LL_GPIO_PULL_NO or LL_GPIO_PULL_UP or LL_GPIO_PULL_DOWN */
unsigned int mode; /* LL_GPIO_MODE_INPUT or LL_GPIO_MODE_OUTPUT or other */
unsigned int out_state; /* 1 (high level) or 0 (low level) */
};
#endif /* CONFIG_GPIO_GET_CONFIG */
/**
* @brief configuration of GPIO device
*/
struct gpio_stm32_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* port base address */
uint32_t *base;
/* IO port */
int port;
struct stm32_pclken pclken;
};
/**
* @brief driver data
*/
struct gpio_stm32_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* device's owner of this data */
const struct device *dev;
/* user ISR cb */
sys_slist_t cb;
};
/**
* @brief helper for configuration of GPIO pin
*
* @param dev GPIO port device pointer
* @param pin IO pin
* @param conf GPIO mode
* @param func Pin function
*
* @return 0 on success, negative errno code on failure
*/
int gpio_stm32_configure(const struct device *dev, int pin, int conf, int func);
#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_STM32_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,713 |
```unknown
config GPIO_NXP_S32
bool "NXP S32 GPIO driver"
default y
depends on DT_HAS_NXP_S32_GPIO_ENABLED
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
Enable the GPIO driver for NXP S32 processors.
``` | /content/code_sandbox/drivers/gpio/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_rzt2m_gpio
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/errno_private.h>
#include <zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h>
#include <soc.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
static const struct device *const ns_portnf_md_dev = DEVICE_DT_GET(DT_NODELABEL(ns_portnf_md));
#define PMm_OFFSET 0x200
#define PMCm_OFFSET 0x400
#define PFCm_OFFSET 0x600
#define PINm_OFFSET 0x800
#define DRCTLm_OFFSET 0xa00
#define PMm_SIZE 0x2
#define DRCTLm_SIZE 0x8
#define PFCm_SIZE 0x4
/* config defines in include/zephyr/dt-bindings/gpio/renesas-rzt2m-gpio.h */
#define DRIVE_SHIFT 0
#define SCHMITT_TRIGGER_SHIFT 4
#define SLEW_RATE_SHIFT 5
#define PULL_SHIFT 2
#define PULL_NONE (0 << PULL_SHIFT)
#define PULL_UP (1 << PULL_SHIFT)
#define PULL_DOWN (2 << PULL_SHIFT)
#define INT_INVERT 0
#define INT_FALLING_EDGE 1
#define INT_RISING_EDGE 2
#define INT_BOTH_EDGE 3
#define IRQ_COUNT 16
#define NS_IRQ_COUNT 14
#define MAX_PORT_SIZE 8
#define RZT2M_GPIO_VALUE_IDENTITY(i, _) i
struct rzt2m_gpio_config {
struct gpio_driver_config common;
uint8_t pin_irqs[MAX_PORT_SIZE];
uint8_t *port_nsr;
uint8_t *ptadr;
uint8_t port;
};
struct rzt2m_gpio_data {
struct gpio_driver_data common;
sys_slist_t cb;
};
struct rzt2m_gpio_irq_slot {
const struct device *dev;
uint8_t pin;
};
struct rzt2m_gpio_common_data {
struct rzt2m_gpio_irq_slot irq_registered_ports[IRQ_COUNT];
};
static struct rzt2m_gpio_common_data rzt2m_gpio_common_data_inst;
static void rzt2m_gpio_unlock(void)
{
rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
rzt2m_unlock_prcrs(PRCRS_GPIO);
}
static void rzt2m_gpio_lock(void)
{
rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
rzt2m_lock_prcrs(PRCRS_GPIO);
}
/* Port m output data store */
static volatile uint8_t *rzt2m_gpio_get_p_reg(const struct device *dev)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint8_t *)(config->port_nsr + config->port);
}
/* Port m input data store */
static volatile uint8_t *rzt2m_gpio_get_pin_reg(const struct device *dev)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint8_t *)(config->port_nsr + PINm_OFFSET + config->port);
}
/* Port m mode register */
static volatile uint16_t *rzt2m_gpio_get_pm_reg(const struct device *dev)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint16_t *)(config->port_nsr + PMm_OFFSET + PMm_SIZE * config->port);
}
/* IO Buffer m function switching register */
static volatile uint64_t *rzt2m_gpio_get_drctl_reg(const struct device *dev)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint64_t *)(config->port_nsr + DRCTLm_OFFSET + DRCTLm_SIZE * config->port);
}
/* Port m region select register */
static volatile uint8_t *rzt2m_gpio_get_rselp_reg(const struct device *dev)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint8_t *)(config->ptadr + config->port);
}
/* Port m mode control register */
static volatile uint8_t *rzt2m_gpio_get_pmc_reg(const struct device *dev, uint8_t port)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint8_t *)(config->port_nsr + PMCm_OFFSET + port);
}
/* Port m function control register */
static volatile uint32_t *rzt2m_gpio_get_pfc_reg(const struct device *dev, uint8_t port)
{
const struct rzt2m_gpio_config *config = dev->config;
return (volatile uint32_t *)(config->port_nsr + PFCm_OFFSET + PFCm_SIZE * port);
}
static int rzt2m_gpio_init(const struct device *dev)
{
rzt2m_gpio_unlock();
volatile uint8_t *rselp_reg = rzt2m_gpio_get_rselp_reg(dev);
*rselp_reg = 0xFF;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_gpio_get_raw(const struct device *dev, gpio_port_value_t *value)
{
rzt2m_gpio_unlock();
volatile uint8_t *pin_reg = rzt2m_gpio_get_pin_reg(dev);
*value = *pin_reg;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
rzt2m_gpio_unlock();
volatile uint8_t *p_reg = rzt2m_gpio_get_p_reg(dev);
*p_reg = (*p_reg & ~mask) | (value & mask);
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
rzt2m_gpio_unlock();
volatile uint8_t *p_reg = rzt2m_gpio_get_p_reg(dev);
*p_reg |= pins;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
rzt2m_gpio_unlock();
volatile uint8_t *p_reg = rzt2m_gpio_get_p_reg(dev);
*p_reg &= ~pins;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_gpio_toggle(const struct device *dev, gpio_port_pins_t pins)
{
rzt2m_gpio_unlock();
volatile uint8_t *p_reg = rzt2m_gpio_get_p_reg(dev);
*p_reg ^= pins;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_gpio_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
volatile uint16_t *pm_reg = rzt2m_gpio_get_pm_reg(dev);
volatile uint64_t *drctl_reg = rzt2m_gpio_get_drctl_reg(dev);
rzt2m_gpio_unlock();
WRITE_BIT(*pm_reg, pin * 2, flags & GPIO_INPUT);
WRITE_BIT(*pm_reg, pin * 2 + 1, flags & GPIO_OUTPUT);
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_LOW) {
rzt2m_port_clear_bits_raw(dev, 1 << pin);
} else if (flags & GPIO_OUTPUT_INIT_HIGH) {
rzt2m_port_set_bits_raw(dev, 1 << pin);
}
}
if (flags & GPIO_PULL_UP && flags & GPIO_PULL_DOWN) {
rzt2m_gpio_lock();
return -EINVAL;
}
uint8_t drctl_pin_config = 0;
if (flags & GPIO_PULL_UP) {
drctl_pin_config |= PULL_UP;
} else if (flags & GPIO_PULL_DOWN) {
drctl_pin_config |= PULL_DOWN;
} else {
drctl_pin_config |= PULL_NONE;
}
drctl_pin_config |=
(flags & RZT2M_GPIO_DRIVE_MASK) >> (RZT2M_GPIO_DRIVE_OFFSET - DRIVE_SHIFT);
drctl_pin_config |= (flags & RZT2M_GPIO_SCHMITT_TRIGGER_MASK) >>
(RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET - SCHMITT_TRIGGER_SHIFT);
drctl_pin_config |= (flags & RZT2M_GPIO_SLEW_RATE_MASK) >>
(RZT2M_GPIO_SLEW_RATE_OFFSET - SLEW_RATE_SHIFT);
uint64_t drctl_pin_value = *drctl_reg & ~(0xFFULL << (pin * 8));
*drctl_reg = drctl_pin_value | ((uint64_t)drctl_pin_config << (pin * 8));
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_gpio_get_pin_irq(const struct device *dev, gpio_pin_t pin)
{
const struct rzt2m_gpio_config *config = dev->config;
if (pin >= MAX_PORT_SIZE) {
return -1;
}
return config->pin_irqs[pin] - 1;
}
static bool rzt2m_gpio_is_irq_used_by_other_pin(const struct device *dev, gpio_pin_t pin,
uint8_t irq)
{
if (irq >= IRQ_COUNT) {
return false;
}
if (rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev == NULL) {
return false;
}
if (rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev != dev) {
return true;
}
return rzt2m_gpio_common_data_inst.irq_registered_ports[irq].pin != pin;
}
static void rzt2m_gpio_isr(uint8_t *irq_n)
{
const struct device *dev = rzt2m_gpio_common_data_inst.irq_registered_ports[*irq_n].dev;
if (dev) {
struct rzt2m_gpio_data *data = dev->data;
int irq_pin = rzt2m_gpio_common_data_inst.irq_registered_ports[*irq_n].pin;
if (irq_pin >= 0) {
gpio_fire_callbacks(&data->cb, dev, 1 << irq_pin);
}
}
}
static int rzt2m_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct rzt2m_gpio_config *config = dev->config;
volatile uint8_t *pmc_reg = rzt2m_gpio_get_pmc_reg(dev, config->port);
volatile uint32_t *pfc_reg = rzt2m_gpio_get_pfc_reg(dev, config->port);
uint32_t ns_portnf_md_val = 0;
syscon_read_reg(ns_portnf_md_dev, 0, &ns_portnf_md_val);
/* level interrupts are not supported */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
uint8_t irq = rzt2m_gpio_get_pin_irq(dev, pin);
bool irq_used_by_other = rzt2m_gpio_is_irq_used_by_other_pin(dev, pin, irq);
if (irq < 0) {
return -ENOTSUP;
}
/* secure range - currently not supported*/
if (irq >= NS_IRQ_COUNT) {
return -ENOSYS;
}
if (mode == GPIO_INT_MODE_DISABLED) {
rzt2m_gpio_unlock();
WRITE_BIT(*pmc_reg, pin, 0);
/* check if selected pin is using irq line to avoid unregistering other pin irq
* handler
*/
if (!irq_used_by_other) {
rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev = NULL;
}
rzt2m_gpio_lock();
return 0;
}
/* the irq line is used by another pin */
if (irq_used_by_other) {
return -EBUSY;
}
uint8_t md_mode = 0x0;
switch (trig) {
case GPIO_INT_TRIG_LOW:
md_mode = INT_FALLING_EDGE;
break;
case GPIO_INT_TRIG_HIGH:
md_mode = INT_RISING_EDGE;
break;
case GPIO_INT_TRIG_BOTH:
md_mode = INT_BOTH_EDGE;
break;
default:
return -EINVAL;
}
rzt2m_gpio_unlock();
uint32_t mdx_mask =
~((uint32_t)0b11 << irq); /* description of interrupt type has length of 2 bits */
ns_portnf_md_val = (ns_portnf_md_val & mdx_mask) | (md_mode << irq);
syscon_write_reg(ns_portnf_md_dev, 0, ns_portnf_md_val); /* set interrupt type */
WRITE_BIT(*pmc_reg, pin, 1); /* enable special function on selected pin */
/* in case of every pin on every port irq function number is 0 */
*pfc_reg &= ~((uint32_t)0b1111 << pin * 4);
/* register handling interrupt in isr for selected port and pin */
rzt2m_gpio_common_data_inst.irq_registered_ports[irq].dev = dev;
rzt2m_gpio_common_data_inst.irq_registered_ports[irq].pin = pin;
rzt2m_gpio_lock();
return 0;
}
static int rzt2m_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, bool set)
{
struct rzt2m_gpio_data *data = dev->data;
return gpio_manage_callback(&data->cb, cb, set);
}
static const struct gpio_driver_api rzt2m_gpio_driver_api = {
.pin_configure = rzt2m_gpio_configure,
.port_get_raw = rzt2m_gpio_get_raw,
.port_set_masked_raw = rzt2m_port_set_masked_raw,
.port_set_bits_raw = rzt2m_port_set_bits_raw,
.port_clear_bits_raw = rzt2m_port_clear_bits_raw,
.port_toggle_bits = rzt2m_gpio_toggle,
.pin_interrupt_configure = rzt2m_gpio_pin_interrupt_configure,
.manage_callback = rzt2m_gpio_manage_callback};
#define RZT2M_INIT_IRQ(irq_n) \
IRQ_CONNECT(DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, irq), \
DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, priority), \
rzt2m_gpio_isr, &n[irq_n], \
DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, flags)) \
irq_enable(DT_IRQ_BY_IDX(DT_INST(0, renesas_rzt2m_gpio_common), irq_n, irq));
static int rzt2m_gpio_common_init(const struct device *dev)
{
struct rzt2m_gpio_common_data *data = dev->data;
static uint8_t n[IRQ_COUNT];
for (int i = 0; i < ARRAY_SIZE(n); i++) {
n[i] = i;
data->irq_registered_ports[i].dev = NULL;
}
FOR_EACH(RZT2M_INIT_IRQ, (), LISTIFY(NS_IRQ_COUNT, RZT2M_GPIO_VALUE_IDENTITY, (,)))
return 0;
}
DEVICE_DT_DEFINE(DT_INST(0, renesas_rzt2m_gpio_common),
rzt2m_gpio_common_init,
NULL,
&rzt2m_gpio_common_data_inst, NULL,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
NULL);
#define VALUE_2X(i, _) UTIL_X2(i)
#define PIN_IRQ_INITIALIZER(idx, inst) \
COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \
([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \
DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)) + 1,), \
())
#define PORT_IRQS_INITIALIZER(inst) \
FOR_EACH_FIXED_ARG(PIN_IRQ_INITIALIZER, (), inst, \
LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
#define RZT2M_GPIO_DEFINE(inst) \
static struct rzt2m_gpio_data rzt2m_gpio_data##inst; \
static struct rzt2m_gpio_config rzt2m_gpio_config##inst = { \
.port_nsr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_GPARENT(inst), port_nsr), \
.ptadr = (uint8_t *)DT_REG_ADDR_BY_NAME(DT_INST_GPARENT(inst), ptadr), \
.port = DT_INST_REG_ADDR(inst), \
.pin_irqs = {PORT_IRQS_INITIALIZER(inst)}, \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)}}; \
DEVICE_DT_INST_DEFINE(inst, rzt2m_gpio_init, NULL, &rzt2m_gpio_data##inst, \
&rzt2m_gpio_config##inst, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&rzt2m_gpio_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RZT2M_GPIO_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_rzt2m.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,793 |
```c
/*
*
*/
#define DT_DRV_COMPAT sifive_gpio0
/**
* @file GPIO driver for the SiFive Freedom Processor
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/util.h>
#include <zephyr/irq.h>
#include <zephyr/irq_multilevel.h>
#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
typedef void (*sifive_cfg_func_t)(void);
/* sifive GPIO register-set structure */
struct gpio_sifive_t {
unsigned int in_val;
unsigned int in_en;
unsigned int out_en;
unsigned int out_val;
unsigned int pue;
unsigned int ds;
unsigned int rise_ie;
unsigned int rise_ip;
unsigned int fall_ie;
unsigned int fall_ip;
unsigned int high_ie;
unsigned int high_ip;
unsigned int low_ie;
unsigned int low_ip;
unsigned int iof_en;
unsigned int iof_sel;
unsigned int invert;
};
struct gpio_sifive_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uintptr_t gpio_base_addr;
/* multi-level encoded interrupt corresponding to pin 0 */
uint32_t gpio_irq_base;
sifive_cfg_func_t gpio_cfg_func;
};
struct gpio_sifive_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of callbacks */
sys_slist_t cb;
};
/* Helper Macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct gpio_sifive_config * const)(dev)->config)
#define DEV_GPIO(dev) \
((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
#define DEV_GPIO_DATA(dev) \
((struct gpio_sifive_data *)(dev)->data)
/* Given gpio_irq_base and the pin number, return the IRQ number for the pin */
static inline unsigned int gpio_sifive_pin_irq(unsigned int base_irq, int pin)
{
unsigned int level = irq_get_level(base_irq);
unsigned int pin_irq = 0;
if (level == 1) {
pin_irq = base_irq + pin;
} else if (level == 2) {
pin_irq = base_irq + (pin << CONFIG_1ST_LEVEL_INTERRUPT_BITS);
}
return pin_irq;
}
/* Given the PLIC source number, return the number of the GPIO pin associated
* with the interrupt
*/
static inline int gpio_sifive_plic_to_pin(unsigned int base_irq, int plic_irq)
{
unsigned int level = irq_get_level(base_irq);
if (level == 2) {
base_irq = irq_from_level_2(base_irq);
}
return (plic_irq - base_irq);
}
static void gpio_sifive_irq_handler(const struct device *dev)
{
struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
/* Calculate pin and mask from base level 2 line */
uint8_t pin = 1 + (riscv_plic_get_irq() -
(uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS));
/* This peripheral tracks each condition separately: a
* transition from low to high will mark the pending bit for
* both rise and high, while low will probably be set from the
* previous state.
*
* It is certainly possible, especially on double-edge, that
* multiple conditions are present. However, there is no way
* to tell which one occurred first, and no provision to
* indicate which one occurred in the callback.
*
* Clear all the conditions so we only invoke the callback
* once. Level conditions will remain set after clear.
*/
gpio->rise_ip = BIT(pin);
gpio->fall_ip = BIT(pin);
gpio->high_ip = BIT(pin);
gpio->low_ip = BIT(pin);
/* Call the corresponding callback registered for the pin */
gpio_fire_callbacks(&data->cb, dev, BIT(pin));
}
/**
* @brief Configure pin
*
* @param dev Device structure
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_sifive_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
/* We cannot support open-source open-drain configuration */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* We only support pull-ups, not pull-downs */
if ((flags & GPIO_PULL_DOWN) != 0) {
return -ENOTSUP;
}
/* Set pull-up if requested */
WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP);
/* Set the initial output value before enabling output to avoid
* glitches
*/
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio->out_val |= BIT(pin);
}
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio->out_val &= ~BIT(pin);
}
/* Enable input/output */
WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT);
WRITE_BIT(gpio->in_en, pin, flags & GPIO_INPUT);
return 0;
}
static int gpio_sifive_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
*value = gpio->in_val;
return 0;
}
static int gpio_sifive_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
gpio->out_val = (gpio->out_val & ~mask) | (value & mask);
return 0;
}
static int gpio_sifive_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
gpio->out_val |= mask;
return 0;
}
static int gpio_sifive_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
gpio->out_val &= ~mask;
return 0;
}
static int gpio_sifive_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
gpio->out_val ^= mask;
return 0;
}
static int gpio_sifive_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
gpio->rise_ie &= ~BIT(pin);
gpio->fall_ie &= ~BIT(pin);
gpio->high_ie &= ~BIT(pin);
gpio->low_ie &= ~BIT(pin);
switch (mode) {
case GPIO_INT_MODE_DISABLED:
irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
break;
case GPIO_INT_MODE_LEVEL:
/* Board supports both levels, but Zephyr does not. */
if (trig == GPIO_INT_TRIG_HIGH) {
gpio->high_ip = BIT(pin);
gpio->high_ie |= BIT(pin);
} else {
__ASSERT_NO_MSG(trig == GPIO_INT_TRIG_LOW);
gpio->low_ip = BIT(pin);
gpio->low_ie |= BIT(pin);
}
irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
break;
case GPIO_INT_MODE_EDGE:
__ASSERT_NO_MSG(GPIO_INT_TRIG_BOTH ==
(GPIO_INT_LOW_0 | GPIO_INT_HIGH_1));
if ((trig & GPIO_INT_HIGH_1) != 0) {
gpio->rise_ip = BIT(pin);
gpio->rise_ie |= BIT(pin);
}
if ((trig & GPIO_INT_LOW_0) != 0) {
gpio->fall_ip = BIT(pin);
gpio->fall_ie |= BIT(pin);
}
irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));
break;
default:
__ASSERT(false, "Invalid MODE %d passed to driver", mode);
return -ENOTSUP;
}
return 0;
}
static int gpio_sifive_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
return gpio_manage_callback(&data->cb, callback, set);
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_sifive_port_get_dir(const struct device *dev, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
map &= cfg->common.port_pin_mask;
if (inputs != NULL) {
*inputs = map & DEV_GPIO(dev)->in_en;
}
if (outputs != NULL) {
*outputs = map & DEV_GPIO(dev)->out_en;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_sifive_driver = {
.pin_configure = gpio_sifive_config,
.port_get_raw = gpio_sifive_port_get_raw,
.port_set_masked_raw = gpio_sifive_port_set_masked_raw,
.port_set_bits_raw = gpio_sifive_port_set_bits_raw,
.port_clear_bits_raw = gpio_sifive_port_clear_bits_raw,
.port_toggle_bits = gpio_sifive_port_toggle_bits,
.pin_interrupt_configure = gpio_sifive_pin_interrupt_configure,
.manage_callback = gpio_sifive_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_sifive_port_get_dir,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
/**
* @brief Initialize a GPIO controller
*
* Perform basic initialization of a GPIO controller
*
* @param dev GPIO device struct
*
* @return 0
*/
static int gpio_sifive_init(const struct device *dev)
{
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
/* Ensure that all gpio registers are reset to 0 initially */
gpio->in_en = 0U;
gpio->out_en = 0U;
gpio->pue = 0U;
gpio->rise_ie = 0U;
gpio->fall_ie = 0U;
gpio->high_ie = 0U;
gpio->low_ie = 0U;
gpio->iof_en = 0U;
gpio->iof_sel = 0U;
gpio->invert = 0U;
/* Setup IRQ handler for each gpio pin */
cfg->gpio_cfg_func();
return 0;
}
static void gpio_sifive_cfg_0(void);
static const struct gpio_sifive_config gpio_sifive_config0 = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
},
.gpio_base_addr = DT_INST_REG_ADDR(0),
.gpio_irq_base = DT_INST_IRQN(0),
.gpio_cfg_func = gpio_sifive_cfg_0,
};
static struct gpio_sifive_data gpio_sifive_data0;
DEVICE_DT_INST_DEFINE(0,
gpio_sifive_init,
NULL,
&gpio_sifive_data0, &gpio_sifive_config0,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_sifive_driver);
#define IRQ_INIT(n) \
IRQ_CONNECT(DT_INST_IRQN_BY_IDX(0, n), \
DT_INST_IRQ_BY_IDX(0, n, priority), \
gpio_sifive_irq_handler, \
DEVICE_DT_INST_GET(0), \
0);
static void gpio_sifive_cfg_0(void)
{
#if DT_INST_IRQ_HAS_IDX(0, 0)
IRQ_INIT(0);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 1)
IRQ_INIT(1);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 2)
IRQ_INIT(2);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 3)
IRQ_INIT(3);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 4)
IRQ_INIT(4);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 5)
IRQ_INIT(5);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 6)
IRQ_INIT(6);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 7)
IRQ_INIT(7);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 8)
IRQ_INIT(8);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 9)
IRQ_INIT(9);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 10)
IRQ_INIT(10);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 11)
IRQ_INIT(11);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 12)
IRQ_INIT(12);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 13)
IRQ_INIT(13);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 14)
IRQ_INIT(14);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 15)
IRQ_INIT(15);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 16)
IRQ_INIT(16);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 17)
IRQ_INIT(17);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 18)
IRQ_INIT(18);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 19)
IRQ_INIT(19);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 20)
IRQ_INIT(20);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 21)
IRQ_INIT(21);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 22)
IRQ_INIT(22);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 23)
IRQ_INIT(23);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 24)
IRQ_INIT(24);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 25)
IRQ_INIT(25);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 26)
IRQ_INIT(26);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 27)
IRQ_INIT(27);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 28)
IRQ_INIT(28);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 29)
IRQ_INIT(29);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 30)
IRQ_INIT(30);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 31)
IRQ_INIT(31);
#endif
}
``` | /content/code_sandbox/drivers/gpio/gpio_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,318 |
```unknown
config GPIO_MAX32
bool "GPIO Driver for MAX32 family of MCUs"
default y
depends on DT_HAS_ADI_MAX32_GPIO_ENABLED
help
Enable GPIO driver for MAX32 line of MCUs
``` | /content/code_sandbox/drivers/gpio/Kconfig.max32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
# CY8C95XX GPIO configuration options
menuconfig GPIO_CY8C95XX
bool "CY8C95XX I2C GPIO chip"
default y
depends on DT_HAS_CYPRESS_CY8C95XX_GPIO_PORT_ENABLED
depends on I2C
help
Enable driver for CY8C95XX I2C GPIO chip.
if GPIO_CY8C95XX
config GPIO_CY8C95XX_INIT_PRIORITY
int "Init priority"
default 70
help
Device driver initialization priority.
endif # GPIO_CY8C95XX
``` | /content/code_sandbox/drivers/gpio/Kconfig.cy8c95xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_tca6424a
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(gpio_tca6424a, CONFIG_GPIO_LOG_LEVEL);
/* TCA6424A auto increment register addresses */
#define TCA6424A_REG_INPUT 0x80
#define TCA6424A_REG_OUTPUT 0x84
#define TCA6424A_REG_POLARITY_INVERSION 0x88
#define TCA6424A_REG_CONFIGURATION 0x8C
/** Cache of the output configuration and data of the pins. */
struct tca6424a_pins_state {
uint32_t input;
uint32_t output;
uint32_t config;
};
struct tca6424a_irq_state {
uint32_t rising;
uint32_t falling;
};
/** Configuration data */
struct tca6424a_drv_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec i2c_spec;
struct gpio_dt_spec int_gpio;
struct gpio_dt_spec reset_gpio;
};
/** Runtime driver data */
struct tca6424a_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t callbacks;
struct k_sem lock;
struct k_work work;
const struct device *dev;
struct gpio_callback int_gpio_cb;
struct tca6424a_pins_state pins_state;
struct tca6424a_irq_state irq_state;
};
/**
* @brief Gets the state of a specified block of 3 registers from the TCA6424A
* and stores it in specified cache and buffer variables.
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Address of the first of 3 registers to be read.
* @param cache Pointer to the location to cache the pins states.
* @param buf Pointer to the buffer to output the register.
*
* @retval 0 if successful.
* @retval Negative value for error code.
*/
static int read_port_regs(const struct device *dev, uint8_t reg, uint32_t *buf)
{
const struct tca6424a_drv_cfg *const config = dev->config;
uint32_t port_data, value;
int ret;
ret = i2c_burst_read_dt(&config->i2c_spec, reg, (uint8_t *)&port_data, 3);
if (ret != 0) {
LOG_ERR("%s: error reading register 0x%X (%d)", dev->name,
reg, ret);
return ret;
}
value = sys_le24_to_cpu(port_data);
*buf = value;
LOG_DBG("%s: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X, "
"REG[0x%X] = 0x%X",
dev->name, reg, (*buf & 0xFF), (reg + 1), ((*buf >> 8) & 0xFF),
(reg + 2), ((*buf >> 16) & 0xFF));
return 0;
}
/**
* @brief writes to a specified block of 3 registers from the TCA6424A
* and stores it in a specified cache variable.
*
* @param dev Pointer to the device structure for the driver instance.
* @param reg Address of the first of 3 registers to be written.
* @param cache Pointer to the location to cache the pins states.
* @param value The pin value to be written into the registers.
*
* @retval 0 if successful.
* @retval Negative value for error code.
*/
static int write_port_regs(const struct device *dev, uint8_t reg, uint32_t value)
{
const struct tca6424a_drv_cfg *const config = dev->config;
uint8_t buf[4];
int ret;
LOG_DBG("%s: Write: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X, "
"REG[0x%X] = 0x%X",
dev->name, reg, (value & 0xFF), (reg + 1), ((value >> 8) & 0xFF),
(reg + 2), ((value >> 16) & 0xFF));
buf[0] = reg;
sys_put_le24(value, &buf[1]);
ret = i2c_write_dt(&config->i2c_spec, buf, sizeof(buf));
if (ret != 0) {
LOG_ERR("%s: error writing to register 0x%X "
"(%d)",
dev->name, reg, ret);
}
return ret;
}
static inline int update_input_regs(const struct device *dev, uint32_t *buf)
{
int ret;
struct tca6424a_drv_data *const drv_data = dev->data;
ret = read_port_regs(dev, TCA6424A_REG_INPUT, buf);
if (ret == 0) {
drv_data->pins_state.input = *buf;
}
return ret;
}
static inline int update_output_regs(const struct device *dev, uint32_t value)
{
int ret;
struct tca6424a_drv_data *const drv_data = dev->data;
ret = write_port_regs(dev, TCA6424A_REG_OUTPUT, value);
if (ret == 0) {
drv_data->pins_state.output = value;
}
return ret;
}
static inline int update_invers_regs(const struct device *dev, uint32_t value)
{
return write_port_regs(dev, TCA6424A_REG_POLARITY_INVERSION, value);
}
static inline int update_config_regs(const struct device *dev, uint32_t value)
{
int ret;
struct tca6424a_drv_data *const drv_data = dev->data;
ret = write_port_regs(dev, TCA6424A_REG_CONFIGURATION, value);
if (ret == 0) {
drv_data->pins_state.config = value;
}
return ret;
}
/**
* @brief Handles interrupt triggered by the interrupt pin of TCA6424A.
*
* If int_gpios is configured in device tree then this will be triggered each
* time a gpio configured as an input changes state. The gpio input states are
* read in this function which clears the interrupt.
*
* @param dev Pointer to the device structure for the driver instance.
*/
static void tca6424a_handle_interrupt(const struct device *dev)
{
struct tca6424a_drv_data *drv_data = dev->data;
struct tca6424a_irq_state *irq_state = &drv_data->irq_state;
int ret;
uint32_t previous_state;
uint32_t current_state;
uint32_t transitioned_pins;
uint32_t interrupt_status;
k_sem_take(&drv_data->lock, K_FOREVER);
/* Any interrupts enabled? */
if (!irq_state->rising && !irq_state->falling) {
k_sem_give(&drv_data->lock);
return;
}
/* Store previous input state then read new value */
previous_state = drv_data->pins_state.input;
ret = update_input_regs(dev, ¤t_state);
if (ret != 0) {
k_sem_give(&drv_data->lock);
return;
}
/* Find out which input pins have changed state */
transitioned_pins = previous_state ^ current_state;
/* Mask gpio transactions with rising/falling edge interrupt config */
interrupt_status = (irq_state->rising & transitioned_pins & current_state);
interrupt_status |= (irq_state->falling & transitioned_pins & previous_state);
k_sem_give(&drv_data->lock);
if (interrupt_status) {
gpio_fire_callbacks(&drv_data->callbacks, dev, interrupt_status);
}
}
/**
* @brief Work handler for TCA6424A interrupt
*
* @param work Work struct that contains pointer to interrupt handler function
*/
static void tca6424a_work_handler(struct k_work *work)
{
struct tca6424a_drv_data *drv_data = CONTAINER_OF(work, struct tca6424a_drv_data, work);
tca6424a_handle_interrupt(drv_data->dev);
}
/**
* @brief ISR for interrupt pin of TCA6424A
*
* @param dev Pointer to the device structure for the driver instance.
* @param gpio_cb Pointer to callback function struct
* @param pins Bitmask of pins that triggered interrupt
*/
static void tca6424a_int_gpio_handler(const struct device *dev, struct gpio_callback *gpio_cb,
uint32_t pins)
{
ARG_UNUSED(dev);
ARG_UNUSED(pins);
struct tca6424a_drv_data *drv_data =
CONTAINER_OF(gpio_cb, struct tca6424a_drv_data, int_gpio_cb);
k_work_submit(&drv_data->work);
}
static int tca6424a_setup_pin(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
struct tca6424a_drv_data *const drv_data = dev->data;
uint32_t reg_cfg = drv_data->pins_state.config;
uint32_t reg_out = drv_data->pins_state.output;
int ret;
/* For each pin, 0 == output, 1 == input */
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
reg_out |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
reg_out &= ~BIT(pin);
}
ret = update_output_regs(dev, reg_out);
if (ret != 0) {
return ret;
}
reg_cfg &= ~BIT(pin);
} else {
reg_cfg |= BIT(pin);
}
ret = update_config_regs(dev, reg_cfg);
return ret;
}
static int tca6424a_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
int ret;
struct tca6424a_drv_data *const drv_data = dev->data;
/* Does not support disconnected pin */
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
/* Single Ended lines (Open drain and open source) not supported */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* The TCA6424A has no internal pull up support */
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
return -ENOTSUP;
}
/* Simultaneous input & output mode not supported */
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = tca6424a_setup_pin(dev, pin, flags);
if (ret != 0) {
LOG_ERR("%s: error setting pin direction (%d)", dev->name, ret);
}
k_sem_give(&drv_data->lock);
return ret;
}
static int tca6424a_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
struct tca6424a_drv_data *const drv_data = dev->data;
uint32_t buf;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = update_input_regs(dev, &buf);
if (ret == 0) {
*value = buf;
}
k_sem_give(&drv_data->lock);
return ret;
}
static int tca6424a_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
struct tca6424a_drv_data *const drv_data = dev->data;
uint32_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->pins_state.output;
reg_out = (reg_out & ~mask) | (mask & value);
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
static int tca6424a_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
return tca6424a_port_set_masked_raw(dev, mask, mask);
}
static int tca6424a_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
return tca6424a_port_set_masked_raw(dev, mask, 0);
}
static int tca6424a_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask)
{
struct tca6424a_drv_data *const drv_data = dev->data;
uint32_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->pins_state.output;
reg_out ^= mask;
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
static int tca6424a_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
struct tca6424a_drv_data *drv_data = dev->data;
struct tca6424a_irq_state *irq = &drv_data->irq_state;
/* Device does not support level-triggered interrupts. */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
if (mode == GPIO_INT_MODE_DISABLED) {
irq->falling &= ~BIT(pin);
irq->rising &= ~BIT(pin);
} else { /* GPIO_INT_MODE_EDGE */
if (trig == GPIO_INT_TRIG_BOTH) {
irq->falling |= BIT(pin);
irq->rising |= BIT(pin);
} else if (trig == GPIO_INT_TRIG_LOW) {
irq->falling |= BIT(pin);
irq->rising &= ~BIT(pin);
} else if (trig == GPIO_INT_TRIG_HIGH) {
irq->falling &= ~BIT(pin);
irq->rising |= BIT(pin);
}
}
k_sem_give(&drv_data->lock);
return 0;
}
static int tca6424a_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct tca6424a_drv_data *drv_data = dev->data;
return gpio_manage_callback(&drv_data->callbacks, callback, set);
}
static const struct gpio_driver_api tca6424a_drv_api = {
.pin_configure = tca6424a_pin_config,
.port_get_raw = tca6424a_port_get_raw,
.port_set_masked_raw = tca6424a_port_set_masked_raw,
.port_set_bits_raw = tca6424a_port_set_bits_raw,
.port_clear_bits_raw = tca6424a_port_clear_bits_raw,
.port_toggle_bits = tca6424a_port_toggle_bits,
.pin_interrupt_configure = tca6424a_pin_interrupt_configure,
.manage_callback = tca6424a_manage_callback,
};
/**
* @brief Initialization function of TCA6424A
*
* This sets initial input/output configuration and output states.
* The interrupt is configured if it is enabled.
*
* @param dev Device struct
*
* @retval 0 if successful.
* @retval Negative value for error code.
*/
static int tca6424a_init(const struct device *dev)
{
const struct tca6424a_drv_cfg *drv_cfg = dev->config;
struct tca6424a_drv_data *drv_data = dev->data;
int ret;
if (!device_is_ready(drv_cfg->i2c_spec.bus)) {
LOG_ERR("I2C device not found");
return -ENODEV;
}
/* If the RESET line is available, use it to reset the expander.
* Otherwise, write reset values to registers that are not used by
* this driver.
*/
if (drv_cfg->reset_gpio.port) {
if (!gpio_is_ready_dt(&drv_cfg->reset_gpio)) {
LOG_ERR("%s is not ready", drv_cfg->reset_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&drv_cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
if (ret != 0) {
LOG_ERR("%s: failed to configure RESET line: %d", dev->name, ret);
return ret;
}
/* RESET signal needs to be active for a minimum of 30 ns. */
k_busy_wait(1);
ret = gpio_pin_set_dt(&drv_cfg->reset_gpio, 0);
if (ret != 0) {
LOG_ERR("%s: failed to deactivate RESET line: %d", dev->name, ret);
return ret;
}
/* Give the expander at least 200 ns to recover after reset. */
k_busy_wait(1);
} else {
ret = update_invers_regs(dev, 0x0);
if (ret != 0) {
LOG_ERR("%s: failed to reset inversion register: %d", dev->name, ret);
return ret;
}
}
/* Set initial configuration of the pins. */
ret = update_config_regs(dev, 0xFFFFFF);
if (ret != 0) {
return ret;
}
ret = update_output_regs(dev, 0x0);
if (ret != 0) {
return ret;
}
/* Read initial state of the input port register. */
ret = update_input_regs(dev, &drv_data->pins_state.input);
if (ret != 0) {
LOG_ERR("%s: failed to initially read input port: %d", dev->name, ret);
return ret;
}
/* If the INT line is available, configure the callback for it. */
if (drv_cfg->int_gpio.port) {
if (!gpio_is_ready_dt(&drv_cfg->int_gpio)) {
LOG_ERR("Cannot get pointer to gpio interrupt device "
"%s init failed", dev->name);
return -EINVAL;
}
drv_data->dev = dev;
k_work_init(&drv_data->work, tca6424a_work_handler);
ret = gpio_pin_configure_dt(&drv_cfg->int_gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("%s init failed: %d", dev->name, ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&drv_cfg->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
LOG_ERR("%s init failed: %d", dev->name, ret);
return ret;
}
gpio_init_callback(&drv_data->int_gpio_cb, tca6424a_int_gpio_handler,
BIT(drv_cfg->int_gpio.pin));
ret = gpio_add_callback(drv_cfg->int_gpio.port, &drv_data->int_gpio_cb);
if (ret != 0) {
LOG_ERR("%s init failed: %d", dev->name, ret);
return ret;
}
}
LOG_DBG("%s init ok", dev->name);
return ret;
}
#define TCA6424A_INST(idx) \
static const struct tca6424a_drv_cfg tca6424a_cfg##idx = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
}, \
.i2c_spec = I2C_DT_SPEC_INST_GET(idx), \
.int_gpio = GPIO_DT_SPEC_INST_GET_OR(idx, int_gpios, {0}), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(idx, reset_gpios, {0}), \
}; \
static struct tca6424a_drv_data tca6424a_data##idx = { \
.lock = Z_SEM_INITIALIZER(tca6424a_data##idx.lock, 1, 1), \
.work = Z_WORK_INITIALIZER(tca6424a_work_handler), \
.dev = DEVICE_DT_INST_GET(idx), \
}; \
DEVICE_DT_INST_DEFINE(idx, tca6424a_init, NULL, &tca6424a_data##idx, &tca6424a_cfg##idx, \
POST_KERNEL, CONFIG_GPIO_TCA6424A_INIT_PRIORITY, &tca6424a_drv_api);
DT_INST_FOREACH_STATUS_OKAY(TCA6424A_INST)
``` | /content/code_sandbox/drivers/gpio/gpio_tca6424a.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,595 |
```c
/*
*
*/
#define DT_DRV_COMPAT ite_it8xxx2_gpiokscan
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
struct gpio_kscan_cfg {
/* The gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
volatile uint8_t *reg_ksi_kso_goen;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
volatile uint8_t *reg_ksi_kso_gctrl;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
volatile uint8_t *reg_ksi_kso_gdat;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
volatile uint8_t *reg_ksi_kso_gdmr;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
volatile uint8_t *reg_ksi_kso_gpod;
};
struct gpio_kscan_data {
/* The gpio_driver_data needs to be first */
struct gpio_driver_data common;
};
static int gpio_kscan_it8xxx2_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl;
volatile uint8_t *reg_ksi_kso_goen = config->reg_ksi_kso_goen;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
volatile uint8_t *reg_ksi_kso_gpod = config->reg_ksi_kso_gpod;
uint8_t mask = BIT(pin);
/* KSI[7:0]/KSO[15:8]/KSO[7:0] pins don't support open source, 1.8V and 5.0V mode */
if ((((flags & GPIO_SINGLE_ENDED) != 0) && ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) ||
((flags & IT8XXX2_GPIO_VOLTAGE_MASK) == IT8XXX2_GPIO_VOLTAGE_1P8) ||
((flags & IT8XXX2_GPIO_VOLTAGE_MASK) == IT8XXX2_GPIO_VOLTAGE_5P0)) {
return -ENOTSUP;
}
/* Set GPIO mode */
*reg_ksi_kso_gctrl |= mask;
if (flags & GPIO_OUTPUT) {
/*
* Select open drain first, so that we don't glitch the signal
* when changing the line to an output.
*/
if (flags & GPIO_OPEN_DRAIN) {
/* Set open-drain and enable internal pullup */
*reg_ksi_kso_gpod |= mask;
} else {
/* Set push-pull and disable internal pullup */
*reg_ksi_kso_gpod &= ~mask;
}
unsigned int key = irq_lock();
/* Set level before change to output */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
*reg_ksi_kso_gdat |= mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
*reg_ksi_kso_gdat &= ~mask;
}
irq_unlock(key);
/* Set output mode */
*reg_ksi_kso_goen |= mask;
} else {
/* Set input mode */
*reg_ksi_kso_goen &= ~mask;
if (flags & GPIO_PULL_UP) {
/* Enable internal pullup */
*reg_ksi_kso_gpod |= mask;
} else {
/* No internal pullup and pulldown */
*reg_ksi_kso_gpod &= ~mask;
}
}
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_kscan_it8xxx2_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_goen = config->reg_ksi_kso_goen;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
volatile uint8_t *reg_ksi_kso_gpod = config->reg_ksi_kso_gpod;
uint8_t mask = BIT(pin);
gpio_flags_t flags = 0;
/* KSI[7:0]/KSO[15:8]/KSO[7:0] pins only support 3.3V */
flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
/* Input or output */
if (*reg_ksi_kso_goen & mask) {
flags |= GPIO_OUTPUT;
/* Open-drain or push-pull */
if (*reg_ksi_kso_gpod & mask) {
flags |= GPIO_OPEN_DRAIN;
}
/* High or low */
if (*reg_ksi_kso_gdat & mask) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
} else {
flags |= GPIO_INPUT;
/* pullup or no pull */
if (*reg_ksi_kso_gpod & mask) {
flags |= GPIO_PULL_UP;
}
}
*out_flags = flags;
return 0;
}
#endif
static int gpio_kscan_it8xxx2_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gdmr = config->reg_ksi_kso_gdmr;
/* Get physical level from all pins of the port */
*value = *reg_ksi_kso_gdmr;
return 0;
}
static int gpio_kscan_it8xxx2_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
unsigned int key = irq_lock();
uint8_t out = *reg_ksi_kso_gdat;
/* Set high/low level to mask pins of the port */
*reg_ksi_kso_gdat = ((out & ~mask) | (value & mask));
irq_unlock(key);
return 0;
}
static int gpio_kscan_it8xxx2_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
unsigned int key = irq_lock();
/* Set high level to pins of the port */
*reg_ksi_kso_gdat |= pins;
irq_unlock(key);
return 0;
}
static int gpio_kscan_it8xxx2_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
unsigned int key = irq_lock();
/* Set low level to pins of the port */
*reg_ksi_kso_gdat &= ~pins;
irq_unlock(key);
return 0;
}
static int gpio_kscan_it8xxx2_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_kscan_cfg *const config = dev->config;
volatile uint8_t *reg_ksi_kso_gdat = config->reg_ksi_kso_gdat;
unsigned int key = irq_lock();
/* Toggle output level to pins of the port */
*reg_ksi_kso_gdat ^= pins;
irq_unlock(key);
return 0;
}
static const struct gpio_driver_api gpio_kscan_it8xxx2_driver_api = {
.pin_configure = gpio_kscan_it8xxx2_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_kscan_it8xxx2_get_config,
#endif
.port_get_raw = gpio_kscan_it8xxx2_port_get_raw,
.port_set_masked_raw = gpio_kscan_it8xxx2_port_set_masked_raw,
.port_set_bits_raw = gpio_kscan_it8xxx2_port_set_bits_raw,
.port_clear_bits_raw = gpio_kscan_it8xxx2_port_clear_bits_raw,
.port_toggle_bits = gpio_kscan_it8xxx2_port_toggle_bits,
};
#define GPIO_KSCAN_IT8XXX2_INIT(inst) \
static const struct gpio_kscan_cfg gpio_kscan_it8xxx2_cfg_##inst = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
DT_INST_PROP(inst, ngpios)) \
}, \
.reg_ksi_kso_goen = (uint8_t *)DT_INST_REG_ADDR_BY_NAME(inst, goen), \
.reg_ksi_kso_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_NAME(inst, gctrl), \
.reg_ksi_kso_gdat = (uint8_t *)DT_INST_REG_ADDR_BY_NAME(inst, gdat), \
.reg_ksi_kso_gdmr = (uint8_t *)DT_INST_REG_ADDR_BY_NAME(inst, gdmr), \
.reg_ksi_kso_gpod = (uint8_t *)DT_INST_REG_ADDR_BY_NAME(inst, gpod), \
}; \
\
static struct gpio_kscan_data gpio_kscan_it8xxx2_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, \
NULL, \
NULL, \
&gpio_kscan_it8xxx2_data_##inst, \
&gpio_kscan_it8xxx2_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_kscan_it8xxx2_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_KSCAN_IT8XXX2_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_kscan_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,351 |
```c
/*
* Xilinx Processor System MIO / EMIO GPIO controller driver
* Parent (IRQ handler) module
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_xlnx_ps.h"
#include "gpio_xlnx_ps_bank.h"
#define LOG_MODULE_NAME gpio_xlnx_ps
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define DT_DRV_COMPAT xlnx_ps_gpio
/*
* An API is required for this driver, but as no pin access is provided at
* this level, use the default API contents provided by the driver subsystem.
*/
static const struct gpio_driver_api gpio_xlnx_ps_default_apis;
/**
* @brief Initialize a Xilinx PS GPIO controller parent device
*
* Initialize a Xilinx PS GPIO controller parent device, whose task it is
* to handle the IRQ line of each controller instance, while the configuration,
* status and data acquisition of each MIO / EMIO GPIO pin associated with
* the parent controller instance is handled via the respective GPIO pin
* bank's child device.
*
* @param dev Pointer to the PS GPIO controller's device.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_init(const struct device *dev)
{
const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
/* Initialize the device's interrupt */
dev_conf->config_func(dev);
return 0;
}
/**
* @brief Xilinx PS GPIO controller parent device ISR
*
* Interrupt service routine for the Xilinx PS GPIO controller's
* IRQ. The ISR iterates all associated MIO / EMIO GPIO pink bank
* child device instances and checks each bank's interrupt status.
* If any pending interrupt is detected within a GPIO pin bank,
* the callbacks registered for the respective bank are triggered
* using the functionality provided by the GPIO sub-system.
*
* @param dev Pointer to the PS GPIO controller's device.
*/
static void gpio_xlnx_ps_isr(const struct device *dev)
{
const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
const struct gpio_driver_api *api;
struct gpio_xlnx_ps_bank_dev_data *bank_data;
uint32_t bank;
uint32_t int_mask;
for (bank = 0; bank < dev_conf->num_banks; bank++) {
api = dev_conf->bank_devices[bank]->api;
int_mask = 0;
if (api != NULL) {
int_mask = api->get_pending_int(dev_conf->bank_devices[bank]);
}
if (int_mask) {
bank_data = (struct gpio_xlnx_ps_bank_dev_data *)
dev_conf->bank_devices[bank]->data;
gpio_fire_callbacks(&bank_data->callbacks,
dev_conf->bank_devices[bank], int_mask);
}
}
}
/* Device definition macros */
/*
* Macros generating a list of all associated GPIO pin bank child
* devices for the parent controller device's config data struct
* specified in the device tree.
*/
#define GPIO_XLNX_PS_GEN_BANK_ARRAY(idx)\
static const struct device *const gpio_xlnx_ps##idx##_banks[] = {\
DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP(idx, DEVICE_DT_GET, (,))\
};
/* Device config & run-time data struct creation macros */
#define GPIO_XLNX_PS_DEV_DATA(idx)\
static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data;
#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
.base_addr = DT_INST_REG_ADDR(idx),\
.bank_devices = gpio_xlnx_ps##idx##_banks,\
.num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
.config_func = gpio_xlnx_ps##idx##_irq_config\
};
/*
* Macro used to generate each parent controller device's IRQ attach
* function.
*/
#define GPIO_XLNX_PS_DEV_CONFIG_IRQ_FUNC(idx)\
static void gpio_xlnx_ps##idx##_irq_config(const struct device *dev)\
{\
ARG_UNUSED(dev);\
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority),\
gpio_xlnx_ps_isr, DEVICE_DT_INST_GET(idx), 0);\
irq_enable(DT_INST_IRQN(idx));\
}
/* Device definition macro */
#define GPIO_XLNX_PS_DEV_DEFINE(idx)\
DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_init, NULL,\
&gpio_xlnx_ps##idx##_data, &gpio_xlnx_ps##idx##_cfg,\
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_default_apis);
/*
* Top-level device initialization macro, executed for each PS GPIO
* parent device entry contained in the device tree which has status
* "okay".
*/
#define GPIO_XLNX_PS_DEV_INITITALIZE(idx)\
GPIO_XLNX_PS_GEN_BANK_ARRAY(idx)\
GPIO_XLNX_PS_DEV_CONFIG_IRQ_FUNC(idx)\
GPIO_XLNX_PS_DEV_DATA(idx)\
GPIO_XLNX_PS_DEV_CONFIG(idx)\
GPIO_XLNX_PS_DEV_DEFINE(idx)
/*
* Register & initialize all instances of the Processor System's MIO / EMIO GPIO
* controller specified in the device tree.
*/
DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_PS_DEV_INITITALIZE);
``` | /content/code_sandbox/drivers/gpio/gpio_xlnx_ps.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,167 |
```c
/*
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_common.h>
#include <fsl_port.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_rv32m1_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Type *gpio_base;
PORT_Type *port_base;
unsigned int flags;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
int (*irq_config_func)(const struct device *dev);
};
struct gpio_rv32m1_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
uint32_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
port_interrupt_t port_interrupt = 0;
if (mode == GPIO_INT_MODE_DISABLED) {
port_interrupt = kPORT_InterruptOrDMADisabled;
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig == GPIO_INT_TRIG_LOW) {
port_interrupt = kPORT_InterruptLogicZero;
} else {
port_interrupt = kPORT_InterruptLogicOne;
}
} else {
switch (trig) {
case GPIO_INT_TRIG_LOW:
port_interrupt = kPORT_InterruptFallingEdge;
break;
case GPIO_INT_TRIG_HIGH:
port_interrupt = kPORT_InterruptRisingEdge;
break;
case GPIO_INT_TRIG_BOTH:
port_interrupt = kPORT_InterruptEitherEdge;
break;
default:
return -EINVAL;
}
}
}
return PORT_PCR_IRQC(port_interrupt);
}
static int gpio_rv32m1_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
uint32_t mask = 0U;
uint32_t pcr = 0U;
/* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) {
return -EINVAL;
}
/* Check for an invalid pin configuration */
if ((flags & GPIO_INT_ENABLE) && ((flags & GPIO_INPUT) == 0)) {
return -EINVAL;
}
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* Check if GPIO port supports interrupts */
if ((flags & GPIO_INT_ENABLE) &&
((config->flags & GPIO_INT_ENABLE) == 0U)) {
return -ENOTSUP;
}
/* The flags contain options that require touching registers in the
* GPIO module and the corresponding PORT module.
*
* Start with the GPIO module and set up the pin direction register.
* 0 - pin is input, 1 - pin is output
*/
switch (flags & GPIO_DIR_MASK) {
case GPIO_INPUT:
gpio_base->PDDR &= ~BIT(pin);
break;
case GPIO_OUTPUT:
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_base->PSOR = BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_base->PCOR = BIT(pin);
}
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
}
/* Set PCR mux to GPIO for the pin we are configuring */
mask |= PORT_PCR_MUX_MASK;
pcr |= PORT_PCR_MUX(kPORT_MuxAsGpio);
/* Now do the PORT module. Figure out the pullup/pulldown
* configuration, but don't write it to the PCR register yet.
*/
mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
if ((flags & GPIO_PULL_UP) != 0) {
/* Enable the pull and select the pullup resistor. */
pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
/* Enable the pull and select the pulldown resistor (deselect
* the pullup resistor.
*/
pcr |= PORT_PCR_PE_MASK;
}
/* Still in the PORT module. Figure out the interrupt configuration,
* but don't write it to the PCR register yet.
*/
mask |= PORT_PCR_IRQC_MASK;
/* Accessing by pin, we only need to write one PCR register. */
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
return 0;
}
static int gpio_rv32m1_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
*value = gpio_base->PDIR;
return 0;
}
static int gpio_rv32m1_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value);
return 0;
}
static int gpio_rv32m1_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PSOR = mask;
return 0;
}
static int gpio_rv32m1_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PCOR = mask;
return 0;
}
static int gpio_rv32m1_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_rv32m1_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PTOR = mask;
return 0;
}
static int gpio_rv32m1_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_rv32m1_config *config = dev->config;
PORT_Type *port_base = config->port_base;
/* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) {
return -EINVAL;
}
/* Check if GPIO port supports interrupts */
if ((mode != GPIO_INT_MODE_DISABLED) &&
((config->flags & GPIO_INT_ENABLE) == 0U)) {
return -ENOTSUP;
}
uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
return 0;
}
static int gpio_rv32m1_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_rv32m1_data *data = dev->data;
gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
static void gpio_rv32m1_port_isr(const struct device *dev)
{
const struct gpio_rv32m1_config *config = dev->config;
struct gpio_rv32m1_data *data = dev->data;
uint32_t int_status;
int_status = config->port_base->ISFR;
/* Clear the port interrupts before invoking callbacks */
config->port_base->ISFR = int_status;
gpio_fire_callbacks(&data->callbacks, dev, int_status);
}
static int gpio_rv32m1_init(const struct device *dev)
{
const struct gpio_rv32m1_config *config = dev->config;
int ret;
if (config->clock_dev) {
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
ret = clock_control_on(config->clock_dev, config->clock_subsys);
if (ret < 0) {
return ret;
}
}
return config->irq_config_func(dev);
}
static const struct gpio_driver_api gpio_rv32m1_driver_api = {
.pin_configure = gpio_rv32m1_configure,
.port_get_raw = gpio_rv32m1_port_get_raw,
.port_set_masked_raw = gpio_rv32m1_port_set_masked_raw,
.port_set_bits_raw = gpio_rv32m1_port_set_bits_raw,
.port_clear_bits_raw = gpio_rv32m1_port_clear_bits_raw,
.port_toggle_bits = gpio_rv32m1_port_toggle_bits,
.pin_interrupt_configure = gpio_rv32m1_pin_interrupt_configure,
.manage_callback = gpio_rv32m1_manage_callback,
};
#define INST_DT_PORT_ADDR(n) \
DT_REG_ADDR(DT_INST_PHANDLE(n, openisa_rv32m1_port))
#define INST_DT_CLK_CTRL_DEV(n) \
UTIL_AND(DT_INST_NODE_HAS_PROP(n, clocks), DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)))
#define INST_DT_CLK_CELL_NAME(n) \
UTIL_AND(DT_INST_NODE_HAS_PROP(n, clocks), DT_INST_CLOCKS_CELL(n, name))
#define GPIO_RV32M1_INIT(n) \
static int gpio_rv32m1_##n##_init(const struct device *dev); \
\
static const struct gpio_rv32m1_config gpio_rv32m1_##n##_config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \
.port_base = (PORT_Type *) INST_DT_PORT_ADDR(n), \
.flags = GPIO_INT_ENABLE, \
.irq_config_func = gpio_rv32m1_##n##_init, \
.clock_dev = INST_DT_CLK_CTRL_DEV(n), \
.clock_subsys = (clock_control_subsys_t) \
INST_DT_CLK_CELL_NAME(n) \
}; \
\
static struct gpio_rv32m1_data gpio_rv32m1_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_rv32m1_init, \
NULL, \
&gpio_rv32m1_##n##_data, \
&gpio_rv32m1_##n##_config, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_rv32m1_driver_api); \
\
static int gpio_rv32m1_##n##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
0, \
gpio_rv32m1_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(0)); \
\
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_RV32M1_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_rv32m1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,604 |
```c
/*
*
*/
/**
* @file
* @brief Driver to provide the GPIO API for a simple 32-bit i/o register
*
* This is a driver for accessing a simple, fixed purpose, 32-bit
* memory-mapped i/o register using the same APIs as GPIO drivers. This is
* useful when an SoC or board has registers that aren't part of a GPIO IP
* block and these registers are used to control things that Zephyr normally
* expects to be specified using a GPIO pin, e.g. for driving an LED, or
* chip-select line for an SPI device.
*
* The implementation expects that all bits of the hardware register are both
* readable and writable, and that for any bits that act as outputs, the value
* read will have the value that was last written to it. This requirement
* stems from the use of a read-modify-write method for all changes.
*
* It is possible to specify a restricted mask of bits that are valid for
* access, and whenever the register is written, the value of bits outside this
* mask will be preserved, even when the whole port is written to using
* gpio_port_write.
*/
#include <zephyr/drivers/gpio/gpio_mmio32.h>
#include <zephyr/irq.h>
#include <errno.h>
static int gpio_mmio32_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
if ((config->mask & (1 << pin)) == 0) {
return -EINVAL; /* Pin not in our validity mask */
}
if (flags & ~(GPIO_INPUT | GPIO_OUTPUT |
GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH |
GPIO_ACTIVE_LOW)) {
/* We ignore direction and fake polarity, rest is unsupported */
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT) != 0) {
unsigned int key;
volatile uint32_t *reg = config->reg;
key = irq_lock();
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
*reg = (*reg | (1 << pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
*reg = (*reg & (config->mask & ~(1 << pin)));
}
irq_unlock(key);
}
return 0;
}
static int gpio_mmio32_port_get_raw(const struct device *dev, uint32_t *value)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
*value = *config->reg & config->mask;
return 0;
}
static int gpio_mmio32_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
volatile uint32_t *reg = config->reg;
unsigned int key;
mask &= config->mask;
value &= mask;
/* Update pin state atomically */
key = irq_lock();
*reg = (*reg & ~mask) | value;
irq_unlock(key);
return 0;
}
static int gpio_mmio32_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
volatile uint32_t *reg = config->reg;
unsigned int key;
mask &= config->mask;
/* Update pin state atomically */
key = irq_lock();
*reg = (*reg | mask);
irq_unlock(key);
return 0;
}
static int gpio_mmio32_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
volatile uint32_t *reg = config->reg;
unsigned int key;
mask &= config->mask;
/* Update pin state atomically */
key = irq_lock();
*reg = (*reg & ~mask);
irq_unlock(key);
return 0;
}
static int gpio_mmio32_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = context->config;
volatile uint32_t *reg = config->reg;
unsigned int key;
mask &= config->mask;
/* Update pin state atomically */
key = irq_lock();
*reg = (*reg ^ mask);
irq_unlock(key);
return 0;
}
const struct gpio_driver_api gpio_mmio32_api = {
.pin_configure = gpio_mmio32_config,
.port_get_raw = gpio_mmio32_port_get_raw,
.port_set_masked_raw = gpio_mmio32_port_set_masked_raw,
.port_set_bits_raw = gpio_mmio32_port_set_bits_raw,
.port_clear_bits_raw = gpio_mmio32_port_clear_bits_raw,
.port_toggle_bits = gpio_mmio32_port_toggle_bits,
};
int gpio_mmio32_init(const struct device *dev)
{
struct gpio_mmio32_context *context = dev->data;
const struct gpio_mmio32_config *config = dev->config;
context->config = config;
return 0;
}
``` | /content/code_sandbox/drivers/gpio/gpio_mmio32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,166 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_ra_gpio
#include <errno.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
#include <zephyr/drivers/pinctrl.h>
enum {
PCNTR1_OFFSET = 0x0,
PCNTR2_OFFSET = 0x4,
PCNTR3_OFFSET = 0x8,
PCNTR4_OFFSET = 0xc
};
enum {
PCNTR1_PDR0_OFFSET = 0,
PCNTR1_PODR0_OFFSET = 16,
};
enum {
PCNTR2_PIDR0_OFFSET = 0,
PCNTR2_EIDR0_OFFSET = 16,
};
enum {
PCNTR3_POSR0_OFFSET = 0,
PCNTR3_PORR0_OFFSET = 16,
};
enum {
PCNTR4_EOSR0_OFFSET = 0,
PCNTR4_EORR0_OFFSET = 16,
};
struct gpio_ra_irq_info {
const uint8_t *const pins;
size_t num;
int port_irq;
int irq;
uint32_t priority;
uint32_t flags;
ra_isr_handler isr;
};
struct gpio_ra_pin_irq_info {
const struct gpio_ra_irq_info *info;
uint8_t pin;
};
struct gpio_ra_config {
struct gpio_driver_config common;
mem_addr_t regs;
struct gpio_ra_irq_info *irq_info;
uint32_t irq_info_size;
uint16_t port;
};
struct gpio_ra_data {
struct gpio_driver_data common;
struct gpio_ra_pin_irq_info port_irq_info[16];
sys_slist_t callbacks;
};
static inline uint32_t gpio_ra_irq_info_event(const struct gpio_ra_irq_info *info)
{
return ((info->flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET);
}
static void gpio_ra_isr(const struct device *dev, uint32_t port_irq)
{
struct gpio_ra_data *data = dev->data;
const struct gpio_ra_pin_irq_info *pin_irq = &data->port_irq_info[port_irq];
const int irq = ra_icu_query_exists_irq(gpio_ra_irq_info_event(pin_irq->info));
if (irq >= 0) {
gpio_fire_callbacks(&data->callbacks, dev, BIT(pin_irq->pin));
ra_icu_clear_int_flag(irq);
}
}
static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin)
{
const struct gpio_ra_config *config = dev->config;
for (int i = 0; i < config->irq_info_size; i++) {
const struct gpio_ra_irq_info *info = &config->irq_info[i];
for (int j = 0; j < info->num; j++) {
if (info->pins[j] == pin) {
return info;
}
}
}
return NULL;
}
static inline uint32_t reg_read(const struct device *dev, size_t offset)
{
const struct gpio_ra_config *config = dev->config;
return sys_read32(config->regs + offset);
}
static inline void reg_write(const struct device *dev, size_t offset, uint32_t value)
{
const struct gpio_ra_config *config = dev->config;
sys_write32(value, config->regs + offset);
}
static inline uint32_t port_read(const struct device *dev)
{
return reg_read(dev, PCNTR2_OFFSET) & UINT16_MAX;
}
static int port_write(const struct device *dev, uint16_t value, uint16_t mask)
{
const uint16_t set = value & mask;
const uint16_t clr = (~value) & mask;
reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET);
return 0;
}
static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const enum gpio_int_mode mode =
flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE);
const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
const struct gpio_ra_config *config = dev->config;
struct gpio_ra_data *data = dev->data;
struct pinctrl_ra_pin pincfg = {0};
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
/* Pin cannot be configured as input and output */
return -ENOTSUP;
} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
/* Pin has to be configured as input or output */
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
pincfg.config |= BIT(PmnPFS_PDR_POS);
}
if (flags & GPIO_PULL_UP) {
pincfg.config |= BIT(PmnPFS_PCR_POS);
}
if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) {
pincfg.config |= BIT(PmnPFS_NCODR_POS);
}
if (flags & GPIO_INT_ENABLE) {
pincfg.config |= BIT(PmnPFS_ISEL_POS);
}
pincfg.config &= ~BIT(PmnPFS_PMR_POS);
pincfg.pin = pin;
pincfg.port = config->port;
if (flags & GPIO_INT_ENABLE) {
const struct gpio_ra_irq_info *irq_info;
uint32_t intcfg;
int irqn;
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig != GPIO_INT_TRIG_LOW) {
return -ENOTSUP;
}
intcfg = ICU_LOW_LEVEL;
} else if (mode == GPIO_INT_MODE_EDGE) {
switch (trig) {
case GPIO_INT_TRIG_LOW:
intcfg = ICU_FALLING;
break;
case GPIO_INT_TRIG_HIGH:
intcfg = ICU_RISING;
break;
case GPIO_INT_TRIG_BOTH:
intcfg = ICU_BOTH_EDGE;
break;
default:
return -ENOTSUP;
}
} else {
return -ENOTSUP;
}
irq_info = query_irq_info(dev, pin);
if (irq_info == NULL) {
return -EINVAL;
}
irqn = ra_icu_irq_connect_dynamic(
irq_info->irq, irq_info->priority, irq_info->isr, dev,
(intcfg << RA_ICU_FLAG_INTCFG_OFFSET) | irq_info->flags);
if (irqn < 0) {
return irqn;
}
data->port_irq_info[irq_info->port_irq].pin = pin;
data->port_irq_info[irq_info->port_irq].info = irq_info;
irq_enable(irqn);
}
return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
{
const struct gpio_ra_config *config = dev->config;
const struct gpio_ra_irq_info *irq_info;
struct pinctrl_ra_pin pincfg;
ra_isr_handler cb;
const void *cbarg;
uint32_t intcfg;
int irqn;
int err;
memset(flags, 0, sizeof(gpio_flags_t));
err = pinctrl_ra_query_config(config->port, pin, &pincfg);
if (err < 0) {
return err;
}
if (pincfg.config & BIT(PmnPFS_PDR_POS)) {
*flags |= GPIO_OUTPUT;
} else {
*flags |= GPIO_INPUT;
}
if (pincfg.config & BIT(PmnPFS_ISEL_POS)) {
*flags |= GPIO_INT_ENABLE;
}
if (pincfg.config & BIT(PmnPFS_PCR_POS)) {
*flags |= GPIO_PULL_UP;
}
irq_info = query_irq_info(dev, pin);
if (irq_info == NULL) {
return 0;
}
irqn = ra_icu_query_exists_irq(gpio_ra_irq_info_event(irq_info));
if (irqn < 0) {
return 0;
}
ra_icu_query_irq_config(irqn, &intcfg, &cb, &cbarg);
if (cbarg != dev) {
return 0;
}
if (intcfg == ICU_FALLING) {
*flags |= GPIO_INT_TRIG_LOW;
*flags |= GPIO_INT_MODE_EDGE;
} else if (intcfg == ICU_RISING) {
*flags |= GPIO_INT_TRIG_HIGH;
*flags |= GPIO_INT_MODE_EDGE;
} else if (intcfg == ICU_BOTH_EDGE) {
*flags |= GPIO_INT_TRIG_BOTH;
*flags |= GPIO_INT_MODE_EDGE;
} else if (intcfg == ICU_LOW_LEVEL) {
*flags |= GPIO_INT_TRIG_LOW;
*flags |= GPIO_INT_MODE_LEVEL;
}
return 0;
}
#endif
static int gpio_ra_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
*value = port_read(dev);
return 0;
}
static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
uint16_t port_val;
port_val = port_read(dev);
port_val = (port_val & ~mask) | (value & mask);
return port_write(dev, port_val, UINT16_MAX);
}
static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
uint16_t port_val;
port_val = port_read(dev);
port_val |= pins;
return port_write(dev, port_val, UINT16_MAX);
}
static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
uint16_t port_val;
port_val = port_read(dev);
port_val &= ~pins;
return port_write(dev, port_val, UINT16_MAX);
}
static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
uint16_t port_val;
port_val = port_read(dev);
port_val ^= pins;
return port_write(dev, port_val, UINT16_MAX);
}
static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct gpio_ra_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_ra_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
gpio_flags_t pincfg;
int err;
err = gpio_ra_pin_get_config(dev, pin, &pincfg);
if (err < 0) {
return err;
}
return gpio_ra_pin_configure(dev, pin, pincfg | mode | trig);
}
static const struct gpio_driver_api gpio_ra_driver_api = {
.pin_configure = gpio_ra_pin_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_ra_pin_get_config,
#endif
.port_get_raw = gpio_ra_port_get_raw,
.port_set_masked_raw = gpio_ra_port_set_masked_raw,
.port_set_bits_raw = gpio_ra_port_set_bits_raw,
.port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
.port_toggle_bits = gpio_ra_port_toggle_bits,
.pin_interrupt_configure = gpio_ra_pin_interrupt_configure,
.manage_callback = gpio_ra_manage_callback,
};
#define RA_NUM_PORT_IRQ0 0
#define RA_NUM_PORT_IRQ1 1
#define RA_NUM_PORT_IRQ2 2
#define RA_NUM_PORT_IRQ3 3
#define RA_NUM_PORT_IRQ4 4
#define RA_NUM_PORT_IRQ5 5
#define RA_NUM_PORT_IRQ6 6
#define RA_NUM_PORT_IRQ7 7
#define RA_NUM_PORT_IRQ8 8
#define RA_NUM_PORT_IRQ9 9
#define RA_NUM_PORT_IRQ10 10
#define RA_NUM_PORT_IRQ11 11
#define RA_NUM_PORT_IRQ12 12
#define RA_NUM_PORT_IRQ13 13
#define RA_NUM_PORT_IRQ14 14
#define RA_NUM_PORT_IRQ15 15
#define GPIO_RA_DECL_PINS(n, p, i) \
const uint8_t _CONCAT(n, ___pins##i[]) = {DT_FOREACH_PROP_ELEM_SEP( \
n, _CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins), DT_PROP_BY_IDX, (,))};
#define GPIO_RA_IRQ_INFO(n, p, i) \
{ \
.port_irq = _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)), \
.irq = DT_IRQ_BY_IDX(n, i, irq), \
.flags = DT_IRQ_BY_IDX(n, i, flags), \
.priority = DT_IRQ_BY_IDX(n, i, priority), \
.pins = _CONCAT(n, ___pins##i), \
.num = ARRAY_SIZE(_CONCAT(n, ___pins##i)), \
.isr = _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i))), \
},
#define GPIO_RA_ISR_DECL(n, p, i) \
static void _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i)))( \
const void *arg) \
{ \
gpio_ra_isr((const struct device *)arg, \
_CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i))); \
}
#define GPIO_RA_INIT(idx) \
static struct gpio_ra_data gpio_ra_data_##idx = {}; \
DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_DECL_PINS); \
DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_ISR_DECL); \
struct gpio_ra_irq_info gpio_ra_irq_info_##idx[] = { \
DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_IRQ_INFO)}; \
static struct gpio_ra_config gpio_ra_config_##idx = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
}, \
.regs = DT_INST_REG_ADDR(idx), \
.port = (DT_INST_REG_ADDR(idx) - DT_REG_ADDR(DT_NODELABEL(ioport0))) / \
DT_INST_REG_SIZE(idx), \
.irq_info = gpio_ra_irq_info_##idx, \
.irq_info_size = ARRAY_SIZE(gpio_ra_irq_info_##idx), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &gpio_ra_data_##idx, &gpio_ra_config_##idx, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_RA_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_renesas_ra.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,292 |
```c
/*
*
*
*/
/**
* @file Driver for MPC23xxx I2C/SPI-based GPIO driver.
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_mcp23xxx.h"
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_mcp23xxx);
#define MCP23XXX_RESET_TIME_US 1
/**
* @brief Reads given register from mcp23xxx.
*
* The registers of the mcp23x0x consist of one 8 bit port.
* The registers of the mcp23x1x consist of two 8 bit ports.
*
* @param dev The mcp23xxx device.
* @param reg The register to be read.
* @param buf The buffer to read data to.
* @return 0 if successful.
* Otherwise <0 will be returned.
*/
static int read_port_regs(const struct device *dev, uint8_t reg, uint16_t *buf)
{
const struct mcp23xxx_config *config = dev->config;
if (config->ngpios == 16U) {
reg *= 2;
}
return config->read_fn(dev, reg, buf);
}
/**
* @brief Writes registers of the mcp23xxx.
*
* On the mcp23x08 one 8 bit port will be written.
* On the mcp23x17 two 8 bit ports will be written.
*
* @param dev The mcp23xxx device.
* @param reg Register to be written.
* @param buf The new register value.
*
* @return 0 if successful. Otherwise <0 will be returned.
*/
static int write_port_regs(const struct device *dev, uint8_t reg, uint16_t value)
{
const struct mcp23xxx_config *config = dev->config;
if (config->ngpios == 16U) {
reg *= 2;
}
return config->write_fn(dev, reg, value);
}
/**
* @brief Writes to the IOCON register of the mcp23xxx.
*
* IOCON is the only register that is not 16 bits wide on 16-pin devices; instead, it is mirrored in
* two adjacent memory locations. Because the underlying `write_fn` always does a 16-bit write for
* 16-pin devices, make sure we write the same value to both IOCON locations.
*
* @param dev The mcp23xxx device.
* @param value the IOCON value to write
*
* @return 0 if successful. Otherwise <0 will be returned.
*/
static int write_iocon(const struct device *dev, uint8_t value)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t extended_value = value | (value << 8);
int ret = write_port_regs(dev, REG_IOCON, extended_value);
if (ret == 0) {
drv_data->reg_cache.iocon = extended_value;
}
return ret;
}
/**
* @brief Setup the pin direction.
*
* @param dev The mcp23xxx device.
* @param pin The pin number.
* @param flags Flags of pin or port.
* @return 0 if successful. Otherwise <0 will be returned.
*/
static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t dir = drv_data->reg_cache.iodir;
uint16_t output = drv_data->reg_cache.gpio;
int ret;
if ((flags & GPIO_OUTPUT) != 0U) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
output |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
output &= ~BIT(pin);
}
dir &= ~BIT(pin);
} else {
dir |= BIT(pin);
}
ret = write_port_regs(dev, REG_GPIO, output);
if (ret != 0) {
return ret;
}
drv_data->reg_cache.gpio = output;
ret = write_port_regs(dev, REG_IODIR, dir);
if (ret == 0) {
drv_data->reg_cache.iodir = dir;
}
return ret;
}
/**
* @brief Setup pin pull up/pull down.
*
* @param dev The mcp23xxx device.
* @param pin The pin number.
* @param flags Flags of pin or port.
* @return 0 if successful. Otherwise <0 will be returned.
*/
static int setup_pin_pull(const struct device *dev, uint32_t pin, int flags)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t port;
int ret;
port = drv_data->reg_cache.gppu;
if ((flags & GPIO_PULL_DOWN) != 0U) {
return -ENOTSUP;
}
WRITE_BIT(port, pin, (flags & GPIO_PULL_UP) != 0);
ret = write_port_regs(dev, REG_GPPU, port);
if (ret == 0) {
drv_data->reg_cache.gppu = port;
}
return ret;
}
static int mcp23xxx_pin_cfg(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
const struct mcp23xxx_config *config = dev->config;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
if ((bool)(flags & GPIO_SINGLE_ENDED) != config->is_open_drain ||
(bool)(flags & GPIO_LINE_OPEN_DRAIN) != config->is_open_drain) {
ret = -ENOTSUP;
goto done;
}
ret = setup_pin_dir(dev, pin, flags);
if (ret < 0) {
LOG_ERR("Error setting pin direction (%d)", ret);
goto done;
}
ret = setup_pin_pull(dev, pin, flags);
if (ret < 0) {
LOG_ERR("Error setting pin pull up/pull down (%d)", ret);
goto done;
}
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int mcp23xxx_port_get_raw(const struct device *dev, uint32_t *value)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t buf;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = read_port_regs(dev, REG_GPIO, &buf);
if (ret == 0) {
*value = buf;
}
k_sem_give(&drv_data->lock);
return ret;
}
static int mcp23xxx_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t buf;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
buf = drv_data->reg_cache.gpio;
buf = (buf & ~mask) | (mask & value);
ret = write_port_regs(dev, REG_GPIO, buf);
if (ret == 0) {
drv_data->reg_cache.gpio = buf;
}
k_sem_give(&drv_data->lock);
return ret;
}
static int mcp23xxx_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
return mcp23xxx_port_set_masked_raw(dev, mask, mask);
}
static int mcp23xxx_port_clear_bits_raw(const struct device *dev, uint32_t mask)
{
return mcp23xxx_port_set_masked_raw(dev, mask, 0);
}
static int mcp23xxx_port_toggle_bits(const struct device *dev, uint32_t mask)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
uint16_t buf;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
buf = drv_data->reg_cache.gpio;
buf ^= mask;
ret = write_port_regs(dev, REG_GPIO, buf);
if (ret == 0) {
drv_data->reg_cache.gpio = buf;
}
k_sem_give(&drv_data->lock);
return ret;
}
static int mcp23xxx_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
const struct mcp23xxx_config *config = dev->config;
if (!config->gpio_int.port) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
uint16_t gpinten = drv_data->reg_cache.gpinten;
uint16_t defval = drv_data->reg_cache.defval;
uint16_t intcon = drv_data->reg_cache.intcon;
int ret;
switch (mode) {
case GPIO_INT_MODE_DISABLED:
gpinten &= ~BIT(pin);
break;
case GPIO_INT_MODE_LEVEL:
gpinten |= BIT(pin);
intcon |= BIT(pin);
switch (trig) {
case GPIO_INT_TRIG_LOW:
defval |= BIT(pin);
break;
case GPIO_INT_TRIG_HIGH:
defval &= ~BIT(pin);
break;
case GPIO_INT_TRIG_BOTH:
/* can't happen */
ret = -ENOTSUP;
goto done;
default:
ret = -EINVAL;
goto done;
}
break;
case GPIO_INT_MODE_EDGE:
gpinten |= BIT(pin);
intcon &= ~BIT(pin);
switch (trig) {
case GPIO_INT_TRIG_LOW:
drv_data->rising_edge_ints &= ~BIT(pin);
drv_data->falling_edge_ints |= BIT(pin);
break;
case GPIO_INT_TRIG_HIGH:
drv_data->rising_edge_ints |= BIT(pin);
drv_data->falling_edge_ints &= ~BIT(pin);
break;
case GPIO_INT_TRIG_BOTH:
drv_data->rising_edge_ints |= BIT(pin);
drv_data->falling_edge_ints |= BIT(pin);
break;
default:
ret = -EINVAL;
goto done;
}
break;
}
ret = write_port_regs(dev, REG_GPINTEN, gpinten);
if (ret != 0) {
goto done;
}
drv_data->reg_cache.gpinten = gpinten;
ret = write_port_regs(dev, REG_DEFVAL, defval);
if (ret != 0) {
goto done;
}
drv_data->reg_cache.defval = defval;
ret = write_port_regs(dev, REG_INTCON, intcon);
if (ret != 0) {
goto done;
}
drv_data->reg_cache.intcon = intcon;
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int mcp23xxx_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct mcp23xxx_drv_data *drv_data = dev->data;
const struct mcp23xxx_config *config = dev->config;
if (!config->gpio_int.port) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
int ret = gpio_manage_callback(&drv_data->callbacks, callback, set);
k_sem_give(&drv_data->lock);
return ret;
}
static void mcp23xxx_work_handler(struct k_work *work)
{
struct mcp23xxx_drv_data *drv_data = CONTAINER_OF(work, struct mcp23xxx_drv_data, work);
const struct device *dev = drv_data->dev;
int ret;
k_sem_take(&drv_data->lock, K_FOREVER);
uint16_t intf;
ret = read_port_regs(dev, REG_INTF, &intf);
if (ret != 0) {
LOG_ERR("Failed to read INTF");
goto fail;
}
if (!intf) {
/* Probable causes:
* - REG_GPIO was read from somewhere else before the interrupt handler had a chance
* to run
* - Even though the datasheet says differently, reading INTCAP while a level
* interrupt is active briefly (~2ns) causes the interrupt line to go high and
* low again. This causes a second ISR to be scheduled, which then won't
* find any active interrupts if the callback has disabled the level interrupt.
*/
LOG_ERR("Spurious interrupt");
goto fail;
}
uint16_t intcap;
/* Read INTCAP to acknowledge the interrupt */
ret = read_port_regs(dev, REG_INTCAP, &intcap);
if (ret != 0) {
LOG_ERR("Failed to read INTCAP");
goto fail;
}
/* mcp23xxx does not support single-edge interrupts in hardware, filter them out manually */
uint16_t level_ints = drv_data->reg_cache.gpinten & drv_data->reg_cache.intcon;
intf &= level_ints | (intcap & drv_data->rising_edge_ints) |
(~intcap & drv_data->falling_edge_ints);
k_sem_give(&drv_data->lock);
gpio_fire_callbacks(&drv_data->callbacks, dev, intf);
return;
fail:
k_sem_give(&drv_data->lock);
}
static void mcp23xxx_int_gpio_handler(const struct device *port, struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct mcp23xxx_drv_data *drv_data =
CONTAINER_OF(cb, struct mcp23xxx_drv_data, int_gpio_cb);
k_work_submit(&drv_data->work);
}
const struct gpio_driver_api gpio_mcp23xxx_api_table = {
.pin_configure = mcp23xxx_pin_cfg,
.port_get_raw = mcp23xxx_port_get_raw,
.port_set_masked_raw = mcp23xxx_port_set_masked_raw,
.port_set_bits_raw = mcp23xxx_port_set_bits_raw,
.port_clear_bits_raw = mcp23xxx_port_clear_bits_raw,
.port_toggle_bits = mcp23xxx_port_toggle_bits,
.pin_interrupt_configure = mcp23xxx_pin_interrupt_configure,
.manage_callback = mcp23xxx_manage_callback,
};
/**
* @brief Initialization function of MCP23XXX
*
* @param dev Device struct.
* @return 0 if successful. Otherwise <0 is returned.
*/
int gpio_mcp23xxx_init(const struct device *dev)
{
const struct mcp23xxx_config *config = dev->config;
struct mcp23xxx_drv_data *drv_data = dev->data;
int err;
if (config->ngpios != 8U && config->ngpios != 16U) {
LOG_ERR("Invalid value ngpios=%u. Expected 8 or 16!", config->ngpios);
return -EINVAL;
}
err = config->bus_fn(dev);
if (err < 0) {
return err;
}
k_sem_init(&drv_data->lock, 0, 1);
/* If the RESET line is available, pulse it. */
if (config->gpio_reset.port) {
err = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (err != 0) {
LOG_ERR("Failed to configure RESET line: %d", err);
return -EIO;
}
k_usleep(MCP23XXX_RESET_TIME_US);
err = gpio_pin_set_dt(&config->gpio_reset, 0);
if (err != 0) {
LOG_ERR("Failed to deactivate RESET line: %d", err);
return -EIO;
}
}
/* If the INT line is available, configure the callback for it. */
if (config->gpio_int.port) {
if (config->ngpios == 16) {
/* send both ports' interrupts through one IRQ pin */
err = write_iocon(dev, REG_IOCON_MIRROR);
if (err != 0) {
LOG_ERR("Failed to enable mirrored IRQ pins: %d", err);
return -EIO;
}
}
if (!gpio_is_ready_dt(&config->gpio_int)) {
LOG_ERR("INT port is not ready");
return -ENODEV;
}
drv_data->dev = dev;
k_work_init(&drv_data->work, mcp23xxx_work_handler);
err = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
if (err != 0) {
LOG_ERR("Failed to configure INT line: %d", err);
return -EIO;
}
gpio_init_callback(&drv_data->int_gpio_cb, mcp23xxx_int_gpio_handler,
BIT(config->gpio_int.pin));
err = gpio_add_callback(config->gpio_int.port, &drv_data->int_gpio_cb);
if (err != 0) {
LOG_ERR("Failed to add INT callback: %d", err);
return -EIO;
}
err = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
if (err != 0) {
LOG_ERR("Failed to configure INT interrupt: %d", err);
return -EIO;
}
}
k_sem_give(&drv_data->lock);
return 0;
}
``` | /content/code_sandbox/drivers/gpio/gpio_mcp23xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,898 |
```unknown
menuconfig GPIO_ADP5585
bool "ADP5585_GPIO I2C GPIO chip"
default y
depends on DT_HAS_ADI_ADP5585_GPIO_ENABLED
select MFD
select I2C
help
Enable the ADP5585 GPIO driver.
config GPIO_ADP5585_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_ADP5585
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.adp5585 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
config GPIO_AD559X
bool "AD559x GPIO driver"
default y
depends on DT_HAS_ADI_AD559X_GPIO_ENABLED
select MFD
help
Enable the AD559x GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.ad559x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
# ESP32 GPIO configuration options
config GPIO_ESP32
bool "ESP32 GPIO"
default y
depends on DT_HAS_ESPRESSIF_ESP32_GPIO_ENABLED
help
Enables the ESP32 GPIO driver
``` | /content/code_sandbox/drivers/gpio/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```c
/*
*
*/
#define DT_DRV_COMPAT rohm_bd8lb600fs_gpio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/mfd/bd8lb600fs.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_bd8lb600fs, CONFIG_GPIO_LOG_LEVEL);
struct bd8lb600fs_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *parent_dev;
int gpios_count;
};
struct bd8lb600fs_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data data;
/* each bit is one output channel, bit 0 = channel 1, ... */
uint32_t state;
/* each bit defines if the output channel is configured, see state */
uint32_t configured;
struct k_mutex lock;
};
static int bd8lb600fs_gpio_pin_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct bd8lb600fs_gpio_config *config = dev->config;
struct bd8lb600fs_gpio_data *data = dev->data;
/* cannot execute a bus operation in an ISR context */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin >= config->gpios_count) {
LOG_ERR("invalid pin number %i", pin);
return -EINVAL;
}
if ((flags & GPIO_INPUT) != 0) {
LOG_ERR("cannot configure pin as input");
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT) == 0) {
LOG_ERR("pin must be configured as an output");
return -ENOTSUP;
}
if ((flags & GPIO_SINGLE_ENDED) == 0) {
LOG_ERR("pin must be configured as single ended");
return -ENOTSUP;
}
if ((flags & GPIO_LINE_OPEN_DRAIN) == 0) {
LOG_ERR("pin must be configured as open drain");
return -ENOTSUP;
}
if ((flags & GPIO_PULL_UP) != 0) {
LOG_ERR("pin cannot have a pull up configured");
return -ENOTSUP;
}
if ((flags & GPIO_PULL_DOWN) != 0) {
LOG_ERR("pin cannot have a pull down configured");
return -ENOTSUP;
}
k_mutex_lock(&data->lock, K_FOREVER);
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
WRITE_BIT(data->state, pin, 0);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
WRITE_BIT(data->state, pin, 1);
}
WRITE_BIT(data->configured, pin, 1);
int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state);
k_mutex_unlock(&data->lock);
return result;
}
static int bd8lb600fs_gpio_port_get_raw(const struct device *dev, uint32_t *value)
{
LOG_ERR("input pins are not available");
return -ENOTSUP;
}
static int bd8lb600fs_gpio_port_set_masked_raw(const struct device *dev, uint32_t mask,
uint32_t value)
{
const struct bd8lb600fs_gpio_config *config = dev->config;
struct bd8lb600fs_gpio_data *data = dev->data;
/* cannot execute a bus operation in an ISR context */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_mutex_lock(&data->lock, K_FOREVER);
data->state = (data->state & ~mask) | (mask & value);
int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state);
k_mutex_unlock(&data->lock);
return result;
}
static int bd8lb600fs_gpio_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
return bd8lb600fs_gpio_port_set_masked_raw(dev, mask, mask);
}
static int bd8lb600fs_gpio_port_clear_bits_raw(const struct device *dev, uint32_t mask)
{
return bd8lb600fs_gpio_port_set_masked_raw(dev, mask, 0);
}
static int bd8lb600fs_gpio_port_toggle_bits(const struct device *dev, uint32_t mask)
{
const struct bd8lb600fs_gpio_config *config = dev->config;
struct bd8lb600fs_gpio_data *data = dev->data;
/* cannot execute a bus operation in an ISR context */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_mutex_lock(&data->lock, K_FOREVER);
data->state ^= mask;
int result = mfd_bd8lb600fs_set_outputs(config->parent_dev, data->state);
k_mutex_unlock(&data->lock);
return result;
}
static const struct gpio_driver_api api_table = {
.pin_configure = bd8lb600fs_gpio_pin_configure,
.port_get_raw = bd8lb600fs_gpio_port_get_raw,
.port_set_masked_raw = bd8lb600fs_gpio_port_set_masked_raw,
.port_set_bits_raw = bd8lb600fs_gpio_port_set_bits_raw,
.port_clear_bits_raw = bd8lb600fs_gpio_port_clear_bits_raw,
.port_toggle_bits = bd8lb600fs_gpio_port_toggle_bits,
};
static int bd8lb600fs_gpio_init(const struct device *dev)
{
const struct bd8lb600fs_gpio_config *config = dev->config;
struct bd8lb600fs_gpio_data *data = dev->data;
if (!device_is_ready(config->parent_dev)) {
LOG_ERR("MFD parent is not ready");
return -ENODEV;
}
int result = k_mutex_init(&data->lock);
if (result != 0) {
LOG_ERR("unable to initialize mutex");
return result;
}
return 0;
}
#define BD8LB600FS_GPIO_INIT(inst) \
static const struct bd8lb600fs_gpio_config bd8lb600fs_##inst##_config = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.parent_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.gpios_count = DT_INST_PROP(inst, ngpios), \
}; \
\
static struct bd8lb600fs_gpio_data bd8lb600fs_##inst##_data = { \
.state = 0x00, \
.configured = 0x00, \
}; \
\
DEVICE_DT_INST_DEFINE(inst, bd8lb600fs_gpio_init, NULL, &bd8lb600fs_##inst##_data, \
&bd8lb600fs_##inst##_config, POST_KERNEL, \
CONFIG_GPIO_BD8LB600FS_INIT_PRIORITY, &api_table);
DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_GPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_bd8lb600fs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,535 |
```objective-c
/*
*
*
* "Bottom" of the SDL GPIO emulator.
* When built with the native_simulator this will be built in the runner context,
* that is, with the host C library, and with the host include paths.
*/
#ifndef DRIVERS_GPIO_GPIO_EMUL_SDL_BOTTOM_H
#define DRIVERS_GPIO_GPIO_EMUL_SDL_BOTTOM_H
#include <stdbool.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Note: None of these are public interfaces. But internal to the SDL GPIO emulator */
#define GPIOEMULSDL_SCANCODE_UNKNOWN 0
struct gpio_sdl_data {
void *dev;
int (*callback)(struct gpio_sdl_data *data);
int event_scan_code;
bool key_down;
};
void gpio_sdl_init_bottom(struct gpio_sdl_data *data);
#ifdef __cplusplus
}
#endif
#endif /* DRIVERS_GPIO_GPIO_EMUL_SDL_BOTTOM_H */
``` | /content/code_sandbox/drivers/gpio/gpio_emul_sdl_bottom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numicro_gpio
#include <errno.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/dt-bindings/gpio/numicro-gpio.h>
#include <NuMicro.h>
#define MODE_PIN_SHIFT(pin) ((pin) * 2)
#define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin))
#define DINOFF_PIN_SHIFT(pin) ((pin) + 16)
#define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin))
#define PUSEL_PIN_SHIFT(pin) ((pin) * 2)
#define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin))
#define PORT_PIN_MASK 0xFFFF
struct gpio_numicro_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_T *regs;
};
struct gpio_numicro_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
/*
* backup of the INTEN register.
* The higher half is RHIEN for whether rising trigger is enabled, and
* the lower half is FLIEN for whether falling trigger is enabled.
*/
uint32_t interrupt_en_reg_bak;
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
};
static int gpio_numicro_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_numicro_config *cfg = dev->config;
GPIO_T * const regs = cfg->regs;
uint32_t mode;
uint32_t debounce_enable = 0;
uint32_t schmitt_enable = 0;
uint32_t disable_input_path = 0;
uint32_t bias = GPIO_PUSEL_DISABLE;
/* Pin mode */
if ((flags & GPIO_OUTPUT) != 0) {
/* Output */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
mode = GPIO_MODE_OPEN_DRAIN;
} else {
/* Output can't be open source */
return -ENOTSUP;
}
} else {
mode = GPIO_MODE_OUTPUT;
}
} else if ((flags & GPIO_INPUT) != 0) {
/* Input */
mode = GPIO_MODE_INPUT;
if ((flags & NUMICRO_GPIO_INPUT_DEBOUNCE) != 0) {
debounce_enable = 1;
}
if ((flags & NUMICRO_GPIO_INPUT_SCHMITT) != 0) {
schmitt_enable = 1;
}
} else {
/* Deactivated: Analog */
mode = GPIO_MODE_INPUT;
disable_input_path = 1;
}
/* Bias */
if ((flags & GPIO_OUTPUT) != 0 || (flags & GPIO_INPUT) != 0) {
if ((flags & GPIO_PULL_UP) != 0) {
bias = GPIO_PUSEL_PULL_UP;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
bias = GPIO_PUSEL_PULL_DOWN;
}
}
regs->MODE = (regs->MODE & ~MODE_MASK(pin)) |
(mode << MODE_PIN_SHIFT(pin));
regs->DBEN = (regs->DBEN & ~BIT(pin)) | (debounce_enable << pin);
regs->SMTEN = (regs->SMTEN & ~BIT(pin)) | (schmitt_enable << pin);
regs->DINOFF = (regs->DINOFF & ~DINOFF_MASK(pin)) |
(disable_input_path << DINOFF_PIN_SHIFT(pin));
regs->PUSEL = (regs->PUSEL & ~PUSEL_MASK(pin)) |
(bias << PUSEL_PIN_SHIFT(pin));
return 0;
}
static int gpio_numicro_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_numicro_config *cfg = dev->config;
*value = cfg->regs->PIN & PORT_PIN_MASK;
return 0;
}
static int gpio_numicro_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_numicro_config *cfg = dev->config;
cfg->regs->DATMSK = ~mask;
cfg->regs->DOUT = value;
return 0;
}
static int gpio_numicro_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_numicro_config *cfg = dev->config;
cfg->regs->DATMSK = ~mask;
cfg->regs->DOUT = PORT_PIN_MASK;
return 0;
}
static int gpio_numicro_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_numicro_config *cfg = dev->config;
cfg->regs->DATMSK = ~mask;
cfg->regs->DOUT = 0;
return 0;
}
static int gpio_numicro_port_toggle_bits(const struct device *dev, uint32_t mask)
{
const struct gpio_numicro_config *cfg = dev->config;
cfg->regs->DATMSK = 0;
cfg->regs->DOUT ^= mask;
return 0;
}
static int gpio_numicro_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin, enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_numicro_config *cfg = dev->config;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
struct gpio_numicro_data *data = dev->data;
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
uint32_t int_type = 0;
uint32_t int_level = 0;
uint32_t int_level_mask = BIT(pin) | BIT(pin + 16);
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode == GPIO_INT_MODE_DISABLE_ONLY) {
cfg->regs->INTEN &= ~(BIT(pin) | BIT(pin + 16));
return 0;
} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
cfg->regs->INTEN |= data->interrupt_en_reg_bak & (BIT(pin) | BIT(pin + 16));
return 0;
}
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
if (mode != GPIO_INT_MODE_DISABLED) {
int_type = (mode == GPIO_INT_MODE_LEVEL) ? 1 : 0;
switch (trig) {
case GPIO_INT_TRIG_LOW:
int_level = BIT(pin);
break;
case GPIO_INT_TRIG_HIGH:
int_level = BIT(pin + 16);
break;
case GPIO_INT_TRIG_BOTH:
int_level = BIT(pin) | BIT(pin + 16);
break;
default:
return -EINVAL;
}
}
cfg->regs->INTTYPE = (cfg->regs->INTTYPE & ~BIT(pin)) | (int_type << pin);
cfg->regs->INTEN = (cfg->regs->INTEN & ~int_level_mask) | int_level;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
data->interrupt_en_reg_bak = cfg->regs->INTEN;
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
return 0;
}
static int gpio_numicro_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_numicro_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void gpio_numicro_isr(const struct device *dev)
{
const struct gpio_numicro_config *cfg = dev->config;
struct gpio_numicro_data *data = dev->data;
uint32_t int_status;
int_status = cfg->regs->INTSRC;
/* Clear the port interrupts */
cfg->regs->INTSRC = int_status;
gpio_fire_callbacks(&data->callbacks, dev, int_status);
}
static const struct gpio_driver_api gpio_numicro_driver_api = {
.pin_configure = gpio_numicro_configure,
.port_get_raw = gpio_numicro_port_get_raw,
.port_set_masked_raw = gpio_numicro_port_set_masked_raw,
.port_set_bits_raw = gpio_numicro_port_set_bits_raw,
.port_clear_bits_raw = gpio_numicro_port_clear_bits_raw,
.port_toggle_bits = gpio_numicro_port_toggle_bits,
.pin_interrupt_configure = gpio_numicro_pin_interrupt_configure,
.manage_callback = gpio_numicro_manage_callback,
};
#define GPIO_NUMICRO_INIT(n) \
static int gpio_numicro_port##n##_init(const struct device *dev)\
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_numicro_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
return 0; \
} \
\
static struct gpio_numicro_data gpio_numicro_port##n##_data; \
\
static const struct gpio_numicro_config gpio_numicro_port##n##_config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.regs = (GPIO_T *)DT_INST_REG_ADDR(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_numicro_port##n##_init, \
NULL, \
&gpio_numicro_port##n##_data, \
&gpio_numicro_port##n##_config, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_numicro_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NUMICRO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_numicro.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,132 |
```unknown
config GPIO_MMIO32
bool
help
This is a driver for accessing a simple, fixed purpose, 32-bit
memory-mapped i/o register using the same APIs as GPIO drivers. This
is useful when an SoC or board has registers that aren't part of a
GPIO IP block and these registers are used to control things that
Zephyr normally expects to be specified using a GPIO pin, e.g. for
driving an LED, or chip-select line for an SPI device.
``` | /content/code_sandbox/drivers/gpio/Kconfig.mmio32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_davinci_gpio
#include <errno.h>
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/pinctrl.h>
LOG_MODULE_REGISTER(gpio_davinci, CONFIG_GPIO_LOG_LEVEL);
/* Helper Macros for GPIO */
#define DEV_CFG(dev) \
((const struct gpio_davinci_config *)((dev)->config))
#define DEV_DATA(dev) ((struct gpio_davinci_data *)(dev)->data)
#define DEV_GPIO_CFG_BASE(dev) \
((struct gpio_davinci_regs *)DEVICE_MMIO_NAMED_GET(dev, port_base))
#define GPIO_DAVINCI_DIR_RESET_VAL (0xFFFFFFFF)
struct gpio_davinci_regs {
uint32_t dir;
uint32_t out_data;
uint32_t set_data;
uint32_t clr_data;
uint32_t in_data;
uint32_t set_ris_trig;
uint32_t clr_ris_trig;
uint32_t set_fal_trig;
uint32_t clr_fal_trig;
uint32_t intstat;
};
struct gpio_davinci_data {
struct gpio_driver_data common;
DEVICE_MMIO_NAMED_RAM(port_base);
sys_slist_t cb;
};
struct gpio_davinci_config {
void (*bank_config)(const struct device *dev);
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(port_base);
uint32_t port_num;
const struct pinctrl_dev_config *pcfg;
};
static int gpio_davinci_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
regs->set_data = BIT(pin);
} else {
regs->clr_data = BIT(pin);
}
regs->dir &= ~(BIT(pin));
} else {
regs->dir |= BIT(pin);
}
return 0;
}
static int gpio_davinci_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
*value = regs->in_data;
return 0;
}
static int gpio_davinci_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask, gpio_port_value_t value)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
regs->out_data = (regs->out_data & (~mask)) | (mask & value);
return 0;
}
static int gpio_davinci_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
regs->set_data |= mask;
return 0;
}
static int gpio_davinci_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
regs->clr_data |= mask;
return 0;
}
static int gpio_davinci_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
regs->out_data ^= mask;
return 0;
}
static const struct gpio_driver_api gpio_davinci_driver_api = {
.pin_configure = gpio_davinci_configure,
.port_get_raw = gpio_davinci_port_get_raw,
.port_set_masked_raw = gpio_davinci_port_set_masked_raw,
.port_set_bits_raw = gpio_davinci_port_set_bits_raw,
.port_clear_bits_raw = gpio_davinci_port_clear_bits_raw,
.port_toggle_bits = gpio_davinci_port_toggle_bits
};
static int gpio_davinci_init(const struct device *dev)
{
const struct gpio_davinci_config *config = DEV_CFG(dev);
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
int ret;
DEVICE_MMIO_NAMED_MAP(dev, port_base, K_MEM_CACHE_NONE);
regs->dir = GPIO_DAVINCI_DIR_RESET_VAL;
config->bank_config(dev);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("failed to apply pinctrl");
return ret;
}
return 0;
}
#define GPIO_DAVINCI_INIT_FUNC(n) \
static void gpio_davinci_bank_##n##_config(const struct device *dev) \
{ \
volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); \
ARG_UNUSED(regs); \
}
#define GPIO_DAVINCI_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
GPIO_DAVINCI_INIT_FUNC(n); \
static const struct gpio_davinci_config gpio_davinci_##n##_config = { \
.bank_config = gpio_davinci_bank_##n##_config, \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
DEVICE_MMIO_NAMED_ROM_INIT(port_base, DT_DRV_INST(n)), \
.port_num = n, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
}; \
\
static struct gpio_davinci_data gpio_davinci_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_davinci_init, \
NULL, \
&gpio_davinci_##n##_data, \
&gpio_davinci_##n##_config, \
PRE_KERNEL_2, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_davinci_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_DAVINCI_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_davinci.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,391 |
```unknown
config GPIO_RZT2M
bool "Renesas RZT2M GPIO"
default y
depends on DT_HAS_RENESAS_RZT2M_GPIO_ENABLED
help
Enable Renesas RZT2M GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.rzt2m | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config GPIO_RENESAS_RA
bool "Renesas RA Series GPIO driver"
default y
select GPIO_GET_CONFIG
depends on DT_HAS_RENESAS_RA_GPIO_ENABLED
help
Enable Renesas RA series GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.renesas_ra | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT brcm_iproc_gpio
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#define IPROC_GPIO_DATA_IN_OFFSET 0x00
#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
#define IPROC_GPIO_OUT_EN_OFFSET 0x08
#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
#define IPROC_GPIO_INT_DE_OFFSET 0x10
#define IPROC_GPIO_INT_EDGE_OFFSET 0x14
#define IPROC_GPIO_INT_MSK_OFFSET 0x18
#define IPROC_GPIO_INT_STAT_OFFSET 0x1c
#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
#define IPROC_GPIO_INT_CLR_OFFSET 0x24
#define IPROC_GPIO_PAD_RES_OFFSET 0x34
#define IPROC_GPIO_RES_EN_OFFSET 0x38
struct gpio_iproc_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
mem_addr_t base;
void (*irq_config_func)(const struct device *dev);
};
struct gpio_iproc_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
#define DEV_CFG(dev) ((const struct gpio_iproc_config *const)(dev)->config)
#define DEV_DATA(dev) ((struct gpio_iproc_data *const)(dev)->data)
static int gpio_iproc_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
/* Setup the pin direcion. */
if (flags & GPIO_OUTPUT) {
/* configure pin for output */
sys_set_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin);
} else if (flags & GPIO_INPUT) {
/* configure pin for input */
sys_clear_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin);
}
return 0;
}
static int gpio_iproc_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
*value = sys_read32(base + IPROC_GPIO_DATA_IN_OFFSET);
return 0;
}
static int gpio_iproc_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET);
value = (value & (~mask)) | (value & mask);
sys_write32(base + IPROC_GPIO_DATA_OUT_OFFSET, value);
return 0;
}
static int gpio_iproc_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
sys_write32(base + IPROC_GPIO_DATA_OUT_OFFSET, mask);
return 0;
}
static int gpio_iproc_port_clear_bits_raw(const struct device *dev, uint32_t mask)
{
uint32_t value;
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
/* Clear pins. */
value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET);
value = (value & ~mask);
sys_write32(base + IPROC_GPIO_DATA_OUT_OFFSET, value);
return 0;
}
static int gpio_iproc_port_toggle_bits(const struct device *dev, uint32_t mask)
{
uint32_t value;
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
/* toggles pins. */
value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET);
value = (value ^ mask);
sys_write32(base + IPROC_GPIO_DATA_OUT_OFFSET, value);
return 0;
}
static int gpio_iproc_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
/* check for interrupt configurations */
if (mode & GPIO_INT_ENABLE) {
if (mode & GPIO_INT_EDGE) {
sys_clear_bit(base + IPROC_GPIO_INT_TYPE_OFFSET, pin);
} else {
sys_set_bit(base + IPROC_GPIO_INT_TYPE_OFFSET, pin);
}
/* Generate interrupt of both falling/rising edge */
if (trig & GPIO_INT_EDGE_BOTH) {
sys_set_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin);
} else if (trig & GPIO_INT_HIGH_1) {
/* Generate interrupt on rising edge */
sys_clear_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin);
sys_set_bit(base + IPROC_GPIO_INT_EDGE_OFFSET, pin);
} else if (trig & GPIO_INT_LOW_0) {
/* Generate interrupt on falling edge */
sys_clear_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin);
sys_clear_bit(base + IPROC_GPIO_INT_EDGE_OFFSET, pin);
}
/* Unmask the interrupt */
sys_clear_bit(base + IPROC_GPIO_INT_MSTAT_OFFSET, pin);
} else {
sys_set_bit(base + IPROC_GPIO_INT_MSK_OFFSET, pin);
}
return 0;
}
static void gpio_iproc_isr(const struct device *dev)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
mem_addr_t base = cfg->base;
struct gpio_iproc_data *context = dev->data;
uint32_t int_stat;
int_stat = sys_read32(base + IPROC_GPIO_INT_STAT_OFFSET);
/* Clear the source of the interrupt */
sys_write32(int_stat, base + IPROC_GPIO_INT_CLR_OFFSET);
/* Handle the interrupt */
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_iproc_manage_callback(const struct device *port, struct gpio_callback *callback,
bool set)
{
struct gpio_iproc_data *context = port->data;
return gpio_manage_callback(&context->cb, callback, set);
}
static const struct gpio_driver_api gpio_iproc_api = {
.pin_configure = gpio_iproc_configure,
.port_get_raw = gpio_iproc_port_get_raw,
.port_set_masked_raw = gpio_iproc_port_set_masked_raw,
.port_set_bits_raw = gpio_iproc_port_set_bits_raw,
.port_clear_bits_raw = gpio_iproc_port_clear_bits_raw,
.port_toggle_bits = gpio_iproc_port_toggle_bits,
.pin_interrupt_configure = gpio_iproc_pin_interrupt_configure,
.manage_callback = gpio_iproc_manage_callback,
};
int gpio_iproc_init(const struct device *dev)
{
const struct gpio_iproc_config *const cfg = DEV_CFG(dev);
cfg->irq_config_func(dev);
return 0;
}
#define GPIO_IPROC_INIT(n) \
static void port_iproc_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_iproc_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
} \
\
static const struct gpio_iproc_config gpio_port_config_##n = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = DT_INST_REG_ADDR(n), \
.irq_config_func = port_iproc_config_func_##n, \
}; \
\
static struct gpio_iproc_data gpio_port_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_iproc_init, NULL, &gpio_port_data_##n, \
&gpio_port_config_##n, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_iproc_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_IPROC_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_iproc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,767 |
```unknown
config GPIO_SC18IM704
bool "NXP SC18IM704 GPIO controller driver"
default y
depends on I2C_SC18IM704
depends on DT_HAS_NXP_SC18IM704_GPIO_ENABLED
help
Enables NXP SC18IM704 GPIO controller driver
config GPIO_SC18IM704_INIT_PRIORITY
int "SC18IM704 GPIO init priority"
default 52
depends on GPIO_SC18IM704
help
SC18IM704 GPIO controller initialization priority.
Note: Has to be greater than the parent SC18IM704 bridge initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.sc18im704 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/atmel-sam0-gpio.h>
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/sam0_eic.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#ifndef PORT_PMUX_PMUXE_A_Val
#define PORT_PMUX_PMUXE_A_Val (0)
#endif
struct gpio_sam0_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
PortGroup *regs;
#ifdef CONFIG_SAM0_EIC
uint8_t id;
#endif
};
struct gpio_sam0_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
const struct device *dev;
gpio_port_pins_t debounce;
#ifdef CONFIG_SAM0_EIC
sys_slist_t callbacks;
#endif
};
#ifdef CONFIG_SAM0_EIC
static void gpio_sam0_isr(uint32_t pins, void *arg)
{
struct gpio_sam0_data *const data = (struct gpio_sam0_data *)arg;
gpio_fire_callbacks(&data->callbacks, data->dev, pins);
}
#endif
static int gpio_sam0_config(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_sam0_config *config = dev->config;
struct gpio_sam0_data *data = dev->data;
PortGroup *regs = config->regs;
PORT_PINCFG_Type pincfg = {
.reg = 0,
};
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* Supports disconnected, input, output, or bidirectional */
if ((flags & GPIO_INPUT) != 0) {
pincfg.bit.INEN = 1;
}
if ((flags & GPIO_OUTPUT) != 0) {
/* Output is incompatible with pull */
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
/* Bidirectional is supported */
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
regs->OUTCLR.reg = BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
regs->OUTSET.reg = BIT(pin);
}
regs->DIRSET.reg = BIT(pin);
} else {
/* Not output, may be input */
regs->DIRCLR.reg = BIT(pin);
/* Pull configuration is supported if not output */
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
pincfg.bit.PULLEN = 1;
if ((flags & GPIO_PULL_UP) != 0) {
regs->OUTSET.reg = BIT(pin);
} else {
regs->OUTCLR.reg = BIT(pin);
}
}
}
/* Preserve debounce flag for interrupt configuration. */
WRITE_BIT(data->debounce, pin,
((flags & SAM0_GPIO_DEBOUNCE) != 0)
&& (pincfg.bit.INEN != 0));
/* Write the now-built pin configuration */
regs->PINCFG[pin] = pincfg;
return 0;
}
static int gpio_sam0_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_sam0_config *config = dev->config;
*value = config->regs->IN.reg;
return 0;
}
static int gpio_sam0_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_sam0_config *config = dev->config;
uint32_t out = config->regs->OUT.reg;
config->regs->OUT.reg = (out & ~mask) | (value & mask);
return 0;
}
static int gpio_sam0_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_sam0_config *config = dev->config;
config->regs->OUTSET.reg = pins;
return 0;
}
static int gpio_sam0_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_sam0_config *config = dev->config;
config->regs->OUTCLR.reg = pins;
return 0;
}
static int gpio_sam0_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_sam0_config *config = dev->config;
config->regs->OUTTGL.reg = pins;
return 0;
}
#ifdef CONFIG_SAM0_EIC
static int gpio_sam0_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_sam0_config *config = dev->config;
struct gpio_sam0_data *const data = dev->data;
PortGroup *regs = config->regs;
PORT_PINCFG_Type pincfg = {
.reg = regs->PINCFG[pin].reg,
};
enum sam0_eic_trigger trigger;
int rc = 0;
data->dev = dev;
switch (mode) {
case GPIO_INT_MODE_DISABLED:
pincfg.bit.PMUXEN = 0;
rc = sam0_eic_disable_interrupt(config->id, pin);
if (rc == -EBUSY) {
/* Ignore diagnostic disabling disabled */
rc = 0;
}
if (rc == 0) {
rc = sam0_eic_release(config->id, pin);
}
break;
case GPIO_INT_MODE_LEVEL:
case GPIO_INT_MODE_EDGE:
/* Enabling interrupts on a pin requires disconnecting
* the pin from the I/O pin controller (PORT) module
* and connecting it to the External Interrupt
* Controller (EIC). This would prevent using the pin
* as an output, so interrupts are only supported if
* the pin is configured as input-only.
*/
if ((pincfg.bit.INEN == 0)
|| ((regs->DIR.reg & BIT(pin)) != 0)) {
rc = -ENOTSUP;
break;
}
/* Transfer control to EIC */
pincfg.bit.PMUXEN = 1;
if ((pin & 1U) != 0) {
regs->PMUX[pin / 2U].bit.PMUXO = PORT_PMUX_PMUXE_A_Val;
} else {
regs->PMUX[pin / 2U].bit.PMUXE = PORT_PMUX_PMUXE_A_Val;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
trigger = (mode == GPIO_INT_MODE_LEVEL)
? SAM0_EIC_LOW
: SAM0_EIC_FALLING;
break;
case GPIO_INT_TRIG_HIGH:
trigger = (mode == GPIO_INT_MODE_LEVEL)
? SAM0_EIC_HIGH
: SAM0_EIC_RISING;
break;
case GPIO_INT_TRIG_BOTH:
trigger = SAM0_EIC_BOTH;
break;
default:
rc = -EINVAL;
break;
}
if (rc == 0) {
rc = sam0_eic_acquire(config->id, pin, trigger,
(data->debounce & BIT(pin)) != 0,
gpio_sam0_isr, data);
}
if (rc == 0) {
rc = sam0_eic_enable_interrupt(config->id, pin);
}
break;
default:
rc = -EINVAL;
break;
}
if (rc == 0) {
/* Update the pin configuration */
regs->PINCFG[pin] = pincfg;
}
return rc;
}
static int gpio_sam0_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_sam0_data *const data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static uint32_t gpio_sam0_get_pending_int(const struct device *dev)
{
const struct gpio_sam0_config *config = dev->config;
return sam0_eic_interrupt_pending(config->id);
}
#endif
static const struct gpio_driver_api gpio_sam0_api = {
.pin_configure = gpio_sam0_config,
.port_get_raw = gpio_sam0_port_get_raw,
.port_set_masked_raw = gpio_sam0_port_set_masked_raw,
.port_set_bits_raw = gpio_sam0_port_set_bits_raw,
.port_clear_bits_raw = gpio_sam0_port_clear_bits_raw,
.port_toggle_bits = gpio_sam0_port_toggle_bits,
#ifdef CONFIG_SAM0_EIC
.pin_interrupt_configure = gpio_sam0_pin_interrupt_configure,
.manage_callback = gpio_sam0_manage_callback,
.get_pending_int = gpio_sam0_get_pending_int,
#endif
};
static int gpio_sam0_init(const struct device *dev) { return 0; }
/* Port A */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(porta), okay)
static const struct gpio_sam0_config gpio_sam0_config_0 = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
},
.regs = (PortGroup *)DT_REG_ADDR(DT_NODELABEL(porta)),
#ifdef CONFIG_SAM0_EIC
.id = 0,
#endif
};
static struct gpio_sam0_data gpio_sam0_data_0;
DEVICE_DT_DEFINE(DT_NODELABEL(porta),
gpio_sam0_init, NULL,
&gpio_sam0_data_0, &gpio_sam0_config_0,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_sam0_api);
#endif
/* Port B */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(portb), okay)
static const struct gpio_sam0_config gpio_sam0_config_1 = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(1),
},
.regs = (PortGroup *)DT_REG_ADDR(DT_NODELABEL(portb)),
#ifdef CONFIG_SAM0_EIC
.id = 1,
#endif
};
static struct gpio_sam0_data gpio_sam0_data_1;
DEVICE_DT_DEFINE(DT_NODELABEL(portb),
gpio_sam0_init, NULL,
&gpio_sam0_data_1, &gpio_sam0_config_1,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_sam0_api);
#endif
/* Port C */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(portc), okay)
static const struct gpio_sam0_config gpio_sam0_config_2 = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(2),
},
.regs = (PortGroup *)DT_REG_ADDR(DT_NODELABEL(portc)),
#ifdef CONFIG_SAM0_EIC
.id = 2,
#endif
};
static struct gpio_sam0_data gpio_sam0_data_2;
DEVICE_DT_DEFINE(DT_NODELABEL(portc),
gpio_sam0_init, NULL,
&gpio_sam0_data_2, &gpio_sam0_config_2,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_sam0_api);
#endif
/* Port D */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(portd), okay)
static const struct gpio_sam0_config gpio_sam0_config_3 = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(3),
},
.regs = (PortGroup *)DT_REG_ADDR(DT_NODELABEL(portd)),
#ifdef CONFIG_SAM0_EIC
.id = 3,
#endif
};
static struct gpio_sam0_data gpio_sam0_data_3;
DEVICE_DT_DEFINE(DT_NODELABEL(portd),
gpio_sam0_init, NULL,
&gpio_sam0_data_3, &gpio_sam0_config_3,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_sam0_api);
#endif
``` | /content/code_sandbox/drivers/gpio/gpio_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,655 |
```unknown
config GPIO_ALTERA_PIO
bool "Altera PIO"
default y
depends on DT_HAS_ALTR_PIO_1_0_ENABLED
help
Enable driver for Altera PIO
``` | /content/code_sandbox/drivers/gpio/Kconfig.altera | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_gpio
#include <zephyr/types.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
#include <driverlib/gpio.h>
#include <driverlib/interrupt.h>
#include <driverlib/ioc.h>
#include <driverlib/prcm.h>
#include <inc/hw_aon_event.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC26XX.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
/* bits 16-18 in iocfg registers correspond to interrupt settings */
#define IOCFG_INT_MASK 0x00070000
/* the rest are for general (non-interrupt) config */
#define IOCFG_GEN_MASK (~IOCFG_INT_MASK)
struct gpio_cc13xx_cc26xx_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t callbacks;
};
static struct gpio_cc13xx_cc26xx_data gpio_cc13xx_cc26xx_data_0;
static const struct gpio_driver_config gpio_cc13xx_cc26xx_cfg_0 = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
};
static int gpio_cc13xx_cc26xx_port_set_bits_raw(const struct device *port,
uint32_t mask);
static int gpio_cc13xx_cc26xx_port_clear_bits_raw(const struct device *port,
uint32_t mask);
static int gpio_cc13xx_cc26xx_config(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
uint32_t config = 0;
__ASSERT_NO_MSG(pin < NUM_IO_MAX);
switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
case GPIO_INPUT:
config = IOC_INPUT_ENABLE;
break;
case GPIO_OUTPUT:
config = IOC_INPUT_DISABLE;
break;
case 0: /* disconnected */
IOCPortConfigureSet(pin, IOC_PORT_GPIO, IOC_NO_IOPULL);
GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
return 0;
default:
return -ENOTSUP;
}
config |= IOC_SLEW_DISABLE | IOC_NO_WAKE_UP;
config |= (flags & CC13XX_CC26XX_GPIO_DEBOUNCE) ?
IOC_HYST_ENABLE : IOC_HYST_DISABLE;
switch (flags & CC13XX_CC26XX_GPIO_DS_MASK) {
case CC13XX_CC26XX_GPIO_DS_DFLT:
config |= IOC_CURRENT_2MA | IOC_STRENGTH_AUTO;
break;
case CC13XX_CC26XX_GPIO_DS_ALT:
/*
* Not all GPIO support 8ma, but setting that bit will use the
* highest supported drive strength.
*/
config |= IOC_CURRENT_8MA | IOC_STRENGTH_MAX;
break;
default:
return -ENOTSUP;
}
switch (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
case 0:
config |= IOC_NO_IOPULL;
break;
case GPIO_PULL_UP:
config |= IOC_IOPULL_UP;
break;
case GPIO_PULL_DOWN:
config |= IOC_IOPULL_DOWN;
break;
default:
return -EINVAL;
}
config |= IOCPortConfigureGet(pin) & IOCFG_INT_MASK;
IOCPortConfigureSet(pin, IOC_PORT_GPIO, config);
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_cc13xx_cc26xx_port_set_bits_raw(port, BIT(pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_cc13xx_cc26xx_port_clear_bits_raw(port, BIT(pin));
}
GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_ENABLE);
} else {
GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
}
return 0;
}
static int gpio_cc13xx_cc26xx_port_get_raw(const struct device *port,
uint32_t *value)
{
__ASSERT_NO_MSG(value != NULL);
*value = GPIO_readMultiDio(GPIO_DIO_ALL_MASK);
return 0;
}
static int gpio_cc13xx_cc26xx_port_set_masked_raw(const struct device *port,
uint32_t mask,
uint32_t value)
{
GPIO_setMultiDio(mask & value);
GPIO_clearMultiDio(mask & ~value);
return 0;
}
static int gpio_cc13xx_cc26xx_port_set_bits_raw(const struct device *port,
uint32_t mask)
{
GPIO_setMultiDio(mask);
return 0;
}
static int gpio_cc13xx_cc26xx_port_clear_bits_raw(const struct device *port,
uint32_t mask)
{
GPIO_clearMultiDio(mask);
return 0;
}
static int gpio_cc13xx_cc26xx_port_toggle_bits(const struct device *port,
uint32_t mask)
{
GPIO_toggleMultiDio(mask);
return 0;
}
static int gpio_cc13xx_cc26xx_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
uint32_t config = 0;
if (mode != GPIO_INT_MODE_DISABLED) {
if (mode == GPIO_INT_MODE_EDGE) {
if (trig == GPIO_INT_TRIG_BOTH) {
config |= IOC_BOTH_EDGES;
} else if (trig == GPIO_INT_TRIG_HIGH) {
config |= IOC_RISING_EDGE;
} else { /* GPIO_INT_TRIG_LOW */
config |= IOC_FALLING_EDGE;
}
} else {
return -ENOTSUP;
}
config |= IOC_INT_ENABLE;
} else {
config |= IOC_INT_DISABLE | IOC_NO_EDGE;
}
config |= IOCPortConfigureGet(pin) & IOCFG_GEN_MASK;
IOCPortConfigureSet(pin, IOC_PORT_GPIO, config);
return 0;
}
static int gpio_cc13xx_cc26xx_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
struct gpio_cc13xx_cc26xx_data *data = port->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static uint32_t gpio_cc13xx_cc26xx_get_pending_int(const struct device *dev)
{
return GPIO_getEventMultiDio(GPIO_DIO_ALL_MASK);
}
static void gpio_cc13xx_cc26xx_isr(const struct device *dev)
{
struct gpio_cc13xx_cc26xx_data *data = dev->data;
uint32_t status = GPIO_getEventMultiDio(GPIO_DIO_ALL_MASK);
GPIO_clearEventMultiDio(status);
gpio_fire_callbacks(&data->callbacks, dev, status);
}
static int gpio_cc13xx_cc26xx_init(const struct device *dev)
{
#ifdef CONFIG_PM
/* Set dependency on gpio resource to turn on power domains */
Power_setDependency(PowerCC26XX_PERIPH_GPIO);
#else
/* Enable peripheral power domain */
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
/* Enable GPIO peripheral */
PRCMPeripheralRunEnable(PRCM_PERIPH_GPIO);
/* Load PRCM settings */
PRCMLoadSet();
while (!PRCMLoadGet()) {
continue;
}
#endif
/* Enable edge detection on any pad as a wakeup source */
HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) =
(HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) &
(~AON_EVENT_MCUWUSEL_WU1_EV_M)) |
AON_EVENT_MCUWUSEL_WU1_EV_PAD;
/* Enable IRQ */
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
gpio_cc13xx_cc26xx_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
/* Peripheral should not be accessed until power domain is on. */
while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_PERIPH) !=
PRCM_DOMAIN_POWER_ON) {
continue;
}
return 0;
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_cc13xx_cc26xx_port_get_direction(const struct device *port, gpio_port_pins_t map,
gpio_port_pins_t *inputs,
gpio_port_pins_t *outputs)
{
uint32_t pin;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
const struct gpio_driver_config *cfg = port->config;
map &= cfg->port_pin_mask;
if (inputs != NULL) {
for (pin = find_lsb_set(map) - 1; map;
map &= ~BIT(pin), pin = find_lsb_set(map) - 1) {
ip |= !!(IOCPortConfigureGet(pin) & IOC_INPUT_ENABLE) * BIT(pin);
}
*inputs = ip;
}
if (outputs != NULL) {
for (pin = find_lsb_set(map) - 1; map;
map &= ~BIT(pin), pin = find_lsb_set(map) - 1) {
op |= GPIO_getOutputEnableDio(pin) * BIT(pin);
}
*outputs = op;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_cc13xx_cc26xx_driver_api = {
.pin_configure = gpio_cc13xx_cc26xx_config,
.port_get_raw = gpio_cc13xx_cc26xx_port_get_raw,
.port_set_masked_raw = gpio_cc13xx_cc26xx_port_set_masked_raw,
.port_set_bits_raw = gpio_cc13xx_cc26xx_port_set_bits_raw,
.port_clear_bits_raw = gpio_cc13xx_cc26xx_port_clear_bits_raw,
.port_toggle_bits = gpio_cc13xx_cc26xx_port_toggle_bits,
.pin_interrupt_configure = gpio_cc13xx_cc26xx_pin_interrupt_configure,
.manage_callback = gpio_cc13xx_cc26xx_manage_callback,
.get_pending_int = gpio_cc13xx_cc26xx_get_pending_int,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_cc13xx_cc26xx_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
DEVICE_DT_INST_DEFINE(0, gpio_cc13xx_cc26xx_init,
NULL, &gpio_cc13xx_cc26xx_data_0,
&gpio_cc13xx_cc26xx_cfg_0,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_cc13xx_cc26xx_driver_api);
``` | /content/code_sandbox/drivers/gpio/gpio_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,295 |
```unknown
# NUMAKER GPIO driver configuration options
config GPIO_NUMAKER
bool "Nuvoton NUMAKER MCU gpio driver"
default y
select HAS_NUMAKER_GPIO
depends on DT_HAS_NUVOTON_NUMAKER_GPIO_ENABLED
help
This option enables the GPIO driver for Nuvoton NUMAKER family of
processors.
``` | /content/code_sandbox/drivers/gpio/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
# SiFive Freedom GPIO configuration option
config GPIO_SIFIVE
bool "SiFive Freedom Processor GPIO driver"
default y
depends on DT_HAS_SIFIVE_GPIO0_ENABLED
help
Enable driver for the SiFive Freedom GPIO controller.
Says n if not sure.
``` | /content/code_sandbox/drivers/gpio/Kconfig.sifive | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Renesas RCAR configuration options
config GPIO_RCAR
bool "Renesas R-Car GPIO"
default y
depends on DT_HAS_RENESAS_RCAR_GPIO_ENABLED
help
Enable Renesas RCAR GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.rcar | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_nct38xx_gpio_port
#include "gpio_nct38xx.h"
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mfd/nct38xx.h>
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(gpio_ntc38xx, CONFIG_GPIO_LOG_LEVEL);
/* Driver config */
struct gpio_nct38xx_port_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* NCT38XX controller dev */
const struct device *mfd;
/* GPIO port index */
uint8_t gpio_port;
/* GPIO port 0 pinmux mask */
uint8_t pinmux_mask;
};
/* Driver data */
struct gpio_nct38xx_port_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* GPIO callback list */
sys_slist_t cb_list_gpio;
/* lock NCT38xx register access */
struct k_sem *lock;
/* I2C device for the MFD parent */
const struct i2c_dt_spec *i2c_dev;
};
/* GPIO api functions */
static int gpio_nct38xx_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint32_t mask;
uint8_t new_reg;
int ret;
/* Don't support simultaneous in/out mode */
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
/* Don't support "open source" mode */
if (((flags & GPIO_SINGLE_ENDED) != 0) && ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
return -ENOTSUP;
}
/* Don't support pull-up/pull-down */
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
return -ENOTSUP;
}
k_sem_take(data->lock, K_FOREVER);
/* Pin multiplexing */
if (config->gpio_port == 0) {
/* Set the mux control bit, but ensure the reserved fields
* are cleared. Note that pinmux_mask contains the set
* of non-reserved bits.
*/
new_reg = BIT(pin) & config->pinmux_mask;
mask = BIT(pin) | ~config->pinmux_mask;
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_MUX_CONTROL, mask, new_reg);
if (ret < 0) {
goto done;
}
}
/* Configure pin as input. */
if (flags & GPIO_INPUT) {
/* Clear the direction bit to set as an input */
new_reg = 0;
mask = BIT(pin);
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DIR(config->gpio_port),
mask, new_reg);
goto done;
}
/* Select open drain 0:push-pull 1:open-drain */
mask = BIT(pin);
if (flags & GPIO_OPEN_DRAIN) {
new_reg = mask;
} else {
new_reg = 0;
}
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_OD_SEL(config->gpio_port),
mask, new_reg);
if (ret < 0) {
goto done;
}
/* Set level 0:low 1:high */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
new_reg = mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
new_reg = 0;
}
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
mask, new_reg);
if (ret < 0) {
goto done;
}
/* Configure pin as output, if requested 0:input 1:output */
if (flags & GPIO_OUTPUT) {
new_reg = BIT(pin);
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DIR(config->gpio_port),
mask, new_reg);
}
done:
k_sem_give(data->lock);
return ret;
}
#ifdef CONFIG_GPIO_GET_CONFIG
int gpio_nct38xx_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint32_t mask = BIT(pin);
uint8_t reg;
int ret;
k_sem_take(data->lock, K_FOREVER);
if (config->gpio_port == 0) {
if (mask & (~config->common.port_pin_mask)) {
ret = -ENOTSUP;
goto done;
}
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_MUX_CONTROL, ®);
if (ret < 0) {
goto done;
}
if ((mask & config->pinmux_mask) && (mask & (~reg))) {
*flags = GPIO_DISCONNECTED;
goto done;
}
}
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DIR(config->gpio_port), ®);
if (ret < 0) {
goto done;
}
if (reg & mask) {
/* Output */
*flags = GPIO_OUTPUT;
/* 0 - push-pull, 1 - open-drain */
ret = i2c_reg_read_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_OD_SEL(config->gpio_port), ®);
if (ret < 0) {
goto done;
}
if (mask & reg) {
*flags |= GPIO_OPEN_DRAIN;
}
/* Output value */
ret = i2c_reg_read_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), ®);
if (ret < 0) {
goto done;
}
if (mask & reg) {
*flags |= GPIO_OUTPUT_HIGH;
} else {
*flags |= GPIO_OUTPUT_LOW;
}
} else {
/* Input */
*flags = GPIO_INPUT;
}
done:
k_sem_give(data->lock);
return ret;
}
#endif /* CONFIG_GPIO_GET_CONFIG */
static int gpio_nct38xx_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
int ret;
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_IN(config->gpio_port),
(uint8_t *)value);
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
int ret;
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
mask, value);
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
int ret;
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
mask, mask);
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
int ret;
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
mask, 0);
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint8_t reg, new_reg;
int ret;
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
®);
if (ret < 0) {
goto done;
}
new_reg = reg ^ mask;
if (new_reg != reg) {
ret = i2c_reg_write_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), new_reg);
}
done:
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint8_t new_reg, new_rise, new_fall;
int ret;
uint32_t mask = BIT(pin);
k_sem_take(data->lock, K_FOREVER);
/* Disable irq before configuring them */
new_reg = 0;
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port),
mask, new_reg);
/* Configure and enable interrupt? */
if (mode == GPIO_INT_MODE_DISABLED) {
goto done;
}
/* set edge register */
if (mode == GPIO_INT_MODE_EDGE) {
if (trig == GPIO_INT_TRIG_LOW) {
new_rise = 0;
new_fall = mask;
} else if (trig == GPIO_INT_TRIG_HIGH) {
new_rise = mask;
new_fall = 0;
} else if (trig == GPIO_INT_TRIG_BOTH) {
new_rise = mask;
new_fall = mask;
} else {
LOG_ERR("Invalid interrupt trigger type %d", trig);
return -EINVAL;
}
} else {
/* level mode */
new_rise = 0;
new_fall = 0;
}
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_ALERT_RISE(config->gpio_port),
mask, new_rise);
if (ret < 0) {
goto done;
}
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_ALERT_FALL(config->gpio_port),
mask, new_fall);
if (ret < 0) {
goto done;
}
if (mode == GPIO_INT_MODE_LEVEL) {
/* set active high/low */
if (trig == GPIO_INT_TRIG_LOW) {
new_reg = 0;
} else if (trig == GPIO_INT_TRIG_HIGH) {
new_reg = mask;
} else {
LOG_ERR("Invalid interrupt trigger type %d", trig);
ret = -EINVAL;
goto done;
}
ret = i2c_reg_update_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_ALERT_LEVEL(config->gpio_port), mask,
new_reg);
if (ret < 0) {
goto done;
}
}
/* Clear pending bit */
ret = i2c_reg_write_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port),
mask);
if (ret < 0) {
goto done;
}
/* Enable it after configuration is completed */
new_reg = mask;
ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port),
mask, new_reg);
done:
k_sem_give(data->lock);
return ret;
}
static int gpio_nct38xx_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct gpio_nct38xx_port_data *const data = dev->data;
return gpio_manage_callback(&data->cb_list_gpio, callback, set);
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_nct38xx_port_get_direction(const struct device *dev, gpio_port_pins_t mask,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint8_t dir_reg;
int ret;
k_sem_take(data->lock, K_FOREVER);
if (config->gpio_port == 0) {
uint8_t enabled_gpios;
/* Remove the disabled GPIOs from the mask */
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_MUX_CONTROL, &enabled_gpios);
mask &= (enabled_gpios & config->common.port_pin_mask);
if (ret < 0) {
goto done;
}
}
/* Read direction register, 0 - input, 1 - output */
ret = i2c_reg_read_byte_dt(data->i2c_dev, NCT38XX_REG_GPIO_DIR(config->gpio_port),
&dir_reg);
if (ret < 0) {
goto done;
}
if (inputs) {
*inputs = mask & (~dir_reg);
}
if (outputs) {
*outputs = mask & dir_reg;
}
done:
k_sem_give(data->lock);
return ret;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
int gpio_nct38xx_dispatch_port_isr(const struct device *dev)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
uint8_t alert_pins, mask;
int ret;
do {
k_sem_take(data->lock, K_FOREVER);
ret = i2c_reg_read_byte_dt(
data->i2c_dev, NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port), &alert_pins);
if (ret < 0) {
k_sem_give(data->lock);
return ret;
}
ret = i2c_reg_read_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), &mask);
if (ret < 0) {
k_sem_give(data->lock);
return ret;
}
alert_pins &= mask;
if (alert_pins) {
ret = i2c_reg_write_byte_dt(data->i2c_dev,
NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port),
alert_pins);
if (ret < 0) {
k_sem_give(data->lock);
return ret;
}
}
k_sem_give(data->lock);
gpio_fire_callbacks(&data->cb_list_gpio, dev, alert_pins);
/*
* Vendor defined alert is generated if at least one STATn bit
* changes from 0 to 1. We should guarantee the STATn bit is
* clear to 0 before leaving isr.
*/
} while (alert_pins);
return 0;
}
static const struct gpio_driver_api gpio_nct38xx_driver = {
.pin_configure = gpio_nct38xx_pin_config,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_nct38xx_pin_get_config,
#endif /* CONFIG_GPIO_GET_CONFIG */
.port_get_raw = gpio_nct38xx_port_get_raw,
.port_set_masked_raw = gpio_nct38xx_port_set_masked_raw,
.port_set_bits_raw = gpio_nct38xx_port_set_bits_raw,
.port_clear_bits_raw = gpio_nct38xx_port_clear_bits_raw,
.port_toggle_bits = gpio_nct38xx_port_toggle_bits,
.pin_interrupt_configure = gpio_nct38xx_pin_interrupt_configure,
.manage_callback = gpio_nct38xx_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_nct38xx_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
static int gpio_nct38xx_port_init(const struct device *dev)
{
const struct gpio_nct38xx_port_config *const config = dev->config;
struct gpio_nct38xx_port_data *const data = dev->data;
if (!device_is_ready(config->mfd)) {
LOG_ERR("%s is not ready", config->mfd->name);
return -ENODEV;
}
data->lock = mfd_nct38xx_get_lock_reference(config->mfd);
data->i2c_dev = mfd_nct38xx_get_i2c_dt_spec(config->mfd);
return 0;
}
/* NCT38XX GPIO port driver must be initialized after NCT38XX GPIO driver */
BUILD_ASSERT(CONFIG_GPIO_NCT38XX_PORT_INIT_PRIORITY > CONFIG_GPIO_NCT38XX_INIT_PRIORITY);
#define GPIO_NCT38XX_PORT_DEVICE_INSTANCE(inst) \
static const struct gpio_nct38xx_port_config gpio_nct38xx_port_cfg_##inst = { \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) & \
DT_INST_PROP(inst, pin_mask)}, \
.mfd = DEVICE_DT_GET(DT_INST_GPARENT(inst)), \
.gpio_port = DT_INST_REG_ADDR(inst), \
.pinmux_mask = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, pinmux_mask), \
(DT_INST_PROP(inst, pinmux_mask)), (0)), \
}; \
BUILD_ASSERT( \
!(DT_INST_REG_ADDR(inst) == 0 && !(DT_INST_NODE_HAS_PROP(inst, pinmux_mask))), \
"Port 0 should assign pinmux_mask property."); \
static struct gpio_nct38xx_port_data gpio_nct38xx_port_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, gpio_nct38xx_port_init, NULL, &gpio_nct38xx_port_data_##inst, \
&gpio_nct38xx_port_cfg_##inst, POST_KERNEL, \
CONFIG_GPIO_NCT38XX_PORT_INIT_PRIORITY, &gpio_nct38xx_driver);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NCT38XX_PORT_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_nct38xx_port.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,213 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
/* pico-sdk includes */
#include <hardware/gpio.h>
#include <hardware/regs/intctrl.h>
#include <hardware/structs/iobank0.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define DT_DRV_COMPAT raspberrypi_pico_gpio
#define ALL_EVENTS (GPIO_IRQ_EDGE_FALL | GPIO_IRQ_EDGE_RISE \
| GPIO_IRQ_LEVEL_LOW | GPIO_IRQ_LEVEL_HIGH)
struct gpio_rpi_config {
struct gpio_driver_config common;
void (*bank_config_func)(void);
};
struct gpio_rpi_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
uint32_t int_enabled_mask;
uint32_t single_ended_mask;
uint32_t open_drain_mask;
};
static int gpio_rpi_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
struct gpio_rpi_data *data = dev->data;
gpio_set_pulls(pin,
(flags & GPIO_PULL_UP) != 0U,
(flags & GPIO_PULL_DOWN) != 0U);
/* Avoid gpio_init, since that also clears previously set direction/high/low */
gpio_set_function(pin, GPIO_FUNC_SIO);
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_SINGLE_ENDED) {
data->single_ended_mask |= BIT(pin);
/* Setting the initial state of output data, and output enable.
* The output data will not change from here on, only output
* enable will. If none of the GPIO_OUTPUT_INIT_* flags have
* been set then fall back to the non-agressive input mode.
*/
if (flags & GPIO_LINE_OPEN_DRAIN) {
data->open_drain_mask |= BIT(pin);
gpio_put(pin, 0);
gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_LOW);
} else {
data->open_drain_mask &= ~(BIT(pin));
gpio_put(pin, 1);
gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_HIGH);
}
} else {
data->single_ended_mask &= ~(BIT(pin));
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_put(pin, 1);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_put(pin, 0);
}
gpio_set_dir(pin, GPIO_OUT);
}
} else if (flags & GPIO_INPUT) {
gpio_set_dir(pin, GPIO_IN);
}
return 0;
}
static int gpio_rpi_port_get_raw(const struct device *dev, uint32_t *value)
{
*value = gpio_get_all();
return 0;
}
static int gpio_rpi_port_set_masked_raw(const struct device *port,
uint32_t mask, uint32_t value)
{
struct gpio_rpi_data *data = port->data;
/* First handle push-pull pins: */
gpio_put_masked(mask & ~data->single_ended_mask, value);
/* Then handle open-drain pins: */
gpio_set_dir_masked(mask & data->single_ended_mask & data->open_drain_mask, ~value);
/* Then handle open-source pins: */
gpio_set_dir_masked(mask & data->single_ended_mask & ~data->open_drain_mask, value);
return 0;
}
static int gpio_rpi_port_set_bits_raw(const struct device *port,
uint32_t pins)
{
struct gpio_rpi_data *data = port->data;
/* First handle push-pull pins: */
gpio_set_mask(pins & ~data->single_ended_mask);
/* Then handle open-drain pins: */
gpio_set_dir_in_masked(pins & data->single_ended_mask & data->open_drain_mask);
/* Then handle open-source pins: */
gpio_set_dir_out_masked(pins & data->single_ended_mask & ~data->open_drain_mask);
return 0;
}
static int gpio_rpi_port_clear_bits_raw(const struct device *port,
uint32_t pins)
{
struct gpio_rpi_data *data = port->data;
/* First handle push-pull pins: */
gpio_clr_mask(pins & ~data->single_ended_mask);
/* Then handle open-drain pins: */
gpio_set_dir_out_masked(pins & data->single_ended_mask & data->open_drain_mask);
/* Then handle open-source pins: */
gpio_set_dir_in_masked(pins & data->single_ended_mask & ~data->open_drain_mask);
return 0;
}
static int gpio_rpi_port_toggle_bits(const struct device *port,
uint32_t pins)
{
struct gpio_rpi_data *data = port->data;
/* First handle push-pull pins: */
gpio_xor_mask(pins & ~data->single_ended_mask);
/* Then handle single-ended pins: */
/* (unfortunately there's no pico-sdk api call that can be used for this,
* but it's possible by accessing the registers directly)
*/
sio_hw->gpio_oe_togl = (pins & data->single_ended_mask);
return 0;
}
static int gpio_rpi_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
struct gpio_rpi_data *data = dev->data;
uint32_t events = 0;
gpio_set_irq_enabled(pin, ALL_EVENTS, false);
if (mode != GPIO_INT_DISABLE) {
if (mode & GPIO_INT_EDGE) {
if (trig & GPIO_INT_LOW_0) {
events |= GPIO_IRQ_EDGE_FALL;
}
if (trig & GPIO_INT_HIGH_1) {
events |= GPIO_IRQ_EDGE_RISE;
}
} else {
if (trig & GPIO_INT_LOW_0) {
events |= GPIO_IRQ_LEVEL_LOW;
}
if (trig & GPIO_INT_HIGH_1) {
events |= GPIO_IRQ_LEVEL_HIGH;
}
}
gpio_set_irq_enabled(pin, events, true);
}
WRITE_BIT(data->int_enabled_mask, pin, mode != GPIO_INT_DISABLE);
return 0;
}
static int gpio_rpi_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_rpi_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static const struct gpio_driver_api gpio_rpi_driver_api = {
.pin_configure = gpio_rpi_configure,
.port_get_raw = gpio_rpi_port_get_raw,
.port_set_masked_raw = gpio_rpi_port_set_masked_raw,
.port_set_bits_raw = gpio_rpi_port_set_bits_raw,
.port_clear_bits_raw = gpio_rpi_port_clear_bits_raw,
.port_toggle_bits = gpio_rpi_port_toggle_bits,
.pin_interrupt_configure = gpio_rpi_pin_interrupt_configure,
.manage_callback = gpio_rpi_manage_callback,
};
static void gpio_rpi_isr(const struct device *dev)
{
struct gpio_rpi_data *data = dev->data;
io_irq_ctrl_hw_t *irq_ctrl_base;
const io_rw_32 *status_reg;
uint32_t events;
uint32_t pin;
irq_ctrl_base = &iobank0_hw->proc0_irq_ctrl;
for (pin = 0; pin < NUM_BANK0_GPIOS; pin++) {
status_reg = &irq_ctrl_base->ints[pin / 8];
events = (*status_reg >> 4 * (pin % 8)) & ALL_EVENTS;
if (events) {
gpio_acknowledge_irq(pin, ALL_EVENTS);
gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
}
}
}
static int gpio_rpi_bank_init(const struct device *dev)
{
const struct gpio_rpi_config *config = dev->config;
config->bank_config_func();
return 0;
}
#define GPIO_RPI_INIT(idx) \
static void bank_##idx##_config_func(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), \
gpio_rpi_isr, DEVICE_DT_INST_GET(idx), 0); \
irq_enable(DT_INST_IRQN(idx)); \
} \
static const struct gpio_rpi_config gpio_rpi_##idx##_config = { \
.bank_config_func = bank_##idx##_config_func, \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
} \
}; \
\
static struct gpio_rpi_data gpio_rpi_##idx##_data; \
\
DEVICE_DT_INST_DEFINE(idx, gpio_rpi_bank_init, NULL, \
&gpio_rpi_##idx##_data, \
&gpio_rpi_##idx##_config, \
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_rpi_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_RPI_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,955 |
```objective-c
/*gpio_dw_registers.h - Private gpio's registers header*/
/*
*
*/
#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
#define ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_
/** This definition of GPIO related registers supports four ports: A, B, C, D
* yet only PORTA supports interrupts and debounce.
*/
#define SWPORTA_DR 0x00
#define SWPORTA_DDR 0x04
#define SWPORTA_CTL 0x08
#define SWPORTB_DR 0x0c
#define SWPORTB_DDR 0x10
#define SWPORTB_CTL 0x14
#define SWPORTC_DR 0x18
#define SWPORTC_DDR 0x1c
#define SWPORTC_CTL 0x20
#define SWPORTD_DR 0x24
#define SWPORTD_DDR 0x28
#define SWPORTD_CTL 0x2c
#define INTEN 0x30
#define INTMASK 0x34
#define INTTYPE_LEVEL 0x38
#define INT_POLARITY 0x3c
#define INTSTATUS 0x40
#define RAW_INTSTATUS 0x44
#define PORTA_DEBOUNCE 0x48
#define PORTA_EOI 0x4c
#define EXT_PORTA 0x50
#define EXT_PORTB 0x54
#define EXT_PORTC 0x58
#define EXT_PORTD 0x5c
#define INT_CLOCK_SYNC 0x60 /* alias LS_SYNC */
#define VER_ID_CODE 0x6c
#define CONFIG_REG2 0x70
#define CONFIG_REG1 0x74
#define LS_SYNC_POS (0)
#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_DW_REGISTERS_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_dw_registers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 407 |
```c
/*
*
*/
#define DT_DRV_COMPAT quicklogic_eos_s3_gpio
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <eoss3_hal_gpio.h>
#include <eoss3_hal_pads.h>
#include <eoss3_hal_pad_config.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define MAX_GPIOS 8U
#define GPIOS_MASK (BIT(MAX_GPIOS) - 1)
#define DISABLED_GPIO_IRQ 0xFFU
struct gpio_eos_s3_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* Pin configuration to determine whether use primary
* or secondary pin for a target GPIO. Secondary pin is used
* when the proper bit is set to 1.
*
* bit_index : primary_pin_number / secondary_pin_number
*
* 0 : 6 / 24
* 1 : 9 / 26
* 2 : 11 / 28
* 3 : 14 / 30
* 4 : 18 / 31
* 5 : 21 / 36
* 6 : 22 / 38
* 7 : 23 / 45
*/
uint8_t pin_secondary_config;
};
struct gpio_eos_s3_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
/* array of interrupts mapped to the gpio number */
uint8_t gpio_irqs[MAX_GPIOS];
};
/* Connection table to configure GPIOs with pads */
static const PadConfig pad_configs[] = {
{.ucPin = PAD_6, .ucFunc = PAD6_FUNC_SEL_GPIO_0},
{.ucPin = PAD_9, .ucFunc = PAD9_FUNC_SEL_GPIO_1},
{.ucPin = PAD_11, .ucFunc = PAD11_FUNC_SEL_GPIO_2},
{.ucPin = PAD_14, .ucFunc = PAD14_FUNC_SEL_GPIO_3},
{.ucPin = PAD_18, .ucFunc = PAD18_FUNC_SEL_GPIO_4},
{.ucPin = PAD_21, .ucFunc = PAD21_FUNC_SEL_GPIO_5},
{.ucPin = PAD_22, .ucFunc = PAD22_FUNC_SEL_GPIO_6},
{.ucPin = PAD_23, .ucFunc = PAD23_FUNC_SEL_GPIO_7},
{.ucPin = PAD_24, .ucFunc = PAD24_FUNC_SEL_GPIO_0},
{.ucPin = PAD_26, .ucFunc = PAD26_FUNC_SEL_GPIO_1},
{.ucPin = PAD_28, .ucFunc = PAD28_FUNC_SEL_GPIO_2},
{.ucPin = PAD_30, .ucFunc = PAD30_FUNC_SEL_GPIO_3},
{.ucPin = PAD_31, .ucFunc = PAD31_FUNC_SEL_GPIO_4},
{.ucPin = PAD_36, .ucFunc = PAD36_FUNC_SEL_GPIO_5},
{.ucPin = PAD_38, .ucFunc = PAD38_FUNC_SEL_GPIO_6},
{.ucPin = PAD_45, .ucFunc = PAD45_FUNC_SEL_GPIO_7},
};
static PadConfig gpio_eos_s3_pad_select(const struct device *dev,
uint8_t gpio_num)
{
const struct gpio_eos_s3_config *config = dev->config;
uint8_t is_secondary = (config->pin_secondary_config >> gpio_num) & 1;
return pad_configs[(MAX_GPIOS * is_secondary) + gpio_num];
}
/* This function maps pad number to IRQ number */
static int gpio_eos_s3_get_irq_num(uint8_t pad)
{
int gpio_irq_num;
switch (pad) {
case PAD_6:
gpio_irq_num = 1;
break;
case PAD_9:
gpio_irq_num = 3;
break;
case PAD_11:
gpio_irq_num = 5;
break;
case PAD_14:
gpio_irq_num = 5;
break;
case PAD_18:
gpio_irq_num = 1;
break;
case PAD_21:
gpio_irq_num = 2;
break;
case PAD_22:
gpio_irq_num = 3;
break;
case PAD_23:
gpio_irq_num = 7;
break;
case PAD_24:
gpio_irq_num = 1;
break;
case PAD_26:
gpio_irq_num = 4;
break;
case PAD_28:
gpio_irq_num = 3;
break;
case PAD_30:
gpio_irq_num = 5;
break;
case PAD_31:
gpio_irq_num = 6;
break;
case PAD_36:
gpio_irq_num = 1;
break;
case PAD_38:
gpio_irq_num = 2;
break;
case PAD_45:
gpio_irq_num = 5;
break;
default:
return -EINVAL;
}
return gpio_irq_num;
}
static int gpio_eos_s3_configure(const struct device *dev,
gpio_pin_t gpio_num,
gpio_flags_t flags)
{
uint32_t *io_mux = (uint32_t *)IO_MUX;
GPIOCfgTypeDef gpio_cfg;
PadConfig pad_config = gpio_eos_s3_pad_select(dev, gpio_num);
if (flags & GPIO_SINGLE_ENDED) {
return -ENOTSUP;
}
gpio_cfg.ucGpioNum = gpio_num;
gpio_cfg.xPadConf = &pad_config;
/* Configure PAD */
if (flags & GPIO_PULL_UP) {
gpio_cfg.xPadConf->ucPull = PAD_PULLUP;
} else if (flags & GPIO_PULL_DOWN) {
gpio_cfg.xPadConf->ucPull = PAD_PULLDOWN;
} else {
/* High impedance */
gpio_cfg.xPadConf->ucPull = PAD_NOPULL;
}
if ((flags & GPIO_INPUT) != 0) {
gpio_cfg.xPadConf->ucMode = PAD_MODE_INPUT_EN;
gpio_cfg.xPadConf->ucSmtTrg = PAD_SMT_TRIG_EN;
}
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
MISC_CTRL->IO_OUTPUT |= (BIT(gpio_num) & GPIOS_MASK);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
MISC_CTRL->IO_OUTPUT &= ~(BIT(gpio_num) & GPIOS_MASK);
}
gpio_cfg.xPadConf->ucMode = PAD_MODE_OUTPUT_EN;
}
if (flags == GPIO_DISCONNECTED) {
gpio_cfg.xPadConf->ucMode = PAD_MODE_INPUT_EN;
gpio_cfg.xPadConf->ucSmtTrg = PAD_SMT_TRIG_DIS;
}
/* Initial PAD configuration */
HAL_PAD_Config(gpio_cfg.xPadConf);
/* Override direction setup to support bidirectional config */
if ((flags & GPIO_DIR_MASK) == (GPIO_INPUT | GPIO_OUTPUT)) {
io_mux += gpio_cfg.xPadConf->ucPin;
*io_mux &= ~PAD_OEN_DISABLE;
*io_mux |= PAD_REN_ENABLE;
}
return 0;
}
static int gpio_eos_s3_port_get_raw(const struct device *dev,
uint32_t *value)
{
ARG_UNUSED(dev);
*value = (MISC_CTRL->IO_INPUT & GPIOS_MASK);
return 0;
}
static int gpio_eos_s3_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
ARG_UNUSED(dev);
uint32_t target_value;
uint32_t output_states = MISC_CTRL->IO_OUTPUT;
target_value = ((output_states & ~mask) | (value & mask));
MISC_CTRL->IO_OUTPUT = (target_value & GPIOS_MASK);
return 0;
}
static int gpio_eos_s3_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
ARG_UNUSED(dev);
MISC_CTRL->IO_OUTPUT |= (mask & GPIOS_MASK);
return 0;
}
static int gpio_eos_s3_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
ARG_UNUSED(dev);
MISC_CTRL->IO_OUTPUT &= ~(mask & GPIOS_MASK);
return 0;
}
static int gpio_eos_s3_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
ARG_UNUSED(dev);
uint32_t target_value;
uint32_t output_states = MISC_CTRL->IO_OUTPUT;
target_value = output_states ^ mask;
MISC_CTRL->IO_OUTPUT = (target_value & GPIOS_MASK);
return 0;
}
static int gpio_eos_s3_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_eos_s3_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_eos_s3_pin_interrupt_configure(const struct device *dev,
gpio_pin_t gpio_num,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
struct gpio_eos_s3_data *data = dev->data;
GPIOCfgTypeDef gpio_cfg;
PadConfig pad_config = gpio_eos_s3_pad_select(dev, gpio_num);
gpio_cfg.ucGpioNum = gpio_num;
gpio_cfg.xPadConf = &pad_config;
if (mode == GPIO_INT_MODE_DISABLED) {
/* Get IRQ number which should be disabled */
int irq_num = gpio_eos_s3_get_irq_num(pad_config.ucPin);
if (irq_num < 0) {
return -EINVAL;
}
/* Disable IRQ */
INTR_CTRL->GPIO_INTR_EN_M4 &= ~BIT((uint32_t)irq_num);
/* Mark corresponding IRQ number as disabled */
data->gpio_irqs[irq_num] = DISABLED_GPIO_IRQ;
/* Clear configuration */
INTR_CTRL->GPIO_INTR_TYPE &= ~((uint32_t)(BIT(irq_num)));
INTR_CTRL->GPIO_INTR_POL &= ~((uint32_t)(BIT(irq_num)));
} else {
/* Prepare configuration */
if (mode == GPIO_INT_MODE_LEVEL) {
gpio_cfg.intr_type = LEVEL_TRIGGERED;
if (trig == GPIO_INT_TRIG_LOW) {
gpio_cfg.pol_type = FALL_LOW;
} else {
gpio_cfg.pol_type = RISE_HIGH;
}
} else {
gpio_cfg.intr_type = EDGE_TRIGGERED;
switch (trig) {
case GPIO_INT_TRIG_LOW:
gpio_cfg.pol_type = FALL_LOW;
break;
case GPIO_INT_TRIG_HIGH:
gpio_cfg.pol_type = RISE_HIGH;
break;
case GPIO_INT_TRIG_BOTH:
return -ENOTSUP;
default:
return -EINVAL;
}
}
/* Set IRQ configuration */
int irq_num = HAL_GPIO_IntrCfg(&gpio_cfg);
if (irq_num < 0) {
return -EINVAL;
}
/* Set corresponding IRQ number as enabled */
data->gpio_irqs[irq_num] = gpio_num;
/* Clear pending GPIO interrupts */
INTR_CTRL->GPIO_INTR |= BIT((uint32_t)irq_num);
/* Enable IRQ */
INTR_CTRL->GPIO_INTR_EN_M4 |= BIT((uint32_t)irq_num);
}
return 0;
}
static void gpio_eos_s3_isr(const struct device *dev)
{
struct gpio_eos_s3_data *data = dev->data;
/* Level interrupts can be only checked from read-only GPIO_INTR_RAW,
* we need to add it to the intr_status.
*/
uint32_t intr_status = (INTR_CTRL->GPIO_INTR | INTR_CTRL->GPIO_INTR_RAW);
/* Clear pending GPIO interrupts */
INTR_CTRL->GPIO_INTR |= intr_status;
/* Fire callbacks */
for (int irq_num = 0; irq_num < MAX_GPIOS; irq_num++) {
if (data->gpio_irqs[irq_num] != DISABLED_GPIO_IRQ) {
gpio_fire_callbacks(&data->callbacks,
dev, BIT(data->gpio_irqs[irq_num]));
}
}
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_eos_s3_port_get_direction(const struct device *port, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
uint32_t pin;
PadConfig pad_config;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
const struct gpio_eos_s3_config *config = dev->config;
map &= config->common.port_pin_mask;
if (inputs != NULL) {
for (pin = find_lsb_set(pins) - 1; pins;
pins &= ~BIT(pin), pin = find_lsb_set(pins) - 1) {
pad_config = gpio_eos_s3_pad_select(port, pin);
ip |= (pad_config.ucMode == PAD_MODE_INPUT_EN &&
pad_config.ucSmtTrg == PAD_SMT_TRIG_EN) *
BIT(pin);
}
*inputs = ip;
}
if (outputs != NULL) {
for (pin = find_lsb_set(pins) - 1; pins;
pins &= ~BIT(pin), pin = find_lsb_set(pins) - 1) {
pad_config = gpio_eos_s3_pad_select(port, pin);
op |= (pad_config.ucMode == PAD_MODE_OUTPUT_EN) * BIT(pin);
}
*outputs = op;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_eos_s3_driver_api = {
.pin_configure = gpio_eos_s3_configure,
.port_get_raw = gpio_eos_s3_port_get_raw,
.port_set_masked_raw = gpio_eos_s3_port_set_masked_raw,
.port_set_bits_raw = gpio_eos_s3_port_set_bits_raw,
.port_clear_bits_raw = gpio_eos_s3_port_clear_bits_raw,
.port_toggle_bits = gpio_eos_s3_port_toggle_bits,
.pin_interrupt_configure = gpio_eos_s3_pin_interrupt_configure,
.manage_callback = gpio_eos_s3_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_eos_s3_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
static int gpio_eos_s3_init(const struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
gpio_eos_s3_isr,
DEVICE_DT_INST_GET(0),
0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
const struct gpio_eos_s3_config gpio_eos_s3_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
},
.pin_secondary_config = DT_INST_PROP(0, pin_secondary_config),
};
static struct gpio_eos_s3_data gpio_eos_s3_data = {
.gpio_irqs = {
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ,
DISABLED_GPIO_IRQ
},
};
DEVICE_DT_INST_DEFINE(0,
gpio_eos_s3_init,
NULL,
&gpio_eos_s3_data,
&gpio_eos_s3_config,
PRE_KERNEL_1,
CONFIG_GPIO_INIT_PRIORITY,
&gpio_eos_s3_driver_api);
``` | /content/code_sandbox/drivers/gpio/gpio_eos_s3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,405 |
```c
/*
*/
#define DT_DRV_COMPAT brcm_bcm2711_gpio
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
#define GPIO_REG_GROUP(n, cnt) (n / cnt)
#define GPIO_REG_SHIFT(n, cnt, bits) ((n % cnt) * bits)
#define GPFSEL(base, n) (base + 0x00 + 0x04 * n)
#define GPSET(base, n) (base + 0x1C + 0x04 * n)
#define GPCLR(base, n) (base + 0x28 + 0x04 * n)
#define GPLEV(base, n) (base + 0x34 + 0x04 * n)
#define GPEDS(base, n) (base + 0x40 + 0x04 * n)
#define GPREN(base, n) (base + 0x4C + 0x04 * n)
#define GPFEN(base, n) (base + 0x58 + 0x04 * n)
#define GPHEN(base, n) (base + 0x64 + 0x04 * n)
#define GPLEN(base, n) (base + 0x70 + 0x04 * n)
#define GPAREN(base, n) (base + 0x7C + 0x04 * n)
#define GPAFEN(base, n) (base + 0x88 + 0x04 * n)
#define GPPULL(base, n) (base + 0xE4 + 0x04 * n)
#define FSEL_GROUPS (10)
#define FSEL_BITS (3)
#define FSEL_OUTPUT (0x1)
#define IO_GROUPS (32)
#define IO_BITS (1)
#define PULL_GROUPS (16)
#define PULL_BITS (2)
#define PULL_UP (0x1)
#define PULL_DOWN (0x2)
#define DEV_CFG(dev) ((const struct gpio_bcm2711_config *const)(dev)->config)
#define DEV_DATA(dev) ((struct gpio_bcm2711_data *const)(dev)->data)
#define RPI_PIN_NUM(dev, n) (DEV_CFG(dev)->offset + n)
#define FROM_U64(val, idx) ((uint32_t)((val >> (idx * 32)) & UINT32_MAX))
struct gpio_bcm2711_config {
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(reg_base);
void (*irq_config_func)(void);
uint8_t offset;
uint8_t ngpios;
};
struct gpio_bcm2711_data {
struct gpio_driver_data common;
DEVICE_MMIO_NAMED_RAM(reg_base);
mem_addr_t base;
sys_slist_t cb;
};
static int gpio_bcm2711_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
{
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint32_t group;
uint32_t shift;
uint32_t regval;
if (flags & GPIO_OPEN_DRAIN) {
return -ENOTSUP;
}
/* Set direction */
{
group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), FSEL_GROUPS);
shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), FSEL_GROUPS, FSEL_BITS);
regval = sys_read32(GPFSEL(data->base, group));
regval &= ~(BIT_MASK(FSEL_BITS) << shift);
if (flags & GPIO_OUTPUT) {
regval |= (FSEL_OUTPUT << shift);
}
sys_write32(regval, GPFSEL(data->base, group));
}
/* Set output level */
if (flags & GPIO_OUTPUT) {
group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), IO_GROUPS);
shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), IO_GROUPS, IO_BITS);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
regval = sys_read32(GPSET(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPSET(data->base, group));
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
regval = sys_read32(GPCLR(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPCLR(data->base, group));
}
}
/* Set pull */
{
group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), PULL_GROUPS);
shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), PULL_GROUPS, PULL_BITS);
regval = sys_read32(GPPULL(data->base, group));
regval &= ~(BIT_MASK(PULL_BITS) << shift);
if (flags & GPIO_PULL_UP) {
regval |= (PULL_UP << shift);
} else if (flags & GPIO_PULL_DOWN) {
regval |= (PULL_DOWN << shift);
}
sys_write32(regval, GPPULL(data->base, group));
}
return 0;
}
static int gpio_bcm2711_port_get_raw(const struct device *port, gpio_port_value_t *value)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval;
regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) |
((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32);
*value = (regval >> cfg->offset) & BIT_MASK(cfg->ngpios);
return 0;
}
static int gpio_bcm2711_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval, regmask;
uint64_t set, clr;
value &= BIT_MASK(cfg->ngpios);
mask &= BIT_MASK(cfg->ngpios);
regval = (uint64_t)value << cfg->offset;
regmask = (uint64_t)mask << cfg->offset;
set = regval & regmask;
clr = regval ^ regmask;
sys_write32(FROM_U64(set, 0), GPSET(data->base, 0));
sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0));
sys_write32(FROM_U64(set, 1), GPSET(data->base, 1));
sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1));
return 0;
}
static int gpio_bcm2711_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval;
regval = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
sys_write32(FROM_U64(regval, 0), GPSET(data->base, 0));
sys_write32(FROM_U64(regval, 1), GPSET(data->base, 1));
return 0;
}
static int gpio_bcm2711_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval;
regval = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
sys_write32(FROM_U64(regval, 0), GPCLR(data->base, 0));
sys_write32(FROM_U64(regval, 1), GPCLR(data->base, 1));
return 0;
}
static int gpio_bcm2711_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval, regmask;
uint64_t set, clr;
regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) |
((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32);
regmask = ((uint64_t)pins & BIT_MASK(cfg->ngpios)) << cfg->offset;
set = regval ^ regmask;
clr = regval & regmask;
sys_write32(FROM_U64(set, 0), GPSET(data->base, 0));
sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0));
sys_write32(FROM_U64(set, 1), GPSET(data->base, 1));
sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1));
return 0;
}
static int gpio_bcm2711_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint32_t group;
uint32_t shift;
uint32_t regval;
group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), IO_GROUPS);
shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), IO_GROUPS, IO_BITS);
/* Clear all detections first */
regval = sys_read32(GPREN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPREN(data->base, group));
regval = sys_read32(GPFEN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPFEN(data->base, group));
regval = sys_read32(GPHEN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPHEN(data->base, group));
regval = sys_read32(GPLEN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPLEN(data->base, group));
regval = sys_read32(GPAREN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPAREN(data->base, group));
regval = sys_read32(GPAFEN(data->base, group));
regval &= ~BIT(shift);
sys_write32(regval, GPAFEN(data->base, group));
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig & GPIO_INT_LOW_0) {
regval = sys_read32(GPLEN(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPLEN(data->base, group));
}
if (trig & GPIO_INT_HIGH_1) {
regval = sys_read32(GPHEN(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPHEN(data->base, group));
}
} else if (mode == GPIO_INT_MODE_EDGE) {
if (trig & GPIO_INT_LOW_0) {
regval = sys_read32(GPAFEN(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPAFEN(data->base, group));
}
if (trig & GPIO_INT_HIGH_1) {
regval = sys_read32(GPAREN(data->base, group));
regval |= BIT(shift);
sys_write32(regval, GPAREN(data->base, group));
}
}
return 0;
}
static int gpio_bcm2711_manage_callback(const struct device *port, struct gpio_callback *cb,
bool set)
{
struct gpio_bcm2711_data *data = DEV_DATA(port);
return gpio_manage_callback(&data->cb, cb, set);
}
static void gpio_bcm2711_isr(const struct device *port)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
uint64_t regval;
uint32_t pins;
regval = ((uint64_t)sys_read32(GPEDS(data->base, 0))) |
((uint64_t)sys_read32(GPEDS(data->base, 1)) << 32);
regval &= BIT_MASK(cfg->ngpios) << cfg->offset;
pins = (uint32_t)(regval >> cfg->offset);
gpio_fire_callbacks(&data->cb, port, pins);
/* Write to clear */
sys_write32(FROM_U64(regval, 0), GPEDS(data->base, 0));
sys_write32(FROM_U64(regval, 1), GPEDS(data->base, 1));
}
int gpio_bcm2711_init(const struct device *port)
{
const struct gpio_bcm2711_config *cfg = DEV_CFG(port);
struct gpio_bcm2711_data *data = DEV_DATA(port);
DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE);
data->base = DEVICE_MMIO_NAMED_GET(port, reg_base);
cfg->irq_config_func();
return 0;
}
static const struct gpio_driver_api gpio_bcm2711_api = {
.pin_configure = gpio_bcm2711_pin_configure,
.port_get_raw = gpio_bcm2711_port_get_raw,
.port_set_masked_raw = gpio_bcm2711_port_set_masked_raw,
.port_set_bits_raw = gpio_bcm2711_port_set_bits_raw,
.port_clear_bits_raw = gpio_bcm2711_port_clear_bits_raw,
.port_toggle_bits = gpio_bcm2711_port_toggle_bits,
.pin_interrupt_configure = gpio_bcm2711_pin_interrupt_configure,
.manage_callback = gpio_bcm2711_manage_callback,
};
#define GPIO_BCM2711_INST(n) \
static struct gpio_bcm2711_data gpio_bcm2711_data_##n; \
\
static void gpio_bcm2711_irq_config_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_bcm2711_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
} \
\
static const struct gpio_bcm2711_config gpio_bcm2711_cfg_##n = { \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}, \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
.irq_config_func = gpio_bcm2711_irq_config_func_##n, \
.offset = DT_INST_REG_ADDR(n), \
.ngpios = DT_INST_PROP(n, ngpios), \
}; \
\
DEVICE_DT_INST_DEFINE(n, gpio_bcm2711_init, NULL, &gpio_bcm2711_data_##n, \
&gpio_bcm2711_cfg_##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_bcm2711_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_BCM2711_INST)
``` | /content/code_sandbox/drivers/gpio/gpio_bcm2711.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,329 |
```c
/*
* Organisation (CSIRO) ABN 41 687 119 230.
*
*/
/*
* This is not a real GPIO driver. It is used to instantiate struct
* devices for the "vnd,gpio" devicetree compatible used in test code.
*/
#define DT_DRV_COMPAT vnd_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct vnd_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
};
struct vnd_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
};
static int vnd_gpio_pin_configure(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
return -ENOTSUP;
}
static int vnd_gpio_port_get_raw(const struct device *port,
gpio_port_value_t *value)
{
return -ENOTSUP;
}
static int vnd_gpio_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return -ENOTSUP;
}
static int vnd_gpio_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
return -ENOTSUP;
}
static int vnd_gpio_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
return -ENOTSUP;
}
static int vnd_gpio_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
return -ENOTSUP;
}
static const struct gpio_driver_api vnd_gpio_api = {
.pin_configure = vnd_gpio_pin_configure,
.port_get_raw = vnd_gpio_port_get_raw,
.port_set_masked_raw = vnd_gpio_port_set_masked_raw,
.port_set_bits_raw = vnd_gpio_port_set_bits_raw,
.port_clear_bits_raw = vnd_gpio_port_clear_bits_raw,
.port_toggle_bits = vnd_gpio_port_toggle_bits,
};
#define VND_GPIO_INIT(n) \
static const struct vnd_gpio_config vnd_gpio_config_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
}; \
\
static struct vnd_gpio_data vnd_gpio_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, NULL, NULL, &vnd_gpio_data_##n, \
&vnd_gpio_config_##n, POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&vnd_gpio_api);
DT_INST_FOREACH_STATUS_OKAY(VND_GPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_test.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 560 |
```c
/*
*
*/
#define DT_DRV_COMPAT efinix_sapphire_gpio
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
LOG_MODULE_REGISTER(gpio_efinix_sapphire);
#define SUPPORTED_FLAGS \
(GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \
GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH)
#define GPIO_LOW 0
#define GPIO_HIGH 1
#define BSP_GPIO_INPUT 0x00
#define BSP_GPIO_OUTPUT 0x04
#define BSP_GPIO_OUTPUT_ENABLE 0x08
#define BSP_GPIO_INTERRUPT_RISE_ENABLE 0x20
#define BSP_GPIO_INTERRUPT_FALL_ENABLE 0x24
#define BSP_GPIO_INTERRUPT_HIGH_ENABLE 0x28
#define BSP_GPIO_INTERRUPT_LOW_ENABLE 0x2c
/* efinix sapphire specific gpio config struct */
struct gpio_efinix_sapphire_cfg {
uint32_t base_addr;
int n_gpios;
struct gpio_driver_config common;
};
/* efinix sapphire specific gpio data struct */
struct gpio_efinix_sapphire_data {
struct gpio_driver_data common;
const struct device *dev;
sys_slist_t cb;
};
/* Device access pointer helpers */
#define DEV_GPIO_CFG(dev) ((const struct gpio_efinix_sapphire_cfg *)(dev)->config)
#define GPIO_OUTPUT_ADDR config->base_addr + BSP_GPIO_OUTPUT
static inline void cfg_output_enable_bit(const struct gpio_efinix_sapphire_cfg *config,
gpio_pin_t pin, uint32_t type)
{
#define GPIO_OUTPUT_ENABLE_ADDR config->base_addr + BSP_GPIO_OUTPUT_ENABLE
uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ENABLE_ADDR);
if (type == GPIO_INPUT) {
sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ENABLE_ADDR);
} else if (type == GPIO_OUTPUT) {
sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ENABLE_ADDR);
}
}
static inline void cfg_output_bit(const struct gpio_efinix_sapphire_cfg *config, gpio_pin_t pin,
uint32_t value)
{
uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR);
if (value == GPIO_LOW) {
sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ADDR);
} else if (value == GPIO_HIGH) {
sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ADDR);
}
}
/* To use the controller bare minimum as IO, Peripheral has to configure, */
/* the Output enable register, b0 : Input, b1 : Output */
static int gpio_efinix_sapphire_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
/* Check if the controller supports the requested GPIO configuration. */
if (flags & ~SUPPORTED_FLAGS) {
return -ENOTSUP;
}
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_MASK) {
/* Pin cannot be configured as input and output */
return -ENOTSUP;
} else if ((flags & GPIO_DIR_MASK) == GPIO_DISCONNECTED) {
/* Pin has to be configured as input or output */
return -ENOTSUP;
}
/* Configure the output register based on the direction flag */
if (flags & GPIO_OUTPUT) {
/* Set the pin as output */
cfg_output_enable_bit(config, BIT(pin), GPIO_OUTPUT);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
/* Set the pin to high */
cfg_output_bit(config, BIT(pin), GPIO_HIGH);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
/* Set the pin to low */
cfg_output_bit(config, BIT(pin), GPIO_LOW);
}
} else {
/* Set the pin as input */
cfg_output_enable_bit(config, BIT(pin), GPIO_INPUT);
}
return 0;
}
static inline uint32_t get_port(const struct gpio_efinix_sapphire_cfg *config)
{
uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR);
return (c_reg_val & BIT_MASK(config->n_gpios));
}
static inline void set_port(const struct gpio_efinix_sapphire_cfg *config, uint32_t value)
{
sys_write32(value, GPIO_OUTPUT_ADDR);
}
static int gpio_efinix_sapphire_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
*value = get_port(config);
return 0;
}
static int gpio_efinix_sapphire_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
uint32_t c_reg_val = get_port(config);
/* Sets ports value at one go */
c_reg_val &= ~mask;
c_reg_val |= (value & mask);
set_port(config, c_reg_val);
return 0;
}
static int gpio_efinix_sapphire_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
uint32_t c_reg_val = get_port(config);
/* Sets ports value at one go */
c_reg_val |= pins;
set_port(config, c_reg_val);
return 0;
}
static int gpio_efinix_sapphire_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
uint32_t c_reg_val = get_port(config);
/* Sets ports value at one go */
c_reg_val &= ~pins;
set_port(config, c_reg_val);
return 0;
}
static int gpio_efinix_sapphire_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
uint32_t c_reg_val = get_port(config);
/* Sets ports value at one go */
c_reg_val ^= pins;
set_port(config, c_reg_val);
return 0;
}
static int gpio_efinix_sapphire_init(const struct device *dev)
{
const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev);
if (config->n_gpios > 4) {
return -EINVAL;
}
return 0;
}
/* API map */
static const struct gpio_driver_api gpio_efinix_sapphire_api = {
.pin_configure = gpio_efinix_sapphire_config,
.port_get_raw = gpio_efinix_sapphire_port_get_raw,
.port_set_masked_raw = gpio_efinix_sapphire_port_set_masked_raw,
.port_set_bits_raw = gpio_efinix_sapphire_port_set_bits_raw,
.port_clear_bits_raw = gpio_efinix_sapphire_port_clear_bits_raw,
.port_toggle_bits = gpio_efinix_sapphire_port_toggle_bits,
};
#define GPIO_EFINIX_SAPPHIRE_INIT(n) \
static struct gpio_efinix_sapphire_cfg gpio_efinix_sapphire_cfg_##n = { \
.base_addr = DT_INST_REG_ADDR(n), \
.n_gpios = DT_INST_PROP(n, ngpios), \
}; \
static struct gpio_efinix_sapphire_data gpio_efinix_sapphire_data_##n; \
DEVICE_DT_INST_DEFINE(n, \
gpio_efinix_sapphire_init, \
NULL, \
&gpio_efinix_sapphire_data_##n, \
&gpio_efinix_sapphire_cfg_##n, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_efinix_sapphire_api \
); \
DT_INST_FOREACH_STATUS_OKAY(GPIO_EFINIX_SAPPHIRE_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_efinix_sapphire.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,691 |
```unknown
#
#
#
config GPIO_SEDI
bool "SEDI GPIO driver"
default y
depends on DT_HAS_INTEL_SEDI_GPIO_ENABLED
help
This option enables Intel SEDI GPIO driver.
This driver is simply a shim driver built upon the SEDI
bare metal GPIO driver in hal-intel module.
``` | /content/code_sandbox/drivers/gpio/Kconfig.sedi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc32xx_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
/* Driverlib includes */
#include <inc/hw_types.h>
#include <inc/hw_memmap.h>
#include <inc/hw_ints.h>
#include <inc/hw_gpio.h>
#include <driverlib/rom.h>
#include <driverlib/pin.h>
#undef __GPIO_H__ /* Zephyr and CC32XX SDK gpio.h conflict */
#include <driverlib/gpio.h>
#include <driverlib/rom_map.h>
#include <driverlib/interrupt.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
/* Reserved */
#define PIN_XX 0xFF
static const uint8_t pinTable[] = {
/* 00 01 02 03 04 05 06 07 */
PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62,
/* 08 09 10 11 12 13 14 15 */
PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06,
/* 16 17 18 19 20 21 22 23 */
PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16,
/* 24 25 26 27 28 29 30 31 */
PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45,
/* 32 */
PIN_52
};
struct gpio_cc32xx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* base address of GPIO port */
unsigned long port_base;
/* GPIO port number */
uint8_t port_num;
};
struct gpio_cc32xx_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of registered callbacks */
sys_slist_t callbacks;
};
static int gpio_cc32xx_port_set_bits_raw(const struct device *port,
uint32_t mask);
static int gpio_cc32xx_port_clear_bits_raw(const struct device *port,
uint32_t mask);
static inline int gpio_cc32xx_config(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == 0) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
MAP_PinTypeGPIO(pinTable[gpio_config->port_num * 8 + pin],
PIN_MODE_0, false);
if (flags & GPIO_OUTPUT) {
MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_OUT);
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_cc32xx_port_set_bits_raw(port, BIT(pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_cc32xx_port_clear_bits_raw(port, BIT(pin));
}
} else {
MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_IN);
}
return 0;
}
static int gpio_cc32xx_port_get_raw(const struct device *port,
uint32_t *value)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
unsigned char pin_packed = 0xFF;
*value = MAP_GPIOPinRead(port_base, pin_packed);
return 0;
}
static int gpio_cc32xx_port_set_masked_raw(const struct device *port,
uint32_t mask,
uint32_t value)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)value);
return 0;
}
static int gpio_cc32xx_port_set_bits_raw(const struct device *port,
uint32_t mask)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)mask);
return 0;
}
static int gpio_cc32xx_port_clear_bits_raw(const struct device *port,
uint32_t mask)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)~mask);
return 0;
}
static int gpio_cc32xx_port_toggle_bits(const struct device *port,
uint32_t mask)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
long value;
value = MAP_GPIOPinRead(port_base, mask);
MAP_GPIOPinWrite(port_base, (unsigned char)mask,
(unsigned char)~value);
return 0;
}
static int gpio_cc32xx_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_cc32xx_config *gpio_config = port->config;
unsigned long port_base = gpio_config->port_base;
unsigned long int_type;
__ASSERT(pin < 8, "Invalid pin number - only 8 pins per port");
/*
* disable interrupt prior to changing int type helps
* prevent spurious interrupts observed when switching
* to level-based
*/
MAP_GPIOIntDisable(port_base, (1 << pin));
if (mode != GPIO_INT_MODE_DISABLED) {
if (mode == GPIO_INT_MODE_EDGE) {
if (trig == GPIO_INT_TRIG_BOTH) {
int_type = GPIO_BOTH_EDGES;
} else if (trig == GPIO_INT_TRIG_HIGH) {
int_type = GPIO_RISING_EDGE;
} else {
int_type = GPIO_FALLING_EDGE;
}
} else { /* GPIO_INT_MODE_LEVEL */
if (trig == GPIO_INT_TRIG_HIGH) {
int_type = GPIO_HIGH_LEVEL;
} else {
int_type = GPIO_LOW_LEVEL;
}
}
MAP_GPIOIntTypeSet(port_base, (1 << pin), int_type);
MAP_GPIOIntClear(port_base, (1 << pin));
MAP_GPIOIntEnable(port_base, (1 << pin));
}
return 0;
}
static int gpio_cc32xx_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_cc32xx_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void gpio_cc32xx_port_isr(const struct device *dev)
{
const struct gpio_cc32xx_config *config = dev->config;
struct gpio_cc32xx_data *data = dev->data;
uint32_t int_status;
/* See which interrupts triggered: */
int_status = (uint32_t)MAP_GPIOIntStatus(config->port_base, 1);
/* Clear GPIO Interrupt */
MAP_GPIOIntClear(config->port_base, int_status);
/* Call the registered callbacks */
gpio_fire_callbacks(&data->callbacks, dev, int_status);
}
static const struct gpio_driver_api api_funcs = {
.pin_configure = gpio_cc32xx_config,
.port_get_raw = gpio_cc32xx_port_get_raw,
.port_set_masked_raw = gpio_cc32xx_port_set_masked_raw,
.port_set_bits_raw = gpio_cc32xx_port_set_bits_raw,
.port_clear_bits_raw = gpio_cc32xx_port_clear_bits_raw,
.port_toggle_bits = gpio_cc32xx_port_toggle_bits,
.pin_interrupt_configure = gpio_cc32xx_pin_interrupt_configure,
.manage_callback = gpio_cc32xx_manage_callback,
};
#define GPIO_CC32XX_INIT_FUNC(n) \
static int gpio_cc32xx_a##n##_init(const struct device *dev) \
{ \
ARG_UNUSED(dev); \
\
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
gpio_cc32xx_port_isr, DEVICE_DT_INST_GET(n), \
0); \
\
MAP_IntPendClear(DT_INST_IRQN(n) + 16); \
irq_enable(DT_INST_IRQN(n)); \
\
return 0; \
}
#define GPIO_CC32XX_DEVICE_INIT(n) \
DEVICE_DT_INST_DEFINE(n, gpio_cc32xx_a##n##_init, \
NULL, &gpio_cc32xx_a##n##_data, \
&gpio_cc32xx_a##n##_config, \
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&api_funcs)
#define GPIO_CC32XX_INIT(n) \
static const struct gpio_cc32xx_config gpio_cc32xx_a##n##_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.port_base = DT_INST_REG_ADDR(n), \
.port_num = n \
}; \
\
static struct gpio_cc32xx_data gpio_cc32xx_a##n##_data; \
\
GPIO_CC32XX_INIT_FUNC(n) \
\
GPIO_CC32XX_DEVICE_INIT(n);
DT_INST_FOREACH_STATUS_OKAY(GPIO_CC32XX_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_cc32xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,250 |
```unknown
# Intel SoC GPIO configuration options
config GPIO_INTEL
bool "Intel Soc GPIO"
default y
depends on DT_HAS_INTEL_GPIO_ENABLED
help
Enable driver for Intel SoC GPIO
config GPIO_INTEL_CHECK_PERMS
bool "Check permissions before manipulating GPIO"
default y
depends on GPIO_INTEL
help
This option enables the checks to make sure the GPIO
pin can be manipulated. Only if the pin is owned by
the host software and its functioning as GPIO, then
the driver allows manipulating the pin.
Say y if unsure.
``` | /content/code_sandbox/drivers/gpio/Kconfig.intel | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```unknown
config GPIO_ITE_IT8XXX2
bool "ITE IT8XXX2 GPIO driver"
default y
depends on DT_HAS_ITE_IT8XXX2_GPIO_ENABLED
help
Enable driver for the ite GPIO controller.
config GPIO_ITE_IT8XXX2_V2
bool "ITE IT8XXX2 GPIO driver V2"
default y
depends on DT_HAS_ITE_IT8XXX2_GPIO_V2_ENABLED
help
Enable driver for the ite GPIO V2 controller.
config GPIO_KSCAN_ITE_IT8XXX2
bool "ITE IT8XXX2 GPIO KSCAN driver"
default y
depends on DT_HAS_ITE_IT8XXX2_GPIOKSCAN_ENABLED
help
Enable GPIO KSCAN driver for ITE chip it8xxx2.
IT8XXX2 support 8 KSI pins and 18 KSO pins, all of them can be configured
to GPIO mode.
KSI[7:0] and KSO[15:0] pins are configured to GPIO mode by
this GPIO_KSCAN_ITE_IT8XXX2 driver.
KSO[17:16] corresponds to GPC5 and GPC3 pin, so they can be configured to
gpio mode by original GPIO_ITE_IT8XXX2 driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 272 |
```unknown
# NuMicro GPIO configuration options
config GPIO_NUMICRO
bool "Nuvoton NuMicro GPIO driver"
default y
depends on DT_HAS_NUVOTON_NUMICRO_GPIO_ENABLED
help
Enable the GPIO driver for the NuMicro family of processors.
``` | /content/code_sandbox/drivers/gpio/Kconfig.numicro | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_gpio
/**
* @file
* @brief GPIO driver for NXP LPC11U6X SoCs
*
* This driver allows to configure the GPIOs found on the LPC11U6x MCUs.
*
* @note See the UM10732 LPC11U6x/E6x user manual for register definitions.
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
/* Offset from syscon base address. */
#define LPC11U6X_PINTSEL_REGS 0x178
/* Offsets from GPIO base address. */
#define LPC11U6X_GPIO_REGS 0x2000
#define LPC11U6X_PINT_REGS 0x4000
/**
* @brief Structure mapping the GPIO registers.
*
* @note The byte and word pin registers are not included because they are
* not used by this driver. A 0x2000 offset is applied to skip them.
*/
struct lpc11u6x_gpio_regs {
volatile uint32_t dir[3];
volatile uint32_t _unused1[29];
volatile uint32_t mask[3];
volatile uint32_t _unused2[29];
volatile uint32_t pin[3];
volatile uint32_t _unused3[29];
volatile uint32_t mpin[3];
volatile uint32_t _unused4[29];
volatile uint32_t set[3];
volatile uint32_t _unused5[29];
volatile uint32_t clr[3];
volatile uint32_t _unused6[29];
volatile uint32_t not[3];
};
/**
* @brief Structure mapping the PINT registers.
*/
struct lpc11u6x_pint_regs {
volatile uint32_t isel;
volatile uint32_t ienr;
volatile uint32_t sienr;
volatile uint32_t cienr;
volatile uint32_t ienf;
volatile uint32_t sienf;
volatile uint32_t cienf;
volatile uint32_t rise;
volatile uint32_t fall;
volatile uint32_t ist;
volatile uint32_t pmctrl;
volatile uint32_t pmsrc;
volatile uint32_t pmcfg;
};
/**
* @brief Structure for resources and information shared between GPIO ports.
*
* This structure is included by all the per-port private configuration.
* It gathers all the resources and information shared between all the GPIO
* ports: GPIO and SYSCON registers base addresses, clock name and subsystem.
*/
struct gpio_lpc11u6x_shared {
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
uint32_t gpio_base;
uint32_t syscon_base;
uint8_t nirqs;
};
struct gpio_lpc11u6x_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct gpio_lpc11u6x_shared *shared;
uint8_t port_num;
uint8_t ngpios;
volatile uint32_t *iocon_base;
};
struct gpio_lpc11u6x_data {
/* gpio_driver_data needs to be first. */
struct gpio_driver_data common;
sys_slist_t cb_list;
};
static int gpio_lpc11u6x_pin_configure(const struct device *port,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
uint8_t port_num = config->port_num;
uint32_t offset;
uint32_t func;
if (pin >= config->ngpios) {
return -EINVAL;
}
/*
* PIO0_4 and PIO0_5 are "true" open drain pins muxed with the I2C port
* 0. They still can be configured as GPIOs but only in open drain mode
* and with no pull-down or pull-up resistor enabled.
*/
if (port_num == 0 && (pin == 4 || pin == 5) &&
((flags & GPIO_OPEN_DRAIN) == 0 ||
(flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)))) {
return -EINVAL;
}
/*
* For PIO0_0 and PIO0_[10-15] function 1 enables GPIO mode. For all
* the other pins, function 0 must be selected.
*/
if (port_num == 0 && (pin == 0 || (pin >= 10 && pin <= 15))) {
func = IOCON_FUNC1;
} else {
func = IOCON_FUNC0;
}
if (flags & GPIO_SINGLE_ENDED) {
/* Open source mode is not supported. */
if (flags & GPIO_LINE_OPEN_DRAIN) {
func |= IOCON_PIO_OD(1);
} else {
return -ENOTSUP;
}
}
if (flags & GPIO_PULL_UP) {
func |= IOCON_PIO_MODE(0x2);
} else if (flags & GPIO_PULL_DOWN) {
func |= IOCON_PIO_MODE(0x1);
} else {
func |= IOCON_PIO_MODE(0x0);
}
/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
if (port_num == 2 && pin > 1) {
offset = pin + 1;
} else {
offset = pin;
}
/* iocon base + offset gives configuration register for this pin */
config->iocon_base[offset] = func;
/* Initial output value. */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_regs->set[port_num] |= BIT(pin);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_regs->clr[port_num] |= BIT(pin);
}
/*
* TODO: maybe configure the STARTERP0 register to allow wake-up from
* deep-sleep or power-down modes.
*/
/* Configure GPIO direction. */
WRITE_BIT(gpio_regs->dir[port_num], pin, flags & GPIO_OUTPUT);
return 0;
}
static int gpio_lpc11u6x_port_get_raw(const struct device *port,
gpio_port_value_t *value)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
*value = gpio_regs->pin[config->port_num];
return 0;
}
static int gpio_lpc11u6x_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
uint8_t port_num = config->port_num;
uint32_t orig_mask;
orig_mask = gpio_regs->mask[port_num];
/* Apply inverted mask (bit set to 1 masks the pin). */
gpio_regs->mask[port_num] = ~mask;
compiler_barrier();
/* Update pins values. */
gpio_regs->mpin[port_num] = value;
compiler_barrier();
/* Restore original mask. */
gpio_regs->mask[port_num] = orig_mask;
compiler_barrier();
return 0;
}
static int gpio_lpc11u6x_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
gpio_regs->set[config->port_num] = pins;
return 0;
}
static int gpio_lpc11u6x_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
gpio_regs->clr[config->port_num] = pins;
return 0;
}
static int gpio_lpc11u6x_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
gpio_regs->not[config->port_num] = pins;
return 0;
}
/**
* @brief Attach a free interrupt line to a GPIO.
*
* @param shared Pointer to a structure shared between all the GPIO ports.
* @param intpin GPIO port and pin numbers encoded into a value compatible
* with the INTPIN register (included in the PINTSEL register).
*
* @retval >0 Number of the attached interrupt on success.
* @retval -EBUSY All the interrupt lines are already attached.
*/
static int
pintsel_attach(const struct gpio_lpc11u6x_shared *shared, uint8_t intpin)
{
uint8_t irq;
int ret = -EBUSY;
uint32_t *pintsel_reg =
(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
for (irq = 0; irq < shared->nirqs; irq++) {
/* GPIO already attached. */
if ((pintsel_reg[irq] & BIT_MASK(5)) == intpin) {
return irq;
}
if (ret < 0 && (pintsel_reg[irq] & BIT_MASK(5)) == 0) {
ret = irq;
}
}
/* Attach GPIO to the first free interrupt found if any. */
if (ret >= 0) {
pintsel_reg[ret] = intpin;
}
return ret;
}
/**
* @brief Detach an interrupt line from a GPIO.
*
* @param shared Pointer to a structure shared between all the GPIO ports.
* @param intpin GPIO port and pin numbers encoded into a value compatible
* with the INTPIN register (included in the PINTSEL register).
*
* @retval >0 Number of the detached interrupt on success.
* @retval -EINVAL No attached interrupt found for the requested GPIO.
*/
static int
pintsel_detach(const struct gpio_lpc11u6x_shared *shared, uint8_t intpin)
{
uint8_t irq;
uint32_t *pintsel_reg =
(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
for (irq = 0; irq < shared->nirqs; irq++) {
if ((pintsel_reg[irq] & BIT_MASK(5)) == intpin) {
pintsel_reg[irq] = 0;
return irq;
}
}
return -EINVAL;
}
static int gpio_lpc11u6x_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_lpc11u6x_config *config = port->config;
struct lpc11u6x_pint_regs *pint_regs = (struct lpc11u6x_pint_regs *)
(config->shared->gpio_base + LPC11U6X_PINT_REGS);
uint8_t intpin;
int irq;
if (pin >= config->ngpios) {
return -EINVAL;
}
/*
* Because the PINTSEL register only have 6 bits to encode a pin
* number, then PIO2_8 to PIO2_23 can't be attached to an interrupt
* line.
*/
if (config->port_num == 2 && pin > 7) {
return -ENOTSUP;
}
/*
* Convert the requested GPIO port and pin numbers into a value
* compatible with the INTPIN register (included in the PINTSEL
* register).
*/
intpin = pin;
if (config->port_num == 1) {
intpin += 24;
} else if (config->port_num == 2) {
intpin += 56;
}
if (mode == GPIO_INT_MODE_DISABLED) {
irq = pintsel_detach(config->shared, intpin);
} else {
irq = pintsel_attach(config->shared, intpin);
}
if (irq < 0) {
return irq;
}
switch (mode) {
case GPIO_INT_MODE_DISABLED:
pint_regs->isel &= ~BIT(irq);
pint_regs->cienr |= BIT(irq);
pint_regs->cienf |= BIT(irq);
break;
case GPIO_INT_MODE_EDGE:
/* Select edge interrupt mode. */
pint_regs->isel &= ~BIT(irq);
/* Enable interrupts on falling and/or rising edges. */
if (trig & GPIO_INT_TRIG_LOW) {
pint_regs->sienf |= BIT(irq);
} else {
pint_regs->cienf |= BIT(irq);
}
if (trig & GPIO_INT_TRIG_HIGH) {
pint_regs->sienr |= BIT(irq);
} else {
pint_regs->cienr |= BIT(irq);
}
break;
case GPIO_INT_MODE_LEVEL:
/* Select level interrupt mode. */
pint_regs->isel |= BIT(irq);
/* Set active level. */
if (trig & GPIO_INT_TRIG_LOW) {
pint_regs->cienf |= BIT(irq);
} else {
pint_regs->sienf |= BIT(irq);
}
/* Enable level interrupt. */
pint_regs->sienr |= BIT(irq);
break;
default:
return -ENOTSUP;
}
/* Clear interrupt status. */
pint_regs->ist |= BIT(irq);
return 0;
}
static int gpio_lpc11u6x_manage_callback(const struct device *port,
struct gpio_callback *cb, bool set)
{
struct gpio_lpc11u6x_data *data = port->data;
return gpio_manage_callback(&data->cb_list, cb, set);
}
static uint32_t gpio_lpc11u6x_get_pending_int(const struct device *dev)
{
ARG_UNUSED(dev);
return -ENOTSUP;
}
static void gpio_lpc11u6x_isr(const void *arg)
{
struct gpio_lpc11u6x_shared *shared =
(struct gpio_lpc11u6x_shared *)arg;
struct lpc11u6x_pint_regs *pint_regs = (struct lpc11u6x_pint_regs *)
(shared->gpio_base + LPC11U6X_PINT_REGS);
uint32_t *pintsel_reg =
(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
uint8_t irq;
uint32_t pins[3] = { 0, 0, 0 };
const struct device *port;
struct gpio_lpc11u6x_data *data;
for (irq = 0; irq < shared->nirqs; irq++) {
uint32_t intpin;
if ((pint_regs->ist & BIT(irq)) == 0) {
continue;
}
/* Clear interrupt status. */
pint_regs->ist |= BIT(irq);
/*
* Look in the PINTSEL register to retrieve the "intpin" value
* attached with the requested interrupt. Extract the GPIO
* port and pin numbers from this "intpin" value and store them
* into an "active pins" mask.
*/
intpin = pintsel_reg[irq] & BIT_MASK(5);
if (intpin < 24) {
pins[0] |= BIT(intpin);
} else if (intpin < 56) {
pins[1] |= BIT(intpin - 24);
} else {
pins[2] |= BIT(intpin - 56);
}
}
/* For each port with active pins, fire the GPIO interrupt callbacks. */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
if (pins[0]) {
port = DEVICE_DT_GET(DT_NODELABEL(gpio0));
data = port->data;
gpio_fire_callbacks(&data->cb_list, port, pins[0]);
}
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
if (pins[1]) {
port = DEVICE_DT_GET(DT_NODELABEL(gpio1));
data = port->data;
gpio_fire_callbacks(&data->cb_list, port, pins[1]);
}
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
if (pins[2]) {
port = DEVICE_DT_GET(DT_NODELABEL(gpio2));
data = port->data;
gpio_fire_callbacks(&data->cb_list, port, pins[2]);
}
#endif
}
static const struct gpio_driver_api gpio_lpc11u6x_driver_api = {
.pin_configure = gpio_lpc11u6x_pin_configure,
.port_get_raw = gpio_lpc11u6x_port_get_raw,
.port_set_masked_raw = gpio_lpc11u6x_port_set_masked_raw,
.port_set_bits_raw = gpio_lpc11u6x_port_set_bits_raw,
.port_clear_bits_raw = gpio_lpc11u6x_port_clear_bits_raw,
.port_toggle_bits = gpio_lpc11u6x_port_toggle_bits,
.pin_interrupt_configure = gpio_lpc11u6x_pin_interrupt_configure,
.manage_callback = gpio_lpc11u6x_manage_callback,
.get_pending_int = gpio_lpc11u6x_get_pending_int,
};
/*
* Note that the first DT instance is used to initialize the resources
* shared between all the ports (IRQ lines, clock).
*/
static const struct gpio_lpc11u6x_shared gpio_lpc11u6x_shared = {
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t) DT_INST_PHA(0, clocks, clkid),
.gpio_base = DT_INST_REG_ADDR_BY_IDX(0, 0),
.syscon_base = DT_INST_REG_ADDR_BY_IDX(0, 1),
.nirqs = DT_NUM_IRQS(DT_DRV_INST(0)),
};
#define IRQ_INIT(n) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, n, irq), \
DT_INST_IRQ_BY_IDX(0, n, priority), \
gpio_lpc11u6x_isr, &gpio_lpc11u6x_shared, 0); \
irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
} while (false)
static int gpio_lpc11u6x_init(const struct device *dev)
{
const struct gpio_lpc11u6x_config *config = dev->config;
int ret;
static bool gpio_ready;
/* Initialize shared resources only once. */
if (gpio_ready) {
return 0;
}
if (!device_is_ready(config->shared->clock_dev)) {
return -ENODEV;
}
/* Enable GPIO and PINT clocks. */
ret = clock_control_on(config->shared->clock_dev, config->shared->clock_subsys);
if (ret < 0) {
return ret;
}
#if DT_INST_IRQ_HAS_IDX(0, 0)
IRQ_INIT(0);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 1)
IRQ_INIT(1);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 2)
IRQ_INIT(2);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 3)
IRQ_INIT(3);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 4)
IRQ_INIT(4);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 5)
IRQ_INIT(5);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 6)
IRQ_INIT(6);
#endif
#if DT_INST_IRQ_HAS_IDX(0, 7)
IRQ_INIT(7);
#endif
gpio_ready = true;
return 0;
}
#define GPIO_LPC11U6X_INIT(id) \
static const struct gpio_lpc11u6x_config \
gpio_lpc11u6x_config_##id = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE( \
DT_NODELABEL(gpio##id)), \
}, \
.shared = &gpio_lpc11u6x_shared, \
.port_num = id, \
.ngpios = DT_PROP(DT_NODELABEL(gpio##id), ngpios), \
.iocon_base = (volatile uint32_t *)DT_REG_ADDR( \
DT_INST_PHANDLE(id, iocon)), \
}; \
\
static struct gpio_lpc11u6x_data gpio_lpc11u6x_data_##id; \
\
DEVICE_DT_DEFINE(DT_NODELABEL(gpio##id), \
&gpio_lpc11u6x_init, \
NULL, \
&gpio_lpc11u6x_data_##id, \
&gpio_lpc11u6x_config_##id, \
PRE_KERNEL_2, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_lpc11u6x_driver_api)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
GPIO_LPC11U6X_INIT(0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
GPIO_LPC11U6X_INIT(1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
GPIO_LPC11U6X_INIT(2);
#endif
``` | /content/code_sandbox/drivers/gpio/gpio_lpc11u6x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,899 |
```unknown
# MCUX LPC GPIO configuration options
config GPIO_MCUX_LPC
bool "MCUX LPC GPIO driver"
default y
depends on DT_HAS_NXP_LPC_GPIO_PORT_ENABLED
help
Enable the MCUX LPC pinmux driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.mcux_lpc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```c
/*
*
*/
#define DT_DRV_COMPAT richtek_rt1718s_gpio_port
/**
* @file Driver for RS1718S TCPC chip GPIOs.
*/
#include "gpio_rt1718s.h"
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(gpio_rt1718s_port, CONFIG_GPIO_LOG_LEVEL);
/* Driver config */
struct gpio_rt1718s_port_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* RT1718S chip device */
const struct device *rt1718s_dev;
};
/* Driver data */
struct gpio_rt1718s_port_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* GPIO callback list */
sys_slist_t cb_list_gpio;
/* lock GPIO registers access */
struct k_sem lock;
};
/* GPIO api functions */
static int gpio_rt1718s_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
uint8_t new_reg = 0;
int ret = 0;
/* Don't support simultaneous in/out mode */
if ((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)) {
return -ENOTSUP;
}
/* Don't support "open source" mode */
if ((flags & GPIO_SINGLE_ENDED) && !(flags & GPIO_LINE_OPEN_DRAIN)) {
return -ENOTSUP;
}
/* RT1718S has 3 GPIOs so check range */
if (pin >= RT1718S_GPIO_NUM) {
return -EINVAL;
}
/* Configure pin as input. */
if (flags & GPIO_INPUT) {
/* Do not set RT1718S_REG_GPIO_CTRL_OE bit for input */
/* Set pull-high/low input */
if (flags & GPIO_PULL_UP) {
new_reg |= RT1718S_REG_GPIO_CTRL_PU;
}
if (flags & GPIO_PULL_DOWN) {
new_reg |= RT1718S_REG_GPIO_CTRL_PD;
}
} else if (flags & GPIO_OUTPUT) {
/* Set GPIO as output */
new_reg |= RT1718S_REG_GPIO_CTRL_OE;
/* Set push-pull or open-drain */
if (!(flags & GPIO_SINGLE_ENDED)) {
new_reg |= RT1718S_REG_GPIO_CTRL_OD_N;
}
/* Set init state */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
new_reg |= RT1718S_REG_GPIO_CTRL_O;
}
}
k_sem_take(&data->lock, K_FOREVER);
ret = rt1718s_reg_write_byte(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin), new_reg);
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
uint8_t reg;
int ret;
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_RT_ST8, ®);
*value = reg & (RT1718S_REG_RT_ST8_GPIO1_I | RT1718S_REG_RT_ST8_GPIO2_I |
RT1718S_REG_RT_ST8_GPIO3_I);
return ret;
}
static int gpio_rt1718s_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
uint8_t new_reg, reg;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
for (int pin = 0; pin < RT1718S_GPIO_NUM; pin++) {
if (mask & BIT(pin)) {
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
®);
if (ret < 0) {
break;
}
if (value & BIT(pin)) {
new_reg = reg | RT1718S_REG_GPIO_CTRL_O;
} else {
new_reg = reg & ~RT1718S_REG_GPIO_CTRL_O;
}
ret = rt1718s_reg_update(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
reg, new_reg);
}
}
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
uint8_t new_reg, reg;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
for (int pin = 0; pin < RT1718S_GPIO_NUM; pin++) {
if (mask & BIT(pin)) {
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
®);
if (ret < 0) {
break;
}
new_reg = reg | RT1718S_REG_GPIO_CTRL_O;
ret = rt1718s_reg_update(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
reg, new_reg);
}
}
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
uint8_t new_reg, reg;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
for (int pin = 0; pin < RT1718S_GPIO_NUM; pin++) {
if (mask & BIT(pin)) {
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
®);
if (ret < 0) {
break;
}
new_reg = reg & ~RT1718S_REG_GPIO_CTRL_O;
ret = rt1718s_reg_update(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
reg, new_reg);
}
}
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
uint8_t new_reg, reg;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
for (int pin = 0; pin < RT1718S_GPIO_NUM; pin++) {
if (mask & BIT(pin)) {
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
®);
if (ret < 0) {
break;
}
new_reg = reg ^ RT1718S_REG_GPIO_CTRL_O;
ret = rt1718s_reg_update(config->rt1718s_dev, RT1718S_REG_GPIO_CTRL(pin),
reg, new_reg);
}
}
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
struct rt1718s_data *const data_rt1718s = config->rt1718s_dev->data;
uint8_t reg_int8, reg_mask8, new_reg_mask8 = 0;
uint8_t mask_rise = BIT(pin), mask_fall = BIT(4 + pin);
uint16_t alert_mask;
int ret;
/* Check passed arguments */
if (mode == GPIO_INT_MODE_LEVEL || pin >= RT1718S_GPIO_NUM) {
return -ENOTSUP;
}
k_sem_take(&data->lock, K_FOREVER);
k_sem_take(&data_rt1718s->lock_tcpci, K_FOREVER);
ret = rt1718s_reg_read_byte(config->rt1718s_dev, RT1718S_REG_RT_MASK8, ®_mask8);
if (ret < 0) {
goto done;
}
/* Disable GPIO interrupt */
if (mode == GPIO_INT_MODE_DISABLED) {
new_reg_mask8 = reg_mask8 & ~(mask_rise | mask_fall);
} else if (mode == GPIO_INT_MODE_EDGE) {
switch (trig) {
case GPIO_INT_TRIG_BOTH:
new_reg_mask8 = reg_mask8 | mask_rise | mask_fall;
break;
case GPIO_INT_TRIG_HIGH:
new_reg_mask8 = (reg_mask8 | mask_rise) & ~mask_fall;
break;
case GPIO_INT_TRIG_LOW:
new_reg_mask8 = (reg_mask8 | mask_fall) & ~mask_rise;
break;
default:
ret = -EINVAL;
goto done;
}
ret = rt1718s_reg_burst_read(config->rt1718s_dev, RT1718S_REG_ALERT_MASK,
(uint8_t *)&alert_mask, sizeof(alert_mask));
if (ret) {
goto done;
}
/* Enable Vendor Defined Alert for GPIO interrupts */
if (!(alert_mask & RT1718S_REG_ALERT_MASK_VENDOR_DEFINED_ALERT)) {
alert_mask |= RT1718S_REG_ALERT_MASK_VENDOR_DEFINED_ALERT;
ret = rt1718s_reg_burst_write(config->rt1718s_dev, RT1718S_REG_ALERT_MASK,
(uint8_t *)&alert_mask, sizeof(alert_mask));
if (ret) {
goto done;
}
}
/* Clear pending interrupts, which were trigger before enabling the pin
* interrupt by user.
*/
reg_int8 = mask_rise | mask_fall;
rt1718s_reg_write_byte(config->rt1718s_dev, RT1718S_REG_RT_INT8, reg_int8);
}
/* MASK8 handles 3 GPIOs interrupts, both edges */
ret = rt1718s_reg_update(config->rt1718s_dev, RT1718S_REG_RT_MASK8, reg_mask8,
new_reg_mask8);
done:
k_sem_give(&data_rt1718s->lock_tcpci);
k_sem_give(&data->lock);
return ret;
}
static int gpio_rt1718s_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct gpio_rt1718s_port_data *const data = dev->data;
return gpio_manage_callback(&data->cb_list_gpio, callback, set);
}
void rt1718s_gpio_alert_handler(const struct device *dev)
{
const struct rt1718s_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data_port = config->gpio_port_dev->data;
uint8_t reg_int8, reg_mask8;
k_sem_take(&data_port->lock, K_FOREVER);
/* Get mask and state of GPIO interrupts */
if (rt1718s_reg_read_byte(dev, RT1718S_REG_RT_INT8, ®_int8) ||
rt1718s_reg_read_byte(dev, RT1718S_REG_RT_MASK8, ®_mask8)) {
k_sem_give(&data_port->lock);
LOG_ERR("i2c access failed");
return;
}
reg_int8 &= reg_mask8;
/* Clear the interrupts */
if (reg_int8) {
if (rt1718s_reg_write_byte(dev, RT1718S_REG_RT_INT8, reg_int8)) {
k_sem_give(&data_port->lock);
LOG_ERR("i2c access failed");
return;
}
}
k_sem_give(&data_port->lock);
if (reg_int8 & RT1718S_GPIO_INT_MASK)
/* Call the GPIO callbacks for rising *or* falling edge */
gpio_fire_callbacks(&data_port->cb_list_gpio, config->gpio_port_dev,
(reg_int8 & 0x7) | ((reg_int8 >> 4) & 0x7));
}
static const struct gpio_driver_api gpio_rt1718s_driver = {
.pin_configure = gpio_rt1718s_pin_config,
.port_get_raw = gpio_rt1718s_port_get_raw,
.port_set_masked_raw = gpio_rt1718s_port_set_masked_raw,
.port_set_bits_raw = gpio_rt1718s_port_set_bits_raw,
.port_clear_bits_raw = gpio_rt1718s_port_clear_bits_raw,
.port_toggle_bits = gpio_rt1718s_port_toggle_bits,
.pin_interrupt_configure = gpio_rt1718s_pin_interrupt_configure,
.manage_callback = gpio_rt1718s_manage_callback,
};
static int gpio_rt1718s_port_init(const struct device *dev)
{
const struct gpio_rt1718s_port_config *const config = dev->config;
struct gpio_rt1718s_port_data *const data = dev->data;
if (!device_is_ready(config->rt1718s_dev)) {
LOG_ERR("%s is not ready", config->rt1718s_dev->name);
return -ENODEV;
}
k_sem_init(&data->lock, 1, 1);
return 0;
}
/* RT1718S GPIO port driver must be initialized after RT1718S chip driver */
BUILD_ASSERT(CONFIG_GPIO_RT1718S_PORT_INIT_PRIORITY > CONFIG_RT1718S_INIT_PRIORITY);
#define GPIO_RT1718S_PORT_DEVICE_INSTANCE(inst) \
static const struct gpio_rt1718s_port_config gpio_rt1718s_port_cfg_##inst = { \
.common = {.port_pin_mask = 0x7}, \
.rt1718s_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
static struct gpio_rt1718s_port_data gpio_rt1718s_port_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, gpio_rt1718s_port_init, NULL, &gpio_rt1718s_port_data_##inst, \
&gpio_rt1718s_port_cfg_##inst, POST_KERNEL, \
CONFIG_GPIO_RT1718S_PORT_INIT_PRIORITY, &gpio_rt1718s_driver);
DT_INST_FOREACH_STATUS_OKAY(GPIO_RT1718S_PORT_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_rt1718s_port.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,251 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_hogs, CONFIG_GPIO_LOG_LEVEL);
struct gpio_hog_dt_spec {
gpio_pin_t pin;
gpio_flags_t flags;
};
struct gpio_hogs {
const struct device *port;
const struct gpio_hog_dt_spec *specs;
size_t num_specs;
};
/* Static initializer for a struct gpio_hog_dt_spec */
#define GPIO_HOG_DT_SPEC_GET_BY_IDX(node_id, idx) \
{ \
.pin = DT_GPIO_HOG_PIN_BY_IDX(node_id, idx), \
.flags = DT_GPIO_HOG_FLAGS_BY_IDX(node_id, idx) | \
COND_CODE_1(DT_PROP(node_id, input), (GPIO_INPUT), \
(COND_CODE_1(DT_PROP(node_id, output_low), \
(GPIO_OUTPUT_INACTIVE), \
(COND_CODE_1(DT_PROP(node_id, output_high), \
(GPIO_OUTPUT_ACTIVE), (0)))))), \
}
/* Expands to 1 if node_id is a GPIO controller, 0 otherwise */
#define GPIO_HOGS_NODE_IS_GPIO_CTLR(node_id) \
DT_PROP_OR(node_id, gpio_controller, 0)
/* Expands to 1 if node_id is a GPIO hog, empty otherwise */
#define GPIO_HOGS_NODE_IS_GPIO_HOG(node_id) \
IF_ENABLED(DT_PROP_OR(node_id, gpio_hog, 0), 1)
/* Expands to 1 if GPIO controller node_id has GPIO hog children, 0 otherwise */
#define GPIO_HOGS_GPIO_CTLR_HAS_HOGS(node_id) \
COND_CODE_0( \
IS_EMPTY(DT_FOREACH_CHILD_STATUS_OKAY(node_id, \
GPIO_HOGS_NODE_IS_GPIO_HOG)), \
(1), (0))
/* Called for GPIO hog indexes */
#define GPIO_HOGS_INIT_GPIO_HOG_BY_IDX(idx, node_id) \
GPIO_HOG_DT_SPEC_GET_BY_IDX(node_id, idx)
/* Called for GPIO hog dts nodes */
#define GPIO_HOGS_INIT_GPIO_HOGS(node_id) \
LISTIFY(DT_NUM_GPIO_HOGS(node_id), \
GPIO_HOGS_INIT_GPIO_HOG_BY_IDX, (,), node_id),
/* Called for GPIO controller dts node children */
#define GPIO_HOGS_COND_INIT_GPIO_HOGS(node_id) \
COND_CODE_0(IS_EMPTY(GPIO_HOGS_NODE_IS_GPIO_HOG(node_id)), \
(GPIO_HOGS_INIT_GPIO_HOGS(node_id)), ())
/* Called for each GPIO controller dts node which has GPIO hog children */
#define GPIO_HOGS_INIT_GPIO_CTLR(node_id) \
{ \
.port = DEVICE_DT_GET(node_id), \
.specs = (const struct gpio_hog_dt_spec []) { \
DT_FOREACH_CHILD_STATUS_OKAY(node_id, \
GPIO_HOGS_COND_INIT_GPIO_HOGS) \
}, \
.num_specs = \
DT_FOREACH_CHILD_STATUS_OKAY_SEP(node_id, \
DT_NUM_GPIO_HOGS, (+)), \
},
/* Called for each GPIO controller dts node */
#define GPIO_HOGS_COND_INIT_GPIO_CTLR(node_id) \
IF_ENABLED(GPIO_HOGS_GPIO_CTLR_HAS_HOGS(node_id), \
(GPIO_HOGS_INIT_GPIO_CTLR(node_id)))
/* Called for each dts node */
#define GPIO_HOGS_COND_INIT(node_id) \
IF_ENABLED(GPIO_HOGS_NODE_IS_GPIO_CTLR(node_id), \
(GPIO_HOGS_COND_INIT_GPIO_CTLR(node_id)))
static const struct gpio_hogs gpio_hogs[] = {
DT_FOREACH_STATUS_OKAY_NODE(GPIO_HOGS_COND_INIT)
};
static int gpio_hogs_init(void)
{
const struct gpio_hogs *hogs;
const struct gpio_hog_dt_spec *spec;
int err;
int i;
int j;
for (i = 0; i < ARRAY_SIZE(gpio_hogs); i++) {
hogs = &gpio_hogs[i];
if (!device_is_ready(hogs->port)) {
LOG_ERR("GPIO port %s not ready", hogs->port->name);
return -ENODEV;
}
for (j = 0; j < hogs->num_specs; j++) {
spec = &hogs->specs[j];
err = gpio_pin_configure(hogs->port, spec->pin, spec->flags);
if (err < 0) {
LOG_ERR("failed to configure GPIO hog for port %s pin %u (err %d)",
hogs->port->name, spec->pin, err);
return err;
}
}
}
return 0;
}
SYS_INIT(gpio_hogs_init, POST_KERNEL, CONFIG_GPIO_HOGS_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/gpio/gpio_hogs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,108 |
```unknown
# SX1509B GPIO configuration options
menuconfig GPIO_SX1509B
bool "SX1509B I2C GPIO chip"
default y
depends on DT_HAS_SEMTECH_SX1509B_ENABLED
select I2C
help
Enable driver for SX1509B I2C GPIO chip.
if GPIO_SX1509B
config GPIO_SX1509B_INIT_PRIORITY
int "Init priority"
default 70
help
Device driver initialization priority.
config GPIO_SX1509B_INTERRUPT
bool "Interrupt enable"
help
Enable support for interrupts on GPIO pins.
config GPIO_SX1509B_DEBOUNCE_TIME
int "Debounce time interval"
range 0 7
default 0
help
Debounce time interval when debounce enabled.
A value V produces a multiplier of 0.5 ms * 2^V, which is
then scaled by 2 MHz / fOSC. See the datasheet for details.
endif # GPIO_SX1509B
``` | /content/code_sandbox/drivers/gpio/Kconfig.sx1509b | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 222 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/shell/shell.h>
#include <stdio.h>
#define ARGV_DEV 1
#define ARGV_PIN 2
#define ARGV_CONF 3
#define ARGV_VALUE 3
#define ARGV_VENDOR_SPECIFIC 4
#define NGPIOS_UNKNOWN -1
#define PIN_NOT_FOUND UINT8_MAX
/* Pin syntax maximum length */
#define PIN_SYNTAX_MAX 32
#define PIN_NUM_MAX 4
struct gpio_ctrl {
const struct device *dev;
int8_t ngpios;
gpio_port_pins_t reserved_mask;
const char **line_names;
uint8_t line_names_len;
const union shell_cmd_entry *subcmd;
};
struct sh_gpio {
const struct device *dev;
gpio_pin_t pin;
};
/*
* Find idx-th pin reference from the set of non reserved
* pin numbers and provided line names.
*/
static void port_pin_get(gpio_port_pins_t reserved_mask, const char **line_names,
uint8_t line_names_len, size_t idx, struct shell_static_entry *entry)
{
static char pin_syntax[PIN_SYNTAX_MAX];
static char pin_num[PIN_NUM_MAX];
const char *name;
gpio_pin_t pin;
bool reserved;
entry->handler = NULL;
/* Find allowed numeric pin reference */
for (pin = 0; pin < GPIO_MAX_PINS_PER_PORT; pin++) {
reserved = ((BIT64(pin) & reserved_mask) != 0);
if (!reserved) {
if (idx == 0) {
break;
}
idx--;
}
}
if (pin < GPIO_MAX_PINS_PER_PORT) {
sprintf(pin_num, "%u", pin);
if ((pin < line_names_len) && (strlen(line_names[pin]) > 0)) {
/* pin can be specified by line name */
name = line_names[pin];
for (int i = 0; i < (sizeof(pin_syntax) - 1); i++) {
/*
* For line-name tab completion to work replace any
* space characters with '_'.
*/
pin_syntax[i] = (name[i] != ' ') ? name[i] : '_';
if (name[i] == '\0') {
break;
}
}
pin_syntax[sizeof(pin_syntax) - 1] = '\0';
entry->syntax = pin_syntax;
entry->help = pin_num;
} else {
/* fallback to pin specified by pin number */
entry->syntax = pin_num;
entry->help = NULL;
}
} else {
/* No more pins */
entry->syntax = NULL;
entry->help = NULL;
}
}
#define GPIO_DT_RESERVED_RANGES_NGPIOS_SHELL(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, ngpios), \
(GPIO_DT_RESERVED_RANGES_NGPIOS(node_id, DT_PROP(node_id, ngpios))), \
(GPIO_MAX_PINS_PER_PORT))
#define GPIO_CTRL_PIN_GET_FN(node_id) \
static const char *node_id##line_names[] = DT_PROP_OR(node_id, gpio_line_names, {NULL}); \
\
static void node_id##cmd_gpio_pin_get(size_t idx, struct shell_static_entry *entry); \
\
SHELL_DYNAMIC_CMD_CREATE(node_id##sub_gpio_pin, node_id##cmd_gpio_pin_get); \
\
static void node_id##cmd_gpio_pin_get(size_t idx, struct shell_static_entry *entry) \
{ \
gpio_port_pins_t reserved_mask = GPIO_DT_RESERVED_RANGES_NGPIOS_SHELL(node_id); \
uint8_t line_names_len = DT_PROP_LEN_OR(node_id, gpio_line_names, 0); \
\
port_pin_get(reserved_mask, node_id##line_names, line_names_len, idx, entry); \
entry->subcmd = NULL; \
}
#define IS_GPIO_CTRL_PIN_GET(node_id) \
COND_CODE_1(DT_PROP(node_id, gpio_controller), (GPIO_CTRL_PIN_GET_FN(node_id)), ())
DT_FOREACH_STATUS_OKAY_NODE(IS_GPIO_CTRL_PIN_GET)
#define GPIO_CTRL_LIST_ENTRY(node_id) \
{ \
.dev = DEVICE_DT_GET(node_id), \
.ngpios = DT_PROP_OR(node_id, ngpios, NGPIOS_UNKNOWN), \
.reserved_mask = GPIO_DT_RESERVED_RANGES_NGPIOS_SHELL(node_id), \
.line_names = node_id##line_names, \
.line_names_len = DT_PROP_LEN_OR(node_id, gpio_line_names, 0), \
.subcmd = &node_id##sub_gpio_pin, \
},
#define IS_GPIO_CTRL_LIST(node_id) \
COND_CODE_1(DT_PROP(node_id, gpio_controller), (GPIO_CTRL_LIST_ENTRY(node_id)), ())
static const struct gpio_ctrl gpio_list[] = {DT_FOREACH_STATUS_OKAY_NODE(IS_GPIO_CTRL_LIST)};
static const struct gpio_ctrl *get_gpio_ctrl_helper(const struct device *dev)
{
size_t i;
if (dev == NULL) {
return NULL;
}
for (i = 0; i < ARRAY_SIZE(gpio_list); i++) {
if (gpio_list[i].dev == dev) {
return &gpio_list[i];
}
}
return NULL;
}
/* Look up a device by some human-readable string identifier. We
* always search among device names. If the feature is available, we
* search by node label as well.
*/
static const struct gpio_ctrl *get_gpio_ctrl(char *id)
{
const struct gpio_ctrl *ctrl;
ctrl = get_gpio_ctrl_helper(device_get_binding(id));
if (ctrl != NULL) {
return ctrl;
}
#ifdef CONFIG_DEVICE_DT_METADATA
ctrl = get_gpio_ctrl_helper(device_get_by_dt_nodelabel(id));
if (ctrl != NULL) {
return ctrl;
}
#endif /* CONFIG_DEVICE_DT_METADATA */
return NULL;
}
int line_cmp(const char *input, const char *line_name)
{
int i = 0;
while (true) {
if ((input[i] == '_') && (line_name[i] == ' ')) {
/* Allow input underscore to match line_name space */
} else if (input[i] != line_name[i]) {
return (input[i] > line_name[i]) ? 1 : -1;
} else if (line_name[i] == '\0') {
return 0;
}
i++;
}
}
static int get_gpio_pin(const struct shell *sh, const struct gpio_ctrl *ctrl, char *line_name)
{
gpio_pin_t pin = PIN_NOT_FOUND;
gpio_pin_t i;
int result;
for (i = 0; i < ctrl->ngpios; i++) {
result = line_cmp(line_name, ctrl->line_names[i]);
if (result == 0) {
if ((BIT64(i) & ctrl->reserved_mask) != 0) {
shell_error(sh, "Reserved pin");
return -EACCES;
} else if (pin == PIN_NOT_FOUND) {
pin = i;
} else {
shell_error(sh, "Line name ambiguous");
return -EFAULT;
}
}
}
if (pin == PIN_NOT_FOUND) {
shell_error(sh, "Line name not found: '%s'", line_name);
return -ENOENT;
}
return pin;
}
static int get_sh_gpio(const struct shell *sh, char **argv, struct sh_gpio *gpio)
{
const struct gpio_ctrl *ctrl;
int ret = 0;
int pin;
ctrl = get_gpio_ctrl(argv[ARGV_DEV]);
if (ctrl == NULL) {
shell_error(sh, "unknown gpio controller: %s", argv[ARGV_DEV]);
return -EINVAL;
}
gpio->dev = ctrl->dev;
pin = shell_strtoul(argv[ARGV_PIN], 0, &ret);
if (ret != 0) {
pin = get_gpio_pin(sh, ctrl, argv[ARGV_PIN]);
if (pin < 0) {
return pin;
}
} else if ((BIT64(pin) & ctrl->reserved_mask) != 0) {
shell_error(sh, "Reserved pin");
return -EACCES;
}
gpio->pin = pin;
return 0;
}
static int cmd_gpio_conf(const struct shell *sh, size_t argc, char **argv, void *data)
{
gpio_flags_t flags = 0;
gpio_flags_t vendor_specific;
struct sh_gpio gpio;
int ret = 0;
ret = get_sh_gpio(sh, argv, &gpio);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
for (int i = 0; i < strlen(argv[ARGV_CONF]); i++) {
switch (argv[ARGV_CONF][i]) {
case 'i':
flags |= GPIO_INPUT;
break;
case 'o':
flags |= GPIO_OUTPUT;
break;
case 'u':
flags |= GPIO_PULL_UP;
break;
case 'd':
flags |= GPIO_PULL_DOWN;
break;
case 'h':
flags |= GPIO_ACTIVE_HIGH;
break;
case 'l':
flags |= GPIO_ACTIVE_LOW;
break;
case '0':
flags |= GPIO_OUTPUT_INIT_LOGICAL | GPIO_OUTPUT_INIT_LOW;
break;
case '1':
flags |= GPIO_OUTPUT_INIT_LOGICAL | GPIO_OUTPUT_INIT_HIGH;
break;
default:
shell_error(sh, "Unknown: '%c'", argv[ARGV_CONF][i]);
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
}
if (((flags & GPIO_INPUT) != 0) == ((flags & GPIO_OUTPUT) != 0)) {
shell_error(sh, "must be either input or output");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
if (((flags & GPIO_PULL_UP) != 0) && ((flags & GPIO_PULL_DOWN) != 0)) {
shell_error(sh, "cannot be pull up and pull down");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
if (((flags & GPIO_ACTIVE_LOW) != 0) && ((flags & GPIO_ACTIVE_HIGH) != 0)) {
shell_error(sh, "cannot be active low and active high");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
if ((flags & GPIO_OUTPUT) != 0) {
/* Default to active high if not specified */
if ((flags & (GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH)) == 0) {
flags |= GPIO_ACTIVE_HIGH;
}
/* Default to initialisation to logic 0 if not specified */
if ((flags & GPIO_OUTPUT_INIT_LOGICAL) == 0) {
flags |= GPIO_OUTPUT_INIT_LOGICAL | GPIO_OUTPUT_INIT_LOW;
}
}
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT_INIT_LOGICAL) != 0)) {
shell_error(sh, "an input cannot be initialised to a logic level");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
if (((flags & GPIO_OUTPUT_INIT_LOW) != 0) && ((flags & GPIO_OUTPUT_INIT_HIGH) != 0)) {
shell_error(sh, "cannot initialise to logic 0 and logic 1");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
if (argc == 5) {
vendor_specific = shell_strtoul(argv[ARGV_VENDOR_SPECIFIC], 0, &ret);
if ((ret == 0) && ((vendor_specific & ~(0xFF00U)) == 0)) {
flags |= vendor_specific;
} else {
/*
* See include/zephyr/dt-bindings/gpio/ for the
* available flags for your vendor.
*/
shell_error(sh, "vendor specific flags must be within "
"the mask 0xFF00");
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
}
ret = gpio_pin_configure(gpio.dev, gpio.pin, flags);
if (ret != 0) {
shell_error(sh, "error: %d", ret);
return ret;
}
return 0;
}
static int cmd_gpio_get(const struct shell *sh, size_t argc, char **argv)
{
struct sh_gpio gpio;
int value;
int ret;
ret = get_sh_gpio(sh, argv, &gpio);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
value = gpio_pin_get(gpio.dev, gpio.pin);
if (value >= 0) {
shell_print(sh, "%u", value);
} else {
shell_error(sh, "error: %d", value);
return value;
}
return 0;
}
static int cmd_gpio_set(const struct shell *sh, size_t argc, char **argv)
{
struct sh_gpio gpio;
unsigned long value;
int ret = 0;
ret = get_sh_gpio(sh, argv, &gpio);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
value = shell_strtoul(argv[ARGV_VALUE], 0, &ret);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
ret = gpio_pin_set(gpio.dev, gpio.pin, value != 0);
if (ret != 0) {
shell_error(sh, "error: %d", ret);
return ret;
}
return 0;
}
static int cmd_gpio_toggle(const struct shell *sh, size_t argc, char **argv)
{
struct sh_gpio gpio;
int ret = 0;
ret = get_sh_gpio(sh, argv, &gpio);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
ret = gpio_pin_toggle(gpio.dev, gpio.pin);
if (ret != 0) {
shell_error(sh, "error: %d", ret);
return ret;
}
return 0;
}
static int cmd_gpio_devices(const struct shell *sh, size_t argc, char **argv)
{
size_t i;
shell_fprintf(sh, SHELL_NORMAL, "%-16s Other names\n", "Device");
for (i = 0; i < ARRAY_SIZE(gpio_list); i++) {
const struct device *dev = gpio_list[i].dev;
shell_fprintf(sh, SHELL_NORMAL, "%-16s", dev->name);
#ifdef CONFIG_DEVICE_DT_METADATA
const struct device_dt_nodelabels *nl = device_get_dt_nodelabels(dev);
if (nl != NULL && nl->num_nodelabels > 0) {
for (size_t j = 0; j < nl->num_nodelabels; j++) {
const char *nodelabel = nl->nodelabels[j];
shell_fprintf(sh, SHELL_NORMAL, " %s", nodelabel);
}
}
#endif
shell_fprintf(sh, SHELL_NORMAL, "\n");
}
return 0;
}
/* 500 msec = 1/2 sec */
#define SLEEP_TIME_MS 500
static int cmd_gpio_blink(const struct shell *sh, size_t argc, char **argv)
{
bool msg_one_shot = true;
struct sh_gpio gpio;
size_t count;
char data;
int ret;
ret = get_sh_gpio(sh, argv, &gpio);
if (ret != 0) {
shell_help(sh);
return SHELL_CMD_HELP_PRINTED;
}
/* dummy read to clear any pending input */
(void)sh->iface->api->read(sh->iface, &data, sizeof(data), &count);
while (true) {
(void)sh->iface->api->read(sh->iface, &data, sizeof(data), &count);
if (count != 0) {
break;
}
ret = gpio_pin_toggle(gpio.dev, gpio.pin);
if (ret != 0) {
shell_error(sh, "%d", ret);
break;
} else if (msg_one_shot) {
msg_one_shot = false;
shell_print(sh, "Hit any key to exit");
}
k_msleep(SLEEP_TIME_MS);
}
return 0;
}
static void device_name_get(size_t idx, struct shell_static_entry *entry)
{
if (idx >= ARRAY_SIZE(gpio_list)) {
entry->syntax = NULL;
return;
}
entry->syntax = gpio_list[idx].dev->name;
entry->handler = NULL;
entry->help = "Device";
entry->subcmd = gpio_list[idx].subcmd;
}
SHELL_DYNAMIC_CMD_CREATE(sub_gpio_dev, device_name_get);
struct pin_info {
const struct device *dev;
bool reserved;
gpio_pin_t pin;
const char *line_name;
};
struct pin_order_user_data {
const struct shell *sh;
struct pin_info prev;
struct pin_info next;
};
typedef void (*pin_foreach_func_t)(const struct pin_info *info, void *user_data);
static void print_gpio_ctrl_info(const struct shell *sh, const struct gpio_ctrl *ctrl)
{
gpio_pin_t pin;
bool reserved;
const char *line_name;
shell_print(sh, " ngpios: %u", ctrl->ngpios);
shell_print(sh, " Reserved pin mask: 0x%08X", ctrl->reserved_mask);
shell_print(sh, "");
shell_print(sh, " Reserved Pin Line Name");
for (pin = 0; pin < ctrl->ngpios; pin++) {
reserved = (BIT64(pin) & ctrl->reserved_mask) != 0;
if (pin < ctrl->line_names_len) {
line_name = ctrl->line_names[pin];
} else {
line_name = "";
}
shell_print(sh, " %c %2u %s", reserved ? '*' : ' ', pin, line_name);
}
}
static void foreach_pin(pin_foreach_func_t func, void *user_data)
{
gpio_port_pins_t reserved_mask;
struct pin_info info;
gpio_pin_t pin;
size_t i;
for (i = 0; i < ARRAY_SIZE(gpio_list); i++) {
for (pin = 0; pin < gpio_list[i].ngpios; pin++) {
info.dev = gpio_list[i].dev;
reserved_mask = gpio_list[i].reserved_mask;
info.reserved = (BIT64(pin) & reserved_mask) != 0;
info.pin = pin;
if (pin < gpio_list[i].line_names_len) {
info.line_name = gpio_list[i].line_names[pin];
} else {
info.line_name = "";
}
func(&info, user_data);
}
}
}
static int pin_cmp(const struct pin_info *a, const struct pin_info *b)
{
int result = strcmp(a->line_name, b->line_name);
if (result != 0) {
return result;
}
result = strcmp(a->dev->name, b->dev->name);
if (result != 0) {
return result;
}
result = (int)a->pin - (int)b->pin;
return result;
}
static void pin_get_next(const struct pin_info *info, void *user_data)
{
struct pin_order_user_data *data = user_data;
int result;
if (data->prev.line_name != NULL) {
result = pin_cmp(info, &data->prev);
} else {
result = 1;
}
if (result > 0) {
if (data->next.line_name == NULL) {
data->next = *info;
return;
}
result = pin_cmp(info, &data->next);
if (result < 0) {
data->next = *info;
}
}
}
static void pin_ordered(const struct pin_info *info, void *user_data)
{
struct pin_order_user_data *data = user_data;
ARG_UNUSED(info);
foreach_pin(pin_get_next, data);
shell_print(data->sh, " %-12s %-8c %-16s %2u",
data->next.line_name,
data->next.reserved ? '*' : ' ',
data->next.dev->name,
data->next.pin);
data->prev = data->next;
data->next.line_name = NULL;
}
static void print_ordered_info(const struct shell *sh)
{
struct pin_order_user_data data = {0};
data.sh = sh;
shell_print(sh, " %-12s %-8s %-16s %-3s",
"Line", "Reserved", "Device", "Pin");
foreach_pin(pin_ordered, &data);
}
static int cmd_gpio_info(const struct shell *sh, size_t argc, char **argv)
{
const struct gpio_ctrl *ctrl = get_gpio_ctrl(argv[ARGV_DEV]);
if (ctrl == NULL) {
/* No device specified */
print_ordered_info(sh);
return 0;
}
print_gpio_ctrl_info(sh, ctrl);
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(sub_gpio,
SHELL_CMD_ARG(conf, &sub_gpio_dev,
"Configure GPIO pin\n"
"Usage: gpio conf <device> <pin> <configuration <i|o>[u|d][h|l][0|1]> [vendor specific]\n"
"<i|o> - input|output\n"
"[u|d] - pull up|pull down, otherwise open\n"
"[h|l] - active high|active low, otherwise defaults to active high\n"
"[0|1] - initialise to logic 0|logic 1, otherwise defaults to logic 0\n"
"[vendor specific] - configuration flags within the mask 0xFF00\n"
" see include/zephyr/dt-bindings/gpio/",
cmd_gpio_conf, 4, 1),
SHELL_CMD_ARG(get, &sub_gpio_dev,
"Get GPIO pin value\n"
"Usage: gpio get <device> <pin>", cmd_gpio_get, 3, 0),
SHELL_CMD_ARG(set, &sub_gpio_dev,
"Set GPIO pin value\n"
"Usage: gpio set <device> <pin> <level 0|1>", cmd_gpio_set, 4, 0),
SHELL_COND_CMD_ARG(CONFIG_GPIO_SHELL_TOGGLE_CMD, toggle, &sub_gpio_dev,
"Toggle GPIO pin\n"
"Usage: gpio toggle <device> <pin>", cmd_gpio_toggle, 3, 0),
SHELL_CMD(devices, NULL,
"List all GPIO devices\n"
"Usage: gpio devices", cmd_gpio_devices),
SHELL_COND_CMD_ARG(CONFIG_GPIO_SHELL_BLINK_CMD, blink, &sub_gpio_dev,
"Blink GPIO pin\n"
"Usage: gpio blink <device> <pin>", cmd_gpio_blink, 3, 0),
SHELL_COND_CMD_ARG(CONFIG_GPIO_SHELL_INFO_CMD, info, &sub_gpio_dev,
"GPIO Information\n"
"Usage: gpio info [device]", cmd_gpio_info, 1, 1),
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_CMD_REGISTER(gpio, &sub_gpio, "GPIO commands", NULL);
``` | /content/code_sandbox/drivers/gpio/gpio_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,081 |
```c
/*
*
*/
#define DT_DRV_COMPAT cypress_psoc6_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "cy_gpio.h"
#include "cy_sysint.h"
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_psoc6);
typedef void (*config_func_t)(const struct device *dev);
struct gpio_psoc6_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_PRT_Type *regs;
config_func_t config_func;
};
struct gpio_psoc6_runtime {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
static int gpio_psoc6_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
uint32_t drv_mode;
uint32_t pin_val;
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_SINGLE_ENDED) {
drv_mode = (flags & GPIO_LINE_OPEN_DRAIN) ?
CY_GPIO_DM_OD_DRIVESLOW_IN_OFF :
CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
pin_val = (flags & GPIO_LINE_OPEN_DRAIN) ? 1 : 0;
} else {
drv_mode = CY_GPIO_DM_STRONG_IN_OFF;
pin_val = (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0;
}
} else {
if ((flags & GPIO_PULL_UP) && (flags & GPIO_PULL_DOWN)) {
drv_mode = CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
} else if (flags & GPIO_PULL_UP) {
drv_mode = CY_GPIO_DM_PULLUP_IN_OFF;
} else if (flags & GPIO_PULL_DOWN) {
drv_mode = CY_GPIO_DM_PULLDOWN_IN_OFF;
} else {
drv_mode = CY_GPIO_DM_ANALOG;
}
pin_val = (flags & GPIO_PULL_UP) ? 1 : 0;
}
if (flags & GPIO_INPUT) {
/* enable input buffer */
drv_mode |= CY_GPIO_DM_HIGHZ;
}
Cy_GPIO_Pin_FastInit(port, pin, drv_mode, pin_val, HSIOM_SEL_GPIO);
Cy_GPIO_SetVtrip(port, pin, CY_GPIO_VTRIP_CMOS);
Cy_GPIO_SetSlewRate(port, pin, CY_GPIO_SLEW_FAST);
Cy_GPIO_SetDriveSel(port, pin, CY_GPIO_DRIVE_FULL);
LOG_DBG("P: 0x%08x, Pin: %d, Mode: 0x%08x, Val: 0x%02x",
(unsigned int) port, pin, drv_mode, pin_val);
return 0;
}
static int gpio_psoc6_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
*value = GPIO_PRT_IN(port);
LOG_DBG("P: 0x%08x, V: 0x%08x", (unsigned int) port, *value);
return 0;
}
static int gpio_psoc6_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
GPIO_PRT_OUT(port) = (GPIO_PRT_IN(port) & ~mask) | (mask & value);
return 0;
}
static int gpio_psoc6_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
GPIO_PRT_OUT_SET(port) = mask;
return 0;
}
static int gpio_psoc6_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
GPIO_PRT_OUT_CLR(port) = mask;
return 0;
}
static int gpio_psoc6_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
GPIO_PRT_OUT_INV(port) = mask;
return 0;
}
static int gpio_psoc6_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
uint32_t is_enabled = ((mode == GPIO_INT_MODE_DISABLED) ? 0 : 1);
uint32_t lv_trg = CY_GPIO_INTR_DISABLE;
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
if (is_enabled) {
switch (trig) {
case GPIO_INT_TRIG_BOTH:
lv_trg = CY_GPIO_INTR_BOTH;
break;
case GPIO_INT_TRIG_HIGH:
lv_trg = CY_GPIO_INTR_RISING;
break;
case GPIO_INT_TRIG_LOW:
lv_trg = CY_GPIO_INTR_FALLING;
break;
default:
return -EINVAL;
}
}
Cy_GPIO_ClearInterrupt(port, pin);
Cy_GPIO_SetInterruptEdge(port, pin, lv_trg);
Cy_GPIO_SetInterruptMask(port, pin, is_enabled);
/**
* The driver will set 50ns glitch free filter for any interrupt.
*/
Cy_GPIO_SetFilter(port, pin);
LOG_DBG("config: Pin: %d, Trg: %d", pin, lv_trg);
return 0;
}
static void gpio_psoc6_isr(const struct device *dev)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
struct gpio_psoc6_runtime *context = dev->data;
uint32_t int_stat;
int_stat = GPIO_PRT_INTR_MASKED(port);
/* Any INTR MMIO registers AHB clearing must be preceded with an AHB
* read access. Taken from Cy_GPIO_ClearInterrupt()
*/
(void)GPIO_PRT_INTR(port);
GPIO_PRT_INTR(port) = int_stat;
/* This read ensures that the initial write has been flushed out to HW
*/
(void)GPIO_PRT_INTR(port);
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_psoc6_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
struct gpio_psoc6_runtime *context = port->data;
return gpio_manage_callback(&context->cb, callback, set);
}
static uint32_t gpio_psoc6_get_pending_int(const struct device *dev)
{
const struct gpio_psoc6_config * const cfg = dev->config;
GPIO_PRT_Type * const port = cfg->regs;
LOG_DBG("Pending: 0x%08x", GPIO_PRT_INTR_MASKED(port));
return GPIO_PRT_INTR_MASKED(port);
}
static const struct gpio_driver_api gpio_psoc6_api = {
.pin_configure = gpio_psoc6_config,
.port_get_raw = gpio_psoc6_port_get_raw,
.port_set_masked_raw = gpio_psoc6_port_set_masked_raw,
.port_set_bits_raw = gpio_psoc6_port_set_bits_raw,
.port_clear_bits_raw = gpio_psoc6_port_clear_bits_raw,
.port_toggle_bits = gpio_psoc6_port_toggle_bits,
.pin_interrupt_configure = gpio_psoc6_pin_interrupt_configure,
.manage_callback = gpio_psoc6_manage_callback,
.get_pending_int = gpio_psoc6_get_pending_int,
};
int gpio_psoc6_init(const struct device *dev)
{
const struct gpio_psoc6_config * const cfg = dev->config;
cfg->config_func(dev);
return 0;
}
#define GPIO_PSOC6_INIT(n) \
static void port_##n##_psoc6_config_func(const struct device *dev); \
\
static const struct gpio_psoc6_config port_##n##_psoc6_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.regs = (GPIO_PRT_Type *)DT_INST_REG_ADDR(n), \
.config_func = port_##n##_psoc6_config_func, \
}; \
\
static struct gpio_psoc6_runtime port_##n##_psoc6_runtime = { 0 }; \
\
DEVICE_DT_INST_DEFINE(n, gpio_psoc6_init, NULL, \
&port_##n##_psoc6_runtime, \
&port_##n##_psoc6_config, PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_psoc6_api); \
\
static void port_##n##_psoc6_config_func(const struct device *dev) \
{ \
CY_PSOC6_DT_INST_NVIC_INSTALL(n, gpio_psoc6_isr); \
};
DT_INST_FOREACH_STATUS_OKAY(GPIO_PSOC6_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_psoc6.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,083 |
```unknown
# ARM CMSDK (Cortex-M System Design Kit) AHB GPIO cfg
config GPIO_CMSDK_AHB
bool "ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers"
default y
depends on DT_HAS_ARM_CMSDK_GPIO_ENABLED
help
Enable config options to support the ARM CMSDK GPIO controllers.
Says n if not sure.
``` | /content/code_sandbox/drivers/gpio/Kconfig.cmsdk_ahb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
# Xilinx GPIO configuration options
config GPIO_XLNX_AXI
bool "Xilinx AXI GPIO driver"
default y
depends on DT_HAS_XLNX_XPS_GPIO_1_00_A_ENABLED
help
Enable Xilinx AXI GPIO v2 driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.xlnx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/interrupt_controller/gd32_exti.h>
#include <zephyr/drivers/reset.h>
#include <gd32_gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#ifdef CONFIG_GD32_HAS_AF_PINMUX
/** SYSCFG DT node */
#define SYSCFG_NODE DT_NODELABEL(syscfg)
#else
/** AFIO DT node */
#define AFIO_NODE DT_NODELABEL(afio)
/** GPIO mode: analog (CTL bits) */
#define CTL_MODE_ANALOG 0x0U
/** GPIO mode: input floating (CTL bits) */
#define CTL_MODE_INP_FLOAT 0x4U
/** GPIO mode: input with pull-up/down (CTL bits) */
#define CTL_MODE_INP_PUPD 0x8U
/** GPIO mode: output push-pull @ 2MHz (CTL bits) */
#define CTL_MODE_OUT_PP 0x2U
/** GPIO mode: output open-drain @ 2MHz (CTL bits) */
#define CTL_MODE_OUT_OD 0x6U
#endif /* CONFIG_GD32_HAS_AF_PINMUX */
/** EXTISS mask */
#define EXTISS_MSK 0xFU
/** EXTISS line step size */
#define EXTISS_STEP 4U
/** EXTISS line shift */
#define EXTISS_LINE_SHIFT(pin) (EXTISS_STEP * ((pin) % EXTISS_STEP))
struct gpio_gd32_config {
struct gpio_driver_config common;
uint32_t reg;
uint16_t clkid;
uint16_t clkid_exti;
struct reset_dt_spec reset;
};
struct gpio_gd32_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
};
/**
* @brief EXTI ISR callback.
*
* @param line EXTI line (equals to GPIO pin number).
* @param arg GPIO port instance.
*/
static void gpio_gd32_isr(uint8_t line, void *arg)
{
const struct device *dev = arg;
struct gpio_gd32_data *data = dev->data;
gpio_fire_callbacks(&data->callbacks, dev, BIT(line));
}
/**
* @brief Configure EXTI source selection register.
*
* @param port GPIO port instance.
* @param pin GPIO pin number.
*
* @retval 0 on success.
* @retval -EINVAL if pin is not valid.
*/
static int gpio_gd32_configure_extiss(const struct device *port,
gpio_pin_t pin)
{
const struct gpio_gd32_config *config = port->config;
uint8_t port_index, shift;
volatile uint32_t *extiss;
switch (pin / EXTISS_STEP) {
#ifdef CONFIG_GD32_HAS_AF_PINMUX
case 0U:
extiss = &SYSCFG_EXTISS0;
break;
case 1U:
extiss = &SYSCFG_EXTISS1;
break;
case 2U:
extiss = &SYSCFG_EXTISS2;
break;
case 3U:
extiss = &SYSCFG_EXTISS3;
break;
#else
case 0U:
extiss = &AFIO_EXTISS0;
break;
case 1U:
extiss = &AFIO_EXTISS1;
break;
case 2U:
extiss = &AFIO_EXTISS2;
break;
case 3U:
extiss = &AFIO_EXTISS3;
break;
#endif /* CONFIG_GD32_HAS_AF_PINMUX */
default:
return -EINVAL;
}
port_index = (config->reg - GPIOA) / (GPIOB - GPIOA);
shift = EXTISS_LINE_SHIFT(pin);
*extiss &= ~(EXTISS_MSK << shift);
*extiss |= port_index << shift;
return 0;
}
static inline int gpio_gd32_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_gd32_config *config = port->config;
#ifdef CONFIG_GD32_HAS_AF_PINMUX
uint32_t ctl, pupd;
ctl = GPIO_CTL(config->reg);
ctl &= ~GPIO_MODE_MASK(pin);
pupd = GPIO_PUD(config->reg);
pupd &= ~GPIO_PUPD_MASK(pin);
if ((flags & GPIO_OUTPUT) != 0U) {
ctl |= GPIO_MODE_SET(pin, GPIO_MODE_OUTPUT);
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0U) {
GPIO_OMODE(config->reg) |= BIT(pin);
} else {
return -ENOTSUP;
}
} else {
GPIO_OMODE(config->reg) &= ~BIT(pin);
}
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
GPIO_BOP(config->reg) = BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
GPIO_BC(config->reg) = BIT(pin);
}
} else if ((flags & GPIO_INPUT) != 0U) {
ctl |= GPIO_MODE_SET(pin, GPIO_MODE_INPUT);
} else {
ctl |= GPIO_MODE_SET(pin, GPIO_MODE_ANALOG);
}
if ((flags & GPIO_PULL_UP) != 0U) {
pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_PULLUP);
} else if ((flags & GPIO_PULL_DOWN) != 0U) {
pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_PULLDOWN);
} else {
pupd |= GPIO_PUPD_SET(pin, GPIO_PUPD_NONE);
}
GPIO_PUD(config->reg) = pupd;
GPIO_CTL(config->reg) = ctl;
#else
volatile uint32_t *ctl_reg;
uint32_t ctl, pin_bit;
pin_bit = BIT(pin);
if (pin < 8U) {
ctl_reg = &GPIO_CTL0(config->reg);
} else {
ctl_reg = &GPIO_CTL1(config->reg);
pin -= 8U;
}
ctl = *ctl_reg;
ctl &= ~GPIO_MODE_MASK(pin);
if ((flags & GPIO_OUTPUT) != 0U) {
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0U) {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_OUT_OD);
} else {
return -ENOTSUP;
}
} else {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_OUT_PP);
}
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
GPIO_BOP(config->reg) = pin_bit;
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
GPIO_BC(config->reg) = pin_bit;
}
} else if ((flags & GPIO_INPUT) != 0U) {
if ((flags & GPIO_PULL_UP) != 0U) {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_PUPD);
GPIO_BOP(config->reg) = pin_bit;
} else if ((flags & GPIO_PULL_DOWN) != 0U) {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_PUPD);
GPIO_BC(config->reg) = pin_bit;
} else {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_INP_FLOAT);
}
} else {
ctl |= GPIO_MODE_SET(pin, CTL_MODE_ANALOG);
}
*ctl_reg = ctl;
#endif /* CONFIG_GD32_HAS_AF_PINMUX */
return 0;
}
static int gpio_gd32_port_get_raw(const struct device *port, uint32_t *value)
{
const struct gpio_gd32_config *config = port->config;
*value = GPIO_ISTAT(config->reg);
return 0;
}
static int gpio_gd32_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_gd32_config *config = port->config;
GPIO_OCTL(config->reg) =
(GPIO_OCTL(config->reg) & ~mask) | (value & mask);
return 0;
}
static int gpio_gd32_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_gd32_config *config = port->config;
GPIO_BOP(config->reg) = pins;
return 0;
}
static int gpio_gd32_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_gd32_config *config = port->config;
GPIO_BC(config->reg) = pins;
return 0;
}
static int gpio_gd32_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_gd32_config *config = port->config;
#ifdef CONFIG_GD32_HAS_AF_PINMUX
GPIO_TG(config->reg) = pins;
#else
GPIO_OCTL(config->reg) ^= pins;
#endif /* CONFIG_GD32_HAS_AF_PINMUX */
return 0;
}
static int gpio_gd32_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
if (mode == GPIO_INT_MODE_DISABLED) {
gd32_exti_disable(pin);
(void)gd32_exti_configure(pin, NULL, NULL);
gd32_exti_trigger(pin, GD32_EXTI_TRIG_NONE);
} else if (mode == GPIO_INT_MODE_EDGE) {
int ret;
ret = gd32_exti_configure(pin, gpio_gd32_isr, (void *)port);
if (ret < 0) {
return ret;
}
ret = gpio_gd32_configure_extiss(port, pin);
if (ret < 0) {
return ret;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
gd32_exti_trigger(pin, GD32_EXTI_TRIG_FALLING);
break;
case GPIO_INT_TRIG_HIGH:
gd32_exti_trigger(pin, GD32_EXTI_TRIG_RISING);
break;
case GPIO_INT_TRIG_BOTH:
gd32_exti_trigger(pin, GD32_EXTI_TRIG_BOTH);
break;
default:
return -ENOTSUP;
}
gd32_exti_enable(pin);
} else {
return -ENOTSUP;
}
return 0;
}
static int gpio_gd32_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_gd32_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static const struct gpio_driver_api gpio_gd32_api = {
.pin_configure = gpio_gd32_configure,
.port_get_raw = gpio_gd32_port_get_raw,
.port_set_masked_raw = gpio_gd32_port_set_masked_raw,
.port_set_bits_raw = gpio_gd32_port_set_bits_raw,
.port_clear_bits_raw = gpio_gd32_port_clear_bits_raw,
.port_toggle_bits = gpio_gd32_port_toggle_bits,
.pin_interrupt_configure = gpio_gd32_pin_interrupt_configure,
.manage_callback = gpio_gd32_manage_callback,
};
static int gpio_gd32_init(const struct device *port)
{
const struct gpio_gd32_config *config = port->config;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid_exti);
(void)reset_line_toggle_dt(&config->reset);
return 0;
}
#define GPIO_GD32_DEFINE(n) \
static const struct gpio_gd32_config gpio_gd32_config##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.reg = DT_INST_REG_ADDR(n), \
.clkid = DT_INST_CLOCKS_CELL(n, id), \
COND_CODE_1(DT_NODE_HAS_STATUS(SYSCFG_NODE, okay), \
(.clkid_exti = DT_CLOCKS_CELL(SYSCFG_NODE, id),), \
(.clkid_exti = DT_CLOCKS_CELL(AFIO_NODE, id),)) \
.reset = RESET_DT_SPEC_INST_GET(n), \
}; \
\
static struct gpio_gd32_data gpio_gd32_data##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_gd32_init, NULL, &gpio_gd32_data##n, \
&gpio_gd32_config##n, PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, &gpio_gd32_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_GD32_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,827 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_pca95xx
/**
* @file Driver for PCA95XX and PCAL95XX I2C-based GPIO driver.
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_pca95xx);
#if CONFIG_LITTLE_ENDIAN
#define LOW_BYTE_LE16_IDX 0
#define HIGH_BYTE_LE16_IDX 1
#else
#define LOW_BYTE_LE16_IDX 1
#define HIGH_BYTE_LE16_IDX 0
#endif
/* Register definitions */
#define REG_INPUT_PORT0 0x00
#define REG_INPUT_PORT1 0x01
#define REG_OUTPUT_PORT0 0x02
#define REG_OUTPUT_PORT1 0x03
#define REG_POL_INV_PORT0 0x04
#define REG_POL_INV_PORT1 0x05
#define REG_CONF_PORT0 0x06
#define REG_CONF_PORT1 0x07
#define REG_OUT_DRV_STRENGTH_PORT0_L 0x40
#define REG_OUT_DRV_STRENGTH_PORT0_H 0x41
#define REG_OUT_DRV_STRENGTH_PORT1_L 0x42
#define REG_OUT_DRV_STRENGTH_PORT1_H 0x43
#define REG_INPUT_LATCH_PORT0 0x44
#define REG_INPUT_LATCH_PORT1 0x45
#define REG_PUD_EN_PORT0 0x46
#define REG_PUD_EN_PORT1 0x47
#define REG_PUD_SEL_PORT0 0x48
#define REG_PUD_SEL_PORT1 0x49
#define REG_INT_MASK_PORT0 0x4A
#define REG_INT_MASK_PORT1 0x4B
#define REG_INT_STATUS_PORT0 0x4C
#define REG_INT_STATUS_PORT1 0x4D
#define REG_OUTPUT_PORT_CONF 0x4F
/* Driver flags */
#define PCA_HAS_PUD BIT(0)
#define PCA_HAS_INTERRUPT BIT(1)
#define PCA_HAS_INTERRUPT_MASK_REG BIT(2)
/** Configuration data */
struct gpio_pca95xx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec bus;
uint8_t capabilities;
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
struct gpio_dt_spec int_gpio;
#endif
};
/** Runtime driver data */
struct gpio_pca95xx_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct {
uint16_t input;
uint16_t output;
uint16_t dir;
uint16_t pud_en;
uint16_t pud_sel;
uint16_t int_mask;
uint16_t input_latch;
} reg_cache;
struct k_sem lock;
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
/* Self-reference to the driver instance */
const struct device *instance;
/* port ISR callback routine address */
sys_slist_t callbacks;
/* interrupt triggering pin masks */
struct {
uint16_t edge_rising;
uint16_t edge_falling;
uint16_t level_high;
uint16_t level_low;
} interrupts;
struct gpio_callback gpio_callback;
struct k_work interrupt_worker;
bool interrupt_active;
#endif
};
static int read_port_reg(const struct device *dev, uint8_t reg, uint8_t pin,
uint16_t *cache, uint16_t *buf)
{
const struct gpio_pca95xx_config * const config = dev->config;
uint8_t b_buf;
int ret;
if (pin >= 8) {
reg++;
}
ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf);
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: error reading register 0x%X (%d)",
config->bus.addr, reg, ret);
return ret;
}
if (pin < 8) {
((uint8_t *)cache)[LOW_BYTE_LE16_IDX] = b_buf;
} else {
((uint8_t *)cache)[HIGH_BYTE_LE16_IDX] = b_buf;
}
*buf = *cache;
LOG_DBG("PCA95XX[0x%X]: Read: REG[0x%X] = 0x%X",
config->bus.addr, reg, b_buf);
return 0;
}
/**
* @brief Read both port 0 and port 1 registers of certain register function.
*
* Given the register in reg, read the pair of port 0 and port 1.
*
* @param dev Device struct of the PCA95XX.
* @param reg Register to read (the PORT0 of the pair of registers).
* @param cache Pointer to the cache to be updated after successful read.
* @param buf Buffer to read data into.
*
* @return 0 if successful, failed otherwise.
*/
static int read_port_regs(const struct device *dev, uint8_t reg,
uint16_t *cache, uint16_t *buf)
{
const struct gpio_pca95xx_config * const config = dev->config;
uint16_t port_data, value;
int ret;
ret = i2c_burst_read_dt(&config->bus, reg, (uint8_t *)&port_data,
sizeof(port_data));
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: error reading register 0x%X (%d)",
config->bus.addr, reg, ret);
return ret;
}
value = sys_le16_to_cpu(port_data);
*cache = value;
*buf = value;
LOG_DBG("PCA95XX[0x%X]: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X",
config->bus.addr, reg, (*buf & 0xFF), (reg + 1), (*buf >> 8));
return 0;
}
static int write_port_reg(const struct device *dev, uint8_t reg, uint8_t pin,
uint16_t *cache, uint16_t value)
{
const struct gpio_pca95xx_config * const config = dev->config;
uint8_t buf[2];
int ret;
if (pin < 8) {
buf[1] = value;
} else {
buf[1] = value >> 8;
reg++;
}
buf[0] = reg;
LOG_DBG("PCA95XX[0x%X]: Write: REG[0x%X] = 0x%X", config->bus.addr,
reg, buf[1]);
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret == 0) {
*cache = value;
} else {
LOG_ERR("PCA95XX[0x%X]: error writing to register 0x%X "
"(%d)", config->bus.addr, reg, ret);
}
return ret;
}
/**
* @brief Write both port 0 and port 1 registers of certain register function.
*
* Given the register in reg, write the pair of port 0 and port 1.
*
* @param dev Device struct of the PCA95XX.
* @param reg Register to write into (the PORT0 of the pair of registers).
* @param cache Pointer to the cache to be updated after successful write.
* @param value New value to set.
*
* @return 0 if successful, failed otherwise.
*/
static int write_port_regs(const struct device *dev, uint8_t reg,
uint16_t *cache, uint16_t value)
{
const struct gpio_pca95xx_config * const config = dev->config;
uint8_t buf[3];
int ret;
LOG_DBG("PCA95XX[0x%X]: Write: REG[0x%X] = 0x%X, REG[0x%X] = "
"0x%X", config->bus.addr, reg, (value & 0xFF),
(reg + 1), (value >> 8));
buf[0] = reg;
sys_put_le16(value, &buf[1]);
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret == 0) {
*cache = value;
} else {
LOG_ERR("PCA95XX[0x%X]: error writing to register 0x%X "
"(%d)", config->bus.addr, reg, ret);
}
return ret;
}
static inline int update_input_reg(const struct device *dev, uint8_t pin,
uint16_t *buf)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return read_port_reg(dev, REG_INPUT_PORT0, pin,
&drv_data->reg_cache.input, buf);
}
static inline int update_input_regs(const struct device *dev, uint16_t *buf)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return read_port_regs(dev, REG_INPUT_PORT0,
&drv_data->reg_cache.input, buf);
}
static inline int update_output_reg(const struct device *dev, uint8_t pin,
uint16_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return write_port_reg(dev, REG_OUTPUT_PORT0, pin,
&drv_data->reg_cache.output, value);
}
static inline int update_output_regs(const struct device *dev, uint16_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return write_port_regs(dev, REG_OUTPUT_PORT0,
&drv_data->reg_cache.output, value);
}
static inline int update_direction_reg(const struct device *dev, uint8_t pin,
uint16_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return write_port_reg(dev, REG_CONF_PORT0, pin,
&drv_data->reg_cache.dir, value);
}
static inline int update_pul_sel_reg(const struct device *dev, uint8_t pin,
uint16_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return write_port_reg(dev, REG_PUD_SEL_PORT0, pin,
&drv_data->reg_cache.pud_sel, value);
}
static inline int update_pul_en_reg(const struct device *dev, uint8_t pin,
uint8_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
return write_port_reg(dev, REG_PUD_EN_PORT0, pin,
&drv_data->reg_cache.pud_en, value);
}
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
static inline int update_int_mask_reg(const struct device *dev, uint8_t pin,
uint16_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
/* If the interrupt mask is present, so is the input latch */
write_port_reg(dev, REG_INPUT_LATCH_PORT0, pin, &drv_data->reg_cache.input_latch, ~value);
return write_port_reg(dev, REG_INT_MASK_PORT0, pin,
&drv_data->reg_cache.int_mask, value);
}
#endif /* CONFIG_GPIO_PCA95XX_INTERRUPT */
/**
* @brief Setup the pin direction (input or output)
*
* @param dev Device struct of the PCA95XX
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t reg_dir = drv_data->reg_cache.dir;
uint16_t reg_out = drv_data->reg_cache.output;
int ret;
/* For each pin, 0 == output, 1 == input */
if ((flags & GPIO_OUTPUT) != 0U) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
reg_out |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
reg_out &= ~BIT(pin);
}
ret = update_output_reg(dev, pin, reg_out);
if (ret != 0) {
return ret;
}
reg_dir &= ~BIT(pin);
} else {
reg_dir |= BIT(pin);
}
ret = update_direction_reg(dev, pin, reg_dir);
return ret;
}
/**
* @brief Setup the pin pull up/pull down status
*
* @param dev Device struct of the PCA95XX
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int setup_pin_pullupdown(const struct device *dev, uint32_t pin,
int flags)
{
const struct gpio_pca95xx_config * const config = dev->config;
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t reg_pud;
int ret;
if ((config->capabilities & PCA_HAS_PUD) == 0) {
/* Chip does not support pull up/pull down */
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
return -ENOTSUP;
}
/* If both GPIO_PULL_UP and GPIO_PULL_DOWN are not set,
* we should disable them in hardware. But need to skip
* if the chip does not support pull up/pull down.
*/
return 0;
}
/* If disabling pull up/down, there is no need to set the selection
* register. Just go straight to disabling.
*/
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
/* Setup pin pull up or pull down */
reg_pud = drv_data->reg_cache.pud_sel;
/* pull down == 0, pull up == 1 */
WRITE_BIT(reg_pud, pin, (flags & GPIO_PULL_UP) != 0U);
ret = update_pul_sel_reg(dev, pin, reg_pud);
if (ret) {
return ret;
}
}
/* enable/disable pull up/down */
reg_pud = drv_data->reg_cache.pud_en;
WRITE_BIT(reg_pud, pin,
(flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U);
ret = update_pul_en_reg(dev, pin, reg_pud);
return ret;
}
/**
* @brief Configure pin or port
*
* @param dev Device struct of the PCA95XX
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_pca95xx_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
int ret;
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
#if (CONFIG_GPIO_LOG_LEVEL >= LOG_LEVEL_DEBUG)
const struct gpio_pca95xx_config * const config = dev->config;
#endif
/* Does not support disconnected pin */
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
/* Open-drain support is per port, not per pin.
* So can't really support the API as-is.
*/
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP;
}
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = setup_pin_dir(dev, pin, flags);
if (ret) {
LOG_ERR("PCA95XX[0x%X]: error setting pin direction (%d)",
config->bus.addr, ret);
goto done;
}
ret = setup_pin_pullupdown(dev, pin, flags);
if (ret) {
LOG_ERR("PCA95XX[0x%X]: error setting pin pull up/down "
"(%d)", config->bus.addr, ret);
goto done;
}
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_pca95xx_port_get_raw(const struct device *dev, uint32_t *value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t buf;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = update_input_regs(dev, &buf);
if (ret != 0) {
goto done;
}
*value = buf;
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_pca95xx_port_set_masked_raw(const struct device *dev,
uint32_t mask, uint32_t value)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->reg_cache.output;
reg_out = (reg_out & ~mask) | (mask & value);
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_pca95xx_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_pca95xx_port_set_masked_raw(dev, mask, mask);
}
static int gpio_pca95xx_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_pca95xx_port_set_masked_raw(dev, mask, 0);
}
static int gpio_pca95xx_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->reg_cache.output;
reg_out ^= mask;
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
static void get_triggered_it(struct gpio_pca95xx_drv_data *drv_data,
uint16_t *trig_edge, uint16_t *trig_level)
{
uint16_t input_cache, changed_pins, input_new;
int ret;
input_cache = drv_data->reg_cache.input;
ret = update_input_regs(drv_data->instance, &input_new);
if (ret == 0) {
changed_pins = (input_cache ^ input_new);
*trig_edge |= (changed_pins & input_new &
drv_data->interrupts.edge_rising);
*trig_edge |= (changed_pins & input_cache &
drv_data->interrupts.edge_falling);
*trig_level |= (input_new & drv_data->interrupts.level_high);
*trig_level |= (~input_new & drv_data->interrupts.level_low);
}
}
static void gpio_pca95xx_interrupt_worker(struct k_work *work)
{
struct gpio_pca95xx_drv_data * const drv_data = CONTAINER_OF(
work, struct gpio_pca95xx_drv_data, interrupt_worker);
const struct gpio_pca95xx_config * const config = drv_data->instance->config;
uint16_t trig_edge = 0, trig_level = 0;
uint32_t triggered_int = 0;
k_sem_take(&drv_data->lock, K_FOREVER);
/* Note: PCA Interrupt status is cleared by reading inputs */
if (config->capabilities & PCA_HAS_INTERRUPT_MASK_REG) {
/* gpio latched read values, to be compared to cached ones */
get_triggered_it(drv_data, &trig_edge, &trig_level);
}
/* gpio unlatched read values, in case signal has flipped again */
get_triggered_it(drv_data, &trig_edge, &trig_level);
triggered_int = (trig_edge | trig_level);
k_sem_give(&drv_data->lock);
if (triggered_int != 0) {
gpio_fire_callbacks(&drv_data->callbacks, drv_data->instance,
triggered_int);
}
/* Emulate level triggering */
if (trig_level != 0) {
/* Reschedule worker */
k_work_submit(&drv_data->interrupt_worker);
}
}
static void gpio_pca95xx_interrupt_callback(const struct device *dev,
struct gpio_callback *cb,
gpio_port_pins_t pins)
{
struct gpio_pca95xx_drv_data * const drv_data =
CONTAINER_OF(cb, struct gpio_pca95xx_drv_data, gpio_callback);
ARG_UNUSED(pins);
/* Cannot read PCA95xx registers from ISR context, queue worker */
k_work_submit(&drv_data->interrupt_worker);
}
static int gpio_pca95xx_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
int ret = 0;
const struct gpio_pca95xx_config * const config = dev->config;
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
uint16_t reg;
bool enabled, edge, level, active;
/* Check if GPIO port supports interrupts */
if ((config->capabilities & PCA_HAS_INTERRUPT) == 0U) {
return -ENOTSUP;
}
/* Check for an invalid pin number */
if (BIT(pin) > config->common.port_pin_mask) {
return -EINVAL;
}
/* Check configured pin direction */
if ((mode != GPIO_INT_MODE_DISABLED) &&
(BIT(pin) & drv_data->reg_cache.dir) != BIT(pin)) {
LOG_ERR("PCA95XX[0x%X]: output pin cannot trigger interrupt",
config->bus.addr);
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
/* Check if GPIO port has an interrupt mask register */
if (config->capabilities & PCA_HAS_INTERRUPT_MASK_REG) {
uint16_t reg_out;
reg_out = drv_data->reg_cache.int_mask;
WRITE_BIT(reg_out, pin, (mode == GPIO_INT_MODE_DISABLED));
ret = update_int_mask_reg(dev, pin, reg_out);
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: failed to update int mask (%d)",
config->bus.addr, ret);
goto err;
}
}
/* Update interrupt masks */
enabled = ((mode & GPIO_INT_MODE_DISABLED) == 0U);
edge = (mode == GPIO_INT_MODE_EDGE);
level = (mode == GPIO_INT_MODE_LEVEL);
WRITE_BIT(drv_data->interrupts.edge_rising, pin, (enabled &&
edge && ((trig & GPIO_INT_TRIG_HIGH) == GPIO_INT_TRIG_HIGH)));
WRITE_BIT(drv_data->interrupts.edge_falling, pin, (enabled &&
edge && ((trig & GPIO_INT_TRIG_LOW) == GPIO_INT_TRIG_LOW)));
WRITE_BIT(drv_data->interrupts.level_high, pin, (enabled &&
level && ((trig & GPIO_INT_TRIG_HIGH) == GPIO_INT_TRIG_HIGH)));
WRITE_BIT(drv_data->interrupts.level_low, pin, (enabled &&
level && ((trig & GPIO_INT_TRIG_LOW) == GPIO_INT_TRIG_LOW)));
active = ((drv_data->interrupts.edge_rising ||
drv_data->interrupts.edge_falling ||
drv_data->interrupts.level_high ||
drv_data->interrupts.level_low) > 0);
/* Enable / disable interrupt as needed */
if (active != drv_data->interrupt_active) {
ret = gpio_pin_interrupt_configure_dt(
&config->int_gpio, active ?
GPIO_INT_EDGE_TO_ACTIVE :
GPIO_INT_MODE_DISABLED);
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: failed to configure interrupt "
"on pin %d (%d)", config->bus.addr,
config->int_gpio.pin, ret);
goto err;
}
drv_data->interrupt_active = active;
if (active) {
/* Read current status to reset any
* active signal on INT line
*/
update_input_regs(dev, ®);
}
}
err:
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_pca95xx_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
const struct gpio_pca95xx_config * const config = dev->config;
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
if ((config->capabilities & PCA_HAS_INTERRUPT) == 0U) {
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
gpio_manage_callback(&drv_data->callbacks, callback, set);
k_sem_give(&drv_data->lock);
return 0;
}
#endif /* CONFIG_GPIO_PCA95XX_INTERRUPT */
static const struct gpio_driver_api gpio_pca95xx_drv_api_funcs = {
.pin_configure = gpio_pca95xx_config,
.port_get_raw = gpio_pca95xx_port_get_raw,
.port_set_masked_raw = gpio_pca95xx_port_set_masked_raw,
.port_set_bits_raw = gpio_pca95xx_port_set_bits_raw,
.port_clear_bits_raw = gpio_pca95xx_port_clear_bits_raw,
.port_toggle_bits = gpio_pca95xx_port_toggle_bits,
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
.pin_interrupt_configure = gpio_pca95xx_pin_interrupt_configure,
.manage_callback = gpio_pca95xx_manage_callback,
#endif
};
/**
* @brief Initialization function of PCA95XX
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_pca95xx_init(const struct device *dev)
{
const struct gpio_pca95xx_config * const config = dev->config;
struct gpio_pca95xx_drv_data * const drv_data =
(struct gpio_pca95xx_drv_data * const)dev->data;
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
k_sem_init(&drv_data->lock, 1, 1);
#ifdef CONFIG_GPIO_PCA95XX_INTERRUPT
/* Check if GPIO port supports interrupts */
if ((config->capabilities & PCA_HAS_INTERRUPT) != 0) {
int ret;
/* Store self-reference for interrupt handling */
drv_data->instance = dev;
/* Prepare interrupt worker */
k_work_init(&drv_data->interrupt_worker,
gpio_pca95xx_interrupt_worker);
/* Configure GPIO interrupt pin */
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("PCA95XX[0x%X]: interrupt GPIO not ready",
config->bus.addr);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: failed to configure interrupt"
" pin %d (%d)", config->bus.addr,
config->int_gpio.pin, ret);
return ret;
}
/* Prepare GPIO callback for interrupt pin */
gpio_init_callback(&drv_data->gpio_callback,
gpio_pca95xx_interrupt_callback,
BIT(config->int_gpio.pin));
ret = gpio_add_callback(config->int_gpio.port, &drv_data->gpio_callback);
if (ret != 0) {
LOG_ERR("PCA95XX[0x%X]: failed to add interrupt callback for"
" pin %d (%d)", config->bus.addr,
config->int_gpio.pin, ret);
return ret;
}
}
#endif
return 0;
}
#define GPIO_PCA95XX_DEVICE_INSTANCE(inst) \
static const struct gpio_pca95xx_config gpio_pca95xx_##inst##_cfg = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.bus = I2C_DT_SPEC_INST_GET(inst), \
.capabilities = \
(DT_INST_PROP(inst, has_pud) ? PCA_HAS_PUD : 0) | \
IF_ENABLED(CONFIG_GPIO_PCA95XX_INTERRUPT, ( \
(DT_INST_NODE_HAS_PROP(inst, interrupt_gpios) ? \
PCA_HAS_INTERRUPT : 0) | \
(DT_INST_PROP(inst, has_interrupt_mask_reg) ? \
PCA_HAS_INTERRUPT_MASK_REG : 0) | \
)) \
0, \
IF_ENABLED(CONFIG_GPIO_PCA95XX_INTERRUPT, \
(.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, interrupt_gpios, {}),)) \
}; \
\
static struct gpio_pca95xx_drv_data gpio_pca95xx_##inst##_drvdata = { \
.reg_cache.input = 0x0, \
.reg_cache.output = 0xFFFF, \
.reg_cache.dir = 0xFFFF, \
.reg_cache.pud_en = 0x0, \
.reg_cache.pud_sel = 0xFFFF, \
.reg_cache.int_mask = 0xFFFF, \
.reg_cache.input_latch = 0x0, \
IF_ENABLED(CONFIG_GPIO_PCA95XX_INTERRUPT, ( \
.interrupt_active = false, \
)) \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
gpio_pca95xx_init, \
NULL, \
&gpio_pca95xx_##inst##_drvdata, \
&gpio_pca95xx_##inst##_cfg, \
POST_KERNEL, CONFIG_GPIO_PCA95XX_INIT_PRIORITY, \
&gpio_pca95xx_drv_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(GPIO_PCA95XX_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_pca95xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,864 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_gpio_v2
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
#include <soc.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define XEC_GPIO_EDGE_DLY_COUNT 4
LOG_MODULE_REGISTER(gpio, CONFIG_GPIO_LOG_LEVEL);
static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
(MCHP_GPIO_PORT_A_BITMAP),
(MCHP_GPIO_PORT_B_BITMAP),
(MCHP_GPIO_PORT_C_BITMAP),
(MCHP_GPIO_PORT_D_BITMAP),
(MCHP_GPIO_PORT_E_BITMAP),
(MCHP_GPIO_PORT_F_BITMAP),
};
struct gpio_xec_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
struct gpio_xec_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uintptr_t pcr1_base;
uintptr_t parin_addr;
uintptr_t parout_addr;
uint8_t girq_id;
uint8_t port_num;
uint32_t flags;
};
/* Each GPIO pin 32-bit control register located consecutively in memory */
static inline uintptr_t pin_ctrl_addr(const struct device *dev, gpio_pin_t pin)
{
const struct gpio_xec_config *config = dev->config;
return config->pcr1_base + ((uintptr_t)pin * 4u);
}
/* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
static inline uintptr_t pin_parin_addr(const struct device *dev)
{
const struct gpio_xec_config *config = dev->config;
return config->parin_addr;
}
/* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
static inline uintptr_t pin_parout_addr(const struct device *dev)
{
const struct gpio_xec_config *config = dev->config;
return config->parout_addr;
}
/*
* Use Zephyr system API to implement
* reg32(addr) = (reg32(addr) & ~mask) | (val & mask)
*/
static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val)
{
uint32_t r = (sys_read32(addr) & ~mask) | (val & mask);
sys_write32(r, addr);
}
/*
* NOTE: gpio_flags_t b[15:0] are defined in the dt-binding gpio header.
* b[31:16] are defined in the driver gpio header.
* Hardware only supports push-pull or open-drain.
*/
static int gpio_xec_validate_flags(gpio_flags_t flags)
{
if ((flags & (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN))
== (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)) {
return -ENOTSUP;
}
if ((flags & (GPIO_INPUT | GPIO_OUTPUT))
== (GPIO_INPUT | GPIO_OUTPUT)) {
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT_INIT_LOW) && (flags & GPIO_OUTPUT_INIT_HIGH)) {
return -EINVAL;
}
return 0;
}
/*
* Each GPIO pin has two 32-bit control registers. Control 1 configures pin
* features except for drive strength and slew rate in Control 2.
* A pin's input and output state can be read/written from either the Control 1
* register or from corresponding bits in the GPIO parallel input/output registers.
* The parallel input and output registers group 32 pins into each register.
* The GPIO hardware restricts the pin output state to Control 1 or the parallel bit.
* Both output bits reflect each other on read and writes but only one is writable
* selected by the output control select bit in Control 1. In the configuration API
* we use Control 1 to configure all pin features and output state. Before exiting,
* we set the output select for parallel mode enabling writes to the parallel output bit.
*/
static int gpio_xec_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_xec_config *config = dev->config;
uintptr_t pcr1_addr = 0u;
uint32_t pcr1 = 0u, pcr1_new = 0u;
uint32_t msk = (MCHP_GPIO_CTRL_PWRG_MASK
| MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_DIR_MASK
| MCHP_GPIO_CTRL_AOD_MASK | BIT(MCHP_GPIO_CTRL_POL_POS)
| MCHP_GPIO_CTRL_MUX_MASK | MCHP_GPIO_CTRL_INPAD_DIS_MASK);
if (!(valid_ctrl_masks[config->port_num] & BIT(pin))) {
return -EINVAL;
}
int ret = gpio_xec_validate_flags(flags);
if (ret) {
return ret;
}
pcr1_addr = pin_ctrl_addr(dev, pin);
pcr1 = sys_read32(pcr1_addr);
/* Check if pin is in GPIO mode */
if (MCHP_GPIO_CTRL_MUX_GET(pcr1) != MCHP_GPIO_CTRL_MUX_F0) {
LOG_WRN("Port:%d pin:0x%x not in GPIO mode. CTRL[%x]=%x", config->port_num, pin,
(uint32_t)pcr1_addr, pcr1);
}
if (flags == GPIO_DISCONNECTED) {
pcr1 = (pcr1 & ~MCHP_GPIO_CTRL_PWRG_MASK) | MCHP_GPIO_CTRL_PWRG_OFF;
sys_write32(pcr1, pcr1_addr);
return 0;
}
/* final pin state will be powered */
pcr1_new = MCHP_GPIO_CTRL_PWRG_VTR_IO;
/* always enable input pad */
if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)) {
pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
sys_write32(pcr1, pcr1_addr);
}
if (flags & GPIO_OUTPUT) {
pcr1_new |= BIT(MCHP_GPIO_CTRL_DIR_POS);
msk |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else { /* copy current input state to output state */
if ((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF) {
pcr1 &= ~(MCHP_GPIO_CTRL_PWRG_MASK);
pcr1 |= MCHP_GPIO_CTRL_PWRG_VTR_IO;
sys_write32(pcr1, pcr1_addr);
}
pcr1 = sys_read32(pcr1_addr);
if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else {
pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
}
}
if (flags & GPIO_LINE_OPEN_DRAIN) {
pcr1_new |= BIT(MCHP_GPIO_CTRL_BUFT_POS);
}
}
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
msk |= MCHP_GPIO_CTRL_PUD_MASK;
/* both bits specifies repeater mode */
if (flags & GPIO_PULL_UP) {
pcr1_new |= MCHP_GPIO_CTRL_PUD_PU;
}
if (flags & GPIO_PULL_DOWN) {
pcr1_new |= MCHP_GPIO_CTRL_PUD_PD;
}
}
/*
* Problem, if pin was power gated off we can't read input.
* How to turn on pin to read input but not glitch it?
*/
pcr1 = (pcr1 & ~msk) | (pcr1_new & msk);
sys_write32(pcr1, pcr1_addr); /* configuration. may generate a single edge */
/* Control output bit becomes read-only and parallel out register bit becomes r/w */
sys_write32(pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS), pcr1_addr);
return 0;
}
static int gen_gpio_ctrl_icfg(enum gpio_int_mode mode, enum gpio_int_trig trig,
uint32_t *pin_ctr1)
{
if (!pin_ctr1) {
return -EINVAL;
}
if (mode == GPIO_INT_MODE_DISABLED) {
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_DISABLE;
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig == GPIO_INT_TRIG_HIGH) {
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_HI;
} else {
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_LO;
}
} else {
switch (trig) {
case GPIO_INT_TRIG_LOW:
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_FEDGE;
break;
case GPIO_INT_TRIG_HIGH:
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_REDGE;
break;
case GPIO_INT_TRIG_BOTH:
*pin_ctr1 = MCHP_GPIO_CTRL_IDET_BEDGE;
break;
default:
return -EINVAL;
}
}
}
return 0;
}
static void gpio_xec_intr_en(gpio_pin_t pin, enum gpio_int_mode mode,
uint8_t girq_id)
{
if (mode != GPIO_INT_MODE_DISABLED) {
/* Enable interrupt to propagate via its GIRQ to the NVIC */
mchp_soc_ecia_girq_src_en(girq_id, pin);
}
}
static int gpio_xec_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_xec_config *config = dev->config;
uintptr_t pcr1_addr = pin_ctrl_addr(dev, pin);
uint32_t pcr1 = 0u;
uint32_t pcr1_req = 0u;
/* Validate pin number range in terms of current port */
if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
return -EINVAL;
}
/* Check if GPIO port supports interrupts */
if ((mode != GPIO_INT_MODE_DISABLED) &&
((config->flags & GPIO_INT_ENABLE) == 0)) {
return -ENOTSUP;
}
pcr1_req = MCHP_GPIO_CTRL_IDET_DISABLE;
if (gen_gpio_ctrl_icfg(mode, trig, &pcr1_req)) {
return -EINVAL;
}
/* Disable interrupt in the EC aggregator */
mchp_soc_ecia_girq_src_dis(config->girq_id, pin);
/* pin configuration matches requested detection mode? */
pcr1 = sys_read32(pcr1_addr);
/* HW detects interrupt on input. Make sure input pad disable is cleared */
pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
if ((pcr1 & MCHP_GPIO_CTRL_IDET_MASK) == pcr1_req) {
gpio_xec_intr_en(pin, mode, config->girq_id);
return 0;
}
pcr1 &= ~MCHP_GPIO_CTRL_IDET_MASK;
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig == GPIO_INT_TRIG_HIGH) {
pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_HI;
} else {
pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_LO;
}
} else if (mode == GPIO_INT_MODE_EDGE) {
if (trig == GPIO_INT_TRIG_LOW) {
pcr1 |= MCHP_GPIO_CTRL_IDET_FEDGE;
} else if (trig == GPIO_INT_TRIG_HIGH) {
pcr1 |= MCHP_GPIO_CTRL_IDET_REDGE;
} else if (trig == GPIO_INT_TRIG_BOTH) {
pcr1 |= MCHP_GPIO_CTRL_IDET_BEDGE;
}
} else {
pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
}
sys_write32(pcr1, pcr1_addr);
/* delay for HW to synchronize after it ungates its clock */
for (int i = 0; i < XEC_GPIO_EDGE_DLY_COUNT; i++) {
sys_read32(pcr1_addr);
}
mchp_soc_ecia_girq_src_clr(config->girq_id, pin);
gpio_xec_intr_en(pin, mode, config->girq_id);
return 0;
}
static int gpio_xec_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
uintptr_t pout_addr = pin_parout_addr(dev);
xec_mask_write32(pout_addr, mask, value);
return 0;
}
static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
uintptr_t pout_addr = pin_parout_addr(dev);
sys_write32(sys_read32(pout_addr) | mask, pout_addr);
return 0;
}
static int gpio_xec_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
uintptr_t pout_addr = pin_parout_addr(dev);
sys_write32(sys_read32(pout_addr) & ~mask, pout_addr);
return 0;
}
static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)
{
uintptr_t pout_addr = pin_parout_addr(dev);
sys_write32(sys_read32(pout_addr) ^ mask, pout_addr);
return 0;
}
static int gpio_xec_port_get_raw(const struct device *dev, uint32_t *value)
{
uintptr_t pin_addr = pin_parin_addr(dev);
*value = sys_read32(pin_addr);
return 0;
}
static int gpio_xec_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_xec_data *data = dev->data;
gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_xec_get_direction(const struct device *port, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
if (!port) {
return -EINVAL;
}
const struct gpio_xec_config *config = port->config;
uint32_t valid_msk = valid_ctrl_masks[config->port_num];
*inputs = 0u;
*outputs = 0u;
for (uint8_t pin = 0; pin < 32; pin++) {
if (!map) {
break;
}
if ((map & BIT(pin)) && (valid_msk & BIT(pin))) {
uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
uint32_t pcr1 = sys_read32(pcr1_addr);
if (!((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF)) {
if (outputs && (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS))) {
*outputs |= BIT(pin);
} else if (inputs && !(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
*inputs |= BIT(pin);
}
}
map &= ~BIT(pin);
}
}
return 0;
}
#endif
#ifdef CONFIG_GPIO_GET_CONFIG
int gpio_xec_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
{
if (!port || !flags) {
return -EINVAL;
}
const struct gpio_xec_config *config = port->config;
uint32_t valid_msk = valid_ctrl_masks[config->port_num];
if (!(valid_msk & BIT(pin))) {
return -EINVAL;
/* Or should we set *flags = GPIO_DISCONNECTED and return success? */
}
uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
uint32_t pcr1 = sys_read32(pcr1_addr);
uint32_t pin_flags = 0u;
if (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS)) {
pin_flags |= GPIO_OUTPUT;
if (pcr1 & BIT(MCHP_GPIO_CTRL_OUTVAL_POS)) {
pin_flags |= GPIO_OUTPUT_INIT_HIGH;
} else {
pin_flags |= GPIO_OUTPUT_INIT_LOW;
}
if (pcr1 & BIT(MCHP_GPIO_CTRL_BUFT_POS)) {
pin_flags |= GPIO_OPEN_DRAIN;
}
} else if (!(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
pin_flags |= GPIO_INPUT;
}
if (pin_flags) {
*flags = pin_flags;
} else {
*flags = GPIO_DISCONNECTED;
}
return 0;
}
#endif
static void gpio_gpio_xec_port_isr(const struct device *dev)
{
const struct gpio_xec_config *config = dev->config;
struct gpio_xec_data *data = dev->data;
uint32_t girq_result;
/*
* Figure out which interrupts have been triggered from the EC
* aggregator result register
*/
girq_result = mchp_soc_ecia_girq_result(config->girq_id);
/* Clear source register in aggregator before firing callbacks */
mchp_soc_ecia_girq_src_clr_bitmap(config->girq_id, girq_result);
gpio_fire_callbacks(&data->callbacks, dev, girq_result);
}
/* GPIO driver official API table */
static const struct gpio_driver_api gpio_xec_driver_api = {
.pin_configure = gpio_xec_configure,
.port_get_raw = gpio_xec_port_get_raw,
.port_set_masked_raw = gpio_xec_port_set_masked_raw,
.port_set_bits_raw = gpio_xec_port_set_bits_raw,
.port_clear_bits_raw = gpio_xec_port_clear_bits_raw,
.port_toggle_bits = gpio_xec_port_toggle_bits,
.pin_interrupt_configure = gpio_xec_pin_interrupt_configure,
.manage_callback = gpio_xec_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_xec_get_direction,
#endif
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_xec_get_config,
#endif
};
#define XEC_GPIO_PORT_FLAGS(n) \
((DT_INST_IRQ_HAS_CELL(n, irq)) ? GPIO_INT_ENABLE : 0)
#define XEC_GPIO_PORT(n) \
static int gpio_xec_port_init_##n(const struct device *dev) \
{ \
if (!(DT_INST_IRQ_HAS_CELL(n, irq))) { \
return 0; \
} \
\
const struct gpio_xec_config *config = dev->config; \
\
mchp_soc_ecia_girq_aggr_en(config->girq_id, 1); \
\
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_gpio_xec_port_isr, \
DEVICE_DT_INST_GET(n), 0U); \
\
irq_enable(DT_INST_IRQN(n)); \
\
return 0; \
} \
\
static struct gpio_xec_data gpio_xec_port_data_##n; \
\
static const struct gpio_xec_config xec_gpio_config_##n = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
.parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
.parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2),\
.port_num = DT_INST_PROP(n, port_id), \
.girq_id = DT_INST_PROP_OR(n, girq_id, 0), \
.flags = XEC_GPIO_PORT_FLAGS(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, gpio_xec_port_init_##n, NULL, \
&gpio_xec_port_data_##n, &xec_gpio_config_##n, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_xec_driver_api);
DT_INST_FOREACH_STATUS_OKAY(XEC_GPIO_PORT)
``` | /content/code_sandbox/drivers/gpio/gpio_mchp_xec_v2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,557 |
```unknown
# EOS_S3 GPIO configuration options
config GPIO_EOS_S3
bool "EOS_S3 GPIO driver"
default y
depends on DT_HAS_QUICKLOGIC_EOS_S3_GPIO_ENABLED
help
Enable the EOS S3 gpio driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.eos_s3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# MCUX RGPIO configuration options
config GPIO_MCUX_RGPIO
bool "MCUX RGPIO driver"
default y
depends on DT_HAS_NXP_IMX_RGPIO_ENABLED
select PINCTRL
help
Enable the MCUX RGPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.mcux_rgpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_nct38xx_gpio_alert
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_nct38xx.h>
#include <zephyr/drivers/mfd/nct38xx.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util_macro.h>
#include "gpio_nct38xx.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(gpio_ntc38xx, CONFIG_GPIO_LOG_LEVEL);
struct nct38xx_mfd {
/* Lock for NCT38xx register access */
struct k_sem *lock;
/* I2C device used for register access */
const struct i2c_dt_spec *i2c_dev;
};
/* Driver config */
struct nct38xx_alert_config {
/* Alert GPIO pin */
const struct gpio_dt_spec irq_gpio;
/* NCT38XX devices which share the same alert pin */
const struct device **nct38xx_dev;
/* Number of NCT38XX devices on the alert pin */
uint32_t nct38xx_num;
};
/* Driver data */
struct nct38xx_alert_data {
/* Alert handler device */
const struct device *alert_dev;
/* Alert pin callback */
struct gpio_callback gpio_cb;
/* Alert worker */
struct k_work alert_worker;
/* Lock for NCT38xx register access */
struct nct38xx_mfd *mfd;
};
static void nct38xx_alert_callback(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
ARG_UNUSED(pins);
struct nct38xx_alert_data *data = CONTAINER_OF(cb, struct nct38xx_alert_data, gpio_cb);
k_work_submit(&data->alert_worker);
}
static bool nct38xx_alert_is_active(struct nct38xx_mfd *mfd)
{
int ret;
uint16_t alert, mask;
k_sem_take(mfd->lock, K_FOREVER);
/* Clear alert */
ret = i2c_burst_read_dt(mfd->i2c_dev, NCT38XX_REG_ALERT, (uint8_t *)&alert,
sizeof(alert));
if (ret < 0) {
goto release_lock;
}
ret = i2c_burst_read_dt(mfd->i2c_dev, NCT38XX_REG_ALERT_MASK,
(uint8_t *)&mask, sizeof(mask));
if (ret < 0) {
goto release_lock;
}
alert &= mask;
if (alert) {
ret = i2c_burst_write_dt(mfd->i2c_dev, NCT38XX_REG_ALERT,
(uint8_t *)&alert, sizeof(alert));
}
release_lock:
k_sem_give(mfd->lock);
if (ret < 0) {
LOG_ERR("i2c access failed");
return false;
}
if (alert & BIT(NCT38XX_REG_ALERT_VENDOR_DEFINDED_ALERT)) {
return true;
}
return false;
}
static void nct38xx_alert_worker(struct k_work *work)
{
struct nct38xx_alert_data *const data =
CONTAINER_OF(work, struct nct38xx_alert_data, alert_worker);
const struct nct38xx_alert_config *const config = data->alert_dev->config;
do {
/* NCT38XX device handler */
for (int i = 0; i < config->nct38xx_num; i++) {
struct nct38xx_mfd *mfd = &data->mfd[i];
if (nct38xx_alert_is_active(mfd)) {
nct38xx_gpio_alert_handler(config->nct38xx_dev[i]);
}
}
/* While the interrupt signal is still active; we have more work to do. */
} while (gpio_pin_get_dt(&config->irq_gpio));
}
static int nct38xx_alert_init(const struct device *dev)
{
const struct nct38xx_alert_config *const config = dev->config;
struct nct38xx_alert_data *const data = dev->data;
int ret;
/* Check NCT38XX devices are all ready. */
for (int i = 0; i < config->nct38xx_num; i++) {
if (!device_is_ready(config->nct38xx_dev[i])) {
LOG_ERR("%s device not ready", config->nct38xx_dev[i]->name);
return -ENODEV;
}
data->mfd[i].lock = mfd_nct38xx_get_lock_reference(config->nct38xx_dev[i]);
data->mfd[i].i2c_dev = mfd_nct38xx_get_i2c_dt_spec(config->nct38xx_dev[i]);
}
/* Set the alert pin for handling the interrupt */
k_work_init(&data->alert_worker, nct38xx_alert_worker);
if (!gpio_is_ready_dt(&config->irq_gpio)) {
LOG_ERR("%s device not ready", config->irq_gpio.port->name);
return -ENODEV;
}
gpio_pin_configure_dt(&config->irq_gpio, GPIO_INPUT);
gpio_init_callback(&data->gpio_cb, nct38xx_alert_callback, BIT(config->irq_gpio.pin));
ret = gpio_add_callback(config->irq_gpio.port, &data->gpio_cb);
if (ret < 0) {
return ret;
}
gpio_pin_interrupt_configure_dt(&config->irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
return 0;
}
/* NCT38XX alert driver must be initialized after NCT38XX GPIO driver */
BUILD_ASSERT(CONFIG_GPIO_NCT38XX_ALERT_INIT_PRIORITY > CONFIG_GPIO_NCT38XX_INIT_PRIORITY);
#define NCT38XX_DEV_AND_COMMA(node_id, prop, idx) \
DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
#define NCT38XX_ALERT_DEVICE_INSTANCE(inst) \
const struct device *nct38xx_dev_##inst[] = { \
DT_INST_FOREACH_PROP_ELEM(inst, nct38xx_dev, NCT38XX_DEV_AND_COMMA)}; \
static struct nct38xx_mfd nct38xx_mfd_##inst[DT_INST_PROP_LEN(inst, nct38xx_dev)]; \
static const struct nct38xx_alert_config nct38xx_alert_cfg_##inst = { \
.irq_gpio = GPIO_DT_SPEC_INST_GET(inst, irq_gpios), \
.nct38xx_dev = &nct38xx_dev_##inst[0], \
.nct38xx_num = DT_INST_PROP_LEN(inst, nct38xx_dev), \
}; \
static struct nct38xx_alert_data nct38xx_alert_data_##inst = { \
.alert_dev = DEVICE_DT_INST_GET(inst), \
.mfd = nct38xx_mfd_##inst, \
}; \
DEVICE_DT_INST_DEFINE(inst, nct38xx_alert_init, NULL, &nct38xx_alert_data_##inst, \
&nct38xx_alert_cfg_##inst, POST_KERNEL, \
CONFIG_GPIO_NCT38XX_ALERT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(NCT38XX_ALERT_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_nct38xx_alert.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,542 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_gpio_port
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <soc.h>
#include <em_gpio.h>
#ifdef CONFIG_SOC_GECKO_DEV_INIT
#include <em_cmu.h>
#endif
#include <zephyr/drivers/gpio/gpio_utils.h>
#if CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY >= CONFIG_GPIO_INIT_PRIORITY
#error CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY must be less than \
CONFIG_GPIO_INIT_PRIORITY.
#endif
#if DT_NODE_HAS_PROP(id, peripheral_id)
#define GET_GECKO_GPIO_INDEX(id) DT_INST_PROP(id, peripheral_id)
#else
#if defined(CONFIG_SOC_SERIES_EFR32BG22) || \
defined(CONFIG_SOC_SERIES_EFR32BG27) || \
defined(CONFIG_SOC_SERIES_EFR32MG21) || \
defined(CONFIG_SOC_SERIES_EFR32MG24)
#define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_PORT_TypeDef)
#else
#define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_P_TypeDef)
#endif
/* Assumption for calculating gpio index:
* 1. Address space of the first GPIO port is the address space for GPIO port A
*/
#define GET_GECKO_GPIO_INDEX(id) (DT_INST_REG_ADDR(id) - DT_REG_ADDR(DT_NODELABEL(gpioa))) \
/ GECKO_GPIO_PORT_ADDR_SPACE_SIZE
#endif /* DT_NODE_HAS_PROP(id, peripheral_id) */
/*
* Macros to set the GPIO MODE registers
*
* See path_to_url
* pages 972 and 982.
*/
/**
* @brief Create the value to set the GPIO MODEL register
* @param[in] pin The index of the pin. Valid values are 0..7.
* @param[in] mode The mode that should be set.
* @return The value that can be set into the GPIO MODEL register.
*/
#define GECKO_GPIO_MODEL(pin, mode) (mode << (pin * 4))
/**
* @brief Create the value to set the GPIO MODEH register
* @param[in] pin The index of the pin. Valid values are 8..15.
* @param[in] mode The mode that should be set.
* @return The value that can be set into the GPIO MODEH register.
*/
#define GECKO_GPIO_MODEH(pin, mode) (mode << ((pin - 8) * 4))
#define NUMBER_OF_PORTS (SIZEOF_FIELD(GPIO_TypeDef, P) / \
SIZEOF_FIELD(GPIO_TypeDef, P[0]))
struct gpio_gecko_common_config {
};
struct gpio_gecko_common_data {
/* a list of all ports */
const struct device *ports[NUMBER_OF_PORTS];
size_t count;
};
struct gpio_gecko_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Port_TypeDef gpio_index;
};
struct gpio_gecko_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
/* mask of pins on which interrupt is enabled */
uint32_t int_enabled_mask;
};
static inline void gpio_gecko_add_port(struct gpio_gecko_common_data *data,
const struct device *dev)
{
__ASSERT(dev, "No port device!");
data->ports[data->count++] = dev;
}
static int gpio_gecko_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_Mode_TypeDef mode;
unsigned int out = 0U;
if (flags & GPIO_OUTPUT) {
/* Following modes enable both output and input */
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
mode = gpioModeWiredAnd;
} else {
mode = gpioModeWiredOr;
}
} else {
mode = gpioModePushPull;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
out = 1U;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
out = 0U;
} else {
out = GPIO_PinOutGet(gpio_index, pin);
}
} else if (flags & GPIO_INPUT) {
if (flags & GPIO_PULL_UP) {
mode = gpioModeInputPull;
out = 1U; /* pull-up*/
} else if (flags & GPIO_PULL_DOWN) {
mode = gpioModeInputPull;
/* out = 0 means pull-down*/
} else {
mode = gpioModeInput;
}
} else {
/* Neither input nor output mode is selected */
mode = gpioModeDisabled;
}
/* The flags contain options that require touching registers in the
* GPIO module and the corresponding PORT module.
*
* Start with the GPIO module and set up the pin direction register.
* 0 - pin is input, 1 - pin is output
*/
GPIO_PinModeSet(gpio_index, pin, mode, out);
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_gecko_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_Mode_TypeDef mode;
unsigned int out;
gpio_flags_t flags = 0;
mode = GPIO_PinModeGet(gpio_index, pin);
out = GPIO_PinOutGet(gpio_index, pin);
switch (mode) {
case gpioModeWiredAnd:
flags = GPIO_OUTPUT | GPIO_OPEN_DRAIN;
if (out) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
break;
case gpioModeWiredOr:
flags = GPIO_OUTPUT | GPIO_OPEN_SOURCE;
if (out) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
break;
case gpioModePushPull:
flags = GPIO_OUTPUT | GPIO_PUSH_PULL;
if (out) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
break;
case gpioModeInputPull:
flags = GPIO_INPUT;
if (out) {
flags |= GPIO_PULL_UP;
} else {
flags |= GPIO_PULL_DOWN;
}
break;
case gpioModeInput:
flags = GPIO_INPUT;
break;
case gpioModeDisabled:
flags = GPIO_DISCONNECTED;
break;
default:
break;
}
*out_flags = flags;
return 0;
}
#endif
static int gpio_gecko_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
*value = GPIO_PortInGet(gpio_index);
return 0;
}
static int gpio_gecko_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_PortOutSetVal(gpio_index, value, mask);
return 0;
}
static int gpio_gecko_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_PortOutSet(gpio_index, mask);
return 0;
}
static int gpio_gecko_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_PortOutClear(gpio_index, mask);
return 0;
}
static int gpio_gecko_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_gecko_config *config = dev->config;
GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_PortOutToggle(gpio_index, mask);
return 0;
}
static int gpio_gecko_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_gecko_config *config = dev->config;
struct gpio_gecko_data *data = dev->data;
/* Interrupt on static level is not supported by the hardware */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_DISABLED) {
GPIO_IntDisable(BIT(pin));
} else {
/* Interrupt line is already in use */
if ((GPIO->IEN & BIT(pin)) != 0) {
/* TODO: Return an error only if request is done for
* a pin from a different port.
*/
return -EBUSY;
}
bool rising_edge = true;
bool falling_edge = true;
if (trig == GPIO_INT_TRIG_LOW) {
rising_edge = false;
falling_edge = true;
} else if (trig == GPIO_INT_TRIG_HIGH) {
rising_edge = true;
falling_edge = false;
} /* default is GPIO_INT_TRIG_BOTH */
GPIO_ExtIntConfig(config->gpio_index, pin, pin,
rising_edge, falling_edge, true);
}
WRITE_BIT(data->int_enabled_mask, pin, mode != GPIO_INT_DISABLE);
return 0;
}
static int gpio_gecko_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_gecko_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
/**
* Handler for both odd and even pin interrupts
*/
static void gpio_gecko_common_isr(const struct device *dev)
{
struct gpio_gecko_common_data *data = dev->data;
uint32_t enabled_int, int_status;
const struct device *port_dev;
struct gpio_gecko_data *port_data;
int_status = GPIO->IF;
for (unsigned int i = 0; int_status && (i < data->count); i++) {
port_dev = data->ports[i];
port_data = port_dev->data;
enabled_int = int_status & port_data->int_enabled_mask;
if (enabled_int != 0) {
int_status &= ~enabled_int;
#if defined(_SILICON_LABS_32B_SERIES_2)
GPIO->IF_CLR = enabled_int;
#else
GPIO->IFC = enabled_int;
#endif
gpio_fire_callbacks(&port_data->callbacks, port_dev,
enabled_int);
}
}
}
static const struct gpio_driver_api gpio_gecko_driver_api = {
.pin_configure = gpio_gecko_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_gecko_get_config,
#endif
.port_get_raw = gpio_gecko_port_get_raw,
.port_set_masked_raw = gpio_gecko_port_set_masked_raw,
.port_set_bits_raw = gpio_gecko_port_set_bits_raw,
.port_clear_bits_raw = gpio_gecko_port_clear_bits_raw,
.port_toggle_bits = gpio_gecko_port_toggle_bits,
.pin_interrupt_configure = gpio_gecko_pin_interrupt_configure,
.manage_callback = gpio_gecko_manage_callback,
};
static const struct gpio_driver_api gpio_gecko_common_driver_api = {
.manage_callback = gpio_gecko_manage_callback,
};
static int gpio_gecko_common_init(const struct device *dev);
static const struct gpio_gecko_common_config gpio_gecko_common_config = {
};
static struct gpio_gecko_common_data gpio_gecko_common_data;
DEVICE_DT_DEFINE(DT_INST(0, silabs_gecko_gpio),
gpio_gecko_common_init,
NULL,
&gpio_gecko_common_data, &gpio_gecko_common_config,
PRE_KERNEL_1, CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY,
&gpio_gecko_common_driver_api);
static int gpio_gecko_common_init(const struct device *dev)
{
#ifdef CONFIG_SOC_GECKO_DEV_INIT
CMU_ClockEnable(cmuClock_GPIO, true);
#endif
gpio_gecko_common_data.count = 0;
IRQ_CONNECT(GPIO_EVEN_IRQn,
DT_IRQ_BY_NAME(DT_INST(0, silabs_gecko_gpio), gpio_even, priority),
gpio_gecko_common_isr,
DEVICE_DT_GET(DT_INST(0, silabs_gecko_gpio)), 0);
IRQ_CONNECT(GPIO_ODD_IRQn,
DT_IRQ_BY_NAME(DT_INST(0, silabs_gecko_gpio), gpio_odd, priority),
gpio_gecko_common_isr,
DEVICE_DT_GET(DT_INST(0, silabs_gecko_gpio)), 0);
irq_enable(GPIO_EVEN_IRQn);
irq_enable(GPIO_ODD_IRQn);
return 0;
}
#define GPIO_PORT_INIT(idx) \
static int gpio_gecko_port##idx##_init(const struct device *dev); \
\
static const struct gpio_gecko_config gpio_gecko_port##idx##_config = { \
.common = { \
.port_pin_mask = (gpio_port_pins_t)(-1), \
}, \
.gpio_index = GET_GECKO_GPIO_INDEX(idx), \
}; \
\
static struct gpio_gecko_data gpio_gecko_port##idx##_data; \
\
DEVICE_DT_INST_DEFINE(idx, \
gpio_gecko_port##idx##_init, \
NULL, \
&gpio_gecko_port##idx##_data, \
&gpio_gecko_port##idx##_config, \
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_gecko_driver_api); \
\
static int gpio_gecko_port##idx##_init(const struct device *dev) \
{ \
gpio_gecko_add_port(&gpio_gecko_common_data, dev); \
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,983 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_common.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_mcux_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Type *gpio_base;
PORT_Type *port_base;
unsigned int flags;
};
struct gpio_mcux_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static int gpio_mcux_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
uint32_t mask = 0U;
uint32_t pcr = 0U;
/* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) {
return -EINVAL;
}
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* The flags contain options that require touching registers in the
* GPIO module and the corresponding PORT module.
*
* Start with the GPIO module and set up the pin direction register.
* 0 - pin is input, 1 - pin is output
*/
switch (flags & GPIO_DIR_MASK) {
case GPIO_INPUT:
gpio_base->PDDR &= ~BIT(pin);
break;
case GPIO_OUTPUT:
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_base->PSOR = BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_base->PCOR = BIT(pin);
}
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
}
/* Set PCR mux to GPIO for the pin we are configuring */
mask |= PORT_PCR_MUX_MASK;
pcr |= PORT_PCR_MUX(PORT_MUX_GPIO);
#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
/* Enable digital input buffer */
pcr |= PORT_PCR_IBE_MASK;
#endif
/* Now do the PORT module. Figure out the pullup/pulldown
* configuration, but don't write it to the PCR register yet.
*/
mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
if ((flags & GPIO_PULL_UP) != 0) {
/* Enable the pull and select the pullup resistor. */
pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
/* Enable the pull and select the pulldown resistor, deselect
* the pullup resistor.
*/
pcr |= PORT_PCR_PE_MASK;
}
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
/* Determine the drive strength */
switch (flags & KINETIS_GPIO_DS_MASK) {
case KINETIS_GPIO_DS_DFLT:
/* Default is low drive strength */
mask |= PORT_PCR_DSE_MASK;
break;
case KINETIS_GPIO_DS_ALT:
/* Alternate is high drive strength */
pcr |= PORT_PCR_DSE_MASK;
break;
default:
return -ENOTSUP;
}
#endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
/* Accessing by pin, we only need to write one PCR register. */
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
return 0;
}
static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
*value = gpio_base->PDIR;
return 0;
}
static int gpio_mcux_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value);
return 0;
}
static int gpio_mcux_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PSOR = mask;
return 0;
}
static int gpio_mcux_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PCOR = mask;
return 0;
}
static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->PTOR = mask;
return 0;
}
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
uint32_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
port_interrupt_t port_interrupt = 0;
if (mode == GPIO_INT_MODE_DISABLED) {
port_interrupt = kPORT_InterruptOrDMADisabled;
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig == GPIO_INT_TRIG_LOW) {
port_interrupt = kPORT_InterruptLogicZero;
} else {
port_interrupt = kPORT_InterruptLogicOne;
}
} else {
switch (trig) {
case GPIO_INT_TRIG_LOW:
port_interrupt = kPORT_InterruptFallingEdge;
break;
case GPIO_INT_TRIG_HIGH:
port_interrupt = kPORT_InterruptRisingEdge;
break;
case GPIO_INT_TRIG_BOTH:
port_interrupt = kPORT_InterruptEitherEdge;
break;
default:
return -EINVAL;
}
}
}
return PORT_PCR_IRQC(port_interrupt);
}
#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
#define GPIO_MCUX_INTERRUPT_DISABLED 0
#define GPIO_MCUX_INTERRUPT_LOGIC_0 0x8
#define GPIO_MCUX_INTERRUPT_RISING_EDGE 0x9
#define GPIO_MCUX_INTERRUPT_FALLING_EDGE 0xA
#define GPIO_MCUX_INTERRUPT_BOTH_EDGE 0xB
#define GPIO_MCUX_INTERRUPT_LOGIC_1 0xC
static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev,
uint32_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
uint8_t gpio_interrupt = 0;
if (mode == GPIO_INT_MODE_DISABLED) {
gpio_interrupt = GPIO_MCUX_INTERRUPT_DISABLED;
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
if (trig == GPIO_INT_TRIG_LOW) {
gpio_interrupt = GPIO_MCUX_INTERRUPT_LOGIC_0;
} else {
gpio_interrupt = GPIO_MCUX_INTERRUPT_LOGIC_1;
}
} else {
switch (trig) {
case GPIO_INT_TRIG_LOW:
gpio_interrupt = GPIO_MCUX_INTERRUPT_FALLING_EDGE;
break;
case GPIO_INT_TRIG_HIGH:
gpio_interrupt = GPIO_MCUX_INTERRUPT_RISING_EDGE;
break;
case GPIO_INT_TRIG_BOTH:
gpio_interrupt = GPIO_MCUX_INTERRUPT_BOTH_EDGE;
break;
default:
return -EINVAL;
}
}
}
return GPIO_ICR_IRQC(gpio_interrupt);
}
#endif /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */
static int gpio_mcux_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin, enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base;
/* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) {
return -EINVAL;
}
/* Check for an invalid pin configuration */
if ((mode != GPIO_INT_MODE_DISABLED) &&
((gpio_base->PDDR & BIT(pin)) != 0)) {
return -EINVAL;
}
/* Check if GPIO port supports interrupts */
if ((mode != GPIO_INT_MODE_DISABLED) &&
((config->flags & GPIO_INT_ENABLE) == 0U)) {
return -ENOTSUP;
}
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig);
gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr;
#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
return 0;
}
static int gpio_mcux_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_mcux_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void gpio_mcux_port_isr(const struct device *dev)
{
const struct gpio_mcux_config *config = dev->config;
struct gpio_mcux_data *data = dev->data;
uint32_t int_status;
#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
int_status = config->port_base->ISFR;
/* Clear the port interrupts */
config->port_base->ISFR = int_status;
#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
int_status = config->gpio_base->ISFR[0];
/* Clear the gpio interrupts */
config->gpio_base->ISFR[0] = int_status;
#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
gpio_fire_callbacks(&data->callbacks, dev, int_status);
}
#define GPIO_HAS_SHARED_IRQ DT_HAS_COMPAT_STATUS_OKAY(nxp_gpio_cluster)
#if GPIO_HAS_SHARED_IRQ
static void gpio_mcux_shared_cluster_isr(const struct device *ports[])
{
const struct device **current_port = &ports[0];
while (*current_port != NULL) {
gpio_mcux_port_isr(*current_port);
current_port++;
}
}
#define CLUSTER_ARRAY_ELEMENT(node_id) DEVICE_DT_GET(node_id),
#define GPIO_MCUX_CLUSTER_INIT(node_id) \
const struct device *shared_array##node_id[DT_CHILD_NUM_STATUS_OKAY(node_id) + 1] = \
{DT_FOREACH_CHILD_STATUS_OKAY(node_id, CLUSTER_ARRAY_ELEMENT) NULL}; \
\
static int gpio_mcux_shared_interrupt_init##node_id(void) \
{ \
IRQ_CONNECT(DT_IRQN(node_id), \
DT_IRQ(node_id, priority), \
gpio_mcux_shared_cluster_isr, \
shared_array##node_id, 0); \
irq_enable(DT_IRQN(node_id)); \
\
return 0; \
} \
SYS_INIT(gpio_mcux_shared_interrupt_init##node_id, POST_KERNEL, 0);
DT_FOREACH_STATUS_OKAY(nxp_gpio_cluster, GPIO_MCUX_CLUSTER_INIT)
#endif
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_mcux_port_get_direction(const struct device *dev, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
const struct gpio_mcux_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
map &= config->common.port_pin_mask;
if (inputs != NULL) {
*inputs = map & (~gpio_base->PDDR);
}
if (outputs != NULL) {
*outputs = map & gpio_base->PDDR;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_mcux_driver_api = {
.pin_configure = gpio_mcux_configure,
.port_get_raw = gpio_mcux_port_get_raw,
.port_set_masked_raw = gpio_mcux_port_set_masked_raw,
.port_set_bits_raw = gpio_mcux_port_set_bits_raw,
.port_clear_bits_raw = gpio_mcux_port_clear_bits_raw,
.port_toggle_bits = gpio_mcux_port_toggle_bits,
.pin_interrupt_configure = gpio_mcux_pin_interrupt_configure,
.manage_callback = gpio_mcux_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_mcux_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
#define GPIO_MCUX_IRQ_INIT(n) \
do { \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_mcux_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
} while (false)
#define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
#define GPIO_DEVICE_INIT_MCUX(n) \
static int gpio_mcux_port## n ## _init(const struct device *dev); \
\
static const struct gpio_mcux_config gpio_mcux_port## n ## _config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \
.port_base = (PORT_Type *) GPIO_PORT_BASE_ADDR(n), \
.flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0), \
GPIO_HAS_SHARED_IRQ), GPIO_INT_ENABLE), \
}; \
\
static struct gpio_mcux_data gpio_mcux_port## n ##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_mcux_port## n ##_init, \
NULL, \
&gpio_mcux_port## n ##_data, \
&gpio_mcux_port## n##_config, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_mcux_driver_api); \
\
static int gpio_mcux_port## n ##_init(const struct device *dev) \
{ \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
(GPIO_MCUX_IRQ_INIT(n);)) \
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_MCUX)
``` | /content/code_sandbox/drivers/gpio/gpio_mcux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,441 |
```c
*
*/
#define DT_DRV_COMPAT intel_sedi_gpio
#include "sedi_driver_gpio.h"
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/pm/device.h>
struct gpio_sedi_config {
/* gpio_driver_data needs to be first */
struct gpio_driver_config common;
sedi_gpio_t device;
uint32_t pin_nums;
void (*irq_config)(void);
DEVICE_MMIO_ROM;
};
struct gpio_sedi_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_config common;
sys_slist_t callbacks;
DEVICE_MMIO_RAM;
};
static int gpio_sedi_init(const struct device *dev);
#ifdef CONFIG_PM_DEVICE
static int gpio_sedi_suspend_device(const struct device *dev)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
int ret;
if (pm_device_is_busy(dev)) {
return -EBUSY;
}
ret = sedi_gpio_set_power(gpio_dev, SEDI_POWER_SUSPEND);
if (ret != SEDI_DRIVER_OK) {
return -EIO;
}
return 0;
}
static int gpio_sedi_resume_device_from_suspend(const struct device *dev)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
int ret;
ret = sedi_gpio_set_power(gpio_dev, SEDI_POWER_FULL);
if (ret != SEDI_DRIVER_OK) {
return -EIO;
}
return 0;
}
static int gpio_sedi_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
ret = gpio_sedi_suspend_device(dev);
break;
case PM_DEVICE_ACTION_RESUME:
ret = gpio_sedi_resume_device_from_suspend(dev);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static void gpio_sedi_callback(const uint32_t pin_mask,
const sedi_gpio_port_t port,
void *param)
{
ARG_UNUSED(port);
struct device *dev = (struct device *)param;
struct gpio_sedi_data *data =
(struct gpio_sedi_data *)(dev->data);
/* call the callbacks */
gpio_fire_callbacks(&data->callbacks, dev, pin_mask);
}
static void gpio_sedi_write_raw(const struct device *dev,
uint32_t pins,
bool is_clear)
{
uint8_t i;
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
sedi_gpio_pin_state_t val;
if (is_clear) {
val = SEDI_GPIO_STATE_LOW;
} else {
val = SEDI_GPIO_STATE_HIGH;
}
for (i = 0; i < config->pin_nums; i++) {
if (pins & 0x1) {
sedi_gpio_write_pin(gpio_dev, i, val);
}
pins >>= 1;
if (pins == 0) {
break;
}
}
}
static int gpio_sedi_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
sedi_gpio_pin_config_t pin_config = { 0 };
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
/* Pin cannot be configured as input and output */
return -ENOTSUP;
} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
/* Pin has to be configured as input or output */
return -ENOTSUP;
}
pin_config.enable_interrupt = false;
/* Map direction */
if (flags & GPIO_OUTPUT) {
pin_config.direction = SEDI_GPIO_DIR_MODE_OUTPUT;
sedi_gpio_config_pin(gpio_dev, pin, pin_config);
/* Set start state */
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
sedi_gpio_write_pin(gpio_dev, pin, 1);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
sedi_gpio_write_pin(gpio_dev, pin, 0);
}
} else {
pin_config.direction = SEDI_GPIO_DIR_MODE_INPUT;
sedi_gpio_config_pin(gpio_dev, pin, pin_config);
}
return 0;
}
static int gpio_sedi_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
*value = sedi_gpio_read_pin_32bits(gpio_dev, 0);
return 0;
}
static int gpio_sedi_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
gpio_sedi_write_raw(dev, (mask & value), false);
return 0;
}
static int gpio_sedi_set_bits_raw(const struct device *dev, uint32_t pins)
{
gpio_sedi_write_raw(dev, pins, false);
return 0;
}
static int gpio_sedi_clear_bits_raw(const struct device *dev, uint32_t pins)
{
gpio_sedi_write_raw(dev, pins, true);
return 0;
}
static int gpio_sedi_toggle_bits(const struct device *dev, uint32_t pins)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
uint8_t i;
for (i = 0; i < config->pin_nums; i++) {
if (pins & 0x1) {
sedi_gpio_toggle_pin(gpio_dev, i);
}
pins >>= 1;
if (pins == 0) {
break;
}
}
return 0;
}
static int gpio_sedi_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
sedi_gpio_pin_config_t pin_config = { 0 };
/* Not support level trigger */
if (mode == GPIO_INT_MODE_LEVEL) {
return -EINVAL;
}
/* Only input needs interrupt enabled */
pin_config.direction = SEDI_GPIO_DIR_MODE_INPUT;
pin_config.enable_wakeup = true;
if (mode == GPIO_INT_MODE_DISABLED) {
pin_config.enable_interrupt = false;
} else {
pin_config.enable_interrupt = true;
switch (trig) {
case GPIO_INT_TRIG_LOW:
pin_config.interrupt_mode =
SEDI_GPIO_INT_MODE_FALLING_EDGE;
break;
case GPIO_INT_TRIG_HIGH:
pin_config.interrupt_mode =
SEDI_GPIO_INT_MODE_RISING_EDGE;
break;
case GPIO_INT_TRIG_BOTH:
pin_config.interrupt_mode =
SEDI_GPIO_INT_MODE_BOTH_EDGE;
break;
default:
return -EINVAL;
}
}
/* Configure interrupt mode */
sedi_gpio_config_pin(gpio_dev, pin, pin_config);
return 0;
}
static int gpio_sedi_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_sedi_data *data = dev->data;
gpio_manage_callback(&(data->callbacks), callback, set);
return 0;
}
static uint32_t gpio_sedi_get_pending(const struct device *dev)
{
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
return sedi_gpio_get_gisr(gpio_dev, 0);
}
static const struct gpio_driver_api gpio_sedi_driver_api = {
.pin_configure = gpio_sedi_configure,
.port_get_raw = gpio_sedi_get_raw,
.port_set_masked_raw = gpio_sedi_set_masked_raw,
.port_set_bits_raw = gpio_sedi_set_bits_raw,
.port_clear_bits_raw = gpio_sedi_clear_bits_raw,
.port_toggle_bits = gpio_sedi_toggle_bits,
.pin_interrupt_configure = gpio_sedi_interrupt_configure,
.manage_callback = gpio_sedi_manage_callback,
.get_pending_int = gpio_sedi_get_pending
};
extern void gpio_isr(IN sedi_gpio_t gpio_device);
static int gpio_sedi_init(const struct device *dev)
{
int ret;
const struct gpio_sedi_config *config = dev->config;
sedi_gpio_t gpio_dev = config->device;
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
/* Call sedi gpio init */
ret = sedi_gpio_init(gpio_dev, gpio_sedi_callback, (void *)dev);
if (ret != 0) {
return ret;
}
sedi_gpio_set_power(gpio_dev, SEDI_POWER_FULL);
config->irq_config();
return 0;
}
#define GPIO_SEDI_IRQ_FLAGS_SENSE0(n) 0
#define GPIO_SEDI_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
#define GPIO_SEDI_IRQ_FLAGS(n) \
_CONCAT(GPIO_SEDI_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))(n)
#define GPIO_DEVICE_INIT_SEDI(n) \
static struct gpio_sedi_data gpio##n##_data; \
static void gpio_sedi_irq_config_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
gpio_isr, n, \
GPIO_SEDI_IRQ_FLAGS(n)); \
irq_enable(DT_INST_IRQN(n)); \
}; \
static const struct gpio_sedi_config gpio##n##_config = { \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
.common = { 0xFFFFFFFF }, \
.device = DT_INST_PROP(n, peripheral_id), \
.pin_nums = DT_INST_PROP(n, ngpios), \
.irq_config = gpio_sedi_irq_config_##n, \
}; \
PM_DEVICE_DEFINE(gpio_##n, gpio_sedi_pm_action); \
DEVICE_DT_INST_DEFINE(n, \
gpio_sedi_init, \
PM_DEVICE_GET(gpio_##n), \
&gpio##n##_data, \
&gpio##n##_config, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_sedi_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_SEDI)
``` | /content/code_sandbox/drivers/gpio/gpio_sedi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,282 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_exti.h>
#include <stm32_ll_gpio.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_system.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/interrupt_controller/exti_stm32.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
#include <zephyr/dt-bindings/gpio/stm32-gpio.h>
#include "stm32_hsem.h"
#include "gpio_stm32.h"
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(stm32, CONFIG_GPIO_LOG_LEVEL);
/**
* @brief Common GPIO driver for STM32 MCUs.
*/
/**
* @brief EXTI interrupt callback
*/
static void gpio_stm32_isr(int line, void *arg)
{
struct gpio_stm32_data *data = arg;
gpio_fire_callbacks(&data->cb, data->dev, BIT(line));
}
/**
* @brief Common gpio flags to custom flags
*/
static int gpio_stm32_flags_to_conf(gpio_flags_t flags, int *pincfg)
{
if ((flags & GPIO_OUTPUT) != 0) {
/* Output only or Output/Input */
*pincfg = STM32_PINCFG_MODE_OUTPUT;
if ((flags & GPIO_SINGLE_ENDED) != 0) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
*pincfg |= STM32_PINCFG_OPEN_DRAIN;
} else {
/* Output can't be open source */
return -ENOTSUP;
}
} else {
*pincfg |= STM32_PINCFG_PUSH_PULL;
}
if ((flags & GPIO_PULL_UP) != 0) {
*pincfg |= STM32_PINCFG_PULL_UP;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
*pincfg |= STM32_PINCFG_PULL_DOWN;
}
} else if ((flags & GPIO_INPUT) != 0) {
/* Input */
*pincfg = STM32_PINCFG_MODE_INPUT;
if ((flags & GPIO_PULL_UP) != 0) {
*pincfg |= STM32_PINCFG_PULL_UP;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
*pincfg |= STM32_PINCFG_PULL_DOWN;
} else {
*pincfg |= STM32_PINCFG_FLOATING;
}
} else {
/* Deactivated: Analog */
*pincfg = STM32_PINCFG_MODE_ANALOG;
}
return 0;
}
#if defined(CONFIG_GPIO_GET_CONFIG) && !defined(CONFIG_SOC_SERIES_STM32F1X)
/**
* @brief Custom stm32 flags to zephyr
*/
static int gpio_stm32_pincfg_to_flags(struct gpio_stm32_pin pin_cfg,
gpio_flags_t *out_flags)
{
gpio_flags_t flags = 0;
if (pin_cfg.mode == LL_GPIO_MODE_OUTPUT) {
flags |= GPIO_OUTPUT;
if (pin_cfg.type == LL_GPIO_OUTPUT_OPENDRAIN) {
flags |= GPIO_OPEN_DRAIN;
}
} else if (pin_cfg.mode == LL_GPIO_MODE_INPUT) {
flags |= GPIO_INPUT;
#ifdef CONFIG_SOC_SERIES_STM32F1X
} else if (pin_cfg.mode == LL_GPIO_MODE_FLOATING) {
flags |= GPIO_INPUT;
#endif
} else {
flags |= GPIO_DISCONNECTED;
}
if (pin_cfg.pupd == LL_GPIO_PULL_UP) {
flags |= GPIO_PULL_UP;
} else if (pin_cfg.pupd == LL_GPIO_PULL_DOWN) {
flags |= GPIO_PULL_DOWN;
}
if (pin_cfg.out_state != 0) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
*out_flags = flags;
return 0;
}
#endif /* CONFIG_GPIO_GET_CONFIG */
/**
* @brief Translate pin to pinval that the LL library needs
*/
static inline uint32_t stm32_pinval_get(int pin)
{
uint32_t pinval;
#ifdef CONFIG_SOC_SERIES_STM32F1X
pinval = (1 << pin) << GPIO_PIN_MASK_POS;
if (pin < 8) {
pinval |= 1 << pin;
} else {
pinval |= (1 << (pin % 8)) | 0x04000000;
}
#else
pinval = 1 << pin;
#endif
return pinval;
}
/**
* @brief Configure the hardware.
*/
static void gpio_stm32_configure_raw(const struct device *dev, int pin,
int conf, int func)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
int pin_ll = stm32_pinval_get(pin);
#ifdef CONFIG_SOC_SERIES_STM32F1X
ARG_UNUSED(func);
uint32_t temp = conf &
(STM32_MODE_INOUT_MASK << STM32_MODE_INOUT_SHIFT);
if (temp == STM32_MODE_INPUT) {
temp = conf & (STM32_CNF_IN_MASK << STM32_CNF_IN_SHIFT);
if (temp == STM32_CNF_IN_ANALOG) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ANALOG);
} else if (temp == STM32_CNF_IN_FLOAT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_FLOATING);
} else {
temp = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
if (temp == STM32_PUPD_PULL_UP) {
LL_GPIO_SetPinPull(gpio, pin_ll,
LL_GPIO_PULL_UP);
} else {
LL_GPIO_SetPinPull(gpio, pin_ll,
LL_GPIO_PULL_DOWN);
}
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_INPUT);
}
} else {
temp = conf & (STM32_CNF_OUT_1_MASK << STM32_CNF_OUT_1_SHIFT);
if (temp == STM32_CNF_GP_OUTPUT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_OUTPUT);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll,
LL_GPIO_MODE_ALTERNATE);
}
temp = conf & (STM32_CNF_OUT_0_MASK << STM32_CNF_OUT_0_SHIFT);
if (temp == STM32_CNF_PUSH_PULL) {
LL_GPIO_SetPinOutputType(gpio, pin_ll,
LL_GPIO_OUTPUT_PUSHPULL);
} else {
LL_GPIO_SetPinOutputType(gpio, pin_ll,
LL_GPIO_OUTPUT_OPENDRAIN);
}
temp = conf &
(STM32_MODE_OSPEED_MASK << STM32_MODE_OSPEED_SHIFT);
if (temp == STM32_MODE_OUTPUT_MAX_2) {
LL_GPIO_SetPinSpeed(gpio, pin_ll,
LL_GPIO_SPEED_FREQ_LOW);
} else if (temp == STM32_MODE_OUTPUT_MAX_10) {
LL_GPIO_SetPinSpeed(gpio, pin_ll,
LL_GPIO_SPEED_FREQ_MEDIUM);
} else {
LL_GPIO_SetPinSpeed(gpio, pin_ll,
LL_GPIO_SPEED_FREQ_HIGH);
}
}
#else
unsigned int mode, otype, ospeed, pupd;
mode = conf & (STM32_MODER_MASK << STM32_MODER_SHIFT);
otype = conf & (STM32_OTYPER_MASK << STM32_OTYPER_SHIFT);
ospeed = conf & (STM32_OSPEEDR_MASK << STM32_OSPEEDR_SHIFT);
pupd = conf & (STM32_PUPDR_MASK << STM32_PUPDR_SHIFT);
z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY);
#if defined(CONFIG_SOC_SERIES_STM32L4X) && defined(GPIO_ASCR_ASC0)
/*
* For STM32L47xx/48xx, register ASCR should be configured to connect
* analog switch of gpio lines to the ADC.
*/
if (mode == STM32_MODER_ANALOG_MODE) {
LL_GPIO_EnablePinAnalogControl(gpio, pin_ll);
}
#endif
LL_GPIO_SetPinOutputType(gpio, pin_ll, otype >> STM32_OTYPER_SHIFT);
LL_GPIO_SetPinSpeed(gpio, pin_ll, ospeed >> STM32_OSPEEDR_SHIFT);
LL_GPIO_SetPinPull(gpio, pin_ll, pupd >> STM32_PUPDR_SHIFT);
if (mode == STM32_MODER_ALT_MODE) {
if (pin < 8) {
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, func);
} else {
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, func);
}
}
LL_GPIO_SetPinMode(gpio, pin_ll, mode >> STM32_MODER_SHIFT);
z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID);
#endif /* CONFIG_SOC_SERIES_STM32F1X */
}
/**
* @brief GPIO port clock handling
*/
static int gpio_stm32_clock_request(const struct device *dev, bool on)
{
const struct gpio_stm32_config *cfg = dev->config;
int ret;
__ASSERT_NO_MSG(dev != NULL);
/* enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (on) {
ret = clock_control_on(clk,
(clock_control_subsys_t)&cfg->pclken);
} else {
ret = clock_control_off(clk,
(clock_control_subsys_t)&cfg->pclken);
}
return ret;
}
static inline uint32_t gpio_stm32_pin_to_exti_line(int pin)
{
#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32F0X)
return ((pin % 4 * 4) << 16) | (pin / 4);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
return ((pin & 0x3) << (16 + 3)) | (pin >> 2);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
/* Gives the LL_SBS_EXTI_LINEn corresponding to the pin */
return (((pin % 4 * 4) << LL_SBS_REGISTER_PINPOS_SHFT) | (pin / 4));
#else
return (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
#endif
}
/* Set the EXTI line corresponding to the PORT [STM32_PORTA .. ] and pin [0..15] */
static void gpio_stm32_set_exti_source(int port, int pin)
{
uint32_t line = gpio_stm32_pin_to_exti_line(pin);
#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
/*
* Ports F and G are not present on some STM32L0 parts, so
* for these parts port H external interrupt should be enabled
* by writing value 0x5 instead of 0x7.
*/
if (port == STM32_PORTH) {
port = LL_SYSCFG_EXTI_PORTH;
}
#endif
z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
#ifdef CONFIG_SOC_SERIES_STM32F1X
LL_GPIO_AF_SetEXTISource(port, line);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
LL_EXTI_SetEXTISource(port, line);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
LL_SBS_SetEXTISource(port, line);
#else
LL_SYSCFG_SetEXTISource(port, line);
#endif
z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
}
/* Gives the PORT [STM32_PORTA .. ] corresponding to the EXTI line of the pin [0..15] */
static int gpio_stm32_get_exti_source(int pin)
{
uint32_t line = gpio_stm32_pin_to_exti_line(pin);
int port;
#ifdef CONFIG_SOC_SERIES_STM32F1X
port = LL_GPIO_AF_GetEXTISource(line);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
port = LL_EXTI_GetEXTISource(line);
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
port = LL_SBS_GetEXTISource(line);
#else
port = LL_SYSCFG_GetEXTISource(line);
#endif
#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
/*
* Ports F and G are not present on some STM32L0 parts, so
* for these parts port H external interrupt is enabled
* by writing value 0x5 instead of 0x7.
*/
if (port == LL_SYSCFG_EXTI_PORTH) {
port = STM32_PORTH;
}
#endif
return port;
}
/**
* @brief Enable EXTI of the specific line
*/
static int gpio_stm32_enable_int(int port, int pin)
{
#if defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
defined(CONFIG_SOC_SERIES_STM32L1X) || \
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
struct stm32_pclken pclken = {
#if defined(CONFIG_SOC_SERIES_STM32H7X)
.bus = STM32_CLOCK_BUS_APB4,
.enr = LL_APB4_GRP1_PERIPH_SYSCFG
#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
.bus = STM32_CLOCK_BUS_APB4,
.enr = LL_APB4_GRP1_PERIPH_SBS
#else
.bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_SYSCFG
#endif /* CONFIG_SOC_SERIES_STM32H7X */
};
int ret;
/* Enable SYSCFG clock */
ret = clock_control_on(clk, (clock_control_subsys_t) &pclken);
if (ret != 0) {
return ret;
}
#endif
gpio_stm32_set_exti_source(port, pin);
return 0;
}
static int gpio_stm32_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
*value = LL_GPIO_ReadInputPort(gpio);
return 0;
}
static int gpio_stm32_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
uint32_t port_value;
z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY);
port_value = LL_GPIO_ReadOutputPort(gpio);
LL_GPIO_WriteOutputPort(gpio, (port_value & ~mask) | (mask & value));
z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID);
return 0;
}
static int gpio_stm32_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
/*
* On F1 series, using LL API requires a costly pin mask translation.
* Skip it and use CMSIS API directly. Valid also on other series.
*/
WRITE_REG(gpio->BSRR, pins);
return 0;
}
static int gpio_stm32_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
#ifdef CONFIG_SOC_SERIES_STM32F1X
/*
* On F1 series, using LL API requires a costly pin mask translation.
* Skip it and use CMSIS API directly.
*/
WRITE_REG(gpio->BRR, pins);
#else
/* On other series, LL abstraction is needed */
LL_GPIO_ResetOutputPin(gpio, pins);
#endif
return 0;
}
static int gpio_stm32_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
/*
* On F1 series, using LL API requires a costly pin mask translation.
* Skip it and use CMSIS API directly. Valid also on other series.
*/
z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY);
WRITE_REG(gpio->ODR, READ_REG(gpio->ODR) ^ pins);
z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID);
return 0;
}
#ifdef CONFIG_SOC_SERIES_STM32F1X
#define IS_GPIO_OUT GPIO_OUT
#else
#define IS_GPIO_OUT STM32_GPIO
#endif
int gpio_stm32_configure(const struct device *dev, int pin, int conf, int func)
{
int ret;
ret = pm_device_runtime_get(dev);
if (ret < 0) {
return ret;
}
gpio_stm32_configure_raw(dev, pin, conf, func);
if (func == IS_GPIO_OUT) {
uint32_t gpio_out = conf & (STM32_ODR_MASK << STM32_ODR_SHIFT);
if (gpio_out == STM32_ODR_1) {
gpio_stm32_port_set_bits_raw(dev, BIT(pin));
} else if (gpio_out == STM32_ODR_0) {
gpio_stm32_port_clear_bits_raw(dev, BIT(pin));
}
}
return pm_device_runtime_put(dev);
}
/**
* @brief Configure pin or port
*/
static int gpio_stm32_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
int err;
int pincfg;
/* figure out if we can map the requested GPIO
* configuration
*/
err = gpio_stm32_flags_to_conf(flags, &pincfg);
if (err != 0) {
return err;
}
/* Enable device clock before configuration (requires bank writes) */
if (((flags & GPIO_OUTPUT) != 0) || ((flags & GPIO_INPUT) != 0)) {
err = pm_device_runtime_get(dev);
if (err < 0) {
return err;
}
}
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_stm32_port_set_bits_raw(dev, BIT(pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_stm32_port_clear_bits_raw(dev, BIT(pin));
}
}
gpio_stm32_configure_raw(dev, pin, pincfg, 0);
#ifdef CONFIG_STM32_WKUP_PINS
if (flags & STM32_GPIO_WKUP) {
#ifdef CONFIG_POWEROFF
struct gpio_dt_spec gpio_dt_cfg = {
.port = dev,
.pin = pin,
.dt_flags = (gpio_dt_flags_t)flags,
};
if (stm32_pwr_wkup_pin_cfg_gpio((const struct gpio_dt_spec *)&gpio_dt_cfg)) {
LOG_ERR("Could not configure GPIO %s pin %d as a wake-up source",
gpio_dt_cfg.port->name, gpio_dt_cfg.pin);
}
#else
LOG_DBG("STM32_GPIO_WKUP flag has no effect when CONFIG_POWEROFF=n");
#endif /* CONFIG_POWEROFF */
}
#endif /* CONFIG_STM32_WKUP_PINS */
/* Release clock only if pin is disconnected */
if (((flags & GPIO_OUTPUT) == 0) && ((flags & GPIO_INPUT) == 0)) {
err = pm_device_runtime_put(dev);
if (err < 0) {
return err;
}
}
return 0;
}
#if defined(CONFIG_GPIO_GET_CONFIG) && !defined(CONFIG_SOC_SERIES_STM32F1X)
/**
* @brief Get configuration of pin
*/
static int gpio_stm32_get_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t *flags)
{
const struct gpio_stm32_config *cfg = dev->config;
GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
struct gpio_stm32_pin pin_config;
int pin_ll;
int err;
err = pm_device_runtime_get(dev);
if (err < 0) {
return err;
}
pin_ll = stm32_pinval_get(pin);
pin_config.type = LL_GPIO_GetPinOutputType(gpio, pin_ll);
pin_config.pupd = LL_GPIO_GetPinPull(gpio, pin_ll);
pin_config.mode = LL_GPIO_GetPinMode(gpio, pin_ll);
pin_config.out_state = LL_GPIO_IsOutputPinSet(gpio, pin_ll);
gpio_stm32_pincfg_to_flags(pin_config, flags);
return pm_device_runtime_put(dev);
}
#endif /* CONFIG_GPIO_GET_CONFIG */
static int gpio_stm32_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_stm32_config *cfg = dev->config;
struct gpio_stm32_data *data = dev->data;
int edge = 0;
int err = 0;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode == GPIO_INT_MODE_DISABLE_ONLY) {
stm32_exti_disable(pin);
goto exit;
} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
stm32_exti_enable(pin);
goto exit;
}
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
if (mode == GPIO_INT_MODE_DISABLED) {
if (gpio_stm32_get_exti_source(pin) == cfg->port) {
stm32_exti_disable(pin);
stm32_exti_unset_callback(pin);
stm32_exti_trigger(pin, STM32_EXTI_TRIG_NONE);
}
/* else: No irq source configured for pin. Nothing to disable */
goto exit;
}
/* Level trigger interrupts not supported */
if (mode == GPIO_INT_MODE_LEVEL) {
err = -ENOTSUP;
goto exit;
}
if (stm32_exti_set_callback(pin, gpio_stm32_isr, data) != 0) {
err = -EBUSY;
goto exit;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
edge = STM32_EXTI_TRIG_FALLING;
break;
case GPIO_INT_TRIG_HIGH:
edge = STM32_EXTI_TRIG_RISING;
break;
case GPIO_INT_TRIG_BOTH:
edge = STM32_EXTI_TRIG_BOTH;
break;
default:
err = -EINVAL;
goto exit;
}
gpio_stm32_enable_int(cfg->port, pin);
stm32_exti_trigger(pin, edge);
stm32_exti_enable(pin);
exit:
return err;
}
static int gpio_stm32_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_stm32_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static const struct gpio_driver_api gpio_stm32_driver = {
.pin_configure = gpio_stm32_config,
#if defined(CONFIG_GPIO_GET_CONFIG) && !defined(CONFIG_SOC_SERIES_STM32F1X)
.pin_get_config = gpio_stm32_get_config,
#endif /* CONFIG_GPIO_GET_CONFIG */
.port_get_raw = gpio_stm32_port_get_raw,
.port_set_masked_raw = gpio_stm32_port_set_masked_raw,
.port_set_bits_raw = gpio_stm32_port_set_bits_raw,
.port_clear_bits_raw = gpio_stm32_port_clear_bits_raw,
.port_toggle_bits = gpio_stm32_port_toggle_bits,
.pin_interrupt_configure = gpio_stm32_pin_interrupt_configure,
.manage_callback = gpio_stm32_manage_callback,
};
#ifdef CONFIG_PM_DEVICE
static int gpio_stm32_pm_action(const struct device *dev,
enum pm_device_action action)
{
switch (action) {
case PM_DEVICE_ACTION_RESUME:
return gpio_stm32_clock_request(dev, true);
case PM_DEVICE_ACTION_SUSPEND:
return gpio_stm32_clock_request(dev, false);
default:
return -ENOTSUP;
}
return 0;
}
#endif /* CONFIG_PM_DEVICE */
/**
* @brief Initialize GPIO port
*
* Perform basic initialization of a GPIO port. The code will
* enable the clock for corresponding peripheral.
*
* @param dev GPIO device struct
*
* @return 0
*/
static int gpio_stm32_init(const struct device *dev)
{
struct gpio_stm32_data *data = dev->data;
int ret;
data->dev = dev;
if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
return -ENODEV;
}
#if (defined(PWR_CR2_IOSV) || defined(PWR_SVMCR_IO2SV)) && \
DT_NODE_HAS_STATUS(DT_NODELABEL(gpiog), okay)
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
/* Port G[15:2] requires external power supply */
/* Cf: L4/L5 RM, Chapter "Independent I/O supply rail" */
LL_PWR_EnableVddIO2();
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
#endif
/* enable port clock (if runtime PM is not enabled) */
ret = gpio_stm32_clock_request(dev, !IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME));
if (ret < 0) {
return ret;
}
if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)) {
pm_device_init_suspended(dev);
}
(void)pm_device_runtime_enable(dev);
return 0;
}
#define GPIO_DEVICE_INIT(__node, __suffix, __base_addr, __port, __cenr, __bus) \
static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
}, \
.base = (uint32_t *)__base_addr, \
.port = __port, \
.pclken = { .bus = __bus, .enr = __cenr } \
}; \
static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
PM_DEVICE_DT_DEFINE(__node, gpio_stm32_pm_action); \
DEVICE_DT_DEFINE(__node, \
gpio_stm32_init, \
PM_DEVICE_DT_GET(__node), \
&gpio_stm32_data_## __suffix, \
&gpio_stm32_cfg_## __suffix, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_stm32_driver)
#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), \
__suffix, \
DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)), \
STM32_PORT##__SUFFIX, \
DT_CLOCKS_CELL(DT_NODELABEL(gpio##__suffix), bits),\
DT_CLOCKS_CELL(DT_NODELABEL(gpio##__suffix), bus))
#define GPIO_DEVICE_INIT_STM32_IF_OKAY(__suffix, __SUFFIX) \
COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(gpio##__suffix), okay), \
(GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX)), \
())
GPIO_DEVICE_INIT_STM32_IF_OKAY(a, A);
GPIO_DEVICE_INIT_STM32_IF_OKAY(b, B);
GPIO_DEVICE_INIT_STM32_IF_OKAY(c, C);
GPIO_DEVICE_INIT_STM32_IF_OKAY(d, D);
GPIO_DEVICE_INIT_STM32_IF_OKAY(e, E);
GPIO_DEVICE_INIT_STM32_IF_OKAY(f, F);
GPIO_DEVICE_INIT_STM32_IF_OKAY(g, G);
GPIO_DEVICE_INIT_STM32_IF_OKAY(h, H);
GPIO_DEVICE_INIT_STM32_IF_OKAY(i, I);
GPIO_DEVICE_INIT_STM32_IF_OKAY(j, J);
GPIO_DEVICE_INIT_STM32_IF_OKAY(k, K);
GPIO_DEVICE_INIT_STM32_IF_OKAY(m, M);
GPIO_DEVICE_INIT_STM32_IF_OKAY(n, N);
GPIO_DEVICE_INIT_STM32_IF_OKAY(o, O);
GPIO_DEVICE_INIT_STM32_IF_OKAY(p, P);
``` | /content/code_sandbox/drivers/gpio/gpio_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,465 |
```c
/*
*
*/
#define DT_DRV_COMPAT ambiq_gpio_bank
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
#include <zephyr/spinlock.h>
#include <am_mcu_apollo.h>
typedef void (*ambiq_gpio_cfg_func_t)(void);
struct ambiq_gpio_config {
struct gpio_driver_config common;
uint32_t base;
uint32_t offset;
uint32_t irq_num;
ambiq_gpio_cfg_func_t cfg_func;
uint8_t ngpios;
};
struct ambiq_gpio_data {
struct gpio_driver_data common;
sys_slist_t cb;
struct k_spinlock lock;
};
static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
pin += dev_cfg->offset;
am_hal_gpio_pincfg_t pincfg = g_AM_HAL_GPIO_DEFAULT;
if (flags & GPIO_INPUT) {
pincfg = g_AM_HAL_GPIO_INPUT;
if (flags & GPIO_PULL_UP) {
pincfg.ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K;
} else if (flags & GPIO_PULL_DOWN) {
pincfg.ePullup = AM_HAL_GPIO_PIN_PULLDOWN;
}
}
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN;
}
} else {
pincfg.eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL;
}
}
if (flags & GPIO_DISCONNECTED) {
pincfg = g_AM_HAL_GPIO_DEFAULT;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
pincfg.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH;
am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
pincfg.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW;
am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR);
}
#else
pin += (dev_cfg->offset >> 2);
am_hal_gpio_pincfg_t pincfg = am_hal_gpio_pincfg_default;
if (flags & GPIO_INPUT) {
pincfg = am_hal_gpio_pincfg_input;
if (flags & GPIO_PULL_UP) {
pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLUP_50K;
} else if (flags & GPIO_PULL_DOWN) {
pincfg.GP.cfg_b.ePullup = AM_HAL_GPIO_PIN_PULLDOWN_50K;
}
}
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
pincfg.GP.cfg_b.eGPOutCfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN;
}
} else {
pincfg.GP.cfg_b.eGPOutCfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL;
}
}
if (flags & GPIO_DISCONNECTED) {
pincfg = am_hal_gpio_pincfg_disabled;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
pincfg.GP.cfg_b.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH;
am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
pincfg.GP.cfg_b.eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW;
am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR);
}
#endif
am_hal_gpio_pinconfig(pin, pincfg);
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int ambiq_gpio_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *out_flags)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
am_hal_gpio_pincfg_t pincfg;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
pin += dev_cfg->offset;
am_hal_gpio_pinconfig_get(pin, &pincfg);
if (pincfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_DISABLE &&
pincfg.eGPInput == AM_HAL_GPIO_PIN_INPUT_NONE) {
*out_flags = GPIO_DISCONNECTED;
}
if (pincfg.eGPInput == AM_HAL_GPIO_PIN_INPUT_ENABLE) {
*out_flags = GPIO_INPUT;
if (pincfg.ePullup == AM_HAL_GPIO_PIN_PULLUP_1_5K) {
*out_flags |= GPIO_PULL_UP;
} else if (pincfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN) {
*out_flags |= GPIO_PULL_DOWN;
}
}
if (pincfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) {
*out_flags = GPIO_OUTPUT | GPIO_PUSH_PULL;
if (pincfg.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH) {
*out_flags |= GPIO_OUTPUT_HIGH;
} else if (pincfg.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW) {
*out_flags |= GPIO_OUTPUT_LOW;
}
}
if (pincfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN) {
*out_flags = GPIO_OUTPUT | GPIO_OPEN_DRAIN;
if (pincfg.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH) {
*out_flags |= GPIO_OUTPUT_HIGH;
} else if (pincfg.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW) {
*out_flags |= GPIO_OUTPUT_LOW;
}
}
#else
pin += (dev_cfg->offset >> 2);
am_hal_gpio_pinconfig_get(pin, &pincfg);
if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_DISABLE &&
pincfg.GP.cfg_b.eGPInput == AM_HAL_GPIO_PIN_INPUT_NONE) {
*out_flags = GPIO_DISCONNECTED;
}
if (pincfg.GP.cfg_b.eGPInput == AM_HAL_GPIO_PIN_INPUT_ENABLE) {
*out_flags = GPIO_INPUT;
if (pincfg.GP.cfg_b.ePullup == AM_HAL_GPIO_PIN_PULLUP_50K) {
*out_flags |= GPIO_PULL_UP;
} else if (pincfg.GP.cfg_b.ePullup == AM_HAL_GPIO_PIN_PULLDOWN_50K) {
*out_flags |= GPIO_PULL_DOWN;
}
}
if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) {
*out_flags = GPIO_OUTPUT | GPIO_PUSH_PULL;
if (pincfg.GP.cfg_b.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH) {
*out_flags |= GPIO_OUTPUT_HIGH;
} else if (pincfg.GP.cfg_b.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW) {
*out_flags |= GPIO_OUTPUT_LOW;
}
}
if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN) {
*out_flags = GPIO_OUTPUT | GPIO_OPEN_DRAIN;
if (pincfg.GP.cfg_b.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH) {
*out_flags |= GPIO_OUTPUT_HIGH;
} else if (pincfg.GP.cfg_b.eCEpol == AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW) {
*out_flags |= GPIO_OUTPUT_LOW;
}
}
#endif
return 0;
}
#endif
#ifdef CONFIG_GPIO_GET_DIRECTION
static int ambiq_gpio_port_get_direction(const struct device *dev, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
am_hal_gpio_pincfg_t pincfg;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t pin_offset = dev_cfg->offset;
if (inputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.eGPInput == AM_HAL_GPIO_PIN_INPUT_ENABLE) {
ip |= BIT(i);
}
}
}
*inputs = ip;
}
if (outputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL ||
pincfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN) {
op |= BIT(i);
}
}
}
*outputs = op;
}
#else
uint32_t pin_offset = dev_cfg->offset >> 2;
if (inputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.GP.cfg_b.eGPInput == AM_HAL_GPIO_PIN_INPUT_ENABLE) {
ip |= BIT(i);
}
}
}
*inputs = ip;
}
if (outputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL ||
pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN) {
op |= BIT(i);
}
}
}
*outputs = op;
}
#endif
return 0;
}
#endif
static int ambiq_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
*value = (*AM_HAL_GPIO_RDn(dev_cfg->offset));
#else
*value = (*AM_HAL_GPIO_RDn(dev_cfg->offset >> 2));
#endif
return 0;
}
static int ambiq_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t pin_offset = dev_cfg->offset;
#else
uint32_t pin_offset = dev_cfg->offset >> 2;
#endif
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((mask >> i) & 1) {
am_hal_gpio_state_write(i + pin_offset, ((value >> i) & 1));
}
}
return 0;
}
static int ambiq_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t pin_offset = dev_cfg->offset;
#else
uint32_t pin_offset = dev_cfg->offset >> 2;
#endif
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_SET);
}
}
return 0;
}
static int ambiq_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t pin_offset = dev_cfg->offset;
#else
uint32_t pin_offset = dev_cfg->offset >> 2;
#endif
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_CLEAR);
}
}
return 0;
}
static int ambiq_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t pin_offset = dev_cfg->offset;
#else
uint32_t pin_offset = dev_cfg->offset >> 2;
#endif
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_TOGGLE);
}
}
return 0;
}
#define APOLLO3_HANDLE_SHARED_GPIO_IRQ(n) \
static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
const struct ambiq_gpio_config *cfg_##n = dev_##n->config; \
struct ambiq_gpio_data *const data_##n = dev_##n->data; \
uint32_t status_##n = (uint32_t)(ui64Status >> cfg_##n->offset); \
if (status_##n) { \
gpio_fire_callbacks(&data_##n->cb, dev_##n, status_##n); \
}
#define APOLLO3P_HANDLE_SHARED_GPIO_IRQ(n) \
static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
struct ambiq_gpio_data *const data_##n = dev_##n->data; \
if (pGpioIntStatusMask->U.Msk[n]) { \
gpio_fire_callbacks(&data_##n->cb, dev_##n, pGpioIntStatusMask->U.Msk[n]); \
}
static void ambiq_gpio_isr(const struct device *dev)
{
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
ARG_UNUSED(dev);
#if defined(CONFIG_SOC_APOLLO3_BLUE)
uint64_t ui64Status;
am_hal_gpio_interrupt_status_get(false, &ui64Status);
am_hal_gpio_interrupt_clear(ui64Status);
DT_INST_FOREACH_STATUS_OKAY(APOLLO3_HANDLE_SHARED_GPIO_IRQ)
#elif defined(CONFIG_SOC_APOLLO3P_BLUE)
AM_HAL_GPIO_MASKCREATE(GpioIntStatusMask);
am_hal_gpio_interrupt_status_get(false, pGpioIntStatusMask);
am_hal_gpio_interrupt_clear(pGpioIntStatusMask);
DT_INST_FOREACH_STATUS_OKAY(APOLLO3P_HANDLE_SHARED_GPIO_IRQ)
#endif
#else
uint32_t int_status;
struct ambiq_gpio_data *const data = dev->data;
const struct ambiq_gpio_config *const dev_cfg = dev->config;
am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status);
am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status);
gpio_fire_callbacks(&data->cb, dev, int_status);
#endif
}
static int ambiq_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
struct ambiq_gpio_data *const data = dev->data;
int ret;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_gpio_pincfg_t pincfg = g_AM_HAL_GPIO_DEFAULT;
int gpio_pin = pin + dev_cfg->offset;
ret = am_hal_gpio_pinconfig_get(gpio_pin, &pincfg);
if (mode == GPIO_INT_MODE_DISABLED) {
pincfg.eIntDir = AM_HAL_GPIO_PIN_INTDIR_NONE;
ret = am_hal_gpio_pinconfig(gpio_pin, pincfg);
k_spinlock_key_t key = k_spin_lock(&data->lock);
AM_HAL_GPIO_MASKCREATE(GpioIntMask);
ret = am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask, gpio_pin));
ret = am_hal_gpio_interrupt_disable(AM_HAL_GPIO_MASKBIT(pGpioIntMask, gpio_pin));
k_spin_unlock(&data->lock, key);
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
pincfg.eIntDir = AM_HAL_GPIO_PIN_INTDIR_HI2LO;
break;
case GPIO_INT_TRIG_HIGH:
pincfg.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI;
break;
case GPIO_INT_TRIG_BOTH:
pincfg.eIntDir = AM_HAL_GPIO_PIN_INTDIR_BOTH;
break;
default:
pincfg.eIntDir = AM_HAL_GPIO_PIN_INTDIR_NONE;
break;
}
ret = am_hal_gpio_pinconfig(gpio_pin, pincfg);
irq_enable(dev_cfg->irq_num);
k_spinlock_key_t key = k_spin_lock(&data->lock);
AM_HAL_GPIO_MASKCREATE(GpioIntMask);
ret = am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask, gpio_pin));
ret = am_hal_gpio_interrupt_enable(AM_HAL_GPIO_MASKBIT(pGpioIntMask, gpio_pin));
k_spin_unlock(&data->lock, key);
}
#else
am_hal_gpio_pincfg_t pincfg = am_hal_gpio_pincfg_default;
int gpio_pin = pin + (dev_cfg->offset >> 2);
uint32_t int_status;
ret = am_hal_gpio_pinconfig_get(gpio_pin, &pincfg);
if (mode == GPIO_INT_MODE_DISABLED) {
pincfg.GP.cfg_b.eIntDir = AM_HAL_GPIO_PIN_INTDIR_NONE;
ret = am_hal_gpio_pinconfig(gpio_pin, pincfg);
k_spinlock_key_t key = k_spin_lock(&data->lock);
ret = am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status);
ret = am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status);
ret = am_hal_gpio_interrupt_control(AM_HAL_GPIO_INT_CHANNEL_0,
AM_HAL_GPIO_INT_CTRL_INDV_DISABLE,
(void *)&gpio_pin);
k_spin_unlock(&data->lock, key);
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
pincfg.GP.cfg_b.eIntDir = AM_HAL_GPIO_PIN_INTDIR_HI2LO;
break;
case GPIO_INT_TRIG_HIGH:
pincfg.GP.cfg_b.eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI;
break;
case GPIO_INT_TRIG_BOTH:
/*
* GPIO_INT_TRIG_BOTH is not supported on Ambiq Apollo4 Plus Platform
* ERR008: GPIO: Dual-edge interrupts are not vectoring
*/
return -ENOTSUP;
default:
return -EINVAL;
}
ret = am_hal_gpio_pinconfig(gpio_pin, pincfg);
irq_enable(dev_cfg->irq_num);
k_spinlock_key_t key = k_spin_lock(&data->lock);
ret = am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status);
ret = am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status);
ret = am_hal_gpio_interrupt_control(AM_HAL_GPIO_INT_CHANNEL_0,
AM_HAL_GPIO_INT_CTRL_INDV_ENABLE,
(void *)&gpio_pin);
k_spin_unlock(&data->lock, key);
}
#endif
return ret;
}
static int ambiq_gpio_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct ambiq_gpio_data *const data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
static void ambiq_gpio_cfg_func(void)
{
/* Apollo3 GPIO banks share the same irq number, connect to bank0 once when init and handle
* different banks in ambiq_gpio_isr
*/
static bool global_irq_init = true;
if (!global_irq_init) {
return;
}
global_irq_init = false;
/* Shared irq config default to BANK0. */
IRQ_CONNECT(GPIO_IRQn, DT_INST_IRQ(0, priority), ambiq_gpio_isr, DEVICE_DT_INST_GET(0), 0);
}
#endif
static int ambiq_gpio_init(const struct device *port)
{
const struct ambiq_gpio_config *const dev_cfg = port->config;
NVIC_ClearPendingIRQ(dev_cfg->irq_num);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
ambiq_gpio_cfg_func();
#else
dev_cfg->cfg_func();
#endif
return 0;
}
static const struct gpio_driver_api ambiq_gpio_drv_api = {
.pin_configure = ambiq_gpio_pin_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = ambiq_gpio_get_config,
#endif
.port_get_raw = ambiq_gpio_port_get_raw,
.port_set_masked_raw = ambiq_gpio_port_set_masked_raw,
.port_set_bits_raw = ambiq_gpio_port_set_bits_raw,
.port_clear_bits_raw = ambiq_gpio_port_clear_bits_raw,
.port_toggle_bits = ambiq_gpio_port_toggle_bits,
.pin_interrupt_configure = ambiq_gpio_pin_interrupt_configure,
.manage_callback = ambiq_gpio_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = ambiq_gpio_port_get_direction,
#endif
};
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
/* Apollo3 GPIO banks share the same irq number, connect irq here will cause build error, so we
* leave this function blank here and do it in ambiq_gpio_cfg_func
*/
#define AMBIQ_GPIO_CONFIG_FUNC(n) static void ambiq_gpio_cfg_func_##n(void){};
#else
#define AMBIQ_GPIO_CONFIG_FUNC(n) \
static void ambiq_gpio_cfg_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), ambiq_gpio_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
return; \
};
#endif
#define AMBIQ_GPIO_DEFINE(n) \
static struct ambiq_gpio_data ambiq_gpio_data_##n; \
static void ambiq_gpio_cfg_func_##n(void); \
static const struct ambiq_gpio_config ambiq_gpio_config_##n = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = DT_REG_ADDR(DT_INST_PARENT(n)), \
.offset = DT_INST_REG_ADDR(n), \
.ngpios = DT_INST_PROP(n, ngpios), \
.irq_num = DT_INST_IRQN(n), \
.cfg_func = ambiq_gpio_cfg_func_##n}; \
AMBIQ_GPIO_CONFIG_FUNC(n) \
DEVICE_DT_INST_DEFINE(n, ambiq_gpio_init, NULL, &ambiq_gpio_data_##n, \
&ambiq_gpio_config_##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&ambiq_gpio_drv_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_GPIO_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,298 |
```c
/*
*
*/
/*
* Driver for GRLIB GRGPIO revision 2.
* - iflag determine pending interrupt.
* - interrupt map decides interrupt number if implemented.
* - logic or/and/xor registers used when possible
*/
#define DT_DRV_COMPAT gaisler_grgpio
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_grgpio.h"
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_grgpio2);
struct cfg {
struct gpio_driver_config common;
volatile struct grgpio_regs *regs;
int interrupt;
};
struct data {
struct gpio_driver_data common;
struct k_spinlock lock;
sys_slist_t cb;
uint32_t imask;
uint32_t connected;
int irqgen;
};
static void grgpio_isr(const struct device *dev);
static int pin_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct cfg *cfg = dev->config;
struct data *data = dev->data;
volatile struct grgpio_regs *regs = cfg->regs;
uint32_t mask = 1 << pin;
if (flags & GPIO_SINGLE_ENDED) {
return -ENOTSUP;
}
if (flags == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
if ((flags & GPIO_DIR_MASK) == (GPIO_INPUT | GPIO_OUTPUT)) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
k_spinlock_key_t key;
/*
* Register operations are atomic, but do the sequence under
* lock so it serializes.
*/
key = k_spin_lock(&data->lock);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
regs->output_or = mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
regs->output_and = ~mask;
}
regs->dir_or = mask;
k_spin_unlock(&data->lock, key);
} else {
regs->dir_and = ~mask;
}
return 0;
}
static int port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct cfg *cfg = dev->config;
*value = cfg->regs->data;
return 0;
}
static int port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct cfg *cfg = dev->config;
struct data *data = dev->data;
volatile struct grgpio_regs *regs = cfg->regs;
uint32_t port_val;
k_spinlock_key_t key;
value &= mask;
key = k_spin_lock(&data->lock);
port_val = (regs->output & ~mask) | value;
regs->output = port_val;
k_spin_unlock(&data->lock, key);
return 0;
}
static int port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct cfg *cfg = dev->config;
volatile struct grgpio_regs *regs = cfg->regs;
regs->output_or = pins;
return 0;
}
static int port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct cfg *cfg = dev->config;
volatile struct grgpio_regs *regs = cfg->regs;
regs->output_and = ~pins;
return 0;
}
static int port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct cfg *cfg = dev->config;
volatile struct grgpio_regs *regs = cfg->regs;
regs->output_xor = pins;
return 0;
}
static uint32_t get_pending_int(const struct device *dev)
{
const struct cfg *cfg = dev->config;
volatile struct grgpio_regs *regs = cfg->regs;
return regs->iflag;
}
static int pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct cfg *cfg = dev->config;
struct data *data = dev->data;
volatile struct grgpio_regs *regs = cfg->regs;
int ret = 0;
const uint32_t mask = 1 << pin;
uint32_t polmask;
k_spinlock_key_t key;
if ((mask & data->imask) == 0) {
/* This pin can not generate interrupt */
return -ENOTSUP;
}
if (mode != GPIO_INT_MODE_DISABLED) {
if (trig == GPIO_INT_TRIG_LOW) {
polmask = 0;
} else if (trig == GPIO_INT_TRIG_HIGH) {
polmask = mask;
} else {
return -ENOTSUP;
}
}
key = k_spin_lock(&data->lock);
if (mode == GPIO_INT_MODE_DISABLED) {
regs->imask_and = ~mask;
} else if (mode == GPIO_INT_MODE_LEVEL) {
regs->imask_and = ~mask;
regs->iedge &= ~mask;
regs->ipol = (regs->ipol & ~mask) | polmask;
regs->imask_or = mask;
} else if (mode == GPIO_INT_MODE_EDGE) {
regs->imask_and = ~mask;
regs->iedge |= mask;
regs->ipol = (regs->ipol & ~mask) | polmask;
regs->imask_or = mask;
} else {
ret = -ENOTSUP;
}
k_spin_unlock(&data->lock, key);
/* Remove old interrupt history for this pin. */
regs->iflag = mask;
int interrupt = cfg->interrupt;
const int irqgen = data->irqgen;
if (irqgen == 0) {
interrupt += pin;
} else if (irqgen == 1) {
;
} else if (irqgen < 32) {
/* look up interrupt number in GRGPIO interrupt map */
uint32_t val = regs->irqmap[pin/4];
val >>= (3 - pin % 4) * 8;
interrupt += (val & 0x1f);
}
if (interrupt && ((1 << interrupt) & data->connected) == 0) {
irq_connect_dynamic(
interrupt,
0,
(void (*)(const void *)) grgpio_isr,
dev,
0
);
irq_enable(interrupt);
data->connected |= 1 << interrupt;
}
return ret;
}
static int manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static void grgpio_isr(const struct device *dev)
{
const struct cfg *cfg = dev->config;
struct data *data = dev->data;
volatile struct grgpio_regs *regs = cfg->regs;
uint32_t pins;
/* no locking needed when iflag is implemented */
pins = regs->iflag;
if (pins == 0) {
return;
}
regs->iflag = pins;
gpio_fire_callbacks(&data->cb, dev, pins);
}
static int grgpio_init(const struct device *dev)
{
const struct cfg *cfg = dev->config;
struct data *data = dev->data;
volatile struct grgpio_regs *regs = cfg->regs;
data->irqgen = (regs->cap & GRGPIO_CAP_IRQGEN) >> GRGPIO_CAP_IRQGEN_BIT;
regs->dir = 0;
/* Mask all Interrupts */
regs->imask = 0;
/* Make IRQ Rising edge triggered default */
regs->ipol = 0xffffffff;
regs->iedge = 0xffffffff;
regs->iflag = 0xffffffff;
/* Read what I/O lines have IRQ support */
data->imask = regs->ipol;
return 0;
}
static const struct gpio_driver_api driver_api = {
.pin_configure = pin_configure,
.port_get_raw = port_get_raw,
.port_set_masked_raw = port_set_masked_raw,
.port_set_bits_raw = port_set_bits_raw,
.port_clear_bits_raw = port_clear_bits_raw,
.port_toggle_bits = port_toggle_bits,
.pin_interrupt_configure = pin_interrupt_configure,
.manage_callback = manage_callback,
.get_pending_int = get_pending_int,
};
#define GRGPIO_INIT(n) \
static const struct cfg cfg_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.regs = (void *) DT_INST_REG_ADDR(n), \
.interrupt = DT_INST_IRQN(n), \
}; \
static struct data data_##n; \
\
DEVICE_DT_INST_DEFINE(n, \
grgpio_init, \
NULL, \
&data_##n, \
&cfg_##n, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&driver_api \
);
DT_INST_FOREACH_STATUS_OKAY(GRGPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_grgpio2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,033 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm6001_gpio
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/dt-bindings/gpio/nordic-npm6001-gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/toolchain.h>
/* nPM6001 GPIO related registers */
#define NPM6001_GPIOOUTSET 0x69U
#define NPM6001_GPIOOUTCLR 0x6AU
#define NPM6001_GPIOIN 0x6BU
#define NPM6001_GPIO0CONF 0x6CU
#define NPM6001_GPIO1CONF 0x6DU
#define NPM6001_GPIO2CONF 0x6EU
/* GPIO(0|1|2)CONF fields */
#define NPM6001_CONF_DIRECTION_OUTPUT BIT(0)
#define NPM6001_CONF_INPUT_ENABLED BIT(1)
#define NPM6001_CONF_PULLDOWN_ENABLED BIT(2)
#define NPM6001_CONF_DRIVE_HIGH BIT(5)
#define NPM6001_CONF_SENSE_CMOS BIT(6)
#define NPM6001_PIN_MAX 2U
#define NPM6001_PIN_MSK 0x7U
struct gpio_npm6001_config {
struct gpio_driver_config common;
struct i2c_dt_spec bus;
};
struct gpio_npm6001_data {
struct gpio_driver_data common;
};
static int gpio_npm6001_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_npm6001_config *config = dev->config;
uint8_t reg = NPM6001_GPIOIN;
uint8_t val;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
ret = i2c_write_read_dt(&config->bus, ®, sizeof(reg), &val,
sizeof(val));
if (ret < 0) {
return ret;
}
*value = val;
return 0;
}
static int gpio_npm6001_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_npm6001_config *config = dev->config;
uint8_t buf[2] = {NPM6001_GPIOOUTSET, (uint8_t)pins & NPM6001_PIN_MSK};
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static int gpio_npm6001_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_npm6001_config *config = dev->config;
uint8_t buf[2] = {NPM6001_GPIOOUTCLR, (uint8_t)pins & NPM6001_PIN_MSK};
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static inline int gpio_npm6001_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_npm6001_config *config = dev->config;
uint8_t buf[2] = {NPM6001_GPIO0CONF, 0U};
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin > NPM6001_PIN_MAX) {
return -EINVAL;
}
/* select GPIO0CONF/GPIO1CONF/GPIO2CONF */
buf[0] += pin;
if ((flags & GPIO_OUTPUT) != 0U) {
/* input buffer enabled to allow reading output level */
buf[1] |= NPM6001_CONF_DIRECTION_OUTPUT |
NPM6001_CONF_INPUT_ENABLED;
/* open-drain/open-source not supported */
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP;
}
/* drive strength (defaults to normal) */
if ((flags & NPM6001_GPIO_DRIVE_MSK) ==
NPM6001_GPIO_DRIVE_HIGH) {
buf[1] |= NPM6001_CONF_DRIVE_HIGH;
}
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
int ret;
ret = gpio_npm6001_port_set_bits_raw(
dev, (gpio_port_pins_t)BIT(pin));
if (ret < 0) {
return ret;
}
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
int ret;
ret = gpio_npm6001_port_clear_bits_raw(
dev, (gpio_port_pins_t)BIT(pin));
if (ret < 0) {
return ret;
}
}
} else if ((flags & GPIO_INPUT) != 0U) {
buf[1] |= NPM6001_CONF_INPUT_ENABLED;
/* pull resistor */
if ((flags & GPIO_PULL_DOWN) != 0U) {
buf[1] |= NPM6001_CONF_PULLDOWN_ENABLED;
} else if ((flags & GPIO_PULL_UP) != 0U) {
return -ENOTSUP;
}
/* input type (defaults to schmitt trigger) */
if ((flags & NPM6001_GPIO_SENSE_MSK) ==
NPM6001_GPIO_SENSE_CMOS) {
buf[1] |= NPM6001_CONF_SENSE_CMOS;
}
} else {
return -ENOTSUP;
}
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static int gpio_npm6001_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
int ret;
ret = gpio_npm6001_port_set_bits_raw(dev, mask & value);
if (ret < 0) {
return ret;
}
return gpio_npm6001_port_clear_bits_raw(
dev, mask & (~value & NPM6001_PIN_MSK));
}
static int gpio_npm6001_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
uint32_t val;
int ret;
ret = gpio_npm6001_port_get_raw(dev, &val);
if (ret < 0) {
return ret;
}
return gpio_npm6001_port_set_masked_raw(dev, pins,
~val & NPM6001_PIN_MSK);
}
static const struct gpio_driver_api gpio_npm6001_api = {
.pin_configure = gpio_npm6001_configure,
.port_get_raw = gpio_npm6001_port_get_raw,
.port_set_masked_raw = gpio_npm6001_port_set_masked_raw,
.port_set_bits_raw = gpio_npm6001_port_set_bits_raw,
.port_clear_bits_raw = gpio_npm6001_port_clear_bits_raw,
.port_toggle_bits = gpio_npm6001_port_toggle_bits,
};
static int gpio_npm6001_init(const struct device *dev)
{
const struct gpio_npm6001_config *config = dev->config;
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
return 0;
}
#define GPIO_NPM6001_DEFINE(n) \
static const struct gpio_npm6001_config gpio_npm6001_config##n = { \
.common = \
{ \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.bus = I2C_DT_SPEC_GET(DT_INST_PARENT(n))}; \
\
static struct gpio_npm6001_data gpio_npm6001_data##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_npm6001_init, NULL, \
&gpio_npm6001_data##n, &gpio_npm6001_config##n, \
POST_KERNEL, CONFIG_GPIO_NPM6001_INIT_PRIORITY, \
&gpio_npm6001_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NPM6001_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_npm6001.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,777 |
```unknown
config GPIO_AXP192
bool "AXP192 GPIO driver"
default y
depends on DT_HAS_X_POWERS_AXP192_GPIO_ENABLED
depends on DT_HAS_X_POWERS_AXP192_ENABLED
select I2C
select MFD
help
Enable the AXP192 GPIO driver.
config GPIO_AXP192_INIT_PRIORITY
int "AXP192 GPIO driver initialization priority"
depends on GPIO_AXP192
default 81
help
Initialization priority for the AXP192 GPIO driver. It must be
greater than the I2C controller init priority and the mfd driver
init priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.axp192 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 135 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mpfs_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/util.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define MSS_GPIO_INPUT_MODE 0x02
#define MSS_GPIO_OUTPUT_MODE 0x05
#define MSS_GPIO_INOUT_MODE 0x03
#define MSS_GPIO_IRQ_LEVEL_HIGH 0x00
#define MSS_GPIO_IRQ_LEVEL_LOW 0x20
#define MSS_GPIO_IRQ_EDGE_POSITIVE 0x40
#define MSS_GPIO_IRQ_EDGE_NEGATIVE 0x60
#define MSS_GPIO_IRQ_EDGE_BOTH 0x80
#define MSS_GPIO_INT_ENABLE_MASK 0x08
#define MSS_OUTPUT_BUFFER_ENABLE_MASK 0x04
struct mss_gpio_t {
uint32_t gpio_cfg[32];
uint32_t gpio_irq;
const uint32_t gpio_in;
uint32_t gpio_out;
uint32_t gpio_cfg_all;
uint32_t gpio_cfg_byte[4];
uint32_t gpio_clr_bits;
uint32_t gpio_set_bits;
};
typedef void (*mss_gpio_cfg_func_t)(void);
struct mss_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uintptr_t gpio_base_addr;
uint32_t gpio_irq_base;
mss_gpio_cfg_func_t gpio_cfg_func;
};
struct mss_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of callbacks */
sys_slist_t cb;
};
/* Helper Macros for GPIO */
#define DEV_GPIO_CFG(dev) \
((const struct mss_gpio_config * const)(dev)->config)
#define DEV_GPIO(dev) \
((volatile struct mss_gpio_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
#define DEV_GPIO_DATA(dev) \
((struct mss_gpio_data *)(dev)->data)
static int mss_gpio_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
uint32_t io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
if (io_flags == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
gpio->gpio_cfg[pin] |= MSS_GPIO_OUTPUT_MODE;
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio->gpio_out |= BIT(pin);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio->gpio_out &= ~BIT(pin);
}
} else if (flags & GPIO_INPUT) {
gpio->gpio_cfg[pin] |= MSS_GPIO_INPUT_MODE;
} else {
return -ENOTSUP;
}
return 0;
}
static int mss_gpio_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_out ^= mask;
return 0;
}
static int mss_gpio_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
*value = gpio->gpio_in;
return 0;
}
static int mss_gpio_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_out = (gpio->gpio_out & ~mask) | (value & mask);
return 0;
}
static int mss_gpio_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_out |= mask;
return 0;
}
static int mss_gpio_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_out &= ~mask;
return 0;
}
static int mss_gpio_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
ARG_UNUSED(trig);
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_cfg[pin] |= (MSS_GPIO_INT_ENABLE_MASK);
switch (mode | trig) {
case GPIO_INT_EDGE_BOTH:
gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_BOTH);
break;
case GPIO_INT_EDGE_RISING:
gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_POSITIVE);
break;
case GPIO_INT_EDGE_FALLING:
gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_NEGATIVE);
break;
case GPIO_INT_LEVEL_LOW:
gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_LEVEL_LOW);
break;
case GPIO_INT_LEVEL_HIGH:
gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_LEVEL_HIGH);
break;
default:
gpio->gpio_cfg[pin] &= ~MSS_GPIO_INT_ENABLE_MASK;
break;
}
return 0;
}
static int mss_gpio_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct mss_gpio_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static const struct gpio_driver_api mss_gpio_driver = {
.pin_configure = mss_gpio_config,
.port_toggle_bits = mss_gpio_port_toggle_bits,
.port_get_raw = mss_gpio_port_get_raw,
.port_set_masked_raw = mss_gpio_port_set_masked_raw,
.port_set_bits_raw = mss_gpio_port_set_bits_raw,
.port_clear_bits_raw = mss_gpio_port_clear_bits_raw,
.pin_interrupt_configure = mss_gpio_pin_interrupt_configure,
.manage_callback = mss_gpio_manage_callback
};
static int mss_gpio_init(const struct device *dev)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
gpio->gpio_irq = 0xFFFFFFFFU;
const struct mss_gpio_config *cfg = DEV_GPIO_CFG(dev);
/* Configure GPIO device */
cfg->gpio_cfg_func();
return 0;
}
static void mss_gpio_irq_handler(const struct device *dev)
{
volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
uint32_t interrupt_status = gpio->gpio_irq;
gpio->gpio_irq = gpio->gpio_irq;
struct mss_gpio_data *data = dev->data;
gpio_fire_callbacks(&data->cb, dev, interrupt_status);
}
#define MSS_GPIO_INIT(n) \
static struct mss_gpio_data mss_gpio_data_##n; \
static void gpio_mss_gpio_cfg_func_##n(void); \
\
static const struct mss_gpio_config mss_gpio_config_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.gpio_base_addr = DT_INST_REG_ADDR(n), \
.gpio_irq_base = DT_INST_IRQN(n), \
.gpio_cfg_func = gpio_mss_gpio_cfg_func_##n \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
mss_gpio_init, \
NULL, \
&mss_gpio_data_##n, &mss_gpio_config_##n, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&mss_gpio_driver); \
\
static void gpio_mss_gpio_cfg_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mss_gpio_irq_handler, \
DEVICE_DT_INST_GET(n), \
0); \
irq_enable(DT_INST_IRQN(n)); \
} \
DT_INST_FOREACH_STATUS_OKAY(MSS_GPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_mchp_mss.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,728 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_gpio
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_gpio, CONFIG_GPIO_LOG_LEVEL);
#ifdef CONFIG_NXP_S32_EIRQ
#include <zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h>
#endif
#ifdef CONFIG_NXP_S32_WKPU
#include <zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h>
#endif
/* SIUL2 Multiplexed Signal Configuration Register (offset from port base) */
#define SIUL2_MSCR(n) (0x4 * (n))
/* SIUL2 Parallel GPIO Pad Data Out (offset from gpio base) */
#define SIUL2_PGPDO 0
/* SIUL2 Parallel GPIO Pad Data In */
#define SIUL2_PGPDI 0x40
/* Handy accessors */
#define GPIO_READ(r) sys_read16(config->gpio_base + (r))
#define GPIO_WRITE(r, v) sys_write16((v), config->gpio_base + (r))
#define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
#define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
#if defined(CONFIG_NXP_S32_EIRQ) || defined(CONFIG_NXP_S32_WKPU)
#define NXP_S32_GPIO_LINE_NOT_FOUND 0xff
struct gpio_nxp_s32_irq_map {
uint8_t pin;
uint8_t line;
} __packed;
struct gpio_nxp_s32_irq_config {
const struct device *ctrl;
uint8_t map_cnt;
struct gpio_nxp_s32_irq_map *map;
};
#endif
struct gpio_nxp_s32_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
mem_addr_t gpio_base;
mem_addr_t port_base;
#ifdef CONFIG_NXP_S32_EIRQ
struct gpio_nxp_s32_irq_config *eirq_info;
#endif
#ifdef CONFIG_NXP_S32_WKPU
struct gpio_nxp_s32_irq_config *wkpu_info;
#endif
};
struct gpio_nxp_s32_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
#if defined(CONFIG_NXP_S32_EIRQ) || defined(CONFIG_NXP_S32_WKPU)
sys_slist_t callbacks;
#if defined(CONFIG_NXP_S32_WKPU)
uint32_t pin_wkpu_mask;
#endif /* defined(CONFIG_NXP_S32_WKPU) */
#endif
};
static ALWAYS_INLINE uint16_t reverse_bits_16(uint16_t value)
{
return (uint16_t)(__RBIT((uint32_t)value) >> 16);
}
static int nxp_s32_gpio_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_nxp_s32_config *config = dev->config;
uint32_t mscr_val;
uint32_t pgpdo_val;
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
#if defined(CONFIG_NXP_S32_WKPU)
struct gpio_nxp_s32_data *data = dev->data;
WRITE_BIT(data->pin_wkpu_mask, pin, (flags & NXP_S32_GPIO_INT_WKPU));
#else
if (flags & NXP_S32_GPIO_INT_WKPU) {
return -ENOTSUP;
}
#endif
mscr_val = PORT_READ(pin);
mscr_val &= ~(SIUL2_MSCR_SSS_MASK | SIUL2_MSCR_OBE_MASK | SIUL2_MSCR_IBE_MASK |
SIUL2_MSCR_PUE_MASK | SIUL2_MSCR_PUS_MASK);
if (flags & GPIO_OUTPUT) {
mscr_val |= SIUL2_MSCR_OBE(1U);
pgpdo_val = GPIO_READ(SIUL2_PGPDO);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
pgpdo_val |= BIT(15 - pin);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
pgpdo_val &= ~BIT(15 - pin);
}
GPIO_WRITE(SIUL2_PGPDO, pgpdo_val);
}
if (flags & GPIO_INPUT) {
mscr_val |= SIUL2_MSCR_IBE(1U);
}
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
mscr_val |= SIUL2_MSCR_PUE(1U);
if (flags & GPIO_PULL_UP) {
mscr_val |= SIUL2_MSCR_PUS(1U);
}
}
PORT_WRITE(pin, mscr_val);
return 0;
}
static int nxp_s32_gpio_port_get_raw(const struct device *port, uint32_t *value)
{
const struct gpio_nxp_s32_config *config = port->config;
*value = reverse_bits_16(GPIO_READ(SIUL2_PGPDI));
return 0;
}
static int nxp_s32_gpio_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_nxp_s32_config *config = port->config;
gpio_port_pins_t pins_value;
pins_value = reverse_bits_16(GPIO_READ(SIUL2_PGPDO));
pins_value = (pins_value & ~mask) | (mask & value);
GPIO_WRITE(SIUL2_PGPDO, reverse_bits_16(pins_value));
return 0;
}
static int nxp_s32_gpio_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_nxp_s32_config *config = port->config;
uint16_t reg_val;
reg_val = GPIO_READ(SIUL2_PGPDO);
reg_val |= reverse_bits_16(pins);
GPIO_WRITE(SIUL2_PGPDO, reg_val);
return 0;
}
static int nxp_s32_gpio_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_nxp_s32_config *config = port->config;
uint16_t reg_val;
reg_val = GPIO_READ(SIUL2_PGPDO);
reg_val &= ~reverse_bits_16(pins);
GPIO_WRITE(SIUL2_PGPDO, reg_val);
return 0;
}
static int nxp_s32_gpio_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
const struct gpio_nxp_s32_config *config = port->config;
uint16_t reg_val;
reg_val = GPIO_READ(SIUL2_PGPDO);
reg_val ^= reverse_bits_16(pins);
GPIO_WRITE(SIUL2_PGPDO, reg_val);
return 0;
}
#if defined(CONFIG_NXP_S32_EIRQ) || defined(CONFIG_NXP_S32_WKPU)
static uint8_t nxp_s32_gpio_pin_to_line(const struct gpio_nxp_s32_irq_config *irq_cfg,
uint8_t pin)
{
uint8_t i;
for (i = 0; i < irq_cfg->map_cnt; i++) {
if (irq_cfg->map[i].pin == pin) {
return irq_cfg->map[i].line;
}
}
return NXP_S32_GPIO_LINE_NOT_FOUND;
}
static void nxp_s32_gpio_isr(uint8_t pin, void *arg)
{
const struct device *dev = (struct device *)arg;
struct gpio_nxp_s32_data *data = dev->data;
gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
}
#if defined(CONFIG_NXP_S32_EIRQ)
static int nxp_s32_gpio_eirq_get_trigger(enum eirq_nxp_s32_trigger *eirq_trigger,
enum gpio_int_trig trigger)
{
switch (trigger) {
case GPIO_INT_TRIG_LOW:
*eirq_trigger = EIRQ_NXP_S32_FALLING_EDGE;
break;
case GPIO_INT_TRIG_HIGH:
*eirq_trigger = EIRQ_NXP_S32_RISING_EDGE;
break;
case GPIO_INT_TRIG_BOTH:
*eirq_trigger = EIRQ_NXP_S32_BOTH_EDGES;
break;
default:
return -ENOTSUP;
}
return 0;
}
static int nxp_s32_gpio_config_eirq(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_nxp_s32_config *config = dev->config;
const struct gpio_nxp_s32_irq_config *irq_cfg = config->eirq_info;
uint8_t irq_line;
enum eirq_nxp_s32_trigger eirq_trigger;
if (irq_cfg == NULL) {
LOG_ERR("external interrupt controller not available or enabled");
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
irq_line = nxp_s32_gpio_pin_to_line(irq_cfg, pin);
if (irq_line == NXP_S32_GPIO_LINE_NOT_FOUND) {
if (mode == GPIO_INT_MODE_DISABLED) {
return 0;
}
LOG_ERR("pin %d cannot be used for external interrupt", pin);
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_DISABLED) {
eirq_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line);
eirq_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line);
} else {
if (nxp_s32_gpio_eirq_get_trigger(&eirq_trigger, trig)) {
return -ENOTSUP;
}
if (eirq_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin,
nxp_s32_gpio_isr, (void *)dev)) {
LOG_ERR("pin %d is already in use", pin);
return -EBUSY;
}
eirq_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, eirq_trigger);
}
return 0;
}
#endif /* CONFIG_NXP_S32_EIRQ */
#if defined(CONFIG_NXP_S32_WKPU)
static int nxp_s32_gpio_wkpu_get_trigger(enum wkpu_nxp_s32_trigger *wkpu_trigger,
enum gpio_int_trig trigger)
{
switch (trigger) {
case GPIO_INT_TRIG_LOW:
*wkpu_trigger = WKPU_NXP_S32_FALLING_EDGE;
break;
case GPIO_INT_TRIG_HIGH:
*wkpu_trigger = WKPU_NXP_S32_RISING_EDGE;
break;
case GPIO_INT_TRIG_BOTH:
*wkpu_trigger = WKPU_NXP_S32_BOTH_EDGES;
break;
default:
return -ENOTSUP;
}
return 0;
}
static int nxp_s32_gpio_config_wkpu(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_nxp_s32_config *config = dev->config;
const struct gpio_nxp_s32_irq_config *irq_cfg = config->wkpu_info;
uint8_t irq_line;
enum wkpu_nxp_s32_trigger wkpu_trigger;
if (irq_cfg == NULL) {
LOG_ERR("WKPU controller not available or enabled");
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
irq_line = nxp_s32_gpio_pin_to_line(irq_cfg, pin);
if (irq_line == NXP_S32_GPIO_LINE_NOT_FOUND) {
if (mode == GPIO_INT_MODE_DISABLED) {
return 0;
}
LOG_ERR("pin %d cannot be used for external interrupt", pin);
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_DISABLED) {
wkpu_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line);
wkpu_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line);
} else {
if (nxp_s32_gpio_wkpu_get_trigger(&wkpu_trigger, trig)) {
return -ENOTSUP;
}
if (wkpu_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin,
nxp_s32_gpio_isr, (void *)dev)) {
LOG_ERR("pin %d is already in use", pin);
return -EBUSY;
}
wkpu_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, wkpu_trigger);
}
return 0;
}
#endif /* CONFIG_NXP_S32_WKPU */
static int nxp_s32_gpio_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
#if defined(CONFIG_NXP_S32_WKPU)
struct gpio_nxp_s32_data *data = dev->data;
if (data->pin_wkpu_mask & BIT(pin)) {
return nxp_s32_gpio_config_wkpu(dev, pin, mode, trig);
}
#endif
#if defined(CONFIG_NXP_S32_EIRQ)
return nxp_s32_gpio_config_eirq(dev, pin, mode, trig);
#endif
}
static int nxp_s32_gpio_manage_callback(const struct device *dev,
struct gpio_callback *cb, bool set)
{
struct gpio_nxp_s32_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, cb, set);
}
#endif /* defined(CONFIG_NXP_S32_EIRQ) || defined(CONFIG_NXP_S32_WKPU) */
#ifdef CONFIG_GPIO_GET_CONFIG
static int nxp_s32_gpio_pin_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_nxp_s32_config *config = dev->config;
uint16_t pins_output;
uint32_t mscr_val;
gpio_flags_t flags = 0;
mscr_val = PORT_READ(pin);
if ((mscr_val & SIUL2_MSCR_IBE_MASK) != 0) {
flags |= GPIO_INPUT;
}
if ((mscr_val & SIUL2_MSCR_OBE_MASK) != 0) {
flags |= GPIO_OUTPUT;
pins_output = GPIO_READ(SIUL2_PGPDO);
if ((pins_output & BIT(15 - pin)) != 0) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
#if defined(SIUL2_MSCR_ODE_MASK)
if ((mscr_val & SIUL2_MSCR_ODE_MASK) != 0) {
flags |= GPIO_OPEN_DRAIN;
}
#endif /* SIUL2_MSCR_ODE_MASK */
}
if ((mscr_val & SIUL2_MSCR_PUE_MASK) != 0) {
if ((mscr_val & SIUL2_MSCR_PUS_MASK) != 0) {
flags |= GPIO_PULL_UP;
} else {
flags |= GPIO_PULL_DOWN;
}
}
*out_flags = flags;
return 0;
}
#endif /* CONFIG_GPIO_GET_CONFIG */
#ifdef CONFIG_GPIO_GET_DIRECTION
static int nxp_s32_gpio_port_get_direction(const struct device *dev,
gpio_port_pins_t map,
gpio_port_pins_t *inputs,
gpio_port_pins_t *outputs)
{
const struct gpio_nxp_s32_config *config = dev->config;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
uint32_t pin;
map &= config->common.port_pin_mask;
if (inputs != NULL) {
while (map) {
pin = find_lsb_set(map) - 1;
ip |= (!!(PORT_READ(pin) & SIUL2_MSCR_IBE_MASK)) * BIT(pin);
map &= ~BIT(pin);
}
*inputs = ip;
}
if (outputs != NULL) {
while (map) {
pin = find_lsb_set(map) - 1;
op |= (!!(PORT_READ(pin) & SIUL2_MSCR_OBE_MASK)) * BIT(pin);
map &= ~BIT(pin);
}
*outputs = op;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_nxp_s32_driver_api = {
.pin_configure = nxp_s32_gpio_configure,
.port_get_raw = nxp_s32_gpio_port_get_raw,
.port_set_masked_raw = nxp_s32_gpio_port_set_masked_raw,
.port_set_bits_raw = nxp_s32_gpio_port_set_bits_raw,
.port_clear_bits_raw = nxp_s32_gpio_port_clear_bits_raw,
.port_toggle_bits = nxp_s32_gpio_port_toggle_bits,
#if defined(CONFIG_NXP_S32_EIRQ) || defined(CONFIG_NXP_S32_WKPU)
.pin_interrupt_configure = nxp_s32_gpio_pin_interrupt_configure,
.manage_callback = nxp_s32_gpio_manage_callback,
#endif
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = nxp_s32_gpio_pin_get_config,
#endif
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = nxp_s32_gpio_port_get_direction,
#endif
};
/* Calculate the port pin mask based on ngpios and gpio-reserved-ranges node
* properties. Multiple reserved ranges are not supported.
*
* For example, for the following gpio node definition:
*
* gpioo: gpio@40521716 {
* ...
* ngpios = <14>;
* gpio-reserved-ranges = <0 10>;
* };
*
* the generated mask will be will be 0x3C00.
*/
#define GPIO_NXP_S32_RESERVED_PIN_MASK(n) \
(GENMASK(DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 0) + \
DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 1) - 1, \
DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 0) \
))
#define GPIO_NXP_S32_PORT_PIN_MASK(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpio_reserved_ranges), \
(GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
& ~(GPIO_NXP_S32_RESERVED_PIN_MASK(n))), \
(GPIO_PORT_PIN_MASK_FROM_DT_INST(n)))
#ifdef CONFIG_NXP_S32_EIRQ
#define GPIO_NXP_S32_EIRQ_NODE(n) \
DT_INST_PHANDLE(n, interrupt_parent)
#define GPIO_NXP_S32_EIRQ_PIN_LINE(idx, n) \
DT_INST_IRQ_BY_IDX(n, idx, gpio_pin), \
DT_INST_IRQ_BY_IDX(n, idx, eirq_line) \
#define GPIO_NXP_S32_SET_EIRQ_INFO(n) \
BUILD_ASSERT((DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupt_parent) == \
DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupts)), \
"interrupts and interrupt-parent must be set when " \
"using external interrupts"); \
IF_ENABLED(DT_NODE_HAS_STATUS(GPIO_NXP_S32_EIRQ_NODE(n), okay), ( \
static uint8_t gpio_nxp_s32_eirq_data_##n[] = { \
LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), \
GPIO_NXP_S32_EIRQ_PIN_LINE, (,), n) \
}; \
static struct gpio_nxp_s32_irq_config gpio_nxp_s32_eirq_##n = { \
.ctrl = DEVICE_DT_GET(GPIO_NXP_S32_EIRQ_NODE(n)), \
.map_cnt = DT_NUM_IRQS(DT_DRV_INST(n)), \
.map = (struct gpio_nxp_s32_irq_map *) \
gpio_nxp_s32_eirq_data_##n, \
}; \
))
#define GPIO_NXP_S32_GET_EIRQ_INFO(n) \
.eirq_info = UTIL_AND(DT_NODE_HAS_STATUS(GPIO_NXP_S32_EIRQ_NODE(n), okay),\
&gpio_nxp_s32_eirq_##n),
#else
#define GPIO_NXP_S32_SET_EIRQ_INFO(n)
#define GPIO_NXP_S32_GET_EIRQ_INFO(n)
#endif /* CONFIG_NXP_S32_EIRQ */
#ifdef CONFIG_NXP_S32_WKPU
#define GPIO_NXP_S32_WKPU_NODE(n) DT_INST_PHANDLE(n, nxp_wkpu)
#define GPIO_NXP_S32_SET_WKPU_INFO(n) \
BUILD_ASSERT((DT_INST_NODE_HAS_PROP(n, nxp_wkpu) == \
DT_INST_NODE_HAS_PROP(n, nxp_wkpu_interrupts)), \
"nxp,wkpu and nxp,wkpu-interrupts must be provided"); \
IF_ENABLED(DT_NODE_HAS_STATUS(GPIO_NXP_S32_WKPU_NODE(n), okay), ( \
static uint8_t gpio_nxp_s32_wkpu_data_##n[] = \
DT_INST_PROP(n, nxp_wkpu_interrupts); \
static struct gpio_nxp_s32_irq_config gpio_nxp_s32_wkpu_##n = { \
.ctrl = DEVICE_DT_GET(GPIO_NXP_S32_WKPU_NODE(n)), \
.map_cnt = sizeof(gpio_nxp_s32_wkpu_data_##n) / \
sizeof(struct gpio_nxp_s32_irq_map), \
.map = (struct gpio_nxp_s32_irq_map *) \
gpio_nxp_s32_wkpu_data_##n, \
}; \
))
#define GPIO_NXP_S32_GET_WKPU_INFO(n) \
.wkpu_info = UTIL_AND(DT_NODE_HAS_STATUS(GPIO_NXP_S32_WKPU_NODE(n), okay),\
&gpio_nxp_s32_wkpu_##n)
#else
#define GPIO_NXP_S32_SET_WKPU_INFO(n)
#define GPIO_NXP_S32_GET_WKPU_INFO(n)
#endif /* CONFIG_NXP_S32_WKPU */
#define GPIO_NXP_S32_DEVICE_INIT(n) \
GPIO_NXP_S32_SET_EIRQ_INFO(n) \
GPIO_NXP_S32_SET_WKPU_INFO(n) \
static const struct gpio_nxp_s32_config gpio_nxp_s32_config_##n = { \
.common = { \
.port_pin_mask = GPIO_NXP_S32_PORT_PIN_MASK(n), \
}, \
.gpio_base = DT_INST_REG_ADDR_BY_NAME(n, pgpdo), \
.port_base = DT_INST_REG_ADDR_BY_NAME(n, mscr), \
GPIO_NXP_S32_GET_EIRQ_INFO(n) \
GPIO_NXP_S32_GET_WKPU_INFO(n) \
}; \
static struct gpio_nxp_s32_data gpio_nxp_s32_data_##n; \
static int gpio_nxp_s32_init_##n(const struct device *dev) \
{ \
return 0; \
} \
DEVICE_DT_INST_DEFINE(n, \
gpio_nxp_s32_init_##n, \
NULL, \
&gpio_nxp_s32_data_##n, \
&gpio_nxp_s32_config_##n, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_nxp_s32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NXP_S32_DEVICE_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,134 |
```unknown
config GPIO_SMARTBOND
bool "Renesas SmartBond(tm) GPIO driver"
default y
depends on DT_HAS_RENESAS_SMARTBOND_GPIO_ENABLED
help
Enable GPIO driver for Renesas SmartBond(tm) MCU family.
``` | /content/code_sandbox/drivers/gpio/Kconfig.smartbond | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config GPIO_SN74HC595
bool "SN74HC595 shift register as GPIO extender"
default y
depends on DT_HAS_TI_SN74HC595_ENABLED
depends on SPI
help
Use SN74HC595 as GPIO extender
if GPIO_SN74HC595
config GPIO_SN74HC595_INIT_PRIORITY
int "Init priority"
default 71
help
Device driver initialization priority.
endif
``` | /content/code_sandbox/drivers/gpio/Kconfig.sn74hc595 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Microchip PolarFire SoC Icicle Kit GPIO configuration options
config GPIO_MCHP_MSS
bool "Microchip PolarFire SoC GPIO driver"
default y
depends on DT_HAS_MICROCHIP_MPFS_GPIO_ENABLED
help
Enable PolarFire SoC Icicle Kit GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.mchp_mss | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
config GPIO_GD32
bool "GD32 GPIO driver"
default y
depends on DT_HAS_GD_GD32_GPIO_ENABLED
select GD32_EXTI
help
Enable the GD32 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
# Emulated GPIO configuration options
config GPIO_EMUL
bool "Emulated GPIO driver"
default y
depends on DT_HAS_ZEPHYR_GPIO_EMUL_ENABLED
help
Enable the emulated GPIO driver. Mainly used for testing, this
driver allows for an arbitrary number of emulated GPIO controllers
to be instantiated. Furthermore, the emulated pins can be "wired"
using the regular GPIO callback API and the additional API
available in drivers/gpio/gpio_emul.h . Configuration for each
GPIO instance is accomplished using device tree and an example of
such a configuration is in
tests/drivers/gpio/gpio_basic_api/boards/native_sim.overlay
If unsure, say N.
``` | /content/code_sandbox/drivers/gpio/Kconfig.emul | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```c
/*
*
*/
#define DT_DRV_COMPAT cypress_cy8c95xx_gpio_port
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(cy8c95xx, CONFIG_GPIO_LOG_LEVEL);
#include <zephyr/drivers/gpio/gpio_utils.h>
/** Cache of the output configuration and data of the pins. */
struct cy8c95xx_pin_state {
uint8_t dir;
uint8_t data_out;
uint8_t pull_up;
uint8_t pull_down;
};
/** Runtime driver data */
struct cy8c95xx_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct cy8c95xx_pin_state pin_state;
struct k_sem *lock;
};
/** Configuration data */
struct cy8c95xx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec i2c;
uint8_t port_num;
};
#define CY8C95XX_REG_INPUT_DATA0 0x00
#define CY8C95XX_REG_OUTPUT_DATA0 0x08
#define CY8C95XX_REG_PORT_SELECT 0x18
#define CY8C95XX_REG_DIR 0x1C
#define CY8C95XX_REG_PULL_UP 0x1D
#define CY8C95XX_REG_PULL_DOWN 0x1E
#define CY8C95XX_REG_ID 0x2E
static int write_pin_state(const struct cy8c95xx_config *cfg, struct cy8c95xx_pin_state *pins)
{
int rc;
rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_OUTPUT_DATA0 + cfg->port_num,
pins->data_out);
if (rc) {
return rc;
}
rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_PORT_SELECT, cfg->port_num);
if (rc) {
return rc;
}
rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_DIR, pins->dir);
if (rc) {
return rc;
}
rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_PULL_UP, pins->pull_up);
if (rc) {
return rc;
}
rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_PULL_DOWN, pins->pull_down);
return rc;
}
static int cy8c95xx_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct cy8c95xx_config *cfg = dev->config;
struct cy8c95xx_drv_data *drv_data = dev->data;
struct cy8c95xx_pin_state *pins = &drv_data->pin_state;
int rc = 0;
uint32_t io_flags;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
/* Open-drain not implemented */
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP;
}
WRITE_BIT(pins->pull_up, pin, (flags & GPIO_PULL_UP) != 0U);
WRITE_BIT(pins->pull_down, pin, (flags & GPIO_PULL_DOWN) != 0U);
/* Disconnected pin not implemented*/
io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
if (io_flags == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
k_sem_take(drv_data->lock, K_FOREVER);
if ((flags & GPIO_OUTPUT) != 0) {
pins->dir &= ~BIT(pin);
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
pins->data_out &= ~BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
pins->data_out |= BIT(pin);
}
} else {
pins->dir |= BIT(pin);
}
LOG_DBG("CFG %u %x : DIR %04x ; DAT %04x",
pin, flags, pins->dir, pins->data_out);
rc = write_pin_state(cfg, pins);
k_sem_give(drv_data->lock);
return rc;
}
static int port_get(const struct device *dev,
gpio_port_value_t *value)
{
const struct cy8c95xx_config *cfg = dev->config;
struct cy8c95xx_drv_data *drv_data = dev->data;
uint8_t pin_data = 0;
int rc = 0;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(drv_data->lock, K_FOREVER);
rc = i2c_reg_read_byte_dt(&cfg->i2c, CY8C95XX_REG_INPUT_DATA0 + cfg->port_num, &pin_data);
if (rc == 0) {
*value = pin_data;
}
k_sem_give(drv_data->lock);
return rc;
}
static int port_write(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value,
gpio_port_value_t toggle)
{
const struct cy8c95xx_config *cfg = dev->config;
struct cy8c95xx_drv_data *drv_data = dev->data;
uint8_t *outp = &drv_data->pin_state.data_out;
uint8_t out = ((*outp & ~mask) | (value & mask)) ^ toggle;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(drv_data->lock, K_FOREVER);
int rc = i2c_reg_write_byte_dt(&cfg->i2c, CY8C95XX_REG_OUTPUT_DATA0 + cfg->port_num, out);
if (rc == 0) {
*outp = out;
}
k_sem_give(drv_data->lock);
LOG_DBG("write msk %04x val %04x tog %04x => %04x: %d",
mask, value, toggle, out, rc);
return rc;
}
static int port_set_masked(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return port_write(dev, mask, value, 0);
}
static int port_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, pins, 0);
}
static int port_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, 0, 0);
}
static int port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, 0, 0, pins);
}
/**
* @brief Initialization function of CY8C95XX
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int cy8c95xx_init(const struct device *dev)
{
const struct cy8c95xx_config *cfg = dev->config;
struct cy8c95xx_drv_data *drv_data = dev->data;
int rc;
uint8_t data = 0;
k_sem_take(drv_data->lock, K_FOREVER);
if (!device_is_ready(cfg->i2c.bus)) {
LOG_ERR("%s is not ready", cfg->i2c.bus->name);
rc = -ENODEV;
goto out;
}
rc = i2c_reg_read_byte_dt(&cfg->i2c, CY8C95XX_REG_ID, &data);
if (rc) {
goto out;
}
LOG_DBG("cy8c95xx device ID %02X", data & 0xF0);
if ((data & 0xF0) != 0x20) {
LOG_WRN("driver only support [0-2] ports operations");
}
/* Reset state mediated by initial configuration */
drv_data->pin_state = (struct cy8c95xx_pin_state) {
.dir = 0xFF,
.data_out = 0xFF,
.pull_up = 0xFF,
.pull_down = 0x00,
};
rc = write_pin_state(cfg, &drv_data->pin_state);
out:
if (rc != 0) {
LOG_ERR("%s init failed: %d", dev->name, rc);
} else {
LOG_DBG("%s init ok", dev->name);
}
k_sem_give(drv_data->lock);
return rc;
}
static const struct gpio_driver_api api_table = {
.pin_configure = cy8c95xx_config,
.port_get_raw = port_get,
.port_set_masked_raw = port_set_masked,
.port_set_bits_raw = port_set_bits,
.port_clear_bits_raw = port_clear_bits,
.port_toggle_bits = port_toggle_bits,
};
static struct k_sem cy8c95xx_lock = Z_SEM_INITIALIZER(cy8c95xx_lock, 1, 1);
#define GPIO_PORT_INIT(idx) \
static const struct cy8c95xx_config cy8c95xx_##idx##_cfg = { \
.common = { \
.port_pin_mask = 0xFF, \
}, \
.i2c = I2C_DT_SPEC_GET(DT_PARENT(DT_INST(idx, DT_DRV_COMPAT))), \
.port_num = DT_INST_REG_ADDR(idx), \
}; \
static struct cy8c95xx_drv_data cy8c95xx_##idx##_drvdata = { \
.lock = &cy8c95xx_lock, \
}; \
DEVICE_DT_INST_DEFINE(idx, cy8c95xx_init, NULL, \
&cy8c95xx_##idx##_drvdata, &cy8c95xx_##idx##_cfg, \
POST_KERNEL, CONFIG_GPIO_CY8C95XX_INIT_PRIORITY, \
&api_table);
DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_cy8c95xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,242 |
```c
/*
*
*/
#define DT_DRV_COMPAT brcm_brcmstb_gpio
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define GIO_DATA 0x04
#define GIO_IODIR 0x08
#define DEV_CFG(dev) ((const struct gpio_brcmstb_config *)(dev)->config)
#define DEV_DATA(dev) ((struct gpio_brcmstb_data *)(dev)->data)
struct gpio_brcmstb_config {
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(reg_base);
mem_addr_t offset;
};
struct gpio_brcmstb_data {
struct gpio_driver_data common;
DEVICE_MMIO_NAMED_RAM(reg_base);
mem_addr_t base;
};
static int gpio_brcmstb_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
{
struct gpio_brcmstb_data *data = port->data;
if (flags & (GPIO_SINGLE_ENDED | GPIO_PULL_UP | GPIO_PULL_DOWN)) {
return -ENOTSUP;
}
if (flags & GPIO_INPUT) {
sys_set_bit(data->base + GIO_IODIR, pin);
} else if (flags & GPIO_OUTPUT) {
sys_clear_bit(data->base + GIO_IODIR, pin);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
sys_set_bit(data->base + GIO_DATA, pin);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
sys_clear_bit(data->base + GIO_DATA, pin);
}
}
return 0;
}
static int gpio_brcmstb_port_get_raw(const struct device *port, gpio_port_value_t *value)
{
struct gpio_brcmstb_data *data = port->data;
*value = sys_read32(data->base + GIO_DATA);
return 0;
}
static int gpio_brcmstb_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask,
gpio_port_value_t value)
{
struct gpio_brcmstb_data *data = port->data;
sys_clear_bits(data->base + GIO_DATA, mask);
sys_set_bits(data->base + GIO_DATA, (value & mask));
return 0;
}
static int gpio_brcmstb_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
struct gpio_brcmstb_data *data = port->data;
sys_set_bits(data->base + GIO_DATA, pins);
return 0;
}
static int gpio_brcmstb_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
struct gpio_brcmstb_data *data = port->data;
sys_clear_bits(data->base + GIO_DATA, pins);
return 0;
}
static int gpio_brcmstb_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
{
struct gpio_brcmstb_data *data = port->data;
uint32_t reg_data;
reg_data = sys_read32(data->base + GIO_DATA);
reg_data ^= pins;
sys_write32(reg_data, data->base + GIO_DATA);
return 0;
}
static const struct gpio_driver_api gpio_brcmstb_api = {
.pin_configure = gpio_brcmstb_pin_configure,
.port_get_raw = gpio_brcmstb_port_get_raw,
.port_set_masked_raw = gpio_brcmstb_port_set_masked_raw,
.port_set_bits_raw = gpio_brcmstb_port_set_bits_raw,
.port_clear_bits_raw = gpio_brcmstb_port_clear_bits_raw,
.port_toggle_bits = gpio_brcmstb_port_toggle_bits,
};
int gpio_brcmstb_init(const struct device *port)
{
const struct gpio_brcmstb_config *config = port->config;
struct gpio_brcmstb_data *data = port->data;
DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE);
data->base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->offset;
return 0;
}
#define GPIO_BRCMSTB_INIT(n) \
static struct gpio_brcmstb_data gpio_brcmstb_data_##n; \
\
static const struct gpio_brcmstb_config gpio_brcmstb_cfg_##n = { \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}, \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
.offset = DT_INST_REG_ADDR(n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, gpio_brcmstb_init, NULL, &gpio_brcmstb_data_##n, \
&gpio_brcmstb_cfg_##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_brcmstb_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_BRCMSTB_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_brcmstb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,112 |
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