text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc_gpio_port
/** @file
* @brief GPIO driver for LPC54XXX family
*
* Note:
* - fsl_pint internally tries to manage interrupts, but this is not used (e.g.
* s_pintCallback), Zephyr's interrupt management system is used in place.
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <fsl_common.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#ifdef CONFIG_NXP_PINT
#include <zephyr/drivers/interrupt_controller/nxp_pint.h>
#endif
#include <fsl_gpio.h>
#include <fsl_device_registers.h>
#ifdef MCI_IO_MUX
#include <zephyr/drivers/pinctrl.h>
#endif
/* Interrupt sources, matching int-source enum in DTS binding definition */
#define INT_SOURCE_PINT 0
#define INT_SOURCE_INTA 1
#define INT_SOURCE_INTB 2
#define INT_SOURCE_NONE 3
struct gpio_mcux_lpc_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Type *gpio_base;
uint8_t int_source;
#ifdef IOPCTL
IOPCTL_Type *pinmux_base;
#endif
#ifdef IOCON
IOCON_Type *pinmux_base;
#endif
#ifdef MCI_IO_MUX
MCI_IO_MUX_Type * pinmux_base;
#endif
uint32_t port_no;
};
struct gpio_mcux_lpc_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
uint32_t port = config->port_no;
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
#ifdef IOPCTL /* RT600 and RT500 series */
IOPCTL_Type *pinmux_base = config->pinmux_base;
volatile uint32_t *pinconfig = (volatile uint32_t *)&(pinmux_base->PIO[port][pin]);
/*
* Enable input buffer for both input and output pins, it costs
* nothing and allows values to be read back.
*/
*pinconfig |= IOPCTL_PIO_INBUF_EN;
if ((flags & GPIO_SINGLE_ENDED) != 0) {
*pinconfig |= IOPCTL_PIO_PSEDRAIN_EN;
} else {
*pinconfig &= ~IOPCTL_PIO_PSEDRAIN_EN;
}
/* Select GPIO mux for this pin (func 0 is always GPIO) */
*pinconfig &= ~(IOPCTL_PIO_FSEL_MASK);
#endif
#ifdef IOCON /* LPC SOCs */
volatile uint32_t *pinconfig;
IOCON_Type *pinmux_base;
pinmux_base = config->pinmux_base;
pinconfig = (volatile uint32_t *)&(pinmux_base->PIO[port][pin]);
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit. */
*pinconfig |= IOCON_PIO_OD_MASK;
}
if ((flags & GPIO_INPUT) != 0) {
/* Set DIGIMODE bit */
*pinconfig |= IOCON_PIO_DIGIMODE_MASK;
}
/* Select GPIO mux for this pin (func 0 is always GPIO) */
*pinconfig &= ~(IOCON_PIO_FUNC_MASK);
#endif
#ifdef MCI_IO_MUX /* RW61x SOCs */
/* Construct a pin control state, and apply it directly. */
pinctrl_soc_pin_t pin_cfg;
if (config->port_no == 1) {
pin_cfg = IOMUX_GPIO_IDX(pin + 32) | IOMUX_TYPE(IOMUX_GPIO);
} else {
pin_cfg = IOMUX_GPIO_IDX(pin) | IOMUX_TYPE(IOMUX_GPIO);
}
/* Add pull up flags, if required */
if ((flags & GPIO_PULL_UP) != 0) {
pin_cfg |= IOMUX_PAD_PULL(0x1);
} else if ((flags & GPIO_PULL_DOWN) != 0) {
pin_cfg |= IOMUX_PAD_PULL(0x2);
}
pinctrl_configure_pins(&pin_cfg, 1, 0);
#endif
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
#ifdef IOPCTL /* RT600 and RT500 series */
*pinconfig |= IOPCTL_PIO_PUPD_EN;
if ((flags & GPIO_PULL_UP) != 0) {
*pinconfig |= IOPCTL_PIO_PULLUP_EN;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
*pinconfig &= ~(IOPCTL_PIO_PULLUP_EN);
}
#endif
#ifdef IOCON /* LPC SOCs */
*pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN);
if ((flags & GPIO_PULL_UP) != 0) {
*pinconfig |= IOCON_PIO_MODE_PULLUP;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
*pinconfig |= IOCON_PIO_MODE_PULLDOWN;
}
#endif
} else {
#ifdef IOPCTL /* RT600 and RT500 series */
*pinconfig &= ~IOPCTL_PIO_PUPD_EN;
#endif
#ifdef IOCON /* LPC SOCs */
*pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN);
#endif
#ifdef MCI_IO_MUX
#endif
}
/* supports access by pin now,you can add access by port when needed */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_base->SET[port] = BIT(pin);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_base->CLR[port] = BIT(pin);
}
/* input-0,output-1 */
WRITE_BIT(gpio_base->DIR[port], pin, flags & GPIO_OUTPUT);
return 0;
}
static int gpio_mcux_lpc_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
*value = gpio_base->PIN[config->port_no];
return 0;
}
static int gpio_mcux_lpc_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
uint32_t port = config->port_no;
/* Writing 0 allows R+W, 1 disables the pin */
gpio_base->MASK[port] = ~mask;
gpio_base->MPIN[port] = value;
/* Enable back the pins, user won't assume pins remain masked*/
gpio_base->MASK[port] = 0U;
return 0;
}
static int gpio_mcux_lpc_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->SET[config->port_no] = mask;
return 0;
}
static int gpio_mcux_lpc_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->CLR[config->port_no] = mask;
return 0;
}
static int gpio_mcux_lpc_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
gpio_base->NOT[config->port_no] = mask;
return 0;
}
#ifdef CONFIG_NXP_PINT
/* Called by PINT when pin interrupt fires */
static void gpio_mcux_lpc_pint_cb(uint8_t pin, void *user)
{
const struct device *dev = user;
const struct gpio_mcux_lpc_config *config = dev->config;
struct gpio_mcux_lpc_data *data = dev->data;
uint32_t gpio_pin;
/* Subtract port number times 32 from pin number to get GPIO API
* pin number.
*/
gpio_pin = pin - (config->port_no * 32);
gpio_fire_callbacks(&data->callbacks, dev, BIT(gpio_pin));
}
/* Installs interrupt handler using PINT interrupt controller. */
static int gpio_mcux_lpc_pint_interrupt_cfg(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_mcux_lpc_config *config = dev->config;
enum nxp_pint_trigger interrupt_mode = NXP_PINT_NONE;
uint32_t port = config->port_no;
int ret;
switch (mode) {
case GPIO_INT_MODE_DISABLED:
nxp_pint_pin_disable((port * 32) + pin);
return 0;
case GPIO_INT_MODE_LEVEL:
if (trig == GPIO_INT_TRIG_HIGH) {
interrupt_mode = NXP_PINT_HIGH;
} else if (trig == GPIO_INT_TRIG_LOW) {
interrupt_mode = NXP_PINT_LOW;
} else {
return -ENOTSUP;
}
break;
case GPIO_INT_MODE_EDGE:
if (trig == GPIO_INT_TRIG_HIGH) {
interrupt_mode = NXP_PINT_RISING;
} else if (trig == GPIO_INT_TRIG_LOW) {
interrupt_mode = NXP_PINT_FALLING;
} else {
interrupt_mode = NXP_PINT_BOTH;
}
break;
default:
return -ENOTSUP;
}
/* PINT treats GPIO pins as continuous. Each port has 32 pins */
ret = nxp_pint_pin_enable((port * 32) + pin, interrupt_mode, (trig & GPIO_INT_WAKEUP));
if (ret < 0) {
return ret;
}
/* Install callback */
return nxp_pint_pin_set_callback((port * 32) + pin,
gpio_mcux_lpc_pint_cb,
(struct device *)dev);
}
#endif /* CONFIG_NXP_PINT */
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
static int gpio_mcux_lpc_module_interrupt_cfg(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_mcux_lpc_config *config = dev->config;
gpio_interrupt_index_t int_idx;
gpio_interrupt_config_t pin_config;
if (config->int_source == INT_SOURCE_NONE) {
return -ENOTSUP;
}
/* Route interrupt to source A or B based on interrupt source */
int_idx = (config->int_source == INT_SOURCE_INTA) ?
kGPIO_InterruptA : kGPIO_InterruptB;
/* Disable interrupt if requested */
if (mode == GPIO_INT_MODE_DISABLED) {
GPIO_PinDisableInterrupt(config->gpio_base, config->port_no, pin, int_idx);
return 0;
}
/* Set pin interrupt level */
if (mode == GPIO_INT_MODE_LEVEL) {
pin_config.mode = kGPIO_PinIntEnableLevel;
} else if (mode == GPIO_INT_MODE_EDGE) {
pin_config.mode = kGPIO_PinIntEnableEdge;
} else {
return -ENOTSUP;
}
/* Set pin interrupt trigger */
if (trig == GPIO_INT_TRIG_HIGH) {
pin_config.polarity = kGPIO_PinIntEnableHighOrRise;
} else if (trig == GPIO_INT_TRIG_LOW) {
pin_config.polarity = kGPIO_PinIntEnableLowOrFall;
} else {
return -ENOTSUP;
}
/* Enable interrupt with new configuration */
GPIO_SetPinInterruptConfig(config->gpio_base, config->port_no, pin, &pin_config);
GPIO_PinEnableInterrupt(config->gpio_base, config->port_no, pin, int_idx);
return 0;
}
/* GPIO module interrupt handler */
void gpio_mcux_lpc_module_isr(const struct device *dev)
{
const struct gpio_mcux_lpc_config *config = dev->config;
struct gpio_mcux_lpc_data *data = dev->data;
uint32_t status;
status = GPIO_PortGetInterruptStatus(config->gpio_base,
config->port_no,
config->int_source == INT_SOURCE_INTA ?
kGPIO_InterruptA : kGPIO_InterruptB);
GPIO_PortClearInterruptFlags(config->gpio_base,
config->port_no,
config->int_source == INT_SOURCE_INTA ?
kGPIO_InterruptA : kGPIO_InterruptB,
status);
gpio_fire_callbacks(&data->callbacks, dev, status);
}
#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
static int gpio_mcux_lpc_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_Type *gpio_base = config->gpio_base;
uint32_t port = config->port_no;
/* Ensure pin used as interrupt is set as input*/
if ((mode & GPIO_INT_ENABLE) &&
((gpio_base->DIR[port] & BIT(pin)) != 0)) {
return -ENOTSUP;
}
#if defined(CONFIG_NXP_PINT)
if (config->int_source == INT_SOURCE_PINT) {
return gpio_mcux_lpc_pint_interrupt_cfg(dev, pin, mode, trig);
}
#endif /* CONFIG_NXP_PINT */
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
return gpio_mcux_lpc_module_interrupt_cfg(dev, pin, mode, trig);
#else
return -ENOTSUP;
#endif
}
static int gpio_mcux_lpc_manage_cb(const struct device *port,
struct gpio_callback *callback, bool set)
{
struct gpio_mcux_lpc_data *data = port->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static int gpio_mcux_lpc_init(const struct device *dev)
{
const struct gpio_mcux_lpc_config *config = dev->config;
GPIO_PortInit(config->gpio_base, config->port_no);
return 0;
}
static const struct gpio_driver_api gpio_mcux_lpc_driver_api = {
.pin_configure = gpio_mcux_lpc_configure,
.port_get_raw = gpio_mcux_lpc_port_get_raw,
.port_set_masked_raw = gpio_mcux_lpc_port_set_masked_raw,
.port_set_bits_raw = gpio_mcux_lpc_port_set_bits_raw,
.port_clear_bits_raw = gpio_mcux_lpc_port_clear_bits_raw,
.port_toggle_bits = gpio_mcux_lpc_port_toggle_bits,
.pin_interrupt_configure = gpio_mcux_lpc_pin_interrupt_configure,
.manage_callback = gpio_mcux_lpc_manage_cb,
};
#ifdef IOPCTL
#define PINMUX_BASE IOPCTL
#endif
#ifdef IOCON
#define PINMUX_BASE IOCON
#endif
#ifdef MCI_IO_MUX
#define PINMUX_BASE MCI_IO_MUX
#endif
#define GPIO_MCUX_LPC_MODULE_IRQ_CONNECT(inst) \
do { \
IRQ_CONNECT(DT_INST_IRQ(inst, irq), \
DT_INST_IRQ(inst, priority), \
gpio_mcux_lpc_module_isr, DEVICE_DT_INST_GET(inst), 0); \
irq_enable(DT_INST_IRQ(inst, irq)); \
} while (false)
#define GPIO_MCUX_LPC_MODULE_IRQ(inst) \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(inst, 0), \
(GPIO_MCUX_LPC_MODULE_IRQ_CONNECT(inst)))
#define GPIO_MCUX_LPC(n) \
static int lpc_gpio_init_##n(const struct device *dev); \
\
static const struct gpio_mcux_lpc_config gpio_mcux_lpc_config_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.gpio_base = (GPIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
.pinmux_base = PINMUX_BASE, \
.int_source = DT_INST_ENUM_IDX(n, int_source), \
.port_no = DT_INST_REG_ADDR(n) \
}; \
\
static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, lpc_gpio_init_##n, NULL, \
&gpio_mcux_lpc_data_##n, \
&gpio_mcux_lpc_config_##n, PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_mcux_lpc_driver_api); \
\
static int lpc_gpio_init_##n(const struct device *dev) \
{ \
gpio_mcux_lpc_init(dev); \
GPIO_MCUX_LPC_MODULE_IRQ(n); \
\
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_MCUX_LPC)
``` | /content/code_sandbox/drivers/gpio/gpio_mcux_lpc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,822 |
```unknown
# Synopsys GPIO via CREG (Control REGisters) driver
config GPIO_SNPS_CREG
bool "SNPS CREG GPIO"
default y
depends on DT_HAS_SNPS_CREG_GPIO_ENABLED
help
Enable driver for SNPS CREG GPIO.
``` | /content/code_sandbox/drivers/gpio/Kconfig.creg_gpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_gpio
/**
* @file
* @brief Intel GPIO Controller Driver
*
* The GPIO controller on Intel SoC serves
* both GPIOs and Pinmuxing function. This driver provides
* the GPIO function.
*
* Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
* each set is further sub-divided into multiple devices, so
* we export GPIO_INTEL_NR_SUBDEVS devices to the kernel.
*/
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <soc.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/slist.h>
#include <zephyr/sys/speculation.h>
#include <zephyr/irq.h>
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
#include <zephyr/acpi/acpi.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define REG_MISCCFG 0x0010
#define MISCCFG_IRQ_ROUTE_POS 3
#define PAD_OWN_MASK 0x03
#define PAD_OWN_HOST 0
#define PAD_OWN_CSME 1
#define PAD_OWN_ISH 2
#define PAD_OWN_IE 3
#define PAD_HOST_SW_OWN_GPIO 1
#define PAD_HOST_SW_OWN_ACPI 0
#define PAD_CFG0_RXPADSTSEL BIT(29)
#define PAD_CFG0_RXRAW1 BIT(28)
#define PAD_CFG0_RXEVCFG_POS 25
#define PAD_CFG0_RXEVCFG_MASK (0x03 << PAD_CFG0_RXEVCFG_POS)
#define PAD_CFG0_RXEVCFG_LEVEL (0 << PAD_CFG0_RXEVCFG_POS)
#define PAD_CFG0_RXEVCFG_EDGE (1 << PAD_CFG0_RXEVCFG_POS)
#define PAD_CFG0_RXEVCFG_DRIVE0 (2 << PAD_CFG0_RXEVCFG_POS)
#define PAD_CFG0_PREGFRXSEL BIT(24)
#define PAD_CFG0_RXINV BIT(23)
#define PAD_CFG0_RXDIS BIT(9)
#define PAD_CFG0_TXDIS BIT(8)
#define PAD_CFG0_RXSTATE BIT(1)
#define PAD_CFG0_RXSTATE_POS 1
#define PAD_CFG0_TXSTATE BIT(0)
#define PAD_CFG0_TXSTATE_POS 0
#define PAD_CFG1_IOSTERM_POS 8
#define PAD_CFG1_IOSTERM_MASK (0x03 << PAD_CFG1_IOSTERM_POS)
#define PAD_CFG1_IOSTERM_FUNC (0 << PAD_CFG1_IOSTERM_POS)
#define PAD_CFG1_IOSTERM_DISPUD (1 << PAD_CFG1_IOSTERM_POS)
#define PAD_CFG1_IOSTERM_PU (2 << PAD_CFG1_IOSTERM_POS)
#define PAD_CFG1_IOSTERM_PD (3 << PAD_CFG1_IOSTERM_POS)
#define PAD_CFG1_TERM_POS 10
#define PAD_CFG1_TERM_MASK (0x0F << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_NONE (0x00 << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PD_5K (0x02 << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PD_20K (0x04 << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_NONE2 (0x08 << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PU_1K (0x09 << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PU_5K (0x0A << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PU_2K (0x0B << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PU_20K (0x0C << PAD_CFG1_TERM_POS)
#define PAD_CFG1_TERM_PU_1K_2K (0x0D << PAD_CFG1_TERM_POS)
#define PAD_CFG1_IOSSTATE_POS 14
#define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
#define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
/* Required by DEVICE_MMIO_NAMED_* macros */
#define DEV_CFG(_dev) \
((const struct gpio_intel_config *)(_dev)->config)
#define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
struct gpio_intel_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(reg_base);
#if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
uint8_t pin_offset;
uint8_t group_index;
uint8_t num_pins;
#endif
};
struct gpio_intel_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
DEVICE_MMIO_NAMED_RAM(reg_base);
/* Pad base address */
uint32_t pad_base;
sys_slist_t cb;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
uint32_t num_pins;
uint32_t pad_owner_reg;
uint32_t host_owner_reg;
uint32_t intr_stat_reg;
uint32_t base_num;
#endif
};
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
#define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
#define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
#define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
#define PIN_OFFSET_GET(dev) (0)
#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
#define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
#define GPIO_BASE_GET(cdf) (0)
#define GPIO_INTERRUPT_BASE_GET(cfg) (0)
#define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
#else /* Non-ACPI */
#define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
#define REG_GPI_INT_STS_BASE_GET(data) REG_GPI_INT_STS_BASE
#define REG_GPI_INT_EN_BASE_GET(data) REG_GPI_INT_EN_BASE
#define PIN_OFFSET_GET(dev) ((const struct gpio_intel_config *)(dev)->config)->pin_offset
#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) GPIO_PAD_OWNERSHIP(pin, offset)
#define REG_PAD_HOST_SW_OWNER_GET(data) REG_PAD_HOST_SW_OWNER
#define GPIO_BASE_GET(cdf) GPIO_BASE(((const struct gpio_intel_config *)(dev)->config))
#define GPIO_INTERRUPT_BASE_GET(cfg) GPIO_INTERRUPT_BASE(cfg)
#define GPIO_GET_PIN_MAX(dev) ((const struct gpio_intel_config *)(dev)->config)->num_pins
#endif
static inline mm_reg_t regs(const struct device *dev)
{
return GPIO_REG_BASE_GET(dev);
}
#if !DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
static inline mm_reg_t pad_base(const struct device *dev)
{
return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base));
}
#endif
#ifdef CONFIG_GPIO_INTEL_CHECK_PERMS
/**
* @brief Check if host has permission to alter this GPIO pin.
*
* @param "struct device *dev" Device struct
* @param "uint32_t raw_pin" Raw GPIO pin
*
* @return true if host owns the GPIO pin, false otherwise
*/
static bool check_perm(const struct device *dev, uint32_t raw_pin)
{
struct gpio_intel_data *data = dev->data;
uint32_t offset, val, pin_offset;
pin_offset = PIN_OFFSET_GET(dev);
/* First is to establish that host software owns the pin */
/* read the Pad Ownership register related to the pin */
offset = GPIO_PAD_OWNERSHIP_GET(data, raw_pin, pin_offset);
val = sys_read32(regs(dev) + offset);
/* get the bits about ownership */
offset = GPIO_OWNERSHIP_BIT(raw_pin);
val = (val >> offset) & PAD_OWN_MASK;
if (val) {
/* PAD_OWN_HOST == 0, so !0 => false*/
return false;
}
/* Also need to make sure the function of pad is GPIO */
offset = data->pad_base + (raw_pin << 4);
val = sys_read32(regs(dev) + offset);
if (val & PAD_CFG0_PMODE_MASK) {
/* mode is not zero => not functioning as GPIO */
return false;
}
return true;
}
#else
#define check_perm(...) (1)
#endif
/*
* as the kernel initializes the subdevices, we add them
* to the list of devices to check at ISR time.
*/
static bool first_inst = true;
static void gpio_intel_isr(const struct device *dev)
{
const struct gpio_intel_config *cfg;
struct gpio_intel_data *data;
struct gpio_callback *cb, *tmp;
uint32_t reg, int_sts, cur_mask, acc_mask;
cfg = dev->config;
data = dev->data;
reg = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_INTERRUPT_BASE_GET(cfg);
int_sts = sys_read32(reg);
acc_mask = 0U;
SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {
cur_mask = int_sts & cb->pin_mask;
acc_mask |= cur_mask;
if (cur_mask) {
__ASSERT(cb->handler, "No callback handler!");
cb->handler(dev, cb, cur_mask);
}
}
/* clear handled interrupt bits */
sys_write32(acc_mask, reg);
}
static int gpio_intel_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
struct gpio_intel_data *data = dev->data;
uint32_t raw_pin, reg, cfg0, cfg1;
/* Only support push-pull mode */
if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP;
}
pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);
raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
if (!check_perm(dev, raw_pin)) {
return -EINVAL;
}
/* read in pad configuration register */
reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
cfg0 = sys_read32(reg);
cfg1 = sys_read32(reg + 4);
/* don't override RX to 1 */
cfg0 &= ~(PAD_CFG0_RXRAW1);
/* set input/output */
if ((flags & GPIO_INPUT) != 0U) {
/* clear RX disable bit */
cfg0 &= ~PAD_CFG0_RXDIS;
} else {
/* set RX disable bit */
cfg0 |= PAD_CFG0_RXDIS;
}
if ((flags & GPIO_OUTPUT) != 0U) {
/* pin to output */
/* set pin output if desired */
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
cfg0 |= PAD_CFG0_TXSTATE;
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
cfg0 &= ~PAD_CFG0_TXSTATE;
}
/* clear TX disable bit */
cfg0 &= ~PAD_CFG0_TXDIS;
} else {
/* set TX disable bit */
cfg0 |= PAD_CFG0_TXDIS;
}
/* pull-up or pull-down */
cfg1 &= ~(PAD_CFG1_TERM_MASK | PAD_CFG1_IOSTERM_MASK);
if ((flags & GPIO_PULL_UP) != 0U) {
cfg1 |= (PAD_CFG1_TERM_PU_20K | PAD_CFG1_IOSTERM_PU);
} else if ((flags & GPIO_PULL_DOWN) != 0U) {
cfg1 |= (PAD_CFG1_TERM_PD_20K | PAD_CFG1_IOSTERM_PD);
} else {
cfg1 |= (PAD_CFG1_TERM_NONE | PAD_CFG1_IOSTERM_FUNC);
}
/* IO Standby state to TX,RX enabled */
cfg1 &= ~PAD_CFG1_IOSSTATE_MASK;
/* write back pad configuration register after all changes */
sys_write32(cfg0, reg);
sys_write32(cfg1, reg + 4);
return 0;
}
static int gpio_intel_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
struct gpio_intel_data *data = dev->data;
uint32_t raw_pin, cfg0, cfg1;
uint32_t reg, reg_en, reg_sts;
/* no double-edge triggering according to data sheet */
if (trig == GPIO_INT_TRIG_BOTH) {
return -ENOTSUP;
}
pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);
raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
if (!check_perm(dev, raw_pin)) {
return -EINVAL;
}
/* set owner to GPIO driver mode for legacy interrupt mode */
reg = regs(dev) + REG_PAD_HOST_SW_OWNER_GET(data) + GPIO_BASE_GET(dev);
sys_bitfield_set_bit(reg, raw_pin);
/* read in pad configuration register */
reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
cfg0 = sys_read32(reg);
cfg1 = sys_read32(reg + 4);
reg_en = regs(dev) + REG_GPI_INT_EN_BASE_GET(data) + GPIO_BASE_GET(dev);
/* disable interrupt bit first before setup */
sys_bitfield_clear_bit(reg_en, raw_pin);
/* clear (by setting) interrupt status bit */
reg_sts = regs(dev) + REG_GPI_INT_STS_BASE_GET(data) + GPIO_BASE_GET(dev);
sys_bitfield_set_bit(reg_sts, raw_pin);
/* clear level/edge configuration bits */
cfg0 &= ~PAD_CFG0_RXEVCFG_MASK;
if (mode == GPIO_INT_MODE_DISABLED) {
/* set RX conf to drive 0 */
cfg0 |= PAD_CFG0_RXEVCFG_DRIVE0;
} else {
/* cannot enable interrupt without pin as input */
if ((cfg0 & PAD_CFG0_RXDIS) != 0U) {
return -ENOTSUP;
}
/*
* Do not enable interrupt with pin as output.
* Hardware does not seem to support triggering
* interrupt by setting line as both input/output
* and then setting output to desired level.
* So just say not supported.
*/
if ((cfg0 & PAD_CFG0_TXDIS) == 0U) {
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_LEVEL) {
/* level trigger */
cfg0 |= PAD_CFG0_RXEVCFG_LEVEL;
} else {
/* edge trigger */
cfg0 |= PAD_CFG0_RXEVCFG_EDGE;
}
/* invert pin for active low triggering */
if (trig == GPIO_INT_TRIG_LOW) {
cfg0 |= PAD_CFG0_RXINV;
} else {
cfg0 &= ~PAD_CFG0_RXINV;
}
}
/* write back pad configuration register after all changes */
sys_write32(cfg0, reg);
sys_write32(cfg1, reg + 4);
if (mode != GPIO_INT_MODE_DISABLED) {
/* enable interrupt bit */
sys_bitfield_set_bit(reg_en, raw_pin);
}
return 0;
}
static int gpio_intel_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_intel_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static int port_get_raw(const struct device *dev, uint32_t mask,
uint32_t *value,
bool read_tx)
{
struct gpio_intel_data *data = dev->data;
uint32_t pin, raw_pin, reg_addr, reg_val, cmp;
if (read_tx) {
cmp = PAD_CFG0_TXSTATE;
} else {
cmp = PAD_CFG0_RXSTATE;
}
*value = 0;
while (mask != 0U) {
pin = find_lsb_set(mask) - 1;
if (pin >= GPIO_GET_PIN_MAX(dev)) {
break;
}
mask &= ~BIT(pin);
raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
if (!check_perm(dev, raw_pin)) {
continue;
}
reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
reg_val = sys_read32(reg_addr);
if ((reg_val & cmp) != 0U) {
*value |= BIT(pin);
}
}
return 0;
}
static int port_set_raw(const struct device *dev, uint32_t mask,
uint32_t value)
{
struct gpio_intel_data *data = dev->data;
uint32_t pin, raw_pin, reg_addr, reg_val;
while (mask != 0) {
pin = find_lsb_set(mask) - 1;
if (pin >= GPIO_GET_PIN_MAX(dev)) {
break;
}
mask &= ~BIT(pin);
raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));
if (!check_perm(dev, raw_pin)) {
continue;
}
reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);
reg_val = sys_read32(reg_addr);
if ((value & BIT(pin)) != 0) {
reg_val |= PAD_CFG0_TXSTATE;
} else {
reg_val &= ~PAD_CFG0_TXSTATE;
}
sys_write32(reg_val, reg_addr);
}
return 0;
}
static int gpio_intel_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
uint32_t port_val;
port_get_raw(dev, mask, &port_val, true);
port_val = (port_val & ~mask) | (mask & value);
port_set_raw(dev, mask, port_val);
return 0;
}
static int gpio_intel_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_intel_port_set_masked_raw(dev, mask, mask);
}
static int gpio_intel_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_intel_port_set_masked_raw(dev, mask, 0);
}
static int gpio_intel_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
uint32_t port_val;
port_get_raw(dev, mask, &port_val, true);
port_val ^= mask;
port_set_raw(dev, mask, port_val);
return 0;
}
static int gpio_intel_port_get_raw(const struct device *dev,
uint32_t *value)
{
return port_get_raw(dev, 0xFFFFFFFF, value, false);
}
static const struct gpio_driver_api gpio_intel_api = {
.pin_configure = gpio_intel_config,
.manage_callback = gpio_intel_manage_callback,
.port_get_raw = gpio_intel_port_get_raw,
.port_set_masked_raw = gpio_intel_port_set_masked_raw,
.port_set_bits_raw = gpio_intel_port_set_bits_raw,
.port_clear_bits_raw = gpio_intel_port_clear_bits_raw,
.port_toggle_bits = gpio_intel_port_toggle_bits,
.pin_interrupt_configure = gpio_intel_pin_interrupt_configure,
};
/* We need support either DTS or ACPI base resource enumeration at time.*/
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid)
{
int ret;
struct gpio_acpi_res res;
struct gpio_intel_data *data = dev->data;
ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res);
if (ret) {
return ret;
}
device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE);
data->num_pins = res.num_pins;
data->pad_owner_reg = res.pad_owner_reg;
data->host_owner_reg = res.host_owner_reg;
data->intr_stat_reg = res.intr_stat_reg;
data->base_num = res.base_num;
data->pad_base = res.pad_base;
/* Note that all controllers are using the same IRQ line.
* So we can just use the values from the first instance.
*/
if (first_inst) {
irq_connect_dynamic(res.irq, DT_INST_IRQ(0, priority),
(void (*)(const void *))gpio_intel_isr, dev, res.irq_flags);
irq_enable(res.irq);
first_inst = false;
}
if (IS_ENABLED(CONFIG_SOC_APOLLO_LAKE)) {
/* route to IRQ 14 */
sys_bitfield_clear_bit(regs(dev) + REG_MISCCFG, MISCCFG_IRQ_ROUTE_POS);
}
return 0;
}
#define GPIO_INIT_FN_DEFINE(n) \
static int gpio_intel_init##n(const struct device *dev) \
{ \
return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index), \
ACPI_DT_HID(DT_DRV_INST(n)), ACPI_DT_UID(DT_DRV_INST(n))); \
}
#define GPIO_MMIO_ROM_INIT(n)
#define GPIO_INIT_CONFIG(n) \
static const struct gpio_intel_config gpio_intel_cfg_##n = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
}
#else
static int gpio_intel_dts_init(const struct device *dev)
{
struct gpio_intel_data *data = dev->data;
#ifdef CONFIG_SOC_APOLLO_LAKE
/*
* On Apollo Lake, each GPIO controller has more than 32 pins.
* But Zephyr API can only manipulate 32 pins per controller.
* So the workaround is to divide each hardware GPIO controller
* into 32-pin blocks so each block has a GPIO driver instance.
* Compounding to the issue is that there cannot be two device
* tree nodes with same register address. So another workaround
* is to increment the register addresses by 1 for each block.
* So when mapping the address, the lowest 8-bit needs to be
* masked to get the actual hardware address. Hence the weird
* code below.
*/
const struct gpio_intel_config *cfg = dev->config;
device_map(&data->reg_base,
cfg->reg_base.phys_addr & ~0xFFU,
cfg->reg_base.size,
K_MEM_CACHE_NONE);
#else
DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
#endif
data->pad_base = pad_base(dev);
if (first_inst) {
/* Note that all controllers are using the same IRQ line.
* So we can just use the values from the first instance.
*/
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
gpio_intel_isr, dev,
DT_INST_IRQ(0, sense));
irq_enable(DT_INST_IRQN(0));
first_inst = false;
}
if (IS_ENABLED(CONFIG_SOC_APOLLO_LAKE)) {
/* route to IRQ 14 */
sys_bitfield_clear_bit(regs(dev) + REG_MISCCFG,
MISCCFG_IRQ_ROUTE_POS);
}
return 0;
}
#define GPIO_INIT_FN_DEFINE(n) \
static int gpio_intel_init##n(const struct device *dev) \
{ \
return gpio_intel_dts_init(dev); \
}
#define GPIO_MMIO_ROM_INIT(n) DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),
#define GPIO_INIT_CONFIG(n) \
static const struct gpio_intel_config gpio_intel_cfg_##n = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
GPIO_MMIO_ROM_INIT(n).pin_offset = DT_INST_PROP(n, pin_offset), \
.group_index = DT_INST_PROP_OR(n, group_index, 0), \
.num_pins = DT_INST_PROP(n, ngpios), \
}
#endif
#define GPIO_INTEL_DEV_CFG_DATA(n) \
GPIO_INIT_FN_DEFINE(n) \
GPIO_INIT_CONFIG(n); \
static struct gpio_intel_data gpio_intel_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_intel_init##n, NULL, &gpio_intel_data_##n, \
&gpio_intel_cfg_##n, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_intel_api);
/* "sub" devices. no more than GPIO_INTEL_NR_SUBDEVS of these! */
DT_INST_FOREACH_STATUS_OKAY(GPIO_INTEL_DEV_CFG_DATA)
``` | /content/code_sandbox/drivers/gpio/gpio_intel.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,447 |
```unknown
# RV32M1 GPIO configuration options
config GPIO_RV32M1
bool "RV32M1 GPIO driver"
default y
depends on DT_HAS_OPENISA_RV32M1_GPIO_ENABLED
help
Enable the RV32M1 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.rv32m1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# NPCX GPIO driver configuration options
config GPIO_NCT38XX
bool "NCT38XX I2C-based GPIO chip"
default y
depends on DT_HAS_NUVOTON_NCT38XX_GPIO_PORT_ENABLED
select I2C
select MFD
help
Enable driver for NCT38XX I2C-based GPIO chip.
if GPIO_NCT38XX
config GPIO_NCT38XX_INIT_PRIORITY
int "NCT38XX GPIO init priority"
default 82
help
NCT38xx GPIO driver initialization priority. The priority must be lower
than MFD_INIT_PRIORITY.
config GPIO_NCT38XX_PORT_INIT_PRIORITY
int "NCT38XX GPIO port init priority"
default 84
help
NCT38xx GPIO port device driver initialization priority. The priority
must be lower than GPIO_NCT38XX_INIT_PRIORITY device.
config GPIO_NCT38XX_ALERT
bool "NCT38XX GPIO interrupt"
default y
depends on DT_HAS_NUVOTON_NCT38XX_GPIO_ALERT_ENABLED
help
Enable interrupt support in NCT38XX driver.
config GPIO_NCT38XX_ALERT_INIT_PRIORITY
int "NCT38XX GPIO alert handler init priority"
default 84
depends on GPIO_NCT38XX_ALERT
help
NCT38XX alert handler initialization priority. This initialization
must take place after the alert GPIO device is initialized.
endif # GPIO_NCT38XX
``` | /content/code_sandbox/drivers/gpio/Kconfig.nct38xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```unknown
config GPIO_BCM2711
bool "BCM2711 GPIO driver"
default y
depends on DT_HAS_BRCM_BCM2711_GPIO_ENABLED
help
Enable BCM2711 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.bcm2711 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mfd/adp5585.h>
#define DT_DRV_COMPAT adi_adp5585_gpio
LOG_MODULE_REGISTER(adp5585_gpio, CONFIG_GPIO_LOG_LEVEL);
#define ADP5585_BANK(offs) (offs >> 3)
#define ADP5585_BIT(offs) (offs & GENMASK(2, 0))
enum adp5585_gpio_pin_direction {
adp5585_pin_input = 0U,
adp5585_pin_output,
};
enum adp5585_gpio_pin_drive_mode {
adp5585_pin_drive_pp = 0U,
adp5585_pin_drive_od,
};
enum adp5585_gpio_pull_config {
adp5585_pull_up_300k = 0U,
adp5585_pull_dn_300k,
adp5585_pull_up_100k, /* not used */
adp5585_pull_disable,
};
enum adp5585_gpio_int_en {
adp5585_int_disable = 0U,
adp5585_int_enable,
};
enum adp5585_gpio_int_level {
adp5585_int_active_low = 0U,
adp5585_int_active_high,
};
/** Configuration data */
struct adp5585_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *mfd_dev;
const struct gpio_dt_spec gpio_int;
};
/** Runtime driver data */
struct adp5585_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
uint16_t output;
sys_slist_t callbacks;
};
static int gpio_adp5585_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct adp5585_gpio_config *cfg = dev->config;
struct adp5585_gpio_data *data = dev->data;
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
int ret = 0;
uint8_t reg_value;
/* ADP5585 has non-contiguous gpio pin layouts, account for this */
if ((pin & cfg->common.port_pin_mask) == 0) {
LOG_ERR("pin %d is invalid for this device", pin);
return -ENOTSUP;
}
uint8_t bank = ADP5585_BANK(pin);
uint8_t bank_pin = ADP5585_BIT(pin);
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
/* Simultaneous PU & PD mode not supported */
if (((flags & GPIO_PULL_UP) != 0) && ((flags & GPIO_PULL_DOWN) != 0)) {
return -ENOTSUP;
}
/* Simultaneous input & output mode not supported */
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
k_sem_take(&parent_data->lock, K_FOREVER);
if ((flags & GPIO_SINGLE_ENDED) != 0) {
reg_value = adp5585_pin_drive_od << bank_pin;
} else {
reg_value = adp5585_pin_drive_pp << bank_pin;
}
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus, ADP5585_GPO_OUT_MODE_A + bank,
BIT(bank_pin), reg_value);
if (ret != 0) {
goto out;
}
uint8_t regaddr = ADP5585_RPULL_CONFIG_A + (bank << 1);
uint8_t shift = bank_pin << 1;
if (bank_pin > 3U) {
regaddr += 1U;
shift = (bank_pin - 3U) << 1;
}
if ((flags & GPIO_PULL_UP) != 0) {
reg_value = adp5585_pull_up_300k << shift;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
reg_value = adp5585_pull_dn_300k << shift;
} else {
reg_value = adp5585_pull_disable << shift;
}
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus, regaddr,
0b11U << shift, reg_value);
if (ret != 0) {
goto out;
}
/* Ensure either Output or Input is specified */
if ((flags & GPIO_OUTPUT) != 0) {
/* Set Low or High if specified */
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
data->output &= ~BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
data->output |= BIT(pin);
}
if (bank == 0) {
/* reg_value for ADP5585_GPO_OUT_MODE */
reg_value = (uint8_t)data->output;
} else {
/* reg_value for ADP5585_GPO_OUT_MODE */
reg_value = (uint8_t)(data->output >> 8);
}
ret = i2c_reg_write_byte_dt(&parent_cfg->i2c_bus,
ADP5585_GPO_OUT_MODE_A + bank,
reg_value);
if (ret != 0) {
goto out;
}
/* reg_value for ADP5585_GPIO_DIRECTION */
reg_value = adp5585_pin_output << bank_pin;
} else if ((flags & GPIO_INPUT) != 0) {
/* reg_value for ADP5585_GPIO_DIRECTION */
reg_value = adp5585_pin_output << bank_pin;
}
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus,
ADP5585_GPIO_DIRECTION_A + bank,
BIT(bank_pin), reg_value);
out:
k_sem_give(&parent_data->lock);
if (ret != 0) {
LOG_ERR("pin configure error: %d", ret);
}
return ret;
}
static int gpio_adp5585_port_read(const struct device *dev, gpio_port_value_t *value)
{
const struct adp5585_gpio_config *cfg = dev->config;
/* struct adp5585_gpio_data *data = dev->data; */
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
uint16_t input_data = 0;
int ret = 0;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&parent_data->lock, K_FOREVER);
/** Read Input Register */
uint8_t gpi_status_reg;
uint8_t gpi_status_buf[2];
ret = i2c_write_read_dt(&parent_cfg->i2c_bus, &gpi_status_reg, 1U,
gpi_status_buf, 2U);
if (ret) {
goto out;
}
input_data = sys_le16_to_cpu(*((uint16_t *)gpi_status_buf));
*value = input_data;
out:
k_sem_give(&parent_data->lock);
LOG_DBG("read %x got %d", input_data, ret);
return ret;
}
static int gpio_adp5585_port_write(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value, gpio_port_value_t toggle)
{
const struct adp5585_gpio_config *cfg = dev->config;
struct adp5585_gpio_data *data = dev->data;
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
uint16_t orig_out;
uint16_t out;
uint8_t reg_value;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&parent_data->lock, K_FOREVER);
orig_out = data->output;
out = ((orig_out & ~mask) | (value & mask)) ^ toggle;
reg_value = (uint8_t)out;
uint8_t gpo_data_out_buf[] = { ADP5585_GPO_DATA_OUT_A,
(uint8_t)out, (uint8_t)(out >> 8) };
ret = i2c_write_dt(&parent_cfg->i2c_bus, gpo_data_out_buf, sizeof(gpo_data_out_buf));
if (ret) {
goto out;
}
data->output = out;
out:
k_sem_give(&parent_data->lock);
LOG_DBG("write %x msk %08x val %08x => %x: %d", orig_out, mask, value, out, ret);
return ret;
}
static int gpio_adp5585_port_set_masked(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
return gpio_adp5585_port_write(dev, mask, value, 0);
}
static int gpio_adp5585_port_set_bits(const struct device *dev, gpio_port_pins_t pins)
{
return gpio_adp5585_port_write(dev, pins, pins, 0);
}
static int gpio_adp5585_port_clear_bits(const struct device *dev, gpio_port_pins_t pins)
{
return gpio_adp5585_port_write(dev, pins, 0, 0);
}
static int gpio_adp5585_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
return gpio_adp5585_port_write(dev, 0, 0, pins);
}
static int gpio_adp5585_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct adp5585_gpio_config *cfg = dev->config;
/* struct adp5585_gpio_data *data = dev->data; */
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
int ret = 0;
if (parent_cfg->nint_gpio.port == NULL) {
return -ENOTSUP;
}
/* ADP5585 has non-contiguous gpio pin layouts, account for this */
if ((pin & cfg->common.port_pin_mask) == 0) {
LOG_ERR("pin %d is invalid for this device", pin);
return -ENOTSUP;
}
/* This device supports only level-triggered interrupts. */
/* This device does NOT support either-level interrupt. */
if (mode == GPIO_INT_MODE_EDGE || trig == GPIO_INT_TRIG_BOTH) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
uint8_t bank = ADP5585_BANK(pin);
uint8_t bank_pin = ADP5585_BIT(pin);
k_sem_take(&parent_data->lock, K_FOREVER);
if (mode == GPIO_INT_MODE_DISABLED) {
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus,
ADP5585_GPI_INTERRUPT_EN_A + bank, BIT(bank_pin),
(adp5585_int_disable << bank_pin));
} else if ((trig & GPIO_INT_TRIG_BOTH) != 0) {
if (trig == GPIO_INT_TRIG_LOW) {
ret = i2c_reg_update_byte_dt(
&parent_cfg->i2c_bus, ADP5585_GPI_INT_LEVEL_A + bank,
BIT(bank_pin), (adp5585_int_active_low << bank_pin));
} else {
ret = i2c_reg_update_byte_dt(
&parent_cfg->i2c_bus, ADP5585_GPI_INT_LEVEL_A + bank,
BIT(bank_pin), (adp5585_int_active_high << bank_pin));
}
/* make sure GPI_n_EVENT_EN is disabled, otherwise it will generate FIFO event */
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus,
ADP5585_GPI_EVENT_EN_A + bank, BIT(bank_pin), 0U);
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus,
ADP5585_GPI_INTERRUPT_EN_A + bank,
BIT(bank_pin), (adp5585_int_enable << bank_pin));
}
k_sem_give(&parent_data->lock);
return ret;
}
static int gpio_adp5585_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct adp5585_gpio_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
void gpio_adp5585_irq_handler(const struct device *dev)
{
const struct adp5585_gpio_config *cfg = dev->config;
struct adp5585_gpio_data *data = dev->data;
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
uint16_t reg_int_status;
int ret = 0;
k_sem_take(&parent_data->lock, K_FOREVER);
/* Read Input Register */
ret = i2c_burst_read_dt(&parent_cfg->i2c_bus, ADP5585_GPI_INT_STAT_A,
(uint8_t *)®_int_status, 2U);
if (ret != 0) {
LOG_WRN("%s failed to read interrupt status %d", dev->name, ret);
goto out;
}
out:
k_sem_give(&parent_data->lock);
if (ret == 0 && reg_int_status != 0) {
gpio_fire_callbacks(&data->callbacks, dev, reg_int_status);
}
}
/**
* @brief Initialization function of ADP5585_GPIO
*
* This sets initial input/ output configuration and output states.
* The interrupt is configured if this is enabled.
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_adp5585_init(const struct device *dev)
{
const struct adp5585_gpio_config *cfg = dev->config;
struct adp5585_gpio_data *data = dev->data;
const struct mfd_adp5585_config *parent_cfg =
(struct mfd_adp5585_config *)(cfg->mfd_dev->config);
struct mfd_adp5585_data *parent_data = (struct mfd_adp5585_data *)(cfg->mfd_dev->data);
int ret = 0;
if (!device_is_ready(cfg->mfd_dev)) {
LOG_ERR("%s: parent dev not ready", dev->name);
ret = -ENODEV;
goto out;
}
if (!device_is_ready(parent_cfg->i2c_bus.bus)) {
LOG_ERR("I2C bus device not found");
ret = -EIO;
goto out;
}
k_sem_take(&parent_data->lock, K_FOREVER);
/** Read output register */
uint8_t gpo_data_out_buf[] = { ADP5585_GPO_DATA_OUT_A,
0x00, 0x00 };
ret = i2c_write_read_dt(&parent_cfg->i2c_bus, gpo_data_out_buf, 1U,
gpo_data_out_buf + 1, 2U);
if (ret) {
goto out;
}
data->output = sys_le16_to_cpu(*((uint16_t *)(gpo_data_out_buf + 1)));
/** Set RPULL to high-z by default */
uint8_t rpull_config_buf[] = { ADP5585_RPULL_CONFIG_A,
0xffU, 0x03U, 0xffU, 0x03U };
ret = i2c_write_dt(&parent_cfg->i2c_bus, rpull_config_buf, sizeof(rpull_config_buf));
if (ret) {
goto out;
}
parent_data->child.gpio_dev = dev;
/** Enable GPI interrupt */
if ((ret == 0) && gpio_is_ready_dt(&parent_cfg->nint_gpio)) {
ret = i2c_reg_update_byte_dt(&parent_cfg->i2c_bus, ADP5585_INT_EN, (1U << 1),
(1U << 1));
}
out:
k_sem_give(&parent_data->lock);
if (ret) {
LOG_ERR("%s init failed: %d", dev->name, ret);
} else {
LOG_INF("%s init ok", dev->name);
}
return ret;
}
static const struct gpio_driver_api api_table = {
.pin_configure = gpio_adp5585_config,
.port_get_raw = gpio_adp5585_port_read,
.port_set_masked_raw = gpio_adp5585_port_set_masked,
.port_set_bits_raw = gpio_adp5585_port_set_bits,
.port_clear_bits_raw = gpio_adp5585_port_clear_bits,
.port_toggle_bits = gpio_adp5585_port_toggle_bits,
.pin_interrupt_configure = gpio_adp5585_pin_interrupt_configure,
.manage_callback = gpio_adp5585_manage_callback,
};
#define GPIO_ADP5585_INIT(inst) \
static const struct adp5585_gpio_config adp5585_gpio_cfg_##inst = { \
.common = { \
.port_pin_mask = GPIO_DT_INST_PORT_PIN_MASK_NGPIOS_EXC( \
inst, DT_INST_PROP(inst, ngpios)) \
}, \
.mfd_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
static struct adp5585_gpio_data adp5585_gpio_drvdata_##inst; \
DEVICE_DT_INST_DEFINE(inst, gpio_adp5585_init, NULL, \
&adp5585_gpio_drvdata_##inst, \
&adp5585_gpio_cfg_##inst, POST_KERNEL, \
CONFIG_GPIO_ADP5585_INIT_PRIORITY, &api_table);
DT_INST_FOREACH_STATUS_OKAY(GPIO_ADP5585_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_adp5585.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,135 |
```unknown
# Microchip XEC GPIO configuration options
config GPIO_XEC
bool "XEC Microchip GPIO driver"
default y
depends on DT_HAS_MICROCHIP_XEC_GPIO_ENABLED
help
Enable the Microchip XEC gpio driver.
config GPIO_XEC_V2
bool "XEC Microchip GPIO driver V2"
default y
depends on DT_HAS_MICROCHIP_XEC_GPIO_V2_ENABLED
help
Enable the Microchip XEC gpio V2 driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```c
/*
*
*/
#define DT_DRV_COMPAT nordic_nrf_gpio
#include <nrfx_gpiote.h>
#include <string.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_nrfx_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t callbacks;
};
struct gpio_nrfx_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
NRF_GPIO_Type *port;
uint32_t edge_sense;
uint8_t port_num;
nrfx_gpiote_t gpiote;
};
static inline struct gpio_nrfx_data *get_port_data(const struct device *port)
{
return port->data;
}
static inline const struct gpio_nrfx_cfg *get_port_cfg(const struct device *port)
{
return port->config;
}
static bool has_gpiote(const struct gpio_nrfx_cfg *cfg)
{
return cfg->gpiote.p_reg != NULL;
}
static nrf_gpio_pin_pull_t get_pull(gpio_flags_t flags)
{
if (flags & GPIO_PULL_UP) {
return NRF_GPIO_PIN_PULLUP;
} else if (flags & GPIO_PULL_DOWN) {
return NRF_GPIO_PIN_PULLDOWN;
}
return NRF_GPIO_PIN_NOPULL;
}
static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
nrfx_err_t err = NRFX_SUCCESS;
uint8_t ch;
bool free_ch = false;
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
nrf_gpio_pin_pull_t pull = get_pull(flags);
nrf_gpio_pin_drive_t drive;
switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
case NRF_GPIO_DRIVE_S0S1:
drive = NRF_GPIO_PIN_S0S1;
break;
case NRF_GPIO_DRIVE_S0H1:
drive = NRF_GPIO_PIN_S0H1;
break;
case NRF_GPIO_DRIVE_H0S1:
drive = NRF_GPIO_PIN_H0S1;
break;
case NRF_GPIO_DRIVE_H0H1:
drive = NRF_GPIO_PIN_H0H1;
break;
case NRF_GPIO_DRIVE_S0 | GPIO_OPEN_DRAIN:
drive = NRF_GPIO_PIN_S0D1;
break;
case NRF_GPIO_DRIVE_H0 | GPIO_OPEN_DRAIN:
drive = NRF_GPIO_PIN_H0D1;
break;
case NRF_GPIO_DRIVE_S1 | GPIO_OPEN_SOURCE:
drive = NRF_GPIO_PIN_D0S1;
break;
case NRF_GPIO_DRIVE_H1 | GPIO_OPEN_SOURCE:
drive = NRF_GPIO_PIN_D0H1;
break;
default:
return -EINVAL;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
nrf_gpio_port_out_set(cfg->port, BIT(pin));
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
nrf_gpio_port_out_clear(cfg->port, BIT(pin));
}
if (!has_gpiote(cfg)) {
nrf_gpio_pin_dir_t dir = (flags & GPIO_OUTPUT)
? NRF_GPIO_PIN_DIR_OUTPUT
: NRF_GPIO_PIN_DIR_INPUT;
nrf_gpio_pin_input_t input = (flags & GPIO_INPUT)
? NRF_GPIO_PIN_INPUT_CONNECT
: NRF_GPIO_PIN_INPUT_DISCONNECT;
nrf_gpio_reconfigure(abs_pin, &dir, &input, &pull, &drive, NULL);
return 0;
}
/* Get the GPIOTE channel associated with this pin, if any. It needs
* to be freed when the pin is reconfigured or disconnected.
*/
if (IS_ENABLED(CONFIG_GPIO_NRFX_INTERRUPT)) {
err = nrfx_gpiote_channel_get(&cfg->gpiote, abs_pin, &ch);
free_ch = (err == NRFX_SUCCESS);
}
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
/* Ignore the error code. The pin may not have been used. */
(void)nrfx_gpiote_pin_uninit(&cfg->gpiote, abs_pin);
} else {
/* Remove previously configured trigger when pin is reconfigured. */
if (IS_ENABLED(CONFIG_GPIO_NRFX_INTERRUPT)) {
nrfx_gpiote_trigger_config_t trigger_config = {
.trigger = NRFX_GPIOTE_TRIGGER_NONE,
};
nrfx_gpiote_input_pin_config_t input_pin_config = {
.p_trigger_config = &trigger_config,
};
err = nrfx_gpiote_input_configure(&cfg->gpiote,
abs_pin, &input_pin_config);
if (err != NRFX_SUCCESS) {
return -EINVAL;
}
}
if (flags & GPIO_OUTPUT) {
nrfx_gpiote_output_config_t output_config = {
.drive = drive,
.input_connect = (flags & GPIO_INPUT)
? NRF_GPIO_PIN_INPUT_CONNECT
: NRF_GPIO_PIN_INPUT_DISCONNECT,
.pull = pull,
};
err = nrfx_gpiote_output_configure(&cfg->gpiote,
abs_pin, &output_config, NULL);
} else {
nrfx_gpiote_input_pin_config_t input_pin_config = {
.p_pull_config = &pull,
};
err = nrfx_gpiote_input_configure(&cfg->gpiote,
abs_pin, &input_pin_config);
}
if (err != NRFX_SUCCESS) {
return -EINVAL;
}
}
if (IS_ENABLED(CONFIG_GPIO_NRFX_INTERRUPT) && free_ch) {
err = nrfx_gpiote_channel_free(&cfg->gpiote, ch);
__ASSERT_NO_MSG(err == NRFX_SUCCESS);
}
return 0;
}
static int gpio_nrfx_port_get_raw(const struct device *port,
gpio_port_value_t *value)
{
NRF_GPIO_Type *reg = get_port_cfg(port)->port;
*value = nrf_gpio_port_in_read(reg);
return 0;
}
static int gpio_nrfx_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
NRF_GPIO_Type *reg = get_port_cfg(port)->port;
const uint32_t set_mask = value & mask;
const uint32_t clear_mask = (~set_mask) & mask;
nrf_gpio_port_out_set(reg, set_mask);
nrf_gpio_port_out_clear(reg, clear_mask);
return 0;
}
static int gpio_nrfx_port_set_bits_raw(const struct device *port,
gpio_port_pins_t mask)
{
NRF_GPIO_Type *reg = get_port_cfg(port)->port;
nrf_gpio_port_out_set(reg, mask);
return 0;
}
static int gpio_nrfx_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t mask)
{
NRF_GPIO_Type *reg = get_port_cfg(port)->port;
nrf_gpio_port_out_clear(reg, mask);
return 0;
}
static int gpio_nrfx_port_toggle_bits(const struct device *port,
gpio_port_pins_t mask)
{
NRF_GPIO_Type *reg = get_port_cfg(port)->port;
const uint32_t value = nrf_gpio_port_out_read(reg) ^ mask;
const uint32_t set_mask = value & mask;
const uint32_t clear_mask = (~value) & mask;
nrf_gpio_port_out_set(reg, set_mask);
nrf_gpio_port_out_clear(reg, clear_mask);
return 0;
}
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
static nrfx_gpiote_trigger_t get_trigger(enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
if (mode == GPIO_INT_MODE_LEVEL) {
return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
NRFX_GPIOTE_TRIGGER_HIGH;
}
return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_HITOLO :
NRFX_GPIOTE_TRIGGER_LOTOHI;
}
static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
nrfx_err_t err;
uint8_t ch;
if (!has_gpiote(cfg)) {
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_DISABLED) {
nrfx_gpiote_trigger_disable(&cfg->gpiote, abs_pin);
return 0;
}
nrfx_gpiote_trigger_config_t trigger_config = {
.trigger = get_trigger(mode, trig),
};
nrfx_gpiote_input_pin_config_t input_pin_config = {
.p_trigger_config = &trigger_config,
};
/* If edge mode is to be used and pin is not configured to use sense for
* edge use IN event.
*/
if (!(BIT(pin) & cfg->edge_sense) &&
(mode == GPIO_INT_MODE_EDGE) &&
(nrf_gpio_pin_dir_get(abs_pin) == NRF_GPIO_PIN_DIR_INPUT)) {
err = nrfx_gpiote_channel_get(&cfg->gpiote, abs_pin, &ch);
if (err == NRFX_ERROR_INVALID_PARAM) {
err = nrfx_gpiote_channel_alloc(&cfg->gpiote, &ch);
if (err != NRFX_SUCCESS) {
return -ENOMEM;
}
}
trigger_config.p_in_channel = &ch;
}
err = nrfx_gpiote_input_configure(&cfg->gpiote, abs_pin, &input_pin_config);
if (err != NRFX_SUCCESS) {
return -EINVAL;
}
nrfx_gpiote_trigger_enable(&cfg->gpiote, abs_pin, true);
return 0;
}
static int gpio_nrfx_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
return gpio_manage_callback(&get_port_data(port)->callbacks,
callback, set);
}
#endif /* CONFIG_GPIO_NRFX_INTERRUPT */
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_nrfx_port_get_direction(const struct device *port,
gpio_port_pins_t map,
gpio_port_pins_t *inputs,
gpio_port_pins_t *outputs)
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
NRF_GPIO_Type *reg = cfg->port;
map &= cfg->common.port_pin_mask;
if (outputs != NULL) {
*outputs = map & nrf_gpio_port_dir_read(cfg->port);
}
if (inputs != NULL) {
*inputs = 0;
while (map) {
uint32_t pin = NRF_CTZ(map);
uint32_t pin_cnf = reg->PIN_CNF[pin];
/* Check if the pin has its input buffer connected. */
if (((pin_cnf & GPIO_PIN_CNF_INPUT_Msk) >>
GPIO_PIN_CNF_INPUT_Pos) ==
GPIO_PIN_CNF_INPUT_Connect) {
*inputs |= BIT(pin);
}
map &= ~BIT(pin);
}
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
/* Get port device from port id. */
static const struct device *get_dev(uint32_t port_id)
{
const struct device *dev = NULL;
#define GPIO_NRF_GET_DEV(i) \
else if (DT_INST_PROP(i, port) == port_id) { \
dev = DEVICE_DT_INST_GET(i); \
}
if (0) {
} /* Followed by else if from FOREACH macro. Done to avoid return statement in macro. */
DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
#undef GPIO_NRF_GET_DEV
return dev;
}
static void nrfx_gpio_handler(nrfx_gpiote_pin_t abs_pin,
nrfx_gpiote_trigger_t trigger,
void *context)
{
uint32_t pin = abs_pin;
uint32_t port_id = nrf_gpio_pin_port_number_extract(&pin);
const struct device *port = get_dev(port_id);
/* If given port is handled directly by nrfx driver it might not be enabled in DT. */
if (port == NULL) {
return;
}
struct gpio_nrfx_data *data = get_port_data(port);
sys_slist_t *list = &data->callbacks;
gpio_fire_callbacks(list, port, BIT(pin));
}
#endif /* CONFIG_GPIO_NRFX_INTERRUPT */
#define GPIOTE_IRQ_HANDLER_CONNECT(node_id) \
IRQ_CONNECT(DT_IRQN(node_id), DT_IRQ(node_id, priority), nrfx_isr, \
NRFX_CONCAT(nrfx_gpiote_, DT_PROP(node_id, instance), _irq_handler), 0);
static int gpio_nrfx_init(const struct device *port)
{
const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
nrfx_err_t err;
if (!has_gpiote(cfg)) {
return 0;
}
if (nrfx_gpiote_init_check(&cfg->gpiote)) {
return 0;
}
err = nrfx_gpiote_init(&cfg->gpiote, 0 /*not used*/);
if (err != NRFX_SUCCESS) {
return -EIO;
}
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
nrfx_gpiote_global_callback_set(&cfg->gpiote, nrfx_gpio_handler, NULL);
DT_FOREACH_STATUS_OKAY(nordic_nrf_gpiote, GPIOTE_IRQ_HANDLER_CONNECT);
#endif /* CONFIG_GPIO_NRFX_INTERRUPT */
return 0;
}
static const struct gpio_driver_api gpio_nrfx_drv_api_funcs = {
.pin_configure = gpio_nrfx_pin_configure,
.port_get_raw = gpio_nrfx_port_get_raw,
.port_set_masked_raw = gpio_nrfx_port_set_masked_raw,
.port_set_bits_raw = gpio_nrfx_port_set_bits_raw,
.port_clear_bits_raw = gpio_nrfx_port_clear_bits_raw,
.port_toggle_bits = gpio_nrfx_port_toggle_bits,
#ifdef CONFIG_GPIO_NRFX_INTERRUPT
.pin_interrupt_configure = gpio_nrfx_pin_interrupt_configure,
.manage_callback = gpio_nrfx_manage_callback,
#endif
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_nrfx_port_get_direction,
#endif
};
#define GPIOTE_PHANDLE(id) DT_INST_PHANDLE(id, gpiote_instance)
#define GPIOTE_INST(id) DT_PROP(GPIOTE_PHANDLE(id), instance)
#define GPIOTE_INSTANCE(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, gpiote_instance), \
(NRFX_GPIOTE_INSTANCE(GPIOTE_INST(id))), \
({ .p_reg = NULL }))
/* Device instantiation is done with node labels because 'port_num' is
* the peripheral number by SoC numbering. We therefore cannot use
* DT_INST APIs here without wider changes.
*/
#define GPIOTE_CHECK(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, gpiote_instance), \
(BUILD_ASSERT(DT_NODE_HAS_STATUS(GPIOTE_PHANDLE(id), okay), \
"Please enable GPIOTE instance for used GPIO port!")), \
())
#define GPIO_NRF_DEVICE(id) \
GPIOTE_CHECK(id); \
static const struct gpio_nrfx_cfg gpio_nrfx_p##id##_cfg = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \
}, \
.port = _CONCAT(NRF_P, DT_INST_PROP(id, port)), \
.port_num = DT_INST_PROP(id, port), \
.edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0), \
.gpiote = GPIOTE_INSTANCE(id), \
}; \
\
static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, gpio_nrfx_init, \
NULL, \
&gpio_nrfx_p##id##_data, \
&gpio_nrfx_p##id##_cfg, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_nrfx_drv_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_nrfx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,626 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_gpio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
#include <NuMicro.h>
#define NU_MFP_POS(pinindex) ((pinindex % 4) * 8)
LOG_MODULE_REGISTER(gpio_numaker, LOG_LEVEL_ERR);
struct gpio_numaker_config {
struct gpio_driver_config common;
uint32_t reg;
uint32_t gpa_base;
uint32_t size;
uint32_t clk_modidx;
const struct device *clk_dev;
};
struct gpio_numaker_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
};
static int gpio_numaker_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_numaker_config *config = dev->config;
struct gpio_numaker_data *data = dev->data;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
uint32_t pinMfpMask = (0x1f << NU_MFP_POS(pin));
uint32_t pinMask = BIT(pin); /* mask for pin index --> (0x01 << pin) */
uint32_t port_index;
uint32_t *GPx_MFPx;
uint32_t pinMfpGpio;
int err = 0;
ARG_UNUSED(data);
/* Check for an invalid pin number */
if (pin > 15) {
return -EINVAL;
}
/* Configure GPIO direction */
switch (flags & GPIO_DIR_MASK) {
case GPIO_INPUT:
GPIO_SetMode(gpio_base, pinMask, GPIO_MODE_INPUT);
break;
case GPIO_OUTPUT:
GPIO_SetMode(gpio_base, pinMask, GPIO_MODE_OUTPUT);
break;
case (GPIO_INPUT | GPIO_OUTPUT):
GPIO_SetMode(gpio_base, pinMask, GPIO_MODE_QUASI);
break;
default:
err = -ENOTSUP;
goto move_exit;
}
if (flags & GPIO_LINE_OPEN_DRAIN) {
GPIO_SetMode(gpio_base, pinMask, GPIO_MODE_OPEN_DRAIN);
}
/* Set Multi-function, default is GPIO */
port_index = (config->reg - config->gpa_base) / config->size;
GPx_MFPx = ((uint32_t *)&SYS->GPA_MFP0) + port_index * 4 + (pin / 4);
pinMfpGpio = 0x00UL;
/*
* E.g.: SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SYS_GPA_MFP0_PA0MFP_Msk) ) |
* SYS_GPA_MFP0_PA0MFP_GPIO;
*/
*GPx_MFPx = (*GPx_MFPx & (~pinMfpMask)) | pinMfpGpio;
/* Set pull control as pull-up, pull-down or pull-disable */
if ((flags & GPIO_PULL_UP) != 0) {
GPIO_SetPullCtl(gpio_base, pinMask, GPIO_PUSEL_PULL_UP);
} else if ((flags & GPIO_PULL_DOWN) != 0) {
GPIO_SetPullCtl(gpio_base, pinMask, GPIO_PUSEL_PULL_DOWN);
} else {
GPIO_SetPullCtl(gpio_base, pinMask, GPIO_PUSEL_DISABLE);
}
/* Set Init Level 0:low 1:high */
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_base->DOUT |= pinMask;
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_base->DOUT &= ~pinMask;
}
move_exit:
return err;
}
static int gpio_numaker_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
/* Get raw bits of GPIO PIN data */
*value = gpio_base->PIN;
return 0;
}
static int gpio_numaker_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
gpio_base->DOUT = (gpio_base->DOUT & ~mask) | (mask & value);
return 0;
}
static int gpio_numaker_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
/* Set raw bits of GPIO output data */
gpio_base->DOUT |= mask;
return 0;
}
static int gpio_numaker_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
/* Clear raw bits of GPIO data */
gpio_base->DOUT &= ~mask;
return 0;
}
static int gpio_numaker_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
/* Toggle raw bits of GPIO data */
gpio_base->DOUT ^= mask;
return 0;
}
static int gpio_numaker_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_numaker_config *config = dev->config;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
uint32_t intAttr;
if (mode == GPIO_INT_MODE_DISABLED) {
GPIO_DisableInt(gpio_base, pin);
/* Clear the port int status */
gpio_base->INTSRC &= BIT(pin);
} else {
switch (trig) {
case GPIO_INT_TRIG_LOW:
intAttr = ((mode == GPIO_INT_MODE_EDGE) ? GPIO_INT_FALLING : GPIO_INT_LOW);
break;
case GPIO_INT_TRIG_HIGH:
intAttr = ((mode == GPIO_INT_MODE_EDGE) ? GPIO_INT_RISING : GPIO_INT_HIGH);
break;
case GPIO_INT_TRIG_BOTH:
if (mode != GPIO_INT_MODE_EDGE) {
return -ENOTSUP;
}
intAttr = GPIO_INT_BOTH_EDGE;
break;
default:
return -ENOTSUP;
}
GPIO_EnableInt(gpio_base, pin, intAttr);
}
return 0;
}
static int gpio_numaker_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct gpio_numaker_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static const struct gpio_driver_api gpio_numaker_api = {
.pin_configure = gpio_numaker_configure,
.port_get_raw = gpio_numaker_port_get_raw,
.port_set_masked_raw = gpio_numaker_port_set_masked_raw,
.port_set_bits_raw = gpio_numaker_port_set_bits_raw,
.port_clear_bits_raw = gpio_numaker_port_clear_bits_raw,
.port_toggle_bits = gpio_numaker_port_toggle_bits,
.pin_interrupt_configure = gpio_numaker_pin_interrupt_configure,
.manage_callback = gpio_numaker_manage_callback};
static void gpio_numaker_isr(const struct device *dev)
{
const struct gpio_numaker_config *config = dev->config;
struct gpio_numaker_data *data = dev->data;
GPIO_T *gpio_base = (GPIO_T *)config->reg;
uint32_t int_status;
/* Get the int status */
int_status = gpio_base->INTSRC;
/* Clear the port int status */
gpio_base->INTSRC = int_status;
gpio_fire_callbacks(&data->callbacks, dev, int_status);
}
#define CLOCK_CTRL_INIT(n) .clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(n))),
#define GPIO_NUMAKER_IRQ_INIT(n) \
do { \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_numaker_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
} while (0)
#define GPIO_NUMAKER_DEFINE(n) \
static const struct gpio_numaker_config gpio_numaker_config##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.reg = DT_INST_REG_ADDR(n), \
.gpa_base = DT_REG_ADDR(DT_NODELABEL(gpioa)), \
.size = DT_REG_SIZE(DT_NODELABEL(gpioa)), \
.clk_modidx = DT_INST_CLOCKS_CELL(n, clock_module_index), \
CLOCK_CTRL_INIT(n)}; \
\
static struct gpio_numaker_data gpio_numaker_data##n; \
\
static int gpio_numaker_init##n(const struct device *dev) \
{ \
const struct gpio_numaker_config *config = dev->config; \
struct numaker_scc_subsys scc_subsys; \
int err; \
\
SYS_UnlockReg(); \
memset(&scc_subsys, 0x00, sizeof(scc_subsys)); \
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC; \
scc_subsys.pcc.clk_modidx = config->clk_modidx; \
err = clock_control_on(config->clk_dev, (clock_control_subsys_t)&scc_subsys); \
if (err == 0) { \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), (GPIO_NUMAKER_IRQ_INIT(n);)) \
} \
\
SYS_LockReg(); \
return err; \
} \
DEVICE_DT_INST_DEFINE(n, gpio_numaker_init##n, NULL, &gpio_numaker_data##n, \
&gpio_numaker_config##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_numaker_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NUMAKER_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,256 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_cmsdk_gpio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/arm_clock_control.h>
#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
/**
* @brief GPIO driver for ARM CMSDK AHB GPIO
*/
typedef void (*gpio_config_func_t)(const struct device *port);
struct gpio_cmsdk_ahb_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
volatile struct gpio_cmsdk_ahb *port;
gpio_config_func_t gpio_config_func;
/* GPIO Clock control in Active State */
struct arm_clock_control_t gpio_cc_as;
/* GPIO Clock control in Sleep State */
struct arm_clock_control_t gpio_cc_ss;
/* GPIO Clock control in Deep Sleep State */
struct arm_clock_control_t gpio_cc_dss;
};
struct gpio_cmsdk_ahb_dev_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of callbacks */
sys_slist_t gpio_cb;
};
static int gpio_cmsdk_ahb_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
*value = cfg->port->data;
return 0;
}
static int gpio_cmsdk_ahb_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
cfg->port->dataout = (cfg->port->dataout & ~mask) | (mask & value);
return 0;
}
static int gpio_cmsdk_ahb_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
cfg->port->dataout |= mask;
return 0;
}
static int gpio_cmsdk_ahb_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
cfg->port->dataout &= ~mask;
return 0;
}
static int gpio_cmsdk_ahb_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
cfg->port->dataout ^= mask;
return 0;
}
static int cmsdk_ahb_gpio_config(const struct device *dev, uint32_t mask,
gpio_flags_t flags)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
if (((flags & GPIO_INPUT) == 0) && ((flags & GPIO_OUTPUT) == 0)) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/*
* Setup the pin direction
* Output Enable:
* 0 - Input
* 1 - Output
*/
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
gpio_cmsdk_ahb_port_set_bits_raw(dev, mask);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
gpio_cmsdk_ahb_port_clear_bits_raw(dev, mask);
}
cfg->port->outenableset = mask;
} else {
cfg->port->outenableclr = mask;
}
cfg->port->altfuncclr = mask;
return 0;
}
/**
* @brief Configure pin or port
*
* @param dev Device struct
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
return cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
}
static int gpio_cmsdk_ahb_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
if (trig == GPIO_INT_TRIG_BOTH) {
return -ENOTSUP;
}
/* For now treat level interrupts as not supported, as we seem to only
* get a single 'edge' still interrupt rather than continuous
* interrupts until the cause is cleared */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
if (mode == GPIO_INT_MODE_DISABLED) {
cfg->port->intenclr = BIT(pin);
} else {
if (mode == GPIO_INT_MODE_EDGE) {
cfg->port->inttypeset = BIT(pin);
} else {
/* LEVEL */
cfg->port->inttypeclr = BIT(pin);
}
/* Level High or Edge Rising */
if (trig == GPIO_INT_TRIG_HIGH) {
cfg->port->intpolset = BIT(pin);
} else {
cfg->port->intpolclr = BIT(pin);
}
cfg->port->intclear = BIT(pin);
cfg->port->intenset = BIT(pin);
}
return 0;
}
static void gpio_cmsdk_ahb_isr(const struct device *dev)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
struct gpio_cmsdk_ahb_dev_data *data = dev->data;
uint32_t int_stat;
int_stat = cfg->port->intstatus;
/* clear the port interrupts */
cfg->port->intclear = int_stat;
gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
}
static int gpio_cmsdk_ahb_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_cmsdk_ahb_dev_data *data = dev->data;
return gpio_manage_callback(&data->gpio_cb, callback, set);
}
static const struct gpio_driver_api gpio_cmsdk_ahb_drv_api_funcs = {
.pin_configure = gpio_cmsdk_ahb_config,
.port_get_raw = gpio_cmsdk_ahb_port_get_raw,
.port_set_masked_raw = gpio_cmsdk_ahb_port_set_masked_raw,
.port_set_bits_raw = gpio_cmsdk_ahb_port_set_bits_raw,
.port_clear_bits_raw = gpio_cmsdk_ahb_port_clear_bits_raw,
.port_toggle_bits = gpio_cmsdk_ahb_port_toggle_bits,
.pin_interrupt_configure = gpio_cmsdk_ahb_pin_interrupt_configure,
.manage_callback = gpio_cmsdk_ahb_manage_callback,
};
/**
* @brief Initialization function of GPIO
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_cmsdk_ahb_init(const struct device *dev)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
if (!device_is_ready(clk)) {
return -ENODEV;
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t) &cfg->gpio_cc_as);
clock_control_off(clk, (clock_control_subsys_t) &cfg->gpio_cc_ss);
clock_control_off(clk, (clock_control_subsys_t) &cfg->gpio_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */
cfg->gpio_config_func(dev);
return 0;
}
#define CMSDK_AHB_GPIO_DEVICE(n) \
static void gpio_cmsdk_port_##n##_config_func(const struct device *dev); \
\
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_port_##n##_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.port = ((volatile struct gpio_cmsdk_ahb *)DT_INST_REG_ADDR(n)),\
.gpio_config_func = gpio_cmsdk_port_##n##_config_func, \
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, \
.device = DT_INST_REG_ADDR(n),}, \
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, \
.device = DT_INST_REG_ADDR(n),}, \
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, \
.device = DT_INST_REG_ADDR(n),}, \
}; \
\
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_port_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_cmsdk_ahb_init, \
NULL, \
&gpio_cmsdk_port_##n##_data, \
&gpio_cmsdk_port_## n ##_config, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_cmsdk_ahb_drv_api_funcs); \
\
static void gpio_cmsdk_port_##n##_config_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_cmsdk_ahb_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(CMSDK_AHB_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_cmsdk_ahb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,262 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_gpio_emul_sdl
#include <zephyr/drivers/gpio/gpio_emul.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include "gpio_emul_sdl_bottom.h"
LOG_MODULE_REGISTER(gpio_emul_sdl, CONFIG_GPIO_LOG_LEVEL);
struct gpio_sdl_config {
const struct device *emul;
const int *codes;
uint8_t num_codes;
struct gpio_sdl_data *data;
};
static int sdl_filter_top(struct gpio_sdl_data *bottom_data)
{
const struct device *port = bottom_data->dev;
const struct gpio_sdl_config *config = port->config;
int ret;
gpio_pin_t pin = 0;
/* Search for the corresponding scancode */
while (pin < config->num_codes) {
if (config->codes[pin] == bottom_data->event_scan_code) {
break;
}
pin++;
}
if (pin == config->num_codes) {
/* Not tracked */
return 1;
}
/* Lock the scheduler so we can't be preempted,
* as the gpio_emul driver keeps a mutex locked
* for as long as there are pending interrupts
*/
k_sched_lock();
/* Update the pin state */
ret = gpio_emul_input_set(config->emul, pin, bottom_data->key_down);
k_sched_unlock();
if (ret < 0) {
LOG_WRN("Failed to emulate input (%d)", ret);
}
return 0;
}
static int gpio_sdl_init(const struct device *dev)
{
const struct gpio_sdl_config *config = dev->config;
for (uint8_t pin = 0; pin < config->num_codes; ++pin) {
if (config->codes[pin] != GPIOEMULSDL_SCANCODE_UNKNOWN) {
LOG_INF("GPIO %s:%u = %u", dev->name, pin, config->codes[pin]);
}
}
config->data->dev = (void *)dev;
config->data->callback = sdl_filter_top;
gpio_sdl_init_bottom(config->data);
return 0;
}
#define GPIO_SDL_DEFINE(inst) \
BUILD_ASSERT(DT_NODE_HAS_COMPAT_STATUS(DT_INST_PARENT(inst), \
zephyr_gpio_emul, okay), \
"Enabled parent zephyr,gpio-emul node is required"); \
\
static const int gpio_sdl_##inst##_codes[] \
= DT_INST_PROP(inst, scancodes); \
\
static struct gpio_sdl_data data_##inst; \
\
static const struct gpio_sdl_config gpio_sdl_##inst##_config = { \
.emul = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.codes = gpio_sdl_##inst##_codes, \
.num_codes = DT_INST_PROP_LEN(inst, scancodes), \
.data = &data_##inst, \
}; \
\
DEVICE_DT_INST_DEFINE(inst, gpio_sdl_init, NULL, NULL, \
&gpio_sdl_##inst##_config, POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(GPIO_SDL_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_emul_sdl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 712 |
```c
/*
*
*
*/
/**
* @file Driver for MPC230xx I2C-based GPIO driver.
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_mcp23xxx.h"
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_mcp230xx);
static int mcp230xx_read_port_regs(const struct device *dev, uint8_t reg, uint16_t *buf)
{
const struct mcp23xxx_config *config = dev->config;
uint16_t port_data = 0;
int ret;
uint8_t nread = (config->ngpios == 8) ? 1 : 2;
ret = i2c_burst_read_dt(&config->bus.i2c, reg, (uint8_t *)&port_data, nread);
if (ret < 0) {
LOG_ERR("i2c_read failed!");
return ret;
}
*buf = sys_le16_to_cpu(port_data);
return 0;
}
static int mcp230xx_write_port_regs(const struct device *dev, uint8_t reg, uint16_t value)
{
const struct mcp23xxx_config *config = dev->config;
int ret;
uint8_t nwrite = (config->ngpios == 8) ? 2 : 3;
uint8_t buf[3];
buf[0] = reg;
sys_put_le16(value, &buf[1]);
ret = i2c_write_dt(&config->bus.i2c, buf, nwrite);
if (ret < 0) {
LOG_ERR("i2c_write failed!");
return ret;
}
return 0;
}
static int mcp230xx_bus_is_ready(const struct device *dev)
{
const struct mcp23xxx_config *config = dev->config;
if (!device_is_ready(config->bus.i2c.bus)) {
LOG_ERR("I2C bus %s not ready", config->bus.i2c.bus->name);
return -ENODEV;
}
return 0;
}
#define GPIO_MCP230XX_DEVICE(inst, num_gpios, open_drain) \
static struct mcp23xxx_drv_data mcp230xx_##inst##_drvdata = { \
/* Default for registers according to datasheet */ \
.reg_cache.iodir = 0xFFFF, .reg_cache.ipol = 0x0, .reg_cache.gpinten = 0x0, \
.reg_cache.defval = 0x0, .reg_cache.intcon = 0x0, .reg_cache.iocon = 0x0, \
.reg_cache.gppu = 0x0, .reg_cache.intf = 0x0, .reg_cache.intcap = 0x0, \
.reg_cache.gpio = 0x0, .reg_cache.olat = 0x0, \
}; \
static const struct mcp23xxx_config mcp230xx_##inst##_config = { \
.config = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.bus = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}, \
.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}), \
.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \
.ngpios = num_gpios, \
.is_open_drain = open_drain, \
.read_fn = mcp230xx_read_port_regs, \
.write_fn = mcp230xx_write_port_regs, \
.bus_fn = mcp230xx_bus_is_ready, \
}; \
DEVICE_DT_INST_DEFINE(inst, gpio_mcp23xxx_init, NULL, &mcp230xx_##inst##_drvdata, \
&mcp230xx_##inst##_config, POST_KERNEL, \
CONFIG_GPIO_MCP230XX_INIT_PRIORITY, &gpio_mcp23xxx_api_table);
#define DT_DRV_COMPAT microchip_mcp23008
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP230XX_DEVICE, 8, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23009
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP230XX_DEVICE, 8, true)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23016
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP230XX_DEVICE, 16, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23017
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP230XX_DEVICE, 16, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23018
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP230XX_DEVICE, 16, true)
#undef DT_DRV_COMPAT
``` | /content/code_sandbox/drivers/gpio/gpio_mcp230xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,129 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_ra_gpio_ioport
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
#include <soc.h>
struct gpio_ra_config {
struct gpio_driver_config common;
uint8_t port_num;
R_PORT0_Type *port;
gpio_pin_t vbatt_pins[];
};
struct gpio_ra_data {
struct gpio_driver_data common;
};
static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_ra_config *config = dev->config;
struct ra_pinctrl_soc_pin pincfg = {0};
if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
return -ENOTSUP;
}
if ((flags & GPIO_PULL_DOWN) != 0U) {
return -ENOTSUP;
}
if ((flags & GPIO_INT_ENABLE) != 0) {
return -ENOTSUP;
}
if (config->vbatt_pins[0] != 0xFF) {
uint32_t clear = 0;
for (int i = 0; config->vbatt_pins[i] != '\0'; i++) {
if (config->vbatt_pins[i] == pin) {
WRITE_BIT(clear, i, 1);
}
}
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
R_SYSTEM->VBTICTLR &= (uint8_t)~clear;
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
pincfg.port_num = config->port_num;
pincfg.pin_num = pin;
/* Change mode to general IO mode and disable IRQ and Analog input */
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PMR_Pos, 0);
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ASEL_Pos, 0);
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0);
if ((flags & GPIO_OUTPUT) != 0U) {
/* Set output pin initial value */
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 0);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1);
}
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1);
} else {
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 0);
}
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_NCODR_Pos, 1);
}
if ((flags & GPIO_PULL_UP) != 0) {
WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PCR_Pos, 1);
}
pincfg.cfg = pincfg.cfg |
(((flags & RENESAS_GPIO_DS_MSK) >> 8) << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
}
static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
*value = port->PIDR;
return 0;
}
static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = ((port->PODR & ~mask) | (value & mask));
return 0;
}
static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR | pins);
return 0;
}
static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR & ~pins);
return 0;
}
static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR ^ pins);
return 0;
}
static const struct gpio_driver_api gpio_ra_drv_api_funcs = {
.pin_configure = gpio_ra_pin_configure,
.port_get_raw = gpio_ra_port_get_raw,
.port_set_masked_raw = gpio_ra_port_set_masked_raw,
.port_set_bits_raw = gpio_ra_port_set_bits_raw,
.port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
.port_toggle_bits = gpio_ra_port_toggle_bits,
.pin_interrupt_configure = NULL,
.manage_callback = NULL,
};
#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
static const struct gpio_ra_config gpio_ra_config_##suffix = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
}, \
.port_num = port_number, \
.port = (R_PORT0_Type *)addr, \
.vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \
}; \
static struct gpio_ra_data gpio_ra_data_##suffix; \
DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra_data_##suffix, &gpio_ra_config_##suffix, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_drv_api_funcs)
#define GPIO_DEVICE_INIT_RA(suffix) \
GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \
DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \
DT_REG_ADDR(DT_NODELABEL(ioport##suffix)))
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay)
GPIO_DEVICE_INIT_RA(0);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay)
GPIO_DEVICE_INIT_RA(1);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay)
GPIO_DEVICE_INIT_RA(2);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay)
GPIO_DEVICE_INIT_RA(3);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay)
GPIO_DEVICE_INIT_RA(4);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay)
GPIO_DEVICE_INIT_RA(5);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay)
GPIO_DEVICE_INIT_RA(6);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay)
GPIO_DEVICE_INIT_RA(7);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay)
GPIO_DEVICE_INIT_RA(8);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay)
GPIO_DEVICE_INIT_RA(9);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay)
GPIO_DEVICE_INIT_RA(a);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay)
GPIO_DEVICE_INIT_RA(b);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) */
``` | /content/code_sandbox/drivers/gpio/gpio_renesas_ra_ioport.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,927 |
```c
/*
*
*/
#define DT_DRV_COMPAT neorv32_gpio
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/irq.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <soc.h>
LOG_MODULE_REGISTER(gpio_neorv32, CONFIG_GPIO_LOG_LEVEL);
#include <zephyr/drivers/gpio/gpio_utils.h>
/* Maximum number of GPIOs supported */
#define MAX_GPIOS 32
struct neorv32_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *syscon;
mm_reg_t input;
mm_reg_t output;
};
struct neorv32_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* Shadow register for output */
uint32_t output;
};
static inline uint32_t neorv32_gpio_read(const struct device *dev)
{
const struct neorv32_gpio_config *config = dev->config;
return sys_read32(config->input);
}
static inline void neorv32_gpio_write(const struct device *dev, uint32_t val)
{
const struct neorv32_gpio_config *config = dev->config;
sys_write32(val, config->output);
}
static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct neorv32_gpio_config *config = dev->config;
struct neorv32_gpio_data *data = dev->data;
unsigned int key;
if (!(BIT(pin) & config->common.port_pin_mask)) {
return -EINVAL;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if ((flags & GPIO_OUTPUT) != 0) {
key = irq_lock();
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
data->output |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
data->output &= ~BIT(pin);
}
neorv32_gpio_write(dev, data->output);
irq_unlock(key);
}
return 0;
}
static int neorv32_gpio_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
*value = neorv32_gpio_read(dev);
return 0;
}
static int neorv32_gpio_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
struct neorv32_gpio_data *data = dev->data;
unsigned int key;
key = irq_lock();
data->output = (data->output & ~mask) | (mask & value);
neorv32_gpio_write(dev, data->output);
irq_unlock(key);
return 0;
}
static int neorv32_gpio_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
struct neorv32_gpio_data *data = dev->data;
unsigned int key;
key = irq_lock();
data->output |= pins;
neorv32_gpio_write(dev, data->output);
irq_unlock(key);
return 0;
}
static int neorv32_gpio_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
struct neorv32_gpio_data *data = dev->data;
unsigned int key;
key = irq_lock();
data->output &= ~pins;
neorv32_gpio_write(dev, data->output);
irq_unlock(key);
return 0;
}
static int neorv32_gpio_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
struct neorv32_gpio_data *data = dev->data;
unsigned int key;
key = irq_lock();
data->output ^= pins;
neorv32_gpio_write(dev, data->output);
irq_unlock(key);
return 0;
}
static int neorv32_gpio_manage_callback(const struct device *dev,
struct gpio_callback *cb,
bool set)
{
ARG_UNUSED(dev);
ARG_UNUSED(cb);
ARG_UNUSED(set);
return -ENOTSUP;
}
static uint32_t neorv32_gpio_get_pending_int(const struct device *dev)
{
return 0;
}
static int neorv32_gpio_init(const struct device *dev)
{
const struct neorv32_gpio_config *config = dev->config;
struct neorv32_gpio_data *data = dev->data;
uint32_t features;
int err;
if (!device_is_ready(config->syscon)) {
LOG_ERR("syscon device not ready");
return -EINVAL;
}
err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
if (err < 0) {
LOG_ERR("failed to determine implemented features (err %d)", err);
return -EIO;
}
if ((features & NEORV32_SYSINFO_FEATURES_IO_GPIO) == 0) {
LOG_ERR("neorv32 gpio not supported");
return -ENODEV;
}
neorv32_gpio_write(dev, data->output);
return 0;
}
static const struct gpio_driver_api neorv32_gpio_driver_api = {
.pin_configure = neorv32_gpio_pin_configure,
.port_get_raw = neorv32_gpio_port_get_raw,
.port_set_masked_raw = neorv32_gpio_port_set_masked_raw,
.port_set_bits_raw = neorv32_gpio_port_set_bits_raw,
.port_clear_bits_raw = neorv32_gpio_port_clear_bits_raw,
.port_toggle_bits = neorv32_gpio_port_toggle_bits,
.manage_callback = neorv32_gpio_manage_callback,
.get_pending_int = neorv32_gpio_get_pending_int,
};
#define NEORV32_GPIO_INIT(n) \
static struct neorv32_gpio_data neorv32_gpio_##n##_data = { \
.output = 0, \
}; \
\
static const struct neorv32_gpio_config neorv32_gpio_##n##_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
}, \
.syscon = DEVICE_DT_GET(DT_INST_PHANDLE(n, syscon)), \
.input = DT_INST_REG_ADDR_BY_NAME(n, input), \
.output = DT_INST_REG_ADDR_BY_NAME(n, output), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
neorv32_gpio_init, \
NULL, \
&neorv32_gpio_##n##_data, \
&neorv32_gpio_##n##_config, \
PRE_KERNEL_2, \
CONFIG_GPIO_INIT_PRIORITY, \
&neorv32_gpio_driver_api);
DT_INST_FOREACH_STATUS_OKAY(NEORV32_GPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_neorv32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,560 |
```unknown
# NPCX GPIO driver configuration options
config GPIO_NPCX
bool "Nuvoton NPCX embedded controller (EC) gpio driver"
default y
depends on DT_HAS_NUVOTON_NPCX_GPIO_ENABLED
help
This option enables the GPIO driver for NPCX family of
processors.
Say y if you wish to use serial port on NPCX MCU.
``` | /content/code_sandbox/drivers/gpio/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```c
/**
* 2022 Ithinx GmbH
* 2023 Amrith Venkat Kesavamoorthi <amrith@mr-beam.org>
* 2023 Mr Beam Lasers GmbH.
*
*
* @see path_to_url
* @see path_to_url
*/
#define DT_DRV_COMPAT nxp_pcf857x
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(pcf857x, CONFIG_GPIO_LOG_LEVEL);
struct pcf857x_pins_cfg {
uint16_t configured_as_outputs; /* 0 for input, 1 for output */
uint16_t outputs_state;
};
/** Runtime driver data of the pcf857x*/
struct pcf857x_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct pcf857x_pins_cfg pins_cfg;
sys_slist_t callbacks;
struct k_sem lock;
struct k_work work;
const struct device *dev;
struct gpio_callback int_gpio_cb;
uint16_t input_port_last;
int num_bytes;
};
/** Configuration data*/
struct pcf857x_drv_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec i2c;
struct gpio_dt_spec gpio_int;
};
/**
* @brief Reads the value of the pins from pcf857x respectively from a connected device.
*
* @param dev Pointer to the device structure of the driver instance.
* @param value Pointer to the input value. It contains the received Bytes(receives 2 Bytes for P0
* and P1).
*
* @retval 0 If successful.
* @retval Negative value for error code.
*/
static int pcf857x_process_input(const struct device *dev, gpio_port_value_t *value)
{
const struct pcf857x_drv_cfg *drv_cfg = dev->config;
struct pcf857x_drv_data *drv_data = dev->data;
int rc = 0;
uint8_t rx_buf[2] = {0};
rc = i2c_read_dt(&drv_cfg->i2c, rx_buf, drv_data->num_bytes);
if (rc != 0) {
LOG_ERR("%s: failed to read from device: %d", dev->name, rc);
return -EIO;
}
if (value) {
*value = sys_get_le16(rx_buf); /*format P17-P10..P07-P00 (bit15-bit8..bit7-bit0)*/
}
drv_data->input_port_last = sys_get_le16(rx_buf);
return rc;
}
/** Register the read-task as work*/
static void pcf857x_work_handler(struct k_work *work)
{
struct pcf857x_drv_data *drv_data = CONTAINER_OF(work, struct pcf857x_drv_data, work);
k_sem_take(&drv_data->lock, K_FOREVER);
uint32_t changed_pins;
uint16_t input_port_last_temp = drv_data->input_port_last;
int rc = pcf857x_process_input(drv_data->dev, &changed_pins);
if (rc) {
LOG_ERR("Failed to read interrupt sources: %d", rc);
}
k_sem_give(&drv_data->lock);
if (input_port_last_temp != (uint16_t)changed_pins && !rc) {
/** Find changed bits*/
changed_pins ^= input_port_last_temp;
gpio_fire_callbacks(&drv_data->callbacks, drv_data->dev, changed_pins);
}
}
/** Callback for interrupt through some level changes on pcf857x pins*/
static void pcf857x_int_gpio_handler(const struct device *dev, struct gpio_callback *gpio_cb,
uint32_t pins)
{
ARG_UNUSED(dev);
ARG_UNUSED(pins);
struct pcf857x_drv_data *drv_data =
CONTAINER_OF(gpio_cb, struct pcf857x_drv_data, int_gpio_cb);
k_work_submit(&drv_data->work);
}
/**
* @brief This function reads a value from the connected device
*
* @param dev Pointer to the device structure of a port.
* @param value Pointer to a variable where pin values will be stored.
*
* @retval 0 If successful.
* @retval Negative value for error code.
*/
static int pcf857x_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
struct pcf857x_drv_data *drv_data = dev->data;
int rc;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if ((~drv_data->pins_cfg.configured_as_outputs & (uint16_t)*value) != (uint16_t)*value) {
LOG_ERR("Pin(s) is/are configured as output which should be input.");
return -EOPNOTSUPP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
/**
* Reading of the input port also clears the generated interrupt,
* thus the configured callbacks must be fired also here if needed.
*/
rc = pcf857x_process_input(dev, value);
k_sem_give(&drv_data->lock);
return rc;
}
/**
* @brief This function realizes the write connection to the i2c device.
*
* @param dev A pointer to the device structure
* @param mask A mask of bits to set some bits to LOW or HIGH
* @param value The value which is written via i2c to the pcf857x's output pins
* @param toggle A way to toggle some bits with xor
*
* @retval 0 If successful.
* @retval Negative value for error code.
*/
static int pcf857x_port_set_raw(const struct device *dev, uint16_t mask, uint16_t value,
uint16_t toggle)
{
const struct pcf857x_drv_cfg *drv_cfg = dev->config;
struct pcf857x_drv_data *drv_data = dev->data;
int rc = 0;
uint16_t tx_buf;
uint8_t tx_buf_p[2];
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if ((drv_data->pins_cfg.configured_as_outputs & value) != value) {
LOG_ERR("Pin(s) is/are configured as input which should be output.");
return -EOPNOTSUPP;
}
tx_buf = (drv_data->pins_cfg.outputs_state & ~mask);
tx_buf |= (value & mask);
tx_buf ^= toggle;
sys_put_le16(tx_buf, tx_buf_p);
rc = i2c_write_dt(&drv_cfg->i2c, tx_buf_p, drv_data->num_bytes);
if (rc != 0) {
LOG_ERR("%s: failed to write output port: %d", dev->name, rc);
return -EIO;
}
k_sem_take(&drv_data->lock, K_FOREVER);
drv_data->pins_cfg.outputs_state = tx_buf;
k_sem_give(&drv_data->lock);
return 0;
}
/**
* @brief This function fills a dummy because the pcf857x has no pins to configure.
* You can use it to set some pins permanent to HIGH or LOW until reset. It uses the port_set_raw
* function to set the pins of pcf857x directly.
*
* @param dev Pointer to the device structure for the driver instance.
* @param pin The bit in the io register which is set to high
* @param flags Flags like the GPIO direction or the state
*
* @retval 0 If successful.
* @retval Negative value for error.
*/
static int pcf857x_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
struct pcf857x_drv_data *drv_data = dev->data;
int ret = 0;
uint16_t temp_pins = drv_data->pins_cfg.outputs_state;
uint16_t temp_outputs = drv_data->pins_cfg.configured_as_outputs;
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_DISCONNECTED | GPIO_SINGLE_ENDED)) {
return -ENOTSUP;
}
if (flags & GPIO_INPUT) {
temp_outputs &= ~BIT(pin);
temp_pins &= ~(1 << pin);
} else if (flags & GPIO_OUTPUT) {
drv_data->pins_cfg.configured_as_outputs |= BIT(pin);
temp_outputs = drv_data->pins_cfg.configured_as_outputs;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
temp_pins |= (1 << pin);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
temp_pins &= ~(1 << pin);
}
ret = pcf857x_port_set_raw(dev, drv_data->pins_cfg.configured_as_outputs, temp_pins, 0);
if (ret == 0) {
k_sem_take(&drv_data->lock, K_FOREVER);
drv_data->pins_cfg.outputs_state = temp_pins;
drv_data->pins_cfg.configured_as_outputs = temp_outputs;
k_sem_give(&drv_data->lock);
}
return ret;
}
/**
* @brief Sets a value to the pins of pcf857x
*
* @param dev Pointer to the device structure for the driver instance.
* @param mask The bit mask which bits should be set
* @param value The value which should be set
*
* @retval 0 If successful.
* @retval Negative value for error.
*/
static int pcf857x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
return pcf857x_port_set_raw(dev, (uint16_t)mask, (uint16_t)value, 0);
}
/**
* @brief Sets some output pins of the pcf857x
*
* @param dev Pointer to the device structure for the driver instance.
* @param pins The pin(s) which will be set in a range from P17-P10..P07-P00
*
* @retval 0 If successful.
* @retval Negative value for error.
*/
static int pcf857x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return pcf857x_port_set_raw(dev, (uint16_t)pins, (uint16_t)pins, 0);
}
/**
* @brief clear some bits
*
* @param dev Pointer to the device structure for the driver instance.
* @param pins Pins which will be cleared
*
* @retval 0 If successful.
* @retval Negative value for error.
*/
static int pcf857x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return pcf857x_port_set_raw(dev, (uint16_t)pins, 0, 0);
}
/**
* @brief Toggle some bits
*
* @param dev Pointer to the device structure for the driver instance.
* @param pins Pins which will be toggled
*
* @retval 0 If successful.
* @retval Negative value for error.
*/
static int pcf857x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
return pcf857x_port_set_raw(dev, 0, 0, (uint16_t)pins);
}
/* Each pin gives an interrupt at pcf857x. In this function the configuration is checked. */
static int pcf857x_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct pcf857x_drv_cfg *drv_cfg = dev->config;
if (!drv_cfg->gpio_int.port) {
return -ENOTSUP;
}
/* This device supports only edge-triggered interrupts. */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
return 0;
}
/** Register the callback in the callback list */
static int pcf857x_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct pcf857x_drv_data *drv_data = dev->data;
return gpio_manage_callback(&drv_data->callbacks, callback, set);
}
/** Initialize the pcf857x */
static int pcf857x_init(const struct device *dev)
{
const struct pcf857x_drv_cfg *drv_cfg = dev->config;
struct pcf857x_drv_data *drv_data = dev->data;
int rc;
if (!device_is_ready(drv_cfg->i2c.bus)) {
LOG_ERR("%s is not ready", drv_cfg->i2c.bus->name);
return -ENODEV;
}
/* If the INT line is available, configure the callback for it. */
if (drv_cfg->gpio_int.port) {
if (!gpio_is_ready_dt(&drv_cfg->gpio_int)) {
LOG_ERR("Port is not ready");
return -ENODEV;
}
rc = gpio_pin_configure_dt(&drv_cfg->gpio_int, GPIO_INPUT);
if (rc != 0) {
LOG_ERR("%s: failed to configure INT line: %d", dev->name, rc);
return -EIO;
}
rc = gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
if (rc != 0) {
LOG_ERR("%s: failed to configure INT interrupt: %d", dev->name, rc);
return -EIO;
}
gpio_init_callback(&drv_data->int_gpio_cb, pcf857x_int_gpio_handler,
BIT(drv_cfg->gpio_int.pin));
rc = gpio_add_callback(drv_cfg->gpio_int.port, &drv_data->int_gpio_cb);
if (rc != 0) {
LOG_ERR("%s: failed to add INT callback: %d", dev->name, rc);
return -EIO;
}
}
return 0;
}
/** Realizes the functions of gpio.h for pcf857x*/
static const struct gpio_driver_api pcf857x_drv_api = {
.pin_configure = pcf857x_pin_configure,
.port_get_raw = pcf857x_port_get_raw,
.port_set_masked_raw = pcf857x_port_set_masked_raw,
.port_set_bits_raw = pcf857x_port_set_bits_raw,
.port_clear_bits_raw = pcf857x_port_clear_bits_raw,
.port_toggle_bits = pcf857x_port_toggle_bits,
.pin_interrupt_configure = pcf857x_pin_interrupt_configure,
.manage_callback = pcf857x_manage_callback,
};
#define GPIO_PCF857X_INST(idx) \
static const struct pcf857x_drv_cfg pcf857x_cfg##idx = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
}, \
.gpio_int = GPIO_DT_SPEC_INST_GET_OR(idx, int_gpios, {0}), \
.i2c = I2C_DT_SPEC_INST_GET(idx), \
}; \
static struct pcf857x_drv_data pcf857x_data##idx = { \
.lock = Z_SEM_INITIALIZER(pcf857x_data##idx.lock, 1, 1), \
.work = Z_WORK_INITIALIZER(pcf857x_work_handler), \
.dev = DEVICE_DT_INST_GET(idx), \
.num_bytes = DT_INST_ENUM_IDX(idx, ngpios) + 1, \
}; \
DEVICE_DT_INST_DEFINE(idx, pcf857x_init, NULL, &pcf857x_data##idx, &pcf857x_cfg##idx, \
POST_KERNEL, CONFIG_GPIO_PCF857X_INIT_PRIORITY, &pcf857x_drv_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_PCF857X_INST);
``` | /content/code_sandbox/drivers/gpio/gpio_pcf857x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,371 |
```unknown
# MCUX IGPIO configuration options
config GPIO_MCUX_IGPIO
bool "MCUX IGPIO driver"
default y
depends on HAS_MCUX_IGPIO
depends on DT_HAS_NXP_IMX_GPIO_ENABLED
select PINCTRL
help
Enable the MCUX IGPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.mcux_igpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
# DesignWare GPIO configuration options
config GPIO_DW
bool "Designware GPIO"
default y
depends on DT_HAS_SNPS_DESIGNWARE_GPIO_ENABLED
help
Enable driver for Designware GPIO
``` | /content/code_sandbox/drivers/gpio/Kconfig.dw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_sc18im704_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_sc18im, CONFIG_GPIO_LOG_LEVEL);
#include "i2c/i2c_sc18im704.h"
#define GPIO_SC18IM_MAX_PINS 8
/* After reset the GPIO config registers are 0x55 */
#define GPIO_SC18IM_DEFAULT_CONF 0x55
#define GPIO_SC18IM_CONF_INPUT 0x01
#define GPIO_SC18IM_CONF_PUSH_PULL 0x02
#define GPIO_SC18IM_CONF_OPEN_DRAIN 0x03
#define GPIO_SC18IM_CONF_MASK 0x03
struct gpio_sc18im_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *bridge;
};
struct gpio_sc18im_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
uint8_t conf1;
uint8_t conf2;
uint8_t output_state;
};
static int gpio_sc18im_port_set_raw(const struct device *port,
uint8_t mask, uint8_t value, uint8_t toggle)
{
const struct gpio_sc18im_config *cfg = port->config;
struct gpio_sc18im_data *data = port->data;
uint8_t buf[] = {
SC18IM704_CMD_WRITE_GPIO,
data->output_state,
SC18IM704_CMD_STOP,
};
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
buf[1] &= ~mask;
buf[1] |= (value & mask);
buf[1] ^= toggle;
ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), NULL, 0);
if (ret < 0) {
LOG_ERR("Failed to write GPIO state (%d)", ret);
return ret;
}
data->output_state = buf[1];
return 0;
}
static int gpio_sc18im_pin_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_sc18im_config *cfg = port->config;
struct gpio_sc18im_data *data = port->data;
uint8_t pin_conf;
int ret;
uint8_t buf[] = {
SC18IM704_CMD_WRITE_REG,
0x00,
0x00,
SC18IM704_CMD_STOP,
};
if (pin >= GPIO_SC18IM_MAX_PINS) {
return -EINVAL;
}
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
return -ENOTSUP;
}
if (flags & GPIO_INPUT) {
pin_conf = GPIO_SC18IM_CONF_INPUT;
} else if (flags & GPIO_OUTPUT) {
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
pin_conf = GPIO_SC18IM_CONF_OPEN_DRAIN;
} else {
/* Open-drain is the only supported single-ended mode */
return -ENOTSUP;
}
} else {
/* Default to push/pull */
pin_conf = GPIO_SC18IM_CONF_PUSH_PULL;
}
} else {
/* Neither input nor output mode is selected */
return -ENOTSUP;
}
ret = sc18im704_claim(cfg->bridge);
if (ret < 0) {
LOG_ERR("Failed to claim bridge (%d)", ret);
return ret;
}
if (pin < 4) {
/* Shift the config to the pin offset */
data->conf1 &= ~(GPIO_SC18IM_CONF_MASK << (pin * 2));
data->conf1 |= pin_conf << (pin * 2);
buf[1] = SC18IM704_REG_GPIO_CONF1;
buf[2] = data->conf1;
} else {
/* Shift the config to the pin offset */
data->conf2 &= ~(GPIO_SC18IM_CONF_MASK << ((pin - 4) * 2));
data->conf2 |= pin_conf << ((pin - 4) * 2);
buf[1] = SC18IM704_REG_GPIO_CONF2;
buf[2] = data->conf2;
}
ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), NULL, 0);
if (ret < 0) {
LOG_ERR("Failed to configure GPIO (%d)", ret);
}
if (ret == 0 && flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_sc18im_port_set_raw(port, BIT(pin), BIT(pin), 0);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_sc18im_port_set_raw(port, BIT(pin), 0, 0);
}
}
sc18im704_release(cfg->bridge);
return ret;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_sc18im_pin_get_config(const struct device *port, gpio_pin_t pin,
gpio_flags_t *flags)
{
struct gpio_sc18im_data *data = port->data;
uint8_t conf;
if (pin >= GPIO_SC18IM_MAX_PINS) {
return -EINVAL;
}
if (pin < 4) {
conf = (data->conf1 >> (2 * pin)) & GPIO_SC18IM_CONF_MASK;
} else {
conf = (data->conf2 >> (2 * (pin - 4))) & GPIO_SC18IM_CONF_MASK;
}
switch (conf) {
case GPIO_SC18IM_CONF_PUSH_PULL:
*flags = GPIO_OUTPUT | GPIO_PUSH_PULL;
break;
case GPIO_SC18IM_CONF_OPEN_DRAIN:
*flags = GPIO_OUTPUT | GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN;
break;
case GPIO_SC18IM_CONF_INPUT:
default:
*flags = GPIO_INPUT;
break;
}
return 0;
}
#endif
static int gpio_sc18im_port_get_raw(const struct device *port, gpio_port_value_t *value)
{
const struct gpio_sc18im_config *cfg = port->config;
uint8_t buf[] = {
SC18IM704_CMD_READ_GPIO,
SC18IM704_CMD_STOP,
};
uint8_t data;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), &data, 1);
if (ret < 0) {
LOG_ERR("Failed to read GPIO state (%d)", ret);
return ret;
}
*value = data;
return 0;
}
static int gpio_sc18im_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return gpio_sc18im_port_set_raw(port, (uint8_t)mask, (uint8_t)value, 0);
}
static int gpio_sc18im_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
return gpio_sc18im_port_set_raw(port, (uint8_t)pins, (uint8_t)pins, 0);
}
static int gpio_sc18im_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
{
return gpio_sc18im_port_set_raw(port, (uint8_t)pins, 0, 0);
}
static int gpio_sc18im_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
{
return gpio_sc18im_port_set_raw(port, 0, 0, (uint8_t)pins);
}
static int gpio_sc18im_init(const struct device *dev)
{
const struct gpio_sc18im_config *cfg = dev->config;
if (!device_is_ready(cfg->bridge)) {
LOG_ERR("Parent device not ready");
return -ENODEV;
}
return 0;
}
static const struct gpio_driver_api gpio_sc18im_driver_api = {
.pin_configure = gpio_sc18im_pin_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_sc18im_pin_get_config,
#endif
.port_get_raw = gpio_sc18im_port_get_raw,
.port_set_masked_raw = gpio_sc18im_port_set_masked_raw,
.port_set_bits_raw = gpio_sc18im_port_set_bits_raw,
.port_clear_bits_raw = gpio_sc18im_port_clear_bits_raw,
.port_toggle_bits = gpio_sc18im_port_toggle_bits,
};
#define CHECK_COMPAT(node) \
COND_CODE_1(DT_NODE_HAS_COMPAT(node, nxp_sc18im704_i2c), (DEVICE_DT_GET(node)), ())
#define GPIO_SC18IM704_I2C_SIBLING(n) \
DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_PARENT(n), CHECK_COMPAT)
#define GPIO_SC18IM704_DEFINE(n) \
static const struct gpio_sc18im_config gpio_sc18im_config_##n = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.bridge = GPIO_SC18IM704_I2C_SIBLING(n), \
}; \
static struct gpio_sc18im_data gpio_sc18im_data_##n = { \
.conf1 = GPIO_SC18IM_DEFAULT_CONF, \
.conf2 = GPIO_SC18IM_DEFAULT_CONF, \
}; \
\
DEVICE_DT_INST_DEFINE(n, gpio_sc18im_init, NULL, \
&gpio_sc18im_data_##n, &gpio_sc18im_config_##n, \
POST_KERNEL, CONFIG_GPIO_SC18IM704_INIT_PRIORITY, \
&gpio_sc18im_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_SC18IM704_DEFINE);
``` | /content/code_sandbox/drivers/gpio/gpio_sc18im704.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,155 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_gpio_emul
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_emul.h>
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_emul);
#define GPIO_EMUL_INT_BITMASK \
(GPIO_INT_DISABLE | GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | \
GPIO_INT_EDGE | GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)
/**
* @brief GPIO Emulator interrupt capabilities
*
* These enumerations are used as a bitmask and allow the GPIO Emulator to
* model GPIO interrupt controllers with varying interrupt trigger support.
*
* For example, some controllers to not support level interrupts,
* some controllers do not support rising and falling edge simultaneously,
* etc.
*
* This primarily affects the behaviour of @ref gpio_pin_interrupt_configure.
*/
enum gpio_emul_interrupt_cap {
GPIO_EMUL_INT_CAP_EDGE_RISING = 1,
GPIO_EMUL_INT_CAP_EDGE_FALLING = 2,
GPIO_EMUL_INT_CAP_LEVEL_HIGH = 16,
GPIO_EMUL_INT_CAP_LEVEL_LOW = 32,
};
/**
* @brief Emulated GPIO controller configuration data
*
* This structure contains all of the state for a given emulated GPIO
* controller as well as all of the pins associated with it.
*
* The @a flags member is a pointer to an array which is @a num_pins in size.
*
* @a num_pins must be in the range [1, @ref GPIO_MAX_PINS_PER_PORT].
*
* Pin direction as well as other pin properties are set using
* specific bits in @a flags. For more details, see @ref gpio_interface.
*
* Changes are synchronized using @ref gpio_emul_data.mu.
*/
struct gpio_emul_config {
/** Common @ref gpio_driver_config */
const struct gpio_driver_config common;
/** Number of pins available in the given GPIO controller instance */
const gpio_pin_t num_pins;
/** Supported interrupts */
const enum gpio_emul_interrupt_cap interrupt_caps;
};
/**
* @brief Emulated GPIO controller data
*
* This structure contains data structures used by a emulated GPIO
* controller.
*
* If the application wishes to specify a "wiring" for the emulated
* GPIO, then a @ref gpio_callback_handler_t should be registered using
* @ref gpio_add_callback.
*
* Changes are to @ref gpio_emul_data and @ref gpio_emul_config are
* synchronized using @a k_spinlock.
*/
struct gpio_emul_data {
/** Common @ref gpio_driver_data */
struct gpio_driver_data common;
/** Pointer to an array of flags is @a num_pins in size */
gpio_flags_t *flags;
/** Input values for each pin */
gpio_port_value_t input_vals;
/** Output values for each pin */
gpio_port_value_t output_vals;
/** Interrupt status for each pin */
gpio_port_pins_t interrupts;
/** Spinlock to synchronize accesses to driver data and config */
struct k_spinlock lock;
/** Is interrupt enabled for each pin */
gpio_port_pins_t enabled_interrupts;
/** Singly-linked list of callbacks associated with the controller */
sys_slist_t callbacks;
};
/**
* @brief Obtain a mask of pins that match all of the provided @p flags
*
* Use this function to see which pins match the current GPIO configuration.
*
* The caller must ensure that @ref gpio_emul_data.lock is locked.
*
* @param port The emulated GPIO device pointer
* @param mask A mask of flags to match
* @param flags The flags to match
*
* @return a mask of the pins with matching @p flags
*/
static gpio_port_pins_t
get_pins_with_flags(const struct device *port, gpio_port_pins_t mask,
gpio_flags_t flags)
{
size_t i;
gpio_port_pins_t matched = 0;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
for (i = 0; i < config->num_pins; ++i) {
if ((drv_data->flags[i] & mask) == flags) {
matched |= BIT(i);
}
}
return matched;
}
/**
* @brief Obtain a mask of pins that are configured as @ref GPIO_INPUT
*
* The caller must ensure that @ref gpio_emul_data.lock is locked.
*
* @param port The emulated GPIO device pointer
*
* @return a mask of pins that are configured as @ref GPIO_INPUT
*/
static inline gpio_port_pins_t get_input_pins(const struct device *port)
{
return get_pins_with_flags(port, GPIO_INPUT, GPIO_INPUT);
}
/**
* @brief Obtain a mask of pins that are configured as @ref GPIO_OUTPUT
*
* The caller must ensure that @ref gpio_emul_data.lock is locked.
*
* @param port The emulated GPIO device pointer
*
* @return a mask of pins that are configured as @ref GPIO_OUTPUT
*/
static inline gpio_port_pins_t get_output_pins(const struct device *port)
{
return get_pins_with_flags(port, GPIO_OUTPUT, GPIO_OUTPUT);
}
/**
* Check if @p port has capabilities specified in @p caps
*
* @param port The emulated GPIO device pointer
* @param caps A bitmask of @ref gpio_emul_interrupt_cap
*
* @return true if all @p caps are present, otherwise false
*/
static inline bool gpio_emul_config_has_caps(const struct device *port,
int caps) {
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
return (caps & config->interrupt_caps) == caps;
}
/*
* GPIO backend API (for setting input pin values)
*/
static void gpio_emul_gen_interrupt_bits(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t prev_values,
gpio_port_value_t values,
gpio_port_pins_t *interrupts,
bool detect_edge)
{
size_t i;
bool bit;
bool prev_bit;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
for (i = 0, *interrupts = 0; mask && i < config->num_pins;
++i, mask >>= 1, prev_values >>= 1, values >>= 1) {
if ((mask & 1) == 0) {
continue;
}
prev_bit = ((prev_values & 1) != 0);
bit = ((values & 1) != 0);
switch (drv_data->flags[i] & GPIO_EMUL_INT_BITMASK) {
case GPIO_INT_EDGE_RISING:
if (gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_EDGE_RISING)) {
if (detect_edge && !prev_bit && bit) {
drv_data->interrupts |= BIT(i);
*interrupts |= (BIT(i) & drv_data->enabled_interrupts);
}
}
break;
case GPIO_INT_EDGE_FALLING:
if (gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_EDGE_FALLING)) {
if (detect_edge && prev_bit && !bit) {
drv_data->interrupts |= BIT(i);
*interrupts |= (BIT(i) & drv_data->enabled_interrupts);
}
}
break;
case GPIO_INT_EDGE_BOTH:
if (gpio_emul_config_has_caps(port,
GPIO_EMUL_INT_CAP_EDGE_RISING | GPIO_EMUL_INT_CAP_EDGE_FALLING)) {
if (detect_edge && prev_bit != bit) {
drv_data->interrupts |= BIT(i);
*interrupts |= (BIT(i) & drv_data->enabled_interrupts);
}
}
break;
case GPIO_INT_LEVEL_LOW:
if (gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_LEVEL_LOW)) {
if (!bit) {
drv_data->interrupts |= BIT(i);
*interrupts |= (BIT(i) & drv_data->enabled_interrupts);
}
}
break;
case GPIO_INT_LEVEL_HIGH:
if (gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_LEVEL_HIGH)) {
if (bit) {
drv_data->interrupts |= BIT(i);
*interrupts |= (BIT(i) & drv_data->enabled_interrupts);
}
}
break;
case 0:
case GPIO_INT_DISABLE:
break;
default:
LOG_DBG("unhandled case %u",
drv_data->flags[i] & GPIO_EMUL_INT_BITMASK);
break;
}
}
}
/**
* @brief Trigger possible interrupt events after an input pin has changed
*
* For more information, see @ref gpio_interface.
*
* The caller must ensure that @ref gpio_emul_data.lock is locked.
*
* @param port The emulated GPIO port
* @param mask The mask of pins that have changed
* @param prev_values Previous pin values
* @param values Current pin values
*/
static void gpio_emul_pend_interrupt(const struct device *port, gpio_port_pins_t mask,
gpio_port_value_t prev_values,
gpio_port_value_t values)
{
gpio_port_pins_t interrupts;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
key = k_spin_lock(&drv_data->lock);
gpio_emul_gen_interrupt_bits(port, mask, prev_values, values,
&interrupts, true);
while (interrupts != 0) {
k_spin_unlock(&drv_data->lock, key);
gpio_fire_callbacks(&drv_data->callbacks, port, interrupts);
key = k_spin_lock(&drv_data->lock);
/* Clear handled interrupts */
drv_data->interrupts &= ~interrupts;
gpio_emul_gen_interrupt_bits(port, mask, prev_values, values,
&interrupts, false);
}
k_spin_unlock(&drv_data->lock, key);
}
int gpio_emul_input_set_masked_int(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t values)
{
gpio_port_pins_t input_mask;
gpio_port_pins_t prev_values;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
if (mask == 0) {
return 0;
}
if (~config->common.port_pin_mask & mask) {
LOG_ERR("Pin not supported port_pin_mask=%x mask=%x",
config->common.port_pin_mask, mask);
return -EINVAL;
}
input_mask = get_input_pins(port);
if (~input_mask & mask) {
LOG_ERR("Not input pin input_mask=%x mask=%x", input_mask,
mask);
return -EINVAL;
}
prev_values = drv_data->input_vals;
drv_data->input_vals &= ~mask;
drv_data->input_vals |= values & mask;
return 0;
}
/* documented in drivers/gpio/gpio_emul.h */
int gpio_emul_input_set_masked(const struct device *port, gpio_port_pins_t mask,
gpio_port_value_t values)
{
struct gpio_emul_data *drv_data = (struct gpio_emul_data *)port->data;
gpio_port_pins_t prev_input_values;
gpio_port_pins_t input_values;
k_spinlock_key_t key;
int rv;
key = k_spin_lock(&drv_data->lock);
prev_input_values = drv_data->input_vals;
rv = gpio_emul_input_set_masked_int(port, mask, values);
input_values = drv_data->input_vals;
k_spin_unlock(&drv_data->lock, key);
if (rv) {
return rv;
}
gpio_emul_pend_interrupt(port, mask, prev_input_values, input_values);
return 0;
}
/* documented in drivers/gpio/gpio_emul.h */
int gpio_emul_output_get_masked(const struct device *port, gpio_port_pins_t mask,
gpio_port_value_t *values)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
k_spinlock_key_t key;
if (mask == 0) {
return 0;
}
if (~config->common.port_pin_mask & mask) {
return -EINVAL;
}
key = k_spin_lock(&drv_data->lock);
*values = drv_data->output_vals & get_output_pins(port);
k_spin_unlock(&drv_data->lock, key);
return 0;
}
/* documented in drivers/gpio/gpio_emul.h */
int gpio_emul_flags_get(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
k_spinlock_key_t key;
if (flags == NULL) {
return -EINVAL;
}
if ((config->common.port_pin_mask & BIT(pin)) == 0) {
return -EINVAL;
}
key = k_spin_lock(&drv_data->lock);
*flags = drv_data->flags[pin];
k_spin_unlock(&drv_data->lock, key);
return 0;
}
/*
* GPIO Driver API
*
* API is documented at drivers/gpio.h
*/
static int gpio_emul_pin_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
k_spinlock_key_t key;
int rv;
if (flags & GPIO_OPEN_DRAIN) {
return -ENOTSUP;
}
if (flags & GPIO_OPEN_SOURCE) {
return -ENOTSUP;
}
if ((config->common.port_pin_mask & BIT(pin)) == 0) {
return -EINVAL;
}
key = k_spin_lock(&drv_data->lock);
drv_data->flags[pin] = flags;
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_LOW) {
drv_data->output_vals &= ~BIT(pin);
if (flags & GPIO_INPUT) {
/* for push-pull mode to generate interrupts */
rv = gpio_emul_input_set_masked_int(
port, BIT(pin), drv_data->output_vals);
__ASSERT_NO_MSG(rv == 0);
}
} else if (flags & GPIO_OUTPUT_INIT_HIGH) {
drv_data->output_vals |= BIT(pin);
if (flags & GPIO_INPUT) {
/* for push-pull mode to generate interrupts */
rv = gpio_emul_input_set_masked_int(
port, BIT(pin), drv_data->output_vals);
__ASSERT_NO_MSG(rv == 0);
}
}
} else if (flags & GPIO_INPUT) {
if (flags & GPIO_PULL_UP) {
rv = gpio_emul_input_set_masked_int(port, BIT(pin), BIT(pin));
__ASSERT_NO_MSG(rv == 0);
} else if (flags & GPIO_PULL_DOWN) {
rv = gpio_emul_input_set_masked_int(
port, BIT(pin), 0);
__ASSERT_NO_MSG(rv == 0);
}
}
k_spin_unlock(&drv_data->lock, key);
gpio_fire_callbacks(&drv_data->callbacks, port, BIT(pin));
/* GPIO pin configuration changed so clear the pending interrupt. */
drv_data->interrupts &= ~((gpio_port_pins_t)BIT(pin));
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_emul_pin_get_config(const struct device *port, gpio_pin_t pin,
gpio_flags_t *out_flags)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
key = k_spin_lock(&drv_data->lock);
*out_flags = drv_data->flags[pin] &
~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH
| GPIO_OUTPUT_INIT_LOGICAL);
if (drv_data->flags[pin] & GPIO_OUTPUT) {
if (drv_data->output_vals & BIT(pin)) {
*out_flags |= GPIO_OUTPUT_HIGH;
} else {
*out_flags |= GPIO_OUTPUT_LOW;
}
}
k_spin_unlock(&drv_data->lock, key);
return 0;
}
#endif
static int gpio_emul_port_get_raw(const struct device *port, gpio_port_value_t *values)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
if (values == NULL) {
return -EINVAL;
}
key = k_spin_lock(&drv_data->lock);
*values = drv_data->input_vals & get_input_pins(port);
k_spin_unlock(&drv_data->lock, key);
return 0;
}
static int gpio_emul_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t values)
{
gpio_port_pins_t output_mask;
gpio_port_pins_t prev_values;
gpio_port_pins_t prev_input_values;
gpio_port_pins_t input_values;
gpio_port_pins_t input_mask;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
int rv;
key = k_spin_lock(&drv_data->lock);
output_mask = get_output_pins(port);
mask &= output_mask;
prev_values = drv_data->output_vals;
prev_values &= output_mask;
values &= mask;
drv_data->output_vals &= ~mask;
drv_data->output_vals |= values;
/* in push-pull, set input values & fire interrupts */
prev_input_values = drv_data->input_vals;
input_mask = mask & get_input_pins(port);
rv = gpio_emul_input_set_masked_int(port, input_mask,
drv_data->output_vals);
input_values = drv_data->input_vals;
k_spin_unlock(&drv_data->lock, key);
__ASSERT_NO_MSG(rv == 0);
gpio_emul_pend_interrupt(port, input_mask, prev_input_values, input_values);
/* for output-wiring, so the user can take action based on output */
if (prev_values ^ values) {
gpio_fire_callbacks(&drv_data->callbacks, port, mask & ~get_input_pins(port));
}
return 0;
}
static int gpio_emul_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
gpio_port_pins_t prev_input_values;
gpio_port_pins_t input_values;
gpio_port_pins_t input_mask;
int rv;
key = k_spin_lock(&drv_data->lock);
pins &= get_output_pins(port);
drv_data->output_vals |= pins;
prev_input_values = drv_data->input_vals;
input_mask = pins & get_input_pins(port);
rv = gpio_emul_input_set_masked_int(port, input_mask,
drv_data->output_vals);
input_values = drv_data->input_vals;
k_spin_unlock(&drv_data->lock, key);
__ASSERT_NO_MSG(rv == 0);
gpio_emul_pend_interrupt(port, input_mask, prev_input_values, input_values);
/* for output-wiring, so the user can take action based on output */
gpio_fire_callbacks(&drv_data->callbacks, port, pins & ~get_input_pins(port));
return 0;
}
static int gpio_emul_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
gpio_port_pins_t prev_input_values;
gpio_port_pins_t input_values;
gpio_port_pins_t input_mask;
int rv;
key = k_spin_lock(&drv_data->lock);
pins &= get_output_pins(port);
drv_data->output_vals &= ~pins;
prev_input_values = drv_data->input_vals;
input_mask = pins & get_input_pins(port);
rv = gpio_emul_input_set_masked_int(port, input_mask, drv_data->output_vals);
input_values = drv_data->input_vals;
k_spin_unlock(&drv_data->lock, key);
__ASSERT_NO_MSG(rv == 0);
gpio_emul_pend_interrupt(port, input_mask, prev_input_values, input_values);
/* for output-wiring, so the user can take action based on output */
gpio_fire_callbacks(&drv_data->callbacks, port, pins & ~get_input_pins(port));
return 0;
}
static int gpio_emul_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
k_spinlock_key_t key;
int rv;
key = k_spin_lock(&drv_data->lock);
drv_data->output_vals ^= (pins & get_output_pins(port));
/* in push-pull, set input values but do not fire interrupts (yet) */
rv = gpio_emul_input_set_masked_int(port, pins & get_input_pins(port),
drv_data->output_vals);
k_spin_unlock(&drv_data->lock, key);
__ASSERT_NO_MSG(rv == 0);
/* for output-wiring, so the user can take action based on output */
gpio_fire_callbacks(&drv_data->callbacks, port, pins);
return 0;
}
static bool gpio_emul_level_trigger_supported(const struct device *port,
enum gpio_int_trig trig)
{
switch (trig) {
case GPIO_INT_TRIG_LOW:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_LEVEL_LOW);
case GPIO_INT_TRIG_HIGH:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_LEVEL_HIGH);
case GPIO_INT_TRIG_BOTH:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_LEVEL_LOW
| GPIO_EMUL_INT_CAP_LEVEL_HIGH);
default:
return false;
}
}
static bool gpio_emul_edge_trigger_supported(const struct device *port,
enum gpio_int_trig trig)
{
switch (trig) {
case GPIO_INT_TRIG_LOW:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_EDGE_FALLING);
case GPIO_INT_TRIG_HIGH:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_EDGE_RISING);
case GPIO_INT_TRIG_BOTH:
return gpio_emul_config_has_caps(port, GPIO_EMUL_INT_CAP_EDGE_FALLING
| GPIO_EMUL_INT_CAP_EDGE_RISING);
default:
return false;
}
}
static int gpio_emul_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
int ret;
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config =
(const struct gpio_emul_config *)port->config;
k_spinlock_key_t key;
if ((BIT(pin) & config->common.port_pin_mask) == 0) {
return -EINVAL;
}
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode != GPIO_INT_MODE_DISABLED && !(mode & GPIO_INT_ENABLE_DISABLE_ONLY)) {
#else
if (mode != GPIO_INT_MODE_DISABLED) {
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
switch (trig) {
case GPIO_INT_TRIG_LOW:
case GPIO_INT_TRIG_HIGH:
case GPIO_INT_TRIG_BOTH:
break;
default:
return -EINVAL;
}
}
if (mode == GPIO_INT_MODE_LEVEL) {
if (!gpio_emul_level_trigger_supported(port, trig)) {
return -ENOTSUP;
}
}
if (mode == GPIO_INT_MODE_EDGE) {
if (!gpio_emul_edge_trigger_supported(port, trig)) {
return -ENOTSUP;
}
}
key = k_spin_lock(&drv_data->lock);
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
/* According to the GPIO interrupt configuration flag documentation,
* changes to the interrupt trigger properties should clear pending
* interrupts.
*/
if (!(mode & GPIO_INT_ENABLE_DISABLE_ONLY)) {
drv_data->interrupts &= ~((gpio_port_pins_t)BIT(pin));
}
#else
drv_data->interrupts &= ~((gpio_port_pins_t)BIT(pin));
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
switch (mode) {
case GPIO_INT_MODE_DISABLED:
drv_data->flags[pin] &= ~GPIO_EMUL_INT_BITMASK;
drv_data->flags[pin] |= GPIO_INT_DISABLE;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
__fallthrough;
case GPIO_INT_MODE_DISABLE_ONLY:
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
drv_data->enabled_interrupts &= ~((gpio_port_pins_t)BIT(pin));
break;
case GPIO_INT_MODE_LEVEL:
case GPIO_INT_MODE_EDGE:
drv_data->flags[pin] &= ~GPIO_EMUL_INT_BITMASK;
drv_data->flags[pin] |= (mode | trig);
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
__fallthrough;
case GPIO_INT_MODE_ENABLE_ONLY:
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
drv_data->enabled_interrupts |= BIT(pin);
break;
default:
ret = -EINVAL;
goto unlock;
}
ret = 0;
unlock:
k_spin_unlock(&drv_data->lock, key);
/* Trigger callback if this pin has pending interrupt */
if (BIT(pin) & (drv_data->interrupts & drv_data->enabled_interrupts)) {
gpio_fire_callbacks(&drv_data->callbacks, port, BIT(pin));
drv_data->interrupts &= ~((gpio_port_pins_t)BIT(pin));
}
return ret;
}
static int gpio_emul_manage_callback(const struct device *port,
struct gpio_callback *cb, bool set)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)port->data;
return gpio_manage_callback(&drv_data->callbacks, cb, set);
}
static gpio_port_pins_t gpio_emul_get_pending_int(const struct device *dev)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)dev->data;
return drv_data->interrupts;
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_emul_port_get_direction(const struct device *port, gpio_port_pins_t map,
gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
{
int i;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
struct gpio_emul_data *const drv_data = (struct gpio_emul_data *)port->data;
const struct gpio_emul_config *config = (const struct gpio_emul_config *)port->config;
map &= config->common.port_pin_mask;
if (inputs != NULL) {
for (i = find_lsb_set(map) - 1; map;
map &= ~BIT(i), i = find_lsb_set(map) - 1) {
ip |= !!(drv_data->flags[i] & GPIO_INPUT) * BIT(i);
}
*inputs = ip;
}
if (outputs != NULL) {
for (i = find_lsb_set(map) - 1; map;
map &= ~BIT(i), i = find_lsb_set(map) - 1) {
op |= !!(drv_data->flags[i] & GPIO_OUTPUT) * BIT(i);
}
*outputs = op;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static const struct gpio_driver_api gpio_emul_driver = {
.pin_configure = gpio_emul_pin_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_emul_pin_get_config,
#endif
.port_get_raw = gpio_emul_port_get_raw,
.port_set_masked_raw = gpio_emul_port_set_masked_raw,
.port_set_bits_raw = gpio_emul_port_set_bits_raw,
.port_clear_bits_raw = gpio_emul_port_clear_bits_raw,
.port_toggle_bits = gpio_emul_port_toggle_bits,
.pin_interrupt_configure = gpio_emul_pin_interrupt_configure,
.manage_callback = gpio_emul_manage_callback,
.get_pending_int = gpio_emul_get_pending_int,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_emul_port_get_direction,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
static int gpio_emul_init(const struct device *dev)
{
struct gpio_emul_data *drv_data =
(struct gpio_emul_data *)dev->data;
sys_slist_init(&drv_data->callbacks);
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int gpio_emul_pm_device_pm_action(const struct device *dev,
enum pm_device_action action)
{
ARG_UNUSED(dev);
ARG_UNUSED(action);
return 0;
}
#endif
/*
* Device Initialization
*/
#define GPIO_EMUL_INT_CAPS(_num) (0 \
+ DT_INST_PROP(_num, rising_edge) \
* GPIO_EMUL_INT_CAP_EDGE_RISING \
+ DT_INST_PROP(_num, falling_edge) \
* GPIO_EMUL_INT_CAP_EDGE_FALLING \
+ DT_INST_PROP(_num, high_level) \
* GPIO_EMUL_INT_CAP_LEVEL_HIGH \
+ DT_INST_PROP(_num, low_level) \
* GPIO_EMUL_INT_CAP_LEVEL_LOW \
)
#define DEFINE_GPIO_EMUL(_num) \
\
static gpio_flags_t \
gpio_emul_flags_##_num[DT_INST_PROP(_num, ngpios)]; \
\
static const struct gpio_emul_config gpio_emul_config_##_num = {\
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(_num), \
}, \
.num_pins = DT_INST_PROP(_num, ngpios), \
.interrupt_caps = GPIO_EMUL_INT_CAPS(_num) \
}; \
BUILD_ASSERT( \
DT_INST_PROP(_num, ngpios) <= GPIO_MAX_PINS_PER_PORT, \
"Too many ngpios"); \
\
static struct gpio_emul_data gpio_emul_data_##_num = { \
.flags = gpio_emul_flags_##_num, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(_num, gpio_emul_pm_device_pm_action); \
\
DEVICE_DT_INST_DEFINE(_num, gpio_emul_init, \
PM_DEVICE_DT_INST_GET(_num), \
&gpio_emul_data_##_num, \
&gpio_emul_config_##_num, POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_emul_driver);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_GPIO_EMUL)
``` | /content/code_sandbox/drivers/gpio/gpio_emul.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,733 |
```unknown
# Kconfig Andes ATCGPIO100 configuration option
#
#
#
config GPIO_ANDES_ATCGPIO100
bool "Andes ATCGPIO100 GPIO driver"
default y
depends on DT_HAS_ANDESTECH_ATCGPIO100_ENABLED
help
Enable driver for the Andes ATCGPIO100 GPIO controller.
Says n if not sure.
``` | /content/code_sandbox/drivers/gpio/Kconfig.andes_atcgpio100 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
menuconfig GPIO_NRFX
bool "nRF GPIO driver"
default y
depends on DT_HAS_NORDIC_NRF_GPIO_ENABLED
select NRFX_GPIOTE0 if HAS_HW_NRF_GPIOTE0
select NRFX_GPIOTE1 if HAS_HW_NRF_GPIOTE1
select NRFX_GPIOTE20 if HAS_HW_NRF_GPIOTE20
select NRFX_GPIOTE30 if HAS_HW_NRF_GPIOTE30
select NRFX_GPIOTE130 if HAS_HW_NRF_GPIOTE130
select NRFX_GPIOTE131 if HAS_HW_NRF_GPIOTE131
help
Enable GPIO driver for nRF line of MCUs.
config GPIO_NRFX_INTERRUPT
bool "Interrupt support"
depends on GPIO_NRFX
default y
help
The option can be used to disable the GPIO interrupt support to
significantly reduce memory footprint in case of application that does
not need GPIO interrupts.
``` | /content/code_sandbox/drivers/gpio/Kconfig.nrfx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_rcar_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
typedef void (*init_func_t)(const struct device *dev);
/* Required by DEVICE_MMIO_NAMED_* macros */
#define DEV_CFG(_dev) \
((const struct gpio_rcar_cfg *)(_dev)->config)
#define DEV_DATA(_dev) ((struct gpio_rcar_data *)(_dev)->data)
struct gpio_rcar_cfg {
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(reg_base);
init_func_t init_func;
const struct device *clock_dev;
struct rcar_cpg_clk mod_clk;
};
struct gpio_rcar_data {
struct gpio_driver_data common;
DEVICE_MMIO_NAMED_RAM(reg_base);
sys_slist_t cb;
};
#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04 /* General Input/Output Switching Register */
#define OUTDT 0x08 /* General Output Register */
#define INDT 0x0c /* General Input Register */
#define INTDT 0x10 /* Interrupt Display Register */
#define INTCLR 0x14 /* Interrupt Clear Register */
#define INTMSK 0x18 /* Interrupt Mask Register */
#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24 /* Edge/level Select Register */
#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
#define OUTDTSEL 0x40 /* Output Data Select Register */
#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
#define INEN 0x50 /* General Input Enable Register */
static inline uint32_t gpio_rcar_read(const struct device *dev, uint32_t offs)
{
return sys_read32(DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs);
}
static inline void gpio_rcar_write(const struct device *dev, uint32_t offs, uint32_t value)
{
sys_write32(value, DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs);
}
static void gpio_rcar_modify_bit(const struct device *dev,
uint32_t offs, int bit, bool value)
{
uint32_t tmp = gpio_rcar_read(dev, offs);
if (value) {
tmp |= BIT(bit);
} else {
tmp &= ~BIT(bit);
}
gpio_rcar_write(dev, offs, tmp);
}
static void gpio_rcar_port_isr(const struct device *dev)
{
struct gpio_rcar_data *data = dev->data;
uint32_t pending, fsb, mask;
pending = gpio_rcar_read(dev, INTDT);
mask = gpio_rcar_read(dev, INTMSK);
while ((pending = gpio_rcar_read(dev, INTDT) &
gpio_rcar_read(dev, INTMSK))) {
fsb = find_lsb_set(pending) - 1;
gpio_fire_callbacks(&data->cb, dev, BIT(fsb));
gpio_rcar_write(dev, INTCLR, BIT(fsb));
}
}
static void gpio_rcar_config_general_input_output_mode(
const struct device *dev,
uint32_t gpio,
bool output)
{
/* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
* "Setting General Input Mode"
*/
/* Configure positive logic in POSNEG */
gpio_rcar_modify_bit(dev, POSNEG, gpio, false);
/* Select "Input Enable/Disable" in INEN for Gen4 SoCs */
#ifdef CONFIG_SOC_SERIES_RCAR_GEN4
gpio_rcar_modify_bit(dev, INEN, gpio, !output);
#endif
/* Select "General Input/Output Mode" in IOINTSEL */
gpio_rcar_modify_bit(dev, IOINTSEL, gpio, false);
/* Select Input Mode or Output Mode in INOUTSEL */
gpio_rcar_modify_bit(dev, INOUTSEL, gpio, output);
/* Select General Output Register to output data in OUTDTSEL */
if (output) {
gpio_rcar_modify_bit(dev, OUTDTSEL, gpio, false);
}
}
static int gpio_rcar_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
/* Pin cannot be configured as input and output */
return -ENOTSUP;
} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
/* Pin has to be configured as input or output */
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_rcar_modify_bit(dev, OUTDT, pin, true);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_rcar_modify_bit(dev, OUTDT, pin, false);
}
gpio_rcar_config_general_input_output_mode(dev, pin, true);
} else {
gpio_rcar_config_general_input_output_mode(dev, pin, false);
}
return 0;
}
static int gpio_rcar_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
*value = gpio_rcar_read(dev, INDT);
return 0;
}
static int gpio_rcar_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
uint32_t port_val;
port_val = gpio_rcar_read(dev, OUTDT);
port_val = (port_val & ~mask) | (value & mask);
gpio_rcar_write(dev, OUTDT, port_val);
return 0;
}
static int gpio_rcar_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
uint32_t port_val;
port_val = gpio_rcar_read(dev, OUTDT);
port_val |= pins;
gpio_rcar_write(dev, OUTDT, port_val);
return 0;
}
static int gpio_rcar_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
uint32_t port_val;
port_val = gpio_rcar_read(dev, OUTDT);
port_val &= ~pins;
gpio_rcar_write(dev, OUTDT, port_val);
return 0;
}
static int gpio_rcar_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
uint32_t port_val;
port_val = gpio_rcar_read(dev, OUTDT);
port_val ^= pins;
gpio_rcar_write(dev, OUTDT, port_val);
return 0;
}
static int gpio_rcar_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
if (mode == GPIO_INT_MODE_DISABLED) {
return -ENOTSUP;
}
/* Configure positive or negative logic in POSNEG */
gpio_rcar_modify_bit(dev, POSNEG, pin,
(trig == GPIO_INT_TRIG_LOW));
/* Configure edge or level trigger in EDGLEVEL */
if (mode == GPIO_INT_MODE_EDGE) {
gpio_rcar_modify_bit(dev, EDGLEVEL, pin, true);
} else {
gpio_rcar_modify_bit(dev, EDGLEVEL, pin, false);
}
if (trig == GPIO_INT_TRIG_BOTH) {
gpio_rcar_modify_bit(dev, BOTHEDGE, pin, true);
}
/* Select "Input Enable" in INEN for Gen4 SoCs */
#ifdef CONFIG_SOC_SERIES_RCAR_GEN4
gpio_rcar_modify_bit(dev, INEN, pin, true);
#endif
gpio_rcar_modify_bit(dev, IOINTSEL, pin, true);
if (mode == GPIO_INT_MODE_EDGE) {
/* Write INTCLR in case of edge trigger */
gpio_rcar_write(dev, INTCLR, BIT(pin));
}
gpio_rcar_write(dev, MSKCLR, BIT(pin));
return 0;
}
static int gpio_rcar_init(const struct device *dev)
{
const struct gpio_rcar_cfg *config = dev->config;
int ret;
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t) &config->mod_clk);
if (ret < 0) {
return ret;
}
DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
config->init_func(dev);
return 0;
}
static int gpio_rcar_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_rcar_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static const struct gpio_driver_api gpio_rcar_driver_api = {
.pin_configure = gpio_rcar_configure,
.port_get_raw = gpio_rcar_port_get_raw,
.port_set_masked_raw = gpio_rcar_port_set_masked_raw,
.port_set_bits_raw = gpio_rcar_port_set_bits_raw,
.port_clear_bits_raw = gpio_rcar_port_clear_bits_raw,
.port_toggle_bits = gpio_rcar_port_toggle_bits,
.pin_interrupt_configure = gpio_rcar_pin_interrupt_configure,
.manage_callback = gpio_rcar_manage_callback,
};
/* Device Instantiation */
#define GPIO_RCAR_INIT(n) \
static void gpio_rcar_##n##_init(const struct device *dev); \
static const struct gpio_rcar_cfg gpio_rcar_cfg_##n = { \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.init_func = gpio_rcar_##n##_init, \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.mod_clk.module = \
DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
.mod_clk.domain = \
DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
}; \
static struct gpio_rcar_data gpio_rcar_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_rcar_init, \
NULL, \
&gpio_rcar_data_##n, \
&gpio_rcar_cfg_##n, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_rcar_driver_api \
); \
static void gpio_rcar_##n##_init(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
0, \
gpio_rcar_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_RCAR_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_rcar.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,431 |
```unknown
# Stellaris
config GPIO_STELLARIS
bool "TI Stellaris GPIO Driver"
default y
depends on DT_HAS_TI_STELLARIS_GPIO_ENABLED
help
Enable support for the Stellaris GPIO controllers.
``` | /content/code_sandbox/drivers/gpio/Kconfig.stellaris | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/sys/util.h>
#include <gpio_imx.h>
#include <string.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct imx_gpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
GPIO_Type *base;
const struct pinctrl_soc_pinmux *pin_muxes;
uint8_t mux_count;
};
struct imx_gpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static int imx_gpio_configure(const struct device *port, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
return -ENOTSUP;
}
__ASSERT_NO_MSG(pin < config->mux_count);
struct pinctrl_soc_pin pin_cfg;
/* Set appropriate bits in pin configuration register */
volatile uint32_t *gpio_cfg_reg =
(volatile uint32_t *)config->pin_muxes[pin].config_register;
uint32_t reg = *gpio_cfg_reg;
#ifdef MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= BIT(MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
} else {
reg &= ~BIT(MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
}
#else
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
#endif
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
reg |= BIT(MCUX_IMX_PULL_ENABLE_SHIFT);
#ifdef CONFIG_SOC_MCIMX6X_M4
reg |= BIT(MCUX_IMX_BIAS_BUS_HOLD_SHIFT);
#endif
if (((flags & GPIO_PULL_UP) != 0)) {
reg |= BIT(MCUX_IMX_BIAS_PULL_UP_SHIFT);
} else {
reg &= ~BIT(MCUX_IMX_BIAS_PULL_UP_SHIFT);
}
} else {
/* Set pin to highz */
reg &= ~BIT(MCUX_IMX_PULL_ENABLE_SHIFT);
#ifdef CONFIG_SOC_MCIMX6X_M4
reg &= ~BIT(MCUX_IMX_BIAS_BUS_HOLD_SHIFT);
#endif
}
/* Init pin configuration struct, and use pinctrl api to apply settings */
__ASSERT_NO_MSG(pin < config->mux_count);
memcpy(&pin_cfg.pinmux, &config->pin_muxes[pin], sizeof(pin_cfg.pinmux));
unsigned int key = irq_lock();
/* cfg register will be set by pinctrl_configure_pins */
pin_cfg.pin_ctrl_flags = reg;
pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
/* Disable interrupts for pin */
GPIO_SetPinIntMode(base, pin, false);
GPIO_SetIntEdgeSelect(base, pin, false);
if ((flags & GPIO_OUTPUT) != 0U) {
/* Set output pin initial value */
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
GPIO_WritePinOutput(base, pin, gpioPinClear);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
GPIO_WritePinOutput(base, pin, gpioPinSet);
}
/* Set pin as output */
WRITE_BIT(base->GDIR, pin, 1U);
} else {
/* Set pin as input */
WRITE_BIT(base->GDIR, pin, 0U);
}
irq_unlock(key);
return 0;
}
static int imx_gpio_port_get_raw(const struct device *port, uint32_t *value)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
*value = GPIO_ReadPortInput(base);
return 0;
}
static int imx_gpio_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
unsigned int key = irq_lock();
GPIO_WritePortOutput(base,
(GPIO_ReadPortInput(base) & ~mask) | (value & mask));
irq_unlock(key);
return 0;
}
static int imx_gpio_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
unsigned int key = irq_lock();
GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) | pins);
irq_unlock(key);
return 0;
}
static int imx_gpio_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
unsigned int key = irq_lock();
GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) & ~pins);
irq_unlock(key);
return 0;
}
static int imx_gpio_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
unsigned int key = irq_lock();
GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) ^ pins);
irq_unlock(key);
return 0;
}
static int imx_gpio_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct imx_gpio_config *config = port->config;
GPIO_Type *base = config->base;
volatile uint32_t *icr_reg;
unsigned int key;
uint32_t icr_val;
uint8_t shift;
if (((base->GDIR & BIT(pin)) != 0U)
&& (mode != GPIO_INT_MODE_DISABLED)) {
/* Interrupt on output pin not supported */
return -ENOTSUP;
}
if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
icr_val = 3U;
} else if ((mode == GPIO_INT_MODE_EDGE) &&
(trig == GPIO_INT_TRIG_HIGH)) {
icr_val = 2U;
} else if ((mode == GPIO_INT_MODE_LEVEL) &&
(trig == GPIO_INT_TRIG_HIGH)) {
icr_val = 1U;
} else {
icr_val = 0U;
}
if (pin < 16U) {
shift = 2U * pin;
icr_reg = &(base->ICR1);
} else if (pin < 32U) {
shift = 2U * (pin - 16U);
icr_reg = &(base->ICR2);
} else {
return -EINVAL;
}
key = irq_lock();
*icr_reg = (*icr_reg & ~(3U << shift)) | (icr_val << shift);
WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
WRITE_BIT(base->ISR, pin, mode != GPIO_INT_MODE_DISABLED);
WRITE_BIT(base->IMR, pin, mode != GPIO_INT_MODE_DISABLED);
irq_unlock(key);
return 0;
}
static int imx_gpio_manage_callback(const struct device *port,
struct gpio_callback *cb, bool set)
{
struct imx_gpio_data *data = port->data;
return gpio_manage_callback(&data->callbacks, cb, set);
}
static void imx_gpio_port_isr(const struct device *port)
{
const struct imx_gpio_config *config = port->config;
struct imx_gpio_data *data = port->data;
uint32_t int_status;
int_status = config->base->ISR & config->base->IMR;
config->base->ISR = int_status;
gpio_fire_callbacks(&data->callbacks, port, int_status);
}
static const struct gpio_driver_api imx_gpio_driver_api = {
.pin_configure = imx_gpio_configure,
.port_get_raw = imx_gpio_port_get_raw,
.port_set_masked_raw = imx_gpio_port_set_masked_raw,
.port_set_bits_raw = imx_gpio_port_set_bits_raw,
.port_clear_bits_raw = imx_gpio_port_clear_bits_raw,
.port_toggle_bits = imx_gpio_port_toggle_bits,
.pin_interrupt_configure = imx_gpio_pin_interrupt_configure,
.manage_callback = imx_gpio_manage_callback,
};
/* These macros will declare an array of pinctrl_soc_pinmux types */
#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
#define IMX_IGPIO_PIN_DECLARE(n) \
const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
DT_INST_FOREACH_PROP_ELEM(n, pinmux, PINMUX_INIT) \
};
#define IMX_IGPIO_PIN_INIT(n) \
.pin_muxes = mcux_igpio_pinmux_##n, \
.mux_count = DT_INST_PROP_LEN(n, pinmux),
#define GPIO_IMX_INIT(n) \
IMX_IGPIO_PIN_DECLARE(n) \
static int imx_gpio_##n##_init(const struct device *port); \
\
static const struct imx_gpio_config imx_gpio_##n##_config = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = (GPIO_Type *)DT_INST_REG_ADDR(n), \
IMX_IGPIO_PIN_INIT(n) \
}; \
\
static struct imx_gpio_data imx_gpio_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
imx_gpio_##n##_init, \
NULL, \
&imx_gpio_##n##_data, \
&imx_gpio_##n##_config, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&imx_gpio_driver_api); \
\
static int imx_gpio_##n##_init(const struct device *port) \
{ \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
DT_INST_IRQ_BY_IDX(n, 0, priority), \
imx_gpio_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \
DT_INST_IRQ_BY_IDX(n, 1, priority), \
imx_gpio_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
\
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_IMX_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_imx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,522 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pca953x, CONFIG_GPIO_LOG_LEVEL);
#include <zephyr/drivers/gpio/gpio_utils.h>
/* PCA953X Register addresses */
#define PCA953X_INPUT_PORT 0x00
#define PCA953X_OUTPUT_PORT 0x01
#define PCA953X_CONFIGURATION 0x03
#define REG_INPUT_LATCH_PORT0 0x42
#define REG_INT_MASK_PORT0 0x45
/* Number of pins supported by the device */
#define NUM_PINS 8
/* Max to select all pins supported on the device. */
#define ALL_PINS ((uint8_t)BIT_MASK(NUM_PINS))
/** Cache of the output configuration and data of the pins. */
struct pca953x_pin_state {
uint8_t dir;
uint8_t input;
uint8_t output;
};
struct pca953x_irq_state {
uint8_t rising;
uint8_t falling;
};
/** Runtime driver data */
struct pca953x_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct pca953x_pin_state pin_state;
struct k_sem lock;
struct gpio_callback gpio_cb;
struct k_work work;
struct pca953x_irq_state irq_state;
const struct device *dev;
/* user ISR cb */
sys_slist_t cb;
};
/** Configuration data */
struct pca953x_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec i2c;
const struct gpio_dt_spec gpio_int;
bool interrupt_enabled;
int interrupt_mask;
int input_latch;
};
/**
* @brief Gets the state of input pins of the PCA953X I/O Port and
* stores in driver data struct.
*
* @param dev Pointer to the device structure for the driver instance.
*
* @retval 0 If successful.
* @retval Negative value for error code.
*/
static int update_input(const struct device *dev)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
uint8_t input_states;
int rc = 0;
rc = i2c_reg_read_byte_dt(&cfg->i2c, PCA953X_INPUT_PORT, &input_states);
if (rc == 0) {
drv_data->pin_state.input = input_states;
}
return rc;
}
/**
* @brief Handles interrupt triggered by the interrupt pin of PCA953X I/O Port.
*
* If nint_gpios is configured in device tree then this will be triggered each
* time a gpio configured as an input changes state. The gpio input states are
* read in this function which clears the interrupt.
*
* @param dev Pointer to the device structure for the driver instance.
*/
static void gpio_pca953x_handle_interrupt(const struct device *dev)
{
struct pca953x_drv_data *drv_data = dev->data;
struct pca953x_irq_state *irq_state = &drv_data->irq_state;
int rc;
uint8_t previous_state;
uint8_t current_state;
uint8_t transitioned_pins;
uint8_t interrupt_status = 0;
k_sem_take(&drv_data->lock, K_FOREVER);
/* Any interrupts enabled? */
if (!irq_state->rising && !irq_state->falling) {
rc = -EINVAL;
goto out;
}
/* Store previous input state then read new value */
previous_state = drv_data->pin_state.input;
rc = update_input(dev);
if (rc != 0) {
goto out;
}
/* Find out which input pins have changed state */
current_state = drv_data->pin_state.input;
transitioned_pins = previous_state ^ current_state;
/* Mask gpio transactions with rising/falling edge interrupt config */
interrupt_status = (irq_state->rising & transitioned_pins &
current_state);
interrupt_status |= (irq_state->falling & transitioned_pins &
previous_state);
out:
k_sem_give(&drv_data->lock);
if ((rc == 0) && (interrupt_status)) {
gpio_fire_callbacks(&drv_data->cb, dev, interrupt_status);
}
}
/**
* @brief Work handler for PCA953X interrupt
*
* @param work Work struct that contains pointer to interrupt handler function
*/
static void gpio_pca953x_work_handler(struct k_work *work)
{
struct pca953x_drv_data *drv_data =
CONTAINER_OF(work, struct pca953x_drv_data, work);
gpio_pca953x_handle_interrupt(drv_data->dev);
}
/**
* @brief ISR for interrupt pin of PCA953X
*
* @param dev Pointer to the device structure for the driver instance.
* @param gpio_cb Pointer to callback function struct
* @param pins Bitmask of pins that triggered interrupt
*/
static void gpio_pca953x_init_cb(const struct device *dev,
struct gpio_callback *gpio_cb, uint32_t pins)
{
struct pca953x_drv_data *drv_data =
CONTAINER_OF(gpio_cb, struct pca953x_drv_data, gpio_cb);
ARG_UNUSED(pins);
k_work_submit(&drv_data->work);
}
static int gpio_pca953x_config(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
struct pca953x_pin_state *pins = &drv_data->pin_state;
int rc = 0;
bool data_first = false;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
/* Single Ended lines (Open drain and open source) not supported */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* The PCA953X has no internal pull up support */
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
return -ENOTSUP;
}
/* Simultaneous input & output mode not supported */
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
/* Ensure either Output or Input is specified */
if ((flags & GPIO_OUTPUT) != 0) {
pins->dir &= ~BIT(pin);
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
pins->output &= ~BIT(pin);
data_first = true;
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
pins->output |= BIT(pin);
data_first = true;
}
} else if ((flags & GPIO_INPUT) != 0) {
pins->dir |= BIT(pin);
} else {
rc = -ENOTSUP;
goto out;
}
/* Set output values */
if (data_first) {
rc = i2c_reg_write_byte_dt(&cfg->i2c, PCA953X_OUTPUT_PORT, pins->output);
}
if (rc == 0) {
/* Set pin directions */
rc = i2c_reg_write_byte_dt(&cfg->i2c, PCA953X_CONFIGURATION, pins->dir);
}
if (rc == 0) {
/* Refresh input status */
rc = update_input(dev);
}
out:
k_sem_give(&drv_data->lock);
return rc;
}
static int gpio_pca953x_port_read(const struct device *dev,
gpio_port_value_t *value)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
uint8_t input_pin_data;
int rc = 0;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
/* Read Input Register */
rc = i2c_reg_read_byte_dt(&cfg->i2c, PCA953X_INPUT_PORT, &input_pin_data);
LOG_DBG("read %x got %d", input_pin_data, rc);
if (rc == 0) {
drv_data->pin_state.input = input_pin_data;
*value = (gpio_port_value_t)(drv_data->pin_state.input);
}
k_sem_give(&drv_data->lock);
return rc;
}
static int gpio_pca953x_port_write(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value,
gpio_port_value_t toggle)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
uint8_t *outp = &drv_data->pin_state.output;
int rc;
uint8_t orig_out;
uint8_t out;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
orig_out = *outp;
out = ((orig_out & ~mask) | (value & mask)) ^ toggle;
rc = i2c_reg_write_byte_dt(&cfg->i2c, PCA953X_OUTPUT_PORT, out);
if (rc == 0) {
*outp = out;
}
k_sem_give(&drv_data->lock);
LOG_DBG("write %x msk %08x val %08x => %x: %d", orig_out, mask,
value, out, rc);
return rc;
}
static int gpio_pca953x_port_set_masked(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return gpio_pca953x_port_write(dev, mask, value, 0);
}
static int gpio_pca953x_port_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return gpio_pca953x_port_write(dev, pins, pins, 0);
}
static int gpio_pca953x_port_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return gpio_pca953x_port_write(dev, pins, 0, 0);
}
static int gpio_pca953x_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return gpio_pca953x_port_write(dev, 0, 0, pins);
}
static int gpio_pca953x_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
struct pca953x_irq_state *irq = &drv_data->irq_state;
if (!cfg->interrupt_enabled) {
return -ENOTSUP;
}
/* Device does not support level-triggered interrupts. */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
if (mode == GPIO_INT_MODE_DISABLED) {
irq->falling &= ~BIT(pin);
irq->rising &= ~BIT(pin);
} else { /* GPIO_INT_MODE_EDGE */
if (trig == GPIO_INT_TRIG_BOTH) {
irq->falling |= BIT(pin);
irq->rising |= BIT(pin);
} else if (trig == GPIO_INT_TRIG_LOW) {
irq->falling |= BIT(pin);
irq->rising &= ~BIT(pin);
} else if (trig == GPIO_INT_TRIG_HIGH) {
irq->falling &= ~BIT(pin);
irq->rising |= BIT(pin);
}
}
k_sem_give(&drv_data->lock);
return 0;
}
static int gpio_pca953x_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct pca953x_drv_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
/**
* @brief Initialization function of PCA953X
*
* This sets initial input/ output configuration and output states.
* The interrupt is configured if this is enabled.
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_pca953x_init(const struct device *dev)
{
const struct pca953x_config *cfg = dev->config;
struct pca953x_drv_data *drv_data = dev->data;
int rc = 0;
if (!device_is_ready(cfg->i2c.bus)) {
LOG_ERR("I2C bus device not found");
goto out;
}
/* Do an initial read, this clears the interrupt pin and sets
* up the initial value of the pin state input data.
*/
rc = update_input(dev);
if (rc) {
goto out;
}
if (cfg->interrupt_enabled) {
if (!gpio_is_ready_dt(&cfg->gpio_int)) {
LOG_ERR("Cannot get pointer to gpio interrupt device");
rc = -EINVAL;
goto out;
}
drv_data->dev = dev;
k_work_init(&drv_data->work, gpio_pca953x_work_handler);
rc = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
if (rc) {
goto out;
}
rc = gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
GPIO_INT_EDGE_TO_ACTIVE);
if (rc) {
goto out;
}
gpio_init_callback(&drv_data->gpio_cb,
gpio_pca953x_init_cb,
BIT(cfg->gpio_int.pin));
rc = gpio_add_callback(cfg->gpio_int.port,
&drv_data->gpio_cb);
if (rc) {
goto out;
}
/* This may not present on all variants of device */
if (cfg->input_latch > -1) {
rc = i2c_reg_write_byte_dt(&cfg->i2c, REG_INPUT_LATCH_PORT0,
cfg->input_latch);
}
if (cfg->interrupt_mask > -1) {
rc = i2c_reg_write_byte_dt(&cfg->i2c, REG_INT_MASK_PORT0,
cfg->interrupt_mask);
}
}
out:
if (rc) {
LOG_ERR("%s init failed: %d", dev->name, rc);
} else {
LOG_INF("%s init ok", dev->name);
}
return rc;
}
static const struct gpio_driver_api api_table = {
.pin_configure = gpio_pca953x_config,
.port_get_raw = gpio_pca953x_port_read,
.port_set_masked_raw = gpio_pca953x_port_set_masked,
.port_set_bits_raw = gpio_pca953x_port_set_bits,
.port_clear_bits_raw = gpio_pca953x_port_clear_bits,
.port_toggle_bits = gpio_pca953x_port_toggle_bits,
.pin_interrupt_configure = gpio_pca953x_pin_interrupt_configure,
.manage_callback = gpio_pca953x_manage_callback,
};
#define GPIO_PCA953X_INIT(n) \
static const struct pca953x_config pca953x_cfg_##n = { \
.i2c = I2C_DT_SPEC_INST_GET(n), \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.interrupt_enabled = DT_INST_NODE_HAS_PROP(n, nint_gpios), \
.gpio_int = GPIO_DT_SPEC_INST_GET_OR(n, nint_gpios, {0}), \
.interrupt_mask = DT_INST_PROP_OR(n, interrupt_mask, -1), \
.input_latch = DT_INST_PROP_OR(n, input_latch, -1), \
}; \
\
static struct pca953x_drv_data pca953x_drvdata_##n = { \
.lock = Z_SEM_INITIALIZER(pca953x_drvdata_##n.lock, 1, 1), \
.pin_state.dir = ALL_PINS, \
.pin_state.output = ALL_PINS, \
}; \
DEVICE_DT_INST_DEFINE(n, \
gpio_pca953x_init, \
NULL, \
&pca953x_drvdata_##n, \
&pca953x_cfg_##n, \
POST_KERNEL, \
CONFIG_GPIO_PCA953X_INIT_PRIORITY, \
&api_table);
#define DT_DRV_COMPAT ti_tca9538
DT_INST_FOREACH_STATUS_OKAY(GPIO_PCA953X_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_pca953x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,687 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm1300_gpio
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/mfd/npm1300.h>
#include <zephyr/dt-bindings/gpio/nordic-npm1300-gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util_macro.h>
/* nPM1300 GPIO base address */
#define NPM_GPIO_BASE 0x06U
/* nPM1300 GPIO registers offsets */
#define NPM_GPIO_OFFSET_MODE 0x00U
#define NPM_GPIO_OFFSET_DRIVE 0x05U
#define NPM_GPIO_OFFSET_PULLUP 0x0AU
#define NPM_GPIO_OFFSET_PULLDOWN 0x0FU
#define NPM_GPIO_OFFSET_OPENDRAIN 0x14U
#define NPM_GPIO_OFFSET_DEBOUNCE 0x19U
#define NPM_GPIO_OFFSET_STATUS 0x1EU
/* nPM1300 Channel counts */
#define NPM1300_GPIO_PINS 5U
#define NPM1300_GPIO_GPIINPUT 0
#define NPM1300_GPIO_GPILOGIC1 1
#define NPM1300_GPIO_GPILOGIC0 2
#define NPM1300_GPIO_GPIEVENTRISE 3
#define NPM1300_GPIO_GPIEVENTFALL 4
#define NPM1300_GPIO_GPOIRQ 5
#define NPM1300_GPIO_GPORESET 6
#define NPM1300_GPIO_GPOPWRLOSSWARN 7
#define NPM1300_GPIO_GPOLOGIC1 8
#define NPM1300_GPIO_GPOLOGIC0 9
struct gpio_npm1300_config {
struct gpio_driver_config common;
const struct device *mfd;
};
struct gpio_npm1300_data {
struct gpio_driver_data common;
};
static int gpio_npm1300_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_npm1300_config *config = dev->config;
int ret;
uint8_t data;
ret = mfd_npm1300_reg_read(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_STATUS, &data);
if (ret < 0) {
return ret;
}
*value = data;
return 0;
}
static int gpio_npm1300_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_npm1300_config *config = dev->config;
int ret = 0;
for (size_t idx = 0; idx < NPM1300_GPIO_PINS; idx++) {
if ((mask & BIT(idx)) != 0U) {
if ((value & BIT(idx)) != 0U) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
NPM_GPIO_OFFSET_MODE + idx,
NPM1300_GPIO_GPOLOGIC1);
} else {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
NPM_GPIO_OFFSET_MODE + idx,
NPM1300_GPIO_GPOLOGIC0);
}
if (ret != 0U) {
return ret;
}
}
}
return ret;
}
static int gpio_npm1300_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return gpio_npm1300_port_set_masked_raw(dev, pins, pins);
}
static int gpio_npm1300_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return gpio_npm1300_port_set_masked_raw(dev, pins, 0U);
}
static inline int gpio_npm1300_configure(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_npm1300_config *config = dev->config;
int ret = 0;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin >= NPM1300_GPIO_PINS) {
return -EINVAL;
}
/* Configure mode */
if ((flags & GPIO_INPUT) != 0U) {
if (flags & GPIO_ACTIVE_LOW) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPIEVENTFALL);
} else {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE,
NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPIEVENTRISE);
}
} else if ((flags & NPM1300_GPIO_WDT_RESET_ON) != 0U) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPORESET);
} else if ((flags & NPM1300_GPIO_PWRLOSSWARN_ON) != 0U) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPOPWRLOSSWARN);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPOLOGIC1);
} else if ((flags & GPIO_OUTPUT) != 0U) {
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_MODE + pin,
NPM1300_GPIO_GPOLOGIC0);
}
if (ret < 0) {
return ret;
}
/* Configure open drain */
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_OPENDRAIN + pin,
!!(flags & GPIO_SINGLE_ENDED));
if (ret < 0) {
return ret;
}
/* Configure pulls */
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_PULLUP + pin,
!!(flags & GPIO_PULL_UP));
if (ret < 0) {
return ret;
}
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_PULLDOWN + pin,
!!(flags & GPIO_PULL_DOWN));
if (ret < 0) {
return ret;
}
/* Configure drive strength and debounce */
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_DRIVE + pin,
!!(flags & NPM1300_GPIO_DRIVE_6MA));
if (ret < 0) {
return ret;
}
ret = mfd_npm1300_reg_write(config->mfd, NPM_GPIO_BASE, NPM_GPIO_OFFSET_DEBOUNCE + pin,
!!(flags & NPM1300_GPIO_DEBOUNCE_ON));
return ret;
}
static int gpio_npm1300_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
int ret;
uint32_t value;
ret = gpio_npm1300_port_get_raw(dev, &value);
if (ret < 0) {
return ret;
}
return gpio_npm1300_port_set_masked_raw(dev, pins, ~value);
}
static const struct gpio_driver_api gpio_npm1300_api = {
.pin_configure = gpio_npm1300_configure,
.port_get_raw = gpio_npm1300_port_get_raw,
.port_set_masked_raw = gpio_npm1300_port_set_masked_raw,
.port_set_bits_raw = gpio_npm1300_port_set_bits_raw,
.port_clear_bits_raw = gpio_npm1300_port_clear_bits_raw,
.port_toggle_bits = gpio_npm1300_port_toggle_bits,
};
static int gpio_npm1300_init(const struct device *dev)
{
const struct gpio_npm1300_config *config = dev->config;
if (!device_is_ready(config->mfd)) {
return -ENODEV;
}
return 0;
}
#define GPIO_NPM1300_DEFINE(n) \
static const struct gpio_npm1300_config gpio_npm1300_config##n = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.mfd = DEVICE_DT_GET(DT_INST_PARENT(n))}; \
\
static struct gpio_npm1300_data gpio_npm1300_data##n; \
\
DEVICE_DT_INST_DEFINE(n, gpio_npm1300_init, NULL, &gpio_npm1300_data##n, \
&gpio_npm1300_config##n, POST_KERNEL, \
CONFIG_GPIO_NPM1300_INIT_PRIORITY, &gpio_npm1300_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_NPM1300_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_npm1300.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,995 |
```c
/*
*
*
*/
/**
* @file Driver for MPC23Sxx SPI-based GPIO driver.
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_mcp23xxx.h"
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_mcp23sxx);
static int mcp23sxx_read_port_regs(const struct device *dev, uint8_t reg, uint16_t *buf)
{
const struct mcp23xxx_config *config = dev->config;
uint16_t port_data = 0;
int ret;
uint8_t nread = (config->ngpios == 8) ? 1 : 2;
uint8_t addr = MCP23SXX_ADDR | MCP23SXX_READBIT;
uint8_t buffer_tx[4] = { addr, reg, 0, 0 };
uint8_t buffer_rx[4] = { 0 };
const struct spi_buf tx_buf = {
.buf = buffer_tx,
.len = 4,
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
const struct spi_buf rx_buf = {
.buf = buffer_rx,
.len = 2 + nread,
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1,
};
ret = spi_transceive_dt(&config->bus.spi, &tx, &rx);
if (ret < 0) {
LOG_ERR("spi_transceive FAIL %d\n", ret);
return ret;
}
port_data = ((uint16_t)buffer_rx[3] << 8 | buffer_rx[2]);
*buf = sys_le16_to_cpu(port_data);
return 0;
}
static int mcp23sxx_write_port_regs(const struct device *dev, uint8_t reg, uint16_t value)
{
const struct mcp23xxx_config *config = dev->config;
int ret;
uint8_t nwrite = (config->ngpios == 8) ? 1 : 2;
uint16_t port_data = sys_cpu_to_le16(value);
uint8_t port_a_data = port_data & 0xFF;
uint8_t port_b_data = (port_data >> 8) & 0xFF;
port_data = sys_cpu_to_le16(value);
uint8_t addr = MCP23SXX_ADDR;
uint8_t buffer_tx[4] = { addr, reg, port_a_data, port_b_data };
const struct spi_buf tx_buf[1] = {
{
.buf = buffer_tx,
.len = nwrite + 2,
}
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
ret = spi_write_dt(&config->bus.spi, &tx);
if (ret < 0) {
LOG_ERR("spi_write FAIL %d\n", ret);
return ret;
}
return 0;
}
static int mcp23sxx_bus_is_ready(const struct device *dev)
{
const struct mcp23xxx_config *config = dev->config;
if (!spi_is_ready_dt(&config->bus.spi)) {
LOG_ERR("SPI bus %s not ready", config->bus.spi.bus->name);
return -ENODEV;
}
return 0;
}
#define GPIO_MCP23SXX_DEVICE(inst, num_gpios, open_drain) \
static struct mcp23xxx_drv_data mcp23sxx_##inst##_drvdata = { \
/* Default for registers according to datasheet */ \
.reg_cache.iodir = 0xFFFF, .reg_cache.ipol = 0x0, .reg_cache.gpinten = 0x0, \
.reg_cache.defval = 0x0, .reg_cache.intcon = 0x0, .reg_cache.iocon = 0x0, \
.reg_cache.gppu = 0x0, .reg_cache.intf = 0x0, .reg_cache.intcap = 0x0, \
.reg_cache.gpio = 0x0, .reg_cache.olat = 0x0, \
}; \
static struct mcp23xxx_config mcp23sxx_##inst##_config = { \
.config = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
}, \
.bus = { \
.spi = SPI_DT_SPEC_INST_GET(inst, \
SPI_OP_MODE_MASTER | SPI_MODE_CPOL | \
SPI_MODE_CPHA | SPI_WORD_SET(8), 0) \
}, \
.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}), \
.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \
.ngpios = num_gpios, \
.is_open_drain = open_drain, \
.read_fn = mcp23sxx_read_port_regs, \
.write_fn = mcp23sxx_write_port_regs, \
.bus_fn = mcp23sxx_bus_is_ready \
}; \
DEVICE_DT_INST_DEFINE(inst, gpio_mcp23xxx_init, NULL, &mcp23sxx_##inst##_drvdata, \
&mcp23sxx_##inst##_config, POST_KERNEL, \
CONFIG_GPIO_MCP23SXX_INIT_PRIORITY, &gpio_mcp23xxx_api_table);
#define DT_DRV_COMPAT microchip_mcp23s08
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP23SXX_DEVICE, 8, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23s09
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP23SXX_DEVICE, 8, true)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23s17
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP23SXX_DEVICE, 16, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT microchip_mcp23s18
DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MCP23SXX_DEVICE, 16, true)
#undef DT_DRV_COMPAT
``` | /content/code_sandbox/drivers/gpio/gpio_mcp23sxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,424 |
```unknown
# PCAL6408a GPIO configuration options
menuconfig GPIO_PCAL64XXA
bool "PCAL64XXA I2C GPIO chip"
default y
depends on DT_HAS_NXP_PCAL6408A_ENABLED || DT_HAS_NXP_PCAL6416A_ENABLED
select I2C
help
Enable driver for PCAL64XXA I2C GPIO chip.
config GPIO_PCAL64XXA_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_PCAL64XXA
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.pcal64xxa | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```c
/*
*
*/
/**
* @file GPIO driver for the AndesTech ATCGPIO100 controller
*/
#include <errno.h>
#include <stdbool.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define DT_DRV_COMPAT andestech_atcgpio100
/* Andes ATCGPIO100 register definition */
#define REG_IDR 0x00 /* ID and Revision reg. */
#define REG_CFG 0x10 /* Hardware configure reg. */
#define REG_DIN 0x20 /* Data In reg. */
#define REG_DOUT 0x24 /* Data Out reg. */
#define REG_DIR 0x28 /* Channel direction reg. */
#define REG_DCLR 0x2C /* Data out clear reg. */
#define REG_DSET 0x30 /* Data out set reg. */
#define REG_PUEN 0x40 /* Pull enable reg. */
#define REG_PTYP 0x44 /* Pull type reg. */
#define REG_INTE 0x50 /* Interrupt enable reg. */
#define REG_IMD0 0x54 /* Interrupt mode 0 ~ 7 reg. */
#define REG_IMD1 0x58 /* Interrupt mode 8 ~ 15 reg. */
#define REG_IMD2 0x5C /* Interrupt mode 16 ~ 23 reg. */
#define REG_IMD3 0x60 /* Interrupt mode 24 ~ 31 reg. */
#define REG_ISTA 0x64 /* Interrupt status reg. */
#define REG_DEBE 0x70 /* De-bounce enable reg. */
#define REG_DEBC 0x74 /* De-Bounce control reg. */
#define INT_NO_OPERATION 0x0
#define INT_HIGH_LEVEL 0x2
#define INT_LOW_LEVEL 0x3
#define INT_NEGATIVE_EDGE 0x5
#define INT_POSITIVE_EDGE 0x6
#define INT_DUAL_EDGE 0x7
#define PULL_CONFIGURED BIT(31)
#define DEBOUNCE_CONFIGURED BIT(29)
#define DF_DEBOUNCED_SETTING (0x80000003)
#define GPIO_BASE(dev) \
((const struct gpio_atcgpio100_config * const)(dev)->config)->base
#define GPIO_CFG(dev) (GPIO_BASE(dev) + REG_CFG)
#define GPIO_DIR(dev) (GPIO_BASE(dev) + REG_DIR)
#define GPIO_DIN(dev) (GPIO_BASE(dev) + REG_DIN)
#define GPIO_DOUT(dev) (GPIO_BASE(dev) + REG_DOUT)
#define GPIO_DCLR(dev) (GPIO_BASE(dev) + REG_DCLR)
#define GPIO_DSET(dev) (GPIO_BASE(dev) + REG_DSET)
#define GPIO_PUEN(dev) (GPIO_BASE(dev) + REG_PUEN)
#define GPIO_PTYP(dev) (GPIO_BASE(dev) + REG_PTYP)
#define GPIO_INTE(dev) (GPIO_BASE(dev) + REG_INTE)
#define GPIO_IMD(dev, idx) (GPIO_BASE(dev) + REG_IMD0 + (idx * 4))
#define GPIO_ISTA(dev) (GPIO_BASE(dev) + REG_ISTA)
#define GPIO_DEBE(dev) (GPIO_BASE(dev) + REG_DEBE)
#define GPIO_DEBC(dev) (GPIO_BASE(dev) + REG_DEBC)
#define SET_GPIO_INT_MODE(cur_val, mode, ch_idx) \
do { \
cur_val &= ~(BIT_MASK(3) << (ch_idx * 4)); \
cur_val |= (mode << (ch_idx * 4)); \
} while (false)
typedef void (*atcgpio100_cfg_func_t)(void);
struct gpio_atcgpio100_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uint32_t base;
uint32_t irq_num;
atcgpio100_cfg_func_t cfg_func;
};
struct gpio_atcgpio100_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* list of callbacks */
sys_slist_t cb;
struct k_spinlock lock;
};
static int gpio_atcgpio100_config(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
struct gpio_atcgpio100_data * const data = port->data;
uint32_t port_value, pin_mask, io_flags;
k_spinlock_key_t key;
/* Does not support disconnected pin, and
* not supporting both input/output at same time.
*/
io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
if ((io_flags == GPIO_DISCONNECTED)
|| (io_flags == (GPIO_INPUT | GPIO_OUTPUT))) {
return -ENOTSUP;
}
pin_mask = BIT(pin);
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
sys_write32(pin_mask, GPIO_DSET(port));
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
sys_write32(pin_mask, GPIO_DCLR(port));
}
key = k_spin_lock(&data->lock);
/* Set channel output */
port_value = sys_read32(GPIO_DIR(port));
sys_write32((port_value | pin_mask), GPIO_DIR(port));
k_spin_unlock(&data->lock, key);
} else if (flags & GPIO_INPUT) {
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
return -ENOTSUP;
}
key = k_spin_lock(&data->lock);
/* Set de-bounce */
if (flags & ATCGPIO100_GPIO_DEBOUNCE) {
/* Default settings: Filter out pulses which are
* less than 4 de-bounce clock period
*/
sys_write32(DF_DEBOUNCED_SETTING, GPIO_DEBC(port));
port_value = sys_read32(GPIO_DEBE(port));
sys_write32((port_value | pin_mask), GPIO_DEBE(port));
}
/* Set channel input */
port_value = sys_read32(GPIO_DIR(port));
sys_write32((port_value & ~pin_mask), GPIO_DIR(port));
k_spin_unlock(&data->lock, key);
} else {
return -ENOTSUP;
}
return 0;
}
static int gpio_atcgpio100_port_get_raw(const struct device *port,
gpio_port_value_t *value)
{
*value = sys_read32(GPIO_DIN(port));
return 0;
}
static int gpio_atcgpio100_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
struct gpio_atcgpio100_data * const data = port->data;
uint32_t port_value;
k_spinlock_key_t key = k_spin_lock(&data->lock);
port_value = sys_read32(GPIO_DOUT(port));
sys_write32((port_value & ~mask) | (value & mask), GPIO_DOUT(port));
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_atcgpio100_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
sys_write32(pins, GPIO_DSET(port));
return 0;
}
static int gpio_atcgpio100_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
sys_write32(pins, GPIO_DCLR(port));
return 0;
}
static int gpio_atcgpio100_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
struct gpio_atcgpio100_data * const data = port->data;
uint32_t port_value;
k_spinlock_key_t key = k_spin_lock(&data->lock);
port_value = sys_read32(GPIO_DOUT(port));
sys_write32((port_value ^ pins), GPIO_DOUT(port));
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_atcgpio100_pin_interrupt_configure(
const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
struct gpio_atcgpio100_data * const data = port->data;
uint32_t port_value, int_mode, imr_idx, ch_idx;
k_spinlock_key_t key;
switch (mode | trig) {
case GPIO_INT_EDGE_BOTH:
int_mode = INT_DUAL_EDGE;
break;
case GPIO_INT_EDGE_RISING:
int_mode = INT_POSITIVE_EDGE;
break;
case GPIO_INT_EDGE_FALLING:
int_mode = INT_NEGATIVE_EDGE;
break;
case GPIO_INT_LEVEL_LOW:
int_mode = INT_LOW_LEVEL;
break;
case GPIO_INT_LEVEL_HIGH:
int_mode = INT_HIGH_LEVEL;
break;
default:
int_mode = INT_NO_OPERATION;
break;
}
imr_idx = (pin / 8);
ch_idx = (pin % 8);
key = k_spin_lock(&data->lock);
if (int_mode == INT_NO_OPERATION) {
/* Disable interrupt of pin */
port_value = sys_read32(GPIO_INTE(port));
sys_write32((port_value & ~BIT(pin)), GPIO_INTE(port));
/* Clear the remain pending interrupt */
port_value = sys_read32(GPIO_ISTA(port));
sys_write32(port_value, GPIO_ISTA(port));
} else {
/* Set interrupt mode of pin */
port_value = sys_read32(GPIO_IMD(port, imr_idx));
SET_GPIO_INT_MODE(port_value, int_mode, ch_idx);
sys_write32(port_value, GPIO_IMD(port, imr_idx));
/* Enable interrupt of pin */
port_value = sys_read32(GPIO_INTE(port));
sys_write32((port_value | BIT(pin)), GPIO_INTE(port));
}
k_spin_unlock(&data->lock, key);
return 0;
}
static int gpio_atcgpio100_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
struct gpio_atcgpio100_data * const data = port->data;
return gpio_manage_callback(&data->cb, callback, set);
}
#ifdef CONFIG_GPIO_GET_DIRECTION
static int gpio_atcgpio100_port_get_dir(const struct device *port,
gpio_port_pins_t map,
gpio_port_pins_t *inputs,
gpio_port_pins_t *outputs)
{
const struct gpio_atcgpio100_config * const dev_cfg = port->config;
uint32_t direction = sys_read32(GPIO_DIR(port));
map &= dev_cfg->common.port_pin_mask;
if (inputs != NULL) {
*inputs = map & ~direction;
}
if (outputs != NULL) {
*outputs = map & direction;
}
return 0;
}
#endif /* CONFIG_GPIO_GET_DIRECTION */
static void gpio_atcgpio100_irq_handler(const struct device *port)
{
struct gpio_atcgpio100_data * const data = port->data;
uint32_t port_value;
port_value = sys_read32(GPIO_ISTA(port));
sys_write32(port_value, GPIO_ISTA(port));
gpio_fire_callbacks(&data->cb, port, port_value);
}
static const struct gpio_driver_api gpio_atcgpio100_api = {
.pin_configure = gpio_atcgpio100_config,
.port_get_raw = gpio_atcgpio100_port_get_raw,
.port_set_masked_raw = gpio_atcgpio100_set_masked_raw,
.port_set_bits_raw = gpio_atcgpio100_set_bits_raw,
.port_clear_bits_raw = gpio_atcgpio100_clear_bits_raw,
.port_toggle_bits = gpio_atcgpio100_toggle_bits,
.pin_interrupt_configure = gpio_atcgpio100_pin_interrupt_configure,
.manage_callback = gpio_atcgpio100_manage_callback,
#ifdef CONFIG_GPIO_GET_DIRECTION
.port_get_direction = gpio_atcgpio100_port_get_dir,
#endif /* CONFIG_GPIO_GET_DIRECTION */
};
static int gpio_atcgpio100_init(const struct device *port)
{
const struct gpio_atcgpio100_config * const dev_cfg = port->config;
/* Disable all interrupts */
sys_write32(BIT_MASK(0), GPIO_INTE(port));
/* Write 1 to clear interrupt status */
sys_write32((uint32_t) BIT64_MASK(32), GPIO_ISTA(port));
/* Configure GPIO device */
dev_cfg->cfg_func();
/* Enable PLIC interrupt GPIO source */
irq_enable(dev_cfg->irq_num);
return 0;
}
#define GPIO_ATCGPIO100_INIT(n) \
static void gpio_atcgpio100_cfg_func_##n(void); \
static struct gpio_atcgpio100_data gpio_atcgpio100_data_##n; \
\
static const struct gpio_atcgpio100_config \
gpio_atcgpio100_config_##n = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = DT_INST_REG_ADDR(n), \
.irq_num = DT_INST_IRQN(n), \
.cfg_func = gpio_atcgpio100_cfg_func_##n \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_atcgpio100_init, \
NULL, \
&gpio_atcgpio100_data_##n, \
&gpio_atcgpio100_config_##n, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_atcgpio100_api); \
\
static void gpio_atcgpio100_cfg_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_atcgpio100_irq_handler, \
DEVICE_DT_INST_GET(n), \
0); \
return; \
} \
DT_INST_FOREACH_STATUS_OKAY(GPIO_ATCGPIO100_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_andes_atcgpio100.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,044 |
```unknown
#
config GPIO_DAVINCI
bool "Davinci GPIO Driver"
default y
depends on DT_HAS_TI_DAVINCI_GPIO_ENABLED
help
Enable the Davinci GPIO controller support.
``` | /content/code_sandbox/drivers/gpio/Kconfig.davinci | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pcal64xxa, CONFIG_GPIO_LOG_LEVEL);
enum pcal6408a_register {
PCAL6408A_REG_INPUT_PORT = 0x00,
PCAL6408A_REG_OUTPUT_PORT = 0x01,
PCAL6408A_REG_POLARITY_INVERSION = 0x02,
PCAL6408A_REG_CONFIGURATION = 0x03,
PCAL6408A_REG_OUTPUT_DRIVE_STRENGTH_0 = 0x40,
PCAL6408A_REG_OUTPUT_DRIVE_STRENGTH_1 = 0x41,
PCAL6408A_REG_INPUT_LATCH = 0x42,
PCAL6408A_REG_PULL_UP_DOWN_ENABLE = 0x43,
PCAL6408A_REG_PULL_UP_DOWN_SELECT = 0x44,
PCAL6408A_REG_INTERRUPT_MASK = 0x45,
PCAL6408A_REG_INTERRUPT_STATUS = 0x46,
PCAL6408A_REG_OUTPUT_PORT_CONFIGURATION = 0x4f,
};
enum pcal6416a_register {
PCAL6416A_REG_INPUT_PORT_0 = 0x00,
PCAL6416A_REG_INPUT_PORT_1 = 0x01,
PCAL6416A_REG_OUTPUT_PORT_0 = 0x02,
PCAL6416A_REG_OUTPUT_PORT_1 = 0x03,
PCAL6416A_REG_POLARITY_INVERSION_0 = 0x04,
PCAL6416A_REG_POLARITY_INVERSION_1 = 0x05,
PCAL6416A_REG_CONFIGURATION_0 = 0x06,
PCAL6416A_REG_CONFIGURATION_1 = 0x07,
PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_0_0 = 0x40,
PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_0_1 = 0x41,
PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_1_0 = 0x42,
PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_1_1 = 0x43,
PCAL6416A_REG_INPUT_LATCH_0 = 0x44,
PCAL6416A_REG_INPUT_LATCH_1 = 0x45,
PCAL6416A_REG_PULL_UP_DOWN_ENABLE_0 = 0x46,
PCAL6416A_REG_PULL_UP_DOWN_ENABLE_1 = 0x47,
PCAL6416A_REG_PULL_UP_DOWN_SELECT_0 = 0x48,
PCAL6416A_REG_PULL_UP_DOWN_SELECT_1 = 0x49,
PCAL6416A_REG_INTERRUPT_MASK_0 = 0x4A,
PCAL6416A_REG_INTERRUPT_MASK_1 = 0x4B,
PCAL6416A_REG_INTERRUPT_STATUS_0 = 0x4C,
PCAL6416A_REG_INTERRUPT_STATUS_1 = 0x4D,
PCAL6416A_REG_OUTPUT_PORT_CONFIGURATION = 0x4F,
};
#if DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6416a)
typedef uint16_t pcal64xxa_data_t;
#define PCAL64XXA_INIT_HIGH UINT16_MAX
#define PRIpcal_data "04" PRIx16
#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6408a)
typedef uint8_t pcal64xxa_data_t;
#define PCAL64XXA_INIT_HIGH UINT8_MAX
#define PRIpcal_data "02" PRIx8
#else
#error "Cannot determine the internal data type size"
#endif
struct pcal64xxa_pins_cfg {
pcal64xxa_data_t configured_as_inputs;
pcal64xxa_data_t outputs_high;
pcal64xxa_data_t pull_ups_selected;
pcal64xxa_data_t pulls_enabled;
};
struct pcal64xxa_triggers {
pcal64xxa_data_t masked;
pcal64xxa_data_t dual_edge;
pcal64xxa_data_t on_low;
};
struct pcal64xxa_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t callbacks;
struct k_sem lock;
struct k_work work;
const struct device *dev;
struct gpio_callback int_gpio_cb;
struct pcal64xxa_pins_cfg pins_cfg;
struct pcal64xxa_triggers triggers;
pcal64xxa_data_t input_port_last;
};
typedef int (*pcal64xxa_pins_cfg_apply)(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_pins_cfg *pins_cfg);
typedef int (*pcal64xxa_triggers_apply)(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_triggers *triggers);
typedef int (*pcal64xxa_reset_state_apply)(const struct i2c_dt_spec *i2c);
typedef int (*pcal64xxa_inputs_read)(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources,
pcal64xxa_data_t *input_port);
typedef int (*pcal64xxa_outputs_write)(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs);
struct pcal64xxa_chip_api {
pcal64xxa_pins_cfg_apply pins_cfg_apply;
pcal64xxa_triggers_apply triggers_apply;
pcal64xxa_inputs_read inputs_read;
pcal64xxa_outputs_write outputs_write;
pcal64xxa_reset_state_apply reset_state_apply;
};
struct pcal64xxa_drv_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec i2c;
uint8_t ngpios;
const struct gpio_dt_spec gpio_reset;
const struct gpio_dt_spec gpio_interrupt;
const struct pcal64xxa_chip_api *chip_api;
};
static int pcal64xxa_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
struct pcal64xxa_drv_data *drv_data = dev->data;
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_pins_cfg pins_cfg;
gpio_flags_t flags_io;
int rc;
LOG_DBG("%s: configure pin %i with flags 0x%08X", dev->name, pin, flags);
/* This device does not support open-source outputs, and open-drain
* outputs can be only configured port-wise.
*/
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* Pins in this device can be either inputs or outputs and cannot be
* completely disconnected.
*/
flags_io = (flags & (GPIO_INPUT | GPIO_OUTPUT));
if (flags_io == (GPIO_INPUT | GPIO_OUTPUT) || flags_io == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
pins_cfg = drv_data->pins_cfg;
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
if ((flags & GPIO_PULL_UP) != 0) {
pins_cfg.pull_ups_selected |= BIT(pin);
} else {
pins_cfg.pull_ups_selected &= ~BIT(pin);
}
pins_cfg.pulls_enabled |= BIT(pin);
} else {
pins_cfg.pulls_enabled &= ~BIT(pin);
}
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
pins_cfg.outputs_high &= ~BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
pins_cfg.outputs_high |= BIT(pin);
}
pins_cfg.configured_as_inputs &= ~BIT(pin);
} else {
pins_cfg.configured_as_inputs |= BIT(pin);
}
rc = drv_cfg->chip_api->pins_cfg_apply(&drv_cfg->i2c, &pins_cfg);
if (rc == 0) {
drv_data->pins_cfg = pins_cfg;
} else {
LOG_ERR("%s: failed to apply pin config", dev->name);
}
k_sem_give(&drv_data->lock);
return rc;
}
static int pcal64xxa_process_input(const struct device *dev, gpio_port_value_t *value)
{
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_drv_data *drv_data = dev->data;
int rc;
pcal64xxa_data_t int_sources;
pcal64xxa_data_t input_port;
k_sem_take(&drv_data->lock, K_FOREVER);
rc = drv_cfg->chip_api->inputs_read(&drv_cfg->i2c, &int_sources, &input_port);
if (rc != 0) {
LOG_ERR("%s: failed to read inputs", dev->name);
k_sem_give(&drv_data->lock);
return rc;
}
if (value) {
*value = input_port;
}
/* It may happen that some inputs change their states between above
* reads of the interrupt status and input port registers. Such changes
* will not be noted in `int_sources`, thus to correctly detect them,
* the current state of inputs needs to be additionally compared with
* the one read last time, and any differences need to be added to
* `int_sources`.
*/
int_sources |= ((input_port ^ drv_data->input_port_last) & ~drv_data->triggers.masked);
drv_data->input_port_last = input_port;
if (int_sources) {
pcal64xxa_data_t dual_edge_triggers = drv_data->triggers.dual_edge;
pcal64xxa_data_t falling_edge_triggers =
~dual_edge_triggers & drv_data->triggers.on_low;
pcal64xxa_data_t fired_triggers = 0;
/* For dual edge triggers, react to all state changes. */
fired_triggers |= (int_sources & dual_edge_triggers);
/* For single edge triggers, fire callbacks only for the pins
* that transitioned to their configured target state (0 for
* falling edges, 1 otherwise, hence the XOR operation below).
*/
fired_triggers |= ((input_port & int_sources) ^ falling_edge_triggers);
/* Give back semaphore before the callback to make the same
* driver available again for the callback.
*/
k_sem_give(&drv_data->lock);
gpio_fire_callbacks(&drv_data->callbacks, dev, fired_triggers);
} else {
k_sem_give(&drv_data->lock);
}
return 0;
}
static void pcal64xxa_work_handler(struct k_work *work)
{
struct pcal64xxa_drv_data *drv_data = CONTAINER_OF(work, struct pcal64xxa_drv_data, work);
(void)pcal64xxa_process_input(drv_data->dev, NULL);
}
static void pcal64xxa_int_gpio_handler(const struct device *dev, struct gpio_callback *gpio_cb,
uint32_t pins)
{
ARG_UNUSED(dev);
ARG_UNUSED(pins);
struct pcal64xxa_drv_data *drv_data =
CONTAINER_OF(gpio_cb, struct pcal64xxa_drv_data, int_gpio_cb);
k_work_submit(&drv_data->work);
}
static int pcal64xxa_port_get_raw(const struct device *dev, gpio_port_value_t *value)
{
int rc;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
/* Reading of the input port also clears the generated interrupt,
* thus the configured callbacks must be fired also here if needed.
*/
rc = pcal64xxa_process_input(dev, value);
return rc;
}
static int pcal64xxa_port_set_raw(const struct device *dev, pcal64xxa_data_t mask,
pcal64xxa_data_t value, pcal64xxa_data_t toggle)
{
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_drv_data *drv_data = dev->data;
int rc;
pcal64xxa_data_t output;
LOG_DBG("%s: setting port with mask 0x%" PRIpcal_data " with value 0x%" PRIpcal_data
" and toggle 0x%" PRIpcal_data,
dev->name, mask, value, toggle);
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
output = (drv_data->pins_cfg.outputs_high & ~mask);
output |= (value & mask);
output ^= toggle;
/*
* No need to limit `out` to only pins configured as outputs,
* as the chip anyway ignores all other bits in the register.
*/
rc = drv_cfg->chip_api->outputs_write(&drv_cfg->i2c, output);
if (rc == 0) {
drv_data->pins_cfg.outputs_high = output;
}
k_sem_give(&drv_data->lock);
if (rc != 0) {
LOG_ERR("%s: failed to write output port: %d", dev->name, rc);
return -EIO;
}
return 0;
}
static int pcal64xxa_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)mask, (pcal64xxa_data_t)value, 0);
}
static int pcal64xxa_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)pins, (pcal64xxa_data_t)pins, 0);
}
static int pcal64xxa_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
return pcal64xxa_port_set_raw(dev, (pcal64xxa_data_t)pins, 0, 0);
}
static int pcal64xxa_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
return pcal64xxa_port_set_raw(dev, 0, 0, (pcal64xxa_data_t)pins);
}
static int pcal64xxa_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_drv_data *drv_data = dev->data;
struct pcal64xxa_triggers triggers;
int rc;
LOG_DBG("%s: configure interrupt for pin %i", dev->name, pin);
if (drv_cfg->gpio_interrupt.port == NULL) {
return -ENOTSUP;
}
/* This device supports only edge-triggered interrupts. */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
triggers = drv_data->triggers;
if (mode == GPIO_INT_MODE_DISABLED) {
triggers.masked |= BIT(pin);
} else {
triggers.masked &= ~BIT(pin);
}
if (trig == GPIO_INT_TRIG_BOTH) {
triggers.dual_edge |= BIT(pin);
} else {
triggers.dual_edge &= ~BIT(pin);
if (trig == GPIO_INT_TRIG_LOW) {
triggers.on_low |= BIT(pin);
} else {
triggers.on_low &= ~BIT(pin);
}
}
rc = drv_cfg->chip_api->triggers_apply(&drv_cfg->i2c, &triggers);
if (rc == 0) {
drv_data->triggers = triggers;
} else {
LOG_ERR("%s: failed to apply triggers", dev->name);
}
k_sem_give(&drv_data->lock);
return rc;
}
static int pcal64xxa_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct pcal64xxa_drv_data *drv_data = dev->data;
return gpio_manage_callback(&drv_data->callbacks, callback, set);
}
static int pcal64xxa_i2c_write(const struct i2c_dt_spec *i2c, uint8_t register_address,
uint8_t value)
{
int rc;
LOG_DBG("writing to register 0x%02X value 0x%02X", register_address, value);
rc = i2c_reg_write_byte_dt(i2c, register_address, value);
if (rc != 0) {
LOG_ERR("unable to write to register 0x%02X, error %i", register_address, rc);
}
return rc;
}
static int pcal64xxa_i2c_read(const struct i2c_dt_spec *i2c, uint8_t register_address,
uint8_t *value)
{
int rc;
rc = i2c_reg_read_byte_dt(i2c, register_address, value);
LOG_DBG("reading from register 0x%02X value 0x%02X", register_address, *value);
if (rc != 0) {
LOG_ERR("unable to read from register 0x%02X, error %i", register_address, rc);
}
return rc;
}
#if DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6408a)
static int pcal6408a_pins_cfg_apply(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_pins_cfg *pins_cfg)
{
int rc;
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_PULL_UP_DOWN_SELECT,
(uint8_t)pins_cfg->pull_ups_selected);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_PULL_UP_DOWN_ENABLE,
(uint8_t)pins_cfg->pulls_enabled);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_OUTPUT_PORT, (uint8_t)pins_cfg->outputs_high);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_CONFIGURATION,
(uint8_t)pins_cfg->configured_as_inputs);
if (rc != 0) {
return -EIO;
}
return 0;
}
static int pcal6408a_inputs_read(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources,
pcal64xxa_data_t *input_port)
{
int rc;
uint8_t value;
rc = pcal64xxa_i2c_read(i2c, PCAL6408A_REG_INTERRUPT_STATUS, &value);
if (rc != 0) {
return -EIO;
}
*int_sources = value;
/* This read also clears the generated interrupt if any. */
rc = pcal64xxa_i2c_read(i2c, PCAL6408A_REG_INPUT_PORT, &value);
if (rc != 0) {
return -EIO;
}
*input_port = value;
return 0;
}
static int pcal6408a_outputs_write(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs)
{
int rc;
/*
* No need to limit `out` to only pins configured as outputs,
* as the chip anyway ignores all other bits in the register.
*/
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_OUTPUT_PORT, (uint8_t)outputs);
if (rc != 0) {
LOG_ERR("failed to write output port: %d", rc);
return -EIO;
}
return 0;
}
static int pcal6408a_triggers_apply(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_triggers *triggers)
{
int rc;
uint8_t input_latch = ~triggers->masked;
uint8_t interrupt_mask = triggers->masked;
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_INPUT_LATCH, (uint8_t)input_latch);
if (rc != 0) {
LOG_ERR("failed to configure input latch: %d", rc);
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6408A_REG_INTERRUPT_MASK, (uint8_t)interrupt_mask);
if (rc != 0) {
LOG_ERR("failed to configure interrupt mask: %d", rc);
return -EIO;
}
return 0;
}
static int pcal6408a_reset_state_apply(const struct i2c_dt_spec *i2c)
{
int rc;
static const uint8_t reset_state[][2] = {
{PCAL6408A_REG_POLARITY_INVERSION, 0},
{PCAL6408A_REG_OUTPUT_DRIVE_STRENGTH_0, 0xff},
{PCAL6408A_REG_OUTPUT_DRIVE_STRENGTH_1, 0xff},
{PCAL6408A_REG_OUTPUT_PORT_CONFIGURATION, 0},
};
for (int i = 0; i < ARRAY_SIZE(reset_state); ++i) {
rc = pcal64xxa_i2c_write(i2c, reset_state[i][0], reset_state[i][1]);
if (rc != 0) {
LOG_ERR("failed to reset register %02x: %d", reset_state[i][0], rc);
return -EIO;
}
}
return 0;
}
static const struct pcal64xxa_chip_api pcal6408a_chip_api = {
.pins_cfg_apply = pcal6408a_pins_cfg_apply,
.triggers_apply = pcal6408a_triggers_apply,
.inputs_read = pcal6408a_inputs_read,
.outputs_write = pcal6408a_outputs_write,
.reset_state_apply = pcal6408a_reset_state_apply,
};
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6408a) */
#if DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6416a)
static int pcal6416a_pins_cfg_apply(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_pins_cfg *pins_cfg)
{
int rc;
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_PULL_UP_DOWN_SELECT_0,
(uint8_t)pins_cfg->pull_ups_selected);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_PULL_UP_DOWN_SELECT_1,
(uint8_t)(pins_cfg->pull_ups_selected >> 8));
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_PULL_UP_DOWN_ENABLE_0,
(uint8_t)pins_cfg->pulls_enabled);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_PULL_UP_DOWN_ENABLE_1,
(uint8_t)(pins_cfg->pulls_enabled >> 8));
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_OUTPUT_PORT_0, (uint8_t)pins_cfg->outputs_high);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_OUTPUT_PORT_1,
(uint8_t)(pins_cfg->outputs_high >> 8));
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_CONFIGURATION_0,
(uint8_t)pins_cfg->configured_as_inputs);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_CONFIGURATION_1,
(uint8_t)(pins_cfg->configured_as_inputs >> 8));
if (rc != 0) {
return -EIO;
}
return 0;
}
static int pcal6416a_inputs_read(const struct i2c_dt_spec *i2c, pcal64xxa_data_t *int_sources,
pcal64xxa_data_t *input_port)
{
int rc;
uint8_t value_low;
uint8_t value_high;
rc = pcal64xxa_i2c_read(i2c, PCAL6416A_REG_INTERRUPT_STATUS_0, &value_low);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_read(i2c, PCAL6416A_REG_INTERRUPT_STATUS_1, &value_high);
if (rc != 0) {
return -EIO;
}
*int_sources = value_low | (value_high << 8);
/* This read also clears the generated interrupt if any. */
rc = pcal64xxa_i2c_read(i2c, PCAL6416A_REG_INPUT_PORT_0, &value_low);
if (rc != 0) {
return -EIO;
}
rc = pcal64xxa_i2c_read(i2c, PCAL6416A_REG_INPUT_PORT_1, &value_high);
if (rc != 0) {
LOG_ERR("failed to read input port: %d", rc);
return -EIO;
}
*input_port = value_low | (value_high << 8);
return 0;
}
static int pcal6416a_outputs_write(const struct i2c_dt_spec *i2c, pcal64xxa_data_t outputs)
{
int rc;
/*
* No need to limit `out` to only pins configured as outputs,
* as the chip anyway ignores all other bits in the register.
*/
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_OUTPUT_PORT_0, (uint8_t)outputs);
if (rc != 0) {
LOG_ERR("failed to write output port: %d", rc);
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_OUTPUT_PORT_1, (uint8_t)(outputs >> 8));
if (rc != 0) {
LOG_ERR("failed to write output port: %d", rc);
return -EIO;
}
return 0;
}
static int pcal6416a_triggers_apply(const struct i2c_dt_spec *i2c,
const struct pcal64xxa_triggers *triggers)
{
int rc;
pcal64xxa_data_t input_latch = ~triggers->masked;
pcal64xxa_data_t interrupt_mask = triggers->masked;
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_INPUT_LATCH_0, (uint8_t)input_latch);
if (rc != 0) {
LOG_ERR("failed to configure input latch: %d", rc);
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_INPUT_LATCH_1, (uint8_t)(input_latch >> 8));
if (rc != 0) {
LOG_ERR("failed to configure input latch: %d", rc);
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_INTERRUPT_MASK_0, (uint8_t)interrupt_mask);
if (rc != 0) {
LOG_ERR("failed to configure interrupt mask: %d", rc);
return -EIO;
}
rc = pcal64xxa_i2c_write(i2c, PCAL6416A_REG_INTERRUPT_MASK_1,
(uint8_t)(interrupt_mask >> 8));
if (rc != 0) {
LOG_ERR("failed to configure interrupt mask: %d", rc);
return -EIO;
}
return 0;
}
static int pcal6416a_reset_state_apply(const struct i2c_dt_spec *i2c)
{
int rc;
static const uint8_t reset_state[][2] = {
{PCAL6416A_REG_POLARITY_INVERSION_0, 0},
{PCAL6416A_REG_POLARITY_INVERSION_1, 0},
{PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_0_0, 0xff},
{PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_0_1, 0xff},
{PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_1_0, 0xff},
{PCAL6416A_REG_OUTPUT_DRIVE_STRENGTH_1_1, 0xff},
{PCAL6416A_REG_OUTPUT_PORT_CONFIGURATION, 0},
};
for (int i = 0; i < ARRAY_SIZE(reset_state); ++i) {
rc = pcal64xxa_i2c_write(i2c, reset_state[i][0], reset_state[i][1]);
if (rc != 0) {
LOG_ERR("failed to reset register %02x: %d", reset_state[i][0], rc);
return -EIO;
}
}
return 0;
}
static const struct pcal64xxa_chip_api pcal6416a_chip_api = {
.pins_cfg_apply = pcal6416a_pins_cfg_apply,
.triggers_apply = pcal6416a_triggers_apply,
.inputs_read = pcal6416a_inputs_read,
.outputs_write = pcal6416a_outputs_write,
.reset_state_apply = pcal6416a_reset_state_apply,
};
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nxp_pcal6416a) */
int pcal64xxa_init(const struct device *dev)
{
const struct pcal64xxa_drv_cfg *drv_cfg = dev->config;
struct pcal64xxa_drv_data *drv_data = dev->data;
const struct pcal64xxa_pins_cfg initial_pins_cfg = {
.configured_as_inputs = PCAL64XXA_INIT_HIGH,
.outputs_high = 0,
.pull_ups_selected = 0,
.pulls_enabled = 0,
};
const struct pcal64xxa_triggers initial_triggers = {
.masked = PCAL64XXA_INIT_HIGH,
};
int rc;
pcal64xxa_data_t int_sources;
LOG_DBG("initializing PCAL64XXA");
if (drv_cfg->ngpios != 8U && drv_cfg->ngpios != 16U) {
LOG_ERR("Invalid value ngpios=%u. Expected 8 or 16!", drv_cfg->ngpios);
return -EINVAL;
}
/*
* executing the is ready check on i2c_bus_dev instead of on i2c.bus
* to avoid a const warning
*/
if (!i2c_is_ready_dt(&drv_cfg->i2c)) {
LOG_ERR("%s is not ready", drv_cfg->i2c.bus->name);
return -ENODEV;
}
/* If the RESET line is available, use it to reset the expander.
* Otherwise, write reset values to registers that are not used by
* this driver.
*/
if (drv_cfg->gpio_reset.port != NULL) {
if (!gpio_is_ready_dt(&drv_cfg->gpio_reset)) {
LOG_ERR("%s: reset gpio device is not ready", dev->name);
return -ENODEV;
}
LOG_DBG("%s: trigger reset", dev->name);
rc = gpio_pin_configure_dt(&drv_cfg->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (rc != 0) {
LOG_ERR("%s: failed to configure RESET line: %d", dev->name, rc);
return -EIO;
}
/* RESET signal needs to be active for a minimum of 30 ns. */
k_busy_wait(1);
rc = gpio_pin_set_dt(&drv_cfg->gpio_reset, 0);
if (rc != 0) {
LOG_ERR("%s: failed to deactivate RESET line: %d", dev->name, rc);
return -EIO;
}
/* Give the expander at least 200 ns to recover after reset. */
k_busy_wait(1);
} else {
rc = drv_cfg->chip_api->reset_state_apply(&drv_cfg->i2c);
if (rc != 0) {
LOG_ERR("%s: failed to apply reset state", dev->name);
return rc;
}
}
/* Set initial configuration of the pins. */
rc = drv_cfg->chip_api->pins_cfg_apply(&drv_cfg->i2c, &initial_pins_cfg);
if (rc != 0) {
LOG_ERR("%s: failed to apply pin config", dev->name);
return rc;
}
drv_data->pins_cfg = initial_pins_cfg;
/* Read initial state of the input port register. */
rc = drv_cfg->chip_api->inputs_read(&drv_cfg->i2c, &int_sources,
&drv_data->input_port_last);
if (rc != 0) {
LOG_ERR("failed to read inputs for device %s", dev->name);
return rc;
}
/* Set initial state of the interrupt related registers. */
rc = drv_cfg->chip_api->triggers_apply(&drv_cfg->i2c, &initial_triggers);
if (rc != 0) {
LOG_ERR("%s: failed to apply triggers", dev->name);
return rc;
}
drv_data->triggers = initial_triggers;
/* If the INT line is available, configure the callback for it. */
if (drv_cfg->gpio_interrupt.port != NULL) {
if (!gpio_is_ready_dt(&drv_cfg->gpio_interrupt)) {
LOG_ERR("%s: interrupt gpio device is not ready", dev->name);
return -ENODEV;
}
rc = gpio_pin_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INPUT);
if (rc != 0) {
LOG_ERR("%s: failed to configure INT line: %d", dev->name, rc);
return -EIO;
}
rc = gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt,
GPIO_INT_EDGE_TO_ACTIVE);
if (rc != 0) {
LOG_ERR("%s: failed to configure INT interrupt: %d", dev->name, rc);
return -EIO;
}
gpio_init_callback(&drv_data->int_gpio_cb, pcal64xxa_int_gpio_handler,
BIT(drv_cfg->gpio_interrupt.pin));
rc = gpio_add_callback(drv_cfg->gpio_interrupt.port, &drv_data->int_gpio_cb);
if (rc != 0) {
LOG_ERR("%s: failed to add INT callback: %d", dev->name, rc);
return -EIO;
}
}
/* Device configured, unlock it so that it can be used. */
k_sem_give(&drv_data->lock);
return 0;
}
#define PCAL64XXA_INIT_INT_GPIO_FIELDS(idx) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, int_gpios), \
(GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), int_gpios, 0)), ({0}))
#define PCAL64XXA_INIT_RESET_GPIO_FIELDS(idx) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, reset_gpios), \
(GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(idx), reset_gpios, 0)), ({0}))
#define GPIO_PCAL6408A_INST(idx) \
static const struct gpio_driver_api pcal6408a_drv_api##idx = { \
.pin_configure = pcal64xxa_pin_configure, \
.port_get_raw = pcal64xxa_port_get_raw, \
.port_set_masked_raw = pcal64xxa_port_set_masked_raw, \
.port_set_bits_raw = pcal64xxa_port_set_bits_raw, \
.port_clear_bits_raw = pcal64xxa_port_clear_bits_raw, \
.port_toggle_bits = pcal64xxa_port_toggle_bits, \
.pin_interrupt_configure = pcal64xxa_pin_interrupt_configure, \
.manage_callback = pcal64xxa_manage_callback, \
}; \
static const struct pcal64xxa_drv_cfg pcal6408a_cfg##idx = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
}, \
.i2c = I2C_DT_SPEC_INST_GET(idx), \
.ngpios = DT_INST_PROP(idx, ngpios), \
.gpio_interrupt = PCAL64XXA_INIT_INT_GPIO_FIELDS(idx), \
.gpio_reset = PCAL64XXA_INIT_RESET_GPIO_FIELDS(idx), \
.chip_api = &pcal6408a_chip_api, \
}; \
static struct pcal64xxa_drv_data pcal6408a_data##idx = { \
.lock = Z_SEM_INITIALIZER(pcal6408a_data##idx.lock, 1, 1), \
.work = Z_WORK_INITIALIZER(pcal64xxa_work_handler), \
.dev = DEVICE_DT_INST_GET(idx), \
}; \
DEVICE_DT_INST_DEFINE(idx, pcal64xxa_init, NULL, &pcal6408a_data##idx, \
&pcal6408a_cfg##idx, POST_KERNEL, \
CONFIG_GPIO_PCAL64XXA_INIT_PRIORITY, &pcal6408a_drv_api##idx);
#define DT_DRV_COMPAT nxp_pcal6408a
DT_INST_FOREACH_STATUS_OKAY(GPIO_PCAL6408A_INST)
#define GPIO_PCAL6416A_INST(idx) \
static const struct gpio_driver_api pcal6416a_drv_api##idx = { \
.pin_configure = pcal64xxa_pin_configure, \
.port_get_raw = pcal64xxa_port_get_raw, \
.port_set_masked_raw = pcal64xxa_port_set_masked_raw, \
.port_set_bits_raw = pcal64xxa_port_set_bits_raw, \
.port_clear_bits_raw = pcal64xxa_port_clear_bits_raw, \
.port_toggle_bits = pcal64xxa_port_toggle_bits, \
.pin_interrupt_configure = pcal64xxa_pin_interrupt_configure, \
.manage_callback = pcal64xxa_manage_callback, \
}; \
static const struct pcal64xxa_drv_cfg pcal6416a_cfg##idx = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
}, \
.i2c = I2C_DT_SPEC_INST_GET(idx), \
.ngpios = DT_INST_PROP(idx, ngpios), \
.gpio_interrupt = PCAL64XXA_INIT_INT_GPIO_FIELDS(idx), \
.gpio_reset = PCAL64XXA_INIT_RESET_GPIO_FIELDS(idx), \
.chip_api = &pcal6416a_chip_api, \
}; \
static struct pcal64xxa_drv_data pcal6416a_data##idx = { \
.lock = Z_SEM_INITIALIZER(pcal6416a_data##idx.lock, 1, 1), \
.work = Z_WORK_INITIALIZER(pcal64xxa_work_handler), \
.dev = DEVICE_DT_INST_GET(idx), \
}; \
DEVICE_DT_INST_DEFINE(idx, pcal64xxa_init, NULL, &pcal6416a_data##idx, \
&pcal6416a_cfg##idx, POST_KERNEL, \
CONFIG_GPIO_PCAL64XXA_INIT_PRIORITY, &pcal6416a_drv_api##idx);
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT nxp_pcal6416a
DT_INST_FOREACH_STATUS_OKAY(GPIO_PCAL6416A_INST)
``` | /content/code_sandbox/drivers/gpio/gpio_pcal64xxa.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,995 |
```unknown
# STMPE1600 GPIO configuration options
menuconfig GPIO_STMPE1600
bool "STMPE1600 I2C-based GPIO chip"
default y
depends on DT_HAS_ST_STMPE1600_ENABLED
depends on I2C
help
Enable driver for STMPE1600 I2C-based GPIO chip.
config GPIO_STMPE1600_INIT_PRIORITY
int "Init priority"
default 70
depends on GPIO_STMPE1600
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.stmpe1600 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam4l_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
typedef void (*config_func_t)(const struct device *dev);
struct gpio_sam_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
Gpio *regs;
config_func_t config_func;
const struct atmel_sam_pmc_config clock_cfg;
};
struct gpio_sam_runtime {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
#define GPIO_SAM_ALL_PINS 0xFFFFFFFF
static int gpio_sam_port_configure(const struct device *dev,
uint32_t mask,
gpio_flags_t flags)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
/* No hardware support */
if (flags & GPIO_SINGLE_ENDED) {
return -ENOTSUP;
}
if (!(flags & (GPIO_OUTPUT | GPIO_INPUT))) {
gpio->IERC = mask;
gpio->PUERC = mask;
gpio->PDERC = mask;
gpio->GPERS = mask;
gpio->ODERC = mask;
gpio->STERC = mask;
return 0;
}
/*
* Always enable schmitt-trigger because SAM4L GPIO Ctrl
* is Input only or Input/Output.
*/
gpio->STERS = mask;
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio->OVRS = mask;
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio->OVRC = mask;
}
gpio->ODERS = mask;
} else {
gpio->ODERC = mask;
}
gpio->PUERC = mask;
gpio->PDERC = mask;
if (flags & GPIO_PULL_UP) {
gpio->PUERS = mask;
} else if (flags & GPIO_PULL_DOWN) {
gpio->PDERS = mask;
}
/* Enable the GPIO to control the pin (instead of a peripheral). */
gpio->GPERS = mask;
return 0;
}
static int gpio_sam_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
return gpio_sam_port_configure(dev, BIT(pin), flags);
}
static int gpio_sam_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
*value = gpio->PVR;
return 0;
}
static int gpio_sam_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
gpio->OVR = (gpio->PVR & ~mask) | (mask & value);
return 0;
}
static int gpio_sam_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
gpio->OVRS = mask;
return 0;
}
static int gpio_sam_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
gpio->OVRC = mask;
return 0;
}
static int gpio_sam_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
gpio->OVRT = mask;
return 0;
}
static int gpio_sam_port_interrupt_configure(const struct device *dev,
uint32_t mask,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
gpio->IERC = mask;
gpio->IMR0C = mask;
gpio->IMR1C = mask;
if (trig != GPIO_INT_TRIG_BOTH) {
if (trig == GPIO_INT_TRIG_HIGH) {
gpio->IMR0S = mask;
} else {
gpio->IMR1S = mask;
}
}
if (mode != GPIO_INT_MODE_DISABLED) {
gpio->IFRC = mask;
gpio->IERS = mask;
}
return 0;
}
static int gpio_sam_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
return gpio_sam_port_interrupt_configure(dev, BIT(pin), mode, trig);
}
static void gpio_sam_isr(const struct device *dev)
{
const struct gpio_sam_config * const cfg = dev->config;
Gpio * const gpio = cfg->regs;
struct gpio_sam_runtime *context = dev->data;
uint32_t int_stat;
int_stat = gpio->IFR;
gpio->IFRC = int_stat;
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_sam_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
struct gpio_sam_runtime *context = port->data;
return gpio_manage_callback(&context->cb, callback, set);
}
static const struct gpio_driver_api gpio_sam_api = {
.pin_configure = gpio_sam_config,
.port_get_raw = gpio_sam_port_get_raw,
.port_set_masked_raw = gpio_sam_port_set_masked_raw,
.port_set_bits_raw = gpio_sam_port_set_bits_raw,
.port_clear_bits_raw = gpio_sam_port_clear_bits_raw,
.port_toggle_bits = gpio_sam_port_toggle_bits,
.pin_interrupt_configure = gpio_sam_pin_interrupt_configure,
.manage_callback = gpio_sam_manage_callback,
};
int gpio_sam_init(const struct device *dev)
{
const struct gpio_sam_config * const cfg = dev->config;
/* Enable GPIO clock in PM */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&cfg->clock_cfg);
cfg->config_func(dev);
return 0;
}
#define GPIO_SAM_IRQ_CONNECT(n, m) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
DT_INST_IRQ_BY_IDX(n, m, priority), \
gpio_sam_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
} while (false)
#define GPIO_SAM_INIT(n) \
static void port_##n##_sam_config_func(const struct device *dev);\
\
static const struct gpio_sam_config port_##n##_sam_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.regs = (Gpio *)DT_INST_REG_ADDR(n), \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
.config_func = port_##n##_sam_config_func, \
}; \
\
static struct gpio_sam_runtime port_##n##_sam_runtime; \
\
DEVICE_DT_INST_DEFINE(n, gpio_sam_init, NULL, \
&port_##n##_sam_runtime, \
&port_##n##_sam_config, PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_sam_api); \
\
static void port_##n##_sam_config_func(const struct device *dev)\
{ \
GPIO_SAM_IRQ_CONNECT(n, 0); \
GPIO_SAM_IRQ_CONNECT(n, 1); \
GPIO_SAM_IRQ_CONNECT(n, 2); \
GPIO_SAM_IRQ_CONNECT(n, 3); \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_SAM_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_sam4l.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,852 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_gpio_pin_configure(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_configure));
return z_impl_gpio_pin_configure((const struct device *)port,
pin,
flags);
}
#include <zephyr/syscalls/gpio_pin_configure_mrsh.c>
#ifdef CONFIG_GPIO_GET_CONFIG
static inline int z_vrfy_gpio_pin_get_config(const struct device *port,
gpio_pin_t pin,
gpio_flags_t *flags)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_get_config));
K_OOPS(K_SYSCALL_MEMORY_WRITE(flags, sizeof(gpio_flags_t)));
return z_impl_gpio_pin_get_config(port, pin, flags);
}
#include <zephyr/syscalls/gpio_pin_get_config_mrsh.c>
#endif
static inline int z_vrfy_gpio_port_get_raw(const struct device *port,
gpio_port_value_t *value)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_get_raw));
K_OOPS(K_SYSCALL_MEMORY_WRITE(value, sizeof(gpio_port_value_t)));
return z_impl_gpio_port_get_raw((const struct device *)port,
(gpio_port_value_t *)value);
}
#include <zephyr/syscalls/gpio_port_get_raw_mrsh.c>
static inline int z_vrfy_gpio_port_set_masked_raw(const struct device *port,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_set_masked_raw));
return z_impl_gpio_port_set_masked_raw((const struct device *)port,
mask,
value);
}
#include <zephyr/syscalls/gpio_port_set_masked_raw_mrsh.c>
static inline int z_vrfy_gpio_port_set_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_set_bits_raw));
return z_impl_gpio_port_set_bits_raw((const struct device *)port,
pins);
}
#include <zephyr/syscalls/gpio_port_set_bits_raw_mrsh.c>
static inline int z_vrfy_gpio_port_clear_bits_raw(const struct device *port,
gpio_port_pins_t pins)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_clear_bits_raw));
return z_impl_gpio_port_clear_bits_raw((const struct device *)port,
pins);
}
#include <zephyr/syscalls/gpio_port_clear_bits_raw_mrsh.c>
static inline int z_vrfy_gpio_port_toggle_bits(const struct device *port,
gpio_port_pins_t pins)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_toggle_bits));
return z_impl_gpio_port_toggle_bits((const struct device *)port, pins);
}
#include <zephyr/syscalls/gpio_port_toggle_bits_mrsh.c>
static inline int z_vrfy_gpio_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
gpio_flags_t flags)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_interrupt_configure));
return z_impl_gpio_pin_interrupt_configure((const struct device *)port,
pin,
flags);
}
#include <zephyr/syscalls/gpio_pin_interrupt_configure_mrsh.c>
static inline int z_vrfy_gpio_get_pending_int(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(dev, get_pending_int));
return z_impl_gpio_get_pending_int((const struct device *)dev);
}
#include <zephyr/syscalls/gpio_get_pending_int_mrsh.c>
#ifdef CONFIG_GPIO_GET_DIRECTION
static inline int z_vrfy_gpio_port_get_direction(const struct device *dev, gpio_port_pins_t map,
gpio_port_pins_t *inputs,
gpio_port_pins_t *outputs)
{
K_OOPS(K_SYSCALL_DRIVER_GPIO(dev, port_get_direction));
if (inputs != NULL) {
K_OOPS(K_SYSCALL_MEMORY_WRITE(inputs, sizeof(gpio_port_pins_t)));
}
if (outputs != NULL) {
K_OOPS(K_SYSCALL_MEMORY_WRITE(outputs, sizeof(gpio_port_pins_t)));
}
return z_impl_gpio_port_get_direction(dev, map, inputs, outputs);
}
#include <zephyr/syscalls/gpio_port_get_direction_mrsh.c>
#endif /* CONFIG_GPIO_GET_DIRECTION */
``` | /content/code_sandbox/drivers/gpio/gpio_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 904 |
```unknown
config GPIO_BRCMSTB
bool "Broadcom Set-top box SoC GPIO Driver"
default y
depends on DT_HAS_BRCM_BRCMSTB_GPIO_ENABLED
help
Enable Driver for Broadcom Set-top box SoC GPIO Banks.
``` | /content/code_sandbox/drivers/gpio/Kconfig.brcmstb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/interrupt_controller/intc_xmc4xxx.h>
#include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
#include <xmc_gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define PORT_TO_PORT_ID(port) ((int)(port) >> 8 & 0xf)
struct gpio_xmc4xxx_config {
/* gpio_driver_config needs to be first, required by Zephyr */
struct gpio_driver_config common;
XMC_GPIO_PORT_t *port;
};
struct gpio_xmc4xxx_data {
/* gpio_driver_data needs to be first, required by Zephyr */
struct gpio_driver_data common;
#if defined(CONFIG_XMC4XXX_INTC)
sys_slist_t callbacks;
#endif
};
static int gpio_xmc4xxx_convert_flags(XMC_GPIO_CONFIG_t *pin_config, gpio_flags_t flags)
{
bool is_input = flags & GPIO_INPUT;
bool is_output = flags & GPIO_OUTPUT;
int ds;
/* GPIO_DISCONNECTED */
if (!is_input && !is_output) {
return -ENOTSUP;
}
if (flags & GPIO_OPEN_SOURCE) {
return -ENOTSUP;
}
if (is_input) {
pin_config->mode = XMC_GPIO_MODE_INPUT_TRISTATE;
if (flags & GPIO_PULL_DOWN) {
pin_config->mode = XMC_GPIO_MODE_INPUT_PULL_DOWN;
}
if (flags & GPIO_PULL_UP) {
pin_config->mode = XMC_GPIO_MODE_INPUT_PULL_UP;
}
}
ds = XMC4XXX_GPIO_GET_DS(flags);
if ((!is_output && ds) || ds > XMC4XXX_GPIO_DS_WEAK) {
return -EINVAL;
}
if (is_output) {
pin_config->mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
if (flags & GPIO_OPEN_DRAIN) {
pin_config->mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN;
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
pin_config->output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
pin_config->output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
}
/* Strong medium edge is default */
pin_config->output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE;
if (ds > 0) {
pin_config->output_strength = ds - 1;
}
}
return 0;
}
static int gpio_xmc4xxx_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
XMC_GPIO_CONFIG_t pin_config = {0};
gpio_port_pins_t pin_mask = config->common.port_pin_mask;
int ret;
if ((BIT(pin) & pin_mask) == 0) {
return -EINVAL;
}
if ((port == (XMC_GPIO_PORT_t *)PORT14_BASE || port == (XMC_GPIO_PORT_t *)PORT15_BASE) &&
(flags & GPIO_OUTPUT)) {
return -EINVAL;
}
ret = gpio_xmc4xxx_convert_flags(&pin_config, flags);
if (ret) {
return ret;
}
XMC_GPIO_Init(port, pin, &pin_config);
return 0;
}
#if defined(CONFIG_XMC4XXX_INTC)
static void gpio_xmc4xxx_isr(const struct device *dev, int pin)
{
struct gpio_xmc4xxx_data *data = dev->data;
gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
}
#endif
#ifdef CONFIG_XMC4XXX_INTC
static int gpio_xmc4xxx_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_xmc4xxx_config *config = dev->config;
int port_id = PORT_TO_PORT_ID(config->port);
if (mode & GPIO_INT_ENABLE) {
return intc_xmc4xxx_gpio_enable_interrupt(port_id, pin, mode, trig,
gpio_xmc4xxx_isr, (void *)dev);
} else if (mode & GPIO_INT_DISABLE) {
return intc_xmc4xxx_gpio_disable_interrupt(port_id, pin);
} else {
return -EINVAL;
}
}
#endif
static int gpio_xmc4xxx_get_raw(const struct device *dev, gpio_port_value_t *value)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
gpio_port_pins_t pin_mask = config->common.port_pin_mask;
*value = port->IN & pin_mask;
return 0;
}
#if defined(CONFIG_XMC4XXX_INTC)
static int gpio_xmc4xxx_manage_callback(const struct device *dev, struct gpio_callback *callback,
bool set)
{
struct gpio_xmc4xxx_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
#endif
static int gpio_xmc4xxx_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
gpio_port_pins_t pin_mask = config->common.port_pin_mask;
mask &= pin_mask;
/* OMR - output modification register. Upper 16 bits is used to clear pins */
port->OMR = (value & mask) | (~value & mask) << 16;
return 0;
}
static int gpio_xmc4xxx_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
gpio_port_pins_t pin_mask = config->common.port_pin_mask;
port->OMR = pins & pin_mask;
return 0;
}
static int gpio_xmc4xxx_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
port->OMR = pins << 16;
return 0;
}
static int gpio_xmc4xxx_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_xmc4xxx_config *config = dev->config;
XMC_GPIO_PORT_t *port = config->port;
gpio_port_pins_t pin_mask = config->common.port_pin_mask;
pins &= pin_mask;
port->OMR = pins | pins << 16;
return 0;
}
static int gpio_xmc4xxx_init(const struct device *dev) { return 0; }
static const struct gpio_driver_api gpio_xmc4xxx_driver_api = {
.pin_configure = gpio_xmc4xxx_pin_configure,
.port_get_raw = gpio_xmc4xxx_get_raw,
.port_set_masked_raw = gpio_xmc4xxx_set_masked_raw,
.port_set_bits_raw = gpio_xmc4xxx_set_bits_raw,
.port_clear_bits_raw = gpio_xmc4xxx_clear_bits_raw,
.port_toggle_bits = gpio_xmc4xxx_toggle_bits,
#ifdef CONFIG_XMC4XXX_INTC
.pin_interrupt_configure = gpio_xmc4xxx_pin_interrupt_configure,
.manage_callback = gpio_xmc4xxx_manage_callback,
#endif
};
#define GPIO_XMC4XXX_INIT(index) \
static struct gpio_xmc4xxx_data xmc4xxx_data_##index; \
\
static const struct gpio_xmc4xxx_config xmc4xxx_config_##index = { \
.port = (XMC_GPIO_PORT_t *)DT_INST_REG_ADDR(index), \
.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(index)}}; \
\
DEVICE_DT_INST_DEFINE(index, gpio_xmc4xxx_init, NULL, &xmc4xxx_data_##index, \
&xmc4xxx_config_##index, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_xmc4xxx_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_XMC4XXX_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,805 |
```unknown
# IMX GPIO configuration options
config GPIO_IMX
bool "IMX GPIO driver"
default y
depends on HAS_IMX_GPIO
depends on DT_HAS_NXP_IMX_GPIO_ENABLED
select PINCTRL
help
Enable the IMX GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.imx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(fxl6408, CONFIG_FXL6408_LOG_LEVEL);
#define DT_DRV_COMPAT fcs_fxl6408
/* Register definitions */
#define REG_DEVICE_ID_CTRL 0x01
#define REG_DIRECTION 0x03
#define REG_OUTPUT 0x05
#define REG_OUTPUT_HIGH_Z 0x07
#define REG_INPUT_DEFAULT_STATE 0x09
#define REG_PUD_EN 0x0B
#define REG_PUD_SEL 0x0D
#define REG_INPUT_VALUE 0x0F
#define REG_INT_MASK 0x11
#define REG_INT_STATUS 0x13
#define SUPPORTED_FLAGS (GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW |\
GPIO_OUTPUT_INIT_HIGH | GPIO_PULL_DOWN | GPIO_PULL_UP |\
GPIO_ACTIVE_HIGH | GPIO_ACTIVE_LOW)
/** Configuration data*/
struct gpio_fxl6408_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/** Controller I2C DT specification */
struct i2c_dt_spec i2c;
};
/** Runtime driver data */
struct gpio_fxl6408_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct {
uint8_t input;
uint8_t output;
uint8_t dir;
uint8_t high_z;
uint8_t pud_en;
uint8_t pud_sel;
} reg_cache;
struct k_sem lock;
};
/**
* @brief Read the port of certain register function.
*
* @param dev Device struct of the FXL6408.
* @param reg Register to read.
* @param cache Pointer to the cache to be updated after successful read.
*
* @return 0 if successful, failed otherwise.
*/
static int read_port_regs(const struct device *dev, uint8_t reg, uint8_t *cache)
{
const struct gpio_fxl6408_config *const config = dev->config;
uint8_t port_data;
int ret;
ret = i2c_reg_read_byte_dt(&config->i2c, reg, &port_data);
if (ret != 0) {
LOG_ERR("Error reading register 0x%X (%d)", reg, ret);
return ret;
}
*cache = port_data;
LOG_DBG("Read: REG[0x%X] = 0x%X", reg, *cache);
return ret;
}
/**
* @brief Write to the port registers of certain register function.
*
* @param dev Device struct of the FXL6408.
* @param reg Register to write into. Possible values: REG_DEVICE_ID_CTRL,
* REG_OUTPUT, REG_DIRECTION, REG_PUD_SEL, REG_PUD_EN, REG_OUTPUT_HIGH_Z and
* REG_INPUT_DEFAULT.
* @param cache Pointer to the cache to be updated after successful write.
* @param value New value to set.
*
* @return 0 if successful, failed otherwise.
*/
static int write_port_regs(const struct device *dev, uint8_t reg,
uint8_t *cache, uint8_t value)
{
const struct gpio_fxl6408_config *const config = dev->config;
int ret = 0;
if (*cache != value) {
ret = i2c_reg_write_byte_dt(&config->i2c, reg, value);
if (ret != 0) {
LOG_ERR("error writing to register 0x%X (%d)",
reg, ret);
return ret;
}
*cache = value;
LOG_DBG("Write: REG[0x%X] = 0x%X", reg, *cache);
}
return ret;
}
static inline int update_input_regs(const struct device *dev, uint8_t *buf)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
int ret = read_port_regs(dev, REG_INPUT_VALUE,
&drv_data->reg_cache.input);
*buf = drv_data->reg_cache.input;
return ret;
}
static inline int update_output_regs(const struct device *dev, uint8_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
return write_port_regs(dev, REG_OUTPUT,
&drv_data->reg_cache.output, value);
}
static inline int update_high_z_regs(const struct device *dev, uint8_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
return write_port_regs(dev, REG_OUTPUT_HIGH_Z,
&drv_data->reg_cache.high_z, value);
}
static inline int update_direction_regs(const struct device *dev, uint8_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
return write_port_regs(dev, REG_DIRECTION,
&drv_data->reg_cache.dir, value);
}
static inline int update_pul_sel_regs(const struct device *dev, uint8_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
return write_port_regs(dev, REG_PUD_SEL,
&drv_data->reg_cache.pud_sel, value);
}
static inline int update_pul_en_regs(const struct device *dev, uint8_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
return write_port_regs(dev, REG_PUD_EN,
&drv_data->reg_cache.pud_en, value);
}
static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
uint8_t reg_dir = drv_data->reg_cache.dir;
uint8_t reg_out = drv_data->reg_cache.output;
uint8_t reg_high_z = drv_data->reg_cache.high_z;
int ret;
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
/* Update the driver data to the actual situation of the FXL6408 */
if (flags & GPIO_OUTPUT) {
if ((flags & GPIO_OUTPUT_INIT_HIGH)) {
reg_out |= BIT(pin);
} else if ((flags & GPIO_OUTPUT_INIT_LOW)) {
reg_out &= ~BIT(pin);
}
reg_dir |= BIT(pin);
reg_high_z &= ~BIT(pin);
} else if (flags & GPIO_INPUT) {
reg_dir &= ~BIT(pin);
reg_high_z &= ~BIT(pin);
} else {
reg_high_z |= BIT(pin);
reg_dir |= BIT(pin);
}
ret = update_output_regs(dev, reg_out);
if (ret != 0) {
return ret;
}
ret = update_high_z_regs(dev, reg_high_z);
if (ret != 0) {
return ret;
}
ret = update_direction_regs(dev, reg_dir);
return ret;
}
/**
* @brief Setup the pin pull up/pull down status
*
* @param dev Device struct of the FXL6408
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int setup_pin_pullupdown(const struct device *dev, uint32_t pin,
int flags)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
uint8_t reg_pud;
int ret;
/* If disabling pull up/down, there is no need to set the selection
* register. Just go straight to disabling.
*/
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
/* Setup pin pull up or pull down */
reg_pud = drv_data->reg_cache.pud_sel;
/* Pull down == 0, pull up == 1 */
WRITE_BIT(reg_pud, pin, (flags & GPIO_PULL_UP) != 0U);
ret = update_pul_sel_regs(dev, reg_pud);
if (ret != 0) {
return ret;
}
}
/* Enable/disable pull up/down */
reg_pud = drv_data->reg_cache.pud_en;
WRITE_BIT(reg_pud, pin,
(flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U);
ret = update_pul_en_regs(dev, reg_pud);
return ret;
}
static int gpio_fxl6408_pin_config(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
int ret;
/* Check if supported flag is set */
if ((flags & ~SUPPORTED_FLAGS) != 0) {
return -ENOTSUP;
}
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = setup_pin_dir(dev, pin, flags);
if (ret != 0) {
LOG_ERR("error setting pin direction (%d)", ret);
goto done;
}
ret = setup_pin_pullupdown(dev, pin, flags);
if (ret) {
LOG_ERR("error setting pin pull up/down (%d)", ret);
goto done;
}
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_fxl6408_port_get_raw(const struct device *dev, uint32_t *value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
uint8_t buf = 0;
int ret = 0;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
ret = update_input_regs(dev, &buf);
if (ret != 0) {
goto done;
}
*value = buf;
done:
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_fxl6408_port_set_masked_raw(const struct device *dev,
uint32_t mask, uint32_t value)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
uint8_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->reg_cache.output;
reg_out = (reg_out & ~mask) | (mask & value);
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
static int gpio_fxl6408_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_fxl6408_port_set_masked_raw(dev, mask, mask);
}
static int gpio_fxl6408_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
return gpio_fxl6408_port_set_masked_raw(dev, mask, 0);
}
static int gpio_fxl6408_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
uint8_t reg_out;
int ret;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
reg_out = drv_data->reg_cache.output;
reg_out ^= mask;
ret = update_output_regs(dev, reg_out);
k_sem_give(&drv_data->lock);
return ret;
}
int gpio_fxl6408_init(const struct device *dev)
{
struct gpio_fxl6408_drv_data *const drv_data =
(struct gpio_fxl6408_drv_data *const)dev->data;
const struct gpio_fxl6408_config *const config = dev->config;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("%s is not ready", config->i2c.bus->name);
return -ENODEV;
}
k_sem_init(&drv_data->lock, 1, 1);
return 0;
}
static const struct gpio_driver_api gpio_fxl_driver = {
.pin_configure = gpio_fxl6408_pin_config,
.port_get_raw = gpio_fxl6408_port_get_raw,
.port_set_masked_raw = gpio_fxl6408_port_set_masked_raw,
.port_set_bits_raw = gpio_fxl6408_port_set_bits_raw,
.port_clear_bits_raw = gpio_fxl6408_port_clear_bits_raw,
.port_toggle_bits = gpio_fxl6408_port_toggle_bits,
};
#define GPIO_FXL6408_DEVICE_INSTANCE(inst) \
static const struct gpio_fxl6408_config gpio_fxl6408_##inst##_cfg = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst),\
}, \
.i2c = I2C_DT_SPEC_INST_GET(inst) \
}; \
\
static struct gpio_fxl6408_drv_data gpio_fxl6408_##inst##_drvdata = { \
.reg_cache = { \
.input = 0x0, \
.output = 0x00, \
.dir = 0x0, \
.high_z = 0xFF, \
.pud_en = 0xFF, \
.pud_sel = 0x0 \
} \
}; \
\
DEVICE_DT_INST_DEFINE(inst, gpio_fxl6408_init, NULL, \
&gpio_fxl6408_##inst##_drvdata, \
&gpio_fxl6408_##inst##_cfg, POST_KERNEL, \
CONFIG_GPIO_FXL6408_INIT_PRIORITY, \
&gpio_fxl_driver);
DT_INST_FOREACH_STATUS_OKAY(GPIO_FXL6408_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_fxl6408.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,213 |
```unknown
# GPIO configuration options
menuconfig GPIO
bool "General-Purpose Input/Output (GPIO) drivers"
help
Include GPIO drivers in system config
if GPIO
module = GPIO
module-str = gpio
source "subsys/logging/Kconfig.template.log_config"
config GPIO_SHELL
bool "GPIO Shell"
depends on SHELL
imply DEVICE_DT_METADATA
help
Enable GPIO Shell for testing.
config GPIO_SHELL_INFO_CMD
bool "GPIO Shell info command"
default y
depends on GPIO_SHELL
help
Enable GPIO Shell information command.
This command provides a shell user extra information about gpio
controller reserved pins and line names.
config GPIO_SHELL_TOGGLE_CMD
bool "GPIO Shell toggle command"
default y
depends on GPIO_SHELL
help
Enable GPIO Shell toggle command.
config GPIO_SHELL_BLINK_CMD
bool "GPIO Shell blink command"
default y
depends on GPIO_SHELL
help
Enable GPIO Shell blink command.
This command provides a shell user the ability to 'blink' a pin
at 1Hz.
config GPIO_INIT_PRIORITY
int "GPIO init priority"
default KERNEL_INIT_PRIORITY_DEFAULT
help
GPIO driver device initialization priority.
config GPIO_GET_DIRECTION
bool "Support for querying GPIO direction [EXPERIMENTAL]"
select EXPERIMENTAL
help
Enable this option if the application does not maintain its own GPIO
direction state.
With this option enabled, the application may query GPIO direction
via gpio_port_get_direction(), gpio_pin_is_input(), and
gpio_pin_is_output().
config GPIO_GET_CONFIG
bool "Support for get configuration function [EXPERIMENTAL]"
select EXPERIMENTAL
help
This option enables the support for getting the current configurations
of GPIOs. The driver must implement it to work.
config GPIO_HOGS
bool "Support for GPIO hogs"
default $(dt_gpio_hogs_enabled)
help
Enable support for GPIO hogs. GPIO hogging is a mechanism for providing
automatic GPIO configuration via devicetree.
config GPIO_HOGS_INIT_PRIORITY
int "GPIO hogs init priority"
default 41
depends on GPIO_HOGS
help
GPIO hogs initialization priority. GPIO hogs must be initialized after the
GPIO controller drivers.
config GPIO_ENABLE_DISABLE_INTERRUPT
bool "Support for enable/disable interrupt without re-config [EXPERIMENTAL]"
select EXPERIMENTAL
help
This option enables the support for enabling/disabling interrupt with
previous configuration, and enabling/disabling the interrupt only turns
on/off the interrupt signal without changing other registers, such as
pending register, etc. The driver must implement it to work.
# zephyr-keep-sorted-start
source "drivers/gpio/Kconfig.ad559x"
source "drivers/gpio/Kconfig.adp5585"
source "drivers/gpio/Kconfig.ads114s0x"
source "drivers/gpio/Kconfig.altera"
source "drivers/gpio/Kconfig.ambiq"
source "drivers/gpio/Kconfig.andes_atcgpio100"
source "drivers/gpio/Kconfig.axp192"
source "drivers/gpio/Kconfig.b91"
source "drivers/gpio/Kconfig.bcm2711"
source "drivers/gpio/Kconfig.bd8lb600fs"
source "drivers/gpio/Kconfig.brcmstb"
source "drivers/gpio/Kconfig.cc13xx_cc26xx"
source "drivers/gpio/Kconfig.cc32xx"
source "drivers/gpio/Kconfig.cmsdk_ahb"
source "drivers/gpio/Kconfig.creg_gpio"
source "drivers/gpio/Kconfig.cy8c95xx"
source "drivers/gpio/Kconfig.davinci"
source "drivers/gpio/Kconfig.dw"
source "drivers/gpio/Kconfig.efinix_sapphire"
source "drivers/gpio/Kconfig.emul"
source "drivers/gpio/Kconfig.emul_sdl"
source "drivers/gpio/Kconfig.ene"
source "drivers/gpio/Kconfig.eos_s3"
source "drivers/gpio/Kconfig.esp32"
source "drivers/gpio/Kconfig.fxl6408"
source "drivers/gpio/Kconfig.gd32"
source "drivers/gpio/Kconfig.gecko"
source "drivers/gpio/Kconfig.grgpio"
source "drivers/gpio/Kconfig.ifx_cat1"
source "drivers/gpio/Kconfig.imx"
source "drivers/gpio/Kconfig.intel"
source "drivers/gpio/Kconfig.iproc"
source "drivers/gpio/Kconfig.it8xxx2"
source "drivers/gpio/Kconfig.litex"
source "drivers/gpio/Kconfig.lmp90xxx"
source "drivers/gpio/Kconfig.lpc11u6x"
source "drivers/gpio/Kconfig.max32"
source "drivers/gpio/Kconfig.mchp_mss"
source "drivers/gpio/Kconfig.mcp23xxx"
source "drivers/gpio/Kconfig.mcux"
source "drivers/gpio/Kconfig.mcux_igpio"
source "drivers/gpio/Kconfig.mcux_lpc"
source "drivers/gpio/Kconfig.mcux_rgpio"
source "drivers/gpio/Kconfig.mmio32"
source "drivers/gpio/Kconfig.nct38xx"
source "drivers/gpio/Kconfig.neorv32"
source "drivers/gpio/Kconfig.npcx"
source "drivers/gpio/Kconfig.npm1300"
source "drivers/gpio/Kconfig.npm6001"
source "drivers/gpio/Kconfig.nrfx"
source "drivers/gpio/Kconfig.numaker"
source "drivers/gpio/Kconfig.numicro"
source "drivers/gpio/Kconfig.nxp_s32"
source "drivers/gpio/Kconfig.pca953x"
source "drivers/gpio/Kconfig.pca95xx"
source "drivers/gpio/Kconfig.pcal64xxa"
source "drivers/gpio/Kconfig.pcf857x"
source "drivers/gpio/Kconfig.psoc6"
source "drivers/gpio/Kconfig.rcar"
source "drivers/gpio/Kconfig.renesas_ra"
source "drivers/gpio/Kconfig.renesas_ra_ioport"
source "drivers/gpio/Kconfig.rpi_pico"
source "drivers/gpio/Kconfig.rt1718s"
source "drivers/gpio/Kconfig.rv32m1"
source "drivers/gpio/Kconfig.rzt2m"
source "drivers/gpio/Kconfig.sam"
source "drivers/gpio/Kconfig.sam0"
source "drivers/gpio/Kconfig.sc18im704"
source "drivers/gpio/Kconfig.sedi"
source "drivers/gpio/Kconfig.sifive"
source "drivers/gpio/Kconfig.smartbond"
source "drivers/gpio/Kconfig.sn74hc595"
source "drivers/gpio/Kconfig.stellaris"
source "drivers/gpio/Kconfig.stm32"
source "drivers/gpio/Kconfig.stmpe1600"
source "drivers/gpio/Kconfig.sx1509b"
source "drivers/gpio/Kconfig.tca6424a"
source "drivers/gpio/Kconfig.test"
source "drivers/gpio/Kconfig.tle9104"
source "drivers/gpio/Kconfig.xec"
source "drivers/gpio/Kconfig.xlnx"
source "drivers/gpio/Kconfig.xlnx_ps"
source "drivers/gpio/Kconfig.xmc4xxx"
# zephyr-keep-sorted-stop
endif # GPIO
``` | /content/code_sandbox/drivers/gpio/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,462 |
```objective-c
/*
* Xilinx Processor System MIO / EMIO GPIO controller driver
*
* Driver private data declarations, parent (IRQ handler) module
*
*/
#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
/* Type definitions */
/* IRQ handler function type */
typedef void (*gpio_xlnx_ps_config_irq_t)(const struct device *dev);
/**
* @brief Run-time modifiable device data structure.
*
* This struct contains all data of the PS GPIO controller parent
* (IRQ handler) which is modifiable at run-time.
*/
struct gpio_xlnx_ps_dev_data {
struct gpio_driver_data common;
};
/**
* @brief Constant device configuration data structure.
*
* This struct contains all data of the PS GPIO controller parent
* which is required for proper operation (such as base memory
* addresses, references to all associated banks etc.) which don't
* have to and therefore cannot be modified at run-time.
*/
struct gpio_xlnx_ps_dev_cfg {
struct gpio_driver_config common;
uint32_t base_addr;
const struct device *const *bank_devices;
uint32_t num_banks;
gpio_xlnx_ps_config_irq_t config_func;
};
#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_xlnx_ps.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 279 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_gpio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <zephyr/dt-bindings/gpio/atmel-sam-gpio.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
typedef void (*config_func_t)(const struct device *dev);
struct gpio_sam_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
Pio *regs;
config_func_t config_func;
const struct atmel_sam_pmc_config clock_cfg;
};
struct gpio_sam_runtime {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
#define GPIO_SAM_ALL_PINS 0xFFFFFFFF
static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
gpio_flags_t flags)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
if ((flags & GPIO_SINGLE_ENDED) != 0) {
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
/* Enable open-drain drive mode */
pio->PIO_MDER = mask;
} else {
/* Open-drain is the only supported single-ended mode */
return -ENOTSUP;
}
} else {
/* Disable open-drain drive mode */
pio->PIO_MDDR = mask;
}
if (!(flags & (GPIO_OUTPUT | GPIO_INPUT))) {
/* Neither input nor output mode is selected */
/* Disable the interrupt. */
pio->PIO_IDR = mask;
/* Disable pull-up. */
pio->PIO_PUDR = mask;
#if defined(CONFIG_SOC_SERIES_SAM4S) || \
defined(CONFIG_SOC_SERIES_SAM4E) || \
defined(CONFIG_SOC_SERIES_SAME70) || \
defined(CONFIG_SOC_SERIES_SAMV71)
/* Disable pull-down. */
pio->PIO_PPDDR = mask;
#endif
/* Let the PIO control the pin (instead of a peripheral). */
pio->PIO_PER = mask;
/* Disable output. */
pio->PIO_ODR = mask;
return 0;
}
/* Setup the pin direction. */
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
/* Set the pin. */
pio->PIO_SODR = mask;
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
/* Clear the pin. */
pio->PIO_CODR = mask;
}
/* Enable the output */
pio->PIO_OER = mask;
/* Enable direct control of output level via PIO_ODSR */
pio->PIO_OWER = mask;
} else {
/* Disable the output */
pio->PIO_ODR = mask;
}
/* Note: Input is always enabled. */
/* Setup selected Pull resistor.
*
* A pull cannot be enabled if the opposite pull is enabled.
* Clear both pulls, then enable the one we need.
*/
pio->PIO_PUDR = mask;
#if defined(CONFIG_SOC_SERIES_SAM4S) || \
defined(CONFIG_SOC_SERIES_SAM4E) || \
defined(CONFIG_SOC_SERIES_SAME70) || \
defined(CONFIG_SOC_SERIES_SAMV71)
pio->PIO_PPDDR = mask;
#endif
if (flags & GPIO_PULL_UP) {
/* Enable pull-up. */
pio->PIO_PUER = mask;
#if defined(CONFIG_SOC_SERIES_SAM4S) || \
defined(CONFIG_SOC_SERIES_SAM4E) || \
defined(CONFIG_SOC_SERIES_SAME70) || \
defined(CONFIG_SOC_SERIES_SAMV71)
/* Setup Pull-down resistor. */
} else if (flags & GPIO_PULL_DOWN) {
/* Enable pull-down. */
pio->PIO_PPDER = mask;
#endif
}
#if defined(CONFIG_SOC_SERIES_SAM3X)
/* Setup debounce. */
if (flags & SAM_GPIO_DEBOUNCE) {
pio->PIO_DIFSR = mask;
} else {
pio->PIO_SCIFSR = mask;
}
#elif defined(CONFIG_SOC_SERIES_SAM4S) || \
defined(CONFIG_SOC_SERIES_SAM4E) || \
defined(CONFIG_SOC_SERIES_SAME70) || \
defined(CONFIG_SOC_SERIES_SAMV71)
/* Setup debounce. */
if (flags & SAM_GPIO_DEBOUNCE) {
pio->PIO_IFSCER = mask;
} else {
pio->PIO_IFSCDR = mask;
}
#endif
/* Enable the PIO to control the pin (instead of a peripheral). */
pio->PIO_PER = mask;
return 0;
}
static int gpio_sam_config(const struct device *dev, gpio_pin_t pin,
gpio_flags_t flags)
{
return gpio_sam_port_configure(dev, BIT(pin), flags);
}
static int gpio_sam_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
*value = pio->PIO_PDSR;
return 0;
}
static int gpio_sam_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
pio->PIO_ODSR = (pio->PIO_ODSR & ~mask) | (mask & value);
return 0;
}
static int gpio_sam_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
/* Set pins. */
pio->PIO_SODR = mask;
return 0;
}
static int gpio_sam_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
/* Clear pins. */
pio->PIO_CODR = mask;
return 0;
}
static int gpio_sam_port_toggle_bits(const struct device *dev, uint32_t mask)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
/* Toggle pins. */
pio->PIO_ODSR ^= mask;
return 0;
}
static int gpio_sam_port_interrupt_configure(const struct device *dev,
uint32_t mask,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
/* Disable the interrupt. */
pio->PIO_IDR = mask;
/* Disable additional interrupt modes. */
pio->PIO_AIMDR = mask;
if (trig != GPIO_INT_TRIG_BOTH) {
/* Enable additional interrupt modes to support single
* edge/level detection.
*/
pio->PIO_AIMER = mask;
if (mode == GPIO_INT_MODE_EDGE) {
pio->PIO_ESR = mask;
} else {
pio->PIO_LSR = mask;
}
uint32_t rising_edge;
if (trig == GPIO_INT_TRIG_HIGH) {
rising_edge = mask;
} else {
rising_edge = ~mask;
}
/* Set to high-level or rising edge. */
pio->PIO_REHLSR = rising_edge & mask;
/* Set to low-level or falling edge. */
pio->PIO_FELLSR = ~rising_edge & mask;
}
if (mode != GPIO_INT_MODE_DISABLED) {
/* Clear any pending interrupts */
(void)pio->PIO_ISR;
/* Enable the interrupt. */
pio->PIO_IER = mask;
}
return 0;
}
static int gpio_sam_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
return gpio_sam_port_interrupt_configure(dev, BIT(pin), mode, trig);
}
static void gpio_sam_isr(const struct device *dev)
{
const struct gpio_sam_config * const cfg = dev->config;
Pio * const pio = cfg->regs;
struct gpio_sam_runtime *context = dev->data;
uint32_t int_stat;
int_stat = pio->PIO_ISR;
gpio_fire_callbacks(&context->cb, dev, int_stat);
}
static int gpio_sam_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
struct gpio_sam_runtime *context = port->data;
return gpio_manage_callback(&context->cb, callback, set);
}
static const struct gpio_driver_api gpio_sam_api = {
.pin_configure = gpio_sam_config,
.port_get_raw = gpio_sam_port_get_raw,
.port_set_masked_raw = gpio_sam_port_set_masked_raw,
.port_set_bits_raw = gpio_sam_port_set_bits_raw,
.port_clear_bits_raw = gpio_sam_port_clear_bits_raw,
.port_toggle_bits = gpio_sam_port_toggle_bits,
.pin_interrupt_configure = gpio_sam_pin_interrupt_configure,
.manage_callback = gpio_sam_manage_callback,
};
int gpio_sam_init(const struct device *dev)
{
const struct gpio_sam_config * const cfg = dev->config;
/* Enable GPIO clock in PMC. This is necessary to enable interrupts */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&cfg->clock_cfg);
cfg->config_func(dev);
return 0;
}
#define GPIO_SAM_INIT(n) \
static void port_##n##_sam_config_func(const struct device *dev); \
\
static const struct gpio_sam_config port_##n##_sam_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
.regs = (Pio *)DT_INST_REG_ADDR(n), \
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
.config_func = port_##n##_sam_config_func, \
}; \
\
static struct gpio_sam_runtime port_##n##_sam_runtime; \
\
DEVICE_DT_INST_DEFINE(n, gpio_sam_init, NULL, \
&port_##n##_sam_runtime, \
&port_##n##_sam_config, PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_sam_api); \
\
static void port_##n##_sam_config_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
gpio_sam_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(GPIO_SAM_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,506 |
```c
/*
* Xilinx Processor System MIO / EMIO GPIO controller driver
* GPIO bank module
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_xlnx_ps_bank.h"
#define LOG_MODULE_NAME gpio_xlnx_ps_bank
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define DT_DRV_COMPAT xlnx_ps_gpio_bank
/**
* @brief GPIO bank pin configuration function
*
* Configures an individual pin within a MIO / EMIO GPIO pin bank.
* The following flags specified by the GPIO subsystem are NOT
* supported by the PS GPIO controller:
*
* - Pull up
* - Pull down
* - Open drain
* - Open source.
*
* @param dev Pointer to the GPIO bank's device.
* @param pin Index of the pin within the bank to be configured
* (decimal index of the pin).
* @param flags Flags specifying the pin's configuration.
*
* @retval 0 if the device initialization completed successfully,
* -EINVAL if the specified pin index is out of range,
* -ENOTSUP if the pin configuration data contains a flag
* that is not supported by the controller.
*/
static int gpio_xlnx_ps_pin_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t pin_mask = BIT(pin);
uint32_t bank_data;
uint32_t dirm_data;
uint32_t oen_data;
/* Validity of the specified pin index is checked in drivers/gpio.h */
/* Check for config flags not supported by the controller */
if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_SINGLE_ENDED)) {
return -ENOTSUP;
}
/* Read the data direction & output enable registers */
dirm_data = sys_read32(GPIO_XLNX_PS_BANK_DIRM_REG);
oen_data = sys_read32(GPIO_XLNX_PS_BANK_OEN_REG);
if (flags & GPIO_OUTPUT) {
dirm_data |= pin_mask;
oen_data |= pin_mask;
/*
* Setting of an initial value (see below) requires the
* direction register to be written *BEFORE* the data
* register, otherwise, the value will not be applied!
* The output enable bit can be set after the initial
* value has been written.
*/
sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG);
/*
* If the current pin is to be configured as an output
* pin, it is up to the caller to specify whether the
* output's initial value shall be high or low.
* -> Write the initial output value into the data register.
*/
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
if (flags & GPIO_OUTPUT_INIT_HIGH) {
bank_data |= pin_mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
bank_data &= ~pin_mask;
}
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
/* Set the pin's output enable bit */
sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG);
} else {
dirm_data &= ~pin_mask;
oen_data &= ~pin_mask;
/*
* Disable the output first in case of an O -> I
* transition, then change the pin's direction.
*/
sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG);
sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG);
}
return 0;
}
/**
* @brief Reads the current bit mask of the entire GPIO pin bank.
*
* Reads the current bit mask of the entire bank from the
* read-only data register. This includes the current values
* of not just all input pins, but both the input and output
* pins within the bank.
*
* @param dev Pointer to the GPIO bank's device.
* @param value Pointer to a variable of type gpio_port_value_t
* to which the current bit mask read from the bank's
* RO data register will be written to.
*
* @retval 0 if the read operation completed successfully,
* -EINVAL if the pointer to the output variable is NULL.
*/
static int gpio_xlnx_ps_bank_get(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
*value = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
}
/**
* @brief Masked write of a bit mask for the entire GPIO pin bank.
*
* Performs a masked write operation on the data register of
* the current GPIO pin bank. The mask is applied twice:
* first, it is applied to the current contents of the bank's
* RO data register, clearing any bits that are zeroes in the
* mask (will not have any effect on input pins). Second, it
* is applied to the data word to be written into the current
* bank's data register. The masked data word read from the
* RO data register and the masked data word provided by the
* caller ar then OR'ed and written to the bank's data register.
*
* @param dev Pointer to the GPIO bank's device.
* @param mask Mask to be applied to both the current contents
* of the data register and the data word provided
* by the caller.
* @param value Value to be written to the current bank's data
* register.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_bank_set_masked(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t bank_data;
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
bank_data = (bank_data & ~mask) | (value & mask);
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
}
/**
* @brief Sets bits in the data register of the GPIO pin bank.
*
* Sets bits in the data register of the current GPIO pin bank
* as a read-modify-write operation. All bits set in the bit
* mask provided by the caller are OR'ed into the current data
* word of the bank. This operation has no effect on the values
* associated with pins configured as inputs.
*
* @param dev Pointer to the GPIO bank's device.
* @param pins Bit mask specifying which bits shall be set in
* the data word of the current GPIO pin bank.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_bank_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t bank_data;
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
bank_data |= pins;
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
}
/**
* @brief Clears bits in the data register of the GPIO pin bank.
*
* Clears bits in the data register of the current GPIO pin bank
* as a read-modify-write operation. All bits set in the bit
* mask provided by the caller are NAND'ed into the current data
* word of the bank. This operation has no effect on the values
* associated with pins configured as inputs.
*
* @param dev Pointer to the GPIO bank's device.
* @param pins Bit mask specifying which bits shall be cleared
* in the data word of the current GPIO pin bank.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_bank_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t bank_data;
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
bank_data &= ~pins;
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
}
/**
* @brief Toggles bits in the data register of the GPIO pin bank.
*
* Toggles bits in the data register of the current GPIO pin bank
* as a read-modify-write operation. All bits set in the bit
* mask provided by the caller are XOR'ed into the current data
* word of the bank. This operation has no effect on the values
* associated with pins configured as inputs.
*
* @param dev Pointer to the GPIO bank's device.
* @param pins Bit mask specifying which bits shall be toggled
* in the data word of the current GPIO pin bank.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_bank_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t bank_data;
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
bank_data ^= pins;
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
}
/**
* @brief Configures the interrupt behaviour of a pin within the
* current GPIO bank.
*
* Configures the interrupt behaviour of a pin within the current
* GPIO bank. If a pin is to be configured to trigger an interrupt,
* the following modes are supported:
*
* - edge or level triggered,
* - rising edge / high level or falling edge / low level,
* - in edge mode only: trigger on both rising and falling edge.
*
* @param dev Pointer to the GPIO bank's device.
* @param pin Index of the pin within the bank to be configured
* (decimal index of the pin).
* @param mode Mode configuration: edge, level or interrupt disabled.
* @param trig Trigger condition configuration: high/low level or
* rising/falling/both edge(s).
*
* @retval 0 if the interrupt configuration completed successfully,
* -EINVAL if the specified pin index is out of range,
* -ENOTSUP if the interrupt configuration data contains an
* invalid combination of configuration flags.
*/
static int gpio_xlnx_ps_bank_pin_irq_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t pin_mask = BIT(pin);
uint32_t int_type_data;
uint32_t int_polarity_data;
uint32_t int_any_data;
/* Validity of the specified pin index is checked in drivers/gpio.h */
/* Disable the specified pin's interrupt before (re-)configuring it */
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_DIS_REG);
int_type_data = sys_read32(GPIO_XLNX_PS_BANK_INT_TYPE_REG);
int_polarity_data = sys_read32(GPIO_XLNX_PS_BANK_INT_POLARITY_REG);
int_any_data = sys_read32(GPIO_XLNX_PS_BANK_INT_ANY_REG);
if (mode != GPIO_INT_MODE_DISABLED) {
if (mode == GPIO_INT_MODE_LEVEL) {
int_type_data &= ~pin_mask;
} else if (mode == GPIO_INT_MODE_EDGE) {
int_type_data |= pin_mask;
} else {
return -EINVAL;
}
if (trig == GPIO_INT_TRIG_LOW) {
int_any_data &= ~pin_mask;
int_polarity_data &= ~pin_mask;
} else if (trig == GPIO_INT_TRIG_HIGH) {
int_any_data &= ~pin_mask;
int_polarity_data |= pin_mask;
} else if (trig == GPIO_INT_TRIG_BOTH) {
if (mode == GPIO_INT_MODE_LEVEL) {
return -EINVAL;
}
int_any_data |= pin_mask;
}
} else { /* mode == GPIO_INT_MODE_DISABLED */
int_any_data &= ~pin_mask;
int_polarity_data &= ~pin_mask;
int_type_data &= ~pin_mask;
}
sys_write32(int_any_data, GPIO_XLNX_PS_BANK_INT_ANY_REG);
sys_write32(int_polarity_data, GPIO_XLNX_PS_BANK_INT_POLARITY_REG);
sys_write32(int_type_data, GPIO_XLNX_PS_BANK_INT_TYPE_REG);
if (mode != GPIO_INT_MODE_DISABLED) {
/* Clear potential stale pending bit before enabling interrupt */
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_STAT_REG);
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_EN_REG);
}
return 0;
}
/**
* @brief Returns the interrupt status of the current GPIO bank.
*
* Returns the interrupt status of the current GPIO bank, in the
* form of a bit mask where each pin with a pending interrupt is
* indicated. This information can either be used by the PM sub-
* system or the parent controller device driver, which manages
* the interrupt line of the entire PS GPIO controller, regardless
* of how many bank sub-devices exist. As the current status is
* read, it is automatically cleared. Callback triggering is handled
* by the parent controller device.
*
* @param dev Pointer to the GPIO bank's device.
*
* @retval A bit mask indicating for which pins within the bank
* an interrupt is pending.
*/
static uint32_t gpio_xlnx_ps_bank_get_int_status(const struct device *dev)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
uint32_t int_status;
int_status = sys_read32(GPIO_XLNX_PS_BANK_INT_STAT_REG);
if (int_status != 0) {
sys_write32(int_status, GPIO_XLNX_PS_BANK_INT_STAT_REG);
}
return int_status;
}
/**
* @brief Callback management re-direction function.
*
* Re-directs any callback management calls relating to the current
* GPIO bank to the GPIO sub-system. Comp. documentation of the
* underlying sub-system's #gpio_manage_callback function.
*
* @param dev Pointer to the GPIO bank's device.
* @param callback Pointer to a GPIO callback struct.
* @param set Callback set flag.
*
* @retval A bit mask indicating for which pins within the bank
* an interrupt is pending.
*/
static int gpio_xlnx_ps_bank_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_xlnx_ps_bank_dev_data *dev_data = dev->data;
return gpio_manage_callback(&dev_data->callbacks, callback, set);
}
/* GPIO bank device driver API */
static const struct gpio_driver_api gpio_xlnx_ps_bank_apis = {
.pin_configure = gpio_xlnx_ps_pin_configure,
.port_get_raw = gpio_xlnx_ps_bank_get,
.port_set_masked_raw = gpio_xlnx_ps_bank_set_masked,
.port_set_bits_raw = gpio_xlnx_ps_bank_set_bits,
.port_clear_bits_raw = gpio_xlnx_ps_bank_clear_bits,
.port_toggle_bits = gpio_xlnx_ps_bank_toggle_bits,
.pin_interrupt_configure = gpio_xlnx_ps_bank_pin_irq_configure,
.manage_callback = gpio_xlnx_ps_bank_manage_callback,
.get_pending_int = gpio_xlnx_ps_bank_get_int_status
};
/**
* @brief Initialize a MIO / EMIO GPIO bank sub-device
*
* Initialize a MIO / EMIO GPIO bank sub-device, which is a child
* of the parent Xilinx PS GPIO controller device driver. This ini-
* tialization function sets up a defined initial state for each
* GPIO bank.
*
* @param dev Pointer to the GPIO bank's device.
*
* @retval Always 0.
*/
static int gpio_xlnx_ps_bank_init(const struct device *dev)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_DIS_REG); /* Disable all interrupts */
sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_STAT_REG); /* Clear all interrupts */
sys_write32(0x0, GPIO_XLNX_PS_BANK_OEN_REG); /* All outputs disabled */
sys_write32(0x0, GPIO_XLNX_PS_BANK_DIRM_REG); /* All pins input */
sys_write32(0x0, GPIO_XLNX_PS_BANK_DATA_REG); /* Zero data register */
return 0;
}
/* MIO / EMIO bank device definition macros */
#define GPIO_XLNX_PS_BANK_INIT(idx)\
static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
.common = {\
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
},\
.base_addr = DT_REG_ADDR(DT_PARENT(DT_INST(idx, DT_DRV_COMPAT))),\
.bank_index = idx,\
};\
static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data;\
DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
&gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
/* Register & initialize all MIO / EMIO GPIO banks specified in the device tree. */
DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_PS_BANK_INIT);
``` | /content/code_sandbox/drivers/gpio/gpio_xlnx_ps_bank.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,838 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_sn74hc595
/**
* @file Driver for 74 HC shift register
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_sn74hc595, CONFIG_GPIO_LOG_LEVEL);
#if CONFIG_SPI_INIT_PRIORITY >= CONFIG_GPIO_SN74HC595_INIT_PRIORITY
#error SPI_INIT_PRIORITY must be lower than SN74HC595_INIT_PRIORITY
#endif
struct gpio_sn74hc595_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config config;
struct spi_dt_spec bus;
struct gpio_dt_spec reset_gpio;
};
struct gpio_sn74hc595_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data data;
struct k_mutex lock;
uint8_t output;
};
static int sn74hc595_spi_write(const struct device *dev, void *buf, size_t len_bytes)
{
const struct gpio_sn74hc595_config *config = dev->config;
__ASSERT(((buf != NULL) || (len_bytes == 0)), "no valid buffer given");
__ASSERT(!k_is_in_isr(), "attempt to access SPI from ISR");
struct spi_buf tx_buf[] = { { .buf = buf, .len = len_bytes } };
const struct spi_buf_set tx = { .buffers = tx_buf, .count = 1 };
return spi_write_dt(&config->bus, &tx);
}
static int gpio_sn74hc595_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(flags);
return 0;
}
static int gpio_sn74hc595_port_get_raw(const struct device *dev, uint32_t *value)
{
struct gpio_sn74hc595_drv_data *drv_data = dev->data;
k_mutex_lock(&drv_data->lock, K_FOREVER);
*value = drv_data->output;
k_mutex_unlock(&drv_data->lock);
return 0;
}
static int gpio_sn74hc595_port_set_masked_raw(const struct device *dev, uint32_t mask,
uint32_t value)
{
struct gpio_sn74hc595_drv_data *drv_data = dev->data;
int ret = 0;
uint8_t output;
k_mutex_lock(&drv_data->lock, K_FOREVER);
/* check if we need to do something at all */
/* current output differs from new masked value */
if ((drv_data->output & mask) != (mask & value)) {
output = (drv_data->output & ~mask) | (mask & value);
ret = sn74hc595_spi_write(dev, &output, 1U);
if (ret < 0) {
goto unlock;
}
drv_data->output = output;
}
unlock:
k_mutex_unlock(&drv_data->lock);
return ret;
}
static int gpio_sn74hc595_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
return gpio_sn74hc595_port_set_masked_raw(dev, mask, mask);
}
static int gpio_sn74hc595_port_clear_bits_raw(const struct device *dev, uint32_t mask)
{
return gpio_sn74hc595_port_set_masked_raw(dev, mask, 0U);
}
static int gpio_sn74hc595_port_toggle_bits(const struct device *dev, uint32_t mask)
{
struct gpio_sn74hc595_drv_data *drv_data = dev->data;
int ret;
uint8_t toggled_output;
k_mutex_lock(&drv_data->lock, K_FOREVER);
toggled_output = drv_data->output ^ mask;
ret = sn74hc595_spi_write(dev, &toggled_output, 1U);
if (ret < 0) {
goto unlock;
}
drv_data->output ^= mask;
unlock:
k_mutex_unlock(&drv_data->lock);
return ret;
}
static const struct gpio_driver_api gpio_sn74hc595_drv_api_funcs = {
.pin_configure = gpio_sn74hc595_config,
.port_get_raw = gpio_sn74hc595_port_get_raw,
.port_set_masked_raw = gpio_sn74hc595_port_set_masked_raw,
.port_set_bits_raw = gpio_sn74hc595_port_set_bits_raw,
.port_clear_bits_raw = gpio_sn74hc595_port_clear_bits_raw,
.port_toggle_bits = gpio_sn74hc595_port_toggle_bits,
};
/**
* @brief Initialization function of sn74hc595
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_sn74hc595_init(const struct device *dev)
{
const struct gpio_sn74hc595_config *config = dev->config;
struct gpio_sn74hc595_drv_data *drv_data = dev->data;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
if (!gpio_is_ready_dt(&config->reset_gpio)) {
LOG_ERR("GPIO port %s not ready", config->reset_gpio.port->name);
return -ENODEV;
}
if (gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_ACTIVE) < 0) {
LOG_ERR("Unable to configure RST GPIO pin %u", config->reset_gpio.pin);
return -EINVAL;
}
gpio_pin_set(config->reset_gpio.port, config->reset_gpio.pin, 0);
drv_data->output = 0U;
return 0;
}
#define SN74HC595_SPI_OPERATION \
((uint16_t)(SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)))
#define SN74HC595_INIT(n) \
static struct gpio_sn74hc595_drv_data sn74hc595_data_##n = { \
.output = 0, \
.lock = Z_MUTEX_INITIALIZER(sn74hc595_data_##n.lock), \
}; \
\
static const struct gpio_sn74hc595_config sn74hc595_config_##n = { \
.config = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.bus = SPI_DT_SPEC_INST_GET(n, SN74HC595_SPI_OPERATION, 0), \
.reset_gpio = GPIO_DT_SPEC_INST_GET(n, reset_gpios), \
}; \
\
DEVICE_DT_DEFINE(DT_DRV_INST(n), &gpio_sn74hc595_init, NULL, \
&sn74hc595_data_##n, &sn74hc595_config_##n, POST_KERNEL, \
CONFIG_GPIO_SN74HC595_INIT_PRIORITY, &gpio_sn74hc595_drv_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(SN74HC595_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_sn74hc595.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,494 |
```unknown
config GPIO_EFINIX_SAPPHIRE
bool "Efinx sapphire GPIO driver"
default y
depends on DT_HAS_EFINIX_SAPPHIRE_GPIO_ENABLED
help
Enable Efinix sapphire GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.efinix_sapphire | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_stellaris_gpio
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
typedef void (*config_func_t)(const struct device *dev);
struct gpio_stellaris_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
uint32_t base;
uint32_t port_map;
config_func_t config_func;
};
struct gpio_stellaris_runtime {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
#define GPIO_REG_ADDR(base, offset) (base + offset)
#define GPIO_RW_ADDR(base, offset, p) \
(GPIO_REG_ADDR(base, offset) | (1 << (p + 2)))
#define GPIO_RW_MASK_ADDR(base, offset, mask) \
(GPIO_REG_ADDR(base, offset) | (mask << 2))
enum gpio_regs {
GPIO_DATA_OFFSET = 0x000,
GPIO_DIR_OFFSET = 0x400,
GPIO_DEN_OFFSET = 0x51C,
GPIO_IS_OFFSET = 0x404,
GPIO_IBE_OFFSET = 0x408,
GPIO_IEV_OFFSET = 0x40C,
GPIO_IM_OFFSET = 0x410,
GPIO_MIS_OFFSET = 0x418,
GPIO_ICR_OFFSET = 0x41C,
};
static void gpio_stellaris_isr(const struct device *dev)
{
const struct gpio_stellaris_config * const cfg = dev->config;
struct gpio_stellaris_runtime *context = dev->data;
uint32_t base = cfg->base;
uint32_t int_stat = sys_read32(GPIO_REG_ADDR(base, GPIO_MIS_OFFSET));
gpio_fire_callbacks(&context->cb, dev, int_stat);
sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET));
}
static int gpio_stellaris_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
uint32_t port_map = cfg->port_map;
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
/* Check for pin availability */
if (!sys_test_bit((uint32_t)&port_map, pin)) {
return -EINVAL;
}
if ((flags & GPIO_OUTPUT) != 0) {
mm_reg_t mask_addr;
mask_addr = GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, BIT(pin));
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
sys_write32(BIT(pin), mask_addr);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
sys_write32(0, mask_addr);
}
sys_set_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin);
/* Pin digital enable */
sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
} else if ((flags & GPIO_INPUT) != 0) {
sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin);
/* Pin digital enable */
sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
} else {
/* Pin digital disable */
sys_clear_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin);
}
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_stellaris_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
gpio_flags_t flags = 0;
mm_reg_t mask_addr;
if (sys_test_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin) == 0) {
flags = GPIO_DISCONNECTED;
} else if (sys_test_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin)) {
mask_addr = GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, BIT(pin));
if (sys_test_bit(mask_addr, pin)) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
} else {
flags = GPIO_INPUT;
}
*out_flags = flags;
return 0;
}
#endif
static int gpio_stellaris_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
*value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
return 0;
}
static int gpio_stellaris_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
return 0;
}
static int gpio_stellaris_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
sys_write32(mask, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
return 0;
}
static int gpio_stellaris_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
sys_write32(0, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask));
return 0;
}
static int gpio_stellaris_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
uint32_t value;
value = sys_read32(GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
value ^= mask;
sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff));
return 0;
}
static int gpio_stellaris_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_stellaris_config *cfg = dev->config;
uint32_t base = cfg->base;
/* Check if GPIO port needs interrupt support */
if (mode == GPIO_INT_MODE_DISABLED) {
/* Set the mask to disable the interrupt */
sys_set_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin);
} else {
if (mode == GPIO_INT_MODE_EDGE) {
sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin);
} else {
sys_set_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin);
}
if (trig == GPIO_INT_TRIG_BOTH) {
sys_set_bit(GPIO_REG_ADDR(base, GPIO_IBE_OFFSET), pin);
} else if (trig == GPIO_INT_TRIG_HIGH) {
sys_set_bit(GPIO_REG_ADDR(base, GPIO_IEV_OFFSET), pin);
} else {
sys_clear_bit(GPIO_REG_ADDR(base,
GPIO_IEV_OFFSET), pin);
}
/* Clear the Mask to enable the interrupt */
sys_clear_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin);
}
return 0;
}
static int gpio_stellaris_init(const struct device *dev)
{
const struct gpio_stellaris_config *cfg = dev->config;
cfg->config_func(dev);
return 0;
}
static int gpio_stellaris_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_stellaris_runtime *context = dev->data;
gpio_manage_callback(&context->cb, callback, set);
return 0;
}
static const struct gpio_driver_api gpio_stellaris_driver_api = {
.pin_configure = gpio_stellaris_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_stellaris_get_config,
#endif
.port_get_raw = gpio_stellaris_port_get_raw,
.port_set_masked_raw = gpio_stellaris_port_set_masked_raw,
.port_set_bits_raw = gpio_stellaris_port_set_bits_raw,
.port_clear_bits_raw = gpio_stellaris_port_clear_bits_raw,
.port_toggle_bits = gpio_stellaris_port_toggle_bits,
.pin_interrupt_configure = gpio_stellaris_pin_interrupt_configure,
.manage_callback = gpio_stellaris_manage_callback,
};
#define STELLARIS_GPIO_DEVICE(n) \
static void port_## n ##_stellaris_config_func(const struct device *dev); \
\
static struct gpio_stellaris_runtime port_## n ##_stellaris_runtime; \
\
static const struct gpio_stellaris_config gpio_stellaris_port_## n ##_config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = DT_INST_REG_ADDR(n), \
.port_map = BIT_MASK(DT_INST_PROP(n, ngpios)), \
.config_func = port_## n ##_stellaris_config_func, \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
gpio_stellaris_init, \
NULL, \
&port_## n ##_stellaris_runtime, \
&gpio_stellaris_port_## n ##_config, \
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_stellaris_driver_api); \
\
static void port_## n ##_stellaris_config_func(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
gpio_stellaris_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(STELLARIS_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_stellaris.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,231 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_rgpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <fsl_common.h>
#include <fsl_rgpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_pin_gaps {
uint8_t start;
uint8_t len;
};
/* Required by DEVICE_MMIO_NAMED_* macros */
#define DEV_CFG(_dev) \
((const struct mcux_rgpio_config *)(_dev)->config)
#define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
struct mcux_rgpio_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
DEVICE_MMIO_NAMED_ROM(reg_base);
const struct pinctrl_soc_pinmux *pin_muxes;
const struct gpio_pin_gaps *pin_gaps;
uint8_t mux_count;
uint8_t gap_count;
};
struct mcux_rgpio_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data general;
DEVICE_MMIO_NAMED_RAM(reg_base);
/* port ISR callback routine address */
sys_slist_t callbacks;
};
static int mcux_rgpio_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
const struct mcux_rgpio_config *config = dev->config;
struct pinctrl_soc_pin pin_cfg;
int cfg_idx = pin, i;
/* Some SOCs have non-contiguous gpio pin layouts, account for this */
for (i = 0; i < config->gap_count; i++) {
if (pin >= config->pin_gaps[i].start) {
if (pin < (config->pin_gaps[i].start +
config->pin_gaps[i].len)) {
/* Pin is not connected to a mux */
return -ENOTSUP;
}
cfg_idx -= config->pin_gaps[i].len;
}
}
/* Init pin configuration struct, and use pinctrl api to apply settings */
if (cfg_idx >= config->mux_count) {
/* Pin is not connected to a mux */
return -ENOTSUP;
}
/* Set appropriate bits in pin configuration register */
volatile uint32_t *gpio_cfg_reg = (volatile uint32_t *)
((size_t)config->pin_muxes[cfg_idx].config_register);
uint32_t reg = *gpio_cfg_reg;
#if defined(CONFIG_SOC_SERIES_IMXRT118X)
/* PUE/PDRV types have the same ODE bit */
if ((flags & GPIO_SINGLE_ENDED)) {
/* Set ODE bit */
reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
} else {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
}
if (config->pin_muxes[pin].pue_mux) {
if (flags & GPIO_PULL_UP) {
reg |= (IOMUXC_SW_PAD_CTL_PAD_PUS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK);
} else if (flags & GPIO_PULL_DOWN) {
reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
} else {
/* Set pin to highz */
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
}
} else {
/* PDRV type register layout */
if (flags & GPIO_PULL_UP) {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
} else if (flags & GPIO_PULL_DOWN) {
reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
} else {
/* Set pin to no pull */
reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
}
}
#else
/* TODO: Default flags, work for i.MX 9352 */
if ((flags & GPIO_SINGLE_ENDED) != 0) {
/* Set ODE bit */
reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
} else {
reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
}
if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
/* i.MX93 has no pull enable bit */
if (((flags & GPIO_PULL_UP) != 0)) {
reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT);
} else {
reg |= (0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT);
reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
}
} else {
/* Set pin to highz */
reg &= ~((0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |
(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT));
}
#endif
memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg));
/* cfg register will be set by pinctrl_configure_pins */
pin_cfg.pin_ctrl_flags = reg;
pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) {
RGPIO_WritePinOutput(base, pin, 1);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
RGPIO_WritePinOutput(base, pin, 0);
}
WRITE_BIT(base->PDDR, pin, flags & GPIO_OUTPUT);
return 0;
}
static int mcux_rgpio_port_get_raw(const struct device *dev, uint32_t *value)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
*value = base->PDIR;
return 0;
}
static int mcux_rgpio_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
base->PDOR = (base->PDOR & ~mask) | (mask & value);
return 0;
}
static int mcux_rgpio_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
RGPIO_PortSet(base, mask);
return 0;
}
static int mcux_rgpio_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
RGPIO_PortClear(base, mask);
return 0;
}
static int mcux_rgpio_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
RGPIO_PortToggle(base, mask);
return 0;
}
static int mcux_rgpio_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
unsigned int key;
uint8_t irqs, irqc;
irqs = 0; /* only irq0 is used for irq */
if (mode == GPIO_INT_MODE_DISABLED) {
irqc = kRGPIO_InterruptOrDMADisabled;
} else if ((mode == GPIO_INT_MODE_EDGE) &&
(trig == GPIO_INT_TRIG_LOW)) {
irqc = kRGPIO_InterruptFallingEdge;
} else if ((mode == GPIO_INT_MODE_EDGE) &&
(trig == GPIO_INT_TRIG_HIGH)) {
irqc = kRGPIO_InterruptRisingEdge;
} else if ((mode == GPIO_INT_MODE_EDGE) &&
(trig == GPIO_INT_TRIG_BOTH)) {
irqc = kRGPIO_InterruptEitherEdge;
} else if ((mode == GPIO_INT_MODE_LEVEL) &&
(trig == GPIO_INT_TRIG_LOW)) {
irqc = kRGPIO_InterruptLogicZero;
} else if ((mode == GPIO_INT_MODE_LEVEL) &&
(trig == GPIO_INT_TRIG_HIGH)) {
irqc = kRGPIO_InterruptLogicOne;
} else {
return -EINVAL; /* should never end up here */
}
key = irq_lock();
RGPIO_SetPinInterruptConfig(base, pin, irqs, irqc);
irq_unlock(key);
return 0;
}
static int mcux_rgpio_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct mcux_rgpio_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void mcux_rgpio_port_isr(const struct device *dev)
{
RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
struct mcux_rgpio_data *data = dev->data;
uint32_t int_flags;
int_flags = base->ISFR[0]; /* Notice: only irq0 is used for now */
base->ISFR[0] = int_flags;
gpio_fire_callbacks(&data->callbacks, dev, int_flags);
}
static const struct gpio_driver_api mcux_rgpio_driver_api = {
.pin_configure = mcux_rgpio_configure,
.port_get_raw = mcux_rgpio_port_get_raw,
.port_set_masked_raw = mcux_rgpio_port_set_masked_raw,
.port_set_bits_raw = mcux_rgpio_port_set_bits_raw,
.port_clear_bits_raw = mcux_rgpio_port_clear_bits_raw,
.port_toggle_bits = mcux_rgpio_port_toggle_bits,
.pin_interrupt_configure = mcux_rgpio_pin_interrupt_configure,
.manage_callback = mcux_rgpio_manage_callback,
};
/* These macros will declare an array of pinctrl_soc_pinmux types */
#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
#define MCUX_RGPIO_PIN_DECLARE(n) \
const struct pinctrl_soc_pinmux mcux_rgpio_pinmux_##n[] = { \
DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
}; \
const uint8_t mcux_rgpio_pin_gaps_##n[] = \
DT_INST_PROP_OR(n, gpio_reserved_ranges, {});
#define MCUX_RGPIO_PIN_INIT(n) \
.pin_muxes = mcux_rgpio_pinmux_##n, \
.pin_gaps = (const struct gpio_pin_gaps *)mcux_rgpio_pin_gaps_##n, \
.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux), \
.gap_count = (ARRAY_SIZE(mcux_rgpio_pin_gaps_##n) / 2)
#define MCUX_RGPIO_IRQ_INIT(n, i) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
DT_INST_IRQ_BY_IDX(n, i, priority), \
mcux_rgpio_port_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
} while (false)
#define MCUX_RGPIO_INIT(n) \
MCUX_RGPIO_PIN_DECLARE(n) \
static int mcux_rgpio_##n##_init(const struct device *dev); \
\
static const struct mcux_rgpio_config mcux_rgpio_##n##_config = {\
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
}, \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
MCUX_RGPIO_PIN_INIT(n) \
}; \
\
static struct mcux_rgpio_data mcux_rgpio_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, \
mcux_rgpio_##n##_init, \
NULL, \
&mcux_rgpio_##n##_data, \
&mcux_rgpio_##n##_config, \
POST_KERNEL, \
CONFIG_GPIO_INIT_PRIORITY, \
&mcux_rgpio_driver_api); \
\
static int mcux_rgpio_##n##_init(const struct device *dev) \
{ \
DEVICE_MMIO_NAMED_MAP(dev, reg_base, \
K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
(MCUX_RGPIO_IRQ_INIT(n, 0);)) \
\
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
(MCUX_RGPIO_IRQ_INIT(n, 1);)) \
\
return 0; \
}
DT_INST_FOREACH_STATUS_OKAY(MCUX_RGPIO_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_mcux_rgpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,997 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_gpio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/sys_io.h>
#include <soc.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define XEC_GPIO_EDGE_DLY_COUNT 4
#define GPIO_IN_BASE(config) \
((__IO uint32_t *)(GPIO_PARIN_BASE + (config->port_num << 2)))
#define GPIO_OUT_BASE(config) \
((__IO uint32_t *)(GPIO_PAROUT_BASE + (config->port_num << 2)))
static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
(MCHP_GPIO_PORT_A_BITMAP),
(MCHP_GPIO_PORT_B_BITMAP),
(MCHP_GPIO_PORT_C_BITMAP),
(MCHP_GPIO_PORT_D_BITMAP),
(MCHP_GPIO_PORT_E_BITMAP),
(MCHP_GPIO_PORT_F_BITMAP)
};
struct gpio_xec_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* port ISR callback routine address */
sys_slist_t callbacks;
};
struct gpio_xec_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
__IO uint32_t *pcr1_base;
uint8_t girq_id;
uint32_t port_num;
uint32_t flags;
};
/*
* notes: The GPIO parallel output bits are read-only until the
* Alternate-Output-Disable (AOD) bit is set in the pin's control
* register. To preload a parallel output value to prevent certain
* classes of glitching for output pins we must:
* Set GPIO control AOD=1 with the pin direction set to input.
* Program the new pin value in the respective GPIO parallel output
* register.
* Program other GPIO control bits except direction.
* Last step set the GPIO control register direction bit to output.
*/
static int gpio_xec_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_xec_config *config = dev->config;
__IO uint32_t *current_pcr1;
uint32_t pcr1 = 0U;
uint32_t mask = 0U;
/* Validate pin number range in terms of current port */
if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
return -EINVAL;
}
/* Don't support "open source" mode */
if (((flags & GPIO_SINGLE_ENDED) != 0U) &&
((flags & GPIO_LINE_OPEN_DRAIN) == 0U)) {
return -ENOTSUP;
}
/* The flags contain options that require touching registers in the
* PCRs for a given GPIO. There are no GPIO modules in Microchip SOCs!
* Keep direction as input until last.
* Clear input pad disable allowing input pad to operate.
* Clear Power gate to allow pads to operate.
*/
mask |= MCHP_GPIO_CTRL_DIR_MASK;
mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK;
mask |= MCHP_GPIO_CTRL_PWRG_MASK;
mask |= MCHP_GPIO_CTRL_AOD_MASK;
current_pcr1 = config->pcr1_base + pin;
if (flags == GPIO_DISCONNECTED) {
pcr1 |= MCHP_GPIO_CTRL_PWRG_OFF;
*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
return 0;
}
pcr1 = MCHP_GPIO_CTRL_PWRG_VTR_IO;
/* Always enable input pad */
if (*current_pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)) {
*current_pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
}
/* Figure out the pullup/pulldown configuration and keep it in the
* pcr1 variable
*/
mask |= MCHP_GPIO_CTRL_PUD_MASK;
if ((flags & GPIO_PULL_UP) != 0U) {
/* Enable the pull and select the pullup resistor. */
pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
} else if ((flags & GPIO_PULL_DOWN) != 0U) {
/* Enable the pull and select the pulldown resistor */
pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
}
/* Push-pull or open drain */
mask |= MCHP_GPIO_CTRL_BUFT_MASK;
if ((flags & GPIO_OPEN_DRAIN) != 0U) {
/* Open drain */
pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
} else {
/* Push-pull */
pcr1 |= MCHP_GPIO_CTRL_BUFT_PUSHPULL;
}
if ((flags & GPIO_OUTPUT) != 0U) {
mask |= MCHP_GPIO_CTRL_OUTV_HI;
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
pcr1 |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
pcr1 &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else { /* Copy current input state to output state */
if ((*current_pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) ==
MCHP_GPIO_CTRL_PWRG_OFF) {
*current_pcr1 = (*current_pcr1 &
~MCHP_GPIO_CTRL_PWRG_MASK) |
MCHP_GPIO_CTRL_PWRG_VTR_IO;
}
if (*current_pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
pcr1 |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
} else {
pcr1 &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
}
}
pcr1 |= MCHP_GPIO_CTRL_DIR_OUTPUT;
}
*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
/* Control output bit becomes ready only and parallel output r/w */
*current_pcr1 = *current_pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS);
return 0;
}
static int gpio_xec_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_xec_config *config = dev->config;
__IO uint32_t *current_pcr1;
uint32_t pcr1 = 0U;
uint32_t mask = 0U;
uint32_t gpio_interrupt = 0U;
/* Validate pin number range in terms of current port */
if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
return -EINVAL;
}
/* Check if GPIO port supports interrupts */
if ((mode != GPIO_INT_MODE_DISABLED) &&
((config->flags & GPIO_INT_ENABLE) == 0U)) {
return -ENOTSUP;
}
/* Disable interrupt in the EC aggregator */
MCHP_GIRQ_ENCLR(config->girq_id) = BIT(pin);
/* Assemble mask for level/edge triggered interrupts */
mask |= MCHP_GPIO_CTRL_IDET_MASK;
if (mode == GPIO_INT_MODE_DISABLED) {
/* Explicitly disable interrupts, otherwise the configuration
* results in level triggered/low interrupts
*/
pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
} else {
if (mode == GPIO_INT_MODE_LEVEL) {
/* Enable level interrupts */
if (trig == GPIO_INT_TRIG_HIGH) {
gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_HI;
} else {
gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_LO;
}
} else {
/* Enable edge interrupts */
switch (trig) {
case GPIO_INT_TRIG_LOW:
gpio_interrupt = MCHP_GPIO_CTRL_IDET_FEDGE;
break;
case GPIO_INT_TRIG_HIGH:
gpio_interrupt = MCHP_GPIO_CTRL_IDET_REDGE;
break;
case GPIO_INT_TRIG_BOTH:
gpio_interrupt = MCHP_GPIO_CTRL_IDET_BEDGE;
break;
default:
return -EINVAL;
}
}
pcr1 |= gpio_interrupt;
}
/* Now write contents of pcr1 variable to the PCR1 register that
* corresponds to the GPIO being configured
*/
current_pcr1 = config->pcr1_base + pin;
*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
/* delay for HW to synchronize after it ungates its clock */
for (int i = 0; i < XEC_GPIO_EDGE_DLY_COUNT; i++) {
(void)*current_pcr1;
}
if (mode != GPIO_INT_MODE_DISABLED) {
/* We enable the interrupts in the EC aggregator so that the
* result can be forwarded to the ARM NVIC
*/
MCHP_GIRQ_SRC_CLR(config->girq_id, pin);
MCHP_GIRQ_ENSET(config->girq_id) = BIT(pin);
}
return 0;
}
static int gpio_xec_port_set_masked_raw(const struct device *dev,
uint32_t mask,
uint32_t value)
{
const struct gpio_xec_config *config = dev->config;
/* GPIO output registers are used for writing */
__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
*gpio_base = (*gpio_base & ~mask) | (mask & value);
return 0;
}
static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
const struct gpio_xec_config *config = dev->config;
/* GPIO output registers are used for writing */
__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
*gpio_base |= mask;
return 0;
}
static int gpio_xec_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_xec_config *config = dev->config;
/* GPIO output registers are used for writing */
__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
*gpio_base &= ~mask;
return 0;
}
static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)
{
const struct gpio_xec_config *config = dev->config;
/* GPIO output registers are used for writing */
__IO uint32_t *gpio_base = GPIO_OUT_BASE(config);
*gpio_base ^= mask;
return 0;
}
static int gpio_xec_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_xec_config *config = dev->config;
/* GPIO input registers are used for reading */
__IO uint32_t *gpio_base = GPIO_IN_BASE(config);
*value = *gpio_base;
return 0;
}
static int gpio_xec_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_xec_data *data = dev->data;
gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
static void gpio_gpio_xec_port_isr(const struct device *dev)
{
const struct gpio_xec_config *config = dev->config;
struct gpio_xec_data *data = dev->data;
uint32_t girq_result;
/* Figure out which interrupts have been triggered from the EC
* aggregator result register
*/
girq_result = MCHP_GIRQ_RESULT(config->girq_id);
/* Clear source register in aggregator before firing callbacks */
REG32(MCHP_GIRQ_SRC_ADDR(config->girq_id)) = girq_result;
gpio_fire_callbacks(&data->callbacks, dev, girq_result);
}
static const struct gpio_driver_api gpio_xec_driver_api = {
.pin_configure = gpio_xec_configure,
.port_get_raw = gpio_xec_port_get_raw,
.port_set_masked_raw = gpio_xec_port_set_masked_raw,
.port_set_bits_raw = gpio_xec_port_set_bits_raw,
.port_clear_bits_raw = gpio_xec_port_clear_bits_raw,
.port_toggle_bits = gpio_xec_port_toggle_bits,
.pin_interrupt_configure = gpio_xec_pin_interrupt_configure,
.manage_callback = gpio_xec_manage_callback,
};
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_000_036), okay)
static int gpio_xec_port000_036_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port000_036_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_000_036)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_000_036)),
.port_num = MCHP_GPIO_000_036,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq)
.girq_id = MCHP_GIRQ11_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port000_036_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_000_036),
gpio_xec_port000_036_init,
NULL,
&gpio_xec_port000_036_data, &gpio_xec_port000_036_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port000_036_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_000_036), irq),
DT_IRQ(DT_NODELABEL(gpio_000_036), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_000_036)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_000_036), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_000_036), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_040_076), okay)
static int gpio_xec_port040_076_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port040_076_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_040_076)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_040_076)),
.port_num = MCHP_GPIO_040_076,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_040_076), irq)
.girq_id = MCHP_GIRQ10_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port040_076_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_040_076),
gpio_xec_port040_076_init,
NULL,
&gpio_xec_port040_076_data, &gpio_xec_port040_076_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port040_076_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_040_076), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_040_076), irq),
DT_IRQ(DT_NODELABEL(gpio_040_076), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_040_076)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_040_076), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_040_076), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_100_136), okay)
static int gpio_xec_port100_136_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port100_136_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_100_136)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_100_136)),
.port_num = MCHP_GPIO_100_136,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_100_136), irq)
.girq_id = MCHP_GIRQ09_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port100_136_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_100_136),
gpio_xec_port100_136_init,
NULL,
&gpio_xec_port100_136_data, &gpio_xec_port100_136_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port100_136_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_100_136), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_100_136), irq),
DT_IRQ(DT_NODELABEL(gpio_100_136), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_100_136)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_100_136), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_100_136), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_140_176), okay)
static int gpio_xec_port140_176_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port140_176_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_140_176)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_140_176)),
.port_num = MCHP_GPIO_140_176,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_140_176), irq)
.girq_id = MCHP_GIRQ08_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port140_176_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_140_176),
gpio_xec_port140_176_init,
NULL,
&gpio_xec_port140_176_data, &gpio_xec_port140_176_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port140_176_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_140_176), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_140_176), irq),
DT_IRQ(DT_NODELABEL(gpio_140_176), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_140_176)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_140_176), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_140_176), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_200_236), okay)
static int gpio_xec_port200_236_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port200_236_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_200_236)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_200_236)),
.port_num = MCHP_GPIO_200_236,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_200_236), irq)
.girq_id = MCHP_GIRQ12_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port200_236_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_200_236),
gpio_xec_port200_236_init,
NULL,
&gpio_xec_port200_236_data, &gpio_xec_port200_236_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port200_236_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_200_236), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_200_236), irq),
DT_IRQ(DT_NODELABEL(gpio_200_236), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_200_236)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_200_236), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_200_236), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_240_276), okay)
static int gpio_xec_port240_276_init(const struct device *dev);
static const struct gpio_xec_config gpio_xec_port240_276_config = {
.common = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(
DT_NODELABEL(gpio_240_276)),
},
.pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_240_276)),
.port_num = MCHP_GPIO_240_276,
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_240_276), irq)
.girq_id = MCHP_GIRQ26_ID,
.flags = GPIO_INT_ENABLE,
#else
.flags = 0,
#endif
};
static struct gpio_xec_data gpio_xec_port240_276_data;
DEVICE_DT_DEFINE(DT_NODELABEL(gpio_240_276),
gpio_xec_port240_276_init,
NULL,
&gpio_xec_port240_276_data, &gpio_xec_port240_276_config,
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
&gpio_xec_driver_api);
static int gpio_xec_port240_276_init(const struct device *dev)
{
#if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_240_276), irq)
const struct gpio_xec_config *config = dev->config;
/* Turn on the block enable in the EC aggregator */
MCHP_GIRQ_BLK_SETEN(config->girq_id);
IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_240_276), irq),
DT_IRQ(DT_NODELABEL(gpio_240_276), priority),
gpio_gpio_xec_port_isr,
DEVICE_DT_GET(DT_NODELABEL(gpio_240_276)), 0U);
irq_enable(DT_IRQ(DT_NODELABEL(gpio_240_276), irq));
#endif
return 0;
}
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_240_276), okay) */
``` | /content/code_sandbox/drivers/gpio/gpio_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,268 |
```c
/*
*
*/
/**
* @file
* @brief GPIO driver for the LMP90xxx AFE.
*/
#define DT_DRV_COMPAT ti_lmp90xxx_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_lmp90xxx);
#include <zephyr/drivers/adc/lmp90xxx.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
struct gpio_lmp90xxx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
const struct device *parent;
};
struct gpio_lmp90xxx_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
};
static int gpio_lmp90xxx_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_lmp90xxx_config *config = dev->config;
int err = 0;
if (pin > LMP90XXX_GPIO_MAX) {
return -EINVAL;
}
if ((flags & GPIO_SINGLE_ENDED) != 0) {
return -ENOTSUP;
}
if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if (flags & GPIO_INT_ENABLE) {
/* LMP90xxx GPIOs do not support interrupts */
return -ENOTSUP;
}
switch (flags & GPIO_DIR_MASK) {
case GPIO_INPUT:
err = lmp90xxx_gpio_set_input(config->parent, pin);
break;
case GPIO_OUTPUT:
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
err = lmp90xxx_gpio_set_pin_value(config->parent, pin,
true);
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
err = lmp90xxx_gpio_set_pin_value(config->parent, pin,
false);
}
if (err) {
return err;
}
err = lmp90xxx_gpio_set_output(config->parent, pin);
break;
default:
return -ENOTSUP;
}
return err;
}
static int gpio_lmp90xxx_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_lmp90xxx_config *config = dev->config;
return lmp90xxx_gpio_port_get_raw(config->parent, value);
}
static int gpio_lmp90xxx_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_lmp90xxx_config *config = dev->config;
return lmp90xxx_gpio_port_set_masked_raw(config->parent, mask, value);
}
static int gpio_lmp90xxx_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_lmp90xxx_config *config = dev->config;
return lmp90xxx_gpio_port_set_bits_raw(config->parent, pins);
}
static int gpio_lmp90xxx_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_lmp90xxx_config *config = dev->config;
return lmp90xxx_gpio_port_clear_bits_raw(config->parent, pins);
}
static int gpio_lmp90xxx_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_lmp90xxx_config *config = dev->config;
return lmp90xxx_gpio_port_toggle_bits(config->parent, pins);
}
static int gpio_lmp90xxx_init(const struct device *dev)
{
const struct gpio_lmp90xxx_config *config = dev->config;
if (!device_is_ready(config->parent)) {
LOG_ERR("parent LMP90xxx device '%s' not ready",
config->parent->name);
return -EINVAL;
}
return 0;
}
static const struct gpio_driver_api gpio_lmp90xxx_api = {
.pin_configure = gpio_lmp90xxx_config,
.port_set_masked_raw = gpio_lmp90xxx_port_set_masked_raw,
.port_set_bits_raw = gpio_lmp90xxx_port_set_bits_raw,
.port_clear_bits_raw = gpio_lmp90xxx_port_clear_bits_raw,
.port_toggle_bits = gpio_lmp90xxx_port_toggle_bits,
.port_get_raw = gpio_lmp90xxx_port_get_raw,
};
BUILD_ASSERT(CONFIG_GPIO_LMP90XXX_INIT_PRIORITY >
CONFIG_ADC_INIT_PRIORITY,
"LMP90xxx GPIO driver must be initialized after LMP90xxx ADC "
"driver");
#define GPIO_LMP90XXX_DEVICE(id) \
static const struct gpio_lmp90xxx_config gpio_lmp90xxx_##id##_cfg = {\
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(id) \
}, \
.parent = DEVICE_DT_GET(DT_INST_BUS(id)), \
}; \
\
static struct gpio_lmp90xxx_data gpio_lmp90xxx_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, \
gpio_lmp90xxx_init, \
NULL, \
&gpio_lmp90xxx_##id##_data, \
&gpio_lmp90xxx_##id##_cfg, POST_KERNEL, \
CONFIG_GPIO_LMP90XXX_INIT_PRIORITY, \
&gpio_lmp90xxx_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_LMP90XXX_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_lmp90xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,183 |
```c
/*
*
*
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/types.h>
#include <zephyr/sys/util.h>
#include <string.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <chip_chipregs.h>
#include <soc_common.h>
LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
#define DT_DRV_COMPAT ite_it8xxx2_gpio
/*
* Structure gpio_ite_cfg is about the setting of gpio
* this config will be used at initial time
*/
struct gpio_ite_cfg {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* gpio port data register (bit mapping to pin) */
uintptr_t reg_gpdr;
/* gpio port control register (byte mapping to pin) */
uintptr_t reg_gpcr;
/* gpio port data mirror register (bit mapping to pin) */
uintptr_t reg_gpdmr;
/* gpio port output type register (bit mapping to pin) */
uintptr_t reg_gpotr;
/* Index in gpio_1p8v for voltage level control register element. */
uint8_t index;
/* gpio's irq */
uint8_t gpio_irq[8];
};
/* Structure gpio_ite_data is about callback function */
struct gpio_ite_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
};
/* dev macros for GPIO */
#define DEV_GPIO_DATA(dev) \
((struct gpio_ite_data *)(dev)->data)
#define DEV_GPIO_CFG(dev) \
((const struct gpio_ite_cfg *)(dev)->config)
/**
* Convert wake-up controller (WUC) group to the corresponding wake-up edge
* sense register (WUESR). Return pointer to the register.
*
* @param grp WUC group.
*
* @return Pointer to corresponding WUESR register.
*/
static volatile uint8_t *wuesr(uint8_t grp)
{
/*
* From WUESR1-WUESR4, the address increases by ones. From WUESR5 on
* the address increases by fours.
*/
return (grp <= 4) ?
(volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) :
(volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5));
}
/**
* Convert wake-up controller (WUC) group to the corresponding wake-up edge
* mode register (WUEMR). Return pointer to the register.
*
* @param grp WUC group.
*
* @return Pointer to corresponding WUEMR register.
*/
static volatile uint8_t *wuemr(uint8_t grp)
{
/*
* From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on
* the address increases by fours.
*/
return (grp <= 4) ?
(volatile uint8_t *)(IT8XXX2_WUC_WUEMR1 + grp-1) :
(volatile uint8_t *)(IT8XXX2_WUC_WUEMR5 + 4*(grp-5));
}
/**
* Convert wake-up controller (WUC) group to the corresponding wake-up both edge
* mode register (WUBEMR). Return pointer to the register.
*
* @param grp WUC group.
*
* @return Pointer to corresponding WUBEMR register.
*/
static volatile uint8_t *wubemr(uint8_t grp)
{
/*
* From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
* the address increases by fours.
*/
return (grp <= 4) ?
(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR1 + grp-1) :
(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR5 + 4*(grp-5));
}
/*
* Array to store the corresponding GPIO WUC group and mask
* for each WUC interrupt. This allows GPIO interrupts coming in through WUC
* to easily identify which pin caused the interrupt.
*/
static const struct {
uint8_t gpio_mask;
uint8_t wuc_group;
uint8_t wuc_mask;
} gpio_irqs[] = {
/* irq gpio_mask, wuc_group, wuc_mask */
[IT8XXX2_IRQ_WU20] = {BIT(0), 2, BIT(0)},
[IT8XXX2_IRQ_WU21] = {BIT(1), 2, BIT(1)},
[IT8XXX2_IRQ_WU22] = {BIT(4), 2, BIT(2)},
[IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
[IT8XXX2_IRQ_WU24] = {BIT(2), 2, BIT(4)},
[IT8XXX2_IRQ_WU40] = {BIT(5), 4, BIT(0)},
[IT8XXX2_IRQ_WU45] = {BIT(6), 4, BIT(5)},
[IT8XXX2_IRQ_WU46] = {BIT(7), 4, BIT(6)},
[IT8XXX2_IRQ_WU50] = {BIT(0), 5, BIT(0)},
[IT8XXX2_IRQ_WU51] = {BIT(1), 5, BIT(1)},
[IT8XXX2_IRQ_WU52] = {BIT(2), 5, BIT(2)},
[IT8XXX2_IRQ_WU53] = {BIT(3), 5, BIT(3)},
[IT8XXX2_IRQ_WU54] = {BIT(4), 5, BIT(4)},
[IT8XXX2_IRQ_WU55] = {BIT(5), 5, BIT(5)},
[IT8XXX2_IRQ_WU56] = {BIT(6), 5, BIT(6)},
[IT8XXX2_IRQ_WU57] = {BIT(7), 5, BIT(7)},
[IT8XXX2_IRQ_WU60] = {BIT(0), 6, BIT(0)},
[IT8XXX2_IRQ_WU61] = {BIT(1), 6, BIT(1)},
[IT8XXX2_IRQ_WU62] = {BIT(2), 6, BIT(2)},
[IT8XXX2_IRQ_WU63] = {BIT(3), 6, BIT(3)},
[IT8XXX2_IRQ_WU64] = {BIT(4), 6, BIT(4)},
[IT8XXX2_IRQ_WU65] = {BIT(5), 6, BIT(5)},
[IT8XXX2_IRQ_WU66] = {BIT(6), 6, BIT(6)},
[IT8XXX2_IRQ_WU67] = {BIT(7), 6, BIT(7)},
[IT8XXX2_IRQ_WU70] = {BIT(0), 7, BIT(0)},
[IT8XXX2_IRQ_WU71] = {BIT(1), 7, BIT(1)},
[IT8XXX2_IRQ_WU72] = {BIT(2), 7, BIT(2)},
[IT8XXX2_IRQ_WU73] = {BIT(3), 7, BIT(3)},
[IT8XXX2_IRQ_WU74] = {BIT(4), 7, BIT(4)},
[IT8XXX2_IRQ_WU75] = {BIT(5), 7, BIT(5)},
[IT8XXX2_IRQ_WU76] = {BIT(6), 7, BIT(6)},
[IT8XXX2_IRQ_WU77] = {BIT(7), 7, BIT(7)},
[IT8XXX2_IRQ_WU80] = {BIT(3), 8, BIT(0)},
[IT8XXX2_IRQ_WU81] = {BIT(4), 8, BIT(1)},
[IT8XXX2_IRQ_WU82] = {BIT(5), 8, BIT(2)},
[IT8XXX2_IRQ_WU83] = {BIT(6), 8, BIT(3)},
[IT8XXX2_IRQ_WU84] = {BIT(2), 8, BIT(4)},
[IT8XXX2_IRQ_WU85] = {BIT(0), 8, BIT(5)},
[IT8XXX2_IRQ_WU86] = {BIT(7), 8, BIT(6)},
[IT8XXX2_IRQ_WU87] = {BIT(7), 8, BIT(7)},
[IT8XXX2_IRQ_WU88] = {BIT(4), 9, BIT(0)},
[IT8XXX2_IRQ_WU89] = {BIT(5), 9, BIT(1)},
[IT8XXX2_IRQ_WU90] = {BIT(6), 9, BIT(2)},
[IT8XXX2_IRQ_WU91] = {BIT(0), 9, BIT(3)},
[IT8XXX2_IRQ_WU92] = {BIT(1), 9, BIT(4)},
[IT8XXX2_IRQ_WU93] = {BIT(2), 9, BIT(5)},
[IT8XXX2_IRQ_WU94] = {BIT(4), 9, BIT(6)},
[IT8XXX2_IRQ_WU95] = {BIT(2), 9, BIT(7)},
[IT8XXX2_IRQ_WU96] = {BIT(0), 10, BIT(0)},
[IT8XXX2_IRQ_WU97] = {BIT(1), 10, BIT(1)},
[IT8XXX2_IRQ_WU98] = {BIT(2), 10, BIT(2)},
[IT8XXX2_IRQ_WU99] = {BIT(3), 10, BIT(3)},
[IT8XXX2_IRQ_WU100] = {BIT(7), 10, BIT(4)},
[IT8XXX2_IRQ_WU101] = {BIT(0), 10, BIT(5)},
[IT8XXX2_IRQ_WU102] = {BIT(1), 10, BIT(6)},
[IT8XXX2_IRQ_WU103] = {BIT(3), 10, BIT(7)},
[IT8XXX2_IRQ_WU104] = {BIT(5), 11, BIT(0)},
[IT8XXX2_IRQ_WU105] = {BIT(6), 11, BIT(1)},
[IT8XXX2_IRQ_WU106] = {BIT(7), 11, BIT(2)},
[IT8XXX2_IRQ_WU107] = {BIT(1), 11, BIT(3)},
[IT8XXX2_IRQ_WU108] = {BIT(3), 11, BIT(4)},
[IT8XXX2_IRQ_WU109] = {BIT(5), 11, BIT(5)},
[IT8XXX2_IRQ_WU110] = {BIT(3), 11, BIT(6)},
[IT8XXX2_IRQ_WU111] = {BIT(4), 11, BIT(7)},
[IT8XXX2_IRQ_WU112] = {BIT(5), 12, BIT(0)},
[IT8XXX2_IRQ_WU113] = {BIT(6), 12, BIT(1)},
[IT8XXX2_IRQ_WU114] = {BIT(4), 12, BIT(2)},
[IT8XXX2_IRQ_WU115] = {BIT(0), 12, BIT(3)},
[IT8XXX2_IRQ_WU116] = {BIT(1), 12, BIT(4)},
[IT8XXX2_IRQ_WU117] = {BIT(2), 12, BIT(5)},
[IT8XXX2_IRQ_WU118] = {BIT(6), 12, BIT(6)},
[IT8XXX2_IRQ_WU119] = {BIT(0), 12, BIT(7)},
[IT8XXX2_IRQ_WU120] = {BIT(1), 13, BIT(0)},
[IT8XXX2_IRQ_WU121] = {BIT(2), 13, BIT(1)},
[IT8XXX2_IRQ_WU122] = {BIT(3), 13, BIT(2)},
[IT8XXX2_IRQ_WU123] = {BIT(3), 13, BIT(3)},
[IT8XXX2_IRQ_WU124] = {BIT(4), 13, BIT(4)},
[IT8XXX2_IRQ_WU125] = {BIT(5), 13, BIT(5)},
[IT8XXX2_IRQ_WU126] = {BIT(7), 13, BIT(6)},
[IT8XXX2_IRQ_WU128] = {BIT(0), 14, BIT(0)},
[IT8XXX2_IRQ_WU129] = {BIT(1), 14, BIT(1)},
[IT8XXX2_IRQ_WU130] = {BIT(2), 14, BIT(2)},
[IT8XXX2_IRQ_WU131] = {BIT(3), 14, BIT(3)},
[IT8XXX2_IRQ_WU132] = {BIT(4), 14, BIT(4)},
[IT8XXX2_IRQ_WU133] = {BIT(5), 14, BIT(5)},
[IT8XXX2_IRQ_WU134] = {BIT(6), 14, BIT(6)},
[IT8XXX2_IRQ_WU135] = {BIT(7), 14, BIT(7)},
[IT8XXX2_IRQ_WU136] = {BIT(0), 15, BIT(0)},
[IT8XXX2_IRQ_WU137] = {BIT(1), 15, BIT(1)},
[IT8XXX2_IRQ_WU138] = {BIT(2), 15, BIT(2)},
[IT8XXX2_IRQ_WU139] = {BIT(3), 15, BIT(3)},
[IT8XXX2_IRQ_WU140] = {BIT(4), 15, BIT(4)},
[IT8XXX2_IRQ_WU141] = {BIT(5), 15, BIT(5)},
[IT8XXX2_IRQ_WU142] = {BIT(6), 15, BIT(6)},
[IT8XXX2_IRQ_WU143] = {BIT(7), 15, BIT(7)},
[IT8XXX2_IRQ_WU144] = {BIT(0), 16, BIT(0)},
[IT8XXX2_IRQ_WU145] = {BIT(1), 16, BIT(1)},
[IT8XXX2_IRQ_WU146] = {BIT(2), 16, BIT(2)},
[IT8XXX2_IRQ_WU147] = {BIT(3), 16, BIT(3)},
[IT8XXX2_IRQ_WU148] = {BIT(4), 16, BIT(4)},
[IT8XXX2_IRQ_WU149] = {BIT(5), 16, BIT(5)},
[IT8XXX2_IRQ_WU150] = {BIT(6), 16, BIT(6)},
[IT8XXX2_IRQ_COUNT] = { 0, 0, 0},
};
BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT8XXX2_IRQ_COUNT + 1);
/* 1.8v gpio group a, b, c, d, e, f, g, h, i, j, k, l, and m */
#define GPIO_GROUP_COUNT 13
#define GPIO_GROUP_INDEX(label) \
(uint8_t)(DT_REG_ADDR(DT_NODELABEL(label)) - \
DT_REG_ADDR(DT_NODELABEL(gpioa)))
/* general control registers for selecting 1.8V/3.3V */
static const struct {
uint8_t offset;
uint8_t mask_1p8v;
} gpio_1p8v[GPIO_GROUP_COUNT][8] = {
[GPIO_GROUP_INDEX(gpioa)] = {
[4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(0)},
[5] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(1)},
[6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(5)},
[7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(6)} },
[GPIO_GROUP_INDEX(gpiob)] = {
[3] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(1)},
[4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(0)},
[5] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(7)},
[6] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(6)},
[7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(4)} },
[GPIO_GROUP_INDEX(gpioc)] = {
[0] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(7)},
[1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(5)},
[2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(4)},
[4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(2)},
[6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(3)},
[7] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(3)} },
[GPIO_GROUP_INDEX(gpiod)] = {
[0] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(2)},
[1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(1)},
[2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(0)},
[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(7)},
[4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(6)},
[5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(4)},
[6] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(5)},
[7] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(6)} },
[GPIO_GROUP_INDEX(gpioe)] = {
[0] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(5)},
[1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(6)},
[2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(7)},
[4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(2)},
[5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(3)},
[6] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(4)},
[7] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(3)} },
[GPIO_GROUP_INDEX(gpiof)] = {
[0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(4)},
[1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(5)},
[2] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(2)},
[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(1)},
[4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(0)},
[5] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(7)},
[6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(6)},
[7] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(5)} },
[GPIO_GROUP_INDEX(gpiog)] = {
[0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(2)},
[1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(4)},
[2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(3)},
[6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(3)} },
[GPIO_GROUP_INDEX(gpioh)] = {
[0] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(2)},
[1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(1)},
[2] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(0)},
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(7)},
[6] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(0)} },
[GPIO_GROUP_INDEX(gpioi)] = {
[0] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(3)},
[1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(4)},
[2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(5)},
[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(6)},
[4] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(7)},
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(4)},
[6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(5)},
[7] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(6)} },
[GPIO_GROUP_INDEX(gpioj)] = {
[0] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(0)},
[1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(1)},
[2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(2)},
[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(3)},
[4] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(0)},
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(1)},
[6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(2)},
[7] = {IT8XXX2_GPIO_GCR33_OFFSET, BIT(2)} },
[GPIO_GROUP_INDEX(gpiok)] = {
[0] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(0)},
[1] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(1)},
[2] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(2)},
[3] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(3)},
[4] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(4)},
[5] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(5)},
[6] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(6)},
[7] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(7)} },
[GPIO_GROUP_INDEX(gpiol)] = {
[0] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(0)},
[1] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(1)},
[2] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(2)},
[3] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(3)},
[4] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(4)},
[5] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(5)},
[6] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(6)},
[7] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(7)} },
/*
* M group's voltage level is according to chip's VCC is connected
* to 1.8V or 3.3V.
*/
[GPIO_GROUP_INDEX(gpiom)] = {
[0] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[1] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[2] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[3] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[4] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[5] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
[6] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)} },
};
/**
* Driver functions
*/
static int gpio_ite_configure(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
volatile uint8_t *reg_1p8v;
volatile uint8_t mask_1p8v;
uint8_t mask = BIT(pin);
__ASSERT(gpio_config->index < GPIO_GROUP_COUNT,
"Invalid GPIO group index");
/* Don't support "open source" mode */
if (((flags & GPIO_SINGLE_ENDED) != 0) &&
((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
return -ENOTSUP;
}
if (flags == GPIO_DISCONNECTED) {
*reg_gpcr = GPCR_PORT_PIN_MODE_TRISTATE;
/*
* Since not all GPIOs can be to configured as tri-state,
* prompt error if pin doesn't support the flag.
*/
if (*reg_gpcr != GPCR_PORT_PIN_MODE_TRISTATE) {
/* Go back to default setting (input) */
*reg_gpcr = GPCR_PORT_PIN_MODE_INPUT;
LOG_ERR("Cannot config GPIO-%c%d as tri-state",
(gpio_config->index + 'A'), pin);
return -ENOTSUP;
}
/*
* The following configuration isn't necessary because the pin
* was configured as disconnected.
*/
return 0;
}
/*
* Select open drain first, so that we don't glitch the signal
* when changing the line to an output.
*/
if (flags & GPIO_OPEN_DRAIN) {
*reg_gpotr |= mask;
} else {
*reg_gpotr &= ~mask;
}
/* 1.8V or 3.3V */
reg_1p8v = &IT8XXX2_GPIO_GCRX(
gpio_1p8v[gpio_config->index][pin].offset);
mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
__ASSERT(!(flags & GPIO_PULL_UP),
"Don't enable internal pullup if 1.8V voltage is used");
*reg_1p8v |= mask_1p8v;
} else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3 ||
volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
*reg_1p8v &= ~mask_1p8v;
} else {
return -EINVAL;
}
}
/* If output, set level before changing type to an output. */
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_OUTPUT_INIT_HIGH) {
*reg_gpdr |= mask;
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
*reg_gpdr &= ~mask;
}
}
/* Set input or output. */
if (flags & GPIO_OUTPUT)
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_OUTPUT) &
~GPCR_PORT_PIN_MODE_INPUT;
else
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
~GPCR_PORT_PIN_MODE_OUTPUT;
/* Handle pullup / pulldown */
if (flags & GPIO_PULL_UP) {
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
~GPCR_PORT_PIN_MODE_PULLDOWN;
} else if (flags & GPIO_PULL_DOWN) {
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
~GPCR_PORT_PIN_MODE_PULLUP;
} else {
/* No pull up/down */
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
GPCR_PORT_PIN_MODE_PULLDOWN);
}
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_ite_get_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
volatile uint8_t *reg_1p8v;
volatile uint8_t mask_1p8v;
uint8_t mask = BIT(pin);
gpio_flags_t flags = 0;
__ASSERT(gpio_config->index < GPIO_GROUP_COUNT,
"Invalid GPIO group index");
/* push-pull or open-drain */
if (*reg_gpotr & mask)
flags |= GPIO_OPEN_DRAIN;
/* 1.8V or 3.3V */
reg_1p8v = &IT8XXX2_GPIO_GCRX(
gpio_1p8v[gpio_config->index][pin].offset);
/*
* Since not all GPIOs support voltage selection, voltage flag
* is only set if voltage selection register is present.
*/
if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
if (*reg_1p8v & mask_1p8v) {
flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
} else {
flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
}
}
/* set input or output. */
if (*reg_gpcr & GPCR_PORT_PIN_MODE_OUTPUT) {
flags |= GPIO_OUTPUT;
/* set level */
if (*reg_gpdr & mask) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
}
if (*reg_gpcr & GPCR_PORT_PIN_MODE_INPUT) {
flags |= GPIO_INPUT;
/* pullup / pulldown */
if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLUP) {
flags |= GPIO_PULL_UP;
}
if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLDOWN) {
flags |= GPIO_PULL_DOWN;
}
}
*out_flags = flags;
return 0;
}
#endif
static int gpio_ite_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
/* Get raw bits of GPIO mirror register */
*value = *reg_gpdmr;
return 0;
}
static int gpio_ite_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
uint8_t out = *reg_gpdr;
*reg_gpdr = ((out & ~mask) | (value & mask));
return 0;
}
static int gpio_ite_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
/* Set raw bits of GPIO data register */
*reg_gpdr |= pins;
return 0;
}
static int gpio_ite_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
/* Clear raw bits of GPIO data register */
*reg_gpdr &= ~pins;
return 0;
}
static int gpio_ite_port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
/* Toggle raw bits of GPIO data register */
*reg_gpdr ^= pins;
return 0;
}
static int gpio_ite_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void gpio_ite_isr(const void *arg)
{
uint8_t irq = ite_intc_get_irq_num();
const struct device *dev = arg;
struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
uint8_t gpio_mask = gpio_irqs[irq].gpio_mask;
if (gpio_irqs[irq].wuc_group) {
/* Clear the WUC status register. */
*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
gpio_fire_callbacks(&data->callbacks, dev, gpio_mask);
}
}
static int gpio_ite_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
uint8_t gpio_irq = gpio_config->gpio_irq[pin];
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
#else
if (mode == GPIO_INT_MODE_DISABLED) {
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
/* Disable GPIO interrupt */
irq_disable(gpio_irq);
return 0;
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
/* Only enable GPIO interrupt */
irq_enable(gpio_irq);
return 0;
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
}
if (mode == GPIO_INT_MODE_LEVEL) {
LOG_ERR("Level trigger mode not supported");
return -ENOTSUP;
}
/* Disable irq before configuring it */
irq_disable(gpio_irq);
if (trig & GPIO_INT_TRIG_BOTH) {
uint8_t wuc_group = gpio_irqs[gpio_irq].wuc_group;
uint8_t wuc_mask = gpio_irqs[gpio_irq].wuc_mask;
/* Set both edges interrupt. */
if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
*(wubemr(wuc_group)) |= wuc_mask;
} else {
*(wubemr(wuc_group)) &= ~wuc_mask;
}
if (trig & GPIO_INT_TRIG_LOW) {
*(wuemr(wuc_group)) |= wuc_mask;
} else {
*(wuemr(wuc_group)) &= ~wuc_mask;
}
/*
* Always write 1 to clear the WUC status register after
* modifying edge mode selection register (WUBEMR and WUEMR).
*/
*(wuesr(wuc_group)) = wuc_mask;
}
/* Enable GPIO interrupt */
irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
irq_enable(gpio_irq);
return 0;
}
static const struct gpio_driver_api gpio_ite_driver_api = {
.pin_configure = gpio_ite_configure,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_ite_get_config,
#endif
.port_get_raw = gpio_ite_port_get_raw,
.port_set_masked_raw = gpio_ite_port_set_masked_raw,
.port_set_bits_raw = gpio_ite_port_set_bits_raw,
.port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
.port_toggle_bits = gpio_ite_port_toggle_bits,
.pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
.manage_callback = gpio_ite_manage_callback,
};
#define GPIO_ITE_DEV_CFG_DATA(inst) \
static struct gpio_ite_data gpio_ite_data_##inst; \
static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
DT_INST_PROP(inst, ngpios)) \
}, \
.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
.index = (uint8_t)(DT_INST_REG_ADDR(inst) - \
DT_REG_ADDR(DT_NODELABEL(gpioa))), \
.gpio_irq[0] = DT_INST_IRQ_BY_IDX(inst, 0, irq), \
.gpio_irq[1] = DT_INST_IRQ_BY_IDX(inst, 1, irq), \
.gpio_irq[2] = DT_INST_IRQ_BY_IDX(inst, 2, irq), \
.gpio_irq[3] = DT_INST_IRQ_BY_IDX(inst, 3, irq), \
.gpio_irq[4] = DT_INST_IRQ_BY_IDX(inst, 4, irq), \
.gpio_irq[5] = DT_INST_IRQ_BY_IDX(inst, 5, irq), \
.gpio_irq[6] = DT_INST_IRQ_BY_IDX(inst, 6, irq), \
.gpio_irq[7] = DT_INST_IRQ_BY_IDX(inst, 7, irq), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
NULL, \
NULL, \
&gpio_ite_data_##inst, \
&gpio_ite_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_ite_driver_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
static int gpio_it8xxx2_init_set(void)
{
if (IS_ENABLED(CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
for (int i = 0; i < 8; i++) {
gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
}
}
if (IS_ENABLED(CONFIG_SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW)) {
const struct device *const gpioh = DEVICE_DT_GET(DT_NODELABEL(gpioh));
gpio_pin_configure(gpioh, 7, GPIO_OUTPUT_LOW);
}
return 0;
}
SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/gpio/gpio_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,092 |
```unknown
config GPIO_RA_IOPORT
bool "Renesas RA GPIO IO port driver"
default y
depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED
help
Enable the Renesas RA GPIO IO port driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.renesas_ra_ioport | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
# CC32XX GPIO configuration options
config GPIO_CC32XX
bool "TI CC32XX GPIO driver"
default y
depends on DT_HAS_TI_CC32XX_GPIO_ENABLED
help
Enable the GPIO driver on TI SimpleLink CC32xx boards
``` | /content/code_sandbox/drivers/gpio/Kconfig.cc32xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
#
# Xilinx Processor System MIO / EMIO GPIO controller driver
# configuration options
#
#
config GPIO_XLNX_PS
bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
default y
depends on DT_HAS_XLNX_PS_GPIO_ENABLED
depends on !QEMU_TARGET
help
Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.xlnx_ps | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
config GPIO_NPM1300
bool "nPM1300 GPIO driver"
default y
depends on DT_HAS_NORDIC_NPM1300_GPIO_ENABLED
select I2C
select MFD
help
Enable the nPM1300 GPIO driver.
config GPIO_NPM1300_INIT_PRIORITY
int "nPM1300 GPIO driver initialization priority"
depends on GPIO_NPM1300
default 85
help
Initialization priority for the nPM1300 GPIO driver. It must be
greater than the I2C controller init priority.
``` | /content/code_sandbox/drivers/gpio/Kconfig.npm1300 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```objective-c
/*
*
*/
/**
* @file Header file for the MCP23Xxx driver.
*/
#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MCP23XXX_H_
#define ZEPHYR_DRIVERS_GPIO_GPIO_MCP23XXX_H_
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#ifdef CONFIG_GPIO_MCP230XX
#include <zephyr/drivers/i2c.h>
#endif /* CONFIG_GPIO_MCP230XX */
#ifdef CONFIG_GPIO_MCP23SXX
#include <zephyr/drivers/spi.h>
#endif /* CONFIG_GPIO_MCP23SXX */
/* Register definitions */
#define REG_IODIR 0x00
#define REG_IPOL 0x01
#define REG_GPINTEN 0x02
#define REG_DEFVAL 0x03
#define REG_INTCON 0x04
#define REG_IOCON 0x05
#define REG_GPPU 0x06
#define REG_INTF 0x07
#define REG_INTCAP 0x08
#define REG_GPIO 0x09
#define REG_OLAT 0x0A
#define REG_IOCON_MIRROR BIT(6)
#define MCP23SXX_ADDR 0x40
#define MCP23SXX_READBIT 0x01
typedef int (*mcp23xxx_read_port_regs)(const struct device *dev, uint8_t reg, uint16_t *buf);
typedef int (*mcp23xxx_write_port_regs)(const struct device *dev, uint8_t reg, uint16_t value);
typedef int (*mcp23xxx_bus_is_ready)(const struct device *dev);
/** Configuration data */
struct mcp23xxx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config config;
/** I2C device */
union {
#ifdef CONFIG_GPIO_MCP230XX
struct i2c_dt_spec i2c;
#endif /* CONFIG_GPIO_MCP230XX */
#ifdef CONFIG_GPIO_MCP23SXX
struct spi_dt_spec spi;
#endif /* CONFIG_GPIO_MCP23SXX */
} bus;
struct gpio_dt_spec gpio_int;
struct gpio_dt_spec gpio_reset;
uint8_t ngpios;
bool is_open_drain;
mcp23xxx_read_port_regs read_fn;
mcp23xxx_write_port_regs write_fn;
mcp23xxx_bus_is_ready bus_fn;
};
/** Runtime driver data */
struct mcp23xxx_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data data;
struct k_sem lock;
sys_slist_t callbacks;
const struct device *dev;
struct gpio_callback int_gpio_cb;
struct k_work work;
uint16_t rising_edge_ints;
uint16_t falling_edge_ints;
struct {
uint16_t iodir;
uint16_t ipol;
uint16_t gpinten;
uint16_t defval;
uint16_t intcon;
uint16_t iocon;
uint16_t gppu;
uint16_t intf;
uint16_t intcap;
uint16_t gpio;
uint16_t olat;
} reg_cache;
};
extern const struct gpio_driver_api gpio_mcp23xxx_api_table;
int gpio_mcp23xxx_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_MCP23XXX_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_mcp23xxx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 690 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_gpio
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <soc/gpio_reg.h>
#include <soc/io_mux_reg.h>
#include <soc/soc.h>
#include <hal/gpio_ll.h>
#include <esp_attr.h>
#include <hal/rtc_io_hal.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
defined(CONFIG_SOC_SERIES_ESP32C3) || \
defined(CONFIG_SOC_SERIES_ESP32C6)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
#ifdef CONFIG_SOC_SERIES_ESP32C2
#define out out.val
#define in in.val
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
/* arch_curr_cpu() is not available for riscv based chips */
#define CPU_ID() 0
#define ISR_HANDLER isr_handler_t
#elif CONFIG_SOC_SERIES_ESP32C3
/* gpio structs in esp32c3 series are different from xtensa ones */
#define out out.data
#define in in.data
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
/* arch_curr_cpu() is not available for riscv based chips */
#define CPU_ID() 0
#define ISR_HANDLER isr_handler_t
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
/* gpio structs in esp32c6 are also different */
#define out out.out_data_orig
#define in in.in_data_next
#define out_w1ts out_w1ts.val
#define out_w1tc out_w1tc.val
/* arch_curr_cpu() is not available for riscv based chips */
#define CPU_ID() 0
#define ISR_HANDLER isr_handler_t
#else
#define CPU_ID() arch_curr_cpu()->id
#define ISR_HANDLER intr_handler_t
#endif
#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0
#endif
struct gpio_esp32_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config drv_cfg;
gpio_dev_t *const gpio_base;
gpio_dev_t *const gpio_dev;
const int gpio_port;
};
struct gpio_esp32_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
sys_slist_t cb;
};
static inline bool rtc_gpio_is_valid_gpio(uint32_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
return (gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
#else
return false;
#endif
}
static inline bool gpio_pin_is_valid(uint32_t pin)
{
return ((BIT(pin) & SOC_GPIO_VALID_GPIO_MASK) != 0);
}
static inline bool gpio_pin_is_output_capable(uint32_t pin)
{
return ((BIT(pin) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0);
}
static int gpio_esp32_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_esp32_config *const cfg = dev->config;
struct gpio_esp32_data *data = dev->data;
uint32_t io_pin = (uint32_t) pin + ((cfg->gpio_port == 1 && pin < 32) ? 32 : 0);
uint32_t key;
int ret = 0;
if (!gpio_pin_is_valid(io_pin)) {
LOG_ERR("Selected IO pin is not valid.");
return -EINVAL;
}
key = irq_lock();
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(io_pin)) {
rtcio_hal_function_select(rtc_io_num_map[io_pin], RTCIO_FUNC_DIGITAL);
}
#endif
if (io_pin >= GPIO_NUM_MAX) {
LOG_ERR("Invalid pin.");
ret = -EINVAL;
goto end;
}
/* Set pin function as GPIO */
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[io_pin], PIN_FUNC_GPIO);
if (flags & GPIO_PULL_UP) {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pullup_en(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
if (rtc_io_desc[rtcio_num].pullup) {
rtcio_hal_pullup_enable(rtcio_num);
} else {
ret = -ENOTSUP;
goto end;
}
#endif
}
} else {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pullup_dis(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
if (rtc_io_desc[rtcio_num].pullup) {
rtcio_hal_pullup_disable(rtcio_num);
}
#else
ret = -ENOTSUP;
goto end;
#endif
}
}
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
gpio_ll_od_enable(cfg->gpio_base, io_pin);
} else {
LOG_ERR("GPIO configuration not supported");
ret = -ENOTSUP;
goto end;
}
} else {
gpio_ll_od_disable(cfg->gpio_base, io_pin);
}
if (flags & GPIO_PULL_DOWN) {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pulldown_en(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
if (rtc_io_desc[rtcio_num].pulldown) {
rtcio_hal_pulldown_enable(rtcio_num);
} else {
ret = -ENOTSUP;
goto end;
}
#endif
}
} else {
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_pulldown_dis(&GPIO, io_pin);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
int rtcio_num = rtc_io_num_map[io_pin];
if (rtc_io_desc[rtcio_num].pulldown) {
rtcio_hal_pulldown_disable(rtcio_num);
}
#else
ret = -ENOTSUP;
goto end;
#endif
}
}
if (flags & GPIO_OUTPUT) {
if (!gpio_pin_is_output_capable(pin)) {
LOG_ERR("GPIO can only be used as input");
ret = -EINVAL;
goto end;
}
/*
* By default, drive strength is set to its maximum value when the pin is set
* to either low or high states. Alternative drive strength is weak-only,
* while any other intermediary combination is considered invalid.
*/
switch (flags & ESP32_GPIO_DS_MASK) {
case ESP32_GPIO_DS_DFLT:
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_set_drive_capability(cfg->gpio_base,
io_pin,
GPIO_DRIVE_CAP_3);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
rtcio_hal_set_drive_capability(rtc_io_num_map[io_pin],
GPIO_DRIVE_CAP_3);
#endif
}
break;
case ESP32_GPIO_DS_ALT:
if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
gpio_ll_set_drive_capability(cfg->gpio_base,
io_pin,
GPIO_DRIVE_CAP_0);
} else {
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
rtcio_hal_set_drive_capability(rtc_io_num_map[io_pin],
GPIO_DRIVE_CAP_0);
#endif
}
break;
default:
ret = -EINVAL;
goto end;
}
gpio_ll_output_enable(&GPIO, io_pin);
esp_rom_gpio_matrix_out(io_pin, SIG_GPIO_OUT_IDX, false, false);
/* Set output pin initial value */
if (flags & GPIO_OUTPUT_INIT_HIGH) {
gpio_ll_set_level(cfg->gpio_base, io_pin, 1);
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_ll_set_level(cfg->gpio_base, io_pin, 0);
}
} else {
gpio_ll_output_disable(&GPIO, io_pin);
}
if (flags & GPIO_INPUT) {
gpio_ll_input_enable(&GPIO, io_pin);
} else {
gpio_ll_input_disable(&GPIO, io_pin);
}
end:
irq_unlock(key);
return ret;
}
static int gpio_esp32_port_get_raw(const struct device *port, uint32_t *value)
{
const struct gpio_esp32_config *const cfg = port->config;
if (cfg->gpio_port == 0) {
*value = cfg->gpio_dev->in;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
*value = cfg->gpio_dev->in1.data;
#endif
}
return 0;
}
static int gpio_esp32_port_set_masked_raw(const struct device *port,
uint32_t mask, uint32_t value)
{
const struct gpio_esp32_config *const cfg = port->config;
uint32_t key = irq_lock();
if (cfg->gpio_port == 0) {
cfg->gpio_dev->out = (cfg->gpio_dev->out & ~mask) | (mask & value);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
cfg->gpio_dev->out1.data = (cfg->gpio_dev->out1.data & ~mask) | (mask & value);
#endif
}
irq_unlock(key);
return 0;
}
static int gpio_esp32_port_set_bits_raw(const struct device *port,
uint32_t pins)
{
const struct gpio_esp32_config *const cfg = port->config;
if (cfg->gpio_port == 0) {
cfg->gpio_dev->out_w1ts = pins;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
cfg->gpio_dev->out1_w1ts.data = pins;
#endif
}
return 0;
}
static int gpio_esp32_port_clear_bits_raw(const struct device *port,
uint32_t pins)
{
const struct gpio_esp32_config *const cfg = port->config;
if (cfg->gpio_port == 0) {
cfg->gpio_dev->out_w1tc = pins;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
cfg->gpio_dev->out1_w1tc.data = pins;
#endif
}
return 0;
}
static int gpio_esp32_port_toggle_bits(const struct device *port,
uint32_t pins)
{
const struct gpio_esp32_config *const cfg = port->config;
uint32_t key = irq_lock();
if (cfg->gpio_port == 0) {
cfg->gpio_dev->out ^= pins;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
} else {
cfg->gpio_dev->out1.data ^= pins;
#endif
}
irq_unlock(key);
return 0;
}
static int convert_int_type(enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
if (mode == GPIO_INT_MODE_DISABLED) {
return GPIO_INTR_DISABLE;
}
if (mode == GPIO_INT_MODE_LEVEL) {
switch (trig) {
case GPIO_INT_TRIG_LOW:
return GPIO_INTR_LOW_LEVEL;
case GPIO_INT_TRIG_HIGH:
return GPIO_INTR_HIGH_LEVEL;
default:
return -EINVAL;
}
} else { /* edge interrupts */
switch (trig) {
case GPIO_INT_TRIG_HIGH:
return GPIO_INTR_POSEDGE;
case GPIO_INT_TRIG_LOW:
return GPIO_INTR_NEGEDGE;
case GPIO_INT_TRIG_BOTH:
return GPIO_INTR_ANYEDGE;
default:
return -EINVAL;
}
}
/* Any other type of interrupt triggering is invalid. */
return -EINVAL;
}
static int gpio_esp32_pin_interrupt_configure(const struct device *port,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_esp32_config *const cfg = port->config;
uint32_t io_pin = (uint32_t) pin + ((cfg->gpio_port == 1 && pin < 32) ? 32 : 0);
int intr_trig_mode = convert_int_type(mode, trig);
uint32_t key;
if (intr_trig_mode < 0) {
return intr_trig_mode;
}
key = irq_lock();
if (cfg->gpio_port == 0) {
gpio_ll_clear_intr_status(cfg->gpio_base, BIT(pin));
} else {
gpio_ll_clear_intr_status_high(cfg->gpio_base, BIT(pin));
}
gpio_ll_set_intr_type(cfg->gpio_base, io_pin, intr_trig_mode);
gpio_ll_intr_enable_on_core(cfg->gpio_base, CPU_ID(), io_pin);
irq_unlock(key);
return 0;
}
static int gpio_esp32_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_esp32_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
static uint32_t gpio_esp32_get_pending_int(const struct device *dev)
{
const struct gpio_esp32_config *const cfg = dev->config;
uint32_t irq_status;
uint32_t const core_id = CPU_ID();
if (cfg->gpio_port == 0) {
gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
} else {
gpio_ll_get_intr_status_high(cfg->gpio_base, core_id, &irq_status);
}
return irq_status;
}
static void IRAM_ATTR gpio_esp32_fire_callbacks(const struct device *dev)
{
const struct gpio_esp32_config *const cfg = dev->config;
struct gpio_esp32_data *data = dev->data;
uint32_t irq_status;
uint32_t const core_id = CPU_ID();
if (cfg->gpio_port == 0) {
gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
gpio_ll_clear_intr_status(cfg->gpio_base, irq_status);
} else {
gpio_ll_get_intr_status_high(cfg->gpio_base, core_id, &irq_status);
gpio_ll_clear_intr_status_high(cfg->gpio_base, irq_status);
}
if (irq_status != 0) {
gpio_fire_callbacks(&data->cb, dev, irq_status);
}
}
static void gpio_esp32_isr(void *param);
static int gpio_esp32_init(const struct device *dev)
{
struct gpio_esp32_data *data = dev->data;
static bool isr_connected;
if (!isr_connected) {
esp_intr_alloc(DT_IRQN(DT_NODELABEL(gpio0)),
0,
(ISR_HANDLER)gpio_esp32_isr,
(void *)dev,
NULL);
isr_connected = true;
}
return 0;
}
static const struct gpio_driver_api gpio_esp32_driver_api = {
.pin_configure = gpio_esp32_config,
.port_get_raw = gpio_esp32_port_get_raw,
.port_set_masked_raw = gpio_esp32_port_set_masked_raw,
.port_set_bits_raw = gpio_esp32_port_set_bits_raw,
.port_clear_bits_raw = gpio_esp32_port_clear_bits_raw,
.port_toggle_bits = gpio_esp32_port_toggle_bits,
.pin_interrupt_configure = gpio_esp32_pin_interrupt_configure,
.manage_callback = gpio_esp32_manage_callback,
.get_pending_int = gpio_esp32_get_pending_int
};
#define ESP_SOC_GPIO_INIT(_id) \
static struct gpio_esp32_data gpio_data_##_id; \
static struct gpio_esp32_config gpio_config_##_id = { \
.drv_cfg = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_id), \
}, \
.gpio_base = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0)), \
.gpio_dev = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio##_id)), \
.gpio_port = _id \
}; \
DEVICE_DT_DEFINE(DT_NODELABEL(gpio##_id), \
&gpio_esp32_init, \
NULL, \
&gpio_data_##_id, \
&gpio_config_##_id, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_esp32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(ESP_SOC_GPIO_INIT);
static void IRAM_ATTR gpio_esp32_isr(void *param)
{
ARG_UNUSED(param);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(0));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(1));
#endif
}
``` | /content/code_sandbox/drivers/gpio/gpio_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,900 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stmpe1600
/**
* @file Driver for STMPE1600 I2C-based GPIO driver.
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(stmpe1600);
/* Register definitions */
#define REG_CHIP_ID_LSB 0x00 /* const 0x00 */
#define REG_CHIP_ID_MSB 0x01 /* const 0x16 */
#define REG_VERSION_ID 0x02 /* Revision number (const 0x01) */
#define REG_SYS_CTRL 0x03 /* Reset and interrupt control */
#define REG_IEGPIOR_LSB 0x08 /* GPIO interrupt enable register */
#define REG_IEGPIOR_MSB 0x09
#define REG_ISGPIOR_LSB 0x0A /* GPIO interrupt status register */
#define REG_ISGPIOR_MSB 0x0B
#define REG_GPMR_LSB 0x10 /* GPIO monitor pin state register */
#define REG_GPMR_MSB 0x11
#define REG_GPSR_LSB 0x12 /* GPIO set pin state register */
#define REG_GPSR_MSB 0x13
#define REG_GPDR_LSB 0x14 /* GPIO set pin direction register */
#define REG_GPDR_MSB 0x15
#define REG_GPPIR_LSB 0x16 /* GPIO polarity inversion register */
#define REG_GPPIR_MSB 0x17
/** Configuration data */
struct stmpe1600_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/** Master I2C DT specification */
struct i2c_dt_spec i2c;
};
/** Runtime driver data */
struct stmpe1600_drvdata {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/** Driver lock */
struct k_sem lock;
/* Registers cache */
uint16_t GPSR;
uint16_t GPDR;
};
static int write_reg16(const struct stmpe1600_config * const config, uint8_t reg, uint16_t value)
{
uint8_t buf[3];
int ret;
LOG_DBG("STMPE1600[0x%02X]: write REG[0x%02X..0x%02X] = %04x",
config->i2c.addr, reg, reg + 1, value);
buf[0] = reg;
sys_put_le16(value, &buf[1]);
ret = i2c_write_dt(&config->i2c, buf, sizeof(buf));
if (ret != 0) {
LOG_ERR("STMPE1600[0x%02X]: write error REG[0x%02X..0x%02X]: %d",
config->i2c.addr, reg, reg + 1, ret);
}
return ret;
}
static int read_reg16(const struct stmpe1600_config * const config, uint8_t reg, uint16_t *value)
{
uint16_t transfer_data;
int ret;
LOG_DBG("STMPE1600[0x%02X]: read REG[0x%02X..0x%02X]",
config->i2c.addr, reg, reg + 1);
ret = i2c_burst_read_dt(&config->i2c, reg, (uint8_t *)&transfer_data,
sizeof(transfer_data));
if (ret != 0) {
LOG_ERR("STMPE1600[0x%02X]: read error REG[0x%02X..0x%02X]: %d",
config->i2c.addr, reg, reg + 1, ret);
} else {
*value = sys_le16_to_cpu(transfer_data);
LOG_DBG("STMPE1600[0x%02X]: read REG[0x%02X..0x%02X] => %04x",
config->i2c.addr, reg, reg + 1, *value);
}
return ret;
}
static int set_pin_dir(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
struct stmpe1600_drvdata *const drvdata = (struct stmpe1600_drvdata *const) dev->data;
bool set_state = false;
uint16_t GPDR = drvdata->GPDR;
uint16_t GPSR = drvdata->GPSR;
int ret;
if ((flags & GPIO_OUTPUT) != 0U) {
GPDR |= BIT(pin);
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
GPSR |= BIT(pin);
set_state = true;
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
GPSR &= ~BIT(pin);
set_state = true;
}
} else {
GPDR &= ~BIT(pin);
}
if (set_state) {
ret = write_reg16(dev->config, REG_GPSR_LSB, GPSR);
if (ret != 0) {
return ret;
}
drvdata->GPSR = GPSR;
}
ret = write_reg16(dev->config, REG_GPDR_LSB, GPDR);
if (ret == 0) {
drvdata->GPDR = GPDR;
}
return ret;
}
static int stmpe1600_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct stmpe1600_config *const config = dev->config;
struct stmpe1600_drvdata *const drvdata = (struct stmpe1600_drvdata *const) dev->data;
int ret;
/* No support for disconnected pin */
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
return -ENOTSUP;
}
/* STMPE1600 does not support any of these modes */
if ((flags & (GPIO_SINGLE_ENDED | GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
return -ENOTSUP;
}
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drvdata->lock, K_FOREVER);
ret = set_pin_dir(dev, pin, flags);
if (ret != 0) {
LOG_ERR("STMPE1600[0x%X]: error setting pin direction (%d)",
config->i2c.addr, ret);
}
k_sem_give(&drvdata->lock);
return ret;
}
static int stmpe1600_port_get_raw(const struct device *dev, uint32_t *value)
{
struct stmpe1600_drvdata *const drvdata = (struct stmpe1600_drvdata *const) dev->data;
uint16_t reg_value;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drvdata->lock, K_FOREVER);
ret = read_reg16(dev->config, REG_GPMR_LSB, ®_value);
k_sem_give(&drvdata->lock);
if (ret == 0) {
*value = reg_value;
}
return ret;
}
static int stmpe1600_port_set_masked_raw(const struct device *dev,
uint32_t mask, uint32_t value)
{
struct stmpe1600_drvdata *const drvdata = dev->data;
uint16_t GPSR;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drvdata->lock, K_FOREVER);
GPSR = (drvdata->GPSR & ~mask) | (mask & value);
ret = write_reg16(dev->config, REG_GPSR_LSB, GPSR);
if (ret == 0) {
drvdata->GPSR = GPSR;
}
k_sem_give(&drvdata->lock);
return ret;
}
static int stmpe1600_port_set_bits_raw(const struct device *dev, uint32_t mask)
{
return stmpe1600_port_set_masked_raw(dev, mask, mask);
}
static int stmpe1600_port_clear_bits_raw(const struct device *dev, uint32_t mask)
{
return stmpe1600_port_set_masked_raw(dev, mask, 0);
}
static int stmpe1600_port_toggle_bits(const struct device *dev, uint32_t mask)
{
struct stmpe1600_drvdata *const drvdata = dev->data;
uint16_t GPSR;
int ret;
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drvdata->lock, K_FOREVER);
GPSR = drvdata->GPSR ^ mask;
ret = write_reg16(dev->config, REG_GPSR_LSB, GPSR);
if (ret == 0) {
drvdata->GPSR = GPSR;
}
k_sem_give(&drvdata->lock);
return ret;
}
static int stmpe1600_init(const struct device *dev)
{
const struct stmpe1600_config *const config = dev->config;
struct stmpe1600_drvdata *const drvdata = (struct stmpe1600_drvdata *const) dev->data;
uint16_t chip_id;
int ret;
LOG_DBG("STMPE1600[0x%02X] init", config->i2c.addr);
k_sem_init(&drvdata->lock, 1, 1);
ret = read_reg16(dev->config, REG_CHIP_ID_LSB, &chip_id);
if (ret != 0) {
LOG_ERR("STMPE1600[0x%02X]: Unable to read Chip ID", config->i2c.addr);
return ret;
}
if (chip_id != 0x1600) {
LOG_ERR("STMPE1600[0x%02X]: Invalid Chip ID", config->i2c.addr);
return -EINVAL;
}
ret = read_reg16(dev->config, REG_GPSR_LSB, &drvdata->GPSR);
if (ret != 0) {
LOG_ERR("STMPE1600[0x%02X]: Unable to read GPSR", config->i2c.addr);
return ret;
}
ret = read_reg16(dev->config, REG_GPDR_LSB, &drvdata->GPDR);
if (ret != 0) {
LOG_ERR("STMPE1600[0x%02X]: Unable to read GPDR", config->i2c.addr);
}
return ret;
}
static const struct gpio_driver_api stmpe1600_drv_api = {
.pin_configure = stmpe1600_configure,
.port_get_raw = stmpe1600_port_get_raw,
.port_set_masked_raw = stmpe1600_port_set_masked_raw,
.port_set_bits_raw = stmpe1600_port_set_bits_raw,
.port_clear_bits_raw = stmpe1600_port_clear_bits_raw,
.port_toggle_bits = stmpe1600_port_toggle_bits,
};
#define STMPE1600_INIT(inst) \
static struct stmpe1600_config stmpe1600_##inst##_config = { \
.common = { .port_pin_mask = 0xffff }, \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}; \
\
static struct stmpe1600_drvdata stmpe1600_##inst##_drvdata; \
\
DEVICE_DT_INST_DEFINE(inst, stmpe1600_init, NULL, \
&stmpe1600_##inst##_drvdata, \
&stmpe1600_##inst##_config, \
POST_KERNEL, \
CONFIG_GPIO_STMPE1600_INIT_PRIORITY, \
&stmpe1600_drv_api);
DT_INST_FOREACH_STATUS_OKAY(STMPE1600_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_stmpe1600.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,582 |
```c
/*
*
*/
#define DT_DRV_COMPAT semtech_sx1509b
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_sx1509b.h>
#include <zephyr/dt-bindings/gpio/semtech-sx1509b.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(sx1509b, CONFIG_GPIO_LOG_LEVEL);
#include <zephyr/drivers/gpio/gpio_utils.h>
/* Number of pins supported by the device */
#define NUM_PINS 16
/* Max to select all pins supported on the device. */
#define ALL_PINS ((uint16_t)BIT_MASK(NUM_PINS))
/* Reset delay is 2.5 ms, round up for Zephyr resolution */
#define RESET_DELAY_MS 3
/** Cache of the output configuration and data of the pins. */
struct sx1509b_pin_state {
uint16_t input_disable; /* 0x00 */
uint16_t long_slew; /* 0x02 */
uint16_t low_drive; /* 0x04 */
uint16_t pull_up; /* 0x06 */
uint16_t pull_down; /* 0x08 */
uint16_t open_drain; /* 0x0A */
uint16_t polarity; /* 0x0C */
uint16_t dir; /* 0x0E */
uint16_t data; /* 0x10 */
} __packed;
struct sx1509b_irq_state {
uint16_t interrupt_mask; /* 0x12 */
uint32_t interrupt_sense; /* 0x14, 0x16 */
} __packed;
struct sx1509b_debounce_state {
uint8_t debounce_config; /* 0x22 */
uint16_t debounce_enable; /* 0x23 */
} __packed;
/** Runtime driver data */
struct sx1509b_drv_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
struct sx1509b_pin_state pin_state;
uint16_t led_drv_enable;
struct sx1509b_debounce_state debounce_state;
struct k_sem lock;
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
struct gpio_callback gpio_cb;
struct k_work work;
struct sx1509b_irq_state irq_state;
const struct device *dev;
/* user ISR cb */
sys_slist_t cb;
#endif /* CONFIG_GPIO_SX1509B_INTERRUPT */
};
/** Configuration data */
struct sx1509b_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
struct i2c_dt_spec bus;
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
struct gpio_dt_spec nint_gpio;
#endif /* CONFIG_GPIO_SX1509B_INTERRUPT */
};
/* General configuration register addresses */
enum {
/* TODO: Add rest of the regs */
SX1509B_REG_CLOCK = 0x1e,
SX1509B_REG_RESET = 0x7d,
};
/* Magic values for softreset */
enum {
SX1509B_REG_RESET_MAGIC0 = 0x12,
SX1509B_REG_RESET_MAGIC1 = 0x34,
};
/* Register bits for SX1509B_REG_CLOCK */
enum {
SX1509B_REG_CLOCK_FOSC_OFF = 0 << 5,
SX1509B_REG_CLOCK_FOSC_EXT = 1 << 5,
SX1509B_REG_CLOCK_FOSC_INT_2MHZ = 2 << 5,
};
/* Register bits for SX1509B_REG_MISC */
enum {
SX1509B_REG_MISC_LOG_A = 1 << 3,
SX1509B_REG_MISC_LOG_B = 1 << 7,
/* ClkX = fOSC */
SX1509B_REG_MISC_FREQ = 1 << 4,
};
/* Pin configuration register addresses */
enum {
SX1509B_REG_INPUT_DISABLE = 0x00,
SX1509B_REG_PULL_UP = 0x06,
SX1509B_REG_PULL_DOWN = 0x08,
SX1509B_REG_OPEN_DRAIN = 0x0a,
SX1509B_REG_DIR = 0x0e,
SX1509B_REG_DATA = 0x10,
SX1509B_REG_INTERRUPT_MASK = 0x12,
SX1509B_REG_INTERRUPT_SENSE = 0x14,
SX1509B_REG_INTERRUPT_SENSE_B = 0x14,
SX1509B_REG_INTERRUPT_SENSE_A = 0x16,
SX1509B_REG_INTERRUPT_SOURCE = 0x18,
SX1509B_REG_MISC = 0x1f,
SX1509B_REG_LED_DRV_ENABLE = 0x20,
SX1509B_REG_DEBOUNCE_CONFIG = 0x22,
SX1509B_REG_DEBOUNCE_ENABLE = 0x23,
};
/* Edge sensitivity types */
enum {
SX1509B_EDGE_NONE = 0x00,
SX1509B_EDGE_RISING = 0x01,
SX1509B_EDGE_FALLING = 0x02,
SX1509B_EDGE_BOTH = 0x03,
};
/* Intensity register addresses for all 16 pins */
static const uint8_t intensity_registers[16] = { 0x2a, 0x2d, 0x30, 0x33,
0x36, 0x3b, 0x40, 0x45,
0x4a, 0x4d, 0x50, 0x53,
0x56, 0x5b, 0x60, 0x65 };
/**
* @brief Write a big-endian word to an internal address of an I2C slave.
*
* @param dev Pointer to the I2C bus spec.
* @param reg_addr Address of the internal register being written.
* @param value Value to be written to internal register.
*
* @retval 0 If successful.
* @retval -EIO General input / output error.
*/
static inline int i2c_reg_write_word_be(const struct i2c_dt_spec *bus,
uint8_t reg_addr, uint16_t value)
{
uint8_t tx_buf[3] = { reg_addr, value >> 8, value & 0xff };
return i2c_write_dt(bus, tx_buf, 3);
}
/**
* @brief Write a big-endian byte to an internal address of an I2C slave.
*
* @param bus Pointer to the I2C bus spec.
* @param reg_addr Address of the internal register being written.
* @param value Value to be written to internal register.
*
* @retval 0 If successful.
* @retval -EIO General input / output error.
*/
static inline int i2c_reg_write_byte_be(const struct i2c_dt_spec *bus,
uint8_t reg_addr, uint8_t value)
{
uint8_t tx_buf[3] = { reg_addr, value };
return i2c_write_dt(bus, tx_buf, 2);
}
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
static int sx1509b_handle_interrupt(const struct device *dev)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
int ret = 0;
uint16_t int_source;
uint8_t cmd = SX1509B_REG_INTERRUPT_SOURCE;
k_sem_take(&drv_data->lock, K_FOREVER);
ret = i2c_write_read_dt(&cfg->bus, &cmd, sizeof(cmd),
(uint8_t *)&int_source, sizeof(int_source));
if (ret != 0) {
goto out;
}
int_source = sys_be16_to_cpu(int_source);
/* reset interrupts before invoking callbacks */
ret = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_INTERRUPT_SOURCE,
int_source);
out:
k_sem_give(&drv_data->lock);
if (ret == 0) {
gpio_fire_callbacks(&drv_data->cb, dev, int_source);
}
return ret;
}
static void sx1509b_work_handler(struct k_work *work)
{
struct sx1509b_drv_data *drv_data =
CONTAINER_OF(work, struct sx1509b_drv_data, work);
sx1509b_handle_interrupt(drv_data->dev);
}
static void sx1509_int_cb(const struct device *dev,
struct gpio_callback *gpio_cb,
uint32_t pins)
{
struct sx1509b_drv_data *drv_data = CONTAINER_OF(gpio_cb,
struct sx1509b_drv_data, gpio_cb);
ARG_UNUSED(pins);
k_work_submit(&drv_data->work);
}
#endif
static int write_pin_state(const struct sx1509b_config *cfg,
struct sx1509b_drv_data *drv_data,
struct sx1509b_pin_state *pins, bool data_first)
{
struct {
uint8_t reg;
struct sx1509b_pin_state pins;
} __packed pin_buf;
int rc;
pin_buf.reg = SX1509B_REG_INPUT_DISABLE;
pin_buf.pins.input_disable = sys_cpu_to_be16(pins->input_disable);
pin_buf.pins.long_slew = sys_cpu_to_be16(pins->long_slew);
pin_buf.pins.low_drive = sys_cpu_to_be16(pins->low_drive);
pin_buf.pins.pull_up = sys_cpu_to_be16(pins->pull_up);
pin_buf.pins.pull_down = sys_cpu_to_be16(pins->pull_down);
pin_buf.pins.open_drain = sys_cpu_to_be16(pins->open_drain);
pin_buf.pins.polarity = sys_cpu_to_be16(pins->polarity);
pin_buf.pins.dir = sys_cpu_to_be16(pins->dir);
pin_buf.pins.data = sys_cpu_to_be16(pins->data);
if (data_first) {
rc = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_DATA,
pins->data);
if (rc == 0) {
rc = i2c_write_dt(&cfg->bus, &pin_buf.reg,
sizeof(pin_buf) - sizeof(pins->data));
}
} else {
rc = i2c_write_dt(&cfg->bus, &pin_buf.reg, sizeof(pin_buf));
}
return rc;
}
static int sx1509b_config(const struct device *dev,
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
struct sx1509b_pin_state *pins = &drv_data->pin_state;
struct sx1509b_debounce_state *debounce = &drv_data->debounce_state;
int rc = 0;
bool data_first = false;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
if (drv_data->led_drv_enable & BIT(pin)) {
/* Disable LED driver */
drv_data->led_drv_enable &= ~BIT(pin);
rc = i2c_reg_write_word_be(&cfg->bus,
SX1509B_REG_LED_DRV_ENABLE,
drv_data->led_drv_enable);
if (rc) {
goto out;
}
}
pins->open_drain &= ~BIT(pin);
if ((flags & GPIO_SINGLE_ENDED) != 0) {
if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
pins->open_drain |= BIT(pin);
} else {
/* Open source not supported */
rc = -ENOTSUP;
goto out;
}
}
if ((flags & GPIO_PULL_UP) != 0) {
pins->pull_up |= BIT(pin);
} else {
pins->pull_up &= ~BIT(pin);
}
if ((flags & GPIO_PULL_DOWN) != 0) {
pins->pull_down |= BIT(pin);
} else {
pins->pull_down &= ~BIT(pin);
}
if ((flags & GPIO_INPUT) != 0) {
pins->input_disable &= ~BIT(pin);
} else {
pins->input_disable |= BIT(pin);
}
if ((flags & GPIO_OUTPUT) != 0) {
pins->dir &= ~BIT(pin);
if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
pins->data &= ~BIT(pin);
data_first = true;
} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
pins->data |= BIT(pin);
data_first = true;
}
} else {
pins->dir |= BIT(pin);
}
if ((flags & SX1509B_GPIO_DEBOUNCE) != 0) {
debounce->debounce_enable |= BIT(pin);
} else {
debounce->debounce_enable &= ~BIT(pin);
}
LOG_DBG("CFG %u %x : ID %04x ; PU %04x ; PD %04x ; DIR %04x ; DAT %04x",
pin, flags,
pins->input_disable, pins->pull_up, pins->pull_down,
pins->dir, pins->data);
rc = write_pin_state(cfg, drv_data, pins, data_first);
if (rc == 0) {
struct {
uint8_t reg;
struct sx1509b_debounce_state debounce;
} __packed debounce_buf;
debounce_buf.reg = SX1509B_REG_DEBOUNCE_CONFIG;
debounce_buf.debounce.debounce_config
= debounce->debounce_config;
debounce_buf.debounce.debounce_enable
= sys_cpu_to_be16(debounce->debounce_enable);
rc = i2c_write_dt(&cfg->bus, &debounce_buf.reg,
sizeof(debounce_buf));
}
out:
k_sem_give(&drv_data->lock);
return rc;
}
static int port_get(const struct device *dev,
gpio_port_value_t *value)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
uint16_t pin_data;
int rc = 0;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
k_sem_take(&drv_data->lock, K_FOREVER);
uint8_t cmd = SX1509B_REG_DATA;
rc = i2c_write_read_dt(&cfg->bus, &cmd, sizeof(cmd), &pin_data,
sizeof(pin_data));
LOG_DBG("read %04x got %d", sys_be16_to_cpu(pin_data), rc);
if (rc != 0) {
goto out;
}
*value = sys_be16_to_cpu(pin_data);
out:
k_sem_give(&drv_data->lock);
return rc;
}
static int port_write(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value,
gpio_port_value_t toggle)
{
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
void *data = &drv_data->pin_state.data;
uint16_t *outp = data;
__ASSERT_NO_MSG(IS_PTR_ALIGNED(data, uint16_t));
k_sem_take(&drv_data->lock, K_FOREVER);
uint16_t orig_out = *outp;
uint16_t out = ((orig_out & ~mask) | (value & mask)) ^ toggle;
int rc = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_DATA, out);
if (rc == 0) {
*outp = out;
}
k_sem_give(&drv_data->lock);
LOG_DBG("write %04x msk %04x val %04x => %04x: %d", orig_out, mask, value, out, rc);
return rc;
}
static int port_set_masked(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
return port_write(dev, mask, value, 0);
}
static int port_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, pins, 0);
}
static int port_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, pins, 0, 0);
}
static int port_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
return port_write(dev, 0, 0, pins);
}
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
static int pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
int rc = 0;
/* Device does not support level-triggered interrupts. */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
struct sx1509b_irq_state *irq = &drv_data->irq_state;
struct {
uint8_t reg;
struct sx1509b_irq_state irq;
} __packed irq_buf;
/* Only level triggered interrupts are supported, and those
* only if interrupt support is enabled.
*/
if (IS_ENABLED(CONFIG_GPIO_SX1509B_INTERRUPT)) {
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
} else if (mode != GPIO_INT_MODE_DISABLED) {
return -ENOTSUP;
}
k_sem_take(&drv_data->lock, K_FOREVER);
irq->interrupt_sense &= ~(SX1509B_EDGE_BOTH << (pin * 2));
if (mode == GPIO_INT_MODE_DISABLED) {
irq->interrupt_mask |= BIT(pin);
} else { /* GPIO_INT_MODE_EDGE */
irq->interrupt_mask &= ~BIT(pin);
if (trig == GPIO_INT_TRIG_BOTH) {
irq->interrupt_sense |= (SX1509B_EDGE_BOTH <<
(pin * 2));
} else if (trig == GPIO_INT_TRIG_LOW) {
irq->interrupt_sense |= (SX1509B_EDGE_FALLING <<
(pin * 2));
} else if (trig == GPIO_INT_TRIG_HIGH) {
irq->interrupt_sense |= (SX1509B_EDGE_RISING <<
(pin * 2));
}
}
irq_buf.reg = SX1509B_REG_INTERRUPT_MASK;
irq_buf.irq.interrupt_mask = sys_cpu_to_be16(irq->interrupt_mask);
irq_buf.irq.interrupt_sense = sys_cpu_to_be32(irq->interrupt_sense);
rc = i2c_write_dt(&cfg->bus, &irq_buf.reg, sizeof(irq_buf));
k_sem_give(&drv_data->lock);
return rc;
}
#endif /* CONFIG_GPIO_SX1509B_INTERRUPT */
/**
* @brief Initialization function of SX1509B
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int sx1509b_init(const struct device *dev)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
int rc;
if (!device_is_ready(cfg->bus.bus)) {
LOG_ERR("I2C bus not ready");
rc = -ENODEV;
goto out;
}
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
drv_data->dev = dev;
if (!gpio_is_ready_dt(&cfg->nint_gpio)) {
rc = -ENODEV;
goto out;
}
k_work_init(&drv_data->work, sx1509b_work_handler);
gpio_pin_configure_dt(&cfg->nint_gpio, GPIO_INPUT);
gpio_pin_interrupt_configure_dt(&cfg->nint_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
gpio_init_callback(&drv_data->gpio_cb, sx1509_int_cb,
BIT(cfg->nint_gpio.pin));
gpio_add_callback(cfg->nint_gpio.port, &drv_data->gpio_cb);
drv_data->irq_state = (struct sx1509b_irq_state) {
.interrupt_mask = ALL_PINS,
};
#endif
rc = i2c_reg_write_byte_dt(&cfg->bus, SX1509B_REG_RESET,
SX1509B_REG_RESET_MAGIC0);
if (rc != 0) {
LOG_ERR("%s: reset m0 failed: %d\n", dev->name, rc);
goto out;
}
rc = i2c_reg_write_byte_dt(&cfg->bus, SX1509B_REG_RESET,
SX1509B_REG_RESET_MAGIC1);
if (rc != 0) {
goto out;
}
k_sleep(K_MSEC(RESET_DELAY_MS));
/* Reset state mediated by initial configuration */
drv_data->pin_state = (struct sx1509b_pin_state) {
.dir = (ALL_PINS
& ~(DT_INST_PROP(0, init_out_low)
| DT_INST_PROP(0, init_out_high))),
.data = (ALL_PINS
& ~DT_INST_PROP(0, init_out_low)),
};
drv_data->debounce_state = (struct sx1509b_debounce_state) {
.debounce_config = CONFIG_GPIO_SX1509B_DEBOUNCE_TIME,
};
rc = i2c_reg_write_byte_dt(&cfg->bus, SX1509B_REG_CLOCK,
SX1509B_REG_CLOCK_FOSC_INT_2MHZ);
if (rc == 0) {
rc = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_DATA,
drv_data->pin_state.data);
}
if (rc == 0) {
rc = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_DIR,
drv_data->pin_state.dir);
}
if (rc == 0) {
rc = i2c_reg_write_byte_be(&cfg->bus, SX1509B_REG_MISC,
SX1509B_REG_MISC_LOG_A |
SX1509B_REG_MISC_LOG_B |
SX1509B_REG_MISC_FREQ);
}
out:
if (rc != 0) {
LOG_ERR("%s init failed: %d", dev->name, rc);
} else {
LOG_INF("%s init ok", dev->name);
}
k_sem_give(&drv_data->lock);
return rc;
}
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
static int gpio_sx1509b_manage_callback(const struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct sx1509b_drv_data *data = dev->data;
return gpio_manage_callback(&data->cb, callback, set);
}
#endif
static const struct gpio_driver_api api_table = {
.pin_configure = sx1509b_config,
.port_get_raw = port_get,
.port_set_masked_raw = port_set_masked,
.port_set_bits_raw = port_set_bits,
.port_clear_bits_raw = port_clear_bits,
.port_toggle_bits = port_toggle_bits,
#ifdef CONFIG_GPIO_SX1509B_INTERRUPT
.pin_interrupt_configure = pin_interrupt_configure,
.manage_callback = gpio_sx1509b_manage_callback,
#endif
};
int sx1509b_led_intensity_pin_configure(const struct device *dev,
gpio_pin_t pin)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
struct sx1509b_pin_state *pins = &drv_data->pin_state;
int rc;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin >= ARRAY_SIZE(intensity_registers)) {
return -ERANGE;
}
k_sem_take(&drv_data->lock, K_FOREVER);
/* Enable LED driver */
drv_data->led_drv_enable |= BIT(pin);
rc = i2c_reg_write_word_be(&cfg->bus, SX1509B_REG_LED_DRV_ENABLE,
drv_data->led_drv_enable);
/* Set intensity to 0 */
if (rc == 0) {
rc = i2c_reg_write_byte_be(&cfg->bus, intensity_registers[pin], 0);
} else {
goto out;
}
pins->input_disable |= BIT(pin);
pins->pull_up &= ~BIT(pin);
pins->dir &= ~BIT(pin);
pins->data &= ~BIT(pin);
if (rc == 0) {
rc = write_pin_state(cfg, drv_data, pins, false);
}
out:
k_sem_give(&drv_data->lock);
return rc;
}
int sx1509b_led_intensity_pin_set(const struct device *dev, gpio_pin_t pin,
uint8_t intensity_val)
{
const struct sx1509b_config *cfg = dev->config;
struct sx1509b_drv_data *drv_data = dev->data;
int rc;
/* Can't do I2C bus operations from an ISR */
if (k_is_in_isr()) {
return -EWOULDBLOCK;
}
if (pin >= ARRAY_SIZE(intensity_registers)) {
return -ERANGE;
}
k_sem_take(&drv_data->lock, K_FOREVER);
rc = i2c_reg_write_byte_be(&cfg->bus, intensity_registers[pin],
intensity_val);
k_sem_give(&drv_data->lock);
return rc;
}
#define GPIO_SX1509B_DEFINE(inst) \
static const struct sx1509b_config sx1509b_cfg##inst = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst),\
}, \
.bus = I2C_DT_SPEC_INST_GET(inst), \
IF_ENABLED(CONFIG_GPIO_SX1509B_INTERRUPT, \
(GPIO_DT_SPEC_INST_GET(inst, nint_gpios))) \
}; \
\
static struct sx1509b_drv_data sx1509b_drvdata##inst = { \
.lock = Z_SEM_INITIALIZER(sx1509b_drvdata##inst.lock, 1, 1), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, sx1509b_init, NULL, &sx1509b_drvdata##inst,\
&sx1509b_cfg##inst, POST_KERNEL, \
CONFIG_GPIO_SX1509B_INIT_PRIORITY, &api_table);
DT_INST_FOREACH_STATUS_OKAY(GPIO_SX1509B_DEFINE)
``` | /content/code_sandbox/drivers/gpio/gpio_sx1509b.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,903 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_smartbond_gpio
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <stdint.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/pm/device.h>
#include <DA1469xAB.h>
#include <da1469x_pdc.h>
#include <da1469x_pd.h>
#define GPIO_PUPD_INPUT 0
#define GPIO_PUPD_INPUT_PU 1
#define GPIO_PUPD_INPUT_PD 2
#define GPIO_PUPD_OUTPUT 3
/* GPIO P0 and P1 share single GPIO and WKUP peripheral instance with separate
* set registers for P0 and P1 interleaved. The starting registers for direct
* data access, bit access, mode, latch and wake-up controller are defined in
* device tree.
*/
struct gpio_smartbond_data_regs {
uint32_t data;
uint32_t _reserved0;
uint32_t set;
uint32_t _reserved1;
uint32_t reset;
};
struct gpio_smartbond_latch_regs {
uint32_t latch;
uint32_t set;
uint32_t reset;
};
struct gpio_smartbond_wkup_regs {
uint32_t select;
uint32_t _reserved0[4];
uint32_t pol;
uint32_t _reserved1[4];
uint32_t status;
uint32_t _reserved2[2];
uint32_t clear;
uint32_t _reserved3[2];
uint32_t sel;
};
struct gpio_smartbond_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* Pins that are configured for both edges (handled by software) */
gpio_port_pins_t both_edges_pins;
sys_slist_t callbacks;
#if CONFIG_PM_DEVICE
/*
* Saved state consist of:
* 1 word for GPIO output port state
* GPIOx_NGPIOS words for each pin mode
*/
uint32_t *gpio_saved_state;
#endif
};
struct gpio_smartbond_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
volatile struct gpio_smartbond_data_regs *data_regs;
volatile uint32_t *mode_regs;
volatile struct gpio_smartbond_latch_regs *latch_regs;
volatile struct gpio_smartbond_wkup_regs *wkup_regs;
/* Value of TRIG_SELECT for PDC_CTRLx_REG entry */
uint8_t wkup_trig_select;
#if CONFIG_PM_DEVICE
uint8_t ngpios;
#endif
};
static void gpio_smartbond_wkup_init(void)
{
static bool wkup_init;
/* Wakeup controller is shared for both GPIO ports and should
* be initialized only once.
*/
if (!wkup_init) {
WAKEUP->WKUP_CTRL_REG = 0;
WAKEUP->WKUP_CLEAR_P0_REG = 0xffffffff;
WAKEUP->WKUP_CLEAR_P1_REG = 0xffffffff;
WAKEUP->WKUP_SELECT_P0_REG = 0;
WAKEUP->WKUP_SELECT_P1_REG = 0;
WAKEUP->WKUP_SEL_GPIO_P0_REG = 0;
WAKEUP->WKUP_SEL_GPIO_P1_REG = 0;
WAKEUP->WKUP_RESET_IRQ_REG = 0;
CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk;
WAKEUP->WKUP_CTRL_REG = WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk;
wkup_init = true;
}
}
static int gpio_smartbond_pin_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_smartbond_config *config = dev->config;
if (flags == GPIO_DISCONNECTED) {
/* Set pin as input with no resistors selected */
config->mode_regs[pin] = GPIO_PUPD_INPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
return 0;
}
if ((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)) {
/* Simultaneous in/out is not supported */
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) {
config->mode_regs[pin] = GPIO_PUPD_OUTPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
if (flags & GPIO_OUTPUT_INIT_LOW) {
config->data_regs->reset = BIT(pin);
} else if (flags & GPIO_OUTPUT_INIT_HIGH) {
config->data_regs->set = BIT(pin);
}
return 0;
}
if (flags & GPIO_PULL_DOWN) {
config->mode_regs[pin] = GPIO_PUPD_INPUT_PD << GPIO_P0_00_MODE_REG_PUPD_Pos;
} else if (flags & GPIO_PULL_UP) {
config->mode_regs[pin] = GPIO_PUPD_INPUT_PU << GPIO_P0_00_MODE_REG_PUPD_Pos;
} else {
config->mode_regs[pin] = GPIO_PUPD_INPUT << GPIO_P0_00_MODE_REG_PUPD_Pos;
}
return 0;
}
static int gpio_smartbond_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_smartbond_config *config = dev->config;
*value = config->data_regs->data;
return 0;
}
static int gpio_smartbond_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_smartbond_config *config = dev->config;
config->data_regs->set = value & mask;
config->data_regs->reset = ~value & mask;
return 0;
}
static int gpio_smartbond_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_smartbond_config *config = dev->config;
config->data_regs->set = pins;
return 0;
}
static int gpio_smartbond_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_smartbond_config *config = dev->config;
config->data_regs->reset = pins;
return 0;
}
static int gpio_smartbond_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
const struct gpio_smartbond_config *config = dev->config;
volatile uint32_t *reg = &config->data_regs->data;
*reg = *reg ^ mask;
return 0;
}
static void gpio_smartbond_arm_next_edge_interrupt(const struct device *dev,
uint32_t pin_mask)
{
const struct gpio_smartbond_config *config = dev->config;
uint32_t pin_value;
do {
pin_value = config->data_regs->data & pin_mask;
if (pin_value) {
config->wkup_regs->pol |= pin_mask;
} else {
config->wkup_regs->pol &= ~pin_mask;
}
} while (pin_value != (config->data_regs->data & pin_mask));
}
static int gpio_smartbond_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_smartbond_config *config = dev->config;
struct gpio_smartbond_data *data = dev->data;
uint32_t pin_mask = BIT(pin);
#if CONFIG_PM
int trig_select_id = (config->wkup_trig_select << 5) | pin;
int pdc_ix;
#endif
/* Not supported by hardware */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
#if CONFIG_PM
pdc_ix = da1469x_pdc_find(trig_select_id, MCU_PDC_MASTER_M33, MCU_PDC_EN_XTAL);
#endif
if (mode == GPIO_INT_MODE_DISABLED) {
config->wkup_regs->sel &= ~pin_mask;
config->wkup_regs->clear = pin_mask;
data->both_edges_pins &= ~pin_mask;
#if CONFIG_PM
if (pdc_ix >= 0) {
da1469x_pdc_del(pdc_ix);
}
#endif
} else {
if (trig == GPIO_INT_TRIG_BOTH) {
/* Not supported by hardware */
data->both_edges_pins |= pin_mask;
gpio_smartbond_arm_next_edge_interrupt(dev, pin_mask);
} else if (trig == GPIO_INT_TRIG_HIGH) {
config->wkup_regs->pol &= ~pin_mask;
} else {
config->wkup_regs->pol |= pin_mask;
}
config->wkup_regs->sel |= pin_mask;
#if CONFIG_PM
if (pdc_ix < 0) {
pdc_ix = da1469x_pdc_add(trig_select_id, MCU_PDC_MASTER_M33,
MCU_PDC_EN_XTAL);
}
if (pdc_ix < 0) {
return -ENOMEM;
}
#endif
}
return 0;
}
static int gpio_smartbond_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_smartbond_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, set);
}
static void gpio_smartbond_isr(const struct device *dev)
{
const struct gpio_smartbond_config *config = dev->config;
struct gpio_smartbond_data *data = dev->data;
uint32_t stat;
uint32_t two_edge_triggered;
WAKEUP->WKUP_RESET_IRQ_REG = WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk;
stat = config->wkup_regs->status;
two_edge_triggered = stat & data->both_edges_pins;
while (two_edge_triggered) {
int pos = find_lsb_set(two_edge_triggered) - 1;
two_edge_triggered &= ~BIT(pos);
/* Re-arm for other edge */
gpio_smartbond_arm_next_edge_interrupt(dev, BIT(pos));
}
config->wkup_regs->clear = stat;
gpio_fire_callbacks(&data->callbacks, dev, stat);
}
#ifdef CONFIG_PM_DEVICE
static void gpio_latch_inst(mem_addr_t data_reg, mem_addr_t mode_reg, mem_addr_t latch_reg,
uint8_t ngpios, uint32_t *data, uint32_t *mode)
{
uint8_t idx;
*data = sys_read32(data_reg);
for (idx = 0; idx < ngpios; idx++, mode_reg += 4) {
mode[idx] = sys_read32(mode_reg);
}
sys_write32(BIT_MASK(ngpios), latch_reg);
}
static void gpio_unlatch_inst(mem_addr_t data_reg, mem_addr_t mode_reg, mem_addr_t latch_reg,
uint8_t ngpios, uint32_t data, uint32_t *mode)
{
uint8_t idx;
sys_write32(data, data_reg);
for (idx = 0; idx < ngpios; idx++, mode_reg += 4) {
sys_write32(mode[idx], mode_reg);
}
sys_write32(BIT_MASK(ngpios), latch_reg);
}
static void gpio_latch(const struct device *dev)
{
const struct gpio_smartbond_config *config = dev->config;
const struct gpio_smartbond_data *data = dev->data;
gpio_latch_inst((mem_addr_t)&config->data_regs->data,
(mem_addr_t)config->mode_regs,
(mem_addr_t)&config->latch_regs->reset,
config->ngpios, data->gpio_saved_state, data->gpio_saved_state + 1);
}
static void gpio_unlatch(const struct device *dev)
{
const struct gpio_smartbond_config *config = dev->config;
const struct gpio_smartbond_data *data = dev->data;
gpio_unlatch_inst((mem_addr_t)&config->data_regs->data,
(mem_addr_t)config->mode_regs,
(mem_addr_t)&config->latch_regs->set,
config->ngpios, data->gpio_saved_state[0], data->gpio_saved_state + 1);
}
static int gpio_smartbond_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
gpio_unlatch(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
gpio_latch(dev);
da1469x_pd_release(MCU_PD_DOMAIN_COM);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
/* GPIO driver registration */
static const struct gpio_driver_api gpio_smartbond_drv_api_funcs = {
.pin_configure = gpio_smartbond_pin_configure,
.port_get_raw = gpio_smartbond_port_get_raw,
.port_set_masked_raw = gpio_smartbond_port_set_masked_raw,
.port_set_bits_raw = gpio_smartbond_port_set_bits_raw,
.port_clear_bits_raw = gpio_smartbond_port_clear_bits_raw,
.port_toggle_bits = gpio_smartbond_port_toggle_bits,
.pin_interrupt_configure = gpio_smartbond_pin_interrupt_configure,
.manage_callback = gpio_smartbond_manage_callback,
};
#define GPIO_SAVED_STATE(id) gpio_smartbond_saved_state_##id
#define GPIO_PM_DEVICE_CFG(fld, val) \
COND_CODE_1(CONFIG_PM_DEVICE, (fld = val,), ())
#define GPIO_PM_DEVICE_STATE(id, ngpios) \
COND_CODE_1(CONFIG_PM_DEVICE, (static uint32_t GPIO_SAVED_STATE(id)[1 + ngpios];), ())
#define GPIO_SMARTBOND_DEVICE(id) \
GPIO_PM_DEVICE_STATE(id, DT_INST_PROP(id, ngpios)) \
static const struct gpio_smartbond_config gpio_smartbond_config_##id = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \
}, \
.data_regs = (volatile struct gpio_smartbond_data_regs *) \
DT_INST_REG_ADDR_BY_NAME(id, data), \
.mode_regs = (volatile uint32_t *)DT_INST_REG_ADDR_BY_NAME(id, mode), \
.latch_regs = (volatile struct gpio_smartbond_latch_regs *) \
DT_INST_REG_ADDR_BY_NAME(id, latch), \
.wkup_regs = (volatile struct gpio_smartbond_wkup_regs *) \
DT_INST_REG_ADDR_BY_NAME(id, wkup), \
.wkup_trig_select = id, \
GPIO_PM_DEVICE_CFG(.ngpios, DT_INST_PROP(id, ngpios)) \
}; \
\
static struct gpio_smartbond_data gpio_smartbond_data_##id = { \
GPIO_PM_DEVICE_CFG(.gpio_saved_state, GPIO_SAVED_STATE(id)) \
}; \
\
static int gpio_smartbond_init_##id(const struct device *dev) \
{ \
da1469x_pd_acquire(MCU_PD_DOMAIN_COM); \
gpio_smartbond_wkup_init(); \
IRQ_CONNECT(DT_INST_IRQN(id), \
DT_INST_IRQ(id, priority), \
gpio_smartbond_isr, \
DEVICE_DT_INST_GET(id), 0); \
irq_enable(DT_INST_IRQN(id)); \
return 0; \
} \
\
PM_DEVICE_DEFINE(id, gpio_smartbond_pm_action); \
DEVICE_DT_INST_DEFINE(id, gpio_smartbond_init_##id, \
PM_DEVICE_GET(id), \
&gpio_smartbond_data_##id, \
&gpio_smartbond_config_##id, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_smartbond_drv_api_funcs);
DT_INST_FOREACH_STATUS_OKAY(GPIO_SMARTBOND_DEVICE)
``` | /content/code_sandbox/drivers/gpio/gpio_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,411 |
```objective-c
/*
* Xilinx Processor System MIO / EMIO GPIO controller driver
*
* Driver private data declarations, GPIO bank module
*
*/
#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
/*
* Register address calculation macros
* Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
*/
#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_conf->base_addr\
+ ((uint32_t)dev_conf->bank_index * 0x8))
#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\
+ ((uint32_t)dev_conf->bank_index * 0x8))
#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\
+ ((uint32_t)dev_conf->bank_index * 0x4))
#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\
+ ((uint32_t)dev_conf->bank_index * 0x4))
#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_conf->base_addr + 0x20C)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_conf->base_addr + 0x210)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_conf->base_addr + 0x214)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_conf->base_addr + 0x218)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_conf->base_addr + 0x21C)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_conf->base_addr + 0x220)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_conf->base_addr + 0x224)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
/**
* @brief Run-time modifiable device data structure.
*
* This struct contains all data of a PS MIO / EMIO GPIO bank
* which is modifiable at run-time, such as the configuration
* parameters and current values of each individual pin belonging
* to the respective bank.
*/
struct gpio_xlnx_ps_bank_dev_data {
struct gpio_driver_data common;
sys_slist_t callbacks;
};
/**
* @brief Constant device configuration data structure.
*
* This struct contains all data of a PS MIO / EMIO GPIO bank
* which is required for proper operation (such as base memory
* addresses etc.) which don't have to and therefore cannot be
* modified at run-time.
*/
struct gpio_xlnx_ps_bank_dev_cfg {
struct gpio_driver_config common;
uint32_t base_addr;
uint8_t bank_index;
};
#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ */
``` | /content/code_sandbox/drivers/gpio/gpio_xlnx_ps_bank.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 824 |
```unknown
# PCA953X GPIO configuration options
menuconfig GPIO_PCA953X
bool "PCA953X I2C GPIO chip"
default y
depends on DT_HAS_TI_TCA9538_ENABLED
select I2C
help
Enable driver for PCA953X I2C GPIO chip.
if GPIO_PCA953X
config GPIO_PCA953X_INIT_PRIORITY
int "Init priority"
default 70
help
Device driver initialization priority.
endif # GPIO_PCA953X
``` | /content/code_sandbox/drivers/gpio/Kconfig.pca953x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
# Infineon CAT1 GPIO configuration options
# an affiliate of Cypress Semiconductor Corporation
config GPIO_INFINEON_CAT1
bool "Infineon CAT1 GPIO driver"
default y
depends on DT_HAS_INFINEON_CAT1_GPIO_ENABLED
help
Enable support for Infineon CAT1 GPIO controllers.
``` | /content/code_sandbox/drivers/gpio/Kconfig.ifx_cat1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# XMC4XXX GPIO configuration
#
config GPIO_XMC4XXX
bool "XMC4XXX GPIO driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_GPIO_ENABLED
help
Enable GPIO driver for XMC4XXX line of MCUs
``` | /content/code_sandbox/drivers/gpio/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_gpio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h>
#include <soc.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "soc_gpio.h"
#include "soc_miwu.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_npcx, LOG_LEVEL_ERR);
/* GPIO module instances */
#define NPCX_GPIO_DEV(inst) DEVICE_DT_INST_GET(inst),
static const struct device *const gpio_devs[] = {
DT_INST_FOREACH_STATUS_OKAY(NPCX_GPIO_DEV)
};
/* Driver config */
struct gpio_npcx_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
/* GPIO controller base address */
uintptr_t base;
/* IO port */
int port;
/* Mapping table between gpio bits and wui */
struct npcx_wui wui_maps[NPCX_GPIO_PORT_PIN_NUM];
/* Mapping table between gpio bits and lvol */
struct npcx_lvol lvol_maps[NPCX_GPIO_PORT_PIN_NUM];
};
/* Driver data */
struct gpio_npcx_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
};
/* Driver convenience defines */
#define HAL_INSTANCE(dev) \
((struct gpio_reg *)((const struct gpio_npcx_config *)(dev)->config)->base)
/* Platform specific GPIO functions */
const struct device *npcx_get_gpio_dev(int port)
{
if (port >= ARRAY_SIZE(gpio_devs)) {
return NULL;
}
return gpio_devs[port];
}
void npcx_gpio_enable_io_pads(const struct device *dev, int pin)
{
const struct gpio_npcx_config *const config = dev->config;
const struct npcx_wui *io_wui = &config->wui_maps[pin];
if (io_wui->table == NPCX_MIWU_TABLE_NONE) {
LOG_ERR("Cannot enable GPIO(%x, %d) pad", config->port, pin);
return;
}
/*
* If this pin is configured as a GPIO interrupt source, do not
* implement bypass. Or ec cannot wake up via this event.
*/
if (pin < NPCX_GPIO_PORT_PIN_NUM && !npcx_miwu_irq_get_state(io_wui)) {
npcx_miwu_io_enable(io_wui);
}
}
void npcx_gpio_disable_io_pads(const struct device *dev, int pin)
{
const struct gpio_npcx_config *const config = dev->config;
const struct npcx_wui *io_wui = &config->wui_maps[pin];
if (io_wui->table == NPCX_MIWU_TABLE_NONE) {
LOG_ERR("Cannot disable GPIO(%x, %d) pad", config->port, pin);
return;
}
/*
* If this pin is configured as a GPIO interrupt source, do not
* implement bypass. Or ec cannot wake up via this event.
*/
if (pin < NPCX_GPIO_PORT_PIN_NUM && !npcx_miwu_irq_get_state(io_wui)) {
npcx_miwu_io_disable(io_wui);
}
}
/* GPIO api functions */
static int gpio_npcx_config(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_npcx_config *const config = dev->config;
const struct npcx_lvol *lvol = &config->lvol_maps[pin];
struct gpio_reg *const inst = HAL_INSTANCE(dev);
uint32_t mask = BIT(pin);
/* Don't support simultaneous in/out mode */
if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
return -ENOTSUP;
}
/* Don't support "open source" mode */
if (((flags & GPIO_SINGLE_ENDED) != 0) &&
((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
return -ENOTSUP;
}
/*
* Configure pin as input, if requested. Output is configured only
* after setting all other attributes, so as not to create a
* temporary incorrect logic state 0:input 1:output
*/
if ((flags & GPIO_OUTPUT) == 0) {
inst->PDIR &= ~mask;
}
/* Does this IO pad support low-voltage input (1.8V) detection? */
if (lvol->ctrl != NPCX_DT_LVOL_CTRL_NONE) {
gpio_flags_t volt = flags & NPCX_GPIO_VOLTAGE_MASK;
/*
* If this IO pad is configured for low-voltage input detection,
* the related drive type must select to open-drain also.
*/
if (volt == NPCX_GPIO_VOLTAGE_1P8) {
flags |= GPIO_OPEN_DRAIN;
npcx_lvol_set_detect_level(lvol->ctrl, lvol->bit, true);
} else {
npcx_lvol_set_detect_level(lvol->ctrl, lvol->bit, false);
}
}
/* Select open drain 0:push-pull 1:open-drain */
if ((flags & GPIO_OPEN_DRAIN) != 0) {
inst->PTYPE |= mask;
} else {
inst->PTYPE &= ~mask;
}
/* Select pull-up/down of GPIO 0:pull-up 1:pull-down */
if ((flags & GPIO_PULL_UP) != 0) {
inst->PPUD &= ~mask;
inst->PPULL |= mask;
} else if ((flags & GPIO_PULL_DOWN) != 0) {
inst->PPUD |= mask;
inst->PPULL |= mask;
} else {
/* disable pull down/up */
inst->PPULL &= ~mask;
}
/* Set level 0:low 1:high */
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
inst->PDOUT |= mask;
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
inst->PDOUT &= ~mask;
}
/* Configure pin as output, if requested 0:input 1:output */
if ((flags & GPIO_OUTPUT) != 0) {
inst->PDIR |= mask;
}
return 0;
}
#ifdef CONFIG_GPIO_GET_CONFIG
static int gpio_npcx_pin_get_config(const struct device *port, gpio_pin_t pin,
gpio_flags_t *out_flags)
{
const struct gpio_npcx_config *const config = port->config;
const struct npcx_lvol *lvol = &config->lvol_maps[pin];
struct gpio_reg *const inst = HAL_INSTANCE(port);
uint32_t mask = BIT(pin);
gpio_flags_t flags = 0;
/* 0:input 1:output */
if (inst->PDIR & mask) {
flags |= GPIO_OUTPUT;
/* 0:push-pull 1:open-drain */
if (inst->PTYPE & mask) {
flags |= GPIO_OPEN_DRAIN;
}
/* 0:low 1:high */
if (inst->PDOUT & mask) {
flags |= GPIO_OUTPUT_HIGH;
} else {
flags |= GPIO_OUTPUT_LOW;
}
} else {
flags |= GPIO_INPUT;
/* 0:disabled 1:enabled pull */
if (inst->PPULL & mask) {
/* 0:pull-up 1:pull-down */
if (inst->PPUD & mask) {
flags |= GPIO_PULL_DOWN;
} else {
flags |= GPIO_PULL_UP;
}
}
}
/* Enable low-voltage detection? */
if (lvol->ctrl != NPCX_DT_LVOL_CTRL_NONE &&
npcx_lvol_get_detect_level(lvol->ctrl, lvol->bit)) {
flags |= NPCX_GPIO_VOLTAGE_1P8;
};
*out_flags = flags;
return 0;
}
#endif
static int gpio_npcx_port_get_raw(const struct device *dev,
gpio_port_value_t *value)
{
struct gpio_reg *const inst = HAL_INSTANCE(dev);
/* Get raw bits of GPIO input registers */
*value = inst->PDIN;
return 0;
}
static int gpio_npcx_port_set_masked_raw(const struct device *dev,
gpio_port_pins_t mask,
gpio_port_value_t value)
{
struct gpio_reg *const inst = HAL_INSTANCE(dev);
uint8_t out = inst->PDOUT;
inst->PDOUT = ((out & ~mask) | (value & mask));
return 0;
}
static int gpio_npcx_port_set_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
struct gpio_reg *const inst = HAL_INSTANCE(dev);
/* Set raw bits of GPIO output registers */
inst->PDOUT |= mask;
return 0;
}
static int gpio_npcx_port_clear_bits_raw(const struct device *dev,
gpio_port_pins_t mask)
{
struct gpio_reg *const inst = HAL_INSTANCE(dev);
/* Clear raw bits of GPIO output registers */
inst->PDOUT &= ~mask;
return 0;
}
static int gpio_npcx_port_toggle_bits(const struct device *dev,
gpio_port_pins_t mask)
{
struct gpio_reg *const inst = HAL_INSTANCE(dev);
/* Toggle raw bits of GPIO output registers */
inst->PDOUT ^= mask;
return 0;
}
static int gpio_npcx_pin_interrupt_configure(const struct device *dev,
gpio_pin_t pin,
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_npcx_config *const config = dev->config;
if (config->wui_maps[pin].table == NPCX_MIWU_TABLE_NONE) {
LOG_ERR("Cannot configure GPIO(%x, %d)", config->port, pin);
return -EINVAL;
}
LOG_DBG("pin_int_conf (%d, %d) match (%d, %d, %d)!!!",
config->port, pin, config->wui_maps[pin].table,
config->wui_maps[pin].group,
config->wui_maps[pin].bit);
#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
if (mode == GPIO_INT_MODE_DISABLE_ONLY) {
npcx_miwu_irq_disable(&config->wui_maps[pin]);
return 0;
} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
npcx_miwu_irq_enable(&config->wui_maps[pin]);
return 0;
}
#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
/* Disable irq of wake-up input io-pads before configuring them */
npcx_miwu_irq_disable(&config->wui_maps[pin]);
/* Configure and enable interrupt? */
if (mode != GPIO_INT_MODE_DISABLED) {
enum miwu_int_mode miwu_mode;
enum miwu_int_trig miwu_trig;
int ret = 0;
/* Determine interrupt is level or edge mode? */
if (mode == GPIO_INT_MODE_EDGE) {
miwu_mode = NPCX_MIWU_MODE_EDGE;
} else {
miwu_mode = NPCX_MIWU_MODE_LEVEL;
}
/* Determine trigger mode is low, high or both? */
if (trig == GPIO_INT_TRIG_LOW) {
miwu_trig = NPCX_MIWU_TRIG_LOW;
} else if (trig == GPIO_INT_TRIG_HIGH) {
miwu_trig = NPCX_MIWU_TRIG_HIGH;
} else if (trig == GPIO_INT_TRIG_BOTH) {
miwu_trig = NPCX_MIWU_TRIG_BOTH;
} else {
LOG_ERR("Invalid interrupt trigger type %d", trig);
return -EINVAL;
}
/* Call MIWU routine to setup interrupt configuration */
ret = npcx_miwu_interrupt_configure(&config->wui_maps[pin],
miwu_mode, miwu_trig);
if (ret != 0) {
LOG_ERR("Configure MIWU interrupt failed");
return ret;
}
/* Enable it after configuration is completed */
npcx_miwu_irq_enable(&config->wui_maps[pin]);
}
return 0;
}
static int gpio_npcx_manage_callback(const struct device *dev,
struct gpio_callback *callback, bool set)
{
const struct gpio_npcx_config *const config = dev->config;
struct miwu_callback *miwu_cb = (struct miwu_callback *)callback;
int pin = find_lsb_set(callback->pin_mask) - 1;
/* pin_mask should not be zero */
if (pin < 0) {
return -EINVAL;
}
/* Has the IO pin valid MIWU input source? */
if (config->wui_maps[pin].table == NPCX_MIWU_TABLE_NONE) {
LOG_ERR("Cannot manage GPIO(%x, %d) callback!", config->port,
pin);
return -EINVAL;
}
/* Initialize WUI information in unused bits field */
npcx_miwu_init_gpio_callback(miwu_cb, &config->wui_maps[pin],
config->port);
/* Insert or remove a IO callback which being called in MIWU ISRs */
return npcx_miwu_manage_callback(miwu_cb, set);
}
/* GPIO driver registration */
static const struct gpio_driver_api gpio_npcx_driver = {
.pin_configure = gpio_npcx_config,
#ifdef CONFIG_GPIO_GET_CONFIG
.pin_get_config = gpio_npcx_pin_get_config,
#endif
.port_get_raw = gpio_npcx_port_get_raw,
.port_set_masked_raw = gpio_npcx_port_set_masked_raw,
.port_set_bits_raw = gpio_npcx_port_set_bits_raw,
.port_clear_bits_raw = gpio_npcx_port_clear_bits_raw,
.port_toggle_bits = gpio_npcx_port_toggle_bits,
.pin_interrupt_configure = gpio_npcx_pin_interrupt_configure,
.manage_callback = gpio_npcx_manage_callback,
};
int gpio_npcx_init(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
#define NPCX_GPIO_DEVICE_INIT(inst) \
static const struct gpio_npcx_config gpio_npcx_cfg_##inst = { \
.common = { \
.port_pin_mask = \
GPIO_PORT_PIN_MASK_FROM_NGPIOS(NPCX_GPIO_PORT_PIN_NUM),\
}, \
.base = DT_INST_REG_ADDR(inst), \
.port = inst, \
.wui_maps = NPCX_DT_WUI_ITEMS_LIST(inst), \
.lvol_maps = NPCX_DT_LVOL_ITEMS_LIST(inst), \
}; \
BUILD_ASSERT(NPCX_DT_WUI_ITEMS_LEN(inst) == NPCX_GPIO_PORT_PIN_NUM, \
"size of prop. wui-maps must equal to pin number!"); \
BUILD_ASSERT(NPCX_DT_LVOL_ITEMS_LEN(inst) == NPCX_GPIO_PORT_PIN_NUM, \
"size of prop. lvol-maps must equal to pin number!"); \
\
static struct gpio_npcx_data gpio_npcx_data_##inst; \
\
DEVICE_DT_INST_DEFINE(inst, \
gpio_npcx_init, \
NULL, \
&gpio_npcx_data_##inst, \
&gpio_npcx_cfg_##inst, \
PRE_KERNEL_1, \
CONFIG_GPIO_INIT_PRIORITY, \
&gpio_npcx_driver);
DT_INST_FOREACH_STATUS_OKAY(NPCX_GPIO_DEVICE_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_npcx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,365 |
```unknown
# NEORV32 GPIO configuration options
config GPIO_NEORV32
bool "NEORV32 GPIO driver"
default y
depends on DT_HAS_NEORV32_GPIO_ENABLED
depends on SYSCON
help
Enable NEORV32 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.neorv32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Atmel SAM0 GPIO configuration options
config GPIO_SAM0
bool "Atmel SAM0 GPIO (PORT) driver"
default y
depends on DT_HAS_ATMEL_SAM0_GPIO_ENABLED
help
Enable support for the Atmel SAM0 'PORT' GPIO controllers.
``` | /content/code_sandbox/drivers/gpio/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
# ADS114S0x GPIO configuration options
menuconfig GPIO_ADS114S0X
bool "ADS114S0x GPIO driver"
default y
depends on DT_HAS_TI_ADS114S0X_GPIO_ENABLED
depends on ADC_ADS114S0X_GPIO
help
Enable GPIO driver for ADS114S0x.
The ADS114S0x is a multi-channel analog frontend (AFE).
The GPIO port of the ADS114S0x (GPIO0 to GPIO3) is exposed as a
GPIO controller driver with read/write support.
config GPIO_ADS114S0X_INIT_PRIORITY
int "Driver init priority"
default 99
depends on GPIO_ADS114S0X
help
Device driver initialization priority. This driver must be
initialized after the ADS114S0x ADC driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.ads114s0x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 179 |
```unknown
# LMP90xxx GPIO configuration options
menuconfig GPIO_LMP90XXX
bool "LMP90xxx GPIO driver"
default y
depends on DT_HAS_TI_LMP90XXX_GPIO_ENABLED
depends on ADC_LMP90XXX_GPIO
help
Enable GPIO driver for LMP90xxx.
The LMP90xxx is a multi-channel, low power sensor analog
frontend (AFE).
The GPIO port of the LMP90xxx (D6 to D0) is exposed as a
GPIO controller driver with read/write support.
config GPIO_LMP90XXX_INIT_PRIORITY
int "Driver init priority"
default 99
depends on GPIO_LMP90XXX
help
Device driver initialization priority. This driver must be
initialized after the LMP90xxx ADC driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.lmp90xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```unknown
config GPIO_ENE_KB1200
bool "ENE KB1200 GPIO Driver"
default y
depends on DT_HAS_ENE_KB1200_GPIO_ENABLED
help
Enable support for the kb1200 GPIO controllers.
``` | /content/code_sandbox/drivers/gpio/Kconfig.ene | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
# Telink B91 GPIO configuration options
config GPIO_TELINK_B91
bool "Telink B91 GPIO driver"
default y
depends on DT_HAS_TELINK_B91_GPIO_ENABLED
help
Enable the B91 GPIO driver.
``` | /content/code_sandbox/drivers/gpio/Kconfig.b91 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
/**
* @file File that collects common data and configs for RS1718S chip. The file
* doesn't provide any API itself. The feature-specific API should be provided
* in separated files e.g. GPIO API.
*
* This file is placed in drivers/gpio directory, because GPIO is only one
* supported feature at the moment. It can be move to tcpc dir in the future.
*/
#define DT_DRV_COMPAT richtek_rt1718s
#include "gpio_rt1718s.h"
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util_macro.h>
LOG_MODULE_REGISTER(gpio_rt1718s, CONFIG_GPIO_LOG_LEVEL);
static void rt1718s_alert_callback(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
ARG_UNUSED(pins);
struct rt1718s_data *data = CONTAINER_OF(cb, struct rt1718s_data, gpio_cb);
k_work_submit(&data->alert_worker);
}
static void rt1718s_alert_worker(struct k_work *work)
{
struct rt1718s_data *const data = CONTAINER_OF(work, struct rt1718s_data, alert_worker);
const struct device *const dev = data->dev;
const struct rt1718s_config *const config = dev->config;
uint16_t alert, mask;
do {
/* Read alert and mask */
k_sem_take(&data->lock_tcpci, K_FOREVER);
if (rt1718s_reg_burst_read(dev, RT1718S_REG_ALERT, (uint8_t *)&alert,
sizeof(alert)) ||
rt1718s_reg_burst_read(dev, RT1718S_REG_ALERT_MASK, (uint8_t *)&mask,
sizeof(mask))) {
k_sem_give(&data->lock_tcpci);
LOG_ERR("i2c access failed");
continue;
}
/* Content of the alert and alert mask registers are
* defined by the TCPCI specification - "A masked
* register will still indicate in the ALERT register,
* but shall not set the Alert# pin low"
*/
alert &= mask;
if (alert) {
/* Clear all alert bits that causes the interrupt */
if (rt1718s_reg_burst_write(dev, RT1718S_REG_ALERT, (uint8_t *)&alert,
sizeof(alert))) {
k_sem_give(&data->lock_tcpci);
LOG_ERR("i2c access failed");
continue;
}
}
k_sem_give(&data->lock_tcpci);
/* There are a few sources of the vendor
* defined alert for the RT1718S, but handle
* only GPIO at the moment.
*/
if (alert & RT1718S_REG_ALERT_VENDOR_DEFINED_ALERT) {
rt1718s_gpio_alert_handler(dev);
}
/* While the interrupt signal is still active, we have more work to do. */
} while (gpio_pin_get_dt(&config->irq_gpio));
}
static int rt1718s_init(const struct device *dev)
{
const struct rt1718s_config *const config = dev->config;
struct rt1718s_data *data = dev->data;
int ret;
/* Check I2C is ready */
if (!device_is_ready(config->i2c_dev.bus)) {
LOG_ERR("%s device not ready", config->i2c_dev.bus->name);
return -ENODEV;
}
k_sem_init(&data->lock_tcpci, 1, 1);
if (IS_ENABLED(CONFIG_GPIO_RT1718S_INTERRUPT)) {
if (!gpio_is_ready_dt(&config->irq_gpio)) {
LOG_ERR("%s device not ready", config->irq_gpio.port->name);
return -ENODEV;
}
/* Set the interrupt pin for handling the alert */
k_work_init(&data->alert_worker, rt1718s_alert_worker);
gpio_pin_configure_dt(&config->irq_gpio, GPIO_INPUT);
gpio_init_callback(&data->gpio_cb, rt1718s_alert_callback,
BIT(config->irq_gpio.pin));
ret = gpio_add_callback(config->irq_gpio.port, &data->gpio_cb);
if (ret < 0) {
return ret;
}
gpio_pin_interrupt_configure_dt(&config->irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
}
return 0;
}
#define CHECK_PORT_DEVICE(node_id) \
COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(richtek_rt1718s_gpio_port), DEVICE_DT_GET(node_id), \
())
#define IRQ_GPIO(inst) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, irq_gpios), \
(.irq_gpio = GPIO_DT_SPEC_INST_GET(inst, irq_gpios)), ())
#define GET_PORT_DEVICE(inst) DT_INST_FOREACH_CHILD_STATUS_OKAY(inst, CHECK_PORT_DEVICE)
#define GPIO_RT1718S_DEVICE_INSTANCE(inst) \
static const struct rt1718s_config rt1718s_cfg_##inst = { \
.i2c_dev = I2C_DT_SPEC_INST_GET(inst), \
.gpio_port_dev = GET_PORT_DEVICE(inst), \
IRQ_GPIO(inst) \
}; \
static struct rt1718s_data rt1718s_data_##inst = { \
.dev = DEVICE_DT_INST_GET(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, rt1718s_init, NULL, &rt1718s_data_##inst, &rt1718s_cfg_##inst, \
POST_KERNEL, CONFIG_RT1718S_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(GPIO_RT1718S_DEVICE_INSTANCE)
``` | /content/code_sandbox/drivers/gpio/gpio_rt1718s.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,240 |
```unknown
config GPIO_RPI_PICO
default y
depends on DT_HAS_RASPBERRYPI_PICO_GPIO_ENABLED
select PICOSDK_USE_GPIO
bool "Raspberry Pi Pico GPIO driver"
``` | /content/code_sandbox/drivers/gpio/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <helpers/nrfx_ram_ctrl.h>
#define _BUILD_MEM_REGION(node_id) \
{.dt_addr = DT_REG_ADDR(DT_PARENT(node_id)),\
.dt_size = DT_REG_SIZE(DT_PARENT(node_id))}
struct ret_mem_region {
uintptr_t dt_addr;
size_t dt_size;
};
static const struct ret_mem_region ret_mem_regions[] = {
DT_FOREACH_STATUS_OKAY(zephyr_retained_ram, _BUILD_MEM_REGION)
};
static int retained_mem_nrf_init(void)
{
const struct ret_mem_region *rmr;
for (size_t i = 0; i < ARRAY_SIZE(ret_mem_regions); i++) {
rmr = &ret_mem_regions[i];
nrfx_ram_ctrl_retention_enable_set((void *)rmr->dt_addr, rmr->dt_size, true);
}
return 0;
}
SYS_INIT(retained_mem_nrf_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 222 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief GPIO driver for Infineon CAT1 MCU family.
*
* Note:
* - Trigger detection on pin rising or falling edge (GPIO_INT_TRIG_BOTH)
* is not supported in current version of GPIO CAT1 driver.
*/
#define DT_DRV_COMPAT infineon_cat1_gpio
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <cyhal_gpio.h>
#include <cyhal_hwmgr.h>
#include <cy_gpio.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gpio_cat1, CONFIG_GPIO_LOG_LEVEL);
/* Device config structure */
struct gpio_cat1_config {
/* gpio_driver_config needs to be first */
struct gpio_driver_config common;
cyhal_gpio_callback_data_t *cb_data_ptr;
GPIO_PRT_Type *regs;
uint8_t ngpios;
uint8_t intr_priority;
};
/* Data structure */
struct gpio_cat1_data {
/* gpio_driver_data needs to be first */
struct gpio_driver_data common;
/* device's owner of this data */
const struct device *dev;
/* callbacks list */
sys_slist_t callbacks;
};
/* Get port number by calculation difference from current port address minus
* GPIO base address divided by GPIO structure size.
*/
#define GET_PORT_NUM(dev) \
(((uint32_t) ((const struct gpio_cat1_config *const) \
(dev)->config)->regs - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE)
#define GET_DEV_OBJ_FROM_LIST(i, _) \
DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio_prt##i))
/* Map port number to device object */
static const struct device *const port_dev_obj[IOSS_GPIO_GPIO_PORT_NR] = {
/* the integer used as the first variable in listify is equivalent to
* IOSS_GPIO_GPIO_PORT_NR for the respective categories, but using
* the macro in LISTIFY causes build failures
*/
#if CONFIG_SOC_FAMILY_INFINEON_CAT1A
LISTIFY(15, GET_DEV_OBJ_FROM_LIST, (,))
#elif CONFIG_SOC_FAMILY_INFINEON_CAT1B
LISTIFY(6, GET_DEV_OBJ_FROM_LIST, (,))
#endif
};
static int gpio_cat1_configure(const struct device *dev,
gpio_pin_t pin, gpio_flags_t flags)
{
cy_rslt_t status;
cyhal_gpio_t gpio_pin = CYHAL_GET_GPIO(GET_PORT_NUM(dev), pin);
cyhal_gpio_drive_mode_t gpio_mode = CYHAL_GPIO_DRIVE_NONE;
cyhal_gpio_direction_t gpio_dir = CYHAL_GPIO_DIR_INPUT;
bool pin_val = false;
switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
case GPIO_INPUT:
gpio_dir = CYHAL_GPIO_DIR_INPUT;
if ((flags & GPIO_PULL_UP) && (flags & GPIO_PULL_DOWN)) {
gpio_mode = CYHAL_GPIO_DRIVE_PULLUPDOWN;
} else if (flags & GPIO_PULL_UP) {
gpio_mode = CYHAL_GPIO_DRIVE_PULLUP;
pin_val = true;
} else if (flags & GPIO_PULL_DOWN) {
gpio_mode = CYHAL_GPIO_DRIVE_PULLDOWN;
} else {
gpio_mode = CYHAL_GPIO_DRIVE_NONE;
}
break;
case GPIO_OUTPUT:
gpio_dir = CYHAL_GPIO_DIR_OUTPUT;
if (flags & GPIO_SINGLE_ENDED) {
if (flags & GPIO_LINE_OPEN_DRAIN) {
gpio_mode = CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW;
pin_val = true;
} else {
gpio_mode = CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH;
pin_val = false;
}
} else {
gpio_mode = CYHAL_GPIO_DRIVE_STRONG;
pin_val = (flags & GPIO_OUTPUT_INIT_HIGH) ? true : false;
}
break;
case GPIO_DISCONNECTED:
/* Handle this after calling cyhal_gpio_init(), otherwise it will cause an assert
* from HAL for freeing an uninitialized pin
*/
break;
default:
return -ENOTSUP;
}
status = cyhal_gpio_init(gpio_pin, gpio_dir, gpio_mode, pin_val);
/* If the gpio requested resource is already in use, try to free and
* initialize again
*/
if (status == CYHAL_HWMGR_RSLT_ERR_INUSE) {
cyhal_gpio_free(gpio_pin);
status = cyhal_gpio_init(gpio_pin, gpio_dir, gpio_mode, pin_val);
}
if (flags & GPIO_DISCONNECTED) {
cyhal_gpio_free(gpio_pin);
}
return (status == CY_RSLT_SUCCESS) ? 0 : -EIO;
}
static int gpio_cat1_port_get_raw(const struct device *dev,
uint32_t *value)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
*value = GPIO_PRT_IN(base);
return 0;
}
static int gpio_cat1_port_set_masked_raw(const struct device *dev,
uint32_t mask, uint32_t value)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
GPIO_PRT_OUT(base) = (GPIO_PRT_OUT(base) & ~mask) | (mask & value);
return 0;
}
static int gpio_cat1_port_set_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
GPIO_PRT_OUT_SET(base) = mask;
return 0;
}
static int gpio_cat1_port_clear_bits_raw(const struct device *dev,
uint32_t mask)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
GPIO_PRT_OUT_CLR(base) = mask;
return 0;
}
static int gpio_cat1_port_toggle_bits(const struct device *dev,
uint32_t mask)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
GPIO_PRT_OUT_INV(base) = mask;
return 0;
}
static uint32_t gpio_cat1_get_pending_int(const struct device *dev)
{
const struct gpio_cat1_config *const cfg = dev->config;
GPIO_PRT_Type *const base = cfg->regs;
return GPIO_PRT_INTR_MASKED(base);
}
static void gpio_event_callback(void *callback_arg, cyhal_gpio_event_t event)
{
ARG_UNUSED(event);
uint32_t port_num = CYHAL_GET_PORT((uint32_t) callback_arg);
uint32_t pin_num = CYHAL_GET_PIN((uint32_t) callback_arg);
const struct device *dev = port_dev_obj[port_num];
/* Goes through and fires callback from a callback list */
if (dev) {
gpio_fire_callbacks(&((struct gpio_cat1_data *const)(dev)->data)->callbacks,
dev, 1 << pin_num);
}
/* NOTE: cyhal gpio handles cleaning of interrupts */
}
static int gpio_cat1_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
enum gpio_int_mode mode, enum gpio_int_trig trig)
{
const struct gpio_cat1_config *const cfg = dev->config;
cyhal_gpio_callback_data_t *cb_data_ptr = cfg->cb_data_ptr;
cyhal_gpio_event_t event = CYHAL_GPIO_IRQ_NONE;
/* Level interrupts (GPIO_INT_MODE_LEVEL) is not supported */
if (mode == GPIO_INT_MODE_LEVEL) {
return -ENOTSUP;
}
switch (trig) {
case GPIO_INT_TRIG_LOW:
event = CYHAL_GPIO_IRQ_FALL;
break;
case GPIO_INT_TRIG_HIGH:
event = CYHAL_GPIO_IRQ_RISE;
break;
case GPIO_INT_TRIG_BOTH:
/* Trigger detection on pin rising or falling edge (GPIO_INT_TRIG_BOTH)
* is not supported. Refer to SWINTEGRATION-696
*/
/* event = CYHAL_GPIO_IRQ_BOTH; */
return -ENOTSUP;
default:
return -ENOTSUP;
}
cyhal_gpio_t gpio_pin = CYHAL_GET_GPIO(GET_PORT_NUM(dev), pin);
/* Find index of free callback data structure */
uint32_t index;
for (index = 0u; index < cfg->ngpios; index++) {
if ((cb_data_ptr[index].callback == NULL) || (cb_data_ptr[index].pin == gpio_pin)) {
break;
}
}
if (index != cfg->ngpios) {
/* Store callback data: gpio callback and gpio device driver handle */
cb_data_ptr[index].callback = &gpio_event_callback;
cb_data_ptr[index].callback_arg = (void *)(gpio_pin);
/* Register/clear a callback handler for pin events */
cyhal_gpio_register_callback(gpio_pin, (mode == GPIO_INT_MODE_DISABLED) ?
NULL : &cb_data_ptr[index]);
/* Enable/disable the specified GPIO event */
cyhal_gpio_enable_event(gpio_pin, event, cfg->intr_priority,
(mode == GPIO_INT_MODE_DISABLED) ? false : true);
return 0;
} else {
return -EINVAL;
}
}
static int gpio_cat1_manage_callback(const struct device *port,
struct gpio_callback *callback,
bool set)
{
return gpio_manage_callback(&((struct gpio_cat1_data *const)(port)->data)->callbacks,
callback, set);
}
static const struct gpio_driver_api gpio_cat1_api = {
.pin_configure = gpio_cat1_configure,
.port_get_raw = gpio_cat1_port_get_raw,
.port_set_masked_raw = gpio_cat1_port_set_masked_raw,
.port_set_bits_raw = gpio_cat1_port_set_bits_raw,
.port_clear_bits_raw = gpio_cat1_port_clear_bits_raw,
.port_toggle_bits = gpio_cat1_port_toggle_bits,
.pin_interrupt_configure = gpio_cat1_pin_interrupt_configure,
.manage_callback = gpio_cat1_manage_callback,
.get_pending_int = gpio_cat1_get_pending_int,
};
#define GPIO_CAT1_INIT(n) \
\
cyhal_gpio_callback_data_t \
_cat1_gpio##n##_cb_data[DT_INST_PROP(n, ngpios)]; \
\
static const struct gpio_cat1_config _cat1_gpio##n##_config = { \
.common = { \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.intr_priority = DT_INST_IRQ_BY_IDX(n, 0, priority), \
.cb_data_ptr = _cat1_gpio##n##_cb_data, \
.ngpios = DT_INST_PROP(n, ngpios), \
.regs = (GPIO_PRT_Type *)DT_INST_REG_ADDR(n), \
}; \
\
static struct gpio_cat1_data _cat1_gpio##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, NULL, NULL, &_cat1_gpio##n##_data, \
&_cat1_gpio##n##_config, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&gpio_cat1_api);
DT_INST_FOREACH_STATUS_OKAY(GPIO_CAT1_INIT)
``` | /content/code_sandbox/drivers/gpio/gpio_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,431 |
```c
/*
*
*/
#define DT_DRV_COMPAT nordic_nrf_gpregret
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/retained_mem.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(retained_mem_nrf_gpregret, CONFIG_RETAINED_MEM_LOG_LEVEL);
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct nrf_gpregret_data {
struct k_mutex lock;
};
#endif
struct nrf_gpregret_config {
uint8_t *addr;
size_t size;
};
static inline void nrf_gpregret_lock_take(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct nrf_gpregret_data *data = dev->data;
k_mutex_lock(&data->lock, K_FOREVER);
#else
ARG_UNUSED(dev);
#endif
}
static inline void nrf_gpregret_lock_release(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct nrf_gpregret_data *data = dev->data;
k_mutex_unlock(&data->lock);
#else
ARG_UNUSED(dev);
#endif
}
static int nrf_gpregret_init(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct nrf_gpregret_data *data = dev->data;
k_mutex_init(&data->lock);
#endif
return 0;
}
static ssize_t nrf_gpregret_size(const struct device *dev)
{
const struct nrf_gpregret_config *config = dev->config;
return (ssize_t)config->size;
}
static int nrf_gpregret_read(const struct device *dev, off_t offset, uint8_t *buffer, size_t size)
{
const struct nrf_gpregret_config *config = dev->config;
nrf_gpregret_lock_take(dev);
memcpy(buffer, (config->addr + offset), size);
nrf_gpregret_lock_release(dev);
return 0;
}
static int nrf_gpregret_write(const struct device *dev, off_t offset, const uint8_t *buffer,
size_t size)
{
const struct nrf_gpregret_config *config = dev->config;
nrf_gpregret_lock_take(dev);
memcpy((config->addr + offset), buffer, size);
nrf_gpregret_lock_release(dev);
return 0;
}
static int nrf_gpregret_clear(const struct device *dev)
{
const struct nrf_gpregret_config *config = dev->config;
nrf_gpregret_lock_take(dev);
memset(config->addr, 0, config->size);
nrf_gpregret_lock_release(dev);
return 0;
}
static const struct retained_mem_driver_api nrf_gpregret_api = {
.size = nrf_gpregret_size,
.read = nrf_gpregret_read,
.write = nrf_gpregret_write,
.clear = nrf_gpregret_clear,
};
#define NRF_GPREGRET_DEVICE(inst) \
IF_ENABLED(CONFIG_RETAINED_MEM_MUTEXES, \
(static struct nrf_gpregret_data nrf_gpregret_data_##inst;) \
) \
static const struct nrf_gpregret_config nrf_gpregret_config_##inst = { \
.addr = (uint8_t *)DT_INST_REG_ADDR(inst), \
.size = DT_INST_REG_SIZE(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&nrf_gpregret_init, \
NULL, \
COND_CODE_1(CONFIG_RETAINED_MEM_MUTEXES, \
(&nrf_gpregret_data_##inst), (NULL) \
), \
&nrf_gpregret_config_##inst, \
POST_KERNEL, \
CONFIG_RETAINED_MEM_INIT_PRIORITY, \
&nrf_gpregret_api);
DT_INST_FOREACH_STATUS_OKAY(NRF_GPREGRET_DEVICE)
``` | /content/code_sandbox/drivers/retained_mem/retained_mem_nrf_gpregret.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 858 |
```unknown
config RETAINED_MEM_NRF_GPREGRET
bool "nRF GPREGRET driver"
default y
depends on DT_HAS_NORDIC_NRF_GPREGRET_ENABLED
help
Enable driver for Nordic nRF GPREGRET-based retained memory
register support.
config RETAINED_MEM_NRF_RAM_CTRL
bool "nRF RAM retention driver"
default y
depends on DT_HAS_ZEPHYR_RETAINED_RAM_ENABLED && RETAINED_MEM_ZEPHYR_RAM && POWEROFF
depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF53X || SOC_SERIES_NRF54LX || SOC_SERIES_NRF91X
help
Enable driver for Nordic RAM retention.
``` | /content/code_sandbox/drivers/retained_mem/Kconfig.nrf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_retained_ram
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/retained_mem.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(retained_mem_zephyr_ram, CONFIG_RETAINED_MEM_LOG_LEVEL);
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_ram_data {
struct k_mutex lock;
};
#endif
struct zephyr_retained_mem_ram_config {
uint8_t *address;
size_t size;
};
static inline void zephyr_retained_mem_ram_lock_take(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_ram_data *data = dev->data;
k_mutex_lock(&data->lock, K_FOREVER);
#else
ARG_UNUSED(dev);
#endif
}
static inline void zephyr_retained_mem_ram_lock_release(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_ram_data *data = dev->data;
k_mutex_unlock(&data->lock);
#else
ARG_UNUSED(dev);
#endif
}
static int zephyr_retained_mem_ram_init(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_ram_data *data = dev->data;
k_mutex_init(&data->lock);
#endif
return 0;
}
static ssize_t zephyr_retained_mem_ram_size(const struct device *dev)
{
const struct zephyr_retained_mem_ram_config *config = dev->config;
return (ssize_t)config->size;
}
static int zephyr_retained_mem_ram_read(const struct device *dev, off_t offset, uint8_t *buffer,
size_t size)
{
const struct zephyr_retained_mem_ram_config *config = dev->config;
zephyr_retained_mem_ram_lock_take(dev);
memcpy(buffer, (config->address + offset), size);
zephyr_retained_mem_ram_lock_release(dev);
return 0;
}
static int zephyr_retained_mem_ram_write(const struct device *dev, off_t offset,
const uint8_t *buffer, size_t size)
{
const struct zephyr_retained_mem_ram_config *config = dev->config;
zephyr_retained_mem_ram_lock_take(dev);
memcpy((config->address + offset), buffer, size);
zephyr_retained_mem_ram_lock_release(dev);
return 0;
}
static int zephyr_retained_mem_ram_clear(const struct device *dev)
{
const struct zephyr_retained_mem_ram_config *config = dev->config;
zephyr_retained_mem_ram_lock_take(dev);
memset(config->address, 0, config->size);
zephyr_retained_mem_ram_lock_release(dev);
return 0;
}
static const struct retained_mem_driver_api zephyr_retained_mem_ram_api = {
.size = zephyr_retained_mem_ram_size,
.read = zephyr_retained_mem_ram_read,
.write = zephyr_retained_mem_ram_write,
.clear = zephyr_retained_mem_ram_clear,
};
#define ZEPHYR_RETAINED_MEM_RAM_DEVICE(inst) \
IF_ENABLED(CONFIG_RETAINED_MEM_MUTEXES, \
(static struct zephyr_retained_mem_ram_data \
zephyr_retained_mem_ram_data_##inst;) \
) \
static const struct zephyr_retained_mem_ram_config \
zephyr_retained_mem_ram_config_##inst = { \
.address = (uint8_t *)DT_REG_ADDR(DT_PARENT(DT_INST(inst, DT_DRV_COMPAT))), \
.size = DT_REG_SIZE(DT_PARENT(DT_INST(inst, DT_DRV_COMPAT))), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&zephyr_retained_mem_ram_init, \
NULL, \
COND_CODE_1(CONFIG_RETAINED_MEM_MUTEXES, \
(&zephyr_retained_mem_ram_data_##inst), (NULL) \
), \
&zephyr_retained_mem_ram_config_##inst, \
POST_KERNEL, \
CONFIG_RETAINED_MEM_INIT_PRIORITY, \
&zephyr_retained_mem_ram_api);
DT_INST_FOREACH_STATUS_OKAY(ZEPHYR_RETAINED_MEM_RAM_DEVICE)
``` | /content/code_sandbox/drivers/retained_mem/retained_mem_zephyr_ram.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 961 |
```unknown
config RETAINED_MEM_ZEPHYR_RAM
bool "Generic Zephyr RAM retained memory driver"
default y
depends on DT_HAS_ZEPHYR_RETAINED_RAM_ENABLED
help
Enable driver for retained memory in RAM.
config RETAINED_MEM_ZEPHYR_REG
bool "Generic Zephyr register retained memory driver"
default y
depends on DT_HAS_ZEPHYR_RETAINED_REG_ENABLED
help
Enable driver for retained memory in retained registers.
``` | /content/code_sandbox/drivers/retained_mem/Kconfig.zephyr | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```c
/*
*
*/
#include <zephyr/drivers/retained_mem.h>
#include <zephyr/internal/syscall_handler.h>
static inline ssize_t z_vrfy_retained_mem_size(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_RETAINED_MEM));
return z_impl_retained_mem_size(dev);
}
#include <zephyr/syscalls/retained_mem_size_mrsh.c>
static inline int z_vrfy_retained_mem_read(const struct device *dev, off_t offset,
uint8_t *buffer, size_t size)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_RETAINED_MEM));
K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, size));
return z_impl_retained_mem_read(dev, offset, buffer, size);
}
#include <zephyr/syscalls/retained_mem_read_mrsh.c>
static inline int z_vrfy_retained_mem_write(const struct device *dev, off_t offset,
const uint8_t *buffer, size_t size)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_RETAINED_MEM));
K_OOPS(K_SYSCALL_MEMORY_READ(buffer, size));
return z_impl_retained_mem_write(dev, offset, buffer, size);
}
#include <zephyr/syscalls/retained_mem_write_mrsh.c>
static inline int z_vrfy_retained_mem_clear(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_RETAINED_MEM));
return z_impl_retained_mem_clear(dev);
}
#include <zephyr/syscalls/retained_mem_clear_mrsh.c>
``` | /content/code_sandbox/drivers/retained_mem/retained_mem_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 335 |
```unknown
menuconfig RETAINED_MEM
bool "Retained memory drivers"
help
Enables support for drivers that can retain their data whilst the
device is powered (may be lost in low power states).
if RETAINED_MEM
config RETAINED_MEM_INIT_PRIORITY
int "Retained memory devices init priority"
default 40
help
Retained memory devices initialization priority,
config RETAINED_MEM_MUTEXES
bool
default y
depends on MULTITHREADING
depends on !RETAINED_MEM_MUTEX_FORCE_DISABLE
config RETAINED_MEM_MUTEX_FORCE_DISABLE
bool "Disable retained memory mutex support"
depends on MULTITHREADING
help
Disable use of mutexes which prevent issues with concurrent retained
memory access. This option should only be enabled when retained
memory access is required in an ISR or for special use cases.
module = RETAINED_MEM
module-str = retained_mem
source "subsys/logging/Kconfig.template.log_config"
source "drivers/retained_mem/Kconfig.nrf"
source "drivers/retained_mem/Kconfig.zephyr"
endif # RETAINED_MEM
``` | /content/code_sandbox/drivers/retained_mem/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_retained_reg
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/retained_mem.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(retained_mem_zephyr_reg, CONFIG_RETAINED_MEM_LOG_LEVEL);
struct zephyr_retained_mem_reg_data {
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct k_mutex lock;
#endif
};
struct zephyr_retained_mem_reg_config {
uint8_t *address;
size_t size;
};
static inline void zephyr_retained_mem_reg_lock_take(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_reg_data *data = dev->data;
k_mutex_lock(&data->lock, K_FOREVER);
#else
ARG_UNUSED(dev);
#endif
}
static inline void zephyr_retained_mem_reg_lock_release(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_reg_data *data = dev->data;
k_mutex_unlock(&data->lock);
#else
ARG_UNUSED(dev);
#endif
}
static int zephyr_retained_mem_reg_init(const struct device *dev)
{
#ifdef CONFIG_RETAINED_MEM_MUTEXES
struct zephyr_retained_mem_reg_data *data = dev->data;
k_mutex_init(&data->lock);
#endif
return 0;
}
static ssize_t zephyr_retained_mem_reg_size(const struct device *dev)
{
const struct zephyr_retained_mem_reg_config *config = dev->config;
return (ssize_t)config->size;
}
static int zephyr_retained_mem_reg_read(const struct device *dev, off_t offset, uint8_t *buffer,
size_t size)
{
const struct zephyr_retained_mem_reg_config *config = dev->config;
zephyr_retained_mem_reg_lock_take(dev);
memcpy(buffer, (config->address + offset), size);
zephyr_retained_mem_reg_lock_release(dev);
return 0;
}
static int zephyr_retained_mem_reg_write(const struct device *dev, off_t offset,
const uint8_t *buffer, size_t size)
{
const struct zephyr_retained_mem_reg_config *config = dev->config;
zephyr_retained_mem_reg_lock_take(dev);
memcpy((config->address + offset), buffer, size);
zephyr_retained_mem_reg_lock_release(dev);
return 0;
}
static int zephyr_retained_mem_reg_clear(const struct device *dev)
{
const struct zephyr_retained_mem_reg_config *config = dev->config;
zephyr_retained_mem_reg_lock_take(dev);
memset(config->address, 0, config->size);
zephyr_retained_mem_reg_lock_release(dev);
return 0;
}
static const struct retained_mem_driver_api zephyr_retained_mem_reg_api = {
.size = zephyr_retained_mem_reg_size,
.read = zephyr_retained_mem_reg_read,
.write = zephyr_retained_mem_reg_write,
.clear = zephyr_retained_mem_reg_clear,
};
#define ZEPHYR_RETAINED_MEM_REG_DEVICE(inst) \
static struct zephyr_retained_mem_reg_data zephyr_retained_mem_reg_data_##inst; \
static const struct zephyr_retained_mem_reg_config \
zephyr_retained_mem_reg_config_##inst = { \
.address = (uint8_t *)DT_INST_REG_ADDR(inst), \
.size = DT_INST_REG_SIZE(inst), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&zephyr_retained_mem_reg_init, \
NULL, \
&zephyr_retained_mem_reg_data_##inst, \
&zephyr_retained_mem_reg_config_##inst, \
POST_KERNEL, \
CONFIG_RETAINED_MEM_INIT_PRIORITY, \
&zephyr_retained_mem_reg_api);
DT_INST_FOREACH_STATUS_OKAY(ZEPHYR_RETAINED_MEM_REG_DEVICE)
``` | /content/code_sandbox/drivers/retained_mem/retained_mem_zephyr_reg.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 897 |
```unknown
config CC13XX_CC26XX_RTC_TIMER
bool "TI SimpleLink CC13xx/CC26xx RTC system clock timer"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_RTC_TIMER_ENABLED
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
help
This module implements a kernel device driver for the TI SimpleLink
CC13XX_CC26XX series Real Time Counter and provides the standard
"system clock driver" interfaces.
``` | /content/code_sandbox/drivers/timer/Kconfig.cc13xx_cc26xx_rtc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
#
config AMBIQ_STIMER_TIMER
bool "Ambiq STIMER system clock driver"
default y
depends on DT_HAS_AMBIQ_STIMER_ENABLED
select AMBIQ_HAL
select TICKLESS_CAPABLE
select AMBIQ_HAL_USE_STIMER
help
Ambiq Apollo stimer driver
``` | /content/code_sandbox/drivers/timer/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
#
config MIPS_CP0_TIMER
bool "MIPS CP0 Timer"
depends on MIPS
select TICKLESS_CAPABLE
help
This module implements a kernel device driver for the MIPS CP0 timer.
``` | /content/code_sandbox/drivers/timer/Kconfig.mips_cp0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/irq.h>
#define TIMER_IRQ UTIL_CAT(XCHAL_TIMER, \
UTIL_CAT(CONFIG_XTENSA_TIMER_ID, _INTERRUPT))
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_CYC 0xffffffffu
#define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
#define MIN_DELAY 1000
static struct k_spinlock lock;
static unsigned int last_count;
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = UTIL_CAT(XCHAL_TIMER,
UTIL_CAT(CONFIG_XTENSA_TIMER_ID, _INTERRUPT));
#endif
static void set_ccompare(uint32_t val)
{
__asm__ volatile ("wsr.CCOMPARE" STRINGIFY(CONFIG_XTENSA_TIMER_ID) " %0"
:: "r"(val));
}
static uint32_t ccount(void)
{
uint32_t val;
__asm__ volatile ("rsr.CCOUNT %0" : "=r"(val));
return val;
}
static void ccompare_isr(const void *arg)
{
ARG_UNUSED(arg);
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t curr = ccount();
uint32_t dticks = (curr - last_count) / CYC_PER_TICK;
last_count += dticks * CYC_PER_TICK;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
uint32_t next = last_count + CYC_PER_TICK;
if ((int32_t)(next - curr) < MIN_DELAY) {
next += CYC_PER_TICK;
}
set_ccompare(next);
}
k_spin_unlock(&lock, key);
sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
#if defined(CONFIG_TICKLESS_KERNEL)
ticks = ticks == K_TICKS_FOREVER ? MAX_TICKS : ticks;
ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t curr = ccount(), cyc, adj;
/* Round up to next tick boundary */
cyc = ticks * CYC_PER_TICK;
adj = (curr - last_count) + (CYC_PER_TICK - 1);
if (cyc <= MAX_CYC - adj) {
cyc += adj;
} else {
cyc = MAX_CYC;
}
cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;
cyc += last_count;
if ((cyc - curr) < MIN_DELAY) {
cyc += CYC_PER_TICK;
}
set_ccompare(cyc);
k_spin_unlock(&lock, key);
#endif
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ret = (ccount() - last_count) / CYC_PER_TICK;
k_spin_unlock(&lock, key);
return ret;
}
uint32_t sys_clock_cycle_get_32(void)
{
return ccount();
}
#ifdef CONFIG_SMP
void smp_timer_init(void)
{
set_ccompare(ccount() + CYC_PER_TICK);
irq_enable(TIMER_IRQ);
}
#endif
static int sys_clock_driver_init(void)
{
IRQ_CONNECT(TIMER_IRQ, 0, ccompare_isr, 0, 0);
set_ccompare(ccount() + CYC_PER_TICK);
irq_enable(TIMER_IRQ);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/xtensa_sys_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 851 |
```c
/*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/interrupt_controller/loapic.h>
#include <zephyr/irq.h>
BUILD_ASSERT(!IS_ENABLED(CONFIG_TICKLESS_KERNEL), "this is a tickfull driver");
/*
* Overview:
*
* This driver enables the local APIC as the Zephyr system timer. It supports
* legacy ("tickful") mode only. The driver will work with any APIC that has
* the ARAT "always running APIC timer" feature (CPUID 0x06, EAX bit 2).
*
* Configuration:
*
* CONFIG_APIC_TIMER=y enables this timer driver.
* CONFIG_APIC_TIMER_IRQ=<irq> which IRQ to configure for the timer.
* CONFIG_APIC_TIMER_IRQ_PRIORITY=<p> priority for IRQ_CONNECT()
*
* CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=<hz> must contain the frequency seen
* by the local APIC timer block (before it gets to the timer divider).
*/
/* These should be merged into include/drivers/interrupt_controller/loapic.h. */
#define DCR_DIVIDER_MASK 0x0000000F /* divider bits */
#define DCR_DIVIDER 0x0000000B /* divide by 1 */
#define LVT_MODE_MASK 0x00060000 /* timer mode bits */
#define LVT_MODE 0x00020000 /* periodic mode */
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = CONFIG_APIC_TIMER_IRQ;
#endif
#define CYCLES_PER_TICK \
(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
BUILD_ASSERT(CYCLES_PER_TICK >= 1, "APIC timer: bad CYCLES_PER_TICK");
static volatile uint64_t total_cycles;
static void isr(const void *arg)
{
ARG_UNUSED(arg);
total_cycles += CYCLES_PER_TICK;
sys_clock_announce(1);
}
uint32_t sys_clock_elapsed(void)
{
return 0U;
}
uint64_t sys_clock_cycle_get_64(void)
{
uint32_t ccr_1st, ccr_2nd;
uint64_t cycles;
/*
* We may race with CCR reaching 0 and reloading, and the interrupt
* handler updating total_cycles. Let's make sure we sample everything
* away from this roll-over transition by ensuring consecutive CCR
* values are descending so we're sure the enclosed (volatile)
* total_cycles sample and CCR value are coherent with each other.
*/
do {
ccr_1st = x86_read_loapic(LOAPIC_TIMER_CCR);
cycles = total_cycles;
ccr_2nd = x86_read_loapic(LOAPIC_TIMER_CCR);
} while (ccr_2nd > ccr_1st);
return cycles + (CYCLES_PER_TICK - ccr_2nd);
}
uint32_t sys_clock_cycle_get_32(void)
{
return (uint32_t)sys_clock_cycle_get_64();
}
static int sys_clock_driver_init(void)
{
uint32_t val;
val = x86_read_loapic(LOAPIC_TIMER_CONFIG); /* set divider */
val &= ~DCR_DIVIDER_MASK;
val |= DCR_DIVIDER;
x86_write_loapic(LOAPIC_TIMER_CONFIG, val);
val = x86_read_loapic(LOAPIC_TIMER); /* set timer mode */
val &= ~LVT_MODE_MASK;
val |= LVT_MODE;
x86_write_loapic(LOAPIC_TIMER, val);
/* remember, wiring up the interrupt will mess with the LVT, too */
IRQ_CONNECT(CONFIG_APIC_TIMER_IRQ,
CONFIG_APIC_TIMER_IRQ_PRIORITY,
isr, 0, 0);
x86_write_loapic(LOAPIC_TIMER_ICR, CYCLES_PER_TICK);
irq_enable(CONFIG_APIC_TIMER_IRQ);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/apic_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 895 |
```unknown
config LITEX_TIMER
bool "LiteX Timer"
default y
depends on DT_HAS_LITEX_TIMER0_ENABLED
select TIMER_HAS_64BIT_CYCLE_COUNTER
help
This module implements a kernel device driver for LiteX Timer.
``` | /content/code_sandbox/drivers/timer/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
config MCHP_XEC_RTOS_TIMER
bool "Microchip XEC series RTOS timer"
default y
depends on DT_HAS_MICROCHIP_XEC_RTOS_TIMER_ENABLED
select TICKLESS_CAPABLE
select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
help
This module implements a kernel device driver for the Microchip
XEC series RTOS timer and provides the standard "system clock
driver" interfaces.
``` | /content/code_sandbox/drivers/timer/Kconfig.mchp_xec_rtos | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
choice
prompt "Default System Timer"
default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_ATOM || SOC_LAKEMONT
default APIC_TSC_DEADLINE_TIMER
depends on X86
help
Select Default System Timer.
config HPET_TIMER
bool "HPET timer"
depends on DT_HAS_INTEL_HPET_ENABLED
select IOAPIC
select LOAPIC
imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
help
This option selects High Precision Event Timer (HPET) as a
system timer.
config APIC_TIMER
bool "Local APIC timer"
select LOAPIC
select TIMER_HAS_64BIT_CYCLE_COUNTER
select SYSTEM_CLOCK_LOCK_FREE_COUNT
help
Use the x86 local APIC in periodic mode as the system time
source. NOTE: this probably isn't what you want except on
older or idiosyncratic hardware (or environments like qemu
without complete APIC emulation). Modern hardware will work
better with CONFIG_APIC_TSC_DEADLINE_TIMER.
config APIC_TSC_DEADLINE_TIMER
bool "Local APIC timer using TSC deadline mode"
select LOAPIC
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
help
Extremely simple timer driver based the local APIC TSC
deadline capability. The use of a free-running 64 bit
counter with comparator eliminates almost all edge cases
from the handling, and the near-instruction-cycle resolution
permits effectively unlimited precision where needed (the
limit becomes the CPU time taken to execute the timing
logic). SMP-safe and very fast, this should be the obvious
choice for any x86 device with invariant TSC and TSC
deadline capability.
config APIC_TIMER_TSC
bool "Local APIC timer using TSC time source"
depends on !SMP
select LOAPIC
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
help
If your CPU supports invariant TSC but no TSC deadline capability
then this choice will rely on the TSC as time source and the
local APIC in one-shot mode as the timeout event source.
You must know the ratio of the TSC frequency to the local APIC
timer frequency.
endchoice
if APIC_TIMER
config APIC_TIMER_IRQ
int "Local APIC timer IRQ"
default 24
help
This option specifies the IRQ used by the local APIC timer.
Note: this MUST be set to the index immediately after the
last IO-APIC IRQ (the timer is the first entry in the APIC
local vector table). This footgun is not intended to be
user-configurable and almost certainly should be managed via
a different mechanism.
endif # APIC_TIMER
if APIC_TIMER_TSC
config APIC_TIMER_TSC_N
int "TSC to local APIC timer frequency multiplier (N)"
default 1
config APIC_TIMER_TSC_M
int "TSC to local APIC timer frequency divisor (M)"
default 1
endif # APIC_TIMER_TSC
config APIC_TIMER_IRQ_PRIORITY
int "Local APIC timer interrupt priority"
depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER || APIC_TIMER_TSC
default 4
help
This option specifies the interrupt priority used by the
local APIC timer.
``` | /content/code_sandbox/drivers/timer/Kconfig.x86 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 745 |
```c
/*
*
* Based on riscv_machine_timer.c and xtensa_sys_timer.c
*
*/
#include <limits.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <soc.h>
#include <mips/mipsregs.h>
#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
/ (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
#define MAX_CYC INT_MAX
#define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
#define MIN_DELAY 1000
#define TICKLESS IS_ENABLED(CONFIG_TICKLESS_KERNEL)
static struct k_spinlock lock;
static uint32_t last_count;
static ALWAYS_INLINE void set_cp0_compare(uint32_t time)
{
_mips_write_32bit_c0_register(CP0_COMPARE, time);
}
static ALWAYS_INLINE uint32_t get_cp0_count(void)
{
return _mips_read_32bit_c0_register(CP0_COUNT);
}
static void timer_isr(const void *arg)
{
ARG_UNUSED(arg);
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t now = get_cp0_count();
uint32_t dticks = ((now - last_count) / CYC_PER_TICK);
last_count = now;
if (!TICKLESS) {
uint32_t next = last_count + CYC_PER_TICK;
if (next - now < MIN_DELAY) {
next += CYC_PER_TICK;
}
set_cp0_compare(next);
}
k_spin_unlock(&lock, key);
sys_clock_announce(TICKLESS ? dticks : 1);
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
if (!TICKLESS) {
return;
}
ticks = ticks == K_TICKS_FOREVER ? MAX_TICKS : ticks;
ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t current_count = get_cp0_count();
uint32_t delay_wanted = ticks * CYC_PER_TICK;
/* Round up to next tick boundary. */
uint32_t adj = (current_count - last_count) + (CYC_PER_TICK - 1);
if (delay_wanted <= MAX_CYC - adj) {
delay_wanted += adj;
} else {
delay_wanted = MAX_CYC;
}
delay_wanted = (delay_wanted / CYC_PER_TICK) * CYC_PER_TICK;
if ((int32_t)(delay_wanted + last_count - current_count) < MIN_DELAY) {
delay_wanted += CYC_PER_TICK;
}
set_cp0_compare(delay_wanted + last_count);
k_spin_unlock(&lock, key);
}
uint32_t sys_clock_elapsed(void)
{
if (!TICKLESS) {
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ticks_elapsed = (get_cp0_count() - last_count) / CYC_PER_TICK;
k_spin_unlock(&lock, key);
return ticks_elapsed;
}
uint32_t sys_clock_cycle_get_32(void)
{
return get_cp0_count();
}
static int sys_clock_driver_init(void)
{
IRQ_CONNECT(MIPS_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
last_count = get_cp0_count();
/*
* In a tickless system the first tick might possibly be pushed
* much further into the future than is being done here.
*/
set_cp0_compare(last_count + CYC_PER_TICK);
irq_enable(MIPS_MACHINE_TIMER_IRQ);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/mips_cp0_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 835 |
```unknown
config RV32M1_LPTMR_TIMER
bool "RV32M1 LPTMR system timer driver"
default y
depends on DT_HAS_OPENISA_RV32M1_LPTMR_ENABLED
depends on RV32M1_INTMUX
help
This module implements a kernel device driver for using the LPTMR
peripheral as the system clock. It provides the standard "system clock
driver" interfaces.
``` | /content/code_sandbox/drivers/timer/Kconfig.rv32m1_lptmr | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
config GECKO_BURTC_TIMER
bool "SiLabs Gecko BURTC system clock driver"
depends on SOC_FAMILY_SILABS_S2
depends on DT_HAS_SILABS_GECKO_BURTC_ENABLED
select SOC_GECKO_BURTC
select TICKLESS_CAPABLE
select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
help
If you enable this, BURTC will be used to provide hw_cycles and
kernel ticks instead of Cortex-M SysTick. You need this for system
to be able to keep track of time and wake up from EM2 & EM3 sleep
states.
NOTE:
Using BURTC instead of SysTick has a large impact on kernel timing
precision.
1. You won't be able to use the usual 0.1ms-granularity tickless
scheduling. Kernel tick duration should be at least 6 BURTC clock
cycles, that is ~183 us @ 32768 Hz (LFXO, LFRCO) or
~6 ms @ 1000 Hz (ULFRCO).
2. In general, accuracy of real-time scheduling by kernel will be
degraded: all timeout-based facilities, such as timers, delayable
work, k_sleep, will issue thread wake ups less precisely than when
using SysTick timer.
3. hw_cycles granularity will be equal to 1 BURTC clock, that is
~31 us @ 32768 Hz or ~1 ms @ 1000 Hz. This reduces timing
precision of all code which relies on cycles API, e.g.
k_cycle_get_32() and similar functions.
If unsure, say 'N'.
``` | /content/code_sandbox/drivers/timer/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 369 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/arch/arc/v2/aux_regs.h>
#include <zephyr/irq.h>
/*
* note: This implementation assumes Timer0 is present. Be sure
* to build the ARC CPU with Timer0.
*
* If secureshield is present and secure firmware is configured,
* use secure Timer 0
*/
#ifdef CONFIG_ARC_SECURE_FIRMWARE
#undef _ARC_V2_TMR0_COUNT
#undef _ARC_V2_TMR0_CONTROL
#undef _ARC_V2_TMR0_LIMIT
#define _ARC_V2_TMR0_COUNT _ARC_V2_S_TMR0_COUNT
#define _ARC_V2_TMR0_CONTROL _ARC_V2_S_TMR0_CONTROL
#define _ARC_V2_TMR0_LIMIT _ARC_V2_S_TMR0_LIMIT
#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(sectimer0))
#else
#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(timer0))
#endif
#define _ARC_V2_TMR_CTRL_IE 0x1 /* interrupt enable */
#define _ARC_V2_TMR_CTRL_NH 0x2 /* count only while not halted */
#define _ARC_V2_TMR_CTRL_W 0x4 /* watchdog mode enable */
#define _ARC_V2_TMR_CTRL_IP 0x8 /* interrupt pending flag */
/* Minimum cycles in the future to try to program. */
#define MIN_DELAY 1024
/* arc timer has 32 bit, here use 31 bit to avoid the possible
* overflow,e.g, 0xffffffff + any value will cause overflow
*/
#define COUNTER_MAX 0x7fffffff
#define TIMER_STOPPED 0x0
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
#define TICKLESS (IS_ENABLED(CONFIG_TICKLESS_KERNEL))
#define SMP_TIMER_DRIVER (CONFIG_SMP && CONFIG_MP_MAX_NUM_CPUS > 1)
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = IRQ_TIMER0;
#endif
static struct k_spinlock lock;
#if SMP_TIMER_DRIVER
volatile static uint64_t last_time;
volatile static uint64_t start_time;
#else
static uint32_t last_load;
/*
* This local variable holds the amount of timer cycles elapsed
* and it is updated in timer_int_handler and sys_clock_set_timeout().
*
* Note:
* At an arbitrary point in time the "current" value of the
* HW timer is calculated as:
*
* t = cycle_counter + elapsed();
*/
static uint32_t cycle_count;
/*
* This local variable holds the amount of elapsed HW cycles
* that have been announced to the kernel.
*/
static uint32_t announced_cycles;
/*
* This local variable holds the amount of elapsed HW cycles due to
* timer wraps ('overflows') and is used in the calculation
* in elapsed() function, as well as in the updates to cycle_count.
*
* Note:
* Each time cycle_count is updated with the value from overflow_cycles,
* the overflow_cycles must be reset to zero.
*/
static volatile uint32_t overflow_cycles;
#endif
/**
* @brief Get contents of Timer0 count register
*
* @return Current Timer0 count
*/
static ALWAYS_INLINE uint32_t timer0_count_register_get(void)
{
return z_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
}
/**
* @brief Set Timer0 count register to the specified value
*/
static ALWAYS_INLINE void timer0_count_register_set(uint32_t value)
{
z_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, value);
}
/**
* @brief Get contents of Timer0 control register
*
* @return Contents of Timer0 control register.
*/
static ALWAYS_INLINE uint32_t timer0_control_register_get(void)
{
return z_arc_v2_aux_reg_read(_ARC_V2_TMR0_CONTROL);
}
/**
* @brief Set Timer0 control register to the specified value
*/
static ALWAYS_INLINE void timer0_control_register_set(uint32_t value)
{
z_arc_v2_aux_reg_write(_ARC_V2_TMR0_CONTROL, value);
}
/**
* @brief Get contents of Timer0 limit register
*
* @return Contents of Timer0 limit register.
*/
static ALWAYS_INLINE uint32_t timer0_limit_register_get(void)
{
return z_arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
}
/**
* @brief Set Timer0 limit register to the specified value
*/
static ALWAYS_INLINE void timer0_limit_register_set(uint32_t count)
{
z_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count);
}
#if !SMP_TIMER_DRIVER
/* This internal function calculates the amount of HW cycles that have
* elapsed since the last time the absolute HW cycles counter has been
* updated. 'cycle_count' may be updated either by the ISR, or
* in sys_clock_set_timeout().
*
* Additionally, the function updates the 'overflow_cycles' counter, that
* holds the amount of elapsed HW cycles due to (possibly) multiple
* timer wraps (overflows).
*
* Prerequisites:
* - reprogramming of LIMIT must be clearing the COUNT
* - ISR must be clearing the 'overflow_cycles' counter.
* - no more than one counter-wrap has occurred between
* - the timer reset or the last time the function was called
* - and until the current call of the function is completed.
* - the function is invoked with interrupts disabled.
*/
static uint32_t elapsed(void)
{
uint32_t val, ctrl;
do {
val = timer0_count_register_get();
ctrl = timer0_control_register_get();
} while (timer0_count_register_get() < val);
if (ctrl & _ARC_V2_TMR_CTRL_IP) {
overflow_cycles += last_load;
/* clear the IP bit of the control register */
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH |
_ARC_V2_TMR_CTRL_IE);
/* use sw triggered irq to remember the timer irq request
* which may be cleared by the above operation. when elapsed ()
* is called in timer_int_handler, no need to do this.
*/
if (!z_arc_v2_irq_unit_is_in_isr() ||
z_arc_v2_aux_reg_read(_ARC_V2_ICAUSE) != IRQ_TIMER0) {
z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT,
IRQ_TIMER0);
}
}
return val + overflow_cycles;
}
#endif
/**
* @brief System clock periodic tick handler
*
* This routine handles the system clock tick interrupt. It always
* announces one tick when TICKLESS is not enabled, or multiple ticks
* when TICKLESS is enabled.
*/
static void timer_int_handler(const void *unused)
{
ARG_UNUSED(unused);
uint32_t dticks;
#if defined(CONFIG_SMP) && CONFIG_MP_MAX_NUM_CPUS > 1
uint64_t curr_time;
k_spinlock_key_t key;
/* clear the IP bit of the control register */
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH |
_ARC_V2_TMR_CTRL_IE);
key = k_spin_lock(&lock);
/* gfrc is the wall clock */
curr_time = z_arc_connect_gfrc_read();
dticks = (curr_time - last_time) / CYC_PER_TICK;
/* last_time should be aligned to ticks */
last_time += dticks * CYC_PER_TICK;
k_spin_unlock(&lock, key);
sys_clock_announce(dticks);
#else
/* timer_int_handler may be triggered by timer irq or
* software helper irq
*/
/* irq with higher priority may call sys_clock_set_timeout
* so need a lock here
*/
uint32_t key;
key = arch_irq_lock();
elapsed();
cycle_count += overflow_cycles;
overflow_cycles = 0;
arch_irq_unlock(key);
dticks = (cycle_count - announced_cycles) / CYC_PER_TICK;
announced_cycles += dticks * CYC_PER_TICK;
sys_clock_announce(TICKLESS ? dticks : 1);
#endif
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
/* If the kernel allows us to miss tick announcements in idle,
* then shut off the counter. (Note: we can assume if idle==true
* that interrupts are already disabled)
*/
#if SMP_TIMER_DRIVER
/* as 64-bits GFRC is used as wall clock, it's ok to ignore idle
* systick will not be missed.
* However for single core using 32-bits arc timer, idle cannot
* be ignored, as 32-bits timer will overflow in a not-long time.
*/
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && ticks == K_TICKS_FOREVER) {
timer0_control_register_set(0);
timer0_count_register_set(0);
timer0_limit_register_set(0);
return;
}
#if defined(CONFIG_TICKLESS_KERNEL)
uint32_t delay;
uint32_t key;
ticks = MIN(MAX_TICKS, ticks);
/* Desired delay in the future
* use MIN_DEALY here can trigger the timer
* irq more soon, no need to go to CYC_PER_TICK
* later.
*/
delay = MAX(ticks * CYC_PER_TICK, MIN_DELAY);
key = arch_irq_lock();
timer0_limit_register_set(delay - 1);
timer0_count_register_set(0);
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH |
_ARC_V2_TMR_CTRL_IE);
arch_irq_unlock(key);
#endif
#else
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && idle && ticks == K_TICKS_FOREVER) {
timer0_control_register_set(0);
timer0_count_register_set(0);
timer0_limit_register_set(0);
last_load = TIMER_STOPPED;
return;
}
#if defined(CONFIG_TICKLESS_KERNEL)
uint32_t delay;
uint32_t unannounced;
ticks = MIN(MAX_TICKS, (uint32_t)(MAX((int32_t)(ticks - 1), 0)));
k_spinlock_key_t key = k_spin_lock(&lock);
cycle_count += elapsed();
/* clear counter early to avoid cycle loss as few as possible,
* between cycle_count and clearing 0, few cycles are possible
* to loss
*/
timer0_count_register_set(0);
overflow_cycles = 0U;
/* normal case */
unannounced = cycle_count - announced_cycles;
if ((int32_t)unannounced < 0) {
/* We haven't announced for more than half the 32-bit
* wrap duration, because new timeouts keep being set
* before the existing one fires. Force an announce
* to avoid loss of a wrap event, making sure the
* delay is at least the minimum delay possible.
*/
last_load = MIN_DELAY;
} else {
/* Desired delay in the future */
delay = ticks * CYC_PER_TICK;
/* Round delay up to next tick boundary */
delay += unannounced;
delay = DIV_ROUND_UP(delay, CYC_PER_TICK) * CYC_PER_TICK;
delay -= unannounced;
delay = MAX(delay, MIN_DELAY);
last_load = MIN(delay, MAX_CYCLES);
}
timer0_limit_register_set(last_load - 1);
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
k_spin_unlock(&lock, key);
#endif
#endif
}
uint32_t sys_clock_elapsed(void)
{
if (!TICKLESS) {
return 0;
}
uint32_t cyc;
k_spinlock_key_t key = k_spin_lock(&lock);
#if SMP_TIMER_DRIVER
cyc = (z_arc_connect_gfrc_read() - last_time);
#else
cyc = elapsed() + cycle_count - announced_cycles;
#endif
k_spin_unlock(&lock, key);
return cyc / CYC_PER_TICK;
}
uint32_t sys_clock_cycle_get_32(void)
{
#if SMP_TIMER_DRIVER
return z_arc_connect_gfrc_read() - start_time;
#else
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ret = elapsed() + cycle_count;
k_spin_unlock(&lock, key);
return ret;
#endif
}
#if SMP_TIMER_DRIVER
void smp_timer_init(void)
{
/* set the initial status of timer0 of each slave core
*/
timer0_control_register_set(0);
timer0_count_register_set(0);
timer0_limit_register_set(0);
z_irq_priority_set(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY, 0);
irq_enable(IRQ_TIMER0);
}
#endif
/**
*
* @brief Initialize and enable the system clock
*
* This routine is used to program the ARCv2 timer to deliver interrupts at the
* rate specified via the CYC_PER_TICK.
*
* @return 0
*/
static int sys_clock_driver_init(void)
{
/* ensure that the timer will not generate interrupts */
timer0_control_register_set(0);
#if SMP_TIMER_DRIVER
IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
timer_int_handler, NULL, 0);
timer0_limit_register_set(CYC_PER_TICK - 1);
last_time = z_arc_connect_gfrc_read();
start_time = last_time;
#else
last_load = CYC_PER_TICK;
overflow_cycles = 0;
announced_cycles = 0;
IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
timer_int_handler, NULL, 0);
timer0_limit_register_set(last_load - 1);
#endif
timer0_count_register_set(0);
timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
/* everything has been configured: safe to enable the interrupt */
irq_enable(IRQ_TIMER0);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/arcv2_timer0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,056 |
```c
/*
*/
#include <cpuid.h> /* Header provided by the toolchain. */
#include <zephyr/init.h>
#include <zephyr/arch/x86/cpuid.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/drivers/interrupt_controller/loapic.h>
#include <zephyr/irq.h>
/*
* This driver is selected when either CONFIG_APIC_TIMER_TSC or
* CONFIG_APIC_TSC_DEADLINE_TIMER is selected. The later is preferred over
* the former when the TSC deadline comparator is available.
*/
BUILD_ASSERT((!IS_ENABLED(CONFIG_APIC_TIMER_TSC) &&
IS_ENABLED(CONFIG_APIC_TSC_DEADLINE_TIMER)) ||
(!IS_ENABLED(CONFIG_APIC_TSC_DEADLINE_TIMER) &&
IS_ENABLED(CONFIG_APIC_TIMER_TSC)),
"one of CONFIG_APIC_TIMER_TSC or CONFIG_APIC_TSC_DEADLINE_TIMER must be set");
/*
* If the TSC deadline comparator is not supported then the ICR in one-shot
* mode is used as a fallback method to trigger the next timeout interrupt.
* Those config symbols must then be defined:
*
* CONFIG_APIC_TIMER_TSC_N=<n>
* CONFIG_APIC_TIMER_TSC_M=<m>
*
* These are set to indicate the ratio of the TSC frequency to the local
* APIC timer frequency. This can be found via CPUID 0x15 (n = EBX, m = EAX)
* on most CPUs.
*/
#ifdef CONFIG_APIC_TIMER_TSC
#define APIC_TIMER_TSC_M CONFIG_APIC_TIMER_TSC_M
#define APIC_TIMER_TSC_N CONFIG_APIC_TIMER_TSC_N
#else
#define APIC_TIMER_TSC_M 1
#define APIC_TIMER_TSC_N 1
#endif
#define IA32_TSC_DEADLINE_MSR 0x6e0
#define IA32_TSC_ADJUST_MSR 0x03b
#define CYC_PER_TICK (uint32_t)(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
/* the unsigned long cast limits divisors to native CPU register width */
#define cycle_diff_t unsigned long
#define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
/*
* We have two constraints on the maximum number of cycles we can wait for.
*
* 1) sys_clock_announce() accepts at most INT32_MAX ticks.
*
* 2) The number of cycles between two reports must fit in a cycle_diff_t
* variable before converting it to ticks.
*
* Then:
*
* 3) Pick the smallest between (1) and (2).
*
* 4) Take into account some room for the unavoidable IRQ servicing latency.
* Let's use 3/4 of the max range.
*
* Finally let's add the LSB value to the result so to clear out a bunch of
* consecutive set bits coming from the original max values to produce a
* nicer literal for assembly generation.
*/
#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
#define CYCLES_MAX (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
struct apic_timer_lvt {
uint8_t vector : 8;
uint8_t unused0 : 8;
uint8_t masked : 1;
enum { ONE_SHOT, PERIODIC, TSC_DEADLINE } mode: 2;
uint32_t unused2 : 13;
};
static struct k_spinlock lock;
static uint64_t last_cycle;
static uint64_t last_tick;
static uint32_t last_elapsed;
static union { uint32_t val; struct apic_timer_lvt lvt; } lvt_reg;
static ALWAYS_INLINE uint64_t rdtsc(void)
{
uint32_t hi, lo;
__asm__ volatile("rdtsc" : "=d"(hi), "=a"(lo));
return lo + (((uint64_t)hi) << 32);
}
static inline void wrmsr(int32_t msr, uint64_t val)
{
uint32_t hi = (uint32_t) (val >> 32);
uint32_t lo = (uint32_t) val;
__asm__ volatile("wrmsr" :: "d"(hi), "a"(lo), "c"(msr));
}
static void set_trigger(uint64_t deadline)
{
if (IS_ENABLED(CONFIG_APIC_TSC_DEADLINE_TIMER)) {
wrmsr(IA32_TSC_DEADLINE_MSR, deadline);
} else {
/* use the timer ICR to trigger next interrupt */
uint64_t curr_cycle = rdtsc();
uint64_t delta_cycles = deadline - MIN(deadline, curr_cycle);
uint64_t icr = (delta_cycles * APIC_TIMER_TSC_M) / APIC_TIMER_TSC_N;
/* cap icr to 32 bits, and not zero */
icr = CLAMP(icr, 1, UINT32_MAX);
x86_write_loapic(LOAPIC_TIMER_ICR, icr);
}
}
static void isr(const void *arg)
{
ARG_UNUSED(arg);
k_spinlock_key_t key = k_spin_lock(&lock);
uint64_t curr_cycle = rdtsc();
uint64_t delta_cycles = curr_cycle - last_cycle;
uint32_t delta_ticks = (cycle_diff_t)delta_cycles / CYC_PER_TICK;
last_cycle += (cycle_diff_t)delta_ticks * CYC_PER_TICK;
last_tick += delta_ticks;
last_elapsed = 0;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
uint64_t next_cycle = last_cycle + CYC_PER_TICK;
set_trigger(next_cycle);
}
k_spin_unlock(&lock, key);
sys_clock_announce(delta_ticks);
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint64_t next_cycle;
if (ticks == K_TICKS_FOREVER) {
next_cycle = last_cycle + CYCLES_MAX;
} else {
next_cycle = (last_tick + last_elapsed + ticks) * CYC_PER_TICK;
if ((next_cycle - last_cycle) > CYCLES_MAX) {
next_cycle = last_cycle + CYCLES_MAX;
}
}
/*
* Interpreted strictly, the IA SDM description of the
* TSC_DEADLINE MSR implies that it will trigger an immediate
* interrupt if we try to set an expiration across the 64 bit
* rollover. Unfortunately there's no way to test that as on
* real hardware it requires more than a century of uptime,
* but this is cheap and safe.
*/
if (next_cycle < last_cycle) {
next_cycle = UINT64_MAX;
}
set_trigger(next_cycle);
k_spin_unlock(&lock, key);
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint64_t curr_cycle = rdtsc();
uint64_t delta_cycles = curr_cycle - last_cycle;
uint32_t delta_ticks = (cycle_diff_t)delta_cycles / CYC_PER_TICK;
last_elapsed = delta_ticks;
k_spin_unlock(&lock, key);
return delta_ticks;
}
uint32_t sys_clock_cycle_get_32(void)
{
return (uint32_t) rdtsc();
}
uint64_t sys_clock_cycle_get_64(void)
{
return rdtsc();
}
static inline uint32_t timer_irq(void)
{
/* The Zephyr APIC API is... idiosyncratic. The timer is a
* "local vector table" interrupt. These aren't system IRQs
* presented to the IO-APIC, they're indices into a register
* array in the local APIC. By Zephyr convention they come
* after all the external IO-APIC interrupts, but that number
* changes depending on device configuration so we have to
* fetch it at runtime. The timer happens to be the first
* entry in the table.
*/
return z_loapic_irq_base();
}
/* The TSC_ADJUST MSR implements a synchronized offset such that
* multiple CPUs (within a socket, anyway) can synchronize exactly, or
* implement managed timing spaces for guests in a recoverable way,
* etc... We set it to zero on all cores for simplicity, because
* firmware often leaves it in an inconsistent state between cores.
*/
static void clear_tsc_adjust(void)
{
/* But don't touch it on ACRN, where an hypervisor bug
* confuses the APIC emulation and deadline interrupts don't
* arrive.
*/
#ifndef CONFIG_BOARD_ACRN
wrmsr(IA32_TSC_ADJUST_MSR, 0);
#endif
}
void smp_timer_init(void)
{
/* Copy the LVT configuration from CPU0, because IRQ_CONNECT()
* doesn't know how to manage LVT interrupts for anything
* other than the calling/initial CPU. Same fence needed to
* prevent later MSR writes from reordering before the APIC
* configuration write.
*/
x86_write_loapic(LOAPIC_TIMER, lvt_reg.val);
__asm__ volatile("mfence" ::: "memory");
clear_tsc_adjust();
irq_enable(timer_irq());
}
static int sys_clock_driver_init(void)
{
#ifdef CONFIG_ASSERT
uint32_t eax, ebx, ecx, edx;
if (IS_ENABLED(CONFIG_APIC_TSC_DEADLINE_TIMER)) {
ecx = 0; /* prevent compiler warning */
__get_cpuid(CPUID_BASIC_INFO_1, &eax, &ebx, &ecx, &edx);
__ASSERT((ecx & BIT(24)) != 0, "No TSC Deadline support");
}
edx = 0; /* prevent compiler warning */
__get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
__ASSERT((edx & BIT(8)) != 0, "No Invariant TSC support");
if (IS_ENABLED(CONFIG_SMP)) {
ebx = 0; /* prevent compiler warning */
__get_cpuid_count(CPUID_EXTENDED_FEATURES_LVL, 0, &eax, &ebx, &ecx, &edx);
__ASSERT((ebx & BIT(1)) != 0, "No TSC_ADJUST MSR support");
}
#endif
if (IS_ENABLED(CONFIG_SMP)) {
clear_tsc_adjust();
}
/* Timer interrupt number is runtime-fetched, so can't use
* static IRQ_CONNECT()
*/
irq_connect_dynamic(timer_irq(), CONFIG_APIC_TIMER_IRQ_PRIORITY, isr, 0, 0);
if (IS_ENABLED(CONFIG_APIC_TIMER_TSC)) {
uint32_t timer_conf;
timer_conf = x86_read_loapic(LOAPIC_TIMER_CONFIG);
timer_conf &= ~0x0f; /* clear divider bits */
timer_conf |= 0x0b; /* divide by 1 */
x86_write_loapic(LOAPIC_TIMER_CONFIG, timer_conf);
}
lvt_reg.val = x86_read_loapic(LOAPIC_TIMER);
lvt_reg.lvt.mode = IS_ENABLED(CONFIG_APIC_TSC_DEADLINE_TIMER) ?
TSC_DEADLINE : ONE_SHOT;
lvt_reg.lvt.masked = 0;
x86_write_loapic(LOAPIC_TIMER, lvt_reg.val);
/* Per the SDM, the TSC_DEADLINE MSR is not serializing, so
* this fence is needed to be sure that an upcoming MSR write
* (i.e. a timeout we're about to set) cannot possibly reorder
* around the initialization we just did.
*/
__asm__ volatile("mfence" ::: "memory");
last_tick = rdtsc() / CYC_PER_TICK;
last_cycle = last_tick * CYC_PER_TICK;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
set_trigger(last_cycle + CYC_PER_TICK);
}
irq_enable(timer_irq());
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/apic_tsc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,734 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <altera_common.h>
#include <zephyr/irq.h>
#include "altera_avalon_timer_regs.h"
#include "altera_avalon_timer.h"
/* The old driver "now" API would return a full uptime value. The new
* one only requires the driver to track ticks since the last announce
* call. Implement the new call in terms of the old one on legacy
* drivers by keeping (yet another) uptime value locally.
*/
static uint32_t driver_uptime;
static uint32_t accumulated_cycle_count;
static int32_t _sys_idle_elapsed_ticks = 1;
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = TIMER_0_IRQ;
#endif
static void wrapped_announce(int32_t ticks)
{
driver_uptime += ticks;
sys_clock_announce(ticks);
}
static void timer_irq_handler(const void *unused)
{
ARG_UNUSED(unused);
accumulated_cycle_count += k_ticks_to_cyc_floor32(1);
/* Clear the interrupt */
alt_handle_irq((void *)TIMER_0_BASE, TIMER_0_IRQ);
wrapped_announce(_sys_idle_elapsed_ticks);
}
uint32_t sys_clock_cycle_get_32(void)
{
/* Per the Altera Embedded IP Peripherals guide, you cannot
* use a timer instance for both the system clock and timestamps
* at the same time.
*
* Having this function return accumulated_cycle_count + get_snapshot()
* does not work reliably. It's possible for the current countdown
* to reset to the next interval before the timer interrupt is
* delivered (and accumulated cycle count gets updated). The result
* is an unlucky call to this function will appear to jump backward
* in time.
*
* To properly obtain timestamps, the CPU must be configured with
* a second timer peripheral instance that is configured to
* count down from some large initial 64-bit value. This
* is currently unimplemented.
*/
return accumulated_cycle_count;
}
uint32_t sys_clock_elapsed(void)
{
return 0;
}
static int sys_clock_driver_init(void)
{
IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE,
k_ticks_to_cyc_floor32(1) & 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE,
(k_ticks_to_cyc_floor32(1) >> 16) & 0xFFFF);
IRQ_CONNECT(TIMER_0_IRQ, 0, timer_irq_handler, NULL, 0);
irq_enable(TIMER_0_IRQ);
alt_avalon_timer_sc_init((void *)TIMER_0_BASE, 0,
TIMER_0_IRQ, k_ticks_to_cyc_floor32(1));
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/altera_avalon_timer_hal.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 655 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_gpt_hw_timer
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <fsl_gpt.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys/time_units.h>
#include <zephyr/irq.h>
/*
* By limiting counter to 30 bits, we ensure that
* timeout calculations will never overflow in sys_clock_set_timeout
*/
#define COUNTER_MAX 0x3fffffff
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
/* Use the first device defined with GPT HW timer compatible string */
#define GPT_INST DT_INST(0, DT_DRV_COMPAT)
/*
* Stores the current number of cycles the system has had announced to it,
* since the last rollover of the free running counter.
*/
static uint32_t announced_cycles;
/*
* Stores the number of cycles that have elapsed due to counter rollover.
* this value is updated in the GPT isr, and is used to keep the value
* returned by sys_clock_cycle_get_32 accurate after a timer rollover.
*/
static uint32_t rollover_cycles;
/* GPT timer base address */
static GPT_Type *base;
/* Lock on shared variables */
static struct k_spinlock lock;
/* Helper function to set GPT compare value, so we don't set a compare point in past */
static void gpt_set_safe(uint32_t next)
{
uint32_t now;
next = MIN(MAX_CYCLES, next);
GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel2, next - 1);
now = GPT_GetCurrentTimerCount(base);
/* GPT fires interrupt at next counter cycle after a compare point is
* hit, so we should bump the compare point if 1 cycle or less exists
* between now and compare point.
*
* We will exit this loop if next==MAX_CYCLES, as we already
* have a rollover interrupt set up for that point, so we
* no longer need to keep bumping the compare point.
*/
if (unlikely(((int32_t)(next - now)) <= 1)) {
uint32_t bump = 1;
do {
next = now + bump;
bump *= 2;
next = MIN(MAX_CYCLES, next);
GPT_SetOutputCompareValue(base,
kGPT_OutputCompare_Channel2, next - 1);
now = GPT_GetCurrentTimerCount(base);
} while ((((int32_t)(next - now)) <= 1) && (next < MAX_CYCLES));
}
}
/* Interrupt fires every time GPT reaches the current capture value */
void mcux_imx_gpt_isr(const void *arg)
{
ARG_UNUSED(arg);
k_spinlock_key_t key;
uint32_t tick_delta = 0, now, status;
key = k_spin_lock(&lock);
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* Get current timer count */
now = GPT_GetCurrentTimerCount(base);
status = GPT_GetStatusFlags(base,
kGPT_OutputCompare2Flag | kGPT_OutputCompare1Flag);
/* Clear GPT capture interrupts */
GPT_ClearStatusFlags(base, status);
if (status & kGPT_OutputCompare1Flag) {
/* Counter has just rolled over. We should
* reset the announced cycles counter, and record the
* cycles that remained before rollover.
*
* Since rollover occurs on a tick boundary, we don't
* need to worry about losing time here due to rounding.
*/
tick_delta += (MAX_CYCLES - announced_cycles) / CYC_PER_TICK;
announced_cycles = 0U;
/* Update count of rolled over cycles */
rollover_cycles += MAX_CYCLES;
}
if (status & kGPT_OutputCompare2Flag) {
/* Normal counter interrupt. Get delta since last announcement */
tick_delta += (now - announced_cycles) / CYC_PER_TICK;
announced_cycles += (((now - announced_cycles) / CYC_PER_TICK) *
CYC_PER_TICK);
}
} else {
GPT_ClearStatusFlags(base, kGPT_OutputCompare1Flag);
/* Update count of rolled over cycles */
rollover_cycles += CYC_PER_TICK;
}
/* Announce progress to the kernel */
k_spin_unlock(&lock, key);
sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? tick_delta : 1);
}
/*
* Next needed call to sys_clock_announce will not be until the specified number
* of ticks from the current time have elapsed.
*/
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* Not supported on tickful kernels */
return;
}
k_spinlock_key_t key;
uint32_t next, adj, now;
ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
/* Clamp ticks. We subtract one since we round up to next tick */
ticks = CLAMP((ticks - 1), 0, (int32_t)MAX_TICKS);
key = k_spin_lock(&lock);
/* Read current timer value */
now = GPT_GetCurrentTimerCount(base);
/* Adjustment value, used to ensure next capture is on tick boundary */
adj = (now - announced_cycles) + (CYC_PER_TICK - 1);
next = ticks * CYC_PER_TICK;
/*
* The following section rounds the capture value up to the next tick
* boundary
*/
next += adj;
next = (next / CYC_PER_TICK) * CYC_PER_TICK;
next += announced_cycles;
/* Set GPT output value */
gpt_set_safe(next);
k_spin_unlock(&lock, key);
}
/* Get the number of ticks since the last call to sys_clock_announce() */
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* Always return 0 for tickful kernel system */
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t cyc = GPT_GetCurrentTimerCount(base);
cyc -= announced_cycles;
k_spin_unlock(&lock, key);
return cyc / CYC_PER_TICK;
}
/* Get the number of elapsed hardware cycles of the clock */
uint32_t sys_clock_cycle_get_32(void)
{
return rollover_cycles + GPT_GetCurrentTimerCount(base);
}
/*
* @brief Initialize system timer driver
*
* Enable the hw timer, setting its tick period, and setup its interrupt
*/
int sys_clock_driver_init(void)
{
gpt_config_t gpt_config;
/* Configure ISR. Use instance 0 of the GPT timer */
IRQ_CONNECT(DT_IRQN(GPT_INST), DT_IRQ(GPT_INST, priority),
mcux_imx_gpt_isr, NULL, 0);
base = (GPT_Type *)DT_REG_ADDR(GPT_INST);
GPT_GetDefaultConfig(&gpt_config);
/* Enable GPT timer to run in SOC low power states */
gpt_config.enableRunInStop = true;
gpt_config.enableRunInWait = true;
gpt_config.enableRunInDoze = true;
/* Use 32KHz clock frequency */
gpt_config.clockSource = kGPT_ClockSource_LowFreq;
/* We use reset mode, but reset at MAX ticks- see comment below */
gpt_config.enableFreeRun = false;
/* Initialize the GPT timer, and enable the relevant interrupts */
GPT_Init(base, &gpt_config);
announced_cycles = 0U;
rollover_cycles = 0U;
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/*
* Set GPT capture value 1 to MAX_CYCLES, and use GPT capture
* value 2 as the source for GPT interrupts. This way, we can
* use the counter as a free running timer, but it will roll
* over on a tick boundary.
*/
GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel1,
MAX_CYCLES - 1);
/* Set initial trigger value to one tick worth of cycles */
GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel2,
CYC_PER_TICK - 1);
/* Enable GPT interrupts for timer match, and reset at capture value 1 */
GPT_EnableInterrupts(base, kGPT_OutputCompare1InterruptEnable |
kGPT_OutputCompare2InterruptEnable);
} else {
/* For a tickful kernel, just roll the counter over every tick */
GPT_SetOutputCompareValue(base, kGPT_OutputCompare_Channel1,
CYC_PER_TICK - 1);
GPT_EnableInterrupts(base, kGPT_OutputCompare1InterruptEnable);
}
/* Enable IRQ */
irq_enable(DT_IRQN(GPT_INST));
/* Start timer */
GPT_StartTimer(base);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/mcux_gpt_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,022 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_rtc_timer
/*
* TI SimpleLink CC13X2/CC26X2 RTC-based system timer
*
* This system timer implementation supports both tickless and ticking modes.
* RTC counts continually in 64-bit mode and timeouts are
* scheduled using the RTC comparator. An interrupt is triggered whenever
* the comparator value set is reached.
*/
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/irq.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys_clock.h>
#include <zephyr/sys/util.h>
#include <driverlib/interrupt.h>
#include <driverlib/aon_rtc.h>
#include <driverlib/aon_event.h>
#define RTC_COUNTS_PER_SEC 0x100000000ULL
/* Number of counts per rtc timer cycle */
#define RTC_COUNTS_PER_CYCLE (RTC_COUNTS_PER_SEC / \
sys_clock_hw_cycles_per_sec())
/* Number of counts per system clock tick */
#define RTC_COUNTS_PER_TICK (RTC_COUNTS_PER_SEC / \
CONFIG_SYS_CLOCK_TICKS_PER_SEC)
/* Number of RTC cycles per system clock tick */
#define CYCLES_PER_TICK (sys_clock_hw_cycles_per_sec() / \
CONFIG_SYS_CLOCK_TICKS_PER_SEC)
/*
* Maximum number of ticks.
*/
#define MAX_CYC 0x7FFFFFFFFFFFULL
#define MAX_TICKS (MAX_CYC / RTC_COUNTS_PER_TICK)
/*
* Due to the nature of clock synchronization, the comparator cannot be set
* to a value that is too close to the current time. This constant defines
* a safe threshold for the comparator.
*/
#define COMPARE_MARGIN 6
/* RTC count of the last announce call, rounded down to tick boundary. */
static volatile uint64_t rtc_last;
#ifdef CONFIG_TICKLESS_KERNEL
static struct k_spinlock lock;
#else
static uint64_t nextThreshold = RTC_COUNTS_PER_TICK;
#endif /* CONFIG_TICKLESS_KERNEL */
static void setThreshold(uint32_t next)
{
uint32_t now;
unsigned int key;
key = irq_lock();
/* get the current RTC count corresponding to compare window */
now = AONRTCCurrentCompareValueGet();
/* if next is too soon, set at least one RTC tick in future */
/* assume next never be more than half the maximum 32 bit count value */
if ((next - now) > (uint32_t)0x80000000) {
/* now is past next */
next = now + COMPARE_MARGIN;
} else if ((now + COMPARE_MARGIN - next) < (uint32_t)0x80000000) {
if (next < now + COMPARE_MARGIN) {
next = now + COMPARE_MARGIN;
}
}
/* set next compare threshold in RTC */
AONRTCCompareValueSet(AON_RTC_CH0, next);
irq_unlock(key);
}
void rtc_isr(const void *arg)
{
#ifndef CONFIG_TICKLESS_KERNEL
uint64_t newThreshold;
uint32_t next;
#else
uint64_t ticks, currCount;
#endif
ARG_UNUSED(arg);
AONRTCEventClear(AON_RTC_CH0);
#ifdef CONFIG_TICKLESS_KERNEL
k_spinlock_key_t key = k_spin_lock(&lock);
currCount = (uint64_t)AONRTCCurrent64BitValueGet();
ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK;
rtc_last += ticks * RTC_COUNTS_PER_TICK;
k_spin_unlock(&lock, key);
sys_clock_announce(ticks);
#else /* !CONFIG_TICKLESS_KERNEL */
/* calculate new 64-bit RTC count for next interrupt */
newThreshold = nextThreshold + RTC_COUNTS_PER_TICK;
next = (uint32_t)((uint64_t)newThreshold >> 16);
setThreshold(next);
nextThreshold = newThreshold;
rtc_last += RTC_COUNTS_PER_TICK;
sys_clock_announce(1);
#endif /* CONFIG_TICKLESS_KERNEL */
}
static void initDevice(void)
{
AONRTCDisable();
AONRTCReset();
HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1;
/* read sync register to complete reset */
HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
AONRTCEventClear(AON_RTC_CH0);
IntPendClear(INT_AON_RTC_COMB);
HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
}
static void startDevice(void)
{
uint32_t compare;
uint64_t period;
unsigned int key;
key = irq_lock();
/* reset timer */
AONRTCReset();
AONRTCEventClear(AON_RTC_CH0);
IntPendClear(INT_AON_RTC_COMB);
/*
* set the compare register to one period.
* For a very small period round up to interrupt upon 4th tick in
* compare register
*/
period = RTC_COUNTS_PER_TICK;
if (period < 0x40000) {
compare = 0x4; /* 4 * 15.5us ~= 62us */
} else {
/* else, interrupt on first period expiration */
compare = period >> 16;
}
/* set the compare value at the RTC */
AONRTCCompareValueSet(AON_RTC_CH0, compare);
/* enable compare channel 0 */
AONEventMcuWakeUpSet(AON_EVENT_MCU_WU0, AON_EVENT_RTC0);
AONRTCChannelEnable(AON_RTC_CH0);
AONRTCCombinedEventConfig(AON_RTC_CH0);
/* start timer */
AONRTCEnable();
irq_unlock(key);
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
#ifdef CONFIG_TICKLESS_KERNEL
ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS);
k_spinlock_key_t key = k_spin_lock(&lock);
/* Compute number of RTC cycles until the next timeout. */
uint64_t count = AONRTCCurrent64BitValueGet();
uint64_t timeout = ticks * RTC_COUNTS_PER_TICK +
(count - rtc_last);
/* Round to the nearest tick boundary. */
timeout = DIV_ROUND_UP(timeout, RTC_COUNTS_PER_TICK) *
RTC_COUNTS_PER_TICK;
timeout = MIN(timeout, MAX_CYC);
timeout += rtc_last;
/* Set the comparator */
setThreshold(timeout >> 16);
k_spin_unlock(&lock, key);
#endif /* CONFIG_TICKLESS_KERNEL */
}
uint32_t sys_clock_elapsed(void)
{
uint32_t ret = (AONRTCCurrent64BitValueGet() - rtc_last) /
RTC_COUNTS_PER_TICK;
return ret;
}
uint32_t sys_clock_cycle_get_32(void)
{
return (uint32_t)(AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE);
}
uint64_t sys_clock_cycle_get_64(void)
{
return AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE;
}
static int sys_clock_driver_init(void)
{
rtc_last = 0U;
initDevice();
startDevice();
/* Enable RTC interrupt. */
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
rtc_isr, 0, 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/cc13xx_cc26xx_rtc_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,620 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/counter.h>
#define COUNTER_MAX 0x00ffffff
#define TIMER_STOPPED 0xff000000
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
/* Minimum cycles in the future to try to program. Note that this is
* NOT simply "enough cycles to get the counter read and reprogrammed
* reliably" -- it becomes the minimum value of the LOAD register, and
* thus reflects how much time we can reliably see expire between
* calls to elapsed() to read the COUNTFLAG bit. So it needs to be
* set to be larger than the maximum time the interrupt might be
* masked. Choosing a fraction of a tick is probably a good enough
* default, with an absolute minimum of 1k cyc.
*/
#define MIN_DELAY MAX(1024U, ((uint32_t)CYC_PER_TICK/16U))
static struct k_spinlock lock;
static uint32_t last_load;
#ifdef CONFIG_CORTEX_M_SYSTICK_64BIT_CYCLE_COUNTER
typedef uint64_t cycle_t;
#else
typedef uint32_t cycle_t;
#endif
/*
* This local variable holds the amount of SysTick HW cycles elapsed
* and it is updated in sys_clock_isr() and sys_clock_set_timeout().
*
* Note:
* At an arbitrary point in time the "current" value of the SysTick
* HW timer is calculated as:
*
* t = cycle_counter + elapsed();
*/
static cycle_t cycle_count;
/*
* This local variable holds the amount of elapsed SysTick HW cycles
* that have been announced to the kernel.
*
* Note:
* Additions/subtractions/comparisons of 64-bits values on 32-bits systems
* are very cheap. Divisions are not. Make sure the difference between
* cycle_count and announced_cycles is stored in a 32-bit variable before
* dividing it by CYC_PER_TICK.
*/
static cycle_t announced_cycles;
/*
* This local variable holds the amount of elapsed HW cycles due to
* SysTick timer wraps ('overflows') and is used in the calculation
* in elapsed() function, as well as in the updates to cycle_count.
*
* Note:
* Each time cycle_count is updated with the value from overflow_cyc,
* the overflow_cyc must be reset to zero.
*/
static volatile uint32_t overflow_cyc;
#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
/* This local variable indicates that the timeout was set right before
* entering idle state.
*
* It is used for chips that has to use a separate idle timer in such
* case because the Cortex-m SysTick is not clocked in the low power
* mode state.
*/
static bool timeout_idle;
/* Cycle counter before entering the idle state. */
static cycle_t cycle_pre_idle;
/* Idle timer value before entering the idle state. */
static uint32_t idle_timer_pre_idle;
/* Idle timer used for timer while entering the idle state */
static const struct device *idle_timer = DEVICE_DT_GET(DT_CHOSEN(zephyr_cortex_m_idle_timer));
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
/* This internal function calculates the amount of HW cycles that have
* elapsed since the last time the absolute HW cycles counter has been
* updated. 'cycle_count' may be updated either by the ISR, or when we
* re-program the SysTick.LOAD register, in sys_clock_set_timeout().
*
* Additionally, the function updates the 'overflow_cyc' counter, that
* holds the amount of elapsed HW cycles due to (possibly) multiple
* timer wraps (overflows).
*
* Prerequisites:
* - reprogramming of SysTick.LOAD must be clearing the SysTick.COUNTER
* register and the 'overflow_cyc' counter.
* - ISR must be clearing the 'overflow_cyc' counter.
* - no more than one counter-wrap has occurred between
* - the timer reset or the last time the function was called
* - and until the current call of the function is completed.
* - the function is invoked with interrupts disabled.
*/
static uint32_t elapsed(void)
{
uint32_t val1 = SysTick->VAL; /* A */
uint32_t ctrl = SysTick->CTRL; /* B */
uint32_t val2 = SysTick->VAL; /* C */
/* SysTick behavior: The counter wraps after zero automatically.
* The COUNTFLAG field of the CTRL register is set when it
* decrements from 1 to 0. Reading the control register
* automatically clears that field. When a timer is started,
* count begins at zero then wraps after the first cycle.
* Reference:
* Armv6-m (B3.3.1) path_to_url
* Armv7-m (B3.3.1) path_to_url
* Armv8-m (B11.1) path_to_url
*
* First, manually wrap/realign val1 and val2 from [0:last_load-1]
* to [1:last_load]. This allows subsequent code to assume that
* COUNTFLAG and wrapping occur on the same cycle.
*
* If the count wrapped...
* 1) Before A then COUNTFLAG will be set and val1 >= val2
* 2) Between A and B then COUNTFLAG will be set and val1 < val2
* 3) Between B and C then COUNTFLAG will be clear and val1 < val2
* 4) After C we'll see it next time
*
* So the count in val2 is post-wrap and last_load needs to be
* added if and only if COUNTFLAG is set or val1 < val2.
*/
if (val1 == 0) {
val1 = last_load;
}
if (val2 == 0) {
val2 = last_load;
}
if ((ctrl & SysTick_CTRL_COUNTFLAG_Msk)
|| (val1 < val2)) {
overflow_cyc += last_load;
/* We know there was a wrap, but we might not have
* seen it in CTRL, so clear it. */
(void)SysTick->CTRL;
}
return (last_load - val2) + overflow_cyc;
}
/* sys_clock_isr is calling directly from the platform's vectors table.
* However using ISR_DIRECT_DECLARE() is not so suitable due to possible
* tracing overflow, so here is a stripped down version of it.
*/
ARCH_ISR_DIAG_OFF
__attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
{
uint32_t dcycles;
uint32_t dticks;
/* Update overflow_cyc and clear COUNTFLAG by invoking elapsed() */
elapsed();
/* Increment the amount of HW cycles elapsed (complete counter
* cycles) and announce the progress to the kernel.
*/
cycle_count += overflow_cyc;
overflow_cyc = 0;
#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
/* Rare case, when the interrupt was triggered, with previously programmed
* LOAD value, just before entering the idle mode (SysTick is clocked) or right
* after exiting the idle mode, before executing the procedure in the
* sys_clock_idle_exit function.
*/
if (timeout_idle) {
ISR_DIRECT_PM();
z_arm_int_exit();
return;
}
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* In TICKLESS mode, the SysTick.LOAD is re-programmed
* in sys_clock_set_timeout(), followed by resetting of
* the counter (VAL = 0).
*
* If a timer wrap occurs right when we re-program LOAD,
* the ISR is triggered immediately after sys_clock_set_timeout()
* returns; in that case we shall not increment the cycle_count
* because the value has been updated before LOAD re-program.
*
* We can assess if this is the case by inspecting COUNTFLAG.
*/
dcycles = cycle_count - announced_cycles;
dticks = dcycles / CYC_PER_TICK;
announced_cycles += dticks * CYC_PER_TICK;
sys_clock_announce(dticks);
} else {
sys_clock_announce(1);
}
ISR_DIRECT_PM();
z_arm_int_exit();
}
ARCH_ISR_DIAG_ON
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
/* Fast CPUs and a 24 bit counter mean that even idle systems
* need to wake up multiple times per second. If the kernel
* allows us to miss tick announcements in idle, then shut off
* the counter. (Note: we can assume if idle==true that
* interrupts are already disabled)
*/
if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && idle && ticks == K_TICKS_FOREVER) {
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
last_load = TIMER_STOPPED;
return;
}
#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
if (idle) {
uint64_t timeout_us =
((uint64_t)ticks * USEC_PER_SEC) / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
struct counter_alarm_cfg cfg = {
.callback = NULL,
.ticks = counter_us_to_ticks(idle_timer, timeout_us),
.user_data = NULL,
.flags = 0,
};
timeout_idle = true;
/* Set the alarm using timer that runs the idle.
* Needed rump-up/setting time, lower accurency etc. should be
* included in the exit-latency in the power state definition.
*/
counter_cancel_channel_alarm(idle_timer, 0);
counter_set_channel_alarm(idle_timer, 0, &cfg);
/* Store current values to calculate a difference in
* measurements after exiting the idle state.
*/
counter_get_value(idle_timer, &idle_timer_pre_idle);
cycle_pre_idle = cycle_count + elapsed();
return;
}
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
#if defined(CONFIG_TICKLESS_KERNEL)
uint32_t delay;
uint32_t val1, val2;
uint32_t last_load_ = last_load;
ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t pending = elapsed();
val1 = SysTick->VAL;
cycle_count += pending;
overflow_cyc = 0U;
uint32_t unannounced = cycle_count - announced_cycles;
if ((int32_t)unannounced < 0) {
/* We haven't announced for more than half the 32-bit
* wrap duration, because new timeouts keep being set
* before the existing one fires. Force an announce
* to avoid loss of a wrap event, making sure the
* delay is at least the minimum delay possible.
*/
last_load = MIN_DELAY;
} else {
/* Desired delay in the future */
delay = ticks * CYC_PER_TICK;
/* Round delay up to next tick boundary */
delay += unannounced;
delay = DIV_ROUND_UP(delay, CYC_PER_TICK) * CYC_PER_TICK;
delay -= unannounced;
delay = MAX(delay, MIN_DELAY);
if (delay > MAX_CYCLES) {
last_load = MAX_CYCLES;
} else {
last_load = delay;
}
}
val2 = SysTick->VAL;
SysTick->LOAD = last_load - 1;
SysTick->VAL = 0; /* resets timer to last_load */
/*
* Add elapsed cycles while computing the new load to cycle_count.
*
* Note that comparing val1 and val2 is normaly not good enough to
* guess if the counter wrapped during this interval. Indeed if val1 is
* close to LOAD, then there are little chances to catch val2 between
* val1 and LOAD after a wrap. COUNTFLAG should be checked in addition.
* But since the load computation is faster than MIN_DELAY, then we
* don't need to worry about this case.
*/
if (val1 < val2) {
cycle_count += (val1 + (last_load_ - val2));
} else {
cycle_count += (val1 - val2);
}
k_spin_unlock(&lock, key);
#endif
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t unannounced = cycle_count - announced_cycles;
uint32_t cyc = elapsed() + unannounced;
k_spin_unlock(&lock, key);
return cyc / CYC_PER_TICK;
}
uint32_t sys_clock_cycle_get_32(void)
{
k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t ret = cycle_count;
ret += elapsed();
k_spin_unlock(&lock, key);
return ret;
}
#ifdef CONFIG_CORTEX_M_SYSTICK_64BIT_CYCLE_COUNTER
uint64_t sys_clock_cycle_get_64(void)
{
k_spinlock_key_t key = k_spin_lock(&lock);
uint64_t ret = cycle_count + elapsed();
k_spin_unlock(&lock, key);
return ret;
}
#endif
void sys_clock_idle_exit(void)
{
#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
if (timeout_idle) {
cycle_t systick_diff, missed_cycles;
uint32_t idle_timer_diff, idle_timer_post, dcycles, dticks;
uint64_t systick_us, idle_timer_us;
/* Get current values for both timers */
counter_get_value(idle_timer, &idle_timer_post);
systick_diff = cycle_count + elapsed() - cycle_pre_idle;
/* Calculate has much time has pasted since last measurement for both timers */
/* Check IDLE timer overflow */
if (idle_timer_pre_idle > idle_timer_post) {
idle_timer_diff =
(counter_get_top_value(idle_timer) - idle_timer_pre_idle) +
idle_timer_post + 1;
} else {
idle_timer_diff = idle_timer_post - idle_timer_pre_idle;
}
idle_timer_us = counter_ticks_to_us(idle_timer, idle_timer_diff);
systick_us =
((uint64_t)systick_diff * USEC_PER_SEC) / sys_clock_hw_cycles_per_sec();
/* Calculate difference in measurements to get how much time
* the SysTick missed in idle state.
*/
if (idle_timer_us < systick_us) {
/* This case is possible, when the time in low power mode is
* very short or 0. SysTick usually has higher measurement
* resolution of than the IDLE timer, thus the measurement of
* passed time since the sys_clock_set_timeout call can be higher.
*/
missed_cycles = 0;
} else {
uint64_t measurement_diff_us;
measurement_diff_us = idle_timer_us - systick_us;
missed_cycles = (sys_clock_hw_cycles_per_sec() * measurement_diff_us) /
USEC_PER_SEC;
}
/* Update the cycle counter to include the cycles missed in idle */
cycle_count += missed_cycles;
/* Announce the passed ticks to the kernel */
dcycles = cycle_count + elapsed() - announced_cycles;
dticks = dcycles / CYC_PER_TICK;
announced_cycles += dticks * CYC_PER_TICK;
sys_clock_announce(dticks);
/* We've alredy performed all needed operations */
timeout_idle = false;
}
#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
if (last_load == TIMER_STOPPED) {
/* We really dont know here how much time has passed,
* so lets restart the timer from scratch.
*/
K_SPINLOCK(&lock) {
last_load = CYC_PER_TICK;
SysTick->LOAD = last_load - 1;
SysTick->VAL = 0; /* resets timer to last_load */
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
}
}
void sys_clock_disable(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
static int sys_clock_driver_init(void)
{
NVIC_SetPriority(SysTick_IRQn, _IRQ_PRIO_OFFSET);
last_load = CYC_PER_TICK;
overflow_cyc = 0U;
SysTick->LOAD = last_load - 1;
SysTick->VAL = 0; /* resets timer to last_load */
SysTick->CTRL |= (SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_CLKSOURCE_Msk);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/cortex_m_systick.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,778 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/drivers/timer/nrf_rtc_timer.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys_clock.h>
#include <zephyr/sys/barrier.h>
#include <haly/nrfy_rtc.h>
#include <zephyr/irq.h>
#define RTC_PRETICK (IS_ENABLED(CONFIG_SOC_NRF53_RTC_PRETICK) && \
IS_ENABLED(CONFIG_SOC_NRF5340_CPUNET))
#define EXT_CHAN_COUNT CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT
#define CHAN_COUNT (EXT_CHAN_COUNT + 1)
#define RTC NRF_RTC1
#define RTC_IRQn NRFX_IRQ_NUMBER_GET(RTC)
#define RTC_LABEL rtc1
#define CHAN_COUNT_MAX (RTC1_CC_NUM - (RTC_PRETICK ? 1 : 0))
BUILD_ASSERT(CHAN_COUNT <= CHAN_COUNT_MAX, "Not enough compare channels");
/* Ensure that counter driver for RTC1 is not enabled. */
BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(RTC_LABEL), disabled),
"Counter for RTC1 must be disabled");
#define COUNTER_BIT_WIDTH 24U
#define COUNTER_SPAN BIT(COUNTER_BIT_WIDTH)
#define COUNTER_MAX (COUNTER_SPAN - 1U)
#define COUNTER_HALF_SPAN (COUNTER_SPAN / 2U)
#define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
#define MAX_TICKS ((COUNTER_HALF_SPAN - CYC_PER_TICK) / CYC_PER_TICK)
#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
#define OVERFLOW_RISK_RANGE_END (COUNTER_SPAN / 16)
#define ANCHOR_RANGE_START (COUNTER_SPAN / 8)
#define ANCHOR_RANGE_END (7 * COUNTER_SPAN / 8)
#define TARGET_TIME_INVALID (UINT64_MAX)
extern void rtc_pretick_rtc1_isr_hook(void);
static volatile uint32_t overflow_cnt;
static volatile uint64_t anchor;
static uint64_t last_count;
static bool sys_busy;
struct z_nrf_rtc_timer_chan_data {
z_nrf_rtc_timer_compare_handler_t callback;
void *user_context;
volatile uint64_t target_time;
};
static struct z_nrf_rtc_timer_chan_data cc_data[CHAN_COUNT];
static atomic_t int_mask;
static atomic_t alloc_mask;
static atomic_t force_isr_mask;
static uint32_t counter_sub(uint32_t a, uint32_t b)
{
return (a - b) & COUNTER_MAX;
}
static void set_comparator(int32_t chan, uint32_t cyc)
{
nrfy_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
}
static bool event_check(int32_t chan)
{
return nrfy_rtc_event_check(RTC, NRF_RTC_CHANNEL_EVENT_ADDR(chan));
}
static void event_clear(int32_t chan)
{
nrfy_rtc_event_clear(RTC, NRF_RTC_CHANNEL_EVENT_ADDR(chan));
}
static void event_enable(int32_t chan)
{
nrfy_rtc_event_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
}
static void event_disable(int32_t chan)
{
nrfy_rtc_event_disable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
}
static uint32_t counter(void)
{
return nrfy_rtc_counter_get(RTC);
}
static uint32_t absolute_time_to_cc(uint64_t absolute_time)
{
/* 24 least significant bits represent target CC value */
return absolute_time & COUNTER_MAX;
}
static uint32_t full_int_lock(void)
{
uint32_t mcu_critical_state;
if (IS_ENABLED(CONFIG_NRF_RTC_TIMER_LOCK_ZERO_LATENCY_IRQS)) {
mcu_critical_state = __get_PRIMASK();
__disable_irq();
} else {
mcu_critical_state = irq_lock();
}
return mcu_critical_state;
}
static void full_int_unlock(uint32_t mcu_critical_state)
{
if (IS_ENABLED(CONFIG_NRF_RTC_TIMER_LOCK_ZERO_LATENCY_IRQS)) {
__set_PRIMASK(mcu_critical_state);
} else {
irq_unlock(mcu_critical_state);
}
}
uint32_t z_nrf_rtc_timer_compare_evt_address_get(int32_t chan)
{
__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
return nrfy_rtc_event_address_get(RTC, nrfy_rtc_compare_event_get(chan));
}
uint32_t z_nrf_rtc_timer_capture_task_address_get(int32_t chan)
{
#if defined(RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk)
__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
if (chan == 0) {
return 0;
}
return nrfy_rtc_task_address_get(RTC, nrfy_rtc_capture_task_get(chan));
#else
ARG_UNUSED(chan);
return 0;
#endif
}
static bool compare_int_lock(int32_t chan)
{
atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
nrfy_rtc_int_disable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
barrier_dmem_fence_full();
barrier_isync_fence_full();
return prev & BIT(chan);
}
bool z_nrf_rtc_timer_compare_int_lock(int32_t chan)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
return compare_int_lock(chan);
}
static void compare_int_unlock(int32_t chan, bool key)
{
if (key) {
atomic_or(&int_mask, BIT(chan));
nrfy_rtc_int_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
if (atomic_get(&force_isr_mask) & BIT(chan)) {
NVIC_SetPendingIRQ(RTC_IRQn);
}
}
}
void z_nrf_rtc_timer_compare_int_unlock(int32_t chan, bool key)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
compare_int_unlock(chan, key);
}
uint32_t z_nrf_rtc_timer_compare_read(int32_t chan)
{
__ASSERT_NO_MSG(chan >= 0 && chan < CHAN_COUNT);
return nrfy_rtc_cc_get(RTC, chan);
}
uint64_t z_nrf_rtc_timer_get_ticks(k_timeout_t t)
{
uint64_t curr_time;
int64_t curr_tick;
int64_t result;
int64_t abs_ticks;
do {
curr_time = z_nrf_rtc_timer_read();
curr_tick = sys_clock_tick_get();
} while (curr_time != z_nrf_rtc_timer_read());
abs_ticks = Z_TICK_ABS(t.ticks);
if (abs_ticks < 0) {
/* relative timeout */
return (t.ticks > COUNTER_SPAN) ?
-EINVAL : (curr_time + t.ticks);
}
/* absolute timeout */
result = abs_ticks - curr_tick;
if (result > COUNTER_SPAN) {
return -EINVAL;
}
return curr_time + result;
}
/** @brief Function safely sets an alarm.
*
* It assumes that provided value is at most COUNTER_HALF_SPAN cycles from now
* (other values are considered to be from the past). It detects late setting
* and properly adjusts CC values that are too near in the future to guarantee
* triggering a COMPARE event soon, not after 512 seconds when the RTC wraps
* around first.
*
* @param[in] chan A channel for which a new CC value is to be set.
*
* @param[in] req_cc Requested CC register value to be set.
*
* @param[in] exact Use @c false to allow CC adjustment if @c req_cc value is
* close to the current value of the timer.
* Use @c true to disallow CC adjustment. The function can
* fail with -EINVAL result if @p req_cc is too close to the
* current value.
*
* @retval 0 The requested CC has been set successfully.
* @retval -EINVAL The requested CC value could not be reliably set.
*/
static int set_alarm(int32_t chan, uint32_t req_cc, bool exact)
{
int ret = 0;
/* Ensure that the value exposed in this driver API is consistent with
* assumptions of this function.
*/
BUILD_ASSERT(NRF_RTC_TIMER_MAX_SCHEDULE_SPAN <= COUNTER_HALF_SPAN);
/* According to product specifications, when the current counter value
* is N, a value of N+2 written to the CC register is guaranteed to
* trigger a COMPARE event at N+2, but tests show that this compare
* value can be missed when the previous CC value is N+1 and the write
* occurs in the second half of the RTC clock cycle (such situation can
* be provoked by test_next_cycle_timeouts in the nrf_rtc_timer suite).
* This never happens when the written value is N+3. Use 3 cycles as
* the nearest possible scheduling then.
*/
enum { MIN_CYCLES_FROM_NOW = 3 };
uint32_t cc_val = req_cc;
uint32_t cc_inc = MIN_CYCLES_FROM_NOW;
/* Disable event routing for the channel to avoid getting a COMPARE
* event for the previous CC value before the new one takes effect
* (however, even if such spurious event was generated, it would be
* properly filtered out in process_channel(), where the target time
* is checked).
* Clear also the event as it may already be generated at this point.
*/
event_disable(chan);
event_clear(chan);
for (;;) {
uint32_t now;
set_comparator(chan, cc_val);
/* Enable event routing after the required CC value was set.
* Even though the above operation may get repeated (see below),
* there is no need to disable event routing in every iteration
* of the loop, as the COMPARE event resulting from any attempt
* of setting the CC register is acceptable (as mentioned above,
* process_channel() does the proper filtering).
*/
event_enable(chan);
now = counter();
/* Check if the CC register was successfully set to a value
* that will for sure trigger a COMPARE event as expected.
* If not, try again, adjusting the CC value accordingly.
* Increase the CC value by a larger number of cycles in each
* trial to avoid spending too much time in this loop if it
* continuously gets interrupted and delayed by something.
*/
if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
(COUNTER_HALF_SPAN - MIN_CYCLES_FROM_NOW)) {
/* If the COMPARE event turns out to be already
* generated, check if the loop can be finished.
*/
if (event_check(chan)) {
/* If the current counter value has not yet
* reached the requested CC value, the event
* must come from the previously set CC value
* (the alarm is apparently rescheduled).
* The event needs to be cleared then and the
* loop needs to be continued.
*/
now = counter();
if (counter_sub(now, req_cc) > COUNTER_HALF_SPAN) {
event_clear(chan);
if (exact) {
ret = -EINVAL;
break;
}
} else {
break;
}
} else if (exact) {
ret = -EINVAL;
break;
}
cc_val = now + cc_inc;
cc_inc++;
} else {
break;
}
}
return ret;
}
static int compare_set_nolocks(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data, bool exact)
{
int ret = 0;
uint32_t cc_value = absolute_time_to_cc(target_time);
uint64_t curr_time = z_nrf_rtc_timer_read();
if (curr_time < target_time) {
if (target_time - curr_time > COUNTER_HALF_SPAN) {
/* Target time is too distant. */
return -EINVAL;
}
if (target_time != cc_data[chan].target_time) {
/* Target time is valid and is different than currently set.
* Set CC value.
*/
ret = set_alarm(chan, cc_value, exact);
}
} else if (!exact) {
/* Force ISR handling when exiting from critical section. */
atomic_or(&force_isr_mask, BIT(chan));
} else {
ret = -EINVAL;
}
if (ret == 0) {
cc_data[chan].target_time = target_time;
cc_data[chan].callback = handler;
cc_data[chan].user_context = user_data;
}
return ret;
}
static int compare_set(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data, bool exact)
{
bool key;
key = compare_int_lock(chan);
int ret = compare_set_nolocks(chan, target_time, handler, user_data, exact);
compare_int_unlock(chan, key);
return ret;
}
int z_nrf_rtc_timer_set(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
return compare_set(chan, target_time, handler, user_data, false);
}
int z_nrf_rtc_timer_exact_set(int32_t chan, uint64_t target_time,
z_nrf_rtc_timer_compare_handler_t handler,
void *user_data)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
return compare_set(chan, target_time, handler, user_data, true);
}
void z_nrf_rtc_timer_abort(int32_t chan)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
bool key = compare_int_lock(chan);
cc_data[chan].target_time = TARGET_TIME_INVALID;
event_clear(chan);
event_disable(chan);
(void)atomic_and(&force_isr_mask, ~BIT(chan));
compare_int_unlock(chan, key);
}
uint64_t z_nrf_rtc_timer_read(void)
{
uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
barrier_dmem_fence_full();
uint32_t cntr = counter();
val += cntr;
if (cntr < OVERFLOW_RISK_RANGE_END) {
/* `overflow_cnt` can have incorrect value due to still unhandled overflow or
* due to possibility that this code preempted overflow interrupt before final write
* of `overflow_cnt`. Update of `anchor` occurs far in time from this moment, so
* `anchor` is considered valid and stable. Because of this timing there is no risk
* of incorrect `anchor` value caused by non-atomic read of 64-bit `anchor`.
*/
if (val < anchor) {
/* Unhandled overflow, detected, let's add correction */
val += COUNTER_SPAN;
}
} else {
/* `overflow_cnt` is considered valid and stable in this range, no need to
* check validity using `anchor`
*/
}
return val;
}
static inline bool in_anchor_range(uint32_t cc_value)
{
return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
}
static inline void anchor_update(uint32_t cc_value)
{
/* Update anchor when far from overflow */
if (in_anchor_range(cc_value)) {
/* In this range `overflow_cnt` is considered valid and stable.
* Write of 64-bit `anchor` is non atomic. However it happens
* far in time from the moment the `anchor` is read in
* `z_nrf_rtc_timer_read`.
*/
anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
}
}
static void sys_clock_timeout_handler(int32_t chan,
uint64_t expire_time,
void *user_data)
{
uint32_t cc_value = absolute_time_to_cc(expire_time);
uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
last_count += dticks * CYC_PER_TICK;
anchor_update(cc_value);
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
/* protection is not needed because we are in the RTC interrupt
* so it won't get preempted by the interrupt.
*/
compare_set(chan, last_count + CYC_PER_TICK,
sys_clock_timeout_handler, NULL, false);
}
sys_clock_announce(dticks);
}
static bool channel_processing_check_and_clear(int32_t chan)
{
if (nrfy_rtc_int_enable_check(RTC, NRF_RTC_CHANNEL_INT_MASK(chan))) {
/* The processing of channel can be caused by CC match
* or be forced.
*/
if ((atomic_and(&force_isr_mask, ~BIT(chan)) & BIT(chan)) ||
event_check(chan)) {
event_clear(chan);
return true;
}
}
return false;
}
static void process_channel(int32_t chan)
{
if (channel_processing_check_and_clear(chan)) {
void *user_context;
uint32_t mcu_critical_state;
uint64_t curr_time;
uint64_t expire_time;
z_nrf_rtc_timer_compare_handler_t handler = NULL;
curr_time = z_nrf_rtc_timer_read();
/* This critical section is used to provide atomic access to
* cc_data structure and prevent higher priority contexts
* (including ZLIs) from overwriting it.
*/
mcu_critical_state = full_int_lock();
/* If target_time is in the past or is equal to current time
* value, execute the handler.
*/
expire_time = cc_data[chan].target_time;
if (curr_time >= expire_time) {
handler = cc_data[chan].callback;
user_context = cc_data[chan].user_context;
cc_data[chan].callback = NULL;
cc_data[chan].target_time = TARGET_TIME_INVALID;
event_disable(chan);
/* Because of the way set_alarm() sets the CC register,
* it may turn out that another COMPARE event has been
* generated for the same alarm. Make sure the event
* is cleared, so that the ISR is not executed again
* unnecessarily.
*/
event_clear(chan);
}
full_int_unlock(mcu_critical_state);
if (handler) {
handler(chan, expire_time, user_context);
}
}
}
/* Note: this function has public linkage, and MUST have this
* particular name. The platform architecture itself doesn't care,
* but there is a test (tests/arch/arm_irq_vector_table) that needs
* to find it to it can set it in a custom vector table. Should
* probably better abstract that at some point (e.g. query and reset
* it by pointer at runtime, maybe?) so we don't have this leaky
* symbol.
*/
void rtc_nrf_isr(const void *arg)
{
ARG_UNUSED(arg);
if (RTC_PRETICK) {
rtc_pretick_rtc1_isr_hook();
}
if (nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
nrfy_rtc_events_process(RTC, NRF_RTC_INT_OVERFLOW_MASK)) {
overflow_cnt++;
}
for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
process_channel(chan);
}
}
int32_t z_nrf_rtc_timer_chan_alloc(void)
{
int32_t chan;
atomic_val_t prev;
do {
chan = alloc_mask ? 31 - __builtin_clz(alloc_mask) : -1;
if (chan < 0) {
return -ENOMEM;
}
prev = atomic_and(&alloc_mask, ~BIT(chan));
} while (!(prev & BIT(chan)));
return chan;
}
void z_nrf_rtc_timer_chan_free(int32_t chan)
{
__ASSERT_NO_MSG(chan > 0 && chan < CHAN_COUNT);
atomic_or(&alloc_mask, BIT(chan));
}
int z_nrf_rtc_timer_trigger_overflow(void)
{
uint32_t mcu_critical_state;
int err = 0;
if (!IS_ENABLED(CONFIG_NRF_RTC_TIMER_TRIGGER_OVERFLOW) ||
(CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT > 0)) {
return -ENOTSUP;
}
mcu_critical_state = full_int_lock();
if (sys_busy) {
err = -EBUSY;
goto bail;
}
if (counter() >= (COUNTER_SPAN - 100)) {
err = -EAGAIN;
goto bail;
}
nrfy_rtc_task_trigger(RTC, NRF_RTC_TASK_TRIGGER_OVERFLOW);
k_busy_wait(80);
uint64_t now = z_nrf_rtc_timer_read();
if (err == 0) {
sys_clock_timeout_handler(0, now, NULL);
}
bail:
full_int_unlock(mcu_critical_state);
return err;
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
uint32_t cyc;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return;
}
if (ticks == K_TICKS_FOREVER) {
cyc = MAX_TICKS * CYC_PER_TICK;
sys_busy = false;
} else {
/* Value of ticks can be zero or negative, what means "announce
* the next tick" (the same as ticks equal to 1).
*/
cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
cyc *= CYC_PER_TICK;
sys_busy = true;
}
uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
/* If we haven't announced for more than half the 24-bit wrap
* duration, then force an announce to avoid loss of a wrap
* event. This can happen if new timeouts keep being set
* before the existing one triggers the interrupt.
*/
if (unannounced >= COUNTER_HALF_SPAN) {
cyc = 0;
}
/* Get the cycles from last_count to the tick boundary after
* the requested ticks have passed starting now.
*/
cyc += unannounced;
cyc = DIV_ROUND_UP(cyc, CYC_PER_TICK) * CYC_PER_TICK;
/* Due to elapsed time the calculation above might produce a
* duration that laps the counter. Don't let it.
* This limitation also guarantees that the anchor will be properly
* updated before every overflow (see anchor_update()).
*/
if (cyc > MAX_CYCLES) {
cyc = MAX_CYCLES;
}
uint64_t target_time = cyc + last_count;
compare_set(0, target_time, sys_clock_timeout_handler, NULL, false);
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
}
uint32_t sys_clock_cycle_get_32(void)
{
return (uint32_t)z_nrf_rtc_timer_read();
}
static void int_event_disable_rtc(void)
{
uint32_t mask = NRF_RTC_INT_TICK_MASK |
NRF_RTC_INT_OVERFLOW_MASK |
NRF_RTC_INT_COMPARE0_MASK |
NRF_RTC_INT_COMPARE1_MASK |
NRF_RTC_INT_COMPARE2_MASK |
NRF_RTC_INT_COMPARE3_MASK;
/* Reset interrupt enabling to expected reset values */
nrfy_rtc_int_disable(RTC, mask);
/* Reset event routing enabling to expected reset values */
nrfy_rtc_event_disable(RTC, mask);
}
void sys_clock_disable(void)
{
nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_STOP);
irq_disable(RTC_IRQn);
int_event_disable_rtc();
NVIC_ClearPendingIRQ(RTC_IRQn);
}
static int sys_clock_driver_init(void)
{
static const enum nrf_lfclk_start_mode mode =
IS_ENABLED(CONFIG_SYSTEM_CLOCK_NO_WAIT) ?
CLOCK_CONTROL_NRF_LF_START_NOWAIT :
(IS_ENABLED(CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY) ?
CLOCK_CONTROL_NRF_LF_START_AVAILABLE :
CLOCK_CONTROL_NRF_LF_START_STABLE);
int_event_disable_rtc();
/* TODO: replace with counter driver to access RTC */
nrfy_rtc_prescaler_set(RTC, 0);
for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
cc_data[chan].target_time = TARGET_TIME_INVALID;
nrfy_rtc_int_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
}
nrfy_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);
NVIC_ClearPendingIRQ(RTC_IRQn);
IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
rtc_nrf_isr, 0, 0);
irq_enable(RTC_IRQn);
nrfy_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
nrfy_rtc_task_trigger(RTC, NRF_RTC_TASK_START);
int_mask = BIT_MASK(CHAN_COUNT);
if (CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT) {
alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << 1;
}
uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
MAX_CYCLES : CYC_PER_TICK;
compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL, false);
z_nrf_clock_control_lf_on(mode);
return 0;
}
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/timer/nrf_rtc_timer.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,591 |
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