text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#include <zephyr/logging/log.h>
#include "mailbox.h"
LOG_MODULE_REGISTER(scmi_mbox);
static void scmi_mbox_cb(const struct device *mbox,
mbox_channel_id_t channel_id,
void *user_data,
struct mbox_msg *data)
{
struct scmi_channel *scmi_chan = user_data;
if (scmi_chan->cb)
scmi_chan->cb(scmi_chan);
}
static int scmi_mbox_send_message(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg)
{
struct scmi_mbox_channel *mbox_chan;
int ret;
mbox_chan = chan->data;
ret = scmi_shmem_write_message(mbox_chan->shmem, msg);
if (ret < 0) {
LOG_ERR("failed to write message to shmem: %d", ret);
return ret;
}
ret = mbox_send_dt(&mbox_chan->tx, NULL);
if (ret < 0) {
LOG_ERR("failed to ring doorbell: %d", ret);
return ret;
}
return 0;
}
static int scmi_mbox_read_message(const struct device *transport,
struct scmi_channel *chan,
struct scmi_message *msg)
{
struct scmi_mbox_channel *mbox_chan;
mbox_chan = chan->data;
return scmi_shmem_read_message(mbox_chan->shmem, msg);
}
static bool scmi_mbox_channel_is_free(const struct device *transport,
struct scmi_channel *chan)
{
struct scmi_mbox_channel *mbox_chan = chan->data;
return scmi_shmem_channel_status(mbox_chan->shmem) &
SCMI_SHMEM_CHAN_STATUS_BUSY_BIT;
}
static int scmi_mbox_setup_chan(const struct device *transport,
struct scmi_channel *chan,
bool tx)
{
int ret;
struct scmi_mbox_channel *mbox_chan;
struct mbox_dt_spec *tx_reply;
mbox_chan = chan->data;
if (!tx) {
return -ENOTSUP;
}
if (mbox_chan->tx_reply.dev) {
tx_reply = &mbox_chan->tx_reply;
} else {
tx_reply = &mbox_chan->tx;
}
ret = mbox_register_callback_dt(tx_reply, scmi_mbox_cb, chan);
if (ret < 0) {
LOG_ERR("failed to register tx reply cb");
return ret;
}
ret = mbox_set_enabled_dt(tx_reply, true);
if (ret < 0) {
LOG_ERR("failed to enable tx reply dbell");
}
/* enable interrupt-based communication */
scmi_shmem_update_flags(mbox_chan->shmem,
SCMI_SHMEM_CHAN_FLAG_IRQ_BIT,
SCMI_SHMEM_CHAN_FLAG_IRQ_BIT);
return 0;
}
static struct scmi_transport_api scmi_mbox_api = {
.setup_chan = scmi_mbox_setup_chan,
.send_message = scmi_mbox_send_message,
.read_message = scmi_mbox_read_message,
.channel_is_free = scmi_mbox_channel_is_free,
};
DT_INST_SCMI_MAILBOX_DEFINE(0, PRE_KERNEL_1,
CONFIG_ARM_SCMI_TRANSPORT_INIT_PRIORITY,
&scmi_mbox_api);
``` | /content/code_sandbox/drivers/firmware/scmi/mailbox.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 702 |
```c
/*
*
*/
#include <zephyr/drivers/firmware/scmi/pinctrl.h>
DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, arm_scmi_pinctrl), NULL);
int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings)
{
struct scmi_protocol *proto;
struct scmi_message msg, reply;
uint32_t config_num;
int32_t status, ret;
proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_PINCTRL);
/* sanity checks */
if (!settings) {
return -EINVAL;
}
if (!proto) {
return -EINVAL;
}
if (proto->id != SCMI_PROTOCOL_PINCTRL) {
return -EINVAL;
}
config_num = SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(settings->attributes);
if (!config_num) {
return -EINVAL;
}
if ((config_num * 2) > ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE) {
return -EINVAL;
}
msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_CONFIGURE,
SCMI_COMMAND, proto->id, 0x0);
msg.len = sizeof(*settings) -
(ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE - config_num * 2) * 4;
msg.content = settings;
reply.hdr = msg.hdr;
reply.len = sizeof(status);
reply.content = &status;
ret = scmi_send_message(proto, &msg, &reply);
if (ret < 0) {
return ret;
}
if (status != SCMI_SUCCESS) {
return scmi_status_to_errno(status);
}
return 0;
}
``` | /content/code_sandbox/drivers/firmware/scmi/pinctrl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 347 |
```unknown
# Atmel SAM WDT configuration
config WDT_SAM
bool "Atmel SAM MCU Family Watchdog (WDT) Driver"
default y
depends on DT_HAS_ATMEL_SAM_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for Atmel SAM MCUs.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```objective-c
/*
*
*/
#ifndef _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
#define _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
#include <zephyr/drivers/firmware/scmi/transport.h>
#include <zephyr/drivers/firmware/scmi/util.h>
#include <zephyr/drivers/firmware/scmi/shmem.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/kernel.h>
#define DT_DRV_COMPAT arm_scmi
/* get a `struct device` for a protocol's shared memory area */
#define _SCMI_MBOX_SHMEM_BY_IDX(node_id, idx) \
COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
(DEVICE_DT_GET(DT_PROP_BY_IDX(node_id, shmem, idx))), \
(NULL))
/* get the name of mailbox channel's private data */
#define _SCMI_MBOX_CHAN_NAME(proto, idx)\
CONCAT(SCMI_TRANSPORT_CHAN_NAME(proto, idx), _, priv)
/* fetch a mailbox channel's doorbell */
#define _SCMI_MBOX_CHAN_DBELL(node_id, name) \
COND_CODE_1(DT_PROP_HAS_NAME(node_id, mboxes, name), \
(MBOX_DT_SPEC_GET(node_id, name)), \
({ }))
/* define private data for a protocol TX channel */
#define _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto) \
static struct scmi_mbox_channel _SCMI_MBOX_CHAN_NAME(proto, 0) =\
{ \
.shmem = _SCMI_MBOX_SHMEM_BY_IDX(node_id, 0), \
.tx = _SCMI_MBOX_CHAN_DBELL(node_id, tx), \
.tx_reply = _SCMI_MBOX_CHAN_DBELL(node_id, tx_reply), \
}
/*
* Define a mailbox channel. This does two things:
* 1) Define the mandatory `struct scmi_channel` structure
* 2) Define the mailbox-specific private data for said
* channel (i.e: a struct scmi_mbox_channel)
*/
#define _SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx) \
_SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto); \
DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, \
&(_SCMI_MBOX_CHAN_NAME(proto, idx))); \
/*
* Optionally define a mailbox channel for a protocol. This is optional
* because a protocol might not have a dedicated channel.
*/
#define _SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, proto, idx) \
COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \
(_SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx)), \
())
/* define a TX channel for a protocol node. This is preferred over
* _SCMI_MBOX_CHAN_DEFINE_OPTIONAL() since support for RX channels
* might be added later on. This macro is supposed to also define
* the RX channel
*/
#define SCMI_MBOX_PROTO_CHAN_DEFINE(node_id)\
_SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, DT_REG_ADDR(node_id), 0)
/* define and validate base protocol TX channel */
#define DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \
BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 1 || \
(DT_INST_PROP_HAS_IDX(inst, shmem, 0) && \
DT_INST_PROP_HAS_NAME(inst, mboxes, tx)), \
"bad bidirectional channel description"); \
\
BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 2 || \
(DT_INST_PROP_HAS_NAME(inst, mboxes, tx) && \
DT_INST_PROP_HAS_NAME(inst, mboxes, tx_reply)), \
"bad unidirectional channel description"); \
\
BUILD_ASSERT(DT_INST_PROP_LEN(inst, shmem) == 1, \
"bad SHMEM count"); \
\
BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) <= 2, \
"bad mbox count"); \
\
_SCMI_MBOX_CHAN_DEFINE(DT_INST(inst, DT_DRV_COMPAT), SCMI_PROTOCOL_BASE, 0)
/*
* Define the mailbox-based transport layer. What this does is:
*
* 1) Goes through all protocol nodes (children of the `scmi` node)
* and creates a `struct scmi_channel` and its associated
* `struct scmi_mbox_channel` if the protocol has a dedicated channel.
*
* 2) Creates aforementioned structures for the base protocol
* (identified by the `scmi` node)
*
* 3) "registers" the driver via `DT_INST_SCMI_TRANSPORT_DEFINE()`.
*/
#define DT_INST_SCMI_MAILBOX_DEFINE(inst, level, prio, api) \
DT_INST_FOREACH_CHILD_STATUS_OKAY(inst, SCMI_MBOX_PROTO_CHAN_DEFINE) \
DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \
DT_INST_SCMI_TRANSPORT_DEFINE(inst, NULL, NULL, NULL, level, prio, api)
struct scmi_mbox_channel {
/* SHMEM area bound to the channel */
const struct device *shmem;
/* TX dbell */
struct mbox_dt_spec tx;
/* TX reply dbell */
struct mbox_dt_spec tx_reply;
};
#endif /* _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_ */
``` | /content/code_sandbox/drivers/firmware/scmi/mailbox.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,211 |
```unknown
# Watchdog configuration options
config WDT_MCUX_WDOG
bool "MCUX WDOG driver"
default y
depends on DT_HAS_NXP_KINETIS_WDOG_ENABLED
depends on CLOCK_CONTROL
help
Enable the mcux wdog driver.
config WDT_MCUX_WDOG32
bool "MCUX WDOG32 driver"
default y
depends on DT_HAS_NXP_KINETIS_WDOG32_ENABLED
depends on CLOCK_CONTROL
help
Enable the mcux wdog32 driver.
config WDT_MCUX_WWDT
bool "MCUX WWDT driver"
default y
depends on DT_HAS_NXP_LPC_WWDT_ENABLED
help
Enable the mcux wwdt driver.
if WDT_MCUX_WWDT
config WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG
int "WWDT timeout warning interrupt configuration"
range 0 1023
default 0
help
WWDT timeout warning interrupt time. The units are
the number of watchdog counter ticks before timeout.
endif # WDT_MCUX_WWDT
``` | /content/code_sandbox/drivers/watchdog/Kconfig.mcux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 232 |
```unknown
#
config WDT_TI_TPS382X
bool "External TI TPS382x Watchdog (WDT) Driver"
default y
depends on DT_HAS_TI_TPS382X_ENABLED
depends on GPIO
help
Enable WDT driver for TI TPS382x. This is an external IC and requires
a GPIO connection from the processor.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.ti_tps382x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <soc.h>
#include <errno.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_cc13xx_cc26xx);
/* Driverlib includes */
#include <driverlib/watchdog.h>
/*
* TI CC13xx/CC26xx watchdog is a 32-bit timer that runs on the MCU clock
* with a fixed 32 divider.
*
* For the default MCU frequency of 48MHz:
* 1ms = (48e6 / 32 / 1000) = 1500 ticks
* Max. value = 2^32 / 1500 ~= 2863311 ms
*
* The watchdog will issue reset only on second in turn time-out (if the timer
* or the interrupt aren't reset after the first time-out). By default, regular
* interrupt is generated but platform supports also NMI (can be enabled by
* setting the `interrupt-nmi` boolean DT property).
*/
#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#define WATCHDOG_DIV_RATIO 32
#define WATCHDOG_MS_RATIO (CPU_FREQ / WATCHDOG_DIV_RATIO / 1000)
#define WATCHDOG_MAX_RELOAD_MS (0xFFFFFFFFu / WATCHDOG_MS_RATIO)
#define WATCHDOG_MS_TO_TICKS(_ms) ((_ms) * WATCHDOG_MS_RATIO)
struct wdt_cc13xx_cc26xx_data {
uint8_t enabled;
uint32_t reload;
wdt_callback_t cb;
uint8_t flags;
};
struct wdt_cc13xx_cc26xx_cfg {
uint32_t reg;
uint8_t irq_nmi;
void (*irq_cfg_func)(void);
};
static int wdt_cc13xx_cc26xx_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_cc13xx_cc26xx_data *data = dev->data;
/* window watchdog not supported */
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
/*
* Note: since this SoC doesn't define CONFIG_WDT_MULTISTAGE, we don't need to
* specifically check for it and return ENOTSUP
*/
if (cfg->window.max > WATCHDOG_MAX_RELOAD_MS) {
return -EINVAL;
}
data->reload = WATCHDOG_MS_TO_TICKS(cfg->window.max);
data->cb = cfg->callback;
data->flags = cfg->flags;
LOG_DBG("raw reload value: %d", data->reload);
return 0;
}
static int wdt_cc13xx_cc26xx_setup(const struct device *dev, uint8_t options)
{
const struct wdt_cc13xx_cc26xx_cfg *config = dev->config;
struct wdt_cc13xx_cc26xx_data *data = dev->data;
/*
* Note: don't check if watchdog is already enabled, an application might
* want to dynamically re-configure its options (e.g., decrease the reload
* value for critical sections).
*/
WatchdogUnlock();
/* clear any previous interrupt flags */
WatchdogIntClear();
/* Stall the WDT counter when halted by debugger */
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
WatchdogStallEnable();
} else {
WatchdogStallDisable();
}
/*
* According to TI's datasheets, the WDT is paused in STANDBY mode,
* so we simply continue with the setup => don't do this check:
* > if (options & WDT_OPT_PAUSE_IN_SLEEP) {
* > return -ENOTSUP;
* > }
*/
/* raw reload value was computed by `_install_timeout()` */
WatchdogReloadSet(data->reload);
/* use the Device Tree-configured interrupt type */
if (config->irq_nmi) {
LOG_DBG("NMI enabled");
WatchdogIntTypeSet(WATCHDOG_INT_TYPE_NMI);
} else {
WatchdogIntTypeSet(WATCHDOG_INT_TYPE_INT);
}
switch ((data->flags & WDT_FLAG_RESET_MASK)) {
case WDT_FLAG_RESET_NONE:
LOG_DBG("reset disabled");
WatchdogResetDisable();
break;
case WDT_FLAG_RESET_SOC:
LOG_DBG("reset enabled");
WatchdogResetEnable();
break;
default:
WatchdogLock();
return -ENOTSUP;
}
data->enabled = 1;
WatchdogEnable();
WatchdogLock();
LOG_DBG("done");
return 0;
}
static int wdt_cc13xx_cc26xx_disable(const struct device *dev)
{
struct wdt_cc13xx_cc26xx_data *data = dev->data;
if (!WatchdogRunning()) {
return -EFAULT;
}
/*
* Node: once started, the watchdog timer cannot be stopped!
* All we can do is disable the timeout reset, but the interrupt
* will be triggered if it was enabled (though it won't trigger the
* user callback due to `enabled` being unsed)!
*/
data->enabled = 0;
WatchdogUnlock();
WatchdogResetDisable();
WatchdogLock();
return 0;
}
static int wdt_cc13xx_cc26xx_feed(const struct device *dev, int channel_id)
{
struct wdt_cc13xx_cc26xx_data *data = dev->data;
WatchdogUnlock();
WatchdogIntClear();
WatchdogReloadSet(data->reload);
WatchdogLock();
LOG_DBG("feed %i", data->reload);
return 0;
}
static void wdt_cc13xx_cc26xx_isr(const struct device *dev)
{
struct wdt_cc13xx_cc26xx_data *data = dev->data;
/* Simulate the watchdog being disabled: don't call the handler. */
if (!data->enabled) {
return;
}
/*
* Note: don't clear the interrupt here, leave it for the callback
* to decide (by calling `_feed()`)
*/
LOG_DBG("ISR");
if (data->cb) {
data->cb(dev, 0);
}
}
static int wdt_cc13xx_cc26xx_init(const struct device *dev)
{
const struct wdt_cc13xx_cc26xx_cfg *config = dev->config;
uint8_t options = 0;
LOG_DBG("init");
config->irq_cfg_func();
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
return 0;
}
#ifdef CONFIG_DEBUG
/* when CONFIG_DEBUG is enabled, pause the WDT during debugging */
options = WDT_OPT_PAUSE_HALTED_BY_DBG;
#endif /* CONFIG_DEBUG */
return wdt_cc13xx_cc26xx_setup(dev, options);
}
static const struct wdt_driver_api wdt_cc13xx_cc26xx_api = {
.setup = wdt_cc13xx_cc26xx_setup,
.disable = wdt_cc13xx_cc26xx_disable,
.install_timeout = wdt_cc13xx_cc26xx_install_timeout,
.feed = wdt_cc13xx_cc26xx_feed,
};
#define CC13XX_CC26XX_WDT_INIT(index) \
static void wdt_cc13xx_cc26xx_irq_cfg_##index(void) \
{ \
if (DT_INST_PROP(index, interrupt_nmi)) { \
return; /* NMI interrupt is used */ \
} \
IRQ_CONNECT(DT_INST_IRQN(index), \
DT_INST_IRQ(index, priority), \
wdt_cc13xx_cc26xx_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
} \
static struct wdt_cc13xx_cc26xx_data wdt_cc13xx_cc26xx_data_##index = { \
.reload = WATCHDOG_MS_TO_TICKS( \
CONFIG_WDT_CC13XX_CC26XX_INITIAL_TIMEOUT), \
.cb = NULL, \
.flags = 0, \
}; \
static struct wdt_cc13xx_cc26xx_cfg wdt_cc13xx_cc26xx_cfg_##index = { \
.reg = DT_INST_REG_ADDR(index), \
.irq_nmi = DT_INST_PROP(index, interrupt_nmi), \
.irq_cfg_func = wdt_cc13xx_cc26xx_irq_cfg_##index, \
}; \
DEVICE_DT_INST_DEFINE(index, \
wdt_cc13xx_cc26xx_init, NULL, \
&wdt_cc13xx_cc26xx_data_##index, \
&wdt_cc13xx_cc26xx_cfg_##index, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&wdt_cc13xx_cc26xx_api);
DT_INST_FOREACH_STATUS_OKAY(CC13XX_CC26XX_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,943 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_IWDG_STM32_H_
#define ZEPHYR_DRIVERS_WATCHDOG_IWDG_STM32_H_
#include <zephyr/types.h>
/**
* @brief Driver for Independent Watchdog (IWDG) for STM32 MCUs
*
* The driver targets all STM32 SoCs. For details please refer to
* an appropriate reference manual and look for chapter called:
*
* Independent watchdog (IWDG)
*
*/
/* driver data */
struct iwdg_stm32_data {
/* IWDG peripheral instance. */
IWDG_TypeDef *Instance;
uint32_t prescaler;
uint32_t reload;
};
#define IWDG_STM32_DATA(dev) \
((struct iwdg_stm32_data * const)(dev)->data)
#define IWDG_STM32_STRUCT(dev) \
((IWDG_TypeDef *)(IWDG_STM32_DATA(dev))->Instance)
#endif /* ZEPHYR_DRIVERS_WATCHDOG_IWDG_STM32_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_iwdg_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 228 |
```c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#define DT_DRV_COMPAT snps_designware_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys_clock.h>
#include <zephyr/math/ilog2.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/clock_control.h>
#include "wdt_dw.h"
#include "wdt_dw_common.h"
LOG_MODULE_REGISTER(wdt_dw, CONFIG_WDT_LOG_LEVEL);
/* Device run time data */
struct dw_wdt_dev_data {
/* MMIO mapping information for watchdog register base address */
DEVICE_MMIO_RAM;
/* Clock frequency */
uint32_t clk_freq;
uint32_t config;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
wdt_callback_t callback;
#endif
};
/* Device constant configuration parameters */
struct dw_wdt_dev_cfg {
DEVICE_MMIO_ROM;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
/* Clock controller dev instance */
const struct device *clk_dev;
/* Identifier for timer to get clock freq from clk manager */
clock_control_subsys_t clkid;
#endif
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
void (*irq_config)(void);
#endif
uint8_t reset_pulse_length;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
/* Reset controller device configurations */
struct reset_dt_spec reset_spec;
#endif
};
static int dw_wdt_setup(const struct device *dev, uint8_t options)
{
struct dw_wdt_dev_data *const dev_data = dev->data;
uintptr_t reg_base = DEVICE_MMIO_GET(dev);
int ret;
ret = dw_wdt_check_options(options);
if (ret != 0) {
return ret;
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
/* Configure response mode */
dw_wdt_response_mode_set((uint32_t)reg_base, !!dev_data->callback);
#endif
return dw_wdt_configure((uint32_t)reg_base, dev_data->config);
}
static int dw_wdt_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *config)
{
__maybe_unused const struct dw_wdt_dev_cfg *const dev_config = dev->config;
struct dw_wdt_dev_data *const dev_data = dev->data;
uintptr_t reg_base = DEVICE_MMIO_GET(dev);
if (config == NULL) {
LOG_ERR("watchdog timeout configuration missing");
return -ENODATA;
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
if (config->callback && !dev_config->irq_config) {
#else
if (config->callback) {
#endif
LOG_ERR("Interrupt is not configured, can't set a callback.");
return -ENOTSUP;
}
if (config->flags) {
LOG_WRN("Watchdog behavior is not configurable.");
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
dev_data->callback = config->callback;
#endif
return dw_wdt_calc_period((uint32_t)reg_base, dev_data->clk_freq, config,
&dev_data->config);
}
static int dw_wdt_feed(const struct device *dev, int channel_id)
{
uintptr_t reg_base = DEVICE_MMIO_GET(dev);
/* Only channel 0 is supported */
if (channel_id) {
return -EINVAL;
}
dw_wdt_counter_restart((uint32_t)reg_base);
return 0;
}
int dw_wdt_disable(const struct device *dev)
{
int ret = -ENOTSUP;
/*
* Once watchdog is enabled by setting WDT_EN bit watchdog cannot be disabled by clearing
* WDT_EN bit and to disable/clear WDT_EN bit watchdog IP should undergo reset
*/
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
const struct dw_wdt_dev_cfg *const dev_config = dev->config;
/*
* Assert and de-assert reset only if the reset prop is defined in the device
* tree node for this dev instance
*/
if (dev_config->reset_spec.dev != NULL) {
if (!device_is_ready(dev_config->reset_spec.dev)) {
LOG_ERR("reset controller device not ready");
return -ENODEV;
}
/* Assert and de-assert reset watchdog */
ret = reset_line_toggle(dev_config->reset_spec.dev, dev_config->reset_spec.id);
if (ret != 0) {
LOG_ERR("watchdog disable/reset failed");
return ret;
}
}
#endif
return ret;
}
static const struct wdt_driver_api dw_wdt_api = {
.setup = dw_wdt_setup,
.disable = dw_wdt_disable,
.install_timeout = dw_wdt_install_timeout,
.feed = dw_wdt_feed,
};
static int dw_wdt_init(const struct device *dev)
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
const struct dw_wdt_dev_cfg *const dev_config = dev->config;
int ret;
uintptr_t reg_base = DEVICE_MMIO_GET(dev);
/* Reset watchdog controller if reset controller is supported */
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
ret = dw_wdt_disable(dev);
if (ret != 0) {
return ret;
}
#endif
/* Get clock frequency from the clock manager if supported */
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(clocks)
struct dw_wdt_dev_data *const dev_data = dev->data;
if (!device_is_ready(dev_config->clk_dev)) {
LOG_ERR("Clock controller device not ready");
return -ENODEV;
}
ret = clock_control_get_rate(dev_config->clk_dev, dev_config->clkid,
&dev_data->clk_freq);
if (ret != 0) {
LOG_ERR("Failed to get watchdog clock rate");
return ret;
}
#endif
ret = dw_wdt_probe((uint32_t)reg_base, dev_config->reset_pulse_length);
if (ret) {
return ret;
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
if (dev_config->irq_config) {
dev_config->irq_config();
}
#endif
/*
* Enable watchdog if it needs to be enabled at boot.
* watchdog timer will be started with maximum timeout
* that is the default value.
*/
if (!IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
dw_wdt_enable((uint32_t)reg_base);
}
return 0;
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
static void dw_wdt_isr(const struct device *dev)
{
struct dw_wdt_dev_data *const dev_data = dev->data;
uintptr_t reg_base = DEVICE_MMIO_GET(dev);
if (dw_wdt_interrupt_status_register_get((uint32_t)reg_base)) {
/*
* Clearing interrupt here will not assert system reset, so interrupt
* will not be cleared here.
*/
if (dev_data->callback) {
dev_data->callback(dev, 0);
}
}
}
#endif
#define CHECK_CLOCK(inst) \
!(DT_INST_NODE_HAS_PROP(inst, clock_frequency) || DT_INST_NODE_HAS_PROP(inst, clocks)) ||
#if DT_INST_FOREACH_STATUS_OKAY(CHECK_CLOCK) 0
#error Clock frequency not configured!
#endif
/* Bindings to the platform */
#define DW_WDT_IRQ_FLAGS(inst) \
COND_CODE_1(DT_INST_IRQ_HAS_CELL(inst, sense), (DT_INST_IRQ(inst, sense)), (0))
#define DW_WDT_RESET_SPEC_INIT(inst) \
.reset_spec = RESET_DT_SPEC_INST_GET(inst),
#define IRQ_CONFIG(inst) \
static void dw_wdt##inst##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), dw_wdt_isr, \
DEVICE_DT_INST_GET(inst), DW_WDT_IRQ_FLAGS(inst)); \
irq_enable(DT_INST_IRQN(inst)); \
}
#define DW_WDT_INIT(inst) \
IF_ENABLED(DT_NODE_HAS_PROP(DT_DRV_INST(inst), interrupts), (IRQ_CONFIG(inst))) \
\
static const struct dw_wdt_dev_cfg wdt_dw##inst##_config = { \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \
.reset_pulse_length = ilog2(DT_INST_PROP_OR(inst, reset_pulse_length, 2)) - 1, \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, resets), \
(DW_WDT_RESET_SPEC_INIT(inst))) \
IF_ENABLED(DT_PHA_HAS_CELL(DT_DRV_INST(inst), clocks, clkid), \
( \
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
.clkid = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, clkid), \
)) \
IF_ENABLED(DT_NODE_HAS_PROP(DT_DRV_INST(inst), interrupts), \
(.irq_config = dw_wdt##inst##_irq_config,) \
) \
}; \
\
static struct dw_wdt_dev_data wdt_dw##inst##_data = { \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clock_frequency), \
(.clk_freq = DT_INST_PROP(inst, clock_frequency)), \
(COND_CODE_1(DT_PHA_HAS_CELL(DT_DRV_INST(inst), clocks, clkid), \
(.clk_freq = 0), \
(.clk_freq = DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency))))), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &dw_wdt_init, NULL, &wdt_dw##inst##_data, \
&wdt_dw##inst##_config, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &dw_wdt_api);
DT_INST_FOREACH_STATUS_OKAY(DW_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_dw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,155 |
```unknown
# Ambiq SDK WDT
#
#
#
config WDT_AMBIQ
bool "AMBIQ WDT driver"
default y
depends on DT_HAS_AMBIQ_WATCHDOG_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_WDT
help
Enable driver for Ambiq WDT.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_
#define ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_
#include <zephyr/sys/util.h>
/**
* @file
* @brief Synopsys Designware Watchdog driver
*
* The DW_apb_wdt is an APB slave peripheral that can be used to prevent system lockup that may be
* caused by conflicting parts or programs in an SoC. This component can be configured, synthesized,
* and programmed based on user-defined options.
*
* The generated interrupt is passed to an interrupt controller. The generated reset is passed to a
* reset controller, which in turn generates a reset for the components in the system. The WDT may
* be reset independently to the other components.
*
* For more information about the specific IP capability, please refer to the DesignWare DW_apb_wdt
* Databook.
*/
/*
* Control Register
*/
#define WDT_CR 0x0
/*
* WDT enable
*/
#define WDT_CR_WDT_EN BIT(0)
/* Watchdog timer disabled
*/
#define WDT_EN_DISABLED 0x0
/* Watchdog timer enabled
*/
#define WDT_EN_ENABLED 0x1
/*
* Response mode
*/
#define WDT_CR_RMOD BIT(1)
/* Generate a system reset
*/
#define RMOD_RESET 0x0
/* First generate an interrupt and even if it is cleared
* by the time a second timeout occurs then generate a system reset
*/
#define RMOD_INTERRUPT 0x1
/*
* Reset pulse length
*/
#define WDT_CR_RPL GENMASK(4, 2)
#define RPL_PCLK_CYCLES2 0x0 /* 2 pclk cycles */
#define RPL_PCLK_CYCLES4 0x1 /* 4 pclk cycles */
#define RPL_PCLK_CYCLES8 0x2 /* 8 pclk cycles */
#define RPL_PCLK_CYCLES16 0x3 /* 16 pclk cycles */
#define RPL_PCLK_CYCLES32 0x4 /* 32 pclk cycles */
#define RPL_PCLK_CYCLES64 0x5 /* 64 pclk cycles */
#define RPL_PCLK_CYCLES128 0x6 /* 128 pclk cycles */
#define RPL_PCLK_CYCLES256 0x7 /* 256 pclk cycles */
/*
* Redundant R/W bit.
*/
#define WDT_CR_NO_NAME BIT(5)
/*
* Timeout Range Register
*/
#define WDT_TORR 0x4
#define TORR_USER0_OR_64K 0x0 /* Time out of WDT_USER_TOP_0 or 64K Clocks */
#define TORR_USER1_OR_128K 0x1 /* Time out of WDT_USER_TOP_1 or 128K Clocks */
#define TORR_USER2_OR_256K 0x2 /* Time out of WDT_USER_TOP_2 or 256K Clocks */
#define TORR_USER3_OR_512K 0x3 /* Time out of WDT_USER_TOP_3 or 512K Clocks */
#define TORR_USER4_OR_1M 0x4 /* Time out of WDT_USER_TOP_4 or 1M Clocks */
#define TORR_USER5_OR_2M 0x5 /* Time out of WDT_USER_TOP_5 or 2M Clocks */
#define TORR_USER6_OR_4M 0x6 /* Time out of WDT_USER_TOP_6 or 4M Clocks */
#define TORR_USER7_OR_8M 0x7 /* Time out of WDT_USER_TOP_7 or 8M Clocks */
#define TORR_USER8_OR_16M 0x8 /* Time out of WDT_USER_TOP_8 or 16M Clocks */
#define TORR_USER9_OR_32M 0x9 /* Time out of WDT_USER_TOP_9 or 32M Clocks */
#define TORR_USER10_OR_64M 0xa /* Time out of WDT_USER_TOP_10 or 64M Clocks */
#define TORR_USER11_OR_128M 0xb /* Time out of WDT_USER_TOP_11 or 128M Clocks */
#define TORR_USER12_OR_256M 0xc /* Time out of WDT_USER_TOP_12 or 256M Clocks */
#define TORR_USER13_OR_512M 0xd /* Time out of WDT_USER_TOP_13 or 512M Clocks */
#define TORR_USER14_OR_1G 0xe /* Time out of WDT_USER_TOP_14 or 1G Clocks */
#define TORR_USER15_OR_2G 0xf /* Time out of WDT_USER_TOP_15 or 2G Clocks */
/*
* Timeout period
*/
#define WDT_TORR_TOP GENMASK(3, 0)
/*
* Timeout period for initialization
*/
#define WDT_TORR_TOP_INIT GENMASK(7, 4)
/*
* Current Counter Value Register.
* bits WDT_CNT_WIDTH - 1 to 0
*/
#define WDT_CCVR 0x8
/*
* Counter Restart Register
*/
#define WDT_CRR 0xc
#define WDT_CRR_MASK GENMASK(7, 0)
/*
* Watchdog timer restart command
*/
#define WDT_CRR_RESTART_KEY 0x76
/*
* Interrupt Status Register
*/
#define WDT_STAT 0x10
#define WDT_STAT_MASK BIT(0)
/*
* Interrupt Clear Register
*/
#define WDT_EOI 0x14
#define WDT_EOI_MASK BIT(0)
/*
* WDT Protection level register
*/
#define WDT_PROT_LEVEL 0x1c
#define WDT_PROT_LEVEL_MASK GENMASK(2, 0)
/*
* Component Parameters Register 5
* Upper limit of Timeout Period parameters
*/
#define WDT_COMP_PARAM_5 0xe4
#define CP_WDT_USER_TOP_MAX WDT_COMP_PARAM_5
/*
* Component Parameters Register 4
* Upper limit of Initial Timeout Period parameters
*/
#define WDT_COMP_PARAM_4 0xe8
#define CP_WDT_USER_TOP_INIT_MAX WDT_COMP_PARAM_4
/*
* Component Parameters Register 3
* The value of this register is derived from the WDT_TOP_RST core Consultant parameter.
*/
#define WDT_COMP_PARAM_3 0xec
#define CD_WDT_TOP_RST WDT_COMP_PARAM_3
/*
* Component Parameters Register 2
* The value of this register is derived from the WDT_CNT_RST core Consultant parameter.
*/
#define WDT_COMP_PARAM_2 0xf0
#define CP_WDT_CNT_RST WDT_COMP_PARAM_2
/*
* Component Parameters Register 1
*/
#define WDT_COMP_PARAM_1 0xf4
/*
* The Watchdog Timer counter width.
*/
#define WDT_CNT_WIDTH GENMASK(28, 24)
/*
* Describes the initial timeout period that is available directly after reset. It controls the
* reset value of the register. If WDT_HC_TOP is 1, then the default initial time period is the
* only possible period.
*/
#define WDT_DFLT_TOP_INIT GENMASK(23, 20)
/*
* Selects the timeout period that is available directly after reset. It controls the reset value
* of the register. If WDT_HC_TOP is set to 1, then the default timeout period is the only possible
* timeout period. Can choose one of 16 values.
*/
#define WDT_DFLT_TOP GENMASK(19, 16)
/*
* The reset pulse length that is available directly after reset.
*/
#define WDT_DFLT_RPL GENMASK(12, 10)
/*
* Width of the APB Data Bus to which this component is attached.
*/
#define APB_DATA_WIDTH GENMASK(9, 8)
/*
* APB data width is 8 bits
*/
#define APB_8BITS 0x0
/*
* APB data width is 16 bits
*/
#define APB_16BITS 0x1
/*
* APB data width is 32 bits
*/
#define APB_32BITS 0x2
/*
* Configures the peripheral to have a pause enable signal (pause) on the interface that can be used
* to freeze the watchdog counter during pause mode.
*/
#define WDT_PAUSE BIT(7)
/*
* When this parameter is set to 1, timeout period range is fixed. The range increments by the power
* of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
* timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
*/
#define WDT_USE_FIX_TOP BIT(6)
/*
* When set to 1, the selected timeout period(s)
*/
#define WDT_HC_TOP BIT(5)
/*
* Configures the reset pulse length to be hard coded.
*/
#define WDT_HC_RPL BIT(4)
/*
* Configures the output response mode to be hard coded.
*/
#define WDT_HC_RMOD BIT(3)
/*
* When set to 1, includes a second timeout period that is used for initialization prior to the
* first kick.
*/
#define WDT_DUAL_TOP BIT(2)
/*
* Describes the output response mode that is available directly after reset. Indicates the output
* response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and
* an interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
* mode is the only possible output response mode.
*/
#define WDT_DFLT_RMOD BIT(1)
/*
* Configures the WDT to be enabled from reset. If this setting is 1, the WDT is always enabled and
* a write to the WDT_EN field (bit 0) of the Watchdog Timer Control Register (WDT_CR) to disable
* it has no effect.
*/
#define WDT_ALWAYS_EN BIT(0)
/*
* Component Version Register
* ASCII value for each number in the version, followed by *.
* For example, 32_30_31_2A represents the version 2.01*.
*/
#define WDT_COMP_VERSION 0xf8
/*
* Component Type Register
* Designware Component Type number = 0x44_57_01_20.
* This assigned unique hex value is constant, and is derived from the two ASCII letters "DW"
* followed by a 16-bit unsigned number.
*/
#define WDT_COMP_TYPE 0xfc
#define WDT_COMP_TYPE_VALUE 0x44570120
/**
* @brief Enable watchdog
*
* @param base Device base address.
*/
static inline void dw_wdt_enable(const uint32_t base)
{
uint32_t control = sys_read32(base + WDT_CR);
control |= WDT_CR_WDT_EN;
sys_write32(control, base + WDT_CR);
}
/**
* @brief Set response mode.
*
* Selects whether watchdog should generate interrupt on the first timeout (true) or reset system
* (false)
*
* @param base Device base address.
* @param mode Response mode.
* false = Generate a system reset,
* true = First generate an interrupt and even if it is cleared by the time a second
* timeout occurs then generate a system reset
*/
static inline void dw_wdt_response_mode_set(const uint32_t base, const bool mode)
{
uint32_t control = sys_read32(base + WDT_CR);
if (mode)
control |= WDT_CR_RMOD;
else
control &= ~WDT_CR_RMOD;
sys_write32(control, base + WDT_CR);
}
/**
* @brief Set reset pulse length.
*
* @param base Device base address.
* @param pclk_cycles Reset pulse length selector (2 to 256 pclk cycles)
*/
static inline void dw_wdt_reset_pulse_length_set(const uint32_t base, const uint32_t pclk_cycles)
{
uint32_t control = sys_read32(base + WDT_CR);
control &= ~WDT_CR_RPL;
control |= FIELD_PREP(WDT_CR_RPL, pclk_cycles);
sys_write32(control, base + WDT_CR);
}
/**
* @brief Set timeout period.
*
* @param base Device base address.
* @param timeout_period Timeout period value selector
*/
static inline void dw_wdt_timeout_period_set(const uint32_t base, const uint32_t timeout_period)
{
uint32_t timeout = sys_read32(base + WDT_TORR);
timeout &= ~WDT_TORR_TOP;
timeout |= FIELD_PREP(WDT_TORR_TOP, timeout_period);
sys_write32(timeout, base + WDT_TORR);
}
/**
* @brief Get actual timeout period range.
*
* @param base Device base address.
* @return Actual timeout period range
*/
static inline uint32_t dw_wdt_timeout_period_get(const uint32_t base)
{
return FIELD_GET(WDT_TORR_TOP, sys_read32(base + WDT_TORR));
}
/**
* @brief Timeout period for initialization.
*
* @param base Device base address.
* @param timeout_period Timeout period value selector
*/
static inline void dw_wdt_timeout_period_init_set(const uint32_t base,
const uint32_t timeout_period)
{
uint32_t timeout = sys_read32(base + WDT_TORR);
timeout &= ~WDT_TORR_TOP_INIT;
timeout |= FIELD_PREP(WDT_TORR_TOP_INIT, timeout_period);
sys_write32(timeout, base + WDT_TORR);
}
/**
* @brief Get WDT Current Counter Value Register.
*
* @param base Device base address.
* @param wdt_counter_width Watchdog Timer counter width
* @return The current value of the internal counter
*/
static inline uint32_t dw_wdt_current_counter_value_register_get(const uint32_t base,
uint32_t wdt_counter_width)
{
uint32_t current_counter_value = sys_read32(base + WDT_CCVR);
current_counter_value &= (1 << (wdt_counter_width - 1));
return current_counter_value;
}
/**
* @brief Counter Restart
*
* Restart the WDT counter. A restart also clears the WDT interrupt.
*
* @param base Device base address.
*/
static inline void dw_wdt_counter_restart(const uint32_t base)
{
sys_write32(WDT_CRR_RESTART_KEY, base + WDT_CRR);
}
/**
* @brief Get Interrupt status
*
* @param base Device base address.
* @return 0x0 (INACTIVE): Interrupt is inactive,
* 0x1 (ACTIVE): Interrupt is active regardless of polarity
*/
static inline uint32_t dw_wdt_interrupt_status_register_get(const uint32_t base)
{
return sys_read32(base + WDT_STAT) & 1;
}
/**
* @brief Clears the watchdog interrupt.
*
* This can be used to clear the interrupt without restarting the watchdog counter.
*
* @param base Device base address.
*/
static inline void dw_wdt_clear_interrupt(const uint32_t base)
{
sys_read32(base + WDT_EOI);
}
/**
* @brief Gets the upper limit of Timeout Period parameters.
*
* @param base Device base address.
* @return Upper limit of Timeout Period parameters.
*/
static inline uint32_t dw_wdt_user_top_max_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_PARAM_5);
}
/**
* @brief Gets the Upper limit of Initial Timeout Period parameters.
*
* @param base Device base address.
* @return Upper limit of Initial Timeout Period parameters.
*/
static inline uint32_t dw_wdt_user_top_init_max_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_PARAM_4);
}
/**
* @brief Get the default value of the timeout range that is selected after reset.
*
* @param base Device base address.
* @return Default timeout range after reset
*/
static inline uint32_t dw_wdt_timeout_period_rst_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_PARAM_3);
}
/**
* @brief Get the default value of the timeout counter that is set after reset.
*
* @param base Device base address.
* @return Default timeout counter value
*/
static inline uint32_t dw_wdt_cnt_rst_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_PARAM_2);
}
/**
* @brief Get the Watchdog timer counter width.
*
* @param base Device base address.
* @return Width of the counter register
*/
static inline uint32_t dw_wdt_cnt_width_get(const uint32_t base)
{
return FIELD_GET(WDT_CNT_WIDTH, sys_read32(base + WDT_COMP_PARAM_1)) + 16;
}
/**
* @brief Describes the initial timeout period that is available directly after reset.
*
* It controls the reset value of the register. If WDT_HC_TOP is 1, then the default initial time
* period is the only possible period.
*
* @param base Device base address.
* @return Initial timeout period
*/
static inline uint32_t dw_wdt_dflt_timeout_period_init_get(const uint32_t base)
{
return FIELD_GET(WDT_DFLT_TOP_INIT, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Get default timeout period
*
* Selects the timeout period that is available directly after reset. It controls the reset value
* of the register. If WDT_HC_TOP is set to 1, then the default timeout period is the only possible
* timeout period. Can choose one of 16 values.
*
* @param base Device base address.
* @return Default timeout period
*/
static inline uint32_t dw_wdt_dflt_timeout_period_get(const uint32_t base)
{
return FIELD_GET(WDT_DFLT_TOP, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief The reset pulse length that is available directly after reset.
*
* @param base Device base address.
* @return Reset pulse length
*/
static inline uint32_t dw_wdt_dflt_rpl_get(const uint32_t base)
{
return FIELD_GET(WDT_DFLT_RPL, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Width of the APB Data Bus to which this component is attached.
*
* @param base Device base address.
* @return APB data width
* 0x0 (APB_8BITS): APB data width is 8 bits
* 0x1 (APB_16BITS): APB data width is 16 bits
* 0x2 (APB_32BITS): APB data width is 32 bits
*/
static inline uint32_t dw_wdt_apb_data_width_get(const uint32_t base)
{
return FIELD_GET(APB_DATA_WIDTH, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Get configuration status of a pause signal
*
* Check the peripheral is configured to have a pause enable signal (pause) on the interface that
* can be used to freeze the watchdog counter during pause mode.
*
* @param base Device base address.
* @return 0x0 (DISABLED): Pause enable signal is non existent
* 0x1 (ENABLED): Pause enable signal is included
*/
static inline uint32_t dw_wdt_pause_get(const uint32_t base)
{
return FIELD_GET(WDT_PAUSE, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Get fixed period status
*
* When this parameter is set to 1, timeout period range is fixed. The range increments by the power
* of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
* timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
*
* @param base Device base address.
* @return 0x0 (USERDEFINED): User must define timeout values
* 0x1 (PREDEFINED): Use predefined timeout values
*/
static inline uint32_t dw_wdt_use_fix_timeout_period_get(const uint32_t base)
{
return FIELD_GET(WDT_USE_FIX_TOP, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Checks if period is hardcoded
*
* When set to 1, the selected timeout period(s) is set to be hard coded.
*
* @param base Device base address.
* @return 0x0 (PROGRAMMABLE): Timeout period is programmable
* 0x1 (HARDCODED): Timeout period is hard coded
*/
static inline uint32_t dw_wdt_hc_timeout_period_get(const uint32_t base)
{
return FIELD_GET(WDT_HC_TOP, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Checks if reset pulse length is hardcoded.
*
* @param base Device base address.
* @return 0x0 (PROGRAMMABLE): Reset pulse length is programmable
* 0x1 (HARDCODED): Reset pulse length is hardcoded
*/
static inline uint32_t dw_wdt_hc_reset_pulse_length_get(const uint32_t base)
{
return FIELD_GET(WDT_HC_RPL, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Checks if the output response mode is hardcoded.
*
* @param base Device base address.
* @return 0x0 (PROGRAMMABLE): Output response mode is programmable
* 0x1 (HARDCODED): Output response mode is hard coded
*/
static inline uint32_t dw_wdt_hc_response_mode_get(const uint32_t base)
{
return FIELD_GET(WDT_HC_RMOD, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Checks if a second timeout period if supported.
*
* When set to 1, includes a second timeout period that is used for initialization prior to the
* first kick.
*
* @param base Device base address.
* @return 0x0 (DISABLED): Second timeout period is not present
* 0x1 (ENABLED): Second timeout period is present
*/
static inline uint32_t dw_wdt_dual_timeout_period_get(const uint32_t base)
{
return FIELD_GET(WDT_DUAL_TOP, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Get default response mode
*
* Describes the output response mode that is available directly after reset. Indicates the output
* response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and an
* interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
* mode is the only possible output response mode.
*
* @param base Device base address.
* @return 0x0 (DISABLED): System reset only
* 0x1 (ENABLED): Interrupt and system reset
*/
static inline uint32_t dw_wdt_dflt_response_mode_get(const uint32_t base)
{
return FIELD_GET(WDT_DFLT_RMOD, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief Checks if watchdog is enabled from reset
*
* If this setting is 1, the WDT is always enabled and a write to the WDT_EN field (bit 0) of the
* Watchdog Timer Control Register (WDT_CR) to disable it has no effect.
*
* @param base Device base address.
* @return 0x0 (DISABLED): Watchdog timer disabled on reset
* 0x1 (ENABLED): Watchdog timer enabled on reset
*/
static inline uint32_t dw_wdt_always_en_get(const uint32_t base)
{
return FIELD_GET(WDT_ALWAYS_EN, sys_read32(base + WDT_COMP_PARAM_1));
}
/**
* @brief ASCII value for each number in the version
*
* For example, 32_30_31_2A represents the version 2.01s
*
* @param base Device base address.
* @return Component version code
*/
static inline uint32_t dw_wdt_comp_version_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_VERSION);
}
/**
* @brief Get Component Type
*
* @param base Device base address.
* @return Components type code
*/
static inline uint32_t dw_wdt_comp_type_get(const uint32_t base)
{
return sys_read32(base + WDT_COMP_TYPE);
}
#endif /* !ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_dw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,379 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_watchdog
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/device.h>
#include <zephyr/sys_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_litex, CONFIG_WDT_LOG_LEVEL);
#include <soc.h>
struct wdt_litex_data {
wdt_callback_t callback;
uint32_t timeout;
bool reset_soc_mode;
bool pause_halted;
};
struct wdt_litex_config {
uint32_t control_addr;
uint32_t cycles_addr;
uint32_t cycles_size;
uint32_t remaining_addr;
uint32_t ev_status_addr;
uint32_t ev_pending_addr;
uint32_t ev_enable_addr;
void (*irq_cfg_func)(void);
};
#define CONTROL_FEED_BIT BIT(0)
#define CONTROL_ENABLE_BIT BIT(8)
#define CONTROL_RESET_BIT BIT(16)
#define CONTROL_PAUSE_HALTED_BIT BIT(24)
static bool wdt_litex_is_enabled(const struct device *dev)
{
const struct wdt_litex_config *config = dev->config;
return litex_read8(config->control_addr) & BIT(0);
}
static void wdt_litex_irq_enable(const struct device *dev)
{
const struct wdt_litex_config *config = dev->config;
struct wdt_litex_data *data = dev->data;
if (!data->callback) {
return;
}
litex_write8(BIT(0), config->ev_pending_addr);
litex_write8(BIT(0), config->ev_enable_addr);
}
static void wdt_litex_enable(const struct device *dev)
{
const struct wdt_litex_config *config = dev->config;
struct wdt_litex_data *data = dev->data;
uint32_t control;
if (config->cycles_size <= 4) {
litex_write32(k_ms_to_cyc_floor32(data->timeout), config->cycles_addr);
} else {
litex_write64(k_ms_to_cyc_floor64(data->timeout), config->cycles_addr);
}
control = CONTROL_FEED_BIT | CONTROL_ENABLE_BIT;
if (data->reset_soc_mode) {
control |= CONTROL_RESET_BIT;
}
if (data->pause_halted) {
control |= CONTROL_PAUSE_HALTED_BIT;
}
litex_write32(control, config->control_addr);
wdt_litex_irq_enable(dev);
}
static int wdt_litex_disable(const struct device *dev)
{
const struct wdt_litex_config *config = dev->config;
litex_write8(0, config->ev_enable_addr);
if (!wdt_litex_is_enabled(dev)) {
return -EFAULT;
}
litex_write16(CONTROL_ENABLE_BIT, config->control_addr);
return 0;
}
static int wdt_litex_feed(const struct device *dev, int channel_id)
{
const struct wdt_litex_config *config = dev->config;
if (channel_id != 0) {
return -EINVAL;
}
litex_write8(CONTROL_FEED_BIT, config->control_addr);
return 0;
}
static int wdt_litex_setup(const struct device *dev, uint8_t options)
{
struct wdt_litex_data *data = dev->data;
data->pause_halted = !!(options & WDT_OPT_PAUSE_HALTED_BY_DBG);
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
if (wdt_litex_is_enabled(dev)) {
return -EBUSY;
}
wdt_litex_enable(dev);
wdt_litex_feed(dev, 0);
return 0;
}
static int wdt_litex_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
const struct wdt_litex_config *config = dev->config;
struct wdt_litex_data *data = dev->data;
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
if (cfg->window.max > (config->cycles_size <= 4 ? k_cyc_to_ms_floor32(UINT32_MAX)
: k_cyc_to_ms_floor64(UINT64_MAX))) {
return -EINVAL;
}
if (wdt_litex_is_enabled(dev)) {
return -EBUSY;
}
data->timeout = cfg->window.max;
data->callback = cfg->callback;
/* Set mode of watchdog and callback */
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
LOG_DBG("Configuring reset SOC mode");
data->reset_soc_mode = true;
break;
case WDT_FLAG_RESET_NONE:
LOG_DBG("Configuring non-reset mode");
data->reset_soc_mode = false;
break;
default:
LOG_ERR("Unsupported watchdog config flag");
return -EINVAL;
}
return 0;
}
static void wdt_litex_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
const struct wdt_litex_config *config = dev->config;
struct wdt_litex_data *data = dev->data;
unsigned int key = irq_lock();
if (data->callback) {
data->callback(dev, 0);
}
litex_write8(BIT(0), config->ev_pending_addr);
irq_unlock(key);
}
static int wdt_litex_init(const struct device *dev)
{
const struct wdt_litex_config *const config = dev->config;
config->irq_cfg_func();
#ifndef CONFIG_WDT_DISABLE_AT_BOOT
wdt_litex_enable(dev);
#endif
return 0;
}
static const struct wdt_driver_api wdt_api = {
.setup = wdt_litex_setup,
.disable = wdt_litex_disable,
.install_timeout = wdt_litex_install_timeout,
.feed = wdt_litex_feed,
};
#define LITEX_WDT_INIT(n) \
static void wdt_litex_cfg_func_##n(void); \
\
static struct wdt_litex_data wdt_litex_data##n; \
static struct wdt_litex_config wdt_litex_config##n = { \
.control_addr = DT_INST_REG_ADDR_BY_NAME(n, control), \
.cycles_addr = DT_INST_REG_ADDR_BY_NAME(n, cycles), \
.cycles_size = DT_INST_REG_SIZE_BY_NAME(n, cycles), \
.remaining_addr = DT_INST_REG_ADDR_BY_NAME(n, remaining), \
.ev_status_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_status), \
.ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_pending), \
.ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, ev_enable), \
.irq_cfg_func = wdt_litex_cfg_func_##n, \
}; \
\
DEVICE_DT_INST_DEFINE(n, wdt_litex_init, NULL, &wdt_litex_data##n, &wdt_litex_config##n, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_api) \
\
static void wdt_litex_cfg_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), wdt_litex_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(LITEX_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,605 |
```c
/*
*
*/
#include <zephyr/drivers/watchdog.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_wdt_setup(const struct device *dev, uint8_t options)
{
K_OOPS(K_SYSCALL_DRIVER_WDT(dev, setup));
return z_impl_wdt_setup(dev, options);
}
#include <zephyr/syscalls/wdt_setup_mrsh.c>
static inline int z_vrfy_wdt_disable(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_WDT(dev, disable));
return z_impl_wdt_disable(dev);
}
#include <zephyr/syscalls/wdt_disable_mrsh.c>
static inline int z_vrfy_wdt_feed(const struct device *dev, int channel_id)
{
K_OOPS(K_SYSCALL_DRIVER_WDT(dev, feed));
return z_impl_wdt_feed(dev, channel_id);
}
#include <zephyr/syscalls/wdt_feed_mrsh.c>
``` | /content/code_sandbox/drivers/watchdog/wdt_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 198 |
```c
/*
*
*/
#define DT_DRV_COMPAT ene_kb1200_watchdog
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <errno.h>
#include <reg/wdt.h>
/* Device config */
struct wdt_kb1200_config {
struct wdt_regs *wdt;
};
/* Device data */
struct wdt_kb1200_data {
wdt_callback_t cb;
bool timeout_installed;
};
/* WDT api functions */
static int wdt_kb1200_setup(const struct device *dev, uint8_t options)
{
struct wdt_kb1200_config const *cfg = dev->config;
struct wdt_kb1200_data *data = dev->data;
if (!data->timeout_installed) {
printk("No valid WDT timeout installed");
return -EINVAL;
}
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
printk("WDT_OPT_PAUSE_HALTED_BY_DBG is not supported");
return -ENOTSUP;
}
/* Setting Clock Source */
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
cfg->wdt->WDTCFG = WDT_ADCO32K;
} else {
cfg->wdt->WDTCFG = WDT_PHER32K;
}
/* Clear Pending Flag */
cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT);
/* WDT enable */
cfg->wdt->WDTCFG |= WDT_FUNCTON_ENABLE;
return 0;
}
static int wdt_kb1200_disable(const struct device *dev)
{
struct wdt_kb1200_config const *cfg = dev->config;
struct wdt_kb1200_data *data = dev->data;
if (!(cfg->wdt->WDTCFG & WDT_FUNCTON_ENABLE)) {
return -EALREADY;
}
/* WDT disable, write bit 7~4 = 1001b */
cfg->wdt->WDTCFG = (cfg->wdt->WDTCFG & ~WDT_FUNCTON_ENABLE) | WDT_DISABLE_PASSWORD;
/* Clear Pending Flag */
cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT);
/* Need disable IE,or the wdt-half-event interrupt will be entered */
cfg->wdt->WDTIE &= ~WDT_HALF_WAY_EVENT;
data->timeout_installed = false;
return 0;
}
static int wdt_kb1200_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
struct wdt_kb1200_config const *cfg = dev->config;
struct wdt_kb1200_data *data = dev->data;
/* Watchdog Counter Match Value */
if (config->window.min > 0U) {
data->timeout_installed = false;
return -EINVAL;
}
cfg->wdt->WDTM = (config->window.max * 1000) / WDT_TICK_TIME_US;
/* (HW design) The counter match value must be >= 3 */
if (cfg->wdt->WDTM < WDT_MIN_CNT) {
data->timeout_installed = false;
return -EINVAL;
}
/* Watchdog behavior flags */
if ((config->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_SOC) {
/* Reset: SoC */
cfg->wdt->WDTCFG_T = WDT_RESET_WHOLE_CHIP_WO_GPIO;
} else if ((config->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_CPU_CORE) {
/* Reset: CPU core */
cfg->wdt->WDTCFG_T = WDT_RESET_WHOLE_CHIP;
} else {
/* Reset: none */
cfg->wdt->WDTCFG_T = WDT_RESET_ONLY_MCU;
}
/* Watchdog callback function */
data->cb = config->callback;
if (data->cb) {
cfg->wdt->WDTIE |= WDT_HALF_WAY_EVENT;
} else {
/* If the callback function is NULL,the SoC will be reset directly.
* But still need enable interrupt.
*/
cfg->wdt->WDTIE |= WDT_HALF_WAY_EVENT;
}
data->timeout_installed = true;
return 0;
}
static int wdt_kb1200_feed(const struct device *dev, int channel_id)
{
struct wdt_kb1200_config const *cfg = dev->config;
ARG_UNUSED(dev);
ARG_UNUSED(channel_id);
if (!(cfg->wdt->WDTCFG & WDT_FUNCTON_ENABLE)) {
return -EINVAL;
}
/* Re-enable to reset counter */
cfg->wdt->WDTCFG |= WDT_FUNCTON_ENABLE;
/* Clear Pending Flag */
cfg->wdt->WDTPF = WDT_HALF_WAY_EVENT;
return 0;
}
static void wdt_kb1200_isr(const struct device *dev)
{
struct wdt_kb1200_data *data = dev->data;
if (data->cb) {
data->cb(dev, 0);
}
}
static const struct wdt_driver_api wdt_kb1200_api = {
.setup = wdt_kb1200_setup,
.disable = wdt_kb1200_disable,
.install_timeout = wdt_kb1200_install_timeout,
.feed = wdt_kb1200_feed,
};
static int wdt_kb1200_init(const struct device *dev)
{
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
wdt_kb1200_disable(dev);
}
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), wdt_kb1200_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
static const struct wdt_kb1200_config wdt_kb1200_config = {
.wdt = (struct wdt_regs *)DT_INST_REG_ADDR(0),
};
static struct wdt_kb1200_data wdt_kb1200_dev_data;
DEVICE_DT_INST_DEFINE(0, wdt_kb1200_init, NULL, &wdt_kb1200_dev_data, &wdt_kb1200_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_kb1200_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_ene_kb1200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,354 |
```unknown
# Kconfig Andes Watchdog configuration options
#
#
#
config WDT_ANDES_ATCWDT200
bool "Andes Watchdog driver"
default y
depends on DT_HAS_ANDESTECH_ATCWDT200_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
select COUNTER
help
Enable driver for the Andes Watchdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.andes_atcwdt200 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```c
/*
*
*/
/**
* @brief Watchdog (WDT) Driver for SiFive Freedom
*/
#define DT_DRV_COMPAT sifive_wdt
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/watchdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_sifive);
#define WDOGCFG_SCALE_MAX 0xf
#define WDOGCFG_SCALE_SHIFT 0
#define WDOGCFG_SCALE_MASK (WDOGCFG_SCALE_MAX << WDOGCFG_SCALE_SHIFT)
#define WDOGCFG_RSTEN BIT(8)
#define WDOGCFG_ZEROCMP BIT(9)
#define WDOGCFG_ENALWAYS BIT(12)
#define WDOGCFG_COREAWAKE BIT(13)
#define WDOGCFG_IP0 BIT(28)
#define WDOGCMP_MAX 0xffff
#define WDOG_KEY 0x51f15e
#define WDOG_FEED 0xd09f00d
#define WDOG_CLK 32768
struct wdt_sifive_reg {
/* offset: 0x000 */
uint32_t wdogcfg;
uint32_t dummy0;
uint32_t wdogcount;
uint32_t dummy1;
/* offset: 0x010 */
uint32_t wdogs;
uint32_t dummy2;
uint32_t wdogfeed;
uint32_t wdogkey;
/* offset: 0x020 */
uint32_t wdogcmp0;
};
struct wdt_sifive_device_config {
uintptr_t regs;
};
struct wdt_sifive_dev_data {
wdt_callback_t cb;
bool enable_cb;
bool timeout_valid;
};
#define DEV_REG(dev) \
((struct wdt_sifive_reg *) \
((const struct wdt_sifive_device_config *const)(dev)->config)->regs)
/**
* @brief Set maximum length of timeout to watchdog
*
* @param dev Watchdog device struct
*/
static void wdt_sifive_set_max_timeout(const struct device *dev)
{
volatile struct wdt_sifive_reg *wdt = DEV_REG(dev);
uint32_t t;
t = wdt->wdogcfg;
t |= WDOGCFG_SCALE_MASK;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcfg = t;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcmp0 = WDOGCMP_MAX;
}
static void wdt_sifive_isr(const struct device *dev)
{
volatile struct wdt_sifive_reg *wdt = DEV_REG(dev);
struct wdt_sifive_dev_data *data = dev->data;
uint32_t t;
wdt_sifive_set_max_timeout(dev);
t = wdt->wdogcfg;
t &= ~WDOGCFG_IP0;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcfg = t;
if (data->enable_cb && data->cb) {
data->enable_cb = false;
data->cb(dev, 0);
}
}
static int wdt_sifive_disable(const struct device *dev)
{
struct wdt_sifive_dev_data *data = dev->data;
wdt_sifive_set_max_timeout(dev);
data->enable_cb = false;
return 0;
}
static int wdt_sifive_setup(const struct device *dev, uint8_t options)
{
volatile struct wdt_sifive_reg *wdt = DEV_REG(dev);
struct wdt_sifive_dev_data *data = dev->data;
uint32_t t, mode;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
mode = WDOGCFG_ENALWAYS;
if ((options & WDT_OPT_PAUSE_IN_SLEEP) ==
WDT_OPT_PAUSE_IN_SLEEP) {
mode = WDOGCFG_COREAWAKE;
}
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ==
WDT_OPT_PAUSE_HALTED_BY_DBG) {
mode = WDOGCFG_COREAWAKE;
}
t = wdt->wdogcfg;
t &= ~(WDOGCFG_ENALWAYS | WDOGCFG_COREAWAKE);
t |= mode;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcfg = t;
return 0;
}
/**
* @brief Calculates the watchdog counter value (wdogcmp0) and
* scaler (wdogscale) to be installed in the watchdog timer
*
* @param timeout Timeout value in milliseconds.
* @param clk Clock of watchdog in Hz.
* @param scaler Pointer to return scaler power of 2
*
* @return Watchdog counter value
*/
static int wdt_sifive_convtime(uint32_t timeout, int clk, int *scaler)
{
uint64_t cnt;
int i;
cnt = (uint64_t)timeout * clk / 1000;
for (i = 0; i < 16; i++) {
if (cnt <= WDOGCMP_MAX) {
break;
}
cnt >>= 1;
}
if (i == 16) {
/* Maximum counter and scaler */
LOG_ERR("Invalid timeout value allowed range");
*scaler = WDOGCFG_SCALE_MAX;
return WDOGCMP_MAX;
}
*scaler = i;
return cnt;
}
static int wdt_sifive_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
volatile struct wdt_sifive_reg *wdt = DEV_REG(dev);
struct wdt_sifive_dev_data *data = dev->data;
uint32_t mode = 0, t;
int cmp, scaler;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
/*
* Freedom watchdog does not support window timeout config.
* So use max field of window.
*/
cmp = wdt_sifive_convtime(cfg->window.max, WDOG_CLK, &scaler);
if (cmp < 0 || WDOGCMP_MAX < cmp) {
LOG_ERR("Unsupported watchdog timeout\n");
return -EINVAL;
}
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
/* WDT supports global SoC reset but cannot callback. */
mode = WDOGCFG_RSTEN | WDOGCFG_ZEROCMP;
break;
case WDT_FLAG_RESET_NONE:
/* No reset */
mode = WDOGCFG_ZEROCMP;
break;
case WDT_FLAG_RESET_CPU_CORE:
default:
LOG_ERR("Unsupported watchdog config flags\n");
wdt_sifive_disable(dev);
return -ENOTSUP;
}
t = wdt->wdogcfg;
t &= ~(WDOGCFG_RSTEN | WDOGCFG_ZEROCMP | WDOGCFG_SCALE_MASK);
t |= mode | scaler;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcfg = t;
wdt->wdogkey = WDOG_KEY;
wdt->wdogcmp0 = cmp;
data->cb = cfg->callback;
data->enable_cb = true;
data->timeout_valid = true;
return 0;
}
static int wdt_sifive_feed(const struct device *dev, int channel_id)
{
volatile struct wdt_sifive_reg *wdt = DEV_REG(dev);
wdt->wdogkey = WDOG_KEY;
wdt->wdogfeed = WDOG_FEED;
return 0;
}
static const struct wdt_driver_api wdt_sifive_api = {
.setup = wdt_sifive_setup,
.disable = wdt_sifive_disable,
.install_timeout = wdt_sifive_install_timeout,
.feed = wdt_sifive_feed,
};
static void wdt_sifive_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority), wdt_sifive_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
static int wdt_sifive_init(const struct device *dev)
{
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
wdt_sifive_disable(dev);
#endif
wdt_sifive_irq_config();
return 0;
}
static struct wdt_sifive_dev_data wdt_sifive_data;
static const struct wdt_sifive_device_config wdt_sifive_cfg = {
.regs = DT_INST_REG_ADDR(0),
};
DEVICE_DT_INST_DEFINE(0, wdt_sifive_init, NULL,
&wdt_sifive_data, &wdt_sifive_cfg, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sifive_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,927 |
```unknown
# LiteX WDT configuration
config WDT_LITEX
bool "LiteX Watchdog (WDT) Driver"
default y
depends on DT_HAS_LITEX_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for LiteX.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/* wdt_xec.c - Microchip XEC watchdog driver */
#define DT_DRV_COMPAT microchip_xec_watchdog
/*
*
*/
#include <zephyr/irq.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_mchp_xec);
#include <zephyr/drivers/watchdog.h>
#include <soc.h>
#include <errno.h>
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"add exactly one wdog node to the devicetree");
struct wdt_xec_config {
struct wdt_regs *regs;
uint8_t girq;
uint8_t girq_pos;
};
struct wdt_xec_data {
wdt_callback_t cb;
bool timeout_installed;
};
static int wdt_xec_setup(const struct device *dev, uint8_t options)
{
struct wdt_xec_config const *cfg = dev->config;
struct wdt_xec_data *data = dev->data;
struct wdt_regs *regs = cfg->regs;
if (regs->CTRL & MCHP_WDT_CTRL_EN) {
return -EBUSY;
}
if (!data->timeout_installed) {
LOG_ERR("No valid WDT timeout installed");
return -EINVAL;
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_WRN("WDT_OPT_PAUSE_IN_SLEEP is not supported");
return -ENOTSUP;
}
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
regs->CTRL |= MCHP_WDT_CTRL_JTAG_STALL_EN;
} else {
regs->CTRL &= ~MCHP_WDT_CTRL_JTAG_STALL_EN;
}
regs->CTRL |= MCHP_WDT_CTRL_EN;
LOG_DBG("WDT Setup and enabled");
return 0;
}
static int wdt_xec_disable(const struct device *dev)
{
struct wdt_xec_config const *cfg = dev->config;
struct wdt_xec_data *data = dev->data;
struct wdt_regs *regs = cfg->regs;
if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) {
return -EALREADY;
}
regs->CTRL &= ~MCHP_WDT_CTRL_EN;
data->timeout_installed = false;
LOG_DBG("WDT Disabled");
return 0;
}
static int wdt_xec_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
struct wdt_xec_config const *cfg = dev->config;
struct wdt_xec_data *data = dev->data;
struct wdt_regs *regs = cfg->regs;
if (regs->CTRL & MCHP_WDT_CTRL_EN) {
return -EBUSY;
}
if (config->window.min > 0U) {
data->timeout_installed = false;
return -EINVAL;
}
regs->LOAD = 0;
data->cb = config->callback;
if (data->cb) {
regs->CTRL |= MCHP_WDT_CTRL_MODE_IRQ;
regs->IEN |= MCHP_WDT_IEN_EVENT_IRQ_EN;
LOG_DBG("WDT callback enabled");
} else {
/* Setting WDT_FLAG_RESET_SOC or not will have no effect:
* even after the cb, if anything is done, SoC will reset
*/
regs->CTRL &= ~MCHP_WDT_CTRL_MODE_IRQ;
regs->IEN &= ~MCHP_WDT_IEN_EVENT_IRQ_EN;
LOG_DBG("WDT Reset enabled");
}
/* Since it almost takes 1ms to decrement the load register
* (See datasheet 18.6.1.4: 33/32.768 KHz = 1.007ms)
* Let's use the given window directly.
*/
regs->LOAD = config->window.max;
data->timeout_installed = true;
return 0;
}
static int wdt_xec_feed(const struct device *dev, int channel_id)
{
struct wdt_xec_config const *cfg = dev->config;
struct wdt_regs *regs = cfg->regs;
ARG_UNUSED(dev);
ARG_UNUSED(channel_id);
if (!(regs->CTRL & MCHP_WDT_CTRL_EN)) {
return -EINVAL;
}
LOG_DBG("WDT Kicking");
regs->KICK = 1;
return 0;
}
static void wdt_xec_isr(const struct device *dev)
{
struct wdt_xec_config const *cfg = dev->config;
struct wdt_xec_data *data = dev->data;
struct wdt_regs *regs = cfg->regs;
LOG_DBG("WDT ISR");
if (data->cb) {
data->cb(dev, 0);
}
#ifdef CONFIG_SOC_SERIES_MEC172X
mchp_soc_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
#else
MCHP_GIRQ_SRC(MCHP_WDT_GIRQ) = BIT(cfg->girq_pos);
#endif
regs->IEN &= ~MCHP_WDT_IEN_EVENT_IRQ_EN;
}
static const struct wdt_driver_api wdt_xec_api = {
.setup = wdt_xec_setup,
.disable = wdt_xec_disable,
.install_timeout = wdt_xec_install_timeout,
.feed = wdt_xec_feed,
};
static int wdt_xec_init(const struct device *dev)
{
struct wdt_xec_config const *cfg = dev->config;
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
wdt_xec_disable(dev);
}
#ifdef CONFIG_SOC_SERIES_MEC172X
mchp_soc_ecia_girq_src_en(cfg->girq, cfg->girq_pos);
#else
MCHP_GIRQ_ENSET(MCHP_WDT_GIRQ) = BIT(cfg->girq_pos);
#endif
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
wdt_xec_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
static const struct wdt_xec_config wdt_xec_config_0 = {
.regs = (struct wdt_regs *)(DT_INST_REG_ADDR(0)),
.girq = DT_INST_PROP_BY_IDX(0, girqs, 0),
.girq_pos = DT_INST_PROP_BY_IDX(0, girqs, 1),
};
static struct wdt_xec_data wdt_xec_dev_data;
DEVICE_DT_INST_DEFINE(0, wdt_xec_init, NULL,
&wdt_xec_dev_data, &wdt_xec_config_0,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&wdt_xec_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,453 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_
#define ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_
/*
* Get register offset for core
*/
#define DSPBRx_OFFSET(x) (0x0020 * (x))
/*
* DSPCxWDTCS
* DSP Core Watch Dog Timer Control & Status
*
* Offset: 04h
* Block: DSPBRx
*
* This register controls the DSP Core watch dog timer policy.
*/
#define DSPCxWDTCS 0x0004
/*
* Pause Code
* type: WO, rst: 00b, rst domain: nan
*
* FW write 76h as the code to set the PAUSED bit. Other value are ignored and has no effect.
*/
#define DSPCxWDTCS_PCODE GENMASK(7, 0)
#define DSPCxWDTCS_PCODE_VALUE 0x76
/*
* Paused
* type: RW/1C, rst: 0b, rst domain: DSPLRST
*
* When set, it pauses the watch dog timer. Set when 76h is written to the PCODE
* field. Clear when FW writes a 1 to the bit.
*/
#define DSPCxWDTCS_PAUSED BIT(8)
/*
* Second Time Out Reset Enable
* type: RW/1S, rst: 0b, rst domain: DSPLRST
*
* When set, it allow the DSP Core reset to take place upon second time out of the
* watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
*/
#define DSPCxWDTCS_STORE BIT(9)
/*
* DSPCxWDTIPPTR
* DSP Core Watch Dog Timer IP Pointer
*
* Offset: 08h
* Block: DSPBRx
*
* This register provides the pointer to the DSP Core watch dog timer IP registers.
*/
#define DSPCxWDTIPPTR 0x0008
/*
* IP Pointer
* type: RO, rst: 07 8300h + 100h * x, rst domain: nan
*
* This field contains the offset to the IP.
*/
#define DSPCxWDTIPPTR_PTR GENMASK(20, 0)
/*
* IP Version
* type: RO, rst: 000b, rst domain: nan
*
* This field indicates the version of the IP.
*/
#define DSPCxWDTIPPTR_VER GENMASK(23, 21)
/**
* @brief Set pause signal
*
* Sets the pause signal to stop the watchdog timing
*
* @param base Device base address.
* @param core Core ID
*/
static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core)
{
const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);
uint32_t control;
control = sys_read32(reg_addr);
control &= DSPCxWDTCS_STORE;
control |= FIELD_PREP(DSPCxWDTCS_PCODE, DSPCxWDTCS_PCODE_VALUE);
sys_write32(control, reg_addr);
}
/**
* @brief Clear pause signal
*
* Clears the pause signal to resume the watchdog timing
*
* @param base Device base address.
* @param core Core ID
*/
static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core)
{
const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core);
uint32_t control;
control = sys_read32(reg_addr);
control &= DSPCxWDTCS_STORE;
control |= DSPCxWDTCS_PAUSED;
sys_write32(control, reg_addr);
}
/**
* @brief Second Time Out Reset Enable
*
* When set, it allow the DSP Core reset to take place upon second time out of the watchdog timer.
*
* @param base Device base address.
* @param core Core ID
*/
static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable)
{
sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core));
}
/*
* Second Time Out Reset Enable
* type: RW/1S, rst: 0b, rst domain: DSPLRST
*
* When set, it allow the DSP Core reset to take place upon second time out of the
* watch dog timer. Clear when DSPCCTL.CPA = 0. Set when FW writes a 1 to the bit.
*/
#define DSPCxWDTCS_STORE BIT(9)
/**
* @brief Get watchdog IP pointer for specified core.
*
* Returns the base address of the watchdog IP
*
* @param base Device base address.
* @param core Core ID
*/
static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core)
{
return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));
}
/**
* @brief Get watchdog version
*
* Returns the version of the watchdog IP
*
* @param base Device base address.
* @param core Core ID
*/
static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core)
{
return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core)));
}
#endif /* ZEPHYR_DRIVERS_WATCHDOG_WDT_INTEL_ADSP_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_intel_adsp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,219 |
```c
/*
*
*/
#define DT_DRV_COMPAT raspberrypi_pico_watchdog
#include <hardware/watchdog.h>
#include <hardware/structs/psm.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/sys_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_rpi_pico, CONFIG_WDT_LOG_LEVEL);
/* Maximum watchdog time is halved due to errata RP2040-E1 */
#define RPI_PICO_MAX_WDT_TIME (0xffffff / 2)
#define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 2
/* Watchdog requires a 1MHz clock source, divided from the crystal oscillator */
#define RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR 1000000
struct wdt_rpi_pico_data {
uint8_t reset_type;
uint32_t load;
bool enabled;
};
struct wdt_rpi_pico_config {
const struct device *clk_dev;
clock_control_subsys_t clk_id;
};
static int wdt_rpi_pico_setup(const struct device *dev, uint8_t options)
{
const struct wdt_rpi_pico_config *config = dev->config;
struct wdt_rpi_pico_data *data = dev->data;
uint32_t ref_clk;
int err;
if ((options & WDT_OPT_PAUSE_IN_SLEEP) == 1) {
return -ENOTSUP;
}
hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
psm_hw->wdsel = 0;
/* TODO: Handle individual core reset when SMP support for RP2040 is added */
if (data->reset_type == WDT_FLAG_RESET_SOC) {
hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS);
} else if (data->reset_type == WDT_FLAG_RESET_CPU_CORE) {
hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_PROC0_BITS);
}
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0) {
hw_clear_bits(&watchdog_hw->ctrl,
(WATCHDOG_CTRL_PAUSE_JTAG_BITS | WATCHDOG_CTRL_PAUSE_DBG0_BITS |
WATCHDOG_CTRL_PAUSE_DBG1_BITS));
} else {
hw_set_bits(&watchdog_hw->ctrl,
(WATCHDOG_CTRL_PAUSE_JTAG_BITS | WATCHDOG_CTRL_PAUSE_DBG0_BITS |
WATCHDOG_CTRL_PAUSE_DBG1_BITS));
}
watchdog_hw->load = data->load;
/* Zero out the scratch registers so that the module reboots at the
* default program counter
*/
watchdog_hw->scratch[4] = 0;
watchdog_hw->scratch[5] = 0;
watchdog_hw->scratch[6] = 0;
watchdog_hw->scratch[7] = 0;
hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
data->enabled = true;
err = clock_control_on(config->clk_dev, config->clk_id);
if (err < 0) {
return err;
}
err = clock_control_get_rate(config->clk_dev, config->clk_id, &ref_clk);
if (err < 0) {
return err;
}
watchdog_hw->tick = (ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR) |
WATCHDOG_TICK_ENABLE_BITS;
return 0;
}
static int wdt_rpi_pico_disable(const struct device *dev)
{
struct wdt_rpi_pico_data *data = dev->data;
if (data->enabled == false) {
return -EFAULT;
}
hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
data->enabled = false;
return 0;
}
static int wdt_rpi_pico_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
struct wdt_rpi_pico_data *data = dev->data;
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
} else if (cfg->window.max * USEC_PER_MSEC > RPI_PICO_MAX_WDT_TIME) {
return -EINVAL;
} else if (cfg->callback != NULL) {
return -ENOTSUP;
} else if ((cfg->flags & WDT_FLAG_RESET_MASK) == WDT_FLAG_RESET_NONE) {
/* The RP2040 does technically support this mode, but requires
* a program counter and stack pointer value to be set,
* therefore do not allow configuring in this mode
*/
return -EINVAL;
}
data->load = (cfg->window.max * USEC_PER_MSEC * RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR);
data->reset_type = (cfg->flags & WDT_FLAG_RESET_MASK);
return 0;
}
static int wdt_rpi_pico_feed(const struct device *dev, int channel_id)
{
struct wdt_rpi_pico_data *data = dev->data;
if (channel_id != 0) {
/* There is only one input to the watchdog */
return -EINVAL;
}
if (data->enabled == false) {
/* Watchdog is not running so does not need to be fed */
return -EINVAL;
}
watchdog_hw->load = data->load;
return 0;
}
static int wdt_rpi_pico_init(const struct device *dev)
{
#ifndef CONFIG_WDT_DISABLE_AT_BOOT
return wdt_rpi_pico_setup(dev, WDT_OPT_PAUSE_HALTED_BY_DBG);
#endif
return 0;
}
static const struct wdt_driver_api wdt_rpi_pico_driver_api = {
.setup = wdt_rpi_pico_setup,
.disable = wdt_rpi_pico_disable,
.install_timeout = wdt_rpi_pico_install_timeout,
.feed = wdt_rpi_pico_feed,
};
#define WDT_RPI_PICO_WDT_DEVICE(idx) \
static const struct wdt_rpi_pico_config wdt_##idx##_config = { \
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.clk_id = (clock_control_subsys_t)DT_INST_PHA_BY_IDX(idx, clocks, 0, clk_id), \
}; \
static struct wdt_rpi_pico_data wdt_##idx##_data = { \
.reset_type = WDT_FLAG_RESET_SOC, \
.load = (CONFIG_WDT_RPI_PICO_INITIAL_TIMEOUT * \
RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR), \
.enabled = false \
}; \
DEVICE_DT_DEFINE(DT_NODELABEL(wdt##idx), wdt_rpi_pico_init, NULL, &wdt_##idx##_data, \
&wdt_##idx##_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_rpi_pico_driver_api)
DT_INST_FOREACH_STATUS_OKAY(WDT_RPI_PICO_WDT_DEVICE);
``` | /content/code_sandbox/drivers/watchdog/wdt_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,530 |
```unknown
config WDT_NPM6001
bool "nPM6001 Watchdog driver"
default y
depends on DT_HAS_NORDIC_NPM6001_WDT_ENABLED
select I2C
select MFD
help
Enable nPM6001 Watchdog driver
config WDT_NPM6001_INIT_PRIORITY
int "nPM6001 Watchdog driver initialization priority"
depends on WDT_NPM6001
default 85
help
Initialization priority for the nPM6001 Watchdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.npm6001 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```c
/*
*/
#define DT_DRV_COMPAT ite_it8xxx2_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <errno.h>
#include <soc.h>
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
LOG_MODULE_REGISTER(wdt_ite_it8xxx2);
#define IT8XXX2_WATCHDOG_MAGIC_BYTE 0x5c
#define WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(ms) ((ms) * 1024 / 1000)
/* enter critical period or not */
static int wdt_warning_fired;
/* device config */
struct wdt_it8xxx2_config {
/* wdt register base address */
struct wdt_it8xxx2_regs *base;
};
/* driver data */
struct wdt_it8xxx2_data {
/* timeout callback used to handle watchdog event */
wdt_callback_t callback;
/* indicate whether a watchdog timeout is installed */
bool timeout_installed;
/* watchdog feed timeout in milliseconds */
uint32_t timeout;
};
static int wdt_it8xxx2_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_data *data = dev->data;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
/* if watchdog is already running */
if ((inst->ETWCFG) & IT8XXX2_WDT_LEWDCNTL) {
return -EBUSY;
}
/*
* Not support lower limit window timeouts (min value must be equal to
* 0). Upper limit window timeouts can't be 0 when we install timeout.
*/
if ((config->window.min != 0) || (config->window.max == 0)) {
data->timeout_installed = false;
return -EINVAL;
}
/* save watchdog timeout */
data->timeout = config->window.max;
/* install user timeout isr */
data->callback = config->callback;
/* mark installed */
data->timeout_installed = true;
return 0;
}
static int wdt_it8xxx2_setup(const struct device *dev, uint8_t options)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_data *data = dev->data;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
uint16_t cnt1 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT((data->timeout
+ CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS));
/* disable pre-warning timer1 interrupt */
irq_disable(DT_INST_IRQN(0));
if (!data->timeout_installed) {
LOG_ERR("No valid WDT timeout installed");
return -EINVAL;
}
if ((inst->ETWCFG) & IT8XXX2_WDT_LEWDCNTL) {
LOG_ERR("WDT is already running");
return -EBUSY;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
return -ENOTSUP;
}
/* pre-warning timer1 is 16-bit counter down timer */
inst->ET1CNTLHR = (cnt0 >> 8) & 0xff;
inst->ET1CNTLLR = cnt0 & 0xff;
/* clear pre-warning timer1 interrupt status */
ite_intc_isr_clear(DT_INST_IRQN(0));
/* enable pre-warning timer1 interrupt */
irq_enable(DT_INST_IRQN(0));
/* don't stop watchdog timer counting */
inst->ETWCTRL &= ~IT8XXX2_WDT_EWDSCEN;
/* set watchdog timer count */
inst->EWDCNTHR = (cnt1 >> 8) & 0xff;
inst->EWDCNTLR = cnt1 & 0xff;
/* allow to write timer1 count register */
inst->ETWCFG &= ~IT8XXX2_WDT_LET1CNTL;
/*
* bit5 = 1: enable key match function to touch watchdog
* bit4 = 1: select watchdog clock source from prescaler
* bit3 = 1: lock watchdog count register (also mark as watchdog running)
* bit1 = 1: lock timer1 prescaler register
*/
inst->ETWCFG = (IT8XXX2_WDT_EWDKEYEN |
IT8XXX2_WDT_EWDSRC |
IT8XXX2_WDT_LEWDCNTL |
IT8XXX2_WDT_LET1PS);
LOG_DBG("WDT Setup and enabled");
return 0;
}
/*
* reload the WDT and pre-warning timer1 counter
*
* @param dev Pointer to the device structure for the driver instance.
* @param channel_id Index of the fed channel, and we only support
* channel_id = 0 now.
*/
static int wdt_it8xxx2_feed(const struct device *dev, int channel_id)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_data *data = dev->data;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
ARG_UNUSED(channel_id);
/* reset pre-warning timer1 */
inst->ETWCTRL |= IT8XXX2_WDT_ET1RST;
/* restart watchdog timer */
inst->EWDKEYR = IT8XXX2_WATCHDOG_MAGIC_BYTE;
/* reset pre-warning timer1 to default if time is touched */
if (wdt_warning_fired) {
wdt_warning_fired = 0;
/* pre-warning timer1 is 16-bit counter down timer */
inst->ET1CNTLHR = (cnt0 >> 8) & 0xff;
inst->ET1CNTLLR = cnt0 & 0xff;
/* clear timer1 interrupt status */
ite_intc_isr_clear(DT_INST_IRQN(0));
/* enable timer1 interrupt */
irq_enable(DT_INST_IRQN(0));
}
LOG_DBG("WDT Kicking");
return 0;
}
static int wdt_it8xxx2_disable(const struct device *dev)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_data *data = dev->data;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
/* stop watchdog timer counting */
inst->ETWCTRL |= IT8XXX2_WDT_EWDSCEN;
/* unlock watchdog count register (also mark as watchdog not running) */
inst->ETWCFG &= ~IT8XXX2_WDT_LEWDCNTL;
/* disable pre-warning timer1 interrupt */
irq_disable(DT_INST_IRQN(0));
/* mark uninstalled */
data->timeout_installed = false;
LOG_DBG("WDT Disabled");
return 0;
}
static void wdt_it8xxx2_isr(const struct device *dev)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_data *data = dev->data;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
/* clear pre-warning timer1 interrupt status */
ite_intc_isr_clear(DT_INST_IRQN(0));
/* reset pre-warning timer1 */
inst->ETWCTRL |= IT8XXX2_WDT_ET1RST;
/* callback function, ex. print warning message */
if (data->callback) {
data->callback(dev, 0);
}
if (IS_ENABLED(CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME)) {
/*
* Once warning timer triggered: if watchdog timer isn't reloaded,
* then we will reduce interval of warning timer to 30ms to print
* more warning messages before watchdog reset.
*/
if (!wdt_warning_fired) {
uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(30);
/* pre-warning timer1 is 16-bit counter down timer */
inst->ET1CNTLHR = (cnt0 >> 8) & 0xff;
inst->ET1CNTLLR = cnt0 & 0xff;
/* clear pre-warning timer1 interrupt status */
ite_intc_isr_clear(DT_INST_IRQN(0));
}
}
wdt_warning_fired++;
LOG_DBG("WDT ISR");
}
static const struct wdt_driver_api wdt_it8xxx2_api = {
.setup = wdt_it8xxx2_setup,
.disable = wdt_it8xxx2_disable,
.install_timeout = wdt_it8xxx2_install_timeout,
.feed = wdt_it8xxx2_feed,
};
static int wdt_it8xxx2_init(const struct device *dev)
{
const struct wdt_it8xxx2_config *const wdt_config = dev->config;
struct wdt_it8xxx2_regs *const inst = wdt_config->base;
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
wdt_it8xxx2_disable(dev);
}
/* unlock access to watchdog registers */
inst->ETWCFG = 0x00;
/* set WDT and timer1 to use 1.024kHz clock */
inst->ET1PSR = IT8XXX2_WDT_ETPS_1P024_KHZ;
/* set WDT key match enabled and WDT clock to use ET1PSR */
inst->ETWCFG = (IT8XXX2_WDT_EWDKEYEN |
IT8XXX2_WDT_EWDSRC);
/*
* select the mode that watchdog can be stopped, this is needed for
* wdt_it8xxx2_disable() api and WDT_OPT_PAUSE_HALTED_BY_DBG flag
*/
inst->ETWCTRL |= IT8XXX2_WDT_EWDSCMS;
IRQ_CONNECT(DT_INST_IRQN(0), 0, wdt_it8xxx2_isr,
DEVICE_DT_INST_GET(0), 0);
return 0;
}
static const struct wdt_it8xxx2_config wdt_it8xxx2_cfg_0 = {
.base = (struct wdt_it8xxx2_regs *)DT_INST_REG_ADDR(0),
};
static struct wdt_it8xxx2_data wdt_it8xxx2_dev_data;
DEVICE_DT_INST_DEFINE(0, wdt_it8xxx2_init, NULL,
&wdt_it8xxx2_dev_data, &wdt_it8xxx2_cfg_0,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&wdt_it8xxx2_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_ite_it8xxx2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,371 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
#define DT_DRV_COMPAT infineon_cat1_watchdog
#include "cyhal_wdt.h"
#include <zephyr/devicetree.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_infineon_cat1, CONFIG_WDT_LOG_LEVEL);
#define IFX_CAT1_WDT_IS_IRQ_EN DT_NODE_HAS_PROP(DT_DRV_INST(0), interrupts)
struct ifx_cat1_wdt_data {
cyhal_wdt_t obj;
#ifdef IFX_CAT1_WDT_IS_IRQ_EN
wdt_callback_t callback;
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
uint32_t timeout;
bool timeout_installed;
};
struct ifx_cat1_wdt_data wdt_data;
#ifdef IFX_CAT1_WDT_IS_IRQ_EN
static void ifx_cat1_wdt_isr_handler(const struct device *dev)
{
struct ifx_cat1_wdt_data *dev_data = dev->data;
if (dev_data->callback) {
dev_data->callback(dev, 0);
}
Cy_WDT_MaskInterrupt();
}
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
static int ifx_cat1_wdt_setup(const struct device *dev, uint8_t options)
{
cy_rslt_t result;
struct ifx_cat1_wdt_data *dev_data = dev->data;
/* Initialize the WDT */
result = cyhal_wdt_init(&dev_data->obj, dev_data->timeout);
if (result != CY_RSLT_SUCCESS) {
LOG_ERR("Initialization failure : 0x%x", result);
return -ENOMSG;
}
#ifdef IFX_CAT1_WDT_IS_IRQ_EN
if (dev_data->callback) {
Cy_WDT_UnmaskInterrupt();
irq_enable(DT_INST_IRQN(0));
}
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
return 0;
}
static int ifx_cat1_wdt_disable(const struct device *dev)
{
struct ifx_cat1_wdt_data *dev_data = dev->data;
#ifdef IFX_CAT1_WDT_IS_IRQ_EN
Cy_WDT_MaskInterrupt();
irq_disable(DT_INST_IRQN(0));
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
cyhal_wdt_free(&dev_data->obj);
return 0;
}
static int ifx_cat1_wdt_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
struct ifx_cat1_wdt_data *dev_data = dev->data;
if (dev_data->timeout_installed) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if (cfg->flags) {
LOG_WRN("Watchdog behavior is not configurable.");
}
if (cfg->callback) {
#ifndef IFX_CAT1_WDT_IS_IRQ_EN
LOG_WRN("Interrupt is not configured, can't set a callback.");
#else
dev_data->callback = cfg->callback;
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
}
/* window watchdog not supported */
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
dev_data->timeout = cfg->window.max;
return 0;
}
static int ifx_cat1_wdt_feed(const struct device *dev, int channel_id)
{
struct ifx_cat1_wdt_data *data = dev->data;
/* Only channel 0 is supported */
if (channel_id) {
return -EINVAL;
}
cyhal_wdt_kick(&data->obj);
return 0;
}
static int ifx_cat1_wdt_init(const struct device *dev)
{
#ifdef IFX_CAT1_WDT_IS_IRQ_EN
/* Connect WDT interrupt to ISR */
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), ifx_cat1_wdt_isr_handler,
DEVICE_DT_INST_GET(0), 0);
#endif /* IFX_CAT1_WDT_IS_IRQ_EN */
return 0;
}
static const struct wdt_driver_api ifx_cat1_wdt_api = {
.setup = ifx_cat1_wdt_setup,
.disable = ifx_cat1_wdt_disable,
.install_timeout = ifx_cat1_wdt_install_timeout,
.feed = ifx_cat1_wdt_feed,
};
DEVICE_DT_INST_DEFINE(0, ifx_cat1_wdt_init, NULL, &wdt_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &ifx_cat1_wdt_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 989 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_wdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_wdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_mcux_wdog);
#define MIN_TIMEOUT 4
struct mcux_wdog_config {
WDOG_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_wdog_data {
wdt_callback_t callback;
wdog_config_t wdog_config;
bool timeout_valid;
};
static int mcux_wdog_setup(const struct device *dev, uint8_t options)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
data->wdog_config.workMode.enableStop =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.workMode.enableDebug =
(options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U;
WDOG_Init(base, &data->wdog_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_wdog_disable(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
WDOG_Deinit(base);
data->timeout_valid = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
static int mcux_wdog_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
uint32_t clock_freq;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
WDOG_GetDefaultConfig(&data->wdog_config);
data->wdog_config.timeoutValue = clock_freq * cfg->window.max / 1000U;
if (cfg->window.min) {
data->wdog_config.enableWindowMode = true;
data->wdog_config.windowValue =
clock_freq * cfg->window.min / 1000U;
} else {
data->wdog_config.enableWindowMode = false;
data->wdog_config.windowValue = 0;
}
if ((data->wdog_config.timeoutValue < MIN_TIMEOUT) ||
(data->wdog_config.timeoutValue < data->wdog_config.windowValue)) {
LOG_ERR("Invalid timeout");
return -EINVAL;
}
data->wdog_config.clockSource = kWDOG_LpoClockSource;
data->wdog_config.enableInterrupt = cfg->callback != NULL;
data->callback = cfg->callback;
data->timeout_valid = true;
return 0;
}
static int mcux_wdog_feed(const struct device *dev, int channel_id)
{
const struct mcux_wdog_config *config = dev->config;
WDOG_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WDOG_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_wdog_isr(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
uint32_t flags;
flags = WDOG_GetStatusFlags(base);
WDOG_ClearStatusFlags(base, flags);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_wdog_init(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
config->irq_config_func(dev);
return 0;
}
static const struct wdt_driver_api mcux_wdog_api = {
.setup = mcux_wdog_setup,
.disable = mcux_wdog_disable,
.install_timeout = mcux_wdog_install_timeout,
.feed = mcux_wdog_feed,
};
static void mcux_wdog_config_func_0(const struct device *dev);
static const struct mcux_wdog_config mcux_wdog_config_0 = {
.base = (WDOG_Type *) DT_INST_REG_ADDR(0),
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)
DT_INST_CLOCKS_CELL(0, name),
.irq_config_func = mcux_wdog_config_func_0,
};
static struct mcux_wdog_data mcux_wdog_data_0;
DEVICE_DT_INST_DEFINE(0,
&mcux_wdog_init,
NULL,
&mcux_wdog_data_0, &mcux_wdog_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_wdog_api);
static void mcux_wdog_config_func_0(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
mcux_wdog_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
``` | /content/code_sandbox/drivers/watchdog/wdt_mcux_wdog.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,248 |
```c
/*
* Driver for Xilinx AXI Timebase WDT core, as described in
* Xilinx document PG128.
*
* Note that the window mode of operation of the core is
* currently not supported. Also, only a full SoC reset is
* supported as a watchdog expiry action.
*
*/
#define DT_DRV_COMPAT xlnx_xps_timebase_wdt_1_00_a
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/hwinfo.h>
enum xilinx_wdt_axi_register {
REG_TWCSR0 = 0x00, /* Control/Status Register 0 */
REG_TWCSR1 = 0x04, /* Control/Status Register 1 */
REG_TBR = 0x08, /* Timebase Register */
REG_MWR = 0x0C, /* Master Write Control Register */
};
enum xilinx_wdt_csr0_bits {
CSR0_WRS = BIT(3),
CSR0_WDS = BIT(2),
CSR0_EWDT1 = BIT(1),
CSR0_EWDT2 = BIT(0),
};
enum xilinx_wdt_csr1_bits {
CSR1_EWDT2 = BIT(0),
};
enum {
TIMER_WIDTH_MIN = 8,
};
LOG_MODULE_REGISTER(wdt_xilinx_axi, CONFIG_WDT_LOG_LEVEL);
struct xilinx_wdt_axi_config {
mem_addr_t base;
uint32_t clock_rate;
uint8_t timer_width_max;
bool enable_once;
};
struct xilinx_wdt_axi_data {
struct k_spinlock lock;
bool timeout_active;
bool wdt_started;
};
static const struct device *first_wdt_dev;
static int wdt_xilinx_axi_setup(const struct device *dev, uint8_t options)
{
const struct xilinx_wdt_axi_config *config = dev->config;
struct xilinx_wdt_axi_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
int ret;
if (!data->timeout_active) {
ret = -EINVAL;
goto out;
}
if (data->wdt_started) {
ret = -EBUSY;
goto out;
}
/* We don't actually know or control at the driver level whether
* the WDT pauses in CPU sleep or when halted by the debugger,
* so we don't check anything with the options.
*/
sys_write32(CSR0_EWDT1 | CSR0_WDS, config->base + REG_TWCSR0);
sys_write32(CSR1_EWDT2, config->base + REG_TWCSR1);
data->wdt_started = true;
ret = 0;
out:
k_spin_unlock(&data->lock, key);
return ret;
}
static int wdt_xilinx_axi_disable(const struct device *dev)
{
const struct xilinx_wdt_axi_config *config = dev->config;
struct xilinx_wdt_axi_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
int ret;
if (config->enable_once) {
ret = -EPERM;
goto out;
}
if (!data->wdt_started) {
ret = -EFAULT;
goto out;
}
sys_write32(CSR0_WDS, config->base + REG_TWCSR0);
sys_write32(0, config->base + REG_TWCSR1);
data->wdt_started = false;
ret = 0;
out:
k_spin_unlock(&data->lock, key);
return ret;
}
static int wdt_xilinx_axi_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct xilinx_wdt_axi_config *config = dev->config;
struct xilinx_wdt_axi_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
uint32_t timer_width;
bool good_timer_width = false;
int ret;
if (data->timeout_active) {
ret = -ENOMEM;
goto out;
}
if (!(cfg->flags & WDT_FLAG_RESET_SOC)) {
ret = -ENOTSUP;
goto out;
}
if (cfg->window.min != 0) {
ret = -EINVAL;
goto out;
}
for (timer_width = TIMER_WIDTH_MIN; timer_width <= config->timer_width_max; timer_width++) {
/* Note: WDT expiry happens after 2 wraps of the timer (first raises an interrupt
* which is not used, second triggers a reset) so add 1 to timer_width.
*/
const uint64_t expiry_cycles = ((uint64_t)1) << (timer_width + 1);
const uint64_t expiry_msec = expiry_cycles * 1000 / config->clock_rate;
if (expiry_msec >= cfg->window.max) {
LOG_INF("Set timer width to %u, actual expiry %u msec", timer_width,
(unsigned int)expiry_msec);
good_timer_width = true;
break;
}
}
if (!good_timer_width) {
LOG_ERR("Cannot support timeout value of %u msec", cfg->window.max);
ret = -EINVAL;
goto out;
}
sys_write32(timer_width, config->base + REG_MWR);
data->timeout_active = true;
ret = 0;
out:
k_spin_unlock(&data->lock, key);
return ret;
}
static int wdt_xilinx_axi_feed(const struct device *dev, int channel_id)
{
const struct xilinx_wdt_axi_config *config = dev->config;
struct xilinx_wdt_axi_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0);
int ret;
if (channel_id != 0 || !data->timeout_active) {
ret = -EINVAL;
goto out;
}
twcsr0 |= CSR0_WDS;
if (data->wdt_started) {
twcsr0 |= CSR0_EWDT1;
}
sys_write32(twcsr0, config->base + REG_TWCSR0);
ret = 0;
out:
k_spin_unlock(&data->lock, key);
return ret;
}
static int wdt_xilinx_axi_init(const struct device *dev)
{
if (IS_ENABLED(CONFIG_WDT_XILINX_AXI_HWINFO_API)) {
if (first_wdt_dev) {
LOG_WRN("Multiple WDT instances, only first will implement HWINFO");
} else {
first_wdt_dev = dev;
}
}
return 0;
}
#ifdef CONFIG_WDT_XILINX_AXI_HWINFO_API
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
if (!first_wdt_dev) {
return -ENOSYS;
}
const struct xilinx_wdt_axi_config *config = first_wdt_dev->config;
if ((sys_read32(config->base + REG_TWCSR0) & CSR0_WRS) != 0) {
*cause = RESET_WATCHDOG;
} else {
*cause = 0;
}
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
if (!first_wdt_dev) {
return -ENOSYS;
}
const struct xilinx_wdt_axi_config *config = first_wdt_dev->config;
struct xilinx_wdt_axi_data *data = first_wdt_dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0);
if ((twcsr0 & CSR0_WRS) != 0) {
twcsr0 |= CSR0_WRS;
sys_write32(twcsr0, config->base + REG_TWCSR0);
}
k_spin_unlock(&data->lock, key);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
if (!first_wdt_dev) {
return -ENOSYS;
}
*supported = RESET_WATCHDOG;
return 0;
}
#endif
static const struct wdt_driver_api wdt_xilinx_api = {
.setup = wdt_xilinx_axi_setup,
.disable = wdt_xilinx_axi_disable,
.install_timeout = wdt_xilinx_axi_install_timeout,
.feed = wdt_xilinx_axi_feed,
};
#define WDT_XILINX_AXI_INIT(inst) \
static struct xilinx_wdt_axi_data wdt_xilinx_axi_##inst##_dev_data; \
\
static const struct xilinx_wdt_axi_config wdt_xilinx_axi_##inst##_cfg = { \
.base = DT_INST_REG_ADDR(inst), \
.clock_rate = DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency), \
.timer_width_max = DT_INST_PROP(inst, xlnx_wdt_interval), \
.enable_once = DT_INST_PROP(inst, xlnx_wdt_enable_once), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &wdt_xilinx_axi_init, NULL, &wdt_xilinx_axi_##inst##_dev_data, \
&wdt_xilinx_axi_##inst##_cfg, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_xilinx_api);
DT_INST_FOREACH_STATUS_OKAY(WDT_XILINX_AXI_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_xilinx_axi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,079 |
```unknown
# Watchdog configuration options
#
#
config WDT_GECKO
bool "Gecko series Watchdog (WDOG) Driver"
default y
depends on DT_HAS_SILABS_GECKO_WDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
select SOC_GECKO_WDOG
help
Enable WDOG driver for Silicon Labs Gecko MCUs.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.gecko | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
config WDT_CC13XX_CC26XX
bool "Watchdog Driver for CC13xx / CC26xx family of MCUs"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable watchdog for CC13xx / CC26xx family of MCUs
config WDT_CC13XX_CC26XX_INITIAL_TIMEOUT
int "Value for initial WDT timeout in ms"
depends on WDT_CC13XX_CC26XX
default 2000
range 1 2863311
help
The CC13xx/CC26xx watchdog timer is sourced from the MCU clock
using a fixed prescaler of 32.
E.g., for the standard 48 MHz MCU clock, the following:
0xFFFFFFFF / (48^9 / 32 / 1000) [ms]
``` | /content/code_sandbox/drivers/watchdog/Kconfig.cc13xx_cc26xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 189 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_xt_wdt
#include <soc/rtc_cntl_reg.h>
#include <hal/xt_wdt_hal.h>
#include <rom/ets_sys.h>
#include <string.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/esp32_clock_control.h>
#ifndef CONFIG_SOC_SERIES_ESP32C3
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#endif
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(xt_wdt_esp32, CONFIG_WDT_LOG_LEVEL);
#ifdef CONFIG_SOC_SERIES_ESP32C3
#define ISR_HANDLER isr_handler_t
#else
#define ISR_HANDLER intr_handler_t
#endif
#define ESP32_XT_WDT_MAX_TIMEOUT 255
struct esp32_xt_wdt_data {
xt_wdt_hal_context_t hal;
wdt_callback_t callback;
uint32_t timeout;
};
struct esp32_xt_wdt_config {
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
int irq_source;
};
static int esp32_xt_wdt_setup(const struct device *dev, uint8_t options)
{
ARG_UNUSED(options);
struct esp32_xt_wdt_data *data = dev->data;
xt_wdt_hal_config_t xt_wdt_hal_config = {
.timeout = data->timeout,
};
xt_wdt_hal_init(&data->hal, &xt_wdt_hal_config);
xt_wdt_hal_enable(&data->hal, true);
return 0;
}
static int esp32_xt_wdt_disable(const struct device *dev)
{
struct esp32_xt_wdt_data *data = dev->data;
xt_wdt_hal_enable(&data->hal, false);
return 0;
}
static int esp32_xt_wdt_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(dev);
ARG_UNUSED(channel_id);
return -ENOSYS;
}
static int esp32_xt_wdt_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct esp32_xt_wdt_data *data = dev->data;
if (cfg->window.min != 0U || cfg->window.max == 0U ||
cfg->window.max >= ESP32_XT_WDT_MAX_TIMEOUT) {
LOG_ERR("Invalid timeout configuration");
return -EINVAL;
}
data->timeout = cfg->window.max;
data->callback = cfg->callback;
return 0;
}
static void esp32_xt_wdt_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
const struct esp32_xt_wdt_config *cfg = dev->config;
struct esp32_xt_wdt_data *data = dev->data;
struct esp32_clock_config clk_cfg = {0};
uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG);
REG_WRITE(RTC_CNTL_INT_CLR_REG, status);
clk_cfg.rtc.rtc_slow_clock_src = ESP32_RTC_SLOW_CLK_SRC_RC_SLOW;
clock_control_configure(cfg->clock_dev,
(clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW,
&clk_cfg);
if (data->callback != NULL) {
data->callback(dev, 0);
}
}
static int esp32_xt_wdt_init(const struct device *dev)
{
const struct esp32_xt_wdt_config *cfg = dev->config;
struct esp32_xt_wdt_data *data = dev->data;
xt_wdt_hal_config_t xt_wdt_hal_config = {
.timeout = ESP32_XT_WDT_MAX_TIMEOUT,
};
xt_wdt_hal_init(&data->hal, &xt_wdt_hal_config);
xt_wdt_hal_enable_backup_clk(&data->hal,
ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ/1000);
int err = esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)esp32_xt_wdt_isr, (void *)dev,
NULL);
if (err) {
LOG_ERR("Failed to register ISR\n");
return -EFAULT;
}
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
return 0;
}
static const struct wdt_driver_api esp32_xt_wdt_api = {
.setup = esp32_xt_wdt_setup,
.disable = esp32_xt_wdt_disable,
.install_timeout = esp32_xt_wdt_install_timeout,
.feed = esp32_xt_wdt_feed
};
static struct esp32_xt_wdt_data esp32_xt_wdt_data0;
static struct esp32_xt_wdt_config esp32_xt_wdt_config0 = {
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
.irq_source = DT_INST_IRQN(0),
};
DEVICE_DT_DEFINE(DT_NODELABEL(xt_wdt),
&esp32_xt_wdt_init,
NULL,
&esp32_xt_wdt_data0,
&esp32_xt_wdt_config0,
POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&esp32_xt_wdt_api);
#if !(defined(CONFIG_SOC_SERIES_ESP32S2) || \
defined(CONFIG_SOC_SERIES_ESP32S3) || \
defined(CONFIG_SOC_SERIES_ESP32C3))
#error "XT WDT is not supported"
#else
BUILD_ASSERT((DT_PROP(DT_INST(0, espressif_esp32_rtc), slow_clk_src) ==
ESP32_RTC_SLOW_CLK_SRC_XTAL32K) ||
(DT_PROP(DT_INST(0, espressif_esp32_rtc), slow_clk_src) ==
ESP32_RTC_SLOW_CLK_32K_EXT_OSC),
"XT WDT is only supported with XTAL32K or 32K_EXT_OSC as slow clock source");
#endif
``` | /content/code_sandbox/drivers/watchdog/xt_wdt_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,307 |
```c
/*
*
* Based on wdt_mcux_wdog32.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_lpc_wwdt
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clock.h>
#include <fsl_wwdt.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_mcux_wwdt);
#define MIN_TIMEOUT 0xFF
struct mcux_wwdt_config {
WWDT_Type *base;
uint8_t clk_divider;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_wwdt_data {
wdt_callback_t callback;
wwdt_config_t wwdt_config;
bool timeout_valid;
};
static int mcux_wwdt_setup(const struct device *dev, uint8_t options)
{
const struct mcux_wwdt_config *config = dev->config;
struct mcux_wwdt_data *data = dev->data;
WWDT_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
WWDT_Init(base, &data->wwdt_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_wwdt_disable(const struct device *dev)
{
const struct mcux_wwdt_config *config = dev->config;
struct mcux_wwdt_data *data = dev->data;
WWDT_Type *base = config->base;
WWDT_Deinit(base);
data->timeout_valid = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
/*
* LPC55xxx WWDT has a fixed divide-by-4 clock prescaler.
* This prescaler is different from the clock divider specified in Device Tree.
*/
#define MSEC_TO_WWDT_TICKS(clock_freq, msec) \
((uint32_t)((clock_freq / MSEC_PER_SEC) * msec) / 4)
static int mcux_wwdt_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct mcux_wwdt_data *data = dev->data;
uint32_t clock_freq;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
#if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) \
|| defined(CONFIG_SOC_SERIES_MCXN)
clock_freq = CLOCK_GetWdtClkFreq(0);
#elif defined(CONFIG_SOC_SERIES_RW6XX)
clock_freq = CLOCK_GetWdtClkFreq();
#else
const struct mcux_wwdt_config *config = dev->config;
CLOCK_SetClkDiv(kCLOCK_DivWdtClk, config->clk_divider, true);
clock_freq = CLOCK_GetWdtClkFreq();
#endif
WWDT_GetDefaultConfig(&data->wwdt_config);
data->wwdt_config.clockFreq_Hz = clock_freq;
data->wwdt_config.timeoutValue =
MSEC_TO_WWDT_TICKS(clock_freq, cfg->window.max);
if (cfg->window.min) {
data->wwdt_config.windowValue =
MSEC_TO_WWDT_TICKS(clock_freq, cfg->window.min);
}
if ((data->wwdt_config.timeoutValue < MIN_TIMEOUT) ||
((data->wwdt_config.windowValue != 0xFFFFFFU) &&
(data->wwdt_config.timeoutValue <
data->wwdt_config.windowValue))) {
return -EINVAL;
}
if (cfg->flags & WDT_FLAG_RESET_SOC) {
data->wwdt_config.enableWatchdogReset = true;
LOG_DBG("Enabling SoC reset");
}
if (cfg->callback && (CONFIG_WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG > 0)) {
data->callback = cfg->callback;
data->wwdt_config.warningValue = CONFIG_WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG;
} else if (cfg->callback) {
return -ENOTSUP;
}
data->timeout_valid = true;
LOG_DBG("Installed timeout (timeoutValue = %d)",
data->wwdt_config.timeoutValue);
return 0;
}
static int mcux_wwdt_feed(const struct device *dev, int channel_id)
{
const struct mcux_wwdt_config *config = dev->config;
WWDT_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WWDT_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_wwdt_isr(const struct device *dev)
{
const struct mcux_wwdt_config *config = dev->config;
struct mcux_wwdt_data *data = dev->data;
WWDT_Type *base = config->base;
uint32_t flags;
flags = WWDT_GetStatusFlags(base);
WWDT_ClearStatusFlags(base, flags);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_wwdt_init(const struct device *dev)
{
const struct mcux_wwdt_config *config = dev->config;
config->irq_config_func(dev);
return 0;
}
static const struct wdt_driver_api mcux_wwdt_api = {
.setup = mcux_wwdt_setup,
.disable = mcux_wwdt_disable,
.install_timeout = mcux_wwdt_install_timeout,
.feed = mcux_wwdt_feed,
};
static void mcux_wwdt_config_func_0(const struct device *dev);
static const struct mcux_wwdt_config mcux_wwdt_config_0 = {
.base = (WWDT_Type *) DT_INST_REG_ADDR(0),
.clk_divider =
DT_INST_PROP(0, clk_divider),
.irq_config_func = mcux_wwdt_config_func_0,
};
static struct mcux_wwdt_data mcux_wwdt_data_0;
DEVICE_DT_INST_DEFINE(0, &mcux_wwdt_init,
NULL, &mcux_wwdt_data_0,
&mcux_wwdt_config_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_wwdt_api);
static void mcux_wwdt_config_func_0(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
mcux_wwdt_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
``` | /content/code_sandbox/drivers/watchdog/wdt_mcux_wwdt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,437 |
```unknown
# STM32 IWDG configuration
config IWDG_STM32
bool "Independent Watchdog (IWDG) Driver for STM32 family of MCUs"
default y
depends on DT_HAS_ST_STM32_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable IWDG driver for STM32 line of MCUs
config IWDG_STM32_INITIAL_TIMEOUT
int "Value for IWDG timeout in ms"
depends on IWDG_STM32
default 100
range 1 26214
help
Set initial timeout value for IWDG in ms if enabled at boot.
The min timeout supported is 1 ms. The max timeout depends on the
MCU's LSI clock frequency and can be calculated with:
max. prescaler value (256) * max. reload ticks (4096) / LSI freq.
Limiting maximum timeout to a safe value of 26214 ms here, which was
calculated for highest LSI frequency among STM32 MCUs of 40 kHz.
config WWDG_STM32
bool "System Window Watchdog (WWDG) Driver for STM32 family of MCUs"
default y
depends on DT_HAS_ST_STM32_WINDOW_WATCHDOG_ENABLED
help
Enable WWDG driver for STM32 line of MCUs
``` | /content/code_sandbox/drivers/watchdog/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 286 |
```c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys_clock.h>
#include <zephyr/math/ilog2.h>
#include "wdt_dw_common.h"
#include "wdt_dw.h"
LOG_MODULE_REGISTER(wdt_dw_common, CONFIG_WDT_LOG_LEVEL);
#define WDT_DW_FLAG_CONFIGURED 0x80000000
int dw_wdt_check_options(const uint8_t options)
{
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
LOG_WRN("Pausing watchdog by debugger is not configurable");
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_WRN("Pausing watchdog in sleep is not configurable");
}
return 0;
}
int dw_wdt_configure(const uint32_t base, const uint32_t config)
{
uint32_t period;
if (!(config & WDT_DW_FLAG_CONFIGURED)) {
LOG_ERR("Timeout not installed.");
return -ENOTSUP;
}
/* Configure timeout */
period = config & ~WDT_DW_FLAG_CONFIGURED;
if (dw_wdt_dual_timeout_period_get(base)) {
dw_wdt_timeout_period_init_set(base, period);
}
dw_wdt_timeout_period_set(base, period);
/* Enable watchdog */
dw_wdt_enable(base);
dw_wdt_counter_restart(base);
return 0;
}
int dw_wdt_calc_period(const uint32_t base, const uint32_t clk_freq,
const struct wdt_timeout_cfg *config, uint32_t *period_out)
{
uint64_t period64;
uint32_t period;
/* Window timeout is not supported by this driver */
if (config->window.min) {
LOG_ERR("Window timeout is not supported.");
return -ENOTSUP;
}
period64 = (uint64_t)clk_freq * config->window.max;
period64 /= 1000;
if (!period64 || (period64 >> 31)) {
LOG_ERR("Window max is out of range.");
return -EINVAL;
}
period = period64 - 1;
period = ilog2(period);
if (period >= dw_wdt_cnt_width_get(base)) {
LOG_ERR("Watchdog timeout too long.");
return -EINVAL;
}
/* The minimum counter value is 64k, maximum 2G */
*period_out = WDT_DW_FLAG_CONFIGURED | (period >= 15 ? period - 15 : 0);
return 0;
}
int dw_wdt_probe(const uint32_t base, const uint32_t reset_pulse_length)
{
/* Check component type */
const uint32_t type = dw_wdt_comp_type_get(base);
if (type != WDT_COMP_TYPE_VALUE) {
LOG_ERR("Invalid component type %x", type);
return -ENODEV;
}
dw_wdt_reset_pulse_length_set(base, reset_pulse_length);
return 0;
}
``` | /content/code_sandbox/drivers/watchdog/wdt_dw_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 641 |
```unknown
config WDT_NXP_S32
bool "NXP S32 SWT driver"
default y
depends on DT_HAS_NXP_S32_SWT_ENABLED
select CLOCK_CONTROL
select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
help
Enable the Software Watchdog Timer (SWT) driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
config WDT_MAX32
bool "MAX32 Watchdog (WDT) Driver"
default y
depends on DT_HAS_ADI_MAX32_WATCHDOG_ENABLED
help
Enable WDT driver for MAX32.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.max32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
config WDT_SHELL
bool "Watchdog (WDT) shell"
depends on SHELL
help
Enable WDT shell.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.shell | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# ESP32 WDT configuration
config WDT_ESP32
bool "ESP32 Watchdog (WDT) Driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for ESP32.
config WDT_XT_ESP32
bool "ESP32 Watchdog for External 32K Crystal Driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_XT_WDT_ENABLED
help
Enable WDT driver for ESP32.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```c
/*
*
*/
#define DT_DRV_COMPAT lowrisc_opentitan_aontimer
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_opentitan, CONFIG_WDT_LOG_LEVEL);
#define OT_REG_WDOG_REGWEN_OFFSET 0x10
#define OT_REG_WDOG_CTRL_OFFSET 0x14
#define OT_REG_WDOG_BARK_THOLD_OFFSET 0x18
#define OT_REG_WDOG_BITE_THOLD_OFFSET 0x1C
#define OT_REG_WDOG_COUNT_OFFSET 0x20
#define OT_REG_INTR_STATE_OFFSET 0x24
struct wdt_ot_aontimer_cfg {
uintptr_t regs;
uint32_t clk_freq;
bool wdog_lock;
};
struct wdt_ot_aontimer_data {
wdt_callback_t bark;
};
static int ot_aontimer_setup(const struct device *dev, uint8_t options)
{
const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
volatile uintptr_t regs = cfg->regs;
sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET);
sys_write32(1, regs + OT_REG_WDOG_CTRL_OFFSET);
if (cfg->wdog_lock) {
/* Force a read to ensure the timer was enabled. */
(void) sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET);
sys_write32(0, regs + OT_REG_WDOG_REGWEN_OFFSET);
}
return 0;
}
static int ot_aontimer_disable(const struct device *dev)
{
const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
volatile uintptr_t regs = cfg->regs;
if (!sys_read32(regs + OT_REG_WDOG_REGWEN_OFFSET)) {
LOG_ERR("Cannot disable - watchdog settings locked.");
return -EPERM;
}
uint32_t ctrl_val = sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET);
if (!(ctrl_val & BIT(0))) {
return -EFAULT;
}
sys_write32(ctrl_val & ~BIT(0), regs + OT_REG_WDOG_CTRL_OFFSET);
return 0;
}
/*
* The OpenTitan AON Timer includes a multi-level watchdog timer.
* While the first stage supports an interrupt callback, the second does not.
* The second stage is mandatory to adjust the "bite" time window.
*
* Some boundaries are enforced to prevent behavior that is technically correct
* but is not likely intended.
* Bark:
* Minimum must be 0. Maximum must be > min.
* The bark interrupt occurs at max (or if the timeout is too long to be
* supported, the value x s.t. min < x < max and x is the largest valid timeout)
* Bite:
* Minimum must be >= bark.min, and maximum >= bark.max. If the timeout is too
* long to fit, it tries to find the value x s.t. min < x < max where x is the
* largest valid timeout.
* The bite action occurs max.
*/
static int ot_aontimer_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_ot_aontimer_data *data = dev->data;
const struct wdt_ot_aontimer_cfg *const dev_cfg = dev->config;
volatile uintptr_t reg_base = dev_cfg->regs;
const uint64_t max_window = (uint64_t) UINT32_MAX * 1000 / dev_cfg->clk_freq;
uint64_t bite_thold;
#ifdef CONFIG_WDT_MULTISTAGE
/* When multistage is selected, add an intermediate bark stage */
uint64_t bark_thold;
struct wdt_timeout_cfg *bite = cfg->next;
if (bite == NULL || bite->window.max < cfg->window.max ||
(uint64_t) bite->window.min > max_window) {
return -EINVAL;
}
/*
* Flag must be clear for stage 1, and reset SOC for stage 2.
* CPU not supported
*/
if (cfg->flags != WDT_FLAG_RESET_NONE || bite->flags != WDT_FLAG_RESET_SOC) {
return -ENOTSUP;
}
#endif
if (cfg->window.min > cfg->window.max || (uint64_t) cfg->window.min > max_window) {
return -EINVAL;
}
if (!sys_read32(reg_base + OT_REG_WDOG_REGWEN_OFFSET)) {
LOG_ERR("Cannot install timeout - watchdog settings locked.");
return -ENOMEM;
}
/* Watchdog is already enabled! */
if (sys_read32(reg_base + OT_REG_WDOG_CTRL_OFFSET) & BIT(0)) {
return -EBUSY;
}
#ifdef CONFIG_WDT_MULTISTAGE
/* Force 64-bit ops to ensure thresholds fits in the timer reg. */
bark_thold = ((uint64_t) cfg->window.max * dev_cfg->clk_freq / 1000);
bite_thold = ((uint64_t) bite->window.max * dev_cfg->clk_freq / 1000);
/* Saturate these config values; min is verified to be < max_window */
if (bark_thold > UINT32_MAX) {
bark_thold = UINT32_MAX;
}
if (bite_thold > UINT32_MAX) {
bite_thold = UINT32_MAX;
}
data->bark = cfg->callback;
sys_write32((uint32_t) bark_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
#else
bite_thold = ((uint64_t) cfg->window.max * dev_cfg->clk_freq / 1000);
/* Saturate this config value; min is verified to be < max_window */
if (bite_thold > UINT32_MAX) {
bite_thold = UINT32_MAX;
}
if (cfg->flags == WDT_FLAG_RESET_NONE) {
/* Set bite -> bark, so we generate an interrupt instead of resetting */
sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
/* Disable bite by writing it to max. Edge case is the bark = max. */
sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
data->bark = cfg->callback;
} else {
data->bark = NULL;
/* Effectively disable bark by setting it to max */
sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET);
sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET);
}
#endif
return 0;
}
static int ot_aontimer_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(channel_id);
const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
volatile uintptr_t regs = cfg->regs;
sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET);
/* Deassert the interrupt line */
sys_write32(BIT(1), regs + OT_REG_INTR_STATE_OFFSET);
return 0;
}
static void wdt_ot_isr(const struct device *dev)
{
const struct wdt_ot_aontimer_cfg *const cfg = dev->config;
struct wdt_ot_aontimer_data *data = dev->data;
volatile uintptr_t regs = cfg->regs;
if (data->bark != NULL) {
data->bark(dev, 0);
}
/* Deassert the interrupt line */
sys_write32(BIT(1), regs + OT_REG_INTR_STATE_OFFSET);
}
static int ot_aontimer_init(const struct device *dev)
{
IRQ_CONNECT(
DT_INST_IRQ_BY_IDX(0, 0, irq),
DT_INST_IRQ_BY_IDX(0, 0, priority), wdt_ot_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQ_BY_IDX(0, 0, irq));
return 0;
}
static struct wdt_ot_aontimer_data ot_aontimer_data;
static struct wdt_ot_aontimer_cfg ot_aontimer_cfg = {
.regs = (volatile uintptr_t) DT_INST_REG_ADDR(0),
.clk_freq = DT_INST_PROP(0, clock_frequency),
.wdog_lock = DT_INST_PROP(0, wdog_lock),
};
static const struct wdt_driver_api ot_aontimer_api = {
.setup = ot_aontimer_setup,
.disable = ot_aontimer_disable,
.install_timeout = ot_aontimer_install_timeout,
.feed = ot_aontimer_feed,
};
DEVICE_DT_INST_DEFINE(0, ot_aontimer_init, NULL,
&ot_aontimer_data, &ot_aontimer_cfg, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&ot_aontimer_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_opentitan.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,924 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_cmsdk_watchdog
/**
* @brief Driver for CMSDK APB Watchdog.
*/
#include <errno.h>
#include <soc.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/sys/printk.h>
#include <zephyr/sys/reboot.h>
struct wdog_cmsdk_apb {
/* offset: 0x000 (r/w) watchdog load register */
volatile uint32_t load;
/* offset: 0x004 (r/ ) watchdog value register */
volatile uint32_t value;
/* offset: 0x008 (r/w) watchdog control register */
volatile uint32_t ctrl;
/* offset: 0x00c ( /w) watchdog clear interrupt register */
volatile uint32_t intclr;
/* offset: 0x010 (r/ ) watchdog raw interrupt status register */
volatile uint32_t rawintstat;
/* offset: 0x014 (r/ ) watchdog interrupt status register */
volatile uint32_t maskintstat;
volatile uint32_t reserved0[762];
/* offset: 0xc00 (r/w) watchdog lock register */
volatile uint32_t lock;
volatile uint32_t reserved1[191];
/* offset: 0xf00 (r/w) watchdog integration test control register */
volatile uint32_t itcr;
/* offset: 0xf04 ( /w) watchdog integration test output set register */
volatile uint32_t itop;
};
#define CMSDK_APB_WDOG_LOAD (0xFFFFFFFF << 0)
#define CMSDK_APB_WDOG_RELOAD (0xE4E1C00 << 0)
#define CMSDK_APB_WDOG_VALUE (0xFFFFFFFF << 0)
#define CMSDK_APB_WDOG_CTRL_RESEN (0x1 << 1)
#define CMSDK_APB_WDOG_CTRL_INTEN (0x1 << 0)
#define CMSDK_APB_WDOG_INTCLR (0x1 << 0)
#define CMSDK_APB_WDOG_RAWINTSTAT (0x1 << 0)
#define CMSDK_APB_WDOG_MASKINTSTAT (0x1 << 0)
#define CMSDK_APB_WDOG_LOCK (0x1 << 0)
#define CMSDK_APB_WDOG_INTEGTESTEN (0x1 << 0)
#define CMSDK_APB_WDOG_INTEGTESTOUTSET (0x1 << 1)
/*
* Value written to the LOCK register to lock or unlock the write access
* to all of the registers of the watchdog (except the LOCK register)
*/
#define CMSDK_APB_WDOG_UNLOCK_VALUE (0x1ACCE551)
#define CMSDK_APB_WDOG_LOCK_VALUE (0x2BDDF662)
#define WDOG_STRUCT \
((volatile struct wdog_cmsdk_apb *)(DT_INST_REG_ADDR(0)))
/* Keep reference of the device to pass it to the callback */
const struct device *wdog_r;
/* watchdog reload value in clock cycles */
static unsigned int reload_cycles = CMSDK_APB_WDOG_RELOAD;
static uint8_t assigned_channels;
static uint8_t flags;
static void (*user_cb)(const struct device *dev, int channel_id);
static void wdog_cmsdk_apb_unlock(const struct device *dev)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
ARG_UNUSED(dev);
wdog->lock = CMSDK_APB_WDOG_UNLOCK_VALUE;
}
static int wdog_cmsdk_apb_setup(const struct device *dev, uint8_t options)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
ARG_UNUSED(dev);
ARG_UNUSED(options);
/* Start the watchdog counter with INTEN bit */
wdog->ctrl = (CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN);
return 0;
}
static int wdog_cmsdk_apb_disable(const struct device *dev)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
ARG_UNUSED(dev);
/* Stop the watchdog counter with INTEN bit */
wdog->ctrl = ~(CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN);
assigned_channels = 0;
return 0;
}
static int wdog_cmsdk_apb_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
uint32_t clk_freq_khz = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency) / 1000;
ARG_UNUSED(dev);
if (config->window.max == 0) {
return -EINVAL;
}
if (assigned_channels == 1) {
return -ENOMEM;
}
/* Reload value */
reload_cycles = config->window.max * clk_freq_khz;
flags = config->flags;
wdog->load = reload_cycles;
/* Configure only the callback */
user_cb = config->callback;
assigned_channels++;
return 0;
}
static int wdog_cmsdk_apb_feed(const struct device *dev, int channel_id)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
ARG_UNUSED(dev);
ARG_UNUSED(channel_id);
/* Clear the interrupt */
wdog->intclr = CMSDK_APB_WDOG_INTCLR;
/* Reload */
wdog->load = reload_cycles;
return 0;
}
static const struct wdt_driver_api wdog_cmsdk_apb_api = {
.setup = wdog_cmsdk_apb_setup,
.disable = wdog_cmsdk_apb_disable,
.install_timeout = wdog_cmsdk_apb_install_timeout,
.feed = wdog_cmsdk_apb_feed,
};
#ifdef CONFIG_RUNTIME_NMI
static int wdog_cmsdk_apb_has_fired(void)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
return (wdog->maskintstat & CMSDK_APB_WDOG_MASKINTSTAT) != 0U;
}
static void wdog_cmsdk_apb_isr(void)
{
/*
* Check if the watchdog was the reason of the NMI interrupt
* and if not, exit immediately
*/
if (!wdog_cmsdk_apb_has_fired()) {
printk("NMI received! Rebooting...\n");
/* In ARM implementation sys_reboot ignores the parameter */
sys_reboot(0);
} else {
if (user_cb != NULL) {
user_cb(wdog_r, 0);
}
}
}
#endif /* CONFIG_RUNTIME_NMI */
static int wdog_cmsdk_apb_init(const struct device *dev)
{
volatile struct wdog_cmsdk_apb *wdog = WDOG_STRUCT;
wdog_r = dev;
/* unlock access to configuration registers */
wdog_cmsdk_apb_unlock(dev);
/* set default reload value */
wdog->load = reload_cycles;
#ifdef CONFIG_RUNTIME_NMI
/* Configure the interrupts */
z_arm_nmi_set_handler(wdog_cmsdk_apb_isr);
#endif
#ifdef CONFIG_WDOG_CMSDK_APB_START_AT_BOOT
wdog_cmsdk_apb_setup(dev, 0);
#endif
return 0;
}
DEVICE_DT_INST_DEFINE(0,
wdog_cmsdk_apb_init,
NULL,
NULL, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&wdog_cmsdk_apb_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_cmsdk_apb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,623 |
```c
/*
*
*/
#include <stdlib.h>
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/watchdog.h>
#define WDT_SETUP_HELP \
"Set up watchdog instance. Syntax:\n" \
"<device>"
#define WDT_DISABLE_HELP \
"Disable watchdog instance. Syntax:\n" \
"<device>"
#define WDT_TIMEOUT_HELP \
"Install a new timeout. Syntax:\n" \
"<device> <none|cpu|soc> <min_ms> <max_ms>"
#define WDT_FEED_HELP \
"Feed specified watchdog timeout. Syntax:\n" \
"<device> <channel_id>"
static const char *const wdt_reset_name[] = {
[WDT_FLAG_RESET_NONE] = "none",
[WDT_FLAG_RESET_CPU_CORE] = "cpu",
[WDT_FLAG_RESET_SOC] = "soc",
};
struct args_index {
uint8_t device;
uint8_t reset;
uint8_t timeout_min;
uint8_t timeout_max;
uint8_t channel_id;
};
static const struct args_index args_indx = {
.device = 1,
.reset = 2,
.timeout_min = 3,
.timeout_max = 4,
.channel_id = 2,
};
static int parse_named_int(const char *name, const char *const keystack[], size_t count)
{
char *endptr;
int i;
/* Attempt to parse name as a number first */
i = strtoul(name, &endptr, 0);
if (*endptr == '\0') {
return i;
}
/* Name is not a number, look it up */
for (i = 0; i < count; i++) {
if (strcmp(name, keystack[i]) == 0) {
return i;
}
}
return -ENOTSUP;
}
static int cmd_setup(const struct shell *sh, size_t argc, char *argv[])
{
const struct device *dev;
dev = device_get_binding(argv[args_indx.device]);
if (!dev) {
shell_error(sh, "WDT device not found");
return -ENODEV;
}
return wdt_setup(dev, 0);
}
static int cmd_disable(const struct shell *sh, size_t argc, char *argv[])
{
const struct device *dev;
dev = device_get_binding(argv[args_indx.device]);
if (!dev) {
shell_error(sh, "WDT device not found");
return -ENODEV;
}
return wdt_disable(dev);
}
static int cmd_timeout(const struct shell *sh, size_t argc, char *argv[])
{
const struct device *dev;
int flags;
int timeout_min;
int timeout_max;
struct wdt_timeout_cfg cfg;
int rc;
dev = device_get_binding(argv[args_indx.device]);
if (!dev) {
shell_error(sh, "WDT device not found");
return -ENODEV;
}
flags = parse_named_int(argv[args_indx.reset], wdt_reset_name, ARRAY_SIZE(wdt_reset_name));
if (flags < 0) {
shell_error(sh, "Reset mode '%s' unknown", argv[args_indx.reset]);
return -EINVAL;
}
timeout_min = parse_named_int(argv[args_indx.timeout_min], NULL, 0);
if (timeout_min < 0) {
shell_error(sh, "Unable to convert '%s' to integer", argv[args_indx.timeout_min]);
return -EINVAL;
}
timeout_max = parse_named_int(argv[args_indx.timeout_max], NULL, 0);
if (timeout_max < 0) {
shell_error(sh, "Unable to convert '%s' to integer", argv[args_indx.timeout_max]);
return -EINVAL;
}
cfg.window.min = timeout_min;
cfg.window.max = timeout_max;
cfg.callback = NULL;
cfg.flags = flags;
rc = wdt_install_timeout(dev, &cfg);
if (rc >= 0) {
shell_print(sh, "Channel ID = %d", rc);
}
return rc;
}
static int cmd_feed(const struct shell *sh, size_t argc, char *argv[])
{
const struct device *dev;
int channel_id;
dev = device_get_binding(argv[args_indx.device]);
if (!dev) {
shell_error(sh, "WDT device not found");
return -ENODEV;
}
channel_id = parse_named_int(argv[args_indx.channel_id], NULL, 0);
if (channel_id < 0) {
shell_error(sh, "Unable to convert '%s' to integer", argv[args_indx.channel_id]);
return -EINVAL;
}
return wdt_feed(dev, channel_id);
}
/* Device name autocompletion support */
static void device_name_get(size_t idx, struct shell_static_entry *entry)
{
const struct device *dev = shell_device_lookup(idx, NULL);
entry->syntax = (dev != NULL) ? dev->name : NULL;
entry->handler = NULL;
entry->help = NULL;
entry->subcmd = NULL;
}
SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
/* clang-format off */
SHELL_STATIC_SUBCMD_SET_CREATE(sub_wdt,
SHELL_CMD_ARG(setup, &dsub_device_name, WDT_SETUP_HELP, cmd_setup,
2, 0),
SHELL_CMD_ARG(disable, &dsub_device_name, WDT_DISABLE_HELP, cmd_disable,
2, 0),
SHELL_CMD_ARG(timeout, &dsub_device_name, WDT_TIMEOUT_HELP, cmd_timeout,
5, 0),
SHELL_CMD_ARG(feed, &dsub_device_name, WDT_FEED_HELP, cmd_feed,
3, 0),
SHELL_SUBCMD_SET_END
);
/* clang-format on */
SHELL_CMD_REGISTER(wdt, &sub_wdt, "Watchdog commands", NULL);
``` | /content/code_sandbox/drivers/watchdog/wdt_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,224 |
```unknown
# Intel TCO WDT support
config WDT_TCO
bool "Intel TCO Watchdog driver"
default y
depends on DT_HAS_INTEL_TCO_WDT_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable support for Intel TCO WDT driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.tco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
# NUMAKER Watchdog Driver configuration options
config WWDT_NUMAKER
bool "Nuvoton NUMAKER MCU Window Watchdog driver"
default y
depends on DT_HAS_NUVOTON_NUMAKER_WWDT_ENABLED
help
This option enables the Watchdog driver for Nuvoton NuMaker family of
processors.
Say y if you wish to enable NuMaker WWDT.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_watchdog
/* Include esp-idf headers first to avoid redefining BIT() macro */
#if defined(CONFIG_SOC_SERIES_ESP32C6)
#include <soc/lp_aon_reg.h>
#else
#include <soc/rtc_cntl_reg.h>
#endif
#include <soc/timer_group_reg.h>
#include <hal/mwdt_ll.h>
#include <hal/wdt_hal.h>
#include <string.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#else
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#endif
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
#define ISR_HANDLER isr_handler_t
#else
#define ISR_HANDLER intr_handler_t
#endif
#define MWDT_TICK_PRESCALER 40000
#define MWDT_TICKS_PER_US 500
struct wdt_esp32_data {
wdt_hal_context_t hal;
uint32_t timeout;
wdt_stage_action_t mode;
wdt_callback_t callback;
};
struct wdt_esp32_config {
wdt_inst_t wdt_inst;
const struct device *clock_dev;
const clock_control_subsys_t clock_subsys;
void (*connect_irq)(void);
int irq_source;
};
static inline void wdt_esp32_seal(const struct device *dev)
{
struct wdt_esp32_data *data = dev->data;
wdt_hal_write_protect_enable(&data->hal);
}
static inline void wdt_esp32_unseal(const struct device *dev)
{
struct wdt_esp32_data *data = dev->data;
wdt_hal_write_protect_disable(&data->hal);
}
static void wdt_esp32_enable(const struct device *dev)
{
struct wdt_esp32_data *data = dev->data;
wdt_esp32_unseal(dev);
wdt_hal_enable(&data->hal);
wdt_esp32_seal(dev);
}
static int wdt_esp32_disable(const struct device *dev)
{
struct wdt_esp32_data *data = dev->data;
wdt_esp32_unseal(dev);
wdt_hal_disable(&data->hal);
wdt_esp32_seal(dev);
return 0;
}
static void wdt_esp32_isr(void *arg);
static int wdt_esp32_feed(const struct device *dev, int channel_id)
{
struct wdt_esp32_data *data = dev->data;
wdt_esp32_unseal(dev);
wdt_hal_feed(&data->hal);
wdt_esp32_seal(dev);
return 0;
}
static int wdt_esp32_set_config(const struct device *dev, uint8_t options)
{
struct wdt_esp32_data *data = dev->data;
wdt_esp32_unseal(dev);
wdt_hal_config_stage(&data->hal, WDT_STAGE0, data->timeout, WDT_STAGE_ACTION_INT);
wdt_hal_config_stage(&data->hal, WDT_STAGE1, data->timeout, data->mode);
wdt_esp32_enable(dev);
wdt_esp32_seal(dev);
wdt_esp32_feed(dev, 0);
return 0;
}
static int wdt_esp32_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_esp32_data *data = dev->data;
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
data->timeout = cfg->window.max;
data->callback = cfg->callback;
/* Set mode of watchdog and callback */
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
data->mode = WDT_STAGE_ACTION_RESET_SYSTEM;
LOG_DBG("Configuring reset SOC mode");
break;
case WDT_FLAG_RESET_CPU_CORE:
data->mode = WDT_STAGE_ACTION_RESET_CPU;
LOG_DBG("Configuring reset CPU mode");
break;
case WDT_FLAG_RESET_NONE:
data->mode = WDT_STAGE_ACTION_OFF;
LOG_DBG("Configuring non-reset mode");
break;
default:
LOG_ERR("Unsupported watchdog config flag");
return -EINVAL;
}
return 0;
}
static int wdt_esp32_init(const struct device *dev)
{
const struct wdt_esp32_config *const config = dev->config;
struct wdt_esp32_data *data = dev->data;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
clock_control_on(config->clock_dev, config->clock_subsys);
wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
esp_intr_alloc(config->irq_source,
0,
(ISR_HANDLER)wdt_esp32_isr,
(void *)dev,
NULL);
#ifndef CONFIG_WDT_DISABLE_AT_BOOT
wdt_esp32_enable(dev);
#endif
return 0;
}
static const struct wdt_driver_api wdt_api = {
.setup = wdt_esp32_set_config,
.disable = wdt_esp32_disable,
.install_timeout = wdt_esp32_install_timeout,
.feed = wdt_esp32_feed
};
#define ESP32_WDT_INIT(idx) \
static struct wdt_esp32_data wdt##idx##_data; \
static struct wdt_esp32_config wdt_esp32_config##idx = { \
.wdt_inst = WDT_MWDT##idx, \
.irq_source = DT_IRQN(DT_NODELABEL(wdt##idx)), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, \
wdt_esp32_init, \
NULL, \
&wdt##idx##_data, \
&wdt_esp32_config##idx, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_api)
static void wdt_esp32_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
const struct wdt_esp32_config *config = dev->config;
struct wdt_esp32_data *data = dev->data;
if (data->callback) {
data->callback(dev, 0);
}
wdt_hal_handle_intr(&data->hal);
}
#if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt0), okay)
ESP32_WDT_INIT(0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(wdt1), okay)
ESP32_WDT_INIT(1);
#endif
``` | /content/code_sandbox/drivers/watchdog/wdt_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,575 |
```unknown
# SiFive Freedom WDT configuration
config WDT_SIFIVE
bool "SiFive Watchdog (WDT) Driver"
default y
depends on DT_HAS_SIFIVE_WDT_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
This option enables WDT driver for SiFive Freedom.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.sifive | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```c
/*
*
*/
#define DT_DRV_COMPAT silabs_gecko_wdog
#include <soc.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <em_wdog.h>
#include <em_cmu.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_gecko, CONFIG_WDT_LOG_LEVEL);
#ifdef cmuClock_CORELE
#define CLOCK_DEF(id) cmuClock_CORELE
#else
#define CLOCK_DEF(id) cmuClock_WDOG##id
#endif /* cmuClock_CORELE */
#define CLOCK_ID(id) CLOCK_DEF(id)
/* Defines maximum WDOG_CTRL.PERSEL value which is used by the watchdog module
* to select its timeout period.
*/
#define WDT_GECKO_MAX_PERIOD_SELECT_VALUE 15
/* Device constant configuration parameters */
struct wdt_gecko_cfg {
WDOG_TypeDef *base;
CMU_Clock_TypeDef clock;
void (*irq_cfg_func)(void);
};
struct wdt_gecko_data {
wdt_callback_t callback;
WDOG_Init_TypeDef wdog_config;
bool timeout_installed;
};
static uint32_t wdt_gecko_get_timeout_from_persel(int perSel)
{
return (8 << perSel) + 1;
}
/* Find the rounded up value of cycles for supplied timeout. When using ULFRCO
* (default), 1 cycle is 1 ms +/- 12%.
*/
static int wdt_gecko_get_persel_from_timeout(uint32_t timeout)
{
int idx;
for (idx = 0; idx < WDT_GECKO_MAX_PERIOD_SELECT_VALUE; idx++) {
if (wdt_gecko_get_timeout_from_persel(idx) >= timeout) {
break;
}
}
return idx;
}
static int wdt_gecko_convert_window(uint32_t window, uint32_t period)
{
int idx = 0;
uint32_t incr_val, comp_val;
incr_val = period / 8;
comp_val = 0; /* Initially 0, disable */
/* Valid window settings range from 12.5% of the calculated
* timeout period up to 87.5% (= 7 * 12.5%)
*/
while (idx < 7) {
if (window > comp_val) {
comp_val += incr_val;
idx++;
continue;
}
break;
}
return idx;
}
static int wdt_gecko_setup(const struct device *dev, uint8_t options)
{
const struct wdt_gecko_cfg *config = dev->config;
struct wdt_gecko_data *data = dev->data;
WDOG_TypeDef *wdog = config->base;
if (!data->timeout_installed) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
data->wdog_config.em2Run =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.em3Run =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.debugRun =
(options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U;
if (data->callback != NULL) {
/* Interrupt mode for window */
/* Clear possible lingering interrupts */
WDOGn_IntClear(wdog, WDOG_IEN_TOUT);
/* Enable timeout interrupt */
WDOGn_IntEnable(wdog, WDOG_IEN_TOUT);
} else {
/* Disable timeout interrupt */
WDOGn_IntDisable(wdog, WDOG_IEN_TOUT);
}
/* Watchdog is started after initialization */
WDOGn_Init(wdog, &data->wdog_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int wdt_gecko_disable(const struct device *dev)
{
const struct wdt_gecko_cfg *config = dev->config;
struct wdt_gecko_data *data = dev->data;
WDOG_TypeDef *wdog = config->base;
WDOGn_Enable(wdog, false);
data->timeout_installed = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
static int wdt_gecko_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_gecko_data *data = dev->data;
data->wdog_config = (WDOG_Init_TypeDef)WDOG_INIT_DEFAULT;
uint32_t installed_timeout;
if (data->timeout_installed) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if ((cfg->window.max < wdt_gecko_get_timeout_from_persel(0)) ||
(cfg->window.max > wdt_gecko_get_timeout_from_persel(
WDT_GECKO_MAX_PERIOD_SELECT_VALUE))) {
LOG_ERR("Upper limit timeout out of range");
return -EINVAL;
}
#if defined(_WDOG_CTRL_CLKSEL_MASK)
data->wdog_config.clkSel = wdogClkSelULFRCO;
#endif
data->wdog_config.perSel = (WDOG_PeriodSel_TypeDef)
wdt_gecko_get_persel_from_timeout(cfg->window.max);
installed_timeout = wdt_gecko_get_timeout_from_persel(
data->wdog_config.perSel);
LOG_INF("Installed timeout value: %u", installed_timeout);
if (cfg->window.min > 0) {
/* Window mode. Use rounded up timeout value to
* calculate minimum window setting.
*/
data->wdog_config.winSel = (WDOG_WinSel_TypeDef)
wdt_gecko_convert_window(cfg->window.min,
installed_timeout);
LOG_INF("Installed window value: %u",
(installed_timeout / 8) * data->wdog_config.winSel);
} else {
/* Normal mode */
data->wdog_config.winSel = wdogIllegalWindowDisable;
}
/* Set mode of watchdog and callback */
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
case WDT_FLAG_RESET_CPU_CORE:
if (cfg->callback != NULL) {
LOG_ERR("Reset mode with callback not supported\n");
return -ENOTSUP;
}
data->wdog_config.resetDisable = false;
LOG_DBG("Configuring reset CPU/SoC mode\n");
break;
case WDT_FLAG_RESET_NONE:
data->wdog_config.resetDisable = true;
data->callback = cfg->callback;
LOG_DBG("Configuring non-reset mode\n");
break;
default:
LOG_ERR("Unsupported watchdog config flag");
return -EINVAL;
}
data->timeout_installed = true;
return 0;
}
static int wdt_gecko_feed(const struct device *dev, int channel_id)
{
const struct wdt_gecko_cfg *config = dev->config;
WDOG_TypeDef *wdog = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WDOGn_Feed(wdog);
LOG_DBG("Fed the watchdog");
return 0;
}
static void wdt_gecko_isr(const struct device *dev)
{
const struct wdt_gecko_cfg *config = dev->config;
struct wdt_gecko_data *data = dev->data;
WDOG_TypeDef *wdog = config->base;
uint32_t flags;
/* Clear IRQ flags */
flags = WDOGn_IntGet(wdog);
WDOGn_IntClear(wdog, flags);
if (data->callback != NULL) {
data->callback(dev, 0);
}
}
static int wdt_gecko_init(const struct device *dev)
{
const struct wdt_gecko_cfg *config = dev->config;
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
/* Ignore any errors */
wdt_gecko_disable(dev);
#endif
/* Enable ULFRCO (1KHz) oscillator */
CMU_OscillatorEnable(cmuOsc_ULFRCO, true, false);
/* Ensure LE modules are clocked */
CMU_ClockEnable(config->clock, true);
#if defined(_SILICON_LABS_32B_SERIES_2)
CMU_ClockSelectSet(config->clock, cmuSelect_ULFRCO);
/* Enable Watchdog clock. */
CMU_ClockEnable(cmuClock_WDOG0, true);
#endif
/* Enable IRQs */
config->irq_cfg_func();
LOG_INF("Device %s initialized", dev->name);
return 0;
}
static const struct wdt_driver_api wdt_gecko_driver_api = {
.setup = wdt_gecko_setup,
.disable = wdt_gecko_disable,
.install_timeout = wdt_gecko_install_timeout,
.feed = wdt_gecko_feed,
};
#define GECKO_WDT_INIT(index) \
\
static void wdt_gecko_cfg_func_##index(void); \
\
static const struct wdt_gecko_cfg wdt_gecko_cfg_##index = { \
.base = (WDOG_TypeDef *) \
DT_INST_REG_ADDR(index),\
.clock = CLOCK_ID(DT_INST_PROP(index, peripheral_id)), \
.irq_cfg_func = wdt_gecko_cfg_func_##index, \
}; \
static struct wdt_gecko_data wdt_gecko_data_##index; \
\
DEVICE_DT_INST_DEFINE(index, \
&wdt_gecko_init, NULL, \
&wdt_gecko_data_##index, \
&wdt_gecko_cfg_##index, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&wdt_gecko_driver_api); \
\
static void wdt_gecko_cfg_func_##index(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(index), \
DT_INST_IRQ(index, priority),\
wdt_gecko_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
}
DT_INST_FOREACH_STATUS_OKAY(GECKO_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,163 |
```c
/*
*
*/
#define DT_DRV_COMPAT ambiq_watchdog
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <errno.h>
#include <am_mcu_apollo.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_ambiq, CONFIG_WDT_LOG_LEVEL);
typedef void (*ambiq_wdt_cfg_func_t)(void);
struct wdt_ambiq_config {
uint32_t base;
uint32_t irq_num;
uint8_t clk_freq;
ambiq_wdt_cfg_func_t cfg_func;
};
struct wdt_ambiq_data {
wdt_callback_t callback;
uint32_t timeout;
bool reset;
};
static void wdt_ambiq_isr(void *arg)
{
const struct device *dev = (const struct device *)arg;
struct wdt_ambiq_data *data = dev->data;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_wdt_int_clear();
#else
uint32_t status;
am_hal_wdt_interrupt_status_get(AM_HAL_WDT_MCU, &status, false);
am_hal_wdt_interrupt_clear(AM_HAL_WDT_MCU, status);
#endif
if (data->callback) {
data->callback(dev, 0);
}
}
static int wdt_ambiq_setup(const struct device *dev, uint8_t options)
{
const struct wdt_ambiq_config *dev_cfg = dev->config;
struct wdt_ambiq_data *data = dev->data;
am_hal_wdt_config_t cfg;
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
uint32_t ui32ClockSource = AM_HAL_WDT_LFRC_CLK_DEFAULT;
if (dev_cfg->clk_freq == 128) {
ui32ClockSource = AM_HAL_WDT_LFRC_CLK_128HZ;
} else if (dev_cfg->clk_freq == 16) {
ui32ClockSource = AM_HAL_WDT_LFRC_CLK_16HZ;
} else if (dev_cfg->clk_freq == 1) {
ui32ClockSource = AM_HAL_WDT_LFRC_CLK_1HZ;
}
cfg.ui32Config = ui32ClockSource | _VAL2FLD(WDT_CFG_RESEN, data->reset) |
AM_HAL_WDT_ENABLE_INTERRUPT;
cfg.ui16InterruptCount = data->timeout;
cfg.ui16ResetCount = data->timeout;
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_LFRC_START, 0);
am_hal_wdt_init(&cfg);
am_hal_wdt_int_enable();
am_hal_wdt_start();
#else
if (dev_cfg->clk_freq == 128) {
cfg.eClockSource = AM_HAL_WDT_128HZ;
} else if (dev_cfg->clk_freq == 16) {
cfg.eClockSource = AM_HAL_WDT_16HZ;
} else if (dev_cfg->clk_freq == 1) {
cfg.eClockSource = AM_HAL_WDT_1HZ;
}
cfg.bInterruptEnable = true;
cfg.ui32InterruptValue = data->timeout;
cfg.bResetEnable = data->reset;
cfg.ui32ResetValue = data->timeout;
cfg.bAlertOnDSPReset = false;
am_hal_wdt_config(AM_HAL_WDT_MCU, &cfg);
am_hal_wdt_interrupt_enable(AM_HAL_WDT_MCU, AM_HAL_WDT_INTERRUPT_MCU);
am_hal_wdt_start(AM_HAL_WDT_MCU, false);
#endif
return 0;
}
static int wdt_ambiq_disable(const struct device *dev)
{
ARG_UNUSED(dev);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_wdt_halt();
#else
am_hal_wdt_stop(AM_HAL_WDT_MCU);
#endif
return 0;
}
static int wdt_ambiq_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
const struct wdt_ambiq_config *dev_cfg = dev->config;
struct wdt_ambiq_data *data = dev->data;
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
data->timeout = cfg->window.max / 1000 * dev_cfg->clk_freq;
data->callback = cfg->callback;
switch (cfg->flags) {
case WDT_FLAG_RESET_CPU_CORE:
case WDT_FLAG_RESET_SOC:
data->reset = true;
break;
case WDT_FLAG_RESET_NONE:
data->reset = false;
break;
default:
LOG_ERR("Unsupported watchdog config flag");
return -EINVAL;
}
return 0;
}
static int wdt_ambiq_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(dev);
ARG_UNUSED(channel_id);
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_wdt_restart();
#else
am_hal_wdt_restart(AM_HAL_WDT_MCU);
#endif
LOG_DBG("Fed the watchdog");
return 0;
}
static int wdt_ambiq_init(const struct device *dev)
{
const struct wdt_ambiq_config *dev_cfg = dev->config;
if (dev_cfg->clk_freq != 128 && dev_cfg->clk_freq != 16 && dev_cfg->clk_freq != 1) {
return -ENOTSUP;
}
NVIC_ClearPendingIRQ(dev_cfg->irq_num);
dev_cfg->cfg_func();
irq_enable(dev_cfg->irq_num);
return 0;
}
static const struct wdt_driver_api wdt_ambiq_driver_api = {
.setup = wdt_ambiq_setup,
.disable = wdt_ambiq_disable,
.install_timeout = wdt_ambiq_install_timeout,
.feed = wdt_ambiq_feed,
};
#define AMBIQ_WDT_INIT(n) \
static struct wdt_ambiq_data wdt_ambiq_data##n; \
static void ambiq_wdt_cfg_func_##n(void) \
{ \
\
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), wdt_ambiq_isr, \
DEVICE_DT_INST_GET(n), 0); \
}; \
static const struct wdt_ambiq_config wdt_ambiq_config##n = { \
.base = DT_INST_REG_ADDR(n), \
.clk_freq = DT_INST_PROP(n, clock_frequency), \
.irq_num = DT_INST_IRQN(n), \
.cfg_func = ambiq_wdt_cfg_func_##n}; \
\
DEVICE_DT_INST_DEFINE(n, wdt_ambiq_init, NULL, &wdt_ambiq_data##n, &wdt_ambiq_config##n, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_ambiq_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,491 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_watchdog
#include <errno.h>
#include <stdint.h>
#include <soc.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <xmc_scu.h>
#include <xmc_wdt.h>
struct wdt_xmc4xxx_dev_data {
wdt_callback_t cb;
uint8_t mode;
bool timeout_valid;
bool is_serviced;
};
/* When the watchdog counter rolls over, the SCU will generate a */
/* pre-warning event which gets routed to the ISR below. If the */
/* watchdog is not serviced, the SCU will only reset the MCU */
/* after the second time the counter rolls over. */
/* Hence the reset will only happen after 2*cfg->window.max have elapsed. */
/* We could potentially manually reset the MCU, but this way the context */
/* information (i.e. that reset happened because of a watchdog) is lost. */
static void wdt_xmc4xxx_isr(const struct device *dev)
{
struct wdt_xmc4xxx_dev_data *data = dev->data;
uint32_t event = XMC_SCU_INTERUPT_GetEventStatus();
/* todo add interrupt controller? */
if ((event & XMC_SCU_INTERRUPT_EVENT_WDT_WARN) == 0) {
return;
}
/* this is a level triggered interrupt. the event must be cleared */
XMC_SCU_INTERRUPT_ClearEventStatus(XMC_SCU_INTERRUPT_EVENT_WDT_WARN);
data->is_serviced = false;
if (data->cb) {
data->cb(dev, 0);
}
/* Ensure that watchdog is serviced if RESET_NONE mode is used */
if (data->mode == WDT_FLAG_RESET_NONE && !data->is_serviced) {
XMC_WDT_Service();
}
XMC_WDT_ClearAlarm();
}
static int wdt_xmc4xxx_disable(const struct device *dev)
{
struct wdt_xmc4xxx_dev_data *data = dev->data;
XMC_WDT_Stop();
XMC_WDT_Disable();
data->timeout_valid = false;
return 0;
}
static int wdt_xmc4xxx_setup(const struct device *dev, uint8_t options)
{
struct wdt_xmc4xxx_dev_data *data = dev->data;
if (!data->timeout_valid) {
return -EINVAL;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
SCU_CLK->SLEEPCR &= ~XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT;
} else {
SCU_CLK->SLEEPCR |= XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT;
}
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) != 0) {
XMC_WDT_SetDebugMode(XMC_WDT_DEBUG_MODE_STOP);
} else {
XMC_WDT_SetDebugMode(XMC_WDT_DEBUG_MODE_RUN);
}
XMC_WDT_Start();
return 0;
}
static int wdt_xmc4xxx_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
XMC_WDT_CONFIG_t wdt_config = {0};
struct wdt_xmc4xxx_dev_data *data = dev->data;
uint32_t wdt_clock;
/* disable the watchdog if timeout was already installed */
if (data->timeout_valid) {
wdt_xmc4xxx_disable(dev);
data->timeout_valid = false;
}
if (cfg->window.min != 0 || cfg->window.max == 0) {
return -EINVAL;
}
wdt_clock = XMC_SCU_CLOCK_GetWdtClockFrequency();
if ((uint64_t)cfg->window.max * wdt_clock / 1000 > UINT32_MAX) {
return -EINVAL;
}
wdt_config.window_upper_bound = (uint64_t)cfg->window.max * wdt_clock / 1000;
XMC_WDT_Init(&wdt_config);
XMC_WDT_SetDebugMode(XMC_WDT_MODE_PREWARNING);
XMC_SCU_INTERRUPT_EnableEvent(XMC_SCU_INTERRUPT_EVENT_WDT_WARN);
if (cfg->flags == WDT_FLAG_RESET_NONE && cfg->callback == NULL) {
return -EINVAL;
}
data->cb = cfg->callback;
data->mode = cfg->flags;
data->timeout_valid = true;
return 0;
}
static int wdt_xmc4xxx_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(channel_id);
struct wdt_xmc4xxx_dev_data *data = dev->data;
XMC_WDT_Service();
data->is_serviced = true;
return 0;
}
static const struct wdt_driver_api wdt_xmc4xxx_api = {
.setup = wdt_xmc4xxx_setup,
.disable = wdt_xmc4xxx_disable,
.install_timeout = wdt_xmc4xxx_install_timeout,
.feed = wdt_xmc4xxx_feed,
};
static struct wdt_xmc4xxx_dev_data wdt_xmc4xxx_data;
static void wdt_xmc4xxx_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), wdt_xmc4xxx_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
static int wdt_xmc4xxx_init(const struct device *dev)
{
wdt_xmc4xxx_irq_config();
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
return 0;
#else
int ret;
const struct wdt_timeout_cfg cfg = {.window.max = CONFIG_WDT_XMC4XXX_DEFAULT_TIMEOUT_MAX_MS,
.flags = WDT_FLAG_RESET_SOC};
ret = wdt_xmc4xxx_install_timeout(dev, &cfg);
if (ret < 0) {
return ret;
}
return wdt_xmc4xxx_setup(dev, WDT_OPT_PAUSE_HALTED_BY_DBG);
#endif
}
DEVICE_DT_INST_DEFINE(0, wdt_xmc4xxx_init, NULL, &wdt_xmc4xxx_data, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_xmc4xxx_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,318 |
```unknown
config WDT_ITE_IT8XXX2
bool "ITE it8xxx2 Watchdog Timer (WDT) driver"
default y
depends on DT_HAS_ITE_IT8XXX2_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
This option enables the Watchdog Timer driver for ITE it8xxx2.
This driver supports only one channel that id is 0 and 16-bits
resolution WDT.
config WDT_ITE_WARNING_LEADING_TIME_MS
int "Number of ms before generating watchdog event/signal"
depends on WDT_ITE_IT8XXX2
default 500
help
This option defines the window in which a watchdog event must be
handled. After this time window, the watchdog reset triggers
immediately.
config WDT_ITE_REDUCE_WARNING_LEADING_TIME
bool "Reduce warning leading time"
depends on WDT_ITE_IT8XXX2
help
Once warning timer triggered, if watchdog timer isn't reloaded,
then we will reduce interval of warning timer to 30ms to print
more warning messages before watchdog reset.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 238 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc32xx_watchdog
#include <zephyr/drivers/watchdog.h>
#include <soc.h>
#include <errno.h>
/* Driverlib includes */
#include <inc/hw_types.h>
#include <inc/hw_wdt.h>
#include <driverlib/pin.h>
#include <driverlib/rom.h>
#include <driverlib/rom_map.h>
#include <driverlib/prcm.h>
#include <driverlib/wdt.h>
#define MAX_RELOAD_VALUE 0xFFFFFFFF
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/logging/log_ctrl.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_cc32xx);
struct wdt_cc32xx_data {
int reload;
wdt_callback_t cb;
uint8_t flags;
};
struct wdt_cc32xx_cfg {
const unsigned long reg;
void (*irq_cfg_func)(void);
};
static uint32_t wdt_cc32xx_msToTicks(uint32_t ms)
{
static const uint32_t ratio = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000;
static const uint32_t maxMs = MAX_RELOAD_VALUE / ratio;
if (ms > maxMs) {
return maxMs;
}
return ms * ratio;
}
static int wdt_cc32xx_enable(const struct device *dev)
{
struct wdt_cc32xx_data *data = dev->data;
const struct wdt_cc32xx_cfg *config = dev->config;
const uint32_t reload = wdt_cc32xx_msToTicks(data->reload);
MAP_WatchdogIntClear(config->reg);
MAP_WatchdogReloadSet(config->reg, reload);
MAP_WatchdogEnable(config->reg);
LOG_DBG("Enabled");
return 0;
}
static int wdt_cc32xx_setup(const struct device *dev, uint8_t options)
{
const struct wdt_cc32xx_cfg *config = dev->config;
int rv;
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
MAP_WatchdogUnlock(config->reg);
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
MAP_WatchdogStallEnable(config->reg);
} else {
MAP_WatchdogStallDisable(config->reg);
}
rv = wdt_cc32xx_enable(dev);
MAP_WatchdogLock(config->reg);
return rv;
}
static int wdt_cc32xx_disable(const struct device *dev)
{
return -ENOTSUP;
}
static int wdt_cc32xx_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_cc32xx_data *data = dev->data;
if (COND_CODE_1(CONFIG_WDT_MULTISTAGE, (cfg->next), (0))) {
return -ENOTSUP;
}
data->reload = cfg->window.max;
data->cb = cfg->callback;
data->flags = cfg->flags;
LOG_DBG("Reload time %d", data->reload);
return 0;
}
static int wdt_cc32xx_feed(const struct device *dev, int channel_id)
{
struct wdt_cc32xx_data *data = dev->data;
const struct wdt_cc32xx_cfg *config = dev->config;
const uint32_t reload = wdt_cc32xx_msToTicks(data->reload);
bool inIsr = k_is_in_isr();
if (!inIsr) {
MAP_WatchdogUnlock(config->reg);
}
MAP_WatchdogIntClear(config->reg);
MAP_WatchdogReloadSet(config->reg, reload);
if (!inIsr) {
MAP_WatchdogLock(config->reg);
}
LOG_DBG("Feed");
return 0;
}
static void wdt_cc32xx_isr(const struct device *dev)
{
struct wdt_cc32xx_data *data = dev->data;
LOG_DBG("ISR");
if (data->cb) {
data->cb(dev, 0);
}
if (data->flags != WDT_FLAG_RESET_NONE) {
LOG_PANIC();
MAP_PRCMMCUReset(data->flags & WDT_FLAG_RESET_SOC);
while (1) {
}
}
}
static int wdt_cc32xx_init(const struct device *dev)
{
const struct wdt_cc32xx_cfg *config = dev->config;
int rv;
LOG_DBG("init");
config->irq_cfg_func();
MAP_PRCMPeripheralClkEnable(PRCM_WDT, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
while (!MAP_PRCMPeripheralStatusGet(PRCM_WDT)) {
}
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
return 0;
}
MAP_WatchdogUnlock(config->reg);
rv = wdt_cc32xx_enable(dev);
MAP_WatchdogLock(config->reg);
return rv;
}
static const struct wdt_driver_api wdt_cc32xx_api = {
.setup = wdt_cc32xx_setup,
.disable = wdt_cc32xx_disable,
.install_timeout = wdt_cc32xx_install_timeout,
.feed = wdt_cc32xx_feed,
};
#define cc32xx_WDT_INIT(index) \
\
static void wdt_cc32xx_irq_cfg_##index(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(index), \
DT_INST_IRQ(index, priority), \
wdt_cc32xx_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
} \
\
static struct wdt_cc32xx_data wdt_cc32xx_data_##index = { \
.reload = CONFIG_WDT_CC32XX_INITIAL_TIMEOUT, \
.cb = NULL, \
.flags = 0, \
}; \
\
static struct wdt_cc32xx_cfg wdt_cc32xx_cfg_##index = { \
.reg = (unsigned long)DT_INST_REG_ADDR(index), \
.irq_cfg_func = wdt_cc32xx_irq_cfg_##index, \
}; \
\
DEVICE_DT_INST_DEFINE(index, \
&wdt_cc32xx_init, NULL, \
&wdt_cc32xx_data_##index, &wdt_cc32xx_cfg_##index, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&wdt_cc32xx_api);
DT_INST_FOREACH_STATUS_OKAY(cc32xx_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_cc32xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,399 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_COMMON_H_
#define ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_COMMON_H_
#include <stdint.h>
/**
* @brief Check watchdog configuration options
*
* Check options value passed to a watchdog setup function. Returns error if unsupported option
* is used.
*
* @param options options value passed to a watchdog setup function.
* @return Error code, 0 on success.
*/
int dw_wdt_check_options(const uint8_t options);
/**
* @brief Configure watchdog device
*
* @param base Device base address.
* @param config device configuration word
* @return Error code, 0 on success.
*/
int dw_wdt_configure(const uint32_t base, const uint32_t config);
/**
* @brief Calculate period
*
* @param [in]base Device base address.
* @param [in]clk_freq frequency of a clock used by watchdog device
* @param [in]config pointer to a watchdog configuration structure
* @param [out]period_out pointer to a variable in which the period configuration word will be
* placed
* @return Error code, 0 on success.
*/
int dw_wdt_calc_period(const uint32_t base, const uint32_t clk_freq,
const struct wdt_timeout_cfg *config, uint32_t *period_out);
/**
* @brief Watchdog probe
*
* Checks device id register and configure a reset pulse length.
*
* @param base Device base address.
* @param reset_pulse_length Length of a reset pulse produced by watchdog
* @return Error code, 0 on success.
*/
int dw_wdt_probe(const uint32_t base, const uint32_t reset_pulse_length);
/**
* @brief Watchdog disable function
*
* @param dev Device structure.
* @return -ENOTSUP. The hardware does not support disabling.
*/
int dw_wdt_disable(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_COMMON_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_dw_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_wdog
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/sys_clock.h>
#include <fsl_wdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_mcux_wdog);
#define WDOG_TMOUT_SEC(x) (((x * 2) / MSEC_PER_SEC) - 1)
struct mcux_wdog_config {
WDOG_Type *base;
void (*irq_config_func)(const struct device *dev);
const struct pinctrl_dev_config *pcfg;
};
struct mcux_wdog_data {
wdt_callback_t callback;
wdog_config_t wdog_config;
bool timeout_valid;
};
static int mcux_wdog_setup(const struct device *dev, uint8_t options)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
data->wdog_config.workMode.enableStop =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.workMode.enableDebug =
(options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U;
WDOG_Init(base, &data->wdog_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_wdog_disable(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
WDOG_Deinit(base);
data->timeout_valid = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
static int mcux_wdog_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct mcux_wdog_data *data = dev->data;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
WDOG_GetDefaultConfig(&data->wdog_config);
data->wdog_config.interruptTimeValue = 0U;
if (cfg->window.max < (MSEC_PER_SEC / 2)) {
LOG_ERR("Invalid window max, shortest window is 500ms");
return -EINVAL;
}
data->wdog_config.timeoutValue =
WDOG_TMOUT_SEC(cfg->window.max);
if (cfg->window.min) {
LOG_ERR("Invalid window.min, Do not support window model");
return -EINVAL;
}
if (data->wdog_config.timeoutValue > 128) {
LOG_ERR("Invalid timeoutValue, valid (0.5s - 128.0s)");
return -EINVAL;
}
data->wdog_config.enableInterrupt = cfg->callback != NULL;
data->callback = cfg->callback;
data->timeout_valid = true;
return 0;
}
static int mcux_wdog_feed(const struct device *dev, int channel_id)
{
const struct mcux_wdog_config *config = dev->config;
WDOG_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WDOG_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_wdog_isr(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
struct mcux_wdog_data *data = dev->data;
WDOG_Type *base = config->base;
uint32_t flags;
flags = WDOG_GetStatusFlags(base);
WDOG_ClearInterruptStatus(base, flags);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_wdog_init(const struct device *dev)
{
const struct mcux_wdog_config *config = dev->config;
int ret;
config->irq_config_func(dev);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0 && ret != -ENOENT) {
return ret;
}
return 0;
}
static const struct wdt_driver_api mcux_wdog_api = {
.setup = mcux_wdog_setup,
.disable = mcux_wdog_disable,
.install_timeout = mcux_wdog_install_timeout,
.feed = mcux_wdog_feed,
};
static void mcux_wdog_config_func(const struct device *dev);
PINCTRL_DT_INST_DEFINE(0);
static const struct mcux_wdog_config mcux_wdog_config = {
.base = (WDOG_Type *) DT_INST_REG_ADDR(0),
.irq_config_func = mcux_wdog_config_func,
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct mcux_wdog_data mcux_wdog_data;
DEVICE_DT_INST_DEFINE(0,
&mcux_wdog_init,
NULL,
&mcux_wdog_data, &mcux_wdog_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_wdog_api);
static void mcux_wdog_config_func(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
mcux_wdog_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
``` | /content/code_sandbox/drivers/watchdog/wdt_mcux_imx_wdog.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,185 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_wwdt
#include <zephyr/kernel.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <NuMicro.h>
LOG_MODULE_REGISTER(wwdt_numaker, CONFIG_WDT_LOG_LEVEL);
#define NUMAKER_PRESCALER_MAX 15U
#define NUMAKER_COUNTER_MAX 0x3eU
#define NUMAKER_COUNTER_MIN 0x01U
/* Device config */
struct wwdt_numaker_config {
/* wdt base address */
WWDT_T *wwdt_base;
uint32_t clk_modidx;
uint32_t clk_src;
uint32_t clk_div;
const struct device *clk_dev;
};
struct wwdt_numaker_data {
wdt_callback_t cb;
bool timeout_valid;
/* watchdog timeout in milliseconds */
uint32_t timeout;
uint32_t prescaler;
uint32_t counter;
};
static int m_wwdt_numaker_clk_get_rate(const struct wwdt_numaker_config *cfg, uint32_t *rate)
{
if (cfg->clk_src == CLK_CLKSEL1_WWDTSEL_LIRC) {
*rate = __LIRC / (cfg->clk_div + 1);
} else {
/* clock source is from HCLK, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 */
SystemCoreClockUpdate();
*rate = CLK_GetHCLKFreq() / 2048 / (cfg->clk_div + 1);
}
return 0;
}
/* Convert watchdog clock to nearest ms (rounded up) */
static uint32_t m_wwdt_numaker_calc_ms(const struct device *dev, uint32_t pow2)
{
const struct wwdt_numaker_config *cfg = dev->config;
uint32_t clk_freq;
uint32_t prescale_clks;
uint32_t period_ms;
m_wwdt_numaker_clk_get_rate(cfg, &clk_freq);
prescale_clks = (1 << pow2) * 64;
period_ms = DIV_ROUND_UP(prescale_clks * MSEC_PER_SEC, clk_freq);
return period_ms;
}
static int m_wwdt_numaker_calc_window(const struct device *dev,
const struct wdt_window *win,
uint32_t *timeout,
uint32_t *prescaler,
uint32_t *counter)
{
uint32_t pow2;
uint32_t gap;
/* Find nearest period value (rounded up) */
for (pow2 = 0U; pow2 <= NUMAKER_PRESCALER_MAX; pow2++) {
*timeout = m_wwdt_numaker_calc_ms(dev, pow2);
if (*timeout >= win->max) {
*prescaler = pow2 << WWDT_CTL_PSCSEL_Pos;
if (win->min == 0U) {
*counter = NUMAKER_COUNTER_MAX;
} else {
gap = DIV_ROUND_UP(win->min
* NUMAKER_COUNTER_MAX,
*timeout);
*counter = NUMAKER_COUNTER_MAX - gap;
if (*counter < NUMAKER_COUNTER_MIN) {
*counter = NUMAKER_COUNTER_MIN;
}
}
return 0;
}
}
return -EINVAL;
}
static int wwdt_numaker_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wwdt_numaker_data *data = dev->data;
const struct wwdt_numaker_config *config = dev->config;
uint32_t timeout;
uint32_t prescaler;
uint32_t counter;
LOG_DBG("");
/* Validate watchdog already running */
if (config->wwdt_base->CTL & WWDT_CTL_WWDTEN_Msk) {
LOG_ERR("watchdog is busy");
return -EBUSY;
}
if (cfg->window.max == 0U) {
LOG_ERR("window.max should be non-zero");
return -EINVAL;
}
if (m_wwdt_numaker_calc_window(dev, &cfg->window, &timeout, &prescaler, &counter) != 0) {
LOG_ERR("window.max is out of range");
return -EINVAL;
}
LOG_DBG("counter=%d", counter);
data->timeout = timeout;
data->prescaler = prescaler;
data->counter = counter;
data->cb = cfg->callback;
data->timeout_valid = true;
return 0;
}
static int wwdt_numaker_disable(const struct device *dev)
{
struct wwdt_numaker_data *data = dev->data;
const struct wwdt_numaker_config *cfg = dev->config;
WWDT_T *wwdt_base = cfg->wwdt_base;
LOG_DBG("");
/* stop counting */
wwdt_base->CTL &= ~WWDT_CTL_WWDTEN_Msk;
/* disable interrupt enable bit */
wwdt_base->CTL &= ~WWDT_CTL_INTEN_Msk;
/* disable interrupt */
irq_disable(DT_INST_IRQN(0));
data->timeout_valid = false;
return 0;
}
static int wwdt_numaker_setup(const struct device *dev, uint8_t options)
{
struct wwdt_numaker_data *data = dev->data;
const struct wwdt_numaker_config *cfg = dev->config;
WWDT_T *wwdt_base = cfg->wwdt_base;
uint32_t dbg_mask = 0U;
LOG_DBG("");
irq_disable(DT_INST_IRQN(0));
/* Validate watchdog already running */
if (wwdt_base->CTL & WWDT_CTL_WWDTEN_Msk) {
LOG_ERR("watchdog is busy");
return -EBUSY;
}
if (!data->timeout_valid) {
LOG_ERR("No valid timeout installed");
return -EINVAL;
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
return -ENOTSUP;
}
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
dbg_mask = WWDT_CTL_ICEDEBUG_Msk;
}
/* Clear WWDT Reset & Compared Match Interrupt System Flag */
wwdt_base->STATUS = WWDT_STATUS_WWDTRF_Msk |
WWDT_STATUS_WWDTIF_Msk;
/* Open WWDT and start counting */
wwdt_base->CTL = data->prescaler |
(data->counter << WWDT_CTL_CMPDAT_Pos) |
WWDT_CTL_INTEN_Msk |
WWDT_CTL_WWDTEN_Msk |
dbg_mask;
irq_enable(DT_INST_IRQN(0));
return 0;
}
static int wwdt_numaker_feed(const struct device *dev, int channel_id)
{
const struct wwdt_numaker_config *cfg = dev->config;
WWDT_T *wwdt_base = cfg->wwdt_base;
LOG_DBG("CNT=%d, CTL=0x%x", wwdt_base->CNT, wwdt_base->CTL);
ARG_UNUSED(channel_id);
/* Reload WWDT Counter */
wwdt_base->RLDCNT = WWDT_RELOAD_WORD;
return 0;
}
static void wwdt_numaker_isr(const struct device *dev)
{
struct wwdt_numaker_data *data = dev->data;
const struct wwdt_numaker_config *cfg = dev->config;
WWDT_T *wwdt_base = cfg->wwdt_base;
LOG_DBG("CNT=%d", wwdt_base->CNT);
if (wwdt_base->STATUS & WWDT_STATUS_WWDTIF_Msk) {
/* Clear WWDT Compared Match Interrupt Flag */
wwdt_base->STATUS = WWDT_STATUS_WWDTIF_Msk;
if (data->cb != NULL) {
data->cb(dev, 0);
}
}
}
static const struct wdt_driver_api wwdt_numaker_api = {
.setup = wwdt_numaker_setup,
.disable = wwdt_numaker_disable,
.install_timeout = wwdt_numaker_install_timeout,
.feed = wwdt_numaker_feed,
};
static int wwdt_numaker_init(const struct device *dev)
{
const struct wwdt_numaker_config *cfg = dev->config;
struct numaker_scc_subsys scc_subsys;
int err;
SYS_UnlockReg();
irq_disable(DT_INST_IRQN(0));
/* CLK controller */
memset(&scc_subsys, 0x00, sizeof(scc_subsys));
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
scc_subsys.pcc.clk_modidx = cfg->clk_modidx;
scc_subsys.pcc.clk_src = cfg->clk_src;
scc_subsys.pcc.clk_div = cfg->clk_div;
/* Equivalent to CLK_EnableModuleClock() */
err = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys);
if (err != 0) {
goto done;
}
/* Equivalent to CLK_SetModuleClock() */
err = clock_control_configure(cfg->clk_dev, (clock_control_subsys_t)&scc_subsys, NULL);
if (err != 0) {
goto done;
}
/* Enable NVIC */
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
wwdt_numaker_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
done:
SYS_LockReg();
return err;
}
/* Set config based on DTS */
static struct wwdt_numaker_config wwdt_numaker_cfg_inst = {
.wwdt_base = (WWDT_T *)DT_INST_REG_ADDR(0),
.clk_modidx = DT_INST_CLOCKS_CELL(0, clock_module_index),
.clk_src = DT_INST_CLOCKS_CELL(0, clock_source),
.clk_div = DT_INST_CLOCKS_CELL(0, clock_divider),
.clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(0))),
};
static struct wwdt_numaker_data wwdt_numaker_data_inst;
DEVICE_DT_INST_DEFINE(0, wwdt_numaker_init, NULL,
&wwdt_numaker_data_inst, &wwdt_numaker_cfg_inst,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&wwdt_numaker_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_wwdt_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,259 |
```c
/*
*
*/
#include <zephyr/sys/math_extras.h>
#include <nrfx_wdt.h>
#include <zephyr/drivers/watchdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_nrfx);
struct wdt_nrfx_data {
wdt_callback_t m_callbacks[NRF_WDT_CHANNEL_NUMBER];
uint32_t m_timeout;
uint8_t m_allocated_channels;
bool enabled;
};
struct wdt_nrfx_config {
nrfx_wdt_t wdt;
};
static int wdt_nrf_setup(const struct device *dev, uint8_t options)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
nrfx_wdt_config_t wdt_config = {
.reload_value = data->m_timeout
};
#if NRF_WDT_HAS_STOP
wdt_config.behaviour |= NRF_WDT_BEHAVIOUR_STOP_ENABLE_MASK;
#endif
if (!(options & WDT_OPT_PAUSE_IN_SLEEP)) {
wdt_config.behaviour |= NRF_WDT_BEHAVIOUR_RUN_SLEEP_MASK;
}
if (!(options & WDT_OPT_PAUSE_HALTED_BY_DBG)) {
wdt_config.behaviour |= NRF_WDT_BEHAVIOUR_RUN_HALT_MASK;
}
err_code = nrfx_wdt_reconfigure(&config->wdt, &wdt_config);
if (err_code != NRFX_SUCCESS) {
return -EBUSY;
}
nrfx_wdt_enable(&config->wdt);
data->enabled = true;
return 0;
}
static int wdt_nrf_disable(const struct device *dev)
{
#if NRFX_WDT_HAS_STOP
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
int channel_id;
err_code = nrfx_wdt_stop(&config->wdt);
if (err_code != NRFX_SUCCESS) {
/* This can only happen if wdt_nrf_setup() is not called first. */
return -EFAULT;
}
nrfx_wdt_channels_free(&config->wdt);
for (channel_id = 0; channel_id < data->m_allocated_channels; channel_id++) {
data->m_callbacks[channel_id] = NULL;
}
data->m_allocated_channels = 0;
data->enabled = false;
return 0;
#else
ARG_UNUSED(dev);
return -EPERM;
#endif
}
static int wdt_nrf_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
nrfx_err_t err_code;
nrfx_wdt_channel_id channel_id;
if (data->enabled) {
return -EBUSY;
}
if (cfg->flags != WDT_FLAG_RESET_SOC) {
return -ENOTSUP;
}
if (cfg->window.min != 0U) {
return -EINVAL;
}
if (data->m_allocated_channels == 0U) {
/* According to relevant Product Specifications, watchdogs
* in all nRF chips can use reload values (determining
* the timeout) from range 0xF-0xFFFFFFFF given in 32768 Hz
* clock ticks. This makes the allowed range of 0x1-0x07CFFFFF
* in milliseconds. Check if the provided value is within
* this range. */
if ((cfg->window.max == 0U) || (cfg->window.max > 0x07CFFFFF)) {
return -EINVAL;
}
/* Save timeout value from first registered watchdog channel. */
data->m_timeout = cfg->window.max;
} else if (cfg->window.max != data->m_timeout) {
return -EINVAL;
}
err_code = nrfx_wdt_channel_alloc(&config->wdt,
&channel_id);
if (err_code == NRFX_ERROR_NO_MEM) {
return -ENOMEM;
}
if (cfg->callback != NULL) {
data->m_callbacks[channel_id] = cfg->callback;
}
data->m_allocated_channels++;
return channel_id;
}
static int wdt_nrf_feed(const struct device *dev, int channel_id)
{
const struct wdt_nrfx_config *config = dev->config;
struct wdt_nrfx_data *data = dev->data;
if ((channel_id >= data->m_allocated_channels) || (channel_id < 0)) {
return -EINVAL;
}
if (!data->enabled) {
/* Watchdog is not running so does not need to be fed */
return -EAGAIN;
}
nrfx_wdt_channel_feed(&config->wdt,
(nrfx_wdt_channel_id)channel_id);
return 0;
}
static const struct wdt_driver_api wdt_nrfx_driver_api = {
.setup = wdt_nrf_setup,
.disable = wdt_nrf_disable,
.install_timeout = wdt_nrf_install_timeout,
.feed = wdt_nrf_feed,
};
static void wdt_event_handler(const struct device *dev, nrf_wdt_event_t event_type,
uint32_t requests, void *p_context)
{
(void)event_type;
(void)p_context;
struct wdt_nrfx_data *data = dev->data;
while (requests) {
uint8_t i = u32_count_trailing_zeros(requests);
if (data->m_callbacks[i]) {
data->m_callbacks[i](dev, i);
}
requests &= ~BIT(i);
}
}
#define WDT(idx) DT_NODELABEL(wdt##idx)
#define WDT_NRFX_WDT_DEVICE(idx) \
static void wdt_##idx##_event_handler(nrf_wdt_event_t event_type, \
uint32_t requests, \
void *p_context) \
{ \
wdt_event_handler(DEVICE_DT_GET(WDT(idx)), event_type, \
requests, p_context); \
} \
static int wdt_##idx##_init(const struct device *dev) \
{ \
const struct wdt_nrfx_config *config = dev->config; \
nrfx_err_t err_code; \
IRQ_CONNECT(DT_IRQN(WDT(idx)), DT_IRQ(WDT(idx), priority), \
nrfx_isr, nrfx_wdt_##idx##_irq_handler, 0); \
err_code = nrfx_wdt_init(&config->wdt, \
NULL, \
wdt_##idx##_event_handler, \
NULL); \
if (err_code != NRFX_SUCCESS) { \
return -EBUSY; \
} \
return 0; \
} \
static struct wdt_nrfx_data wdt_##idx##_data; \
static const struct wdt_nrfx_config wdt_##idx##z_config = { \
.wdt = NRFX_WDT_INSTANCE(idx), \
}; \
DEVICE_DT_DEFINE(WDT(idx), \
wdt_##idx##_init, \
NULL, \
&wdt_##idx##_data, \
&wdt_##idx##z_config, \
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&wdt_nrfx_driver_api)
#ifdef CONFIG_HAS_HW_NRF_WDT0
WDT_NRFX_WDT_DEVICE(0);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT1
WDT_NRFX_WDT_DEVICE(1);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT30
WDT_NRFX_WDT_DEVICE(30);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT31
WDT_NRFX_WDT_DEVICE(31);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT010
WDT_NRFX_WDT_DEVICE(010);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT011
WDT_NRFX_WDT_DEVICE(011);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT130
WDT_NRFX_WDT_DEVICE(130);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT131
WDT_NRFX_WDT_DEVICE(131);
#endif
#ifdef CONFIG_HAS_HW_NRF_WDT132
WDT_NRFX_WDT_DEVICE(132);
#endif
``` | /content/code_sandbox/drivers/watchdog/wdt_nrfx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,854 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_window_watchdog
#include <zephyr/drivers/watchdog.h>
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_wwdg.h>
#include <stm32_ll_system.h>
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clock.h>
#include "wdt_wwdg_stm32.h"
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_wwdg_stm32);
#define WWDG_INTERNAL_DIVIDER 4096U
#define WWDG_RESET_LIMIT WWDG_COUNTER_MIN
#define WWDG_COUNTER_MIN 0x40
#define WWDG_COUNTER_MAX 0x7f
#if defined WWDG_CFR_WDGTB_Pos
#define WWDG_PRESCALER_POS WWDG_CFR_WDGTB_Pos
#define WWDG_PRESCALER_MASK WWDG_CFR_WDGTB_Msk
#else
#error "WWDG CFR WDGTB position not defined for soc"
#endif
/*
* additionally to the internal divider, the clock is divided by a
* programmable prescaler.
*/
#if defined(LL_WWDG_PRESCALER_128)
#define WWDG_PRESCALER_EXPONENT_MAX 7 /* 2^7 = 128 */
#elif defined(LL_WWDG_PRESCALER_8)
#define WWDG_PRESCALER_EXPONENT_MAX 3 /* 2^3 = 8 */
#endif
/* The timeout of the WWDG in milliseconds is calculated by the below formula:
*
* t_WWDG = 1000 * ((counter & 0x3F) + 1) / f_WWDG (ms)
*
* where:
* - t_WWDG: WWDG timeout
* - counter: a value in [0x40, 0x7F] representing the cycles before timeout.
* Giving the counter a value below 0x40, will result in an
* immediate system reset. A reset is produced when the counter
* rolls over from 0x40 to 0x3F.
* - f_WWDG: the frequency of the WWDG clock. This can be calculated by the
* below formula:
* f_WWDG = f_PCLK / (4096 * prescaler) (Hz)
* where:
* - f_PCLK: the clock frequency of the system
* - 4096: the constant internal divider
* - prescaler: the programmable divider with valid values of 1, 2, 4 or 8,
* and for some series additionally 16, 32, 64 and 128
*
* The minimum timeout is calculated with:
* - counter = 0x40
* - prescaler = 1
* The maximum timeout is calculated with:
* - counter = 0x7F
* - prescaler = 8
*
* E.g. for f_PCLK = 2MHz
* t_WWDG_min = 1000 * ((0x40 & 0x3F) + 1) / (2000000 / (4096 * 1))
* = 2.048 ms
* t_WWDG_max = 1000 * ((0x7F & 0x3F) + 1) / (2000000 / (4096 * 8))
* = 1048.576 ms
*/
#define ABS_DIFF_UINT(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
#define WWDG_TIMEOUT_ERROR_MARGIN(__TIMEOUT__) (__TIMEOUT__ / 10)
#define IS_WWDG_TIMEOUT(__TIMEOUT_GOLDEN__, __TIMEOUT__) \
(__TIMEOUT__ - __TIMEOUT_GOLDEN__) < \
WWDG_TIMEOUT_ERROR_MARGIN(__TIMEOUT_GOLDEN__)
static void wwdg_stm32_irq_config(const struct device *dev);
static uint32_t wwdg_stm32_get_pclk(const struct device *dev)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
uint32_t pclk_rate;
if (clock_control_get_rate(clk, (clock_control_subsys_t) &cfg->pclken,
&pclk_rate) < 0) {
LOG_ERR("Failed call clock_control_get_rate");
return -EIO;
}
return pclk_rate;
}
/**
* @brief Calculates the timeout in microseconds.
*
* @param dev Pointer to device structure.
* @param prescaler_exp The prescaler exponent value(Base 2).
* @param counter The counter value.
* @return The timeout calculated in microseconds.
*/
static uint32_t wwdg_stm32_get_timeout(const struct device *dev,
uint32_t prescaler_exp,
uint32_t counter)
{
uint32_t divider = WWDG_INTERNAL_DIVIDER * (1 << prescaler_exp);
float f_wwdg = (float)wwdg_stm32_get_pclk(dev) / divider;
return USEC_PER_SEC * (((counter & 0x3F) + 1) / f_wwdg);
}
/**
* @brief Calculates prescaler & counter values.
*
* @param dev Pointer to device structure.
* @param timeout Timeout value in microseconds.
* @param prescaler_exp Pointer to prescaler exponent value(Base 2).
* @param counter Pointer to counter value.
*/
static void wwdg_stm32_convert_timeout(const struct device *dev,
uint32_t timeout,
uint32_t *prescaler_exp,
uint32_t *counter)
{
uint32_t clock_freq = wwdg_stm32_get_pclk(dev);
/* Convert timeout to seconds. */
float timeout_s = (float)timeout / USEC_PER_SEC;
float wwdg_freq;
*prescaler_exp = 0U;
*counter = 0;
for (*prescaler_exp = 0; *prescaler_exp <= WWDG_PRESCALER_EXPONENT_MAX;
(*prescaler_exp)++) {
wwdg_freq = ((float)clock_freq) / WWDG_INTERNAL_DIVIDER
/ (1 << *prescaler_exp);
/* +1 to ceil the result, which may lose from truncation */
*counter = (uint32_t)(timeout_s * wwdg_freq + 1) - 1;
*counter += WWDG_RESET_LIMIT;
if (*counter <= WWDG_COUNTER_MAX) {
return;
}
}
/* timeout longer than wwdg can provide, set to max possible value */
*counter = WWDG_COUNTER_MAX;
*prescaler_exp = WWDG_PRESCALER_EXPONENT_MAX;
}
static int wwdg_stm32_setup(const struct device *dev, uint8_t options)
{
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
/* Deactivate running when debugger is attached. */
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
#if defined(CONFIG_SOC_SERIES_STM32F0X)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#endif
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP);
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP);
#else
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP);
#endif /* CONFIG_SOC_SERIES_STM32H7X */
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
/* Ensure that Early Wakeup Interrupt Flag is cleared */
LL_WWDG_ClearFlag_EWKUP(wwdg);
/* Enable the WWDG */
LL_WWDG_Enable(wwdg);
return 0;
}
static int wwdg_stm32_disable(const struct device *dev)
{
/* watchdog cannot be stopped once started unless SOC gets a reset */
ARG_UNUSED(dev);
return -EPERM;
}
static int wwdg_stm32_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
uint32_t timeout = config->window.max * USEC_PER_MSEC;
uint32_t calculated_timeout;
uint32_t prescaler_exp = 0U;
uint32_t counter = 0U;
if (config->callback != NULL) {
data->callback = config->callback;
}
wwdg_stm32_convert_timeout(dev, timeout, &prescaler_exp, &counter);
calculated_timeout = wwdg_stm32_get_timeout(dev, prescaler_exp, counter);
LOG_DBG("prescaler: %d", (1 << prescaler_exp));
LOG_DBG("Desired WDT: %d us", timeout);
LOG_DBG("Set WDT: %d us", calculated_timeout);
if (!(IS_WWDG_COUNTER(counter) &&
IS_WWDG_TIMEOUT(timeout, calculated_timeout))) {
/* One of the parameters provided is invalid */
return -EINVAL;
}
data->counter = counter;
/* Configure WWDG */
/* Set the programmable prescaler */
LL_WWDG_SetPrescaler(wwdg,
(prescaler_exp << WWDG_PRESCALER_POS) & WWDG_PRESCALER_MASK);
/* Set window the same as the counter to be able to feed the WWDG almost
* immediately
*/
LL_WWDG_SetWindow(wwdg, counter);
LL_WWDG_SetCounter(wwdg, counter);
return 0;
}
static int wwdg_stm32_feed(const struct device *dev, int channel_id)
{
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
ARG_UNUSED(channel_id);
LL_WWDG_SetCounter(wwdg, data->counter);
return 0;
}
void wwdg_stm32_isr(const struct device *dev)
{
struct wwdg_stm32_data *data = WWDG_STM32_DATA(dev);
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
if (LL_WWDG_IsEnabledIT_EWKUP(wwdg)) {
if (LL_WWDG_IsActiveFlag_EWKUP(wwdg)) {
LL_WWDG_ClearFlag_EWKUP(wwdg);
data->callback(dev, 0);
}
}
}
static const struct wdt_driver_api wwdg_stm32_api = {
.setup = wwdg_stm32_setup,
.disable = wwdg_stm32_disable,
.install_timeout = wwdg_stm32_install_timeout,
.feed = wwdg_stm32_feed,
};
static int wwdg_stm32_init(const struct device *dev)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
wwdg_stm32_irq_config(dev);
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
return clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken);
}
static struct wwdg_stm32_data wwdg_stm32_dev_data = {
.counter = WWDG_RESET_LIMIT,
.callback = NULL
};
static struct wwdg_stm32_config wwdg_stm32_dev_config = {
.pclken = {
.enr = DT_INST_CLOCKS_CELL(0, bits),
.bus = DT_INST_CLOCKS_CELL(0, bus)
},
.Instance = (WWDG_TypeDef *)DT_INST_REG_ADDR(0),
};
DEVICE_DT_INST_DEFINE(0, wwdg_stm32_init, NULL,
&wwdg_stm32_dev_data, &wwdg_stm32_dev_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&wwdg_stm32_api);
static void wwdg_stm32_irq_config(const struct device *dev)
{
WWDG_TypeDef *wwdg = WWDG_STM32_STRUCT(dev);
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
wwdg_stm32_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
LL_WWDG_EnableIT_EWKUP(wwdg);
}
``` | /content/code_sandbox/drivers/watchdog/wdt_wwdg_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,933 |
```unknown
# Xilinx watchdog configuration
config WDT_XILINX_AXI
bool "Xilinx AXI Timebase WDT driver"
default y
depends on DT_HAS_XLNX_XPS_TIMEBASE_WDT_1_00_A_ENABLED
help
Enable the Xilinx AXI Timebase WDT driver.
if WDT_XILINX_AXI
config WDT_XILINX_AXI_HWINFO_API
bool "Expose HWINFO API in Xilinx AXI Timebase WDT driver"
default y
select HWINFO
help
Controls whether the Xilinx AXI Timebase WDT driver exposes a HWINFO
API which allows determining whether the WDT initiated the last
system reset. This may need to be disabled if using a device or SoC
which already implements this API.
endif # WDT_XILINX_AXI
``` | /content/code_sandbox/drivers/watchdog/Kconfig.xlnx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 184 |
```unknown
# Watchdog configuration options
config WDT_MCUX_IMX_WDOG
bool "MCUX IMX WDOG driver"
default y
depends on DT_HAS_NXP_IMX_WDOG_ENABLED
select PINCTRL
help
Enable the mcux imx wdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.mcux_imx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_swt
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(swt_nxp_s32);
/* Software Watchdog Timer (SWT) register definitions */
/* Control */
#define SWT_CR 0x0
#define SWT_CR_WEN_MASK BIT(0)
#define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v))
#define SWT_CR_FRZ_MASK BIT(1)
#define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v))
#define SWT_CR_STP_MASK BIT(2)
#define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v))
#define SWT_CR_SLK_MASK BIT(4)
#define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v))
#define SWT_CR_HLK_MASK BIT(5)
#define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v))
#define SWT_CR_ITR_MASK BIT(6)
#define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v))
#define SWT_CR_WND_MASK BIT(7)
#define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v))
#define SWT_CR_RIA_MASK BIT(8)
#define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v))
#define SWT_CR_SMD_MASK GENMASK(10, 9)
#define SWT_CR_SMD(v) FIELD_PREP(SWT_CR_SMD_MASK, (v))
#define SWT_CR_MAP_MASK GENMASK(31, 24)
#define SWT_CR_MAP(v) FIELD_PREP(SWT_CR_MAP_MASK, (v))
/* Interrupt */
#define SWT_IR 0x4
#define SWT_IR_TIF_MASK BIT(0)
#define SWT_IR_TIF(v) FIELD_PREP(SWT_IR_TIF_MASK, (v))
/* Timeout */
#define SWT_TO 0x8
#define SWT_TO_WTO_MASK GENMASK(31, 0)
#define SWT_TO_WTO(v) FIELD_PREP(SWT_TO_WTO_MASK, (v))
/* Window */
#define SWT_WN 0xc
#define SWT_WN_WST_MASK GENMASK(31, 0)
#define SWT_WN_WST(v) FIELD_PREP(SWT_WN_WST_MASK, (v))
/* Service */
#define SWT_SR 0x10
#define SWT_SR_WSC_MASK GENMASK(15, 0)
#define SWT_SR_WSC(v) FIELD_PREP(SWT_SR_WSC_MASK, (v))
/* Counter Output */
#define SWT_CO 0x14
#define SWT_CO_CNT_MASK GENMASK(31, 0)
#define SWT_CO_CNT(v) FIELD_PREP(SWT_CO_CNT_MASK, (v))
/* Service Key */
#define SWT_SK 0x18
#define SWT_SK_SK_MASK GENMASK(15, 0)
#define SWT_SK_SK(v) FIELD_PREP(SWT_SK_SK_MASK, (v))
/* Event Request */
#define SWT_RRR 0x1c
#define SWT_RRR_RRF_MASK BIT(0)
#define SWT_RRR_RRF(v) FIELD_PREP(SWT_RRR_RRF_MASK, (v))
#define SWT_TO_WTO_MIN 0x100
#define SWT_SR_WSC_UNLOCK_KEY1 0xC520U
#define SWT_SR_WSC_UNLOCK_KEY2 0xD928U
#define SWT_SR_WSC_SERVICE_KEY1 0xA602U
#define SWT_SR_WSC_SERVICE_KEY2 0xB480U
#define SWT_SOFT_LOCK_TIMEOUT_US 3000
/* Handy accessors */
#define REG_READ(r) sys_read32(config->base + (r))
#define REG_WRITE(r, v) sys_write32((v), config->base + (r))
enum swt_service_mode {
SWT_FIXED_SERVICE = 0,
SWT_KEYED_SERVICE = 1,
};
enum swt_lock_mode {
SWT_UNLOCKED = 0,
SWT_SOFT_LOCK = 1,
SWT_HARD_LOCK = 2,
};
struct swt_nxp_s32_timeout {
uint32_t period;
uint32_t window_start;
bool window_mode;
};
struct swt_nxp_s32_config {
mem_addr_t base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
uint8_t master_access_mask;
enum swt_lock_mode lock_mode;
enum swt_service_mode service_mode;
uint16_t initial_key;
bool reset_on_invalid_access;
};
struct swt_nxp_s32_data {
wdt_callback_t callback;
bool timeout_valid;
struct swt_nxp_s32_timeout timeout;
};
static void swt_lock(const struct swt_nxp_s32_config *config)
{
switch (config->lock_mode) {
case SWT_HARD_LOCK:
REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_HLK(1U));
break;
case SWT_SOFT_LOCK:
REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U));
break;
case SWT_UNLOCKED:
__fallthrough;
default:
break;
}
}
static int swt_unlock(const struct swt_nxp_s32_config *config)
{
int err = 0;
if (FIELD_GET(SWT_CR_HLK_MASK, REG_READ(SWT_CR)) != 0U) {
LOG_ERR("Watchdog hard-locked");
err = -EFAULT;
} else if (FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR)) != 0U) {
REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY1));
REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY2));
if (!WAIT_FOR(FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR) != 0),
SWT_SOFT_LOCK_TIMEOUT_US, NULL)) {
LOG_ERR("Timedout while trying to unlock");
err = -ETIMEDOUT;
/* make sure is locked again before we leave */
REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U));
}
}
return err;
}
static inline uint16_t swt_gen_service_key(const struct swt_nxp_s32_config *config)
{
/* Calculated pseudo-random key according to Service Key Generation chapter in RM */
return (uint16_t)((FIELD_GET(SWT_SK_SK_MASK, REG_READ(SWT_SK)) * 17U) + 3U);
}
static int swt_nxp_s32_setup(const struct device *dev, uint8_t options)
{
const struct swt_nxp_s32_config *config = dev->config;
struct swt_nxp_s32_data *data = dev->data;
int err;
uint32_t reg_val;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
err = swt_unlock(config);
if (err) {
return err;
}
reg_val = REG_READ(SWT_CR);
reg_val &= ~(SWT_CR_WND_MASK | SWT_CR_STP_MASK | SWT_CR_FRZ_MASK | SWT_CR_ITR_MASK);
REG_WRITE(SWT_CR, reg_val |
SWT_CR_WND(data->timeout.window_mode ? 1U : 0U) |
SWT_CR_ITR(data->callback ? 1U : 0U) |
SWT_CR_STP((options & WDT_OPT_PAUSE_IN_SLEEP) ? 1U : 0U) |
SWT_CR_FRZ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ? 1U : 0U));
REG_WRITE(SWT_IR, SWT_IR_TIF(1U));
REG_WRITE(SWT_TO, SWT_TO_WTO(data->timeout.period));
REG_WRITE(SWT_WN, SWT_WN_WST(data->timeout.window_start));
if (config->service_mode == SWT_KEYED_SERVICE) {
REG_WRITE(SWT_SK, SWT_SK_SK(config->initial_key));
}
REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_WEN(1U));
swt_lock(config);
return 0;
}
static int swt_nxp_s32_disable(const struct device *dev)
{
const struct swt_nxp_s32_config *config = dev->config;
struct swt_nxp_s32_data *data = dev->data;
int err;
if (!FIELD_GET(SWT_CR_WEN_MASK, REG_READ(SWT_CR))) {
LOG_ERR("Watchdog is not enabled");
return -EFAULT;
}
err = swt_unlock(config);
if (err) {
return err;
}
/* Disable the watchdog and clear interrupt flags */
REG_WRITE(SWT_CR, REG_READ(SWT_CR) & ~SWT_CR_WEN_MASK);
REG_WRITE(SWT_IR, SWT_IR_TIF(1U));
swt_lock(config);
data->timeout_valid = false;
return 0;
}
static int swt_nxp_s32_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct swt_nxp_s32_config *config = dev->config;
struct swt_nxp_s32_data *data = dev->data;
bool window_mode = false;
uint32_t window = 0;
uint32_t period;
uint32_t clock_rate;
int err;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
if (err) {
LOG_ERR("Failed to get module clock frequency");
return err;
}
period = clock_rate / 1000U * cfg->window.max;
if (cfg->window.min) {
window_mode = true;
window = clock_rate / 1000U * (cfg->window.max - cfg->window.min);
}
if ((period < SWT_TO_WTO_MIN) || (period < window)) {
LOG_ERR("Invalid timeout");
return -EINVAL;
}
data->timeout.period = period;
data->timeout.window_start = window;
data->timeout.window_mode = window_mode;
data->callback = cfg->callback;
data->timeout_valid = true;
LOG_DBG("Installed timeout: period=%d, window=%d (%s)",
period, window, window_mode ? "enabled" : "disabled");
return 0;
}
static int swt_nxp_s32_feed(const struct device *dev, int channel)
{
const struct swt_nxp_s32_config *config = dev->config;
bool match_unlock_seq = false;
int err = 0;
ARG_UNUSED(channel);
switch (config->service_mode) {
case SWT_FIXED_SERVICE:
REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_SERVICE_KEY1));
REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_SERVICE_KEY2));
break;
case SWT_KEYED_SERVICE:
/*
* If one or more service routines use both unlock keys in the proper order,
* the watchdog unlocks the soft lock
*/
if (swt_gen_service_key(config) == SWT_SR_WSC_UNLOCK_KEY1) {
match_unlock_seq = true;
}
REG_WRITE(SWT_SR, SWT_SR_WSC(swt_gen_service_key(config)));
if (swt_gen_service_key(config) == SWT_SR_WSC_UNLOCK_KEY1) {
match_unlock_seq = true;
}
REG_WRITE(SWT_SR, SWT_SR_WSC(swt_gen_service_key(config)));
if (match_unlock_seq && (config->lock_mode == SWT_SOFT_LOCK)) {
/*
* Service key generated matched the unlock sequence, complete the
* unlock sequence and reinitiate the soft lock
*/
REG_WRITE(SWT_SR, SWT_SR_WSC(SWT_SR_WSC_UNLOCK_KEY2));
swt_lock(config);
}
break;
default:
LOG_ERR("Invalid service mode");
err = -EINVAL;
break;
}
LOG_DBG("Fed the watchdog");
return err;
}
static void swt_nxp_s32_isr(const struct device *dev)
{
const struct swt_nxp_s32_config *config = dev->config;
struct swt_nxp_s32_data *data = dev->data;
uint32_t reg_val;
if (FIELD_GET(SWT_IR_TIF_MASK, REG_READ(SWT_IR)) &&
FIELD_GET(SWT_CR_ITR_MASK, REG_READ(SWT_CR))) {
/* Clear interrupt flag */
reg_val = REG_READ(SWT_IR);
reg_val &= SWT_IR_TIF_MASK;
REG_WRITE(SWT_IR, reg_val);
if (data->callback) {
/* SWT only has one channel */
data->callback(dev, 0U);
}
}
}
static int swt_nxp_s32_init(const struct device *dev)
{
const struct swt_nxp_s32_config *config = dev->config;
int err;
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
err = clock_control_on(config->clock_dev, config->clock_subsys);
if (err) {
return err;
}
REG_WRITE(SWT_CR,
SWT_CR_MAP(config->master_access_mask) |
SWT_CR_RIA(config->reset_on_invalid_access) |
SWT_CR_SMD(config->service_mode));
return 0;
}
static const struct wdt_driver_api swt_nxp_s32_driver_api = {
.setup = swt_nxp_s32_setup,
.disable = swt_nxp_s32_disable,
.install_timeout = swt_nxp_s32_install_timeout,
.feed = swt_nxp_s32_feed,
};
#define SWT_NXP_S32_DEVICE_INIT(n) \
static struct swt_nxp_s32_data swt_nxp_s32_data_##n; \
\
static const struct swt_nxp_s32_config swt_nxp_s32_config_##n = { \
.base = DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
.master_access_mask = DT_INST_PROP(n, master_access_mask), \
.reset_on_invalid_access = DT_INST_PROP(n, reset_on_invalid_access), \
.service_mode = DT_INST_ENUM_IDX(n, service_mode), \
.initial_key = (uint16_t)DT_INST_PROP(n, initial_key), \
.lock_mode = DT_INST_ENUM_IDX(n, lock_mode), \
}; \
\
static int swt_nxp_s32_##n##_init(const struct device *dev) \
{ \
int err; \
\
err = swt_nxp_s32_init(dev); \
if (err) { \
return err; \
} \
\
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
swt_nxp_s32_isr, DEVICE_DT_INST_GET(n), \
COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, flags), \
(DT_INST_IRQ(n, flags)), (0))); \
irq_enable(DT_INST_IRQN(n)); \
\
return 0; \
} \
\
DEVICE_DT_INST_DEFINE(n, \
swt_nxp_s32_##n##_init, \
NULL, \
&swt_nxp_s32_data_##n, \
&swt_nxp_s32_config_##n, \
POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&swt_nxp_s32_driver_api);
DT_INST_FOREACH_STATUS_OKAY(SWT_NXP_S32_DEVICE_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,500 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm6001_wdt
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/toolchain.h>
/* nPM6001 Watchdog related registers */
#define NPM6001_WDARMEDVALUE 0x54U
#define NPM6001_WDARMEDSTROBE 0x55U
#define NPM6001_WDTRIGGERVALUE0 0x56U
#define NPM6001_WDTRIGGERVALUE1 0x57U
#define NPM6001_WDTRIGGERVALUE2 0x58U
#define NPM6001_WDDATASTROBE 0x5DU
#define NPM6001_WDPWRUPVALUE 0x5EU
#define NPM6001_WDPWRUPSTROBE 0x5FU
#define NPM6001_WDKICK 0x60U
#define NPM6001_WDREQPOWERDOWN 0x62U
/* nPM6001 WDTRIGGERVALUEx ms/LSB, min/max values */
#define NPM6001_WDTRIGGERVALUE_MS_LSB 4000U
#define NPM6001_WDTRIGGERVALUE_MIN 0x2U
#define NPM6001_WDTRIGGERVALUE_MAX 0xFFFFFFU
/* nPM6001 WDPWRUPVALUE fields */
#define NPM6001_WDPWRUPVALUE_OSC_ENABLE BIT(0)
#define NPM6001_WDPWRUPVALUE_COUNTER_ENABLE BIT(1)
#define NPM6001_WDPWRUPVALUE_LS_ENABLE BIT(2)
struct wdt_npm6001_config {
struct i2c_dt_spec bus;
};
static int wdt_npm6001_setup(const struct device *dev, uint8_t options)
{
ARG_UNUSED(dev);
ARG_UNUSED(options);
return 0;
}
static int wdt_npm6001_disable(const struct device *dev)
{
const struct wdt_npm6001_config *config = dev->config;
uint8_t buf[4] = {NPM6001_WDARMEDVALUE, 1U, NPM6001_WDARMEDSTROBE, 1U};
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static int wdt_npm6001_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *timeout)
{
const struct wdt_npm6001_config *config = dev->config;
uint32_t window;
uint8_t buf[2];
int ret;
if (timeout->window.min != 0U) {
return -EINVAL;
}
/* round-up timeout, e.g. 5s -> 8s */
window = (((timeout->window.max + NPM6001_WDTRIGGERVALUE_MS_LSB - 1U) /
NPM6001_WDTRIGGERVALUE_MS_LSB) +
1U);
if ((window < NPM6001_WDTRIGGERVALUE_MIN) ||
(window > NPM6001_WDTRIGGERVALUE_MAX)) {
return -EINVAL;
}
/* enable OSC/COUNTER/LS */
buf[0] = NPM6001_WDPWRUPVALUE;
buf[1] = NPM6001_WDPWRUPVALUE_OSC_ENABLE |
NPM6001_WDPWRUPVALUE_COUNTER_ENABLE |
NPM6001_WDPWRUPVALUE_LS_ENABLE;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDPWRUPSTROBE;
buf[1] = 1U;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
/* write trigger value */
buf[0] = NPM6001_WDTRIGGERVALUE0;
buf[1] = (uint8_t)window;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDTRIGGERVALUE1;
buf[1] = (uint8_t)(window >> 8U);
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDTRIGGERVALUE2;
buf[1] = (uint8_t)(window >> 16U);
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDDATASTROBE;
buf[1] = 1U;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
/* arm watchdog & kick */
buf[0] = NPM6001_WDARMEDVALUE;
buf[1] = 1U;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDARMEDSTROBE;
buf[1] = 1U;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
buf[0] = NPM6001_WDKICK;
buf[1] = 1U;
ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
if (ret < 0) {
return ret;
}
return 0;
}
static int wdt_npm6001_feed(const struct device *dev, int channel_id)
{
const struct wdt_npm6001_config *config = dev->config;
uint8_t buf[2] = {NPM6001_WDKICK, 1U};
ARG_UNUSED(channel_id);
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static const struct wdt_driver_api wdt_npm6001_api = {
.setup = wdt_npm6001_setup,
.disable = wdt_npm6001_disable,
.install_timeout = wdt_npm6001_install_timeout,
.feed = wdt_npm6001_feed,
};
static int wdt_npm6001_init(const struct device *dev)
{
const struct wdt_npm6001_config *config = dev->config;
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
return 0;
}
#define WDT_NPM6001_DEFINE(n) \
static const struct wdt_npm6001_config wdt_npm6001_config##n = { \
.bus = I2C_DT_SPEC_GET(DT_INST_PARENT(n)), \
}; \
\
DEVICE_DT_INST_DEFINE(n, &wdt_npm6001_init, NULL, NULL, \
&wdt_npm6001_config##n, POST_KERNEL, \
CONFIG_WDT_NPM6001_INIT_PRIORITY, \
&wdt_npm6001_api);
DT_INST_FOREACH_STATUS_OKAY(WDT_NPM6001_DEFINE)
``` | /content/code_sandbox/drivers/watchdog/wdt_npm6001.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,614 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_watchdog
/**
* @file
* @brief Nuvoton NPCX watchdog modules driver
*
* This file contains the drivers of NPCX Watchdog module that generates the
* clocks and interrupts (T0 Timer) used for its callback functions in the
* system. It also provides watchdog reset signal generation in response to a
* failure detection. Please refer the block diagram for more detail.
*
* +---------------------+ +-----------------+
* LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
* (32kHz) | (TWCP 1:32) | | | (TWDT0) | Event
* +---------------------+ | +-----------------+
* +---------------------------------+
* |
* | +-------------------+ +-----------------+
* +--->| Watchdog Prescale |--->| 8-Bit Watchdog |-----> Watchdog Event/Reset
* | (WDCP 1:32) | | Counter (WDCNT) | after n clocks
* +-------------------+ +-----------------+
*
*/
#include "soc_miwu.h"
#include <assert.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include "soc_dbg.h"
LOG_MODULE_REGISTER(wdt_npcx, CONFIG_WDT_LOG_LEVEL);
/* Watchdog operating frequency is fixed to LFCLK (32.768) kHz */
#define NPCX_WDT_CLK LFCLK
/*
* Maximum watchdog window time. Keep the timer and watchdog clock prescaler
* (TWCP) to 0x5. Since the watchdog counter is 8-bits, maximum time supported
* by npcx watchdog is 256 * (32 * 32768) / 32768 = 8192 sec.
* The maximum time supported of T0OUT is 65536 * 32 / 32768 = 64 sec.
* Thus, the maximum time of watchdog set here is 64 sec.
*/
#define NPCX_WDT_MAX_WND_TIME 64000UL
/*
* Minimum watchdog window time. Ensure we have waited at least 3 watchdog
* clocks since touching WD timer. 3 / (32768 / 1024) HZ = 93.75ms
*/
#define NPCX_WDT_MIN_WND_TIME 100UL
/* Timeout for reloading and restarting Timer 0. (Unit:ms) */
#define NPCX_T0CSR_RST_TIMEOUT 2
/* Timeout for stopping watchdog. (Unit:ms) */
#define NPCX_WATCHDOG_STOP_TIMEOUT 1
/* Device config */
struct wdt_npcx_config {
/* wdt controller base address */
uintptr_t base;
/* t0 timer wake-up input source configuration */
const struct npcx_wui t0out;
};
/* Driver data */
struct wdt_npcx_data {
/* Timestamp of touching watchdog last time */
int64_t last_watchdog_touch;
/* Timeout callback used to handle watchdog event */
wdt_callback_t cb;
/* Watchdog feed timeout in milliseconds */
uint32_t timeout;
/* Indicate whether a watchdog timeout is installed */
bool timeout_installed;
};
struct miwu_callback miwu_cb;
/* Driver convenience defines */
#define HAL_INSTANCE(dev) ((struct twd_reg *)((const struct wdt_npcx_config *)(dev)->config)->base)
/* WDT local inline functions */
static inline int wdt_t0out_reload(const struct device *dev)
{
struct twd_reg *const inst = HAL_INSTANCE(dev);
uint64_t st;
/* Reload and restart T0 timer */
inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
BIT(NPCX_T0CSR_RST);
/* Wait for timer is loaded and restart */
st = k_uptime_get();
while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
if (k_uptime_get() - st > NPCX_T0CSR_RST_TIMEOUT) {
/* RST bit is still set? */
if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
LOG_ERR("Timeout: reload T0 timer!");
return -ETIMEDOUT;
}
}
}
return 0;
}
static inline int wdt_wait_stopped(const struct device *dev)
{
struct twd_reg *const inst = HAL_INSTANCE(dev);
uint64_t st;
st = k_uptime_get();
/* If watchdog is still running? */
while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
if (k_uptime_get() - st > NPCX_WATCHDOG_STOP_TIMEOUT) {
/* WD_RUN bit is still set? */
if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
LOG_ERR("Timeout: stop watchdog timer!");
return -ETIMEDOUT;
}
}
}
return 0;
}
/* WDT local functions */
static void wdt_t0out_isr(const struct device *dev, struct npcx_wui *wui)
{
struct wdt_npcx_data *const data = dev->data;
ARG_UNUSED(wui);
LOG_DBG("WDT reset will issue after %d delay cycle! WUI(%d %d %d)",
CONFIG_WDT_NPCX_WARNING_LEADING_TIME_MS, wui->table, wui->group, wui->bit);
/* Handle watchdog event here. */
if (data->cb) {
data->cb(dev, 0);
}
}
static void wdt_config_t0out_interrupt(const struct device *dev)
{
const struct wdt_npcx_config *const config = dev->config;
/* Initialize a miwu device input and its callback function */
npcx_miwu_init_dev_callback(&miwu_cb, &config->t0out, wdt_t0out_isr,
dev);
npcx_miwu_manage_callback(&miwu_cb, true);
/*
* Configure the T0 wake-up event triggered from a rising edge
* on T0OUT signal.
*/
npcx_miwu_interrupt_configure(&config->t0out,
NPCX_MIWU_MODE_EDGE, NPCX_MIWU_TRIG_HIGH);
}
/* WDT api functions */
static int wdt_npcx_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_npcx_data *const data = dev->data;
struct twd_reg *const inst = HAL_INSTANCE(dev);
/* If watchdog is already running */
if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
return -EBUSY;
}
/* No window watchdog support */
if (cfg->window.min != 0) {
data->timeout_installed = false;
return -EINVAL;
}
/*
* Since the watchdog counter in npcx series is 8-bits, maximum time
* supported by it is 256 * (32 * 32) / 32768 = 8 sec. This makes the
* allowed range of 1-8000 in milliseconds. Check if the provided value
* is within this range.
*/
if (cfg->window.max > NPCX_WDT_MAX_WND_TIME || cfg->window.max == 0) {
data->timeout_installed = false;
return -EINVAL;
}
/* Save watchdog timeout */
data->timeout = cfg->window.max;
/* Install user timeout isr */
data->cb = cfg->callback;
data->timeout_installed = true;
return 0;
}
static int wdt_npcx_setup(const struct device *dev, uint8_t options)
{
struct twd_reg *const inst = HAL_INSTANCE(dev);
const struct wdt_npcx_config *const config = dev->config;
struct wdt_npcx_data *const data = dev->data;
uint32_t wd_cnt, pre_scal;
uint8_t wdcp;
int rv;
/* Disable irq of t0-out expired event first */
npcx_miwu_irq_disable(&config->t0out);
if (!data->timeout_installed) {
LOG_ERR("No valid WDT timeout installed");
return -EINVAL;
}
if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
LOG_ERR("WDT timer is busy");
return -EBUSY;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
return -ENOTSUP;
}
/* Stall the WDT counter when halted by debugger */
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) != 0) {
npcx_dbg_freeze_enable(true);
} else {
npcx_dbg_freeze_enable(false);
}
/*
* One clock period of T0 timer is 32/32.768 KHz = 0.976 ms.
* Then the counter value is timeout/0.976 - 1.
*/
inst->TWDT0 = MAX(DIV_ROUND_UP(data->timeout * NPCX_WDT_CLK,
32 * 1000) - 1, 1);
/* Configure 8-bit watchdog counter
* Change the prescaler of watchdog clock for larger timeout
*/
wd_cnt = DIV_ROUND_UP((data->timeout + CONFIG_WDT_NPCX_WARNING_LEADING_TIME_MS) *
NPCX_WDT_CLK,
32 * 1000);
pre_scal = DIV_ROUND_UP(wd_cnt, 255);
/*
* Find the smallest power of 2 greater than or equal to the
* prescaler
*/
wdcp = LOG2(pre_scal - 1) + 1;
pre_scal = 1 << wdcp;
inst->WDCP = wdcp;
inst->WDCNT = wd_cnt / pre_scal;
LOG_DBG("WDT setup: TWDT0, WDCNT are %d, %d", inst->TWDT0, inst->WDCNT);
/* Reload and restart T0 timer */
rv = wdt_t0out_reload(dev);
/* Configure t0 timer interrupt and its isr. */
wdt_config_t0out_interrupt(dev);
/* Enable irq of t0-out expired event */
npcx_miwu_irq_enable(&config->t0out);
return rv;
}
static int wdt_npcx_disable(const struct device *dev)
{
const struct wdt_npcx_config *const config = dev->config;
struct wdt_npcx_data *const data = dev->data;
struct twd_reg *const inst = HAL_INSTANCE(dev);
uint16_t min_wnd_t;
/*
* Ensure we have waited at least 3 watchdog ticks before
* stopping watchdog
*/
min_wnd_t = DIV_ROUND_UP(3 * NPCX_WDT_CLK, 32 * (1 << inst->WDCP));
while (k_uptime_get() - data->last_watchdog_touch < min_wnd_t) {
continue;
}
/*
* Stop and unlock watchdog by writing 87h, 61h and 63h
* sequence bytes to WDSDM register
*/
inst->WDSDM = 0x87;
inst->WDSDM = 0x61;
inst->WDSDM = 0x63;
/* Disable irq of t0-out expired event and mark it uninstalled */
npcx_miwu_irq_disable(&config->t0out);
data->timeout_installed = false;
/* Wait until watchdog is stopped. */
return wdt_wait_stopped(dev);
}
static int wdt_npcx_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(channel_id);
struct wdt_npcx_data *const data = dev->data;
struct twd_reg *const inst = HAL_INSTANCE(dev);
/* Feed watchdog by writing 5Ch to WDSDM */
inst->WDSDM = 0x5C;
data->last_watchdog_touch = k_uptime_get();
/* Reload and restart T0 timer */
return wdt_t0out_reload(dev);
}
/* WDT driver registration */
static const struct wdt_driver_api wdt_npcx_driver_api = {
.setup = wdt_npcx_setup,
.disable = wdt_npcx_disable,
.install_timeout = wdt_npcx_install_timeout,
.feed = wdt_npcx_feed,
};
static int wdt_npcx_init(const struct device *dev)
{
struct twd_reg *const inst = HAL_INSTANCE(dev);
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
wdt_npcx_disable(dev);
#endif
/*
* TWCFG (Timer Watchdog Configuration) setting
* [7:6]- Reserved = 0
* [5] - WDSDME = 1: Feed watchdog by writing 5Ch to WDSDM
* [4] - WDCT0I = 1: Select T0IN as watchdog prescaler clock
* [3] - LWDCNT = 0: Don't lock WDCNT register
* [2] - LTWDT0 = 0: Don't lock TWDT0 register
* [1] - LTWCP = 0: Don't lock TWCP register
* [0] - LTWCFG = 0: Don't lock TWCFG register
*/
inst->TWCFG = BIT(NPCX_TWCFG_WDSDME) | BIT(NPCX_TWCFG_WDCT0I);
/* Disable early touch functionality */
inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
BIT(NPCX_T0CSR_TESDIS);
/*
* Plan clock frequency of T0 timer and watchdog timer as below:
* - T0 Timer freq is LFCLK/32 Hz
* - Watchdog freq is T0CLK/32 Hz (ie. LFCLK/1024 Hz)
*/
inst->WDCP = 0x05; /* Prescaler is 32 in Watchdog Timer */
inst->TWCP = 0x05; /* Prescaler is 32 in T0 Timer */
return 0;
}
static const struct wdt_npcx_config wdt_npcx_cfg_0 = {
.base = DT_INST_REG_ADDR(0),
.t0out = NPCX_DT_WUI_ITEM_BY_NAME(0, t0_out)
};
static struct wdt_npcx_data wdt_npcx_data_0;
DEVICE_DT_INST_DEFINE(0, wdt_npcx_init, NULL,
&wdt_npcx_data_0, &wdt_npcx_cfg_0,
PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&wdt_npcx_driver_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_npcx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,243 |
```unknown
# Smartbond watchdog driver config
config WDT_SMARTBOND
bool "Watchdog Driver for Smartbond family of MCUs"
default y
depends on DT_HAS_RENESAS_SMARTBOND_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable watchdog driver for Smartbond line of MCUs
config WDT_SMARTBOND_NMI
bool "NMI pre-reset interrupt enable"
default n
depends on WDT_SMARTBOND
select RUNTIME_NMI
help
Watchdog timer generates NMI at value 0, and WDOG (SYS)
reset at <= -16. Timer can be frozen/resumed using
SET_FREEZE_REG[FRZ_WDOG]/RESET_FREEZE_REG[FRZ_WDOG].
When not set:
Watchdog timer generates a WDOG (SYS)
reset at value 0 and can not be frozen by Software.
Note that this bit can only be set to 1 by SW and
only be reset with a WDOG (SYS) reset or SW reset.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.smartbond | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
config FWDGT_GD32
bool "GD32 Free watchdog timer (FWDGT) driver"
default y
depends on DT_HAS_GD_GD32_FWDGT_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
select USE_GD32_FWDGT
help
Enable the Free watchdog timer (FWDGT) driver for GD32 SoCs.
config WWDGT_GD32
bool "GD32 Window watchdog timer (WWDGT) Driver"
default y
depends on DT_HAS_GD_GD32_WWDGT_ENABLED
select USE_GD32_WWDGT
help
Enable the Window watchdog timer (WWDGT) driver for GD32 SoCs.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_NXP_FS26_H_
#define ZEPHYR_DRIVERS_WATCHDOG_WDT_NXP_FS26_H_
/* FS26 SPI Tx frame fields */
/* Main or Fail-safe register selection (M/FS) */
#define FS26_M_FS (0x1 << 31)
/* Register Address + M/FS */
#define FS26_REG_ADDR_SHIFT (25)
#define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
#define FS26_SET_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
#define FS26_GET_REG_ADDR(n) (((n) & FS26_REG_ADDR_MASK) >> FS26_REG_ADDR_SHIFT)
/* Read/Write (reading = 0) */
#define FS26_RW (0x1 << 24)
/* FS26 SPI Rx frame fields */
/* Device status flags */
#define FS26_DEV_STATUS_SHIFT (24)
#define FS26_DEV_STATUS_MASK (0xff << FS26_DEV_STATUS_SHIFT)
#define FS26_GET_DEV_STATUS(n) (((n) << FS26_DEV_STATUS_SHIFT) & FS26_DEV_STATUS_MASK)
/* Main State machine availability (M_AVAL) */
#define FS26_M_AVAL (0x1 << 31)
/* Fail Safe State machine status (FS_EN) */
#define FS26_FS_EN (0x1 << 30)
/* Interrupt notification from the Fail-Safe domain */
#define FS26_FS_G (0x1 << 29)
/* Interrupt notification from the M_COM_FLG register */
#define FS26_COM_G (0x1 << 28)
/* Interrupt notification from the M_WIO_FLG register */
#define FS26_WIO_G (0x1 << 27)
/* Interrupt notification from the M_VSUP_FLG register */
#define FS26_VSUP_G (0x1 << 26)
/* Interrupt notification from the M_REG_FLG register */
#define FS26_REG_G (0x1 << 25)
/* Interrupt notification from the M_TSD_FLG register */
#define FS26_TSD_G (0x1 << 24)
/* FS26 SPI Tx/Rx frame common fields */
/* DATA_MSB */
#define FS26_DATA_SHIFT (8)
#define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT)
#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
/* DATA_LSB */
#define FS26_DATA_LSB_SHIFT (8)
#define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT)
#define FS26_SET_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
#define FS26_GET_DATA_LSB(n) (((n) & FS26_DATA_LSB_MASK) >> FS26_DATA_LSB_SHIFT)
/* DATA_MSB */
#define FS26_DATA_MSB_SHIFT (16)
#define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT)
#define FS26_SET_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
#define FS26_GET_DATA_MSB(n) (((n) & FS26_DATA_MSB_MASK) >> FS26_DATA_MSB_SHIFT)
/* CRC */
#define FS26_CRC_SHIFT (0)
#define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT)
#define FS26_SET_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
#define FS26_GET_CRC(n) (((n) & FS26_CRC_MASK) >> FS26_CRC_SHIFT)
/* FS26 SPI register map */
#define FS26_M_DEVICE_ID (0x0)
#define FS26_M_PROGID (0x1)
#define FS26_M_STATUS (0x2)
#define FS26_M_TSD_FLG (0x3)
#define FS26_M_TSD_MSK (0x4)
#define FS26_M_REG_FLG (0x5)
#define FS26_M_REG_MSK (0x6)
#define FS26_M_VSUP_FLG (0x7)
#define FS26_M_VSUP_MSK (0x8)
#define FS26_M_WIO_FLG (0x9)
#define FS26_M_WIO_MSK (0xa)
#define FS26_M_COM_FLG (0xb)
#define FS26_M_COM_MSK (0xc)
#define FS26_M_SYS_CFG (0xd)
#define FS26_M_TSD_CFG (0xe)
#define FS26_M_REG_CFG (0xf)
#define FS26_M_WIO_CFG (0x10)
#define FS26_M_REG_CTRL1 (0x11)
#define FS26_M_REG_CTRL2 (0x12)
#define FS26_M_AMUX_CTRL (0x13)
#define FS26_M_LDT_CFG1 (0x14)
#define FS26_M_LDT_CFG2 (0x15)
#define FS26_M_LDT_CFG3 (0x16)
#define FS26_M_LDT_CTRL (0x17)
#define FS26_M_MEMORY0 (0x18)
#define FS26_M_MEMORY1 (0x19)
/* FS26 Fail Safe register map */
#define FS26_FS_GRL_FLAGS (0x40)
#define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41)
#define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42)
#define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43)
#define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44)
#define FS26_FS_I_WD_CFG (0x45)
#define FS26_FS_I_NOT_WD_CFG (0x46)
#define FS26_FS_I_SAFE_INPUTS (0x47)
#define FS26_FS_I_NOT_SAFE_INPUTS (0x48)
#define FS26_FS_I_FSSM (0x49)
#define FS26_FS_I_NOT_FSSM (0x4a)
#define FS26_FS_WDW_DURATION (0x4b)
#define FS26_FS_NOT_WDW_DURATION (0x4c)
#define FS26_FS_WD_ANSWER (0x4d)
#define FS26_FS_WD_TOKEN (0x4e)
#define FS26_FS_ABIST_ON_DEMAND (0x4f)
#define FS26_FS_OVUV_REG_STATUS (0x50)
#define FS26_FS_RELEASE_FS0B_FS1B (0x51)
#define FS26_FS_SAFE_IOS_1 (0x52)
#define FS26_FS_SAFE_IOS_2 (0x53)
#define FS26_FS_DIAG_SAFETY1 (0x54)
#define FS26_FS_DIAG_SAFETY2 (0x55)
#define FS26_FS_INTB_MASK (0x56)
#define FS26_FS_STATES (0x57)
#define FS26_FS_LP_REQ (0x58)
#define FS26_FS_LDT_LPSEL (0x59)
/* FS_I_OVUV_SAFE_REACTION1 register */
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_PRE */
#define VMON_PRE_OV_FS_REACTION_SHIFT (14)
#define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
#define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
#define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
#define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_PRE */
#define VMON_PRE_UV_FS_REACTION_SHIFT (12)
#define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
#define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
#define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
#define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_CORE */
#define VMON_CORE_OV_FS_REACTION_SHIFT (10)
#define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
#define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
#define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
#define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_CORE */
#define VMON_CORE_UV_FS_REACTION_SHIFT (8)
#define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
#define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
#define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
#define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO1 */
#define VMON_LDO1_OV_FS_REACTION_SHIFT (6)
#define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
#define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
#define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
#define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO1 */
#define VMON_LDO1_UV_FS_REACTION_SHIFT (4)
#define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
#define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
#define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
#define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO2 */
#define VMON_LDO2_OV_FS_REACTION_SHIFT (2)
#define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
#define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
#define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
#define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO2 */
#define VMON_LDO2_UV_FS_REACTION_SHIFT (0)
#define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
#define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
#define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
#define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
/* FS_I_OVUV_SAFE_REACTION2 register */
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_EXT */
#define VMON_EXT_OV_FS_REACTION_SHIFT (14)
#define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
#define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
#define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
#define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_EXT */
#define VMON_EXT_UV_FS_REACTION_SHIFT (12)
#define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
#define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
#define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
#define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_REF */
#define VMON_REF_OV_FS_REACTION_SHIFT (10)
#define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
#define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
#define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
#define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_REF */
#define VMON_REF_UV_FS_REACTION_SHIFT (8)
#define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
#define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
#define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
#define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK2 */
#define VMON_TRK2_OV_FS_REACTION_SHIFT (6)
#define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
#define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
#define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
#define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK2 */
#define VMON_TRK2_UV_FS_REACTION_SHIFT (4)
#define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
#define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
#define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
#define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK1 */
#define VMON_TRK1_OV_FS_REACTION_SHIFT (2)
#define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
#define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
#define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
#define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
/* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK1 */
#define VMON_TRK1_UV_FS_REACTION_SHIFT (0)
#define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
#define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
#define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
#define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
/* FS26_FS_I_WD_CFG register */
/* Watchdog error counter limit */
#define WD_ERR_LIMIT_SHIFT (14)
#define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
#define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
#define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
#define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
#define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
/* Watchdog refresh counter limit */
#define WD_RFR_LIMIT_SHIFT (11)
#define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
#define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
#define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
#define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
#define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
/* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
#define WD_FS_REACTION_SHIFT (8)
#define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
#define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
#define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
#define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
/* Reflect the value of the Watchdog Refresh Counter */
#define WD_RFR_CNT_SHIFT (8)
#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
#define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT))
/* Reflect the value of the Watchdog Error Counter */
#define WD_ERR_CNT_SHIFT (0)
#define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT)
#define WD_ERR_CNT(n) \
(((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : (((n) & (0x7 << WD_RFR_CNT_SHIFT)))
/* FS26_FS_I_SAFE_INPUTS register */
/* FCCU Monitoring Configuration */
#define FCCU_CFG_SHIFT (13)
#define FCCU_CFG_MASK (0x7 << FCCU_CFG_SHIFT)
#define FCCU_CFG_NO_MONITORING (0x0 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU1_FCCU2_PAIR (0x1 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU1_FCCU2_SINGLE (0x2 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU1_ONLY (0x3 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU2_ONLY (0x4 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU1_FCCU2_PWM (0x5 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU1_PWM_FCCU2_SINGLE (0x6 << FCCU_CFG_SHIFT)
#define FCCU_CFG_FCCU2_PWM_FCCU1_SINGLE (0x7 << FCCU_CFG_SHIFT)
/* FCCU12 Fault Polarity */
#define FCCU12_FLT_POL_SHIFT (12)
#define FCCU12_FLT_POL_MASK (0x1 << FCCU12_FLT_POL_SHIFT)
#define FCCU12_FLT_POL_FCCU1_0_FCCU2_1_IS_FAULT (0x0 << FCCU12_FLT_POL_SHIFT)
#define FCCU12_FLT_POL_FCCU1_1_FCCU2_0_IS_FAULT (0x1 << FCCU12_FLT_POL_SHIFT)
/* FCCU1 Fault Polarity */
#define FCCU1_FLT_POL_SHIFT (11)
#define FCCU1_FLT_POL_MASK (0x1 << FCCU1_FLT_POL_SHIFT)
#define FCCU1_FLT_POL_LOW (0x0 << FCCU1_FLT_POL_SHIFT)
#define FCCU1_FLT_POL_HIGH (0x1 << FCCU1_FLT_POL_SHIFT)
/* FCCU2 Fault Polarity */
#define FCCU2_FLT_POL_SHIFT (10)
#define FCCU2_FLT_POL_MASK (0x1 << FCCU2_FLT_POL_SHIFT)
#define FCCU2_FLT_POL_LOW (0x0 << FCCU2_FLT_POL_SHIFT)
#define FCCU2_FLT_POL_HIGH (0x1 << FCCU2_FLT_POL_SHIFT)
/* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU12 */
#define FCCU12_FS_REACTION_SHIFT (9)
#define FCCU12_FS_REACTION_MASK (0x1 << FCCU12_FS_REACTION_SHIFT)
#define FCCU12_FS_REACTION (FCCU12_FS_REACTION_MASK)
/* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU1 */
#define FCCU1_FS_REACTION_SHIFT (8)
#define FCCU1_FS_REACTION_MASK (0x1 << FCCU1_FS_REACTION_SHIFT)
#define FCCU1_FS_REACTION (FCCU1_FS_REACTION_MASK)
/* Reaction on RSTB or FAIL SAFE output in case of FAULT DETECTION ON FCCU2 */
#define FCCU2_FS_REACTION_SHIFT (7)
#define FCCU2_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
#define FCCU2_FS_REACTION (FCCU2_FS_REACTION_MASK)
/* ERRORMON Fault Polarity */
#define ERRMON_FLT_POLARITY_SHIFT (5)
#define ERRMON_FLT_POLARITY_MASK (0x1 << ERRMON_FLT_POLARITY_SHIFT)
#define ERRMON_FLT_POLARITY_LOW (0x0 << ERRMON_FLT_POLARITY_SHIFT)
#define ERRMON_FLT_POLARITY_HIGH (0x1 << ERRMON_FLT_POLARITY_SHIFT)
/* Acknowledge timing following a fault detection on ERRMON */
#define ERRMON_ACK_TIME_SHIFT (3)
#define ERRMON_ACK_TIME_MASK (0x3 << ERRMON_ACK_TIME_SHIFT)
#define ERRMON_ACK_TIME_1MS (0x0 << ERRMON_ACK_TIME_SHIFT)
#define ERRMON_ACK_TIME_8MS (0x1 << ERRMON_ACK_TIME_SHIFT)
#define ERRMON_ACK_TIME_16MS (0x2 << ERRMON_ACK_TIME_SHIFT)
#define ERRMON_ACK_TIME_32MS (0x3 << ERRMON_ACK_TIME_SHIFT)
/* Reaction on RSTB or Fail Safe output in case of fault detection on ERRMON */
#define ERRMON_FS_REACTION_SHIFT (2)
#define ERRMON_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
#define ERRMON_FS_REACTION (FCCU2_FS_REACTION_MASK)
/* FCCU pin filtering time settings */
#define FCCU12_FILT_SHIFT (0)
#define FCCU12_FILT_MASK (0x3 << FCCU12_FILT_SHIFT)
#define FCCU12_FILT_3US (0x0 << FCCU12_FILT_SHIFT)
#define FCCU12_FILT_6US (0x1 << FCCU12_FILT_SHIFT)
#define FCCU12_FILT_10US (0x2 << FCCU12_FILT_SHIFT)
#define FCCU12_FILT_20US (0x3 << FCCU12_FILT_SHIFT)
/* FS26_FS_I_FSSM register */
/* Configure the maximum level of the fault counter */
#define FLT_ERR_CNT_LIMIT_SHIFT (14)
#define FLT_ERR_CNT_LIMIT_MASK (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
#define FLT_ERR_CNT_LIMIT_2 (0x0 << FLT_ERR_CNT_LIMIT_SHIFT)
#define FLT_ERR_CNT_LIMIT_6 (0x1 << FLT_ERR_CNT_LIMIT_SHIFT)
#define FLT_ERR_CNT_LIMIT_8 (0x2 << FLT_ERR_CNT_LIMIT_SHIFT)
#define FLT_ERR_CNT_LIMIT_12 (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
/* Configure the RSTB and FS0B behavior when fault error counter intermediate value */
#define FLT_ERR_REACTION_SHIFT (8)
#define FLT_ERR_REACTION_MASK (0x3 << FLT_ERR_REACTION_SHIFT)
#define FLT_ERR_REACTION_NO_EFFECT (0x0 << FLT_ERR_REACTION_SHIFT)
#define FLT_ERR_REACTION_FS0B (0x1 << FLT_ERR_REACTION_SHIFT)
#define FLT_ERR_REACTION_RSTB_FS0B (0x2 << FLT_ERR_REACTION_SHIFT)
/* Reset duration configuration */
#define RSTB_DUR_SHIFT (9)
#define RSTB_DUR_MASK (0x1 << RSTB_DUR_SHIFT)
#define RSTB_DUR_1MS (RSTB_DUR_MASK)
#define RSTB_DUR_10MS (0)
/* Assert RSTB in case a short to high is detected on FS0B */
#define BACKUP_SAFETY_PATH_FS0B_SHIFT (7)
#define BACKUP_SAFETY_PATH_FS0B_MASK (0x1 << BACKUP_SAFETY_PATH_FS0B_SHIFT)
#define BACKUP_SAFETY_PATH_FS0B (BACKUP_SAFETY_PATH_FS0B_MASK)
/* Assert RSTB in case a short to high is detected on FS1B */
#define BACKUP_SAFETY_PATH_FS1B_SHIFT (6)
#define BACKUP_SAFETY_PATH_FS1B_MASK (0x1 << BACKUP_SAFETY_PATH_FS1B_SHIFT)
#define BACKUP_SAFETY_PATH_FS1B (BACKUP_SAFETY_PATH_FS1B_MASK)
/* Disable CLK Monitoring */
#define CLK_MON_DIS_SHIFT (5)
#define CLK_MON_DIS_MASK (0x1 << CLK_MON_DIS_SHIFT)
#define CLK_MON_DIS (CLK_MON_DIS_MASK)
/* Disable 8s RSTB timer */
#define DIS8S_SHIFT (4)
#define DIS8S_MASK (0x1 << DIS8S_SHIFT)
#define DIS8S (DIS8S_MASK)
/* Reflect the value of the Watchdog Error Counter */
#define FLT_ERR_CNT_SHIFT (0)
#define FLT_ERR_CNT_MASK (0xf << FLT_ERR_CNT_SHIFT)
#define FLT_ERR_CNT(n) \
((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT)))
/* FS26_FS_WDW_DURATION register */
/* Watchdog window period */
#define WDW_PERIOD_SHIFT (12)
#define WDW_PERIOD_MASK (0xf << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_3MS (0x3 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_4MS (0x4 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_6MS (0x5 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_8MS (0x6 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_32MS (0xa << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_64MS (0xb << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_128MS (0xc << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_256MS (0xd << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_512MS (0xe << WDW_PERIOD_SHIFT)
#define WDW_PERIOD_1024MS (0xf << WDW_PERIOD_SHIFT)
/* Watchdog window duty cycle */
#define WDW_DC_SHIFT (6)
#define WDW_DC_MASK (0x7 << WDW_DC_SHIFT)
#define WDW_DC_31_68 (0x0 << WDW_PERIOD_SHIFT)
#define WDW_DC_37_62 (0x1 << WDW_PERIOD_SHIFT)
#define WDW_DC_50_50 (0x2 << WDW_PERIOD_SHIFT)
#define WDW_DC_62_37 (0x3 << WDW_PERIOD_SHIFT)
#define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT)
/* Watchdog window period */
#define WDW_RECOVERY_SHIFT (0)
#define WDW_RECOVERY_MASK (0xf << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_3MS (0x3 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_4MS (0x4 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_6MS (0x5 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_8MS (0x6 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_32MS (0xa << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_64MS (0xb << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_128MS (0xc << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_256MS (0xd << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_512MS (0xe << WDW_RECOVERY_SHIFT)
#define WDW_RECOVERY_1024MS (0xf << WDW_RECOVERY_SHIFT)
/* FS26_FS_DIAG_SAFETY1 register */
/* Bad WD refresh, Error in the data */
#define BAD_WD_DATA_SHIFT (10)
#define BAD_WD_DATA_MASK (0x1 << BAD_WD_DATA_SHIFT)
#define BAD_WD_DATA (BAD_WD_DATA_MASK)
/* Bad WD refresh, Error in the timing */
#define BAD_WD_TIMING_SHIFT (9)
#define BAD_WD_TIMING_MASK (0x1 << BAD_WD_TIMING_SHIFT)
#define BAD_WD_TIMING (BAD_WD_TIMING_MASK)
/* ABIST 1 pass */
#define ABIST1_PASS_SHIFT (8)
#define ABIST1_PASS_MASK (0x1 << ABIST1_PASS_SHIFT)
#define ABIST1_PASS (ABIST1_PASS_MASK)
/* ABIST 2 pass */
#define ABIST2_PASS_SHIFT (7)
#define ABIST2_PASS_MASK (0x1 << ABIST2_PASS_SHIFT)
#define ABIST2_PASS (ABIST2_PASS_MASK)
/* ABIST 2 done */
#define ABIST2_DONE_SHIFT (6)
#define ABIST2_DONE_MASK (0x1 << ABIST2_DONE_SHIFT)
#define ABIST2_DONE (ABIST2_DONE_MASK)
/* SPI CLK error */
#define SPI_FS_CLK_SHIFT (5)
#define SPI_FS_CLK_MASK (0x1 << SPI_FS_CLK_SHIFT)
#define SPI_FS_CLK (SPI_FS_CLK_MASK)
/* SPI invalid read/write error */
#define SPI_FS_REQ_SHIFT (4)
#define SPI_FS_REQ_MASK (0x1 << SPI_FS_REQ_SHIFT)
#define SPI_FS_REQ (SPI_FS_REQ_MASK)
/* SPI CRC error */
#define SPI_FS_CRC_SHIFT (3)
#define SPI_FS_CRC_MASK (0x1 << SPI_FS_CRC_SHIFT)
#define SPI_FS_CRC (SPI_FS_CRC_MASK)
/* FS OSC drift */
#define FS_OSC_DRIFT_SHIFT (2)
#define FS_OSC_DRIFT_MASK (0x1 << FS_OSC_DRIFT_SHIFT)
#define FS_OSC_DRIFT (FS_OSC_DRIFT_MASK)
/* LBIST STATUS */
#define LBIST_STATUS_SHIFT (0)
#define LBIST_STATUS_MASK (0x3 << LBIST_STATUS_SHIFT)
#define LBIST_STATUS (LBIST_STATUS_MASK)
#define LBIST_STATUS_FAIL (0x0 << LBIST_STATUS_SHIFT)
#define LBIST_STATUS_BYPASSED (0x1 << LBIST_STATUS_SHIFT)
#define LBIST_STATUS_FAIL2 (0x2 << LBIST_STATUS_SHIFT)
#define LBIST_STATUS_OK (0x3 << LBIST_STATUS_SHIFT)
/* FS26_FS_STATES register */
/* Leave debug mode */
#define EXIT_DBG_MODE_SHIFT (14)
#define EXIT_DBG_MODE_MASK (0x1 << EXIT_DBG_MODE_SHIFT)
#define EXIT_DBG_MODE (EXIT_DBG_MODE_MASK)
/* debug mode */
#define DBG_MODE_SHIFT (13)
#define DBG_MODE_MASK (0x1 << DBG_MODE_SHIFT)
#define DBG_MODE (DBG_MODE_MASK)
/* OTP crc error */
#define OTP_CORRUPT_SHIFT (12)
#define OTP_CORRUPT_MASK (0x1 << OTP_CORRUPT_SHIFT)
#define OTP_CORRUPT (OTP_CORRUPT_MASK)
/* INIT register error */
#define REG_CORRUPT_SHIFT (11)
#define REG_CORRUPT_MASK (0x1 << REG_CORRUPT_SHIFT)
#define REG_CORRUPT (REG_CORRUPT_MASK)
/* LBIST STATUS */
#define FS_STATES_SHIFT (0)
#define FS_STATES_MASK (0x1f << FS_STATES_SHIFT)
#define FS_STATES (FS_STATES_MASK)
#define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT)
#define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT)
#define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT)
#define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT)
#define FS_STATES_SAFETY_OUT_NOT (0xa << FS_STATES_SHIFT)
#define FS_STATES_NORMAL (0xb << FS_STATES_SHIFT)
/* FS26_FS_GRL_FLAGS register */
/* Report an issue in the communication (SPI) */
#define FS_COM_G_SHIFT (15)
#define FS_COM_G_MASK (0x1 << FS_COM_G_SHIFT)
#define FS_COM_G (FS_COM_G_MASK)
/* Report an issue on the Watchdog Refresh */
#define FS_WD_G_SHIFT (14)
#define FS_WD_G_MASK (0x1 << FS_WD_G_SHIFT)
#define FS_WD_G (FS_WD_G_MASK)
/* Report an issue in one of the Fail Safe IOs */
#define FS_IO_G_SHIFT (13)
#define FS_IO_G_MASK (0x1 << FS_IO_G_SHIFT)
#define FS_IO_G (FS_IO_G_MASK)
/* Report an issue in one of the voltage monitoring (OV or UV) */
#define FS_REG_OVUV_G_SHIFT (12)
#define FS_REG_OVUV_G_MASK (0x1 << FS_REG_OVUV_G_SHIFT)
#define FS_REG_OVUV_G (FS_REG_OVUV_G_MASK)
/* Report an issue on BIST (Logical or Analog) */
#define FS_BIST_G_SHIFT (11)
#define FS_BIST_G_MASK (0x1 << FS_BIST_G_SHIFT)
#define FS_BIST_G (FS_BIST_G_MASK)
/* FS26_FS_SAFE_IOS_1 register */
/* Go Back to INIT Fail Safe Request */
#define FS_GOTO_INIT_SHIFT (1)
#define FS_GOTO_INIT_MASK (0x1 << FS_GOTO_INIT_SHIFT)
#define FS_GOTO_INIT (FS_GOTO_INIT_MASK)
/* FS26_FS_INTB_MASK register */
/* Interrupt Mask on BAD_WD_REFRESH */
#define BAD_WD_M (0x1 << 5)
#endif /* ZEPHYR_DRIVERS_WATCHDOG_WDT_NXP_FS26_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_nxp_fs26.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,301 |
```unknown
# Microchip XEC Watchdog Timer configuration
config WDT_XEC
bool "Microchip XEC series Watchdog Timer (WDT) driver"
default y
depends on DT_HAS_MICROCHIP_XEC_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for Microchip XEC MCU series.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_wwdgt
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys_clock.h>
#include <gd32_wwdgt.h>
LOG_MODULE_REGISTER(wdt_wwdgt_gd32, CONFIG_WDT_LOG_LEVEL);
#define WWDGT_PRESCALER_EXP_MAX (3U)
#define WWDGT_COUNTER_MIN (0x40U)
#define WWDGT_COUNTER_MAX (0x7fU)
#define WWDGT_INTERNAL_DIVIDER (4096ULL)
struct gd32_wwdgt_config {
uint16_t clkid;
struct reset_dt_spec reset;
};
/* mutable driver data */
struct gd32_wwdgt_data {
/* counter update value*/
uint8_t counter;
/* user defined callback */
wdt_callback_t callback;
};
static void gd32_wwdgt_irq_config(const struct device *dev);
/**
* @param timeout Timeout value in milliseconds.
* @param exp exponent part of prescaler
*
* @return ticks count calculated by this formula.
*
* timeout = pclk * INTERNAL_DIVIDER * (2^prescaler_exp) * (count + 1)
* transform as
* count = (timeout * pclk / INTERNAL_DIVIDER * (2^prescaler_exp) ) - 1
*
* and add WWDGT_COUNTER_MIN to this as a offset value.
*/
static inline uint32_t gd32_wwdgt_calc_ticks(const struct device *dev,
uint32_t timeout, uint32_t exp)
{
const struct gd32_wwdgt_config *config = dev->config;
uint32_t pclk;
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid,
&pclk);
return ((timeout * pclk)
/ (WWDGT_INTERNAL_DIVIDER * (1 << exp) * MSEC_PER_SEC) - 1)
+ WWDGT_COUNTER_MIN;
}
/**
* @brief Calculates WWDGT config value from timeout window.
*
* @param win Pointer to timeout window struct.
* @param counter Pointer to the storage of counter value.
* @param wval Pointer to the storage of window value.
* @param prescaler Pointer to the storage of prescaler value.
*
* @return 0 on success, -EINVAL if the window-max is out of range
*/
static int gd32_wwdgt_calc_window(const struct device *dev,
const struct wdt_window *win,
uint32_t *counter, uint32_t *wval,
uint32_t *prescaler)
{
for (uint32_t shift = 0U; shift <= WWDGT_PRESCALER_EXP_MAX; shift++) {
uint32_t max_count = gd32_wwdgt_calc_ticks(dev, win->max, shift);
if (max_count <= WWDGT_COUNTER_MAX) {
*counter = max_count;
*prescaler = CFG_PSC(shift);
if (win->min == 0U) {
*wval = max_count;
} else {
*wval = gd32_wwdgt_calc_ticks(dev, win->min, shift);
}
return 0;
}
}
return -EINVAL;
}
static int gd32_wwdgt_setup(const struct device *dev, uint8_t options)
{
ARG_UNUSED(dev);
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
#if CONFIG_GD32_DBG_SUPPORT
dbg_periph_enable(DBG_WWDGT_HOLD);
#else
LOG_ERR("Debug support not enabled");
return -ENOTSUP;
#endif
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP not supported");
return -ENOTSUP;
}
wwdgt_enable();
wwdgt_flag_clear();
wwdgt_interrupt_enable();
return 0;
}
static int gd32_wwdgt_disable(const struct device *dev)
{
/* watchdog cannot be stopped once started */
ARG_UNUSED(dev);
return -EPERM;
}
static int gd32_wwdgt_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
uint32_t prescaler = 0U;
uint32_t counter = 0U;
uint32_t window = 0U;
struct gd32_wwdgt_data *data = dev->data;
if (config->window.max == 0U) {
LOG_ERR("window.max must be non-zero");
return -EINVAL;
}
if (gd32_wwdgt_calc_window(dev, &config->window, &counter, &window,
&prescaler) != 0) {
LOG_ERR("window.max in out of range");
return -EINVAL;
}
data->callback = config->callback;
data->counter = counter;
wwdgt_config(counter, window, prescaler);
return 0;
}
static int gd32_wwdgt_feed(const struct device *dev, int channel_id)
{
struct gd32_wwdgt_data *data = dev->data;
ARG_UNUSED(channel_id);
wwdgt_counter_update(data->counter);
return 0;
}
static void gd32_wwdgt_isr(const struct device *dev)
{
struct gd32_wwdgt_data *data = dev->data;
if (wwdgt_flag_get() != 0) {
wwdgt_flag_clear();
if (data->callback != NULL) {
data->callback(dev, 0);
}
}
}
static void gd32_wwdgt_irq_config(const struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), gd32_wwdgt_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
static const struct wdt_driver_api wwdgt_gd32_api = {
.setup = gd32_wwdgt_setup,
.disable = gd32_wwdgt_disable,
.install_timeout = gd32_wwdgt_install_timeout,
.feed = gd32_wwdgt_feed,
};
static int gd32_wwdgt_init(const struct device *dev)
{
const struct gd32_wwdgt_config *config = dev->config;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t)&config->clkid);
(void)reset_line_toggle_dt(&config->reset);
gd32_wwdgt_irq_config(dev);
return 0;
}
static const struct gd32_wwdgt_config wwdgt_cfg = {
.clkid = DT_INST_CLOCKS_CELL(0, id),
.reset = RESET_DT_SPEC_INST_GET(0),
};
static struct gd32_wwdgt_data wwdgt_data = {
.counter = WWDGT_COUNTER_MIN,
.callback = NULL
};
DEVICE_DT_INST_DEFINE(0, gd32_wwdgt_init, NULL, &wwdgt_data, &wwdgt_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wwdgt_gd32_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_wwdgt_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,589 |
```unknown
# Intel ADSP Watchdog configuration options
config WDT_INTEL_ADSP
bool "Intel ADSP Watchdog driver"
default y
depends on DT_HAS_INTEL_ADSP_WATCHDOG_ENABLED
help
Intel ADSP Watchdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.intel_adsp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
# NPCX WDT driver configuration options
config WDT_NPCX
bool "Nuvoton NPCX embedded controller (EC) Watchdog Timer driver"
default y
depends on DT_HAS_NUVOTON_NPCX_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
This option enables the Watchdog Timer driver for NPCX family of
processors.
Say y if you wish to use watchdog on NPCX MCU.
config WDT_NPCX_WARNING_LEADING_TIME_MS
int "Milliseconds before generating watchdog event/signal"
depends on WDT_NPCX
default 500
help
This option defines the window in which a watchdog event must be
handled. After this time window, the watchdog reset triggers
immediately.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 158 |
```unknown
# Synopsys DesignWare Watchdog configuration options
config WDT_DW
bool "Synopsys DesignWare Watchdog driver"
default y
depends on DT_HAS_SNPS_DESIGNWARE_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Synopsys DesignWare Watchdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.dw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
# OpenTitan Always-On Timer support
config WDT_OPENTITAN
bool "OpenTitan Always-On (AON) Timer"
depends on DT_HAS_LOWRISC_OPENTITAN_AONTIMER_ENABLED
default y
select HAS_WDT_MULTISTAGE
help
This option enables support for the watchdog portion of the OpenTitan AON
timer.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.opentitan | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
# nrfx WDT support
config WDT_NRFX
bool "nRF WDT nrfx driver"
default y
depends on DT_HAS_NORDIC_NRF_WDT_ENABLED
select NRFX_WDT0 if HAS_HW_NRF_WDT0
select NRFX_WDT1 if HAS_HW_NRF_WDT1
select NRFX_WDT30 if HAS_HW_NRF_WDT30
select NRFX_WDT31 if HAS_HW_NRF_WDT31
select NRFX_WDT010 if HAS_HW_NRF_WDT010
select NRFX_WDT011 if HAS_HW_NRF_WDT011
select NRFX_WDT130 if HAS_HW_NRF_WDT130
select NRFX_WDT131 if HAS_HW_NRF_WDT131
select NRFX_WDT132 if HAS_HW_NRF_WDT132
help
Enable support for nrfx WDT driver for nRF MCU series.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.nrfx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 196 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm1300_wdt
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/mfd/npm1300.h>
#include <zephyr/dt-bindings/gpio/nordic-npm1300-gpio.h>
/* nPM1300 TIMER base address */
#define TIME_BASE 0x07U
/* nPM1300 timer register offsets */
#define TIME_OFFSET_START 0x00U
#define TIME_OFFSET_STOP 0x01U
#define TIME_OFFSET_WDOG_KICK 0x04U
#define TIME_OFFSET_MODE 0x05U
/* nPM1300 timer modes */
#define TIME_MODE_BOOT 0x00U
#define TIME_MODE_WARN 0x01U
#define TIME_MODE_RESET 0x02U
#define TIME_MODE_GEN 0x03U
struct wdt_npm1300_config {
const struct device *mfd;
struct gpio_dt_spec reset_gpios;
};
struct wdt_npm1300_data {
bool timeout_valid;
};
static int wdt_npm1300_setup(const struct device *dev, uint8_t options)
{
const struct wdt_npm1300_config *config = dev->config;
struct wdt_npm1300_data *data = dev->data;
if (!data->timeout_valid) {
return -EINVAL;
}
return mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_START, 1U);
}
static int wdt_npm1300_disable(const struct device *dev)
{
const struct wdt_npm1300_config *config = dev->config;
struct wdt_npm1300_data *data = dev->data;
int ret;
ret = mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_STOP, 1U);
if (ret < 0) {
return ret;
}
data->timeout_valid = false;
return 0;
}
static int wdt_npm1300_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *timeout)
{
const struct wdt_npm1300_config *config = dev->config;
struct wdt_npm1300_data *data = dev->data;
uint8_t mode;
int ret;
if (data->timeout_valid) {
return -ENOMEM;
}
if (timeout->window.min != 0U) {
return -EINVAL;
}
ret = mfd_npm1300_set_timer(config->mfd, timeout->window.max);
if (ret < 0) {
return ret;
}
switch (timeout->flags & WDT_FLAG_RESET_MASK) {
case WDT_FLAG_RESET_NONE:
/* Watchdog expiry causes warn event only, and does not reset */
mode = TIME_MODE_GEN;
break;
case WDT_FLAG_RESET_CPU_CORE:
/* Watchdog expiry causes warn event, then asserts reset output */
mode = TIME_MODE_WARN;
break;
case WDT_FLAG_RESET_SOC:
/* Watchdog expiry causes warn event, then full power cycle */
mode = TIME_MODE_RESET;
break;
default:
return -EINVAL;
}
ret = mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_MODE, mode);
if (ret < 0) {
return ret;
}
data->timeout_valid = true;
return 0;
}
static int wdt_npm1300_feed(const struct device *dev, int channel_id)
{
const struct wdt_npm1300_config *config = dev->config;
if (channel_id != 0) {
return -EINVAL;
}
return mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_WDOG_KICK, 1U);
}
static const struct wdt_driver_api wdt_npm1300_api = {
.setup = wdt_npm1300_setup,
.disable = wdt_npm1300_disable,
.install_timeout = wdt_npm1300_install_timeout,
.feed = wdt_npm1300_feed,
};
static int wdt_npm1300_init(const struct device *dev)
{
const struct wdt_npm1300_config *config = dev->config;
int ret;
if (!device_is_ready(config->mfd)) {
return -ENODEV;
}
if (config->reset_gpios.port != NULL) {
if (!gpio_is_ready_dt(&config->reset_gpios)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->reset_gpios, NPM1300_GPIO_WDT_RESET_ON);
if (ret != 0) {
return ret;
}
}
return 0;
}
#define WDT_NPM1300_DEFINE(n) \
static struct wdt_npm1300_data data##n; \
\
static const struct wdt_npm1300_config config##n = { \
.mfd = DEVICE_DT_GET(DT_INST_PARENT(n)), \
.reset_gpios = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
}; \
\
DEVICE_DT_INST_DEFINE(n, &wdt_npm1300_init, NULL, &data##n, &config##n, POST_KERNEL, \
CONFIG_WDT_NPM1300_INIT_PRIORITY, &wdt_npm1300_api);
DT_INST_FOREACH_STATUS_OKAY(WDT_NPM1300_DEFINE)
``` | /content/code_sandbox/drivers/watchdog/wdt_npm1300.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,186 |
```c
/*
*
* Based on wdt_mcux_wdog.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_kinetis_wdog32
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_wdog32.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_mcux_wdog32);
#define MIN_TIMEOUT 1
struct mcux_wdog32_config {
WDOG_Type *base;
#if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency)
uint32_t clock_frequency;
#else /* !DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
#endif /* !DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
wdog32_clock_source_t clk_source;
wdog32_clock_prescaler_t clk_divider;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_wdog32_data {
wdt_callback_t callback;
wdog32_config_t wdog_config;
bool timeout_valid;
};
static int mcux_wdog32_setup(const struct device *dev, uint8_t options)
{
const struct mcux_wdog32_config *config = dev->config;
struct mcux_wdog32_data *data = dev->data;
WDOG_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
data->wdog_config.workMode.enableStop =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.workMode.enableDebug =
(options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U;
WDOG32_Init(base, &data->wdog_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_wdog32_disable(const struct device *dev)
{
const struct mcux_wdog32_config *config = dev->config;
struct mcux_wdog32_data *data = dev->data;
WDOG_Type *base = config->base;
WDOG32_Deinit(base);
data->timeout_valid = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
#define MSEC_TO_WDOG32_TICKS(clock_freq, divider, msec) \
((uint32_t)(clock_freq * msec / 1000U / divider))
static int mcux_wdog32_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct mcux_wdog32_config *config = dev->config;
struct mcux_wdog32_data *data = dev->data;
uint32_t clock_freq;
int div;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
#if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency)
clock_freq = config->clock_frequency;
#else /* !DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
#endif /* !DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
div = config->clk_divider == kWDOG32_ClockPrescalerDivide1 ? 1U : 256U;
WDOG32_GetDefaultConfig(&data->wdog_config);
data->wdog_config.timeoutValue =
MSEC_TO_WDOG32_TICKS(clock_freq, div, cfg->window.max);
if (cfg->window.min) {
data->wdog_config.enableWindowMode = true;
data->wdog_config.windowValue =
MSEC_TO_WDOG32_TICKS(clock_freq, div, cfg->window.min);
} else {
data->wdog_config.enableWindowMode = false;
data->wdog_config.windowValue = 0;
}
if ((data->wdog_config.timeoutValue < MIN_TIMEOUT) ||
(data->wdog_config.timeoutValue < data->wdog_config.windowValue)) {
LOG_ERR("Invalid timeout");
return -EINVAL;
}
data->wdog_config.prescaler = config->clk_divider;
data->wdog_config.clockSource = config->clk_source;
data->wdog_config.enableInterrupt = cfg->callback != NULL;
data->callback = cfg->callback;
data->timeout_valid = true;
LOG_DBG("Installed timeout (timeoutValue = %d)",
data->wdog_config.timeoutValue);
return 0;
}
static int mcux_wdog32_feed(const struct device *dev, int channel_id)
{
const struct mcux_wdog32_config *config = dev->config;
WDOG_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WDOG32_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_wdog32_isr(const struct device *dev)
{
const struct mcux_wdog32_config *config = dev->config;
struct mcux_wdog32_data *data = dev->data;
WDOG_Type *base = config->base;
uint32_t flags;
flags = WDOG32_GetStatusFlags(base);
WDOG32_ClearStatusFlags(base, flags);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_wdog32_init(const struct device *dev)
{
const struct mcux_wdog32_config *config = dev->config;
config->irq_config_func(dev);
return 0;
}
static const struct wdt_driver_api mcux_wdog32_api = {
.setup = mcux_wdog32_setup,
.disable = mcux_wdog32_disable,
.install_timeout = mcux_wdog32_install_timeout,
.feed = mcux_wdog32_feed,
};
#define TO_WDOG32_CLK_SRC(val) _DO_CONCAT(kWDOG32_ClockSource, val)
#define TO_WDOG32_CLK_DIV(val) _DO_CONCAT(kWDOG32_ClockPrescalerDivide, val)
static void mcux_wdog32_config_func_0(const struct device *dev);
static const struct mcux_wdog32_config mcux_wdog32_config_0 = {
.base = (WDOG_Type *) DT_INST_REG_ADDR(0),
#if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency)
.clock_frequency = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
#else /* !DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.clock_subsys = (clock_control_subsys_t)
DT_INST_CLOCKS_CELL(0, name),
#endif /* DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) */
.clk_source =
TO_WDOG32_CLK_SRC(DT_INST_PROP(0, clk_source)),
.clk_divider =
TO_WDOG32_CLK_DIV(DT_INST_PROP(0, clk_divider)),
.irq_config_func = mcux_wdog32_config_func_0,
};
static struct mcux_wdog32_data mcux_wdog32_data_0;
DEVICE_DT_INST_DEFINE(0, &mcux_wdog32_init,
NULL, &mcux_wdog32_data_0,
&mcux_wdog32_config_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_wdog32_api);
static void mcux_wdog32_config_func_0(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
mcux_wdog32_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
``` | /content/code_sandbox/drivers/watchdog/wdt_mcux_wdog32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,746 |
```c
/*
*
*/
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/logging/log_ctrl.h>
#define WDT_CHANNEL_COUNT DT_PROP(DT_WDT_COUNTER, num_channels)
#define DT_WDT_COUNTER DT_COMPAT_GET_ANY_STATUS_OKAY(zephyr_counter_watchdog)
#define WDT_SUPPORTED_CFG_FLAGS (WDT_FLAG_RESET_NONE | WDT_FLAG_RESET_SOC)
extern void sys_arch_reboot(int type);
struct wdt_counter_data {
wdt_callback_t callback[CONFIG_WDT_COUNTER_CH_COUNT];
uint32_t timeout[CONFIG_WDT_COUNTER_CH_COUNT];
uint8_t flags[CONFIG_WDT_COUNTER_CH_COUNT];
uint8_t alloc_cnt;
};
static struct wdt_counter_data wdt_data;
struct wdt_counter_config {
const struct device *counter;
};
static int wdt_counter_setup(const struct device *dev, uint8_t options)
{
const struct wdt_counter_config *config = dev->config;
const struct device *counter = config->counter;
if ((options & WDT_OPT_PAUSE_IN_SLEEP) || (options & WDT_OPT_PAUSE_HALTED_BY_DBG)) {
return -ENOTSUP;
}
return counter_start(counter);
}
static int wdt_counter_disable(const struct device *dev)
{
const struct wdt_counter_config *config = dev->config;
const struct device *counter = config->counter;
return counter_stop(counter);
}
static void counter_alarm_callback(const struct device *dev,
uint8_t chan_id, uint32_t ticks,
void *user_data)
{
const struct device *wdt_dev = user_data;
struct wdt_counter_data *data = wdt_dev->data;
counter_stop(dev);
if (data->callback[chan_id]) {
data->callback[chan_id](wdt_dev, chan_id);
}
if (data->flags[chan_id] & WDT_FLAG_RESET_SOC) {
LOG_PANIC();
sys_arch_reboot(0);
}
}
static int timeout_set(const struct device *dev, int chan_id, bool cancel)
{
const struct wdt_counter_config *config = dev->config;
struct wdt_counter_data *data = dev->data;
const struct device *counter = config->counter;
struct counter_alarm_cfg alarm_cfg = {
.callback = counter_alarm_callback,
.ticks = data->timeout[chan_id],
.user_data = (void *)dev,
.flags = 0
};
if (cancel) {
int err = counter_cancel_channel_alarm(counter, chan_id);
if (err < 0) {
return err;
}
}
return counter_set_channel_alarm(counter, chan_id, &alarm_cfg);
}
static int wdt_counter_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_counter_data *data = dev->data;
const struct wdt_counter_config *config = dev->config;
const struct device *counter = config->counter;
int chan_id;
if (!device_is_ready(counter)) {
return -EIO;
}
uint32_t max_timeout = counter_get_top_value(counter) -
counter_get_guard_period(counter,
COUNTER_GUARD_PERIOD_LATE_TO_SET);
uint32_t timeout_ticks = counter_us_to_ticks(counter, cfg->window.max * 1000);
if (cfg->flags & ~WDT_SUPPORTED_CFG_FLAGS) {
return -ENOTSUP;
}
if (cfg->window.min != 0U) {
return -EINVAL;
}
if (timeout_ticks > max_timeout || timeout_ticks == 0) {
return -EINVAL;
}
if (data->alloc_cnt == 0) {
return -ENOMEM;
}
data->alloc_cnt--;
chan_id = data->alloc_cnt;
data->timeout[chan_id] = timeout_ticks;
data->callback[chan_id] = cfg->callback;
data->flags[chan_id] = cfg->flags;
int err = timeout_set(dev, chan_id, false);
if (err < 0) {
return err;
}
return chan_id;
}
static int wdt_counter_feed(const struct device *dev, int chan_id)
{
const struct wdt_counter_config *config = dev->config;
if (chan_id > counter_get_num_of_channels(config->counter)) {
return -EINVAL;
}
/* Move alarm further in time. */
return timeout_set(dev, chan_id, true);
}
static const struct wdt_driver_api wdt_counter_driver_api = {
.setup = wdt_counter_setup,
.disable = wdt_counter_disable,
.install_timeout = wdt_counter_install_timeout,
.feed = wdt_counter_feed,
};
static const struct wdt_counter_config wdt_counter_config = {
.counter = DEVICE_DT_GET(DT_PHANDLE(DT_WDT_COUNTER, counter)),
};
static int wdt_counter_init(const struct device *dev)
{
const struct wdt_counter_config *config = dev->config;
struct wdt_counter_data *data = dev->data;
uint8_t ch_cnt = counter_get_num_of_channels(config->counter);
data->alloc_cnt = MIN(ch_cnt, CONFIG_WDT_COUNTER_CH_COUNT);
return 0;
}
DEVICE_DT_DEFINE(DT_WDT_COUNTER, wdt_counter_init, NULL,
&wdt_data, &wdt_counter_config,
POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&wdt_counter_driver_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_counter.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,132 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_fs26_wdog
#include <zephyr/kernel.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/sys/byteorder.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_nxp_fs26);
#include "wdt_nxp_fs26.h"
#if defined(CONFIG_BIG_ENDIAN)
#define SWAP_ENDIANNESS
#endif
#define FS26_CRC_TABLE_SIZE 256U
#define FS26_CRC_INIT 0xff
#define FS26_FS_WD_TOKEN_DEFAULT 0x5ab2
#define FS26_INIT_FS_TIMEOUT_MS 1000U
/* Helper macros to set register values from Kconfig options */
#define WD_ERR_LIMIT(x) _CONCAT(WD_ERR_LIMIT_, x)
#define WD_RFR_LIMIT(x) _CONCAT(WD_RFR_LIMIT_, x)
#define WDW_PERIOD(x) _CONCAT(_CONCAT(WDW_PERIOD_, x), MS)
#define BAD_WD_REFRESH_ERROR_STRING(x) \
((((x) & BAD_WD_DATA) ? "error in the data" : \
(((x) & BAD_WD_TIMING) ? "error in the timing (window)" \
: "unknown error")))
enum fs26_wd_type {
FS26_WD_SIMPLE,
FS26_WD_CHALLENGER
};
struct fs26_spi_rx_frame {
union {
struct {
uint8_t m_aval : 1;
uint8_t fs_en : 1;
uint8_t fs_g : 1;
uint8_t com_g : 1;
uint8_t wio_g : 1;
uint8_t vsup_g : 1;
uint8_t reg_g : 1;
uint8_t tsd_g : 1;
};
uint8_t raw;
} status;
uint16_t data;
};
struct fs26_spi_tx_frame {
bool write;
uint8_t addr;
uint16_t data;
};
struct wdt_nxp_fs26_config {
struct spi_dt_spec spi;
enum fs26_wd_type wd_type;
struct gpio_dt_spec int_gpio;
};
struct wdt_nxp_fs26_data {
wdt_callback_t callback;
uint16_t token; /* local copy of the watchdog token */
bool timeout_installed;
uint8_t window_period;
uint8_t window_duty_cycle;
uint8_t fs_reaction;
struct gpio_callback int_gpio_cb;
struct k_sem int_sem;
struct k_thread int_thread;
K_KERNEL_STACK_MEMBER(int_thread_stack, CONFIG_WDT_NXP_FS26_INT_THREAD_STACK_SIZE);
};
/*
* Allowed values for watchdog period and duty cycle (CLOSED window).
* The index is the value to write to the register. Keep values in ascending order.
*/
static const uint32_t fs26_period_values[] = {
0, 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 64, 128, 256, 512, 1024
};
static const double fs26_dc_closed_values[] = {
0.3125, 0.375, 0.5, 0.625, 0.6875, 0.75, 0.8125
};
/* CRC lookup table */
static const uint8_t FS26_CRC_TABLE[FS26_CRC_TABLE_SIZE] = {
0x00u, 0x1du, 0x3au, 0x27u, 0x74u, 0x69u, 0x4eu, 0x53u, 0xe8u,
0xf5u, 0xd2u, 0xcfu, 0x9cu, 0x81u, 0xa6u, 0xbbu, 0xcdu, 0xd0u,
0xf7u, 0xeau, 0xb9u, 0xa4u, 0x83u, 0x9eu, 0x25u, 0x38u, 0x1fu,
0x02u, 0x51u, 0x4cu, 0x6bu, 0x76u, 0x87u, 0x9au, 0xbdu, 0xa0u,
0xf3u, 0xeeu, 0xc9u, 0xd4u, 0x6fu, 0x72u, 0x55u, 0x48u, 0x1bu,
0x06u, 0x21u, 0x3cu, 0x4au, 0x57u, 0x70u, 0x6du, 0x3eu, 0x23u,
0x04u, 0x19u, 0xa2u, 0xbfu, 0x98u, 0x85u, 0xd6u, 0xcbu, 0xecu,
0xf1u, 0x13u, 0x0eu, 0x29u, 0x34u, 0x67u, 0x7au, 0x5du, 0x40u,
0xfbu, 0xe6u, 0xc1u, 0xdcu, 0x8fu, 0x92u, 0xb5u, 0xa8u, 0xdeu,
0xc3u, 0xe4u, 0xf9u, 0xaau, 0xb7u, 0x90u, 0x8du, 0x36u, 0x2bu,
0x0cu, 0x11u, 0x42u, 0x5fu, 0x78u, 0x65u, 0x94u, 0x89u, 0xaeu,
0xb3u, 0xe0u, 0xfdu, 0xdau, 0xc7u, 0x7cu, 0x61u, 0x46u, 0x5bu,
0x08u, 0x15u, 0x32u, 0x2fu, 0x59u, 0x44u, 0x63u, 0x7eu, 0x2du,
0x30u, 0x17u, 0x0au, 0xb1u, 0xacu, 0x8bu, 0x96u, 0xc5u, 0xd8u,
0xffu, 0xe2u, 0x26u, 0x3bu, 0x1cu, 0x01u, 0x52u, 0x4fu, 0x68u,
0x75u, 0xceu, 0xd3u, 0xf4u, 0xe9u, 0xbau, 0xa7u, 0x80u, 0x9du,
0xebu, 0xf6u, 0xd1u, 0xccu, 0x9fu, 0x82u, 0xa5u, 0xb8u, 0x03u,
0x1eu, 0x39u, 0x24u, 0x77u, 0x6au, 0x4du, 0x50u, 0xa1u, 0xbcu,
0x9bu, 0x86u, 0xd5u, 0xc8u, 0xefu, 0xf2u, 0x49u, 0x54u, 0x73u,
0x6eu, 0x3du, 0x20u, 0x07u, 0x1au, 0x6cu, 0x71u, 0x56u, 0x4bu,
0x18u, 0x05u, 0x22u, 0x3fu, 0x84u, 0x99u, 0xbeu, 0xa3u, 0xf0u,
0xedu, 0xcau, 0xd7u, 0x35u, 0x28u, 0x0fu, 0x12u, 0x41u, 0x5cu,
0x7bu, 0x66u, 0xddu, 0xc0u, 0xe7u, 0xfau, 0xa9u, 0xb4u, 0x93u,
0x8eu, 0xf8u, 0xe5u, 0xc2u, 0xdfu, 0x8cu, 0x91u, 0xb6u, 0xabu,
0x10u, 0x0du, 0x2au, 0x37u, 0x64u, 0x79u, 0x5eu, 0x43u, 0xb2u,
0xafu, 0x88u, 0x95u, 0xc6u, 0xdbu, 0xfcu, 0xe1u, 0x5au, 0x47u,
0x60u, 0x7du, 0x2eu, 0x33u, 0x14u, 0x09u, 0x7fu, 0x62u, 0x45u,
0x58u, 0x0bu, 0x16u, 0x31u, 0x2cu, 0x97u, 0x8au, 0xadu, 0xb0u,
0xe3u, 0xfeu, 0xd9u, 0xc4u
};
static uint8_t fs26_calcrc(const uint8_t *data, size_t size)
{
uint8_t crc;
uint8_t tableidx;
uint8_t i;
/* Set CRC token value */
crc = FS26_CRC_INIT;
for (i = size; i > 0; i--) {
tableidx = crc ^ data[i];
crc = FS26_CRC_TABLE[tableidx];
}
return crc;
}
static int fs26_spi_transceive(const struct spi_dt_spec *spi,
struct fs26_spi_tx_frame *tx_frame,
struct fs26_spi_rx_frame *rx_frame)
{
uint32_t tx_buf;
uint32_t rx_buf;
uint8_t crc;
int retval;
struct spi_buf spi_tx_buf = {
.buf = &tx_buf,
.len = sizeof(tx_buf)
};
struct spi_buf spi_rx_buf = {
.buf = &rx_buf,
.len = sizeof(rx_buf)
};
struct spi_buf_set spi_tx_set = {
.buffers = &spi_tx_buf,
.count = 1U
};
struct spi_buf_set spi_rx_set = {
.buffers = &spi_rx_buf,
.count = 1U
};
/* Create frame to Tx, always for Fail Safe */
tx_buf = (uint32_t)(FS26_SET_REG_ADDR(tx_frame->addr)
| FS26_SET_DATA(tx_frame->data)
| (tx_frame->write ? FS26_RW : 0));
crc = fs26_calcrc((uint8_t *)&tx_buf, sizeof(tx_buf) - 1);
tx_buf |= (uint32_t)FS26_SET_CRC(crc);
#if defined(SWAP_ENDIANNESS)
tx_buf = __builtin_bswap32(tx_buf);
#endif
retval = spi_transceive_dt(spi, &spi_tx_set, &spi_rx_set);
if (retval) {
goto error;
}
#if defined(SWAP_ENDIANNESS)
rx_buf = __builtin_bswap32(rx_buf);
#endif
/* Verify CRC of Rx frame */
crc = fs26_calcrc((uint8_t *)&rx_buf, sizeof(rx_buf) - 1);
if (crc != ((uint8_t)FS26_GET_CRC(rx_buf))) {
LOG_ERR("Rx invalid CRC");
retval = -EIO;
goto error;
}
if (rx_frame) {
rx_frame->status.raw = (uint8_t)FS26_GET_DEV_STATUS(rx_buf);
rx_frame->data = (uint16_t)FS26_GET_DATA(rx_buf);
}
error:
return retval;
}
/**
* @brief Get value of register with address @p addr
*
* @param spi SPI specs for interacting with the device
* @param addr Register address
* @param rx_frame SPI frame containing read data and device status flags
*
* @return 0 on success, error code otherwise
*/
static int fs26_getreg(const struct spi_dt_spec *spi, uint8_t addr,
struct fs26_spi_rx_frame *rx_frame)
{
struct fs26_spi_tx_frame tx_frame = {
.addr = addr,
.write = 0,
.data = 0
};
return fs26_spi_transceive(spi, &tx_frame, rx_frame);
}
/**
* @brief Set @p regval value in register with address @p addr
*
* @param spi SPI specs for interacting with the device
* @param addr Register address
* @param regval Register value to set
*
* @return 0 on success, error code otherwise
*/
static int fs26_setreg(const struct spi_dt_spec *spi, uint8_t addr, uint16_t regval)
{
struct fs26_spi_tx_frame tx_frame = {
.addr = addr,
.write = true,
.data = regval
};
return fs26_spi_transceive(spi, &tx_frame, NULL);
}
/**
* @brief Calculate watchdog answer based on received token
*
* @return answer value to write to FS_WD_ANSWER
*/
static inline uint16_t fs26_wd_compute_answer(uint16_t token)
{
uint32_t tmp = token;
tmp *= 4U;
tmp += 6U;
tmp -= 4U;
tmp = ~tmp;
tmp /= 4U;
return (uint16_t)tmp;
}
/**
* @brief Refresh the watchdog and verify the refresh was good.
*
* @return 0 on success, error code otherwise
*/
static int fs26_wd_refresh(const struct device *dev)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct wdt_nxp_fs26_data *data = dev->data;
int retval = 0;
int key;
uint16_t answer;
struct fs26_spi_rx_frame rx_frame;
if (config->wd_type == FS26_WD_SIMPLE) {
if (fs26_setreg(&config->spi, FS26_FS_WD_ANSWER, data->token) == 0) {
LOG_ERR("Failed to write answer");
retval = -EIO;
}
} else if (config->wd_type == FS26_WD_CHALLENGER) {
key = irq_lock();
/* Read challenge token generated by the device */
if (fs26_getreg(&config->spi, FS26_FS_WD_TOKEN, &rx_frame)) {
LOG_ERR("Failed to obtain watchdog token");
retval = -EIO;
} else {
data->token = rx_frame.data;
LOG_DBG("Watchdog token is %x", data->token);
answer = fs26_wd_compute_answer(data->token);
if (fs26_setreg(&config->spi, FS26_FS_WD_ANSWER, answer)) {
LOG_ERR("Failed to write answer");
retval = -EIO;
}
}
irq_unlock(key);
} else {
retval = -EINVAL;
}
/* Check if watchdog refresh was successful */
if (!retval) {
if (!fs26_getreg(&config->spi, FS26_FS_GRL_FLAGS, &rx_frame)) {
if ((rx_frame.data & FS_WD_G_MASK) == FS_WD_G) {
if (!fs26_getreg(&config->spi, FS26_FS_DIAG_SAFETY1, &rx_frame)) {
LOG_ERR("Bad watchdog refresh, %s",
BAD_WD_REFRESH_ERROR_STRING(rx_frame.data));
}
retval = -EIO;
} else {
LOG_DBG("Refreshed the watchdog");
}
}
}
return retval;
}
/**
* @brief Wait for state machine to be at in INIT_FS state
*
* @return 0 on success, -ETIMEDOUT if timedout
*/
static int fs26_poll_for_init_fs_state(const struct device *dev)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct fs26_spi_rx_frame rx_frame;
uint32_t regval = 0;
int64_t timeout;
int64_t now;
timeout = k_uptime_get() + FS26_INIT_FS_TIMEOUT_MS;
do {
if (!fs26_getreg(&config->spi, FS26_FS_STATES, &rx_frame)) {
regval = rx_frame.data;
}
k_sleep(K_MSEC(1));
now = k_uptime_get();
} while ((now < timeout) && (regval & FS_STATES_MASK) != FS_STATES_INIT_FS);
if (now >= timeout) {
LOG_ERR("Timedout waiting for INIT_FS state");
return -ETIMEDOUT;
}
return 0;
}
/**
* @brief Go to INIT_FS state from any FS state after INIT_FS
*
* After INIT_FS closure, it is possible to come back to INIT_FS with the
* GOTO_INIT bit in FS_SAFE_IOS_1 register from any FS state after INIT_FS.
*
* @return 0 on success, error code otherwise
*/
static int fs26_goto_init_fs_state(const struct device *dev)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct fs26_spi_rx_frame rx_frame;
uint32_t current_state;
int retval = -EIO;
if (!fs26_getreg(&config->spi, FS26_FS_STATES, &rx_frame)) {
current_state = rx_frame.data & FS_STATES_MASK;
if (current_state < FS_STATES_INIT_FS) {
LOG_ERR("Cannot go to INIT_FS from current state %x", current_state);
retval = -EIO;
} else if (current_state == FS_STATES_INIT_FS) {
retval = 0;
} else {
fs26_setreg(&config->spi, FS26_FS_SAFE_IOS_1, (uint32_t)FS_GOTO_INIT);
retval = fs26_poll_for_init_fs_state(dev);
}
}
return retval;
}
/**
* @brief Close INIT_FS phase with a (good) watchdog refresh.
*
* @return 0 on success, error code otherwise
*/
static inline int fs26_exit_init_fs_state(const struct device *dev)
{
return fs26_wd_refresh(dev);
}
static int wdt_nxp_fs26_feed(const struct device *dev, int channel_id)
{
struct wdt_nxp_fs26_data *data = dev->data;
if (channel_id != 0) {
LOG_ERR("Invalid channel ID");
return -EINVAL;
}
if (!data->timeout_installed) {
LOG_ERR("No timeout installed");
return -EINVAL;
}
return fs26_wd_refresh(dev);
}
static int wdt_nxp_fs26_setup(const struct device *dev, uint8_t options)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct wdt_nxp_fs26_data *data = dev->data;
uint32_t regval;
if (!data->timeout_installed) {
LOG_ERR("No timeout installed");
return -EINVAL;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) || (options & WDT_OPT_PAUSE_HALTED_BY_DBG)) {
return -ENOTSUP;
}
/*
* Apply fail-safe reaction configuration on RSTB and/or the safety output(s),
* configurable during the initialization phase.
*/
if (fs26_goto_init_fs_state(dev)) {
LOG_ERR("Failed to go to INIT_FS");
return -EIO;
}
regval = WD_ERR_LIMIT(CONFIG_WDT_NXP_FS26_ERROR_COUNTER_LIMIT)
| WD_RFR_LIMIT(CONFIG_WDT_NXP_FS26_REFRESH_COUNTER_LIMIT)
| ((data->fs_reaction << WD_FS_REACTION_SHIFT) & WD_FS_REACTION_MASK);
fs26_setreg(&config->spi, FS26_FS_I_WD_CFG, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_WD_CFG, ~regval);
/* Apply watchdog window configuration, configurable during any FS state */
regval = ((data->window_period << WDW_PERIOD_SHIFT) & WDW_PERIOD_MASK)
| ((data->window_duty_cycle << WDW_DC_SHIFT) & WDW_DC_MASK)
| WDW_RECOVERY_DISABLE;
fs26_setreg(&config->spi, FS26_FS_WDW_DURATION, regval);
fs26_setreg(&config->spi, FS26_FS_NOT_WDW_DURATION, ~regval);
/*
* The new watchdog window is effective after the next watchdog refresh,
* so feed the watchdog once to make it effective after exiting this
* function. Also it's required to close init phase.
*/
if (fs26_exit_init_fs_state(dev)) {
LOG_ERR("Failed to close INIT_FS");
return -EIO;
}
return 0;
}
static int wdt_nxp_fs26_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_nxp_fs26_data *data = dev->data;
uint32_t window_min;
uint8_t i;
if (data->timeout_installed) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if ((cfg->window.max == 0) || (cfg->window.max > 1024)
|| (cfg->window.max <= cfg->window.min)) {
LOG_ERR("Invalid timeout value");
return -EINVAL;
}
/* Find nearest period value (rounded up) */
for (i = 0; i < ARRAY_SIZE(fs26_period_values); i++) {
if (fs26_period_values[i] >= cfg->window.max) {
break;
}
}
data->window_period = i;
LOG_DBG("window.max requested %d ms, using %d ms",
cfg->window.max, fs26_period_values[data->window_period]);
/*
* Find nearest duty cycle value based on new period, that results in a
* window's minimum near the requested (rounded up)
*/
for (i = 0; i < ARRAY_SIZE(fs26_dc_closed_values); i++) {
window_min = (uint32_t)(fs26_dc_closed_values[i]
* fs26_period_values[data->window_period]);
if (window_min >= cfg->window.min) {
break;
}
}
if (i >= ARRAY_SIZE(fs26_dc_closed_values)) {
LOG_ERR("Watchdog opened window too small");
return -EINVAL;
}
data->window_duty_cycle = i;
LOG_DBG("window.min requested %d ms, using %d ms (%.2f%%)",
cfg->window.min, window_min,
fs26_dc_closed_values[data->window_duty_cycle] * 100);
/* Fail-safe reaction configuration */
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
__fallthrough;
case WDT_FLAG_RESET_CPU_CORE:
data->fs_reaction = WD_FS_REACTION_RSTB_FS0B >> WD_FS_REACTION_SHIFT;
LOG_DBG("Configuring reset mode");
break;
case WDT_FLAG_RESET_NONE:
data->fs_reaction = WD_FS_REACTION_NO_ACTION >> WD_FS_REACTION_SHIFT;
LOG_DBG("Configuring non-reset mode");
break;
default:
LOG_ERR("Unsupported watchdog configuration flag");
return -EINVAL;
}
data->callback = cfg->callback;
data->timeout_installed = true;
/* Always return channel ID equal to 0 */
return 0;
}
static int wdt_nxp_fs26_disable(const struct device *dev)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct wdt_nxp_fs26_data *data = dev->data;
struct fs26_spi_rx_frame rx_frame;
uint32_t regval;
if (fs26_getreg(&config->spi, FS26_FS_WDW_DURATION, &rx_frame)) {
return -EIO;
}
if ((rx_frame.data & WDW_PERIOD_MASK) == WDW_PERIOD_DISABLE) {
LOG_ERR("Watchdog already disabled");
return -EFAULT;
}
/* The watchdog window can be disabled only during the initialization phase */
if (fs26_goto_init_fs_state(dev)) {
LOG_ERR("Failed to go to INIT_FS");
return -EIO;
}
regval = WDW_PERIOD_DISABLE | WDW_RECOVERY_DISABLE;
fs26_setreg(&config->spi, FS26_FS_WDW_DURATION, regval);
fs26_setreg(&config->spi, FS26_FS_NOT_WDW_DURATION, ~regval);
/* The watchdog disabling is effective when the initialization phase is closed */
if (fs26_exit_init_fs_state(dev)) {
LOG_ERR("Failed to close INIT_FS");
return -EIO;
}
LOG_DBG("Watchdog disabled");
data->timeout_installed = false;
return 0;
}
static void wdt_nxp_fs26_int_thread(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
const struct device *dev = p1;
const struct wdt_nxp_fs26_config *config = dev->config;
struct wdt_nxp_fs26_data *data = dev->data;
struct fs26_spi_rx_frame rx_frame;
uint32_t regval;
while (1) {
k_sem_take(&data->int_sem, K_FOREVER);
if ((!fs26_getreg(&config->spi, FS26_FS_GRL_FLAGS, &rx_frame))
&& ((rx_frame.data & FS_WD_G_MASK) == FS_WD_G)) {
if ((!fs26_getreg(&config->spi, FS26_FS_DIAG_SAFETY1, &rx_frame))
&& (rx_frame.data & BAD_WD_TIMING)) {
/* Clear flag */
regval = BAD_WD_TIMING;
fs26_setreg(&config->spi, FS26_FS_DIAG_SAFETY1, regval);
/* Invoke user callback */
if (data->callback && data->timeout_installed) {
data->callback(dev, 0);
}
}
}
}
}
static void wdt_nxp_fs26_int_callback(const struct device *dev,
struct gpio_callback *cb,
uint32_t pins)
{
struct wdt_nxp_fs26_data *data = CONTAINER_OF(cb, struct wdt_nxp_fs26_data,
int_gpio_cb);
ARG_UNUSED(dev);
ARG_UNUSED(pins);
k_sem_give(&data->int_sem);
}
static int wdt_nxp_fs26_init(const struct device *dev)
{
const struct wdt_nxp_fs26_config *config = dev->config;
struct wdt_nxp_fs26_data *data = dev->data;
struct fs26_spi_rx_frame rx_frame;
uint32_t regval;
/* Validate bus is ready */
if (!spi_is_ready_dt(&config->spi)) {
return -ENODEV;
}
k_sem_init(&data->int_sem, 0, 1);
/* Configure GPIO used for INTB signal */
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("GPIO port %s not ready", config->int_gpio.port->name);
return -ENODEV;
}
if (gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT)) {
LOG_ERR("Unable to configure GPIO pin %u", config->int_gpio.pin);
return -EIO;
}
gpio_init_callback(&(data->int_gpio_cb), wdt_nxp_fs26_int_callback,
BIT(config->int_gpio.pin));
if (gpio_add_callback(config->int_gpio.port, &(data->int_gpio_cb))) {
return -EINVAL;
}
if (gpio_pin_interrupt_configure_dt(&config->int_gpio,
GPIO_INT_EDGE_FALLING)) {
return -EINVAL;
}
k_thread_create(&data->int_thread, data->int_thread_stack,
CONFIG_WDT_NXP_FS26_INT_THREAD_STACK_SIZE,
wdt_nxp_fs26_int_thread,
(void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_WDT_NXP_FS26_INT_THREAD_PRIO),
0, K_NO_WAIT);
/* Verify FS BIST before proceeding */
if (fs26_getreg(&config->spi, FS26_FS_DIAG_SAFETY1, &rx_frame)) {
return -EIO;
}
if ((rx_frame.data & (ABIST1_PASS_MASK | LBIST_STATUS_MASK))
!= (ABIST1_PASS | LBIST_STATUS_OK)) {
LOG_ERR("BIST failed 0x%x", rx_frame.data);
return -EIO;
}
/* Get FS state machine state */
if (fs26_getreg(&config->spi, FS26_FS_STATES, &rx_frame)) {
return -EIO;
}
/* Verify if in DEBUG mode */
if ((rx_frame.data & DBG_MODE_MASK) == DBG_MODE) {
if (IS_ENABLED(CONFIG_WDT_NXP_FS26_EXIT_DEBUG_MODE)) {
LOG_DBG("Exiting DEBUG mode");
regval = rx_frame.data | EXIT_DBG_MODE;
fs26_setreg(&config->spi, FS26_FS_STATES, regval);
} else {
LOG_ERR("In DEBUG mode, watchdog is disabled");
return -EIO;
}
}
/* Go to INIT_FS state, if not already there */
if (fs26_goto_init_fs_state(dev)) {
LOG_ERR("Failed to go to INIT_FS");
return -EIO;
}
/* Clear pending FS diagnostic flags before initializing */
regval = BAD_WD_DATA | BAD_WD_TIMING | ABIST2_PASS | ABIST2_DONE
| SPI_FS_CLK | SPI_FS_REQ | SPI_FS_CRC | FS_OSC_DRIFT;
fs26_setreg(&config->spi, FS26_FS_DIAG_SAFETY1, regval);
/*
* Perform the following sequence for all INIT_FS registers (FS_I_xxxx)
* - Write the desired data in the FS_I_Register_A (data)
* - Write the opposite in the FS_I_NOT_Register_A (~data)
*/
/* OVUV_SAFE_REACTION1 */
regval = VMON_PRE_OV_FS_REACTION_NO_EFFECT |
VMON_PRE_UV_FS_REACTION_NO_EFFECT |
VMON_CORE_OV_FS_REACTION_NO_EFFECT |
VMON_CORE_UV_FS_REACTION_NO_EFFECT |
VMON_LDO1_OV_FS_REACTION_NO_EFFECT |
VMON_LDO1_UV_FS_REACTION_NO_EFFECT |
VMON_LDO2_OV_FS_REACTION_NO_EFFECT |
VMON_LDO2_UV_FS_REACTION_NO_EFFECT;
fs26_setreg(&config->spi, FS26_FS_I_OVUV_SAFE_REACTION1, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_OVUV_SAFE_REACTION1, ~regval);
/* OVUV_SAFE_REACTION2 */
regval = VMON_EXT_OV_FS_REACTION_NO_EFFECT |
VMON_EXT_UV_FS_REACTION_NO_EFFECT |
VMON_REF_OV_FS_REACTION_NO_EFFECT |
VMON_REF_UV_FS_REACTION_NO_EFFECT |
VMON_TRK2_OV_FS_REACTION_NO_EFFECT |
VMON_TRK2_UV_FS_REACTION_NO_EFFECT |
VMON_TRK1_OV_FS_REACTION_NO_EFFECT |
VMON_TRK1_UV_FS_REACTION_NO_EFFECT;
fs26_setreg(&config->spi, FS26_FS_I_OVUV_SAFE_REACTION2, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_OVUV_SAFE_REACTION2, ~regval);
/* FS_I_SAFE_INPUTS */
regval = FCCU_CFG_NO_MONITORING | ERRMON_ACK_TIME_32MS;
fs26_setreg(&config->spi, FS26_FS_I_SAFE_INPUTS, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_SAFE_INPUTS, ~regval);
/* FS_I_FSSM */
regval = FLT_ERR_REACTION_NO_EFFECT | CLK_MON_DIS | DIS8S;
fs26_setreg(&config->spi, FS26_FS_I_FSSM, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_FSSM, ~regval);
/* FS_I_WD_CFG */
regval = WD_ERR_LIMIT(CONFIG_WDT_NXP_FS26_ERROR_COUNTER_LIMIT)
| WD_RFR_LIMIT(CONFIG_WDT_NXP_FS26_REFRESH_COUNTER_LIMIT)
| WD_FS_REACTION_NO_ACTION;
fs26_setreg(&config->spi, FS26_FS_I_WD_CFG, regval);
fs26_setreg(&config->spi, FS26_FS_I_NOT_WD_CFG, ~regval);
/* FS_WDW_DURATION */
/* Watchdog always disabled at boot */
regval = WDW_PERIOD_DISABLE | WDW_RECOVERY_DISABLE;
fs26_setreg(&config->spi, FS26_FS_WDW_DURATION, regval);
fs26_setreg(&config->spi, FS26_FS_NOT_WDW_DURATION, ~regval);
/* Set watchdog seed if not using the default */
if (data->token != FS26_FS_WD_TOKEN_DEFAULT) {
LOG_DBG("Set seed to %x", data->token);
fs26_setreg(&config->spi, FS26_FS_WD_TOKEN, data->token);
}
/* Mask all Fail-Safe interrupt sources except for watchdog bad refresh */
regval = ~BAD_WD_M;
fs26_setreg(&config->spi, FS26_FS_INTB_MASK, regval);
/* Mask all main interrupt souces */
regval = 0xffff;
fs26_setreg(&config->spi, FS26_M_TSD_MSK, regval);
fs26_setreg(&config->spi, FS26_M_REG_MSK, regval);
fs26_setreg(&config->spi, FS26_M_VSUP_MSK, regval);
fs26_setreg(&config->spi, FS26_M_WIO_MSK, regval);
fs26_setreg(&config->spi, FS26_M_COM_MSK, regval);
/* INIT_FS must be closed before the 256 ms timeout */
if (fs26_exit_init_fs_state(dev)) {
LOG_ERR("Failed to close INIT_FS");
return -EIO;
}
/* After INIT_FS is completed, check for data corruption in init registers */
if (!fs26_getreg(&config->spi, FS26_FS_STATES, &rx_frame)) {
if ((rx_frame.data & REG_CORRUPT_MASK) == REG_CORRUPT) {
LOG_ERR("Data content corruption detected in init registers");
return -EIO;
}
}
return 0;
}
static const struct wdt_driver_api wdt_nxp_fs26_api = {
.setup = wdt_nxp_fs26_setup,
.disable = wdt_nxp_fs26_disable,
.install_timeout = wdt_nxp_fs26_install_timeout,
.feed = wdt_nxp_fs26_feed,
};
#define FS26_WDT_DEVICE_INIT(n) \
COND_CODE_1(DT_INST_ENUM_IDX(n, type), \
(BUILD_ASSERT(CONFIG_WDT_NXP_FS26_SEED != 0x0, \
"Seed value 0x0000 is not allowed");), \
(BUILD_ASSERT((CONFIG_WDT_NXP_FS26_SEED != 0x0) \
&& (CONFIG_WDT_NXP_FS26_SEED != 0xffff), \
"Seed values 0x0000 and 0xffff are not allowed");)) \
\
static struct wdt_nxp_fs26_data wdt_nxp_fs26_data_##n = { \
.token = CONFIG_WDT_NXP_FS26_SEED, \
}; \
\
static const struct wdt_nxp_fs26_config wdt_nxp_fs26_config_##n = { \
.spi = SPI_DT_SPEC_INST_GET(n, \
SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(32), 0), \
.wd_type = _CONCAT(FS26_WD_, DT_INST_STRING_UPPER_TOKEN(n, type)), \
.int_gpio = GPIO_DT_SPEC_INST_GET(n, int_gpios), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
wdt_nxp_fs26_init, \
NULL, \
&wdt_nxp_fs26_data_##n, \
&wdt_nxp_fs26_config_##n, \
POST_KERNEL, \
CONFIG_WDT_NXP_FS26_INIT_PRIORITY, \
&wdt_nxp_fs26_api);
DT_INST_FOREACH_STATUS_OKAY(FS26_WDT_DEVICE_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_nxp_fs26.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,170 |
```c
/*
*
*/
#define DT_DRV_COMPAT adi_max32_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <soc.h>
#include <errno.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_max32, CONFIG_WDT_LOG_LEVEL);
#include <wrap_max32_wdt.h>
struct max32_wdt_config {
mxc_wdt_regs_t *regs;
const struct device *clock;
struct max32_perclk perclk;
void (*irq_func)(void);
};
struct max32_wdt_data {
struct wdt_window timeout;
wdt_callback_t callback;
};
static int wdt_max32_calculate_timeout(uint32_t timeout, uint32_t clock_src)
{
int i;
uint32_t clk_frequency = 0;
uint32_t number_of_tick = 0;
clk_frequency = ADI_MAX32_GET_PRPH_CLK_FREQ(clock_src);
if (clk_frequency == 0) {
LOG_ERR("Unsupported clock source.");
return -ENOTSUP;
}
number_of_tick = ((uint64_t)timeout * (uint64_t)clk_frequency) / 1000;
i = LOG2CEIL(number_of_tick); /* Find closest bigger 2^i value than number_of_tick. */
i = CLAMP(i, 16, 31); /* Limit i between 16 and 31. */
/* It returns 31 - i because period thresholds are inverse ordered in register. */
return (31 - i);
}
static int wdt_max32_disable(const struct device *dev)
{
const struct max32_wdt_config *cfg = dev->config;
if (!(cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN)) {
return -EFAULT;
}
MXC_WDT_Disable(cfg->regs);
return 0;
}
static int wdt_max32_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(channel_id);
const struct max32_wdt_config *cfg = dev->config;
MXC_WDT_ResetTimer(cfg->regs);
return 0;
}
static int wdt_max32_setup(const struct device *dev, uint8_t options)
{
const struct max32_wdt_config *cfg = dev->config;
if (cfg->regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) {
return -EBUSY;
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
MXC_WDT_ResetTimer(cfg->regs);
MXC_WDT_Enable(cfg->regs);
return 0;
}
static int wdt_max32_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
int ret = 0;
const struct max32_wdt_config *dev_cfg = dev->config;
struct max32_wdt_data *data = dev->data;
mxc_wdt_regs_t *regs = dev_cfg->regs;
wrap_mxc_wdt_cfg_t wdt_cfg;
if (cfg->window.max == 0U) {
return -EINVAL;
}
if (regs->ctrl & WRAP_MXC_F_WDT_CTRL_EN) {
return -EBUSY;
}
data->timeout = cfg->window;
data->callback = cfg->callback;
/* Default values to eliminate warnings */
wdt_cfg.mode = MXC_WDT_COMPATIBILITY;
wdt_cfg.upperResetPeriod = 0;
wdt_cfg.lowerResetPeriod = 0;
wdt_cfg.upperIntPeriod = 0;
wdt_cfg.lowerIntPeriod = 0;
if (data->timeout.min > 0) {
wdt_cfg.mode = MXC_WDT_WINDOWED;
ret = Wrap_MXC_WDT_Init(regs, &wdt_cfg);
if (ret != E_NO_ERROR) {
LOG_DBG("%s does not support windowed mode.", CONFIG_BOARD);
return -EINVAL;
}
int lower_timeout_period =
wdt_max32_calculate_timeout(data->timeout.min, dev_cfg->perclk.clk_src);
if (lower_timeout_period == -ENOTSUP) {
return -EINVAL;
}
if (data->callback == NULL) {
wdt_cfg.lowerResetPeriod = lower_timeout_period;
wdt_cfg.lowerIntPeriod = lower_timeout_period; /* Not used */
} else {
switch (lower_timeout_period) {
case MXC_WDT_PERIOD_2_16: /* Min timeout */
wdt_cfg.lowerResetPeriod = MXC_WDT_PERIOD_2_17;
wdt_cfg.lowerIntPeriod = MXC_WDT_PERIOD_2_16;
break;
default:
/* Generate interrupt just before reset */
wdt_cfg.lowerResetPeriod = lower_timeout_period;
/* +1 means one steps before */
wdt_cfg.lowerIntPeriod = lower_timeout_period + 1;
break;
}
}
}
int upper_timeout_period =
wdt_max32_calculate_timeout(data->timeout.max, dev_cfg->perclk.clk_src);
if (upper_timeout_period == -ENOTSUP) {
return -EINVAL;
}
if (data->callback == NULL) {
wdt_cfg.upperResetPeriod = upper_timeout_period;
wdt_cfg.upperIntPeriod = upper_timeout_period; /* Not used */
} else {
switch (upper_timeout_period) {
case MXC_WDT_PERIOD_2_16: /* Min timeout */
wdt_cfg.upperResetPeriod = MXC_WDT_PERIOD_2_17;
wdt_cfg.upperIntPeriod = MXC_WDT_PERIOD_2_16;
break;
default:
/* Generate interrupt just before reset */
wdt_cfg.upperResetPeriod = upper_timeout_period;
/* +1 means one steps before */
wdt_cfg.upperIntPeriod = upper_timeout_period + 1;
break;
}
}
Wrap_MXC_WDT_SetResetPeriod(regs, &wdt_cfg);
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
MXC_WDT_EnableReset(regs);
LOG_DBG("Configuring reset SOC mode.");
break;
case WDT_FLAG_RESET_NONE:
MXC_WDT_DisableReset(regs);
LOG_DBG("Configuring non-reset mode.");
break;
default:
LOG_ERR("Unsupported watchdog config flag.");
return -ENOTSUP;
}
/* If callback is not null, enable interrupt. */
if (data->callback) {
Wrap_MXC_WDT_SetIntPeriod(regs, &wdt_cfg);
MXC_WDT_EnableInt(regs);
}
return ret;
}
static void wdt_max32_isr(const void *param)
{
const struct device *dev = (const struct device *)param;
const struct max32_wdt_config *cfg = dev->config;
struct max32_wdt_data *data = dev->data;
if (data->callback) {
data->callback(dev, 0);
}
MXC_WDT_ClearIntFlag(cfg->regs);
}
static int wdt_max32_init(const struct device *dev)
{
int ret = 0;
const struct max32_wdt_config *cfg = dev->config;
mxc_wdt_regs_t *regs = cfg->regs;
/* Enable clock */
ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
if (ret) {
return ret;
}
ret = Wrap_MXC_WDT_SelectClockSource(regs, cfg->perclk.clk_src);
if (ret != E_NO_ERROR) {
LOG_ERR("WDT instance does not support given clock source.");
return -ENOTSUP;
}
/* Disable all actions */
MXC_WDT_Disable(regs);
MXC_WDT_DisableReset(regs);
MXC_WDT_DisableInt(regs);
MXC_WDT_ClearResetFlag(regs);
MXC_WDT_ClearIntFlag(regs);
cfg->irq_func(); /* WDT IRQ enable*/
return 0;
}
static const struct wdt_driver_api max32_wdt_api = {.setup = wdt_max32_setup,
.disable = wdt_max32_disable,
.install_timeout = wdt_max32_install_timeout,
.feed = wdt_max32_feed};
#define MAX32_WDT_INIT(_num) \
static void wdt_max32_irq_init_##_num(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), wdt_max32_isr, \
DEVICE_DT_INST_GET(_num), 0); \
irq_enable(DT_INST_IRQN(_num)); \
} \
static struct max32_wdt_data max32_wdt_data##_num; \
static const struct max32_wdt_config max32_wdt_config##_num = { \
.regs = (mxc_wdt_regs_t *)DT_INST_REG_ADDR(_num), \
.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
.perclk.clk_src = \
DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK), \
.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
.irq_func = &wdt_max32_irq_init_##_num, \
}; \
DEVICE_DT_INST_DEFINE(_num, wdt_max32_init, NULL, &max32_wdt_data##_num, \
&max32_wdt_config##_num, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &max32_wdt_api);
DT_INST_FOREACH_STATUS_OKAY(MAX32_WDT_INIT)
``` | /content/code_sandbox/drivers/watchdog/wdt_max32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,118 |
```unknown
# Watchdog configuration options
menuconfig WATCHDOG
bool "Watchdog drivers"
help
Include support for watchdogs.
if WATCHDOG
config HAS_WDT_DISABLE_AT_BOOT
bool
config WDT_DISABLE_AT_BOOT
bool "Disable at boot"
depends on HAS_WDT_DISABLE_AT_BOOT
help
Disable watchdog at Zephyr system startup.
module = WDT
module-str = watchdog
source "subsys/logging/Kconfig.template.log_config"
config HAS_WDT_MULTISTAGE
bool
config WDT_MULTISTAGE
bool "Multistage timeouts"
depends on HAS_WDT_MULTISTAGE
help
Enable multistage operation of watchdog timeouts.
config WDT_COUNTER
bool "Counter based watchdog"
default y
depends on DT_HAS_ZEPHYR_COUNTER_WATCHDOG_ENABLED
select COUNTER
help
Watchdog emulated with counter device. If counter device supports using
zero latency interrupts (ZLI) then expiration callback can be called from
that context. This watchdog can be used along hardware watchdog to
overcome hardware watchdog limitations, e.g. Nordic devices reset
unconditionally at fixed time after hitting watchdog interrupt, leaving
no time to print debug information. Watchdog has limitations since it
cannot interrupt same or higher priorities so it cannot fully replace
hardware based watchdog.
if WDT_COUNTER
config WDT_COUNTER_CH_COUNT
int "Maximum number of supported channel"
default 4
range 1 $(UINT8_MAX)
help
Note that actual channel count will be limited to number of channels
supported by the counter device which is used for watchdog.
endif # WDT_COUNTER
source "drivers/watchdog/Kconfig.stm32"
source "drivers/watchdog/Kconfig.cmsdk_apb"
source "drivers/watchdog/Kconfig.sam"
source "drivers/watchdog/Kconfig.esp32"
source "drivers/watchdog/Kconfig.sam0"
source "drivers/watchdog/Kconfig.nrfx"
source "drivers/watchdog/Kconfig.mcux"
source "drivers/watchdog/Kconfig.mcux_imx"
source "drivers/watchdog/Kconfig.xec"
source "drivers/watchdog/Kconfig.gecko"
source "drivers/watchdog/Kconfig.sifive"
source "drivers/watchdog/Kconfig.npcx"
source "drivers/watchdog/Kconfig.cc32xx"
source "drivers/watchdog/Kconfig.cc13xx_cc26xx"
source "drivers/watchdog/Kconfig.it8xxx2"
source "drivers/watchdog/Kconfig.rpi_pico"
source "drivers/watchdog/Kconfig.gd32"
source "drivers/watchdog/Kconfig.npm1300"
source "drivers/watchdog/Kconfig.npm6001"
source "drivers/watchdog/Kconfig.nxp_s32"
source "drivers/watchdog/Kconfig.dw"
source "drivers/watchdog/Kconfig.intel_adsp"
source "drivers/watchdog/Kconfig.smartbond"
source "drivers/watchdog/Kconfig.ti_tps382x"
source "drivers/watchdog/Kconfig.tco"
source "drivers/watchdog/Kconfig.xlnx"
source "drivers/watchdog/Kconfig.ifx_cat1"
source "drivers/watchdog/Kconfig.opentitan"
source "drivers/watchdog/Kconfig.andes_atcwdt200"
source "drivers/watchdog/Kconfig.nxp_fs26"
source "drivers/watchdog/Kconfig.ambiq"
source "drivers/watchdog/Kconfig.shell"
source "drivers/watchdog/Kconfig.max32"
source "drivers/watchdog/Kconfig.xmc4xxx"
source "drivers/watchdog/Kconfig.numaker"
source "drivers/watchdog/Kconfig.ene"
source "drivers/watchdog/Kconfig.litex"
endif # WATCHDOG
``` | /content/code_sandbox/drivers/watchdog/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 764 |
```c
/*
*
*/
#define DT_DRV_COMPAT andestech_atcwdt200
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/syscon.h>
LOG_MODULE_REGISTER(wdt_andes);
/* Watchdog register */
#define REG_IDR 0x00
#define REG_CTRL 0x10
#define REG_RESTAR 0x14
#define REG_WREN 0x18
#define REG_STATUS 0x1c
#define WDT_CTRL(addr) (addr + REG_CTRL)
#define WDT_RESTAR(addr) (addr + REG_RESTAR)
#define WDT_WREN(addr) (addr + REG_WREN)
#define WDT_STATUS(addr) (addr + REG_STATUS)
/* Atcwdt200 magic number */
/* 0x10 Control Register */
#define WDT_CTRL_RSTTIME_POW_2_7 0x000
#define WDT_CTRL_RSTTIME_POW_2_8 0x100
#define WDT_CTRL_RSTTIME_POW_2_9 0x200
#define WDT_CTRL_RSTTIME_POW_2_10 0x300
#define WDT_CTRL_RSTTIME_POW_2_11 0x400
#define WDT_CTRL_RSTTIME_POW_2_12 0x500
#define WDT_CTRL_RSTTIME_POW_2_13 0x600
#define WDT_CTRL_RSTTIME_POW_2_14 0x700
#define WDT_CTRL_INTTIME_POW_2_6 0x000
#define WDT_CTRL_INTTIME_POW_2_8 0x010
#define WDT_CTRL_INTTIME_POW_2_10 0x020
#define WDT_CTRL_INTTIME_POW_2_11 0x030
#define WDT_CTRL_INTTIME_POW_2_12 0x040
#define WDT_CTRL_INTTIME_POW_2_13 0x050
#define WDT_CTRL_INTTIME_POW_2_14 0x060
#define WDT_CTRL_INTTIME_POW_2_15 0x070
#define WDT_CTRL_INTTIME_POW_2_17 0x080
#define WDT_CTRL_INTTIME_POW_2_19 0x090
#define WDT_CTRL_INTTIME_POW_2_21 0x0A0
#define WDT_CTRL_INTTIME_POW_2_23 0x0B0
#define WDT_CTRL_INTTIME_POW_2_25 0x0C0
#define WDT_CTRL_INTTIME_POW_2_27 0x0D0
#define WDT_CTRL_INTTIME_POW_2_29 0x0E0
#define WDT_CTRL_INTTIME_POW_2_31 0x0F0
#define WDT_CTRL_RSTEN 0x8
#define WDT_CTRL_INTEN 0x4
#define WDT_CTRL_APBCLK 0x2
#define WDT_CTRL_EXTCLK 0x0
#define WDT_CTRL_EN 0x1
/* Magic Number for Restart Register */
#define WDT_RESTART_NUM 0xcafe
/* Magic Number for Write Enable Register */
#define WDT_WREN_NUM 0x5aa5
/* 0x1C Status Register */
#define WDT_ST_INTEXPIRED 0x1
#define WDT_ST_INTEXPIRED_CLR 0x1
#define WDOGCFG_PERIOD_MIN BIT(7)
#define WDOGCFG_PERIOD_MAX BIT(14)
#define EXT_CLOCK_FREQ BIT(15)
static const struct device *const pit_counter_dev =
DEVICE_DT_GET(DT_NODELABEL(pit0));
struct counter_alarm_cfg alarm_cfg;
struct wdt_atcwdt200_config {
uintptr_t base;
};
struct wdt_atcwdt200_dev_data {
bool timeout_valid;
counter_alarm_callback_t counter_callback;
struct k_spinlock lock;
};
static int wdt_atcwdt200_disable(const struct device *dev);
static void wdt_counter_cb(const struct device *counter_dev, uint8_t chan_id,
uint32_t counter,
void *user_data)
{
const struct device *dev = DEVICE_DT_INST_GET(0);
struct wdt_atcwdt200_dev_data *wdt_data = dev->data;
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
k_spinlock_key_t key;
key = k_spin_lock(&wdt_data->lock);
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(WDT_RESTART_NUM, WDT_RESTAR(wdt_addr));
counter_set_channel_alarm(counter_dev, 2, &alarm_cfg);
k_spin_unlock(&wdt_data->lock, key);
}
/**
* @brief Set maximum length of timeout to watchdog
*
* @param dev Watchdog device struct
*/
static void wdt_atcwdt200_set_max_timeout(const struct device *dev)
{
struct wdt_atcwdt200_dev_data *data = dev->data;
k_spinlock_key_t key;
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
uint32_t reg, counter_freq;
key = k_spin_lock(&data->lock);
counter_freq = counter_get_frequency(pit_counter_dev);
alarm_cfg.flags = 0;
alarm_cfg.callback = wdt_counter_cb;
alarm_cfg.user_data = &alarm_cfg;
alarm_cfg.ticks = ((WDOGCFG_PERIOD_MAX * counter_freq) / EXT_CLOCK_FREQ) >> 1;
reg = WDT_CTRL_RSTTIME_POW_2_14;
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(reg, WDT_CTRL(wdt_addr));
data->timeout_valid = true;
k_spin_unlock(&data->lock, key);
}
static int wdt_atcwdt200_disable(const struct device *dev)
{
struct wdt_atcwdt200_dev_data *data = dev->data;
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
k_spinlock_key_t key;
uint32_t reg;
key = k_spin_lock(&data->lock);
reg = sys_read32(WDT_CTRL(wdt_addr));
reg &= ~(WDT_CTRL_RSTEN | WDT_CTRL_EN);
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(reg, WDT_CTRL(wdt_addr));
k_spin_unlock(&data->lock, key);
wdt_atcwdt200_set_max_timeout(dev);
counter_cancel_channel_alarm(pit_counter_dev, 2);
return 0;
}
static int wdt_atcwdt200_setup(const struct device *dev, uint8_t options)
{
struct wdt_atcwdt200_dev_data *data = dev->data;
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
k_spinlock_key_t key;
uint32_t reg;
uint32_t ret = 0;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
key = k_spin_lock(&data->lock);
reg = sys_read32(WDT_CTRL(wdt_addr));
reg |= (WDT_CTRL_RSTEN | WDT_CTRL_EN);
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ==
WDT_OPT_PAUSE_HALTED_BY_DBG) {
counter_cancel_channel_alarm(pit_counter_dev, 2);
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(reg, WDT_CTRL(wdt_addr));
goto out;
} else {
ret = counter_set_channel_alarm(pit_counter_dev, 2, &alarm_cfg);
if (ret != 0) {
ret = -EINVAL;
goto out;
}
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(reg, WDT_CTRL(wdt_addr));
}
out:
k_spin_unlock(&data->lock, key);
return ret;
}
/**
* @brief Calculates the watchdog counter value (wdogcmp0) and
* scaler (wdogscale) to be installed in the watchdog timer
*
* @param timeout Timeout value in milliseconds.
* @param scaler Pointer to return scaler power of 2
*
* @return Watchdog counter value
*/
static uint32_t wdt_atcwdt200_convtime(uint32_t timeout, uint32_t *scaler)
{
int i;
uint32_t rst_period, cnt;
cnt = (uint32_t)((timeout * EXT_CLOCK_FREQ) / 1000);
rst_period = cnt;
for (i = 0; i < 14 && cnt > 0; i++) {
cnt >>= 1;
}
*scaler = i;
return rst_period;
}
static int wdt_atcwdt200_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_atcwdt200_dev_data *data = dev->data;
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
k_spinlock_key_t key;
uint32_t rst_period, reg, counter_freq, scaler;
if (cfg->window.min != 0U || cfg->window.max == 0U) {
return -EINVAL;
}
counter_freq = counter_get_frequency(pit_counter_dev);
rst_period = wdt_atcwdt200_convtime(cfg->window.max, &scaler);
if (rst_period < 0 || WDOGCFG_PERIOD_MAX < rst_period) {
LOG_ERR("Unsupported watchdog timeout\n");
return -EINVAL;
}
wdt_atcwdt200_disable(dev);
key = k_spin_lock(&data->lock);
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
if (scaler < 7) {
reg = WDT_CTRL_RSTTIME_POW_2_7;
} else {
scaler = scaler - 7;
reg = scaler << 8;
}
alarm_cfg.flags = 0;
alarm_cfg.callback = wdt_counter_cb;
alarm_cfg.user_data = &alarm_cfg;
alarm_cfg.ticks = (((cfg->window.max * counter_freq) / 1000) >> 1);
break;
case WDT_FLAG_RESET_NONE:
case WDT_FLAG_RESET_CPU_CORE:
default:
LOG_ERR("Unsupported watchdog config flags\n");
k_spin_unlock(&data->lock, key);
return -ENOTSUP;
}
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(reg, WDT_CTRL(wdt_addr));
k_spin_unlock(&data->lock, key);
return 0;
}
static int wdt_atcwdt200_feed(const struct device *dev, int channel_id)
{
uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
ARG_UNUSED(channel_id);
sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
sys_write32(WDT_RESTART_NUM, WDT_RESTAR(wdt_addr));
return 0;
}
static const struct wdt_driver_api wdt_atcwdt200_api = {
.setup = wdt_atcwdt200_setup,
.disable = wdt_atcwdt200_disable,
.install_timeout = wdt_atcwdt200_install_timeout,
.feed = wdt_atcwdt200_feed,
};
static int wdt_atcwdt200_init(const struct device *dev)
{
struct wdt_atcwdt200_dev_data *data = dev->data;
data->timeout_valid = false;
data->counter_callback = wdt_counter_cb;
counter_start(pit_counter_dev);
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
wdt_atcwdt200_disable(dev);
#else
data->timeout_valid = true;
wdt_atcwdt200_set_max_timeout(dev);
wdt_atcwdt200_setup(dev, 0x0);
#endif
return 0;
}
static struct wdt_atcwdt200_dev_data wdt_atcwdt200_data;
static const struct wdt_atcwdt200_config wdt_atcwdt200_cfg = {
.base = DT_INST_REG_ADDR(0),
};
DEVICE_DT_INST_DEFINE(0, wdt_atcwdt200_init, NULL,
&wdt_atcwdt200_data, &wdt_atcwdt200_cfg, PRE_KERNEL_2,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_atcwdt200_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_andes_atcwdt200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,724 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdog_smartbond, CONFIG_WDT_LOG_LEVEL);
#define DT_DRV_COMPAT renesas_smartbond_watchdog
/* driver data */
struct wdog_smartbond_data {
/* Reload value calculated in setup */
uint32_t reload_val;
#ifdef CONFIG_WDT_SMARTBOND_NMI
const struct device *wdog_device;
wdt_callback_t callback;
#endif
};
static struct wdog_smartbond_data wdog_smartbond_dev_data = {};
static int wdg_smartbond_setup(const struct device *dev, uint8_t options)
{
ARG_UNUSED(dev);
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_ERR("Watchdog pause in sleep is not supported");
return -ENOTSUP;
}
return 0;
}
static int wdg_smartbond_disable(const struct device *dev)
{
ARG_UNUSED(dev);
if (SYS_WDOG->WATCHDOG_CTRL_REG & SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk) {
/* watchdog cannot be stopped once started when NMI_RST is 1 */
return -EPERM;
}
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
return 0;
}
#ifdef CONFIG_WDT_SMARTBOND_NMI
static void wdog_smartbond_nmi_isr(void)
{
if (wdog_smartbond_dev_data.callback) {
wdog_smartbond_dev_data.callback(wdog_smartbond_dev_data.wdog_device, 0);
}
}
#endif /* CONFIG_RUNTIME_NMI */
static int wdg_smartbond_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
struct wdog_smartbond_data *data = (struct wdog_smartbond_data *)(dev)->data;
uint32_t reload_val;
#ifndef CONFIG_WDT_SMARTBOND_NMI
if (config->callback != NULL) {
return -ENOTSUP;
}
#endif
/* For RC32K timer ticks every ~10ms, for RCX ~21ms */
if (CRG_TOP->CLK_RCX_REG & CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk) {
reload_val = config->window.max / 21;
} else {
reload_val = config->window.max / 10;
}
if (reload_val < 1 || reload_val >= 0x2000 || config->window.min != 0) {
/* Out of range supported by watchdog */
LOG_ERR("Watchdog timeout out of range");
return -EINVAL;
}
#if CONFIG_WDT_SMARTBOND_NMI
data->callback = config->callback;
data->wdog_device = dev;
z_arm_nmi_set_handler(wdog_smartbond_nmi_isr);
SYS_WDOG->WATCHDOG_CTRL_REG = 2;
#else
SYS_WDOG->WATCHDOG_CTRL_REG = 2 | SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk;
#endif
data->reload_val = reload_val;
while (SYS_WDOG->WATCHDOG_CTRL_REG & SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk) {
/* wait */
}
SYS_WDOG->WATCHDOG_REG = reload_val;
return 0;
}
static int wdg_smartbond_feed(const struct device *dev, int channel_id)
{
struct wdog_smartbond_data *data = (struct wdog_smartbond_data *)(dev)->data;
ARG_UNUSED(channel_id);
while (SYS_WDOG->WATCHDOG_CTRL_REG & SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk) {
/* wait */
}
SYS_WDOG->WATCHDOG_REG = data->reload_val;
return 0;
}
static const struct wdt_driver_api wdg_smartbond_api = {
.setup = wdg_smartbond_setup,
.disable = wdg_smartbond_disable,
.install_timeout = wdg_smartbond_install_timeout,
.feed = wdg_smartbond_feed,
};
static int wdg_smartbond_init(const struct device *dev)
{
ARG_UNUSED(dev);
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
#endif
return 0;
}
DEVICE_DT_INST_DEFINE(0, wdg_smartbond_init, NULL, &wdog_smartbond_dev_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdg_smartbond_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 960 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_WATCHDOG_WWDG_STM32_H_
#define ZEPHYR_DRIVERS_WATCHDOG_WWDG_STM32_H_
#include <zephyr/types.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
/**
* @brief Driver for System Window Watchdog (WWDG) for STM32 MCUs
*
* The driver targets all STM32 SoCs. For details please refer to
* an appropriate reference manual and look for chapter called:
*
* System window watchdog (WWDG)
*
*/
/* driver configuration */
struct wwdg_stm32_config {
struct stm32_pclken pclken;
WWDG_TypeDef *Instance;
};
/* driver data */
struct wwdg_stm32_data {
/* WWDG reset counter */
uint8_t counter;
/* WWDG user defined callback on EWI */
wdt_callback_t callback;
};
#define WWDG_STM32_CFG(dev) \
((const struct wwdg_stm32_config *const)(dev)->config)
#define WWDG_STM32_DATA(dev) \
((struct wwdg_stm32_data *const)(dev)->data)
#define WWDG_STM32_STRUCT(dev) \
((WWDG_TypeDef *)(WWDG_STM32_CFG(dev))->Instance)
#endif /* ZEPHYR_DRIVERS_WATCHDOG_WWDG_STM32_H_ */
``` | /content/code_sandbox/drivers/watchdog/wdt_wwdg_stm32.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 317 |
```unknown
config WDT_CC32XX
bool "Watchdog Driver for cc32xx family of MCUs"
default y
depends on DT_HAS_TI_CC32XX_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Watchdog for cc32xx family of MCUs
config WDT_CC32XX_INITIAL_TIMEOUT
int "Value for WDT timeout in ms"
depends on WDT_CC32XX
default 2000
range 1 53687
help
Max value depend on system frequency.
80 Mhz: 0xFFFFFFFF / (80e9 / 1000)
``` | /content/code_sandbox/drivers/watchdog/Kconfig.cc32xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
config WDT_NPM1300
bool "nPM1300 Watchdog driver"
default y
depends on DT_HAS_NORDIC_NPM1300_WDT_ENABLED
select I2C
select MFD
help
Enable nPM1300 Watchdog driver
config WDT_NPM1300_INIT_PRIORITY
int "nPM1300 Watchdog driver initialization priority"
depends on WDT_NPM1300
default 85
help
Initialization priority for the nPM1300 Watchdog driver.
It must be greater than GPIO_NPM1300_INIT_PRIORITY.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.npm1300 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```unknown
# ARM CMSDK (Cortex-M System Design Kit) AHB WDOG cfg
config WDOG_CMSDK_APB
bool "CMSDK APB Watchdog Driver for ARM family of MCUs"
default y
depends on DT_HAS_ARM_CMSDK_WATCHDOG_ENABLED
depends on RUNTIME_NMI
help
Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM
family of MCUs.
config WDOG_CMSDK_APB_START_AT_BOOT
bool "Start Watchdog during boot"
depends on WDOG_CMSDK_APB
help
Enable this setting to allow WDOG to be automatically started
during device initialization. Note that once WDOG is started
it must be reloaded before the counter reaches 0, otherwise
the MCU will be reset.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.cmsdk_apb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 174 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_iwdg.h>
#include <stm32_ll_system.h>
#include <errno.h>
#include "wdt_iwdg_stm32.h"
#define IWDG_PRESCALER_MIN (4U)
#if defined(LL_IWDG_PRESCALER_1024)
#define IWDG_PRESCALER_MAX (1024U)
#else
#define IWDG_PRESCALER_MAX (256U)
#endif
#define IWDG_RELOAD_MIN (0x0000U)
#define IWDG_RELOAD_MAX (0x0FFFU)
/* Minimum timeout in microseconds. */
#define IWDG_TIMEOUT_MIN (IWDG_PRESCALER_MIN * (IWDG_RELOAD_MIN + 1U) \
* USEC_PER_SEC / LSI_VALUE)
/* Maximum timeout in microseconds. */
#define IWDG_TIMEOUT_MAX ((uint64_t)IWDG_PRESCALER_MAX * \
(IWDG_RELOAD_MAX + 1U) * \
USEC_PER_SEC / LSI_VALUE)
#define IS_IWDG_TIMEOUT(__TIMEOUT__) \
(((__TIMEOUT__) >= IWDG_TIMEOUT_MIN) && \
((__TIMEOUT__) <= IWDG_TIMEOUT_MAX))
/*
* Status register needs 5 LSI clock cycles divided by prescaler to be updated.
* With highest prescaler and considering clock variation, we will wait
* maximum 6 cycles (48 ms at 32 kHz) for register update.
*/
#define IWDG_SR_UPDATE_TIMEOUT (6U * IWDG_PRESCALER_MAX * \
MSEC_PER_SEC / LSI_VALUE)
/**
* @brief Calculates prescaler & reload values.
*
* @param timeout Timeout value in microseconds.
* @param prescaler Pointer to prescaler value.
* @param reload Pointer to reload value.
*/
static void iwdg_stm32_convert_timeout(uint32_t timeout,
uint32_t *prescaler,
uint32_t *reload)
{
uint16_t divider = 4U;
uint8_t shift = 0U;
/* Convert timeout to LSI clock ticks. */
uint32_t ticks = (uint64_t)timeout * LSI_VALUE / USEC_PER_SEC;
while ((ticks / divider) > IWDG_RELOAD_MAX) {
shift++;
divider = 4U << shift;
}
/*
* Value of the 'shift' variable corresponds to the
* defines of LL_IWDG_PRESCALER_XX type.
*/
*prescaler = shift;
*reload = (uint32_t)(ticks / divider) - 1U;
}
static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
{
struct iwdg_stm32_data *data = IWDG_STM32_DATA(dev);
IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
uint32_t tickstart;
/* Deactivate running when debugger is attached. */
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
#if defined(CONFIG_SOC_SERIES_STM32F0X)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
#elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
#endif
#if defined(CONFIG_SOC_SERIES_STM32H7X)
LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP);
#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP);
#else
LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);
#endif
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
return -ENOTSUP;
}
/* Enable the IWDG now and write IWDG registers at the same time */
LL_IWDG_Enable(iwdg);
LL_IWDG_EnableWriteAccess(iwdg);
/* Write the prescaler and reload counter to the IWDG registers*/
LL_IWDG_SetPrescaler(iwdg, data->prescaler);
LL_IWDG_SetReloadCounter(iwdg, data->reload);
tickstart = k_uptime_get_32();
/* Wait for the update operation completed */
while (LL_IWDG_IsReady(iwdg) == 0) {
if ((k_uptime_get_32() - tickstart) > IWDG_SR_UPDATE_TIMEOUT) {
return -ENODEV;
}
}
/* Reload counter just before leaving */
LL_IWDG_ReloadCounter(iwdg);
return 0;
}
static int iwdg_stm32_disable(const struct device *dev)
{
/* watchdog cannot be stopped once started */
ARG_UNUSED(dev);
return -EPERM;
}
static int iwdg_stm32_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
struct iwdg_stm32_data *data = IWDG_STM32_DATA(dev);
uint32_t timeout = config->window.max * USEC_PER_MSEC;
uint32_t prescaler = 0U;
uint32_t reload = 0U;
if (config->callback != NULL) {
return -ENOTSUP;
}
/* Calculating parameters to be applied later, on setup */
iwdg_stm32_convert_timeout(timeout, &prescaler, &reload);
if (!(IS_IWDG_TIMEOUT(timeout) && IS_IWDG_PRESCALER(prescaler) &&
IS_IWDG_RELOAD(reload))) {
/* One of the parameters provided is invalid */
return -EINVAL;
}
/* Store the calculated values to write in the iwdg registers */
data->prescaler = prescaler;
data->reload = reload;
/* Do not enable and update the iwdg here but during wdt_setup() */
return 0;
}
static int iwdg_stm32_feed(const struct device *dev, int channel_id)
{
IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
ARG_UNUSED(channel_id);
LL_IWDG_ReloadCounter(iwdg);
return 0;
}
static const struct wdt_driver_api iwdg_stm32_api = {
.setup = iwdg_stm32_setup,
.disable = iwdg_stm32_disable,
.install_timeout = iwdg_stm32_install_timeout,
.feed = iwdg_stm32_feed,
};
static int iwdg_stm32_init(const struct device *dev)
{
#ifndef CONFIG_WDT_DISABLE_AT_BOOT
struct wdt_timeout_cfg config = {
.window.max = CONFIG_IWDG_STM32_INITIAL_TIMEOUT
};
/* Watchdog should be configured and started by `wdt_setup`*/
iwdg_stm32_install_timeout(dev, &config);
iwdg_stm32_setup(dev, 0); /* no option specified */
#endif
/*
* The ST production value for the option bytes where WDG_SW bit is
* present is 0x00FF55AA, namely the Software watchdog mode is
* enabled by default.
* If the IWDG is started by either hardware option or software access,
* the LSI oscillator is forced ON and cannot be disabled.
*
* t_IWDG(ms) = t_LSI(ms) x 4 x 2^(IWDG_PR[2:0]) x (IWDG_RLR[11:0] + 1)
*/
return 0;
}
static struct iwdg_stm32_data iwdg_stm32_dev_data = {
.Instance = (IWDG_TypeDef *)DT_INST_REG_ADDR(0)
};
DEVICE_DT_INST_DEFINE(0, iwdg_stm32_init, NULL,
&iwdg_stm32_dev_data, NULL,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&iwdg_stm32_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_iwdg_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,829 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_tps382x
#include <errno.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_ti_tps382x, CONFIG_WDT_LOG_LEVEL);
struct ti_tps382x_config {
struct gpio_dt_spec wdi_gpio;
int timeout;
};
static int ti_tps382x_init(const struct device *dev)
{
const struct ti_tps382x_config *config = dev->config;
if (!gpio_is_ready_dt(&config->wdi_gpio)) {
LOG_ERR("WDI gpio not ready");
return -ENODEV;
}
return 0;
}
static int ti_tps382x_setup(const struct device *dev, uint8_t options)
{
const struct ti_tps382x_config *config = dev->config;
return gpio_pin_configure_dt(&config->wdi_gpio, GPIO_OUTPUT);
}
static int ti_tps382x_disable(const struct device *dev)
{
const struct ti_tps382x_config *config = dev->config;
/* The watchdog timer can be disabled by disconnecting the WDI pin from
* the system. Do this by changing the gpio to an input (tri-state).
*/
return gpio_pin_configure_dt(&config->wdi_gpio, GPIO_INPUT);
}
static int ti_tps382x_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct ti_tps382x_config *config = dev->config;
if (cfg->window.max != config->timeout) {
LOG_ERR("Upper limit of watchdog timeout must be %d not %u",
config->timeout, cfg->window.max);
return -EINVAL;
} else if (cfg->window.min != 0) {
LOG_ERR("Window timeouts not supported");
return -EINVAL;
} else if (cfg->callback != NULL) {
LOG_ERR("Callbacks not supported");
return -EINVAL;
}
return 0;
}
static int ti_tps382x_feed(const struct device *dev, int channel_id)
{
const struct ti_tps382x_config *config = dev->config;
return gpio_pin_toggle_dt(&config->wdi_gpio);
}
static const struct wdt_driver_api ti_tps382x_api = {
.setup = ti_tps382x_setup,
.disable = ti_tps382x_disable,
.install_timeout = ti_tps382x_install_timeout,
.feed = ti_tps382x_feed,
};
#define WDT_TI_TPS382X_INIT(n) \
static const struct ti_tps382x_config ti_tps382x_##n##config = { \
.wdi_gpio = GPIO_DT_SPEC_INST_GET(n, wdi_gpios), \
.timeout = DT_INST_PROP(n, timeout_period), \
}; \
\
DEVICE_DT_INST_DEFINE( \
n, ti_tps382x_init, NULL, NULL, &ti_tps382x_##n##config, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&ti_tps382x_api \
);
DT_INST_FOREACH_STATUS_OKAY(WDT_TI_TPS382X_INIT);
``` | /content/code_sandbox/drivers/watchdog/wdt_ti_tps382x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 686 |
```c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
/**
* @file
*
* @brief Intel ACE per-core watchdogs driver
*
* The ace platform has a set of designware watchdogs, one for each core. This driver is responsible
* for finding the base addresses of subordinate devices, controlling the pause signal and handling
* interrupts. The registers from the DSP Core Watch Dog Timer Control & Status block are used for
* this purpose. This block is shared by all per-core watchdogs.
*
* The base addresses of the subordinate watchdogs are read from the control registers. As a result,
* in the device tree we have only one base address for the intel watchdog.
*
* The designware watchdog only supports a hardware pause signal. It cannot be paused
* programmatically. On ace platform there are GPIO-like registers that allows control of a hardware
* pause signal for subordinate watchdogs.
*
* All subordinate watchdog devices share the same interrupt number. Each watchdog reports
* an interrupt to the core to which it has been assigned. The same interrupt number cannot
* be used by multiple devices in the device tree. This driver handles interrupts from all
* subordinate watchdogs and identifies which device signal it.
*/
#define DT_DRV_COMPAT intel_adsp_watchdog
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys_clock.h>
#include <zephyr/math/ilog2.h>
#include "wdt_dw.h"
#include "wdt_dw_common.h"
#include "wdt_intel_adsp.h"
LOG_MODULE_REGISTER(wdt_intel_adsp, CONFIG_WDT_LOG_LEVEL);
#define DEV_NODE DT_INST(0, DT_DRV_COMPAT)
#define WDT_INTEL_ADSP_INTERRUPT_SUPPORT DT_NODE_HAS_PROP(DEV_NODE, interrupts)
/* Device run time data */
struct intel_adsp_wdt_dev_data {
uint32_t core_wdt[CONFIG_MP_MAX_NUM_CPUS];
uint32_t period_cfg;
bool allow_reset;
#if WDT_INTEL_ADSP_INTERRUPT_SUPPORT
wdt_callback_t callback;
#endif
};
/* Device constant configuration parameters */
struct intel_adsp_wdt_dev_cfg {
uint32_t base;
uint32_t clk_freq;
};
static int intel_adsp_wdt_setup(const struct device *dev, uint8_t options)
{
const struct intel_adsp_wdt_dev_cfg *const dev_config = dev->config;
struct intel_adsp_wdt_dev_data *const dev_data = dev->data;
unsigned int i;
int ret;
ret = dw_wdt_check_options(options);
if (ret) {
return ret;
}
for (i = 0; i < arch_num_cpus(); i++) {
ret = dw_wdt_configure(dev_data->core_wdt[i], dev_data->period_cfg);
if (ret) {
return ret;
}
#if WDT_INTEL_ADSP_INTERRUPT_SUPPORT
dw_wdt_response_mode_set(dev_data->core_wdt[i], !!dev_data->callback);
#endif
intel_adsp_wdt_reset_set(dev_config->base, i, dev_data->allow_reset);
}
return 0;
}
static int intel_adsp_wdt_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
const struct intel_adsp_wdt_dev_cfg *const dev_config = dev->config;
struct intel_adsp_wdt_dev_data *const dev_data = dev->data;
int ret;
#if WDT_INTEL_ADSP_INTERRUPT_SUPPORT
dev_data->callback = config->callback;
#else
if (config->callback) {
LOG_ERR("Interrupt is not configured, can't set a callback.");
return -ENOTSUP;
}
#endif
ret = dw_wdt_calc_period(dev_data->core_wdt[0], dev_config->clk_freq, config,
&dev_data->period_cfg);
if (ret) {
return ret;
}
if (config->flags & WDT_FLAG_RESET_CPU_CORE) {
dev_data->allow_reset = true;
}
return 0;
}
static int intel_adsp_wdt_feed(const struct device *dev, int channel_id)
{
struct intel_adsp_wdt_dev_data *const dev_data = dev->data;
if (channel_id >= arch_num_cpus()) {
return -EINVAL;
}
dw_wdt_counter_restart(dev_data->core_wdt[channel_id]);
return 0;
}
#if WDT_INTEL_ADSP_INTERRUPT_SUPPORT
static void intel_adsp_wdt_isr(const struct device *dev)
{
struct intel_adsp_wdt_dev_data *const dev_data = dev->data;
const uint32_t cpu = arch_proc_id();
const uint32_t base = dev_data->core_wdt[cpu];
if (dw_wdt_interrupt_status_register_get(base)) {
if (dev_data->callback) {
dev_data->callback(dev, cpu);
}
dw_wdt_clear_interrupt(base);
}
}
#endif
static int intel_adsp_wdt_init(const struct device *dev)
{
const unsigned int reset_pulse_length =
ilog2(DT_PROP(DEV_NODE, reset_pulse_length)) - 1;
const struct intel_adsp_wdt_dev_cfg *const dev_config = dev->config;
struct intel_adsp_wdt_dev_data *const dev_data = dev->data;
unsigned int i;
int ret;
for (i = 0; i < arch_num_cpus(); i++) {
dev_data->core_wdt[i] = intel_adsp_wdt_pointer_get(dev_config->base, i);
ret = dw_wdt_probe(dev_data->core_wdt[i], reset_pulse_length);
if (ret) {
return ret;
}
}
#if WDT_INTEL_ADSP_INTERRUPT_SUPPORT
IRQ_CONNECT(DT_IRQN(DEV_NODE), DT_IRQ(DEV_NODE, priority), intel_adsp_wdt_isr,
DEVICE_DT_GET(DEV_NODE), DT_IRQ(DEV_NODE, sense));
irq_enable(DT_IRQN(DEV_NODE));
#endif
return 0;
}
/**
* @brief Pause watchdog operation
*
* Sets the pause signal to stop the watchdog timing
*
* @param dev Pointer to the device structure
* @param channel_id Channel identifier
*/
int intel_adsp_watchdog_pause(const struct device *dev, const int channel_id)
{
const struct intel_adsp_wdt_dev_cfg *const dev_config = dev->config;
if (channel_id >= arch_num_cpus()) {
return -EINVAL;
}
intel_adsp_wdt_pause(dev_config->base, channel_id);
return 0;
}
/**
* @brief Resume watchdog operation
*
* Clears the pause signal to resume the watchdog timing
*
* @param dev Pointer to the device structure
* @param channel_id Channel identifier
*/
int intel_adsp_watchdog_resume(const struct device *dev, const int channel_id)
{
const struct intel_adsp_wdt_dev_cfg *const dev_config = dev->config;
if (channel_id >= arch_num_cpus()) {
return -EINVAL;
}
intel_adsp_wdt_resume(dev_config->base, channel_id);
return 0;
}
int dw_wdt_disable(const struct device *dev)
{
return -ENOTSUP;
}
static const struct wdt_driver_api intel_adsp_wdt_api = {
.setup = intel_adsp_wdt_setup,
.disable = dw_wdt_disable,
.install_timeout = intel_adsp_wdt_install_timeout,
.feed = intel_adsp_wdt_feed,
};
#if !(DT_NODE_HAS_PROP(DEV_NODE, clock_frequency) || DT_NODE_HAS_PROP(DEV_NODE, clocks))
#error Clock frequency not configured!
#endif
static const struct intel_adsp_wdt_dev_cfg wdt_intel_adsp_config = {
.base = DT_REG_ADDR(DEV_NODE),
COND_CODE_1(DT_NODE_HAS_PROP(DEV_NODE, clock_frequency),
(.clk_freq = DT_PROP(DEV_NODE, clock_frequency)),
(.clk_freq = DT_PROP_BY_PHANDLE(DEV_NODE, clocks, clock_frequency))
),
};
static struct intel_adsp_wdt_dev_data wdt_intel_adsp_data;
DEVICE_DT_DEFINE(DEV_NODE, &intel_adsp_wdt_init, NULL, &wdt_intel_adsp_data, &wdt_intel_adsp_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &intel_adsp_wdt_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_intel_adsp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,757 |
```unknown
# Infineon CAT1 Watchdog configuration options
# an affiliate of Cypress Semiconductor Corporation
#
config WDT_INFINEON_CAT1
bool "Infineon CAT1 Watchdog Driver"
default y
depends on DT_HAS_INFINEON_CAT1_WATCHDOG_ENABLED
select USE_INFINEON_WDT
help
Enable Watchdog driver for Infineon CAT1 devices.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.ifx_cat1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# Infineon XMC4xxx WDT configuration
config WDT_XMC4XXX
bool "Infineon XMC4xxx MCU Family Watchdog (WDT) Driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for Infineon XMC4xxx MCUs.
if WDT_XMC4XXX && !WDT_DISABLE_AT_BOOT
config WDT_XMC4XXX_DEFAULT_TIMEOUT_MAX_MS
int "Default watchdog timeout to use at startup"
default 20000
help
Default watchdog timeout to use if the watchdog is not disabled
at startup.
endif
``` | /content/code_sandbox/drivers/watchdog/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```unknown
# Atmel SAM0 WDT configuration
config WDT_SAM0
bool "Atmel SAM0 series Watchdog (WDT) Driver"
default y
depends on DT_HAS_ATMEL_SAM0_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
Enable WDT driver for Atmel SAM0 MCUs.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_watchdog
/**
* @brief Watchdog (WDT) Driver for Atmel SAM MCUs
*
* Note:
* - Once the watchdog disable bit is set, it cannot be cleared till next
* power reset, i.e, the watchdog cannot be started once stopped.
* - Since the MCU boots with WDT enabled, the CONFIG_WDT_DISABLE_AT_BOOT
* is set default at boot and watchdog module is disabled in the MCU for
* systems that don't need watchdog functionality.
* - If the application needs to use the watchdog in the system, then
* CONFIG_WDT_DISABLE_AT_BOOT must be unset in the app's config file
*/
#include <zephyr/drivers/watchdog.h>
#include <zephyr/irq.h>
#include <soc.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_sam);
#define SAM_PRESCALAR 128
#define WDT_MAX_VALUE 4095
/* Device constant configuration parameters */
struct wdt_sam_dev_cfg {
Wdt *regs;
};
struct wdt_sam_dev_data {
wdt_callback_t cb;
uint32_t mode;
bool timeout_valid;
bool mode_set;
};
static struct wdt_sam_dev_data wdt_sam_data = { 0 };
static void wdt_sam_isr(const struct device *dev)
{
const struct wdt_sam_dev_cfg *config = dev->config;
uint32_t wdt_sr;
Wdt * const wdt = config->regs;
struct wdt_sam_dev_data *data = dev->data;
/* Clear status bit to acknowledge interrupt by dummy read. */
wdt_sr = wdt->WDT_SR;
data->cb(dev, 0);
}
/**
* @brief Calculates the watchdog counter value (WDV)
* to be installed in the watchdog timer
*
* @param timeout Timeout value in milliseconds.
* @param slow clock on board in Hz.
*/
int wdt_sam_convert_timeout(uint32_t timeout, uint32_t sclk)
{
uint32_t max, min;
timeout = timeout * 1000U;
min = (SAM_PRESCALAR * 1000000) / sclk;
max = min * WDT_MAX_VALUE;
if ((timeout < min) || (timeout > max)) {
LOG_ERR("Invalid timeout value allowed range:"
"%d ms to %d ms", min / 1000U, max / 1000U);
return -EINVAL;
}
return WDT_MR_WDV(timeout / min);
}
static int wdt_sam_disable(const struct device *dev)
{
const struct wdt_sam_dev_cfg *config = dev->config;
Wdt * const wdt = config->regs;
struct wdt_sam_dev_data *data = dev->data;
/* since Watchdog mode register is 'write-once', we can't disable if
* someone has already set the mode register
*/
if (data->mode_set) {
return -EPERM;
}
/* do we handle -EFAULT here */
/* Watchdog Mode register is 'write-once' only register.
* Once disabled, it cannot be enabled until the device is reset
*/
wdt->WDT_MR |= WDT_MR_WDDIS;
data->mode_set = true;
return 0;
}
static int wdt_sam_setup(const struct device *dev, uint8_t options)
{
const struct wdt_sam_dev_cfg *config = dev->config;
Wdt * const wdt = config->regs;
struct wdt_sam_dev_data *data = dev->data;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
/* since Watchdog mode register is 'write-once', we can't set if
* someone has already set the mode register
*/
if (data->mode_set) {
return -EPERM;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) == WDT_OPT_PAUSE_IN_SLEEP) {
data->mode |= WDT_MR_WDIDLEHLT;
}
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ==
WDT_OPT_PAUSE_HALTED_BY_DBG) {
data->mode |= WDT_MR_WDDBGHLT;
}
wdt->WDT_MR = data->mode;
data->mode_set = true;
return 0;
}
static int wdt_sam_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
uint32_t wdt_mode = 0U;
int timeout_value;
struct wdt_sam_dev_data *data = dev->data;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if (cfg->window.min != 0U) {
return -EINVAL;
}
/*
* Convert time to cycles. SAM3X SoC doesn't supports window
* timeout config. So the api expects the timeout to be filled
* in the max field of the timeout config.
*/
timeout_value = wdt_sam_convert_timeout(cfg->window.max,
(uint32_t) CHIP_FREQ_XTAL_32K);
if (timeout_value < 0) {
return -EINVAL;
}
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
/*A Watchdog fault (underflow or error) activates all resets */
wdt_mode = WDT_MR_WDRSTEN; /* WDT reset enable */
break;
case WDT_FLAG_RESET_NONE:
/* A Watchdog fault (underflow or error) asserts interrupt. */
if (cfg->callback) {
wdt_mode = WDT_MR_WDFIEN; /* WDT fault interrupt. */
data->cb = cfg->callback;
} else {
LOG_ERR("Invalid(NULL) ISR callback passed\n");
return -EINVAL;
}
break;
/* Processor only reset mode not available in same70 series */
#ifdef WDT_MR_WDRPROC
case WDT_FLAG_RESET_CPU_CORE:
/*A Watchdog fault activates the processor reset*/
LOG_DBG("Configuring reset CPU only mode\n");
wdt_mode = WDT_MR_WDRSTEN | /* WDT reset enable */
WDT_MR_WDRPROC; /* WDT reset processor only*/
break;
#endif
default:
LOG_ERR("Unsupported watchdog config Flag\n");
return -ENOTSUP;
}
data->mode = wdt_mode |
WDT_MR_WDV(timeout_value) |
WDT_MR_WDD(timeout_value);
data->timeout_valid = true;
return 0;
}
static int wdt_sam_feed(const struct device *dev, int channel_id)
{
const struct wdt_sam_dev_cfg *config = dev->config;
/*
* On watchdog restart the Watchdog counter is immediately
* reloaded/fed with the 12-bit watchdog counter
* value from WDT_MR and restarted
*/
Wdt * const wdt = config->regs;
wdt->WDT_CR |= WDT_CR_KEY_PASSWD | WDT_CR_WDRSTT;
return 0;
}
static const struct wdt_driver_api wdt_sam_api = {
.setup = wdt_sam_setup,
.disable = wdt_sam_disable,
.install_timeout = wdt_sam_install_timeout,
.feed = wdt_sam_feed,
};
static const struct wdt_sam_dev_cfg wdt_sam_cfg = {
.regs = (Wdt *)DT_INST_REG_ADDR(0),
};
static void wdt_sam_irq_config(void)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority), wdt_sam_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
}
static int wdt_sam_init(const struct device *dev)
{
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
wdt_sam_disable(dev);
#endif
wdt_sam_irq_config();
return 0;
}
DEVICE_DT_INST_DEFINE(0, wdt_sam_init, NULL,
&wdt_sam_data, &wdt_sam_cfg, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sam_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,797 |
```unknown
menuconfig WDT_NXP_FS26
bool "NXP FS26 SBC watchdog driver"
default y
depends on DT_HAS_NXP_FS26_WDOG_ENABLED
select SPI
select GPIO
help
Enable the NXP FS26 SBC watchdog driver.
if WDT_NXP_FS26
config WDT_NXP_FS26_INIT_PRIORITY
int
default 80
help
Device driver initialization priority. Device is connected to SPI bus,
so it has to be initialized after SPI driver.
config WDT_NXP_FS26_ERROR_COUNTER_LIMIT
int "Watchdog error counter limit"
default 6
help
Sets the maximum value of the watchdog error counter. Each time a
watchdog failure occurs, the device increments this counter by 2. The
watchdog error counter is decremented by 1 each time the watchdog is
properly refreshed.
Possible values are 2, 4, 6, 8.
config WDT_NXP_FS26_REFRESH_COUNTER_LIMIT
int "Watchdog refresh counter limit"
default 6
help
Sets the maximum value of the watchdog refresh counter. Each time the
watchdog is properly refreshed, this counter is incremented by 1. Each
time this counter reaches its maximum value and if the next refresh is
also good, the fault error counter is decremented by 1. Each time
there is a bad watchdog refresh, this counter is reset to 0.
Possible values are 1, 2, 4, 6.
config WDT_NXP_FS26_SEED
hex "Watchdog seed"
default 0x5ab2
range 0x0 0xffff
help
Seed to pass to the device. This property can be used with both simple
and challenger watchdog configurations. In simple watchdog
configuration, values 0xffff and 0x0000 are not allowed. In challenger
watchdog configuration, value 0x0000 is not allowed.
config WDT_NXP_FS26_EXIT_DEBUG_MODE
bool "Exit DEBUG mode"
help
If the device is started in DEBUG mode, the driver will exit this mode
so that the watchdog is enabled. Otherwise, if the device is in DEBUG
mode and this driver is enabled, it will fail to initialize.
config WDT_NXP_FS26_INT_THREAD_STACK_SIZE
int "Stack size for internal interrupt handler"
default 1024
help
Size of the stack used for internal thread which is ran for
interrupt processing.
config WDT_NXP_FS26_INT_THREAD_PRIO
int "Priority for internal incoming packet handler"
default 2
help
Priority level for internal cooperative thread which is ran for
interrupt processing.
endif # WDT_NXP_FS26
``` | /content/code_sandbox/drivers/watchdog/Kconfig.nxp_fs26 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 583 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_fwdgt
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys_clock.h>
#include <gd32_fwdgt.h>
LOG_MODULE_REGISTER(wdt_fwdgt_gd32, CONFIG_WDT_LOG_LEVEL);
#define FWDGT_RELOAD_MAX (0xFFFU)
#define FWDGT_PRESCALER_MAX (256U)
#if defined(CONFIG_GD32_HAS_IRC_32K)
#define RCU_IRC_LOW_SPEED RCU_IRC32K
#elif defined(CONFIG_GD32_HAS_IRC_40K)
#define RCU_IRC_LOW_SPEED RCU_IRC40K
#else
#error IRC frequency was not configured
#endif
#define IS_VALID_FWDGT_PRESCALER(psc) \
(((psc) == FWDGT_PSC_DIV4) || ((psc) == FWDGT_PSC_DIV8) || \
((psc) == FWDGT_PSC_DIV16) || ((psc) == FWDGT_PSC_DIV32) || \
((psc) == FWDGT_PSC_DIV64) || ((psc) == FWDGT_PSC_DIV128) || \
((psc) == FWDGT_PSC_DIV256))
#define FWDGT_INITIAL_TIMEOUT DT_INST_PROP(0, initial_timeout_ms)
#if (FWDGT_INITIAL_TIMEOUT <= 0)
#error Must be initial-timeout > 0
#elif (FWDGT_INITIAL_TIMEOUT > \
(FWDGT_PRESCALER_MAX * FWDGT_RELOAD_MAX * MSEC_PER_SEC / \
CONFIG_GD32_LOW_SPEED_IRC_FREQUENCY))
#error Must be initial-timeout <= (256 * 4095 * 1000 / GD32_LOW_SPEED_IRC_FREQUENCY)
#endif
/**
* @brief Calculates FWDGT config value from timeout.
*
* @param timeout Timeout value in milliseconds.
* @param prescaler Pointer to the storage of prescaler value.
* @param reload Pointer to the storage of reload value.
*
* @return 0 on success, -EINVAL if the timeout is out of range
*/
static int gd32_fwdgt_calc_timeout(uint32_t timeout, uint32_t *prescaler,
uint32_t *reload)
{
uint16_t divider = 4U;
uint8_t shift = 0U;
uint32_t ticks = (uint64_t)CONFIG_GD32_LOW_SPEED_IRC_FREQUENCY *
timeout / MSEC_PER_SEC;
while ((ticks / divider) > FWDGT_RELOAD_MAX) {
shift++;
divider = 4U << shift;
}
if (!IS_VALID_FWDGT_PRESCALER(PSC_PSC(shift)) || timeout == 0U) {
return -EINVAL;
}
/* convert the 'shift' to prescaler value */
*prescaler = PSC_PSC(shift);
*reload = (ticks / divider) - 1U;
return 0;
}
static int gd32_fwdgt_setup(const struct device *dev, uint8_t options)
{
ARG_UNUSED(dev);
if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) != 0U) {
#if CONFIG_GD32_DBG_SUPPORT
dbg_periph_enable(DBG_FWDGT_HOLD);
#else
LOG_ERR("Debug support not enabled");
return -ENOTSUP;
#endif
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0U) {
LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP not supported");
return -ENOTSUP;
}
fwdgt_enable();
return 0;
}
static int gd32_fwdgt_disable(const struct device *dev)
{
/* watchdog cannot be stopped once started */
ARG_UNUSED(dev);
return -EPERM;
}
static int gd32_fwdgt_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
uint32_t prescaler = 0U;
uint32_t reload = 0U;
ErrStatus errstat = ERROR;
/* Callback is not supported by FWDGT */
if (config->callback != NULL) {
LOG_ERR("callback not supported by FWDGT");
return -ENOTSUP;
}
/* Calculate prescaler and reload value from timeout value */
if (gd32_fwdgt_calc_timeout(config->window.max, &prescaler,
&reload) != 0) {
LOG_ERR("window max is out of range");
return -EINVAL;
}
/* Configure and run FWDGT */
fwdgt_write_enable();
errstat = fwdgt_config(reload, prescaler);
if (errstat != SUCCESS) {
LOG_ERR("fwdgt_config() failed: %d", errstat);
return -EINVAL;
}
fwdgt_write_disable();
return 0;
}
static int gd32_fwdgt_feed(const struct device *dev, int channel_id)
{
ARG_UNUSED(channel_id);
fwdgt_counter_reload();
return 0;
}
static const struct wdt_driver_api fwdgt_gd32_api = {
.setup = gd32_fwdgt_setup,
.disable = gd32_fwdgt_disable,
.install_timeout = gd32_fwdgt_install_timeout,
.feed = gd32_fwdgt_feed,
};
static int gd32_fwdgt_init(const struct device *dev)
{
int ret = 0;
/* Turn on and wait stabilize system clock oscillator. */
rcu_osci_on(RCU_IRC_LOW_SPEED);
while (!rcu_osci_stab_wait(RCU_IRC_LOW_SPEED)) {
}
#if !defined(CONFIG_WDT_DISABLE_AT_BOOT)
const struct wdt_timeout_cfg config = {
.window.max = FWDGT_INITIAL_TIMEOUT
};
ret = gd32_fwdgt_install_timeout(dev, &config);
#endif
return ret;
}
DEVICE_DT_INST_DEFINE(0, gd32_fwdgt_init, NULL, NULL, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &fwdgt_gd32_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_fwdgt_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,253 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_tco_wdt
#include <zephyr/kernel.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(wdt_tco, CONFIG_WDT_LOG_LEVEL);
#define BASE(d) ((struct tco_config *)(d)->config)->base
#define TCO_RLD(d) (BASE(d) + 0x00) /* TCO Timer Reload/Curr. Value */
#define TCO_DAT_IN(d) (BASE(d) + 0x02) /* TCO Data In Register */
#define TCO_DAT_OUT(d) (BASE(d) + 0x03) /* TCO Data Out Register */
#define TCO1_STS(d) (BASE(d) + 0x04) /* TCO1 Status Register */
#define TCO2_STS(d) (BASE(d) + 0x06) /* TCO2 Status Register */
#define TCO1_CNT(d) (BASE(d) + 0x08) /* TCO1 Control Register */
#define TCO2_CNT(d) (BASE(d) + 0x0a) /* TCO2 Control Register */
#define TCO_MSG(d) (BASE(d) + 0x0c) /* TCO Message Registers */
#define TCO_WDSTATUS(d) (BASE(d) + 0x0e) /* TCO Watchdog Status Register */
#define TCO_TMR(d) (BASE(d) + 0x12) /* TCO Timer Register */
/* TCO1_STS bits */
#define STS_NMI2SMI BIT(0)
#define STS_OS_TCO_SMI BIT(1)
#define STS_TCO_INT BIT(2)
#define STS_TIMEOUT BIT(3)
#define STS_NEWCENTURY BIT(7)
#define STS_BIOSWR BIT(8)
#define STS_CPUSCI BIT(9)
#define STS_CPUSMI BIT(10)
#define STS_CPUSERR BIT(12)
#define STS_SLVSEL BIT(13)
/* TCO2_STS bits */
#define STS_INTRD_DET BIT(0)
#define STS_SECOND_TO BIT(1)
#define STS_NRSTRAP BIT(2)
#define STS_SMLINK_SLAVE_SMI BIT(3)
/* TCO1_CNT bits */
#define CNT_NR_MSUS BIT(0)
#define CNT_NMI_NOW BIT(8)
#define CNT_NMI2SMI_EN BIT(9)
#define CNT_TCO_TMR_HALT BIT(11)
#define CNT_TCO_LOCK BIT(12)
/* TCO_TMR bits */
#define TMR_TCOTMR BIT_MASK(10)
#define TMR_MIN 0x04
#define TMR_MAX 0x3f
struct tco_data {
struct k_spinlock lock;
bool no_reboot;
};
struct tco_config {
io_port_t base;
};
static int set_no_reboot(const struct device *dev, bool set)
{
uint16_t val, newval;
val = sys_in16(TCO1_CNT(dev));
if (set) {
val |= CNT_NR_MSUS;
} else {
val &= ~CNT_NR_MSUS;
}
sys_out16(val, TCO1_CNT(dev));
newval = sys_in16(TCO1_CNT(dev));
if (val != newval) {
return -EIO;
}
return 0;
}
static int tco_setup(const struct device *dev, uint8_t options)
{
struct tco_data *data = dev->data;
k_spinlock_key_t key;
uint16_t val;
int err;
key = k_spin_lock(&data->lock);
err = set_no_reboot(dev, data->no_reboot);
if (err) {
k_spin_unlock(&data->lock, key);
LOG_ERR("Failed to update no_reboot bit (err %d)", err);
return err;
}
/* Reload the timer */
sys_out16(0x01, TCO_RLD(dev));
/* Enable the timer to start counting by clearing the TCO_TMR_HALT field */
val = sys_in16(TCO1_CNT(dev));
val &= ~CNT_TCO_TMR_HALT;
sys_out16(val, TCO1_CNT(dev));
val = sys_in16(TCO1_CNT(dev));
k_spin_unlock(&data->lock, key);
if ((val & CNT_TCO_TMR_HALT) == CNT_TCO_TMR_HALT) {
return -EIO;
}
return 0;
}
static int tco_disable(const struct device *dev)
{
struct tco_data *data = dev->data;
k_spinlock_key_t key;
uint16_t val;
key = k_spin_lock(&data->lock);
/* Set the TCO_TMR_HALT field so that the timer gets halted */
val = sys_in16(TCO1_CNT(dev));
val |= CNT_TCO_TMR_HALT;
sys_out16(val, TCO1_CNT(dev));
val = sys_in16(TCO1_CNT(dev));
set_no_reboot(dev, true);
k_spin_unlock(&data->lock, key);
if ((val & CNT_TCO_TMR_HALT) == 0) {
return -EIO;
}
return 0;
}
static uint16_t msec_to_ticks(uint32_t msec)
{
/* Convert from milliseconds to timer ticks. The timer is clocked at
* approximately 0.6 seconds.
*/
return ((msec / MSEC_PER_SEC) * 10) / 6;
}
static int tco_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct tco_data *data = dev->data;
k_spinlock_key_t key;
uint16_t val, ticks;
/* TCO watchdog doesn't support windowed timeouts */
if (cfg->window.min != 0) {
return -EINVAL;
}
/* No callback support */
if (cfg->callback != NULL) {
return -ENOTSUP;
}
ticks = msec_to_ticks(cfg->window.max);
LOG_DBG("window.max %u -> ticks %u", cfg->window.max, ticks);
if (ticks < TMR_MIN || ticks > TMR_MAX) {
return -EINVAL;
}
switch (cfg->flags) {
case WDT_FLAG_RESET_SOC:
data->no_reboot = false;
break;
case WDT_FLAG_RESET_NONE:
data->no_reboot = true;
break;
case WDT_FLAG_RESET_CPU_CORE:
LOG_ERR("CPU-only reset not supported");
return -ENOTSUP;
default:
LOG_ERR("Unknown watchdog configuration flags");
return -EINVAL;
}
key = k_spin_lock(&data->lock);
/* Set the TCO_TMR field. This value is loaded into the timer each time
* the TCO_RLD register is written.
*/
val = sys_in16(TCO_TMR(dev));
val &= ~TMR_TCOTMR;
val |= ticks;
sys_out16(val, TCO_TMR(dev));
val = sys_in16(TCO_TMR(dev));
k_spin_unlock(&data->lock, key);
if ((val & TMR_TCOTMR) != ticks) {
LOG_ERR("val %u", val);
return -EIO;
}
return 0;
}
static int tco_feed(const struct device *dev, int channel_id)
{
struct tco_data *data = dev->data;
k_spinlock_key_t key;
key = k_spin_lock(&data->lock);
/* TCORLD: Writing any value to this register will reload the timer to
* prevent the timeout.
*/
sys_out16(0x01, TCO_RLD(dev));
k_spin_unlock(&data->lock, key);
return 0;
}
static const struct wdt_driver_api tco_driver_api = {
.setup = tco_setup,
.disable = tco_disable,
.install_timeout = tco_install_timeout,
.feed = tco_feed,
};
static int wdt_init(const struct device *dev)
{
const struct tco_config *config = dev->config;
struct tco_data *data = dev->data;
k_spinlock_key_t key;
LOG_DBG("Using 0x%04x as TCOBA", config->base);
key = k_spin_lock(&data->lock);
sys_out16(STS_TIMEOUT, TCO1_STS(dev)); /* Clear the Time Out Status bit */
sys_out16(STS_SECOND_TO, TCO2_STS(dev)); /* Clear SECOND_TO_STS bit */
set_no_reboot(dev, data->no_reboot);
k_spin_unlock(&data->lock, key);
if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
tco_disable(dev);
}
return 0;
}
static struct tco_data wdt_data = {
};
static const struct tco_config wdt_config = {
.base = DT_INST_REG_ADDR(0),
};
DEVICE_DT_INST_DEFINE(0, wdt_init, NULL, &wdt_data, &wdt_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&tco_driver_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_tco.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,948 |
```unknown
config WDT_ENE_KB1200
bool "ENE KB1200 watchdog driver"
default y
depends on DT_HAS_ENE_KB1200_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
help
This option enables the KB1200 watchdog driver.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.ene | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
config WDT_RPI_PICO
bool "Raspberry Pi Pico Watchdog driver"
default y
depends on DT_HAS_RASPBERRYPI_PICO_WATCHDOG_ENABLED
select HAS_WDT_DISABLE_AT_BOOT
config WDT_RPI_PICO_INITIAL_TIMEOUT
int "Default watchdog timeout in us"
depends on WDT_RPI_PICO
default 8388607
range 1 8388607
help
Sets the default watchdog timeout at start-up, the feed function must
be called every interval prior to this time elapsing to prevent a
reboot of the module. The default is just over 8 seconds, which is the
largest timeout possible.
``` | /content/code_sandbox/drivers/watchdog/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 147 |
```unknown
# ILI9XXX display driver configuration options
config ILI9XXX
bool
help
Hidden configuration entry for all ILI9XXX drivers.
config ILI9XXX_READ
bool "Allow display_read API with ILI9XXX"
help
Support display_read API with ILI9XXX controllers. This API is opt-in,
because it adds code overhead and is not very performant due to
the requirement to bitshift data read from the ILI9XXX. Note the
API only supports RGB565 mode.
config ILI9340
bool "ILI9340 display driver"
default y
depends on DT_HAS_ILITEK_ILI9340_ENABLED
select MIPI_DBI
select ILI9XXX
help
Enable driver for ILI9340 display driver.
config ILI9341
bool "ILI9341 display driver"
default y
depends on DT_HAS_ILITEK_ILI9341_ENABLED
select MIPI_DBI
select ILI9XXX
help
Enable driver for ILI9341 display driver.
config ILI9342C
bool "ILI9342C display driver"
default y
depends on DT_HAS_ILITEK_ILI9342C_ENABLED
select MIPI_DBI
select ILI9XXX
help
Enable driver for ILI9342C display driver.
config ILI9488
bool "ILI9488 display driver"
default y
depends on DT_HAS_ILITEK_ILI9488_ENABLED
select MIPI_DBI
select ILI9XXX
help
Enable driver for ILI9488 display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.ili9xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 341 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_watchdog
#include <soc.h>
#include <zephyr/drivers/watchdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_sam0);
#define WDT_REGS ((Wdt *)DT_INST_REG_ADDR(0))
#ifndef WDT_CONFIG_PER_8_Val
#define WDT_CONFIG_PER_8_Val WDT_CONFIG_PER_CYC8_Val
#endif
#ifndef WDT_CONFIG_PER_8K_Val
#define WDT_CONFIG_PER_8K_Val WDT_CONFIG_PER_CYC8192_Val
#endif
#ifndef WDT_CONFIG_PER_16K_Val
#define WDT_CONFIG_PER_16K_Val WDT_CONFIG_PER_CYC16384_Val
#endif
/* syncbusy check is different for SAM D/E */
#ifdef WDT_STATUS_SYNCBUSY
#define WDT_SYNCBUSY WDT_REGS->STATUS.bit.SYNCBUSY
#else
#define WDT_SYNCBUSY WDT_REGS->SYNCBUSY.reg
#endif
struct wdt_sam0_dev_data {
wdt_callback_t cb;
bool timeout_valid;
};
static struct wdt_sam0_dev_data wdt_sam0_data = { 0 };
static void wdt_sam0_wait_synchronization(void)
{
while (WDT_SYNCBUSY) {
/* wait for SYNCBUSY */
}
}
static inline void wdt_sam0_set_enable(bool on)
{
#ifdef WDT_CTRLA_ENABLE
WDT_REGS->CTRLA.bit.ENABLE = on;
#else
WDT_REGS->CTRL.bit.ENABLE = on;
#endif
}
static inline bool wdt_sam0_is_enabled(void)
{
#ifdef WDT_CTRLA_ENABLE
return WDT_REGS->CTRLA.bit.ENABLE;
#else
return WDT_REGS->CTRL.bit.ENABLE;
#endif
}
static uint32_t wdt_sam0_timeout_to_wdt_period(uint32_t timeout_ms)
{
uint32_t next_pow2;
uint32_t cycles;
/* Calculate number of clock cycles @ 1.024 kHz input clock */
cycles = (timeout_ms * 1024U) / 1000;
/* Minimum wdt period is 8 clock cycles (register value 0) */
if (cycles <= 8U) {
return 0;
}
/* Round up to next pow2 and calculate the register value */
next_pow2 = (1ULL << 32) >> __builtin_clz(cycles - 1);
return find_msb_set(next_pow2 >> 4);
}
static void wdt_sam0_isr(const struct device *dev)
{
struct wdt_sam0_dev_data *data = dev->data;
WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
if (data->cb != NULL) {
data->cb(dev, 0);
}
}
static int wdt_sam0_setup(const struct device *dev, uint8_t options)
{
struct wdt_sam0_dev_data *data = dev->data;
if (wdt_sam0_is_enabled()) {
LOG_ERR("Watchdog already setup");
return -EBUSY;
}
if (!data->timeout_valid) {
LOG_ERR("No valid timeout installed");
return -EINVAL;
}
if (options & WDT_OPT_PAUSE_IN_SLEEP) {
LOG_ERR("Pause in sleep not supported");
return -ENOTSUP;
}
if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
LOG_ERR("Pause when halted by debugger not supported");
return -ENOTSUP;
}
/* Enable watchdog */
wdt_sam0_set_enable(1);
wdt_sam0_wait_synchronization();
return 0;
}
static int wdt_sam0_disable(const struct device *dev)
{
if (!wdt_sam0_is_enabled()) {
return -EFAULT;
}
wdt_sam0_set_enable(0);
wdt_sam0_wait_synchronization();
return 0;
}
static int wdt_sam0_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
struct wdt_sam0_dev_data *data = dev->data;
uint32_t window, per;
/* CONFIG is enable protected, error out if already enabled */
if (wdt_sam0_is_enabled()) {
LOG_ERR("Watchdog already setup");
return -EBUSY;
}
if (cfg->flags != WDT_FLAG_RESET_SOC) {
LOG_ERR("Only SoC reset supported");
return -ENOTSUP;
}
if (cfg->window.max == 0) {
LOG_ERR("Upper limit timeout out of range");
return -EINVAL;
}
per = wdt_sam0_timeout_to_wdt_period(cfg->window.max);
if (per > WDT_CONFIG_PER_16K_Val) {
LOG_ERR("Upper limit timeout out of range");
goto timeout_invalid;
}
if (cfg->window.min) {
/* Window mode */
window = wdt_sam0_timeout_to_wdt_period(cfg->window.min);
if (window > WDT_CONFIG_PER_8K_Val) {
LOG_ERR("Lower limit timeout out of range");
goto timeout_invalid;
}
if (per <= window) {
/* Ensure we have a window */
per = window + 1;
}
#ifdef WDT_CTRLA_WEN
WDT_REGS->CTRLA.bit.WEN = 1;
#else
WDT_REGS->CTRL.bit.WEN = 1;
#endif
wdt_sam0_wait_synchronization();
} else {
/* Normal mode */
if (cfg->callback) {
if (per == WDT_CONFIG_PER_8_Val) {
/* Ensure we have time for the early warning */
per += 1U;
}
WDT_REGS->EWCTRL.bit.EWOFFSET = per - 1U;
}
window = WDT_CONFIG_PER_8_Val;
#ifdef WDT_CTRLA_WEN
WDT_REGS->CTRLA.bit.WEN = 0;
#else
WDT_REGS->CTRL.bit.WEN = 0;
#endif
wdt_sam0_wait_synchronization();
}
WDT_REGS->CONFIG.reg = WDT_CONFIG_WINDOW(window) | WDT_CONFIG_PER(per);
wdt_sam0_wait_synchronization();
/* Only enable IRQ if a callback was provided */
data->cb = cfg->callback;
if (data->cb) {
WDT_REGS->INTENSET.reg = WDT_INTENSET_EW;
} else {
WDT_REGS->INTENCLR.reg = WDT_INTENCLR_EW;
WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
}
data->timeout_valid = true;
return 0;
timeout_invalid:
data->timeout_valid = false;
data->cb = NULL;
return -EINVAL;
}
static int wdt_sam0_feed(const struct device *dev, int channel_id)
{
struct wdt_sam0_dev_data *data = dev->data;
if (!data->timeout_valid) {
LOG_ERR("No valid timeout installed");
return -EINVAL;
}
if (WDT_SYNCBUSY) {
return -EAGAIN;
}
WDT_REGS->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val;
return 0;
}
static const struct wdt_driver_api wdt_sam0_api = {
.setup = wdt_sam0_setup,
.disable = wdt_sam0_disable,
.install_timeout = wdt_sam0_install_timeout,
.feed = wdt_sam0_feed,
};
static int wdt_sam0_init(const struct device *dev)
{
#ifdef CONFIG_WDT_DISABLE_AT_BOOT
/* Ignore any errors */
wdt_sam0_disable(dev);
#endif
/* Enable APB clock */
#ifdef MCLK
MCLK->APBAMASK.bit.WDT_ = 1;
/* watchdog clock is fed by OSCULP32K */
#else
PM->APBAMASK.bit.WDT_ = 1;
/* Connect to GCLK2 (~1.024 kHz) */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
| GCLK_CLKCTRL_GEN_GCLK2
| GCLK_CLKCTRL_CLKEN;
#endif
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority), wdt_sam0_isr,
DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
static struct wdt_sam0_dev_data wdt_sam0_data;
DEVICE_DT_INST_DEFINE(0, wdt_sam0_init, NULL,
&wdt_sam0_data, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sam0_api);
``` | /content/code_sandbox/drivers/watchdog/wdt_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,906 |
```unknown
config INTEL_MULTIBOOTFB_DISPLAY
bool "Intel Multiboot Framebuffer"
default y
depends on MULTIBOOT && MULTIBOOT_INFO && \
DT_HAS_INTEL_MULTIBOOT_FRAMEBUFFER_ENABLED
help
Enable Intel Multiboot framebuffer-based display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.intel_multibootfb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```unknown
config RM68200
bool "RM68200 display driver"
default y
depends on MIPI_DSI
depends on DT_HAS_RAYDIUM_RM68200_ENABLED
help
Enable driver for RM68200 display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.rm68200 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
# UC81xx display controller configuration options
config UC81XX
bool "UltraChip UC81xx compatible display controller driver"
default y
depends on DT_HAS_ULTRACHIP_UC8175_ENABLED || DT_HAS_ULTRACHIP_UC8176_ENABLED || DT_HAS_ULTRACHIP_UC8179_ENABLED
select MIPI_DBI
help
Enable driver for UC81xx compatible controller.
``` | /content/code_sandbox/drivers/display/Kconfig.uc81xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
config HX8394
bool "HX8394 display driver"
default y
depends on MIPI_DSI
depends on DT_HAS_HIMAX_HX8394_ENABLED
help
Enable driver for HX8394 display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.hx8394 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# SDL based emulated display configuration options
menuconfig SDL_DISPLAY
bool "SDL based emulated display"
default y
depends on DT_HAS_ZEPHYR_SDL_DC_ENABLED
select HAS_SDL
help
Enable SDL based emulated display compliant with display driver API.
if SDL_DISPLAY
choice SDL_DISPLAY_DEFAULT_PIXEL_FORMAT
prompt "Default pixel format"
default SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_ARGB_8888
help
Default pixel format to be used by the display
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_ARGB_8888
bool "ARGB 8888"
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_888
bool "RGB 888"
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01
bool "Mono Black=0"
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10
bool "Mono Black=1"
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_565
bool "RGB 565"
config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_BGR_565
bool "BGR 565"
endchoice
config SDL_DISPLAY_ZOOM_PCT
int "Default zoom percentage"
default 100
range 10 10000
help
SDL window zoom percentage to adjust readability on small screens
config SDL_DISPLAY_USE_HARDWARE_ACCELERATOR
bool "Use hardware accelerator"
default y
help
Enable hardware acceleration for graphics rendering
config SDL_DISPLAY_MONO_MSB_FIRST
bool "Configure bit order in monochrome formats to MSB first"
default y
help
If selected, set the MSB to represent the first pixel.
This applies when the pixel format is MONO01/MONO10.
endif # SDL_DISPLAY
``` | /content/code_sandbox/drivers/display/Kconfig.sdl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 344 |
```c
/*
*/
#include "display_ili9xxx.h"
#include <zephyr/dt-bindings/display/ili9xxx.h>
#include <zephyr/drivers/display.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_ili9xxx, CONFIG_DISPLAY_LOG_LEVEL);
struct ili9xxx_data {
uint8_t bytes_per_pixel;
enum display_pixel_format pixel_format;
enum display_orientation orientation;
};
#ifdef CONFIG_ILI9XXX_READ
/* We set this LUT directly when reads are enabled,
* so that we can be sure the bitshift to convert GRAM data back
* to RGB565 will result in correct data
*/
const uint8_t ili9xxx_rgb_lut[] = {
0, 2, 4, 6,
8, 10, 12, 14,
16, 18, 20, 22,
24, 26, 28, 30,
32, 34, 36, 38,
40, 42, 44, 46,
48, 50, 52, 54,
56, 58, 60, 62,
0, 1, 2, 3,
4, 5, 6, 7,
8, 9, 10, 11,
12, 13, 14, 15,
16, 17, 18, 19,
20, 21, 22, 23,
24, 25, 26, 27,
28, 29, 30, 31,
32, 33, 34, 35,
36, 37, 38, 39,
40, 41, 42, 43,
44, 45, 46, 47,
48, 49, 50, 51,
52, 53, 54, 55,
56, 57, 58, 59,
60, 61, 62, 63,
0, 2, 4, 6,
8, 10, 12, 14,
16, 18, 20, 22,
24, 26, 28, 30,
32, 34, 36, 38,
40, 42, 44, 46,
48, 50, 52, 54,
56, 58, 60, 62
};
#endif
int ili9xxx_transmit(const struct device *dev, uint8_t cmd, const void *tx_data,
size_t tx_len)
{
const struct ili9xxx_config *config = dev->config;
return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, tx_data, tx_len);
}
static int ili9xxx_exit_sleep(const struct device *dev)
{
int r;
r = ili9xxx_transmit(dev, ILI9XXX_SLPOUT, NULL, 0);
if (r < 0) {
return r;
}
k_sleep(K_MSEC(ILI9XXX_SLEEP_OUT_TIME));
return 0;
}
static void ili9xxx_hw_reset(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
if (mipi_dbi_reset(config->mipi_dev, ILI9XXX_RESET_PULSE_TIME) < 0) {
return;
};
k_sleep(K_MSEC(ILI9XXX_RESET_WAIT_TIME));
}
static int ili9xxx_set_mem_area(const struct device *dev, const uint16_t x,
const uint16_t y, const uint16_t w,
const uint16_t h)
{
int r;
uint16_t spi_data[2];
spi_data[0] = sys_cpu_to_be16(x);
spi_data[1] = sys_cpu_to_be16(x + w - 1U);
r = ili9xxx_transmit(dev, ILI9XXX_CASET, &spi_data[0], 4U);
if (r < 0) {
return r;
}
spi_data[0] = sys_cpu_to_be16(y);
spi_data[1] = sys_cpu_to_be16(y + h - 1U);
r = ili9xxx_transmit(dev, ILI9XXX_PASET, &spi_data[0], 4U);
if (r < 0) {
return r;
}
return 0;
}
static int ili9xxx_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct ili9xxx_config *config = dev->config;
struct ili9xxx_data *data = dev->data;
struct display_buffer_descriptor mipi_desc;
int r;
const uint8_t *write_data_start = (const uint8_t *)buf;
uint16_t write_cnt;
uint16_t nbr_of_writes;
uint16_t write_h;
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
__ASSERT((desc->pitch * data->bytes_per_pixel * desc->height) <=
desc->buf_size,
"Input buffer to small");
LOG_DBG("Writing %dx%d (w,h) @ %dx%d (x,y)", desc->width, desc->height,
x, y);
r = ili9xxx_set_mem_area(dev, x, y, desc->width, desc->height);
if (r < 0) {
return r;
}
if (desc->pitch > desc->width) {
write_h = 1U;
nbr_of_writes = desc->height;
mipi_desc.height = 1;
mipi_desc.buf_size = desc->pitch * data->bytes_per_pixel;
} else {
write_h = desc->height;
mipi_desc.height = desc->height;
mipi_desc.buf_size = desc->width * data->bytes_per_pixel * write_h;
nbr_of_writes = 1U;
}
mipi_desc.width = desc->width;
/* Per MIPI API, pitch must always match width */
mipi_desc.pitch = desc->width;
r = ili9xxx_transmit(dev, ILI9XXX_RAMWR, NULL, 0);
if (r < 0) {
return r;
}
for (write_cnt = 0U; write_cnt < nbr_of_writes; ++write_cnt) {
r = mipi_dbi_write_display(config->mipi_dev,
&config->dbi_config,
write_data_start,
&mipi_desc,
data->pixel_format);
if (r < 0) {
return r;
}
write_data_start += desc->pitch * data->bytes_per_pixel;
}
return 0;
}
#ifdef CONFIG_ILI9XXX_READ
static int ili9xxx_read(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc, void *buf)
{
const struct ili9xxx_config *config = dev->config;
struct ili9xxx_data *data = dev->data;
struct display_buffer_descriptor mipi_desc;
int r;
uint32_t gram_data, nbr_of_reads;
uint16_t *read_data_start = (uint16_t *)buf;
if (data->pixel_format != PIXEL_FORMAT_RGB_565) {
/* Only RGB565 can be supported, see note below */
return -ENOTSUP;
}
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
__ASSERT((desc->pitch * data->bytes_per_pixel * desc->height) <=
desc->buf_size,
"Output buffer to small");
LOG_DBG("Reading %dx%d (w,h) @ %dx%d (x,y)", desc->width, desc->height,
x, y);
r = ili9xxx_set_mem_area(dev, x, y, desc->width, desc->height);
if (r < 0) {
return r;
}
/*
* ILI9XXX stores all pixel data in graphics ram (GRAM) as 18 bit
* values. When using RGB565 pixel format, pixels are converted to
* 18 bit values via a lookup table. When using RGB888 format, the
* lower 2 bits of each pixel are simply dropped. When reading pixels,
* the response format will always look like so:
* | R[5:0] | x | x | G[5:0] | x | x | B[5:0] | x | x |
* Where x represents "don't care". The internal format of the
* ILI9XXX graphics RAM results in the following restrictions:
* - RGB888 mode can't be supported.
* - we can only read one pixel at once (since we need to do
* byte manipulation on the output)
*/
/* Setup MIPI descriptor to read 3 bytes (one pixel in GRAM) */
mipi_desc.width = 1;
mipi_desc.height = 1;
/* Per MIPI API, pitch must always match width */
mipi_desc.pitch = 1;
nbr_of_reads = desc->width * desc->height;
/* Initial read command should consist of RAMRD command, plus
* 8 dummy clock cycles
*/
uint8_t cmd[] = {ILI9XXX_RAMRD, 0xFF};
for (uint32_t read_cnt = 0; read_cnt < nbr_of_reads; read_cnt++) {
r = mipi_dbi_command_read(config->mipi_dev,
&config->dbi_config,
cmd, sizeof(cmd),
(uint8_t *)&gram_data, 3);
if (r < 0) {
return r;
}
/* Bitshift the graphics RAM data to RGB565.
* For more details on the formatting of this data,
* see "Read data through 4-line SPI mode" diagram
* on page 64 of datasheet.
*/
read_data_start[read_cnt] =
((gram_data & 0xF80000) >> 11) | /* Blue */
((gram_data & 0x1C00) << 3) | /* Green */
((gram_data & 0xE000) >> 13) | /* Green */
(gram_data & 0xF8); /* Red */
/* After first read, we should use read memory continue command */
cmd[0] = ILI9XXX_RAMRD_CONT;
}
return 0;
}
#endif
static int ili9xxx_display_blanking_off(const struct device *dev)
{
LOG_DBG("Turning display blanking off");
return ili9xxx_transmit(dev, ILI9XXX_DISPON, NULL, 0);
}
static int ili9xxx_display_blanking_on(const struct device *dev)
{
LOG_DBG("Turning display blanking on");
return ili9xxx_transmit(dev, ILI9XXX_DISPOFF, NULL, 0);
}
static int
ili9xxx_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct ili9xxx_data *data = dev->data;
int r;
uint8_t tx_data;
uint8_t bytes_per_pixel;
if (pixel_format == PIXEL_FORMAT_RGB_565) {
bytes_per_pixel = 2U;
tx_data = ILI9XXX_PIXSET_MCU_16_BIT | ILI9XXX_PIXSET_RGB_16_BIT;
} else if (pixel_format == PIXEL_FORMAT_RGB_888) {
bytes_per_pixel = 3U;
tx_data = ILI9XXX_PIXSET_MCU_18_BIT | ILI9XXX_PIXSET_RGB_18_BIT;
} else {
LOG_ERR("Unsupported pixel format");
return -ENOTSUP;
}
r = ili9xxx_transmit(dev, ILI9XXX_PIXSET, &tx_data, 1U);
if (r < 0) {
return r;
}
data->pixel_format = pixel_format;
data->bytes_per_pixel = bytes_per_pixel;
return 0;
}
static int ili9xxx_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
const struct ili9xxx_config *config = dev->config;
struct ili9xxx_data *data = dev->data;
int r;
uint8_t tx_data = ILI9XXX_MADCTL_BGR;
if (config->quirks->cmd_set == CMD_SET_1) {
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
tx_data |= ILI9XXX_MADCTL_MX;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) {
tx_data |= ILI9XXX_MADCTL_MV;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) {
tx_data |= ILI9XXX_MADCTL_MY;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) {
tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MX |
ILI9XXX_MADCTL_MY;
}
} else if (config->quirks->cmd_set == CMD_SET_2) {
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
/* Do nothing */
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) {
tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MY;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) {
tx_data |= ILI9XXX_MADCTL_MY | ILI9XXX_MADCTL_MX;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) {
tx_data |= ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MX;
}
}
r = ili9xxx_transmit(dev, ILI9XXX_MADCTL, &tx_data, 1U);
if (r < 0) {
return r;
}
data->orientation = orientation;
return 0;
}
static void ili9xxx_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
struct ili9xxx_data *data = dev->data;
const struct ili9xxx_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->supported_pixel_formats =
PIXEL_FORMAT_RGB_565 | PIXEL_FORMAT_RGB_888;
capabilities->current_pixel_format = data->pixel_format;
if (data->orientation == DISPLAY_ORIENTATION_NORMAL ||
data->orientation == DISPLAY_ORIENTATION_ROTATED_180) {
capabilities->x_resolution = config->x_resolution;
capabilities->y_resolution = config->y_resolution;
} else {
capabilities->x_resolution = config->y_resolution;
capabilities->y_resolution = config->x_resolution;
}
capabilities->current_orientation = data->orientation;
}
static int ili9xxx_configure(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
int r;
enum display_pixel_format pixel_format;
enum display_orientation orientation;
/* pixel format */
if (config->pixel_format == ILI9XXX_PIXEL_FORMAT_RGB565) {
pixel_format = PIXEL_FORMAT_RGB_565;
} else {
pixel_format = PIXEL_FORMAT_RGB_888;
}
r = ili9xxx_set_pixel_format(dev, pixel_format);
if (r < 0) {
return r;
}
/* orientation */
if (config->rotation == 0U) {
orientation = DISPLAY_ORIENTATION_NORMAL;
} else if (config->rotation == 90U) {
orientation = DISPLAY_ORIENTATION_ROTATED_90;
} else if (config->rotation == 180U) {
orientation = DISPLAY_ORIENTATION_ROTATED_180;
} else {
orientation = DISPLAY_ORIENTATION_ROTATED_270;
}
r = ili9xxx_set_orientation(dev, orientation);
if (r < 0) {
return r;
}
if (config->inversion) {
r = ili9xxx_transmit(dev, ILI9XXX_DINVON, NULL, 0U);
if (r < 0) {
return r;
}
}
r = config->regs_init_fn(dev);
if (r < 0) {
return r;
}
return 0;
}
static int ili9xxx_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
int r;
if (!device_is_ready(config->mipi_dev)) {
LOG_ERR("MIPI DBI device is not ready");
return -ENODEV;
}
ili9xxx_hw_reset(dev);
r = ili9xxx_transmit(dev, ILI9XXX_SWRESET, NULL, 0);
if (r < 0) {
LOG_ERR("Error transmit command Software Reset (%d)", r);
return r;
}
#ifdef CONFIG_ILI9XXX_READ
/* Set RGB LUT table to enable display read API */
ili9xxx_transmit(dev, ILI9XXX_RGBSET, ili9xxx_rgb_lut, sizeof(ili9xxx_rgb_lut));
#endif
k_sleep(K_MSEC(ILI9XXX_RESET_WAIT_TIME));
ili9xxx_display_blanking_on(dev);
r = ili9xxx_configure(dev);
if (r < 0) {
LOG_ERR("Could not configure display (%d)", r);
return r;
}
r = ili9xxx_exit_sleep(dev);
if (r < 0) {
LOG_ERR("Could not exit sleep mode (%d)", r);
return r;
}
return 0;
}
static const struct display_driver_api ili9xxx_api = {
.blanking_on = ili9xxx_display_blanking_on,
.blanking_off = ili9xxx_display_blanking_off,
.write = ili9xxx_write,
#ifdef CONFIG_ILI9XXX_READ
.read = ili9xxx_read,
#endif
.get_capabilities = ili9xxx_get_capabilities,
.set_pixel_format = ili9xxx_set_pixel_format,
.set_orientation = ili9xxx_set_orientation,
};
#ifdef CONFIG_ILI9340
static const struct ili9xxx_quirks ili9340_quirks = {
.cmd_set = CMD_SET_1,
};
#endif
#ifdef CONFIG_ILI9341
static const struct ili9xxx_quirks ili9341_quirks = {
.cmd_set = CMD_SET_1,
};
#endif
#ifdef CONFIG_ILI9342C
static const struct ili9xxx_quirks ili9342c_quirks = {
.cmd_set = CMD_SET_2,
};
#endif
#ifdef CONFIG_ILI9488
static const struct ili9xxx_quirks ili9488_quirks = {
.cmd_set = CMD_SET_1,
};
#endif
#define INST_DT_ILI9XXX(n, t) DT_INST(n, ilitek_ili##t)
#define ILI9XXX_INIT(n, t) \
ILI##t##_REGS_INIT(n); \
\
static const struct ili9xxx_config ili9xxx_config_##n = { \
.quirks = &ili##t##_quirks, \
.mipi_dev = DEVICE_DT_GET(DT_PARENT(INST_DT_ILI9XXX(n, t))), \
.dbi_config = { \
.mode = MIPI_DBI_MODE_SPI_4WIRE, \
.config = MIPI_DBI_SPI_CONFIG_DT( \
INST_DT_ILI9XXX(n, t), \
SPI_OP_MODE_MASTER | \
SPI_WORD_SET(8), \
0), \
}, \
.pixel_format = DT_PROP(INST_DT_ILI9XXX(n, t), pixel_format), \
.rotation = DT_PROP(INST_DT_ILI9XXX(n, t), rotation), \
.x_resolution = ILI##t##_X_RES, \
.y_resolution = ILI##t##_Y_RES, \
.inversion = DT_PROP(INST_DT_ILI9XXX(n, t), display_inversion),\
.regs = &ili9xxx_regs_##n, \
.regs_init_fn = ili##t##_regs_init, \
}; \
\
static struct ili9xxx_data ili9xxx_data_##n; \
\
DEVICE_DT_DEFINE(INST_DT_ILI9XXX(n, t), ili9xxx_init, \
NULL, &ili9xxx_data_##n, \
&ili9xxx_config_##n, POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, &ili9xxx_api)
#define DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(t) \
LISTIFY(DT_NUM_INST_STATUS_OKAY(ilitek_ili##t), ILI9XXX_INIT, (;), t)
#ifdef CONFIG_ILI9340
#include "display_ili9340.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9340);
#endif
#ifdef CONFIG_ILI9341
#include "display_ili9341.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9341);
#endif
#ifdef CONFIG_ILI9342C
#include "display_ili9342c.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9342c);
#endif
#ifdef CONFIG_ILI9488
#include "display_ili9488.h"
DT_INST_FOREACH_ILI9XXX_STATUS_OKAY(9488);
#endif
``` | /content/code_sandbox/drivers/display/display_ili9xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,642 |
```c
/*
*
*/
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/sys/byteorder.h>
#include "uc81xx_regs.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(uc81xx, CONFIG_DISPLAY_LOG_LEVEL);
/**
* UC81XX compatible EPD controller driver.
*
* Currently only the black/white panels are supported (KW mode),
* also first gate/source should be 0.
*/
#define UC81XX_PIXELS_PER_BYTE 8U
struct uc81xx_dt_array {
uint8_t *data;
uint8_t len;
};
enum uc81xx_profile_type {
UC81XX_PROFILE_FULL = 0,
UC81XX_PROFILE_PARTIAL,
UC81XX_NUM_PROFILES,
UC81XX_PROFILE_INVALID = UC81XX_NUM_PROFILES,
};
struct uc81xx_profile {
struct uc81xx_dt_array pwr;
uint8_t cdi;
bool override_cdi;
uint8_t tcon;
bool override_tcon;
uint8_t pll;
bool override_pll;
uint8_t vdcs;
bool override_vdcs;
const struct uc81xx_dt_array lutc;
const struct uc81xx_dt_array lutww;
const struct uc81xx_dt_array lutkw;
const struct uc81xx_dt_array lutwk;
const struct uc81xx_dt_array lutkk;
const struct uc81xx_dt_array lutbd;
};
struct uc81xx_quirks {
uint16_t max_width;
uint16_t max_height;
bool auto_copy;
int (*set_cdi)(const struct device *dev, bool border);
int (*set_tres)(const struct device *dev);
int (*set_ptl)(const struct device *dev, uint16_t x, uint16_t y,
uint16_t x_end_idx, uint16_t y_end_idx,
const struct display_buffer_descriptor *desc);
};
struct uc81xx_config {
const struct uc81xx_quirks *quirks;
const struct device *mipi_dev;
const struct mipi_dbi_config dbi_config;
struct gpio_dt_spec busy_gpio;
uint16_t height;
uint16_t width;
struct uc81xx_dt_array softstart;
const struct uc81xx_profile *profiles[UC81XX_NUM_PROFILES];
};
struct uc81xx_data {
bool blanking_on;
enum uc81xx_profile_type profile;
};
static inline void uc81xx_busy_wait(const struct device *dev)
{
const struct uc81xx_config *config = dev->config;
int pin = gpio_pin_get_dt(&config->busy_gpio);
while (pin > 0) {
__ASSERT(pin >= 0, "Failed to get pin level");
k_sleep(K_MSEC(UC81XX_BUSY_DELAY));
pin = gpio_pin_get_dt(&config->busy_gpio);
}
}
static inline int uc81xx_write_cmd(const struct device *dev, uint8_t cmd,
const uint8_t *data, size_t len)
{
const struct uc81xx_config *config = dev->config;
int err;
uc81xx_busy_wait(dev);
err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, data, len);
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return err;
}
static inline int uc81xx_write_cmd_pattern(const struct device *dev,
uint8_t cmd,
uint8_t pattern, size_t len)
{
const struct uc81xx_config *config = dev->config;
struct display_buffer_descriptor mipi_desc;
int err;
uint8_t data[64];
uc81xx_busy_wait(dev);
err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, NULL, 0);
if (err < 0) {
return err;
}
/*
* MIPI display write API requires a display buffer descriptor.
* Create one that describes the buffer we are writing
*/
mipi_desc.height = 1;
memset(data, pattern, sizeof(data));
while (len) {
mipi_desc.buf_size = mipi_desc.width = mipi_desc.pitch =
MIN(len, sizeof(data));
err = mipi_dbi_write_display(config->mipi_dev,
&config->dbi_config,
data, &mipi_desc,
PIXEL_FORMAT_MONO10);
if (err < 0) {
goto out;
}
len -= mipi_desc.buf_size;
}
out:
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return err;
}
static inline int uc81xx_write_cmd_uint8(const struct device *dev, uint8_t cmd,
uint8_t data)
{
return uc81xx_write_cmd(dev, cmd, &data, 1);
}
static inline int uc81xx_write_array_opt(const struct device *dev, uint8_t cmd,
const struct uc81xx_dt_array *array)
{
if (array->len && array->data) {
return uc81xx_write_cmd(dev, cmd, array->data, array->len);
} else {
return 0;
}
}
static int uc81xx_have_profile(const struct device *dev,
enum uc81xx_profile_type type)
{
const struct uc81xx_config *config = dev->config;
return type < UC81XX_NUM_PROFILES &&
config->profiles[type];
}
static int uc81xx_set_profile(const struct device *dev,
enum uc81xx_profile_type type)
{
const struct uc81xx_config *config = dev->config;
const struct uc81xx_profile *p;
struct uc81xx_data *data = dev->data;
uint8_t psr =
UC81XX_PSR_KW_R |
UC81XX_PSR_UD |
UC81XX_PSR_SHL |
UC81XX_PSR_SHD |
UC81XX_PSR_RST;
if (type >= UC81XX_NUM_PROFILES) {
return -EINVAL;
}
/* No need to update the current profile, so do nothing */
if (data->profile == type) {
return 0;
}
p = config->profiles[type];
data->profile = type;
LOG_DBG("Initialize UC81XX controller with profile %d", type);
if (p) {
LOG_HEXDUMP_DBG(p->pwr.data, p->pwr.len, "PWR");
if (uc81xx_write_array_opt(dev, UC81XX_CMD_PWR, &p->pwr)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_BTST,
&config->softstart)) {
return -EIO;
}
/*
* Enable LUT overrides if a LUT has been provided by
* the user.
*/
if (p->lutc.len || p->lutww.len || p->lutkw.len ||
p->lutwk.len || p->lutbd.len) {
LOG_DBG("Using LUT from registers");
psr |= UC81XX_PSR_REG;
}
}
/* Panel settings, KW mode and soft reset */
LOG_DBG("PSR: %#hhx", psr);
if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_PSR, psr)) {
return -EIO;
}
/* Set panel resolution */
if (config->quirks->set_tres(dev)) {
return -EIO;
}
/* Set CDI and enable border output */
if (config->quirks->set_cdi(dev, true)) {
return -EIO;
}
/*
* The rest of the configuration is optional and depends on
* having profile overrides specified in the device tree.
*/
if (!p) {
return 0;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTC, &p->lutc)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTWW, &p->lutww)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTKW, &p->lutkw)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTWK, &p->lutwk)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTKK, &p->lutkk)) {
return -EIO;
}
if (uc81xx_write_array_opt(dev, UC81XX_CMD_LUTBD, &p->lutbd)) {
return -EIO;
}
if (p->override_pll) {
LOG_DBG("PLL: %#hhx", p->pll);
if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_PLL, p->pll)) {
return -EIO;
}
}
if (p->override_vdcs) {
LOG_DBG("VDCS: %#hhx", p->vdcs);
if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_VDCS, p->vdcs)) {
return -EIO;
}
}
if (p->override_tcon) {
if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_TCON, p->tcon)) {
return -EIO;
}
}
return 0;
}
static int uc81xx_update_display(const struct device *dev)
{
LOG_DBG("Trigger update sequence");
/* Turn on: booster, controller, regulators, and sensor. */
if (uc81xx_write_cmd(dev, UC81XX_CMD_PON, NULL, 0)) {
return -EIO;
}
k_sleep(K_MSEC(UC81XX_PON_DELAY));
if (uc81xx_write_cmd(dev, UC81XX_CMD_DRF, NULL, 0)) {
return -EIO;
}
k_sleep(K_MSEC(UC81XX_BUSY_DELAY));
/* Turn on: booster, controller, regulators, and sensor. */
if (uc81xx_write_cmd(dev, UC81XX_CMD_POF, NULL, 0)) {
return -EIO;
}
return 0;
}
static int uc81xx_blanking_off(const struct device *dev)
{
struct uc81xx_data *data = dev->data;
if (data->blanking_on) {
/* Update EPD panel in normal mode */
if (uc81xx_update_display(dev)) {
return -EIO;
}
}
data->blanking_on = false;
return 0;
}
static int uc81xx_blanking_on(const struct device *dev)
{
struct uc81xx_data *data = dev->data;
if (!data->blanking_on) {
if (uc81xx_set_profile(dev, UC81XX_PROFILE_FULL)) {
return -EIO;
}
}
data->blanking_on = true;
return 0;
}
static int uc81xx_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct uc81xx_config *config = dev->config;
struct uc81xx_data *data = dev->data;
uint16_t x_end_idx = x + desc->width - 1;
uint16_t y_end_idx = y + desc->height - 1;
size_t buf_len;
const uint8_t back_buffer = data->blanking_on ?
UC81XX_CMD_DTM1 : UC81XX_CMD_DTM2;
LOG_DBG("x %u, y %u, height %u, width %u, pitch %u",
x, y, desc->height, desc->width, desc->pitch);
buf_len = MIN(desc->buf_size,
desc->height * desc->width / UC81XX_PIXELS_PER_BYTE);
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT(buf != NULL, "Buffer is not available");
__ASSERT(buf_len != 0U, "Buffer of length zero");
__ASSERT(!(desc->width % UC81XX_PIXELS_PER_BYTE),
"Buffer width not multiple of %d", UC81XX_PIXELS_PER_BYTE);
if ((y_end_idx > (config->height - 1)) ||
(x_end_idx > (config->width - 1))) {
LOG_ERR("Position out of bounds");
return -EINVAL;
}
if (!data->blanking_on) {
/* Blanking isn't on, so this is a partial
* refresh. Request the partial profile if it
* exists. If a partial profile hasn't been provided,
* we continue to use the full refresh profile. Note
* that the controller still only scans a partial
* window.
*
* This operation becomes a no-op if the profile is
* already active
*/
if (uc81xx_have_profile(dev, UC81XX_PROFILE_PARTIAL) &&
uc81xx_set_profile(dev, UC81XX_PROFILE_PARTIAL)) {
return -EIO;
}
}
if (uc81xx_write_cmd(dev, UC81XX_CMD_PTIN, NULL, 0)) {
return -EIO;
}
if (config->quirks->set_ptl(dev, x, y, x_end_idx, y_end_idx, desc)) {
return -EIO;
}
if (uc81xx_write_cmd(dev, UC81XX_CMD_DTM2, (uint8_t *)buf, buf_len)) {
return -EIO;
}
/* Update the display */
if (data->blanking_on == false) {
/* Disable border output */
if (config->quirks->set_cdi(dev, false)) {
return -EIO;
}
if (uc81xx_update_display(dev)) {
return -EIO;
}
/* Enable border output */
if (config->quirks->set_cdi(dev, true)) {
return -EIO;
}
}
if (!config->quirks->auto_copy) {
/* Some controllers don't copy the new data to the old
* data buffer on refresh. Do that manually here if
* needed.
*/
if (config->quirks->set_ptl(dev, x, y, x_end_idx, y_end_idx, desc)) {
return -EIO;
}
if (uc81xx_write_cmd(dev, back_buffer,
(uint8_t *)buf, buf_len)) {
return -EIO;
}
}
if (uc81xx_write_cmd(dev, UC81XX_CMD_PTOUT, NULL, 0)) {
return -EIO;
}
return 0;
}
static void uc81xx_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct uc81xx_config *config = dev->config;
memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = config->width;
caps->y_resolution = config->height;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
caps->current_pixel_format = PIXEL_FORMAT_MONO10;
caps->screen_info = SCREEN_INFO_MONO_MSB_FIRST | SCREEN_INFO_EPD;
}
static int uc81xx_set_pixel_format(const struct device *dev,
const enum display_pixel_format pf)
{
if (pf == PIXEL_FORMAT_MONO10) {
return 0;
}
LOG_ERR("not supported");
return -ENOTSUP;
}
static int uc81xx_clear_and_write_buffer(const struct device *dev,
uint8_t pattern, bool update)
{
const struct uc81xx_config *config = dev->config;
const int size = config->width * config->height
/ UC81XX_PIXELS_PER_BYTE;
if (uc81xx_write_cmd_pattern(dev, UC81XX_CMD_DTM1, pattern, size)) {
return -EIO;
}
if (uc81xx_write_cmd_pattern(dev, UC81XX_CMD_DTM2, pattern, size)) {
return -EIO;
}
if (update == true) {
if (uc81xx_update_display(dev)) {
return -EIO;
}
}
return 0;
}
static int uc81xx_controller_init(const struct device *dev)
{
const struct uc81xx_config *config = dev->config;
struct uc81xx_data *data = dev->data;
mipi_dbi_reset(config->mipi_dev, UC81XX_RESET_DELAY);
k_sleep(K_MSEC(UC81XX_RESET_DELAY));
uc81xx_busy_wait(dev);
data->blanking_on = true;
data->profile = UC81XX_PROFILE_INVALID;
if (uc81xx_set_profile(dev, UC81XX_PROFILE_FULL)) {
return -EIO;
}
if (uc81xx_clear_and_write_buffer(dev, 0xff, false)) {
return -EIO;
}
return 0;
}
static int uc81xx_init(const struct device *dev)
{
const struct uc81xx_config *config = dev->config;
LOG_DBG("");
if (!device_is_ready(config->mipi_dev)) {
LOG_ERR("MIPI device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&config->busy_gpio)) {
LOG_ERR("Busy GPIO device not ready");
return -ENODEV;
}
gpio_pin_configure_dt(&config->busy_gpio, GPIO_INPUT);
if (config->width > config->quirks->max_width ||
config->height > config->quirks->max_height) {
LOG_ERR("Display size out of range.");
return -EINVAL;
}
return uc81xx_controller_init(dev);
}
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8175)
static int uc81xx_set_tres_8(const struct device *dev)
{
const struct uc81xx_config *config = dev->config;
const struct uc81xx_tres8 tres = {
.hres = config->width,
.vres = config->height,
};
LOG_HEXDUMP_DBG(&tres, sizeof(tres), "TRES");
return uc81xx_write_cmd(dev, UC81XX_CMD_TRES, (const void *)&tres, sizeof(tres));
}
static inline int uc81xx_set_ptl_8(const struct device *dev, uint16_t x, uint16_t y,
uint16_t x_end_idx, uint16_t y_end_idx,
const struct display_buffer_descriptor *desc)
{
const struct uc81xx_ptl8 ptl = {
.hrst = x,
.hred = x_end_idx,
.vrst = y,
.vred = y_end_idx,
.flags = UC81XX_PTL_FLAG_PT_SCAN,
};
/* Setup Partial Window and enable Partial Mode */
LOG_HEXDUMP_DBG(&ptl, sizeof(ptl), "ptl");
return uc81xx_write_cmd(dev, UC81XX_CMD_PTL, (const void *)&ptl, sizeof(ptl));
}
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8176) || DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8179)
static int uc81xx_set_tres_16(const struct device *dev)
{
const struct uc81xx_config *config = dev->config;
const struct uc81xx_tres16 tres = {
.hres = sys_cpu_to_be16(config->width),
.vres = sys_cpu_to_be16(config->height),
};
LOG_HEXDUMP_DBG(&tres, sizeof(tres), "TRES");
return uc81xx_write_cmd(dev, UC81XX_CMD_TRES, (const void *)&tres, sizeof(tres));
}
static inline int uc81xx_set_ptl_16(const struct device *dev, uint16_t x, uint16_t y,
uint16_t x_end_idx, uint16_t y_end_idx,
const struct display_buffer_descriptor *desc)
{
const struct uc81xx_ptl16 ptl = {
.hrst = sys_cpu_to_be16(x),
.hred = sys_cpu_to_be16(x_end_idx),
.vrst = sys_cpu_to_be16(y),
.vred = sys_cpu_to_be16(y_end_idx),
.flags = UC81XX_PTL_FLAG_PT_SCAN,
};
/* Setup Partial Window and enable Partial Mode */
LOG_HEXDUMP_DBG(&ptl, sizeof(ptl), "ptl");
return uc81xx_write_cmd(dev, UC81XX_CMD_PTL, (const void *)&ptl, sizeof(ptl));
}
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8175) || DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8176)
static int uc8176_set_cdi(const struct device *dev, bool border)
{
const struct uc81xx_config *config = dev->config;
const struct uc81xx_data *data = dev->data;
const struct uc81xx_profile *p = config->profiles[data->profile];
uint8_t cdi = UC8176_CDI_VBD1 | UC8176_CDI_DDX0 |
(p ? (p->cdi & UC8176_CDI_CDI_MASK) : 0);
if (!p || !p->override_cdi) {
return 0;
}
if (!border) {
/* Floating border */
cdi |= UC8176_CDI_VBD1 | UC8176_CDI_VBD0;
}
LOG_DBG("CDI: %#hhx", cdi);
return uc81xx_write_cmd_uint8(dev, UC81XX_CMD_CDI, cdi);
}
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8175)
static const struct uc81xx_quirks uc8175_quirks = {
.max_width = 80,
.max_height = 160,
.auto_copy = false,
.set_cdi = uc8176_set_cdi,
.set_tres = uc81xx_set_tres_8,
.set_ptl = uc81xx_set_ptl_8,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8176)
static const struct uc81xx_quirks uc8176_quirks = {
.max_width = 400,
.max_height = 300,
.auto_copy = false,
.set_cdi = uc8176_set_cdi,
.set_tres = uc81xx_set_tres_16,
.set_ptl = uc81xx_set_ptl_16,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8179)
static int uc8179_set_cdi(const struct device *dev, bool border)
{
const struct uc81xx_config *config = dev->config;
const struct uc81xx_data *data = dev->data;
const struct uc81xx_profile *p = config->profiles[data->profile];
uint8_t cdi[UC8179_CDI_REG_LENGTH] = {
UC8179_CDI_BDV1 | UC8179_CDI_N2OCP | UC8179_CDI_DDX0,
p ? p->cdi : 0,
};
if (!p || !p->override_cdi) {
return 0;
}
cdi[UC8179_CDI_BDZ_DDX_IDX] |= border ? 0 : UC8179_CDI_BDZ;
LOG_HEXDUMP_DBG(cdi, sizeof(cdi), "CDI");
return uc81xx_write_cmd(dev, UC81XX_CMD_CDI, cdi, sizeof(cdi));
}
static const struct uc81xx_quirks uc8179_quirks = {
.max_width = 800,
.max_height = 600,
.auto_copy = true,
.set_cdi = uc8179_set_cdi,
.set_tres = uc81xx_set_tres_16,
.set_ptl = uc81xx_set_ptl_16,
};
#endif
static const struct display_driver_api uc81xx_driver_api = {
.blanking_on = uc81xx_blanking_on,
.blanking_off = uc81xx_blanking_off,
.write = uc81xx_write,
.get_capabilities = uc81xx_get_capabilities,
.set_pixel_format = uc81xx_set_pixel_format,
};
#define UC81XX_MAKE_ARRAY_OPT(n, p) \
static uint8_t data_ ## n ## _ ## p[] = DT_PROP_OR(n, p, {})
#define UC81XX_MAKE_ARRAY(n, p) \
static uint8_t data_ ## n ## _ ## p[] = DT_PROP(n, p)
#define UC81XX_ASSIGN_ARRAY(n, p) \
{ \
.data = data_ ## n ## _ ## p, \
.len = sizeof(data_ ## n ## _ ## p), \
}
#define UC81XX_PROFILE(n) \
UC81XX_MAKE_ARRAY_OPT(n, pwr); \
UC81XX_MAKE_ARRAY_OPT(n, lutc); \
UC81XX_MAKE_ARRAY_OPT(n, lutww); \
UC81XX_MAKE_ARRAY_OPT(n, lutkw); \
UC81XX_MAKE_ARRAY_OPT(n, lutwk); \
UC81XX_MAKE_ARRAY_OPT(n, lutkk); \
UC81XX_MAKE_ARRAY_OPT(n, lutbd); \
\
static const struct uc81xx_profile uc81xx_profile_ ## n = { \
.pwr = UC81XX_ASSIGN_ARRAY(n, pwr), \
.cdi = DT_PROP_OR(n, cdi, 0), \
.override_cdi = DT_NODE_HAS_PROP(n, cdi), \
.tcon = DT_PROP_OR(n, tcon, 0), \
.override_tcon = DT_NODE_HAS_PROP(n, tcon), \
.pll = DT_PROP_OR(n, pll, 0), \
.override_pll = DT_NODE_HAS_PROP(n, pll), \
.vdcs = DT_PROP_OR(n, vdcs, 0), \
.override_vdcs = DT_NODE_HAS_PROP(n, vdcs), \
\
.lutc = UC81XX_ASSIGN_ARRAY(n, lutc), \
.lutww = UC81XX_ASSIGN_ARRAY(n, lutww), \
.lutkw = UC81XX_ASSIGN_ARRAY(n, lutkw), \
.lutwk = UC81XX_ASSIGN_ARRAY(n, lutwk), \
.lutkk = UC81XX_ASSIGN_ARRAY(n, lutkk), \
.lutbd = UC81XX_ASSIGN_ARRAY(n, lutbd), \
};
#define _UC81XX_PROFILE_PTR(n) &uc81xx_profile_ ## n
#define UC81XX_PROFILE_PTR(n) \
COND_CODE_1(DT_NODE_EXISTS(n), \
(_UC81XX_PROFILE_PTR(n)), \
NULL)
#define UC81XX_DEFINE(n, quirks_ptr) \
UC81XX_MAKE_ARRAY_OPT(n, softstart); \
\
DT_FOREACH_CHILD(n, UC81XX_PROFILE); \
\
static const struct uc81xx_config uc81xx_cfg_ ## n = { \
.quirks = quirks_ptr, \
.mipi_dev = DEVICE_DT_GET(DT_PARENT(n)), \
.dbi_config = { \
.mode = MIPI_DBI_MODE_SPI_4WIRE, \
.config = MIPI_DBI_SPI_CONFIG_DT(n, \
SPI_OP_MODE_MASTER | \
SPI_LOCK_ON | SPI_WORD_SET(8), \
0), \
}, \
.busy_gpio = GPIO_DT_SPEC_GET(n, busy_gpios), \
\
.height = DT_PROP(n, height), \
.width = DT_PROP(n, width), \
\
.softstart = UC81XX_ASSIGN_ARRAY(n, softstart), \
\
.profiles = { \
[UC81XX_PROFILE_FULL] = \
UC81XX_PROFILE_PTR(DT_CHILD(n, full)), \
[UC81XX_PROFILE_PARTIAL] = \
UC81XX_PROFILE_PTR(DT_CHILD(n, partial)), \
}, \
}; \
\
static struct uc81xx_data uc81xx_data_##n = {}; \
\
DEVICE_DT_DEFINE(n, uc81xx_init, NULL, \
&uc81xx_data_ ## n, \
&uc81xx_cfg_ ## n, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&uc81xx_driver_api);
DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8175, UC81XX_DEFINE,
&uc8175_quirks);
DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8176, UC81XX_DEFINE,
&uc8176_quirks);
DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8179, UC81XX_DEFINE,
&uc8179_quirks);
``` | /content/code_sandbox/drivers/display/uc81xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,369 |
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