text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ssd1306, CONFIG_DISPLAY_LOG_LEVEL);
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/kernel.h>
#include "ssd1306_regs.h"
#define SSD1306_CLOCK_DIV_RATIO 0x0
#define SSD1306_CLOCK_FREQUENCY 0x8
#define SSD1306_PANEL_VCOM_DESEL_LEVEL 0x20
#define SSD1306_PANEL_PUMP_VOLTAGE SSD1306_SET_PUMP_VOLTAGE_90
#ifndef SSD1306_ADDRESSING_MODE
#define SSD1306_ADDRESSING_MODE (SSD1306_SET_MEM_ADDRESSING_HORIZONTAL)
#endif
union ssd1306_bus {
struct i2c_dt_spec i2c;
struct spi_dt_spec spi;
};
typedef bool (*ssd1306_bus_ready_fn)(const struct device *dev);
typedef int (*ssd1306_write_bus_fn)(const struct device *dev, uint8_t *buf, size_t len,
bool command);
typedef const char *(*ssd1306_bus_name_fn)(const struct device *dev);
struct ssd1306_config {
union ssd1306_bus bus;
struct gpio_dt_spec data_cmd;
struct gpio_dt_spec reset;
ssd1306_bus_ready_fn bus_ready;
ssd1306_write_bus_fn write_bus;
ssd1306_bus_name_fn bus_name;
uint16_t height;
uint16_t width;
uint8_t segment_offset;
uint8_t page_offset;
uint8_t display_offset;
uint8_t multiplex_ratio;
uint8_t prechargep;
bool segment_remap;
bool com_invdir;
bool com_sequential;
bool color_inversion;
bool sh1106_compatible;
int ready_time_ms;
bool use_internal_iref;
};
struct ssd1306_data {
enum display_pixel_format pf;
};
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1306fb, i2c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1106, i2c))
static bool ssd1306_bus_ready_i2c(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
return i2c_is_ready_dt(&config->bus.i2c);
}
static int ssd1306_write_bus_i2c(const struct device *dev, uint8_t *buf, size_t len, bool command)
{
const struct ssd1306_config *config = dev->config;
return i2c_burst_write_dt(&config->bus.i2c,
command ? SSD1306_CONTROL_ALL_BYTES_CMD :
SSD1306_CONTROL_ALL_BYTES_DATA,
buf, len);
}
static const char *ssd1306_bus_name_i2c(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
return config->bus.i2c.bus->name;
}
#endif
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1306fb, spi) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1106, spi))
static bool ssd1306_bus_ready_spi(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
if (gpio_pin_configure_dt(&config->data_cmd, GPIO_OUTPUT_INACTIVE) < 0) {
return false;
}
return spi_is_ready_dt(&config->bus.spi);
}
static int ssd1306_write_bus_spi(const struct device *dev, uint8_t *buf, size_t len, bool command)
{
const struct ssd1306_config *config = dev->config;
int ret;
gpio_pin_set_dt(&config->data_cmd, command ? 0 : 1);
struct spi_buf tx_buf = {
.buf = buf,
.len = len
};
struct spi_buf_set tx_bufs = {
.buffers = &tx_buf,
.count = 1
};
ret = spi_write_dt(&config->bus.spi, &tx_bufs);
return ret;
}
static const char *ssd1306_bus_name_spi(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
return config->bus.spi.bus->name;
}
#endif
static inline bool ssd1306_bus_ready(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
return config->bus_ready(dev);
}
static inline int ssd1306_write_bus(const struct device *dev, uint8_t *buf, size_t len,
bool command)
{
const struct ssd1306_config *config = dev->config;
return config->write_bus(dev, buf, len, command);
}
static inline int ssd1306_set_panel_orientation(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {(config->segment_remap ? SSD1306_SET_SEGMENT_MAP_REMAPED
: SSD1306_SET_SEGMENT_MAP_NORMAL),
(config->com_invdir ? SSD1306_SET_COM_OUTPUT_SCAN_FLIPPED
: SSD1306_SET_COM_OUTPUT_SCAN_NORMAL)};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static inline int ssd1306_set_timing_setting(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {SSD1306_SET_CLOCK_DIV_RATIO,
(SSD1306_CLOCK_FREQUENCY << 4) | SSD1306_CLOCK_DIV_RATIO,
SSD1306_SET_CHARGE_PERIOD,
config->prechargep,
SSD1306_SET_VCOM_DESELECT_LEVEL,
SSD1306_PANEL_VCOM_DESEL_LEVEL};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static inline int ssd1306_set_hardware_config(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {
SSD1306_SET_START_LINE,
SSD1306_SET_DISPLAY_OFFSET,
config->display_offset,
SSD1306_SET_PADS_HW_CONFIG,
(config->com_sequential ? SSD1306_SET_PADS_HW_SEQUENTIAL
: SSD1306_SET_PADS_HW_ALTERNATIVE),
SSD1306_SET_MULTIPLEX_RATIO,
config->multiplex_ratio,
};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static inline int ssd1306_set_charge_pump(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {
(config->sh1106_compatible ? SH1106_SET_DCDC_MODE : SSD1306_SET_CHARGE_PUMP_ON),
(config->sh1106_compatible ? SH1106_SET_DCDC_ENABLED
: SSD1306_SET_CHARGE_PUMP_ON_ENABLED),
SSD1306_PANEL_PUMP_VOLTAGE,
};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static inline int ssd1306_set_iref_mode(const struct device *dev)
{
int ret = 0;
const struct ssd1306_config *config = dev->config;
uint8_t cmd_buf[] = {
SSD1306_SET_IREF_MODE,
SSD1306_SET_IREF_MODE_INTERNAL,
};
if (config->use_internal_iref) {
ret = ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
return ret;
}
static int ssd1306_resume(const struct device *dev)
{
uint8_t cmd_buf[] = {
SSD1306_DISPLAY_ON,
};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static int ssd1306_suspend(const struct device *dev)
{
uint8_t cmd_buf[] = {
SSD1306_DISPLAY_OFF,
};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static int ssd1306_write_default(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf,
const size_t buf_len)
{
const struct ssd1306_config *config = dev->config;
uint8_t x_off = config->segment_offset;
uint8_t cmd_buf[] = {
SSD1306_SET_MEM_ADDRESSING_MODE,
SSD1306_ADDRESSING_MODE,
SSD1306_SET_COLUMN_ADDRESS,
x + x_off,
(x + desc->width - 1) + x_off,
SSD1306_SET_PAGE_ADDRESS,
y/8,
((y + desc->height)/8 - 1)
};
if (ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true)) {
LOG_ERR("Failed to write command");
return -1;
}
return ssd1306_write_bus(dev, (uint8_t *)buf, buf_len, false);
}
static int ssd1306_write_sh1106(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf,
const size_t buf_len)
{
const struct ssd1306_config *config = dev->config;
uint8_t x_offset = x + config->segment_offset;
uint8_t cmd_buf[] = {
SSD1306_SET_LOWER_COL_ADDRESS |
(x_offset & SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_SET_HIGHER_COL_ADDRESS |
((x_offset >> 4) & SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_SET_PAGE_START_ADDRESS | (y / 8)
};
uint8_t *buf_ptr = (uint8_t *)buf;
for (uint8_t n = 0; n < desc->height / 8; n++) {
cmd_buf[sizeof(cmd_buf) - 1] =
SSD1306_SET_PAGE_START_ADDRESS | (n + (y / 8));
LOG_HEXDUMP_DBG(cmd_buf, sizeof(cmd_buf), "cmd_buf");
if (ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true)) {
return -1;
}
if (ssd1306_write_bus(dev, buf_ptr, desc->width, false)) {
return -1;
}
buf_ptr = buf_ptr + desc->width;
if (buf_ptr > ((uint8_t *)buf + buf_len)) {
LOG_ERR("Exceeded buffer length");
return -1;
}
}
return 0;
}
static int ssd1306_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct ssd1306_config *config = dev->config;
size_t buf_len;
if (desc->pitch < desc->width) {
LOG_ERR("Pitch is smaller then width");
return -1;
}
buf_len = MIN(desc->buf_size, desc->height * desc->width / 8);
if (buf == NULL || buf_len == 0U) {
LOG_ERR("Display buffer is not available");
return -1;
}
if (desc->pitch > desc->width) {
LOG_ERR("Unsupported mode");
return -1;
}
if ((y & 0x7) != 0U) {
LOG_ERR("Unsupported origin");
return -1;
}
LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch,
desc->width, desc->height, buf_len);
if (config->sh1106_compatible) {
return ssd1306_write_sh1106(dev, x, y, desc, buf, buf_len);
}
return ssd1306_write_default(dev, x, y, desc, buf, buf_len);
}
static int ssd1306_set_contrast(const struct device *dev, const uint8_t contrast)
{
uint8_t cmd_buf[] = {
SSD1306_SET_CONTRAST_CTRL,
contrast,
};
return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
}
static void ssd1306_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct ssd1306_config *config = dev->config;
struct ssd1306_data *data = dev->data;
caps->x_resolution = config->width;
caps->y_resolution = config->height;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10 | PIXEL_FORMAT_MONO01;
caps->current_pixel_format = data->pf;
caps->screen_info = SCREEN_INFO_MONO_VTILED;
caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int ssd1306_set_pixel_format(const struct device *dev,
const enum display_pixel_format pf)
{
struct ssd1306_data *data = dev->data;
uint8_t cmd;
int ret;
if (pf == data->pf) {
return 0;
}
if (pf == PIXEL_FORMAT_MONO10) {
cmd = SSD1306_SET_REVERSE_DISPLAY;
} else if (pf == PIXEL_FORMAT_MONO01) {
cmd = SSD1306_SET_NORMAL_DISPLAY;
} else {
LOG_WRN("Unsupported pixel format");
return -ENOTSUP;
}
ret = ssd1306_write_bus(dev, &cmd, 1, true);
if (ret) {
return ret;
}
data->pf = pf;
return 0;
}
static int ssd1306_init_device(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
struct ssd1306_data *data = dev->data;
uint8_t cmd_buf[] = {
SSD1306_SET_ENTIRE_DISPLAY_OFF,
(config->color_inversion ? SSD1306_SET_REVERSE_DISPLAY
: SSD1306_SET_NORMAL_DISPLAY),
};
data->pf = config->color_inversion ? PIXEL_FORMAT_MONO10 : PIXEL_FORMAT_MONO01;
/* Reset if pin connected */
if (config->reset.port) {
k_sleep(K_MSEC(SSD1306_RESET_DELAY));
gpio_pin_set_dt(&config->reset, 1);
k_sleep(K_MSEC(SSD1306_RESET_DELAY));
gpio_pin_set_dt(&config->reset, 0);
}
/* Turn display off */
if (ssd1306_suspend(dev)) {
return -EIO;
}
if (ssd1306_set_timing_setting(dev)) {
return -EIO;
}
if (ssd1306_set_hardware_config(dev)) {
return -EIO;
}
if (ssd1306_set_panel_orientation(dev)) {
return -EIO;
}
if (ssd1306_set_charge_pump(dev)) {
return -EIO;
}
if (ssd1306_set_iref_mode(dev)) {
return -EIO;
}
if (ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true)) {
return -EIO;
}
if (ssd1306_set_contrast(dev, CONFIG_SSD1306_DEFAULT_CONTRAST)) {
return -EIO;
}
ssd1306_resume(dev);
return 0;
}
static int ssd1306_init(const struct device *dev)
{
const struct ssd1306_config *config = dev->config;
k_sleep(K_TIMEOUT_ABS_MS(config->ready_time_ms));
if (!ssd1306_bus_ready(dev)) {
LOG_ERR("Bus device %s not ready!", config->bus_name(dev));
return -EINVAL;
}
if (config->reset.port) {
int ret;
ret = gpio_pin_configure_dt(&config->reset,
GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
return ret;
}
}
if (ssd1306_init_device(dev)) {
LOG_ERR("Failed to initialize device!");
return -EIO;
}
return 0;
}
static const struct display_driver_api ssd1306_driver_api = {
.blanking_on = ssd1306_suspend,
.blanking_off = ssd1306_resume,
.write = ssd1306_write,
.set_contrast = ssd1306_set_contrast,
.get_capabilities = ssd1306_get_capabilities,
.set_pixel_format = ssd1306_set_pixel_format,
};
#define SSD1306_CONFIG_SPI(node_id) \
.bus = {.spi = SPI_DT_SPEC_GET( \
node_id, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0)}, \
.bus_ready = ssd1306_bus_ready_spi, \
.write_bus = ssd1306_write_bus_spi, \
.bus_name = ssd1306_bus_name_spi, \
.data_cmd = GPIO_DT_SPEC_GET(node_id, data_cmd_gpios),
#define SSD1306_CONFIG_I2C(node_id) \
.bus = {.i2c = I2C_DT_SPEC_GET(node_id)}, \
.bus_ready = ssd1306_bus_ready_i2c, \
.write_bus = ssd1306_write_bus_i2c, \
.bus_name = ssd1306_bus_name_i2c, \
.data_cmd = {0},
#define SSD1306_DEFINE(node_id) \
static struct ssd1306_data data##node_id; \
static const struct ssd1306_config config##node_id = { \
.reset = GPIO_DT_SPEC_GET_OR(node_id, reset_gpios, {0}), \
.height = DT_PROP(node_id, height), \
.width = DT_PROP(node_id, width), \
.segment_offset = DT_PROP(node_id, segment_offset), \
.page_offset = DT_PROP(node_id, page_offset), \
.display_offset = DT_PROP(node_id, display_offset), \
.multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \
.segment_remap = DT_PROP(node_id, segment_remap), \
.com_invdir = DT_PROP(node_id, com_invdir), \
.com_sequential = DT_PROP(node_id, com_sequential), \
.prechargep = DT_PROP(node_id, prechargep), \
.color_inversion = DT_PROP(node_id, inversion_on), \
.sh1106_compatible = DT_NODE_HAS_COMPAT(node_id, sinowealth_sh1106), \
.ready_time_ms = DT_PROP(node_id, ready_time_ms), \
.use_internal_iref = DT_PROP(node_id, use_internal_iref), \
COND_CODE_1(DT_ON_BUS(node_id, spi), (SSD1306_CONFIG_SPI(node_id)), \
(SSD1306_CONFIG_I2C(node_id))) \
}; \
\
DEVICE_DT_DEFINE(node_id, ssd1306_init, NULL, &data##node_id, &config##node_id, \
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1306_driver_api);
DT_FOREACH_STATUS_OKAY(solomon_ssd1306fb, SSD1306_DEFINE)
DT_FOREACH_STATUS_OKAY(sinowealth_sh1106, SSD1306_DEFINE)
``` | /content/code_sandbox/drivers/display/ssd1306.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,256 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_
/**
* @name Controller registers
* @{
*/
/* NT35510 ID */
#define NT35510_ID 0x80U
#define NT35510_CMD_NOP 0x00 /* NOP */
#define NT35510_CMD_SWRESET 0x01 /* SW reset */
#define NT35510_CMD_RDDID 0x04 /* Read display ID */
#define NT35510_CMD_RDNUMED 0x05 /* Read number of errors on DSI */
#define NT35510_CMD_RDDPM 0x0A /* Read display power mode */
#define NT35510_CMD_RDDMADCTL 0x0B /* Read display MADCTL */
#define NT35510_CMD_RDDCOLMOD 0x0C /* Read display pixel format */
#define NT35510_CMD_RDDIM 0x0D /* Read display image mode */
#define NT35510_CMD_RDDSM 0x0E /* Read display signal mode */
#define NT35510_CMD_RDDSDR 0x0F /* Read display self-diagnostics result */
#define NT35510_CMD_SLPIN 0x10 /* Sleep in */
#define NT35510_CMD_SLPOUT 0x11 /* Sleep out */
#define NT35510_CMD_PTLON 0x12 /* Partial mode on */
#define NT35510_CMD_NORON 0x13 /* Normal display mode on */
#define NT35510_CMD_INVOFF 0x20 /* Display inversion off */
#define NT35510_CMD_INVON 0x21 /* Display inversion on */
#define NT35510_CMD_ALLPOFF 0x22 /* All pixel off */
#define NT35510_CMD_ALLPON 0x23 /* All pixel on */
#define NT35510_CMD_GAMSET 0x26 /* Gamma set */
#define NT35510_CMD_DISPOFF 0x28 /* Display off */
#define NT35510_CMD_DISPON 0x29 /* Display on */
#define NT35510_CMD_CASET 0x2A /* Column address set */
#define NT35510_CMD_RASET 0x2B /* Row address set */
#define NT35510_CMD_RAMWR 0x2C /* Memory write */
#define NT35510_CMD_RAMRD 0x2E /* Memory read */
#define NT35510_CMD_PLTAR 0x30 /* Partial area */
#define NT35510_CMD_TOPC 0x32 /* Turn On Peripheral Command */
#define NT35510_CMD_TEOFF 0x34 /* Tearing effect line off */
#define NT35510_CMD_TEEON 0x35 /* Tearing effect line on */
#define NT35510_CMD_MADCTL 0x36 /* Memory data access control */
#define NT35510_CMD_IDMOFF 0x38 /* Idle mode off */
#define NT35510_CMD_IDMON 0x39 /* Idle mode on */
#define NT35510_CMD_COLMOD 0x3A /* Interface pixel format */
#define NT35510_CMD_RAMWRC 0x3C /* Memory write continue */
#define NT35510_CMD_RAMRDC 0x3E /* Memory read continue */
#define NT35510_CMD_STESL 0x44 /* Set tearing effect scan line */
#define NT35510_CMD_GSL 0x45 /* Get scan line */
#define NT35510_CMD_DSTBON 0x4F /* Deep standby mode on */
#define NT35510_CMD_WRPFD 0x50 /* Write profile value for display */
#define NT35510_CMD_WRDISBV 0x51 /* Write display brightness */
#define NT35510_CMD_RDDISBV 0x52 /* Read display brightness */
#define NT35510_CMD_WRCTRLD 0x53 /* Write CTRL display */
#define NT35510_CMD_RDCTRLD 0x54 /* Read CTRL display value */
#define NT35510_CMD_WRCABC 0x55 /* Write content adaptative brightness control */
#define NT35510_CMD_RDCABC 0x56 /* Read content adaptive brightness control */
#define NT35510_CMD_WRHYSTE 0x57 /* Write hysteresis */
#define NT35510_CMD_WRGAMMSET 0x58 /* Write gamme setting */
#define NT35510_CMD_RDFSVM 0x5A /* Read FS value MSBs */
#define NT35510_CMD_RDFSVL 0x5B /* Read FS value LSBs */
#define NT35510_CMD_RDMFFSVM 0x5C /* Read median filter FS value MSBs */
#define NT35510_CMD_RDMFFSVL 0x5D /* Read median filter FS value LSBs */
#define NT35510_CMD_WRCABCMB 0x5E /* Write CABC minimum brightness */
#define NT35510_CMD_RDCABCMB 0x5F /* Read CABC minimum brightness */
#define NT35510_CMD_WRLSCC 0x65 /* Write light sensor compensation coefficient value */
#define NT35510_CMD_RDLSCCM 0x66 /* Read light sensor compensation coefficient value MSBs */
#define NT35510_CMD_RDLSCCL 0x67 /* Read light sensor compensation coefficient value LSBs */
#define NT35510_CMD_RDBWLB 0x70 /* Read black/white low bits */
#define NT35510_CMD_RDBKX 0x71 /* Read Bkx */
#define NT35510_CMD_RDBKY 0x72 /* Read Bky */
#define NT35510_CMD_RDWX 0x73 /* Read Wx */
#define NT35510_CMD_RDWY 0x74 /* Read Wy */
#define NT35510_CMD_RDRGLB 0x75 /* Read red/green low bits */
#define NT35510_CMD_RDRX 0x76 /* Read Rx */
#define NT35510_CMD_RDRY 0x77 /* Read Ry */
#define NT35510_CMD_RDGX 0x78 /* Read Gx */
#define NT35510_CMD_RDGY 0x79 /* Read Gy */
#define NT35510_CMD_RDBALB 0x7A /* Read blue/acolor low bits */
#define NT35510_CMD_RDBX 0x7B /* Read Bx */
#define NT35510_CMD_RDBY 0x7C /* Read By */
#define NT35510_CMD_RDAX 0x7D /* Read Ax */
#define NT35510_CMD_RDAY 0x7E /* Read Ay */
#define NT35510_CMD_RDDDBS 0xA1 /* Read DDB start */
#define NT35510_CMD_RDDDBC 0xA8 /* Read DDB continue */
#define NT35510_CMD_RDDCS 0xAA /* Read first checksum */
#define NT35510_CMD_RDCCS 0xAF /* Read continue checksum */
#define NT35510_CMD_RDID1 0xDA /* Read ID1 value */
#define NT35510_CMD_RDID2 0xDB /* Read ID2 value */
#define NT35510_CMD_RDID3 0xDC /* Read ID3 value */
/** @} */
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_NT35510_H_ */
``` | /content/code_sandbox/drivers/display/display_nt35510.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,723 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_dcnano_lcdif
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <fsl_lcdif.h>
#ifdef CONFIG_HAS_MCUX_CACHE
#include <fsl_cache.h>
#endif
LOG_MODULE_REGISTER(display_mcux_dcnano_lcdif, CONFIG_DISPLAY_LOG_LEVEL);
struct mcux_dcnano_lcdif_config {
LCDIF_Type *base;
void (*irq_config_func)(const struct device *dev);
const struct gpio_dt_spec backlight_gpio;
lcdif_dpi_config_t dpi_config;
/* Pointer to start of first framebuffer */
uint8_t *fb_ptr;
/* Number of bytes used for each framebuffer */
uint32_t fb_bytes;
};
struct mcux_dcnano_lcdif_data {
/* Pointer to active framebuffer */
const uint8_t *active_fb;
uint8_t *fb[CONFIG_MCUX_DCNANO_LCDIF_FB_NUM];
lcdif_fb_config_t fb_config;
uint8_t pixel_bytes;
struct k_sem sem;
/* Tracks index of next active driver framebuffer */
uint8_t next_idx;
};
static int mcux_dcnano_lcdif_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
struct mcux_dcnano_lcdif_data *data = dev->data;
uint32_t h_idx;
const uint8_t *src;
uint8_t *dst;
__ASSERT((data->pixel_bytes * desc->pitch * desc->height) <=
desc->buf_size, "Input buffer too small");
LOG_DBG("W=%d, H=%d @%d,%d", desc->width, desc->height, x, y);
if ((x == 0) && (y == 0) &&
(desc->width == config->dpi_config.panelWidth) &&
(desc->height == config->dpi_config.panelHeight) &&
(desc->pitch == desc->width)) {
/* We can use the display buffer directly, without copying */
LOG_DBG("Setting FB from %p->%p",
(void *)data->active_fb, (void *)buf);
data->active_fb = buf;
} else {
/* We must use partial framebuffer copy */
if (CONFIG_MCUX_DCNANO_LCDIF_FB_NUM == 0) {
LOG_ERR("Partial display refresh requires driver framebuffers");
return -ENOTSUP;
} else if (data->active_fb != data->fb[data->next_idx]) {
/*
* Copy the entirety of the current framebuffer to new
* buffer, since we are changing the active buffer address
*/
src = data->active_fb;
dst = data->fb[data->next_idx];
memcpy(dst, src, config->fb_bytes);
}
/* Write the display update to the active framebuffer */
src = buf;
dst = data->fb[data->next_idx];
dst += data->pixel_bytes * (y * config->dpi_config.panelWidth + x);
for (h_idx = 0; h_idx < desc->height; h_idx++) {
memcpy(dst, src, data->pixel_bytes * desc->width);
src += data->pixel_bytes * desc->pitch;
dst += data->pixel_bytes * config->dpi_config.panelWidth;
}
LOG_DBG("Setting FB from %p->%p", (void *) data->active_fb,
(void *) data->fb[data->next_idx]);
/* Set new active framebuffer */
data->active_fb = data->fb[data->next_idx];
}
#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_MCUX_DCNANO_LCDIF_MAINTAIN_CACHE)
CACHE64_CleanCacheByRange((uint32_t) data->active_fb,
config->fb_bytes);
#endif
k_sem_reset(&data->sem);
/* Set new framebuffer */
LCDIF_SetFrameBufferStride(config->base, 0,
config->dpi_config.panelWidth * data->pixel_bytes);
LCDIF_SetFrameBufferAddr(config->base, 0,
(uint32_t)data->active_fb);
LCDIF_SetFrameBufferConfig(config->base, 0, &data->fb_config);
#if CONFIG_MCUX_DCNANO_LCDIF_FB_NUM != 0
/* Update index of active framebuffer */
data->next_idx = (data->next_idx + 1) % CONFIG_MCUX_DCNANO_LCDIF_FB_NUM;
#endif
/* Wait for frame to complete */
k_sem_take(&data->sem, K_FOREVER);
return 0;
}
static void mcux_dcnano_lcdif_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
struct mcux_dcnano_lcdif_data *data = dev->data;
capabilities->y_resolution = config->dpi_config.panelHeight;
capabilities->x_resolution = config->dpi_config.panelWidth;
capabilities->supported_pixel_formats =
(PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888);
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
switch (data->fb_config.format) {
case kLCDIF_PixelFormatRGB565:
/* Zephyr stores RGB565 as big endian, and LCDIF
* expects little endian. Use BGR565 format to resolve
* this.
*/
capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
break;
case kLCDIF_PixelFormatXRGB8888:
capabilities->current_pixel_format = PIXEL_FORMAT_ARGB_8888;
break;
default:
/* Other LCDIF formats don't have a Zephyr enum yet */
return;
}
}
static void *mcux_dcnano_lcdif_get_framebuffer(const struct device *dev)
{
struct mcux_dcnano_lcdif_data *data = dev->data;
return (void *)data->active_fb;
}
static int mcux_dcnano_lcdif_display_blanking_off(const struct device *dev)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
return gpio_pin_set_dt(&config->backlight_gpio, 1);
}
static int mcux_dcnano_lcdif_display_blanking_on(const struct device *dev)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
return gpio_pin_set_dt(&config->backlight_gpio, 0);
}
static int mcux_dcnano_lcdif_set_pixel_format(const struct device *dev,
const enum display_pixel_format
pixel_format)
{
struct mcux_dcnano_lcdif_data *data = dev->data;
switch (pixel_format) {
case PIXEL_FORMAT_BGR_565:
/* Zephyr stores RGB565 as big endian, and LCDIF
* expects little endian. Use BGR565 format to resolve
* this.
*/
data->fb_config.format = kLCDIF_PixelFormatRGB565;
data->pixel_bytes = 2;
break;
case PIXEL_FORMAT_ARGB_8888:
data->fb_config.format = kLCDIF_PixelFormatXRGB8888;
data->pixel_bytes = 4;
break;
default:
return -ENOTSUP;
}
return 0;
}
static void mcux_dcnano_lcdif_isr(const struct device *dev)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
struct mcux_dcnano_lcdif_data *data = dev->data;
uint32_t status;
status = LCDIF_GetAndClearInterruptPendingFlags(config->base);
if (0 != (status & kLCDIF_Display0FrameDoneInterrupt)) {
k_sem_give(&data->sem);
}
}
static int mcux_dcnano_lcdif_init(const struct device *dev)
{
const struct mcux_dcnano_lcdif_config *config = dev->config;
struct mcux_dcnano_lcdif_data *data = dev->data;
int ret;
ret = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT_ACTIVE);
if (ret) {
return ret;
}
/* Convert pixel format from devicetree to the format used by HAL */
ret = mcux_dcnano_lcdif_set_pixel_format(dev, data->fb_config.format);
if (ret) {
return ret;
}
LCDIF_Init(config->base);
LCDIF_DpiModeSetConfig(config->base, 0, &config->dpi_config);
LCDIF_EnableInterrupts(config->base, kLCDIF_Display0FrameDoneInterrupt);
config->irq_config_func(dev);
for (int i = 0; i < CONFIG_MCUX_DCNANO_LCDIF_FB_NUM; i++) {
/* Record pointers to each driver framebuffer */
data->fb[i] = config->fb_ptr + (config->fb_bytes * i);
}
data->active_fb = config->fb_ptr;
k_sem_init(&data->sem, 1, 1);
#ifdef CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
/* Clear external memory, as it is uninitialized */
memset(config->fb_ptr, 0, config->fb_bytes * CONFIG_MCUX_DCNANO_LCDIF_FB_NUM);
#endif
return 0;
}
static const struct display_driver_api mcux_dcnano_lcdif_api = {
.blanking_on = mcux_dcnano_lcdif_display_blanking_on,
.blanking_off = mcux_dcnano_lcdif_display_blanking_off,
.set_pixel_format = mcux_dcnano_lcdif_set_pixel_format,
.write = mcux_dcnano_lcdif_write,
.get_capabilities = mcux_dcnano_lcdif_get_capabilities,
.get_framebuffer = mcux_dcnano_lcdif_get_framebuffer,
};
#define MCUX_DCNANO_LCDIF_PIXEL_BYTES(n) \
(DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(n, pixel_format)) / 8)
#define MCUX_DCNANO_LCDIF_FB_SIZE(n) DT_INST_PROP(n, width) * \
DT_INST_PROP(n, height) * MCUX_DCNANO_LCDIF_PIXEL_BYTES(n)
/* When using external framebuffer mem, we should not allocate framebuffers
* in SRAM. Instead, we use external framebuffer address and size
* from devicetree.
*/
#ifdef CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
#define MCUX_DCNANO_LCDIF_FRAMEBUFFER_DECL(n)
#define MCUX_DCNANO_LCDIF_FRAMEBUFFER(n) \
(uint8_t *)CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
#else
#define MCUX_DCNANO_LCDIF_FRAMEBUFFER_DECL(n) uint8_t __aligned(LCDIF_FB_ALIGN) \
mcux_dcnano_lcdif_frame_buffer_##n[DT_INST_PROP(n, width) * \
DT_INST_PROP(n, height) * \
MCUX_DCNANO_LCDIF_PIXEL_BYTES(n) * \
CONFIG_MCUX_DCNANO_LCDIF_FB_NUM]
#define MCUX_DCNANO_LCDIF_FRAMEBUFFER(n) mcux_dcnano_lcdif_frame_buffer_##n
#endif
#define MCUX_DCNANO_LCDIF_DEVICE_INIT(n) \
static void mcux_dcnano_lcdif_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
mcux_dcnano_lcdif_isr, \
DEVICE_DT_INST_GET(n), \
0); \
irq_enable(DT_INST_IRQN(n)); \
} \
MCUX_DCNANO_LCDIF_FRAMEBUFFER_DECL(n); \
struct mcux_dcnano_lcdif_data mcux_dcnano_lcdif_data_##n = { \
.fb_config = { \
.enable = true, \
.enableGamma = false, \
.format = DT_INST_PROP(n, pixel_format), \
}, \
.next_idx = 0, \
.pixel_bytes = MCUX_DCNANO_LCDIF_PIXEL_BYTES(n), \
}; \
struct mcux_dcnano_lcdif_config mcux_dcnano_lcdif_config_##n = { \
.base = (LCDIF_Type *) DT_INST_REG_ADDR(n), \
.irq_config_func = mcux_dcnano_lcdif_config_func_##n, \
.backlight_gpio = GPIO_DT_SPEC_INST_GET(n, backlight_gpios), \
.dpi_config = { \
.panelWidth = DT_INST_PROP(n, width), \
.panelHeight = DT_INST_PROP(n, height), \
.hsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
hsync_len), \
.hfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
hfront_porch), \
.hbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
hback_porch), \
.vsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
vsync_len), \
.vfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
vfront_porch), \
.vbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
vback_porch), \
.polarityFlags = (DT_PROP(DT_INST_CHILD(n, \
display_timings), de_active) ? \
kLCDIF_DataEnableActiveHigh : \
kLCDIF_DataEnableActiveLow) | \
(DT_PROP(DT_INST_CHILD(n, \
display_timings), pixelclk_active) ? \
kLCDIF_DriveDataOnRisingClkEdge : \
kLCDIF_DriveDataOnFallingClkEdge) | \
(DT_PROP(DT_INST_CHILD(n, \
display_timings), hsync_active) ? \
kLCDIF_HsyncActiveHigh : \
kLCDIF_HsyncActiveLow) | \
(DT_PROP(DT_INST_CHILD(n, \
display_timings), vsync_active) ? \
kLCDIF_VsyncActiveHigh : \
kLCDIF_VsyncActiveLow), \
.format = DT_INST_ENUM_IDX(n, data_bus_width), \
}, \
.fb_ptr = MCUX_DCNANO_LCDIF_FRAMEBUFFER(n), \
.fb_bytes = MCUX_DCNANO_LCDIF_FB_SIZE(n), \
}; \
DEVICE_DT_INST_DEFINE(n, \
&mcux_dcnano_lcdif_init, \
NULL, \
&mcux_dcnano_lcdif_data_##n, \
&mcux_dcnano_lcdif_config_##n, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&mcux_dcnano_lcdif_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_DCNANO_LCDIF_DEVICE_INIT)
``` | /content/code_sandbox/drivers/display/display_mcux_dcnano_lcdif.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,341 |
```c
/*
*
*/
#define DT_DRV_COMPAT sitronix_st7796s
#include <zephyr/device.h>
#include <zephyr/drivers/display.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_st7796s, CONFIG_DISPLAY_LOG_LEVEL);
#include "display_st7796s.h"
/* Magic numbers used to lock/unlock command settings */
#define ST7796S_UNLOCK_1 0xC3
#define ST7796S_UNLOCK_2 0x96
#define ST7796S_LOCK_1 0x3C
#define ST7796S_LOCK_2 0x69
#define ST7796S_PIXEL_SIZE 2 /* Only 16 bit color mode supported with this driver */
struct st7796s_config {
const struct device *mipi_dbi;
const struct mipi_dbi_config dbi_config;
uint16_t width;
uint16_t height;
bool inverted; /* Display color inversion */
/* Display configuration parameters */
uint8_t dic; /* Display inversion control */
uint8_t frmctl1[2]; /* Frame rate control, normal mode */
uint8_t frmctl2[2]; /* Frame rate control, idle mode */
uint8_t frmctl3[2]; /* Frame rate control, partial mode */
uint8_t bpc[4]; /* Blanking porch control */
uint8_t dfc[4]; /* Display function control */
uint8_t pwr1[2]; /* Power control 1 */
uint8_t pwr2; /* Power control 2 */
uint8_t pwr3; /* Power control 3 */
uint8_t vcmpctl; /* VCOM control */
uint8_t doca[8]; /* Display output ctrl */
uint8_t pgc[14]; /* Positive gamma control */
uint8_t ngc[14]; /* Negative gamma control */
uint8_t madctl; /* Memory data access control */
bool rgb_is_inverted;
};
static int st7796s_send_cmd(const struct device *dev,
uint8_t cmd, const uint8_t *data, size_t len)
{
const struct st7796s_config *config = dev->config;
return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config,
cmd, data, len);
}
static int st7796s_set_cursor(const struct device *dev,
const uint16_t x, const uint16_t y,
const uint16_t width, const uint16_t height)
{
uint16_t addr_data[2];
int ret;
/* Column address */
addr_data[0] = sys_cpu_to_be16(x);
addr_data[1] = sys_cpu_to_be16(x + width - 1);
ret = st7796s_send_cmd(dev, ST7796S_CMD_CASET,
(uint8_t *)addr_data, sizeof(addr_data));
if (ret < 0) {
return ret;
}
/* Row address */
addr_data[0] = sys_cpu_to_be16(y);
addr_data[1] = sys_cpu_to_be16(y + height - 1);
ret = st7796s_send_cmd(dev, ST7796S_CMD_RASET,
(uint8_t *)addr_data, sizeof(addr_data));
return ret;
}
static int st7796s_blanking_on(const struct device *dev)
{
return st7796s_send_cmd(dev, ST7796S_CMD_DISPOFF, NULL, 0);
}
static int st7796s_blanking_off(const struct device *dev)
{
return st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0);
}
static int st7796s_get_pixelfmt(const struct device *dev)
{
const struct st7796s_config *config = dev->config;
/*
* Invert the pixel format for 8-bit 8080 Parallel Interface.
*
* Zephyr uses big endian byte order when the pixel format has
* multiple bytes.
*
* For RGB565, Red is placed in byte 1 and Blue in byte 0.
* For BGR565, Red is placed in byte 0 and Blue in byte 1.
*
* This is not an issue when using a 16-bit interface.
* For RGB565, this would map to Red being in D[11:15] and
* Blue in D[0:4] and vice versa for BGR565.
*
* However this is an issue when using a 8-bit interface.
* For RGB565, Blue is placed in byte 0 as mentioned earlier.
* However the controller expects Red to be in D[3:7] of byte 0.
*
* Hence we report pixel format as RGB when MADCTL setting is BGR
* and vice versa.
*/
if (config->dbi_config.mode == MIPI_DBI_MODE_8080_BUS_8_BIT) {
if (config->madctl & ST7796S_MADCTL_BGR) {
return PIXEL_FORMAT_RGB_565;
} else {
return PIXEL_FORMAT_BGR_565;
}
}
/*
* Invert the pixel format if rgb_is_inverted is enabled.
* Report pixel format as the same format set in the MADCTL
* if rgb_is_inverted is disabled.
* Report pixel format as RGB if MADCTL setting is BGR and vice versa
* if rgb_is_inverted is enabled.
* It is a workaround for supporting buggy modules that display RGB as BGR.
*/
if (!(config->madctl & ST7796S_MADCTL_BGR) != !config->rgb_is_inverted) {
return PIXEL_FORMAT_BGR_565;
} else {
return PIXEL_FORMAT_RGB_565;
}
}
static int st7796s_write(const struct device *dev,
const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct st7796s_config *config = dev->config;
int ret;
struct display_buffer_descriptor mipi_desc;
enum display_pixel_format pixfmt;
ret = st7796s_set_cursor(dev, x, y, desc->width, desc->height);
if (ret < 0) {
return ret;
}
mipi_desc.buf_size = desc->width * desc->height * ST7796S_PIXEL_SIZE;
ret = mipi_dbi_command_write(config->mipi_dbi,
&config->dbi_config, ST7796S_CMD_RAMWR,
NULL, 0);
if (ret < 0) {
return ret;
}
pixfmt = st7796s_get_pixelfmt(dev);
return mipi_dbi_write_display(config->mipi_dbi,
&config->dbi_config, buf,
&mipi_desc, pixfmt);
}
static void st7796s_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct st7796s_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->current_pixel_format = st7796s_get_pixelfmt(dev);
capabilities->x_resolution = config->width;
capabilities->y_resolution = config->height;
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int st7796s_lcd_config(const struct device *dev)
{
const struct st7796s_config *config = dev->config;
int ret;
uint8_t param;
/* Unlock display configuration */
param = ST7796S_UNLOCK_1;
ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
if (ret < 0) {
return ret;
}
param = ST7796S_UNLOCK_2;
ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_DIC, &config->dic, sizeof(config->dic));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR1, config->frmctl1,
sizeof(config->frmctl1));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR2, config->frmctl2,
sizeof(config->frmctl2));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_FRMCTR3, config->frmctl3,
sizeof(config->frmctl3));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_BPC, config->bpc, sizeof(config->bpc));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_DFC, config->dfc, sizeof(config->dfc));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR1, config->pwr1, sizeof(config->pwr1));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR2, &config->pwr2, sizeof(config->pwr2));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_PWR3, &config->pwr3, sizeof(config->pwr3));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_VCMPCTL, &config->vcmpctl,
sizeof(config->vcmpctl));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_DOCA, config->doca,
sizeof(config->doca));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_PGC, config->pgc, sizeof(config->pgc));
if (ret < 0) {
return ret;
}
ret = st7796s_send_cmd(dev, ST7796S_CMD_NGC, config->ngc, sizeof(config->ngc));
if (ret < 0) {
return ret;
}
/* Lock display configuration */
param = ST7796S_LOCK_1;
ret = st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
if (ret < 0) {
return ret;
}
param = ST7796S_LOCK_2;
return st7796s_send_cmd(dev, ST7796S_CMD_CSCON, ¶m, sizeof(param));
}
static int st7796s_init(const struct device *dev)
{
const struct st7796s_config *config = dev->config;
int ret;
uint8_t param;
/* Since VDDI comes up before reset pin is low, we must reset display
* state. Pulse for 100 MS, per datasheet
*/
ret = mipi_dbi_reset(config->mipi_dbi, 100);
if (ret < 0) {
return ret;
}
/* Delay an additional 100ms after reset */
k_msleep(100);
/* Configure controller parameters */
ret = st7796s_lcd_config(dev);
if (ret < 0) {
LOG_ERR("Could not set LCD configuration (%d)", ret);
return ret;
}
if (config->inverted) {
ret = st7796s_send_cmd(dev, ST7796S_CMD_INVON, NULL, 0);
} else {
ret = st7796s_send_cmd(dev, ST7796S_CMD_INVOFF, NULL, 0);
}
if (ret < 0) {
return ret;
}
param = ST7796S_CONTROL_16BIT;
ret = st7796s_send_cmd(dev, ST7796S_CMD_COLMOD, ¶m, sizeof(param));
if (ret < 0) {
return ret;
}
param = config->madctl;
ret = st7796s_send_cmd(dev, ST7796S_CMD_MADCTL, ¶m, sizeof(param));
if (ret < 0) {
return ret;
}
/* Exit sleep */
st7796s_send_cmd(dev, ST7796S_CMD_SLPOUT, NULL, 0);
/* Delay 5ms after sleep out command, per datasheet */
k_msleep(5);
/* Turn on display */
st7796s_send_cmd(dev, ST7796S_CMD_DISPON, NULL, 0);
return 0;
}
static const struct display_driver_api st7796s_api = {
.blanking_on = st7796s_blanking_on,
.blanking_off = st7796s_blanking_off,
.write = st7796s_write,
.get_capabilities = st7796s_get_capabilities,
};
#define ST7796S_INIT(n) \
static const struct st7796s_config st7796s_config_##n = { \
.mipi_dbi = DEVICE_DT_GET(DT_INST_PARENT(n)), \
.dbi_config = { \
.config = MIPI_DBI_SPI_CONFIG_DT( \
DT_DRV_INST(n), \
SPI_OP_MODE_MASTER | \
SPI_WORD_SET(8), \
0), \
.mode = DT_INST_PROP_OR(n, mipi_mode, \
MIPI_DBI_MODE_SPI_4WIRE), \
}, \
.width = DT_INST_PROP(n, width), \
.height = DT_INST_PROP(n, height), \
.inverted = DT_INST_PROP(n, color_invert), \
.dic = DT_INST_ENUM_IDX(n, invert_mode), \
.frmctl1 = DT_INST_PROP(n, frmctl1), \
.frmctl2 = DT_INST_PROP(n, frmctl2), \
.frmctl3 = DT_INST_PROP(n, frmctl3), \
.bpc = DT_INST_PROP(n, bpc), \
.dfc = DT_INST_PROP(n, dfc), \
.pwr1 = DT_INST_PROP(n, pwr1), \
.pwr2 = DT_INST_PROP(n, pwr2), \
.pwr3 = DT_INST_PROP(n, pwr3), \
.vcmpctl = DT_INST_PROP(n, vcmpctl), \
.doca = DT_INST_PROP(n, doca), \
.pgc = DT_INST_PROP(n, pgc), \
.ngc = DT_INST_PROP(n, ngc), \
.madctl = DT_INST_PROP(n, madctl), \
.rgb_is_inverted = DT_INST_PROP(n, rgb_is_inverted), \
}; \
\
DEVICE_DT_INST_DEFINE(n, st7796s_init, \
NULL, \
NULL, \
&st7796s_config_##n, \
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \
&st7796s_api);
DT_INST_FOREACH_STATUS_OKAY(ST7796S_INIT)
``` | /content/code_sandbox/drivers/display/display_st7796s.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,408 |
```objective-c
/*
*
*/
#ifndef ST7735R_DISPLAY_DRIVER_H__
#define ST7735R_DISPLAY_DRIVER_H__
#include <zephyr/kernel.h>
#define ST7735R_CMD_SW_RESET 0x01
#define ST7735R_CMD_RDDID 0x04
#define ST7735R_CMD_RDDST 0x09
#define ST7735R_CMD_RDDPM 0x0A
#define ST7735R_CMD_RDD_MADCTL 0x0B
#define ST7735R_CMD_RDD_COLMOD 0x0C
#define ST7735R_CMD_RDDIM 0x0D
#define ST7735R_CMD_RDDSM 0x0E
#define ST7735R_CMD_SLEEP_IN 0x10
#define ST7735R_CMD_SLEEP_OUT 0x11
#define ST7735R_CMD_PTLON 0x12
#define ST7735R_CMD_NORON 0x13
#define ST7735R_CMD_INV_OFF 0x20
#define ST7735R_CMD_INV_ON 0x21
#define ST7735R_CMD_GAMSET 0x26
#define ST7735R_CMD_DISP_OFF 0x28
#define ST7735R_CMD_DISP_ON 0x29
#define ST7735R_CMD_CASET 0x2a
#define ST7735R_CMD_RASET 0x2b
#define ST7735R_CMD_RAMWR 0x2c
#define ST7735R_CMD_RGBSET 0x2D
#define ST7735R_CMD_RAMRD 0x2E
#define ST7735R_CMD_PTLAR 0x30
#define ST7735R_CMD_TEOFF 0x34
#define ST7735R_CMD_TEON 0x35
#define ST7735R_CMD_MADCTL 0x36
#define ST7735R_CMD_IDMOFF 0x38
#define ST7735R_CMD_IDMON 0x39
#define ST7735R_CMD_COLMOD 0x3a
#define ST7735R_CMD_FRMCTR1 0xB1
#define ST7735R_CMD_FRMCTR2 0xB2
#define ST7735R_CMD_FRMCTR3 0xB3
#define ST7735R_CMD_INVCTR 0xB4
#define ST7735R_CMD_PWCTR1 0xC0
#define ST7735R_CMD_PWCTR2 0xC1
#define ST7735R_CMD_PWCTR3 0xC2
#define ST7735R_CMD_PWCTR4 0xC3
#define ST7735R_CMD_PWCTR5 0xC4
#define ST7735R_CMD_VMCTR1 0xC5
#define ST7735R_CMD_VMOFCTR 0xC7
#define ST7735R_CMD_WRID2 0xD1
#define ST7735R_CMD_WRID3 0xD2
#define ST7735R_CMD_NVCTR1 0xD9
#define ST7735R_CMD_NVCTR2 0xDE
#define ST7735R_CMD_NVCTR3 0xDF
#define ST7735R_CMD_RDID1 0xDA
#define ST7735R_CMD_RDID2 0xDB
#define ST7735R_CMD_RDID3 0xDC
#define ST7735R_CMD_NVCTR2 0xDE
#define ST7735R_CMD_NVCTR3 0xDF
#define ST7735R_CMD_GAMCTRP1 0xE0
#define ST7735R_CMD_GAMCTRN1 0xE1
/* CMD_MADCTL bits */
#define ST7735R_MADCTL_RBG 0x00
#define ST7735R_MADCTL_BGR 0x08
#endif /* ST7735R_DISPLAY_DRIVER_H__ */
``` | /content/code_sandbox/drivers/display/display_st7735r.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 859 |
```unknown
config NT35510
bool "NT35510 display driver"
default y
depends on DT_HAS_FRIDA_NT35510_ENABLED
select MIPI_DSI
help
Enable driver for NT35510 display driver.
if NT35510
config DISPLAY_NT35510_INIT_PRIORITY
int "Initialization priority"
default DISPLAY_INIT_PRIORITY
help
NT35510 display driver initialization priority.
endif
``` | /content/code_sandbox/drivers/display/Kconfig.nt35510 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
# STM32 LTDC display driver configuration options
menuconfig STM32_LTDC
bool "STM32 LCD-TFT display controller driver"
default y
depends on DT_HAS_ST_STM32_LTDC_ENABLED
select USE_STM32_HAL_LTDC
select CACHE_MANAGEMENT if CPU_HAS_DCACHE
help
Enable driver for STM32 LCT-TFT display controller periheral.
if STM32_LTDC
choice STM32_LTDC_PIXEL_FORMAT
prompt "Color pixel format"
default STM32_LTDC_RGB565
depends on STM32_LTDC
help
Specify the color pixel format for the STM32 LCD-TFT display controller.
config STM32_LTDC_ARGB8888
bool "ARGB8888"
help
One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
(4 bytes per pixel)
config STM32_LTDC_RGB888
bool "RGB888"
help
One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
(3 bytes per pixel)
config STM32_LTDC_RGB565
bool "RGB565"
help
One pixel consists of 5-bit red, 6-bit green and 5-bit blue value
(2 bytes per pixel)
endchoice
config STM32_LTDC_FB_NUM
int "Frame buffer number"
default 1
range 0 2
help
STM32 LTDC frame buffer number config:
- 0 frame buffer maintained by application, must write with full screen pixels.
- 1 single frame buffer in stm32 ltdc driver.
- 2 double frame buffer in stm32 ltdc driver.
config STM32_LTDC_DISABLE_FMC_BANK1
bool "Disable FMC bank1 for STM32F7/H7 series"
depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32F7X
default y
help
Disable FMC bank1 if not used to prevent speculative read accesses.
Refer to AN4861 "4.6 Special recommendations for Cortex-M7 (STM32F7/H7)".
endif # STM32_LTDC
``` | /content/code_sandbox/drivers/display/Kconfig.stm32_ltdc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 461 |
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ssd1327, CONFIG_DISPLAY_LOG_LEVEL);
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/kernel.h>
#include "ssd1327_regs.h"
#define SSD1327_ENABLE_VDD 0x01
#define SSD1327_ENABLE_SECOND_PRECHARGE 0x62
#define SSD1327_VCOMH_VOLTAGE 0x0f
#define SSD1327_PHASES_VALUE 0xf1
#define SSD1327_DEFAULT_PRECHARGE_V 0x08
#define SSD1327_UNLOCK_COMMAND 0x12
struct ssd1327_config {
const struct device *mipi_dev;
const struct mipi_dbi_config dbi_config;
uint16_t height;
uint16_t width;
uint8_t oscillator_freq;
uint8_t start_line;
uint8_t display_offset;
uint8_t multiplex_ratio;
uint8_t prechargep;
uint8_t remap_value;
bool color_inversion;
};
struct ssd1327_data {
uint8_t contrast;
uint8_t scan_mode;
};
static inline int ssd1327_write_bus_cmd(const struct device *dev, const uint8_t cmd,
const uint8_t *data, size_t len)
{
const struct ssd1327_config *config = dev->config;
int err;
/* Values given after the memory register must be sent with pin D/C set to 0. */
/* Data is sent as a command following the mipi_cbi api */
err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, NULL, 0);
if (err) {
return err;
}
for (size_t i = 0; i < len; i++) {
err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
data[i], NULL, 0);
if (err) {
return err;
}
}
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return 0;
}
static inline int ssd1327_set_timing_setting(const struct device *dev)
{
const struct ssd1327_config *config = dev->config;
uint8_t buf;
buf = SSD1327_PHASES_VALUE;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PHASE_LENGTH, &buf, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_OSC_FREQ, &config->oscillator_freq, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_PERIOD, &config->prechargep, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_LINEAR_LUT, NULL, 0)) {
return -EIO;
}
buf = SSD1327_DEFAULT_PRECHARGE_V;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_PRECHARGE_VOLTAGE, &buf, 1)) {
return -EIO;
}
buf = SSD1327_VCOMH_VOLTAGE;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_VCOMH, &buf, 1)) {
return -EIO;
}
buf = SSD1327_ENABLE_SECOND_PRECHARGE;
if (ssd1327_write_bus_cmd(dev, SSD1327_FUNCTION_SELECTION_B, &buf, 1)) {
return -EIO;
}
buf = SSD1327_UNLOCK_COMMAND;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COMMAND_LOCK, &buf, 1)) {
return -EIO;
}
return 0;
}
static inline int ssd1327_set_hardware_config(const struct device *dev)
{
const struct ssd1327_config *config = dev->config;
uint8_t buf;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_START_LINE, &config->start_line, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_DISPLAY_OFFSET, &config->display_offset, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_NORMAL_DISPLAY, NULL, 0)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_MULTIPLEX_RATIO, &config->multiplex_ratio, 1)) {
return -EIO;
}
buf = SSD1327_ENABLE_VDD;
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_FUNCTION_A, &buf, 1)) {
return -EIO;
}
return 0;
}
static int ssd1327_resume(const struct device *dev)
{
return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_ON, NULL, 0);
}
static int ssd1327_suspend(const struct device *dev)
{
return ssd1327_write_bus_cmd(dev, SSD1327_DISPLAY_OFF, NULL, 0);
}
static int ssd1327_set_display(const struct device *dev)
{
const struct ssd1327_config *config = dev->config;
uint8_t x_position[] = {
0,
config->width - 1
};
uint8_t y_position[] = {
0,
config->height - 1
};
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position))) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position))) {
return -EIO;
}
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_SEGMENT_MAP_REMAPED, &config->remap_value, 1)) {
return -EIO;
}
return 0;
}
static int ssd1327_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct ssd1327_config *config = dev->config;
struct display_buffer_descriptor mipi_desc;
int err;
size_t buf_len;
uint8_t x_position[] = { x, x + desc->width - 1 };
uint8_t y_position[] = { y, y + desc->height - 1 };
if (desc->pitch < desc->width) {
LOG_ERR("Pitch is smaller than width");
return -1;
}
mipi_desc.pitch = desc->pitch;
/* Following the datasheet, in the GDDRAM, two segment are split in one register */
buf_len = MIN(desc->buf_size, desc->height * desc->width / 2);
if (buf == NULL || buf_len == 0U) {
LOG_ERR("Display buffer is not available");
return -1;
}
mipi_desc.buf_size = buf_len;
if (desc->pitch > desc->width) {
LOG_ERR("Unsupported mode");
return -1;
}
if ((y & 0x7) != 0U) {
LOG_ERR("Unsupported origin");
return -1;
}
mipi_desc.height = desc->height;
mipi_desc.width = desc->width;
LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch,
desc->width, desc->height, buf_len);
err = ssd1327_write_bus_cmd(dev, SSD1327_SET_COLUMN_ADDR, x_position, sizeof(x_position));
if (err) {
return err;
}
err = ssd1327_write_bus_cmd(dev, SSD1327_SET_ROW_ADDR, y_position, sizeof(y_position));
if (err) {
return err;
}
err = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, buf, &mipi_desc,
PIXEL_FORMAT_MONO10);
if (err) {
return err;
}
return mipi_dbi_release(config->mipi_dev, &config->dbi_config);
}
static int ssd1327_set_contrast(const struct device *dev, const uint8_t contrast)
{
return ssd1327_write_bus_cmd(dev, SSD1327_SET_CONTRAST_CTRL, &contrast, 1);
}
static void ssd1327_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct ssd1327_config *config = dev->config;
memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = config->width;
caps->y_resolution = config->height;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
caps->current_pixel_format = PIXEL_FORMAT_MONO10;
caps->screen_info = SCREEN_INFO_MONO_VTILED;
}
static int ssd1327_set_pixel_format(const struct device *dev,
const enum display_pixel_format pf)
{
if (pf == PIXEL_FORMAT_MONO10) {
return 0;
}
LOG_ERR("Unsupported pixel format");
return -ENOTSUP;
}
static int ssd1327_init_device(const struct device *dev)
{
const struct ssd1327_config *config = dev->config;
uint8_t buf;
/* Turn display off */
if (ssd1327_suspend(dev)) {
return -EIO;
}
if (ssd1327_set_display(dev)) {
return -EIO;
}
if (ssd1327_set_contrast(dev, CONFIG_SSD1327_DEFAULT_CONTRAST)) {
return -EIO;
}
if (ssd1327_set_hardware_config(dev)) {
return -EIO;
}
buf = (config->color_inversion ?
SSD1327_SET_REVERSE_DISPLAY : SSD1327_SET_NORMAL_DISPLAY);
if (ssd1327_write_bus_cmd(dev, SSD1327_SET_ENTIRE_DISPLAY_OFF, &buf, 1)) {
return -EIO;
}
if (ssd1327_set_timing_setting(dev)) {
return -EIO;
}
if (ssd1327_resume(dev)) {
return -EIO;
}
return 0;
}
static int ssd1327_init(const struct device *dev)
{
const struct ssd1327_config *config = dev->config;
LOG_DBG("Initializing device");
if (!device_is_ready(config->mipi_dev)) {
LOG_ERR("MIPI Device not ready!");
return -EINVAL;
}
if (mipi_dbi_reset(config->mipi_dev, SSD1327_RESET_DELAY)) {
LOG_ERR("Failed to reset device!");
return -EIO;
}
k_msleep(SSD1327_RESET_DELAY);
if (ssd1327_init_device(dev)) {
LOG_ERR("Failed to initialize device!");
return -EIO;
}
return 0;
}
static struct display_driver_api ssd1327_driver_api = {
.blanking_on = ssd1327_suspend,
.blanking_off = ssd1327_resume,
.write = ssd1327_write,
.set_contrast = ssd1327_set_contrast,
.get_capabilities = ssd1327_get_capabilities,
.set_pixel_format = ssd1327_set_pixel_format,
};
#define SSD1327_DEFINE(node_id) \
static struct ssd1327_data data##node_id; \
static const struct ssd1327_config config##node_id = { \
.mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \
.dbi_config = { .mode = MIPI_DBI_MODE_SPI_4WIRE, \
.config = MIPI_DBI_SPI_CONFIG_DT(node_id, \
SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \
SPI_HOLD_ON_CS | SPI_LOCK_ON, 0), \
}, \
.height = DT_PROP(node_id, height), \
.width = DT_PROP(node_id, width), \
.oscillator_freq = DT_PROP(node_id, oscillator_freq), \
.display_offset = DT_PROP(node_id, display_offset), \
.start_line = DT_PROP(node_id, start_line), \
.multiplex_ratio = DT_PROP(node_id, multiplex_ratio), \
.prechargep = DT_PROP(node_id, prechargep), \
.remap_value = DT_PROP(node_id, remap_value), \
.color_inversion = DT_PROP(node_id, inversion_on), \
}; \
\
DEVICE_DT_DEFINE(node_id, ssd1327_init, NULL, &data##node_id, &config##node_id, \
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1327_driver_api);
DT_FOREACH_STATUS_OKAY(solomon_ssd1327fb, SSD1327_DEFINE)
``` | /content/code_sandbox/drivers/display/ssd1327.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,885 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_
#include <zephyr/device.h>
/* Commands/registers. */
#define ILI9342C_GAMSET 0x26
#define ILI9342C_IFMODE 0xB0
#define ILI9342C_FRMCTR1 0xB1
#define ILI9342C_INVTR 0xB4
#define ILI9342C_DISCTRL 0xB6
#define ILI9342C_ETMOD 0xB7
#define ILI9342C_PWCTRL1 0xC0
#define ILI9342C_PWCTRL2 0xC1
#define ILI9342C_PWCTRL3 0xC2
#define ILI9342C_VMCTRL1 0xC5
#define ILI9342C_SETEXTC 0xC8
#define ILI9342C_PGAMCTRL 0xE0
#define ILI9342C_NGAMCTRL 0xE1
#define ILI9342C_IFCTL 0xF6
/* Commands/registers length. */
#define ILI9342C_GAMSET_LEN 1U
#define ILI9342C_IFMODE_LEN 1U
#define ILI9342C_FRMCTR1_LEN 2U
#define ILI9342C_INVTR_LEN 1U
#define ILI9342C_DISCTRL_LEN 4U
#define ILI9342C_ETMOD_LEN 1U
#define ILI9342C_PWCTRL1_LEN 2U
#define ILI9342C_PWCTRL2_LEN 1U
#define ILI9342C_PWCTRL3_LEN 1U
#define ILI9342C_VMCTRL1_LEN 1U
#define ILI9342C_SETEXTC_LEN 3U
#define ILI9342C_PGAMCTRL_LEN 15U
#define ILI9342C_NGAMCTRL_LEN 15U
#define ILI9342C_IFCTL_LEN 3U
/** X resolution (pixels). */
#define ILI9342c_X_RES 320U
/** Y resolution (pixels). */
#define ILI9342c_Y_RES 240U
/** ILI9342C registers to be initialized. */
struct ili9342c_regs {
uint8_t gamset[ILI9342C_GAMSET_LEN];
uint8_t ifmode[ILI9342C_IFMODE_LEN];
uint8_t frmctr1[ILI9342C_FRMCTR1_LEN];
uint8_t invtr[ILI9342C_INVTR_LEN];
uint8_t disctrl[ILI9342C_DISCTRL_LEN];
uint8_t etmod[ILI9342C_ETMOD_LEN];
uint8_t pwctrl1[ILI9342C_PWCTRL1_LEN];
uint8_t pwctrl2[ILI9342C_PWCTRL2_LEN];
uint8_t pwctrl3[ILI9342C_PWCTRL3_LEN];
uint8_t vmctrl1[ILI9342C_VMCTRL1_LEN];
uint8_t setextc[ILI9342C_SETEXTC_LEN];
uint8_t pgamctrl[ILI9342C_PGAMCTRL_LEN];
uint8_t ngamctrl[ILI9342C_NGAMCTRL_LEN];
uint8_t ifctl[ILI9342C_IFCTL_LEN];
};
/* Initializer macro for ILI9342C registers. */
#define ILI9342c_REGS_INIT(n) \
static const struct ili9342c_regs ili9xxx_regs_##n = { \
.gamset = DT_PROP(DT_INST(n, ilitek_ili9342c), gamset), \
.ifmode = DT_PROP(DT_INST(n, ilitek_ili9342c), ifmode), \
.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9342c), frmctr1), \
.invtr = DT_PROP(DT_INST(n, ilitek_ili9342c), invtr), \
.disctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), disctrl), \
.etmod = DT_PROP(DT_INST(n, ilitek_ili9342c), etmod), \
.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl1), \
.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl2), \
.pwctrl3 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl3), \
.vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), vmctrl1), \
.setextc = {0xFF, 0x93, 0x42}, \
.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), pgamctrl), \
.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), ngamctrl), \
.ifctl = DT_PROP(DT_INST(n, ilitek_ili9342c), ifctl), \
};
/**
* @brief Initialize ILI9342C registers with DT values.
*
* @param dev ILI9342C device instance
* @return 0 on success, errno otherwise.
*/
int ili9342c_regs_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9342C_H_ */
``` | /content/code_sandbox/drivers/display/display_ili9342c.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,231 |
```unknown
# Microbit display driver configuration options
config MICROBIT_DISPLAY
bool "BBC micro:bit 5x5 LED Display support"
depends on BOARD_BBC_MICROBIT || BOARD_BBC_MICROBIT_V2
depends on PRINTK
help
Enable this to be able to display images and text on the 5x5
LED matrix display on the BBC micro:bit.
config MICROBIT_DISPLAY_STR_MAX
int "Maximum length of strings that can be shown on the display"
range 3 $(UINT8_MAX)
default 40
depends on MICROBIT_DISPLAY
help
This value specifies the maximum length of strings that can
be displayed using the mb_display_string() and mb_display_print()
APIs.
``` | /content/code_sandbox/drivers/display/Kconfig.microbit | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```unknown
# Configuration options for dummy display
config DUMMY_DISPLAY
bool "Dummy display driver"
help
Enable dummy display driver compliant with display driver API.
``` | /content/code_sandbox/drivers/display/Kconfig.dummy | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config LS0XX
bool "LS0XX memory display controller driver"
default y
depends on DT_HAS_SHARP_LS0XX_ENABLED
select SPI
help
Enable driver for sharp memory display series LS0XXX7DXXX
``` | /content/code_sandbox/drivers/display/Kconfig.ls0xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
config LED_STRIP_MATRIX
bool "LED strip matrix display driver"
default y
depends on DT_HAS_LED_STRIP_MATRIX_ENABLED
depends on LED_STRIP
help
Enable LED strip matrix display (LED strip arranged in
a grid pattern) driver.
``` | /content/code_sandbox/drivers/display/Kconfig.led_strip_matrix | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_ltdc
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <stm32_ll_rcc.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/cache.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
/* Horizontal synchronization pulse polarity */
#define LTDC_HSPOL_ACTIVE_LOW 0x00000000
#define LTDC_HSPOL_ACTIVE_HIGH 0x80000000
/* Vertical synchronization pulse polarity */
#define LTDC_VSPOL_ACTIVE_LOW 0x00000000
#define LTDC_VSPOL_ACTIVE_HIGH 0x40000000
/* Data enable pulse polarity */
#define LTDC_DEPOL_ACTIVE_LOW 0x00000000
#define LTDC_DEPOL_ACTIVE_HIGH 0x20000000
/* Pixel clock polarity */
#define LTDC_PCPOL_ACTIVE_LOW 0x00000000
#define LTDC_PCPOL_ACTIVE_HIGH 0x10000000
#if CONFIG_STM32_LTDC_ARGB8888
#define STM32_LTDC_INIT_PIXEL_SIZE 4u
#define STM32_LTDC_INIT_PIXEL_FORMAT LTDC_PIXEL_FORMAT_ARGB8888
#define DISPLAY_INIT_PIXEL_FORMAT PIXEL_FORMAT_ARGB_8888
#elif CONFIG_STM32_LTDC_RGB888
#define STM32_LTDC_INIT_PIXEL_SIZE 3u
#define STM32_LTDC_INIT_PIXEL_FORMAT LTDC_PIXEL_FORMAT_RGB888
#define DISPLAY_INIT_PIXEL_FORMAT PIXEL_FORMAT_RGB_888
#elif CONFIG_STM32_LTDC_RGB565
#define STM32_LTDC_INIT_PIXEL_SIZE 2u
#define STM32_LTDC_INIT_PIXEL_FORMAT LTDC_PIXEL_FORMAT_RGB565
#define DISPLAY_INIT_PIXEL_FORMAT PIXEL_FORMAT_RGB_565
#else
#error "Invalid LTDC pixel format chosen"
#endif
struct display_stm32_ltdc_data {
LTDC_HandleTypeDef hltdc;
enum display_pixel_format current_pixel_format;
uint8_t current_pixel_size;
uint8_t *frame_buffer;
uint32_t frame_buffer_len;
const uint8_t *pend_buf;
const uint8_t *front_buf;
struct k_sem sem;
};
struct display_stm32_ltdc_config {
uint32_t width;
uint32_t height;
struct gpio_dt_spec disp_on_gpio;
struct gpio_dt_spec bl_ctrl_gpio;
struct stm32_pclken pclken;
const struct reset_dt_spec reset;
const struct pinctrl_dev_config *pctrl;
void (*irq_config_func)(const struct device *dev);
const struct device *display_controller;
};
static void stm32_ltdc_global_isr(const struct device *dev)
{
struct display_stm32_ltdc_data *data = dev->data;
if (__HAL_LTDC_GET_FLAG(&data->hltdc, LTDC_FLAG_LI) &&
__HAL_LTDC_GET_IT_SOURCE(&data->hltdc, LTDC_IT_LI)) {
if (data->front_buf != data->pend_buf) {
data->front_buf = data->pend_buf;
LTDC_LAYER(&data->hltdc, LTDC_LAYER_1)->CFBAR = (uint32_t)data->front_buf;
__HAL_LTDC_RELOAD_CONFIG(&data->hltdc);
k_sem_give(&data->sem);
}
__HAL_LTDC_CLEAR_FLAG(&data->hltdc, LTDC_FLAG_LI);
}
}
static int stm32_ltdc_set_pixel_format(const struct device *dev,
const enum display_pixel_format format)
{
int err;
struct display_stm32_ltdc_data *data = dev->data;
switch (format) {
case PIXEL_FORMAT_RGB_565:
err = HAL_LTDC_SetPixelFormat(&data->hltdc, LTDC_PIXEL_FORMAT_RGB565, 0);
data->current_pixel_format = PIXEL_FORMAT_RGB_565;
data->current_pixel_size = 2u;
break;
case PIXEL_FORMAT_RGB_888:
err = HAL_LTDC_SetPixelFormat(&data->hltdc, LTDC_PIXEL_FORMAT_RGB888, 0);
data->current_pixel_format = PIXEL_FORMAT_RGB_888;
data->current_pixel_size = 3u;
break;
case PIXEL_FORMAT_ARGB_8888:
err = HAL_LTDC_SetPixelFormat(&data->hltdc, LTDC_PIXEL_FORMAT_ARGB8888, 0);
data->current_pixel_format = PIXEL_FORMAT_ARGB_8888;
data->current_pixel_size = 4u;
default:
err = -ENOTSUP;
break;
}
return err;
}
static int stm32_ltdc_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
ARG_UNUSED(dev);
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
return -ENOTSUP;
}
static void stm32_ltdc_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
struct display_stm32_ltdc_data *data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = data->hltdc.LayerCfg[0].WindowX1 -
data->hltdc.LayerCfg[0].WindowX0;
capabilities->y_resolution = data->hltdc.LayerCfg[0].WindowY1 -
data->hltdc.LayerCfg[0].WindowY0;
capabilities->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888 |
PIXEL_FORMAT_RGB_888 |
PIXEL_FORMAT_RGB_565;
capabilities->screen_info = 0;
capabilities->current_pixel_format = data->current_pixel_format;
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int stm32_ltdc_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct display_stm32_ltdc_config *config = dev->config;
struct display_stm32_ltdc_data *data = dev->data;
uint8_t *dst = NULL;
const uint8_t *pend_buf = NULL;
const uint8_t *src = buf;
uint16_t row;
if ((x == 0) && (y == 0) &&
(desc->width == config->width) &&
(desc->height == config->height) &&
(desc->pitch == desc->width)) {
/* Use buf as ltdc frame buffer directly if it length same as ltdc frame buffer. */
pend_buf = buf;
} else {
if (CONFIG_STM32_LTDC_FB_NUM == 0) {
LOG_ERR("Partial write requires internal frame buffer");
return -ENOTSUP;
}
dst = data->frame_buffer;
if (CONFIG_STM32_LTDC_FB_NUM == 2) {
if (data->front_buf == data->frame_buffer) {
dst = data->frame_buffer + data->frame_buffer_len;
}
memcpy(dst, data->front_buf, data->frame_buffer_len);
}
pend_buf = dst;
/* dst = pointer to upper left pixel of the rectangle
* to be updated in frame buffer.
*/
dst += (x * data->current_pixel_size);
dst += (y * config->width * data->current_pixel_size);
for (row = 0; row < desc->height; row++) {
(void) memcpy(dst, src, desc->width * data->current_pixel_size);
sys_cache_data_flush_range(dst, desc->width * data->current_pixel_size);
dst += (config->width * data->current_pixel_size);
src += (desc->pitch * data->current_pixel_size);
}
}
if (data->front_buf == pend_buf) {
return 0;
}
k_sem_reset(&data->sem);
data->pend_buf = pend_buf;
k_sem_take(&data->sem, K_FOREVER);
return 0;
}
static int stm32_ltdc_read(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
const struct display_stm32_ltdc_config *config = dev->config;
struct display_stm32_ltdc_data *data = dev->data;
uint8_t *dst = buf;
const uint8_t *src = data->front_buf;
uint16_t row;
/* src = pointer to upper left pixel of the rectangle to be read from frame buffer */
src += (x * data->current_pixel_size);
src += (y * config->width * data->current_pixel_size);
for (row = 0; row < desc->height; row++) {
(void) memcpy(dst, src, desc->width * data->current_pixel_size);
sys_cache_data_flush_range(dst, desc->width * data->current_pixel_size);
src += (config->width * data->current_pixel_size);
dst += (desc->pitch * data->current_pixel_size);
}
return 0;
}
static int stm32_ltdc_display_blanking_off(const struct device *dev)
{
const struct display_stm32_ltdc_config *config = dev->config;
const struct device *display_dev = config->display_controller;
if (display_dev == NULL) {
return 0;
}
if (!device_is_ready(display_dev)) {
LOG_ERR("Display device %s not ready", display_dev->name);
return -ENODEV;
}
return display_blanking_off(display_dev);
}
static int stm32_ltdc_display_blanking_on(const struct device *dev)
{
const struct display_stm32_ltdc_config *config = dev->config;
const struct device *display_dev = config->display_controller;
if (display_dev == NULL) {
return 0;
}
if (!device_is_ready(config->display_controller)) {
LOG_ERR("Display device %s not ready", display_dev->name);
return -ENODEV;
}
return display_blanking_on(display_dev);
}
static int stm32_ltdc_init(const struct device *dev)
{
int err;
const struct display_stm32_ltdc_config *config = dev->config;
struct display_stm32_ltdc_data *data = dev->data;
/* Configure and set display on/off GPIO */
if (config->disp_on_gpio.port) {
err = gpio_pin_configure_dt(&config->disp_on_gpio, GPIO_OUTPUT_ACTIVE);
if (err < 0) {
LOG_ERR("Configuration of display on/off control GPIO failed");
return err;
}
}
/* Configure and set display backlight control GPIO */
if (config->bl_ctrl_gpio.port) {
err = gpio_pin_configure_dt(&config->bl_ctrl_gpio, GPIO_OUTPUT_ACTIVE);
if (err < 0) {
LOG_ERR("Configuration of display backlight control GPIO failed");
return err;
}
}
/* Configure DT provided pins */
if (!IS_ENABLED(CONFIG_MIPI_DSI)) {
err = pinctrl_apply_state(config->pctrl, PINCTRL_STATE_DEFAULT);
if (err < 0) {
LOG_ERR("LTDC pinctrl setup failed");
return err;
}
}
if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
/* Turn on LTDC peripheral clock */
err = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &config->pclken);
if (err < 0) {
LOG_ERR("Could not enable LTDC peripheral clock");
return err;
}
#if defined(CONFIG_SOC_SERIES_STM32F4X)
LL_RCC_PLLSAI_Disable();
LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
LL_RCC_PLLSAIM_DIV_8,
192,
LL_RCC_PLLSAIR_DIV_4,
LL_RCC_PLLSAIDIVR_DIV_8);
LL_RCC_PLLSAI_Enable();
while (LL_RCC_PLLSAI_IsReady() != 1) {
}
#endif
#if defined(CONFIG_SOC_SERIES_STM32F7X)
LL_RCC_PLLSAI_Disable();
LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
LL_RCC_PLLM_DIV_25,
384,
LL_RCC_PLLSAIR_DIV_5,
LL_RCC_PLLSAIDIVR_DIV_8);
LL_RCC_PLLSAI_Enable();
while (LL_RCC_PLLSAI_IsReady() != 1) {
}
#endif
/* reset LTDC peripheral */
(void)reset_line_toggle_dt(&config->reset);
data->current_pixel_format = DISPLAY_INIT_PIXEL_FORMAT;
data->current_pixel_size = STM32_LTDC_INIT_PIXEL_SIZE;
k_sem_init(&data->sem, 0, 1);
config->irq_config_func(dev);
#ifdef CONFIG_STM32_LTDC_DISABLE_FMC_BANK1
/* Clear MBKEN and MTYP[1:0] bits. */
#ifdef CONFIG_SOC_SERIES_STM32F7X
FMC_Bank1->BTCR[0] &= ~(0x0000000D);
#else /* CONFIG_SOC_SERIES_STM32H7X */
FMC_Bank1_R->BTCR[0] &= ~(0x0000000D);
#endif
#endif /* CONFIG_STM32_LTDC_DISABLE_FMC_BANK1 */
/* Initialise the LTDC peripheral */
err = HAL_LTDC_Init(&data->hltdc);
if (err != HAL_OK) {
return err;
}
/* Configure layer 1 (only one layer is used) */
/* LTDC starts fetching pixels and sending them to display after this call */
err = HAL_LTDC_ConfigLayer(&data->hltdc, &data->hltdc.LayerCfg[0], LTDC_LAYER_1);
if (err != HAL_OK) {
return err;
}
/* Disable layer 2, since it not used */
__HAL_LTDC_LAYER_DISABLE(&data->hltdc, LTDC_LAYER_2);
/* Set the line interrupt position */
LTDC->LIPCR = 0U;
__HAL_LTDC_CLEAR_FLAG(&data->hltdc, LTDC_FLAG_LI);
__HAL_LTDC_ENABLE_IT(&data->hltdc, LTDC_IT_LI);
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int stm32_ltdc_suspend(const struct device *dev)
{
const struct display_stm32_ltdc_config *config = dev->config;
int err;
/* Turn off disp_en (if its GPIO is defined in device tree) */
if (config->disp_on_gpio.port) {
err = gpio_pin_set_dt(&config->disp_on_gpio, 0);
if (err < 0) {
return err;
}
}
/* Turn off backlight (if its GPIO is defined in device tree) */
if (config->bl_ctrl_gpio.port) {
err = gpio_pin_set_dt(&config->bl_ctrl_gpio, 0);
if (err < 0) {
return err;
}
}
/* Reset LTDC peripheral registers */
(void)reset_line_toggle_dt(&config->reset);
/* Turn off LTDC peripheral clock */
err = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &config->pclken);
return err;
}
static int stm32_ltdc_pm_action(const struct device *dev,
enum pm_device_action action)
{
int err;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
err = stm32_ltdc_init(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
err = stm32_ltdc_suspend(dev);
break;
default:
return -ENOTSUP;
}
if (err < 0) {
LOG_ERR("%s: failed to set power mode", dev->name);
}
return err;
}
#endif /* CONFIG_PM_DEVICE */
static const struct display_driver_api stm32_ltdc_display_api = {
.write = stm32_ltdc_write,
.read = stm32_ltdc_read,
.get_capabilities = stm32_ltdc_get_capabilities,
.set_pixel_format = stm32_ltdc_set_pixel_format,
.set_orientation = stm32_ltdc_set_orientation,
.blanking_off = stm32_ltdc_display_blanking_off,
.blanking_on = stm32_ltdc_display_blanking_on,
};
#if DT_INST_NODE_HAS_PROP(0, ext_sdram)
#if DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram1))
#define FRAME_BUFFER_SECTION __stm32_sdram1_section
#elif DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram2))
#define FRAME_BUFFER_SECTION __stm32_sdram2_section
#else
#error "LTDC ext-sdram property in device tree does not reference SDRAM1 or SDRAM2 node"
#define FRAME_BUFFER_SECTION
#endif /* DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram1)) */
#else
#define FRAME_BUFFER_SECTION
#endif /* DT_INST_NODE_HAS_PROP(0, ext_sdram) */
#ifdef CONFIG_MIPI_DSI
#define STM32_LTDC_DEVICE_PINCTRL_INIT(n)
#define STM32_LTDC_DEVICE_PINCTRL_GET(n) (NULL)
#else
#define STM32_LTDC_DEVICE_PINCTRL_INIT(n) PINCTRL_DT_INST_DEFINE(n)
#define STM32_LTDC_DEVICE_PINCTRL_GET(n) PINCTRL_DT_INST_DEV_CONFIG_GET(n)
#endif
#define STM32_LTDC_FRAME_BUFFER_LEN(inst) \
(STM32_LTDC_INIT_PIXEL_SIZE * DT_INST_PROP(inst, height) * DT_INST_PROP(inst, width)) \
#define STM32_LTDC_DEVICE(inst) \
STM32_LTDC_DEVICE_PINCTRL_INIT(inst); \
PM_DEVICE_DT_INST_DEFINE(inst, stm32_ltdc_pm_action); \
static void stm32_ltdc_irq_config_func_##inst(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), \
stm32_ltdc_global_isr, \
DEVICE_DT_INST_GET(inst), \
0); \
irq_enable(DT_INST_IRQN(inst)); \
} \
/* frame buffer aligned to cache line width for optimal cache flushing */ \
FRAME_BUFFER_SECTION static uint8_t __aligned(32) \
frame_buffer_##inst[CONFIG_STM32_LTDC_FB_NUM * \
STM32_LTDC_FRAME_BUFFER_LEN(inst)]; \
static struct display_stm32_ltdc_data stm32_ltdc_data_##inst = { \
.frame_buffer = frame_buffer_##inst, \
.frame_buffer_len = STM32_LTDC_FRAME_BUFFER_LEN(inst), \
.front_buf = frame_buffer_##inst, \
.pend_buf = frame_buffer_##inst, \
.hltdc = { \
.Instance = (LTDC_TypeDef *) DT_INST_REG_ADDR(inst), \
.Init = { \
.HSPolarity = (DT_PROP(DT_INST_CHILD(inst, display_timings), \
hsync_active) ? \
LTDC_HSPOL_ACTIVE_HIGH : LTDC_HSPOL_ACTIVE_LOW),\
.VSPolarity = (DT_PROP(DT_INST_CHILD(inst, \
display_timings), vsync_active) ? \
LTDC_VSPOL_ACTIVE_HIGH : LTDC_VSPOL_ACTIVE_LOW),\
.DEPolarity = (DT_PROP(DT_INST_CHILD(inst, \
display_timings), de_active) ? \
LTDC_DEPOL_ACTIVE_HIGH : LTDC_DEPOL_ACTIVE_LOW),\
.PCPolarity = (DT_PROP(DT_INST_CHILD(inst, \
display_timings), pixelclk_active) ? \
LTDC_PCPOL_ACTIVE_HIGH : LTDC_PCPOL_ACTIVE_LOW),\
.HorizontalSync = DT_PROP(DT_INST_CHILD(inst, \
display_timings), hsync_len) - 1, \
.VerticalSync = DT_PROP(DT_INST_CHILD(inst, \
display_timings), vsync_len) - 1, \
.AccumulatedHBP = DT_PROP(DT_INST_CHILD(inst, \
display_timings), hback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), hsync_len) - 1, \
.AccumulatedVBP = DT_PROP(DT_INST_CHILD(inst, \
display_timings), vback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), vsync_len) - 1, \
.AccumulatedActiveW = DT_PROP(DT_INST_CHILD(inst, \
display_timings), hback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), hsync_len) + \
DT_INST_PROP(inst, width) - 1, \
.AccumulatedActiveH = DT_PROP(DT_INST_CHILD(inst, \
display_timings), vback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), vsync_len) + \
DT_INST_PROP(inst, height) - 1, \
.TotalWidth = DT_PROP(DT_INST_CHILD(inst, \
display_timings), hback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), hsync_len) + \
DT_INST_PROP(inst, width) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), hfront_porch) - 1, \
.TotalHeigh = DT_PROP(DT_INST_CHILD(inst, \
display_timings), vback_porch) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), vsync_len) + \
DT_INST_PROP(inst, height) + \
DT_PROP(DT_INST_CHILD(inst, \
display_timings), vfront_porch) - 1, \
.Backcolor.Red = \
DT_INST_PROP_OR(inst, def_back_color_red, 0xFF), \
.Backcolor.Green = \
DT_INST_PROP_OR(inst, def_back_color_green, 0xFF), \
.Backcolor.Blue = \
DT_INST_PROP_OR(inst, def_back_color_blue, 0xFF), \
}, \
.LayerCfg[0] = { \
.WindowX0 = DT_INST_PROP_OR(inst, window0_x0, 0), \
.WindowX1 = DT_INST_PROP_OR(inst, window0_x1, \
DT_INST_PROP(inst, width)), \
.WindowY0 = DT_INST_PROP_OR(inst, window0_y0, 0), \
.WindowY1 = DT_INST_PROP_OR(inst, window0_y1, \
DT_INST_PROP(inst, height)), \
.PixelFormat = STM32_LTDC_INIT_PIXEL_FORMAT, \
.Alpha = 255, \
.Alpha0 = 0, \
.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA, \
.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA, \
.FBStartAdress = (uint32_t) frame_buffer_##inst, \
.ImageWidth = DT_INST_PROP(inst, width), \
.ImageHeight = DT_INST_PROP(inst, height), \
.Backcolor.Red = \
DT_INST_PROP_OR(inst, def_back_color_red, 0xFF), \
.Backcolor.Green = \
DT_INST_PROP_OR(inst, def_back_color_green, 0xFF), \
.Backcolor.Blue = \
DT_INST_PROP_OR(inst, def_back_color_blue, 0xFF), \
}, \
}, \
}; \
static const struct display_stm32_ltdc_config stm32_ltdc_config_##inst = { \
.width = DT_INST_PROP(inst, width), \
.height = DT_INST_PROP(inst, height), \
.disp_on_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, disp_on_gpios), \
(GPIO_DT_SPEC_INST_GET(inst, disp_on_gpios)), ({ 0 })), \
.bl_ctrl_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, bl_ctrl_gpios), \
(GPIO_DT_SPEC_INST_GET(inst, bl_ctrl_gpios)), ({ 0 })), \
.reset = RESET_DT_SPEC_INST_GET(0), \
.pclken = { \
.enr = DT_INST_CLOCKS_CELL(inst, bits), \
.bus = DT_INST_CLOCKS_CELL(inst, bus) \
}, \
.pctrl = STM32_LTDC_DEVICE_PINCTRL_GET(inst), \
.irq_config_func = stm32_ltdc_irq_config_func_##inst, \
.display_controller = DEVICE_DT_GET_OR_NULL( \
DT_INST_PHANDLE(inst, display_controller)), \
}; \
DEVICE_DT_INST_DEFINE(inst, \
&stm32_ltdc_init, \
PM_DEVICE_DT_INST_GET(inst), \
&stm32_ltdc_data_##inst, \
&stm32_ltdc_config_##inst, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&stm32_ltdc_display_api);
DT_INST_FOREACH_STATUS_OKAY(STM32_LTDC_DEVICE)
``` | /content/code_sandbox/drivers/display/display_stm32_ltdc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,800 |
```c
/*
*
*/
#include "display_ili9488.h"
#include "display_ili9xxx.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_ili9488, CONFIG_DISPLAY_LOG_LEVEL);
int ili9488_regs_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
const struct ili9488_regs *regs = config->regs;
int r;
LOG_HEXDUMP_DBG(regs->frmctr1, ILI9488_FRMCTR1_LEN, "FRMCTR1");
r = ili9xxx_transmit(dev, ILI9488_FRMCTR1, regs->frmctr1,
ILI9488_FRMCTR1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->disctrl, ILI9488_DISCTRL_LEN, "DISCTRL");
r = ili9xxx_transmit(dev, ILI9488_DISCTRL, regs->disctrl,
ILI9488_DISCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9488_PWCTRL1_LEN, "PWCTRL1");
r = ili9xxx_transmit(dev, ILI9488_PWCTRL1, regs->pwctrl1,
ILI9488_PWCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9488_PWCTRL2_LEN, "PWCTRL2");
r = ili9xxx_transmit(dev, ILI9488_PWCTRL2, regs->pwctrl2,
ILI9488_PWCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl, ILI9488_VMCTRL_LEN, "VMCTRL");
r = ili9xxx_transmit(dev, ILI9488_VMCTRL, regs->vmctrl,
ILI9488_VMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9488_PGAMCTRL_LEN, "PGAMCTRL");
r = ili9xxx_transmit(dev, ILI9488_PGAMCTRL, regs->pgamctrl,
ILI9488_PGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9488_NGAMCTRL_LEN, "NGAMCTRL");
r = ili9xxx_transmit(dev, ILI9488_NGAMCTRL, regs->ngamctrl,
ILI9488_NGAMCTRL_LEN);
if (r < 0) {
return r;
}
return 0;
}
``` | /content/code_sandbox/drivers/display/display_ili9488.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 598 |
```unknown
config OTM8009A
bool "OTM8009A display driver"
default y
depends on DT_HAS_ORISETECH_OTM8009A_ENABLED
select MIPI_DSI
help
Enable driver for OTM8009A display driver.
if OTM8009A
config DISPLAY_OTM8009A_INIT_PRIORITY
int "Initialization priority"
default DISPLAY_INIT_PRIORITY
help
OTM8009A display driver initialization priority.
endif
``` | /content/code_sandbox/drivers/display/Kconfig.otm8009a | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
# ST7789V display driver configuration options
menuconfig ST7789V
bool "ST7789V display driver"
default y
depends on DT_HAS_SITRONIX_ST7789V_ENABLED
select MIPI_DBI
help
Enable driver for ST7789V display driver.
choice ST7789V_PIXEL_FORMAT
prompt "Color pixel format"
default ST7789V_RGB565
depends on ST7789V
help
Specify the color pixel format for the ST7789V display controller.
config ST7789V_RGB888
bool "RGB888"
config ST7789V_RGB565
bool "RGB565"
config ST7789V_BGR565
bool "BGR565"
endchoice
``` | /content/code_sandbox/drivers/display/Kconfig.st7789v | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```objective-c
/*
*
*/
#ifndef __SSD1327_REGS_H__
#define __SSD1327_REGS_H__
/*
* Fundamental Command Table
*/
#define SSD1327_SET_COLUMN_ADDR 0x15
#define SSD1327_SET_ROW_ADDR 0x75
#define SSD1327_SET_CONTRAST_CTRL 0x81
#define SSD1327_SET_SEGMENT_MAP_REMAPED 0xa0
#define SSD1327_SET_DISPLAY_START_LINE 0xa1
#define SSD1327_SET_DISPLAY_OFFSET 0xa2
#define SSD1327_SET_NORMAL_DISPLAY 0xa4
#define SSD1327_SET_ENTIRE_DISPLAY_ON 0xa5
#define SSD1327_SET_ENTIRE_DISPLAY_OFF 0xa6
#define SSD1327_SET_REVERSE_DISPLAY 0xa7
#define SSD1327_SET_MULTIPLEX_RATIO 0xa8
#define SSD1327_DISPLAY_OFF 0xae
#define SSD1327_DISPLAY_ON 0xaf
#define SSD1327_SET_FUNCTION_A 0xab
#define SSD1327_SET_PHASE_LENGTH 0xb1
#define SSD1327_SET_OSC_FREQ 0xb3
#define SSD1327_SET_PRECHARGE_PERIOD 0xb6
#define SSD1327_FUNCTION_SELECTION_B 0xd5
#define SSD1327_LINEAR_LUT 0xb9
#define SSD1327_SET_PRECHARGE_VOLTAGE 0xbc
#define SSD1327_SET_VCOMH 0xbe
#define SSD1327_SET_COMMAND_LOCK 0xfd
/* Time constant in ms */
#define SSD1327_RESET_DELAY 10
#endif
``` | /content/code_sandbox/drivers/display/ssd1327_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 345 |
```c
/*
*
*
* Based on the NT35510 driver provided by STMicroelectronics at
* path_to_url
*/
#define DT_DRV_COMPAT frida_nt35510
#include <errno.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
#include "display_nt35510.h"
LOG_MODULE_REGISTER(nt35510, CONFIG_DISPLAY_LOG_LEVEL);
/**
* @brief Possible values of COLMOD parameter corresponding to used pixel formats
*/
#define NT35510_COLMOD_RGB565 0x55
#define NT35510_COLMOD_RGB888 0x77
/**
* @brief NT35510_480X800 Timing parameters for Portrait orientation mode
*/
#define NT35510_480X800_HSYNC ((uint16_t)2) /* Horizontal synchronization */
#define NT35510_480X800_HBP ((uint16_t)34) /* Horizontal back porch */
#define NT35510_480X800_HFP ((uint16_t)34) /* Horizontal front porch */
#define NT35510_480X800_VSYNC ((uint16_t)120) /* Vertical synchronization */
#define NT35510_480X800_VBP ((uint16_t)150) /* Vertical back porch */
#define NT35510_480X800_VFP ((uint16_t)150) /* Vertical front porch */
/**
* @brief NT35510_800X480 Timing parameters for Landscape orientation mode
* Same values as for Portrait mode in fact.
*/
#define NT35510_800X480_HSYNC NT35510_480X800_VSYNC /* Horizontal synchronization */
#define NT35510_800X480_HBP NT35510_480X800_VBP /* Horizontal back porch */
#define NT35510_800X480_HFP NT35510_480X800_VFP /* Horizontal front porch */
#define NT35510_800X480_VSYNC NT35510_480X800_HSYNC /* Vertical synchronization */
#define NT35510_800X480_VBP NT35510_480X800_HBP /* Vertical back porch */
#define NT35510_800X480_VFP NT35510_480X800_HFP /* Vertical front porch */
struct nt35510_config {
const struct device *mipi_dsi;
const struct gpio_dt_spec reset;
const struct gpio_dt_spec backlight;
uint8_t data_lanes;
uint16_t width;
uint16_t height;
uint8_t channel;
uint16_t rotation;
};
struct nt35510_data {
enum display_pixel_format pixel_format;
enum display_orientation orientation;
uint16_t xres;
uint16_t yres;
};
struct nt35510_init_cmd {
uint8_t reg;
uint8_t cmd_len;
uint8_t cmd[5];
} __packed;
static const struct nt35510_init_cmd init_cmds[] = {
/* LV2: Page 1 enable */
{.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x01}},
/* AVDD: 5.2V */
{.reg = 0xb0, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}},
/* AVDD: Ratio */
{.reg = 0xb6, .cmd_len = 3, .cmd = {0x46, 0x46, 0x46}},
/* AVEE: -5.2V */
{.reg = 0xb1, .cmd_len = 3, .cmd = {0x03, 0x03, 0x03}},
/* AVEE: Ratio */
{.reg = 0xb7, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}},
/* VCL: -2.5V */
{.reg = 0xb2, .cmd_len = 3, .cmd = {0x00, 0x00, 0x02}},
/* VCL: Ratio */
{.reg = 0xb8, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}},
/* VGH: 15V (Free Pump) */
{.reg = 0xbf, .cmd_len = 1, .cmd = {0x01}},
/* Frida LCD MFR specific */
{.reg = 0xb3, .cmd_len = 3, .cmd = {0x09, 0x09, 0x09}},
/* VGH: Ratio */
{.reg = 0xb9, .cmd_len = 3, .cmd = {0x36, 0x36, 0x36}},
/* VGL_REG: -10V */
{.reg = 0xb5, .cmd_len = 3, .cmd = {0x08, 0x08, 0x08}},
/* VGLX: Ratio */
{.reg = 0xba, .cmd_len = 3, .cmd = {0x26, 0x26, 0x26}},
/* VGMP/VGSP: 4.5V/0V */
{.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}},
/* VGMN/VGSN:-4.5V/0V */
{.reg = 0xbd, .cmd_len = 3, .cmd = {0x00, 0x80, 0x00}},
/* VCOM: -1.325V */
{.reg = 0xbe, .cmd_len = 2, .cmd = {0x00, 0x50}},
/* LV2: Page 0 enable */
{.reg = 0xf0, .cmd_len = 5, .cmd = {0x55, 0xaa, 0x52, 0x08, 0x00}},
/* Display optional control */
{.reg = 0xb1, .cmd_len = 2, .cmd = {0xfc, 0x00}},
/* Set source output data hold time */
{.reg = 0xb6, .cmd_len = 1, .cmd = {0x03}},
/* Display resolution control */
{.reg = 0xb5, .cmd_len = 1, .cmd = {0x51}},
/* Gate EQ control */
{.reg = 0xb7, .cmd_len = 2, .cmd = {0x00, 0x00}},
/* Src EQ control(Mode2) */
{.reg = 0xb8, .cmd_len = 4, .cmd = {0x01, 0x02, 0x02, 0x02}},
/* Frida LCD MFR specific */
{.reg = 0xbc, .cmd_len = 3, .cmd = {0x00, 0x00, 0x00}},
/* Frida LCD MFR specific */
{.reg = 0xcc, .cmd_len = 3, .cmd = {0x03, 0x00, 0x00}},
/* Frida LCD MFR specific */
{.reg = 0xba, .cmd_len = 1, .cmd = {0x01}}};
static const struct nt35510_init_cmd portrait_cmds[] = {
{.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x00}},
{.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}},
{.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}}};
static const struct nt35510_init_cmd landscape_cmds[] = {
{.reg = NT35510_CMD_MADCTL, .cmd_len = 1, .cmd = {0x60}},
{.reg = NT35510_CMD_CASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x03, 0x1f}},
{.reg = NT35510_CMD_RASET, .cmd_len = 4, .cmd = {0x00, 0x00, 0x01, 0xdf}}};
static const struct nt35510_init_cmd turn_on_cmds[] = {
/* Content Adaptive Backlight Control section start */
{.reg = NT35510_CMD_WRDISBV, .cmd_len = 1, .cmd = {0x7f}},
/* Brightness Control Block, Display Dimming & BackLight on */
{.reg = NT35510_CMD_WRCTRLD, .cmd_len = 1, .cmd = {0x2c}},
/* Image Content based Adaptive Brightness [Still Picture] */
{.reg = NT35510_CMD_WRCABC, .cmd_len = 1, .cmd = {0x02}},
/* Brightness, use maximum as default */
{.reg = NT35510_CMD_WRCABCMB, .cmd_len = 1, .cmd = {0xff}},
/* Turn on display */
{.reg = MIPI_DCS_SET_DISPLAY_ON, .cmd_len = 0, .cmd = {}},
/* Send Command GRAM memory write (no parameters)
* this initiates frame write via other DSI commands sent by
* DSI host from LTDC incoming pixels in video mode
*/
{.reg = NT35510_CMD_RAMWR, .cmd_len = 0, .cmd = {}},
};
/* Write data buffer to LCD register */
static int nt35510_write_reg(const struct device *dev, uint8_t reg, const uint8_t *buf, size_t len)
{
int ret;
const struct nt35510_config *cfg = dev->config;
ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len);
if (ret < 0) {
LOG_ERR("Failed writing reg: 0x%x result: (%d)", reg, ret);
return ret;
}
return 0;
}
/* Write an 8-bit value to a register */
static int nt35510_write_reg_val(const struct device *dev, uint8_t reg, uint8_t value)
{
return nt35510_write_reg(dev, reg, &value, 1);
}
/* Write a list of commands to registers */
static int nt35510_write_sequence(const struct device *dev, const struct nt35510_init_cmd *cmd,
uint8_t nr_cmds)
{
int ret = 0;
/* Loop trough all commands as long as writes are successful*/
for (int i = 0; i < nr_cmds && ret == 0; i++) {
ret = nt35510_write_reg(dev, cmd->reg, cmd->cmd, cmd->cmd_len);
cmd++;
}
return ret;
}
/* Initialization, configuration turn on sequence */
static int nt35510_config(const struct device *dev)
{
struct nt35510_data *data = dev->data;
int ret;
ret = nt35510_write_sequence(dev, init_cmds, ARRAY_SIZE(init_cmds));
if (ret < 0) {
return ret;
}
/* Add a delay, otherwise MADCTL not taken */
k_msleep(200);
/* Configure orientation */
if (data->orientation == DISPLAY_ORIENTATION_NORMAL) {
ret = nt35510_write_sequence(dev, portrait_cmds, ARRAY_SIZE(portrait_cmds));
} else {
ret = nt35510_write_sequence(dev, landscape_cmds, ARRAY_SIZE(landscape_cmds));
}
if (ret < 0) {
return ret;
}
/* Exit sleep mode */
ret = nt35510_write_reg(dev, NT35510_CMD_SLPOUT, NULL, 0);
if (ret < 0) {
return ret;
}
/* Wait for sleep out exit */
k_msleep(20);
/* Set color mode */
ret = nt35510_write_reg_val(dev, NT35510_CMD_COLMOD,
data->pixel_format == PIXEL_FORMAT_RGB_565
? NT35510_COLMOD_RGB565
: NT35510_COLMOD_RGB888);
if (ret < 0) {
return ret;
}
/* Adjust brightness and turn on display */
ret = nt35510_write_sequence(dev, turn_on_cmds, ARRAY_SIZE(turn_on_cmds));
return ret;
}
static int nt35510_blanking_on(const struct device *dev)
{
const struct nt35510_config *cfg = dev->config;
int ret;
if (cfg->backlight.port != NULL) {
ret = gpio_pin_set_dt(&cfg->backlight, 0);
if (ret) {
LOG_ERR("Disable backlight failed! (%d)", ret);
return ret;
}
}
return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
}
static int nt35510_blanking_off(const struct device *dev)
{
const struct nt35510_config *cfg = dev->config;
int ret;
if (cfg->backlight.port != NULL) {
ret = gpio_pin_set_dt(&cfg->backlight, 1);
if (ret) {
LOG_ERR("Enable backlight failed! (%d)", ret);
return ret;
}
}
return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
}
static int nt35510_set_brightness(const struct device *dev, const uint8_t brightness)
{
return nt35510_write_reg(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 1);
}
static void nt35510_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct nt35510_config *cfg = dev->config;
struct nt35510_data *data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = cfg->width;
capabilities->y_resolution = cfg->height;
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565 | PIXEL_FORMAT_RGB_888;
capabilities->current_pixel_format = data->pixel_format;
capabilities->current_orientation = data->orientation;
}
static int nt35510_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct nt35510_data *data = dev->data;
if (pixel_format == PIXEL_FORMAT_RGB_565 || pixel_format == PIXEL_FORMAT_RGB_888) {
data->pixel_format = pixel_format;
return 0;
}
LOG_ERR("Pixel format not supported");
return -ENOTSUP;
}
static int nt35510_check_id(const struct device *dev)
{
const struct nt35510_config *cfg = dev->config;
uint8_t id = 0;
int ret;
ret = mipi_dsi_dcs_read(cfg->mipi_dsi, cfg->channel, NT35510_CMD_RDID2, &id, 1);
if (ret != sizeof(id)) {
LOG_ERR("Failed reading ID (%d)", ret);
return -EIO;
}
if (id != NT35510_ID) {
LOG_ERR("ID 0x%x, expected: 0x%x)", id, NT35510_ID);
return -EINVAL;
}
return 0;
}
static int nt35510_init(const struct device *dev)
{
const struct nt35510_config *cfg = dev->config;
struct nt35510_data *data = dev->data;
struct mipi_dsi_device mdev;
int ret;
if (cfg->reset.port) {
if (!gpio_is_ready_dt(&cfg->reset)) {
LOG_ERR("Reset GPIO device is not ready!");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_ERR("Reset display failed! (%d)", ret);
return ret;
}
k_msleep(20);
ret = gpio_pin_set_dt(&cfg->reset, 1);
if (ret < 0) {
LOG_ERR("Enable display failed! (%d)", ret);
return ret;
}
k_msleep(200);
}
/* Store x/y resolution & rotation */
if (cfg->rotation == 0) {
data->xres = cfg->width;
data->yres = cfg->height;
data->orientation = DISPLAY_ORIENTATION_NORMAL;
} else if (cfg->rotation == 90) {
data->xres = cfg->height;
data->yres = cfg->width;
data->orientation = DISPLAY_ORIENTATION_ROTATED_90;
} else if (cfg->rotation == 180) {
data->xres = cfg->width;
data->yres = cfg->height;
data->orientation = DISPLAY_ORIENTATION_ROTATED_180;
} else if (cfg->rotation == 270) {
data->xres = cfg->height;
data->yres = cfg->width;
data->orientation = DISPLAY_ORIENTATION_ROTATED_270;
}
/* Attach to MIPI-DSI host */
mdev.data_lanes = cfg->data_lanes;
mdev.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM;
if (data->pixel_format == PIXEL_FORMAT_RGB_565) {
mdev.pixfmt = MIPI_DSI_PIXFMT_RGB565;
} else {
mdev.pixfmt = MIPI_DSI_PIXFMT_RGB888;
}
mdev.timings.hactive = data->xres;
mdev.timings.hbp = NT35510_480X800_HBP;
mdev.timings.hfp = NT35510_480X800_HFP;
mdev.timings.hsync = NT35510_480X800_HSYNC;
mdev.timings.vactive = data->yres;
mdev.timings.vbp = NT35510_480X800_VBP;
mdev.timings.vfp = NT35510_480X800_VFP;
mdev.timings.vsync = NT35510_480X800_VSYNC;
ret = mipi_dsi_attach(cfg->mipi_dsi, cfg->channel, &mdev);
if (ret < 0) {
LOG_ERR("MIPI-DSI attach failed! (%d)", ret);
return ret;
}
ret = nt35510_check_id(dev);
if (ret) {
LOG_ERR("Panel ID check failed! (%d)", ret);
return ret;
}
ret = gpio_pin_configure_dt(&cfg->backlight, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Backlight pin init fail (%d)", ret);
return ret;
}
ret = nt35510_config(dev);
if (ret) {
LOG_ERR("DSI init sequence failed! (%d)", ret);
return ret;
}
ret = nt35510_blanking_off(dev);
if (ret) {
LOG_ERR("Display blanking off failed! (%d)", ret);
return ret;
}
LOG_INF("Init complete(%d)", ret);
return 0;
}
static const struct display_driver_api nt35510_api = {
.blanking_on = nt35510_blanking_on,
.blanking_off = nt35510_blanking_off,
.set_brightness = nt35510_set_brightness,
.get_capabilities = nt35510_get_capabilities,
.set_pixel_format = nt35510_set_pixel_format,
};
#define NT35510_DEFINE(n) \
static const struct nt35510_config nt35510_config_##n = { \
.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(n)), \
.reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
.backlight = GPIO_DT_SPEC_INST_GET_OR(n, bl_gpios, {0}), \
.data_lanes = DT_INST_PROP_BY_IDX(n, data_lanes, 0), \
.width = DT_INST_PROP(n, width), \
.height = DT_INST_PROP(n, height), \
.channel = DT_INST_REG_ADDR(n), \
.rotation = DT_INST_PROP(n, rotation), \
}; \
\
static struct nt35510_data nt35510_data_##n = { \
.pixel_format = DT_INST_PROP(n, pixel_format), \
}; \
DEVICE_DT_INST_DEFINE(n, &nt35510_init, NULL, &nt35510_data_##n, &nt35510_config_##n, \
POST_KERNEL, CONFIG_DISPLAY_NT35510_INIT_PRIORITY, &nt35510_api);
DT_INST_FOREACH_STATUS_OKAY(NT35510_DEFINE)
``` | /content/code_sandbox/drivers/display/display_nt35510.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,590 |
```unknown
# SSD16XX display controller configuration options
config SSD16XX
bool "SSD16XX compatible display controller driver"
default y
depends on \
DT_HAS_SOLOMON_SSD1608_ENABLED || \
DT_HAS_SOLOMON_SSD1673_ENABLED || \
DT_HAS_SOLOMON_SSD1675A_ENABLED || \
DT_HAS_SOLOMON_SSD1680_ENABLED || \
DT_HAS_SOLOMON_SSD1681_ENABLED
select MIPI_DBI
help
Enable driver for SSD16XX compatible controller.
``` | /content/code_sandbox/drivers/display/Kconfig.ssd16xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
#include <zephyr/drivers/display.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <soc.h>
#include <hal/nrf_timer.h>
#ifdef PWM_PRESENT
#include <hal/nrf_pwm.h>
#endif
#include <nrfx_gpiote.h>
#ifdef PPI_PRESENT
#include <nrfx_ppi.h>
#endif
#include <nrf_peripherals.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(nrf_led_matrix, CONFIG_DISPLAY_LOG_LEVEL);
#define MATRIX_NODE DT_INST(0, nordic_nrf_led_matrix)
#define TIMER_NODE DT_PHANDLE(MATRIX_NODE, timer)
#define USE_PWM DT_NODE_HAS_PROP(MATRIX_NODE, pwm)
#define PWM_NODE DT_PHANDLE(MATRIX_NODE, pwm)
#define ROW_COUNT DT_PROP_LEN(MATRIX_NODE, row_gpios)
#define COL_COUNT DT_PROP_LEN(MATRIX_NODE, col_gpios)
#define GROUP_SIZE DT_PROP(MATRIX_NODE, pixel_group_size)
#if (GROUP_SIZE > DT_PROP(TIMER_NODE, cc_num) - 1) || \
(USE_PWM && GROUP_SIZE > PWM0_CH_NUM)
#error "Invalid pixel-group-size configured."
#endif
#define X_PIXELS DT_PROP(MATRIX_NODE, width)
#define Y_PIXELS DT_PROP(MATRIX_NODE, height)
#define PIXEL_COUNT DT_PROP_LEN(MATRIX_NODE, pixel_mapping)
#if (PIXEL_COUNT != (X_PIXELS * Y_PIXELS))
#error "Invalid length of pixel-mapping."
#endif
#define PIXEL_MAPPING(idx) DT_PROP_BY_IDX(MATRIX_NODE, pixel_mapping, idx)
#define GET_DT_ROW_IDX(pixel_idx) \
_GET_ROW_IDX(PIXEL_MAPPING(pixel_idx))
#define GET_ROW_IDX(dev_config, pixel_idx) \
_GET_ROW_IDX(dev_config->pixel_mapping[pixel_idx])
#define _GET_ROW_IDX(byte) (byte >> 4)
#define GET_DT_COL_IDX(pixel_idx) \
_GET_COL_IDX(PIXEL_MAPPING(pixel_idx))
#define GET_COL_IDX(dev_config, pixel_idx) \
_GET_COL_IDX(dev_config->pixel_mapping[pixel_idx])
#define _GET_COL_IDX(byte) (byte & 0xF)
#define CHECK_PIXEL(node_id, pha, idx) \
BUILD_ASSERT(GET_DT_ROW_IDX(idx) < ROW_COUNT, \
"Invalid row index in pixel-mapping["#idx"]."); \
BUILD_ASSERT(GET_DT_COL_IDX(idx) < COL_COUNT, \
"Invalid column index in pixel-mapping["#idx"].");
DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping, CHECK_PIXEL)
#define REFRESH_FREQUENCY DT_PROP(MATRIX_NODE, refresh_frequency)
#define BASE_FREQUENCY 8000000
#define TIMER_CLK_CONFIG NRF_TIMER_FREQ_8MHz
#define PWM_CLK_CONFIG NRF_PWM_CLK_8MHz
#define BRIGHTNESS_MAX 255
/* Always round up, as even a partially filled group uses the full time slot. */
#define PIXEL_SLOTS (ROW_COUNT * NRFX_CEIL_DIV(COL_COUNT, GROUP_SIZE))
#define QUANTUM (BASE_FREQUENCY \
/ (REFRESH_FREQUENCY * PIXEL_SLOTS * BRIGHTNESS_MAX))
#define PIXEL_PERIOD (BRIGHTNESS_MAX * QUANTUM)
#if (PIXEL_PERIOD > BIT_MASK(16)) || \
(USE_PWM && PIXEL_PERIOD > PWM_COUNTERTOP_COUNTERTOP_Msk)
#error "Invalid pixel period. Change refresh-frequency or pixel-group-size."
#endif
#define ACTIVE_LOW_MASK 0x80
#define PSEL_MASK 0x7F
#if (GROUP_SIZE > 1)
#define ITERATION_COUNT ROW_COUNT * COL_COUNT
#else
#define ITERATION_COUNT PIXEL_COUNT
#endif
struct display_drv_config {
NRF_TIMER_Type *timer;
#if USE_PWM
NRF_PWM_Type *pwm;
#else
nrfx_gpiote_t gpiote;
#endif
uint8_t rows[ROW_COUNT];
uint8_t cols[COL_COUNT];
uint8_t pixel_mapping[PIXEL_COUNT];
#if (GROUP_SIZE > 1)
uint8_t refresh_order[ITERATION_COUNT];
#endif
};
struct display_drv_data {
#if USE_PWM
uint16_t seq[PWM0_CH_NUM];
#else
uint8_t gpiote_ch[GROUP_SIZE];
#endif
uint8_t framebuf[PIXEL_COUNT];
uint8_t iteration;
uint8_t prev_row_idx;
uint8_t brightness;
bool blanking;
};
static void set_pin(uint8_t pin_info, bool active)
{
uint32_t value = active ? 1 : 0;
if (pin_info & ACTIVE_LOW_MASK) {
value = !value;
}
nrf_gpio_pin_write(pin_info & PSEL_MASK, value);
}
static int api_blanking_on(const struct device *dev)
{
struct display_drv_data *dev_data = dev->data;
const struct display_drv_config *dev_config = dev->config;
if (!dev_data->blanking) {
nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_STOP);
for (uint8_t i = 0; i < ROW_COUNT; ++i) {
set_pin(dev_config->rows[i], false);
}
for (uint8_t i = 0; i < COL_COUNT; ++i) {
set_pin(dev_config->cols[i], false);
}
dev_data->blanking = true;
}
return 0;
}
static int api_blanking_off(const struct device *dev)
{
struct display_drv_data *dev_data = dev->data;
const struct display_drv_config *dev_config = dev->config;
if (dev_data->blanking) {
dev_data->iteration = ITERATION_COUNT - 1;
nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_CLEAR);
nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
dev_data->blanking = false;
}
return 0;
}
static void *api_get_framebuffer(const struct device *dev)
{
struct display_drv_data *dev_data = dev->data;
return dev_data->framebuf;
}
static int api_set_brightness(const struct device *dev,
const uint8_t brightness)
{
struct display_drv_data *dev_data = dev->data;
uint8_t new_brightness = CLAMP(brightness, 1, BRIGHTNESS_MAX);
int16_t delta = (int16_t)new_brightness - dev_data->brightness;
dev_data->brightness = new_brightness;
for (uint8_t i = 0; i < PIXEL_COUNT; ++i) {
uint8_t old_val = dev_data->framebuf[i];
if (old_val) {
int16_t new_val = old_val + delta;
dev_data->framebuf[i] =
(uint8_t)CLAMP(new_val, 1, BRIGHTNESS_MAX);
}
}
return 0;
}
static int api_set_pixel_format(const struct device *dev,
const enum display_pixel_format format)
{
switch (format) {
case PIXEL_FORMAT_MONO01:
return 0;
default:
return -ENOTSUP;
}
}
static int api_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
switch (orientation) {
case DISPLAY_ORIENTATION_NORMAL:
return 0;
default:
return -ENOTSUP;
}
}
static void api_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
caps->x_resolution = X_PIXELS;
caps->y_resolution = Y_PIXELS;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO01;
caps->screen_info = 0;
caps->current_pixel_format = PIXEL_FORMAT_MONO01;
caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static inline void move_to_next_pixel(uint8_t *mask, uint8_t *data,
const uint8_t **byte_buf)
{
*mask <<= 1;
if (!*mask) {
*mask = 0x01;
*data = *(*byte_buf)++;
}
}
static int api_write(const struct device *dev,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
struct display_drv_data *dev_data = dev->data;
const uint8_t *byte_buf = buf;
uint16_t end_x = x + desc->width;
uint16_t end_y = y + desc->height;
if (x >= X_PIXELS || end_x > X_PIXELS ||
y >= Y_PIXELS || end_y > Y_PIXELS) {
return -EINVAL;
}
if (desc->pitch < desc->width) {
return -EINVAL;
}
uint16_t to_skip = desc->pitch - desc->width;
uint8_t mask = 0;
uint8_t data = 0;
for (uint16_t py = y; py < end_y; ++py) {
for (uint16_t px = x; px < end_x; ++px) {
move_to_next_pixel(&mask, &data, &byte_buf);
dev_data->framebuf[px + (py * X_PIXELS)] =
(data & mask) ? dev_data->brightness : 0;
}
if (to_skip) {
uint16_t cnt = to_skip;
do {
move_to_next_pixel(&mask, &data, &byte_buf);
} while (--cnt);
}
}
return 0;
}
const struct display_driver_api driver_api = {
.blanking_on = api_blanking_on,
.blanking_off = api_blanking_off,
.write = api_write,
.get_framebuffer = api_get_framebuffer,
.set_brightness = api_set_brightness,
.get_capabilities = api_get_capabilities,
.set_pixel_format = api_set_pixel_format,
.set_orientation = api_set_orientation,
};
static void prepare_pixel_pulse(const struct device *dev,
uint8_t pixel_idx,
uint8_t channel_idx)
{
struct display_drv_data *dev_data = dev->data;
const struct display_drv_config *dev_config = dev->config;
uint8_t col_idx = GET_COL_IDX(dev_config, pixel_idx);
uint8_t col_pin_info = dev_config->cols[col_idx];
uint8_t col_psel = (col_pin_info & PSEL_MASK);
bool col_active_low = (col_pin_info & ACTIVE_LOW_MASK);
uint16_t pulse = dev_data->framebuf[pixel_idx] * QUANTUM;
#if USE_PWM
dev_config->pwm->PSEL.OUT[channel_idx] = col_psel;
dev_data->seq[channel_idx] = pulse | (col_active_low ? 0 : BIT(15));
#else
uint32_t gpiote_cfg = GPIOTE_CONFIG_MODE_Task
| (col_psel << GPIOTE_CONFIG_PSEL_Pos);
if (col_active_low) {
gpiote_cfg |= (GPIOTE_CONFIG_POLARITY_LoToHi
<< GPIOTE_CONFIG_POLARITY_Pos)
/* If there should be no pulse at all for
* a given pixel, its column GPIO needs
* to be configured as initially inactive.
*/
| ((pulse == 0 ? GPIOTE_CONFIG_OUTINIT_High
: GPIOTE_CONFIG_OUTINIT_Low)
<< GPIOTE_CONFIG_OUTINIT_Pos);
} else {
gpiote_cfg |= (GPIOTE_CONFIG_POLARITY_HiToLo
<< GPIOTE_CONFIG_POLARITY_Pos)
| ((pulse == 0 ? GPIOTE_CONFIG_OUTINIT_Low
: GPIOTE_CONFIG_OUTINIT_High)
<< GPIOTE_CONFIG_OUTINIT_Pos);
}
/* First timer channel is used for timing the period of pulses. */
nrf_timer_cc_set(dev_config->timer, 1 + channel_idx, pulse);
dev_config->gpiote.p_reg->CONFIG[dev_data->gpiote_ch[channel_idx]] = gpiote_cfg;
#endif /* USE_PWM */
}
static void timer_irq_handler(void *arg)
{
const struct device *dev = arg;
struct display_drv_data *dev_data = dev->data;
const struct display_drv_config *dev_config = dev->config;
uint8_t iteration = dev_data->iteration;
uint8_t pixel_idx;
uint8_t row_idx;
/* The timer is automagically stopped and cleared by shortcuts
* on the same event (COMPARE0) that generates this interrupt.
* But the event itself needs to be cleared here.
*/
nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
/* Disable the row that was enabled in the previous iteration. */
set_pin(dev_config->rows[dev_data->prev_row_idx], false);
/* Disconnect used column pins from the peripheral that drove them. */
#if USE_PWM
nrf_pwm_disable(dev_config->pwm);
for (int i = 0; i < GROUP_SIZE; ++i) {
dev_config->pwm->PSEL.OUT[i] = NRF_PWM_PIN_NOT_CONNECTED;
}
#else
for (int i = 0; i < GROUP_SIZE; ++i) {
dev_config->gpiote.p_reg->CONFIG[dev_data->gpiote_ch[i]] = 0;
}
#endif
for (int i = 0; i < GROUP_SIZE; ++i) {
#if (GROUP_SIZE > 1)
do {
++iteration;
if (iteration >= ITERATION_COUNT) {
iteration = 0;
}
pixel_idx = dev_config->refresh_order[iteration];
} while (pixel_idx >= PIXEL_COUNT);
#else
++iteration;
if (iteration >= ITERATION_COUNT) {
iteration = 0;
}
pixel_idx = iteration;
#endif /* (GROUP_SIZE > 1) */
if (i == 0) {
row_idx = GET_ROW_IDX(dev_config, pixel_idx);
} else {
/* If the next pixel is in a different row, it cannot
* be lit within this group.
*/
if (row_idx != GET_ROW_IDX(dev_config, pixel_idx)) {
break;
}
}
dev_data->iteration = iteration;
prepare_pixel_pulse(dev, pixel_idx, i);
}
/* Enable the row drive for the current pixel. */
set_pin(dev_config->rows[row_idx], true);
dev_data->prev_row_idx = row_idx;
#if USE_PWM
/* Now that all the channels are configured, the PWM can be started. */
nrf_pwm_enable(dev_config->pwm);
nrf_pwm_task_trigger(dev_config->pwm, NRF_PWM_TASK_SEQSTART0);
#endif
/* Restart the timer. */
nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
}
static int instance_init(const struct device *dev)
{
struct display_drv_data *dev_data = dev->data;
const struct display_drv_config *dev_config = dev->config;
#if USE_PWM
uint32_t out_psels[NRF_PWM_CHANNEL_COUNT] = {
NRF_PWM_PIN_NOT_CONNECTED,
NRF_PWM_PIN_NOT_CONNECTED,
NRF_PWM_PIN_NOT_CONNECTED,
NRF_PWM_PIN_NOT_CONNECTED,
};
nrf_pwm_sequence_t sequence = {
.values.p_raw = dev_data->seq,
.length = PWM0_CH_NUM,
};
nrf_pwm_pins_set(dev_config->pwm, out_psels);
nrf_pwm_configure(dev_config->pwm,
PWM_CLK_CONFIG, NRF_PWM_MODE_UP, PIXEL_PERIOD);
nrf_pwm_decoder_set(dev_config->pwm,
NRF_PWM_LOAD_INDIVIDUAL, NRF_PWM_STEP_TRIGGERED);
nrf_pwm_sequence_set(dev_config->pwm, 0, &sequence);
nrf_pwm_loop_set(dev_config->pwm, 0);
nrf_pwm_shorts_set(dev_config->pwm, NRF_PWM_SHORT_SEQEND0_STOP_MASK);
#else
nrfx_err_t err;
nrf_ppi_channel_t ppi_ch;
for (int i = 0; i < GROUP_SIZE; ++i) {
uint8_t *gpiote_ch = &dev_data->gpiote_ch[i];
err = nrfx_ppi_channel_alloc(&ppi_ch);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate PPI channel.");
/* Do not bother with freeing resources allocated
* so far. The application needs to be reconfigured
* anyway.
*/
return -ENOMEM;
}
err = nrfx_gpiote_channel_alloc(&dev_config->gpiote, gpiote_ch);
if (err != NRFX_SUCCESS) {
LOG_ERR("Failed to allocate GPIOTE channel.");
/* Do not bother with freeing resources allocated
* so far. The application needs to be reconfigured
* anyway.
*/
return -ENOMEM;
}
nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
nrf_timer_event_address_get(dev_config->timer,
nrf_timer_compare_event_get(1 + i)),
nrf_gpiote_event_address_get(dev_config->gpiote.p_reg,
nrf_gpiote_out_task_get(*gpiote_ch)));
nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
}
#endif /* USE_PWM */
for (uint8_t i = 0; i < ROW_COUNT; ++i) {
uint8_t row_pin_info = dev_config->rows[i];
set_pin(row_pin_info, false);
nrf_gpio_cfg(row_pin_info & PSEL_MASK,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_H0H1,
NRF_GPIO_PIN_NOSENSE);
}
for (uint8_t i = 0; i < COL_COUNT; ++i) {
uint8_t col_pin_info = dev_config->cols[i];
set_pin(col_pin_info, false);
nrf_gpio_cfg(col_pin_info & PSEL_MASK,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
}
nrf_timer_bit_width_set(dev_config->timer, NRF_TIMER_BIT_WIDTH_16);
nrf_timer_prescaler_set(dev_config->timer, TIMER_CLK_CONFIG);
nrf_timer_cc_set(dev_config->timer, 0, PIXEL_PERIOD);
nrf_timer_shorts_set(dev_config->timer,
NRF_TIMER_SHORT_COMPARE0_STOP_MASK |
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
nrf_timer_int_enable(dev_config->timer, NRF_TIMER_INT_COMPARE0_MASK);
IRQ_CONNECT(DT_IRQN(TIMER_NODE), DT_IRQ(TIMER_NODE, priority),
timer_irq_handler, DEVICE_DT_GET(MATRIX_NODE), 0);
irq_enable(DT_IRQN(TIMER_NODE));
return 0;
}
static struct display_drv_data instance_data = {
.brightness = 0xFF,
.blanking = true,
};
#if !USE_PWM
#define CHECK_GPIOTE_INST(node_id, prop, idx) \
BUILD_ASSERT(NRF_DT_GPIOTE_INST_BY_IDX(node_id, prop, idx) == \
NRF_DT_GPIOTE_INST_BY_IDX(node_id, prop, 0), \
"All column GPIOs must use the same GPIOTE instance");
DT_FOREACH_PROP_ELEM(MATRIX_NODE, col_gpios, CHECK_GPIOTE_INST)
#endif
#define GET_PIN_INFO(node_id, pha, idx) \
(DT_GPIO_PIN_BY_IDX(node_id, pha, idx) | \
(DT_PROP_BY_PHANDLE_IDX(node_id, pha, idx, port) << 5) | \
((DT_GPIO_FLAGS_BY_IDX(node_id, pha, idx) & GPIO_ACTIVE_LOW) ? \
ACTIVE_LOW_MASK : 0)),
#define ADD_FF(i, _) 0xFF
#define FILL_ROW_WITH_FF(node_id, pha, idx) LISTIFY(COL_COUNT, ADD_FF, (,)),
#define GET_PIXEL_ORDINAL(node_id, pha, idx) \
[GET_DT_ROW_IDX(idx) * COL_COUNT + \
GET_DT_COL_IDX(idx)] = idx,
static const struct display_drv_config instance_config = {
.timer = (NRF_TIMER_Type *)DT_REG_ADDR(TIMER_NODE),
#if USE_PWM
.pwm = (NRF_PWM_Type *)DT_REG_ADDR(PWM_NODE),
#else
.gpiote = NRFX_GPIOTE_INSTANCE(
NRF_DT_GPIOTE_INST_BY_IDX(MATRIX_NODE, col_gpios, 0)),
#endif
.rows = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios, GET_PIN_INFO) },
.cols = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, col_gpios, GET_PIN_INFO) },
.pixel_mapping = DT_PROP(MATRIX_NODE, pixel_mapping),
#if (GROUP_SIZE > 1)
/* The whole array is by default filled with FFs, then the elements
* for the actually used row/columns pairs are overwritten (using
* designators) with the proper ordinal values for pixels.
*/
.refresh_order = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios,
FILL_ROW_WITH_FF)
DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping,
GET_PIXEL_ORDINAL) },
#endif
};
DEVICE_DT_DEFINE(MATRIX_NODE,
instance_init, NULL,
&instance_data, &instance_config,
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &driver_api);
``` | /content/code_sandbox/drivers/display/display_nrf_led_matrix.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,573 |
```c
/*
*
*/
#define LOG_LEVEL CONFIG_DISPLAY_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ssd16xx);
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/display.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/display/ssd16xx.h>
#include "ssd16xx_regs.h"
/**
* SSD16xx compatible EPD controller driver.
*/
#define EPD_PANEL_NUMOF_ROWS_PER_PAGE 8
#define SSD16XX_PANEL_FIRST_PAGE 0
#define SSD16XX_PANEL_FIRST_GATE 0
#define SSD16XX_PIXELS_PER_BYTE 8
#define SSD16XX_DEFAULT_TR_VALUE 25U
#define SSD16XX_TR_SCALE_FACTOR 256U
enum ssd16xx_profile_type {
SSD16XX_PROFILE_FULL = 0,
SSD16XX_PROFILE_PARTIAL,
SSD16XX_NUM_PROFILES,
SSD16XX_PROFILE_INVALID = SSD16XX_NUM_PROFILES,
};
struct ssd16xx_quirks {
/* Gates */
uint16_t max_width;
/* Sources */
uint16_t max_height;
/* Width (bits) of integer type representing an x coordinate */
uint8_t pp_width_bits;
/* Width (bits) of integer type representing a y coordinate */
uint8_t pp_height_bits;
/*
* Device specific flags to be included in
* SSD16XX_CMD_UPDATE_CTRL2 for a full refresh.
*/
uint8_t ctrl2_full;
/*
* Device specific flags to be included in
* SSD16XX_CMD_UPDATE_CTRL2 for a partial refresh.
*/
uint8_t ctrl2_partial;
};
struct ssd16xx_data {
bool read_supported;
uint8_t scan_mode;
bool blanking_on;
enum ssd16xx_profile_type profile;
enum display_orientation orientation;
};
struct ssd16xx_dt_array {
uint8_t *data;
uint8_t len;
};
struct ssd16xx_profile {
struct ssd16xx_dt_array lut;
struct ssd16xx_dt_array gdv;
struct ssd16xx_dt_array sdv;
uint8_t vcom;
uint8_t bwf;
uint8_t dummy_line;
uint8_t gate_line_width;
bool override_vcom;
bool override_bwf;
bool override_dummy_line;
bool override_gate_line_width;
};
struct ssd16xx_config {
const struct device *mipi_dev;
const struct mipi_dbi_config dbi_config;
struct gpio_dt_spec busy_gpio;
const struct ssd16xx_quirks *quirks;
struct ssd16xx_dt_array softstart;
const struct ssd16xx_profile *profiles[SSD16XX_NUM_PROFILES];
uint16_t rotation;
uint16_t height;
uint16_t width;
uint8_t tssv;
};
static int ssd16xx_set_profile(const struct device *dev,
enum ssd16xx_profile_type type);
static inline void ssd16xx_busy_wait(const struct device *dev)
{
const struct ssd16xx_config *config = dev->config;
int pin = gpio_pin_get_dt(&config->busy_gpio);
while (pin > 0) {
__ASSERT(pin >= 0, "Failed to get pin level");
k_msleep(SSD16XX_BUSY_DELAY);
pin = gpio_pin_get_dt(&config->busy_gpio);
}
}
static inline int ssd16xx_write_cmd(const struct device *dev, uint8_t cmd,
const uint8_t *data, size_t len)
{
const struct ssd16xx_config *config = dev->config;
int err;
ssd16xx_busy_wait(dev);
err = mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, data, len);
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return err;
}
static inline int ssd16xx_write_uint8(const struct device *dev, uint8_t cmd,
uint8_t data)
{
return ssd16xx_write_cmd(dev, cmd, &data, 1);
}
static inline int ssd16xx_read_cmd(const struct device *dev, uint8_t cmd,
uint8_t *data, size_t len)
{
const struct ssd16xx_config *config = dev->config;
const struct ssd16xx_data *dev_data = dev->data;
if (!dev_data->read_supported) {
return -ENOTSUP;
}
ssd16xx_busy_wait(dev);
return mipi_dbi_command_read(config->mipi_dev, &config->dbi_config,
&cmd, 1, data, len);
}
static inline size_t push_x_param(const struct device *dev,
uint8_t *data, uint16_t x)
{
const struct ssd16xx_config *config = dev->config;
if (config->quirks->pp_width_bits == 8) {
data[0] = (uint8_t)x;
return 1;
}
if (config->quirks->pp_width_bits == 16) {
sys_put_le16(sys_cpu_to_le16(x), data);
return 2;
}
LOG_ERR("Unsupported pp_width_bits %u",
config->quirks->pp_width_bits);
return 0;
}
static inline size_t push_y_param(const struct device *dev,
uint8_t *data, uint16_t y)
{
const struct ssd16xx_config *config = dev->config;
if (config->quirks->pp_height_bits == 8) {
data[0] = (uint8_t)y;
return 1;
}
if (config->quirks->pp_height_bits == 16) {
sys_put_le16(sys_cpu_to_le16(y), data);
return 2;
}
LOG_ERR("Unsupported pp_height_bitsa %u",
config->quirks->pp_height_bits);
return 0;
}
static inline int ssd16xx_set_ram_param(const struct device *dev,
uint16_t sx, uint16_t ex,
uint16_t sy, uint16_t ey)
{
int err;
uint8_t tmp[4];
size_t len;
len = push_x_param(dev, tmp, sx);
len += push_x_param(dev, tmp + len, ex);
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_RAM_XPOS_CTRL, tmp, len);
if (err < 0) {
return err;
}
len = push_y_param(dev, tmp, sy);
len += push_y_param(dev, tmp + len, ey);
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_RAM_YPOS_CTRL, tmp, len);
if (err < 0) {
return err;
}
return 0;
}
static inline int ssd16xx_set_ram_ptr(const struct device *dev, uint16_t x,
uint16_t y)
{
int err;
uint8_t tmp[2];
size_t len;
len = push_x_param(dev, tmp, x);
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_RAM_XPOS_CNTR, tmp, len);
if (err < 0) {
return err;
}
len = push_y_param(dev, tmp, y);
return ssd16xx_write_cmd(dev, SSD16XX_CMD_RAM_YPOS_CNTR, tmp, len);
}
static int ssd16xx_activate(const struct device *dev, uint8_t ctrl2)
{
int err;
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_UPDATE_CTRL2, ctrl2);
if (err < 0) {
return err;
}
return ssd16xx_write_cmd(dev, SSD16XX_CMD_MASTER_ACTIVATION, NULL, 0);
}
static int ssd16xx_update_display(const struct device *dev)
{
const struct ssd16xx_config *config = dev->config;
const struct ssd16xx_data *data = dev->data;
const struct ssd16xx_profile *p = config->profiles[data->profile];
const struct ssd16xx_quirks *quirks = config->quirks;
const bool load_lut = !p || p->lut.len == 0;
const bool load_temp = load_lut && config->tssv;
const bool partial = data->profile == SSD16XX_PROFILE_PARTIAL;
const uint8_t update_cmd =
SSD16XX_CTRL2_ENABLE_CLK |
SSD16XX_CTRL2_ENABLE_ANALOG |
(load_lut ? SSD16XX_CTRL2_LOAD_LUT : 0) |
(load_temp ? SSD16XX_CTRL2_LOAD_TEMPERATURE : 0) |
(partial ? quirks->ctrl2_partial : quirks->ctrl2_full) |
SSD16XX_CTRL2_DISABLE_ANALOG |
SSD16XX_CTRL2_DISABLE_CLK;
return ssd16xx_activate(dev, update_cmd);
}
static int ssd16xx_blanking_off(const struct device *dev)
{
struct ssd16xx_data *data = dev->data;
if (data->blanking_on) {
data->blanking_on = false;
return ssd16xx_update_display(dev);
}
return 0;
}
static int ssd16xx_blanking_on(const struct device *dev)
{
struct ssd16xx_data *data = dev->data;
if (!data->blanking_on) {
if (ssd16xx_set_profile(dev, SSD16XX_PROFILE_FULL)) {
return -EIO;
}
}
data->blanking_on = true;
return 0;
}
static int ssd16xx_set_window(const struct device *dev,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc)
{
const struct ssd16xx_config *config = dev->config;
const struct ssd16xx_data *data = dev->data;
int err;
uint16_t x_start;
uint16_t x_end;
uint16_t y_start;
uint16_t y_end;
uint16_t panel_h = config->height -
config->height % EPD_PANEL_NUMOF_ROWS_PER_PAGE;
if (desc->pitch < desc->width) {
LOG_ERR("Pitch is smaller than width");
return -EINVAL;
}
if (desc->pitch > desc->width) {
LOG_ERR("Unsupported mode");
return -ENOTSUP;
}
if (data->orientation == DISPLAY_ORIENTATION_NORMAL ||
data->orientation == DISPLAY_ORIENTATION_ROTATED_180) {
if ((y + desc->height) > panel_h) {
LOG_ERR("Buffer out of bounds (height)");
return -EINVAL;
}
if ((x + desc->width) > config->width) {
LOG_ERR("Buffer out of bounds (width)");
return -EINVAL;
}
if ((desc->height % EPD_PANEL_NUMOF_ROWS_PER_PAGE) != 0U) {
LOG_ERR("Buffer height not multiple of %d", EPD_PANEL_NUMOF_ROWS_PER_PAGE);
return -EINVAL;
}
if ((y % EPD_PANEL_NUMOF_ROWS_PER_PAGE) != 0U) {
LOG_ERR("Y coordinate not multiple of %d", EPD_PANEL_NUMOF_ROWS_PER_PAGE);
return -EINVAL;
}
} else {
if ((y + desc->height) > config->width) {
LOG_ERR("Buffer out of bounds (height)");
return -EINVAL;
}
if ((x + desc->width) > panel_h) {
LOG_ERR("Buffer out of bounds (width)");
return -EINVAL;
}
if ((desc->width % SSD16XX_PIXELS_PER_BYTE) != 0U) {
LOG_ERR("Buffer width not multiple of %d", SSD16XX_PIXELS_PER_BYTE);
return -EINVAL;
}
if ((x % SSD16XX_PIXELS_PER_BYTE) != 0U) {
LOG_ERR("X coordinate not multiple of %d", SSD16XX_PIXELS_PER_BYTE);
return -EINVAL;
}
}
switch (data->orientation) {
case DISPLAY_ORIENTATION_NORMAL:
x_start = (panel_h - 1 - y) / SSD16XX_PIXELS_PER_BYTE;
x_end = (panel_h - 1 - (y + desc->height - 1)) / SSD16XX_PIXELS_PER_BYTE;
y_start = x;
y_end = (x + desc->width - 1);
break;
case DISPLAY_ORIENTATION_ROTATED_90:
x_start = (panel_h - 1 - x) / SSD16XX_PIXELS_PER_BYTE;
x_end = (panel_h - 1 - (x + desc->width - 1)) / SSD16XX_PIXELS_PER_BYTE;
y_start = (config->width - 1 - y);
y_end = (config->width - 1 - (y + desc->height - 1));
break;
case DISPLAY_ORIENTATION_ROTATED_180:
x_start = y / SSD16XX_PIXELS_PER_BYTE;
x_end = (y + desc->height - 1) / SSD16XX_PIXELS_PER_BYTE;
y_start = (x + desc->width - 1);
y_end = x;
break;
case DISPLAY_ORIENTATION_ROTATED_270:
x_start = x / SSD16XX_PIXELS_PER_BYTE;
x_end = (x + desc->width - 1) / SSD16XX_PIXELS_PER_BYTE;
y_start = y;
y_end = (y + desc->height - 1);
break;
default:
return -EINVAL;
}
err = ssd16xx_set_ram_param(dev, x_start, x_end, y_start, y_end);
if (err < 0) {
return err;
}
err = ssd16xx_set_ram_ptr(dev, x_start, y_start);
if (err < 0) {
return err;
}
return 0;
}
static int ssd16xx_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct ssd16xx_config *config = dev->config;
const struct ssd16xx_data *data = dev->data;
const bool have_partial_refresh =
config->profiles[SSD16XX_PROFILE_PARTIAL] != NULL;
const bool partial_refresh = !data->blanking_on && have_partial_refresh;
const size_t buf_len = MIN(desc->buf_size,
desc->height * desc->width / 8);
int err;
if (buf == NULL || buf_len == 0U) {
LOG_ERR("Display buffer is not available");
return -EINVAL;
}
if (partial_refresh) {
/*
* Request the partial profile. This operation becomes
* a no-op if the profile is already active.
*/
err = ssd16xx_set_profile(dev, SSD16XX_PROFILE_PARTIAL);
if (err < 0) {
return -EIO;
}
}
err = ssd16xx_set_window(dev, x, y, desc);
if (err < 0) {
return err;
}
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_WRITE_RAM, (uint8_t *)buf,
buf_len);
if (err < 0) {
return err;
}
if (!data->blanking_on) {
err = ssd16xx_update_display(dev);
if (err < 0) {
return err;
}
}
if (data->blanking_on && have_partial_refresh) {
/*
* We will trigger a full refresh when blanking is
* turned off. The controller won't keep track of the
* old frame buffer, which is needed to perform a
* partial update, when this happens. Maintain the old
* frame buffer manually here to make sure future
* partial updates will work as expected.
*/
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_WRITE_RED_RAM,
(uint8_t *)buf, buf_len);
if (err < 0) {
return err;
}
} else if (partial_refresh) {
/*
* We just performed a partial refresh. After the
* refresh, the controller swaps the black/red buffers
* containing the current and new image. We need to
* perform a second write here to ensure that future
* updates work on an up-to-date framebuffer.
*/
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_WRITE_RAM,
(uint8_t *)buf, buf_len);
if (err < 0) {
return err;
}
}
return 0;
}
int ssd16xx_read_ram(const struct device *dev, enum ssd16xx_ram ram_type,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
const struct ssd16xx_data *data = dev->data;
const size_t buf_len = MIN(desc->buf_size,
desc->height * desc->width / 8);
int err;
uint8_t ram_ctrl;
if (!data->read_supported) {
return -ENOTSUP;
}
switch (ram_type) {
case SSD16XX_RAM_BLACK:
ram_ctrl = SSD16XX_RAM_READ_CTRL_BLACK;
break;
case SSD16XX_RAM_RED:
ram_ctrl = SSD16XX_RAM_READ_CTRL_RED;
break;
default:
return -EINVAL;
}
if (buf == NULL || buf_len == 0U) {
LOG_ERR("Display buffer is not available");
return -EINVAL;
}
err = ssd16xx_set_window(dev, x, y, desc);
if (err < 0) {
return err;
}
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_RAM_READ_CTRL,
&ram_ctrl, sizeof(ram_ctrl));
if (err < 0) {
return err;
}
err = ssd16xx_read_cmd(dev, SSD16XX_CMD_READ_RAM, (uint8_t *)buf,
buf_len);
if (err < 0) {
return err;
}
return 0;
}
static int ssd16xx_read(const struct device *dev,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
return ssd16xx_read_ram(dev, SSD16XX_RAM_BLACK, x, y, desc, buf);
}
static void ssd16xx_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct ssd16xx_config *config = dev->config;
struct ssd16xx_data *data = dev->data;
memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = config->width;
caps->y_resolution = config->height -
config->height % EPD_PANEL_NUMOF_ROWS_PER_PAGE;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
caps->current_pixel_format = PIXEL_FORMAT_MONO10;
caps->screen_info = SCREEN_INFO_MONO_MSB_FIRST | SCREEN_INFO_EPD;
if (data->orientation == DISPLAY_ORIENTATION_NORMAL ||
data->orientation == DISPLAY_ORIENTATION_ROTATED_180) {
caps->screen_info |= SCREEN_INFO_MONO_VTILED;
}
caps->current_orientation = data->orientation;
}
static int ssd16xx_set_pixel_format(const struct device *dev,
const enum display_pixel_format pf)
{
if (pf == PIXEL_FORMAT_MONO10) {
return 0;
}
LOG_ERR("not supported");
return -ENOTSUP;
}
static int ssd16xx_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
struct ssd16xx_data *data = dev->data;
int err;
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
data->scan_mode = SSD16XX_DATA_ENTRY_XDYIY;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) {
data->scan_mode = SSD16XX_DATA_ENTRY_XDYDX;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) {
data->scan_mode = SSD16XX_DATA_ENTRY_XIYDY;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) {
data->scan_mode = SSD16XX_DATA_ENTRY_XIYIX;
}
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_ENTRY_MODE, data->scan_mode);
if (err < 0) {
return err;
}
data->orientation = orientation;
return 0;
}
static int ssd16xx_clear_cntlr_mem(const struct device *dev, uint8_t ram_cmd)
{
const struct ssd16xx_config *config = dev->config;
uint16_t panel_h = config->height / EPD_PANEL_NUMOF_ROWS_PER_PAGE;
uint16_t last_gate = config->width - 1;
uint8_t clear_page[64];
int err;
/*
* Clear unusable memory area when the resolution of the panel is not
* multiple of an octet.
*/
if (config->height % EPD_PANEL_NUMOF_ROWS_PER_PAGE) {
panel_h += 1;
}
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_ENTRY_MODE,
SSD16XX_DATA_ENTRY_XIYDY);
if (err < 0) {
return err;
}
err = ssd16xx_set_ram_param(dev, SSD16XX_PANEL_FIRST_PAGE,
panel_h - 1, last_gate,
SSD16XX_PANEL_FIRST_GATE);
if (err < 0) {
return err;
}
err = ssd16xx_set_ram_ptr(dev, SSD16XX_PANEL_FIRST_PAGE, last_gate);
if (err < 0) {
return err;
}
memset(clear_page, 0xff, sizeof(clear_page));
for (int h = 0; h < panel_h; h++) {
size_t x = config->width;
while (x) {
size_t l = MIN(x, sizeof(clear_page));
x -= l;
err = ssd16xx_write_cmd(dev, ram_cmd, clear_page, l);
if (err < 0) {
return err;
}
}
}
return 0;
}
static inline int ssd16xx_load_ws_from_otp_tssv(const struct device *dev)
{
const struct ssd16xx_config *config = dev->config;
/*
* Controller has an integrated temperature sensor or external
* temperature sensor is connected to the controller.
*/
LOG_INF("Select and load WS from OTP");
return ssd16xx_write_uint8(dev, SSD16XX_CMD_TSENSOR_SELECTION,
config->tssv);
}
static inline int ssd16xx_load_ws_from_otp(const struct device *dev)
{
int16_t t = (SSD16XX_DEFAULT_TR_VALUE * SSD16XX_TR_SCALE_FACTOR);
uint8_t tmp[2];
int err;
LOG_INF("Load default WS (25 degrees Celsius) from OTP");
err = ssd16xx_activate(dev, SSD16XX_CTRL2_ENABLE_CLK);
if (err < 0) {
return err;
}
/* Load temperature value */
sys_put_be16(t, tmp);
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_TSENS_CTRL, tmp, 2);
if (err < 0) {
return err;
}
err = ssd16xx_activate(dev, SSD16XX_CTRL2_DISABLE_CLK);
if (err < 0) {
return err;
}
return 0;
}
static int ssd16xx_load_lut(const struct device *dev,
const struct ssd16xx_dt_array *lut)
{
const struct ssd16xx_config *config = dev->config;
if (lut && lut->len) {
LOG_DBG("Using user-provided LUT");
return ssd16xx_write_cmd(dev, SSD16XX_CMD_UPDATE_LUT,
lut->data, lut->len);
} else {
if (config->tssv) {
return ssd16xx_load_ws_from_otp_tssv(dev);
} else {
return ssd16xx_load_ws_from_otp(dev);
}
}
}
static int ssd16xx_set_profile(const struct device *dev,
enum ssd16xx_profile_type type)
{
const struct ssd16xx_config *config = dev->config;
struct ssd16xx_data *data = dev->data;
const struct ssd16xx_profile *p;
const uint16_t last_gate = config->width - 1;
uint8_t gdo[3];
size_t gdo_len;
int err = 0;
if (type >= SSD16XX_NUM_PROFILES) {
return -EINVAL;
}
p = config->profiles[type];
/*
* The full profile is the only one that always exists. If it
* hasn't been specified, we use the defaults.
*/
if (!p && type != SSD16XX_PROFILE_FULL) {
return -ENOENT;
}
if (type == data->profile) {
return 0;
}
/*
* Perform a soft reset to make sure registers are reset. This
* will leave the RAM contents intact.
*/
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_SW_RESET, NULL, 0);
if (err < 0) {
return err;
}
gdo_len = push_y_param(dev, gdo, last_gate);
gdo[gdo_len++] = 0U;
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_GDO_CTRL, gdo, gdo_len);
if (err < 0) {
return err;
}
if (config->softstart.len) {
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_SOFTSTART,
config->softstart.data,
config->softstart.len);
if (err < 0) {
return err;
}
}
err = ssd16xx_load_lut(dev, p ? &p->lut : NULL);
if (err < 0) {
return err;
}
if (p && p->override_dummy_line) {
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_DUMMY_LINE,
p->dummy_line);
if (err < 0) {
return err;
}
}
if (p && p->override_gate_line_width) {
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_GATE_LINE_WIDTH,
p->override_gate_line_width);
if (err < 0) {
return err;
}
}
if (p && p->gdv.len) {
LOG_DBG("Setting GDV");
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_GDV_CTRL,
p->gdv.data, p->gdv.len);
if (err < 0) {
return err;
}
}
if (p && p->sdv.len) {
LOG_DBG("Setting SDV");
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_SDV_CTRL,
p->sdv.data, p->sdv.len);
if (err < 0) {
return err;
}
}
if (p && p->override_vcom) {
LOG_DBG("Setting VCOM");
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_VCOM_VOLTAGE,
&p->vcom, 1);
if (err < 0) {
return err;
}
}
if (p && p->override_bwf) {
LOG_DBG("Setting BWF");
err = ssd16xx_write_cmd(dev, SSD16XX_CMD_BWF_CTRL,
&p->bwf, 1);
if (err < 0) {
return err;
}
}
err = ssd16xx_write_uint8(dev, SSD16XX_CMD_ENTRY_MODE, data->scan_mode);
if (err < 0) {
return err;
}
data->profile = type;
return 0;
}
static int ssd16xx_controller_init(const struct device *dev)
{
const struct ssd16xx_config *config = dev->config;
struct ssd16xx_data *data = dev->data;
enum display_orientation orientation;
int err;
LOG_DBG("");
data->blanking_on = false;
data->profile = SSD16XX_PROFILE_INVALID;
err = mipi_dbi_reset(config->mipi_dev, SSD16XX_RESET_DELAY);
if (err < 0) {
return err;
}
k_msleep(SSD16XX_RESET_DELAY);
err = ssd16xx_set_profile(dev, SSD16XX_PROFILE_FULL);
if (err < 0) {
return err;
}
err = ssd16xx_clear_cntlr_mem(dev, SSD16XX_CMD_WRITE_RAM);
if (err < 0) {
return err;
}
err = ssd16xx_clear_cntlr_mem(dev, SSD16XX_CMD_WRITE_RED_RAM);
if (err < 0) {
return err;
}
if (config->rotation == 0U) {
orientation = DISPLAY_ORIENTATION_NORMAL;
} else if (config->rotation == 90U) {
orientation = DISPLAY_ORIENTATION_ROTATED_90;
} else if (config->rotation == 180U) {
orientation = DISPLAY_ORIENTATION_ROTATED_180;
} else {
orientation = DISPLAY_ORIENTATION_ROTATED_270;
}
err = ssd16xx_set_orientation(dev, orientation);
if (err < 0) {
return err;
}
err = ssd16xx_update_display(dev);
if (err < 0) {
return err;
}
return 0;
}
static int ssd16xx_init(const struct device *dev)
{
const struct ssd16xx_config *config = dev->config;
struct ssd16xx_data *data = dev->data;
int err;
LOG_DBG("");
if (!device_is_ready(config->mipi_dev)) {
LOG_ERR("MIPI Device not ready");
return -ENODEV;
}
data->read_supported =
(config->dbi_config.config.operation & SPI_HALF_DUPLEX) != 0;
if (!gpio_is_ready_dt(&config->busy_gpio)) {
LOG_ERR("Busy GPIO device not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->busy_gpio, GPIO_INPUT);
if (err < 0) {
LOG_ERR("Failed to configure busy GPIO");
return err;
}
if (config->width > config->quirks->max_width ||
config->height > config->quirks->max_height) {
LOG_ERR("Display size out of range.");
return -EINVAL;
}
return ssd16xx_controller_init(dev);
}
static const struct display_driver_api ssd16xx_driver_api = {
.blanking_on = ssd16xx_blanking_on,
.blanking_off = ssd16xx_blanking_off,
.write = ssd16xx_write,
.read = ssd16xx_read,
.get_capabilities = ssd16xx_get_capabilities,
.set_pixel_format = ssd16xx_set_pixel_format,
.set_orientation = ssd16xx_set_orientation,
};
#if DT_HAS_COMPAT_STATUS_OKAY(solomon_ssd1608)
static struct ssd16xx_quirks quirks_solomon_ssd1608 = {
.max_width = 320,
.max_height = 240,
.pp_width_bits = 16,
.pp_height_bits = 16,
.ctrl2_full = SSD16XX_GEN1_CTRL2_TO_PATTERN,
.ctrl2_partial = SSD16XX_GEN1_CTRL2_TO_PATTERN,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(solomon_ssd1673)
static struct ssd16xx_quirks quirks_solomon_ssd1673 = {
.max_width = 250,
.max_height = 150,
.pp_width_bits = 8,
.pp_height_bits = 8,
.ctrl2_full = SSD16XX_GEN1_CTRL2_TO_PATTERN,
.ctrl2_partial = SSD16XX_GEN1_CTRL2_TO_PATTERN,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(solomon_ssd1675a)
static struct ssd16xx_quirks quirks_solomon_ssd1675a = {
.max_width = 296,
.max_height = 160,
.pp_width_bits = 8,
.pp_height_bits = 16,
.ctrl2_full = SSD16XX_GEN1_CTRL2_TO_PATTERN,
.ctrl2_partial = SSD16XX_GEN1_CTRL2_TO_PATTERN,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(solomon_ssd1680)
static const struct ssd16xx_quirks quirks_solomon_ssd1680 = {
.max_width = 296,
.max_height = 176,
.pp_width_bits = 8,
.pp_height_bits = 16,
.ctrl2_full = SSD16XX_GEN2_CTRL2_DISPLAY,
.ctrl2_partial = SSD16XX_GEN2_CTRL2_DISPLAY | SSD16XX_GEN2_CTRL2_MODE2,
};
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(solomon_ssd1681)
static struct ssd16xx_quirks quirks_solomon_ssd1681 = {
.max_width = 200,
.max_height = 200,
.pp_width_bits = 8,
.pp_height_bits = 16,
.ctrl2_full = SSD16XX_GEN2_CTRL2_DISPLAY,
.ctrl2_partial = SSD16XX_GEN2_CTRL2_DISPLAY | SSD16XX_GEN2_CTRL2_MODE2,
};
#endif
#define SOFTSTART_ASSIGN(n) \
.softstart = { \
.data = softstart_##n, \
.len = sizeof(softstart_##n), \
},
#define SSD16XX_MAKE_ARRAY_OPT(n, p) \
static uint8_t data_ ## n ## _ ## p[] = DT_PROP_OR(n, p, {})
#define SSD16XX_ASSIGN_ARRAY(n, p) \
{ \
.data = data_ ## n ## _ ## p, \
.len = sizeof(data_ ## n ## _ ## p), \
}
#define SSD16XX_PROFILE(n) \
SSD16XX_MAKE_ARRAY_OPT(n, lut); \
SSD16XX_MAKE_ARRAY_OPT(n, gdv); \
SSD16XX_MAKE_ARRAY_OPT(n, sdv); \
\
static const struct ssd16xx_profile ssd16xx_profile_ ## n = { \
.lut = SSD16XX_ASSIGN_ARRAY(n, lut), \
.gdv = SSD16XX_ASSIGN_ARRAY(n, gdv), \
.sdv = SSD16XX_ASSIGN_ARRAY(n, sdv), \
.vcom = DT_PROP_OR(n, vcom, 0), \
.override_vcom = DT_NODE_HAS_PROP(n, vcom), \
.bwf = DT_PROP_OR(n, border_waveform, 0), \
.override_bwf = DT_NODE_HAS_PROP(n, border_waveform), \
.dummy_line = DT_PROP_OR(n, dummy_line, 0), \
.override_dummy_line = DT_NODE_HAS_PROP(n, dummy_line), \
.gate_line_width = DT_PROP_OR(n, gate_line_width, 0), \
.override_gate_line_width = DT_NODE_HAS_PROP( \
n, gate_line_width), \
};
#define _SSD16XX_PROFILE_PTR(n) &ssd16xx_profile_ ## n
#define SSD16XX_PROFILE_PTR(n) \
COND_CODE_1(DT_NODE_EXISTS(n), \
(_SSD16XX_PROFILE_PTR(n)), \
NULL)
#define SSD16XX_DEFINE(n, quirks_ptr) \
SSD16XX_MAKE_ARRAY_OPT(n, softstart); \
\
DT_FOREACH_CHILD(n, SSD16XX_PROFILE); \
\
static const struct ssd16xx_config ssd16xx_cfg_ ## n = { \
.mipi_dev = DEVICE_DT_GET(DT_PARENT(n)), \
.dbi_config = { \
.mode = MIPI_DBI_MODE_SPI_4WIRE, \
.config = MIPI_DBI_SPI_CONFIG_DT(n, \
SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \
SPI_HOLD_ON_CS | SPI_LOCK_ON, 0), \
}, \
.busy_gpio = GPIO_DT_SPEC_GET(n, busy_gpios), \
.quirks = quirks_ptr, \
.height = DT_PROP(n, height), \
.width = DT_PROP(n, width), \
.rotation = DT_PROP(n, rotation), \
.tssv = DT_PROP_OR(n, tssv, 0), \
.softstart = SSD16XX_ASSIGN_ARRAY(n, softstart), \
.profiles = { \
[SSD16XX_PROFILE_FULL] = \
SSD16XX_PROFILE_PTR(DT_CHILD(n, full)), \
[SSD16XX_PROFILE_PARTIAL] = \
SSD16XX_PROFILE_PTR(DT_CHILD(n, partial)),\
}, \
}; \
\
static struct ssd16xx_data ssd16xx_data_ ## n; \
\
DEVICE_DT_DEFINE(n, \
ssd16xx_init, NULL, \
&ssd16xx_data_ ## n, \
&ssd16xx_cfg_ ## n, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&ssd16xx_driver_api)
DT_FOREACH_STATUS_OKAY_VARGS(solomon_ssd1608, SSD16XX_DEFINE,
&quirks_solomon_ssd1608);
DT_FOREACH_STATUS_OKAY_VARGS(solomon_ssd1673, SSD16XX_DEFINE,
&quirks_solomon_ssd1673);
DT_FOREACH_STATUS_OKAY_VARGS(solomon_ssd1675a, SSD16XX_DEFINE,
&quirks_solomon_ssd1675a);
DT_FOREACH_STATUS_OKAY_VARGS(solomon_ssd1680, SSD16XX_DEFINE,
&quirks_solomon_ssd1680);
DT_FOREACH_STATUS_OKAY_VARGS(solomon_ssd1681, SSD16XX_DEFINE,
&quirks_solomon_ssd1681);
``` | /content/code_sandbox/drivers/display/ssd16xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,359 |
```c
/*
*
*/
#define DT_DRV_COMPAT sitronix_st7735r
#include "display_st7735r.h"
#include <zephyr/device.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/display.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_st7735r, CONFIG_DISPLAY_LOG_LEVEL);
#define ST7735R_RESET_TIME 1
#define ST7735R_EXIT_SLEEP_TIME K_MSEC(120)
#define ST7735R_PIXEL_SIZE 2u
struct st7735r_config {
const struct device *mipi_dev;
const struct mipi_dbi_config dbi_config;
uint16_t height;
uint16_t width;
uint8_t madctl;
uint8_t colmod;
uint8_t caset[4];
uint8_t raset[4];
uint8_t vmctr1;
uint8_t invctr;
uint8_t pwctr1[3];
uint8_t pwctr2[1];
uint8_t pwctr3[2];
uint8_t pwctr4[2];
uint8_t pwctr5[2];
uint8_t frmctr1[3];
uint8_t frmctr2[3];
uint8_t frmctr3[6];
uint8_t gamctrp1[16];
uint8_t gamctrn1[16];
bool inversion_on;
bool rgb_is_inverted;
};
struct st7735r_data {
uint16_t x_offset;
uint16_t y_offset;
};
static void st7735r_set_lcd_margins(const struct device *dev,
uint16_t x_offset, uint16_t y_offset)
{
struct st7735r_data *data = dev->data;
data->x_offset = x_offset;
data->y_offset = y_offset;
}
static int st7735r_transmit_hold(const struct device *dev, uint8_t cmd,
const uint8_t *tx_data, size_t tx_count)
{
const struct st7735r_config *config = dev->config;
return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, tx_data, tx_count);
}
static int st7735r_transmit(const struct device *dev, uint8_t cmd,
const uint8_t *tx_data, size_t tx_count)
{
const struct st7735r_config *config = dev->config;
int ret;
ret = st7735r_transmit_hold(dev, cmd, tx_data, tx_count);
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return ret;
}
static int st7735r_exit_sleep(const struct device *dev)
{
int ret;
ret = st7735r_transmit(dev, ST7735R_CMD_SLEEP_OUT, NULL, 0);
if (ret < 0) {
return ret;
}
k_sleep(ST7735R_EXIT_SLEEP_TIME);
return 0;
}
static int st7735r_reset_display(const struct device *dev)
{
const struct st7735r_config *config = dev->config;
int ret;
LOG_DBG("Resetting display");
ret = mipi_dbi_reset(config->mipi_dev, ST7735R_RESET_TIME);
if (ret != 0) {
ret = st7735r_transmit(dev, ST7735R_CMD_SW_RESET, NULL, 0);
if (ret < 0) {
return ret;
}
}
k_sleep(ST7735R_EXIT_SLEEP_TIME);
return 0;
}
static int st7735r_blanking_on(const struct device *dev)
{
return st7735r_transmit(dev, ST7735R_CMD_DISP_OFF, NULL, 0);
}
static int st7735r_blanking_off(const struct device *dev)
{
return st7735r_transmit(dev, ST7735R_CMD_DISP_ON, NULL, 0);
}
static int st7735r_set_mem_area(const struct device *dev,
const uint16_t x, const uint16_t y,
const uint16_t w, const uint16_t h)
{
const struct st7735r_config *config = dev->config;
struct st7735r_data *data = dev->data;
uint16_t spi_data[2];
int ret;
/* ST7735S requires repeating COLMOD for each transfer */
ret = st7735r_transmit_hold(dev, ST7735R_CMD_COLMOD, &config->colmod, 1);
if (ret < 0) {
return ret;
}
uint16_t ram_x = x + data->x_offset;
uint16_t ram_y = y + data->y_offset;
spi_data[0] = sys_cpu_to_be16(ram_x);
spi_data[1] = sys_cpu_to_be16(ram_x + w - 1);
ret = st7735r_transmit_hold(dev, ST7735R_CMD_CASET, (uint8_t *)&spi_data[0], 4);
if (ret < 0) {
return ret;
}
spi_data[0] = sys_cpu_to_be16(ram_y);
spi_data[1] = sys_cpu_to_be16(ram_y + h - 1);
ret = st7735r_transmit_hold(dev, ST7735R_CMD_RASET, (uint8_t *)&spi_data[0], 4);
if (ret < 0) {
return ret;
}
/* NB: CS still held - data transfer coming next */
return 0;
}
static int st7735r_write(const struct device *dev,
const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct st7735r_config *config = dev->config;
const uint8_t *write_data_start = (uint8_t *) buf;
uint16_t write_cnt;
uint16_t nbr_of_writes;
uint16_t write_h;
int ret;
enum display_pixel_format fmt;
struct display_buffer_descriptor mipi_desc;
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
__ASSERT((desc->pitch * ST7735R_PIXEL_SIZE * desc->height)
<= desc->buf_size, "Input buffer too small");
LOG_DBG("Writing %dx%d (w,h) @ %dx%d (x,y)",
desc->width, desc->height, x, y);
ret = st7735r_set_mem_area(dev, x, y, desc->width, desc->height);
if (ret < 0) {
goto out;
}
if (desc->pitch > desc->width) {
write_h = 1U;
nbr_of_writes = desc->height;
mipi_desc.height = 1;
mipi_desc.buf_size = desc->pitch * ST7735R_PIXEL_SIZE;
} else {
write_h = desc->height;
nbr_of_writes = 1U;
mipi_desc.height = desc->height;
mipi_desc.buf_size = desc->width * ST7735R_PIXEL_SIZE * write_h;
}
mipi_desc.width = desc->width;
/* Per MIPI API, pitch must always match width */
mipi_desc.pitch = desc->width;
if (!(config->madctl & ST7735R_MADCTL_BGR) != !config->rgb_is_inverted) {
fmt = PIXEL_FORMAT_BGR_565;
} else {
fmt = PIXEL_FORMAT_RGB_565;
}
ret = st7735r_transmit_hold(dev, ST7735R_CMD_RAMWR,
(void *) write_data_start,
desc->width * ST7735R_PIXEL_SIZE * write_h);
if (ret < 0) {
goto out;
}
write_data_start += (desc->pitch * ST7735R_PIXEL_SIZE);
for (write_cnt = 1U; write_cnt < nbr_of_writes; ++write_cnt) {
ret = mipi_dbi_write_display(config->mipi_dev,
&config->dbi_config,
write_data_start,
&mipi_desc,
fmt);
if (ret < 0) {
goto out;
}
write_data_start += (desc->pitch * ST7735R_PIXEL_SIZE);
}
ret = 0;
out:
mipi_dbi_release(config->mipi_dev, &config->dbi_config);
return ret;
}
static void st7735r_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct st7735r_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->width;
capabilities->y_resolution = config->height;
/*
* Invert the pixel format if rgb_is_inverted is enabled.
* Report pixel format as the same format set in the MADCTL
* if disabling the rgb_is_inverted option.
* Or not so, reporting pixel format as RGB if MADCTL setting
* is BGR. And also vice versa.
* It is a workaround for supporting buggy modules that display RGB as BGR.
*/
if (!(config->madctl & ST7735R_MADCTL_BGR) != !config->rgb_is_inverted) {
capabilities->supported_pixel_formats = PIXEL_FORMAT_BGR_565;
capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
} else {
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565;
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565;
}
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int st7735r_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
const struct st7735r_config *config = dev->config;
if ((pixel_format == PIXEL_FORMAT_RGB_565) &&
(~config->madctl & ST7735R_MADCTL_BGR)) {
return 0;
}
if ((pixel_format == PIXEL_FORMAT_BGR_565) &&
(config->madctl & ST7735R_MADCTL_BGR)) {
return 0;
}
LOG_ERR("Pixel format change not implemented");
return -ENOTSUP;
}
static int st7735r_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
LOG_ERR("Changing display orientation not implemented");
return -ENOTSUP;
}
static int st7735r_lcd_init(const struct device *dev)
{
const struct st7735r_config *config = dev->config;
struct st7735r_data *data = dev->data;
int ret;
st7735r_set_lcd_margins(dev, data->x_offset, data->y_offset);
ret = st7735r_transmit(dev, ST7735R_CMD_FRMCTR1, config->frmctr1,
sizeof(config->frmctr1));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_FRMCTR2, config->frmctr2,
sizeof(config->frmctr2));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_FRMCTR3, config->frmctr3,
sizeof(config->frmctr3));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_INVCTR, &config->invctr, 1);
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_PWCTR1, config->pwctr1,
sizeof(config->pwctr1));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_PWCTR2, config->pwctr2,
sizeof(config->pwctr2));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_PWCTR3, config->pwctr3,
sizeof(config->pwctr3));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_PWCTR4, config->pwctr4,
sizeof(config->pwctr4));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_PWCTR5, config->pwctr5,
sizeof(config->pwctr5));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_VMCTR1, &config->vmctr1, 1);
if (ret < 0) {
return ret;
}
if (config->inversion_on) {
ret = st7735r_transmit(dev, ST7735R_CMD_INV_ON, NULL, 0);
} else {
ret = st7735r_transmit(dev, ST7735R_CMD_INV_OFF, NULL, 0);
}
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_MADCTL, &config->madctl, 1);
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_COLMOD, &config->colmod, 1);
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_CASET, config->caset,
sizeof(config->caset));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_RASET, config->raset,
sizeof(config->raset));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_GAMCTRP1, config->gamctrp1,
sizeof(config->gamctrp1));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_GAMCTRN1, config->gamctrn1,
sizeof(config->gamctrn1));
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_NORON, NULL, 0);
if (ret < 0) {
return ret;
}
ret = st7735r_transmit(dev, ST7735R_CMD_DISP_ON, NULL, 0);
if (ret < 0) {
return ret;
}
return 0;
}
static int st7735r_init(const struct device *dev)
{
const struct st7735r_config *config = dev->config;
int ret;
if (!device_is_ready(config->mipi_dev)) {
LOG_ERR("MIPI bus %s not ready", config->mipi_dev->name);
return -ENODEV;
}
ret = st7735r_reset_display(dev);
if (ret < 0) {
LOG_ERR("Couldn't reset display");
return ret;
}
ret = st7735r_exit_sleep(dev);
if (ret < 0) {
LOG_ERR("Couldn't exit sleep");
return ret;
}
ret = st7735r_lcd_init(dev);
if (ret < 0) {
LOG_ERR("Couldn't init LCD");
return ret;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int st7735r_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = st7735r_exit_sleep(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
ret = st7735r_transmit(dev, ST7735R_CMD_SLEEP_IN, NULL, 0);
break;
default:
ret = -ENOTSUP;
break;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static const struct display_driver_api st7735r_api = {
.blanking_on = st7735r_blanking_on,
.blanking_off = st7735r_blanking_off,
.write = st7735r_write,
.get_capabilities = st7735r_get_capabilities,
.set_pixel_format = st7735r_set_pixel_format,
.set_orientation = st7735r_set_orientation,
};
#define ST7735R_INIT(inst) \
const static struct st7735r_config st7735r_config_ ## inst = { \
.mipi_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.dbi_config = MIPI_DBI_CONFIG_DT_INST(inst, \
SPI_OP_MODE_MASTER | \
((DT_INST_PROP(inst, mipi_mode) == \
MIPI_DBI_MODE_SPI_4WIRE) ? SPI_WORD_SET(8) : \
SPI_WORD_SET(9)) | \
SPI_HOLD_ON_CS | SPI_LOCK_ON, 0), \
.width = DT_INST_PROP(inst, width), \
.height = DT_INST_PROP(inst, height), \
.madctl = DT_INST_PROP(inst, madctl), \
.colmod = DT_INST_PROP(inst, colmod), \
.caset = DT_INST_PROP(inst, caset), \
.raset = DT_INST_PROP(inst, raset), \
.vmctr1 = DT_INST_PROP(inst, vmctr1), \
.invctr = DT_INST_PROP(inst, invctr), \
.pwctr1 = DT_INST_PROP(inst, pwctr1), \
.pwctr2 = DT_INST_PROP(inst, pwctr2), \
.pwctr3 = DT_INST_PROP(inst, pwctr3), \
.pwctr4 = DT_INST_PROP(inst, pwctr4), \
.pwctr5 = DT_INST_PROP(inst, pwctr5), \
.frmctr1 = DT_INST_PROP(inst, frmctr1), \
.frmctr2 = DT_INST_PROP(inst, frmctr2), \
.frmctr3 = DT_INST_PROP(inst, frmctr3), \
.gamctrp1 = DT_INST_PROP(inst, gamctrp1), \
.gamctrn1 = DT_INST_PROP(inst, gamctrn1), \
.inversion_on = DT_INST_PROP(inst, inversion_on), \
.rgb_is_inverted = DT_INST_PROP(inst, rgb_is_inverted), \
}; \
\
static struct st7735r_data st7735r_data_ ## inst = { \
.x_offset = DT_INST_PROP(inst, x_offset), \
.y_offset = DT_INST_PROP(inst, y_offset), \
}; \
\
PM_DEVICE_DT_INST_DEFINE(inst, st7735r_pm_action); \
\
DEVICE_DT_INST_DEFINE(inst, st7735r_init, PM_DEVICE_DT_INST_GET(inst), \
&st7735r_data_ ## inst, &st7735r_config_ ## inst, \
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \
&st7735r_api);
DT_INST_FOREACH_STATUS_OKAY(ST7735R_INIT)
``` | /content/code_sandbox/drivers/display/display_st7735r.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,254 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_dummy_dc
#include <errno.h>
#include <string.h>
#include <zephyr/drivers/display.h>
#include <zephyr/device.h>
struct dummy_display_config {
uint16_t height;
uint16_t width;
};
struct dummy_display_data {
enum display_pixel_format current_pixel_format;
};
static int dummy_display_init(const struct device *dev)
{
struct dummy_display_data *disp_data = dev->data;
disp_data->current_pixel_format = PIXEL_FORMAT_ARGB_8888;
return 0;
}
static int dummy_display_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct dummy_display_config *config = dev->config;
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT(desc->pitch <= config->width,
"Pitch in descriptor is larger than screen size");
__ASSERT(desc->height <= config->height,
"Height in descriptor is larger than screen size");
__ASSERT(x + desc->pitch <= config->width,
"Writing outside screen boundaries in horizontal direction");
__ASSERT(y + desc->height <= config->height,
"Writing outside screen boundaries in vertical direction");
if (desc->width > desc->pitch ||
x + desc->pitch > config->width ||
y + desc->height > config->height) {
return -EINVAL;
}
return 0;
}
static int dummy_display_blanking_off(const struct device *dev)
{
return 0;
}
static int dummy_display_blanking_on(const struct device *dev)
{
return 0;
}
static int dummy_display_set_brightness(const struct device *dev,
const uint8_t brightness)
{
return 0;
}
static int dummy_display_set_contrast(const struct device *dev,
const uint8_t contrast)
{
return 0;
}
static void dummy_display_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct dummy_display_config *config = dev->config;
struct dummy_display_data *disp_data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->width;
capabilities->y_resolution = config->height;
capabilities->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888 |
PIXEL_FORMAT_RGB_888 |
PIXEL_FORMAT_MONO01 |
PIXEL_FORMAT_MONO10;
capabilities->current_pixel_format = disp_data->current_pixel_format;
capabilities->screen_info = SCREEN_INFO_MONO_VTILED |
SCREEN_INFO_MONO_MSB_FIRST;
}
static int dummy_display_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct dummy_display_data *disp_data = dev->data;
disp_data->current_pixel_format = pixel_format;
return 0;
}
static const struct display_driver_api dummy_display_api = {
.blanking_on = dummy_display_blanking_on,
.blanking_off = dummy_display_blanking_off,
.write = dummy_display_write,
.set_brightness = dummy_display_set_brightness,
.set_contrast = dummy_display_set_contrast,
.get_capabilities = dummy_display_get_capabilities,
.set_pixel_format = dummy_display_set_pixel_format,
};
#define DISPLAY_DUMMY_DEFINE(n) \
static const struct dummy_display_config dd_config_##n = { \
.height = DT_INST_PROP(n, height), \
.width = DT_INST_PROP(n, width), \
}; \
\
static struct dummy_display_data dd_data_##n; \
\
DEVICE_DT_INST_DEFINE(n, &dummy_display_init, NULL, \
&dd_data_##n, \
&dd_config_##n, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&dummy_display_api); \
DT_INST_FOREACH_STATUS_OKAY(DISPLAY_DUMMY_DEFINE)
``` | /content/code_sandbox/drivers/display/display_dummy.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 856 |
```unknown
# ST7735R display driver configuration options
config ST7735R
bool "ST7735R/ST7735S display driver"
default y
depends on DT_HAS_SITRONIX_ST7735R_ENABLED
select MIPI_DBI
help
Enable driver for ST7735R/ST7735S display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.st7735r | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
/*
* This tool uses display controller driver API and requires
* a suitable LED matrix controller driver.
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <string.h>
#include <zephyr/sys/printk.h>
#include <zephyr/display/mb_display.h>
#include <zephyr/drivers/display.h>
#include "mb_font.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mb_disp, CONFIG_DISPLAY_LOG_LEVEL);
#define MODE_MASK BIT_MASK(16)
#define SCROLL_OFF 0
#define SCROLL_START 1
#define SCROLL_DEFAULT_DURATION_MS 80
#define MB_DISP_XRES 5
#define MB_DISP_YRES 5
struct mb_display {
const struct device *lm_dev; /* LED matrix display device */
struct k_work_delayable dwork; /* Delayable work item */
uint8_t img_count; /* Image count */
uint8_t cur_img; /* Current image or character to show */
uint8_t scroll:3, /* Scroll shift */
first:1, /* First frame of a scroll sequence */
loop:1, /* Loop to beginning */
text:1, /* We're showing a string (not image) */
img_sep:1, /* One column image separation */
msb:1; /* MSB represents the first pixel */
int32_t duration; /* Duration for each shown image */
union {
const struct mb_image *img; /* Array of images to show */
const char *str; /* String to be shown */
};
/* Buffer for printed strings */
char str_buf[CONFIG_MICROBIT_DISPLAY_STR_MAX];
};
static inline const struct mb_image *get_font(char ch)
{
if (ch < MB_FONT_START || ch > MB_FONT_END) {
return &mb_font[' ' - MB_FONT_START];
}
return &mb_font[ch - MB_FONT_START];
}
static ALWAYS_INLINE uint8_t flip_pixels(uint8_t b)
{
b = (b & 0xf0) >> 4 | (b & 0x0f) << 4;
b = (b & 0xcc) >> 2 | (b & 0x33) << 2;
b = (b & 0xaa) >> 1 | (b & 0x55) << 1;
return b;
}
static int update_content(struct mb_display *disp, const struct mb_image *img)
{
const struct display_buffer_descriptor buf_desc = {
.buf_size = sizeof(struct mb_image),
.width = MB_DISP_XRES,
.height = MB_DISP_YRES,
.pitch = 8,
};
struct mb_image tmp_img;
int ret;
if (disp->msb) {
for (int i = 0; i < sizeof(struct mb_image); i++) {
tmp_img.row[i] = flip_pixels(img->row[i]);
}
ret = display_write(disp->lm_dev, 0, 0, &buf_desc, &tmp_img);
} else {
ret = display_write(disp->lm_dev, 0, 0, &buf_desc, img);
}
if (ret < 0) {
LOG_ERR("Write to display controller failed");
return ret;
}
LOG_DBG("Image duration %d", disp->duration);
if (disp->duration != SYS_FOREVER_MS) {
k_work_reschedule(&disp->dwork, K_MSEC(disp->duration));
}
return ret;
}
static int start_image(struct mb_display *disp, const struct mb_image *img)
{
int ret;
ret = display_blanking_off(disp->lm_dev);
if (ret < 0) {
LOG_ERR("Set blanking off failed");
return ret;
}
return update_content(disp, img);
}
static int reset_display(struct mb_display *disp)
{
int ret;
disp->str = NULL;
disp->cur_img = 0U;
disp->img = NULL;
disp->img_count = 0U;
disp->scroll = SCROLL_OFF;
ret = display_blanking_on(disp->lm_dev);
if (ret < 0) {
LOG_ERR("Set blanking on failed");
}
return ret;
}
static const struct mb_image *current_img(struct mb_display *disp)
{
if (disp->scroll && disp->first) {
return get_font(' ');
}
if (disp->text) {
return get_font(disp->str[disp->cur_img]);
} else {
return &disp->img[disp->cur_img];
}
}
static const struct mb_image *next_img(struct mb_display *disp)
{
if (disp->text) {
if (disp->first) {
return get_font(disp->str[0]);
} else if (disp->str[disp->cur_img]) {
return get_font(disp->str[disp->cur_img + 1]);
} else {
return get_font(' ');
}
} else {
if (disp->first) {
return &disp->img[0];
} else if (disp->cur_img < (disp->img_count - 1)) {
return &disp->img[disp->cur_img + 1];
} else {
return get_font(' ');
}
}
}
static inline bool last_frame(struct mb_display *disp)
{
if (disp->text) {
return (disp->str[disp->cur_img] == '\0');
} else {
return (disp->cur_img >= disp->img_count);
}
}
static inline uint8_t scroll_steps(struct mb_display *disp)
{
return MB_DISP_XRES + disp->img_sep;
}
static int update_scroll(struct mb_display *disp)
{
if (disp->scroll < scroll_steps(disp)) {
struct mb_image img;
for (int i = 0; i < MB_DISP_XRES; i++) {
const struct mb_image *i1 = current_img(disp);
const struct mb_image *i2 = next_img(disp);
img.row[i] = ((i1->row[i] >> disp->scroll) |
(i2->row[i] << (scroll_steps(disp) -
disp->scroll)));
}
disp->scroll++;
return update_content(disp, &img);
} else {
if (disp->first) {
disp->first = 0U;
} else {
disp->cur_img++;
}
if (last_frame(disp)) {
if (!disp->loop) {
return reset_display(disp);
}
disp->cur_img = 0U;
disp->first = 1U;
}
disp->scroll = SCROLL_START;
return update_content(disp, current_img(disp));
}
}
static int update_image(struct mb_display *disp)
{
disp->cur_img++;
if (last_frame(disp)) {
if (!disp->loop) {
return reset_display(disp);
}
disp->cur_img = 0U;
}
return update_content(disp, current_img(disp));
}
static void update_display_work(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct mb_display *disp = CONTAINER_OF(dwork, struct mb_display, dwork);
int ret;
if (disp->scroll) {
ret = update_scroll(disp);
} else {
ret = update_image(disp);
}
__ASSERT(ret == 0, "Failed to update display");
}
static int start_scroll(struct mb_display *disp, int32_t duration)
{
/* Divide total duration by number of scrolling steps */
if (duration) {
disp->duration = duration / scroll_steps(disp);
} else {
disp->duration = SCROLL_DEFAULT_DURATION_MS;
}
disp->scroll = SCROLL_START;
disp->first = 1U;
disp->cur_img = 0U;
return start_image(disp, get_font(' '));
}
static int start_single(struct mb_display *disp, int32_t duration)
{
disp->duration = duration;
if (disp->text) {
return start_image(disp, get_font(disp->str[0]));
} else {
return start_image(disp, disp->img);
}
}
void mb_display_stop(struct mb_display *disp)
{
struct k_work_sync sync;
int ret;
k_work_cancel_delayable_sync(&disp->dwork, &sync);
LOG_DBG("delayable work stopped %p", disp);
ret = reset_display(disp);
__ASSERT(ret == 0, "Failed to reset display");
}
void mb_display_image(struct mb_display *disp, uint32_t mode, int32_t duration,
const struct mb_image *img, uint8_t img_count)
{
int ret;
mb_display_stop(disp);
__ASSERT(img && img_count > 0, "Invalid parameters");
disp->text = 0U;
disp->img_count = img_count;
disp->img = img;
disp->img_sep = 0U;
disp->cur_img = 0U;
disp->loop = !!(mode & MB_DISPLAY_FLAG_LOOP);
switch (mode & MODE_MASK) {
case MB_DISPLAY_MODE_DEFAULT:
case MB_DISPLAY_MODE_SINGLE:
ret = start_single(disp, duration);
__ASSERT(ret == 0, "Failed to start single mode");
break;
case MB_DISPLAY_MODE_SCROLL:
ret = start_scroll(disp, duration);
__ASSERT(ret == 0, "Failed to start scroll mode");
break;
default:
__ASSERT(0, "Invalid display mode");
}
}
void mb_display_print(struct mb_display *disp, uint32_t mode,
int32_t duration, const char *fmt, ...)
{
va_list ap;
int ret;
mb_display_stop(disp);
va_start(ap, fmt);
vsnprintk(disp->str_buf, sizeof(disp->str_buf), fmt, ap);
va_end(ap);
if (disp->str_buf[0] == '\0') {
return;
}
disp->str = disp->str_buf;
disp->text = 1U;
disp->img_sep = 1U;
disp->cur_img = 0U;
disp->loop = !!(mode & MB_DISPLAY_FLAG_LOOP);
switch (mode & MODE_MASK) {
case MB_DISPLAY_MODE_DEFAULT:
case MB_DISPLAY_MODE_SCROLL:
ret = start_scroll(disp, duration);
__ASSERT(ret == 0, "Failed to start scroll mode");
break;
case MB_DISPLAY_MODE_SINGLE:
ret = start_single(disp, duration);
__ASSERT(ret == 0, "Failed to start single mode");
break;
default:
__ASSERT(0, "Invalid display mode");
}
}
static int mb_display_init(struct mb_display *disp)
{
struct display_capabilities caps;
int ret;
display_get_capabilities(disp->lm_dev, &caps);
if (caps.x_resolution != MB_DISP_XRES ||
caps.y_resolution != MB_DISP_YRES) {
LOG_ERR("Not supported display resolution");
return -ENOTSUP;
}
if (caps.screen_info & SCREEN_INFO_MONO_MSB_FIRST) {
disp->msb = 1U;
}
ret = display_set_brightness(disp->lm_dev, 0xFF);
if (ret < 0) {
LOG_ERR("Failed to set brightness");
return ret;
}
k_work_init_delayable(&disp->dwork, update_display_work);
return 0;
}
static struct mb_display display;
struct mb_display *mb_display_get(void)
{
return &display;
}
static int mb_display_init_on_boot(void)
{
display.lm_dev = DEVICE_DT_GET_ONE(nordic_nrf_led_matrix);
if (!device_is_ready(display.lm_dev)) {
LOG_ERR("Display controller device not ready");
return -ENODEV;
}
return mb_display_init(&display);
}
SYS_INIT(mb_display_init_on_boot, APPLICATION, CONFIG_DISPLAY_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/display/mb_display.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,603 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_
#include <zephyr/device.h>
/* Commands/registers. */
#define ILI9488_FRMCTR1 0xB1
#define ILI9488_DISCTRL 0xB6
#define ILI9488_PWCTRL1 0xC0
#define ILI9488_PWCTRL2 0xC1
#define ILI9488_VMCTRL 0xC5
#define ILI9488_PGAMCTRL 0xE0
#define ILI9488_NGAMCTRL 0xE1
/* Commands/registers length. */
#define ILI9488_FRMCTR1_LEN 2U
#define ILI9488_DISCTRL_LEN 3U
#define ILI9488_PWCTRL1_LEN 2U
#define ILI9488_PWCTRL2_LEN 1U
#define ILI9488_VMCTRL_LEN 4U
#define ILI9488_PGAMCTRL_LEN 15U
#define ILI9488_NGAMCTRL_LEN 15U
/** X resolution (pixels). */
#define ILI9488_X_RES 320U
/** Y resolution (pixels). */
#define ILI9488_Y_RES 480U
/** ILI9488 registers to be initialized. */
struct ili9488_regs {
uint8_t frmctr1[ILI9488_FRMCTR1_LEN];
uint8_t disctrl[ILI9488_DISCTRL_LEN];
uint8_t pwctrl1[ILI9488_PWCTRL1_LEN];
uint8_t pwctrl2[ILI9488_PWCTRL2_LEN];
uint8_t vmctrl[ILI9488_VMCTRL_LEN];
uint8_t pgamctrl[ILI9488_PGAMCTRL_LEN];
uint8_t ngamctrl[ILI9488_NGAMCTRL_LEN];
};
/* Initializer macro for ILI9488 registers. */
#define ILI9488_REGS_INIT(n) \
static const struct ili9488_regs ili9xxx_regs_##n = { \
.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \
.disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \
.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \
.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl2), \
.vmctrl = DT_PROP(DT_INST(n, ilitek_ili9488), vmctrl), \
.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), pgamctrl), \
.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), ngamctrl), \
}
/**
* @brief Initialize ILI9488 registers with DT values.
*
* @param dev ILI9488 device instance
* @return 0 on success, errno otherwise.
*/
int ili9488_regs_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9488_H_ */
``` | /content/code_sandbox/drivers/display/display_ili9488.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 691 |
```objective-c
/*
*
*/
#ifndef _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_
#define _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_
#define ST7796S_CMD_SLPIN 0x10 /* Sleep in */
#define ST7796S_CMD_SLPOUT 0x11 /* Sleep out */
#define ST7796S_CMD_INVOFF 0x20 /* Display inversion off */
#define ST7796S_CMD_INVON 0x21 /* Display inversion on */
#define ST7796S_CMD_CASET 0x2A /* Column address set */
#define ST7796S_CMD_RASET 0x2B /* Row address set */
#define ST7796S_CMD_RAMWR 0x2C /* Memory write */
#define ST7796S_CMD_DISPOFF 0x28 /* Display off */
#define ST7796S_CMD_DISPON 0x29 /* Display on */
#define ST7796S_CMD_MADCTL 0x36 /* Memory data access control */
#define ST7796S_CMD_COLMOD 0x3A /* Interface pixel format */
#define ST7796S_CMD_FRMCTR1 0xB1 /* Frame rate control 1 (normal mode) */
#define ST7796S_CMD_FRMCTR2 0xB2 /* Frame rate control 2 (idle mode) */
#define ST7796S_CMD_FRMCTR3 0xB3 /* Frame rate control 3 (partial mode) */
#define ST7796S_CMD_DIC 0xB4 /* Display inversion control */
#define ST7796S_CMD_BPC 0xB5 /* Blanking porch control */
#define ST7796S_CMD_DFC 0xB6 /* Display function control */
#define ST7796S_CMD_PWR1 0xC0 /* Power control 1 */
#define ST7796S_CMD_PWR2 0xC1 /* Power control 1 */
#define ST7796S_CMD_PWR3 0xC2 /* Power control 1 */
#define ST7796S_CMD_VCMPCTL 0xC5 /* VCOM control */
#define ST7796S_CMD_PGC 0xE0 /* Positive gamma control */
#define ST7796S_CMD_NGC 0xE1 /* Negative gamma control */
#define ST7796S_CMD_DOCA 0xE8 /* Display output control adjust */
#define ST7796S_CMD_CSCON 0xF0 /* Command set control */
#define ST7796S_CONTROL_16BIT 0x5 /* Sets control interface to 16 bit mode */
#define ST7796S_MADCTL_BGR BIT(3) /* Sets BGR color mode */
#endif /* _ZEPHYR_DRIVERS_DISPLAY_ST7796S_H_ */
``` | /content/code_sandbox/drivers/display/display_st7796s.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 560 |
```unknown
config MAX7219
bool "MAX7219 LED display driver"
default y
depends on DT_HAS_MAXIM_MAX7219_ENABLED
select SPI
help
Enable driver for the Maxim MAX7219 SPI LED display driver.
It is supporting up to 64 individual LEDs per MAX7219.
``` | /content/code_sandbox/drivers/display/Kconfig.max7219 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
menuconfig DISPLAY_MCUX_DCNANO_LCDIF
bool "MCUX DCNano LCDIF driver"
default y
depends on DT_HAS_NXP_DCNANO_LCDIF_ENABLED
help
Enable support for mcux DCNano LCDIF driver.
if DISPLAY_MCUX_DCNANO_LCDIF
config MCUX_DCNANO_LCDIF_FB_NUM
int "Framebuffers to allocate in driver"
default 1
range 0 2
help
Number of framebuffers to allocate in DCNANO driver. Driver allocated
framebuffers are required to support partial display updates.
The driver has been validated to support 0 through 2 framebuffers.
Note that hardware will likely perform best if zero driver
framebuffers are allocated by the driver, and the application
implements double framebuffering by always calling display_write with
a buffer equal in size to the connected panel.
config MCUX_DCNANO_LCDIF_MAINTAIN_CACHE
bool "Maintain cache coherency"
default y
help
Maintain cache coherency for LCDIF framebuffer. This is generally
required, unless an external framebuffer is utilized with custom
caching settings, or caching is disabled.
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
bool "Use external memory for framebuffer"
imply MEMC
help
Use external memory for framebuffer. Configures the LCDIF to write
framebuffer data to a memory mapped external device.
Note that no specific linker section is used for this framebuffer, so
if the application uses the external memory for other purposes, care
should be taken to ensure that the memory allocated for the LCDIF
does not overlap with other data. Each allocated LCDIF buffer will
utilize (lcd_width * lcd_height * bytes_per_pixel) bytes of data,
and buffers will be allocated contiguously.
if MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
hex "LCDIF framebuffer address"
help
Address of memory mapped external framebuffer.
Must be 128 byte aligned
endif # MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
endif # DISPLAY_MCUX_ELCDIF
``` | /content/code_sandbox/drivers/display/Kconfig.mcux_dcnano_lcdif | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 460 |
```c
/*
*
*/
#include "display_ili9340.h"
#include "display_ili9xxx.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_ili9340, CONFIG_DISPLAY_LOG_LEVEL);
int ili9340_regs_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
const struct ili9340_regs *regs = config->regs;
int r;
LOG_HEXDUMP_DBG(regs->gamset, ILI9340_GAMSET_LEN, "GAMSET");
r = ili9xxx_transmit(dev, ILI9340_GAMSET, regs->gamset,
ILI9340_GAMSET_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->frmctr1, ILI9340_FRMCTR1_LEN, "FRMCTR1");
r = ili9xxx_transmit(dev, ILI9340_FRMCTR1, regs->frmctr1,
ILI9340_FRMCTR1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->disctrl, ILI9340_DISCTRL_LEN, "DISCTRL");
r = ili9xxx_transmit(dev, ILI9340_DISCTRL, regs->disctrl,
ILI9340_DISCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9340_PWCTRL1_LEN, "PWCTRL1");
r = ili9xxx_transmit(dev, ILI9340_PWCTRL1, regs->pwctrl1,
ILI9340_PWCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9340_PWCTRL2_LEN, "PWCTRL2");
r = ili9xxx_transmit(dev, ILI9340_PWCTRL2, regs->pwctrl2,
ILI9340_PWCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl1, ILI9340_VMCTRL1_LEN, "VMCTRL1");
r = ili9xxx_transmit(dev, ILI9340_VMCTRL1, regs->vmctrl1,
ILI9340_VMCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl2, ILI9340_VMCTRL2_LEN, "VMCTRL2");
r = ili9xxx_transmit(dev, ILI9340_VMCTRL2, regs->vmctrl2,
ILI9340_VMCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9340_PGAMCTRL_LEN, "PGAMCTRL");
r = ili9xxx_transmit(dev, ILI9340_PGAMCTRL, regs->pgamctrl,
ILI9340_PGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9340_NGAMCTRL_LEN, "NGAMCTRL");
r = ili9xxx_transmit(dev, ILI9340_NGAMCTRL, regs->ngamctrl,
ILI9340_NGAMCTRL_LEN);
if (r < 0) {
return r;
}
return 0;
}
``` | /content/code_sandbox/drivers/display/display_ili9340.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 748 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_
#define ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_
/* UC8176/UC8179 */
#define UC81XX_CMD_PSR 0x00
#define UC81XX_CMD_PWR 0x01
#define UC81XX_CMD_POF 0x02
#define UC81XX_CMD_PFS 0x03
#define UC81XX_CMD_PON 0x04
#define UC81XX_CMD_PMES 0x05
#define UC81XX_CMD_BTST 0x06
#define UC81XX_CMD_DSLP 0x07
#define UC81XX_CMD_DTM1 0x10
#define UC81XX_CMD_DSP 0x11
#define UC81XX_CMD_DRF 0x12
/* UC8179 only */
#define UC81XX_CMD_DTM2 0x13
#define UC81XX_CMD_DUSPI 0x15
#define UC81XX_CMD_AUTO 0x17
#define UC81XX_CMD_LUTOPT 0x2A
#define UC81XX_CMD_KWOPT 0x2B
#define UC81XX_CMD_LUTC 0x20
#define UC81XX_CMD_LUTWW 0x21
#define UC81XX_CMD_LUTKW 0x22
#define UC81XX_CMD_LUTWK 0x23
#define UC81XX_CMD_LUTKK 0x24
#define UC81XX_CMD_LUTBD 0x25
/* UC8176/UC8179 */
#define UC81XX_CMD_PLL 0x30
#define UC81XX_CMD_TSC 0x40
#define UC81XX_CMD_TSE 0x41
#define UC81XX_CMD_TSW 0x42
#define UC81XX_CMD_TSR 0x43
/* UC8179 */
#define UC81XX_CMD_PBC 0x44
/* UC8176/UC8179 - different register layouts */
#define UC81XX_CMD_CDI 0x50
/* UC8176/UC8179 */
#define UC81XX_CMD_LPD 0x51
/* UC8179 */
#define UC81XX_CMD_EVS 0x52
/* UC8176/UC8179 */
#define UC81XX_CMD_TCON 0x60
#define UC81XX_CMD_TRES 0x61
#define UC81XX_CMD_GSST 0x65
#define UC81XX_CMD_REV 0x70
#define UC81XX_CMD_FLG 0x71
#define UC81XX_CMD_AMV 0x80
#define UC81XX_CMD_VV 0x81
#define UC81XX_CMD_VDCS 0x82
#define UC81XX_CMD_PTL 0x90
#define UC81XX_CMD_PTIN 0x91
#define UC81XX_CMD_PTOUT 0x92
#define UC81XX_CMD_PGM 0xA0
#define UC81XX_CMD_APG 0xA1
#define UC81XX_CMD_ROTP 0xA2
#define UC81XX_CMD_CCSET 0xE0
#define UC81XX_CMD_PWS 0xE3
/* UC8179 */
#define UC81XX_CMD_LVSEL 0xE4
/* UC8176/UC8179 */
#define UC81XX_CMD_TSSET 0xE5
/* UC8179 */
#define UC81XX_CMD_TSBDRY 0xE7
#define UC81XX_PSR_REG BIT(5)
#define UC81XX_PSR_KW_R BIT(4)
#define UC81XX_PSR_UD BIT(3)
#define UC81XX_PSR_SHL BIT(2)
#define UC81XX_PSR_SHD BIT(1)
#define UC81XX_PSR_RST BIT(0)
#define UC81XX_AUTO_PON_DRF_POF 0xA5
#define UC81XX_AUTO_PON_DRF_POF_DSLP 0xA7
#define UC8176_CDI_VBD_MASK 0xc0
#define UC8176_CDI_VBD0 BIT(6)
#define UC8176_CDI_VBD1 BIT(7)
#define UC8176_CDI_DDX1 BIT(5)
#define UC8176_CDI_DDX0 BIT(4)
#define UC8176_CDI_CDI_MASK 0x0f
#define UC8179_CDI_REG_LENGTH 2U
#define UC8179_CDI_BDZ_DDX_IDX 0
#define UC8179_CDI_CDI_IDX 1
#define UC8179_CDI_BDZ BIT(7)
#define UC8179_CDI_BDV1 BIT(5)
#define UC8179_CDI_BDV0 BIT(4)
#define UC8179_CDI_N2OCP BIT(3)
#define UC8179_CDI_DDX1 BIT(1)
#define UC8179_CDI_DDX0 BIT(0)
struct uc81xx_tres8 {
uint8_t hres;
uint8_t vres;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_tres8) == 2);
struct uc81xx_ptl8 {
uint8_t hrst;
uint8_t hred;
uint8_t vrst;
uint8_t vred;
uint8_t flags;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_ptl8) == 5);
struct uc81xx_tres16 {
uint16_t hres;
uint16_t vres;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_tres16) == 4);
struct uc81xx_ptl16 {
uint16_t hrst;
uint16_t hred;
uint16_t vrst;
uint16_t vred;
uint8_t flags;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_ptl16) == 9);
#define UC81XX_PTL_FLAG_PT_SCAN BIT(0)
/* Time constants in ms */
#define UC81XX_RESET_DELAY 10U
#define UC81XX_PON_DELAY 100U
#define UC81XX_BUSY_DELAY 1U
#endif /* ZEPHYR_DRIVERS_DISPLAY_UC81XX_REGS_H_ */
``` | /content/code_sandbox/drivers/display/uc81xx_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,366 |
```objective-c
/*
*
*
* "Bottom" of the SDL display driver.
* When built with the native_simulator this will be built in the runner context,
* that is, with the host C library, and with the host include paths.
*/
#ifndef DRIVERS_DISPLAY_DISPLAY_SDL_BOTTOM_H
#define DRIVERS_DISPLAY_DISPLAY_SDL_BOTTOM_H
#include <stdbool.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Note: None of these functions are public interfaces. But internal to the SDL display driver */
int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct,
bool use_accelerator, void **window, void **renderer, void **mutex,
void **texture, void **read_texture);
void sdl_display_write_bottom(const uint16_t height, const uint16_t width,
const uint16_t x, const uint16_t y,
void *renderer, void *mutex, void *texture,
uint8_t *buf, bool display_on);
int sdl_display_read_bottom(const uint16_t height, const uint16_t width,
const uint16_t x, const uint16_t y,
void *renderer, void *buf, uint16_t pitch,
void *mutex, void *texture, void **read_texture);
void sdl_display_blanking_off_bottom(void *renderer, void *texture);
void sdl_display_blanking_on_bottom(void *renderer);
void sdl_display_cleanup_bottom(void **window, void **renderer, void **mutex, void **texture,
void **read_texture);
#ifdef __cplusplus
}
#endif
#endif /* DRIVERS_DISPLAY_DISPLAY_SDL_BOTTOM_H */
``` | /content/code_sandbox/drivers/display/display_sdl_bottom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 341 |
```c
/*
*
*/
#define DT_DRV_COMPAT sharp_ls0xx
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ls0xx, CONFIG_DISPLAY_LOG_LEVEL);
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/display.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
/* Supports LS012B7DD01, LS012B7DD06, LS013B7DH03, LS013B7DH05
* LS013B7DH06, LS027B7DH01A, LS032B7DD02, LS044Q7DH01
*/
/* Note:
* -> high/1 means white, low/0 means black
* -> Display expects LSB first
*/
#define LS0XX_PANEL_WIDTH DT_INST_PROP(0, width)
#define LS0XX_PANEL_HEIGHT DT_INST_PROP(0, height)
#define LS0XX_PIXELS_PER_BYTE 8U
/* Adding 2 for the line number and dummy byte
* line_buf format for each row.
* +-------------------+-------------------+----------------+
* | line num (8 bits) | data (WIDTH bits) | dummy (8 bits) |
* +-------------------+-------------------+----------------+
*/
#define LS0XX_BYTES_PER_LINE ((LS0XX_PANEL_WIDTH / LS0XX_PIXELS_PER_BYTE) + 2)
#define LS0XX_BIT_WRITECMD 0x01
#define LS0XX_BIT_VCOM 0x02
#define LS0XX_BIT_CLEAR 0x04
struct ls0xx_config {
struct spi_dt_spec bus;
#if DT_INST_NODE_HAS_PROP(0, disp_en_gpios)
struct gpio_dt_spec disp_en_gpio;
#endif
#if DT_INST_NODE_HAS_PROP(0, extcomin_gpios)
struct gpio_dt_spec extcomin_gpio;
#endif
};
#if DT_INST_NODE_HAS_PROP(0, extcomin_gpios)
/* Driver will handle VCOM toggling */
static void ls0xx_vcom_toggle(void *a, void *b, void *c)
{
const struct ls0xx_config *config = a;
while (1) {
gpio_pin_toggle_dt(&config->extcomin_gpio);
k_usleep(3);
gpio_pin_toggle_dt(&config->extcomin_gpio);
k_msleep(1000 / DT_INST_PROP(0, extcomin_frequency));
}
}
K_THREAD_STACK_DEFINE(vcom_toggle_stack, 256);
struct k_thread vcom_toggle_thread;
#endif
static int ls0xx_blanking_off(const struct device *dev)
{
#if DT_INST_NODE_HAS_PROP(0, disp_en_gpios)
const struct ls0xx_config *config = dev->config;
return gpio_pin_set_dt(&config->disp_en_gpio, 1);
#else
LOG_WRN("Unsupported");
return -ENOTSUP;
#endif
}
static int ls0xx_blanking_on(const struct device *dev)
{
#if DT_INST_NODE_HAS_PROP(0, disp_en_gpios)
const struct ls0xx_config *config = dev->config;
return gpio_pin_set_dt(&config->disp_en_gpio, 0);
#else
LOG_WRN("Unsupported");
return -ENOTSUP;
#endif
}
static int ls0xx_cmd(const struct device *dev, uint8_t *buf, uint8_t len)
{
const struct ls0xx_config *config = dev->config;
struct spi_buf cmd_buf = { .buf = buf, .len = len };
struct spi_buf_set buf_set = { .buffers = &cmd_buf, .count = 1 };
return spi_write_dt(&config->bus, &buf_set);
}
static int ls0xx_clear(const struct device *dev)
{
const struct ls0xx_config *config = dev->config;
uint8_t clear_cmd[2] = { LS0XX_BIT_CLEAR, 0 };
int err;
err = ls0xx_cmd(dev, clear_cmd, sizeof(clear_cmd));
spi_release_dt(&config->bus);
return err;
}
static int ls0xx_update_display(const struct device *dev,
uint16_t start_line,
uint16_t num_lines,
const uint8_t *data)
{
const struct ls0xx_config *config = dev->config;
uint8_t write_cmd[1] = { LS0XX_BIT_WRITECMD };
uint8_t ln = start_line;
uint8_t dummy = 27;
struct spi_buf line_buf[3] = {
{
.len = sizeof(ln),
.buf = &ln,
},
{
.len = LS0XX_BYTES_PER_LINE - 2,
},
{
.len = sizeof(dummy),
.buf = &dummy,
},
};
struct spi_buf_set line_set = {
.buffers = line_buf,
.count = ARRAY_SIZE(line_buf),
};
int err;
LOG_DBG("Lines %d to %d", start_line, start_line + num_lines - 1);
err = ls0xx_cmd(dev, write_cmd, sizeof(write_cmd));
/* Send each line to the screen including
* the line number and dummy bits
*/
for (; ln <= start_line + num_lines - 1; ln++) {
line_buf[1].buf = (uint8_t *)data;
err |= spi_write_dt(&config->bus, &line_set);
data += LS0XX_PANEL_WIDTH / LS0XX_PIXELS_PER_BYTE;
}
/* Send another trailing 8 bits for the last line
* These can be any bits, it does not matter
* just reusing the write_cmd buffer
*/
err |= ls0xx_cmd(dev, write_cmd, sizeof(write_cmd));
spi_release_dt(&config->bus);
return err;
}
/* Buffer width should be equal to display width */
static int ls0xx_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
LOG_DBG("X: %d, Y: %d, W: %d, H: %d", x, y, desc->width, desc->height);
if (buf == NULL) {
LOG_WRN("Display buffer is not available");
return -EINVAL;
}
if (desc->width != LS0XX_PANEL_WIDTH) {
LOG_ERR("Width not a multiple of %d", LS0XX_PANEL_WIDTH);
return -EINVAL;
}
if (desc->pitch != desc->width) {
LOG_ERR("Unsupported mode");
return -ENOTSUP;
}
if ((y + desc->height) > LS0XX_PANEL_HEIGHT) {
LOG_ERR("Buffer out of bounds (height)");
return -EINVAL;
}
if (x != 0) {
LOG_ERR("X-coordinate has to be 0");
return -EINVAL;
}
/* Adding 1 since line numbering on the display starts with 1 */
return ls0xx_update_display(dev, y + 1, desc->height, buf);
}
static void ls0xx_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = LS0XX_PANEL_WIDTH;
caps->y_resolution = LS0XX_PANEL_HEIGHT;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO01;
caps->current_pixel_format = PIXEL_FORMAT_MONO01;
caps->screen_info = SCREEN_INFO_X_ALIGNMENT_WIDTH;
}
static int ls0xx_set_pixel_format(const struct device *dev,
const enum display_pixel_format pf)
{
if (pf == PIXEL_FORMAT_MONO01) {
return 0;
}
LOG_ERR("not supported");
return -ENOTSUP;
}
static int ls0xx_init(const struct device *dev)
{
const struct ls0xx_config *config = dev->config;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
#if DT_INST_NODE_HAS_PROP(0, disp_en_gpios)
if (!gpio_is_ready_dt(&config->disp_en_gpio)) {
LOG_ERR("DISP port device not ready");
return -ENODEV;
}
LOG_INF("Configuring DISP pin to OUTPUT_HIGH");
gpio_pin_configure_dt(&config->disp_en_gpio, GPIO_OUTPUT_HIGH);
#endif
#if DT_INST_NODE_HAS_PROP(0, extcomin_gpios)
if (!gpio_is_ready_dt(&config->extcomin_gpio)) {
LOG_ERR("EXTCOMIN port device not ready");
return -ENODEV;
}
LOG_INF("Configuring EXTCOMIN pin");
gpio_pin_configure_dt(&config->extcomin_gpio, GPIO_OUTPUT_LOW);
/* Start thread for toggling VCOM */
k_tid_t vcom_toggle_tid = k_thread_create(&vcom_toggle_thread,
vcom_toggle_stack,
K_THREAD_STACK_SIZEOF(vcom_toggle_stack),
ls0xx_vcom_toggle,
(void *)config, NULL, NULL,
3, 0, K_NO_WAIT);
k_thread_name_set(vcom_toggle_tid, "ls0xx_vcom");
#endif /* DT_INST_NODE_HAS_PROP(0, extcomin_gpios) */
/* Clear display else it shows random data */
return ls0xx_clear(dev);
}
static const struct ls0xx_config ls0xx_config = {
.bus = SPI_DT_SPEC_INST_GET(
0, SPI_OP_MODE_MASTER | SPI_WORD_SET(8) |
SPI_TRANSFER_LSB | SPI_CS_ACTIVE_HIGH |
SPI_HOLD_ON_CS | SPI_LOCK_ON, 0),
#if DT_INST_NODE_HAS_PROP(0, disp_en_gpios)
.disp_en_gpio = GPIO_DT_SPEC_INST_GET(0, disp_en_gpios),
#endif
#if DT_INST_NODE_HAS_PROP(0, extcomin_gpios)
.extcomin_gpio = GPIO_DT_SPEC_INST_GET(0, extcomin_gpios),
#endif
};
static const struct display_driver_api ls0xx_driver_api = {
.blanking_on = ls0xx_blanking_on,
.blanking_off = ls0xx_blanking_off,
.write = ls0xx_write,
.get_capabilities = ls0xx_get_capabilities,
.set_pixel_format = ls0xx_set_pixel_format,
};
DEVICE_DT_INST_DEFINE(0, ls0xx_init, NULL, NULL, &ls0xx_config, POST_KERNEL,
CONFIG_DISPLAY_INIT_PRIORITY, &ls0xx_driver_api);
``` | /content/code_sandbox/drivers/display/ls0xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,245 |
```c
/**
*/
#define DT_DRV_COMPAT galaxycore_gc9x01x
#include "display_gc9x01x.h"
#include <zephyr/dt-bindings/display/panel.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_gc9x01x, CONFIG_DISPLAY_LOG_LEVEL);
/* Maximum number of default init registers */
#define GC9X01X_NUM_DEFAULT_INIT_REGS 12U
/* Display data struct */
struct gc9x01x_data {
uint8_t bytes_per_pixel;
enum display_pixel_format pixel_format;
enum display_orientation orientation;
};
/* Configuration data struct.*/
struct gc9x01x_config {
const struct device *mipi_dev;
struct mipi_dbi_config dbi_config;
uint8_t pixel_format;
uint16_t orientation;
uint16_t x_resolution;
uint16_t y_resolution;
bool inversion;
const void *regs;
};
/* Initialization command data struct */
struct gc9x01x_default_init_regs {
uint8_t cmd;
uint8_t len;
uint8_t data[GC9X01X_NUM_DEFAULT_INIT_REGS];
};
/*
* Default initialization commands. There are a lot of undocumented commands
* within the manufacturer sample code, that are essential for proper operation of
* the display controller
*/
static const struct gc9x01x_default_init_regs default_init_regs[] = {
{
.cmd = 0xEBU,
.len = 1U,
.data = {0x14U},
},
{
.cmd = 0x84U,
.len = 1U,
.data = {0x40U},
},
{
.cmd = 0x85U,
.len = 1U,
.data = {0xFFU},
},
{
.cmd = 0x86U,
.len = 1U,
.data = {0xFFU},
},
{
.cmd = 0x87U,
.len = 1U,
.data = {0xFFU},
},
{
.cmd = 0x88U,
.len = 1U,
.data = {0x0AU},
},
{
.cmd = 0x89U,
.len = 1U,
.data = {0x21U},
},
{
.cmd = 0x8AU,
.len = 1U,
.data = {0x00U},
},
{
.cmd = 0x8BU,
.len = 1U,
.data = {0x80U},
},
{
.cmd = 0x8CU,
.len = 1U,
.data = {0x01U},
},
{
.cmd = 0x8DU,
.len = 1U,
.data = {0x01U},
},
{
.cmd = 0x8EU,
.len = 1U,
.data = {0xFFU},
},
{
.cmd = 0x8FU,
.len = 1U,
.data = {0xFFU},
},
{
.cmd = 0xB6U,
.len = 2U,
.data = {0x00U, 0x20U},
},
{
.cmd = 0x90U,
.len = 4U,
.data = {0x08U, 0x08U, 0x08U, 0x08U},
},
{
.cmd = 0xBDU,
.len = 1U,
.data = {0x06U},
},
{
.cmd = 0xBCU,
.len = 1U,
.data = {0x00U},
},
{
.cmd = 0xFFU,
.len = 3U,
.data = {0x60U, 0x01U, 0x04U},
},
{
.cmd = 0xBEU,
.len = 1U,
.data = {0x11U},
},
{
.cmd = 0xE1U,
.len = 2U,
.data = {0x10U, 0x0EU},
},
{
.cmd = 0xDFU,
.len = 3U,
.data = {0x21U, 0x0CU, 0x02U},
},
{
.cmd = 0xEDU,
.len = 2U,
.data = {0x1BU, 0x0BU},
},
{
.cmd = 0xAEU,
.len = 1U,
.data = {0x77U},
},
{
.cmd = 0xCDU,
.len = 1U,
.data = {0x63U},
},
{
.cmd = 0x70U,
.len = 9U,
.data = {0x07U, 0x07U, 0x04U, 0x0EU, 0x0FU, 0x09U, 0x07U, 0x08U, 0x03U},
},
{
.cmd = 0x62U,
.len = 12U,
.data = {0x18U, 0x0DU, 0x71U, 0xEDU, 0x70U, 0x70U, 0x18U, 0x0FU, 0x71U, 0xEFU,
0x70U, 0x70U},
},
{
.cmd = 0x63U,
.len = 12U,
.data = {0x18U, 0x11U, 0x71U, 0xF1U, 0x70U, 0x70U, 0x18U, 0x13U, 0x71U, 0xF3U,
0x70U, 0x70U},
},
{
.cmd = 0x64U,
.len = 7U,
.data = {0x28U, 0x29U, 0xF1U, 0x01U, 0xF1U, 0x00U, 0x07U},
},
{
.cmd = 0x66U,
.len = 10U,
.data = {0x3CU, 0x00U, 0xCDU, 0x67U, 0x45U, 0x45U, 0x10U, 0x00U, 0x00U, 0x00U},
},
{
.cmd = 0x67U,
.len = 10U,
.data = {0x00U, 0x3CU, 0x00U, 0x00U, 0x00U, 0x01U, 0x54U, 0x10U, 0x32U, 0x98U},
},
{
.cmd = 0x74U,
.len = 7U,
.data = {0x10U, 0x85U, 0x80U, 0x00U, 0x00U, 0x4EU, 0x00U},
},
{
.cmd = 0x98U,
.len = 2U,
.data = {0x3EU, 0x07U},
},
};
static int gc9x01x_transmit(const struct device *dev, uint8_t cmd, const void *tx_data,
size_t tx_len)
{
const struct gc9x01x_config *config = dev->config;
return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config,
cmd, tx_data, tx_len);
}
static int gc9x01x_regs_init(const struct device *dev)
{
const struct gc9x01x_config *config = dev->config;
const struct gc9x01x_regs *regs = config->regs;
int ret;
if (!device_is_ready(config->mipi_dev)) {
return -ENODEV;
}
/* Enable inter-command mode */
ret = gc9x01x_transmit(dev, GC9X01X_CMD_INREGEN1, NULL, 0);
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_INREGEN2, NULL, 0);
if (ret < 0) {
return ret;
}
/* Apply default init sequence */
for (int i = 0; (i < ARRAY_SIZE(default_init_regs)) && (ret == 0); i++) {
ret = gc9x01x_transmit(dev, default_init_regs[i].cmd, default_init_regs[i].data,
default_init_regs[i].len);
if (ret < 0) {
return ret;
}
}
/* Apply generic configuration */
ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL2, regs->pwrctrl2, sizeof(regs->pwrctrl2));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL3, regs->pwrctrl3, sizeof(regs->pwrctrl3));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_PWRCTRL4, regs->pwrctrl4, sizeof(regs->pwrctrl4));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA1, regs->gamma1, sizeof(regs->gamma1));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA2, regs->gamma2, sizeof(regs->gamma2));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA3, regs->gamma3, sizeof(regs->gamma3));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_GAMMA4, regs->gamma4, sizeof(regs->gamma4));
if (ret < 0) {
return ret;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_FRAMERATE, regs->framerate,
sizeof(regs->framerate));
if (ret < 0) {
return ret;
}
/* Enable Tearing line */
ret = gc9x01x_transmit(dev, GC9X01X_CMD_TEON, NULL, 0);
if (ret < 0) {
return ret;
}
return 0;
}
static int gc9x01x_exit_sleep(const struct device *dev)
{
int ret;
ret = gc9x01x_transmit(dev, GC9X01X_CMD_SLPOUT, NULL, 0);
if (ret < 0) {
return ret;
}
/*
* Exit sleepmode and enable display. 30ms on top of the sleepout time to account for
* any manufacturing defects.
* This is to allow time for the supply voltages and clock circuits stabilize
*/
k_msleep(GC9X01X_SLEEP_IN_OUT_DURATION_MS + 30);
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int gc9x01x_enter_sleep(const struct device *dev)
{
int ret;
ret = gc9x01x_transmit(dev, GC9X01X_CMD_SLPIN, NULL, 0);
if (ret < 0) {
return ret;
}
/*
* Exit sleepmode and enable display. 30ms on top of the sleepout time to account for
* any manufacturing defects.
*/
k_msleep(GC9X01X_SLEEP_IN_OUT_DURATION_MS + 30);
return 0;
}
#endif
static int gc9x01x_hw_reset(const struct device *dev)
{
const struct gc9x01x_config *config = dev->config;
int ret;
ret = mipi_dbi_reset(config->mipi_dev, 100);
if (ret < 0) {
return ret;
}
k_msleep(10);
return ret;
}
static int gc9x01x_display_blanking_off(const struct device *dev)
{
LOG_DBG("Turning display blanking off");
return gc9x01x_transmit(dev, GC9X01X_CMD_DISPON, NULL, 0);
}
static int gc9x01x_display_blanking_on(const struct device *dev)
{
LOG_DBG("Turning display blanking on");
return gc9x01x_transmit(dev, GC9X01X_CMD_DISPOFF, NULL, 0);
}
static int gc9x01x_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct gc9x01x_data *data = dev->data;
int ret;
uint8_t tx_data;
uint8_t bytes_per_pixel;
if (pixel_format == PIXEL_FORMAT_RGB_565) {
bytes_per_pixel = 2U;
tx_data = GC9X01X_PIXFMT_VAL_MCU_16_BIT | GC9X01X_PIXFMT_VAL_RGB_16_BIT;
} else if (pixel_format == PIXEL_FORMAT_RGB_888) {
bytes_per_pixel = 3U;
tx_data = GC9X01X_PIXFMT_VAL_MCU_18_BIT | GC9X01X_PIXFMT_VAL_RGB_18_BIT;
} else {
LOG_ERR("Unsupported pixel format");
return -ENOTSUP;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_PIXFMT, &tx_data, 1U);
if (ret < 0) {
return ret;
}
data->pixel_format = pixel_format;
data->bytes_per_pixel = bytes_per_pixel;
return 0;
}
static int gc9x01x_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
struct gc9x01x_data *data = dev->data;
int ret;
uint8_t tx_data = GC9X01X_MADCTL_VAL_BGR;
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
/* works 0 - default */
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_90) {
/* works CW 90 */
tx_data |= GC9X01X_MADCTL_VAL_MV | GC9X01X_MADCTL_VAL_MY;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_180) {
/* works CW 180 */
tx_data |= GC9X01X_MADCTL_VAL_MY | GC9X01X_MADCTL_VAL_MX | GC9X01X_MADCTL_VAL_MH;
} else if (orientation == DISPLAY_ORIENTATION_ROTATED_270) {
/* works CW 270 */
tx_data |= GC9X01X_MADCTL_VAL_MV | GC9X01X_MADCTL_VAL_MX;
}
ret = gc9x01x_transmit(dev, GC9X01X_CMD_MADCTL, &tx_data, 1U);
if (ret < 0) {
return ret;
}
data->orientation = orientation;
return 0;
}
static int gc9x01x_configure(const struct device *dev)
{
const struct gc9x01x_config *config = dev->config;
int ret;
/* Set all the required registers. */
ret = gc9x01x_regs_init(dev);
if (ret < 0) {
return ret;
}
/* Pixel format */
ret = gc9x01x_set_pixel_format(dev, config->pixel_format);
if (ret < 0) {
return ret;
}
/* Orientation */
ret = gc9x01x_set_orientation(dev, config->orientation);
if (ret < 0) {
return ret;
}
/* Display inversion mode. */
if (config->inversion) {
ret = gc9x01x_transmit(dev, GC9X01X_CMD_INVON, NULL, 0);
if (ret < 0) {
return ret;
}
}
return 0;
}
static int gc9x01x_init(const struct device *dev)
{
int ret;
gc9x01x_hw_reset(dev);
gc9x01x_display_blanking_on(dev);
ret = gc9x01x_configure(dev);
if (ret < 0) {
LOG_ERR("Could not configure display (%d)", ret);
return ret;
}
ret = gc9x01x_exit_sleep(dev);
if (ret < 0) {
LOG_ERR("Could not exit sleep mode (%d)", ret);
return ret;
}
return 0;
}
static int gc9x01x_set_mem_area(const struct device *dev, const uint16_t x, const uint16_t y,
const uint16_t w, const uint16_t h)
{
int ret;
uint16_t spi_data[2];
spi_data[0] = sys_cpu_to_be16(x);
spi_data[1] = sys_cpu_to_be16(x + w - 1U);
ret = gc9x01x_transmit(dev, GC9X01X_CMD_COLSET, &spi_data[0], 4U);
if (ret < 0) {
return ret;
}
spi_data[0] = sys_cpu_to_be16(y);
spi_data[1] = sys_cpu_to_be16(y + h - 1U);
ret = gc9x01x_transmit(dev, GC9X01X_CMD_ROWSET, &spi_data[0], 4U);
if (ret < 0) {
return ret;
}
return 0;
}
static int gc9x01x_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct gc9x01x_config *config = dev->config;
struct gc9x01x_data *data = dev->data;
int ret;
const uint8_t *write_data_start = (const uint8_t *)buf;
struct display_buffer_descriptor mipi_desc;
uint16_t write_cnt;
uint16_t nbr_of_writes;
uint16_t write_h;
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
__ASSERT((desc->pitch * data->bytes_per_pixel * desc->height) <= desc->buf_size,
"Input buffer to small");
LOG_DBG("Writing %dx%d (w,h) @ %dx%d (x,y)", desc->width, desc->height, x, y);
ret = gc9x01x_set_mem_area(dev, x, y, desc->width, desc->height);
if (ret < 0) {
return ret;
}
if (desc->pitch > desc->width) {
write_h = 1U;
nbr_of_writes = desc->height;
mipi_desc.height = 1;
mipi_desc.buf_size = desc->pitch * data->bytes_per_pixel;
} else {
write_h = desc->height;
mipi_desc.height = desc->height;
mipi_desc.buf_size = desc->width * data->bytes_per_pixel * write_h;
nbr_of_writes = 1U;
}
mipi_desc.width = desc->width;
/* Per MIPI API, pitch must always match width */
mipi_desc.pitch = desc->width;
ret = gc9x01x_transmit(dev, GC9X01X_CMD_MEMWR, NULL, 0);
if (ret < 0) {
return ret;
}
for (write_cnt = 0U; write_cnt < nbr_of_writes; ++write_cnt) {
ret = mipi_dbi_write_display(config->mipi_dev,
&config->dbi_config,
write_data_start,
&mipi_desc,
data->pixel_format);
if (ret < 0) {
return ret;
}
write_data_start += desc->pitch * data->bytes_per_pixel;
}
return 0;
}
static void gc9x01x_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
struct gc9x01x_data *data = dev->data;
const struct gc9x01x_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565 | PIXEL_FORMAT_RGB_888;
capabilities->current_pixel_format = data->pixel_format;
if (data->orientation == DISPLAY_ORIENTATION_NORMAL ||
data->orientation == DISPLAY_ORIENTATION_ROTATED_180) {
capabilities->x_resolution = config->x_resolution;
capabilities->y_resolution = config->y_resolution;
} else {
capabilities->x_resolution = config->y_resolution;
capabilities->y_resolution = config->x_resolution;
}
capabilities->current_orientation = data->orientation;
}
#ifdef CONFIG_PM_DEVICE
static int gc9x01x_pm_action(const struct device *dev, enum pm_device_action action)
{
int ret;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = gc9x01x_exit_sleep(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
ret = gc9x01x_enter_sleep(dev);
break;
default:
ret = -ENOTSUP;
break;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
/* Device driver API*/
static const struct display_driver_api gc9x01x_api = {
.blanking_on = gc9x01x_display_blanking_on,
.blanking_off = gc9x01x_display_blanking_off,
.write = gc9x01x_write,
.get_capabilities = gc9x01x_get_capabilities,
.set_pixel_format = gc9x01x_set_pixel_format,
.set_orientation = gc9x01x_set_orientation,
};
#define GC9X01X_INIT(inst) \
GC9X01X_REGS_INIT(inst); \
static const struct gc9x01x_config gc9x01x_config_##inst = { \
.mipi_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.dbi_config = { \
.mode = MIPI_DBI_MODE_SPI_4WIRE, \
.config = MIPI_DBI_SPI_CONFIG_DT_INST(inst, \
SPI_OP_MODE_MASTER | \
SPI_WORD_SET(8), 0), \
}, \
.pixel_format = DT_INST_PROP(inst, pixel_format), \
.orientation = DT_INST_ENUM_IDX(inst, orientation), \
.x_resolution = DT_INST_PROP(inst, width), \
.y_resolution = DT_INST_PROP(inst, height), \
.inversion = DT_INST_PROP(inst, display_inversion), \
.regs = &gc9x01x_regs_##inst, \
}; \
static struct gc9x01x_data gc9x01x_data_##inst; \
PM_DEVICE_DT_INST_DEFINE(inst, gc9x01x_pm_action); \
DEVICE_DT_INST_DEFINE(inst, &gc9x01x_init, PM_DEVICE_DT_INST_GET(inst), \
&gc9x01x_data_##inst, &gc9x01x_config_##inst, POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, &gc9x01x_api);
DT_INST_FOREACH_STATUS_OKAY(GC9X01X_INIT)
``` | /content/code_sandbox/drivers/display/display_gc9x01x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,301 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_sdl_dc
#include <zephyr/drivers/display.h>
#include <string.h>
#include <stdlib.h>
#include <soc.h>
#include <zephyr/sys/byteorder.h>
#include "display_sdl_bottom.h"
#include "cmdline.h"
#define LOG_LEVEL CONFIG_DISPLAY_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_sdl);
static uint32_t sdl_display_zoom_pct;
struct sdl_display_config {
uint16_t height;
uint16_t width;
};
struct sdl_display_data {
void *window;
void *renderer;
void *mutex;
void *texture;
void *read_texture;
bool display_on;
enum display_pixel_format current_pixel_format;
uint8_t *buf;
uint8_t *read_buf;
};
static inline uint32_t mono_pixel_order(uint32_t order)
{
if (IS_ENABLED(CONFIG_SDL_DISPLAY_MONO_MSB_FIRST)) {
return BIT(7 - order);
} else {
return BIT(order);
}
}
static int sdl_display_init(const struct device *dev)
{
const struct sdl_display_config *config = dev->config;
struct sdl_display_data *disp_data = dev->data;
bool use_accelerator = true;
LOG_DBG("Initializing display driver");
IF_DISABLED(CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR, (use_accelerator = false));
disp_data->current_pixel_format =
#if defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_888)
PIXEL_FORMAT_RGB_888
#elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01)
PIXEL_FORMAT_MONO01
#elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10)
PIXEL_FORMAT_MONO10
#elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_565)
PIXEL_FORMAT_RGB_565
#elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_BGR_565)
PIXEL_FORMAT_BGR_565
#else /* SDL_DISPLAY_DEFAULT_PIXEL_FORMAT */
PIXEL_FORMAT_ARGB_8888
#endif /* SDL_DISPLAY_DEFAULT_PIXEL_FORMAT */
;
if (sdl_display_zoom_pct == UINT32_MAX) {
sdl_display_zoom_pct = CONFIG_SDL_DISPLAY_ZOOM_PCT;
}
int rc = sdl_display_init_bottom(config->height, config->width, sdl_display_zoom_pct,
use_accelerator, &disp_data->window, &disp_data->renderer,
&disp_data->mutex, &disp_data->texture,
&disp_data->read_texture);
if (rc != 0) {
LOG_ERR("Failed to create SDL display");
return -EIO;
}
disp_data->display_on = false;
return 0;
}
static void sdl_display_write_argb8888(void *disp_buf,
const struct display_buffer_descriptor *desc, const void *buf)
{
__ASSERT((desc->pitch * 4U * desc->height) <= desc->buf_size,
"Input buffer to small");
memcpy(disp_buf, buf, desc->pitch * 4U * desc->height);
}
static void sdl_display_write_rgb888(uint8_t *disp_buf,
const struct display_buffer_descriptor *desc, const void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint32_t pixel;
const uint8_t *byte_ptr;
__ASSERT((desc->pitch * 3U * desc->height) <= desc->buf_size,
"Input buffer to small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
byte_ptr = (const uint8_t *)buf +
((h_idx * desc->pitch) + w_idx) * 3U;
pixel = *byte_ptr << 16;
pixel |= *(byte_ptr + 1) << 8;
pixel |= *(byte_ptr + 2);
*((uint32_t *)disp_buf) = pixel;
disp_buf += 4;
}
}
}
static void sdl_display_write_rgb565(uint8_t *disp_buf,
const struct display_buffer_descriptor *desc, const void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint32_t pixel;
const uint16_t *pix_ptr;
uint16_t rgb565;
__ASSERT((desc->pitch * 2U * desc->height) <= desc->buf_size,
"Input buffer to small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
pix_ptr = (const uint16_t *)buf +
((h_idx * desc->pitch) + w_idx);
rgb565 = sys_be16_to_cpu(*pix_ptr);
pixel = (((rgb565 >> 11) & 0x1F) * 255 / 31) << 16;
pixel |= (((rgb565 >> 5) & 0x3F) * 255 / 63) << 8;
pixel |= (rgb565 & 0x1F) * 255 / 31;
*((uint32_t *)disp_buf) = pixel;
disp_buf += 4;
}
}
}
static void sdl_display_write_bgr565(uint8_t *disp_buf,
const struct display_buffer_descriptor *desc, const void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint32_t pixel;
const uint16_t *pix_ptr;
__ASSERT((desc->pitch * 2U * desc->height) <= desc->buf_size,
"Input buffer to small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
pix_ptr = (const uint16_t *)buf +
((h_idx * desc->pitch) + w_idx);
pixel = (((*pix_ptr >> 11) & 0x1F) * 255 / 31) << 16;
pixel |= (((*pix_ptr >> 5) & 0x3F) * 255 / 63) << 8;
pixel |= (*pix_ptr & 0x1F) * 255 / 31;
*((uint32_t *)disp_buf) = pixel;
disp_buf += 4;
}
}
}
static void sdl_display_write_mono(uint8_t *disp_buf,
const struct display_buffer_descriptor *desc, const void *buf,
const bool one_is_black)
{
uint32_t w_idx;
uint32_t h_idx;
uint32_t tile_idx;
uint32_t pixel;
const uint8_t *byte_ptr;
uint32_t one_color;
uint8_t *disp_buf_start;
__ASSERT((desc->pitch * desc->height) <= (desc->buf_size * 8U),
"Input buffer to small");
__ASSERT((desc->height % 8) == 0U,
"Input buffer height not aligned per 8 pixels");
if (one_is_black) {
one_color = 0U;
} else {
one_color = 0x00FFFFFF;
}
for (tile_idx = 0U; tile_idx < desc->height/8U; ++tile_idx) {
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
byte_ptr = (const uint8_t *)buf +
((tile_idx * desc->pitch) + w_idx);
disp_buf_start = disp_buf;
for (h_idx = 0U; h_idx < 8; ++h_idx) {
if ((*byte_ptr & mono_pixel_order(h_idx)) != 0U) {
pixel = one_color;
} else {
pixel = (~one_color) & 0x00FFFFFF;
}
*((uint32_t *)disp_buf) = pixel;
disp_buf += (desc->width * 4U);
}
disp_buf = disp_buf_start;
disp_buf += 4;
}
disp_buf += 7 * (desc->width * 4U);
}
}
static int sdl_display_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct sdl_display_config *config = dev->config;
struct sdl_display_data *disp_data = dev->data;
LOG_DBG("Writing %dx%d (w,h) bitmap @ %dx%d (x,y)", desc->width,
desc->height, x, y);
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT(desc->pitch <= config->width,
"Pitch in descriptor is larger than screen size");
__ASSERT(desc->height <= config->height,
"Height in descriptor is larger than screen size");
__ASSERT(x + desc->width <= config->width,
"Writing outside screen boundaries in horizontal direction");
__ASSERT(y + desc->height <= config->height,
"Writing outside screen boundaries in vertical direction");
if (desc->width > desc->pitch ||
x + desc->width > config->width ||
y + desc->height > config->height) {
return -EINVAL;
}
if (disp_data->current_pixel_format == PIXEL_FORMAT_ARGB_8888) {
sdl_display_write_argb8888(disp_data->buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_RGB_888) {
sdl_display_write_rgb888(disp_data->buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_MONO10) {
sdl_display_write_mono(disp_data->buf, desc, buf, true);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_MONO01) {
sdl_display_write_mono(disp_data->buf, desc, buf, false);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_RGB_565) {
sdl_display_write_rgb565(disp_data->buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_BGR_565) {
sdl_display_write_bgr565(disp_data->buf, desc, buf);
}
sdl_display_write_bottom(desc->height, desc->width, x, y,
disp_data->renderer, disp_data->mutex, disp_data->texture,
disp_data->buf, disp_data->display_on);
return 0;
}
static void sdl_display_read_argb8888(const uint8_t *read_buf,
const struct display_buffer_descriptor *desc, void *buf)
{
__ASSERT((desc->pitch * 4U * desc->height) <= desc->buf_size, "Read buffer is too small");
memcpy(buf, read_buf, desc->pitch * 4U * desc->height);
}
static void sdl_display_read_rgb888(const uint8_t *read_buf,
const struct display_buffer_descriptor *desc, void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint8_t *buf8;
const uint32_t *pix_ptr;
__ASSERT((desc->pitch * 3U * desc->height) <= desc->buf_size, "Read buffer is too small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
buf8 = ((uint8_t *)buf) + desc->pitch * 3U * h_idx;
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
pix_ptr = (const uint32_t *)read_buf + ((h_idx * desc->pitch) + w_idx);
*buf8 = (*pix_ptr & 0xFF0000) >> 16;
buf8 += 1;
*buf8 = (*pix_ptr & 0xFF00) >> 8;
buf8 += 1;
*buf8 = (*pix_ptr & 0xFF);
buf8 += 1;
}
}
}
static void sdl_display_read_rgb565(const uint8_t *read_buf,
const struct display_buffer_descriptor *desc, void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint16_t pixel;
uint16_t *buf16;
const uint32_t *pix_ptr;
__ASSERT((desc->pitch * 2U * desc->height) <= desc->buf_size, "Read buffer is too small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
buf16 = (void *)(((uint8_t *)buf) + desc->pitch * 2U * h_idx);
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
pix_ptr = (const uint32_t *)read_buf + ((h_idx * desc->pitch) + w_idx);
pixel = (*pix_ptr & 0xF80000) >> 8;
pixel |= (*pix_ptr & 0x00FC00) >> 5;
pixel |= (*pix_ptr & 0x0000F8) >> 3;
*buf16 = sys_be16_to_cpu(pixel);
buf16 += 1;
}
}
}
static void sdl_display_read_bgr565(const uint8_t *read_buf,
const struct display_buffer_descriptor *desc, void *buf)
{
uint32_t w_idx;
uint32_t h_idx;
uint16_t pixel;
uint16_t *buf16;
const uint32_t *pix_ptr;
__ASSERT((desc->pitch * 2U * desc->height) <= desc->buf_size, "Read buffer is too small");
for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
buf16 = (void *)(((uint8_t *)buf) + desc->pitch * 2U * h_idx);
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
pix_ptr = (const uint32_t *)read_buf + ((h_idx * desc->pitch) + w_idx);
pixel = (*pix_ptr & 0xF80000) >> 8;
pixel |= (*pix_ptr & 0x00FC00) >> 5;
pixel |= (*pix_ptr & 0x0000F8) >> 3;
*buf16 = pixel;
buf16 += 1;
}
}
}
static void sdl_display_read_mono(const uint8_t *read_buf,
const struct display_buffer_descriptor *desc, void *buf,
const bool one_is_black)
{
uint32_t w_idx;
uint32_t h_idx;
uint32_t tile_idx;
uint8_t tile;
const uint32_t *pix_ptr;
uint8_t *buf8;
__ASSERT((desc->pitch * desc->height) <= (desc->buf_size * 8U), "Read buffer is too small");
__ASSERT((desc->height % 8U) == 0U, "Read buffer height not aligned per 8 pixels");
for (tile_idx = 0U; tile_idx < (desc->height / 8U); ++tile_idx) {
buf8 = (void *)(((uint8_t *)buf) + desc->pitch * tile_idx);
for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
tile = 0;
for (h_idx = 0U; h_idx < 8; ++h_idx) {
pix_ptr = (const uint32_t *)read_buf +
((tile_idx * 8 + h_idx) * desc->pitch + w_idx);
if ((*pix_ptr)) {
tile |= mono_pixel_order(h_idx);
}
}
*buf8 = one_is_black ? ~tile : tile;
buf8 += 1;
}
}
}
static int sdl_display_read(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
struct sdl_display_data *disp_data = dev->data;
int err;
LOG_DBG("Reading %dx%d (w,h) bitmap @ %dx%d (x,y)", desc->width,
desc->height, x, y);
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
memset(disp_data->read_buf, 0, desc->pitch * desc->height * 4);
err = sdl_display_read_bottom(desc->height, desc->width, x, y, disp_data->renderer,
disp_data->read_buf, desc->pitch, disp_data->mutex,
disp_data->texture, disp_data->read_texture);
if (err) {
return err;
}
if (disp_data->current_pixel_format == PIXEL_FORMAT_ARGB_8888) {
sdl_display_read_argb8888(disp_data->read_buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_RGB_888) {
sdl_display_read_rgb888(disp_data->read_buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_MONO10) {
sdl_display_read_mono(disp_data->read_buf, desc, buf, true);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_MONO01) {
sdl_display_read_mono(disp_data->read_buf, desc, buf, false);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_RGB_565) {
sdl_display_read_rgb565(disp_data->read_buf, desc, buf);
} else if (disp_data->current_pixel_format == PIXEL_FORMAT_BGR_565) {
sdl_display_read_bgr565(disp_data->read_buf, desc, buf);
}
return 0;
}
static int sdl_display_blanking_off(const struct device *dev)
{
struct sdl_display_data *disp_data = dev->data;
LOG_DBG("Turning display blacking off");
disp_data->display_on = true;
sdl_display_blanking_off_bottom(disp_data->renderer, disp_data->texture);
return 0;
}
static int sdl_display_blanking_on(const struct device *dev)
{
struct sdl_display_data *disp_data = dev->data;
LOG_DBG("Turning display blanking on");
disp_data->display_on = false;
sdl_display_blanking_on_bottom(disp_data->renderer);
return 0;
}
static void sdl_display_get_capabilities(
const struct device *dev, struct display_capabilities *capabilities)
{
const struct sdl_display_config *config = dev->config;
struct sdl_display_data *disp_data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->width;
capabilities->y_resolution = config->height;
capabilities->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888 |
PIXEL_FORMAT_RGB_888 |
PIXEL_FORMAT_MONO01 |
PIXEL_FORMAT_MONO10 |
PIXEL_FORMAT_RGB_565 |
PIXEL_FORMAT_BGR_565;
capabilities->current_pixel_format = disp_data->current_pixel_format;
capabilities->screen_info = SCREEN_INFO_MONO_VTILED |
(IS_ENABLED(CONFIG_SDL_DISPLAY_MONO_MSB_FIRST) ? SCREEN_INFO_MONO_MSB_FIRST : 0);
}
static int sdl_display_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct sdl_display_data *disp_data = dev->data;
switch (pixel_format) {
case PIXEL_FORMAT_ARGB_8888:
case PIXEL_FORMAT_RGB_888:
case PIXEL_FORMAT_MONO01:
case PIXEL_FORMAT_MONO10:
case PIXEL_FORMAT_RGB_565:
case PIXEL_FORMAT_BGR_565:
disp_data->current_pixel_format = pixel_format;
return 0;
default:
LOG_ERR("Pixel format not supported");
return -ENOTSUP;
}
}
static void sdl_display_cleanup(struct sdl_display_data *disp_data)
{
sdl_display_cleanup_bottom(&disp_data->window, &disp_data->renderer, &disp_data->mutex,
&disp_data->texture, &disp_data->read_texture);
}
static const struct display_driver_api sdl_display_api = {
.blanking_on = sdl_display_blanking_on,
.blanking_off = sdl_display_blanking_off,
.write = sdl_display_write,
.read = sdl_display_read,
.get_capabilities = sdl_display_get_capabilities,
.set_pixel_format = sdl_display_set_pixel_format,
};
#define DISPLAY_SDL_DEFINE(n) \
static const struct sdl_display_config sdl_config_##n = { \
.height = DT_INST_PROP(n, height), \
.width = DT_INST_PROP(n, width), \
}; \
\
static uint8_t sdl_buf_##n[4 * DT_INST_PROP(n, height) \
* DT_INST_PROP(n, width)]; \
static uint8_t sdl_read_buf_##n[4 * DT_INST_PROP(n, height) \
* DT_INST_PROP(n, width)]; \
static struct sdl_display_data sdl_data_##n = { \
.buf = sdl_buf_##n, \
.read_buf = sdl_read_buf_##n, \
}; \
\
DEVICE_DT_INST_DEFINE(n, &sdl_display_init, NULL, \
&sdl_data_##n, \
&sdl_config_##n, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&sdl_display_api); \
\
static void sdl_display_cleanup_##n(void) \
{ \
sdl_display_cleanup(&sdl_data_##n); \
} \
\
NATIVE_TASK(sdl_display_cleanup_##n, ON_EXIT, 1);
DT_INST_FOREACH_STATUS_OKAY(DISPLAY_SDL_DEFINE)
static void display_sdl_options(void)
{
static struct args_struct_t sdl_display_options[] = {
{ .option = "display_zoom_pct",
.name = "pct",
.type = 'u',
.dest = (void *)&sdl_display_zoom_pct,
.descript = "Display zoom percentage (100 == 1:1 scale), "
"by default " STRINGIFY(CONFIG_SDL_DISPLAY_ZOOM_PCT)
" = CONFIG_SDL_DISPLAY_ZOOM_PCT"
},
ARG_TABLE_ENDMARKER
};
native_add_command_line_opts(sdl_display_options);
}
NATIVE_TASK(display_sdl_options, PRE_BOOT_1, 1);
``` | /content/code_sandbox/drivers/display/display_sdl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,943 |
```c
/*
*
*/
#define DT_DRV_COMPAT led_strip_matrix
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(led_strip_matrix, CONFIG_DISPLAY_LOG_LEVEL);
struct led_strip_buffer {
const struct device *const dev;
const size_t chain_length;
struct led_rgb *pixels;
};
struct led_strip_matrix_config {
size_t num_of_strips;
const struct led_strip_buffer *strips;
uint16_t height;
uint16_t width;
uint16_t module_width;
uint16_t module_height;
bool circulative;
bool start_from_right;
bool start_from_bottom;
bool modules_circulative;
bool modules_start_from_right;
bool modules_start_from_bottom;
enum display_pixel_format pixel_format;
};
static size_t pixel_index(const struct led_strip_matrix_config *config, uint16_t x, uint16_t y)
{
const size_t mods_per_row = config->width / config->module_width;
const size_t mod_w = config->module_width;
const size_t mod_h = config->module_height;
const size_t mod_pixels = mod_w * mod_h;
const size_t mod_row =
config->modules_start_from_bottom ? (mod_h - 1) - (y / mod_h) : y / mod_h;
const size_t y_in_mod = config->start_from_bottom ? (mod_h - 1) - (y % mod_h) : y % mod_h;
size_t mod_col = x / mod_w;
size_t x_in_mod = x % mod_w;
if (config->modules_circulative) {
if (config->modules_start_from_right) {
mod_col = mods_per_row - 1 - mod_col;
}
} else {
if ((mod_row % 2) == !config->modules_start_from_right) {
mod_col = mods_per_row - 1 - mod_col;
}
}
if (config->circulative) {
if (config->start_from_right) {
x_in_mod = (mod_w - 1) - (x % mod_w);
}
} else {
if ((y_in_mod % 2) == !config->start_from_right) {
x_in_mod = (mod_w - 1) - (x % mod_w);
}
}
return (mods_per_row * mod_row + mod_col) * mod_pixels + y_in_mod * mod_w + x_in_mod;
}
static struct led_rgb *pixel_address(const struct led_strip_matrix_config *config, uint16_t x,
uint16_t y)
{
size_t idx = pixel_index(config, x, y);
for (size_t i = 0; i < config->num_of_strips; i++) {
if (idx < config->strips[i].chain_length) {
return &config->strips[i].pixels[idx];
}
idx -= config->strips[i].chain_length;
}
return NULL;
}
static inline int check_descriptor(const struct led_strip_matrix_config *config, const uint16_t x,
const uint16_t y, const struct display_buffer_descriptor *desc)
{
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT(desc->pitch <= config->width, "Pitch in descriptor is larger than screen size");
__ASSERT(desc->height <= config->height, "Height in descriptor is larger than screen size");
__ASSERT(x + desc->pitch <= config->width,
"Writing outside screen boundaries in horizontal direction");
__ASSERT(y + desc->height <= config->height,
"Writing outside screen boundaries in vertical direction");
if (desc->width > desc->pitch || x + desc->pitch > config->width ||
y + desc->height > config->height) {
return -EINVAL;
}
return 0;
}
static int led_strip_matrix_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct led_strip_matrix_config *config = dev->config;
const uint8_t *buf_ptr = buf;
int rc;
rc = check_descriptor(config, x, y, desc);
if (rc) {
LOG_ERR("Invalid descriptor: %d", rc);
return rc;
}
for (size_t ypos = y; ypos < (y + desc->height); ypos++) {
for (size_t xpos = x; xpos < (x + desc->width); xpos++) {
struct led_rgb *pix = pixel_address(config, xpos, ypos);
if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) {
uint32_t color = *((uint32_t *)buf_ptr);
pix->r = (color >> 16) & 0xFF;
pix->g = (color >> 8) & 0xFF;
pix->b = (color) & 0xFF;
buf_ptr += 4;
} else {
pix->r = *buf_ptr;
buf_ptr++;
pix->g = *buf_ptr;
buf_ptr++;
pix->b = *buf_ptr;
buf_ptr++;
}
}
buf_ptr += (desc->pitch - desc->width) *
(config->pixel_format == PIXEL_FORMAT_ARGB_8888 ? 4 : 3);
}
for (size_t i = 0; i < config->num_of_strips; i++) {
rc = led_strip_update_rgb(config->strips[i].dev, config->strips[i].pixels,
config->width * config->height);
if (rc) {
LOG_ERR("couldn't update strip: %d", rc);
}
}
return rc;
}
static int led_strip_matrix_read(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, void *buf)
{
const struct led_strip_matrix_config *config = dev->config;
uint8_t *buf_ptr = buf;
int rc;
rc = check_descriptor(config, x, y, desc);
if (rc) {
LOG_ERR("Invalid descriptor: %d", rc);
return rc;
}
for (size_t ypos = y; ypos < (y + desc->height); ypos++) {
for (size_t xpos = x; xpos < (x + desc->width); xpos++) {
struct led_rgb *pix = pixel_address(config, xpos, ypos);
if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) {
uint32_t *pix_ptr = (uint32_t *)buf_ptr;
*pix_ptr = 0xFF000000 | pix->r << 16 | pix->g << 8 | pix->b;
} else {
*buf_ptr = pix->r;
buf_ptr++;
*buf_ptr = pix->g;
buf_ptr++;
*buf_ptr = pix->b;
buf_ptr++;
}
}
buf_ptr += (desc->pitch - desc->width) *
(config->pixel_format == PIXEL_FORMAT_ARGB_8888 ? 4 : 3);
}
return 0;
}
static void led_strip_matrix_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct led_strip_matrix_config *config = dev->config;
memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = config->width;
caps->y_resolution = config->height;
caps->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888 | PIXEL_FORMAT_RGB_888;
caps->current_pixel_format = config->pixel_format;
caps->screen_info = 0;
}
static const struct display_driver_api led_strip_matrix_api = {
.write = led_strip_matrix_write,
.read = led_strip_matrix_read,
.get_capabilities = led_strip_matrix_get_capabilities,
};
static int led_strip_matrix_init(const struct device *dev)
{
const struct led_strip_matrix_config *config = dev->config;
for (size_t i = 0; i < config->num_of_strips; i++) {
if (!device_is_ready(config->strips[i].dev)) {
LOG_ERR("LED strip device %s is not ready", config->strips[i].dev->name);
return -EINVAL;
}
}
return 0;
}
#define CHAIN_LENGTH(idx, inst) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, chain_lengths), \
(DT_INST_PROP_BY_IDX(inst, chain_lengths, idx)), \
(DT_INST_PROP_BY_PHANDLE_IDX(inst, led_strips, idx, chain_length)))
#define STRIP_BUFFER_INITIALIZER(idx, inst) \
{ \
.dev = DEVICE_DT_GET(DT_INST_PROP_BY_IDX(inst, led_strips, idx)), \
.chain_length = CHAIN_LENGTH(idx, inst), \
.pixels = pixels##inst##_##idx, \
}
#define DECLARE_PIXELS(idx, inst) \
static struct led_rgb pixels##inst##_##idx[CHAIN_LENGTH(idx, inst)];
#define AMOUNT_OF_LEDS(inst) LISTIFY(DT_INST_PROP_LEN(inst, led_strips), CHAIN_LENGTH, (+), inst)
#define VALIDATE_CHAIN_LENGTH(idx, inst) \
BUILD_ASSERT( \
CHAIN_LENGTH(idx, inst) % \
(DT_INST_PROP(inst, width) / DT_INST_PROP(inst, horizontal_modules) * \
(DT_INST_PROP(inst, height) / DT_INST_PROP(inst, vertical_modules))) == \
0);
#define LED_STRIP_MATRIX_DEFINE(inst) \
LISTIFY(DT_INST_PROP_LEN(inst, led_strips), DECLARE_PIXELS, (;), inst); \
static const struct led_strip_buffer strip_buffer##inst[] = { \
LISTIFY(DT_INST_PROP_LEN(inst, led_strips), STRIP_BUFFER_INITIALIZER, (,), inst), \
}; \
static const struct led_strip_matrix_config dd_config_##inst = { \
.num_of_strips = DT_INST_PROP_LEN(inst, led_strips), \
.strips = strip_buffer##inst, \
.width = DT_INST_PROP(inst, width), \
.height = DT_INST_PROP(inst, height), \
.module_width = \
DT_INST_PROP(inst, width) / DT_INST_PROP(inst, horizontal_modules), \
.module_height = \
DT_INST_PROP(inst, height) / DT_INST_PROP(inst, vertical_modules), \
.circulative = DT_INST_PROP(inst, circulative), \
.start_from_right = DT_INST_PROP(inst, start_from_right), \
.modules_circulative = DT_INST_PROP(inst, modules_circulative), \
.modules_start_from_right = DT_INST_PROP(inst, modules_start_from_right), \
.pixel_format = DT_INST_PROP(inst, pixel_format), \
}; \
\
BUILD_ASSERT((DT_INST_PROP(inst, pixel_format) == PIXEL_FORMAT_RGB_888) || \
(DT_INST_PROP(inst, pixel_format) == PIXEL_FORMAT_ARGB_8888)); \
BUILD_ASSERT((DT_INST_PROP(inst, width) * DT_INST_PROP(inst, height)) == \
AMOUNT_OF_LEDS(inst)); \
BUILD_ASSERT((DT_INST_PROP(inst, width) % DT_INST_PROP(inst, horizontal_modules)) == 0); \
BUILD_ASSERT((DT_INST_PROP(inst, height) % DT_INST_PROP(inst, vertical_modules)) == 0); \
LISTIFY(DT_INST_PROP_LEN(inst, led_strips), VALIDATE_CHAIN_LENGTH, (;), inst); \
\
DEVICE_DT_INST_DEFINE(inst, led_strip_matrix_init, NULL, NULL, &dd_config_##inst, \
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, \
&led_strip_matrix_api);
DT_INST_FOREACH_STATUS_OKAY(LED_STRIP_MATRIX_DEFINE)
``` | /content/code_sandbox/drivers/display/display_led_strip_matrix.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,570 |
```objective-c
/* ssd16xx_regs.h - Registers definition for SSD16XX compatible controller */
/*
*
*/
#ifndef __SSD16XX_REGS_H__
#define __SSD16XX_REGS_H__
#define SSD16XX_CMD_GDO_CTRL 0x01
#define SSD16XX_CMD_GDV_CTRL 0x03
#define SSD16XX_CMD_SDV_CTRL 0x04
#define SSD16XX_CMD_SOFTSTART 0x0c
#define SSD16XX_CMD_GSCAN_START 0x0f
#define SSD16XX_CMD_SLEEP_MODE 0x10
#define SSD16XX_CMD_ENTRY_MODE 0x11
#define SSD16XX_CMD_SW_RESET 0x12
#define SSD16XX_CMD_TSENSOR_SELECTION 0x18
#define SSD16XX_CMD_TSENS_CTRL 0x1a
#define SSD16XX_CMD_READ_TSENS_CTRL 0x1b
#define SSD16XX_CMD_MASTER_ACTIVATION 0x20
#define SSD16XX_CMD_UPDATE_CTRL1 0x21
#define SSD16XX_CMD_UPDATE_CTRL2 0x22
#define SSD16XX_CMD_WRITE_RAM 0x24
#define SSD16XX_CMD_WRITE_RED_RAM 0x26
#define SSD16XX_CMD_READ_RAM 0x27
#define SSD16XX_CMD_VCOM_SENSE 0x28
#define SSD16XX_CMD_VCOM_SENSE_DURATON 0x29
#define SSD16XX_CMD_PRGM_VCOM_OTP 0x2a
#define SSD16XX_CMD_VCOM_VOLTAGE 0x2c
#define SSD16XX_CMD_READ_OTP_REG 0x2d
#define SSD16XX_CMD_READ_USER_ID 0x2e
#define SSD16XX_CMD_READ_STATUS 0x2f
#define SSD16XX_CMD_PRGM_WS_OTP 0x30
#define SSD16XX_CMD_LOAD_WS_OTP 0x31
#define SSD16XX_CMD_UPDATE_LUT 0x32
#define SSD16XX_CMD_PRGM_OTP_SELECTION 0x36
#define SSD16XX_CMD_OTP_SELECTION_CTRL 0x37
#define SSD16XX_CMD_DUMMY_LINE 0x3a
#define SSD16XX_CMD_GATE_LINE_WIDTH 0x3b
#define SSD16XX_CMD_BWF_CTRL 0x3c
#define SSD16XX_CMD_RAM_READ_CTRL 0x41
#define SSD16XX_CMD_RAM_XPOS_CTRL 0x44
#define SSD16XX_CMD_RAM_YPOS_CTRL 0x45
#define SSD16XX_CMD_RAM_XPOS_CNTR 0x4e
#define SSD16XX_CMD_RAM_YPOS_CNTR 0x4f
/* Data entry sequence modes */
#define SSD16XX_DATA_ENTRY_MASK 0x07
#define SSD16XX_DATA_ENTRY_XDYDX 0x00
#define SSD16XX_DATA_ENTRY_XIYDX 0x01
#define SSD16XX_DATA_ENTRY_XDYIX 0x02
#define SSD16XX_DATA_ENTRY_XIYIX 0x03
#define SSD16XX_DATA_ENTRY_XDYDY 0x04
#define SSD16XX_DATA_ENTRY_XIYDY 0x05
#define SSD16XX_DATA_ENTRY_XDYIY 0x06
#define SSD16XX_DATA_ENTRY_XIYIY 0x07
/* Options for display update */
#define SSD16XX_CTRL1_INITIAL_UPDATE_LL 0x00
#define SSD16XX_CTRL1_INITIAL_UPDATE_LH 0x01
#define SSD16XX_CTRL1_INITIAL_UPDATE_HL 0x02
#define SSD16XX_CTRL1_INITIAL_UPDATE_HH 0x03
/* Options for display update sequence */
#define SSD16XX_CTRL2_ENABLE_CLK 0x80
#define SSD16XX_CTRL2_ENABLE_ANALOG 0x40
#define SSD16XX_CTRL2_LOAD_TEMPERATURE 0x20
#define SSD16XX_CTRL2_LOAD_LUT 0x10
#define SSD16XX_CTRL2_DISABLE_ANALOG 0x02
#define SSD16XX_CTRL2_DISABLE_CLK 0x01
#define SSD16XX_GEN1_CTRL2_TO_INITIAL 0x08
#define SSD16XX_GEN1_CTRL2_TO_PATTERN 0x04
#define SSD16XX_GEN2_CTRL2_MODE2 0x08
#define SSD16XX_GEN2_CTRL2_DISPLAY 0x04
#define SSD16XX_SLEEP_MODE_DSM 0x01
#define SSD16XX_SLEEP_MODE_PON 0x00
#define SSD16XX_RAM_READ_CTRL_BLACK 0
#define SSD16XX_RAM_READ_CTRL_RED 1
/* time constants in ms */
#define SSD16XX_RESET_DELAY 1
#define SSD16XX_BUSY_DELAY 1
#endif /* __SSD16XX_REGS_H__ */
``` | /content/code_sandbox/drivers/display/ssd16xx_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,049 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_
/**
* @name General parameters.
* @{
*/
/** ID1 */
#define OTM8009A_ID1 0x40U
/** Read ID1 command */
#define OTM8009A_CMD_ID1 0xDA
/** Reset pulse time (ms), ref. Table 6.3.4.1 */
#define OTM8009A_RESET_TIME 10U
/** Wake up time after reset pulse, ref. Table 6.3.4.1 */
#define OTM8009A_WAKE_TIME 20U
/** Time to wait after exiting sleep mode (ms), ref. 5.2.11. */
#define OTM8009A_EXIT_SLEEP_MODE_WAIT_TIME 5U
/** @} */
/**
* @name Display timings (ref. table 6.4.2.1)
* @{
*/
/** Horizontal low pulse width */
#define OTM8009A_HSYNC 2U
/** Horizontal front porch. */
#define OTM8009A_HFP 34U
/** Horizontal back porch. */
#define OTM8009A_HBP 34U
/** Vertical low pulse width. */
#define OTM8009A_VSYNC 1U
/** Vertical front porch. */
#define OTM8009A_VFP 16U
/** Vertical back porch. */
#define OTM8009A_VBP 15U
/** @} */
/**
* @name Register fields.
* @{
*/
/**
* @name MIPI DCS Write Control Display fields.
* @{
*/
/** Write Control Display: brightness control. */
#define OTM8009A_WRCTRLD_BCTRL BIT(5)
/** Write Control Display: display dimming. */
#define OTM8009A_WRCTRLD_DD BIT(3)
/** Write Control Display: backlight. */
#define OTM8009A_WRCTRLD_BL BIT(2)
/** Adaptibe Brightness Control: off. */
#define OTM8009A_WRCABC_OFF 0x00U
/** Adaptibe Brightness Control: user interface. */
#define OTM8009A_WRCABC_UI 0x01U
/** Adaptibe Brightness Control: still picture. */
#define OTM8009A_WRCABC_ST 0x02U
/** Adaptibe Brightness Control: moving image. */
#define OTM8009A_WRCABC_MV 0x03U
/** @} */
/**
* @name MIPI MCS (Manufacturer Command Set).
* @{
*/
/** Address Shift Function */
#define OTM8009A_MCS_ADRSFT 0x0000U
/** Panel Type Setting */
#define OTM8009A_MCS_PANSET 0xB3A6U
/* Source Driver Timing Setting */
#define OTM8009A_MCS_SD_CTRL 0xC0A2U
/** Panel Driving Mode */
#define OTM8009A_MCS_P_DRV_M 0xC0B4U
/** Oscillator Adjustment for Idle/Normal mode */
#define OTM8009A_MCS_OSC_ADJ 0xC181U
/** RGB Video Mode Setting */
#define OTM8009A_MCS_RGB_VID_SET 0xC1A1U
/** Source Driver Precharge Control */
#define OTM8009A_MCS_SD_PCH_CTRL 0xC480U
/** Command not documented */
#define OTM8009A_MCS_NO_DOC1 0xC48AU
/** Power Control Setting 1 */
#define OTM8009A_MCS_PWR_CTRL1 0xC580U
/** Power Control Setting 2 for Normal Mode */
#define OTM8009A_MCS_PWR_CTRL2 0xC590U
/** Power Control Setting 4 for DC Voltage */
#define OTM8009A_MCS_PWR_CTRL4 0xC5B0U
/** PWM Parameter 1 */
#define OTM8009A_MCS_PWM_PARA1 0xC680U
/** PWM Parameter 2 */
#define OTM8009A_MCS_PWM_PARA2 0xC6B0U
/** PWM Parameter 3 */
#define OTM8009A_MCS_PWM_PARA3 0xC6B1U
/** PWM Parameter 4 */
#define OTM8009A_MCS_PWM_PARA4 0xC6B3U
/** PWM Parameter 5 */
#define OTM8009A_MCS_PWM_PARA5 0xC6B4U
/** PWM Parameter 6 */
#define OTM8009A_MCS_PWM_PARA6 0xC6B5U
/** Panel Control Setting 1 */
#define OTM8009A_MCS_PANCTRLSET1 0xCB80U
/** Panel Control Setting 2 */
#define OTM8009A_MCS_PANCTRLSET2 0xCB90U
/** Panel Control Setting 3 */
#define OTM8009A_MCS_PANCTRLSET3 0xCBA0U
/** Panel Control Setting 4 */
#define OTM8009A_MCS_PANCTRLSET4 0xCBB0U
/** Panel Control Setting 5 */
#define OTM8009A_MCS_PANCTRLSET5 0xCBC0U
/** Panel Control Setting 6 */
#define OTM8009A_MCS_PANCTRLSET6 0xCBD0U
/** Panel Control Setting 7 */
#define OTM8009A_MCS_PANCTRLSET7 0xCBE0U
/** Panel Control Setting 8 */
#define OTM8009A_MCS_PANCTRLSET8 0xCBF0U
/** Panel U2D Setting 1 */
#define OTM8009A_MCS_PANU2D1 0xCC80U
/** Panel U2D Setting 2 */
#define OTM8009A_MCS_PANU2D2 0xCC90U
/** Panel U2D Setting 3 */
#define OTM8009A_MCS_PANU2D3 0xCCA0U
/** Panel D2U Setting 1 */
#define OTM8009A_MCS_PAND2U1 0xCCB0U
/** Panel D2U Setting 2 */
#define OTM8009A_MCS_PAND2U2 0xCCC0U
/** Panel D2U Setting 3 */
#define OTM8009A_MCS_PAND2U3 0xCCD0U
/** GOA VST Setting */
#define OTM8009A_MCS_GOAVST 0xCE80U
/** GOA CLKA1 Setting */
#define OTM8009A_MCS_GOACLKA1 0xCEA0U
/** GOA CLKA2 Setting */
#define OTM8009A_MCS_GOACLKA2 0xCEA7U
/** GOA CLKA3 Setting */
#define OTM8009A_MCS_GOACLKA3 0xCEB0U
/** GOA CLKA4 Setting */
#define OTM8009A_MCS_GOACLKA4 0xCEB7U
/** GOA ECLK Setting */
#define OTM8009A_MCS_GOAECLK 0xCFC0U
/** GOA Other Options 1 */
#define OTM8009A_MCS_GOAPT1 0xCFC6U
/** GOA Signal Toggle Option Setting */
#define OTM8009A_MCS_GOATGOPT 0xCFC7U
/** Command not documented */
#define OTM8009A_MCS_NO_DOC2 0xCFD0U
/** GVDD/NGVDD */
#define OTM8009A_MCS_GVDDSET 0xD800U
/** VCOM Voltage Setting */
#define OTM8009A_MCS_VCOMDC 0xD900U
/** Gamma Correction 2.2+ Setting */
#define OTM8009A_MCS_GMCT2_2P 0xE100U
/** Gamma Correction 2.2- Setting */
#define OTM8009A_MCS_GMCT2_2N 0xE200U
/** Command not documented */
#define OTM8009A_MCS_NO_DOC3 0xF5B6U
/** Enable Access Command2 "CMD2" */
#define OTM8009A_MCS_CMD2_ENA1 0xFF00U
/** Enable Access Orise Command2 */
#define OTM8009A_MCS_CMD2_ENA2 0xFF80U
/** @} */
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_ */
``` | /content/code_sandbox/drivers/display/display_otm8009a.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,843 |
```c
/*
*
*/
#include "display_ili9342c.h"
#include "display_ili9xxx.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_ili9342c, CONFIG_DISPLAY_LOG_LEVEL);
int ili9342c_regs_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
const struct ili9342c_regs *regs = config->regs;
int r;
/* some commands require that SETEXTC be set first before it becomes enabled. */
LOG_HEXDUMP_DBG(regs->setextc, ILI9342C_SETEXTC_LEN, "SETEXTC");
r = ili9xxx_transmit(dev, ILI9342C_SETEXTC, regs->setextc,
ILI9342C_SETEXTC_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->gamset, ILI9342C_GAMSET_LEN, "GAMSET");
r = ili9xxx_transmit(dev, ILI9342C_GAMSET, regs->gamset,
ILI9342C_GAMSET_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ifmode, ILI9342C_IFMODE_LEN, "IFMODE");
r = ili9xxx_transmit(dev, ILI9342C_IFMODE, regs->ifmode,
ILI9342C_IFMODE_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->frmctr1, ILI9342C_FRMCTR1_LEN, "FRMCTR1");
r = ili9xxx_transmit(dev, ILI9342C_FRMCTR1, regs->frmctr1,
ILI9342C_FRMCTR1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->invtr, ILI9342C_INVTR_LEN, "INVTR");
r = ili9xxx_transmit(dev, ILI9342C_INVTR, regs->invtr,
ILI9342C_INVTR_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->disctrl, ILI9342C_DISCTRL_LEN, "DISCTRL");
r = ili9xxx_transmit(dev, ILI9342C_DISCTRL, regs->disctrl,
ILI9342C_DISCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->etmod, ILI9342C_ETMOD_LEN, "ETMOD");
r = ili9xxx_transmit(dev, ILI9342C_ETMOD, regs->etmod,
ILI9342C_ETMOD_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9342C_PWCTRL1_LEN, "PWCTRL1");
r = ili9xxx_transmit(dev, ILI9342C_PWCTRL1, regs->pwctrl1,
ILI9342C_PWCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9342C_PWCTRL2_LEN, "PWCTRL2");
r = ili9xxx_transmit(dev, ILI9342C_PWCTRL2, regs->pwctrl2,
ILI9342C_PWCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl3, ILI9342C_PWCTRL3_LEN, "PWCTRL3");
r = ili9xxx_transmit(dev, ILI9342C_PWCTRL3, regs->pwctrl3,
ILI9342C_PWCTRL3_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl1, ILI9342C_VMCTRL1_LEN, "VMCTRL1");
r = ili9xxx_transmit(dev, ILI9342C_VMCTRL1, regs->vmctrl1,
ILI9342C_VMCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9342C_PGAMCTRL_LEN, "PGAMCTRL");
r = ili9xxx_transmit(dev, ILI9342C_PGAMCTRL, regs->pgamctrl,
ILI9342C_PGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9342C_NGAMCTRL_LEN, "NGAMCTRL");
r = ili9xxx_transmit(dev, ILI9342C_NGAMCTRL, regs->ngamctrl,
ILI9342C_NGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ifctl, ILI9342C_IFCTL_LEN, "IFCTL");
r = ili9xxx_transmit(dev, ILI9342C_IFCTL, regs->ifctl,
ILI9342C_IFCTL_LEN);
if (r < 0) {
return r;
}
return 0;
}
``` | /content/code_sandbox/drivers/display/display_ili9342c.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,154 |
```c
/*
*
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <SDL.h>
#include "nsi_tracing.h"
int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct,
bool use_accelerator, void **window, void **renderer, void **mutex,
void **texture, void **read_texture)
{
*window = SDL_CreateWindow("Zephyr Display", SDL_WINDOWPOS_UNDEFINED,
SDL_WINDOWPOS_UNDEFINED, width * zoom_pct / 100,
height * zoom_pct / 100, SDL_WINDOW_SHOWN);
if (*window == NULL) {
nsi_print_warning("Failed to create SDL window: %s", SDL_GetError());
return -1;
}
if (use_accelerator) {
*renderer = SDL_CreateRenderer(*window, -1, SDL_RENDERER_ACCELERATED);
} else {
*renderer = SDL_CreateRenderer(*window, -1, SDL_RENDERER_SOFTWARE);
}
if (*renderer == NULL) {
nsi_print_warning("Failed to create SDL renderer: %s",
SDL_GetError());
return -1;
}
*mutex = SDL_CreateMutex();
if (*mutex == NULL) {
nsi_print_warning("Failed to create SDL mutex: %s", SDL_GetError());
return -1;
}
SDL_RenderSetLogicalSize(*renderer, width, height);
*texture = SDL_CreateTexture(*renderer, SDL_PIXELFORMAT_ARGB8888,
SDL_TEXTUREACCESS_STATIC, width, height);
if (*texture == NULL) {
nsi_print_warning("Failed to create SDL texture: %s", SDL_GetError());
return -1;
}
*read_texture = SDL_CreateTexture(*renderer, SDL_PIXELFORMAT_ARGB8888,
SDL_TEXTUREACCESS_TARGET, width, height);
if (*read_texture == NULL) {
nsi_print_warning("Failed to create SDL texture for read: %s", SDL_GetError());
return -1;
}
SDL_SetRenderDrawColor(*renderer, 0, 0, 0, 0xFF);
SDL_RenderClear(*renderer);
SDL_RenderPresent(*renderer);
return 0;
}
void sdl_display_write_bottom(const uint16_t height, const uint16_t width,
const uint16_t x, const uint16_t y,
void *renderer, void *mutex, void *texture,
uint8_t *buf, bool display_on)
{
SDL_Rect rect;
int err;
rect.x = x;
rect.y = y;
rect.w = width;
rect.h = height;
err = SDL_TryLockMutex(mutex);
if (err) {
nsi_print_warning("Failed to lock SDL mutex: %s", SDL_GetError());
return;
}
SDL_UpdateTexture(texture, &rect, buf, 4 * rect.w);
if (display_on) {
SDL_RenderClear(renderer);
SDL_RenderCopy(renderer, texture, NULL, NULL);
SDL_RenderPresent(renderer);
}
SDL_UnlockMutex(mutex);
}
int sdl_display_read_bottom(const uint16_t height, const uint16_t width,
const uint16_t x, const uint16_t y,
void *renderer, void *buf, uint16_t pitch,
void *mutex, void *texture, void *read_texture)
{
SDL_Rect rect;
int err;
rect.x = x;
rect.y = y;
rect.w = width;
rect.h = height;
err = SDL_TryLockMutex(mutex);
if (err) {
nsi_print_warning("Failed to lock SDL mutex: %s", SDL_GetError());
return -1;
}
SDL_SetRenderTarget(renderer, read_texture);
SDL_RenderClear(renderer);
SDL_RenderCopy(renderer, texture, NULL, NULL);
SDL_RenderReadPixels(renderer, &rect, SDL_PIXELFORMAT_ARGB8888, buf, width * 4);
SDL_SetRenderTarget(renderer, NULL);
SDL_UnlockMutex(mutex);
return err;
}
void sdl_display_blanking_off_bottom(void *renderer, void *texture)
{
SDL_RenderClear(renderer);
SDL_RenderCopy(renderer, texture, NULL, NULL);
SDL_RenderPresent(renderer);
}
void sdl_display_blanking_on_bottom(void *renderer)
{
SDL_RenderClear(renderer);
SDL_RenderPresent(renderer);
}
void sdl_display_cleanup_bottom(void **window, void **renderer, void **mutex, void **texture,
void **read_texture)
{
if (*read_texture != NULL) {
SDL_DestroyTexture(*read_texture);
*read_texture = NULL;
}
if (*texture != NULL) {
SDL_DestroyTexture(*texture);
*texture = NULL;
}
if (*mutex != NULL) {
SDL_DestroyMutex(*mutex);
*mutex = NULL;
}
if (*renderer != NULL) {
SDL_DestroyRenderer(*renderer);
*renderer = NULL;
}
if (*window != NULL) {
SDL_DestroyWindow(*window);
*window = NULL;
}
}
``` | /content/code_sandbox/drivers/display/display_sdl_bottom.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,038 |
```unknown
# SSD1306 display controller configuration options
menuconfig SSD1306
bool "SSD1306 display driver"
default y
depends on DT_HAS_SOLOMON_SSD1306FB_ENABLED || DT_HAS_SINOWEALTH_SH1106_ENABLED
select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1306FB),i2c)
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1306FB),spi)
select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1106),i2c)
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1106),spi)
help
Enable driver for SSD1306 display driver.
if SSD1306
config SSD1306_DEFAULT_CONTRAST
int "SSD1306 default contrast"
default 128
range 0 $(UINT8_MAX)
help
SSD1306 default contrast.
endif # SSD1306
``` | /content/code_sandbox/drivers/display/Kconfig.ssd1306 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 217 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_smartbond_display
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
#include <zephyr/drivers/display.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/dma.h>
#include <da1469x_lcdc.h>
#include <DA1469xAB.h>
#include <da1469x_pd.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(smartbond_display, CONFIG_DISPLAY_LOG_LEVEL);
#define SMARTBOND_IRQN DT_INST_IRQN(0)
#define SMARTBOND_IRQ_PRIO DT_INST_IRQ(0, priority)
#define LCDC_SMARTBOND_CLK_DIV(_freq) \
((32000000U % (_freq)) ? (96000000U / (_freq)) : (32000000U / (_freq)))
#define LCDC_SMARTBOND_IS_PLL_REQUIRED \
!!(32000000U % DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency))
#define DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED \
DT_INST_ENUM_IDX_OR(0, dma_prefetch, 0)
#define LCDC_LAYER0_OFFSETX_REG_SET_FIELD(_field, _var, _val)\
((_var)) = \
((_var) & ~(LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)) | \
(((_val) << LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Pos) & \
LCDC_LCDC_LAYER0_OFFSETX_REG_ ## _field ## _Msk)
#define DISPLAY_SMARTBOND_PIXEL_SIZE(inst) \
(DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(inst, pixel_format)) / 8)
#if CONFIG_DISPLAY_RENESAS_LCDC_BUFFER_PSRAM
#define DISPLAY_BUFFER_LINKER_SECTION \
Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(psram)))
#else
#define DISPLAY_BUFFER_LINKER_SECTION
#endif
struct display_smartbond_data {
/* Provide mutual exclusion when a display operation is requested. */
struct k_sem device_sem;
/* Frame update synchronization token */
struct k_sem sync_sem;
/* Flag indicating whether or not an underflow took place */
volatile bool underflow_flag;
/* Layer settings */
lcdc_smartbond_layer_cfg layer;
/* Frame buffer */
uint8_t *buffer;
/* DMA device */
const struct device *dma;
/* DMA configuration structures */
struct dma_config dma_cfg;
struct dma_block_config dma_block_cfg;
/* DMA memory transfer synchronization token */
struct k_sem dma_sync_sem;
/* Granted DMA channel used for memory transfers */
int dma_channel;
#if defined(CONFIG_PM_DEVICE)
ATOMIC_DEFINE(pm_policy_state_flag, 1);
#endif
};
struct display_smartbond_config {
/* Reference to device instance's pinctrl configurations */
const struct pinctrl_dev_config *pcfg;
/* Display ON/OFF GPIO */
const struct gpio_dt_spec disp;
/* Host controller's timing settings */
lcdc_smartbond_timing_cfg timing_cfg;
/* Parallel interface settings */
lcdc_smartbond_mode_cfg mode;
/* Background default color configuration */
lcdc_smartbond_bgcolor_cfg bgcolor_cfg;
/* Display dimensions */
const uint16_t x_res;
const uint16_t y_res;
/* Pixel size in bytes */
uint8_t pixel_size;
enum display_pixel_format pixel_format;
};
static inline void lcdc_smartbond_pm_policy_state_lock_get(struct display_smartbond_data *data)
{
#ifdef CONFIG_PM_DEVICE
if (atomic_test_and_set_bit(data->pm_policy_state_flag, 0) == 0) {
/*
* Prevent the SoC from etering the normal sleep state as PDC does not support
* waking up the application core following LCDC events.
*/
pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
#endif
}
static inline void lcdc_smartbond_pm_policy_state_lock_put(struct display_smartbond_data *data)
{
#ifdef CONFIG_PM_DEVICE
if (atomic_test_and_clear_bit(data->pm_policy_state_flag, 0) == 1) {
/* Allow the SoC to enter the nornmal sleep state once LCDC is inactive */
pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
}
#endif
}
/* Display pixel to layer color format translation */
static uint8_t lcdc_smartbond_pixel_to_lcm(enum display_pixel_format pixel_format)
{
switch (pixel_format) {
case PIXEL_FORMAT_RGB_565:
return (uint8_t)LCDC_SMARTBOND_L0_RGB565;
case PIXEL_FORMAT_ARGB_8888:
return (uint8_t)LCDC_SMARTBOND_L0_ARGB8888;
default:
LOG_ERR("Unsupported pixel format");
return 0;
};
}
static int display_smartbond_configure(const struct device *dev)
{
uint8_t clk_div =
LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency));
const struct display_smartbond_config *config = dev->config;
struct display_smartbond_data *data = dev->data;
int ret = 0;
/* First enable the controller so registers can be written. */
da1469x_lcdc_set_status(true, LCDC_SMARTBOND_IS_PLL_REQUIRED, clk_div);
if (!da1469x_lcdc_check_id()) {
LOG_ERR("Invalid LCDC ID");
da1469x_lcdc_set_status(false, false, 0);
return -EINVAL;
}
da1469x_lcdc_parallel_interface_configure((lcdc_smartbond_mode_cfg *)&config->mode);
da1469x_lcdc_bgcolor_configure((lcdc_smartbond_bgcolor_cfg *)&config->bgcolor_cfg);
/*
* Partial update is not supported and so timing and layer settings can be configured
* once at initialization.
*/
ret = da1469x_lcdc_timings_configure(config->x_res, config->y_res,
(lcdc_smartbond_timing_cfg *)&config->timing_cfg);
if (ret < 0) {
LOG_ERR("Unable to configure timing settings");
da1469x_lcdc_set_status(false, false, 0);
return ret;
}
/*
* Stride should be updated at the end of a frame update (typically in ISR context).
* It's OK to update stride here as continuous mode should not be enabled yet.
*/
data->layer.color_format =
lcdc_smartbond_pixel_to_lcm(config->pixel_format);
data->layer.stride =
da1469x_lcdc_stride_calculation(data->layer.color_format, config->x_res);
ret = da1469x_lcdc_layer_configure(&data->layer);
if (ret < 0) {
LOG_ERR("Unable to configure layer settings");
da1469x_lcdc_set_status(false, false, 0);
}
LCDC_LAYER0_OFFSETX_REG_SET_FIELD(LCDC_L0_DMA_PREFETCH,
LCDC->LCDC_LAYER0_OFFSETX_REG, DISPLAY_SMARTBOND_IS_DMA_PREFETCH_ENABLED);
LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_MODE_EN_Msk;
return ret;
}
static void smartbond_display_isr(const void *arg)
{
struct display_smartbond_data *data = ((const struct device *)arg)->data;
data->underflow_flag = LCDC_STATUS_REG_GET_FIELD(LCDC_STICKY_UNDERFLOW);
/*
* Underflow sticky bit will remain high until cleared by writing
* any value to LCDC_INTERRUPT_REG.
*/
LCDC->LCDC_INTERRUPT_REG &= ~LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk;
/* Notify that current frame update is completed */
k_sem_give(&data->sync_sem);
}
static void display_smartbond_dma_cb(const struct device *dma, void *arg,
uint32_t id, int status)
{
struct display_smartbond_data *data = arg;
if (status < 0) {
LOG_WRN("DMA transfer did not complete");
}
k_sem_give(&data->dma_sync_sem);
}
static int display_smartbond_dma_config(const struct device *dev)
{
struct display_smartbond_data *data = dev->data;
data->dma = DEVICE_DT_GET(DT_NODELABEL(dma));
if (!device_is_ready(data->dma)) {
LOG_ERR("DMA device is not ready");
return -ENODEV;
}
data->dma_cfg.channel_direction = MEMORY_TO_MEMORY;
data->dma_cfg.user_data = data;
data->dma_cfg.dma_callback = display_smartbond_dma_cb;
data->dma_cfg.block_count = 1;
data->dma_cfg.head_block = &data->dma_block_cfg;
data->dma_cfg.error_callback_dis = 1;
/* Request an arbitrary DMA channel */
data->dma_channel = dma_request_channel(data->dma, NULL);
if (data->dma_channel < 0) {
LOG_ERR("Could not acquire a DMA channel");
return -EIO;
}
return 0;
}
static int display_smartbond_resume(const struct device *dev)
{
const struct display_smartbond_config *config = dev->config;
int ret;
/* Select default state */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("Could not apply LCDC pins' default state (%d)", ret);
return -EIO;
}
#if LCDC_SMARTBOND_IS_PLL_REQUIRED
const struct device *clock_dev = DEVICE_DT_GET(DT_NODELABEL(osc));
if (!device_is_ready(clock_dev)) {
LOG_WRN("Clock device is not ready");
return -ENODEV;
}
ret = z_smartbond_select_sys_clk(SMARTBOND_CLK_PLL96M);
if (ret < 0) {
LOG_WRN("Could not switch to PLL");
return -EIO;
}
#endif
ret = display_smartbond_dma_config(dev);
if (ret < 0) {
return ret;
}
return display_smartbond_configure(dev);
}
#if defined(CONFIG_PM_DEVICE)
static void display_smartbond_dma_deconfig(const struct device *dev)
{
struct display_smartbond_data *data = dev->data;
__ASSERT(data->dma, "DMA should be already initialized");
dma_release_channel(data->dma, data->dma_channel);
}
static int display_smartbond_suspend(const struct device *dev)
{
const struct display_smartbond_config *config = dev->config;
int ret;
/* Select sleep state; it's OK if settings fails for any reason */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
LOG_WRN("Could not apply DISPLAY pins' sleep state");
}
/* Disable host controller to minimize power consumption */
da1469x_lcdc_set_status(false, false, 0);
display_smartbond_dma_deconfig(dev);
return 0;
}
#endif
static int display_smartbond_init(const struct device *dev)
{
const struct display_smartbond_config *config = dev->config;
struct display_smartbond_data *data = dev->data;
int ret;
/* Device should be ready to be acquired */
k_sem_init(&data->device_sem, 1, 1);
/* Event should be signaled by LCDC ISR */
k_sem_init(&data->sync_sem, 0, 1);
/* Event should be signaled by DMA ISR */
k_sem_init(&data->dma_sync_sem, 0, 1);
/* As per docs, display port should be enabled by default. */
if (gpio_is_ready_dt(&config->disp)) {
ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not activate display port");
return -EIO;
}
}
IRQ_CONNECT(SMARTBOND_IRQN, SMARTBOND_IRQ_PRIO, smartbond_display_isr,
DEVICE_DT_INST_GET(0), 0);
/*
* Currently, there is no API to explicitly enable/disable the display controller.
* At the same time, the controller is set to continuous mode meaning that
* as long as a display panel is turned on, frame updates should happen all
* the time (otherwise contents on the display pane will be lost as the latter
* does not integrate an SDRAM memory to keep its frame).
* As such, resume/suspend operations are bound to blanking operations.
* That is, when the display is blanked on we can safely consider that display
* is no longer functional and thus, the controller can be suspended (allowing the
* SoC to enter the sleep state). Once the display is blanked off, then we consider
* that the controller should be resumed and sleep should be prevented at all
* (this is because the controller is powered by the same power domain used to
* power the application core). Side effect of the above is that the controller
* should be configured at initialization phase as display operations might
* be requested before the display is blanked off for the very first time.
*/
ret = display_smartbond_resume(dev);
if (ret == 0) {
/* Display port should be enabled at this moment and so sleep is not allowed. */
lcdc_smartbond_pm_policy_state_lock_get(data);
}
return ret;
}
static int display_smartbond_blanking_on(const struct device *dev)
{
const struct display_smartbond_config *config = dev->config;
struct display_smartbond_data *data = dev->data;
int ret = 0;
k_sem_take(&data->device_sem, K_FOREVER);
/*
* This bit will force LCD controller's output to blank that is,
* the controller will keep operating without outputting any
* pixel data.
*/
LCDC->LCDC_MODE_REG |= LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk;
/* If enabled, disable display port. */
if (gpio_is_ready_dt(&config->disp)) {
ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_WRN("Display port could not be de-activated");
}
}
/*
* At this moment the display panel should be turned off and so the device
* can enter the suspend state.
*/
lcdc_smartbond_pm_policy_state_lock_put(data);
k_sem_give(&data->device_sem);
return ret;
}
static int display_smartbond_blanking_off(const struct device *dev)
{
const struct display_smartbond_config *config = dev->config;
struct display_smartbond_data *data = dev->data;
int ret = 0;
k_sem_take(&data->device_sem, K_FOREVER);
/* If used, enable display port */
if (gpio_is_ready_dt(&config->disp)) {
ret = gpio_pin_configure_dt(&config->disp, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_WRN("Display port could not be activated");
}
}
/*
* This bit will force LCD controller's output to blank that is,
* the controller will keep operating without outputting any
* pixel data.
*/
LCDC->LCDC_MODE_REG &= ~LCDC_LCDC_MODE_REG_LCDC_FORCE_BLANK_Msk;
/*
* At this moment the display should be turned on and so the device
* cannot enter the suspend state.
*/
lcdc_smartbond_pm_policy_state_lock_get(data);
k_sem_give(&data->device_sem);
return ret;
}
static void *display_smartbond_get_framebuffer(const struct device *dev)
{
struct display_smartbond_data *data = dev->data;
return ((void *)data->buffer);
}
static void display_smartbond_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
memset(capabilities, 0, sizeof(*capabilities));
/*
* Multiple color formats should be supported by LCDC. Currently, RGB56 and ARGB888
* exposed by display API are supported. In the future we should consider supporting
* more color formats which should require changes in LVGL porting.
* Here, only one color format should be supported as the frame buffer is accessed
* directly by LCDC and is allocated statically during device initialization. The color
* format is defined based on the pixel-format property dictated by lcd-controller
* bindings.
*/
capabilities->supported_pixel_formats = DT_INST_PROP(0, pixel_format);
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
capabilities->current_pixel_format = DT_INST_PROP(0, pixel_format);
capabilities->x_resolution = DT_INST_PROP(0, width);
capabilities->y_resolution = DT_INST_PROP(0, height);
}
static int display_smartbond_read(const struct device *dev,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
struct display_smartbond_data *data = dev->data;
const struct display_smartbond_config *config = dev->config;
uint8_t *dst = buf;
const uint8_t *src = data->buffer;
k_sem_take(&data->device_sem, K_FOREVER);
/* pointer to upper left pixel of the rectangle */
src += (x * config->pixel_size);
src += (y * data->layer.stride);
data->dma_block_cfg.block_size = desc->width * config->pixel_size;
/*
* Source and destination base address is word aligned.
* Data size should be selected based on color depth as
* cursor is shifted multiple of pixel color depth.
*/
data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size =
!(config->pixel_size & 3) ? 4 :
!(config->pixel_size & 1) ? 2 : 1;
data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length =
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 :
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1;
for (int row = 0; row < desc->height; row++) {
data->dma_block_cfg.dest_address = (uint32_t)dst;
data->dma_block_cfg.source_address = (uint32_t)src;
if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) {
LOG_ERR("Could not configure DMA");
k_sem_give(&data->device_sem);
return -EIO;
}
if (dma_start(data->dma, data->dma_channel)) {
LOG_ERR("Could not start DMA");
k_sem_give(&data->device_sem);
return -EIO;
}
k_sem_take(&data->dma_sync_sem, K_FOREVER);
src += data->layer.stride;
dst += (desc->pitch * config->pixel_size);
}
if (dma_stop(data->dma, data->dma_channel)) {
LOG_WRN("Could not stop DMA");
}
k_sem_give(&data->device_sem);
return 0;
}
static int display_smartbond_write(const struct device *dev,
const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
struct display_smartbond_data *data = dev->data;
const struct display_smartbond_config *config = dev->config;
uint8_t *dst = data->buffer;
const uint8_t *src = buf;
k_sem_take(&data->device_sem, K_FOREVER);
/* pointer to upper left pixel of the rectangle */
dst += (x * config->pixel_size);
dst += (y * data->layer.stride);
/*
* Wait for the current frame to finish. Do not disable continuous mode as this
* will have visual artifacts.
*/
LCDC->LCDC_INTERRUPT_REG |= LCDC_LCDC_INTERRUPT_REG_LCDC_VSYNC_IRQ_EN_Msk;
k_sem_take(&data->sync_sem, K_FOREVER);
data->dma_block_cfg.block_size = desc->width * config->pixel_size;
/*
* Source and destination base address is word aligned.
* Data size should be selected based on color depth as
* cursor is shifted multiple of pixel color depth.
*/
data->dma_cfg.source_data_size = data->dma_cfg.dest_data_size =
!(config->pixel_size & 3) ? 4 :
!(config->pixel_size & 1) ? 2 : 1;
data->dma_cfg.dest_burst_length = data->dma_cfg.source_burst_length =
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 7) ? 8 :
!((data->dma_block_cfg.block_size / data->dma_cfg.source_data_size) & 3) ? 4 : 1;
for (int row = 0; row < desc->height; row++) {
data->dma_block_cfg.dest_address = (uint32_t)dst;
data->dma_block_cfg.source_address = (uint32_t)src;
if (dma_config(data->dma, data->dma_channel, &data->dma_cfg)) {
LOG_ERR("Could not configure DMA");
k_sem_give(&data->device_sem);
return -EIO;
}
if (dma_start(data->dma, data->dma_channel)) {
LOG_ERR("Could not start DMA");
k_sem_give(&data->device_sem);
return -EIO;
}
k_sem_take(&data->dma_sync_sem, K_FOREVER);
dst += data->layer.stride;
src += (desc->pitch * config->pixel_size);
}
if (dma_stop(data->dma, data->dma_channel)) {
LOG_WRN("Could not stop DMA");
}
k_sem_give(&data->device_sem);
return 0;
}
#if defined(CONFIG_PM_DEVICE)
static int display_smartbond_pm_action(const struct device *dev, enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
/* A non-zero value should not affect sleep */
(void)display_smartbond_suspend(dev);
break;
case PM_DEVICE_ACTION_RESUME:
/*
* The resume error code should not be taken into consideration
* by the PM subsystem
*/
ret = display_smartbond_resume(dev);
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif
static const struct display_driver_api display_smartbond_driver_api = {
.write = display_smartbond_write,
.read = display_smartbond_read,
.get_framebuffer = display_smartbond_get_framebuffer,
.get_capabilities = display_smartbond_get_capabilities,
.blanking_off = display_smartbond_blanking_off,
.blanking_on = display_smartbond_blanking_on
};
#define SMARTBOND_DISPLAY_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
PM_DEVICE_DT_INST_DEFINE(inst, display_smartbond_pm_action); \
\
__aligned(4) static uint8_t buffer_ ## inst[(((DT_INST_PROP(inst, width) * \
DISPLAY_SMARTBOND_PIXEL_SIZE(inst)) + 0x3) & ~0x3) * \
DT_INST_PROP(inst, height)] DISPLAY_BUFFER_LINKER_SECTION; \
\
static const struct display_smartbond_config display_smartbond_config_## inst = { \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.disp = GPIO_DT_SPEC_INST_GET_OR(inst, disp_gpios, {}), \
.timing_cfg.vsync_len = \
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len), \
.timing_cfg.hsync_len = \
DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len), \
.timing_cfg.hfront_porch = \
DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch), \
.timing_cfg.vfront_porch = \
DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch), \
.timing_cfg.hback_porch = \
DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch), \
.timing_cfg.vback_porch = \
DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch), \
.bgcolor_cfg = {0xFF, 0xFF, 0xFF, 0}, \
.x_res = DT_INST_PROP(inst, width), \
.y_res = DT_INST_PROP(inst, height), \
.pixel_size = DISPLAY_SMARTBOND_PIXEL_SIZE(inst), \
.pixel_format = DT_INST_PROP(0, pixel_format), \
.mode.vsync_pol = \
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
.mode.hsync_pol = \
DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
.mode.de_pol = \
DT_PROP(DT_INST_CHILD(inst, display_timings), de_active) ? 0 : 1, \
.mode.pixelclk_pol = \
DT_PROP(DT_INST_CHILD(inst, display_timings), pixelclk_active) ? 0 : 1, \
}; \
\
static struct display_smartbond_data display_smartbond_data_## inst = { \
.buffer = buffer_ ##inst, \
.layer.start_x = 0, \
.layer.start_y = 0, \
.layer.size_x = DT_INST_PROP(inst, width), \
.layer.size_y = DT_INST_PROP(inst, height), \
.layer.frame_buf = (uint32_t)buffer_ ## inst, \
}; \
\
\
DEVICE_DT_INST_DEFINE(inst, display_smartbond_init, PM_DEVICE_DT_INST_GET(inst), \
&display_smartbond_data_## inst, \
&display_smartbond_config_## inst, \
POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, \
&display_smartbond_driver_api);
SMARTBOND_DISPLAY_INIT(0);
``` | /content/code_sandbox/drivers/display/display_renesas_lcdc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,776 |
```objective-c
/*
*
*/
#ifndef ST7789V_DISPLAY_DRIVER_H__
#define ST7789V_DISPLAY_DRIVER_H__
#include <zephyr/kernel.h>
#define ST7789V_CMD_NOP 0x00
#define ST7789V_CMD_SW_RESET 0x01
#define ST7789V_CMD_SLEEP_IN 0x10
#define ST7789V_CMD_SLEEP_OUT 0x11
#define ST7789V_CMD_INV_OFF 0x20
#define ST7789V_CMD_INV_ON 0x21
#define ST7789V_CMD_GAMSET 0x26
#define ST7789V_CMD_DISP_OFF 0x28
#define ST7789V_CMD_DISP_ON 0x29
#define ST7789V_CMD_CASET 0x2a
#define ST7789V_CMD_RASET 0x2b
#define ST7789V_CMD_RAMWR 0x2c
#define ST7789V_CMD_MADCTL 0x36
#define ST7789V_MADCTL_MY_TOP_TO_BOTTOM 0x00
#define ST7789V_MADCTL_MY_BOTTOM_TO_TOP 0x80
#define ST7789V_MADCTL_MX_LEFT_TO_RIGHT 0x00
#define ST7789V_MADCTL_MX_RIGHT_TO_LEFT 0x40
#define ST7789V_MADCTL_MV_REVERSE_MODE 0x20
#define ST7789V_MADCTL_MV_NORMAL_MODE 0x00
#define ST7789V_MADCTL_ML 0x10
#define ST7789V_MADCTL_RBG 0x00
#define ST7789V_MADCTL_BGR 0x08
#define ST7789V_MADCTL_MH_LEFT_TO_RIGHT 0x00
#define ST7789V_MADCTL_MH_RIGHT_TO_LEFT 0x04
#define ST7789V_CMD_COLMOD 0x3a
#define ST7789V_COLMOD_RGB_65K (0x5 << 4)
#define ST7789V_COLMOD_RGB_262K (0x6 << 4)
#define ST7789V_COLMOD_FMT_12bit (3)
#define ST7789V_COLMOD_FMT_16bit (5)
#define ST7789V_COLMOD_FMT_18bit (6)
#define ST7789V_CMD_RAMCTRL 0xb0
#define ST7789V_CMD_RGBCTRL 0xb1
#define ST7789V_CMD_PORCTRL 0xb2
#define ST7789V_CMD_CMD2EN 0xdf
#define ST7789V_CMD_DGMEN 0xba
#define ST7789V_CMD_GCTRL 0xb7
#define ST7789V_CMD_VCOMS 0xbb
#define ST7789V_CMD_LCMCTRL 0xc0
#define ST7789V_LCMCTRL_XMY 0x40
#define ST7789V_LCMCTRL_XBGR 0x20
#define ST7789V_LCMCTRL_XINV 0x10
#define ST7789V_LCMCTRL_XMX 0x08
#define ST7789V_LCMCTRL_XMH 0x04
#define ST7789V_LCMCTRL_XMV 0x02
#define ST7789V_CMD_VDVVRHEN 0xc2
#define ST7789V_CMD_VRH 0xc3
#define ST7789V_CMD_VDS 0xc4
#define ST7789V_CMD_FRCTRL2 0xc6
#define ST7789V_CMD_PWCTRL1 0xd0
#define ST7789V_CMD_PVGAMCTRL 0xe0
#define ST7789V_CMD_NVGAMCTRL 0xe1
#endif
``` | /content/code_sandbox/drivers/display/display_st7789v.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 836 |
```c
/*
*
*/
#define DT_DRV_COMPAT himax_hx8394
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(hx8394, CONFIG_DISPLAY_LOG_LEVEL);
struct hx8394_config {
const struct device *mipi_dsi;
const struct gpio_dt_spec reset_gpio;
const struct gpio_dt_spec bl_gpio;
uint8_t num_of_lanes;
uint8_t pixel_format;
uint16_t panel_width;
uint16_t panel_height;
uint8_t channel;
};
/* MIPI DCS commands specific to this display driver */
#define HX8394_SETMIPI 0xBA
#define HX8394_MIPI_LPTX_BTA_READ BIT(6)
#define HX8394_MIPI_LP_CD_DIS BIT(5)
#define HX8394_MIPI_TA_6TL 0x3
#define HX8394_MIPI_DPHYCMD_LPRX_8NS 0x40
#define HX8394_MIPI_DPHYCMD_LPRX_66mV 0x20
#define HX8394_MIPI_DPHYCMD_LPTX_SRLIM 0x8
#define HX8394_MIPI_DPHYCMD_LDO_1_55V 0x60
#define HX8394_MIPI_DPHYCMD_HSRX_7X 0x8
#define HX8394_MIPI_DPHYCMD_HSRX_100OHM 0x2
#define HX8394_MIPI_DPHYCMD_LPCD_1X 0x1
#define HX8394_SET_ADDRESS 0x36
#define HX8394_FLIP_HORIZONTAL BIT(1)
#define HX8394_FLIP_VERTICAL BIT(0)
#define HX8394_SETPOWER 0xB1
#define HX8394_POWER_AP_1_0UA 0x8
#define HX8394_POWER_HX5186 0x40
#define HX8394_POWER_VRHP_4_8V 0x12
#define HX8394_POWER_VRHN_4_8V 0x12
#define HX8394_POWER_VPPS_8_25V 0x60
#define HX8394_POWER_XDK_X2 0x1
#define HX8394_POWER_VSP_FBOFF 0x8
#define HX8394_POWER_FS0_DIV_8 0x2
#define HX8394_POWER_CLK_OPT_VGH_HSYNC_RST 0x10
#define HX8394_POWER_CLK_OPT_VGL_HSYNC_RST 0x20
#define HX8394_POWER_FS2_DIV_192 0x4
#define HX8394_POWER_FS1_DIV_224 0x50
#define HX8394_POWER_BTP_5_55V 0x11
#define HX8394_POWER_VGH_RATIO_2VSPVSN 0x60
#define HX8394_POWER_BTN_5_55V 0x11
#define HX8394_POWER_VGL_RATIO_2VSPVSN 0x60
#define HX8394_POWER_VGHS_16V 0x57
#define HX8394_POWER_VGLS_12_4V 0x47
#define HX8394_SETDISP 0xB2
#define HX8394_DISP_COL_INV 0x0
#define HX8394_DISP_MESSI_ENB 0x80
#define HX8394_DISP_NL_1280 0x64
#define HX8394_DISP_BP_14 0xC
#define HX8394_DISP_FP_15 0xD
#define HX8394_DISP_RTN_144 0x2F
#define HX8394_SETCYC 0xB4
#define HX8394_SETGIP0 0xD3
#define HX8394_GIP0_EQ_OPT_BOTH 0x0
#define HX8394_GIP0_EQ_HSYNC_NORMAL 0x0
#define HX8394_GIP0_EQ_VSEL_VSSA 0x0
#define HX8394_SHP_START_4 0x40
#define HX8394_SCP_WIDTH_7X_HSYNC 0x7
#define HX8394_CHR0_12X_HSYNC 0xA
#define HX8394_CHR1_18X_HSYNC 0x10
#define HX8394_SETGIP1 0xD5
#define HX8394_SETGIP2 0xD6
#define HX8394_SETVCOM 0xB6
#define HX8394_VCMC_F_1_76V 0x92
#define HX8394_VCMC_B_1_76V 0x92
#define HX8394_SETGAMMA 0xE0
#define HX8394_SETPANEL 0xCC
#define HX8394_COLOR_BGR BIT(0)
#define HX8394_REV_PANEL BIT(1)
#define HX8394_SETBANK 0xBD
#define HX8394_SET_TEAR 0x35
#define HX8394_TEAR_VBLANK 0x0
#define HX8394_SETEXTC 0xB9
#define HX8394_EXTC1_MAGIC 0xFF
#define HX8394_EXTC2_MAGIC 0x83
#define HX8394_EXTC3_MAGIC 0x94
const uint8_t enable_extension[] = {
HX8394_SETEXTC,
HX8394_EXTC1_MAGIC,
HX8394_EXTC2_MAGIC,
HX8394_EXTC3_MAGIC,
};
const uint8_t address_config[] = {
HX8394_SET_ADDRESS,
HX8394_FLIP_HORIZONTAL
};
const uint8_t power_config[] = {
HX8394_SETPOWER,
(HX8394_POWER_HX5186 | HX8394_POWER_AP_1_0UA),
HX8394_POWER_VRHP_4_8V,
(HX8394_POWER_VPPS_8_25V | HX8394_POWER_VRHN_4_8V),
(HX8394_POWER_VSP_FBOFF | HX8394_POWER_XDK_X2),
(HX8394_POWER_CLK_OPT_VGL_HSYNC_RST |
HX8394_POWER_CLK_OPT_VGH_HSYNC_RST |
HX8394_POWER_FS0_DIV_8),
(HX8394_POWER_FS1_DIV_224 | HX8394_POWER_FS2_DIV_192),
(HX8394_POWER_VGH_RATIO_2VSPVSN | HX8394_POWER_BTP_5_55V),
(HX8394_POWER_VGL_RATIO_2VSPVSN | HX8394_POWER_BTN_5_55V),
HX8394_POWER_VGHS_16V,
HX8394_POWER_VGLS_12_4V
};
const uint8_t line_config[] = {
HX8394_SETDISP,
HX8394_DISP_COL_INV,
HX8394_DISP_MESSI_ENB,
HX8394_DISP_NL_1280,
HX8394_DISP_BP_14,
HX8394_DISP_FP_15,
HX8394_DISP_RTN_144
};
const uint8_t cycle_config[] = {
HX8394_SETCYC,
0x73, /* SPON delay */
0x74, /* SPOFF delay */
0x73, /* CON delay */
0x74, /* COFF delay */
0x73, /* CON1 delay */
0x74, /* COFF1 delay */
0x1, /* EQON time */
0xC, /* SON time */
0x86, /* SOFF time */
0x75, /* SAP1_P, SAP2 (1st and second stage op amp bias) */
0x00, /* DX2 off, EQ off, EQ_MI off */
0x3F, /* DX2 off period setting */
0x73, /* SPON_MPU delay */
0x74, /* SPOFF_MPU delay */
0x73, /* CON_MPU delay */
0x74, /* COFF_MPU delay */
0x73, /* CON1_MPU delay */
0x74, /* COFF1_MPU delay */
0x1, /* EQON_MPU time */
0xC, /* SON_MPU time */
0x86 /* SOFF_MPU time */
};
const uint8_t gip0_config[] = {
HX8394_SETGIP0,
(HX8394_GIP0_EQ_OPT_BOTH | HX8394_GIP0_EQ_HSYNC_NORMAL),
HX8394_GIP0_EQ_VSEL_VSSA,
0x7, /* EQ_DELAY_ON1 (in cycles of TCON CLK */
0x7, /* EQ_DELAY_OFF1 (in cycles of TCON CLK */
0x40, /* GPWR signal frequency (64x per frame) */
0x7, /* GPWR signal non overlap timing (in cycles of TCON */
0xC, /* GIP dummy clock for first CKV */
0x00, /* GIP dummy clock for second CKV */
/* Group delays. Sets start/end signal delay from VYSNC
* falling edge in multiples of HSYNC
*/
0x8, /* SHR0_2 = 8, SHR0_3 = 0 */
0x10, /* SHR0_1 = 1, SHR0[11:8] = 0x0 */
0x8, /* SHR0 = 0x8 */
0x0, /* SHR0_GS[11:8]. Unset. */
0x8, /* SHR0_GS = 0x8 */
0x54, /* SHR1_3 = 0x5, SHR1_2 = 0x4 */
0x15, /* SHR1_1 = 0x1, SHR1[11:8] = 0x5 */
0xA, /* SHR1[7:0] = 0xA (SHR1 = 0x50A) */
0x5, /* SHR1_GS[11:8] = 0x5 */
0xA, /* SHR1_GS[7:0] = 0xA (SHR1_GS = 0x50A) */
0x2, /* SHR2_3 = 0x0, SHR2_2 = 0x2 */
0x15, /* SHR2_1 = 0x1, SHR2[11:8] = 0x5 */
0x6, /* SHR2[7:0] = 0x6 (SHR2 = 0x506) */
0x5, /* SHR2_GS[11:8] = 0x5 */
0x6, /* SHR2_GS[7:0 = 0x6 (SHR2_GS = 0x506) */
(HX8394_SHP_START_4 | HX8394_SCP_WIDTH_7X_HSYNC),
0x44, /* SHP2 = 0x4, SHP1 = 0x4 */
HX8394_CHR0_12X_HSYNC,
HX8394_CHR0_12X_HSYNC,
0x4B, /* CHP0 = 4x hsync, CCP0 = 0xB */
HX8394_CHR1_18X_HSYNC,
0x7, /* CHR1_GS = 9x hsync */
0x7, /* CHP1 = 1x hsync, CCP1 = 0x7 */
/* These parameters are not documented in datasheet */
0xC,
0x40
};
const uint8_t gip1_config[] = {
HX8394_SETGIP1,
/* Select output clock sources
* See COSn_L/COSn_R values in datasheet
*/
0x1C, /* COS1_L */
0x1C, /* COS1_R */
0x1D, /* COS2_L */
0x1D, /* COS2_R */
0x00, /* COS3_L */
0x01, /* COS3_R */
0x02, /* COS4_L */
0x03, /* COS4_R */
0x04, /* COS5_L */
0x05, /* COS5_R */
0x06, /* COS6_L */
0x07, /* COS6_R */
0x08, /* COS7_L */
0x09, /* COS7_R */
0x0A, /* COS8_L */
0x0B, /* COS8_R */
0x24, /* COS9_L */
0x25, /* COS9_R */
0x18, /* COS10_L */
0x18, /* COS10_R */
0x26, /* COS11_L */
0x27, /* COS11_R */
0x18, /* COS12_L */
0x18, /* COS12_R */
0x18, /* COS13_L */
0x18, /* COS13_R */
0x18, /* COS14_L */
0x18, /* COS14_R */
0x18, /* COS15_L */
0x18, /* COS15_R */
0x18, /* COS16_L */
0x18, /* COS16_R */
0x18, /* COS17_L */
0x18, /* COS17_R */
0x18, /* COS18_L */
0x18, /* COS18_R */
0x18, /* COS19_L */
0x18, /* COS19_R */
0x20, /* COS20_L */
0x21, /* COS20_R */
0x18, /* COS21_L */
0x18, /* COS21_R */
0x18, /* COS22_L */
0x18 /* COS22_R */
};
const uint8_t gip2_config[] = {
HX8394_SETGIP2,
/* Select output clock sources for GS mode.
* See COSn_L_GS/COSn_R_GS values in datasheet
*/
0x1C, /* COS1_L_GS */
0x1C, /* COS1_R_GS */
0x1D, /* COS2_L_GS */
0x1D, /* COS2_R_GS */
0x07, /* COS3_L_GS */
0x06, /* COS3_R_GS */
0x05, /* COS4_L_GS */
0x04, /* COS4_R_GS */
0x03, /* COS5_L_GS */
0x02, /* COS5_R_GS */
0x01, /* COS6_L_GS */
0x00, /* COS6_R_GS */
0x0B, /* COS7_L_GS */
0x0A, /* COS7_R_GS */
0x09, /* COS8_L_GS */
0x08, /* COS8_R_GS */
0x21, /* COS9_L_GS */
0x20, /* COS9_R_GS */
0x18, /* COS10_L_GS */
0x18, /* COS10_R_GS */
0x27, /* COS11_L_GS */
0x26, /* COS11_R_GS */
0x18, /* COS12_L_GS */
0x18, /* COS12_R_GS */
0x18, /* COS13_L_GS */
0x18, /* COS13_R_GS */
0x18, /* COS14_L_GS */
0x18, /* COS14_R_GS */
0x18, /* COS15_L_GS */
0x18, /* COS15_R_GS */
0x18, /* COS16_L_GS */
0x18, /* COS16_R_GS */
0x18, /* COS17_L_GS */
0x18, /* COS17_R_GS */
0x18, /* COS18_L_GS */
0x18, /* COS18_R_GS */
0x18, /* COS19_L_GS */
0x18, /* COS19_R_GS */
0x25, /* COS20_L_GS */
0x24, /* COS20_R_GS */
0x18, /* COS21_L_GS */
0x18, /* COS21_R_GS */
0x18, /* COS22_L_GS */
0x18 /* COS22_R_GS */
};
const uint8_t vcom_config[] = {
HX8394_SETVCOM,
HX8394_VCMC_F_1_76V,
HX8394_VCMC_B_1_76V
};
const uint8_t gamma_config[] = {
HX8394_SETGAMMA,
0x00, /* VHP0 */
0x0A, /* VHP1 */
0x15, /* VHP2 */
0x1B, /* VHP3 */
0x1E, /* VHP4 */
0x21, /* VHP5 */
0x24, /* VHP6 */
0x22, /* VHP7 */
0x47, /* VMP0 */
0x56, /* VMP1 */
0x65, /* VMP2 */
0x66, /* VMP3 */
0x6E, /* VMP4 */
0x82, /* VMP5 */
0x88, /* VMP6 */
0x8B, /* VMP7 */
0x9A, /* VMP8 */
0x9D, /* VMP9 */
0x98, /* VMP10 */
0xA8, /* VMP11 */
0xB9, /* VMP12 */
0x5D, /* VLP0 */
0x5C, /* VLP1 */
0x61, /* VLP2 */
0x66, /* VLP3 */
0x6A, /* VLP4 */
0x6F, /* VLP5 */
0x7F, /* VLP6 */
0x7F, /* VLP7 */
0x00, /* VHN0 */
0x0A, /* VHN1 */
0x15, /* VHN2 */
0x1B, /* VHN3 */
0x1E, /* VHN4 */
0x21, /* VHN5 */
0x24, /* VHN6 */
0x22, /* VHN7 */
0x47, /* VMN0 */
0x56, /* VMN1 */
0x65, /* VMN2 */
0x65, /* VMN3 */
0x6E, /* VMN4 */
0x81, /* VMN5 */
0x87, /* VMN6 */
0x8B, /* VMN7 */
0x98, /* VMN8 */
0x9D, /* VMN9 */
0x99, /* VMN10 */
0xA8, /* VMN11 */
0xBA, /* VMN12 */
0x5D, /* VLN0 */
0x5D, /* VLN1 */
0x62, /* VLN2 */
0x67, /* VLN3 */
0x6B, /* VLN4 */
0x72, /* VLN5 */
0x7F, /* VLN6 */
0x7F /* VLN7 */
};
const uint8_t hx8394_cmd1[] = {0xC0U, 0x1FU, 0x31U};
const uint8_t panel_config[] = {
HX8394_SETPANEL,
(HX8394_COLOR_BGR | HX8394_REV_PANEL)
};
const uint8_t hx8394_cmd2[] = {0xD4, 0x2};
const uint8_t hx8394_bank2[] = {
0xD8U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU,
0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU,
0xFFU
};
const uint8_t hx8394_bank1[] = {0xB1U, 0x00U};
const uint8_t hx8394_bank0[] = {
0xBFU, 0x40U, 0x81U, 0x50U,
0x00U, 0x1AU, 0xFCU, 0x01
};
const uint8_t hx8394_cmd3[] = {0xC6U, 0xEDU};
const uint8_t tear_config[] = {HX8394_SET_TEAR, HX8394_TEAR_VBLANK};
static ssize_t hx8394_mipi_tx(const struct device *mipi_dev, uint8_t channel,
const void *buf, size_t len)
{
/* Send MIPI transfers using low power mode */
struct mipi_dsi_msg msg = {
.tx_buf = buf,
.tx_len = len,
.flags = MIPI_DSI_MSG_USE_LPM,
};
switch (len) {
case 0U:
msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
break;
case 1U:
msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
break;
case 2U:
msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
break;
default:
msg.type = MIPI_DSI_GENERIC_LONG_WRITE;
break;
}
return mipi_dsi_transfer(mipi_dev, channel, &msg);
}
static int hx8394_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
LOG_WRN("Write not supported, use LCD controller display driver");
return 0;
}
static int hx8394_blanking_off(const struct device *dev)
{
const struct hx8394_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 1);
} else {
return -ENOTSUP;
}
}
static int hx8394_blanking_on(const struct device *dev)
{
const struct hx8394_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 0);
} else {
return -ENOTSUP;
}
}
static int hx8394_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
const struct hx8394_config *config = dev->config;
if (pixel_format == config->pixel_format) {
return 0;
}
LOG_WRN("Pixel format change not implemented");
return -ENOTSUP;
}
static int hx8394_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
const struct hx8394_config *config = dev->config;
uint8_t param[2] = {0};
/* Note- this simply flips the scan direction of the display
* driver. Can be useful if your application needs the display
* flipped on the X or Y axis
*/
param[0] = HX8394_SET_ADDRESS;
switch (orientation) {
case DISPLAY_ORIENTATION_NORMAL:
/* Default orientation for this display flips image on x axis */
param[1] = HX8394_FLIP_HORIZONTAL;
break;
case DISPLAY_ORIENTATION_ROTATED_90:
param[1] = HX8394_FLIP_VERTICAL;
break;
case DISPLAY_ORIENTATION_ROTATED_180:
param[1] = 0;
break;
case DISPLAY_ORIENTATION_ROTATED_270:
param[1] = HX8394_FLIP_HORIZONTAL | HX8394_FLIP_VERTICAL;
break;
default:
return -ENOTSUP;
}
return hx8394_mipi_tx(config->mipi_dsi, config->channel, param, 2);
}
static void hx8394_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct hx8394_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->panel_width;
capabilities->y_resolution = config->panel_height;
capabilities->supported_pixel_formats = config->pixel_format;
capabilities->current_pixel_format = config->pixel_format;
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static const struct display_driver_api hx8394_api = {
.blanking_on = hx8394_blanking_on,
.blanking_off = hx8394_blanking_off,
.write = hx8394_write,
.get_capabilities = hx8394_get_capabilities,
.set_pixel_format = hx8394_set_pixel_format,
.set_orientation = hx8394_set_orientation,
};
static int hx8394_init(const struct device *dev)
{
const struct hx8394_config *config = dev->config;
int ret;
struct mipi_dsi_device mdev;
uint8_t param[2];
uint8_t setmipi[7] = {
HX8394_SETMIPI,
(HX8394_MIPI_LPTX_BTA_READ | HX8394_MIPI_LP_CD_DIS),
HX8394_MIPI_TA_6TL,
(HX8394_MIPI_DPHYCMD_LPRX_8NS |
HX8394_MIPI_DPHYCMD_LPRX_66mV |
HX8394_MIPI_DPHYCMD_LPTX_SRLIM),
(HX8394_MIPI_DPHYCMD_LDO_1_55V |
HX8394_MIPI_DPHYCMD_HSRX_7X |
HX8394_MIPI_DPHYCMD_HSRX_100OHM |
HX8394_MIPI_DPHYCMD_LPCD_1X),
/* The remaining parameters here are not documented */
0xB2U, 0xC0U};
mdev.data_lanes = config->num_of_lanes;
mdev.pixfmt = config->pixel_format;
/* HX8394 runs in video mode */
mdev.mode_flags = MIPI_DSI_MODE_VIDEO;
ret = mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev);
if (ret < 0) {
LOG_ERR("Could not attach to MIPI-DSI host");
return ret;
}
if (gpio_is_ready_dt(&config->reset_gpio)) {
/* Regulator API will have supplied power to the display
* driver. Per datasheet, we must wait 1ms for the RESX
* pin to be valid.
*/
k_sleep(K_MSEC(1));
/* Initialize reset GPIO */
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
return ret;
}
/* Pull reset GPIO low */
gpio_pin_set_dt(&config->reset_gpio, 0);
/* Datasheet says we must keep reset pin low at least 10us.
* hold it low for 1ms to be safe.
*/
k_sleep(K_MSEC(1));
gpio_pin_set_dt(&config->reset_gpio, 1);
/* Per datasheet, we must delay at least 50ms before first
* host command
*/
k_sleep(K_MSEC(50));
}
/* Enable extended commands */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
enable_extension, sizeof(enable_extension));
if (ret < 0) {
return ret;
}
/* Set the number of lanes to DSISETUP0 parameter */
setmipi[1] |= (config->num_of_lanes - 1);
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
setmipi, sizeof(setmipi));
if (ret < 0) {
return ret;
}
/* Set scan direction */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
address_config, sizeof(address_config));
if (ret < 0) {
return ret;
}
/* Set voltage and current targets */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
power_config, sizeof(power_config));
if (ret < 0) {
return ret;
}
/* Setup display line count and front/back porch size */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
line_config, sizeof(line_config));
if (ret < 0) {
return ret;
}
/* Setup display cycle counts (in counts of TCON CLK) */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
cycle_config, sizeof(cycle_config));
if (ret < 0) {
return ret;
}
/* Set group delay values */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
gip0_config, sizeof(gip0_config));
if (ret < 0) {
return ret;
}
/* Set group clock selections */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
gip1_config, sizeof(gip1_config));
if (ret < 0) {
return ret;
}
/* Set group clock selections for GS mode */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
gip2_config, sizeof(gip2_config));
if (ret < 0) {
return ret;
}
/* Delay for a moment before setting VCOM. It is not clear
* from the datasheet why this is required, but without this
* delay the panel stops responding to additional commands
*/
k_msleep(1);
/* Set VCOM voltage config */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
vcom_config, sizeof(vcom_config));
if (ret < 0) {
return ret;
}
/* Set manufacturer supplied gamma values */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
gamma_config, sizeof(gamma_config));
if (ret < 0) {
return ret;
}
/* This command is not documented in datasheet, but is included
* in the display initialization done by MCUXpresso SDK
*/
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_cmd1, sizeof(hx8394_cmd1));
if (ret < 0) {
return ret;
}
/* Set panel to BGR mode, and reverse colors */
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
panel_config, sizeof(panel_config));
if (ret < 0) {
return ret;
}
/* This command is not documented in datasheet, but is included
* in the display initialization done by MCUXpresso SDK
*/
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_cmd2, sizeof(hx8394_cmd2));
if (ret < 0) {
return ret;
}
/* Write values to manufacturer register banks */
param[0] = HX8394_SETBANK;
param[1] = 0x2;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 2);
if (ret < 0) {
return ret;
}
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_bank2, sizeof(hx8394_bank2));
if (ret < 0) {
return ret;
}
param[1] = 0x0;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 2);
if (ret < 0) {
return ret;
}
/* Select bank 1 */
param[1] = 0x1;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 2);
if (ret < 0) {
return ret;
}
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_bank1, sizeof(hx8394_bank1));
if (ret < 0) {
return ret;
}
/* Select bank 0 */
param[1] = 0x0;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 2);
if (ret < 0) {
return ret;
}
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_bank0, sizeof(hx8394_bank0));
if (ret < 0) {
return ret;
}
/* This command is not documented in datasheet, but is included
* in the display initialization done by MCUXpresso SDK
*/
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
hx8394_cmd3, sizeof(hx8394_cmd3));
if (ret < 0) {
return ret;
}
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
tear_config, sizeof(tear_config));
if (ret < 0) {
return ret;
}
param[0] = MIPI_DCS_EXIT_SLEEP_MODE;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 1);
if (ret < 0) {
return ret;
}
/* We must delay 120ms after exiting sleep mode per datasheet */
k_sleep(K_MSEC(120));
param[0] = MIPI_DCS_SET_DISPLAY_ON;
ret = hx8394_mipi_tx(config->mipi_dsi, config->channel,
param, 1);
if (config->bl_gpio.port != NULL) {
ret = gpio_pin_configure_dt(&config->bl_gpio, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure bl GPIO (%d)", ret);
return ret;
}
}
return ret;
}
#define HX8394_PANEL(id) \
static const struct hx8394_config hx8394_config_##id = { \
.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(id)), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(id, reset_gpios, {0}), \
.bl_gpio = GPIO_DT_SPEC_INST_GET_OR(id, bl_gpios, {0}), \
.num_of_lanes = DT_INST_PROP_BY_IDX(id, data_lanes, 0), \
.pixel_format = DT_INST_PROP(id, pixel_format), \
.panel_width = DT_INST_PROP(id, width), \
.panel_height = DT_INST_PROP(id, height), \
.channel = DT_INST_REG_ADDR(id), \
}; \
DEVICE_DT_INST_DEFINE(id, \
&hx8394_init, \
NULL, \
NULL, \
&hx8394_config_##id, \
POST_KERNEL, \
CONFIG_APPLICATION_INIT_PRIORITY, \
&hx8394_api);
DT_INST_FOREACH_STATUS_OKAY(HX8394_PANEL)
``` | /content/code_sandbox/drivers/display/display_hx8394.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,827 |
```c
/*
*
*/
#define DT_DRV_COMPAT maxim_max7219
/**
* @file
* @brief MAX7219 LED display driver
*
* This driver map the segment as x, digit as y.
*
* A MAX7219 has 8x8 pixels.
* Two MAX7219s (with cascading) have 8x16 pixels.
* So on and so forth.
*
* Datasheet: path_to_url
*
* Limitations:
* 1. This driver only implements no-decode mode.
*/
#include <stddef.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
LOG_MODULE_REGISTER(max7219, CONFIG_DISPLAY_LOG_LEVEL);
#define MAX7219_SEGMENTS_PER_DIGIT 8
#define MAX7219_DIGITS_PER_DEVICE 8
/* clang-format off */
/* MAX7219 registers and fields */
#define MAX7219_REG_NOOP 0x00
#define MAX7219_NOOP 0x00
#define MAX7219_REG_DECODE_MODE 0x09
#define MAX7219_NO_DECODE 0x00
#define MAX7219_REG_INTENSITY 0x0A
#define MAX7219_REG_SCAN_LIMIT 0x0B
#define MAX7219_REG_SHUTDOWN 0x0C
#define MAX7219_SHUTDOWN_MODE 0x00
#define MAX7219_LEAVE_SHUTDOWN_MODE 0x01
#define MAX7219_REG_DISPLAY_TEST 0x0F
#define MAX7219_LEAVE_DISPLAY_TEST_MODE 0x00
#define MAX7219_DISPLAY_TEST_MODE 0x01
/* clang-format on */
struct max7219_config {
struct spi_dt_spec spi;
uint32_t num_cascading;
uint8_t intensity;
uint8_t scan_limit;
};
struct max7219_data {
/* Keep all digit_buf for all cascading MAX7219 */
uint8_t *digit_buf;
uint8_t *tx_buf;
};
static int max7219_transmit_all(const struct device *dev, const uint8_t addr, const uint8_t value)
{
const struct max7219_config *dev_config = dev->config;
struct max7219_data *dev_data = dev->data;
const struct spi_buf tx_buf = {
.buf = dev_data->tx_buf,
.len = dev_config->num_cascading * 2,
};
const struct spi_buf_set tx_bufs = {
.buffers = &tx_buf,
.count = 1U,
};
for (int i = 0; i < dev_config->num_cascading; i++) {
dev_data->tx_buf[i * 2] = addr;
dev_data->tx_buf[i * 2 + 1] = value;
}
return spi_write_dt(&dev_config->spi, &tx_bufs);
}
static int max7219_transmit_one(const struct device *dev, const uint8_t max7219_idx,
const uint8_t addr, const uint8_t value)
{
const struct max7219_config *dev_config = dev->config;
struct max7219_data *dev_data = dev->data;
const struct spi_buf tx_buf = {
.buf = dev_data->tx_buf,
.len = dev_config->num_cascading * 2,
};
const struct spi_buf_set tx_bufs = {
.buffers = &tx_buf,
.count = 1U,
};
for (int i = 0; i < dev_config->num_cascading; i++) {
if (i != (dev_config->num_cascading - 1 - max7219_idx)) {
dev_data->tx_buf[i * 2] = MAX7219_REG_NOOP;
dev_data->tx_buf[i * 2 + 1] = MAX7219_NOOP;
continue;
}
dev_data->tx_buf[i * 2] = addr;
dev_data->tx_buf[i * 2 + 1] = value;
}
return spi_write_dt(&dev_config->spi, &tx_bufs);
}
static inline uint8_t next_pixel(uint8_t *mask, uint8_t *data, const uint8_t **buf)
{
*mask <<= 1;
if (!*mask) {
*mask = 0x01;
*data = *(*buf)++;
}
return *data & *mask;
}
static inline void skip_pixel(uint8_t *mask, uint8_t *data, const uint8_t **buf, uint16_t count)
{
while (count--) {
next_pixel(mask, data, buf);
}
}
static int max7219_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct max7219_config *dev_config = dev->config;
struct max7219_data *dev_data = dev->data;
const uint16_t max_width = MAX7219_SEGMENTS_PER_DIGIT;
const uint16_t max_height = dev_config->num_cascading * MAX7219_DIGITS_PER_DEVICE;
/*
* MAX7219 only supports PIXEL_FORMAT_MONO01. 1 bit stands for 1 pixel.
*/
__ASSERT((desc->pitch * desc->height) <= (desc->buf_size * 8U), "Input buffer to small");
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT(desc->pitch <= max_width, "Pitch in descriptor is larger than screen size");
__ASSERT(desc->height <= max_height, "Height in descriptor is larger than screen size");
__ASSERT(x + desc->pitch <= max_width,
"Writing outside screen boundaries in horizontal direction");
__ASSERT(y + desc->height <= max_height,
"Writing outside screen boundaries in vertical direction");
if (desc->width > desc->pitch || (desc->pitch * desc->height) > (desc->buf_size * 8U)) {
return -EINVAL;
}
if ((x + desc->pitch) > max_width || (y + desc->height) > max_height) {
return -EINVAL;
}
const uint16_t end_x = x + desc->width;
const uint16_t end_y = y + desc->height;
const uint8_t *byte_buf = buf;
const uint16_t to_skip = desc->pitch - desc->width;
uint8_t mask = 0;
uint8_t data = 0;
for (uint16_t py = y; py < end_y; ++py) {
const uint8_t max7219_idx = py / MAX7219_DIGITS_PER_DEVICE;
const uint8_t digit_idx = py % MAX7219_DIGITS_PER_DEVICE;
uint8_t segment = dev_data->digit_buf[py];
int ret;
for (uint16_t px = x; px < end_x; ++px) {
WRITE_BIT(segment, px, next_pixel(&mask, &data, &byte_buf));
}
skip_pixel(&mask, &data, &byte_buf, to_skip);
/* led register address begins from 1 */
ret = max7219_transmit_one(dev, max7219_idx, digit_idx + 1, segment);
if (ret < 0) {
return ret;
}
dev_data->digit_buf[y] = segment;
}
return 0;
}
static int max7219_set_brightness(const struct device *dev, const uint8_t brightness)
{
int ret;
/*
* max7219 supports intensity value from 0x0 to 0xF.
* map the brightness from [0, 255] to [0, 15]
*/
ret = max7219_transmit_all(dev, MAX7219_REG_INTENSITY, brightness >> 4);
if (ret < 0) {
LOG_ERR("Failed to set brightness");
return ret;
}
return 0;
}
static int max7219_set_pixel_format(const struct device *dev,
const enum display_pixel_format format)
{
ARG_UNUSED(dev);
switch (format) {
case PIXEL_FORMAT_MONO01:
return 0;
default:
return -ENOTSUP;
}
}
static int max7219_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
ARG_UNUSED(dev);
switch (orientation) {
case DISPLAY_ORIENTATION_NORMAL:
return 0;
default:
return -ENOTSUP;
}
}
static void max7219_get_capabilities(const struct device *dev, struct display_capabilities *caps)
{
const struct max7219_config *dev_config = dev->config;
caps->x_resolution = MAX7219_SEGMENTS_PER_DIGIT;
caps->y_resolution = MAX7219_DIGITS_PER_DEVICE * dev_config->num_cascading;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO01;
caps->screen_info = 0;
caps->current_pixel_format = PIXEL_FORMAT_MONO01;
caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static const struct display_driver_api max7219_api = {
.write = max7219_write,
.set_brightness = max7219_set_brightness,
.get_capabilities = max7219_get_capabilities,
.set_pixel_format = max7219_set_pixel_format,
.set_orientation = max7219_set_orientation,
};
static int max7219_init(const struct device *dev)
{
const struct max7219_config *dev_config = dev->config;
struct max7219_data *dev_data = dev->data;
int ret;
if (!spi_is_ready_dt(&dev_config->spi)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
/* turn off all leds */
memset(dev_data->digit_buf, 0,
dev_config->num_cascading * MAX7219_DIGITS_PER_DEVICE * sizeof(uint8_t));
ret = max7219_transmit_all(dev, MAX7219_REG_DISPLAY_TEST, MAX7219_LEAVE_DISPLAY_TEST_MODE);
if (ret < 0) {
LOG_ERR("Failed to disable display test");
return ret;
}
ret = max7219_transmit_all(dev, MAX7219_REG_DECODE_MODE, MAX7219_NO_DECODE);
if (ret < 0) {
LOG_ERR("Failed to set decode mode");
return ret;
}
ret = max7219_transmit_all(dev, MAX7219_REG_INTENSITY, dev_config->intensity);
if (ret < 0) {
LOG_ERR("Failed to set global brightness");
return ret;
}
ret = max7219_transmit_all(dev, MAX7219_REG_SCAN_LIMIT, dev_config->scan_limit);
if (ret < 0) {
LOG_ERR("Failed to set scan limit");
return ret;
}
ret = max7219_transmit_all(dev, MAX7219_REG_SHUTDOWN, MAX7219_LEAVE_SHUTDOWN_MODE);
if (ret < 0) {
LOG_ERR("Failed to leave shutdown state");
return ret;
}
const struct display_buffer_descriptor desc = {
.buf_size = dev_config->num_cascading * MAX7219_DIGITS_PER_DEVICE,
.height = dev_config->num_cascading * MAX7219_DIGITS_PER_DEVICE,
.width = MAX7219_DIGITS_PER_DEVICE,
.pitch = MAX7219_DIGITS_PER_DEVICE,
};
ret = max7219_write(dev, 0, 0, &desc, dev_data->digit_buf);
if (ret < 0) {
return ret;
}
return 0;
}
#define DISPLAY_MAX7219_INIT(n) \
static uint8_t max7219_digit_data_##n[DT_INST_PROP(n, num_cascading) * \
MAX7219_DIGITS_PER_DEVICE]; \
static uint8_t max7219_tx_buf##n[DT_INST_PROP(n, num_cascading) * 2]; \
static struct max7219_data max7219_data_##n = { \
.digit_buf = max7219_digit_data_##n, \
.tx_buf = max7219_tx_buf##n, \
}; \
static const struct max7219_config max7219_config_##n = { \
.spi = SPI_DT_SPEC_INST_GET( \
n, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U), \
.num_cascading = DT_INST_PROP(n, num_cascading), \
.intensity = DT_INST_PROP(n, intensity), \
.scan_limit = DT_INST_PROP(n, scan_limit), \
}; \
DEVICE_DT_INST_DEFINE(n, max7219_init, NULL, &max7219_data_##n, \
&max7219_config_##n, POST_KERNEL, \
CONFIG_DISPLAY_INIT_PRIORITY, &max7219_api);
DT_INST_FOREACH_STATUS_OKAY(DISPLAY_MAX7219_INIT)
``` | /content/code_sandbox/drivers/display/display_max7219.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,783 |
```objective-c
/*
*
*/
#ifndef __SSD1306_REGS_H__
#define __SSD1306_REGS_H__
/* All following bytes will contain commands */
#define SSD1306_CONTROL_ALL_BYTES_CMD 0x00
/* All following bytes will contain data */
#define SSD1306_CONTROL_ALL_BYTES_DATA 0x40
/* The next byte will contain a command */
#define SSD1306_CONTROL_BYTE_CMD 0x80
/* The next byte will contain data */
#define SSD1306_CONTROL_BYTE_DATA 0xc0
#define SSD1306_READ_STATUS_MASK 0xc0
#define SSD1306_READ_STATUS_BUSY 0x80
#define SSD1306_READ_STATUS_ON 0x40
/*
* Fundamental Command Table
*/
#define SSD1306_SET_CONTRAST_CTRL 0x81 /* double byte command */
#define SSD1306_SET_ENTIRE_DISPLAY_OFF 0xa4
#define SSD1306_SET_ENTIRE_DISPLAY_ON 0xa5
/* RAM data of 1 indicates an "ON" pixel */
#define SSD1306_SET_NORMAL_DISPLAY 0xa6
/* RAM data of 0 indicates an "ON" pixel */
#define SSD1306_SET_REVERSE_DISPLAY 0xa7
#define SSD1306_DISPLAY_OFF 0xae
#define SSD1306_DISPLAY_ON 0xaf
/*
* Addressing Setting Command Table
*/
#define SSD1306_SET_LOWER_COL_ADDRESS 0x00
#define SSD1306_SET_LOWER_COL_ADDRESS_MASK 0x0f
#define SSD1306_SET_HIGHER_COL_ADDRESS 0x10
#define SSD1306_SET_HIGHER_COL_ADDRESS_MASK 0x0f
#define SSD1306_SET_MEM_ADDRESSING_MODE 0x20 /* double byte command */
#define SSD1306_SET_MEM_ADDRESSING_HORIZONTAL 0x00
#define SSD1306_SET_MEM_ADDRESSING_VERTICAL 0x01
#define SSD1306_SET_MEM_ADDRESSING_PAGE 0x02
#define SSD1306_SET_COLUMN_ADDRESS 0x21 /* triple byte command */
#define SSD1306_SET_PAGE_ADDRESS 0x22 /* triple byte command */
#define SSD1306_SET_PAGE_START_ADDRESS 0xb0
#define SSD1306_SET_PAGE_START_ADDRESS_MASK 0x07
/*
* Hardware Configuration Command Table
*/
#define SSD1306_SET_START_LINE 0x40
#define SSD1306_SET_START_LINE_MASK 0x3f
#define SSD1306_SET_SEGMENT_MAP_NORMAL 0xa0
#define SSD1306_SET_SEGMENT_MAP_REMAPED 0xa1
#define SSD1306_SET_MULTIPLEX_RATIO 0xa8 /* double byte command */
#define SSD1306_SET_COM_OUTPUT_SCAN_NORMAL 0xc0
#define SSD1306_SET_COM_OUTPUT_SCAN_FLIPPED 0xc8
#define SSD1306_SET_DISPLAY_OFFSET 0xd3 /* double byte command */
#define SSD1306_SET_PADS_HW_CONFIG 0xda /* double byte command */
#define SSD1306_SET_PADS_HW_SEQUENTIAL 0x02
#define SSD1306_SET_PADS_HW_ALTERNATIVE 0x12
#define SSD1306_SET_IREF_MODE 0xad
#define SSD1306_SET_IREF_MODE_INTERNAL 0x30
#define SSD1306_SET_IREF_MODE_EXTERNAL 0x00
/*
* Timing and Driving Scheme Setting Command Table
*/
#define SSD1306_SET_CLOCK_DIV_RATIO 0xd5 /* double byte command */
#define SSD1306_SET_CHARGE_PERIOD 0xd9 /* double byte command */
#define SSD1306_SET_VCOM_DESELECT_LEVEL 0xdb /* double byte command */
#define SSD1306_NOP 0xe3
/*
* Charge Pump Command Table
*/
#define SSD1306_SET_CHARGE_PUMP_ON 0x8d /* double byte command */
#define SSD1306_SET_CHARGE_PUMP_ON_DISABLED 0x10
#define SSD1306_SET_CHARGE_PUMP_ON_ENABLED 0x14
#define SH1106_SET_DCDC_MODE 0xad /* double byte command */
#define SH1106_SET_DCDC_DISABLED 0x8a
#define SH1106_SET_DCDC_ENABLED 0x8b
#define SSD1306_SET_PUMP_VOLTAGE_64 0x30
#define SSD1306_SET_PUMP_VOLTAGE_74 0x31
#define SSD1306_SET_PUMP_VOLTAGE_80 0x32
#define SSD1306_SET_PUMP_VOLTAGE_90 0x33
/*
* Read modify write
*/
#define SSD1306_READ_MODIFY_WRITE_START 0xe0
#define SSD1306_READ_MODIFY_WRITE_END 0xee
/* time constants in ms */
#define SSD1306_RESET_DELAY 1
#endif
``` | /content/code_sandbox/drivers/display/ssd1306_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,008 |
```c
/*
*
* This code attempts to be endian-agnostic. It manipulates the framebuffer
* address space only in 32-bit words (and assumes those words are 0xAARRGGBB).
*
*/
#define DT_DRV_COMPAT intel_multiboot_framebuffer
#include <errno.h>
#include <zephyr/arch/x86/multiboot.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/display.h>
#include <string.h>
struct framebuf_dev_config {
uint16_t width;
uint16_t height;
};
struct framebuf_dev_data {
void *buffer;
uint32_t pitch;
};
static int framebuf_set_pixel_format(const struct device *dev,
const enum display_pixel_format format)
{
switch (format) {
case PIXEL_FORMAT_ARGB_8888:
return 0;
default:
return -ENOTSUP;
}
}
static int framebuf_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
switch (orientation) {
case DISPLAY_ORIENTATION_NORMAL:
return 0;
default:
return -ENOTSUP;
}
}
static void framebuf_get_capabilities(const struct device *dev,
struct display_capabilities *caps)
{
const struct framebuf_dev_config *config = dev->config;
caps->x_resolution = config->width;
caps->y_resolution = config->height;
caps->supported_pixel_formats = PIXEL_FORMAT_ARGB_8888;
caps->screen_info = 0;
caps->current_pixel_format = PIXEL_FORMAT_ARGB_8888;
caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int framebuf_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
struct framebuf_dev_data *data = dev->data;
uint32_t *dst = data->buffer;
const uint32_t *src = buf;
uint32_t row;
dst += x;
dst += (y * data->pitch);
for (row = 0; row < desc->height; ++row) {
(void) memcpy(dst, src, desc->width * sizeof(uint32_t));
dst += data->pitch;
src += desc->pitch;
}
return 0;
}
static int framebuf_read(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
void *buf)
{
struct framebuf_dev_data *data = dev->data;
uint32_t *src = data->buffer;
uint32_t *dst = buf;
uint32_t row;
src += x;
src += (y * data->pitch);
for (row = 0; row < desc->height; ++row) {
(void) memcpy(dst, src, desc->width * sizeof(uint32_t));
src += data->pitch;
dst += desc->pitch;
}
return 0;
}
const struct display_driver_api framebuf_display_api = {
.write = framebuf_write,
.read = framebuf_read,
.get_capabilities = framebuf_get_capabilities,
.set_pixel_format = framebuf_set_pixel_format,
.set_orientation = framebuf_set_orientation
};
static int multiboot_framebuf_init(const struct device *dev)
{
const struct framebuf_dev_config *config = dev->config;
struct framebuf_dev_data *data = dev->data;
struct multiboot_info *info = &multiboot_info;
if ((info->flags & MULTIBOOT_INFO_FLAGS_FB) &&
(info->fb_width >= config->width) &&
(info->fb_height >= config->height) &&
(info->fb_bpp == 32) && (info->fb_addr_hi == 0)) {
/*
* We have a usable multiboot framebuffer - it is 32 bpp
* and at least as large as the requested dimensions. Compute
* the pitch and adjust the start address center our canvas.
*/
uint16_t adj_x;
uint16_t adj_y;
uint32_t *buffer;
adj_x = info->fb_width - config->width;
adj_y = info->fb_height - config->height;
data->pitch = (info->fb_pitch / 4) + adj_x;
adj_x /= 2U;
adj_y /= 2U;
buffer = (uint32_t *) (uintptr_t) info->fb_addr_lo;
buffer += adj_x;
buffer += adj_y * data->pitch;
data->buffer = buffer;
return 0;
} else {
return -ENOTSUP;
}
}
static const struct framebuf_dev_config config = {
.width = DT_INST_PROP(0, width),
.height = DT_INST_PROP(0, height),
};
static struct framebuf_dev_data data;
DEVICE_DT_INST_DEFINE(0, multiboot_framebuf_init, NULL, &data, &config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&framebuf_display_api);
``` | /content/code_sandbox/drivers/display/display_intel_multibootfb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,069 |
```c
/*
*
*/
#include "display_ili9341.h"
#include "display_ili9xxx.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_ili9341, CONFIG_DISPLAY_LOG_LEVEL);
int ili9341_regs_init(const struct device *dev)
{
const struct ili9xxx_config *config = dev->config;
const struct ili9341_regs *regs = config->regs;
int r;
LOG_HEXDUMP_DBG(regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN, "PWSEQCTRL");
r = ili9xxx_transmit(dev, ILI9341_PWSEQCTRL, regs->pwseqctrl, ILI9341_PWSEQCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->timctrla, ILI9341_TIMCTRLA_LEN, "TIMCTRLA");
r = ili9xxx_transmit(dev, ILI9341_TIMCTRLA, regs->timctrla, ILI9341_TIMCTRLA_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->timctrlb, ILI9341_TIMCTRLB_LEN, "TIMCTRLB");
r = ili9xxx_transmit(dev, ILI9341_TIMCTRLB, regs->timctrlb, ILI9341_TIMCTRLB_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pumpratioctrl, ILI9341_PUMPRATIOCTRL_LEN, "PUMPRATIOCTRL");
r = ili9xxx_transmit(dev, ILI9341_PUMPRATIOCTRL, regs->pumpratioctrl,
ILI9341_PUMPRATIOCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrla, ILI9341_PWCTRLA_LEN, "PWCTRLA");
r = ili9xxx_transmit(dev, ILI9341_PWCTRLA, regs->pwctrla, ILI9341_PWCTRLA_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrlb, ILI9341_PWCTRLB_LEN, "PWCTRLB");
r = ili9xxx_transmit(dev, ILI9341_PWCTRLB, regs->pwctrlb, ILI9341_PWCTRLB_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->gamset, ILI9341_GAMSET_LEN, "GAMSET");
r = ili9xxx_transmit(dev, ILI9341_GAMSET, regs->gamset, ILI9341_GAMSET_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->frmctr1, ILI9341_FRMCTR1_LEN, "FRMCTR1");
r = ili9xxx_transmit(dev, ILI9341_FRMCTR1, regs->frmctr1, ILI9341_FRMCTR1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->disctrl, ILI9341_DISCTRL_LEN, "DISCTRL");
r = ili9xxx_transmit(dev, ILI9341_DISCTRL, regs->disctrl, ILI9341_DISCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl1, ILI9341_PWCTRL1_LEN, "PWCTRL1");
r = ili9xxx_transmit(dev, ILI9341_PWCTRL1, regs->pwctrl1, ILI9341_PWCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pwctrl2, ILI9341_PWCTRL2_LEN, "PWCTRL2");
r = ili9xxx_transmit(dev, ILI9341_PWCTRL2, regs->pwctrl2, ILI9341_PWCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl1, ILI9341_VMCTRL1_LEN, "VMCTRL1");
r = ili9xxx_transmit(dev, ILI9341_VMCTRL1, regs->vmctrl1, ILI9341_VMCTRL1_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->vmctrl2, ILI9341_VMCTRL2_LEN, "VMCTRL2");
r = ili9xxx_transmit(dev, ILI9341_VMCTRL2, regs->vmctrl2, ILI9341_VMCTRL2_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->pgamctrl, ILI9341_PGAMCTRL_LEN, "PGAMCTRL");
r = ili9xxx_transmit(dev, ILI9341_PGAMCTRL, regs->pgamctrl, ILI9341_PGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ngamctrl, ILI9341_NGAMCTRL_LEN, "NGAMCTRL");
r = ili9xxx_transmit(dev, ILI9341_NGAMCTRL, regs->ngamctrl, ILI9341_NGAMCTRL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->enable3g, ILI9341_ENABLE3G_LEN, "ENABLE3G");
r = ili9xxx_transmit(dev, ILI9341_ENABLE3G, regs->enable3g, ILI9341_ENABLE3G_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ifmode, ILI9341_IFMODE_LEN, "IFMODE");
r = ili9xxx_transmit(dev, ILI9341_IFMODE, regs->ifmode, ILI9341_IFMODE_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->ifctl, ILI9341_IFCTL_LEN, "IFCTL");
r = ili9xxx_transmit(dev, ILI9341_IFCTL, regs->ifctl, ILI9341_IFCTL_LEN);
if (r < 0) {
return r;
}
LOG_HEXDUMP_DBG(regs->etmod, ILI9341_ETMOD_LEN, "ETMOD");
r = ili9xxx_transmit(dev, ILI9341_ETMOD, regs->etmod, ILI9341_ETMOD_LEN);
if (r < 0) {
return r;
}
return 0;
}
``` | /content/code_sandbox/drivers/display/display_ili9341.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,454 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_
#include <zephyr/device.h>
/* Commands/registers. */
#define ILI9341_GAMSET 0x26
#define ILI9341_IFMODE 0xB0
#define ILI9341_FRMCTR1 0xB1
#define ILI9341_DISCTRL 0xB6
#define ILI9341_ETMOD 0xB7
#define ILI9341_PWCTRL1 0xC0
#define ILI9341_PWCTRL2 0xC1
#define ILI9341_VMCTRL1 0xC5
#define ILI9341_VMCTRL2 0xC7
#define ILI9341_PWCTRLA 0xCB
#define ILI9341_PWCTRLB 0xCF
#define ILI9341_PGAMCTRL 0xE0
#define ILI9341_NGAMCTRL 0xE1
#define ILI9341_TIMCTRLA 0xE8
#define ILI9341_TIMCTRLB 0xEA
#define ILI9341_PWSEQCTRL 0xED
#define ILI9341_ENABLE3G 0xF2
#define ILI9341_IFCTL 0xF6
#define ILI9341_PUMPRATIOCTRL 0xF7
/* Commands/registers length. */
#define ILI9341_GAMSET_LEN 1U
#define ILI9341_IFMODE_LEN 1U
#define ILI9341_FRMCTR1_LEN 2U
#define ILI9341_DISCTRL_LEN 4U
#define ILI9341_PWCTRL1_LEN 1U
#define ILI9341_PWCTRL2_LEN 1U
#define ILI9341_VMCTRL1_LEN 2U
#define ILI9341_VMCTRL2_LEN 1U
#define ILI9341_PGAMCTRL_LEN 15U
#define ILI9341_NGAMCTRL_LEN 15U
#define ILI9341_PWCTRLA_LEN 5U
#define ILI9341_PWCTRLB_LEN 3U
#define ILI9341_PWSEQCTRL_LEN 4U
#define ILI9341_TIMCTRLA_LEN 3U
#define ILI9341_TIMCTRLB_LEN 2U
#define ILI9341_PUMPRATIOCTRL_LEN 1U
#define ILI9341_ENABLE3G_LEN 1U
#define ILI9341_IFCTL_LEN 3U
#define ILI9341_ETMOD_LEN 1U
/** X resolution (pixels). */
#define ILI9341_X_RES 240U
/** Y resolution (pixels). */
#define ILI9341_Y_RES 320U
/** ILI9341 registers to be initialized. */
struct ili9341_regs {
uint8_t gamset[ILI9341_GAMSET_LEN];
uint8_t ifmode[ILI9341_IFMODE_LEN];
uint8_t frmctr1[ILI9341_FRMCTR1_LEN];
uint8_t disctrl[ILI9341_DISCTRL_LEN];
uint8_t pwctrl1[ILI9341_PWCTRL1_LEN];
uint8_t pwctrl2[ILI9341_PWCTRL2_LEN];
uint8_t vmctrl1[ILI9341_VMCTRL1_LEN];
uint8_t vmctrl2[ILI9341_VMCTRL2_LEN];
uint8_t pgamctrl[ILI9341_PGAMCTRL_LEN];
uint8_t ngamctrl[ILI9341_NGAMCTRL_LEN];
uint8_t pwctrla[ILI9341_PWCTRLA_LEN];
uint8_t pwctrlb[ILI9341_PWCTRLB_LEN];
uint8_t pwseqctrl[ILI9341_PWSEQCTRL_LEN];
uint8_t timctrla[ILI9341_TIMCTRLA_LEN];
uint8_t timctrlb[ILI9341_TIMCTRLB_LEN];
uint8_t pumpratioctrl[ILI9341_PUMPRATIOCTRL_LEN];
uint8_t enable3g[ILI9341_ENABLE3G_LEN];
uint8_t ifctl[ILI9341_IFCTL_LEN];
uint8_t etmod[ILI9341_ETMOD_LEN];
};
/* Initializer macro for ILI9341 registers. */
#define ILI9341_REGS_INIT(n) \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), gamset) == ILI9341_GAMSET_LEN, \
"ili9341: Error length gamma set (GAMSET) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ifmode) == ILI9341_IFMODE_LEN, \
"ili9341: Error length frame rate control (IFMODE) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), frmctr1) == ILI9341_FRMCTR1_LEN, \
"ili9341: Error length frame rate control (FRMCTR1) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), disctrl) == ILI9341_DISCTRL_LEN, \
"ili9341: Error length display function control (DISCTRL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl1) == ILI9341_PWCTRL1_LEN, \
"ili9341: Error length power control 1 (PWCTRL1) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl2) == ILI9341_PWCTRL2_LEN, \
"ili9341: Error length power control 2 (PWCTRL2) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl1) == ILI9341_VMCTRL1_LEN, \
"ili9341: Error length VCOM control 1 (VMCTRL1) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl2) == ILI9341_VMCTRL2_LEN, \
"ili9341: Error length VCOM control 2 (VMCTRL2) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pgamctrl) == ILI9341_PGAMCTRL_LEN, \
"ili9341: Error length positive gamma correction (PGAMCTRL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ngamctrl) == ILI9341_NGAMCTRL_LEN, \
"ili9341: Error length negative gamma correction (NGAMCTRL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrla) == ILI9341_PWCTRLA_LEN, \
"ili9341: Error length power control A (PWCTRLA) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrlb) == ILI9341_PWCTRLB_LEN, \
"ili9341: Error length power control B (PWCTRLB) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwseqctrl) == ILI9341_PWSEQCTRL_LEN, \
"ili9341: Error length power on sequence control (PWSEQCTRL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), timctrla) == ILI9341_TIMCTRLA_LEN, \
"ili9341: Error length driver timing control A (TIMCTRLA) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), timctrlb) == ILI9341_TIMCTRLB_LEN, \
"ili9341: Error length driver timing control B (TIMCTRLB) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pumpratioctrl) == \
ILI9341_PUMPRATIOCTRL_LEN, \
"ili9341: Error length Pump ratio control (PUMPRATIOCTRL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), enable3g) == ILI9341_ENABLE3G_LEN, \
"ili9341: Error length enable 3G (ENABLE3G) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ifctl) == ILI9341_IFCTL_LEN, \
"ili9341: Error length frame rate control (IFCTL) register"); \
BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), etmod) == ILI9341_ETMOD_LEN, \
"ili9341: Error length entry Mode Set (ETMOD) register"); \
static const struct ili9341_regs ili9xxx_regs_##n = { \
.gamset = DT_PROP(DT_INST(n, ilitek_ili9341), gamset), \
.ifmode = DT_PROP(DT_INST(n, ilitek_ili9341), ifmode), \
.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9341), frmctr1), \
.disctrl = DT_PROP(DT_INST(n, ilitek_ili9341), disctrl), \
.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl1), \
.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl2), \
.vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl1), \
.vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl2), \
.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pgamctrl), \
.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), ngamctrl), \
.pwctrla = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrla), \
.pwctrlb = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrlb), \
.pwseqctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pwseqctrl), \
.timctrla = DT_PROP(DT_INST(n, ilitek_ili9341), timctrla), \
.timctrlb = DT_PROP(DT_INST(n, ilitek_ili9341), timctrlb), \
.pumpratioctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pumpratioctrl), \
.enable3g = DT_PROP(DT_INST(n, ilitek_ili9341), enable3g), \
.ifctl = DT_PROP(DT_INST(n, ilitek_ili9341), ifctl), \
.etmod = DT_PROP(DT_INST(n, ilitek_ili9341), etmod), \
}
/**
* @brief Initialize ILI9341 registers with DT values.
*
* @param dev ILI9341 device instance
* @return 0 on success, errno otherwise.
*/
int ili9341_regs_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9341_H_ */
``` | /content/code_sandbox/drivers/display/display_ili9341.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,576 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9XXX_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9XXX_H_
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/sys/util.h>
/* Commands/registers. */
#define ILI9XXX_SWRESET 0x01
#define ILI9XXX_SLPOUT 0x11
#define ILI9XXX_DINVON 0x21
#define ILI9XXX_GAMSET 0x26
#define ILI9XXX_DISPOFF 0x28
#define ILI9XXX_DISPON 0x29
#define ILI9XXX_CASET 0x2a
#define ILI9XXX_PASET 0x2b
#define ILI9XXX_RAMWR 0x2c
#define ILI9XXX_RGBSET 0x2d
#define ILI9XXX_RAMRD 0x2e
#define ILI9XXX_MADCTL 0x36
#define ILI9XXX_PIXSET 0x3A
#define ILI9XXX_RAMRD_CONT 0x3e
/* MADCTL register fields. */
#define ILI9XXX_MADCTL_MY BIT(7U)
#define ILI9XXX_MADCTL_MX BIT(6U)
#define ILI9XXX_MADCTL_MV BIT(5U)
#define ILI9XXX_MADCTL_ML BIT(4U)
#define ILI9XXX_MADCTL_BGR BIT(3U)
#define ILI9XXX_MADCTL_MH BIT(2U)
/* PIXSET register fields. */
#define ILI9XXX_PIXSET_RGB_18_BIT 0x60
#define ILI9XXX_PIXSET_RGB_16_BIT 0x50
#define ILI9XXX_PIXSET_MCU_18_BIT 0x06
#define ILI9XXX_PIXSET_MCU_16_BIT 0x05
/** Command/data GPIO level for commands. */
#define ILI9XXX_CMD 1U
/** Command/data GPIO level for data. */
#define ILI9XXX_DATA 0U
/** Sleep out time (ms), ref. 8.2.12 of ILI9XXX manual. */
#define ILI9XXX_SLEEP_OUT_TIME 120
/** Reset pulse time (ms), ref 15.4 of ILI9XXX manual. */
#define ILI9XXX_RESET_PULSE_TIME 1
/** Reset wait time (ms), ref 15.4 of ILI9XXX manual. */
#define ILI9XXX_RESET_WAIT_TIME 5
enum madctl_cmd_set {
CMD_SET_1, /* Default for most of ILI9xxx display controllers */
CMD_SET_2, /* Used by ILI9342c */
};
struct ili9xxx_quirks {
enum madctl_cmd_set cmd_set;
};
struct ili9xxx_config {
const struct ili9xxx_quirks *quirks;
const struct device *mipi_dev;
struct mipi_dbi_config dbi_config;
uint8_t pixel_format;
uint16_t rotation;
uint16_t x_resolution;
uint16_t y_resolution;
bool inversion;
const void *regs;
int (*regs_init_fn)(const struct device *dev);
};
int ili9xxx_transmit(const struct device *dev, uint8_t cmd,
const void *tx_data, size_t tx_len);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9XXX_H_ */
``` | /content/code_sandbox/drivers/display/display_ili9xxx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 730 |
```objective-c
/**
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_
#define ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_
#include <zephyr/sys/util.h>
/* Command registers */
#define GC9X01X_CMD_SLPIN 0x10U /* Enter Sleep Mode */
#define GC9X01X_CMD_SLPOUT 0x11U /* Exit Sleep Mode */
#define GC9X01X_CMD_PTLON 0x12U /* Partial Mode ON */
#define GC9X01X_CMD_NORON 0x13U /* Normal Display Mode ON */
#define GC9X01X_CMD_INVOFF 0x20U /* Display Inversion OFF */
#define GC9X01X_CMD_INVON 0x21U /* Display Inversion ON */
#define GC9X01X_CMD_DISPOFF 0x28U /* Display OFF */
#define GC9X01X_CMD_DISPON 0x29U /* Display ON */
#define GC9X01X_CMD_COLSET 0x2AU /* Column Address Set */
#define GC9X01X_CMD_ROWSET 0x2BU /* Row Address Set */
#define GC9X01X_CMD_MEMWR 0x2CU /* Memory Write */
#define GC9X01X_CMD_PTLAR 0x30U /* Partial Area */
#define GC9X01X_CMD_VSCRDEF 0x33U /* Vertical Scrolling Definition */
#define GC9X01X_CMD_TEOFF 0x34U /* Tearing Effect Line OFF */
#define GC9X01X_CMD_TEON 0x35U /* Tearing Effect Line ON */
#define GC9X01X_CMD_MADCTL 0x36U /* Memory Access Control */
#define GC9X01X_CMD_VSCRSADD 0x37U /* Vertical Scrolling Start Address */
#define GC9X01X_CMD_PIXFMT 0x3AU /* Pixel Format Set */
#define GC9X01X_CMD_DFUNCTR 0xB6U /* Display Function Control */
#define GC9X01X_CMD_PWRCTRL1 0xC1U /* Power Control 1 */
#define GC9X01X_CMD_PWRCTRL2 0xC3U /* Power Control 2 */
#define GC9X01X_CMD_PWRCTRL3 0xC4U /* Power Control 3 */
#define GC9X01X_CMD_PWRCTRL4 0xC9U /* Power Control 4 */
#define GC9X01X_CMD_READID1 0xDAU /* Read ID 1 */
#define GC9X01X_CMD_READID2 0xDBU /* Read ID 2 */
#define GC9X01X_CMD_READID3 0xDCU /* Read ID 3 */
#define GC9X01X_CMD_GAMMA1 0xF0U /* Gamma1 (negative polarity) */
#define GC9X01X_CMD_GAMMA2 0xF1U /* Gamma2 */
#define GC9X01X_CMD_GAMMA3 0xF2U /* Gamma3 (positive polarity) */
#define GC9X01X_CMD_GAMMA4 0xF3U /* Gamma4 */
#define GC9X01X_CMD_INREGEN1 0xFEU /* Inter Register Enable 1 */
#define GC9X01X_CMD_INREGEN2 0xEFU /* Inter Register Enable 2 */
#define GC9X01X_CMD_FRAMERATE 0xE8U /* Frame Rate Control */
/* GC9X01X_CMD_MADCTL register fields */
#define GC9X01X_MADCTL_VAL_MY BIT(7U)
#define GC9X01X_MADCTL_VAL_MX BIT(6U)
#define GC9X01X_MADCTL_VAL_MV BIT(5U)
#define GC9X01X_MADCTL_VAL_ML BIT(4U)
#define GC9X01X_MADCTL_VAL_BGR BIT(3U)
#define GC9X01X_MADCTL_VAL_MH BIT(2U)
/* GC9X01X_CMD_PIXFMT register fields */
#define GC9X01X_PIXFMT_VAL_RGB_18_BIT 0x60U
#define GC9X01X_PIXFMT_VAL_RGB_16_BIT 0x50U
#define GC9X01X_PIXFMT_VAL_MCU_18_BIT 0x06U
#define GC9X01X_PIXFMT_VAL_MCU_16_BIT 0x05U
/* Duration to enter/exit sleep mode (see 6.2.3 and 6.4.2 in datasheet) */
#define GC9X01X_SLEEP_IN_OUT_DURATION_MS 120
/* GC9X01X registers to be intitialized */
#define GC9X01X_CMD_PWRCTRL1_LEN 1U
#define GC9X01X_CMD_PWRCTRL2_LEN 1U
#define GC9X01X_CMD_PWRCTRL3_LEN 1U
#define GC9X01X_CMD_PWRCTRL4_LEN 1U
#define GC9X01X_CMD_GAMMA1_LEN 6U
#define GC9X01X_CMD_GAMMA2_LEN 6U
#define GC9X01X_CMD_GAMMA3_LEN 6U
#define GC9X01X_CMD_GAMMA4_LEN 6U
#define GC9X01X_CMD_FRAMERATE_LEN 1U
struct gc9x01x_regs {
uint8_t pwrctrl1[GC9X01X_CMD_PWRCTRL1_LEN];
uint8_t pwrctrl2[GC9X01X_CMD_PWRCTRL2_LEN];
uint8_t pwrctrl3[GC9X01X_CMD_PWRCTRL3_LEN];
uint8_t pwrctrl4[GC9X01X_CMD_PWRCTRL4_LEN];
uint8_t gamma1[GC9X01X_CMD_GAMMA1_LEN];
uint8_t gamma2[GC9X01X_CMD_GAMMA2_LEN];
uint8_t gamma3[GC9X01X_CMD_GAMMA3_LEN];
uint8_t gamma4[GC9X01X_CMD_GAMMA4_LEN];
uint8_t framerate[GC9X01X_CMD_FRAMERATE_LEN];
};
#define GC9X01X_REGS_INIT(inst) \
static const struct gc9x01x_regs gc9x01x_regs_##inst = { \
.pwrctrl1 = DT_INST_PROP(inst, pwrctrl1), \
.pwrctrl2 = DT_INST_PROP(inst, pwrctrl2), \
.pwrctrl3 = DT_INST_PROP(inst, pwrctrl3), \
.pwrctrl4 = DT_INST_PROP(inst, pwrctrl4), \
.gamma1 = DT_INST_PROP(inst, gamma1), \
.gamma2 = DT_INST_PROP(inst, gamma2), \
.gamma3 = DT_INST_PROP(inst, gamma3), \
.gamma4 = DT_INST_PROP(inst, gamma4), \
.framerate = DT_INST_PROP(inst, framerate), \
};
#endif /* ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_ */
``` | /content/code_sandbox/drivers/display/display_gc9x01x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,552 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9340_H_
#define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9340_H_
#include <zephyr/device.h>
/* Commands/registers. */
#define ILI9340_GAMSET 0x26
#define ILI9340_FRMCTR1 0xB1
#define ILI9340_DISCTRL 0xB6
#define ILI9340_PWCTRL1 0xC0
#define ILI9340_PWCTRL2 0xC1
#define ILI9340_VMCTRL1 0xC5
#define ILI9340_VMCTRL2 0xC7
#define ILI9340_PGAMCTRL 0xE0
#define ILI9340_NGAMCTRL 0xE1
/* Commands/registers length. */
#define ILI9340_GAMSET_LEN 1U
#define ILI9340_FRMCTR1_LEN 2U
#define ILI9340_DISCTRL_LEN 3U
#define ILI9340_PWCTRL1_LEN 2U
#define ILI9340_PWCTRL2_LEN 1U
#define ILI9340_VMCTRL1_LEN 2U
#define ILI9340_VMCTRL2_LEN 1U
#define ILI9340_PGAMCTRL_LEN 15U
#define ILI9340_NGAMCTRL_LEN 15U
/** X resolution (pixels). */
#define ILI9340_X_RES 240U
/** Y resolution (pixels). */
#define ILI9340_Y_RES 320U
/** ILI9340 registers to be initialized. */
struct ili9340_regs {
uint8_t gamset[ILI9340_GAMSET_LEN];
uint8_t frmctr1[ILI9340_FRMCTR1_LEN];
uint8_t disctrl[ILI9340_DISCTRL_LEN];
uint8_t pwctrl1[ILI9340_PWCTRL1_LEN];
uint8_t pwctrl2[ILI9340_PWCTRL2_LEN];
uint8_t vmctrl1[ILI9340_VMCTRL1_LEN];
uint8_t vmctrl2[ILI9340_VMCTRL2_LEN];
uint8_t pgamctrl[ILI9340_PGAMCTRL_LEN];
uint8_t ngamctrl[ILI9340_NGAMCTRL_LEN];
};
/* Initializer macro for ILI9340 registers. */
#define ILI9340_REGS_INIT(n) \
static const struct ili9340_regs ili9xxx_regs_##n = { \
.gamset = DT_PROP(DT_INST(n, ilitek_ili9340), gamset), \
.frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9340), frmctr1), \
.disctrl = DT_PROP(DT_INST(n, ilitek_ili9340), disctrl), \
.pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl1), \
.pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl2), \
.vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl1), \
.vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl2), \
.pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), pgamctrl), \
.ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), ngamctrl), \
}
/**
* @brief Initialize ILI9340 registers with DT values.
*
* @param dev ILI9340 device instance
* @return 0 on success, errno otherwise.
*/
int ili9340_regs_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_ILI9340_H_ */
``` | /content/code_sandbox/drivers/display/display_ili9340.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 831 |
```c
/*
*
*/
#define DT_DRV_COMPAT sitronix_st7789v
#include "display_st7789v.h"
#include <zephyr/device.h>
#include <zephyr/drivers/mipi_dbi.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/display.h>
#define LOG_LEVEL CONFIG_DISPLAY_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(display_st7789v);
struct st7789v_config {
const struct device *mipi_dbi;
const struct mipi_dbi_config dbi_config;
uint8_t vcom;
uint8_t gctrl;
bool vdv_vrh_enable;
uint8_t vrh_value;
uint8_t vdv_value;
uint8_t mdac;
uint8_t gamma;
uint8_t colmod;
uint8_t lcm;
bool inversion_on;
uint8_t porch_param[5];
uint8_t cmd2en_param[4];
uint8_t pwctrl1_param[2];
uint8_t pvgam_param[14];
uint8_t nvgam_param[14];
uint8_t ram_param[2];
uint8_t rgb_param[3];
uint16_t height;
uint16_t width;
};
struct st7789v_data {
uint16_t x_offset;
uint16_t y_offset;
};
#ifdef CONFIG_ST7789V_RGB888
#define ST7789V_PIXEL_SIZE 3u
#else
#define ST7789V_PIXEL_SIZE 2u
#endif
static void st7789v_set_lcd_margins(const struct device *dev,
uint16_t x_offset, uint16_t y_offset)
{
struct st7789v_data *data = dev->data;
data->x_offset = x_offset;
data->y_offset = y_offset;
}
static void st7789v_transmit(const struct device *dev, uint8_t cmd,
uint8_t *tx_data, size_t tx_count)
{
const struct st7789v_config *config = dev->config;
mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, cmd,
tx_data, tx_count);
}
static void st7789v_exit_sleep(const struct device *dev)
{
st7789v_transmit(dev, ST7789V_CMD_SLEEP_OUT, NULL, 0);
k_sleep(K_MSEC(120));
}
static void st7789v_reset_display(const struct device *dev)
{
const struct st7789v_config *config = dev->config;
int ret;
LOG_DBG("Resetting display");
k_sleep(K_MSEC(1));
ret = mipi_dbi_reset(config->mipi_dbi, 6);
if (ret == -ENOTSUP) {
/* Send software reset command */
st7789v_transmit(dev, ST7789V_CMD_SW_RESET, NULL, 0);
k_sleep(K_MSEC(5));
} else {
k_sleep(K_MSEC(20));
}
}
static int st7789v_blanking_on(const struct device *dev)
{
st7789v_transmit(dev, ST7789V_CMD_DISP_OFF, NULL, 0);
return 0;
}
static int st7789v_blanking_off(const struct device *dev)
{
st7789v_transmit(dev, ST7789V_CMD_DISP_ON, NULL, 0);
return 0;
}
static void st7789v_set_mem_area(const struct device *dev, const uint16_t x,
const uint16_t y, const uint16_t w, const uint16_t h)
{
struct st7789v_data *data = dev->data;
uint16_t spi_data[2];
uint16_t ram_x = x + data->x_offset;
uint16_t ram_y = y + data->y_offset;
spi_data[0] = sys_cpu_to_be16(ram_x);
spi_data[1] = sys_cpu_to_be16(ram_x + w - 1);
st7789v_transmit(dev, ST7789V_CMD_CASET, (uint8_t *)&spi_data[0], 4);
spi_data[0] = sys_cpu_to_be16(ram_y);
spi_data[1] = sys_cpu_to_be16(ram_y + h - 1);
st7789v_transmit(dev, ST7789V_CMD_RASET, (uint8_t *)&spi_data[0], 4);
}
static int st7789v_write(const struct device *dev,
const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct st7789v_config *config = dev->config;
struct display_buffer_descriptor mipi_desc;
const uint8_t *write_data_start = (uint8_t *) buf;
uint16_t nbr_of_writes;
uint16_t write_h;
enum display_pixel_format pixfmt;
__ASSERT(desc->width <= desc->pitch, "Pitch is smaller then width");
__ASSERT((desc->pitch * ST7789V_PIXEL_SIZE * desc->height) <= desc->buf_size,
"Input buffer to small");
LOG_DBG("Writing %dx%d (w,h) @ %dx%d (x,y)",
desc->width, desc->height, x, y);
st7789v_set_mem_area(dev, x, y, desc->width, desc->height);
if (desc->pitch > desc->width) {
write_h = 1U;
nbr_of_writes = desc->height;
mipi_desc.height = 1;
mipi_desc.buf_size = desc->pitch * ST7789V_PIXEL_SIZE;
} else {
write_h = desc->height;
nbr_of_writes = 1U;
mipi_desc.height = desc->height;
mipi_desc.buf_size = desc->width * write_h * ST7789V_PIXEL_SIZE;
}
if (IS_ENABLED(CONFIG_ST7789V_RGB565)) {
pixfmt = PIXEL_FORMAT_RGB_565;
} else if (IS_ENABLED(CONFIG_ST7789V_BGR565)) {
pixfmt = PIXEL_FORMAT_BGR_565;
} else {
pixfmt = PIXEL_FORMAT_RGB_888;
}
mipi_desc.width = desc->width;
/* Per MIPI API, pitch must always match width */
mipi_desc.pitch = desc->width;
/* Send RAMWR command */
st7789v_transmit(dev, ST7789V_CMD_RAMWR, NULL, 0);
for (uint16_t write_cnt = 0U; write_cnt < nbr_of_writes; ++write_cnt) {
mipi_dbi_write_display(config->mipi_dbi, &config->dbi_config,
write_data_start, &mipi_desc, pixfmt);
write_data_start += (desc->pitch * ST7789V_PIXEL_SIZE);
}
return 0;
}
static void st7789v_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct st7789v_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->width;
capabilities->y_resolution = config->height;
#ifdef CONFIG_ST7789V_RGB565
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565;
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565;
#elif CONFIG_ST7789V_BGR565
capabilities->supported_pixel_formats = PIXEL_FORMAT_BGR_565;
capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
#else
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_888;
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_888;
#endif
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static int st7789v_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
#ifdef CONFIG_ST7789V_RGB565
if (pixel_format == PIXEL_FORMAT_RGB_565) {
#elif CONFIG_ST7789V_BGR565
if (pixel_format == PIXEL_FORMAT_BGR_565) {
#else
if (pixel_format == PIXEL_FORMAT_RGB_888) {
#endif
return 0;
}
LOG_ERR("Pixel format change not implemented");
return -ENOTSUP;
}
static int st7789v_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
LOG_ERR("Changing display orientation not implemented");
return -ENOTSUP;
}
static void st7789v_lcd_init(const struct device *dev)
{
struct st7789v_data *data = dev->data;
const struct st7789v_config *config = dev->config;
uint8_t tmp;
st7789v_set_lcd_margins(dev, data->x_offset,
data->y_offset);
st7789v_transmit(dev, ST7789V_CMD_CMD2EN,
(uint8_t *)config->cmd2en_param,
sizeof(config->cmd2en_param));
st7789v_transmit(dev, ST7789V_CMD_PORCTRL,
(uint8_t *)config->porch_param,
sizeof(config->porch_param));
/* Digital Gamma Enable, default disabled */
tmp = 0x00;
st7789v_transmit(dev, ST7789V_CMD_DGMEN, &tmp, 1);
/* Frame Rate Control in Normal Mode, default value */
tmp = 0x0f;
st7789v_transmit(dev, ST7789V_CMD_FRCTRL2, &tmp, 1);
tmp = config->gctrl;
st7789v_transmit(dev, ST7789V_CMD_GCTRL, &tmp, 1);
tmp = config->vcom;
st7789v_transmit(dev, ST7789V_CMD_VCOMS, &tmp, 1);
if (config->vdv_vrh_enable) {
tmp = 0x01;
st7789v_transmit(dev, ST7789V_CMD_VDVVRHEN, &tmp, 1);
tmp = config->vrh_value;
st7789v_transmit(dev, ST7789V_CMD_VRH, &tmp, 1);
tmp = config->vdv_value;
st7789v_transmit(dev, ST7789V_CMD_VDS, &tmp, 1);
}
st7789v_transmit(dev, ST7789V_CMD_PWCTRL1,
(uint8_t *)config->pwctrl1_param,
sizeof(config->pwctrl1_param));
/* Memory Data Access Control */
tmp = config->mdac;
st7789v_transmit(dev, ST7789V_CMD_MADCTL, &tmp, 1);
/* Interface Pixel Format */
tmp = config->colmod;
st7789v_transmit(dev, ST7789V_CMD_COLMOD, &tmp, 1);
tmp = config->lcm;
st7789v_transmit(dev, ST7789V_CMD_LCMCTRL, &tmp, 1);
tmp = config->gamma;
st7789v_transmit(dev, ST7789V_CMD_GAMSET, &tmp, 1);
if (config->inversion_on) {
st7789v_transmit(dev, ST7789V_CMD_INV_ON, NULL, 0);
} else {
st7789v_transmit(dev, ST7789V_CMD_INV_OFF, NULL, 0);
}
st7789v_transmit(dev, ST7789V_CMD_PVGAMCTRL,
(uint8_t *)config->pvgam_param,
sizeof(config->pvgam_param));
st7789v_transmit(dev, ST7789V_CMD_NVGAMCTRL,
(uint8_t *)config->nvgam_param,
sizeof(config->nvgam_param));
st7789v_transmit(dev, ST7789V_CMD_RAMCTRL,
(uint8_t *)config->ram_param,
sizeof(config->ram_param));
st7789v_transmit(dev, ST7789V_CMD_RGBCTRL,
(uint8_t *)config->rgb_param,
sizeof(config->rgb_param));
}
static int st7789v_init(const struct device *dev)
{
const struct st7789v_config *config = dev->config;
if (!device_is_ready(config->mipi_dbi)) {
LOG_ERR("MIPI DBI device not ready");
return -ENODEV;
}
st7789v_reset_display(dev);
st7789v_blanking_on(dev);
st7789v_lcd_init(dev);
st7789v_exit_sleep(dev);
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int st7789v_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
st7789v_exit_sleep(dev);
break;
case PM_DEVICE_ACTION_SUSPEND:
st7789v_transmit(dev, ST7789V_CMD_SLEEP_IN, NULL, 0);
break;
default:
ret = -ENOTSUP;
break;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static const struct display_driver_api st7789v_api = {
.blanking_on = st7789v_blanking_on,
.blanking_off = st7789v_blanking_off,
.write = st7789v_write,
.get_capabilities = st7789v_get_capabilities,
.set_pixel_format = st7789v_set_pixel_format,
.set_orientation = st7789v_set_orientation,
};
#define ST7789V_WORD_SIZE(inst) \
((DT_INST_PROP(inst, mipi_mode) == MIPI_DBI_MODE_SPI_4WIRE) ? \
SPI_WORD_SET(8) : SPI_WORD_SET(9))
#define ST7789V_INIT(inst) \
static const struct st7789v_config st7789v_config_ ## inst = { \
.mipi_dbi = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.dbi_config = MIPI_DBI_CONFIG_DT_INST(inst, \
ST7789V_WORD_SIZE(inst) | \
SPI_OP_MODE_MASTER, 0), \
.vcom = DT_INST_PROP(inst, vcom), \
.gctrl = DT_INST_PROP(inst, gctrl), \
.vdv_vrh_enable = (DT_INST_NODE_HAS_PROP(inst, vrhs) \
&& DT_INST_NODE_HAS_PROP(inst, vdvs)), \
.vrh_value = DT_INST_PROP_OR(inst, vrhs, 0), \
.vdv_value = DT_INST_PROP_OR(inst, vdvs, 0), \
.mdac = DT_INST_PROP(inst, mdac), \
.gamma = DT_INST_PROP(inst, gamma), \
.colmod = DT_INST_PROP(inst, colmod), \
.lcm = DT_INST_PROP(inst, lcm), \
.inversion_on = !DT_INST_PROP(inst, inversion_off), \
.porch_param = DT_INST_PROP(inst, porch_param), \
.cmd2en_param = DT_INST_PROP(inst, cmd2en_param), \
.pwctrl1_param = DT_INST_PROP(inst, pwctrl1_param), \
.pvgam_param = DT_INST_PROP(inst, pvgam_param), \
.nvgam_param = DT_INST_PROP(inst, nvgam_param), \
.ram_param = DT_INST_PROP(inst, ram_param), \
.rgb_param = DT_INST_PROP(inst, rgb_param), \
.width = DT_INST_PROP(inst, width), \
.height = DT_INST_PROP(inst, height), \
}; \
\
static struct st7789v_data st7789v_data_ ## inst = { \
.x_offset = DT_INST_PROP(inst, x_offset), \
.y_offset = DT_INST_PROP(inst, y_offset), \
}; \
\
PM_DEVICE_DT_INST_DEFINE(inst, st7789v_pm_action); \
\
DEVICE_DT_INST_DEFINE(inst, &st7789v_init, PM_DEVICE_DT_INST_GET(inst), \
&st7789v_data_ ## inst, &st7789v_config_ ## inst, \
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \
&st7789v_api);
DT_INST_FOREACH_STATUS_OKAY(ST7789V_INIT)
``` | /content/code_sandbox/drivers/display/display_st7789v.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,545 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_elcdif
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <fsl_elcdif.h>
#ifdef CONFIG_HAS_MCUX_CACHE
#include <fsl_cache.h>
#endif
#ifdef CONFIG_MCUX_ELCDIF_PXP
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_mcux_pxp.h>
#endif
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(display_mcux_elcdif, CONFIG_DISPLAY_LOG_LEVEL);
/* Define the heap size. 512 bytes of padding are included for kernel heap structures */
K_HEAP_DEFINE(display_heap, CONFIG_MCUX_ELCDIF_FB_NUM * CONFIG_MCUX_ELCDIF_FB_SIZE + 512);
static const uint32_t supported_fmts = PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888;
struct mcux_elcdif_config {
LCDIF_Type *base;
void (*irq_config_func)(const struct device *dev);
elcdif_rgb_mode_config_t rgb_mode;
const struct pinctrl_dev_config *pincfg;
const struct gpio_dt_spec backlight_gpio;
const struct device *pxp;
};
struct mcux_elcdif_data {
/* Pointer to active framebuffer */
const uint8_t *active_fb;
/* Pointers to driver allocated framebuffers */
uint8_t *fb[CONFIG_MCUX_ELCDIF_FB_NUM];
enum display_pixel_format pixel_format;
size_t pixel_bytes;
size_t fb_bytes;
elcdif_rgb_mode_config_t rgb_mode;
struct k_sem sem;
/* Tracks index of next active driver framebuffer */
uint8_t next_idx;
#ifdef CONFIG_MCUX_ELCDIF_PXP
/* Given to when PXP completes operation */
struct k_sem pxp_done;
#endif
};
#ifdef CONFIG_MCUX_ELCDIF_PXP
static void mcux_elcdif_pxp_callback(const struct device *dma_dev, void *user_data,
uint32_t channel, int ret)
{
struct mcux_elcdif_data *data = user_data;
k_sem_give(&data->pxp_done);
}
#endif /* CONFIG_MCUX_ELCDIF_PXP */
static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
const struct mcux_elcdif_config *config = dev->config;
struct mcux_elcdif_data *dev_data = dev->data;
int h_idx;
const uint8_t *src;
uint8_t *dst;
int ret = 0;
bool full_fb = false;
__ASSERT((dev_data->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size,
"Input buffer too small");
LOG_DBG("W=%d, H=%d, @%d,%d", desc->width, desc->height, x, y);
if ((x == 0) && (y == 0) && (desc->width == config->rgb_mode.panelWidth) &&
(desc->height == config->rgb_mode.panelHeight) && (desc->pitch == desc->width)) {
/* We can use the display buffer directly, no need to copy it */
LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, (void *)buf);
dev_data->active_fb = buf;
full_fb = true;
} else if ((x == 0) && (y == 0) && (desc->width == config->rgb_mode.panelHeight) &&
(desc->height == config->rgb_mode.panelWidth) && (desc->pitch == desc->width) &&
IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP)) {
/* With the PXP, we can rotate this display buffer to align
* with output dimensions
*/
LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb, (void *)buf);
dev_data->active_fb = buf;
full_fb = true;
} else {
/* We must use partial framebuffer copy */
if (CONFIG_MCUX_ELCDIF_FB_NUM == 0) {
LOG_ERR("Partial display refresh requires driver framebuffers");
return -ENOTSUP;
} else if (dev_data->active_fb != dev_data->fb[dev_data->next_idx]) {
/*
* We must copy the entire current framebuffer to new
* buffer, since we wil change the active buffer
* address
*/
src = dev_data->active_fb;
dst = dev_data->fb[dev_data->next_idx];
memcpy(dst, src, dev_data->fb_bytes);
}
/* Now, write the display update into active framebuffer */
src = buf;
dst = dev_data->fb[dev_data->next_idx];
dst += dev_data->pixel_bytes * (y * config->rgb_mode.panelWidth + x);
for (h_idx = 0; h_idx < desc->height; h_idx++) {
memcpy(dst, src, dev_data->pixel_bytes * desc->width);
src += dev_data->pixel_bytes * desc->pitch;
dst += dev_data->pixel_bytes * config->rgb_mode.panelWidth;
}
LOG_DBG("Setting FB from %p->%p", (void *)dev_data->active_fb,
(void *)dev_data->fb[dev_data->next_idx]);
/* Set new active framebuffer */
dev_data->active_fb = dev_data->fb[dev_data->next_idx];
}
#ifdef CONFIG_HAS_MCUX_CACHE
DCACHE_CleanByRange((uint32_t)dev_data->active_fb, dev_data->fb_bytes);
#endif
#ifdef CONFIG_MCUX_ELCDIF_PXP
if (full_fb) {
/* Configure PXP using DMA API, and rotate/flip frame */
struct dma_config pxp_dma = {0};
struct dma_block_config pxp_block = {0};
/* Source buffer is input to display_write, we will
* place modified output into a driver framebuffer.
*/
dev_data->active_fb = dev_data->fb[dev_data->next_idx];
pxp_block.source_address = (uint32_t)buf;
pxp_block.dest_address = (uint32_t)dev_data->active_fb;
pxp_block.block_size = desc->buf_size;
/* DMA slot sets pixel format and rotation angle */
if (dev_data->pixel_format == PIXEL_FORMAT_BGR_565) {
pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB565);
} else if (dev_data->pixel_format == PIXEL_FORMAT_RGB_888) {
pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_RGB888);
} else if (dev_data->pixel_format == PIXEL_FORMAT_ARGB_8888) {
pxp_dma.dma_slot = DMA_MCUX_PXP_FMT(DMA_MCUX_PXP_FMT_ARGB8888);
} else {
/* Cannot rotate */
return -ENOTSUP;
}
if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_ROTATE_90)) {
pxp_dma.dma_slot |= DMA_MCUX_PXP_CMD(DMA_MCUX_PXP_CMD_ROTATE_90);
} else if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_ROTATE_180)) {
pxp_dma.dma_slot |= DMA_MCUX_PXP_CMD(DMA_MCUX_PXP_CMD_ROTATE_180);
} else if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_ROTATE_270)) {
pxp_dma.dma_slot |= DMA_MCUX_PXP_CMD(DMA_MCUX_PXP_CMD_ROTATE_270);
} else {
pxp_dma.dma_slot |= DMA_MCUX_PXP_CMD(DMA_MCUX_PXP_CMD_ROTATE_0);
}
/* DMA linked_channel sets the flip direction */
if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_FLIP_HORIZONTAL)) {
pxp_dma.linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_HORIZONTAL);
} else if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_FLIP_VERTICAL)) {
pxp_dma.linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_VERTICAL);
} else if (IS_ENABLED(CONFIG_MCUX_ELCDIF_PXP_FLIP_BOTH)) {
pxp_dma.linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_BOTH);
} else {
pxp_dma.linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_DISABLE);
}
pxp_dma.channel_direction = MEMORY_TO_MEMORY;
pxp_dma.source_data_size = desc->width * dev_data->pixel_bytes;
pxp_dma.dest_data_size = config->rgb_mode.panelWidth * dev_data->pixel_bytes;
/* Burst lengths are heights of source/dest buffer in pixels */
pxp_dma.source_burst_length = desc->height;
pxp_dma.dest_burst_length = config->rgb_mode.panelHeight;
pxp_dma.head_block = &pxp_block;
pxp_dma.dma_callback = mcux_elcdif_pxp_callback;
pxp_dma.user_data = dev_data;
ret = dma_config(config->pxp, 0, &pxp_dma);
if (ret < 0) {
return ret;
}
ret = dma_start(config->pxp, 0);
if (ret < 0) {
return ret;
}
k_sem_take(&dev_data->pxp_done, K_FOREVER);
} else {
LOG_WRN("PXP rotation/flip will not work correctly unless a full sized "
"framebuffer is provided");
}
#endif /* CONFIG_MCUX_ELCDIF_PXP */
/* Queue next framebuffer */
ELCDIF_SetNextBufferAddr(config->base, (uint32_t)dev_data->active_fb);
#if CONFIG_MCUX_ELCDIF_FB_NUM != 0
/* Update index of active framebuffer */
dev_data->next_idx = (dev_data->next_idx + 1) % CONFIG_MCUX_ELCDIF_FB_NUM;
#endif
if (IS_ENABLED(CONFIG_MCUX_ELCDIF_LP)) {
ELCDIF_EnableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable);
}
/* Wait for frame send to complete */
k_sem_take(&dev_data->sem, K_FOREVER);
return ret;
}
static int mcux_elcdif_display_blanking_off(const struct device *dev)
{
const struct mcux_elcdif_config *config = dev->config;
return gpio_pin_set_dt(&config->backlight_gpio, 1);
}
static int mcux_elcdif_display_blanking_on(const struct device *dev)
{
const struct mcux_elcdif_config *config = dev->config;
return gpio_pin_set_dt(&config->backlight_gpio, 0);
}
static int mcux_elcdif_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct mcux_elcdif_data *dev_data = dev->data;
const struct mcux_elcdif_config *config = dev->config;
if (!(pixel_format & supported_fmts)) {
LOG_ERR("Unsupported pixel format");
return -ENOTSUP;
}
dev_data->pixel_format = pixel_format;
dev_data->pixel_bytes = DISPLAY_BITS_PER_PIXEL(pixel_format) / 8;
dev_data->fb_bytes =
config->rgb_mode.panelWidth * config->rgb_mode.panelHeight * dev_data->pixel_bytes;
for (int i = 0; i < CONFIG_MCUX_ELCDIF_FB_NUM; i++) {
k_heap_free(&display_heap, dev_data->fb[i]);
dev_data->fb[i] =
k_heap_aligned_alloc(&display_heap, 64, dev_data->fb_bytes, K_FOREVER);
if (dev_data->fb[i] == NULL) {
LOG_ERR("Could not allocate memory for framebuffers");
return -ENOMEM;
}
memset(dev_data->fb[i], 0, dev_data->fb_bytes);
}
dev_data->rgb_mode = config->rgb_mode;
if (pixel_format == PIXEL_FORMAT_BGR_565) {
dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB565;
} else if (pixel_format == PIXEL_FORMAT_RGB_888) {
dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatRGB888;
} else if (pixel_format == PIXEL_FORMAT_ARGB_8888) {
dev_data->rgb_mode.pixelFormat = kELCDIF_PixelFormatXRGB8888;
}
ELCDIF_RgbModeSetPixelFormat(config->base, dev_data->rgb_mode.pixelFormat);
return 0;
}
static int mcux_elcdif_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
LOG_ERR("Changing display orientation not implemented");
return -ENOTSUP;
}
static void mcux_elcdif_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct mcux_elcdif_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->rgb_mode.panelWidth;
capabilities->y_resolution = config->rgb_mode.panelHeight;
capabilities->supported_pixel_formats = supported_fmts;
capabilities->current_pixel_format = ((struct mcux_elcdif_data *)dev->data)->pixel_format;
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static void mcux_elcdif_isr(const struct device *dev)
{
const struct mcux_elcdif_config *config = dev->config;
struct mcux_elcdif_data *dev_data = dev->data;
uint32_t status;
status = ELCDIF_GetInterruptStatus(config->base);
ELCDIF_ClearInterruptStatus(config->base, status);
if (config->base->CUR_BUF == ((uint32_t)dev_data->active_fb)) {
if (IS_ENABLED(CONFIG_MCUX_ELCDIF_LP)) {
/* Disable frame completion interrupt if Low power mode is activated*/
ELCDIF_DisableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable);
}
/* Post to sem to notify that frame display is complete.*/
k_sem_give(&dev_data->sem);
}
}
static int mcux_elcdif_init(const struct device *dev)
{
const struct mcux_elcdif_config *config = dev->config;
struct mcux_elcdif_data *dev_data = dev->data;
int err;
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
err = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
return err;
}
k_sem_init(&dev_data->sem, 0, 1);
#ifdef CONFIG_MCUX_ELCDIF_PXP
k_sem_init(&dev_data->pxp_done, 0, 1);
if (!device_is_ready(config->pxp)) {
LOG_ERR("PXP device is not ready");
return -ENODEV;
}
#endif
config->irq_config_func(dev);
/* Set default pixel format obtained from device tree */
mcux_elcdif_set_pixel_format(dev, dev_data->pixel_format);
dev_data->active_fb = dev_data->fb[0];
ELCDIF_RgbModeInit(config->base, &dev_data->rgb_mode);
if (!IS_ENABLED(CONFIG_MCUX_ELCDIF_LP)) {
ELCDIF_EnableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable);
}
ELCDIF_RgbModeStart(config->base);
return 0;
}
static const struct display_driver_api mcux_elcdif_api = {
.blanking_on = mcux_elcdif_display_blanking_on,
.blanking_off = mcux_elcdif_display_blanking_off,
.write = mcux_elcdif_write,
.get_capabilities = mcux_elcdif_get_capabilities,
.set_pixel_format = mcux_elcdif_set_pixel_format,
.set_orientation = mcux_elcdif_set_orientation,
};
#define MCUX_ELCDIF_DEVICE_INIT(id) \
PINCTRL_DT_INST_DEFINE(id); \
static void mcux_elcdif_config_func_##id(const struct device *dev); \
static const struct mcux_elcdif_config mcux_elcdif_config_##id = { \
.base = (LCDIF_Type *)DT_INST_REG_ADDR(id), \
.irq_config_func = mcux_elcdif_config_func_##id, \
.rgb_mode = \
{ \
.panelWidth = DT_INST_PROP(id, width), \
.panelHeight = DT_INST_PROP(id, height), \
.hsw = DT_PROP(DT_INST_CHILD(id, display_timings), hsync_len), \
.hfp = DT_PROP(DT_INST_CHILD(id, display_timings), hfront_porch), \
.hbp = DT_PROP(DT_INST_CHILD(id, display_timings), hback_porch), \
.vsw = DT_PROP(DT_INST_CHILD(id, display_timings), vsync_len), \
.vfp = DT_PROP(DT_INST_CHILD(id, display_timings), vfront_porch), \
.vbp = DT_PROP(DT_INST_CHILD(id, display_timings), vback_porch), \
.polarityFlags = \
(DT_PROP(DT_INST_CHILD(id, display_timings), hsync_active) \
? kELCDIF_HsyncActiveHigh \
: kELCDIF_HsyncActiveLow) | \
(DT_PROP(DT_INST_CHILD(id, display_timings), vsync_active) \
? kELCDIF_VsyncActiveHigh \
: kELCDIF_VsyncActiveLow) | \
(DT_PROP(DT_INST_CHILD(id, display_timings), de_active) \
? kELCDIF_DataEnableActiveHigh \
: kELCDIF_DataEnableActiveLow) | \
(DT_PROP(DT_INST_CHILD(id, display_timings), \
pixelclk_active) \
? kELCDIF_DriveDataOnRisingClkEdge \
: kELCDIF_DriveDataOnFallingClkEdge), \
.dataBus = LCDIF_CTRL_LCD_DATABUS_WIDTH( \
DT_INST_ENUM_IDX(id, data_bus_width)), \
}, \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id), \
.backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios), \
IF_ENABLED(CONFIG_MCUX_ELCDIF_PXP, \
(.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),))}; \
static struct mcux_elcdif_data mcux_elcdif_data_##id = { \
.next_idx = 0, \
.pixel_format = DT_INST_PROP(id, pixel_format), \
}; \
DEVICE_DT_INST_DEFINE(id, &mcux_elcdif_init, NULL, &mcux_elcdif_data_##id, \
&mcux_elcdif_config_##id, POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, \
&mcux_elcdif_api); \
static void mcux_elcdif_config_func_##id(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), mcux_elcdif_isr, \
DEVICE_DT_INST_GET(id), 0); \
irq_enable(DT_INST_IRQN(id)); \
}
DT_INST_FOREACH_STATUS_OKAY(MCUX_ELCDIF_DEVICE_INIT)
``` | /content/code_sandbox/drivers/display/display_mcux_elcdif.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,379 |
```unknown
menuconfig DISPLAY_MCUX_ELCDIF
bool "MCUX eLCDIF driver"
default y
depends on DT_HAS_NXP_IMX_ELCDIF_ENABLED
help
Enable support for mcux eLCDIF driver.
if DISPLAY_MCUX_ELCDIF
config MCUX_ELCDIF_FB_NUM
int "Framebuffers to allocate in driver"
default 2
range 0 2
help
Number of framebuffers to allocate in ELCDIF driver. Driver allocated
framebuffers are required to support partial display updates.
The driver has been validated to support 0 through 2 framebuffers.
Note that hardware will likely perform best if zero driver
framebuffers are allocated by the driver, and the application
implements double framebuffering by always calling display_write with
a buffer equal in size to the connected panel.
NOTE: when no framebuffers are allocated, the ELCDIF will be
set to display an empty buffer during initialization. This means
the display will show what is effectively a dump of
system RAM until a new framebuffer is written. If the security
implications of this concern you, leave at least one driver
framebuffer enabled.
config MCUX_ELCDIF_FB_SIZE
int "Framebuffer size required by the eLCDIF driver"
default 3686400
help
eLCDIF driver allocates framebuffers to support partial display updates.
The framebuffer size is computed as : panel_width * panel_height * bpp.
The default value is set to afford for a default resolution of 1280x720 and
4-bytes pixel format, e.g. ARGB8888. Applications should change this value
according to the actual used resolution and format to optimize the heap size.
config MCUX_ELCDIF_PXP
bool "Use PXP for display rotation"
depends on MCUX_PXP
depends on (MCUX_ELCDIF_FB_NUM > 0)
help
Use the PXP for display rotation. This requires the LCDIF node
have a "nxp,pxp" devicetree property pointing to the PXP device node.
The ELCDIF will only utilize the PXP to rotate frames if
display_write is called with a framebuffer equal in size to the
display.
config MCUX_ELCDIF_LP
bool "ELCDIF low power"
help
This option, when enabled, will enable CUR_FRAME_DONE_IRQ at the display
write function and disable it at the interruption handler for each new frame.
Disabling the interrupt when no new frame needs to be sent gives the CPU the
possibility to enter low-power mode, thus saving energy.
This option, when disabled, CUR_FRAME_DONE_IRQ will be enabled only
once at initialization. This option should be disabled when the application's
frame rate is close to the display's refresh rate to avoid introducing
additional latency caused by frequently enabling and disabling CUR_FRAME_DONE_IRQ.
if MCUX_ELCDIF_PXP
choice MCUX_ELCDIF_PXP_ROTATE_DIRECTION
default MCUX_ELCDIF_PXP_ROTATE_0
prompt "Rotation angle of PXP"
help
Set rotation angle of PXP. The ELCDIF cannot detect the correct
rotation angle based on the call to display_write, so the user should
configure it here. In order for PXP rotation to work, calls to
display_write MUST supply a framebuffer equal in size to screen width
and height (without rotation applied). Note that the width and
height settings of the screen in devicetree should not be modified
from their values in the default screen orientation when using this
functionality.
config MCUX_ELCDIF_PXP_ROTATE_0
bool "Rotate display by 0 degrees"
help
Rotate display by 0 degrees. Primarily useful for testing,
production applications should simply disable the PXP.
config MCUX_ELCDIF_PXP_ROTATE_90
bool "Rotate display by 90 degrees"
help
Rotate display counter-clockwise by 90 degrees.
For LVGL, this corresponds to a rotation of 270 degrees
config MCUX_ELCDIF_PXP_ROTATE_180
bool "Rotate display by 180 degrees"
help
Rotate display counter-clockwise by 180 degrees
config MCUX_ELCDIF_PXP_ROTATE_270
bool "Rotate display by 270 degrees"
help
Rotate display counter-clockwise by 270 degrees
For LVGL, this corresponds to a rotation of 90 degrees
endchoice
choice MCUX_ELCDIF_PXP_FLIP_DIRECTION
default MCUX_ELCDIF_PXP_FLIP_DISABLE
prompt "Flip direction of PXP"
help
Set flip direction of PXP. The ELCDIF cannot detect the correct
rotation angle based on the call to display_write, so the user should
configure it here. In order for PXP flip to work, calls to
display_write MUST supply a framebuffer equal in size to screen width
and height (without flip applied). Note that the width and
height settings of the screen in devicetree should not be modified
from their values in the default screen orientation when using this
functionality.
config MCUX_ELCDIF_PXP_FLIP_DISABLE
bool "Do not flip display"
config MCUX_ELCDIF_PXP_FLIP_HORIZONTAL
bool "Flip display horizontally"
config MCUX_ELCDIF_PXP_FLIP_VERTICAL
bool "Flip display vertically"
config MCUX_ELCDIF_PXP_FLIP_BOTH
bool "Flib display both horizontally and vertically"
endchoice
endif # MCUX_ELCDIF_PXP
endif # DISPLAY_MCUX_ELCDIF
``` | /content/code_sandbox/drivers/display/Kconfig.mcux_elcdif | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,211 |
```c
/*
*
*/
#define DT_DRV_COMPAT orisetech_otm8009a
#include <zephyr/kernel.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(otm8009a, CONFIG_DISPLAY_LOG_LEVEL);
#include "display_otm8009a.h"
struct otm8009a_config {
const struct device *mipi_dsi;
const struct gpio_dt_spec reset;
const struct gpio_dt_spec backlight;
uint8_t data_lanes;
uint16_t width;
uint16_t height;
uint8_t channel;
uint16_t rotation;
};
struct otm8009a_data {
uint16_t xres;
uint16_t yres;
uint8_t dsi_pixel_format;
enum display_pixel_format pixel_format;
enum display_orientation orientation;
};
static inline int otm8009a_dcs_write(const struct device *dev, uint8_t cmd, const void *buf,
size_t len)
{
const struct otm8009a_config *cfg = dev->config;
int ret;
ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, cmd, buf, len);
if (ret < 0) {
LOG_ERR("DCS 0x%x write failed! (%d)", cmd, ret);
return ret;
}
return 0;
}
static int otm8009a_mcs_write(const struct device *dev, uint16_t cmd, const void *buf, size_t len)
{
const struct otm8009a_config *cfg = dev->config;
uint8_t scmd;
int ret;
scmd = cmd & 0xFF;
ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, OTM8009A_MCS_ADRSFT, &scmd, 1);
if (ret < 0) {
return ret;
}
ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, cmd >> 8, buf, len);
if (ret < 0) {
return ret;
}
return 0;
}
static int otm8009a_check_id(const struct device *dev)
{
const struct otm8009a_config *cfg = dev->config;
uint32_t id = 0;
int ret;
ret = mipi_dsi_dcs_read(cfg->mipi_dsi, cfg->channel, OTM8009A_CMD_ID1, &id, sizeof(id));
if (ret != sizeof(id)) {
LOG_ERR("Read panel ID failed! (%d)", ret);
return -EIO;
}
if (id != OTM8009A_ID1) {
LOG_ERR("ID 0x%x (should 0x%x)", id, OTM8009A_ID1);
return -EINVAL;
}
return 0;
}
static int otm8009a_configure(const struct device *dev)
{
struct otm8009a_data *data = dev->data;
uint8_t buf[4];
int ret;
static const uint8_t pwr_ctrl2[] = {0x96, 0x34, 0x01, 0x33, 0x33, 0x34, 0x33};
static const uint8_t sd_ctrl[] = {0x0D, 0x1B, 0x02, 0x01, 0x3C, 0x08};
static const uint8_t goavst[] = {
0x85, 0x01, 0x00, 0x84, 0x01, 0x00, 0x81, 0x01, 0x28, 0x82, 0x01, 0x28
};
static const uint8_t goaclka1[] = {0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 0x00};
static const uint8_t goaclka2[] = {0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00};
static const uint8_t goaclka3[] = {0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 0x00};
static const uint8_t goaclka4[] = {0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00};
static const uint8_t goaeclk[] = {0x01, 0x01, 0x20, 0x20, 0x00, 0x00};
static const uint8_t panctrlset1[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t panctrlset2[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t panctrlset3[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t panctrlset4[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t panctrlset5[] = {
0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t panctrlset6[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t panctrlset7[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t panctrlset8[] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
};
static const uint8_t panu2d1[] = {
0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t panu2d2[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C,
0x02
};
static const uint8_t panu2d3[] = {
0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t pand2u1[] = {
0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t pand2u2[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09,
0x01
};
static const uint8_t pand2u3[] = {
0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
static const uint8_t pgamma[] = {
0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10,
0x0A, 0x01
};
static const uint8_t ngamma[] = {
0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10,
0x0A, 0x01
};
/* enter command 2 mode to access manufacturer registers (ref. 5.3) */
buf[0] = 0x80;
buf[1] = 0x09;
buf[2] = 0x01;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_CMD2_ENA1, buf, 3);
if (ret < 0) {
return ret;
}
/* enter Orise command 2 mode */
buf[0] = 0x80;
buf[1] = 0x09;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_CMD2_ENA2, buf, 2);
if (ret < 0) {
return ret;
}
/* source driver precharge control */
buf[0] = 0x30;
buf[1] = 0x8A;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_SD_PCH_CTRL, buf, 2);
if (ret < 0) {
return ret;
}
/* not documented */
buf[0] = 0x40;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC1, buf, 1);
if (ret < 0) {
return ret;
}
/* power control settings 4 for DC voltage settings */
/* enable GVDD test mode */
buf[0] = 0x04;
buf[1] = 0xA9;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PWR_CTRL4, buf, 2);
if (ret < 0) {
return ret;
}
/* power control settings 2 for normal mode */
/* set pump 4 vgh voltage from 15.0v down to 13.0v */
/* set pump 5 vgh voltage from -12.0v downto -9.0v */
/* set pump 4&5 x6 (ONLY VALID when PUMP4_EN_ASDM_HV = "0") */
/* change pump4 clock ratio from 1 line to 1/2 line */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PWR_CTRL2, pwr_ctrl2, sizeof(pwr_ctrl2));
if (ret < 0) {
return ret;
}
/* panel driving mode */
/* set column inversion */
buf[0] = 0x50;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_P_DRV_M, buf, 1);
if (ret < 0) {
return ret;
}
/* VCOM voltage setting */
/* VCOM Voltage settings from -1.0000v downto -1.2625v */
buf[0] = 0x4E;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_VCOMDC, buf, 1);
if (ret < 0) {
return ret;
}
/* oscillator adjustment for idle/normal mode */
/* set 65Hz */
buf[0] = 0x66;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_OSC_ADJ, buf, 1);
if (ret < 0) {
return ret;
}
/* RGB video mode setting */
buf[0] = 0x08;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_RGB_VID_SET, buf, 1);
if (ret < 0) {
return ret;
}
/* GVDD/NGVDD */
buf[0] = 0x79;
buf[1] = 0x79;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GVDDSET, buf, 2);
if (ret < 0) {
return ret;
}
/* source driver timing setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_SD_CTRL, sd_ctrl, sizeof(sd_ctrl));
if (ret < 0) {
return ret;
}
/* panel type setting */
buf[0] = 0x00;
buf[1] = 0x01;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANSET, buf, 2);
if (ret < 0) {
return ret;
}
/* GOA VST setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOAVST, goavst, sizeof(goavst));
if (ret < 0) {
return ret;
}
/* GOA CLKA1 setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOACLKA1, goaclka1, sizeof(goaclka1));
if (ret < 0) {
return ret;
}
/* GOA CLKA2 setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOACLKA2, goaclka2, sizeof(goaclka2));
if (ret < 0) {
return ret;
}
/* GOA CLKA3 setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOACLKA3, goaclka3, sizeof(goaclka3));
if (ret < 0) {
return ret;
}
/* GOA CLKA4 setting */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOACLKA4, goaclka4, sizeof(goaclka4));
if (ret < 0) {
return ret;
}
/* GOA ECLK */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOAECLK, goaeclk, sizeof(goaeclk));
if (ret < 0) {
return ret;
}
/** GOA Other Options 1 */
buf[0] = 0x01;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOAPT1, buf, 1);
if (ret < 0) {
return ret;
}
/* GOA Signal Toggle Option Setting */
buf[0] = 0x02;
buf[1] = 0x00;
buf[2] = 0x00;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GOATGOPT, buf, 3);
if (ret < 0) {
return ret;
}
/* not documented */
buf[0] = 0x00;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC2, buf, 1);
if (ret < 0) {
return ret;
}
/* Panel Control Setting 1 */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET1, panctrlset1, sizeof(panctrlset1));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET2, panctrlset2, sizeof(panctrlset2));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET3, panctrlset3, sizeof(panctrlset3));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET4, panctrlset4, sizeof(panctrlset4));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET5, panctrlset5, sizeof(panctrlset5));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET6, panctrlset6, sizeof(panctrlset6));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET7, panctrlset7, sizeof(panctrlset7));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANCTRLSET8, panctrlset8, sizeof(panctrlset8));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANU2D1, panu2d1, sizeof(panu2d1));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANU2D2, panu2d2, sizeof(panu2d2));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PANU2D3, panu2d3, sizeof(panu2d3));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PAND2U1, pand2u1, sizeof(pand2u1));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PAND2U2, pand2u2, sizeof(pand2u2));
if (ret < 0) {
return ret;
}
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PAND2U3, pand2u3, sizeof(pand2u3));
if (ret < 0) {
return ret;
}
/* power control setting 1 */
/* Pump 1 min and max DM */
buf[0] = 0x08;
buf[1] = 0x66;
buf[2] = 0x83;
buf[3] = 0x00;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PWR_CTRL1, buf, 4);
if (ret < 0) {
return ret;
}
/* not documented */
buf[0] = 0x06;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC3, buf, 1);
if (ret < 0) {
return ret;
}
/* PWM parameter 3 */
/* Freq: 19.5 KHz */
buf[0] = 0x06;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PWM_PARA3, buf, 1);
if (ret < 0) {
return ret;
}
/* gamma correction 2.2+ */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GMCT2_2P, pgamma, sizeof(pgamma));
if (ret < 0) {
return ret;
}
/* gamma correction 2.2- */
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_GMCT2_2N, ngamma, sizeof(ngamma));
if (ret < 0) {
return ret;
}
/* exit command 2 mode */
buf[0] = 0xFF;
buf[1] = 0xFF;
buf[2] = 0xFF;
ret = otm8009a_mcs_write(dev, OTM8009A_MCS_CMD2_ENA1, buf, 3);
if (ret < 0) {
return ret;
}
/* exit sleep mode */
ret = otm8009a_dcs_write(dev, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
if (ret < 0) {
return ret;
}
k_msleep(OTM8009A_EXIT_SLEEP_MODE_WAIT_TIME);
/* set pixel color format */
switch (data->dsi_pixel_format) {
case MIPI_DSI_PIXFMT_RGB565:
buf[0] = MIPI_DCS_PIXEL_FORMAT_16BIT;
break;
case MIPI_DSI_PIXFMT_RGB888:
buf[0] = MIPI_DCS_PIXEL_FORMAT_24BIT;
break;
default:
LOG_ERR("Unsupported pixel format 0x%x!", data->dsi_pixel_format);
return -ENOTSUP;
}
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_PIXEL_FORMAT, buf, 1);
if (ret < 0) {
return ret;
}
/* configure address mode */
if (data->orientation == DISPLAY_ORIENTATION_NORMAL) {
buf[0] = 0x00;
} else if (data->orientation == DISPLAY_ORIENTATION_ROTATED_90) {
buf[0] = MIPI_DCS_ADDRESS_MODE_MIRROR_X | MIPI_DCS_ADDRESS_MODE_SWAP_XY;
} else if (data->orientation == DISPLAY_ORIENTATION_ROTATED_180) {
buf[0] = MIPI_DCS_ADDRESS_MODE_MIRROR_X | MIPI_DCS_ADDRESS_MODE_MIRROR_Y;
} else if (data->orientation == DISPLAY_ORIENTATION_ROTATED_270) {
buf[0] = MIPI_DCS_ADDRESS_MODE_MIRROR_Y | MIPI_DCS_ADDRESS_MODE_SWAP_XY;
}
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_ADDRESS_MODE, buf, 1);
if (ret < 0) {
return ret;
}
buf[0] = 0x00;
buf[1] = 0x00;
sys_put_be16(data->xres, (uint8_t *)&buf[2]);
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_COLUMN_ADDRESS, buf, 4);
if (ret < 0) {
return ret;
}
buf[0] = 0x00;
buf[1] = 0x00;
sys_put_be16(data->yres, (uint8_t *)&buf[2]);
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_PAGE_ADDRESS, buf, 4);
if (ret < 0) {
return ret;
}
/* backlight control */
buf[0] = OTM8009A_WRCTRLD_BCTRL | OTM8009A_WRCTRLD_DD | OTM8009A_WRCTRLD_BL;
ret = otm8009a_dcs_write(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, buf, 1);
if (ret < 0) {
return ret;
}
/* adaptive brightness control */
buf[0] = OTM8009A_WRCABC_UI;
ret = otm8009a_dcs_write(dev, MIPI_DCS_WRITE_POWER_SAVE, buf, 1);
if (ret < 0) {
return ret;
}
/* adaptive brightness control minimum brightness */
buf[0] = 0xFF;
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, buf, 1);
if (ret < 0) {
return ret;
}
/* brightness */
buf[0] = 0xFF;
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, buf, 1);
if (ret < 0) {
return ret;
}
/* Display On */
ret = otm8009a_dcs_write(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
if (ret < 0) {
return ret;
}
/* trigger display write (from data coming by DSI bus) */
ret = otm8009a_dcs_write(dev, MIPI_DCS_WRITE_MEMORY_START, NULL, 0);
if (ret < 0) {
return ret;
}
return 0;
}
static int otm8009a_blanking_on(const struct device *dev)
{
const struct otm8009a_config *cfg = dev->config;
int ret;
if (cfg->backlight.port != NULL) {
ret = gpio_pin_set_dt(&cfg->backlight, 0);
if (ret) {
LOG_ERR("Disable backlight failed! (%d)", ret);
return ret;
}
}
return otm8009a_dcs_write(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
}
static int otm8009a_blanking_off(const struct device *dev)
{
const struct otm8009a_config *cfg = dev->config;
int ret;
if (cfg->backlight.port != NULL) {
ret = gpio_pin_set_dt(&cfg->backlight, 1);
if (ret) {
LOG_ERR("Enable backlight failed! (%d)", ret);
return ret;
}
}
return otm8009a_dcs_write(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
}
static int otm8009a_write(const struct device *dev, uint16_t x, uint16_t y,
const struct display_buffer_descriptor *desc, const void *buf)
{
return -ENOTSUP;
}
static int otm8009a_set_brightness(const struct device *dev, uint8_t brightness)
{
return otm8009a_dcs_write(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 1);
}
static void otm8009a_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct otm8009a_config *cfg = dev->config;
struct otm8009a_data *data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = cfg->width;
capabilities->y_resolution = cfg->height;
capabilities->supported_pixel_formats = data->pixel_format;
capabilities->current_pixel_format = data->pixel_format;
capabilities->current_orientation = data->orientation;
}
static const struct display_driver_api otm8009a_api = {
.blanking_on = otm8009a_blanking_on,
.blanking_off = otm8009a_blanking_off,
.write = otm8009a_write,
.set_brightness = otm8009a_set_brightness,
.get_capabilities = otm8009a_get_capabilities,
};
static int otm8009a_init(const struct device *dev)
{
const struct otm8009a_config *cfg = dev->config;
struct otm8009a_data *data = dev->data;
struct mipi_dsi_device mdev;
int ret;
if (cfg->reset.port) {
if (!gpio_is_ready_dt(&cfg->reset)) {
LOG_ERR("Reset GPIO device is not ready!");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_ERR("Reset display failed! (%d)", ret);
return ret;
}
k_msleep(OTM8009A_RESET_TIME);
ret = gpio_pin_set_dt(&cfg->reset, 1);
if (ret < 0) {
LOG_ERR("Enable display failed! (%d)", ret);
return ret;
}
k_msleep(OTM8009A_WAKE_TIME);
}
/* store x/y resolution & rotation */
if (cfg->rotation == 0) {
data->xres = cfg->width;
data->yres = cfg->height;
data->orientation = DISPLAY_ORIENTATION_NORMAL;
} else if (cfg->rotation == 90) {
data->xres = cfg->height;
data->yres = cfg->width;
data->orientation = DISPLAY_ORIENTATION_ROTATED_90;
} else if (cfg->rotation == 180) {
data->xres = cfg->width;
data->yres = cfg->height;
data->orientation = DISPLAY_ORIENTATION_ROTATED_180;
} else if (cfg->rotation == 270) {
data->xres = cfg->height;
data->yres = cfg->width;
data->orientation = DISPLAY_ORIENTATION_ROTATED_270;
}
/* attach to MIPI-DSI host */
mdev.data_lanes = cfg->data_lanes;
mdev.pixfmt = data->dsi_pixel_format;
mdev.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM;
mdev.timings.hactive = data->xres;
mdev.timings.hbp = OTM8009A_HBP;
mdev.timings.hfp = OTM8009A_HFP;
mdev.timings.hsync = OTM8009A_HSYNC;
mdev.timings.vactive = data->yres;
mdev.timings.vbp = OTM8009A_VBP;
mdev.timings.vfp = OTM8009A_VFP;
mdev.timings.vsync = OTM8009A_VSYNC;
ret = mipi_dsi_attach(cfg->mipi_dsi, cfg->channel, &mdev);
if (ret < 0) {
LOG_ERR("MIPI-DSI attach failed! (%d)", ret);
return ret;
}
ret = otm8009a_check_id(dev);
if (ret) {
LOG_ERR("Panel ID check failed! (%d)", ret);
return ret;
}
ret = otm8009a_configure(dev);
if (ret) {
LOG_ERR("DSI init sequence failed! (%d)", ret);
return ret;
}
ret = otm8009a_blanking_off(dev);
if (ret) {
LOG_ERR("Display blanking off failed! (%d)", ret);
return ret;
}
return 0;
}
#define OTM8009A_DEVICE(inst) \
static const struct otm8009a_config otm8009a_config_##inst = { \
.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \
.backlight = GPIO_DT_SPEC_INST_GET_OR(inst, bl_gpios, {0}), \
.data_lanes = DT_INST_PROP_BY_IDX(inst, data_lanes, 0), \
.width = DT_INST_PROP(inst, width), \
.height = DT_INST_PROP(inst, height), \
.channel = DT_INST_REG_ADDR(inst), \
.rotation = DT_INST_PROP(inst, rotation), \
}; \
static struct otm8009a_data otm8009a_data_##inst = { \
.dsi_pixel_format = DT_INST_PROP(inst, pixel_format), \
}; \
DEVICE_DT_INST_DEFINE(inst, &otm8009a_init, NULL, &otm8009a_data_##inst, \
&otm8009a_config_##inst, POST_KERNEL, \
CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY, &otm8009a_api); \
DT_INST_FOREACH_STATUS_OKAY(OTM8009A_DEVICE)
``` | /content/code_sandbox/drivers/display/display_otm8009a.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,579 |
```unknown
# Display drivers
menuconfig DISPLAY
bool "Display controller drivers"
help
Enable display drivers
if DISPLAY
config DISPLAY_INIT_PRIORITY
int "Display devices init priority"
default 85
help
Display devices initialization priority.
module = DISPLAY
module-str = display
source "subsys/logging/Kconfig.template.log_config"
source "drivers/display/Kconfig.mcux_elcdif"
source "drivers/display/Kconfig.microbit"
source "drivers/display/Kconfig.nrf_led_matrix"
source "drivers/display/Kconfig.ili9xxx"
source "drivers/display/Kconfig.sdl"
source "drivers/display/Kconfig.ssd1306"
source "drivers/display/Kconfig.ssd1327"
source "drivers/display/Kconfig.ssd16xx"
source "drivers/display/Kconfig.st7735r"
source "drivers/display/Kconfig.st7789v"
source "drivers/display/Kconfig.st7796s"
source "drivers/display/Kconfig.stm32_ltdc"
source "drivers/display/Kconfig.uc81xx"
source "drivers/display/Kconfig.dummy"
source "drivers/display/Kconfig.ls0xx"
source "drivers/display/Kconfig.rm67162"
source "drivers/display/Kconfig.rm68200"
source "drivers/display/Kconfig.max7219"
source "drivers/display/Kconfig.intel_multibootfb"
source "drivers/display/Kconfig.mcux_dcnano_lcdif"
source "drivers/display/Kconfig.otm8009a"
source "drivers/display/Kconfig.hx8394"
source "drivers/display/Kconfig.gc9x01x"
source "drivers/display/Kconfig.led_strip_matrix"
source "drivers/display/Kconfig.renesas_lcdc"
source "drivers/display/Kconfig.nt35510"
endif # DISPLAY
``` | /content/code_sandbox/drivers/display/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 358 |
```unknown
config RM67162
bool "RM67162 display driver"
default y
select MIPI_DSI
depends on DT_HAS_RAYDIUM_RM67162_ENABLED
help
Enable driver for RM67162 display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.rm67162 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```c
/*
*
*/
#include <zephyr/display/mb_display.h>
#include "mb_font.h"
const struct mb_image mb_font[MB_FONT_COUNT] = {
/* ' ' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '!' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '"' */
MB_IMAGE({ 0, 1, 0, 1, 0 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '#' */
MB_IMAGE({ 0, 1, 0, 1, 0 },
{ 1, 1, 1, 1, 1 },
{ 0, 1, 0, 1, 0 },
{ 1, 1, 1, 1, 1 },
{ 0, 1, 0, 1, 0 }),
/* '$' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 1, 0, 0, 1 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 1 },
{ 0, 1, 1, 1, 0 }),
/* '%' */
MB_IMAGE({ 1, 1, 0, 0, 1 },
{ 1, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 1 },
{ 1, 0, 0, 1, 1 }),
/* '&' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 1 }),
/* ''' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '(' */
MB_IMAGE({ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 }),
/* ')' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '*' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 0, 0, 0 }),
/* '+' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* ',' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '-' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '.' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '/' */
MB_IMAGE({ 0, 0, 0, 0, 1 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* '0' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* '1' */
MB_IMAGE({ 0, 0, 1, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 1, 1, 0 }),
/* '2' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 }),
/* '3' */
MB_IMAGE({ 1, 1, 1, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* '4' */
MB_IMAGE({ 0, 0, 1, 1, 0 },
{ 0, 1, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 1, 1 },
{ 0, 0, 0, 1, 0 }),
/* '5' */
MB_IMAGE({ 1, 1, 1, 1, 1 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 },
{ 0, 0, 0, 0, 1 },
{ 1, 1, 1, 1, 0 }),
/* '6' */
MB_IMAGE({ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 1, 1, 0 }),
/* '7' */
MB_IMAGE({ 1, 1, 1, 1, 1 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* '8' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 1, 1, 0 }),
/* '9' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* ':' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* ';' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '<' */
MB_IMAGE({ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 1, 0 }),
/* '=' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 0, 0 }),
/* '>' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '?' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 0, 1, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 0, 0 }),
/* '@' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 0, 0, 1, 1 },
{ 0, 1, 1, 0, 0 }),
/* 'A' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'B' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 }),
/* 'C' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 }),
/* 'D' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 }),
/* 'E' */
MB_IMAGE({ 1, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 }),
/* 'F' */
MB_IMAGE({ 1, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* 'G' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 1, 1 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 1, 1, 0 }),
/* 'H' */
MB_IMAGE({ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'I' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 1, 1, 0, 0 }),
/* 'J' */
MB_IMAGE({ 1, 1, 1, 1, 1 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'K' */
MB_IMAGE({ 1, 0, 0, 1, 0 },
{ 1, 0, 1, 0, 0 },
{ 1, 1, 0, 0, 0 },
{ 1, 0, 1, 0, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'L' */
MB_IMAGE({ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 }),
/* 'M' */
MB_IMAGE({ 1, 0, 0, 0, 1 },
{ 1, 1, 0, 1, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 }),
/* 'N' */
MB_IMAGE({ 1, 0, 0, 0, 1 },
{ 1, 1, 0, 0, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 0, 0, 1, 1 },
{ 1, 0, 0, 0, 1 }),
/* 'O' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'P' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* 'Q' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 0, 1, 1, 0 }),
/* 'R' */
MB_IMAGE({ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 0, 1 }),
/* 'S' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 }),
/* 'T' */
MB_IMAGE({ 1, 1, 1, 1, 1 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 }),
/* 'U' */
MB_IMAGE({ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'V' */
MB_IMAGE({ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 }),
/* 'W' */
MB_IMAGE({ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 1, 0, 1, 1 },
{ 1, 0, 0, 0, 1 }),
/* 'X' */
MB_IMAGE({ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'Y' */
MB_IMAGE({ 1, 0, 0, 0, 1 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 0, 0 }),
/* 'Z' */
MB_IMAGE({ 1, 1, 1, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 }),
/* '[' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 1, 1, 0 }),
/* '\' */
MB_IMAGE({ 1, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 0, 1 }),
/* ']' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 0 }),
/* '^' */
MB_IMAGE({ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* '_' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 1 }),
/* '`' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 }),
/* 'a' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 1 }),
/* 'b' */
MB_IMAGE({ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 }),
/* 'c' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 }),
/* 'd' */
MB_IMAGE({ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 0 }),
/* 'e' */
MB_IMAGE({ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 }),
/* 'f' */
MB_IMAGE({ 0, 0, 1, 1, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* 'g' */
MB_IMAGE({ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'h' */
MB_IMAGE({ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'i' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* 'j' */
MB_IMAGE({ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'k' */
MB_IMAGE({ 1, 0, 0, 0, 0 },
{ 1, 0, 1, 0, 0 },
{ 1, 1, 0, 0, 0 },
{ 1, 0, 1, 0, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'l' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 1, 0 }),
/* 'm' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 1, 0, 1, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 }),
/* 'n' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'o' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 }),
/* 'p' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 1, 1, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* 'q' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 0, 0, 1, 0 }),
/* 'r' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 0 }),
/* 's' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 1, 1, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 1, 1, 0, 0, 0 }),
/* 't' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 1, 1, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 0, 1, 1, 1 }),
/* 'u' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 1 }),
/* 'v' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 }),
/* 'w' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 1, 0, 1 },
{ 1, 1, 0, 1, 1 }),
/* 'x' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 1, 0, 0, 1, 0 }),
/* 'y' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 1, 1, 0, 0, 0 }),
/* 'z' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 1, 1, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 1, 1, 1, 0 }),
/* '{' */
MB_IMAGE({ 0, 0, 1, 1, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 0, 1, 0, 0 },
{ 0, 0, 1, 1, 0 }),
/* '|' */
MB_IMAGE({ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 }),
/* '}' */
MB_IMAGE({ 1, 1, 0, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 1, 0, 0, 0 },
{ 1, 1, 0, 0, 0 }),
/* '~' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0 },
{ 0, 1, 1, 0, 0 },
{ 0, 0, 0, 1, 1 },
{ 0, 0, 0, 0, 0 }),
};
``` | /content/code_sandbox/drivers/display/mb_font.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,815 |
```c
/*
*
*/
#define DT_DRV_COMPAT raydium_rm68200
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(rm68200, CONFIG_DISPLAY_LOG_LEVEL);
/* DCS Commands */
#define DCS_CMD_PAGE 0xFE
#define DCS_CMD_PAGE_UCS 0x0
#define DCS_CMD_PAGE_SET_PAGE0 0x1
#define DCS_CMD_PAGE_SET_PAGE1 0x2
#define DCS_CMD_PAGE_SET_PAGE2 0x3
#define DCS_CMD_PAGE_SET_PAGE3 0x4
/* MCS Commands */
#define MCS_STBCTR 0x12
#define MCS_SGOPCTR 0x16
#define MCS_SDCTR 0x1A
#define MCS_INVCTR 0x1B
#define MCS_EXT_PWR_IC_TYPE 0x24
#define MCS_EXT_PWR_SET_AVDD 0x25
#define MCS_AVEE_FROM_PFM 0x26
#define MCS_AVDD_FROM_PFM 0x27
#define MCS_SETAVEE 0x29
#define MCS_BT2CTR 0x2B
#define MCS_BT3CTR 0x2F
#define MCS_BT4CTR 0x34
#define MCS_VCMCTR 0x46
#define MCS_SETVGMN 0x52
#define MCS_SETVGSN 0x53
#define MCS_SETVGMP 0x54
#define MCS_SETVGSP 0x55
#define MCS_SW_CTRL 0x5F
#define MCS_GAMMA_VP1 0x60
#define MCS_GAMMA_VP4 0x61
#define MCS_GAMMA_VP8 0x62
#define MCS_GAMMA_VP16 0x63
#define MCS_GAMMA_VP24 0x64
#define MCS_GAMMA_VP52 0x65
#define MCS_GAMMA_VP80 0x66
#define MCS_GAMMA_VP108 0x67
#define MCS_GAMMA_VP147 0x68
#define MCS_GAMMA_VP175 0x69
#define MCS_GAMMA_VP203 0x6A
#define MCS_GAMMA_VP231 0x6B
#define MCS_GAMMA_VP239 0x6C
#define MCS_GAMMA_VP247 0x6D
#define MCS_GAMMA_VP251 0x6E
#define MCS_GAMMA_VP255 0x6F
#define MCS_GAMMA_VN1 0x70
#define MCS_GAMMA_VN4 0x71
#define MCS_GAMMA_VN8 0x72
#define MCS_GAMMA_VN16 0x73
#define MCS_GAMMA_VN24 0x74
#define MCS_GAMMA_VN52 0x75
#define MCS_GAMMA_VN80 0x76
#define MCS_GAMMA_VN108 0x77
#define MCS_GAMMA_VN147 0x78
#define MCS_GAMMA_VN175 0x79
#define MCS_GAMMA_VN203 0x7A
#define MCS_GAMMA_VN231 0x7B
#define MCS_GAMMA_VN239 0x7C
#define MCS_GAMMA_VN247 0x7D
#define MCS_GAMMA_VN251 0x7E
#define MCS_GAMMA_VN255 0x7F
#define MCS_GAMMA_UPDATE 0x80
struct rm68200_config {
const struct device *mipi_dsi;
const struct gpio_dt_spec reset_gpio;
const struct gpio_dt_spec bl_gpio;
uint8_t num_of_lanes;
uint8_t pixel_format;
uint16_t panel_width;
uint16_t panel_height;
uint8_t channel;
};
static int rm68200_dcs_write(const struct device *dev, uint8_t cmd, uint8_t *buf,
uint8_t len)
{
const struct rm68200_config *config = dev->config;
return mipi_dsi_dcs_write(config->mipi_dsi, config->channel, cmd, buf, len);
}
static int rm68200_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
return 0;
}
static int rm68200_blanking_off(const struct device *dev)
{
const struct rm68200_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 1);
} else {
return -ENOTSUP;
}
}
static int rm68200_blanking_on(const struct device *dev)
{
const struct rm68200_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 0);
} else {
return -ENOTSUP;
}
}
static int rm68200_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
const struct rm68200_config *config = dev->config;
if (pixel_format == config->pixel_format) {
return 0;
}
LOG_ERR("Pixel format change not implemented");
return -ENOTSUP;
}
static int rm68200_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
LOG_ERR("Changing display orientation not implemented");
return -ENOTSUP;
}
static void rm68200_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct rm68200_config *config = dev->config;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->panel_width;
capabilities->y_resolution = config->panel_height;
capabilities->supported_pixel_formats = config->pixel_format;
capabilities->current_pixel_format = config->pixel_format;
capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
}
static const struct display_driver_api rm68200_api = {
.blanking_on = rm68200_blanking_on,
.blanking_off = rm68200_blanking_off,
.write = rm68200_write,
.get_capabilities = rm68200_get_capabilities,
.set_pixel_format = rm68200_set_pixel_format,
.set_orientation = rm68200_set_orientation,
};
static int rm68200_init(const struct device *dev)
{
const struct rm68200_config *config = dev->config;
uint8_t param;
int ret;
struct mipi_dsi_device mdev;
mdev.data_lanes = config->num_of_lanes;
mdev.pixfmt = config->pixel_format;
/* RM68200 runs in video mode */
mdev.mode_flags = MIPI_DSI_MODE_VIDEO;
ret = mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev);
if (ret < 0) {
LOG_ERR("Could not attach to MIPI-DSI host");
return ret;
}
if (config->reset_gpio.port != NULL) {
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure reset GPIO (%d)", ret);
return ret;
}
/* Power to the display has been enabled via the regulator fixed api during
* regulator init.
* reset:0 -> reset:1
*/
gpio_pin_set_dt(&config->reset_gpio, 0);
/* Per datasheet, reset low pulse width should be at least 15usec */
k_sleep(K_USEC(50));
gpio_pin_set_dt(&config->reset_gpio, 1);
/* Per datasheet, it is necessary to wait 5msec after releasing reset */
k_sleep(K_MSEC(5));
}
param = DCS_CMD_PAGE_SET_PAGE0;
rm68200_dcs_write(dev, DCS_CMD_PAGE, ¶m, 1);
param = 0xC0;
rm68200_dcs_write(dev, MCS_EXT_PWR_IC_TYPE, ¶m, 1);
param = 0x53;
rm68200_dcs_write(dev, MCS_EXT_PWR_SET_AVDD, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_AVEE_FROM_PFM, ¶m, 1);
param = 0xE5;
rm68200_dcs_write(dev, MCS_BT2CTR, ¶m, 1);
param = 0x0A;
rm68200_dcs_write(dev, MCS_AVDD_FROM_PFM, ¶m, 1);
param = 0x0A;
rm68200_dcs_write(dev, MCS_SETAVEE, ¶m, 1);
param = 0x52;
rm68200_dcs_write(dev, MCS_SGOPCTR, ¶m, 1);
param = 0x53;
rm68200_dcs_write(dev, MCS_BT3CTR, ¶m, 1);
param = 0x5A;
rm68200_dcs_write(dev, MCS_BT4CTR, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_INVCTR, ¶m, 1);
param = 0x0A;
rm68200_dcs_write(dev, MCS_STBCTR, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, MCS_SDCTR, ¶m, 1);
param = 0x56;
rm68200_dcs_write(dev, MCS_VCMCTR, ¶m, 1);
param = 0xA0;
rm68200_dcs_write(dev, MCS_SETVGMN, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_SETVGSN, ¶m, 1);
param = 0xA0;
rm68200_dcs_write(dev, MCS_SETVGMP, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_SETVGSP, ¶m, 1);
param = 0x10U | (config->num_of_lanes - 1U);
rm68200_dcs_write(dev, MCS_SW_CTRL, ¶m, 1);
param = DCS_CMD_PAGE_SET_PAGE2;
rm68200_dcs_write(dev, DCS_CMD_PAGE, ¶m, 1);
/* There is no description for the below registers in the datasheet */
param = 0x05;
rm68200_dcs_write(dev, 0x00, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, 0x02, ¶m, 1);
param = 0x0F;
rm68200_dcs_write(dev, 0x03, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x04, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x05, ¶m, 1);
param = 0x50;
rm68200_dcs_write(dev, 0x06, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x07, ¶m, 1);
param = 0x16;
rm68200_dcs_write(dev, 0x08, ¶m, 1);
param = 0x0D;
rm68200_dcs_write(dev, 0x09, ¶m, 1);
param = 0x11;
rm68200_dcs_write(dev, 0x0A, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x0B, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x0C, ¶m, 1);
param = 0x50;
rm68200_dcs_write(dev, 0x0D, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, 0x0E, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x0F, ¶m, 1);
param = 0x01;
rm68200_dcs_write(dev, 0x10, ¶m, 1);
param = 0x02;
rm68200_dcs_write(dev, 0x11, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x12, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x13, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x14, ¶m, 1);
param = 0x85;
rm68200_dcs_write(dev, 0x15, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x16, ¶m, 1);
param = 0x03;
rm68200_dcs_write(dev, 0x17, ¶m, 1);
param = 0x04;
rm68200_dcs_write(dev, 0x18, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x19, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, 0x1A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x1B, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x1C, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x1D, ¶m, 1);
param = 0x85;
rm68200_dcs_write(dev, 0x1E, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x1F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x20, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x21, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x22, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x23, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x24, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x25, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x26, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x27, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x28, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x29, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, 0x2A, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x2B, ¶m, 1);
param = 0x01;
rm68200_dcs_write(dev, 0x2D, ¶m, 1);
param = 0x02;
rm68200_dcs_write(dev, 0x2F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x30, ¶m, 1);
param = 0x40;
rm68200_dcs_write(dev, 0x31, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x32, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x33, ¶m, 1);
param = 0x54;
rm68200_dcs_write(dev, 0x34, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x35, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x36, ¶m, 1);
param = 0x03;
rm68200_dcs_write(dev, 0x37, ¶m, 1);
param = 0x04;
rm68200_dcs_write(dev, 0x38, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x39, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, 0x3A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x3B, ¶m, 1);
param = 0x40;
rm68200_dcs_write(dev, 0x3D, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x3F, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x40, ¶m, 1);
param = 0x54;
rm68200_dcs_write(dev, 0x41, ¶m, 1);
param = 0x7D;
rm68200_dcs_write(dev, 0x42, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x43, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x44, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x45, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x46, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x47, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x48, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x49, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4B, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4C, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4D, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4E, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x4F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x50, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x51, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x52, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x53, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x54, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x55, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x56, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x58, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x59, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5B, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5C, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5D, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5E, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x5F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x60, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x61, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x62, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x63, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x64, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x65, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x66, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x67, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x68, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x69, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6B, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6C, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6D, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6E, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x6F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x70, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x71, ¶m, 1);
param = 0x20;
rm68200_dcs_write(dev, 0x72, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x73, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x74, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x75, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x76, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x77, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x78, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x79, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x7A, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x7B, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x7C, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x7D, ¶m, 1);
param = 0xBF;
rm68200_dcs_write(dev, 0x7E, ¶m, 1);
param = 0x02;
rm68200_dcs_write(dev, 0x7F, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, 0x80, ¶m, 1);
param = 0x14;
rm68200_dcs_write(dev, 0x81, ¶m, 1);
param = 0x10;
rm68200_dcs_write(dev, 0x82, ¶m, 1);
param = 0x16;
rm68200_dcs_write(dev, 0x83, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, 0x84, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0x85, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x86, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x87, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x88, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x89, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x8A, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, 0x8B, ¶m, 1);
param = 0x0A;
rm68200_dcs_write(dev, 0x8C, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, 0x8D, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x8E, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x8F, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0x90, ¶m, 1);
param = 0x04;
rm68200_dcs_write(dev, 0x91, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x92, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x93, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x94, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x95, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0x96, ¶m, 1);
param = 0x01;
rm68200_dcs_write(dev, 0x97, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x98, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x99, ¶m, 1);
param = 0x0F;
rm68200_dcs_write(dev, 0x9A, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, 0x9B, ¶m, 1);
param = 0x0D;
rm68200_dcs_write(dev, 0x9C, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x9D, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x9E, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0x9F, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xA0, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xA2, ¶m, 1);
param = 0x09;
rm68200_dcs_write(dev, 0xA3, ¶m, 1);
param = 0x13;
rm68200_dcs_write(dev, 0xA4, ¶m, 1);
param = 0x17;
rm68200_dcs_write(dev, 0xA5, ¶m, 1);
param = 0x11;
rm68200_dcs_write(dev, 0xA6, ¶m, 1);
param = 0x15;
rm68200_dcs_write(dev, 0xA7, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, 0xA9, ¶m, 1);
param = 0x03;
rm68200_dcs_write(dev, 0xAA, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xAB, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xAC, ¶m, 1);
param = 0x05;
rm68200_dcs_write(dev, 0xAD, ¶m, 1);
param = 0x01;
rm68200_dcs_write(dev, 0xAE, ¶m, 1);
param = 0x17;
rm68200_dcs_write(dev, 0xAF, ¶m, 1);
param = 0x13;
rm68200_dcs_write(dev, 0xB0, ¶m, 1);
param = 0x15;
rm68200_dcs_write(dev, 0xB1, ¶m, 1);
param = 0x11;
rm68200_dcs_write(dev, 0xB2, ¶m, 1);
param = 0x0F;
rm68200_dcs_write(dev, 0xB3, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xB4, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xB5, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xB6, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xB7, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xB8, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, 0xB9, ¶m, 1);
param = 0x0D;
rm68200_dcs_write(dev, 0xBA, ¶m, 1);
param = 0x09;
rm68200_dcs_write(dev, 0xBB, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xBC, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xBD, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, 0xBE, ¶m, 1);
param = 0x03;
rm68200_dcs_write(dev, 0xBF, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC0, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC1, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC2, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC3, ¶m, 1);
param = 0x02;
rm68200_dcs_write(dev, 0xC4, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, 0xC5, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC6, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xC7, ¶m, 1);
param = 0x08;
rm68200_dcs_write(dev, 0xC8, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, 0xC9, ¶m, 1);
param = 0x0A;
rm68200_dcs_write(dev, 0xCA, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xCB, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xCC, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xCD, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xCE, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xCF, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, 0xD0, ¶m, 1);
param = 0x10;
rm68200_dcs_write(dev, 0xD1, ¶m, 1);
param = 0x14;
rm68200_dcs_write(dev, 0xD2, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, 0xD3, ¶m, 1);
param = 0x16;
rm68200_dcs_write(dev, 0xD4, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, 0xD5, ¶m, 1);
param = 0x04;
rm68200_dcs_write(dev, 0xD6, ¶m, 1);
param = 0x3F;
rm68200_dcs_write(dev, 0xD7, ¶m, 1);
param = 0x02;
rm68200_dcs_write(dev, 0xDC, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, 0xDE, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, DCS_CMD_PAGE, ¶m, 1);
param = 0x75;
rm68200_dcs_write(dev, 0x01, ¶m, 1);
/* Gamma Settings */
param = DCS_CMD_PAGE_SET_PAGE3;
rm68200_dcs_write(dev, DCS_CMD_PAGE, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_GAMMA_VP1, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, MCS_GAMMA_VP4, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VP8, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, MCS_GAMMA_VP16, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, MCS_GAMMA_VP24, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VP52, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, MCS_GAMMA_VP80, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, MCS_GAMMA_VP108, ¶m, 1);
param = 0x15;
rm68200_dcs_write(dev, MCS_GAMMA_VP147, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, MCS_GAMMA_VP175, ¶m, 1);
param = 0x10;
rm68200_dcs_write(dev, MCS_GAMMA_VP203, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, MCS_GAMMA_VP231, ¶m, 1);
param = 0x0F;
rm68200_dcs_write(dev, MCS_GAMMA_VP239, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VP247, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, MCS_GAMMA_VP251, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_GAMMA_VP255, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_GAMMA_VN1, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, MCS_GAMMA_VN4, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VN8, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, MCS_GAMMA_VN16, ¶m, 1);
param = 0x06;
rm68200_dcs_write(dev, MCS_GAMMA_VN24, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VN52, ¶m, 1);
param = 0x0E;
rm68200_dcs_write(dev, MCS_GAMMA_VN80, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, MCS_GAMMA_VN108, ¶m, 1);
param = 0x15;
rm68200_dcs_write(dev, MCS_GAMMA_VN147, ¶m, 1);
param = 0x0B;
rm68200_dcs_write(dev, MCS_GAMMA_VN175, ¶m, 1);
param = 0x10;
rm68200_dcs_write(dev, MCS_GAMMA_VN203, ¶m, 1);
param = 0x07;
rm68200_dcs_write(dev, MCS_GAMMA_VN231, ¶m, 1);
param = 0x0F;
rm68200_dcs_write(dev, MCS_GAMMA_VN239, ¶m, 1);
param = 0x12;
rm68200_dcs_write(dev, MCS_GAMMA_VN247, ¶m, 1);
param = 0x0C;
rm68200_dcs_write(dev, MCS_GAMMA_VN251, ¶m, 1);
param = 0x00;
rm68200_dcs_write(dev, MCS_GAMMA_VN255, ¶m, 1);
/* Page 0 */
param = DCS_CMD_PAGE_UCS;
rm68200_dcs_write(dev, DCS_CMD_PAGE, ¶m, 1);
rm68200_dcs_write(dev, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
k_sleep(K_MSEC(200));
rm68200_dcs_write(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
k_sleep(K_MSEC(100));
rm68200_dcs_write(dev, MIPI_DCS_WRITE_MEMORY_START, NULL, 0);
param = 0x00;
rm68200_dcs_write(dev, MIPI_DCS_SET_TEAR_ON, ¶m, 1);
k_sleep(K_MSEC(200));
if (config->bl_gpio.port != NULL) {
ret = gpio_pin_configure_dt(&config->bl_gpio, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure bl GPIO (%d)", ret);
return ret;
}
}
return 0;
}
#define RM68200_PANEL(id) \
static const struct rm68200_config rm68200_config_##id = { \
.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(id)), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(id, reset_gpios, {0}), \
.bl_gpio = GPIO_DT_SPEC_INST_GET_OR(id, bl_gpios, {0}), \
.num_of_lanes = DT_INST_PROP_BY_IDX(id, data_lanes, 0), \
.pixel_format = DT_INST_PROP(id, pixel_format), \
.panel_width = DT_INST_PROP(id, width), \
.panel_height = DT_INST_PROP(id, height), \
.channel = DT_INST_REG_ADDR(id), \
}; \
DEVICE_DT_INST_DEFINE(id, \
&rm68200_init, \
NULL, \
NULL, \
&rm68200_config_##id, \
POST_KERNEL, \
CONFIG_APPLICATION_INIT_PRIORITY, \
&rm68200_api);
DT_INST_FOREACH_STATUS_OKAY(RM68200_PANEL)
``` | /content/code_sandbox/drivers/display/display_rm68200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,404 |
```unknown
config DISPLAY_NRF_LED_MATRIX
bool "LED matrix driven by GPIOs"
default y
depends on DT_HAS_NORDIC_NRF_LED_MATRIX_ENABLED
select NRFX_GPIOTE
select NRFX_PPI if HAS_HW_NRF_PPI
help
Enable driver for a LED matrix with rows and columns driven by
GPIOs. The driver allows setting one of 256 levels of brightness
(where 0 means off completely) for each of the LEDs independently.
Assignment of GPIOs to rows and columns and the mapping of those
to pixels are specified in properties of a "nordic,nrf-led-matrix"
compatible node in devicetree.
The driver uses one TIMER instance and, depending on what is set in
devicetree, one PWM instance or one or more GPIOTE and PPI channels
(the latter value depends on the chosen pixel group size - the number
of LEDs in one row that can be lit simultaneously).
``` | /content/code_sandbox/drivers/display/Kconfig.nrf_led_matrix | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```unknown
config ST7796S
bool "ST7796S display driver"
default y
depends on DT_HAS_SITRONIX_ST7796S_ENABLED
select MIPI_DBI
help
Enable driver for ST7796S display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.st7796s | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# Smartbond display controller configuration options
config DISPLAY_RENESAS_LCDC
bool "Smartbond display controller driver"
depends on DT_HAS_RENESAS_SMARTBOND_DISPLAY_ENABLED
select DMA
default y
help
Enable Smartbond display controller.
config DISPLAY_RENESAS_LCDC_BUFFER_PSRAM
bool "Allocate the display buffer into PSRAM"
depends on DISPLAY_RENESAS_LCDC
select MEMC
help
Allocate the display buffer into PSRAM
``` | /content/code_sandbox/drivers/display/Kconfig.renesas_lcdc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
# SSD1327 display controller configuration options
menuconfig SSD1327
bool "SSD1327 display driver"
default y
depends on DT_HAS_SOLOMON_SSD1327FB_ENABLED
select MIPI_DBI
help
Enable driver for SSD1327 display.
if SSD1327
config SSD1327_DEFAULT_CONTRAST
int "SSD1327 default contrast"
default 128
range 0 255
help
SSD1327 default contrast.
endif # SSD1327
``` | /content/code_sandbox/drivers/display/Kconfig.ssd1327 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```unknown
config GC9X01X
bool "GC9X01X display driver"
default y
depends on DT_HAS_GALAXYCORE_GC9X01X_ENABLED
select MIPI_DBI
help
Enable driver for GC9X01X display driver.
``` | /content/code_sandbox/drivers/display/Kconfig.gc9x01x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```objective-c
/*
*
*/
#define MB_FONT_COUNT 95
#define MB_FONT_START ' '
#define MB_FONT_END '~'
extern const struct mb_image mb_font[MB_FONT_COUNT];
``` | /content/code_sandbox/drivers/display/mb_font.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config TLC59731_STRIP
bool "TLC59731 LED controller"
default y
depends on DT_HAS_TI_TLC59731_ENABLED
select GPIO
help
Enable driver for the Texas Instruments TLC59731 EasySet LED
controllers.
``` | /content/code_sandbox/drivers/led_strip/Kconfig.tlc59731 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
#
#
#
config APA102_STRIP
bool "APA102 SPI LED strip driver"
default y
depends on DT_HAS_APA_APA102_ENABLED
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_APA_APA102),spi)
select LED_STRIP_RGB_SCRATCH
help
Enable the LED strip driver for a chain of APA102 RGB LEDs.
These are sold as DotStar by Adafruit and Superled by others.
``` | /content/code_sandbox/drivers/led_strip/Kconfig.apa102 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```c
/*
*
*/
#include <zephyr/drivers/led_strip.h>
#include <errno.h>
#include <string.h>
#if DT_NODE_HAS_STATUS(DT_INST(0, greeled_lpd8806), okay)
#define DT_DRV_COMPAT greeled_lpd8806
#else
#define DT_DRV_COMPAT greeled_lpd8803
#endif
#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(lpd880x);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/util.h>
/*
* LPD880X SPI master configuration:
*
* - mode 0 (the default), 8 bit, MSB first, one-line SPI
* - no shenanigans (no CS hold, release device lock, not an EEPROM)
*/
#define LPD880X_SPI_OPERATION (SPI_OP_MODE_MASTER | \
SPI_TRANSFER_MSB | \
SPI_WORD_SET(8))
struct lpd880x_config {
struct spi_dt_spec bus;
size_t length;
};
static int lpd880x_update(const struct device *dev, void *data, size_t size)
{
const struct lpd880x_config *config = dev->config;
/*
* Per the AdaFruit reverse engineering notes on the protocol,
* a zero byte propagates through at most 32 LED driver ICs.
* The LPD8803 is the worst case, at 3 output channels per IC.
*/
uint8_t reset_size = DIV_ROUND_UP(DIV_ROUND_UP(size, 3), 32);
uint8_t reset_buf[reset_size];
uint8_t last = 0x00;
const struct spi_buf bufs[3] = {
{
/* Prepares the strip to shift in new data values. */
.buf = reset_buf,
.len = reset_size
},
{
/* Displays the serialized pixel data. */
.buf = data,
.len = size
},
{
/* Ensures the last byte of pixel data is displayed. */
.buf = &last,
.len = sizeof(last)
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 3
};
size_t rc;
(void)memset(reset_buf, 0x00, reset_size);
rc = spi_write_dt(&config->bus, &tx);
if (rc) {
LOG_ERR("can't update strip: %d", rc);
}
return rc;
}
static int lpd880x_strip_update_rgb(const struct device *dev,
struct led_rgb *pixels,
size_t num_pixels)
{
uint8_t *px = (uint8_t *)pixels;
uint8_t r, g, b;
size_t i;
/*
* Overwrite a prefix of the pixels array with its on-wire
* representation, eliminating padding/scratch garbage, if any.
*/
for (i = 0; i < num_pixels; i++) {
r = 0x80 | (pixels[i].r >> 1);
g = 0x80 | (pixels[i].g >> 1);
b = 0x80 | (pixels[i].b >> 1);
/*
* GRB is the ordering used by commonly available
* LPD880x strips.
*/
*px++ = g;
*px++ = r;
*px++ = b;
}
return lpd880x_update(dev, pixels, 3 * num_pixels);
}
static int lpd880x_strip_update_channels(const struct device *dev,
uint8_t *channels,
size_t num_channels)
{
size_t i;
for (i = 0; i < num_channels; i++) {
channels[i] = 0x80 | (channels[i] >> 1);
}
return lpd880x_update(dev, channels, num_channels);
}
static size_t lpd880x_strip_length(const struct device *dev)
{
const struct lpd880x_config *config = dev->config;
return config->length;
}
static int lpd880x_strip_init(const struct device *dev)
{
const struct lpd880x_config *config = dev->config;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI device %s not ready", config->bus.bus->name);
return -ENODEV;
}
return 0;
}
static const struct lpd880x_config lpd880x_config = {
.bus = SPI_DT_SPEC_INST_GET(0, LPD880X_SPI_OPERATION, 0),
.length = DT_INST_PROP(0, chain_length),
};
static const struct led_strip_driver_api lpd880x_strip_api = {
.update_rgb = lpd880x_strip_update_rgb,
.update_channels = lpd880x_strip_update_channels,
.length = lpd880x_strip_length,
};
DEVICE_DT_INST_DEFINE(0, lpd880x_strip_init, NULL,
NULL, &lpd880x_config,
POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY,
&lpd880x_strip_api);
``` | /content/code_sandbox/drivers/led_strip/lpd880x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,115 |
```c
/*
*
*/
#define DT_DRV_COMPAT raydium_rm67162
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/mipi_dsi/mipi_dsi_mcux_2l.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/policy.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(rm67162, CONFIG_DISPLAY_LOG_LEVEL);
/*
* These commands are taken from NXP's MCUXpresso SDK.
* Additional documentation is added where possible, but the
* Manufacture command set pages are not described in the datasheet
*/
static const struct {
uint8_t cmd;
uint8_t param;
} rm67162_init_400x392[] = {
/* CMD Mode switch, select manufacture command set page 0 */
{.cmd = 0xFE, .param = 0x01},
{.cmd = 0x06, .param = 0x62},
{.cmd = 0x0E, .param = 0x80},
{.cmd = 0x0F, .param = 0x80},
{.cmd = 0x10, .param = 0x71},
{.cmd = 0x13, .param = 0x81},
{.cmd = 0x14, .param = 0x81},
{.cmd = 0x15, .param = 0x82},
{.cmd = 0x16, .param = 0x82},
{.cmd = 0x18, .param = 0x88},
{.cmd = 0x19, .param = 0x55},
{.cmd = 0x1A, .param = 0x10},
{.cmd = 0x1C, .param = 0x99},
{.cmd = 0x1D, .param = 0x03},
{.cmd = 0x1E, .param = 0x03},
{.cmd = 0x1F, .param = 0x03},
{.cmd = 0x20, .param = 0x03},
{.cmd = 0x25, .param = 0x03},
{.cmd = 0x26, .param = 0x8D},
{.cmd = 0x2A, .param = 0x03},
{.cmd = 0x2B, .param = 0x8D},
{.cmd = 0x36, .param = 0x00},
{.cmd = 0x37, .param = 0x10},
{.cmd = 0x3A, .param = 0x00},
{.cmd = 0x3B, .param = 0x00},
{.cmd = 0x3D, .param = 0x20},
{.cmd = 0x3F, .param = 0x3A},
{.cmd = 0x40, .param = 0x30},
{.cmd = 0x41, .param = 0x30},
{.cmd = 0x42, .param = 0x33},
{.cmd = 0x43, .param = 0x22},
{.cmd = 0x44, .param = 0x11},
{.cmd = 0x45, .param = 0x66},
{.cmd = 0x46, .param = 0x55},
{.cmd = 0x47, .param = 0x44},
{.cmd = 0x4C, .param = 0x33},
{.cmd = 0x4D, .param = 0x22},
{.cmd = 0x4E, .param = 0x11},
{.cmd = 0x4F, .param = 0x66},
{.cmd = 0x50, .param = 0x55},
{.cmd = 0x51, .param = 0x44},
{.cmd = 0x57, .param = 0xB3},
{.cmd = 0x6B, .param = 0x19},
{.cmd = 0x70, .param = 0x55},
{.cmd = 0x74, .param = 0x0C},
/* VGMP/VGSP Voltage Control (select manufacture command set page 1 ) */
{.cmd = 0xFE, .param = 0x02},
{.cmd = 0x9B, .param = 0x40},
{.cmd = 0x9C, .param = 0x67},
{.cmd = 0x9D, .param = 0x20},
/* VGMP/VGSP Voltage Control (select manufacture command set page 2 ) */
{.cmd = 0xFE, .param = 0x03},
{.cmd = 0x9B, .param = 0x40},
{.cmd = 0x9C, .param = 0x67},
{.cmd = 0x9D, .param = 0x20},
/* VSR Command (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x5D, .param = 0x10},
/* VSR1 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x00, .param = 0x8D},
{.cmd = 0x01, .param = 0x00},
{.cmd = 0x02, .param = 0x01},
{.cmd = 0x03, .param = 0x01},
{.cmd = 0x04, .param = 0x10},
{.cmd = 0x05, .param = 0x01},
{.cmd = 0x06, .param = 0xA7},
{.cmd = 0x07, .param = 0x20},
{.cmd = 0x08, .param = 0x00},
/* VSR2 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x09, .param = 0xC2},
{.cmd = 0x0A, .param = 0x00},
{.cmd = 0x0B, .param = 0x02},
{.cmd = 0x0C, .param = 0x01},
{.cmd = 0x0D, .param = 0x40},
{.cmd = 0x0E, .param = 0x06},
{.cmd = 0x0F, .param = 0x01},
{.cmd = 0x10, .param = 0xA7},
{.cmd = 0x11, .param = 0x00},
/* VSR3 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x12, .param = 0xC2},
{.cmd = 0x13, .param = 0x00},
{.cmd = 0x14, .param = 0x02},
{.cmd = 0x15, .param = 0x01},
{.cmd = 0x16, .param = 0x40},
{.cmd = 0x17, .param = 0x07},
{.cmd = 0x18, .param = 0x01},
{.cmd = 0x19, .param = 0xA7},
{.cmd = 0x1A, .param = 0x00},
/* VSR4 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x1B, .param = 0x82},
{.cmd = 0x1C, .param = 0x00},
{.cmd = 0x1D, .param = 0xFF},
{.cmd = 0x1E, .param = 0x05},
{.cmd = 0x1F, .param = 0x60},
{.cmd = 0x20, .param = 0x02},
{.cmd = 0x21, .param = 0x01},
{.cmd = 0x22, .param = 0x7C},
{.cmd = 0x23, .param = 0x00},
/* VSR5 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x24, .param = 0xC2},
{.cmd = 0x25, .param = 0x00},
{.cmd = 0x26, .param = 0x04},
{.cmd = 0x27, .param = 0x02},
{.cmd = 0x28, .param = 0x70},
{.cmd = 0x29, .param = 0x05},
{.cmd = 0x2A, .param = 0x74},
{.cmd = 0x2B, .param = 0x8D},
{.cmd = 0x2D, .param = 0x00},
/* VSR6 Timing Set (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x2F, .param = 0xC2},
{.cmd = 0x30, .param = 0x00},
{.cmd = 0x31, .param = 0x04},
{.cmd = 0x32, .param = 0x02},
{.cmd = 0x33, .param = 0x70},
{.cmd = 0x34, .param = 0x07},
{.cmd = 0x35, .param = 0x74},
{.cmd = 0x36, .param = 0x8D},
{.cmd = 0x37, .param = 0x00},
/* VSR Marping command (select manufacture command set page 3 ) */
{.cmd = 0xFE, .param = 0x04},
{.cmd = 0x5E, .param = 0x20},
{.cmd = 0x5F, .param = 0x31},
{.cmd = 0x60, .param = 0x54},
{.cmd = 0x61, .param = 0x76},
{.cmd = 0x62, .param = 0x98},
/* Select manufacture command set page 4 */
/* ELVSS -2.4V(RT4723). 0x15: RT4723. 0x01: RT4723B. 0x17: STAM1332. */
{.cmd = 0xFE, .param = 0x05},
{.cmd = 0x05, .param = 0x15},
{.cmd = 0x2A, .param = 0x04},
{.cmd = 0x91, .param = 0x00},
/* Select user command set */
{.cmd = 0xFE, .param = 0x00},
/* Set tearing effect signal to only output at V-blank*/
{.cmd = 0x35, .param = 0x00},
};
struct rm67162_config {
const struct device *mipi_dsi;
uint8_t channel;
uint8_t num_of_lanes;
const struct gpio_dt_spec reset_gpio;
const struct gpio_dt_spec bl_gpio;
const struct gpio_dt_spec te_gpio;
uint16_t panel_width;
uint16_t panel_height;
};
struct rm67162_data {
uint8_t pixel_format;
uint8_t bytes_per_pixel;
struct gpio_callback te_gpio_cb;
struct k_sem te_sem;
};
static void rm67162_te_isr_handler(const struct device *gpio_dev,
struct gpio_callback *cb, uint32_t pins)
{
struct rm67162_data *data = CONTAINER_OF(cb, struct rm67162_data, te_gpio_cb);
k_sem_give(&data->te_sem);
}
static int rm67162_init(const struct device *dev)
{
const struct rm67162_config *config = dev->config;
struct rm67162_data *data = dev->data;
struct mipi_dsi_device mdev = {0};
int ret;
uint32_t i;
uint8_t cmd, param;
/* Attach to MIPI DSI host */
mdev.data_lanes = config->num_of_lanes;
mdev.pixfmt = data->pixel_format;
ret = mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev);
if (ret < 0) {
LOG_ERR("Could not attach to MIPI-DSI host");
return ret;
}
if (config->reset_gpio.port != NULL) {
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure reset GPIO (%d)", ret);
return ret;
}
/*
* Power to the display has been enabled via the regulator fixed api during
* regulator init. Per datasheet, we must wait at least 10ms before
* starting reset sequence after power on.
*/
k_sleep(K_MSEC(10));
/* Start reset sequence */
ret = gpio_pin_set_dt(&config->reset_gpio, 0);
if (ret < 0) {
LOG_ERR("Could not pull reset low (%d)", ret);
return ret;
}
/* Per datasheet, reset low pulse width should be at least 10usec */
k_sleep(K_USEC(30));
gpio_pin_set_dt(&config->reset_gpio, 1);
if (ret < 0) {
LOG_ERR("Could not pull reset high (%d)", ret);
return ret;
}
/*
* It is necessary to wait at least 120msec after releasing reset,
* before sending additional commands. This delay can be 5msec
* if we are certain the display module is in SLEEP IN state,
* but this is not guaranteed (for example, with a warm reset)
*/
k_sleep(K_MSEC(150));
}
/* Now, write initialization settings for display, running at 400x392 */
for (i = 0; i < ARRAY_SIZE(rm67162_init_400x392); i++) {
cmd = rm67162_init_400x392[i].cmd;
param = rm67162_init_400x392[i].param;
ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
cmd, ¶m, 1);
if (ret < 0) {
return ret;
}
}
/* Set pixel format */
if (data->pixel_format == MIPI_DSI_PIXFMT_RGB888) {
param = MIPI_DCS_PIXEL_FORMAT_24BIT;
data->bytes_per_pixel = 3;
} else if (data->pixel_format == MIPI_DSI_PIXFMT_RGB565) {
param = MIPI_DCS_PIXEL_FORMAT_16BIT;
data->bytes_per_pixel = 2;
} else {
/* Unsupported pixel format */
LOG_ERR("Pixel format not supported");
return -ENOTSUP;
}
ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_SET_PIXEL_FORMAT, ¶m, 1);
if (ret < 0) {
return ret;
}
/* Delay 50 ms before exiting sleep mode */
k_sleep(K_MSEC(50));
ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
if (ret < 0) {
return ret;
}
/*
* We must wait 5 ms after exiting sleep mode before sending additional
* commands. If we intend to enter sleep mode, we must delay
* 120 ms before sending that command. To be safe, delay 150ms
*/
k_sleep(K_MSEC(150));
/* Setup backlight */
if (config->bl_gpio.port != NULL) {
ret = gpio_pin_configure_dt(&config->bl_gpio, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure bl GPIO (%d)", ret);
return ret;
}
}
if (config->te_gpio.port != NULL) {
/* Setup TE pin */
ret = gpio_pin_configure_dt(&config->te_gpio, GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Could not configure TE GPIO (%d)", ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->te_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure TE interrupt (%d)", ret);
return ret;
}
/* Init and install GPIO callback */
gpio_init_callback(&data->te_gpio_cb, rm67162_te_isr_handler,
BIT(config->te_gpio.pin));
gpio_add_callback(config->te_gpio.port, &data->te_gpio_cb);
/* Setup te pin semaphore */
k_sem_init(&data->te_sem, 0, 1);
}
/* Now, enable display */
return mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
}
/* Helper to write framebuffer data to rm67162 via MIPI interface. */
static int rm67162_write_fb(const struct device *dev, bool first_write,
const uint8_t *src, uint32_t len)
{
const struct rm67162_config *config = dev->config;
uint32_t wlen = 0;
struct mipi_dsi_msg msg = {0};
/* Note- we need to set custom flags on the DCS message,
* so we bypass the mipi_dsi_dcs_write API
*/
if (first_write) {
msg.cmd = MIPI_DCS_WRITE_MEMORY_START;
} else {
msg.cmd = MIPI_DCS_WRITE_MEMORY_CONTINUE;
}
msg.type = MIPI_DSI_DCS_LONG_WRITE;
msg.flags = MCUX_DSI_2L_FB_DATA;
while (len > 0) {
msg.tx_len = len;
msg.tx_buf = src;
wlen = mipi_dsi_transfer(config->mipi_dsi, config->channel, &msg);
if (wlen < 0) {
return wlen;
}
/* Advance source pointer and decrement remaining */
src += wlen;
len -= wlen;
/* All future commands should use WRITE_MEMORY_CONTINUE */
msg.cmd = MIPI_DCS_WRITE_MEMORY_CONTINUE;
}
return wlen;
}
static int rm67162_write(const struct device *dev, const uint16_t x,
const uint16_t y,
const struct display_buffer_descriptor *desc,
const void *buf)
{
const struct rm67162_config *config = dev->config;
struct rm67162_data *data = dev->data;
int ret;
uint16_t start, end, h_idx;
const uint8_t *src;
bool first_cmd;
uint8_t param[4];
LOG_DBG("W=%d, H=%d @%d,%d", desc->width, desc->height, x, y);
/*
* RM67162 runs in MIPI DBI mode. This means we can use command mode
* to write to the video memory buffer on the RM67162 control IC,
* and the IC will update the display automatically.
*/
/* Set column address of target area */
/* First two bytes are starting X coordinate */
start = x;
end = x + desc->width - 1;
sys_put_be16(start, ¶m[0]);
/* Second two bytes are ending X coordinate */
sys_put_be16(end, ¶m[2]);
ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_SET_COLUMN_ADDRESS, param,
sizeof(param));
if (ret < 0) {
return ret;
}
/* Set page address of target area */
/* First two bytes are starting Y coordinate */
start = y;
end = y + desc->height - 1;
sys_put_be16(start, ¶m[0]);
/* Second two bytes are ending X coordinate */
sys_put_be16(end, ¶m[2]);
ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_SET_PAGE_ADDRESS, param,
sizeof(param));
if (ret < 0) {
return ret;
}
/*
* Now, write the framebuffer. If the tearing effect GPIO is present,
* wait until the display controller issues an interrupt (which will
* give to the TE semaphore) before sending the frame
*/
if (config->te_gpio.port != NULL) {
/* Block sleep state until next TE interrupt so we can send
* frame during that interval
*/
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE,
PM_ALL_SUBSTATES);
k_sem_take(&data->te_sem, K_FOREVER);
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE,
PM_ALL_SUBSTATES);
}
src = buf;
first_cmd = true;
if (desc->pitch == desc->width) {
/* Buffer is contiguous, we can perform entire transfer */
rm67162_write_fb(dev, first_cmd, src,
desc->height * desc->width * data->bytes_per_pixel);
} else {
/* Buffer is not contiguous, we must write each line separately */
for (h_idx = 0; h_idx < desc->height; h_idx++) {
rm67162_write_fb(dev, first_cmd, src,
desc->width * data->bytes_per_pixel);
first_cmd = false;
/* The pitch is not equal to width, account for it here */
src += data->bytes_per_pixel * (desc->pitch - desc->width);
}
}
return 0;
}
static void rm67162_get_capabilities(const struct device *dev,
struct display_capabilities *capabilities)
{
const struct rm67162_config *config = dev->config;
const struct rm67162_data *data = dev->data;
memset(capabilities, 0, sizeof(struct display_capabilities));
capabilities->x_resolution = config->panel_width;
capabilities->y_resolution = config->panel_height;
capabilities->supported_pixel_formats = PIXEL_FORMAT_RGB_565 |
PIXEL_FORMAT_RGB_888;
switch (data->pixel_format) {
case MIPI_DSI_PIXFMT_RGB565:
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_565;
break;
case MIPI_DSI_PIXFMT_RGB888:
capabilities->current_pixel_format = PIXEL_FORMAT_RGB_888;
break;
default:
LOG_WRN("Unsupported display format");
/* Other display formats not implemented */
break;
}
capabilities->current_orientation = DISPLAY_ORIENTATION_ROTATED_90;
}
static int rm67162_blanking_off(const struct device *dev)
{
const struct rm67162_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 1);
} else {
return -ENOTSUP;
}
}
static int rm67162_blanking_on(const struct device *dev)
{
const struct rm67162_config *config = dev->config;
if (config->bl_gpio.port != NULL) {
return gpio_pin_set_dt(&config->bl_gpio, 0);
} else {
return -ENOTSUP;
}
}
static int rm67162_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
const struct rm67162_config *config = dev->config;
struct rm67162_data *data = dev->data;
uint8_t param;
switch (pixel_format) {
case PIXEL_FORMAT_RGB_565:
data->pixel_format = MIPI_DSI_PIXFMT_RGB565;
return 0;
case PIXEL_FORMAT_RGB_888:
data->pixel_format = MIPI_DSI_PIXFMT_RGB888;
return 0;
default:
/* Other display formats not implemented */
return -ENOTSUP;
}
if (data->pixel_format == MIPI_DSI_PIXFMT_RGB888) {
param = MIPI_DCS_PIXEL_FORMAT_24BIT;
data->bytes_per_pixel = 3;
} else if (data->pixel_format == MIPI_DSI_PIXFMT_RGB565) {
param = MIPI_DCS_PIXEL_FORMAT_16BIT;
data->bytes_per_pixel = 2;
}
return mipi_dsi_dcs_write(config->mipi_dsi, config->channel,
MIPI_DCS_SET_PIXEL_FORMAT, ¶m, 1);
}
static int rm67162_set_orientation(const struct device *dev,
const enum display_orientation orientation)
{
if (orientation == DISPLAY_ORIENTATION_NORMAL) {
return 0;
}
LOG_ERR("Changing display orientation not implemented");
return -ENOTSUP;
}
#ifdef CONFIG_PM_DEVICE
static int rm67162_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct rm67162_config *config = dev->config;
struct rm67162_data *data = dev->data;
struct mipi_dsi_device mdev = {0};
mdev.data_lanes = config->num_of_lanes;
mdev.pixfmt = data->pixel_format;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
/* Detach from the MIPI DSI controller */
return mipi_dsi_detach(config->mipi_dsi, config->channel, &mdev);
case PM_DEVICE_ACTION_RESUME:
return mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev);
default:
return -ENOTSUP;
}
}
#endif /* CONFIG_PM_DEVICE */
static const struct display_driver_api rm67162_api = {
.blanking_on = rm67162_blanking_on,
.blanking_off = rm67162_blanking_off,
.get_capabilities = rm67162_get_capabilities,
.write = rm67162_write,
.set_pixel_format = rm67162_set_pixel_format,
.set_orientation = rm67162_set_orientation,
};
#define RM67162_PANEL(id) \
static const struct rm67162_config rm67162_config_##id = { \
.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(id)), \
.num_of_lanes = DT_INST_PROP_BY_IDX(id, data_lanes, 0), \
.channel = DT_INST_REG_ADDR(id), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(id, reset_gpios, {0}), \
.bl_gpio = GPIO_DT_SPEC_INST_GET_OR(id, bl_gpios, {0}), \
.te_gpio = GPIO_DT_SPEC_INST_GET_OR(id, te_gpios, {0}), \
.panel_width = DT_INST_PROP(id, width), \
.panel_height = DT_INST_PROP(id, height), \
}; \
static struct rm67162_data rm67162_data_##id = { \
.pixel_format = DT_INST_PROP(id, pixel_format), \
}; \
PM_DEVICE_DT_INST_DEFINE(id, rm67162_pm_action); \
DEVICE_DT_INST_DEFINE(id, \
&rm67162_init, \
PM_DEVICE_DT_INST_GET(id), \
&rm67162_data_##id, \
&rm67162_config_##id, \
POST_KERNEL, \
CONFIG_APPLICATION_INIT_PRIORITY, \
&rm67162_api);
DT_INST_FOREACH_STATUS_OKAY(RM67162_PANEL)
``` | /content/code_sandbox/drivers/display/display_rm67162.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,398 |
```c
/*
*
*/
#define DT_DRV_COMPAT apa_apa102
#include <errno.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/util.h>
struct apa102_config {
struct spi_dt_spec bus;
size_t length;
};
static int apa102_update(const struct device *dev, void *buf, size_t size)
{
const struct apa102_config *config = dev->config;
static const uint8_t zeros[] = { 0, 0, 0, 0 };
static const uint8_t ones[] = { 0xFF, 0xFF, 0xFF, 0xFF };
const struct spi_buf tx_bufs[] = {
{
/* Start frame: at least 32 zeros */
.buf = (uint8_t *)zeros,
.len = sizeof(zeros),
},
{
/* LED data itself */
.buf = buf,
.len = size,
},
{
/* End frame: at least 32 ones to clock the
* remaining bits to the LEDs at the end of
* the strip.
*/
.buf = (uint8_t *)ones,
.len = sizeof(ones),
},
};
const struct spi_buf_set tx = {
.buffers = tx_bufs,
.count = ARRAY_SIZE(tx_bufs)
};
return spi_write_dt(&config->bus, &tx);
}
static int apa102_update_rgb(const struct device *dev, struct led_rgb *pixels,
size_t count)
{
uint8_t *p = (uint8_t *)pixels;
size_t i;
/* SOF (3 bits) followed by the 0 to 31 global dimming level */
uint8_t prefix = 0xE0 | 31;
/* Rewrite to the on-wire format */
for (i = 0; i < count; i++) {
uint8_t r = pixels[i].r;
uint8_t g = pixels[i].g;
uint8_t b = pixels[i].b;
*p++ = prefix;
*p++ = b;
*p++ = g;
*p++ = r;
}
BUILD_ASSERT(sizeof(struct led_rgb) == 4);
return apa102_update(dev, pixels, sizeof(struct led_rgb) * count);
}
static size_t apa102_length(const struct device *dev)
{
const struct apa102_config *config = dev->config;
return config->length;
}
static int apa102_init(const struct device *dev)
{
const struct apa102_config *config = dev->config;
if (!spi_is_ready_dt(&config->bus)) {
return -ENODEV;
}
return 0;
}
static const struct led_strip_driver_api apa102_api = {
.update_rgb = apa102_update_rgb,
.length = apa102_length,
};
#define APA102_DEVICE(idx) \
static const struct apa102_config apa102_##idx##_config = { \
.bus = SPI_DT_SPEC_INST_GET( \
idx, \
SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), \
0), \
.length = DT_INST_PROP(idx, chain_length), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, \
apa102_init, \
NULL, \
NULL, \
&apa102_##idx##_config, \
POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, \
&apa102_api);
DT_INST_FOREACH_STATUS_OKAY(APA102_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/apa102.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 780 |
```c
/*
*
* Adapted from the SPI driver, using the procedure in this blog post:
* path_to_url
*
* Note: the word "word" refers to a 32-bit integer unless otherwise stated.
*
* WS/LRCK frequency:
* This refers to the "I2S word or channel select" clock.
* The I2C peripheral sends two 16-bit channel values for each clock period.
* A single LED color (8 data bits) will take up one 32-bit word or one LRCK
* period. This means a standard RGB led will take 3 LRCK periods to transmit.
*
*/
#define DT_DRV_COMPAT worldsemi_ws2812_i2s
#include <string.h>
#include <zephyr/drivers/led_strip.h>
#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ws2812_i2s);
#include <zephyr/device.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#define WS2812_I2S_PRE_DELAY_WORDS 1
struct ws2812_i2s_cfg {
struct device const *dev;
size_t tx_buf_bytes;
struct k_mem_slab *mem_slab;
uint8_t num_colors;
size_t length;
const uint8_t *color_mapping;
uint16_t reset_words;
uint32_t lrck_period;
uint32_t extra_wait_time_us;
bool active_low;
uint8_t nibble_one;
uint8_t nibble_zero;
};
/* Serialize an 8-bit color channel value into two 16-bit I2S values (or 1 32-bit
* word).
*/
static inline void ws2812_i2s_ser(uint32_t *word, uint8_t color, const uint8_t sym_one,
const uint8_t sym_zero)
{
*word = 0;
for (uint16_t i = 0; i < 8; i++) {
if ((1 << i) & color) {
*word |= sym_one << (i * 4);
} else {
*word |= sym_zero << (i * 4);
}
}
/* Swap the two I2S values due to the (audio) channel TX order. */
*word = (*word >> 16) | (*word << 16);
}
static int ws2812_strip_update_rgb(const struct device *dev, struct led_rgb *pixels,
size_t num_pixels)
{
const struct ws2812_i2s_cfg *cfg = dev->config;
uint8_t sym_one, sym_zero;
uint32_t reset_word;
uint32_t *tx_buf;
uint32_t flush_time_us;
void *mem_block;
int ret;
if (cfg->active_low) {
sym_one = (~cfg->nibble_one) & 0x0F;
sym_zero = (~cfg->nibble_zero) & 0x0F;
reset_word = 0xFFFFFFFF;
} else {
sym_one = cfg->nibble_one & 0x0F;
sym_zero = cfg->nibble_zero & 0x0F;
reset_word = 0;
}
/* Acquire memory for the I2S payload. */
ret = k_mem_slab_alloc(cfg->mem_slab, &mem_block, K_SECONDS(10));
if (ret < 0) {
LOG_ERR("Unable to allocate mem slab for TX (err %d)", ret);
return -ENOMEM;
}
tx_buf = (uint32_t *)mem_block;
/* Add a pre-data reset, so the first pixel isn't skipped by the strip. */
for (uint16_t i = 0; i < WS2812_I2S_PRE_DELAY_WORDS; i++) {
*tx_buf = reset_word;
tx_buf++;
}
/*
* Convert pixel data into I2S frames. Each frame has pixel data
* in color mapping on-wire format (e.g. GRB, GRBW, RGB, etc).
*/
for (uint16_t i = 0; i < num_pixels; i++) {
for (uint16_t j = 0; j < cfg->num_colors; j++) {
uint8_t pixel;
switch (cfg->color_mapping[j]) {
/* White channel is not supported by LED strip API. */
case LED_COLOR_ID_WHITE:
pixel = 0;
break;
case LED_COLOR_ID_RED:
pixel = pixels[i].r;
break;
case LED_COLOR_ID_GREEN:
pixel = pixels[i].g;
break;
case LED_COLOR_ID_BLUE:
pixel = pixels[i].b;
break;
default:
return -EINVAL;
}
ws2812_i2s_ser(tx_buf, pixel, sym_one, sym_zero);
tx_buf++;
}
}
for (uint16_t i = 0; i < cfg->reset_words; i++) {
*tx_buf = reset_word;
tx_buf++;
}
/* Flush the buffer on the wire. */
ret = i2s_write(cfg->dev, mem_block, cfg->tx_buf_bytes);
if (ret < 0) {
k_mem_slab_free(cfg->mem_slab, mem_block);
LOG_ERR("Failed to write data: %d", ret);
return ret;
}
ret = i2s_trigger(cfg->dev, I2S_DIR_TX, I2S_TRIGGER_START);
if (ret < 0) {
LOG_ERR("Failed to trigger command %d on TX: %d", I2S_TRIGGER_START, ret);
return ret;
}
ret = i2s_trigger(cfg->dev, I2S_DIR_TX, I2S_TRIGGER_DRAIN);
if (ret < 0) {
LOG_ERR("Failed to trigger command %d on TX: %d", I2S_TRIGGER_DRAIN, ret);
return ret;
}
/* Wait until transaction is over */
flush_time_us = cfg->lrck_period * cfg->tx_buf_bytes / sizeof(uint32_t);
k_usleep(flush_time_us + cfg->extra_wait_time_us);
return ret;
}
static size_t ws2812_strip_length(const struct device *dev)
{
const struct ws2812_i2s_cfg *cfg = dev->config;
return cfg->length;
}
static int ws2812_i2s_init(const struct device *dev)
{
const struct ws2812_i2s_cfg *cfg = dev->config;
struct i2s_config config;
uint32_t lrck_hz;
int ret;
lrck_hz = USEC_PER_SEC / cfg->lrck_period;
LOG_DBG("Word clock: freq %u Hz period %u us",
lrck_hz, cfg->lrck_period);
/* 16-bit stereo, 100kHz LCLK */
config.word_size = 16;
config.channels = 2;
config.format = I2S_FMT_DATA_FORMAT_I2S;
config.options = I2S_OPT_BIT_CLK_MASTER | I2S_OPT_FRAME_CLK_MASTER;
config.frame_clk_freq = lrck_hz; /* WS (or LRCK) */
config.mem_slab = cfg->mem_slab;
config.block_size = cfg->tx_buf_bytes;
config.timeout = 1000;
ret = i2s_configure(cfg->dev, I2S_DIR_TX, &config);
if (ret < 0) {
LOG_ERR("Failed to configure I2S device: %d\n", ret);
return ret;
}
for (uint16_t i = 0; i < cfg->num_colors; i++) {
switch (cfg->color_mapping[i]) {
case LED_COLOR_ID_WHITE:
case LED_COLOR_ID_RED:
case LED_COLOR_ID_GREEN:
case LED_COLOR_ID_BLUE:
break;
default:
LOG_ERR("%s: invalid channel to color mapping."
"Check the color-mapping DT property",
dev->name);
return -EINVAL;
}
}
return 0;
}
static const struct led_strip_driver_api ws2812_i2s_api = {
.update_rgb = ws2812_strip_update_rgb,
.length = ws2812_strip_length,
};
/* Integer division, but always rounds up: e.g. 10/3 = 4 */
#define WS2812_ROUNDED_DIVISION(x, y) ((x + (y - 1)) / y)
#define WS2812_I2S_LRCK_PERIOD_US(idx) DT_INST_PROP(idx, lrck_period)
#define WS2812_RESET_DELAY_US(idx) DT_INST_PROP(idx, reset_delay)
/* Rounds up to the next 20us. */
#define WS2812_RESET_DELAY_WORDS(idx) WS2812_ROUNDED_DIVISION(WS2812_RESET_DELAY_US(idx), \
WS2812_I2S_LRCK_PERIOD_US(idx))
#define WS2812_NUM_COLORS(idx) (DT_INST_PROP_LEN(idx, color_mapping))
#define WS2812_I2S_NUM_PIXELS(idx) (DT_INST_PROP(idx, chain_length))
#define WS2812_I2S_BUFSIZE(idx) \
(((WS2812_NUM_COLORS(idx) * WS2812_I2S_NUM_PIXELS(idx)) + \
WS2812_I2S_PRE_DELAY_WORDS + WS2812_RESET_DELAY_WORDS(idx)) * 4)
#define WS2812_I2S_DEVICE(idx) \
\
K_MEM_SLAB_DEFINE_STATIC(ws2812_i2s_##idx##_slab, WS2812_I2S_BUFSIZE(idx), 2, 4); \
\
static const uint8_t ws2812_i2s_##idx##_color_mapping[] = \
DT_INST_PROP(idx, color_mapping); \
\
static const struct ws2812_i2s_cfg ws2812_i2s_##idx##_cfg = { \
.dev = DEVICE_DT_GET(DT_INST_PROP(idx, i2s_dev)), \
.tx_buf_bytes = WS2812_I2S_BUFSIZE(idx), \
.mem_slab = &ws2812_i2s_##idx##_slab, \
.num_colors = WS2812_NUM_COLORS(idx), \
.length = DT_INST_PROP(idx, chain_length), \
.color_mapping = ws2812_i2s_##idx##_color_mapping, \
.lrck_period = WS2812_I2S_LRCK_PERIOD_US(idx), \
.extra_wait_time_us = DT_INST_PROP(idx, extra_wait_time), \
.reset_words = WS2812_RESET_DELAY_WORDS(idx), \
.active_low = DT_INST_PROP(idx, out_active_low), \
.nibble_one = DT_INST_PROP(idx, nibble_one), \
.nibble_zero = DT_INST_PROP(idx, nibble_zero), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, ws2812_i2s_init, NULL, NULL, &ws2812_i2s_##idx##_cfg, \
POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY, &ws2812_i2s_api);
DT_INST_FOREACH_STATUS_OKAY(WS2812_I2S_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/ws2812_i2s.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,405 |
```c
/*
*
*/
#define DT_DRV_COMPAT worldsemi_ws2812_gpio
#include <zephyr/drivers/led_strip.h>
#include <string.h>
#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ws2812_gpio);
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/dt-bindings/led/led.h>
struct ws2812_gpio_cfg {
struct gpio_dt_spec gpio;
uint8_t num_colors;
const uint8_t *color_mapping;
size_t length;
};
/*
* This is hard-coded to nRF51 in two ways:
*
* 1. The assembly delays T1H, T0H, TxL
* 2. GPIO set/clear
*/
/*
* T1H: 1 bit high pulse delay: 12 cycles == .75 usec
* T0H: 0 bit high pulse delay: 4 cycles == .25 usec
* TxL: inter-bit low pulse delay: 8 cycles == .5 usec
*
* We can't use k_busy_wait() here: its argument is in microseconds,
* and we need roughly .05 microsecond resolution.
*/
#define DELAY_T1H "nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n"
#define DELAY_T0H "nop\nnop\nnop\nnop\n"
#define DELAY_TxL "nop\nnop\nnop\nnop\nnop\nnop\nnop\nnop\n"
/*
* GPIO set/clear (these make assumptions about assembly details
* below).
*
* This uses OUTCLR == OUTSET+4.
*
* We should be able to make this portable using the results of
* path_to_url
*
* We already have the GPIO device stashed in ws2812_gpio_config, so
* this driver can be used as a test case for the optimized API.
*
* Per Arm docs, both Rd and Rn must be r0-r7, so we use the "l"
* constraint in the below assembly.
*/
#define SET_HIGH "str %[p], [%[r], #0]\n" /* OUTSET = BIT(LED_PIN) */
#define SET_LOW "str %[p], [%[r], #4]\n" /* OUTCLR = BIT(LED_PIN) */
/* Send out a 1 bit's pulse */
#define ONE_BIT(base, pin) do { \
__asm volatile (SET_HIGH \
DELAY_T1H \
SET_LOW \
DELAY_TxL \
:: \
[r] "l" (base), \
[p] "l" (pin)); } while (false)
/* Send out a 0 bit's pulse */
#define ZERO_BIT(base, pin) do { \
__asm volatile (SET_HIGH \
DELAY_T0H \
SET_LOW \
DELAY_TxL \
:: \
[r] "l" (base), \
[p] "l" (pin)); } while (false)
static int send_buf(const struct device *dev, uint8_t *buf, size_t len)
{
const struct ws2812_gpio_cfg *config = dev->config;
volatile uint32_t *base = (uint32_t *)&NRF_GPIO->OUTSET;
const uint32_t val = BIT(config->gpio.pin);
struct onoff_manager *mgr =
z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
struct onoff_client cli;
unsigned int key;
int rc;
sys_notify_init_spinwait(&cli.notify);
rc = onoff_request(mgr, &cli);
if (rc < 0) {
return rc;
}
while (sys_notify_fetch_result(&cli.notify, &rc)) {
/* pend until clock is up and running */
}
key = irq_lock();
while (len--) {
uint32_t b = *buf++;
int32_t i;
/*
* Generate signal out of the bits, MSbit first.
*
* Accumulator maintenance and branching mean the
* inter-bit time will be longer than TxL, but the
* wp.josh.com blog post says we have at least 5 usec
* of slack time between bits before we risk the
* signal getting latched, so this will be fine as
* long as the compiler does something minimally
* reasonable.
*/
for (i = 7; i >= 0; i--) {
if (b & BIT(i)) {
ONE_BIT(base, val);
} else {
ZERO_BIT(base, val);
}
}
}
irq_unlock(key);
rc = onoff_release(mgr);
/* Returns non-negative value on success. Cap to 0 as API states. */
rc = MIN(rc, 0);
return rc;
}
static int ws2812_gpio_update_rgb(const struct device *dev,
struct led_rgb *pixels,
size_t num_pixels)
{
const struct ws2812_gpio_cfg *config = dev->config;
uint8_t *ptr = (uint8_t *)pixels;
size_t i;
/* Convert from RGB to on-wire format (e.g. GRB, GRBW, RGB, etc) */
for (i = 0; i < num_pixels; i++) {
uint8_t j;
for (j = 0; j < config->num_colors; j++) {
switch (config->color_mapping[j]) {
/* White channel is not supported by LED strip API. */
case LED_COLOR_ID_WHITE:
*ptr++ = 0;
break;
case LED_COLOR_ID_RED:
*ptr++ = pixels[i].r;
break;
case LED_COLOR_ID_GREEN:
*ptr++ = pixels[i].g;
break;
case LED_COLOR_ID_BLUE:
*ptr++ = pixels[i].b;
break;
default:
return -EINVAL;
}
}
}
return send_buf(dev, (uint8_t *)pixels, num_pixels * config->num_colors);
}
static size_t ws2812_gpio_length(const struct device *dev)
{
const struct ws2812_gpio_cfg *config = dev->config;
return config->length;
}
static const struct led_strip_driver_api ws2812_gpio_api = {
.update_rgb = ws2812_gpio_update_rgb,
.length = ws2812_gpio_length,
};
/*
* Retrieve the channel to color mapping (e.g. RGB, BGR, GRB, ...) from the
* "color-mapping" DT property.
*/
#define WS2812_COLOR_MAPPING(idx) \
static const uint8_t ws2812_gpio_##idx##_color_mapping[] = \
DT_INST_PROP(idx, color_mapping)
#define WS2812_NUM_COLORS(idx) (DT_INST_PROP_LEN(idx, color_mapping))
/*
* The inline assembly above is designed to work on nRF51 devices with
* the 16 MHz clock enabled.
*
* TODO: try to make this portable, or at least port to more devices.
*/
#define WS2812_GPIO_DEVICE(idx) \
\
static int ws2812_gpio_##idx##_init(const struct device *dev) \
{ \
const struct ws2812_gpio_cfg *cfg = dev->config; \
uint8_t i; \
\
if (!gpio_is_ready_dt(&cfg->gpio)) { \
LOG_ERR("GPIO device not ready"); \
return -ENODEV; \
} \
\
for (i = 0; i < cfg->num_colors; i++) { \
switch (cfg->color_mapping[i]) { \
case LED_COLOR_ID_WHITE: \
case LED_COLOR_ID_RED: \
case LED_COLOR_ID_GREEN: \
case LED_COLOR_ID_BLUE: \
break; \
default: \
LOG_ERR("%s: invalid channel to color mapping." \
" Check the color-mapping DT property", \
dev->name); \
return -EINVAL; \
} \
} \
\
return gpio_pin_configure_dt(&cfg->gpio, GPIO_OUTPUT); \
} \
\
WS2812_COLOR_MAPPING(idx); \
\
static const struct ws2812_gpio_cfg ws2812_gpio_##idx##_cfg = { \
.gpio = GPIO_DT_SPEC_INST_GET(idx, gpios), \
.num_colors = WS2812_NUM_COLORS(idx), \
.color_mapping = ws2812_gpio_##idx##_color_mapping, \
.length = DT_INST_PROP(idx, chain_length), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, \
ws2812_gpio_##idx##_init, \
NULL, \
NULL, \
&ws2812_gpio_##idx##_cfg, POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, \
&ws2812_gpio_api);
DT_INST_FOREACH_STATUS_OKAY(WS2812_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/ws2812_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,046 |
```unknown
#
config TLC5971_STRIP
bool "TLC5971 (and compatible) LED strip driver"
depends on SPI
help
Enable LED strip driver for daisy chains of TLC5971-ish devices
``` | /content/code_sandbox/drivers/led_strip/Kconfig.tlc5971 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ws2812_rpi_pico_pio, CONFIG_LED_STRIP_LOG_LEVEL);
#define DT_DRV_COMPAT worldsemi_ws2812_rpi_pico_pio
struct ws2812_led_strip_data {
uint32_t sm;
};
struct ws2812_led_strip_config {
const struct device *piodev;
const uint8_t gpio_pin;
uint8_t num_colors;
size_t length;
uint32_t frequency;
const uint8_t *const color_mapping;
uint16_t reset_delay;
uint32_t cycles_per_bit;
};
struct ws2812_rpi_pico_pio_config {
const struct device *piodev;
const struct pinctrl_dev_config *const pcfg;
struct pio_program program;
};
static int ws2812_led_strip_sm_init(const struct device *dev)
{
const struct ws2812_led_strip_config *config = dev->config;
const float clkdiv =
sys_clock_hw_cycles_per_sec() / (config->cycles_per_bit * config->frequency);
pio_sm_config sm_config = pio_get_default_sm_config();
PIO pio;
int sm;
pio = pio_rpi_pico_get_pio(config->piodev);
sm = pio_claim_unused_sm(pio, false);
if (sm < 0) {
return -EINVAL;
}
sm_config_set_sideset(&sm_config, 1, false, false);
sm_config_set_sideset_pins(&sm_config, config->gpio_pin);
sm_config_set_out_shift(&sm_config, false, true, (config->num_colors == 4 ? 32 : 24));
sm_config_set_fifo_join(&sm_config, PIO_FIFO_JOIN_TX);
sm_config_set_clkdiv(&sm_config, clkdiv);
pio_sm_set_consecutive_pindirs(pio, sm, config->gpio_pin, 1, true);
pio_sm_init(pio, sm, -1, &sm_config);
pio_sm_set_enabled(pio, sm, true);
return sm;
}
/*
* Latch current color values on strip and reset its state machines.
*/
static inline void ws2812_led_strip_reset_delay(uint16_t delay)
{
k_usleep(delay);
}
static int ws2812_led_strip_update_rgb(const struct device *dev, struct led_rgb *pixels,
size_t num_pixels)
{
const struct ws2812_led_strip_config *config = dev->config;
struct ws2812_led_strip_data *data = dev->data;
PIO pio = pio_rpi_pico_get_pio(config->piodev);
for (size_t i = 0; i < num_pixels; i++) {
uint32_t color = 0;
for (size_t j = 0; j < config->num_colors; j++) {
switch (config->color_mapping[j]) {
/* White channel is not supported by LED strip API. */
case LED_COLOR_ID_WHITE:
color |= 0;
break;
case LED_COLOR_ID_RED:
color |= pixels[i].r << (8 * (2 - j));
break;
case LED_COLOR_ID_GREEN:
color |= pixels[i].g << (8 * (2 - j));
break;
case LED_COLOR_ID_BLUE:
color |= pixels[i].b << (8 * (2 - j));
break;
}
}
pio_sm_put_blocking(pio, data->sm, color << (config->num_colors == 4 ? 0 : 8));
}
ws2812_led_strip_reset_delay(config->reset_delay);
return 0;
}
static size_t ws2812_led_strip_length(const struct device *dev)
{
const struct ws2812_led_strip_config *config = dev->config;
return config->length;
}
static const struct led_strip_driver_api ws2812_led_strip_api = {
.update_rgb = ws2812_led_strip_update_rgb,
.length = ws2812_led_strip_length,
};
/*
* Retrieve the channel to color mapping (e.g. RGB, BGR, GRB, ...) from the
* "color-mapping" DT property.
*/
static int ws2812_led_strip_init(const struct device *dev)
{
const struct ws2812_led_strip_config *config = dev->config;
struct ws2812_led_strip_data *data = dev->data;
int sm;
if (!device_is_ready(config->piodev)) {
LOG_ERR("%s: PIO device not ready", dev->name);
return -ENODEV;
}
for (uint32_t i = 0; i < config->num_colors; i++) {
switch (config->color_mapping[i]) {
case LED_COLOR_ID_WHITE:
case LED_COLOR_ID_RED:
case LED_COLOR_ID_GREEN:
case LED_COLOR_ID_BLUE:
break;
default:
LOG_ERR("%s: invalid channel to color mapping."
" Check the color-mapping DT property",
dev->name);
return -EINVAL;
}
}
sm = ws2812_led_strip_sm_init(dev);
if (sm < 0) {
return sm;
}
data->sm = sm;
return 0;
}
static int ws2812_rpi_pico_pio_init(const struct device *dev)
{
const struct ws2812_rpi_pico_pio_config *config = dev->config;
PIO pio;
if (!device_is_ready(config->piodev)) {
LOG_ERR("%s: PIO device not ready", dev->name);
return -ENODEV;
}
pio = pio_rpi_pico_get_pio(config->piodev);
pio_add_program(pio, &config->program);
return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
}
#define CYCLES_PER_BIT(node) \
(DT_PROP_BY_IDX(node, bit_waveform, 0) + DT_PROP_BY_IDX(node, bit_waveform, 1) + \
DT_PROP_BY_IDX(node, bit_waveform, 2))
#define WS2812_CHILD_INIT(node) \
static const uint8_t ws2812_led_strip_##node##_color_mapping[] = \
DT_PROP(node, color_mapping); \
struct ws2812_led_strip_data ws2812_led_strip_##node##_data; \
\
static const struct ws2812_led_strip_config ws2812_led_strip_##node##_config = { \
.piodev = DEVICE_DT_GET(DT_PARENT(DT_PARENT(node))), \
.gpio_pin = DT_GPIO_PIN_BY_IDX(node, gpios, 0), \
.num_colors = DT_PROP_LEN(node, color_mapping), \
.length = DT_PROP(node, chain_length), \
.color_mapping = ws2812_led_strip_##node##_color_mapping, \
.reset_delay = DT_PROP(node, reset_delay), \
.frequency = DT_PROP(node, frequency), \
.cycles_per_bit = CYCLES_PER_BIT(DT_PARENT(node)), \
}; \
\
DEVICE_DT_DEFINE(node, &ws2812_led_strip_init, NULL, &ws2812_led_strip_##node##_data, \
&ws2812_led_strip_##node##_config, POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, &ws2812_led_strip_api);
#define SET_DELAY(op, inst, i) \
(op | (((DT_INST_PROP_BY_IDX(inst, bit_waveform, i) - 1) & 0xF) << 8))
/*
* This pio program runs [T0+T1+T2] cycles per 1 loop.
* The first `out` instruction outputs 0 by [T2] times to the sideset pin.
* These zeros are padding. Here is the start of actual data transmission.
* The second `jmp` instruction output 1 by [T0] times to the sideset pin.
* This `jmp` instruction jumps to line 3 if the value of register x is true.
* Otherwise, jump to line 4.
* The third `jmp` instruction outputs 1 by [T1] times to the sideset pin.
* After output, return to the first line.
* The fourth `jmp` instruction outputs 0 by [T1] times.
* After output, return to the first line and output 0 by [T2] times.
*
* In the case of configuration, T0=3, T1=3, T2 =4,
* the final output is 1110000000 in case register x is false.
* It represents code 0, defined in the datasheet.
* And outputs 1111110000 in case of x is true. It represents code 1.
*/
#define WS2812_RPI_PICO_PIO_INIT(inst) \
PINCTRL_DT_INST_DEFINE(inst); \
\
DT_INST_FOREACH_CHILD_STATUS_OKAY(inst, WS2812_CHILD_INIT); \
\
static const uint16_t rpi_pico_pio_ws2812_instructions_##inst[] = { \
SET_DELAY(0x6021, inst, 2), /* 0: out x, 1 side 0 [T2 - 1] */ \
SET_DELAY(0x1023, inst, 0), /* 1: jmp !x, 3 side 1 [T0 - 1] */ \
SET_DELAY(0x1000, inst, 1), /* 2: jmp 0 side 1 [T1 - 1] */ \
SET_DELAY(0x0000, inst, 1), /* 3: jmp 0 side 0 [T1 - 1] */ \
}; \
\
static const struct ws2812_rpi_pico_pio_config rpi_pico_pio_ws2812_##inst##_config = { \
.piodev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.program = \
{ \
.instructions = rpi_pico_pio_ws2812_instructions_##inst, \
.length = ARRAY_SIZE(rpi_pico_pio_ws2812_instructions_##inst), \
.origin = -1, \
}, \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &ws2812_rpi_pico_pio_init, NULL, NULL, \
&rpi_pico_pio_ws2812_##inst##_config, POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(WS2812_RPI_PICO_PIO_INIT)
``` | /content/code_sandbox/drivers/led_strip/ws2812_rpi_pico_pio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,372 |
```unknown
config LPD880X_STRIP
bool "LPD880x SPI LED strip driver"
default y
depends on DT_HAS_GREELED_LPD8803_ENABLED || DT_HAS_GREELED_LPD8806_ENABLED
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8803),spi) \
|| $(dt_compat_on_bus,$(DT_COMPAT_GREELED_LPD8806),spi)
help
Enable LED strip driver for daisy chains of LPD880x
(LPD8803, LPD8806, or compatible) devices.
Each LPD880x LED driver chip has some output channels
(3 channels for LPD8803, 6 for LPD8806), whose PWM
duty cycle can be set at 7 bit resolution via a
reduced SPI interface (MOSI and CLK lines only).
Each chip also includes data and clock out pins for
daisy chaining LED strips.
``` | /content/code_sandbox/drivers/led_strip/Kconfig.lpd880x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 207 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_tlc59731
/**
* @file
* @brief LED driver for the TLC59731 LED driver.
*
* TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
* With Single-Wire Interface (EasySet)
*
* The EasySet protocol is based on short pulses and the time between
* them. At least one pulse must be sent every T_CYCLE, which can be
* between 1.67us and 50us. We want to go as fast as possible, but
* delays under 1us don't work very well, so we settle on 5us for the
* cycle time.
* A pulse must be high for at least 14ns. In practice, turning a GPIO on
* and immediately off again already takes longer than that, so no delay
* is needed there.
* A zero is represented by no additional pulses within a cycle.
* A one is represented by an additional pulse between 275ns and 2.5us
* (half a cycle) after the first one. We need at least some delay to get to
* 275ns, but because of the limited granularity of k_busy_wait we use a
* full 1us. After the pulse, we wait an additional T_CYCLE_1 to complete
* the cycle. This time can be slightly shorter because the second pulse
* already closes the cycle.
* Finally we need to keep the line low for T_H0 to complete the address
* for a single chip, and T_H1 to complete the write for all chips.
*/
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(tlc59731, CONFIG_LED_STRIP_LOG_LEVEL);
/* Pulse timing */
#define TLC59731_DELAY 0x01 /* us */
#define TLC59731_T_CYCLE_0 0x04 /* us */
#define TLC59731_T_CYCLE_1 0x01 /* us */
#define TLC59731_T_H0 (4 * TLC59731_T_CYCLE_0)
#define TLC59731_T_H1 (8 * TLC59731_T_CYCLE_0)
/* Threshould levels */
#define TLC59731_HIGH 0x01
#define TLC59731_LOW 0x00
/* Write command */
#define TLC59731_WR 0x3A
struct tlc59731_cfg {
struct gpio_dt_spec sdi_gpio;
size_t length;
};
static inline int rgb_pulse(const struct gpio_dt_spec *led_dev)
{
int fret = 0;
fret = gpio_pin_set_dt(led_dev, TLC59731_HIGH);
if (fret != 0) {
return fret;
}
fret = gpio_pin_set_dt(led_dev, TLC59731_LOW);
if (fret != 0) {
return fret;
}
return fret;
}
static int rgb_write_bit(const struct gpio_dt_spec *led_dev, uint8_t data)
{
rgb_pulse(led_dev);
k_busy_wait(TLC59731_DELAY);
if (data) {
rgb_pulse(led_dev);
k_busy_wait(TLC59731_T_CYCLE_1);
} else {
k_busy_wait(TLC59731_T_CYCLE_0);
}
return 0;
}
static int rgb_write_data(const struct gpio_dt_spec *led_dev, uint8_t data)
{
int8_t idx = 7;
while (idx >= 0) {
rgb_write_bit(led_dev, data & BIT((idx--)));
}
return 0;
}
static int tlc59731_led_set_color(const struct device *dev, struct led_rgb *pixel)
{
const struct tlc59731_cfg *tlc_conf = dev->config;
const struct gpio_dt_spec *led_gpio = &tlc_conf->sdi_gpio;
rgb_write_data(led_gpio, TLC59731_WR);
rgb_write_data(led_gpio, pixel->r);
rgb_write_data(led_gpio, pixel->g);
rgb_write_data(led_gpio, pixel->b);
return 0;
}
static int tlc59731_gpio_update_rgb(const struct device *dev, struct led_rgb *pixels,
size_t num_pixels)
{
size_t i;
int err = 0;
for (i = 0; i < num_pixels; i++) {
err = tlc59731_led_set_color(dev, &pixels[i]);
if (err) {
break;
}
}
return err;
}
static size_t tlc59731_length(const struct device *dev)
{
const struct tlc59731_cfg *config = dev->config;
return config->length;
}
static const struct led_strip_driver_api tlc59731_gpio_api = {
.update_rgb = tlc59731_gpio_update_rgb,
.length = tlc59731_length,
};
static int tlc59731_gpio_init(const struct device *dev)
{
const struct tlc59731_cfg *tlc_conf = dev->config;
const struct gpio_dt_spec *led = &tlc_conf->sdi_gpio;
int err = 0;
if (!device_is_ready(led->port)) {
LOG_ERR("%s: no LEDs found (DT child nodes missing)", dev->name);
err = -ENODEV;
goto scape;
}
err = gpio_pin_configure_dt(led, GPIO_OUTPUT_ACTIVE);
if (err < 0) {
LOG_ERR("%s: Unable to setup SDI port", dev->name);
err = -EIO;
goto scape;
}
err = gpio_pin_set_dt(led, TLC59731_LOW);
if (err < 0) {
LOG_ERR("%s: Unable to set the SDI-GPIO)", dev->name);
err = -EIO;
goto scape;
}
gpio_pin_set_dt(led, TLC59731_HIGH);
gpio_pin_set_dt(led, TLC59731_LOW);
k_busy_wait((TLC59731_DELAY + TLC59731_T_CYCLE_0));
scape:
return err;
}
#define TLC59731_DEVICE(i) \
static struct tlc59731_cfg tlc59731_cfg_##i = { \
.sdi_gpio = GPIO_DT_SPEC_INST_GET(i, gpios), \
.length = DT_INST_PROP(i, chain_length), \
}; \
\
DEVICE_DT_INST_DEFINE(i, tlc59731_gpio_init, NULL, NULL, &tlc59731_cfg_##i, POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, &tlc59731_gpio_api);
DT_INST_FOREACH_STATUS_OKAY(TLC59731_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/tlc59731.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,423 |
```unknown
#
# The following blog post is an excellent resource about pulse timing:
#
# path_to_url
config WS2812_STRIP_SPI
bool "WS2812 LED strip SPI driver"
default y
depends on DT_HAS_WORLDSEMI_WS2812_SPI_ENABLED
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_SPI),spi)
help
Enable driver for WS2812 (and compatibles) LED strip using SPI.
The SPI driver is portable, but requires significantly more
memory (1 byte of overhead per bit of pixel data).
config WS2812_STRIP_I2S
bool "WS2812 LED strip I2S driver"
default y
depends on DT_HAS_WORLDSEMI_WS2812_I2S_ENABLED
select I2S if $(dt_compat_on_bus,$(DT_COMPAT_WORLDSEMI_WS2812_I2S),i2s)
help
Enable driver for WS2812 (and compatibles) LED strip using I2S.
Uses the I2S peripheral, memory usage is 4 bytes per color,
times the number of pixels. A few more for the start and end
delay. The reset delay has a coarse resolution of ~20us.
config WS2812_STRIP_GPIO
bool "WS2812 LED strip GPIO driver"
# Only an Cortex-M0 inline assembly implementation for the nRF51
# is supported currently.
default y
depends on DT_HAS_WORLDSEMI_WS2812_GPIO_ENABLED
depends on SOC_SERIES_NRF51X
select LED_STRIP_RGB_SCRATCH
help
Enable driver for WS2812 (and compatibles) LED strip directly controlling with GPIO.
The GPIO driver does bit-banging with inline assembly,
and is not available on all SoCs.
Note that this driver is not compatible with the Everlight B1414
controller.
config WS2812_STRIP_RPI_PICO_PIO
bool "WS2812 LED strip Raspberry Pi Pico PIO driver"
default y
depends on DT_HAS_WORLDSEMI_WS2812_RPI_PICO_PIO_ENABLED
select PICOSDK_USE_PIO
help
Enable driver for WS2812 (and compatibles) LED strip using
the RaspberryPi Pico's PIO.
``` | /content/code_sandbox/drivers/led_strip/Kconfig.ws2812 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 477 |
```unknown
# Top-level configuration file for LED strip drivers.
menuconfig LED_STRIP
bool "Light-Emitting Diode (LED) strip drivers"
help
Include LED strip drivers in the system configuration.
if LED_STRIP
module = LED_STRIP
module-str = LED strip
source "subsys/logging/Kconfig.template.log_config"
config LED_STRIP_INIT_PRIORITY
int "LED strip initialization priority"
default 90
help
System initialization priority for LED strip drivers.
# Hidden option. The extra byte enables efficient serialization and transmission
# for drivers which require 4 B on wire for every 3 B of color, e.g. APA102, but
# is not normally needed.
config LED_STRIP_RGB_SCRATCH
bool
source "drivers/led_strip/Kconfig.lpd880x"
source "drivers/led_strip/Kconfig.ws2812"
source "drivers/led_strip/Kconfig.apa102"
source "drivers/led_strip/Kconfig.tlc5971"
source "drivers/led_strip/Kconfig.tlc59731"
endif # LED_STRIP
``` | /content/code_sandbox/drivers/led_strip/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 218 |
```c
/*
*
*/
#define DT_DRV_COMPAT worldsemi_ws2812_spi
#include <zephyr/drivers/led_strip.h>
#include <string.h>
#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ws2812_spi);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/sys/util.h>
#include <zephyr/dt-bindings/led/led.h>
/* spi-one-frame and spi-zero-frame in DT are for 8-bit frames. */
#define SPI_FRAME_BITS 8
/*
* SPI master configuration:
*
* - mode 0 (the default), 8 bit, MSB first (arbitrary), one-line SPI
* - no shenanigans (don't hold CS, don't hold the device lock, this
* isn't an EEPROM)
*/
#define SPI_OPER(idx) (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | \
SPI_WORD_SET(SPI_FRAME_BITS))
struct ws2812_spi_cfg {
struct spi_dt_spec bus;
uint8_t *px_buf;
uint8_t one_frame;
uint8_t zero_frame;
uint8_t num_colors;
const uint8_t *color_mapping;
size_t length;
uint16_t reset_delay;
};
static const struct ws2812_spi_cfg *dev_cfg(const struct device *dev)
{
return dev->config;
}
/*
* Serialize an 8-bit color channel value into an equivalent sequence
* of SPI frames, MSbit first, where a one bit becomes SPI frame
* one_frame, and zero bit becomes zero_frame.
*/
static inline void ws2812_spi_ser(uint8_t buf[8], uint8_t color,
const uint8_t one_frame, const uint8_t zero_frame)
{
int i;
for (i = 0; i < 8; i++) {
buf[i] = color & BIT(7 - i) ? one_frame : zero_frame;
}
}
/*
* Latch current color values on strip and reset its state machines.
*/
static inline void ws2812_reset_delay(uint16_t delay)
{
k_usleep(delay);
}
static int ws2812_strip_update_rgb(const struct device *dev,
struct led_rgb *pixels,
size_t num_pixels)
{
const struct ws2812_spi_cfg *cfg = dev_cfg(dev);
const uint8_t one = cfg->one_frame, zero = cfg->zero_frame;
struct spi_buf buf = {
.buf = cfg->px_buf,
.len = (cfg->length * 8 * cfg->num_colors),
};
const struct spi_buf_set tx = {
.buffers = &buf,
.count = 1
};
uint8_t *px_buf = cfg->px_buf;
size_t i;
int rc;
/*
* Convert pixel data into SPI frames. Each frame has pixel data
* in color mapping on-wire format (e.g. GRB, GRBW, RGB, etc).
*/
for (i = 0; i < num_pixels; i++) {
uint8_t j;
for (j = 0; j < cfg->num_colors; j++) {
uint8_t pixel;
switch (cfg->color_mapping[j]) {
/* White channel is not supported by LED strip API. */
case LED_COLOR_ID_WHITE:
pixel = 0;
break;
case LED_COLOR_ID_RED:
pixel = pixels[i].r;
break;
case LED_COLOR_ID_GREEN:
pixel = pixels[i].g;
break;
case LED_COLOR_ID_BLUE:
pixel = pixels[i].b;
break;
default:
return -EINVAL;
}
ws2812_spi_ser(px_buf, pixel, one, zero);
px_buf += 8;
}
}
/*
* Display the pixel data.
*/
rc = spi_write_dt(&cfg->bus, &tx);
ws2812_reset_delay(cfg->reset_delay);
return rc;
}
static size_t ws2812_strip_length(const struct device *dev)
{
const struct ws2812_spi_cfg *cfg = dev_cfg(dev);
return cfg->length;
}
static int ws2812_spi_init(const struct device *dev)
{
const struct ws2812_spi_cfg *cfg = dev_cfg(dev);
uint8_t i;
if (!spi_is_ready_dt(&cfg->bus)) {
LOG_ERR("SPI device %s not ready", cfg->bus.bus->name);
return -ENODEV;
}
for (i = 0; i < cfg->num_colors; i++) {
switch (cfg->color_mapping[i]) {
case LED_COLOR_ID_WHITE:
case LED_COLOR_ID_RED:
case LED_COLOR_ID_GREEN:
case LED_COLOR_ID_BLUE:
break;
default:
LOG_ERR("%s: invalid channel to color mapping."
"Check the color-mapping DT property",
dev->name);
return -EINVAL;
}
}
return 0;
}
static const struct led_strip_driver_api ws2812_spi_api = {
.update_rgb = ws2812_strip_update_rgb,
.length = ws2812_strip_length,
};
#define WS2812_SPI_NUM_PIXELS(idx) \
(DT_INST_PROP(idx, chain_length))
#define WS2812_SPI_HAS_WHITE(idx) \
(DT_INST_PROP(idx, has_white_channel) == 1)
#define WS2812_SPI_ONE_FRAME(idx) \
(DT_INST_PROP(idx, spi_one_frame))
#define WS2812_SPI_ZERO_FRAME(idx) \
(DT_INST_PROP(idx, spi_zero_frame))
#define WS2812_SPI_BUFSZ(idx) \
(WS2812_NUM_COLORS(idx) * 8 * WS2812_SPI_NUM_PIXELS(idx))
/*
* Retrieve the channel to color mapping (e.g. RGB, BGR, GRB, ...) from the
* "color-mapping" DT property.
*/
#define WS2812_COLOR_MAPPING(idx) \
static const uint8_t ws2812_spi_##idx##_color_mapping[] = \
DT_INST_PROP(idx, color_mapping)
#define WS2812_NUM_COLORS(idx) (DT_INST_PROP_LEN(idx, color_mapping))
/* Get the latch/reset delay from the "reset-delay" DT property. */
#define WS2812_RESET_DELAY(idx) DT_INST_PROP(idx, reset_delay)
#define WS2812_SPI_DEVICE(idx) \
\
static uint8_t ws2812_spi_##idx##_px_buf[WS2812_SPI_BUFSZ(idx)]; \
\
WS2812_COLOR_MAPPING(idx); \
\
static const struct ws2812_spi_cfg ws2812_spi_##idx##_cfg = { \
.bus = SPI_DT_SPEC_INST_GET(idx, SPI_OPER(idx), 0), \
.px_buf = ws2812_spi_##idx##_px_buf, \
.one_frame = WS2812_SPI_ONE_FRAME(idx), \
.zero_frame = WS2812_SPI_ZERO_FRAME(idx), \
.num_colors = WS2812_NUM_COLORS(idx), \
.color_mapping = ws2812_spi_##idx##_color_mapping, \
.length = DT_INST_PROP(idx, chain_length), \
.reset_delay = WS2812_RESET_DELAY(idx), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, \
ws2812_spi_init, \
NULL, \
NULL, \
&ws2812_spi_##idx##_cfg, \
POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, \
&ws2812_spi_api);
DT_INST_FOREACH_STATUS_OKAY(WS2812_SPI_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/ws2812_spi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,634 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_tlc5971
#include <zephyr/kernel.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/led_strip.h>
#include <zephyr/drivers/led_strip/tlc5971.h>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(tlc5971, CONFIG_LED_STRIP_LOG_LEVEL);
struct tlc5971_config {
struct spi_dt_spec bus;
const uint8_t *color_mapping;
uint8_t num_pixels;
uint8_t num_colors;
};
struct tlc5971_data {
uint8_t *data_buffer;
uint8_t gbc_color_1;
uint8_t gbc_color_2;
uint8_t gbc_color_3;
uint8_t control_data;
};
/** SPI operation word constant, SPI mode 0, CPOL = 0, CPHA = 0 */
#define TLC5971_SPI_OPERATION (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8))
/** Number of supported colors */
#define TLC5971_NUMBER_OF_COLORS 3
/**
* @brief Number of RGB pixels per TLC5791 device
*
* The TLC5971 has 4x RGB outputs per device, where each RGB group constitues a pixel from this
* drivers point of view.
*/
#define TLC5971_PIXELS_PER_DEVICE 4
/** Length in bytes of data packet per TLC5791 device */
#define TLC5971_PACKET_LEN 28
/** write command for writing control data and GS data to internal registers */
#define TLC5971_WRITE_COMMAND 0x25
/** GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock). */
#define TLC5971_BYTE27_CTRL_BIT_EXTGCK BIT(0)
/** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
#define TLC5971_BYTE27_CTRL_BIT_OUTTMG BIT(1)
/** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
#define TLC5971_BYTE26_CTRL_BIT_BLANK BIT(5)
/** Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled). */
#define TLC5971_BYTE26_CTRL_BIT_DSPRPT BIT(6)
/** Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). */
#define TLC5971_BYTE26_CTRL_BIT_TMGRST BIT(7)
/** Bit mask for write cmd in data byte 27 */
#define TLC5971_BYTE27_WRITE_CMD_MASK GENMASK(7, 2)
/** Bit mask for control bits in data byte 27 */
#define TLC5971_BYTE27_CTRL_MASK GENMASK(1, 0)
/** Bit mask for control bits in data byte 26 */
#define TLC5971_BYTE26_CTRL_MASK GENMASK(7, 5)
/** Bit mask for global brightness control for color 1 in data byte 26, upper 5 bits of GBC */
#define TLC5971_BYTE26_GBC1_MASK GENMASK(4, 0)
/** Bit mask for global brightness control for color 1 in data byte 25, lower 2 bits of GBC */
#define TLC5971_BYTE25_GBC1_MASK GENMASK(7, 6)
/** Bit mask for global brightness control for color 2 in data byte 25, upper 6 bits of GBC */
#define TLC5971_BYTE25_GBC2_MASK GENMASK(5, 0)
/** Bit mask for global brightness control for color 2 in data byte 24, lower 1 bits of GBC */
#define TLC5971_BYTE24_GBC2_MASK BIT(7)
/** Bit mask for global brightness control for color 3 in data byte 24, all 7 bits of GBC */
#define TLC5971_BYTE24_GBC3_MASK GENMASK(6, 0)
/**
* @brief create data byte 27 from control data
*
* @param control_data control bits
* @return uint8_t the serialized data byte 27
*/
static inline uint8_t tlc5971_data_byte27(uint8_t control_data)
{
return FIELD_PREP(TLC5971_BYTE27_WRITE_CMD_MASK, TLC5971_WRITE_COMMAND) |
FIELD_PREP(TLC5971_BYTE27_CTRL_MASK, control_data);
}
/**
* @brief create data byte 26 from control data and color 1 GBC
*
* @param control_data control bits
* @param gbc_color_1 global brightness control for color 1 LEDs
* @return uint8_t the serialized data byte 26
*/
static inline uint8_t tlc5971_data_byte26(uint8_t control_data, uint8_t gbc_color_1)
{
return FIELD_PREP(TLC5971_BYTE26_CTRL_MASK, control_data) |
FIELD_PREP(TLC5971_BYTE26_GBC1_MASK, (gbc_color_1 >> 2));
}
/**
* @brief create data byte 25 from color 1 and 2 GBC
*
* @param gbc_color_1 global brightness control for color 1 LEDs
* @param gbc_color_2 global brightness control for color 2 LEDs
* @return uint8_t the serialized data byte 25
*/
static inline uint8_t tlc5971_data_byte25(uint8_t gbc_color_1, uint8_t gbc_color_2)
{
return FIELD_PREP(TLC5971_BYTE25_GBC1_MASK, gbc_color_1) |
FIELD_PREP(TLC5971_BYTE25_GBC2_MASK, (gbc_color_2 >> 1));
}
/**
* @brief create data byte 24 from color 2 and 3 GBC
*
* @param gbc_color_2 global brightness control for color 2 LEDs
* @param gbc_color_3 global brightness control for color 3 LEDs
* @return uint8_t the serialized data byte 24
*/
static inline uint8_t tlc5971_data_byte24(uint8_t gbc_color_2, uint8_t gbc_color_3)
{
return FIELD_PREP(TLC5971_BYTE24_GBC2_MASK, gbc_color_2) |
FIELD_PREP(TLC5971_BYTE24_GBC3_MASK, gbc_color_3);
}
/**
* @brief map user colors to tlc5971 color order
*
* @param color_id color id from color mapping
* @param pixel_data rgb data to be mapped
* @return the mapped color value
*/
static uint8_t tlc5971_map_color(int color_id, const struct led_rgb *pixel_data)
{
uint8_t temp = 0;
switch (color_id) {
case LED_COLOR_ID_RED:
temp = pixel_data->r;
break;
case LED_COLOR_ID_GREEN:
temp = pixel_data->g;
break;
case LED_COLOR_ID_BLUE:
temp = pixel_data->b;
break;
default:
temp = 0;
break;
}
return temp;
}
/**
* @brief serialize control data and pixel data for device daisy chain
*
* the serializer only supports "full" devices, meaning each device is expected
* to be mounted with all 4 LEDs.
*
* @param dev device pointer
* @param pixels pixel RGB data for daisy chain
* @param num_pixels number of pixels in daisy chain
*/
static void tlc5971_fill_data_buffer(const struct device *dev, struct led_rgb *pixels,
size_t num_pixels)
{
const struct tlc5971_config *cfg = dev->config;
struct tlc5971_data *data = dev->data;
uint8_t *data_buffer = data->data_buffer;
int count = 0;
/*
* tlc5971 device order is reversed as the rgb data for the last device in the daisy chain
* should be transmitted first.
*/
for (int device = (num_pixels / TLC5971_PIXELS_PER_DEVICE) - 1; device >= 0; device--) {
/*
* The SPI frame format expects a BGR color order for the global brightness control
* values, but since the led_strip API allows custom color mappings, we simply use
* color_x terms to keep things generic.
*/
data_buffer[count++] = tlc5971_data_byte27(data->control_data);
data_buffer[count++] = tlc5971_data_byte26(data->control_data, data->gbc_color_1);
data_buffer[count++] = tlc5971_data_byte25(data->gbc_color_1, data->gbc_color_2);
data_buffer[count++] = tlc5971_data_byte24(data->gbc_color_2, data->gbc_color_3);
for (int pixel = (TLC5971_PIXELS_PER_DEVICE - 1); pixel >= 0; pixel--) {
/* data is "reversed" so RGB0 comes last, i.e at byte 0 */
const struct led_rgb *pixel_data =
&pixels[(device * TLC5971_PIXELS_PER_DEVICE) + pixel];
/*
* Convert pixel data into SPI frames, mapping user colors to tlc5971
* data frame color order (BGR).
*/
for (int color = 0; color < cfg->num_colors; color++) {
uint8_t temp =
tlc5971_map_color(cfg->color_mapping[color], pixel_data);
/*
* The tlc5971 rgb values are 16 bit but zephyr's rgb values are
* 8 bit. Simply upscale to 16 bit by using the 8 bit value for both
* LSB and MSB of the 16 bit word.
*/
data_buffer[count++] = temp;
data_buffer[count++] = temp;
}
}
}
}
static int tlc5971_transmit_data(const struct device *dev, size_t num_pixels)
{
const struct tlc5971_config *cfg = dev->config;
struct tlc5971_data *data = dev->data;
struct spi_buf buf = {
.buf = data->data_buffer,
.len = (num_pixels / TLC5971_PIXELS_PER_DEVICE) * TLC5971_PACKET_LEN,
};
const struct spi_buf_set tx = {
.buffers = &buf,
.count = 1,
};
return spi_write_dt(&cfg->bus, &tx);
}
static int tlc5971_update_rgb(const struct device *dev, struct led_rgb *pixels, size_t num_pixels)
{
tlc5971_fill_data_buffer(dev, pixels, num_pixels);
return tlc5971_transmit_data(dev, num_pixels);
}
static size_t tlc5971_length(const struct device *dev)
{
const struct tlc5971_config *cfg = dev->config;
return (size_t)cfg->num_pixels;
}
int tlc5971_set_global_brightness(const struct device *dev, struct led_rgb pixel)
{
const struct tlc5971_config *cfg = dev->config;
struct tlc5971_data *data = dev->data;
int res = -EINVAL;
if ((pixel.r <= TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX) &&
(pixel.g <= TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX) &&
(pixel.b <= TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX)) {
data->gbc_color_1 = tlc5971_map_color(cfg->color_mapping[0], &pixel);
data->gbc_color_2 = tlc5971_map_color(cfg->color_mapping[1], &pixel);
data->gbc_color_3 = tlc5971_map_color(cfg->color_mapping[2], &pixel);
res = 0;
}
return res;
}
static int tlc5971_init(const struct device *dev)
{
const struct tlc5971_config *cfg = dev->config;
struct tlc5971_data *data = dev->data;
if (!spi_is_ready_dt(&cfg->bus)) {
LOG_ERR("%s: SPI device %s not ready", dev->name, cfg->bus.bus->name);
return -ENODEV;
}
if ((cfg->num_pixels % TLC5971_PIXELS_PER_DEVICE) != 0) {
LOG_ERR("%s: chain length must be multiple of 4", dev->name);
return -EINVAL;
}
if (cfg->num_colors != TLC5971_NUMBER_OF_COLORS) {
LOG_ERR("%s: the tlc5971 only supports %i colors", dev->name,
TLC5971_NUMBER_OF_COLORS);
return -EINVAL;
}
for (int i = 0; i < cfg->num_colors; i++) {
switch (cfg->color_mapping[i]) {
case LED_COLOR_ID_RED:
case LED_COLOR_ID_GREEN:
case LED_COLOR_ID_BLUE:
break;
default:
LOG_ERR("%s: invalid color mapping", dev->name);
return -EINVAL;
}
}
/*
* set up sane defaults for control data.
* unblanks leds, enables auto display repeat, enables timing resetm uses internal clock for
* PWM generation and sets the GS reference clock edge select to rising edge
*/
data->control_data = TLC5971_BYTE27_CTRL_BIT_OUTTMG | TLC5971_BYTE26_CTRL_BIT_DSPRPT |
TLC5971_BYTE26_CTRL_BIT_TMGRST;
return 0;
}
static const struct led_strip_driver_api tlc5971_api = {
.update_rgb = tlc5971_update_rgb,
.length = tlc5971_length,
};
#define TLC5971_DATA_BUFFER_LENGTH(inst) \
(DT_INST_PROP(inst, chain_length) / TLC5971_PIXELS_PER_DEVICE) * TLC5971_PACKET_LEN
#define TLC5971_DEVICE(inst) \
static const uint8_t tlc5971_##inst##_color_mapping[] = DT_INST_PROP(inst, color_mapping); \
static const struct tlc5971_config tlc5971_##inst##_config = { \
.bus = SPI_DT_SPEC_INST_GET(inst, TLC5971_SPI_OPERATION, 0), \
.num_pixels = DT_INST_PROP(inst, chain_length), \
.num_colors = DT_INST_PROP_LEN(inst, color_mapping), \
.color_mapping = tlc5971_##inst##_color_mapping, \
}; \
static uint8_t tlc5971_##inst##_data_buffer[TLC5971_DATA_BUFFER_LENGTH(inst)]; \
static struct tlc5971_data tlc5971_##inst##_data = { \
.data_buffer = tlc5971_##inst##_data_buffer, \
.gbc_color_1 = TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX, \
.gbc_color_2 = TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX, \
.gbc_color_3 = TLC5971_GLOBAL_BRIGHTNESS_CONTROL_MAX, \
}; \
DEVICE_DT_INST_DEFINE(inst, tlc5971_init, NULL, &tlc5971_##inst##_data, \
&tlc5971_##inst##_config, POST_KERNEL, \
CONFIG_LED_STRIP_INIT_PRIORITY, &tlc5971_api);
DT_INST_FOREACH_STATUS_OKAY(TLC5971_DEVICE)
``` | /content/code_sandbox/drivers/led_strip/tlc5971.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,245 |
```unknown
# Sequans HW spinlock configuration
config SQN_HWSPINLOCK
bool "Sequans HW spinlock Driver"
default y
depends on DT_HAS_SQN_HWSPINLOCK_ENABLED
help
Enable HW spinlock for SQN
if SQN_HWSPINLOCK
config SQN_HWSPINLOCK_RELAX_TIME
int "Sequans HW spinlock relax time"
default 50
help
Default HW spinlock relax time in microseconds.
endif #SQN_HWSPINLOCK
``` | /content/code_sandbox/drivers/hwspinlock/Kconfig.sqn | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```c
/*
*
*/
#include <zephyr/drivers/hwspinlock.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_hwspinlock_trylock(const struct device *dev, uint32_t id)
{
K_OOPS(K_SYSCALL_DRIVER_HWSPINLOCK(dev, trylock));
return z_impl_hwspinlock_trylock(dev, id);
}
#include <zephyr/syscalls/hwspinlock_trylock_mrsh.c>
static inline void z_vrfy_hwspinlock_lock(const struct device *dev, uint32_t id)
{
K_OOPS(K_SYSCALL_DRIVER_HWSPINLOCK(dev, lock));
z_impl_hwspinlock_lock(dev, id);
}
#include <zephyr/syscalls/hwspinlock_lock_mrsh.c>
static inline void z_vrfy_hwspinlock_unlock(const struct device *dev, uint32_t id)
{
K_OOPS(K_SYSCALL_DRIVER_HWSPINLOCK(dev, unlock));
z_impl_hwspinlock_unlock(dev, id);
}
#include <zephyr/syscalls/hwspinlock_unlock_mrsh.c>
static inline uint32_t z_vrfy_hwspinlock_get_max_id(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_HWSPINLOCK(dev, get_max_id));
return z_impl_hwspinlock_get_max_id(dev);
}
#include <zephyr/syscalls/hwspinlock_get_max_id_mrsh.c>
``` | /content/code_sandbox/drivers/hwspinlock/hwspinlock_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 296 |
```unknown
# HW spinlock configuration options
menuconfig HWSPINLOCK
bool "HW spinlock Support"
help
Include support for HW spinlock.
if HWSPINLOCK
config HWSPINLOCK_INIT_PRIORITY
int "HW spinlock init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
HW spinlock driver device initialization priority.
source "drivers/hwspinlock/Kconfig.sqn"
endif
``` | /content/code_sandbox/drivers/hwspinlock/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
# Hidden option to enable the vnd,w1 1-Wire host driver used in testing.
config W1_TEST
def_bool DT_HAS_VND_W1_ENABLED
depends on DT_HAS_VND_W1_ENABLED
``` | /content/code_sandbox/drivers/w1/Kconfig.test | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```c
/*
*
*/
#define DT_DRV_COMPAT sqn_hwspinlock
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/hwspinlock.h>
#include <zephyr/sys/printk.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(sqn_hwspinlock);
struct sqn_hwspinlock_data {
DEVICE_MMIO_RAM;
};
struct sqn_hwspinlock_config {
DEVICE_MMIO_ROM;
uint32_t num_locks;
};
static inline mem_addr_t get_lock_addr(const struct device *dev, uint32_t id)
{
return (mem_addr_t)(DEVICE_MMIO_GET(dev) + id * sizeof(uint32_t));
}
/*
* To define CPU id, we use the affinity2 and affinity1
* fields of the MPIDR register.
*/
static uint8_t mpidr_to_cpuid(uint64_t mpidr_val)
{
uint8_t cpuid = ((mpidr_val >> 8) & 0x0F) | ((mpidr_val >> 12) & 0xF0);
return ++cpuid;
}
static int sqn_hwspinlock_trylock(const struct device *dev, uint32_t id)
{
const struct sqn_hwspinlock_config *config = dev->config;
uint8_t cpuid;
if (id > config->num_locks)
return -EINVAL;
/*
* If the register value is equal to cpuid, this means that the current
* core has already locked the HW spinlock.
* If not, we try to lock the HW spinlock by writing cpuid, then check
* whether it is locked.
*/
cpuid = mpidr_to_cpuid(read_mpidr_el1());
if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
}
sys_write8(cpuid, get_lock_addr(dev, id));
if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
}
return -EBUSY;
}
static void sqn_hwspinlock_lock(const struct device *dev, uint32_t id)
{
const struct sqn_hwspinlock_config *config = dev->config;
uint8_t cpuid;
if (id > config->num_locks) {
LOG_ERR("unsupported hwspinlock id '%d'", id);
return;
}
/*
* Writing cpuid is equivalent to trying to lock HW spinlock, after
* which we check whether we've locked by reading the register value
* and comparing it with cpuid.
*/
cpuid = mpidr_to_cpuid(read_mpidr_el1());
if (sys_read8(get_lock_addr(dev, id)) == 0) {
sys_write8(cpuid, get_lock_addr(dev, id));
}
while (sys_read8(get_lock_addr(dev, id)) != cpuid) {
k_busy_wait(CONFIG_SQN_HWSPINLOCK_RELAX_TIME);
sys_write8(cpuid, get_lock_addr(dev, id));
}
}
static void sqn_hwspinlock_unlock(const struct device *dev, uint32_t id)
{
const struct sqn_hwspinlock_config *config = dev->config;
uint8_t cpuid;
if (id > config->num_locks) {
LOG_ERR("unsupported hwspinlock id '%d'", id);
return;
}
/*
* If the HW spinlock register value is equal to the cpuid and we write
* the cpuid, then the register value will be 0. So to unlock the
* hwspinlock, we write cpuid.
*/
cpuid = mpidr_to_cpuid(read_mpidr_el1());
sys_write8(cpuid, get_lock_addr(dev, id));
}
static uint32_t sqn_hwspinlock_get_max_id(const struct device *dev)
{
const struct sqn_hwspinlock_config *config = dev->config;
return config->num_locks;
}
static const struct hwspinlock_driver_api hwspinlock_api = {
.trylock = sqn_hwspinlock_trylock,
.lock = sqn_hwspinlock_lock,
.unlock = sqn_hwspinlock_unlock,
.get_max_id = sqn_hwspinlock_get_max_id,
};
static int sqn_hwspinlock_init(const struct device *dev)
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
return 0;
}
#define SQN_HWSPINLOCK_INIT(idx) \
static struct sqn_hwspinlock_data sqn_hwspinlock##idx##_data; \
static const struct sqn_hwspinlock_config sqn_hwspinlock##idx##_config = { \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(idx)), \
.num_locks = DT_INST_PROP(idx, num_locks), \
}; \
DEVICE_DT_INST_DEFINE(idx, \
sqn_hwspinlock_init, \
NULL, \
&sqn_hwspinlock##idx##_data, \
&sqn_hwspinlock##idx##_config, \
PRE_KERNEL_1, CONFIG_HWSPINLOCK_INIT_PRIORITY, \
&hwspinlock_api)
DT_INST_FOREACH_STATUS_OKAY(SQN_HWSPINLOCK_INIT);
``` | /content/code_sandbox/drivers/hwspinlock/sqn_hwspinlock.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,132 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/w1.h>
static inline int z_vrfy_w1_reset_bus(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, reset_bus));
return z_impl_w1_reset_bus((const struct device *)dev);
}
#include <zephyr/syscalls/w1_reset_bus_mrsh.c>
static inline int z_vrfy_w1_read_bit(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, read_bit));
return z_impl_w1_read_bit((const struct device *)dev);
}
#include <zephyr/syscalls/w1_read_bit_mrsh.c>
static inline int z_vrfy_w1_write_bit(const struct device *dev, bool bit)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, write_bit));
return z_impl_w1_write_bit((const struct device *)dev, bit);
}
#include <zephyr/syscalls/w1_write_bit_mrsh.c>
static inline int z_vrfy_w1_read_byte(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, read_byte));
return z_impl_w1_read_byte((const struct device *)dev);
}
#include <zephyr/syscalls/w1_read_byte_mrsh.c>
static inline int z_vrfy_w1_write_byte(const struct device *dev, uint8_t byte)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, write_byte));
return z_impl_w1_write_byte((const struct device *)dev, (uint8_t)byte);
}
#include <zephyr/syscalls/w1_write_byte_mrsh.c>
static inline int z_vrfy_w1_read_block(const struct device *dev,
uint8_t *buffer, size_t len)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_W1));
K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, len));
return z_impl_w1_read_block((const struct device *)dev,
(uint8_t *)buffer, (size_t)len);
}
#include <zephyr/syscalls/w1_read_block_mrsh.c>
static inline int z_vrfy_w1_write_block(const struct device *dev,
const uint8_t *buffer, size_t len)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_W1));
K_OOPS(K_SYSCALL_MEMORY_READ(buffer, len));
return z_impl_w1_write_block((const struct device *)dev,
(const uint8_t *)buffer, (size_t)len);
}
#include <zephyr/syscalls/w1_write_block_mrsh.c>
static inline int z_vrfy_w1_change_bus_lock(const struct device *dev, bool lock)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_W1));
return z_impl_w1_change_bus_lock((const struct device *)dev, lock);
}
#include <zephyr/syscalls/w1_change_bus_lock_mrsh.c>
static inline int z_vrfy_w1_configure(const struct device *dev,
enum w1_settings_type type, uint32_t value)
{
K_OOPS(K_SYSCALL_DRIVER_W1(dev, configure));
return z_impl_w1_configure(dev, type, value);
}
#include <zephyr/syscalls/w1_configure_mrsh.c>
static inline size_t z_vrfy_w1_get_slave_count(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_W1));
return z_impl_w1_get_slave_count((const struct device *)dev);
}
#include <zephyr/syscalls/w1_get_slave_count_mrsh.c>
#if CONFIG_W1_NET
static inline int z_vrfy_w1_search_bus(const struct device *dev,
uint8_t command, uint8_t family,
w1_search_callback_t callback,
void *user_data)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_W1));
K_OOPS(K_SYSCALL_VERIFY_MSG(callback == 0,
"callbacks may not be set from user mode"));
/* user_data is not dereferenced, no need to check parameter */
return z_impl_w1_search_bus((const struct device *)dev,
(uint8_t)command, (uint8_t)family,
(w1_search_callback_t)callback,
(void *)user_data);
}
#include <zephyr/syscalls/w1_search_bus_mrsh.c>
#endif /* CONFIG_W1_NET */
``` | /content/code_sandbox/drivers/w1/w1_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 935 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_w1_gpio
/**
* @brief 1-Wire Bus Master driver using Zephyr GPIO interface.
*
* This file contains the implementation of the 1-Wire Bus Master driver using
* the Zephyr GPIO interface. The driver is based on GPIO bit-banging and
* follows the timing specifications for 1-Wire communication.
*
* The driver supports both standard speed and overdrive speed modes.
*
* This driver is heavily based on the w1_zephyr_serial.c driver and the
* technical documentation from Maxim Integrated.
*
* - w1_zephyr_serial.c: drivers/w1/w1_zephyr_serial.c
* - Maxim Integrated 1-Wire Communication Through Software:
* path_to_url
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(w1_gpio, CONFIG_W1_LOG_LEVEL);
/*
* The time critical sections are used to ensure that the timing
* between communication operations is correct.
*/
#if defined(CONFIG_W1_ZEPHYR_GPIO_TIME_CRITICAL)
#define W1_GPIO_ENTER_CRITICAL() irq_lock()
#define W1_GPIO_EXIT_CRITICAL(key) irq_unlock(key)
#define W1_GPIO_WAIT_US(us) k_busy_wait(us)
#else
#define W1_GPIO_ENTER_CRITICAL() 0u
#define W1_GPIO_EXIT_CRITICAL(key) (void)key
#define W1_GPIO_WAIT_US(us) k_usleep(us)
#endif
/*
* Standard timing between communication operations:
*/
#define W1_GPIO_TIMING_STD_A 6u
#define W1_GPIO_TIMING_STD_B 64u
#define W1_GPIO_TIMING_STD_C 60u
#define W1_GPIO_TIMING_STD_D 10u
#define W1_GPIO_TIMING_STD_E 9u
#define W1_GPIO_TIMING_STD_F 55u
#define W1_GPIO_TIMING_STD_G 0u
#define W1_GPIO_TIMING_STD_H 480u
#define W1_GPIO_TIMING_STD_I 70u
#define W1_GPIO_TIMING_STD_J 410u
/*
* Overdrive timing between communication operations:
*
* Not completely correct since the overdrive communication requires
* delays of 2.5us, 7.5us and 8.5us.
* The delays are approximated by flooring the values.
*/
#define W1_GPIO_TIMING_OD_A 1u
#define W1_GPIO_TIMING_OD_B 7u
#define W1_GPIO_TIMING_OD_C 7u
#define W1_GPIO_TIMING_OD_D 2u
#define W1_GPIO_TIMING_OD_E 1u
#define W1_GPIO_TIMING_OD_F 7u
#define W1_GPIO_TIMING_OD_G 2u
#define W1_GPIO_TIMING_OD_H 70u
#define W1_GPIO_TIMING_OD_I 8u
#define W1_GPIO_TIMING_OD_J 40u
struct w1_gpio_timing {
uint16_t a;
uint16_t b;
uint16_t c;
uint16_t d;
uint16_t e;
uint16_t f;
uint16_t g;
uint16_t h;
uint16_t i;
uint16_t j;
};
struct w1_gpio_config {
/** w1 master config, common to all drivers */
struct w1_master_config master_config;
/** GPIO device used for 1-Wire communication */
const struct gpio_dt_spec spec;
};
struct w1_gpio_data {
/** w1 master data, common to all drivers */
struct w1_master_data master_data;
/** timing parameters for 1-Wire communication */
const struct w1_gpio_timing *timing;
/** overdrive speed mode active */
bool overdrive_active;
};
static const struct w1_gpio_timing std = {
.a = W1_GPIO_TIMING_STD_A,
.b = W1_GPIO_TIMING_STD_B,
.c = W1_GPIO_TIMING_STD_C,
.d = W1_GPIO_TIMING_STD_D,
.e = W1_GPIO_TIMING_STD_E,
.f = W1_GPIO_TIMING_STD_F,
.g = W1_GPIO_TIMING_STD_G,
.h = W1_GPIO_TIMING_STD_H,
.i = W1_GPIO_TIMING_STD_I,
.j = W1_GPIO_TIMING_STD_J,
};
static const struct w1_gpio_timing od = {
.a = W1_GPIO_TIMING_OD_A,
.b = W1_GPIO_TIMING_OD_B,
.c = W1_GPIO_TIMING_OD_C,
.d = W1_GPIO_TIMING_OD_D,
.e = W1_GPIO_TIMING_OD_E,
.f = W1_GPIO_TIMING_OD_F,
.g = W1_GPIO_TIMING_OD_G,
.h = W1_GPIO_TIMING_OD_H,
.i = W1_GPIO_TIMING_OD_I,
.j = W1_GPIO_TIMING_OD_J,
};
static int w1_gpio_reset_bus(const struct device *dev)
{
const struct w1_gpio_config *cfg = dev->config;
const struct w1_gpio_data *data = dev->data;
const struct gpio_dt_spec *spec = &cfg->spec;
const struct w1_gpio_timing *timing = data->timing;
int ret = 0;
unsigned int key = W1_GPIO_ENTER_CRITICAL();
W1_GPIO_WAIT_US(timing->g);
ret = gpio_pin_set_dt(spec, 0);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(timing->h);
ret = gpio_pin_set_dt(spec, 1);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(timing->i);
ret = gpio_pin_get_dt(spec);
if (ret < 0) {
goto out;
}
ret ^= 0x01;
W1_GPIO_WAIT_US(timing->j);
out:
W1_GPIO_EXIT_CRITICAL(key);
return ret;
}
static int w1_gpio_read_bit(const struct device *dev)
{
const struct w1_gpio_config *cfg = dev->config;
const struct w1_gpio_data *data = dev->data;
const struct gpio_dt_spec *spec = &cfg->spec;
const struct w1_gpio_timing *timing = data->timing;
int ret = 0;
unsigned int key = W1_GPIO_ENTER_CRITICAL();
ret = gpio_pin_set_dt(spec, 0);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(timing->a);
ret = gpio_pin_set_dt(spec, 1);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(timing->e);
ret = gpio_pin_get_dt(spec);
if (ret < 0) {
goto out;
}
ret &= 0x01;
W1_GPIO_WAIT_US(timing->f);
out:
W1_GPIO_EXIT_CRITICAL(key);
return ret;
}
static int w1_gpio_write_bit(const struct device *dev, const bool bit)
{
const struct w1_gpio_config *cfg = dev->config;
const struct w1_gpio_data *data = dev->data;
const struct gpio_dt_spec *spec = &cfg->spec;
const struct w1_gpio_timing *timing = data->timing;
int ret = 0;
unsigned int key = W1_GPIO_ENTER_CRITICAL();
ret = gpio_pin_set_dt(spec, 0);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(bit ? timing->a : timing->c);
ret = gpio_pin_set_dt(spec, 1);
if (ret < 0) {
goto out;
}
W1_GPIO_WAIT_US(bit ? timing->b : timing->d);
out:
W1_GPIO_EXIT_CRITICAL(key);
return ret;
}
static int w1_gpio_read_byte(const struct device *dev)
{
int ret = 0;
int byte = 0x00;
for (int i = 0; i < 8; i++) {
ret = w1_gpio_read_bit(dev);
if (ret < 0) {
return ret;
}
byte >>= 1;
if (ret) {
byte |= 0x80;
}
}
return byte;
}
static int w1_gpio_write_byte(const struct device *dev, const uint8_t byte)
{
int ret = 0;
uint8_t write = byte;
for (int i = 0; i < 8; i++) {
ret = w1_gpio_write_bit(dev, write & 0x01);
if (ret < 0) {
return ret;
}
write >>= 1;
}
return ret;
}
static int w1_gpio_configure(const struct device *dev, enum w1_settings_type type, uint32_t value)
{
struct w1_gpio_data *data = dev->data;
switch (type) {
case W1_SETTING_SPEED:
data->overdrive_active = (value != 0);
data->timing = data->overdrive_active ? &od : &std;
return 0;
default:
return -ENOTSUP;
}
}
static int w1_gpio_init(const struct device *dev)
{
const struct w1_gpio_config *cfg = dev->config;
const struct gpio_dt_spec *spec = &cfg->spec;
struct w1_gpio_data *data = dev->data;
if (gpio_is_ready_dt(spec)) {
int ret = gpio_pin_configure_dt(spec, GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Failed to configure GPIO port %s pin %d", spec->port->name,
spec->pin);
return ret;
}
} else {
LOG_ERR("GPIO port %s is not ready", spec->port->name);
return -ENODEV;
}
data->timing = &std;
data->overdrive_active = false;
LOG_DBG("w1-gpio initialized, with %d slave devices", cfg->master_config.slave_count);
return 0;
}
static const struct w1_driver_api w1_gpio_driver_api = {
.reset_bus = w1_gpio_reset_bus,
.read_bit = w1_gpio_read_bit,
.write_bit = w1_gpio_write_bit,
.read_byte = w1_gpio_read_byte,
.write_byte = w1_gpio_write_byte,
.configure = w1_gpio_configure,
};
#define W1_ZEPHYR_GPIO_INIT(inst) \
static const struct w1_gpio_config w1_gpio_cfg_##inst = { \
.master_config.slave_count = W1_INST_SLAVE_COUNT(inst), \
.spec = GPIO_DT_SPEC_INST_GET(inst, gpios)}; \
static struct w1_gpio_data w1_gpio_data_##inst = {}; \
DEVICE_DT_INST_DEFINE(inst, &w1_gpio_init, NULL, &w1_gpio_data_##inst, \
&w1_gpio_cfg_##inst, POST_KERNEL, CONFIG_W1_INIT_PRIORITY, \
&w1_gpio_driver_api);
DT_INST_FOREACH_STATUS_OKAY(W1_ZEPHYR_GPIO_INIT)
``` | /content/code_sandbox/drivers/w1/w1_zephyr_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,349 |
```unknown
# Configuration options for the Zephyr DS2485 1-Wire master driver
config W1_DS2485
bool "DS2485 1-wire master driver"
select I2C
depends on DT_HAS_MAXIM_DS2485_ENABLED
select W1_DS2477_85_COMMON
default y
help
Enable the ds2485 w1 master driver.
``` | /content/code_sandbox/drivers/w1/Kconfig.ds2485 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# Common configuration options for DS2477 and DS2485 1-Wire master drivers
config W1_DS2477_85_COMMON
bool
help
This enables support for the shared ds2477/85 1-Wire driver.
``` | /content/code_sandbox/drivers/w1/Kconfig.ds2477_85 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_W1_DS2477_DS2485_COMMON_H_
#define ZEPHYR_DRIVERS_W1_DS2477_DS2485_COMMON_H_
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/kernel.h>
/* memory specific commands */
#define CMD_WR_MEM 0x96
#define CMD_RD_MEM 0x44
#define CMD_SET_PAGE_PROTECT 0xc3
#define CMD_RD_STATUS 0xaa
/* configuration specific commands */
#define CMD_SET_I2C_ADDR 0x75
#define CMD_RD_W1_PORT_CFG 0x52
#define CMD_WR_W1_PORT_CFG 0x99
#define CMD_MASTER_RESET 0x62
/* 1-Wire specific commands */
#define CMD_W1_SCRIPT 0x88
#define CMD_W1_BLOCK 0xab
#define CMD_RD_BLOCK 0x50
#define CMD_WR_BLOCK 0x68
#define CMD_SEARCH 0x11
#define CMD_FULL_CMD_SEQ 0x57
/* crc16 specific commands */
#define CMD_COMPUTE_CRC 0xcc
/* i2c command overhead len */
#define CMD_OVERHEAD_LEN 2U
/* memory specific commands' data length */
#define CMD_WR_MEM_LEN 33U
#define CMD_RD_MEM_LEN 1U
#define CMD_SET_PAGE_PROTECT_LEN 2U
#define CMD_RD_STATUS_LEN 1U
/* configuration specific commands */
#define CMD_SET_I2C_ADDR_LEN 1U
#define CMD_RD_W1_PORT_CFG_LEN 1U
#define CMD_WR_W1_PORT_CFG_LEN 3U
/* 1-Wire specific commands */
#define CMD_W1_SCRIPT_LEN 1U
#define CMD_W1_BLOCK_LEN 1U
#define CMD_RD_BLOCK_LEN 1U
#define CMD_WR_BLOCK_LEN 1U
#define CMD_SEARCH_LEN 2U
#define CMD_FULL_CMD_SEQ_LEN 9U
/* crc16 specific commands */
#define CMD_COMPUTE_CRC_LEN 1U
/* I2C communication result bytes */
#define DS2477_88_RES_SUCCESS 0xaa
#define DS2477_88_RES_INVALID_PARAM 0x77
#define DS2477_88_RES_COMM_FAILURE 0x22
#define DS2477_88_RES_RESET_FAILURE 0x22
#define DS2477_88_RES_NO_PRESENCE 0x33
#define DS2477_88_RES_WP_FAILURE 0x55
/* primitive commands, executable via the script command */
#define SCRIPT_OW_RESET 0x00
#define SCRIPT_OW_WRITE_BIT 0x01
#define SCRIPT_OW_READ_BIT 0x02
#define SCRIPT_OW_WRITE_BYTE 0x03
#define SCRIPT_OW_READ_BYTE 0x04
#define SCRIPT_OW_TRIPLET 0x05
#define SCRIPT_OW_OV_SKIP 0x06
#define SCRIPT_OW_SKIP 0x07
#define SCRIPT_OW_READ_BLOCK 0x08
#define SCRIPT_OW_WRITE_BLOCK 0x09
#define SCRIPT_OW_DELAY 0x0a
#define SCRIPT_OW_PRIME_SPU 0x0b
#define SCRIPT_OW_SPU_OFF 0x0c
#define SCRIPT_OW_SPEED 0x0d
/* port configuration register offsets */
#define PORT_REG_MASTER_CONFIGURATION 0x00
#define PORT_REG_STANDARD_SPEED_T_RSTL 0x01
#define PORT_REG_STANDARD_SPEED_T_MSI 0x02
#define PORT_REG_STANDARD_SPEED_T_MSP 0x03
#define PORT_REG_STANDARD_SPEED_T_RSTH 0x04
#define PORT_REG_STANDARD_SPEED_T_W0L 0x05
#define PORT_REG_STANDARD_SPEED_T_W1L 0x06
#define PORT_REG_STANDARD_SPEED_T_MSR 0x07
#define PORT_REG_STANDARD_SPEED_T_REC 0x08
#define PORT_REG_OVERDRIVE_SPEED_T_RSTL 0x09
#define PORT_REG_OVERDRIVE_SPEED_T_MSI 0x0a
#define PORT_REG_OVERDRIVE_SPEED_T_MSP 0x0b
#define PORT_REG_OVERDRIVE_SPEED_T_RSTH 0x0c
#define PORT_REG_OVERDRIVE_SPEED_T_W0L 0x0d
#define PORT_REG_OVERDRIVE_SPEED_T_W1L 0x0e
#define PORT_REG_OVERDRIVE_SPEED_T_MSR 0x0f
#define PORT_REG_OVERDRIVE_SPEED_T_REC 0x10
#define PORT_REG_RPUP_BUF 0x11
#define PORT_REG_PDSLEW 0x12
#define PORT_REG_COUNT 0x13
/* upper limit of 1-wire command length supported(in bytes) */
#define MAX_BLOCK_LEN 126U
/* limit of 1-wire command len is 126 bytes, but currently not used: */
#define SCRIPT_WR_LEN 1U
/* variant independent timing */
#define DS2477_85_T_RM_us 50000U
#define DS2477_85_T_WM_us 100000U
#define DS2477_85_T_WS_us 15000U
/* default 1-wire timing parameters (cfg. value==6) */
#define DS2477_85_STD_SPD_T_RSTL_us 560U
#define DS2477_85_STD_SPD_T_MSI_us 7U
#define DS2477_85_STD_SPD_T_MSP_us 68U
#define DS2477_85_STD_SPD_T_RSTH_us 560U
#define DS2477_85_STD_SPD_T_W0L_us 68U
#define DS2477_85_STD_SPD_T_W1L_us 8U
#define DS2477_85_STD_SPD_T_MSR_us 12U
#define DS2477_85_STD_SPD_T_REC_us 6U
#define DS2477_85_OVD_SPD_T_RSTL_us 56U
#define DS2477_85_OVD_SPD_T_MSI_us 2U
#define DS2477_85_OVD_SPD_T_MSP_us 8U
#define DS2477_85_OVD_SPD_T_RSTH_us 56U
#define DS2477_85_OVD_SPD_T_W0L_us 8U
#define DS2477_85_OVD_SPD_T_W1L_us 1U
#define DS2477_85_OVD_SPD_T_MSR_us 2U
#define DS2477_85_OVD_SPD_T_REC_us 6U
#define DS2477_85_STD_SPD_T_SLOT_us \
(DS2477_85_STD_SPD_T_W0L_us + DS2477_85_STD_SPD_T_REC_us)
#define DS2477_85_STD_SPD_T_RESET_us \
(DS2477_85_STD_SPD_T_RSTL_us + DS2477_85_STD_SPD_T_RSTH_us)
#define DS2477_85_OVD_SPD_T_SLOT_us \
(DS2477_85_OVD_SPD_T_W0L_us + DS2477_85_OVD_SPD_T_REC_us)
#define DS2477_85_OVD_SPD_T_RESET_us \
(DS2477_85_OVD_SPD_T_RSTL_us + DS2477_85_OVD_SPD_T_RSTH_us)
/* defines for DTS switching-th, active-pull-th and weak-pullup enums */
#define RPUP_BUF_CUSTOM BIT(15)
#define RPUP_BUF_SW_TH_Msk GENMASK(5, 4)
#define RPUP_BUF_SW_TH_PREP(x) FIELD_PREP(RPUP_BUF_SW_TH_Msk, x)
#define RPUP_BUF_SW_TH_LOW RPUP_BUF_SW_TH_PREP(0)
#define RPUP_BUF_SW_TH_MEDIUM RPUP_BUF_SW_TH_PREP(1)
#define RPUP_BUF_SW_TH_HIGH RPUP_BUF_SW_TH_PREP(2)
#define RPUP_BUF_SW_TH_OFF RPUP_BUF_SW_TH_PREP(3)
#define RPUP_BUF_APULL_TH_Msk GENMASK(3, 2)
#define RPUP_BUF_APULL_TH_PREP(x) FIELD_PREP(RPUP_BUF_APULL_TH_Msk, x)
#define RPUP_BUF_APULL_TH_LOW RPUP_BUF_APULL_TH_PREP(0)
#define RPUP_BUF_APULL_TH_MEDIUM RPUP_BUF_APULL_TH_PREP(1)
#define RPUP_BUF_APULL_TH_HIGH RPUP_BUF_APULL_TH_PREP(2)
#define RPUP_BUF_APULL_TH_OFF RPUP_BUF_APULL_TH_PREP(3)
#define RPUP_BUF_WPULL_Msk GENMASK(1, 0)
#define RPUP_BUF_WPULL_PREP(x) FIELD_PREP(RPUP_BUF_WPULL_Msk, x)
#define RPUP_BUF_WPULL_EXTERN RPUP_BUF_WPULL_PREP(0)
#define RPUP_BUF_WPULL_500 RPUP_BUF_WPULL_PREP(1)
#define RPUP_BUF_WPULL_1000 RPUP_BUF_WPULL_PREP(2)
#define RPUP_BUF_WPULL_333 RPUP_BUF_WPULL_PREP(3)
/* defines for standard and overdrive slew enums */
#define PDSLEW_CUSTOM BIT(15)
#define PDSLEW_STD_Msk GENMASK(5, 3)
#define PDSLEW_STD_PREP(x) FIELD_PREP(PDSLEW_STD_Msk, BIT(x))
#define PDSLEW_STD_50 PDSLEW_STD_PREP(0)
#define PDSLEW_STD_150 PDSLEW_STD_PREP(1)
#define PDSLEW_STD_1300 PDSLEW_STD_PREP(2)
#define PDSLEW_OVD_Msk GENMASK(2, 0)
#define PDSLEW_OVD_PREP(x) FIELD_PREP(PDSLEW_OVD_Msk, BIT(x))
#define PDSLEW_OVD_50 PDSLEW_OVD_PREP(0)
#define PDSLEW_OVD_150 PDSLEW_OVD_PREP(1)
/* speed mode dependent timing parameters */
struct mode_timing {
uint16_t t_slot;
uint16_t t_reset;
};
union master_config_reg {
struct {
uint16_t res : 12;
uint16_t apu : 1;
uint16_t spu : 1;
uint16_t pdn : 1;
uint16_t od_active : 1;
};
uint16_t value;
};
typedef int (*variant_w1_script_cmd_fn)(const struct device *dev,
int w1_delay_us, uint8_t w1_cmd,
const uint8_t *tx_buf,
const uint8_t tx_len, uint8_t *rx_buf,
uint8_t rx_len);
struct w1_ds2477_85_config {
/** w1 master config, common to all drivers */
struct w1_master_config master_config;
/** I2C device */
const struct i2c_dt_spec i2c_spec;
/** config reg of weak pullup, active pullup, and switch threshold */
uint16_t rpup_buf;
/** config reg of standard and overdrive slew */
uint16_t pdslew;
/** mode dependent timing parameters (@0: standard, @1: overdrive) */
struct mode_timing mode_timing[2];
/** variant dependent time of 1 operation in us */
uint16_t t_op_us;
/** variant dependent time of 1 sequence in us */
uint16_t t_seq_us;
/** variant specific script command */
variant_w1_script_cmd_fn w1_script_cmd;
/** indicates enable active pull-up configuration */
bool apu;
};
struct w1_ds2477_85_data {
/** w1 master data, common to all drivers */
struct w1_master_data master_data;
/** master specific runtime configuration */
union master_config_reg master_reg;
};
#define W1_DS2477_85_DT_CONFIG_GET(node_id, _t_op, _t_seq, _script_cmd) \
{ \
.i2c_spec = I2C_DT_SPEC_GET(node_id), \
.master_config.slave_count = \
W1_SLAVE_COUNT(node_id), \
.rpup_buf = RPUP_BUF_CUSTOM | \
RPUP_BUF_SW_TH_PREP(DT_ENUM_IDX(node_id, \
switching_threshold)) | \
RPUP_BUF_APULL_TH_PREP(DT_ENUM_IDX(node_id, \
active_pull_threshold)) | \
RPUP_BUF_WPULL_PREP(DT_ENUM_IDX(node_id, weak_pullup)),\
.pdslew = PDSLEW_CUSTOM | \
PDSLEW_STD_PREP(DT_ENUM_IDX(node_id, \
standard_slew)) | \
PDSLEW_OVD_PREP(DT_ENUM_IDX(node_id, \
overdrive_slew)), \
.apu = DT_PROP(node_id, active_pullup), \
.mode_timing = { \
{ \
.t_slot = DS2477_85_STD_SPD_T_SLOT_us, \
.t_reset = DS2477_85_STD_SPD_T_RESET_us, \
}, \
{ \
.t_slot = DS2477_85_OVD_SPD_T_SLOT_us, \
.t_reset = DS2477_85_OVD_SPD_T_RESET_us, \
}, \
}, \
.t_op_us = _t_op, \
.t_seq_us = _t_seq, \
.w1_script_cmd = _script_cmd, \
}
#define W1_DS2477_85_DT_CONFIG_INST_GET(inst, _t_op, _t_seq, _script_cmd) \
W1_DS2477_85_DT_CONFIG_GET(DT_DRV_INST(inst), _t_op, _t_seq, \
_script_cmd)
int w1_ds2477_85_init(const struct device *dev);
int ds2477_85_write_port_config(const struct device *dev, uint8_t reg,
uint16_t value);
int ds2477_85_read_port_config(const struct device *dev, uint8_t reg,
uint16_t *value);
int ds2477_85_reset_master(const struct device *dev);
int ds2477_85_reset_bus(const struct device *dev);
int ds2477_85_read_bit(const struct device *dev);
int ds2477_85_write_bit(const struct device *dev, const bool bit);
int ds2477_85_read_byte(const struct device *dev);
int ds2477_85_write_byte(const struct device *dev, const uint8_t tx_byte);
int ds2477_85_write_block(const struct device *dev, const uint8_t *buffer,
size_t tx_len);
int ds2477_85_read_block(const struct device *dev, uint8_t *buffer,
size_t rx_len);
int ds2477_85_configure(const struct device *dev, enum w1_settings_type type,
uint32_t value);
#endif /* ZEPHYR_DRIVERS_W1_DS2477_DS2485_COMMON_H_ */
``` | /content/code_sandbox/drivers/w1/w1_ds2477_85_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,255 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/sys/crc.h>
#include <zephyr/types.h>
#include <zephyr/drivers/w1.h>
int z_impl_w1_read_block(const struct device *dev, uint8_t *buffer, size_t len)
{
const struct w1_driver_api *api = dev->api;
int ret;
if (api->read_block != NULL) {
return api->read_block(dev, buffer, len);
}
for (int i = 0; i < len; ++i) {
ret = w1_read_byte(dev);
if (ret < 0) {
return ret;
}
buffer[i] = ret;
}
return 0;
}
int z_impl_w1_write_block(const struct device *dev, const uint8_t *buffer,
size_t len)
{
const struct w1_driver_api *api = dev->api;
int ret;
if (api->write_block != NULL) {
return api->write_block(dev, buffer, len);
}
for (int i = 0; i < len; ++i) {
ret = w1_write_byte(dev, buffer[i]);
if (ret < 0) {
return ret;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/w1/w1_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 276 |
```c
/*
*
*/
/**
* @brief Common functions for Maxim DS2477,DS2485 1-Wire Masters
*/
#include "w1_ds2477_85_common.h"
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
LOG_MODULE_REGISTER(w1_ds2477_85, CONFIG_W1_LOG_LEVEL);
int ds2477_85_write_port_config(const struct device *dev, uint8_t reg, uint16_t value)
{
const struct w1_ds2477_85_config *cfg = dev->config;
uint8_t buf[5] = {CMD_WR_W1_PORT_CFG, CMD_WR_W1_PORT_CFG_LEN, reg};
int ret;
__ASSERT_NO_MSG(reg <= PORT_REG_COUNT);
sys_put_le16(value, &buf[3]);
ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_WR_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN));
if (ret < 0) {
return ret;
}
k_usleep(cfg->t_op_us);
ret = i2c_read_dt(&cfg->i2c_spec, buf, 2);
if (ret < 0) {
return ret;
}
if ((buf[0] != 1) || (buf[1] != DS2477_88_RES_SUCCESS)) {
return -EIO;
}
return 0;
}
int ds2477_85_read_port_config(const struct device *dev, uint8_t reg, uint16_t *value)
{
const struct w1_ds2477_85_config *cfg = dev->config;
uint8_t buf[4] = {CMD_RD_W1_PORT_CFG, CMD_RD_W1_PORT_CFG_LEN, reg};
int ret;
__ASSERT_NO_MSG(value != NULL && reg <= PORT_REG_COUNT);
ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_RD_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN));
if (ret < 0) {
return ret;
}
k_usleep(cfg->t_op_us);
ret = i2c_read_dt(&cfg->i2c_spec, buf, 4);
if (ret < 0) {
return ret;
}
if ((buf[0] != 3) || (buf[1] != DS2477_88_RES_SUCCESS)) {
return -EIO;
}
*value = sys_get_le16(&buf[2]);
return 0;
}
int ds2477_85_reset_master(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
uint8_t buf[2] = {CMD_MASTER_RESET};
int ret;
ret = i2c_write_dt(&cfg->i2c_spec, buf, 1);
if (ret < 0) {
LOG_ERR("initiate reset failed");
return ret;
}
k_usleep(cfg->t_op_us);
ret = i2c_read_dt(&cfg->i2c_spec, buf, 2);
if (ret < 0) {
return ret;
}
if ((buf[0] != 1) || (buf[1] != DS2477_88_RES_SUCCESS)) {
return -EIO;
}
return 0;
}
int ds2477_85_reset_bus(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
uint16_t delay_us = cfg->mode_timing[data->master_reg.od_active].t_reset;
uint8_t tx_data;
uint8_t rx_data;
int ret;
tx_data = data->master_reg.od_active ? BIT(3) : BIT(7);
ret = cfg->w1_script_cmd(dev, delay_us, SCRIPT_OW_RESET, &tx_data, 1, &rx_data, 1);
switch (ret) {
case DS2477_88_RES_COMM_FAILURE:
/* presence not detected */
return 0;
case DS2477_88_RES_SUCCESS:
/* at least 1 device present */
return 1;
default:
return -EIO;
}
}
int ds2477_85_read_bit(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
uint16_t delay_us = cfg->mode_timing[data->master_reg.od_active].t_slot;
uint8_t rx_data;
int ret;
ret = cfg->w1_script_cmd(dev, delay_us, SCRIPT_OW_READ_BIT, NULL, 0, &rx_data, 1);
if (ret != DS2477_88_RES_SUCCESS) {
return -EIO;
}
return (rx_data & BIT(5)) ? 1 : 0;
}
int ds2477_85_write_bit(const struct device *dev, const bool bit)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
uint16_t delay_us = cfg->mode_timing[data->master_reg.od_active].t_slot;
uint8_t tx_data = (uint8_t)bit;
uint8_t rx_data;
int ret;
ret = cfg->w1_script_cmd(dev, delay_us, SCRIPT_OW_WRITE_BIT, &tx_data, 1, &rx_data, 1);
if (ret != DS2477_88_RES_SUCCESS) {
return -EIO;
}
return 0;
}
int ds2477_85_read_byte(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
uint16_t delay_us = cfg->mode_timing[data->master_reg.od_active].t_slot * 8;
uint8_t rx_data;
int ret;
ret = cfg->w1_script_cmd(dev, delay_us, SCRIPT_OW_READ_BYTE, NULL, 0, &rx_data, 1);
if (ret != DS2477_88_RES_SUCCESS) {
return -EIO;
}
return rx_data;
}
int ds2477_85_write_byte(const struct device *dev, const uint8_t tx_byte)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
uint16_t delay_us = cfg->mode_timing[data->master_reg.od_active].t_slot * 8;
uint8_t rx_data;
int ret;
ret = cfg->w1_script_cmd(dev, delay_us, SCRIPT_OW_WRITE_BYTE, &tx_byte, 1, &rx_data, 1);
if (ret != DS2477_88_RES_SUCCESS) {
return -EIO;
}
return 0;
}
int ds2477_85_write_block(const struct device *dev, const uint8_t *buffer, size_t tx_len)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
int w1_timing = cfg->mode_timing[data->master_reg.od_active].t_slot * 8 * tx_len;
uint8_t buf[3] = {CMD_WR_BLOCK, (tx_len + CMD_WR_BLOCK_LEN), 0};
struct i2c_msg tx_msg[2] = {
{.buf = buf, .len = (CMD_WR_BLOCK_LEN + CMD_OVERHEAD_LEN), .flags = I2C_MSG_WRITE},
{.buf = (uint8_t *)buffer, .len = tx_len, .flags = (I2C_MSG_WRITE | I2C_MSG_STOP)},
};
int ret;
__ASSERT_NO_MSG(tx_len <= MAX_BLOCK_LEN);
if (tx_len == 0) {
return 0;
}
ret = i2c_transfer_dt(&cfg->i2c_spec, tx_msg, 2);
if (ret < 0) {
LOG_ERR("write block fail: %x", ret);
return ret;
}
k_usleep(cfg->t_op_us + (cfg->t_seq_us * tx_len) + w1_timing);
ret = i2c_read_dt(&cfg->i2c_spec, buf, 2);
if (ret < 0) {
return ret;
}
if ((buf[0] != 1) || (buf[1] != DS2477_88_RES_SUCCESS)) {
return -EIO;
}
return 0;
}
int ds2477_85_read_block(const struct device *dev, uint8_t *buffer, size_t rx_len)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
int w1_timing = cfg->mode_timing[data->master_reg.od_active].t_slot * 8 * rx_len;
uint8_t buf[3] = {CMD_RD_BLOCK, CMD_RD_BLOCK_LEN, rx_len};
struct i2c_msg rx_msg[2] = {
{.buf = buf, .len = 2, .flags = I2C_MSG_READ},
{.buf = buffer, .len = rx_len, .flags = (I2C_MSG_READ | I2C_MSG_STOP)}
};
int ret;
__ASSERT_NO_MSG(rx_len <= MAX_BLOCK_LEN);
if (rx_len == 0) {
return 0;
}
ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_RD_BLOCK_LEN + CMD_OVERHEAD_LEN));
if (ret < 0) {
LOG_ERR("read block fail: %x", ret);
return ret;
}
k_usleep(cfg->t_op_us + (cfg->t_seq_us * rx_len) + w1_timing);
ret = i2c_transfer_dt(&cfg->i2c_spec, rx_msg, 2);
if (ret < 0) {
return ret;
}
if (buf[1] != DS2477_88_RES_SUCCESS) {
return -EIO;
}
return 0;
}
int ds2477_85_configure(const struct device *dev, enum w1_settings_type type, uint32_t value)
{
struct w1_ds2477_85_data *data = dev->data;
switch (type) {
case W1_SETTING_SPEED:
__ASSERT_NO_MSG(value <= 1);
data->master_reg.od_active = value;
break;
default:
return -EINVAL;
}
return ds2477_85_write_port_config(dev, PORT_REG_MASTER_CONFIGURATION,
data->master_reg.value);
}
int w1_ds2477_85_init(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
struct w1_ds2477_85_data *data = dev->data;
data->master_reg.apu = cfg->apu;
if (ds2477_85_write_port_config(dev, PORT_REG_MASTER_CONFIGURATION,
data->master_reg.value) < 0) {
return -EIO;
}
if (ds2477_85_write_port_config(dev, PORT_REG_RPUP_BUF, cfg->rpup_buf) < 0) {
return -EIO;
}
if (ds2477_85_write_port_config(dev, PORT_REG_PDSLEW, cfg->pdslew) < 0) {
return -EIO;
}
LOG_DBG("cfg: rpup_buf=%02x, pdslew:%02x", cfg->rpup_buf, cfg->pdslew);
/* RPUP/BUF configuration is applied after a bus reset */
(void)ds2477_85_reset_bus(dev);
LOG_DBG("w1-ds2477/85 init; %d slave devices",
cfg->master_config.slave_count);
return 0;
}
``` | /content/code_sandbox/drivers/w1/w1_ds2477_85_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,575 |
```c
/*
*
*/
#define DT_DRV_COMPAT maxim_ds2485
/**
* @brief Driver for the Maxim ds2485 1-Wire Master
*/
#include "w1_ds2477_85_common.h"
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(w1_ds2485, CONFIG_W1_LOG_LEVEL);
/* upper limits; guaranteed over operating temperature range */
#define DS2485_T_OSCWUP_us 1000U
#define DS2485_T_OP_us 400U
#define DS2485_T_SEQ_us 10U
int ds2485_w1_script_cmd(const struct device *dev, int w1_delay_us, uint8_t w1_cmd,
const uint8_t *tx_buf, const uint8_t tx_len,
uint8_t *rx_buf, uint8_t rx_len)
{
const struct w1_ds2477_85_config *cfg = dev->config;
uint8_t i2c_len = 3 + tx_len;
uint8_t tx_bytes[3 + SCRIPT_WR_LEN] = {
CMD_W1_SCRIPT, tx_len + CMD_W1_SCRIPT_LEN, w1_cmd
};
uint8_t rx_bytes[3];
struct i2c_msg rx_msg[2] = {
{
.buf = rx_bytes,
.len = (CMD_W1_SCRIPT_LEN + CMD_OVERHEAD_LEN),
.flags = I2C_MSG_READ,
},
{
.buf = rx_buf,
.len = rx_len,
.flags = (I2C_MSG_READ | I2C_MSG_STOP),
},
};
int ret;
__ASSERT_NO_MSG(tx_len <= SCRIPT_WR_LEN);
memcpy(&tx_bytes[3], tx_buf, tx_len);
ret = i2c_write_dt(&cfg->i2c_spec, tx_bytes, i2c_len);
if (ret < 0) {
return ret;
}
k_usleep(DS2485_T_OP_us + DS2485_T_SEQ_us + w1_delay_us);
ret = i2c_transfer_dt(&cfg->i2c_spec, rx_msg, 2);
if (ret < 0) {
LOG_ERR("scripts_cmd fail: ret: %x", ret);
return ret;
}
if ((rx_bytes[0] != (rx_len + 2)) || (rx_bytes[2] != w1_cmd)) {
LOG_ERR("scripts_cmd fail: response: %x,%x:",
rx_bytes[0], rx_bytes[2]);
return -EIO;
}
return rx_bytes[1];
}
static int w1_ds2485_init(const struct device *dev)
{
const struct w1_ds2477_85_config *cfg = dev->config;
if (!device_is_ready(cfg->i2c_spec.bus)) {
LOG_ERR("%s is not ready", cfg->i2c_spec.bus->name);
return -ENODEV;
}
if (ds2477_85_reset_master(dev)) {
return -EIO;
}
k_usleep(DS2485_T_OSCWUP_us);
return w1_ds2477_85_init(dev);
}
static const struct w1_driver_api w1_ds2485_driver_api = {
.reset_bus = ds2477_85_reset_bus,
.read_bit = ds2477_85_read_bit,
.write_bit = ds2477_85_write_bit,
.read_byte = ds2477_85_read_byte,
.write_byte = ds2477_85_write_byte,
.read_block = ds2477_85_read_block,
.write_block = ds2477_85_write_block,
.configure = ds2477_85_configure,
};
#define W1_DS2485_INIT(inst) \
static const struct w1_ds2477_85_config w1_ds2477_85_cfg_##inst = \
W1_DS2477_85_DT_CONFIG_INST_GET(inst, DS2485_T_OP_us, \
DS2485_T_SEQ_us, \
ds2485_w1_script_cmd); \
\
static struct w1_ds2477_85_data w1_ds2477_85_data_##inst = {}; \
DEVICE_DT_INST_DEFINE(inst, &w1_ds2485_init, NULL, \
&w1_ds2477_85_data_##inst, \
&w1_ds2477_85_cfg_##inst, POST_KERNEL, \
CONFIG_W1_INIT_PRIORITY, &w1_ds2485_driver_api);
DT_INST_FOREACH_STATUS_OKAY(W1_DS2485_INIT)
``` | /content/code_sandbox/drivers/w1/w1_ds2485.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 994 |
```c
/*
*
*/
#include "w1_ds2482_84_common.h"
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#define DT_DRV_COMPAT maxim_ds2484
LOG_MODULE_REGISTER(ds2484, CONFIG_W1_LOG_LEVEL);
struct ds2484_config {
struct w1_master_config w1_config;
const struct i2c_dt_spec i2c_spec;
const struct gpio_dt_spec slpz_spec;
bool apu;
};
struct ds2484_data {
struct w1_master_data w1_data;
uint8_t reg_device_config;
};
static int ds2484_reset_bus(const struct device *dev)
{
const struct ds2484_config *config = dev->config;
return ds2482_84_reset_bus(&config->i2c_spec);
}
static int ds2484_read_bit(const struct device *dev)
{
const struct ds2484_config *config = dev->config;
return ds2482_84_read_bit(&config->i2c_spec);
}
static int ds2484_write_bit(const struct device *dev, bool bit)
{
const struct ds2484_config *config = dev->config;
return ds2482_84_write_bit(&config->i2c_spec, bit);
}
static int ds2484_read_byte(const struct device *dev)
{
const struct ds2484_config *config = dev->config;
return ds2482_84_read_byte(&config->i2c_spec);
}
static int ds2484_write_byte(const struct device *dev, uint8_t byte)
{
const struct ds2484_config *config = dev->config;
return ds2482_84_write_byte(&config->i2c_spec, byte);
}
static int ds2484_configure(const struct device *dev, enum w1_settings_type type, uint32_t value)
{
const struct ds2484_config *config = dev->config;
struct ds2484_data *data = dev->data;
switch (type) {
case W1_SETTING_SPEED:
WRITE_BIT(data->reg_device_config, DEVICE_1WS_pos, value);
break;
case W1_SETTING_STRONG_PULLUP:
WRITE_BIT(data->reg_device_config, DEVICE_SPU_pos, value);
break;
default:
return -EINVAL;
}
return ds2482_84_write_config(&config->i2c_spec, data->reg_device_config);
}
#ifdef CONFIG_PM_DEVICE
static int ds2484_pm_control(const struct device *dev, enum pm_device_action action)
{
const struct ds2484_config *config = dev->config;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
if (!config->slpz_spec.port) {
return -ENOTSUP;
}
return gpio_pin_set_dt(&config->slpz_spec, 1);
case PM_DEVICE_ACTION_RESUME:
if (!config->slpz_spec.port) {
return -ENOTSUP;
}
return gpio_pin_set_dt(&config->slpz_spec, 0);
default:
return -ENOTSUP;
};
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static int ds2484_init(const struct device *dev)
{
int ret;
const struct ds2484_config *config = dev->config;
struct ds2484_data *data = dev->data;
if (config->slpz_spec.port) {
if (!gpio_is_ready_dt(&config->slpz_spec)) {
LOG_ERR("Port (SLPZ) not ready");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->slpz_spec, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
LOG_ERR("Pin configuration (SLPZ) failed: %d", ret);
return ret;
}
}
if (!device_is_ready(config->i2c_spec.bus)) {
return -ENODEV;
}
ret = ds2482_84_reset_device(&config->i2c_spec);
if (ret < 0) {
LOG_ERR("Device reset failed: %d", ret);
return ret;
}
WRITE_BIT(data->reg_device_config, DEVICE_APU_pos, config->apu);
ret = ds2482_84_write_config(&config->i2c_spec, data->reg_device_config);
if (ret < 0) {
LOG_ERR("Device config update failed: %d", ret);
return ret;
}
return 0;
}
static const struct w1_driver_api ds2484_driver_api = {
.reset_bus = ds2484_reset_bus,
.read_bit = ds2484_read_bit,
.write_bit = ds2484_write_bit,
.read_byte = ds2484_read_byte,
.write_byte = ds2484_write_byte,
.configure = ds2484_configure,
};
#define DS2484_INIT(inst) \
static const struct ds2484_config inst_##inst##_config = { \
.w1_config.slave_count = W1_INST_SLAVE_COUNT(inst), \
.i2c_spec = I2C_DT_SPEC_INST_GET(inst), \
.slpz_spec = GPIO_DT_SPEC_INST_GET_OR(inst, slpz_gpios, {0}), \
.apu = DT_INST_PROP(inst, active_pullup), \
}; \
static struct ds2484_data inst_##inst##_data; \
PM_DEVICE_DT_INST_DEFINE(inst, ds2484_pm_control); \
DEVICE_DT_INST_DEFINE(inst, ds2484_init, PM_DEVICE_DT_INST_GET(inst), &inst_##inst##_data, \
&inst_##inst##_config, POST_KERNEL, CONFIG_W1_INIT_PRIORITY, \
&ds2484_driver_api);
DT_INST_FOREACH_STATUS_OKAY(DS2484_INIT)
/*
* Make sure that this driver is not initialized before the i2c bus is available
*/
BUILD_ASSERT(CONFIG_W1_INIT_PRIORITY > CONFIG_I2C_INIT_PRIORITY);
``` | /content/code_sandbox/drivers/w1/w1_ds2484.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,292 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_W1_W1_DS2482_800_H_
#define ZEPHYR_DRIVERS_W1_W1_DS2482_800_H_
#include <zephyr/drivers/i2c.h>
int ds2482_change_bus_lock_impl(const struct device *dev, bool lock);
#endif /* ZEPHYR_DRIVERS_W1_W1_DS2482_800_H_ */
``` | /content/code_sandbox/drivers/w1/w1_ds2482-800.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
config W1_DS2482_800
bool "DS2482-800, 8-Channel 1-Wire Master"
select I2C
depends on DT_HAS_MAXIM_DS2482_800_ENABLED
default y
``` | /content/code_sandbox/drivers/w1/Kconfig.ds2482-800 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_w1_serial
/**
* @brief 1-Wire Bus Master driver using Zephyr serial interface.
*
* This driver implements the 1-Wire interface using an uart.
* The driver uses a uart peripheral with a baudrate of 115.2 kBd to send
* and receive data bits and a baurade of 9.6 kBd for slave reset and
* presence detection as suggested for normal speed operating mode in:
* path_to_url
* For overdrive speed communication baudrates of 1 MBd and 115.2 kBd
* are used, respectively.
*/
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/w1.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/__assert.h>
LOG_MODULE_REGISTER(w1_serial, CONFIG_W1_LOG_LEVEL);
#define W1_SERIAL_READ_REQ_BYTE 0xFF
#define W1_SERIAL_BIT_1 0xFF
#define W1_SERIAL_BIT_0 0x00
/* Standard speed signal parameters:
* RST: t_RSTL=520us; t_slot=1041us
* DATA: t_low1=8.68us; t_low0=78.1us; t_slot=86.8us
*/
#define W1_SERIAL_STD_RESET_BYTE 0xF0
#define W1_SERIAL_STD_RESET_BAUD 9600u
#define W1_SERIAL_STD_DATA_BAUD 115200u
/*
* Overdrive speed signal parameters:
* RST: t_RSTL=52.1us; t_slot=86.8us
* DATA: t_low1=1.0us; t_low0=9.0us; t_slot=10.0us
*/
#define W1_SERIAL_OD_RESET_BYTE 0xE0
#define W1_SERIAL_OD_RESET_BAUD 115200u
#define W1_SERIAL_OD_DATA_BAUD 1000000u
struct w1_serial_config {
/** w1 master config, common to all drivers */
struct w1_master_config master_config;
/** UART device used for 1-Wire communication */
const struct device *uart_dev;
};
struct w1_serial_data {
/** w1 master data, common to all drivers */
struct w1_master_data master_data;
struct uart_config uart_cfg;
bool overdrive_active;
};
/*
* Concurrently transmits and receives one 1-Wire bit
* by sending and receiving one uart byte
*/
static int serial_tx_rx(const struct device *dev, const uint8_t *tx_data,
uint8_t *rx_data, size_t len, uint32_t timeout)
{
const struct w1_serial_config *cfg = dev->config;
k_timepoint_t end;
uint8_t dummy;
int ret = 0;
__ASSERT_NO_MSG(tx_data != NULL);
__ASSERT_NO_MSG(rx_data != NULL);
for (int i = 0; i < len; ++i) {
while (uart_poll_in(cfg->uart_dev, &dummy) == 0) {
/* poll in any buffered data */
}
uart_poll_out(cfg->uart_dev, tx_data[i]);
end = sys_timepoint_calc(K_USEC(timeout));
do {
ret = uart_poll_in(cfg->uart_dev, &rx_data[i]);
} while (ret != 0 && !sys_timepoint_expired(end));
}
return ret;
}
/* Concurretly tranmits and receives one 1-Wire byte */
static int serial_tx_rx_byte(const struct device *dev, uint8_t tx_byte,
uint8_t *rx_byte)
{
__ASSERT_NO_MSG(rx_byte != NULL);
uint8_t byte_representation[8];
for (int i = 0; i < 8; ++i) {
/*
* Transmitting 0xFF the uart start bit pulls the line low to
* indicate either write Bit 1, or read low time.
* Write Bit 0 is represented as 0x00
*/
byte_representation[i] =
((tx_byte & (1 << i)) != 0) ? W1_SERIAL_BIT_1 : W1_SERIAL_BIT_0;
}
if (serial_tx_rx(dev, &byte_representation[0], &byte_representation[0],
8, CONFIG_W1_ZEPHYR_SERIAL_BIT_TIMEOUT) < 0) {
return -EIO;
}
*rx_byte = 0;
for (int i = 0; i < 8; ++i) {
/*
* rx-byte different from 0xFF indicates that a slave has
* pulled line low to transmit a 0 bit, otherwise a 1 bit.
*/
*rx_byte |= (uint8_t)(byte_representation[i] == 0xFF) << i;
}
return 0;
}
static int w1_serial_reset_bus(const struct device *dev)
{
const struct w1_serial_config *cfg = dev->config;
struct w1_serial_data *data = dev->data;
uint8_t reset_byte = data->overdrive_active ?
W1_SERIAL_OD_RESET_BYTE : W1_SERIAL_STD_RESET_BYTE;
/* reset uses 115200/9600=12 slower baudrate,
* adjust timeout accordingly, also valid for overdrive speed.
*/
const uint32_t reset_timeout = CONFIG_W1_ZEPHYR_SERIAL_BIT_TIMEOUT * 12;
data->uart_cfg.baudrate = data->overdrive_active ?
W1_SERIAL_OD_RESET_BAUD : W1_SERIAL_STD_RESET_BAUD;
if (uart_configure(cfg->uart_dev, &data->uart_cfg) != 0) {
LOG_ERR("Failed set baud rate for reset pulse");
return -EIO;
}
if (serial_tx_rx(dev, &reset_byte, &reset_byte, 1, reset_timeout) < 0) {
LOG_ERR("tx_rx_error reset_present");
return -EIO;
}
data->uart_cfg.baudrate = data->overdrive_active ?
W1_SERIAL_OD_DATA_BAUD : W1_SERIAL_STD_DATA_BAUD;
if (uart_configure(cfg->uart_dev, &data->uart_cfg) != 0) {
LOG_ERR("Failed set baud rate for data transfer");
return -EIO;
}
/* At least 1 device is present on bus, if reset_byte is different
* from 0xF0. But Bus probably shorted if reset_byte is 0x00.
*/
return (reset_byte != W1_SERIAL_STD_RESET_BYTE) && (reset_byte != 0x00);
}
static int w1_serial_read_bit(const struct device *dev)
{
uint8_t tx_bit = W1_SERIAL_READ_REQ_BYTE;
uint8_t rx_bit;
if (serial_tx_rx(dev, &tx_bit, &rx_bit, 1,
CONFIG_W1_ZEPHYR_SERIAL_BIT_TIMEOUT) != 0) {
return -EIO;
};
return rx_bit == W1_SERIAL_READ_REQ_BYTE;
}
static int w1_serial_write_bit(const struct device *dev, const bool bit)
{
uint8_t tx_bit;
uint8_t rx_bit;
tx_bit = bit ? W1_SERIAL_BIT_1 : W1_SERIAL_BIT_0;
if (serial_tx_rx(dev, &tx_bit, &rx_bit, 1,
CONFIG_W1_ZEPHYR_SERIAL_BIT_TIMEOUT) != 0) {
return -EIO;
}
return 0;
}
static int w1_serial_read_byte(const struct device *dev)
{
uint8_t tx_byte = 0xFF;
uint8_t rx_byte;
if (serial_tx_rx_byte(dev, tx_byte, &rx_byte) != 0) {
return -EIO;
}
return rx_byte;
}
static int w1_serial_write_byte(const struct device *dev, const uint8_t byte)
{
uint8_t rx_byte;
return serial_tx_rx_byte(dev, byte, &rx_byte);
}
static int w1_serial_configure(const struct device *dev,
enum w1_settings_type type, uint32_t value)
{
const struct w1_serial_config *cfg = dev->config;
struct w1_serial_data *data = dev->data;
int ret = 0;
bool temp;
switch (type) {
case W1_SETTING_SPEED:
temp = (bool)value;
if (temp == data->overdrive_active) {
break;
}
data->overdrive_active = temp;
data->uart_cfg.baudrate = data->overdrive_active ?
W1_SERIAL_OD_DATA_BAUD : W1_SERIAL_STD_DATA_BAUD;
if (uart_configure(cfg->uart_dev, &data->uart_cfg) != 0) {
LOG_ERR("Failed set baud rate for data transfer");
ret = -EIO;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
static int w1_serial_init(const struct device *dev)
{
const struct w1_serial_config *cfg = dev->config;
struct w1_serial_data *data = dev->data;
if (!device_is_ready(cfg->uart_dev)) {
LOG_ERR("Serial device not ready");
return -ENODEV;
}
data->uart_cfg.baudrate = W1_SERIAL_STD_DATA_BAUD;
data->uart_cfg.parity = UART_CFG_PARITY_NONE;
data->uart_cfg.data_bits = UART_CFG_DATA_BITS_8;
data->uart_cfg.stop_bits = UART_CFG_STOP_BITS_1;
data->uart_cfg.flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
if (uart_configure(cfg->uart_dev, &data->uart_cfg) != 0) {
LOG_ERR("Failed to configure UART");
return -EINVAL;
}
data->overdrive_active = false;
LOG_DBG("w1-serial initialized, with %d slave devices",
cfg->master_config.slave_count);
return 0;
}
static const struct w1_driver_api w1_serial_driver_api = {
.reset_bus = w1_serial_reset_bus,
.read_bit = w1_serial_read_bit,
.write_bit = w1_serial_write_bit,
.read_byte = w1_serial_read_byte,
.write_byte = w1_serial_write_byte,
.configure = w1_serial_configure,
};
#define W1_ZEPHYR_SERIAL_INIT(inst) \
static const struct w1_serial_config w1_serial_cfg_##inst = { \
.uart_dev = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.master_config.slave_count = W1_INST_SLAVE_COUNT(inst) \
}; \
static struct w1_serial_data w1_serial_data_##inst = {}; \
DEVICE_DT_INST_DEFINE(inst, &w1_serial_init, NULL, &w1_serial_data_##inst, \
&w1_serial_cfg_##inst, POST_KERNEL, \
CONFIG_W1_INIT_PRIORITY, &w1_serial_driver_api); \
DT_INST_FOREACH_STATUS_OKAY(W1_ZEPHYR_SERIAL_INIT)
``` | /content/code_sandbox/drivers/w1/w1_zephyr_serial.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,334 |
```unknown
config W1_DS2484
bool "DS2484 Single-Channel 1-Wire Master"
select I2C
depends on DT_HAS_MAXIM_DS2484_ENABLED
default y
``` | /content/code_sandbox/drivers/w1/Kconfig.ds2484 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
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