text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
config CLOCK_CONTROL_RENESAS_RA_CGC
bool "RA CGC driver"
default y
depends on SOC_FAMILY_RENESAS_RA
depends on HAS_RENESAS_RA_FSP
help
Enable support for Renesas RA CGC driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.renesas_ra_cgc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# Fixed clock control driver config
config CLOCK_CONTROL_FIXED_RATE_CLOCK
bool "Fixed Clock Clock Control"
default n
help
Enable driver for devicetree defined fixed clocks.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.fixed | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```c
/*
*
*/
#include <zephyr/drivers/sensor.h>
#include <zephyr/drivers/clock_control.h>
#include "nrf_clock_calibration.h"
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <nrfx_clock.h>
#include <zephyr/logging/log.h>
#include <stdlib.h>
LOG_MODULE_DECLARE(clock_control, CONFIG_CLOCK_CONTROL_L... | /content/code_sandbox/drivers/clock_control/nrf_clock_calibration.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,805 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_ccm
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/imx_ccm.h>
#include <fsl_clock.h>
#if defined(CONFIG_SOC_MIMX8QM6_ADSP) || defined(CONFIG_SOC_MIMX8QX6_ADSP)
#inclu... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_ccm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,174 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc_syscon
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <soc.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(cloc... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_syscon.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,335 |
```c
/*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_system.h>
#include <stm32_ll_utils.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/dr... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,110 |
```c
/*
*
*/
#define DT_DRV_COMPAT aspeed_ast10x0_clock
#include <errno.h>
#include <zephyr/dt-bindings/clock/ast10x0_clock.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/sys/util.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LO... | /content/code_sandbox/drivers/clock_control/clock_control_ast10x0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,385 |
```unknown
# STM32 MCU clock control driver config
menuconfig CLOCK_CONTROL_STM32_CUBE
bool "STM32 Reset & Clock Control"
depends on SOC_FAMILY_STM32
select USE_STM32_LL_UTILS
select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X || \
SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_... | /content/code_sandbox/drivers/clock_control/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,730 |
```objective-c
/*
*
*/
#ifndef LITEX_MMCM_H
#define LITEX_MMCM_H
#include <zephyr/types.h>
/* Common values */
#define PICOS_IN_SEC 1000000000000
#define BITS_PER_BYTE 8
/* MMCM specific numbers */
#define CLKOUT_MAX 7
#define DELAY_TIME_MAX 63
#define PHASE_MUX_MAX 7
#define HIGH_LOW_TIME_REG_MAX 63
#define... | /content/code_sandbox/drivers/clock_control/clock_control_litex.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,333 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control/clock_control_adsp.h>
#include <zephyr/drivers/clock_control.h>
static int cavs_clock_ctrl_set_rate(const struct device *clk,
clock_control_subsys_t sys,
clock_control_subsys_rate_t rate)
{
uint32_t freq_idx = (uint32_t)r... | /content/code_sandbox/drivers/clock_control/clock_control_adsp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clo... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_h5.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,639 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_STM32_LL_MCO_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_STM32_LL_MCO_H_
#include <stm32_ll_utils.h>
#if CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK
#define MCO1_SOURCE LL_RCC_MCO1SOURCE_NOCLOCK
#elif CONFIG_CLOCK_STM32_MCO1_SRC_EXT_HSE
#define MCO1_SO... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_mco.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,240 |
```unknown
config CLOCK_CONTROL_NXP_S32
bool "NXP S32 clock control driver"
default y
depends on DT_HAS_NXP_S32_CLOCK_ENABLED
help
Enable support for NXP S32 clock control driver.
if CLOCK_CONTROL_NXP_S32
config CLOCK_CONTROL_NXP_S32_CLOCK_CONFIG_IDX
int
default 0
help
This option specifies the zero-bas... | /content/code_sandbox/drivers/clock_control/Kconfig.nxp_s32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defi... | /content/code_sandbox/drivers/clock_control/clock_stm32l0_l1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 697 |
```unknown
config CLOCK_CONTROL_MAX32
bool "MAX32 Clock Control Driver"
default y
depends on DT_HAS_ADI_MAX32_GCR_ENABLED
help
Enable clock control support for Analog Devices MAX32xxx/MAX78xxx SoC series.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.max32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
#define DT_DRV_COMPAT espressif_esp32_rtc
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#if defined(CONFIG_SOC_SERIES_ESP32)
#define DT_CPU_COMPAT espressif_xtensa_lx6
#undef CPU_RESET_REASON
#define CPU_RESET_REASON SW_CPU_RESET
#include <zephyr/dt-bindings/clock/esp32_clock.h>
#include <esp32/rom/rtc.h>... | /content/code_sandbox/drivers/clock_control/clock_control_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,121 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
/**
* @brief Activate default clo... | /content/code_sandbox/drivers/clock_control/clock_stm32c0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 124 |
```unknown
# Clock controller driver configuration options
config CLOCK_CONTROL_NRF_FORCE_ALT
bool
depends on SOC_COMPATIBLE_NRF
help
This option can be enabled to force an alternative implementation
of the clock control driver.
menuconfig CLOCK_CONTROL_NRF
bool "NRF Clock controller support"
default y
d... | /content/code_sandbox/drivers/clock_control/Kconfig.nrf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,352 |
```unknown
config CLOCK_CONTROL_NRF_AUXPLL
bool "nRF Auxiliary PLL driver"
default y
depends on DT_HAS_NORDIC_NRF_AUXPLL_ENABLED
help
Driver for nRF Auxiliary PLL.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.nrf_auxpll | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
#include <stdint.h>
#include <zephyr/device.h>
#include <stm32_ll_utils.h>
/* Macros to fill up multiplication and division factors values */
#define z_pllm(v) LL_RCC_PLLM_DIV_ ... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 399 |
```unknown
# ESP32 Clock Driver configuration options
config CLOCK_CONTROL_ESP32
bool "ESP32 Clock driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_RTC_ENABLED
help
Enable support for ESP32 clock driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*
*/
#define DT_DRV_COMPAT pwm_clock
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#... | /content/code_sandbox/drivers/clock_control/clock_control_pwm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,057 |
```unknown
config CLOCK_CONTROL_RENESAS_RA
bool "Renesas RA series clock generation circuit driver"
default y
depends on DT_HAS_RENESAS_RA_CLOCK_GENERATION_CIRCUIT_ENABLED
help
Enable Renesas RA series clock generation circuit driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.renesas_ra | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Clock control driver for Infineon CAT1 MCU family.
*/
#include <zephyr/drivers/clock_control.h>
#include <cyhal_clock.h>
#include <cyhal_utils.h>
#include <cyhal_clock_impl.h>
#define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_B... | /content/code_sandbox/drivers/clock_control/clock_control_ifx_cat1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,044 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_nrf_auxpll
#include <errno.h>
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/toolchain.h>
#include <... | /content/code_sandbox/drivers/clock_control/clock_control_nrf_auxpll.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,187 |
```c
/*
*
*/
#include <assert.h>
#include <soc.h>
#include <zephyr/sys/onoff.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/smartbond_clock_control.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <da1469x_clock.h>
#include <da1469x_qspic.h>
#if defined(C... | /content/code_sandbox/drivers/clock_control/clock_control_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,509 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include "clock_control_renesas_cpg_mssr.h"
#include <stdlib.h>
#define LOG_LEVEL CONFIG_CLOCK_C... | /content/code_sandbox/drivers/clock_control/clock_control_renesas_cpg_mssr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,217 |
```c
/*
*
*
*/
#include <zephyr/drivers/clock_control.h>
#define DT_DRV_COMPAT fixed_clock
struct fixed_rate_clock_config {
uint32_t rate;
};
static int fixed_rate_clk_on(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
ARG_UNUSED(sys);
return 0;
}
static int fixed_rate_clk_... | /content/code_sandbox/drivers/clock_control/clock_control_fixed_rate.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 392 |
```unknown
# Intel cAVS clock control driver
config CLOCK_CONTROL_ADSP
bool "Intel CAVS clock control"
default y
depends on DT_HAS_INTEL_ADSP_SHIM_CLKCTL_ENABLED
select ADSP_CLOCK
help
Driver for the CAVS clocks. Allow type of clock (and
thus frequency) to be chosen.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.cavs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
# NuMaker clock controller driver configuration options
config CLOCK_CONTROL_NUMAKER_SCC
bool "NuMaker system clock controller driver"
default y
depends on DT_HAS_NUVOTON_NUMAKER_SCC_ENABLED
help
Enable support for NuMaker system clock controller driver
``` | /content/code_sandbox/drivers/clock_control/Kconfig.numaker | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
config CLOCK_CONTROL_RCAR_CPG_MSSR
bool "RCar CPG MSSR driver"
default y
depends on SOC_FAMILY_RENESAS_RCAR
help
Enable support for Renesas RCar CPG MSSR driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.rcar | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config CLOCK_CONTROL_AGILEX5
bool "Agilex5 SoCFPGA clock control driver"
default y
depends on DT_HAS_INTEL_AGILEX5_CLOCK_ENABLED
help
This option enables the clock driver for Intel Agilex5 SoCFPGA SOC.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.agilex5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```c
/*
*
* Based on clock_control_mcux_sim.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_kinetis_mcg
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
#include <soc.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_mcg.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 394 |
```c
/*
*
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
*
*/
#define DT_DRV_COMPAT renesas_r8a7795_cpg_mssr
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
#include <zephyr/dt-bi... | /content/code_sandbox/drivers/clock_control/clock_control_r8a7795_cpg_mssr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,081 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clo... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_u5.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,928 |
```c
/*
*
*/
#include <string.h>
#define DT_DRV_COMPAT renesas_ra_clock_generation_circuit
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/dt-bindings/clock/renesas-ra-cgc.h>
#if DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, pll))
#define SYSCLK... | /content/code_sandbox/drivers/clock_control/clock_control_renesas_ra.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,659 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <socfpga_system_manager.h>
#include "clock_control_agilex5_ll.h"
LOG_MODULE_REGISTER(clock_control_agilex5_ll, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
/* Clock manager individual group base addresses. */
struct clock_agilex5_ll_params {
mm... | /content/code_sandbox/drivers/clock_control/clock_control_agilex5_ll.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,397 |
```unknown
# MCUXpresso SDK CCM
config CLOCK_CONTROL_MCUX_CCM_REV2
bool "MCUX CCM Rev 2 driver"
default y
depends on DT_HAS_NXP_IMX_CCM_REV2_ENABLED
help
Enable support for mcux ccm rev 2 driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_ccm_rev2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```c
/*
*
* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
*
*/
#define DT_DRV_COMPAT renesas_r8a779f0_cpg_mssr
#include <errno.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/cloc... | /content/code_sandbox/drivers/clock_control/clock_control_r8a779f0_cpg_mssr.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,892 |
```c
/*
*
*/
#define DT_DRV_COMPAT arm_beetle_syscon
/**
* @file
* @brief Driver for Clock Control of Beetle MCUs.
*
* This file contains the Clock Control driver implementation for the
* Beetle MCUs.
*/
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <zephyr/sys/u... | /content/code_sandbox/drivers/clock_control/beetle_clock_control.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,675 |
```c
/*
*
*/
#include <string.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys)... | /content/code_sandbox/drivers/clock_control/clock_control_renesas_ra_cgc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 702 |
```c
/*
*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_agilex_ll.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
static int clk_get_rate(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(dev);
switch ((intp... | /content/code_sandbox/drivers/clock_control/clock_agilex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 254 |
```c
/*
*
*/
#include <zephyr/drivers/firmware/scmi/clk.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(arm_scmi_clock);
#define DT_DRV_COMPAT arm_scmi_clock
struct scmi_clock_data {
uint32_t clk_num;
};
static int scmi_clock_on_off(const struct device *dev,
... | /content/code_sandbox/drivers/clock_control/clock_control_arm_scmi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 572 |
```c
/*
*
*/
#define DT_DRV_COMPAT ambiq_clkctrl
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/clock_control_ambiq.h>
#include <am_mcu_apollo.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clo... | /content/code_sandbox/drivers/clock_control/clock_control_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 990 |
```unknown
# Smartbond clock control driver config
config CLOCK_CONTROL_SMARTBOND
bool "Smartbond Clock Control"
depends on SOC_FAMILY_RENESAS_SMARTBOND
help
Enable driver for Clock Control subsystem found in SmartBond
if CLOCK_CONTROL_SMARTBOND
config SMARTBOND_LP_OSC_CALIBRATION_INTERVAL
int "Low-power osc... | /content/code_sandbox/drivers/clock_control/Kconfig.smartbond | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_pcc
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/npcx_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control_npcx, LOG_LEVEL_ERR);
/* Driver config */
struct npcx_pcc_config {
/* cdcg device base ... | /content/code_sandbox/drivers/clock_control/clock_control_npcx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,557 |
```unknown
config CLOCK_CONTROL_GD32
bool "GD32 clock control"
default y
depends on DT_HAS_GD_GD32_CCTL_ENABLED
help
Enable driver for Gigadevice Reset Clock Unit (RCU).
``` | /content/code_sandbox/drivers/clock_control/Kconfig.gd32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
config CLOCK_CONTROL_PWM
bool "Generic PWM clock"
default y
depends on DT_HAS_PWM_CLOCK_ENABLED
select PWM
help
Enable generic PWM clock.
config CLOCK_CONTROL_PWM_INIT_PRIORITY
int "Initialization priority of the pwm clock device"
default 51
depends on CLOCK_CONTROL_PWM
help
Initialization p... | /content/code_sandbox/drivers/clock_control/Kconfig.pwm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
# OpenISA RV32M1 PPC
config CLOCK_CONTROL_RV32M1_PCC
bool "RV32M1 PCC driver"
default y
depends on DT_HAS_OPENISA_RV32M1_PCC_ENABLED
help
Enable support for RV32M1 PCC driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.rv32m1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
# Microchip XEC
config CLOCK_CONTROL_MCHP_XEC
bool "MCHP XEC PCR clock control driver"
default y
depends on DT_HAS_MICROCHIP_XEC_PCR_ENABLED
help
Enable support for Microchip XEC PCR clock driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_h7.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,737 |
```c
/*
*
* Based on clock_control_mcux_sim.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_kinetis_scg
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/kinetis_scg.h>
#include <soc.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_scg.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,658 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defined(STM32_PLL_ENABLED)
/*... | /content/code_sandbox/drivers/clock_control/clock_stm32f0_f3.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,413 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_LPC11U6X_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_LPC11U6X_H_
#include <zephyr/drivers/pinctrl.h>
#define LPC11U6X_SYS_AHB_CLK_CTRL_I2C0 (1 << 5)
#define LPC11U6X_SYS_AHB_CLK_CTRL_GPIO (1 << 6)
#define LPC11U6X_SYS_AHB... | /content/code_sandbox/drivers/clock_control/clock_control_lpc11u6x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,709 |
```c
/*
*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
#include <zephyr/logging/log.h>
#include "clock_control_agilex5_ll.h"
#define DT_DRV_COMPAT intel_agilex5_clock
LOG_MODULE_REGISTER(clock_control_agilex5, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
struct cl... | /content/code_sandbox/drivers/clock_control/clock_control_agilex5.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 504 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/sys/onoff.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include "nrf_clock_calibration.h"
#include <nrfx_clock.h>
#include <zephyr/logging/log.h>
#include <zephyr/shell/shell.h>
#include <zephyr/irq.h>
LOG_MOD... | /content/code_sandbox/drivers/clock_control/clock_control_nrf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,545 |
```c
/*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <wrap_max32_sys.h>
#define DT_DRV_COMPAT adi_max32_gcr
static inline int api_on(const struct device *dev, clock_control_subsys_t clkcfg)
{
ARG_UNUSED(dev);
struct max32_perclk *percl... | /content/code_sandbox/drivers/clock_control/clock_control_max32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,182 |
```unknown
# NPCX Clock controller driver configuration options
config CLOCK_CONTROL_NPCX
bool "NPCX clock controller driver"
default y
depends on DT_HAS_NUVOTON_NPCX_PCC_ENABLED
help
Enable support for NPCX clock controller driver.
if CLOCK_CONTROL_NPCX
config CLOCK_CONTROL_NPCX_EXTERNAL_SRC
bool "Generate... | /content/code_sandbox/drivers/clock_control/Kconfig.npcx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 247 |
```unknown
# Beetle MCU clock control driver config
if SOC_FAMILY_ARM
menuconfig CLOCK_CONTROL_BEETLE
bool "BEETLE Clock Control"
default y
depends on DT_HAS_ARM_BEETLE_SYSCON_ENABLED
help
Enable driver for Reset & Clock Control subsystem found
in STM32F4 family of MCUs
if CLOCK_CONTROL_BEETLE
config CLO... | /content/code_sandbox/drivers/clock_control/Kconfig.beetle | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_pmc
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_... | /content/code_sandbox/drivers/clock_control/clock_control_sam_pmc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 916 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/drivers/clock_control/clock_agilex_ll.h>
#include <socfpga_system_manager.h>
/*
* Intel SoC re-use Arm Trusted Firmware (ATF) driver code in Zephyr.
* The migrated ATF driver code uses mmio_X macro to access the ... | /content/code_sandbox/drivers/clock_control/clock_agilex_ll.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,172 |
```unknown
# MCUXpresso SDK SIM
config CLOCK_CONTROL_MCUX_SIM
bool "MCUX SIM driver"
default y
depends on DT_HAS_NXP_KINETIS_SIM_ENABLED
help
Enable support for mcux sim driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_sim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
# MCUXpresso SDK SCG
config CLOCK_CONTROL_MCUX_SCG
bool "MCUX SCG driver"
default y
depends on DT_HAS_NXP_KINETIS_SCG_ENABLED
help
Enable support for mcux scg driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_scg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
# MCUXpresso SDK MCG
config CLOCK_CONTROL_MCUX_MCG
bool "MCUX MCG driver"
default y
depends on DT_HAS_NXP_KINETIS_MCG_ENABLED
help
Enable support for mcux mcg driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_mcg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config CLOCK_CONTROL_ARM_SCMI
bool "SCMI clock protocol clock controller driver"
default y
depends on ARM_SCMI_CLK_HELPERS
help
Enable support for SCMI-based clock control.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.arm_scmi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defined(RCC_CFGR_USBPRE)
#defi... | /content/code_sandbox/drivers/clock_control/clock_stm32f1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,463 |
```unknown
# Clock controller driver configuration options
#
# Clock controller drivers
#
menuconfig CLOCK_CONTROL
bool "Clock controller drivers"
help
Enable support for hardware clock controller. Such hardware can
provide clock for other subsystem, and thus can be also used for
power efficiency by contro... | /content/code_sandbox/drivers/clock_control/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 565 |
```unknown
# MCUXpresso SDK SYSCON
config CLOCK_CONTROL_MCUX_SYSCON
bool "MCUX LPC clock driver"
default y
depends on DT_HAS_NXP_LPC_SYSCON_ENABLED
help
Enable support for mcux clock driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_syscon | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_kinetis_sim
#include <errno.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/kinetis_sim.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_sim.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 921 |
```c
/*
*
*/
#define DT_DRV_COMPAT gd_gd32_cctl
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <gd32_regs.h>
/** RCU offset (from id cell) */
#define GD32_... | /content/code_sandbox/drivers/clock_control/clock_control_gd32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,852 |
```c
/*
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_pcc
#include <errno.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control);
struct rv32m1_pcc_config {
uint32_t base_a... | /content/code_sandbox/drivers/clock_control/clock_control_rv32m1_pcc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 490 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/sys/time_units.h>
#include ... | /content/code_sandbox/drivers/clock_control/clock_stm32l4_l5_wb_wl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 656 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#define ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#include <zephyr/spinlock.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/device_mmio.h>
#define CPG_NUM_DOMAINS 2
struct cpg_clk_info_table... | /content/code_sandbox/drivers/clock_control/clock_control_renesas_cpg_mssr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,576 |
```c
/*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_system.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/drivers/clock_control/stm32_clo... | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_wba.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,982 |
```unknown
# MCUXpresso SDK CCM
config CLOCK_CONTROL_MCUX_CCM
bool "MCUX CCM driver"
default y
depends on DT_HAS_NXP_IMX_CCM_ENABLED
help
Enable support for mcux ccm driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_ccm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_syscon
#include <zephyr/devicetree.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control/lpc11u6x_clock_control.h>
#include "clock_control_lpc11u6x.h"
static void syscon_power_up(struct lpc11u6x_syscon_regs *syscon,
... | /content/code_sandbox/drivers/clock_control/clock_control_lpc11u6x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,200 |
```c
/*
*
*/
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_litex.h>
#include "clock_control_litex.h"
#include <zephyr/logging/log.h>
#include <zephyr/logging/log_ctrl.h>
#include <zeph... | /content/code_sandbox/drivers/clock_control/clock_control_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14,495 |
```unknown
# Infineon CAT1 clock control driver
# an affiliate of Cypress Semiconductor Corporation
config CLOCK_CONTROL_INFINEON_CAT1
bool "Infineon CAT1 clock control driver"
default y
depends on SOC_FAMILY_INFINEON_CAT1
help
This option enables the clock control driver for Infineon CAT1 family.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.ifx_cat1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_crs.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defi... | /content/code_sandbox/drivers/clock_control/clock_stm32g0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 508 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
#include <stdint.h>
#include <zephyr/sys/sys_io.h>
/* Clock manager register offsets */
#define CLKMGR_CTRL 0x00
#define CLKMGR_STAT 0x04
#define CLKMGR_INTRCLR 0x14
/* Clock mana... | /content/code_sandbox/drivers/clock_control/clock_control_agilex5_ll.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,688 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_ccm_rev2
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control);
static int ... | /content/code_sandbox/drivers/clock_control/clock_control_mcux_ccm_rev2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,862 |
```c
/*
*
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#define DT_DRV_COMPAT st_stm32_clock_mux
LOG_MODULE_REGISTER(clock_mux, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
struct st... | /content/code_sandbox/drivers/clock_control/clock_stm32_mux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 305 |
```unknown
# Raspberry Pi Pico Clock Controller Driver configuration options
config CLOCK_CONTROL_RPI_PICO
bool "Raspberry Pi Pico Clock Controller Driver"
default y
depends on DT_HAS_RASPBERRYPI_PICO_CLOCK_CONTROLLER_ENABLED
if CLOCK_CONTROL_RPI_PICO
config RPI_PICO_ROSC_USE_MEASURED_FREQ
bool "Use measured fr... | /content/code_sandbox/drivers/clock_control/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_pcr
#include <soc.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>... | /content/code_sandbox/drivers/clock_control/clock_control_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,811 |
```unknown
config ADC_SAM
bool "Atmel SAM series ADC Driver"
default y
depends on DT_HAS_ATMEL_SAM_ADC_ENABLED
select ADC_CONFIGURABLE_INPUTS
help
Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver.
``` | /content/code_sandbox/drivers/adc/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
# Organisation (CSIRO) ABN 41 687 119 230.
# Hidden option for turning on the dummy driver for vnd,adc devices
# used in testing.
config ADC_TEST
def_bool DT_HAS_VND_ADC_ENABLED
depends on DT_HAS_VND_ADC_ENABLED
``` | /content/code_sandbox/drivers/adc/Kconfig.test | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_adc
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_mchp_xec);
#include <zephyr/drivers/adc.h>
#ifdef CONFIG_SOC_SERIES_MEC172X
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#endif
#include <zephyr... | /content/code_sandbox/drivers/adc/adc_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,596 |
```c
/*
*
*/
#define DT_DRV_COMPAT renesas_smartbond_sdadc
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include <DA1469xAB.h>
#include <da1469x_pd.h>
#include "adc_context.h"
#include <zephyr/dt-bindings/adc/smartbond-adc.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#... | /content/code_sandbox/drivers/adc/adc_smartbond_sdadc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,150 |
```unknown
# ADS1112 ADC configuration options
config ADC_ADS1112
bool "Texas Instruments ADS1112 ADC driver"
depends on DT_HAS_TI_ADS1112_ENABLED
select I2C
select ADC_CONFIGURABLE_INPUTS
help
Enable the driver implementation for the ADS1112
``` | /content/code_sandbox/drivers/adc/Kconfig.ads1112 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```c
/*
*
*/
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
#include <haly/nrfy_saadc.h>
#include <zephyr/dt-bindings/adc/nrf-adc.h>
#include <zephyr/linker/devicetree_regions.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(adc_nr... | /content/code_sandbox/drivers/adc/adc_nrfx_saadc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,539 |
```unknown
# ADC configuration options
config ADC_MCUX_ADC12
bool "MCUX ADC12 driver"
default y
depends on DT_HAS_NXP_KINETIS_ADC12_ENABLED
select PINCTRL
help
Enable the MCUX ADC12 driver.
config ADC_MCUX_ADC16
bool "MCUX ADC16 driver"
default y
depends on DT_HAS_NXP_KINETIS_ADC16_ENABLED
select PINCTRL... | /content/code_sandbox/drivers/adc/Kconfig.mcux | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 712 |
```unknown
#
config ADC_ADS7052
bool "Texas instruments ADS7052 SPI"
default y
depends on DT_HAS_TI_ADS7052_ENABLED
select SPI
select ADC_CONFIGURABLE_INPUTS
help
Enable the driver implementation for the ADS7052
if ADC_ADS7052
config ADC_ADS7052_INIT_PRIORITY
int "ADS7052 init priority"
default 80
help
... | /content/code_sandbox/drivers/adc/Kconfig.ads7052 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 197 |
```unknown
#
config ADC_AMBIQ
bool "Ambiq Adc Driver"
default y
depends on DT_HAS_AMBIQ_ADC_ENABLED
select AMBIQ_HAL
select AMBIQ_HAL_USE_ADC
help
Enables the Adc driver for Ambiq devices.
``` | /content/code_sandbox/drivers/adc/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_adc
#include <errno.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(adc_cc13xx_cc26xx);
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/adc.h>
#include <soc.h>
... | /content/code_sandbox/drivers/adc/adc_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,569 |
```c
/*
*
* Based on adc_mcux_adc12.c, which are:
*
*/
#define DT_DRV_COMPAT nxp_mcux_12b1msps_sar
#include <zephyr/drivers/adc.h>
#include <fsl_adc.h>
#include <zephyr/drivers/pinctrl.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(adc_mcux_1... | /content/code_sandbox/drivers/adc/adc_mcux_12b1msps_sar.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,665 |
```c
/*
*
*/
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
/*
* This requires to be included _after_ `#define AD... | /content/code_sandbox/drivers/adc/adc_tla2021.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,181 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_adc
#include <errno.h>
#include <soc.h>
#include <stdint.h>
#include <xmc_scu.h>
#include <xmc_vadc.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
#define LOG_L... | /content/code_sandbox/drivers/adc/adc_xmc4xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,577 |
```unknown
#
menuconfig ADC_MAX11102_17
bool "Maxim Integrated MAX11102-MAX11117"
default y
depends on DT_HAS_MAXIM_MAX11102_ENABLED \
|| DT_HAS_MAXIM_MAX11103_ENABLED \
|| DT_HAS_MAXIM_MAX11105_ENABLED \
|| DT_HAS_MAXIM_MAX11106_ENABLED \
|| DT_HAS_MAXIM_MAX11110_ENABLED \
|| DT_HAS_MAXIM_MAX11111_ENABLE... | /content/code_sandbox/drivers/adc/Kconfig.max11102_17 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 257 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER 1
#include "adc_contex... | /content/code_sandbox/drivers/adc/adc_ads1119.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,591 |
```c
/*
*
*/
#define DT_DRV_COMPAT ene_kb1200_adc
#include <zephyr/kernel.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <errno.h>
#include <reg/adc.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
struct adc_kb1200_config {
/* ADC Register base address */
struc... | /content/code_sandbox/drivers/adc/adc_ene_kb1200.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,923 |
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