text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
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```c
/* uart_h5.c - UART based Bluetooth driver */
/*
*
*/
#include <errno.h>
#include <stddef.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/debug/stack.h>
#include <zephyr/sys/printk.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <zephyr/bluetooth/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include "../util.h"
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_driver);
#define DT_DRV_COMPAT zephyr_bt_hci_3wire_uart
#define HCI_3WIRE_ACK_PKT 0x00
#define HCI_COMMAND_PKT 0x01
#define HCI_ACLDATA_PKT 0x02
#define HCI_SCODATA_PKT 0x03
#define HCI_EVENT_PKT 0x04
#define HCI_ISODATA_PKT 0x05
#define HCI_3WIRE_LINK_PKT 0x0f
#define HCI_VENDOR_PKT 0xff
static bool reliable_packet(uint8_t type)
{
switch (type) {
case HCI_COMMAND_PKT:
case HCI_ACLDATA_PKT:
case HCI_EVENT_PKT:
case HCI_ISODATA_PKT:
return true;
default:
return false;
}
}
/* FIXME: Correct timeout */
#define H5_RX_ACK_TIMEOUT K_MSEC(250)
#define H5_TX_ACK_TIMEOUT K_MSEC(250)
#define SLIP_DELIMITER 0xc0
#define SLIP_ESC 0xdb
#define SLIP_ESC_DELIM 0xdc
#define SLIP_ESC_ESC 0xdd
#define H5_RX_ESC 1
#define H5_TX_ACK_PEND 2
#define H5_HDR_SEQ(hdr) ((hdr)[0] & 0x07)
#define H5_HDR_ACK(hdr) (((hdr)[0] >> 3) & 0x07)
#define H5_HDR_CRC(hdr) (((hdr)[0] >> 6) & 0x01)
#define H5_HDR_RELIABLE(hdr) (((hdr)[0] >> 7) & 0x01)
#define H5_HDR_PKT_TYPE(hdr) ((hdr)[1] & 0x0f)
#define H5_HDR_LEN(hdr) ((((hdr)[1] >> 4) & 0x0f) + ((hdr)[2] << 4))
#define H5_SET_SEQ(hdr, seq) ((hdr)[0] |= (seq))
#define H5_SET_ACK(hdr, ack) ((hdr)[0] |= (ack) << 3)
#define H5_SET_RELIABLE(hdr) ((hdr)[0] |= 1 << 7)
#define H5_SET_TYPE(hdr, type) ((hdr)[1] |= type)
#define H5_SET_LEN(hdr, len) (((hdr)[1] |= ((len) & 0x0f) << 4), \
((hdr)[2] |= (len) >> 4))
struct h5_data {
/* Needed for delayed work callbacks */
const struct device *dev;
bt_hci_recv_t recv;
struct net_buf *rx_buf;
struct k_fifo tx_queue;
struct k_fifo rx_queue;
struct k_fifo unack_queue;
struct k_work_delayable ack_work;
struct k_work_delayable retx_work;
uint8_t tx_win;
uint8_t tx_ack;
uint8_t tx_seq;
uint8_t rx_ack;
enum {
UNINIT,
INIT,
ACTIVE,
} link_state;
enum {
START,
HEADER,
PAYLOAD,
END,
} rx_state;
uint8_t unack_queue_len;
};
struct h5_config {
const struct device *uart;
k_thread_stack_t *rx_stack;
size_t rx_stack_size;
struct k_thread *rx_thread;
k_thread_stack_t *tx_stack;
size_t tx_stack_size;
struct k_thread *tx_thread;
};
static const uint8_t sync_req[] = { 0x01, 0x7e };
static const uint8_t sync_rsp[] = { 0x02, 0x7d };
/* Third byte may change */
static uint8_t conf_req[3] = { 0x03, 0xfc };
static const uint8_t conf_rsp[] = { 0x04, 0x7b };
/* H5 signal buffers pool */
#define MAX_SIG_LEN 3
#define SIGNAL_COUNT (2 * DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT))
#define SIG_BUF_SIZE (BT_BUF_RESERVE + MAX_SIG_LEN)
NET_BUF_POOL_DEFINE(h5_pool, SIGNAL_COUNT, SIG_BUF_SIZE, 0, NULL);
static void h5_reset_rx(struct h5_data *h5)
{
if (h5->rx_buf) {
net_buf_unref(h5->rx_buf);
h5->rx_buf = NULL;
}
h5->rx_state = START;
}
static int h5_unslip_byte(const struct device *uart, uint8_t *byte)
{
int count;
if (*byte != SLIP_ESC) {
return 0;
}
do {
count = uart_fifo_read(uart, byte, sizeof(*byte));
} while (!count);
switch (*byte) {
case SLIP_ESC_DELIM:
*byte = SLIP_DELIMITER;
break;
case SLIP_ESC_ESC:
*byte = SLIP_ESC;
break;
default:
LOG_ERR("Invalid escape byte %x\n", *byte);
return -EIO;
}
return 0;
}
static void process_unack(struct h5_data *h5)
{
uint8_t next_seq = h5->tx_seq;
uint8_t number_removed = h5->unack_queue_len;
if (!h5->unack_queue_len) {
return;
}
LOG_DBG("rx_ack %u tx_ack %u tx_seq %u unack_queue_len %u", h5->rx_ack, h5->tx_ack,
h5->tx_seq, h5->unack_queue_len);
while (h5->unack_queue_len > 0) {
if (next_seq == h5->rx_ack) {
/* Next sequence number is the same as last received
* ack number
*/
break;
}
number_removed--;
/* Similar to (n - 1) % 8 with unsigned conversion */
next_seq = (next_seq - 1) & 0x07;
}
if (next_seq != h5->rx_ack) {
LOG_ERR("Wrong sequence: rx_ack %u tx_seq %u next_seq %u", h5->rx_ack,
h5->tx_seq, next_seq);
}
LOG_DBG("Need to remove %u packet from the queue", number_removed);
while (number_removed) {
struct net_buf *buf = k_fifo_get(&h5->unack_queue, K_NO_WAIT);
if (!buf) {
LOG_ERR("Unack queue is empty");
break;
}
/* TODO: print or do something with packet */
LOG_DBG("Remove buf from the unack_queue");
net_buf_unref(buf);
h5->unack_queue_len--;
number_removed--;
}
}
static void h5_print_header(const uint8_t *hdr, const char *str)
{
if (H5_HDR_RELIABLE(hdr)) {
LOG_DBG("%s REL: seq %u ack %u crc %u type %u len %u", str, H5_HDR_SEQ(hdr),
H5_HDR_ACK(hdr), H5_HDR_CRC(hdr), H5_HDR_PKT_TYPE(hdr), H5_HDR_LEN(hdr));
} else {
LOG_DBG("%s UNREL: ack %u crc %u type %u len %u", str, H5_HDR_ACK(hdr),
H5_HDR_CRC(hdr), H5_HDR_PKT_TYPE(hdr), H5_HDR_LEN(hdr));
}
}
#if defined(CONFIG_BT_HCI_DRIVER_LOG_LEVEL_DBG)
static void hexdump(const char *str, const uint8_t *packet, size_t length)
{
int n = 0;
if (!length) {
printk("%s zero-length signal packet\n", str);
return;
}
while (length--) {
if (n % 16 == 0) {
printk("%s %08X ", str, n);
}
printk("%02X ", *packet++);
n++;
if (n % 8 == 0) {
if (n % 16 == 0) {
printk("\n");
} else {
printk(" ");
}
}
}
if (n % 16) {
printk("\n");
}
}
#else
#define hexdump(str, packet, length)
#endif
static uint8_t h5_slip_byte(const struct device *uart, uint8_t byte)
{
switch (byte) {
case SLIP_DELIMITER:
uart_poll_out(uart, SLIP_ESC);
uart_poll_out(uart, SLIP_ESC_DELIM);
return 2;
case SLIP_ESC:
uart_poll_out(uart, SLIP_ESC);
uart_poll_out(uart, SLIP_ESC_ESC);
return 2;
default:
uart_poll_out(uart, byte);
return 1;
}
}
static void h5_send(const struct device *dev, const uint8_t *payload, uint8_t type, int len)
{
const struct h5_config *cfg = dev->config;
struct h5_data *h5 = dev->data;
uint8_t hdr[4];
int i;
hexdump("<= ", payload, len);
(void)memset(hdr, 0, sizeof(hdr));
/* Set ACK for outgoing packet and stop delayed work */
H5_SET_ACK(hdr, h5->tx_ack);
/* If cancel fails we may ack the same seq number twice, this is OK. */
(void)k_work_cancel_delayable(&h5->ack_work);
if (reliable_packet(type)) {
H5_SET_RELIABLE(hdr);
H5_SET_SEQ(hdr, h5->tx_seq);
h5->tx_seq = (h5->tx_seq + 1) % 8;
}
H5_SET_TYPE(hdr, type);
H5_SET_LEN(hdr, len);
/* Calculate CRC */
hdr[3] = ~((hdr[0] + hdr[1] + hdr[2]) & 0xff);
h5_print_header(hdr, "TX: <");
uart_poll_out(cfg->uart, SLIP_DELIMITER);
for (i = 0; i < 4; i++) {
h5_slip_byte(cfg->uart, hdr[i]);
}
for (i = 0; i < len; i++) {
h5_slip_byte(cfg->uart, payload[i]);
}
uart_poll_out(cfg->uart, SLIP_DELIMITER);
}
/* Delayed work taking care about retransmitting packets */
static void retx_timeout(struct k_work *work)
{
struct k_work_delayable *delayable = k_work_delayable_from_work(work);
struct h5_data *h5 = CONTAINER_OF(delayable, struct h5_data, retx_work);
LOG_DBG("unack_queue_len %u", h5->unack_queue_len);
if (h5->unack_queue_len) {
struct k_fifo tmp_queue;
struct net_buf *buf;
k_fifo_init(&tmp_queue);
/* Queue to temporary queue */
while ((buf = k_fifo_get(&h5->tx_queue, K_NO_WAIT))) {
k_fifo_put(&tmp_queue, buf);
}
/* Queue unack packets to the beginning of the queue */
while ((buf = k_fifo_get(&h5->unack_queue, K_NO_WAIT))) {
/* include also packet type */
net_buf_push(buf, sizeof(uint8_t));
k_fifo_put(&h5->tx_queue, buf);
h5->tx_seq = (h5->tx_seq - 1) & 0x07;
h5->unack_queue_len--;
}
/* Queue saved packets from temp queue */
while ((buf = k_fifo_get(&tmp_queue, K_NO_WAIT))) {
k_fifo_put(&h5->tx_queue, buf);
}
}
}
static void ack_timeout(struct k_work *work)
{
struct k_work_delayable *delayable = k_work_delayable_from_work(work);
struct h5_data *h5 = CONTAINER_OF(delayable, struct h5_data, ack_work);
LOG_DBG("");
h5_send(h5->dev, NULL, HCI_3WIRE_ACK_PKT, 0);
}
static void h5_process_complete_packet(const struct device *dev, uint8_t *hdr)
{
struct h5_data *h5 = dev->data;
struct net_buf *buf;
LOG_DBG("");
/* rx_ack should be in every packet */
h5->rx_ack = H5_HDR_ACK(hdr);
if (reliable_packet(H5_HDR_PKT_TYPE(hdr))) {
/* For reliable packet increment next transmit ack number */
h5->tx_ack = (h5->tx_ack + 1) % 8;
/* Submit delayed work to ack the packet */
k_work_reschedule(&h5->ack_work, H5_RX_ACK_TIMEOUT);
}
h5_print_header(hdr, "RX: >");
process_unack(h5);
buf = h5->rx_buf;
h5->rx_buf = NULL;
switch (H5_HDR_PKT_TYPE(hdr)) {
case HCI_3WIRE_ACK_PKT:
net_buf_unref(buf);
break;
case HCI_3WIRE_LINK_PKT:
k_fifo_put(&h5->rx_queue, buf);
break;
case HCI_EVENT_PKT:
case HCI_ACLDATA_PKT:
case HCI_ISODATA_PKT:
hexdump("=> ", buf->data, buf->len);
h5->recv(dev, buf);
break;
}
}
static inline struct net_buf *get_evt_buf(uint8_t evt)
{
return bt_buf_get_evt(evt, false, K_NO_WAIT);
}
static void bt_uart_isr(const struct device *uart, void *user_data)
{
const struct device *dev = user_data;
struct h5_data *h5 = dev->data;
static int remaining;
uint8_t byte;
int ret;
static uint8_t hdr[4];
size_t buf_tailroom;
while (uart_irq_update(uart) &&
uart_irq_is_pending(uart)) {
if (!uart_irq_rx_ready(uart)) {
if (uart_irq_tx_ready(uart)) {
LOG_DBG("transmit ready");
} else {
LOG_DBG("spurious interrupt");
}
/* Only the UART RX path is interrupt-enabled */
break;
}
ret = uart_fifo_read(uart, &byte, sizeof(byte));
if (!ret) {
continue;
}
switch (h5->rx_state) {
case START:
if (byte == SLIP_DELIMITER) {
h5->rx_state = HEADER;
remaining = sizeof(hdr);
}
break;
case HEADER:
/* In a case we confuse ending slip delimiter
* with starting one.
*/
if (byte == SLIP_DELIMITER) {
remaining = sizeof(hdr);
continue;
}
if (h5_unslip_byte(uart, &byte) < 0) {
h5_reset_rx(h5);
continue;
}
memcpy(&hdr[sizeof(hdr) - remaining], &byte, 1);
remaining--;
if (remaining) {
break;
}
remaining = H5_HDR_LEN(hdr);
switch (H5_HDR_PKT_TYPE(hdr)) {
case HCI_EVENT_PKT:
/* The buffer is allocated only once we know
* the exact event type.
*/
h5->rx_state = PAYLOAD;
break;
case HCI_ACLDATA_PKT:
h5->rx_buf = bt_buf_get_rx(BT_BUF_ACL_IN,
K_NO_WAIT);
if (!h5->rx_buf) {
LOG_WRN("No available data buffers");
h5_reset_rx(h5);
continue;
}
h5->rx_state = PAYLOAD;
break;
case HCI_ISODATA_PKT:
h5->rx_buf = bt_buf_get_rx(BT_BUF_ISO_IN, K_NO_WAIT);
if (!h5->rx_buf) {
LOG_WRN("No available data buffers");
h5_reset_rx(h5);
continue;
}
h5->rx_state = PAYLOAD;
break;
case HCI_3WIRE_LINK_PKT:
case HCI_3WIRE_ACK_PKT:
h5->rx_buf = net_buf_alloc(&h5_pool, K_NO_WAIT);
if (!h5->rx_buf) {
LOG_WRN("No available signal buffers");
h5_reset_rx(h5);
continue;
}
h5->rx_state = PAYLOAD;
break;
default:
LOG_ERR("Wrong packet type %u", H5_HDR_PKT_TYPE(hdr));
h5->rx_state = END;
break;
}
if (!remaining) {
h5->rx_state = END;
}
break;
case PAYLOAD:
if (h5_unslip_byte(uart, &byte) < 0) {
h5_reset_rx(h5);
continue;
}
/* Allocate HCI event buffer now that we know the
* exact event type.
*/
if (!h5->rx_buf) {
h5->rx_buf = get_evt_buf(byte);
if (!h5->rx_buf) {
LOG_WRN("No available event buffers");
h5_reset_rx(h5);
continue;
}
}
buf_tailroom = net_buf_tailroom(h5->rx_buf);
if (buf_tailroom < sizeof(byte)) {
LOG_ERR("Not enough space in buffer %zu/%zu", sizeof(byte),
buf_tailroom);
h5_reset_rx(h5);
break;
}
net_buf_add_mem(h5->rx_buf, &byte, sizeof(byte));
remaining--;
if (!remaining) {
h5->rx_state = END;
}
break;
case END:
if (byte != SLIP_DELIMITER) {
LOG_ERR("Missing ending SLIP_DELIMITER");
h5_reset_rx(h5);
break;
}
LOG_DBG("Received full packet: type %u", H5_HDR_PKT_TYPE(hdr));
/* Check when full packet is received, it can be done
* when parsing packet header but we need to receive
* full packet anyway to clear UART.
*/
if (H5_HDR_RELIABLE(hdr) &&
H5_HDR_SEQ(hdr) != h5->tx_ack) {
LOG_ERR("Seq expected %u got %u. Drop packet", h5->tx_ack,
H5_HDR_SEQ(hdr));
h5_reset_rx(h5);
break;
}
h5_process_complete_packet(dev, hdr);
h5->rx_state = START;
break;
}
}
}
static uint8_t h5_get_type(struct net_buf *buf)
{
return net_buf_pull_u8(buf);
}
static int h5_queue(const struct device *dev, struct net_buf *buf)
{
struct h5_data *h5 = dev->data;
uint8_t type;
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
switch (bt_buf_get_type(buf)) {
case BT_BUF_CMD:
type = HCI_COMMAND_PKT;
break;
case BT_BUF_ACL_OUT:
type = HCI_ACLDATA_PKT;
break;
case BT_BUF_ISO_OUT:
type = HCI_ISODATA_PKT;
break;
default:
LOG_ERR("Unknown packet type %u", bt_buf_get_type(buf));
return -1;
}
memcpy(net_buf_push(buf, sizeof(type)), &type, sizeof(type));
k_fifo_put(&h5->tx_queue, buf);
return 0;
}
static void tx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct h5_data *h5 = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
LOG_DBG("");
/* FIXME: make periodic sending */
h5_send(dev, sync_req, HCI_3WIRE_LINK_PKT, sizeof(sync_req));
while (true) {
struct net_buf *buf;
uint8_t type;
LOG_DBG("link_state %u", h5->link_state);
switch (h5->link_state) {
case UNINIT:
/* FIXME: send sync */
k_sleep(K_MSEC(100));
break;
case INIT:
/* FIXME: send conf */
k_sleep(K_MSEC(100));
break;
case ACTIVE:
buf = k_fifo_get(&h5->tx_queue, K_FOREVER);
type = h5_get_type(buf);
h5_send(dev, buf->data, type, buf->len);
/* buf is dequeued from tx_queue and queued to unack
* queue.
*/
k_fifo_put(&h5->unack_queue, buf);
h5->unack_queue_len++;
k_work_reschedule(&h5->retx_work, H5_TX_ACK_TIMEOUT);
break;
}
}
}
static void h5_set_txwin(struct h5_data *h5, uint8_t *conf)
{
conf[2] = h5->tx_win & 0x07;
}
static void rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct h5_data *h5 = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
LOG_DBG("");
while (true) {
struct net_buf *buf;
buf = k_fifo_get(&h5->rx_queue, K_FOREVER);
hexdump("=> ", buf->data, buf->len);
if (!memcmp(buf->data, sync_req, sizeof(sync_req))) {
if (h5->link_state == ACTIVE) {
/* TODO Reset H5 */
}
h5_send(dev, sync_rsp, HCI_3WIRE_LINK_PKT, sizeof(sync_rsp));
} else if (!memcmp(buf->data, sync_rsp, sizeof(sync_rsp))) {
if (h5->link_state == ACTIVE) {
/* TODO Reset H5 */
}
h5->link_state = INIT;
h5_set_txwin(h5, conf_req);
h5_send(dev, conf_req, HCI_3WIRE_LINK_PKT, sizeof(conf_req));
} else if (!memcmp(buf->data, conf_req, 2)) {
/*
* The Host sends Config Response messages without a
* Configuration Field.
*/
h5_send(dev, conf_rsp, HCI_3WIRE_LINK_PKT, sizeof(conf_rsp));
/* Then send Config Request with Configuration Field */
h5_set_txwin(h5, conf_req);
h5_send(dev, conf_req, HCI_3WIRE_LINK_PKT, sizeof(conf_req));
} else if (!memcmp(buf->data, conf_rsp, 2)) {
h5->link_state = ACTIVE;
if (buf->len > 2) {
/* Configuration field present */
h5->tx_win = (buf->data[2] & 0x07);
}
LOG_DBG("Finished H5 configuration, tx_win %u", h5->tx_win);
} else {
LOG_ERR("Not handled yet %x %x", buf->data[0], buf->data[1]);
}
net_buf_unref(buf);
/* Make sure we don't hog the CPU if the rx_queue never
* gets empty.
*/
k_yield();
}
}
static void h5_init(const struct device *dev)
{
const struct h5_config *cfg = dev->config;
struct h5_data *h5 = dev->data;
k_tid_t tid;
LOG_DBG("");
h5->link_state = UNINIT;
h5->rx_state = START;
h5->tx_win = 4U;
/* TX thread */
k_fifo_init(&h5->tx_queue);
tid = k_thread_create(cfg->tx_thread, cfg->tx_stack, cfg->tx_stack_size,
tx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_HCI_TX_PRIO),
0, K_NO_WAIT);
k_thread_name_set(tid, "tx_thread");
k_fifo_init(&h5->rx_queue);
tid = k_thread_create(cfg->rx_thread, cfg->rx_stack, cfg->rx_stack_size,
rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_RX_PRIO),
0, K_NO_WAIT);
k_thread_name_set(tid, "rx_thread");
/* Unack queue */
k_fifo_init(&h5->unack_queue);
/* Init delayed work */
k_work_init_delayable(&h5->ack_work, ack_timeout);
k_work_init_delayable(&h5->retx_work, retx_timeout);
}
static int h5_open(const struct device *dev, bt_hci_recv_t recv)
{
const struct h5_config *cfg = dev->config;
struct h5_data *h5 = dev->data;
LOG_DBG("");
/* This is needed so that we can access the device struct from within the
* delayed work callbacks.
*/
h5->dev = dev;
h5->recv = recv;
uart_irq_rx_disable(cfg->uart);
uart_irq_tx_disable(cfg->uart);
bt_uart_drain(cfg->uart);
uart_irq_callback_user_data_set(cfg->uart, bt_uart_isr, (void *)dev);
h5_init(dev);
uart_irq_rx_enable(cfg->uart);
return 0;
}
static const struct bt_hci_driver_api h5_driver_api = {
.open = h5_open,
.send = h5_queue,
};
#define BT_UART_DEVICE_INIT(inst) \
static K_KERNEL_STACK_DEFINE(rx_thread_stack_##inst, CONFIG_BT_DRV_RX_STACK_SIZE); \
static struct k_thread rx_thread_##inst; \
static K_KERNEL_STACK_DEFINE(tx_thread_stack_##inst, CONFIG_BT_DRV_TX_STACK_SIZE); \
static struct k_thread tx_thread_##inst; \
static const struct h5_config h5_config_##inst = { \
.uart = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.rx_stack = rx_thread_stack_##inst, \
.rx_stack_size = K_KERNEL_STACK_SIZEOF(rx_thread_stack_##inst), \
.rx_thread = &rx_thread_##inst, \
.tx_stack = tx_thread_stack_##inst, \
.tx_stack_size = K_KERNEL_STACK_SIZEOF(tx_thread_stack_##inst), \
.tx_thread = &tx_thread_##inst, \
}; \
static struct h5_data h5_##inst; \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &h5_##inst, &h5_config_##inst, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &h5_driver_api)
DT_INST_FOREACH_STATUS_OKAY(BT_UART_DEVICE_INIT)
``` | /content/code_sandbox/drivers/bluetooth/hci/h5.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,940 |
```c
/* spi.c - SPI based Bluetooth driver */
#define DT_DRV_COMPAT zephyr_bt_hci_spi
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_driver);
/* Special Values */
#define SPI_WRITE 0x0A
#define SPI_READ 0x0B
#define READY_NOW 0x02
#define EVT_BLUE_INITIALIZED 0x01
/* Offsets */
#define STATUS_HEADER_READY 0
#define STATUS_HEADER_TOREAD 3
#define STATUS_HEADER_TOWRITE 1
#define PACKET_TYPE 0
#define EVT_HEADER_TYPE 0
#define EVT_HEADER_EVENT 1
#define EVT_HEADER_SIZE 2
#define EVT_LE_META_SUBEVENT 3
#define EVT_VENDOR_CODE_LSB 3
#define EVT_VENDOR_CODE_MSB 4
#define CMD_OGF 1
#define CMD_OCF 2
/* Max SPI buffer length for transceive operations.
*
* Buffer size needs to be at least the size of the larger RX/TX buffer
* required by the SPI slave, as the legacy spi_transceive requires both RX/TX
* to be the same length. Size also needs to be compatible with the
* slave device used (e.g. nRF5X max buffer length for SPIS is 255).
*/
#define SPI_MAX_MSG_LEN 255 /* As defined by X-NUCLEO-IDB04A1 BSP */
#define DATA_DELAY_US DT_INST_PROP(0, controller_data_delay_us)
/* Single byte header denoting the buffer type */
#define H4_HDR_SIZE 1
/* Maximum L2CAP MTU that can fit in a single packet */
#define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
#if CONFIG_BT_L2CAP_TX_MTU > MAX_MTU
#warning CONFIG_BT_L2CAP_TX_MTU is too large and can result in packets that cannot \
be transmitted across this HCI link
#endif /* CONFIG_BT_L2CAP_TX_MTU > MAX_MTU */
struct bt_spi_data {
bt_hci_recv_t recv;
};
static uint8_t __noinit rxmsg[SPI_MAX_MSG_LEN];
static uint8_t __noinit txmsg[SPI_MAX_MSG_LEN];
static const struct gpio_dt_spec irq_gpio = GPIO_DT_SPEC_INST_GET(0, irq_gpios);
static const struct gpio_dt_spec rst_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios);
static struct gpio_callback gpio_cb;
static K_SEM_DEFINE(sem_initialised, 0, 1);
static K_SEM_DEFINE(sem_request, 0, 1);
static K_SEM_DEFINE(sem_busy, 1, 1);
static K_KERNEL_STACK_DEFINE(spi_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE);
static struct k_thread spi_rx_thread_data;
static const struct spi_dt_spec bus = SPI_DT_SPEC_INST_GET(
0, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0);
static struct spi_buf spi_tx_buf;
static struct spi_buf spi_rx_buf;
static const struct spi_buf_set spi_tx = {
.buffers = &spi_tx_buf,
.count = 1
};
static const struct spi_buf_set spi_rx = {
.buffers = &spi_rx_buf,
.count = 1
};
static inline int bt_spi_transceive(void *tx, uint32_t tx_len,
void *rx, uint32_t rx_len)
{
spi_tx_buf.buf = tx;
spi_tx_buf.len = (size_t)tx_len;
spi_rx_buf.buf = rx;
spi_rx_buf.len = (size_t)rx_len;
return spi_transceive_dt(&bus, &spi_tx, &spi_rx);
}
static inline uint16_t bt_spi_get_cmd(uint8_t *msg)
{
return (msg[CMD_OCF] << 8) | msg[CMD_OGF];
}
static inline uint16_t bt_spi_get_evt(uint8_t *msg)
{
return (msg[EVT_VENDOR_CODE_MSB] << 8) | msg[EVT_VENDOR_CODE_LSB];
}
static void bt_spi_isr(const struct device *unused1,
struct gpio_callback *unused2,
uint32_t unused3)
{
LOG_DBG("");
k_sem_give(&sem_request);
}
static bool bt_spi_handle_vendor_evt(uint8_t *msg)
{
bool handled = false;
switch (bt_spi_get_evt(msg)) {
case EVT_BLUE_INITIALIZED: {
k_sem_give(&sem_initialised);
handled = true;
}
default:
break;
}
return handled;
}
static int bt_spi_get_header(uint8_t op, uint16_t *size)
{
uint8_t header_master[5] = {op, 0, 0, 0, 0};
uint8_t header_slave[5];
bool reading = (op == SPI_READ);
bool loop_cond;
uint8_t size_offset;
int ret;
if (!(op == SPI_READ || op == SPI_WRITE)) {
return -EINVAL;
}
if (reading) {
size_offset = STATUS_HEADER_TOREAD;
}
do {
ret = bt_spi_transceive(header_master, 5, header_slave, 5);
if (ret) {
break;
}
if (reading) {
/* When reading, keep looping if there is not yet any data */
loop_cond = header_slave[STATUS_HEADER_TOREAD] == 0U;
} else {
/* When writing, keep looping if all bytes are zero */
loop_cond = ((header_slave[1] | header_slave[2] | header_slave[3] |
header_slave[4]) == 0U);
}
} while ((header_slave[STATUS_HEADER_READY] != READY_NOW) || loop_cond);
*size = (reading ? header_slave[size_offset] : SPI_MAX_MSG_LEN);
return ret;
}
static struct net_buf *bt_spi_rx_buf_construct(uint8_t *msg)
{
bool discardable = false;
k_timeout_t timeout = K_FOREVER;
struct bt_hci_acl_hdr acl_hdr;
struct net_buf *buf;
int len;
switch (msg[PACKET_TYPE]) {
case BT_HCI_H4_EVT:
switch (msg[EVT_HEADER_EVENT]) {
case BT_HCI_EVT_VENDOR:
/* Run event through interface handler */
if (bt_spi_handle_vendor_evt(msg)) {
return NULL;
}
/* Event has not yet been handled */
__fallthrough;
default:
if (msg[EVT_HEADER_EVENT] == BT_HCI_EVT_LE_META_EVENT &&
(msg[EVT_LE_META_SUBEVENT] == BT_HCI_EVT_LE_ADVERTISING_REPORT)) {
discardable = true;
timeout = K_NO_WAIT;
}
buf = bt_buf_get_evt(msg[EVT_HEADER_EVENT],
discardable, timeout);
if (!buf) {
LOG_DBG("Discard adv report due to insufficient buf");
return NULL;
}
}
len = sizeof(struct bt_hci_evt_hdr) + msg[EVT_HEADER_SIZE];
if (len > net_buf_tailroom(buf)) {
LOG_ERR("Event too long: %d", len);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, &msg[1], len);
break;
case BT_HCI_H4_ACL:
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
memcpy(&acl_hdr, &msg[1], sizeof(acl_hdr));
len = sizeof(acl_hdr) + sys_le16_to_cpu(acl_hdr.len);
if (len > net_buf_tailroom(buf)) {
LOG_ERR("ACL too long: %d", len);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, &msg[1], len);
break;
default:
LOG_ERR("Unknown BT buf type %d", msg[0]);
return NULL;
}
return buf;
}
static void bt_spi_rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct bt_spi_data *hci = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct net_buf *buf;
uint16_t size = 0U;
int ret;
(void)memset(&txmsg, 0xFF, SPI_MAX_MSG_LEN);
while (true) {
/* Wait for interrupt pin to be active */
k_sem_take(&sem_request, K_FOREVER);
LOG_DBG("");
/* Wait for SPI bus to be available */
k_sem_take(&sem_busy, K_FOREVER);
ret = bt_spi_get_header(SPI_READ, &size);
/* Delay here is rounded up to next tick */
k_sleep(K_USEC(DATA_DELAY_US));
/* Read data */
if (ret == 0 && size != 0) {
do {
ret = bt_spi_transceive(&txmsg, size,
&rxmsg, size);
if (rxmsg[0] == 0U) {
/* Consider increasing controller-data-delay-us
* if this message is extremely common.
*/
LOG_DBG("Controller not ready for SPI transaction "
"of %d bytes", size);
}
} while (rxmsg[0] == 0U && ret == 0);
}
k_sem_give(&sem_busy);
if (ret || size == 0) {
if (ret) {
LOG_ERR("Error %d", ret);
}
continue;
}
LOG_HEXDUMP_DBG(rxmsg, size, "SPI RX");
/* Construct net_buf from SPI data */
buf = bt_spi_rx_buf_construct(rxmsg);
if (buf) {
/* Handle the received HCI data */
hci->recv(dev, buf);
}
}
}
static int bt_spi_send(const struct device *dev, struct net_buf *buf)
{
uint16_t size;
uint8_t rx_first[1];
int ret;
ARG_UNUSED(dev);
LOG_DBG("");
/* Buffer needs an additional byte for type */
if (buf->len >= SPI_MAX_MSG_LEN) {
LOG_ERR("Message too long (%d)", buf->len);
return -EINVAL;
}
/* Wait for SPI bus to be available */
k_sem_take(&sem_busy, K_FOREVER);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
net_buf_push_u8(buf, BT_HCI_H4_ACL);
break;
case BT_BUF_CMD:
net_buf_push_u8(buf, BT_HCI_H4_CMD);
break;
default:
LOG_ERR("Unsupported type");
k_sem_give(&sem_busy);
return -EINVAL;
}
ret = bt_spi_get_header(SPI_WRITE, &size);
size = MIN(buf->len, size);
if (size < buf->len) {
LOG_WRN("Unable to write full data, skipping");
size = 0;
ret = -ECANCELED;
}
if (!ret) {
/* Delay here is rounded up to next tick */
k_sleep(K_USEC(DATA_DELAY_US));
/* Transmit the message */
while (true) {
ret = bt_spi_transceive(buf->data, size,
rx_first, 1);
if (rx_first[0] != 0U || ret) {
break;
}
/* Consider increasing controller-data-delay-us
* if this message is extremely common.
*/
LOG_DBG("Controller not ready for SPI transaction of %d bytes", size);
}
}
k_sem_give(&sem_busy);
if (ret) {
LOG_ERR("Error %d", ret);
goto out;
}
LOG_HEXDUMP_DBG(buf->data, buf->len, "SPI TX");
out:
net_buf_unref(buf);
return ret;
}
static int bt_spi_open(const struct device *dev, bt_hci_recv_t recv)
{
struct bt_spi_data *hci = dev->data;
int err;
/* Configure RST pin and hold BLE in Reset */
err = gpio_pin_configure_dt(&rst_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
return err;
}
/* Configure IRQ pin and the IRQ call-back/handler */
err = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
if (err) {
return err;
}
gpio_init_callback(&gpio_cb, bt_spi_isr, BIT(irq_gpio.pin));
err = gpio_add_callback(irq_gpio.port, &gpio_cb);
if (err) {
return err;
}
/* Enable the interrupt line */
err = gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (err) {
return err;
}
hci->recv = recv;
/* Take BLE out of reset */
k_sleep(K_MSEC(DT_INST_PROP_OR(0, reset_assert_duration_ms, 0)));
gpio_pin_set_dt(&rst_gpio, 0);
/* Start RX thread */
k_thread_create(&spi_rx_thread_data, spi_rx_stack,
K_KERNEL_STACK_SIZEOF(spi_rx_stack),
bt_spi_rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO),
0, K_NO_WAIT);
/* Device will let us know when it's ready */
k_sem_take(&sem_initialised, K_FOREVER);
return 0;
}
static const struct bt_hci_driver_api drv = {
.open = bt_spi_open,
.send = bt_spi_send,
};
static int bt_spi_init(const struct device *dev)
{
ARG_UNUSED(dev);
if (!spi_is_ready_dt(&bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&rst_gpio)) {
LOG_ERR("Reset GPIO device not ready");
return -ENODEV;
}
LOG_DBG("BT SPI initialized");
return 0;
}
#define HCI_DEVICE_INIT(inst) \
static struct bt_spi_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, bt_spi_init, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_BT_SPI_INIT_PRIORITY, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/spi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,158 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief PSoC 6 BLE (BLESS) driver.
*/
#include <errno.h>
#include <stddef.h>
#include <string.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/bluetooth/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(psoc6_bless);
#include "cy_ble_stack_pvt.h"
#include "cycfg_ble.h"
#define DT_DRV_COMPAT infineon_cat1_bless_hci
struct psoc6_bless_data {
bt_hci_recv_t recv;
};
#define BLE_LOCK_TMOUT_MS (1000)
#define BLE_THREAD_SEM_TMOUT_MS (1000)
#define CYBLE_STACK_SIZE (CY_BLE_STACK_RAM_SIZE + 4096)
#define PSOC6_BLESS_OP_SET_PUBLIC_ADDR BT_OP(BT_OGF_VS, 0x1a0)
static K_SEM_DEFINE(psoc6_bless_rx_sem, 0, 1);
static K_SEM_DEFINE(psoc6_bless_operation_sem, 1, 1);
static K_KERNEL_STACK_DEFINE(psoc6_bless_rx_thread_stack, CONFIG_BT_RX_STACK_SIZE);
static struct k_thread psoc6_bless_rx_thread_data;
static cy_stc_ble_hci_tx_packet_info_t hci_tx_pkt;
extern void Cy_BLE_EnableLowPowerMode(void);
CY_ALIGN(sizeof(uint32_t)) CY_NOINIT uint8_t psoc6_bless_stack_memory[CYBLE_STACK_SIZE];
/** BLE Stack parameters */
static cy_stc_ble_stack_params_t psoc6_bless_stack_param = {
.memoryHeapPtr = psoc6_bless_stack_memory,
.totalHeapSz = CYBLE_STACK_SIZE,
.dleMaxTxCapability = CONFIG_BT_PSOC6_BLESS_MAX_TX_PAYLOAD,
.dleMaxRxCapability = CONFIG_BT_PSOC6_BLESS_MAX_RX_PAYLOAD,
.featureMask = (CY_BLE_DLE_FEATURE | CY_BLE_LL_PRIVACY_FEATURE |
CY_BLE_SECURE_CONN_FEATURE | CY_BLE_PHY_UPDATE_FEATURE |
CY_BLE_STORE_BONDLIST_FEATURE | CY_BLE_STORE_RESOLVING_LIST_FEATURE |
CY_BLE_STORE_WHITELIST_FEATURE | CY_BLE_TX_POWER_CALIBRATION_FEATURE),
.maxConnCount = CY_BLE_CONN_COUNT,
.tx5dbmModeEn = CY_BLE_ENABLE_TX_5DBM,
};
static const cy_stc_sysint_t psoc6_bless_isr_cfg = {
.intrSrc = DT_INST_IRQN(0),
.intrPriority = DT_INST_IRQ(0, priority),
};
static cy_stc_ble_hw_config_t psoc6_bless_hw_config = {
.blessIsrConfig = &psoc6_bless_isr_cfg,
};
static const cy_stc_ble_config_t psoc6_bless_config = {
.stackParam = &psoc6_bless_stack_param,
.hw = &psoc6_bless_hw_config,
};
static void psoc6_bless_rx_thread(void *, void *, void *)
{
while (true) {
k_sem_take(&psoc6_bless_rx_sem, K_MSEC(BLE_THREAD_SEM_TMOUT_MS));
Cy_BLE_ProcessEvents();
}
}
static void psoc6_bless_isr_handler(const struct device *dev)
{
if (Cy_BLE_HAL_BlessInterruptHandler()) {
k_sem_give(&psoc6_bless_rx_sem);
}
}
static void psoc6_bless_events_handler(uint32_t eventCode, void *eventParam)
{
const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
struct psoc6_bless_data *hci = dev->data;
cy_stc_ble_hci_tx_packet_info_t *hci_rx = NULL;
struct net_buf *buf = NULL;
size_t buf_tailroom = 0;
if (eventCode != CY_BLE_EVT_HCI_PKT_RCVD) {
LOG_DBG("Other EVENT 0x%X", eventCode);
return;
}
hci_rx = eventParam;
switch (hci_rx->packetType) {
case BT_HCI_H4_EVT:
buf = bt_buf_get_evt(hci_rx->data[0], 0, K_NO_WAIT);
if (!buf) {
LOG_ERR("Failed to allocate the buffer for RX: EVENT ");
return;
}
break;
case BT_HCI_H4_ACL:
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (!buf) {
LOG_ERR("Failed to allocate the buffer for RX: ACL ");
return;
}
bt_buf_set_type(buf, BT_BUF_ACL_IN);
break;
default:
LOG_WRN("Unsupported HCI Packet Received");
return;
}
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < hci_rx->dataLength) {
LOG_WRN("Not enough space for rx data");
return;
}
net_buf_add_mem(buf, hci_rx->data, hci_rx->dataLength);
hci->recv(dev, buf);
}
static int psoc6_bless_open(const struct device *dev, bt_hci_recv_t recv)
{
struct psoc6_bless_data *hci = dev->data;
k_tid_t tid;
hci->recv = recv;
tid = k_thread_create(&psoc6_bless_rx_thread_data, psoc6_bless_rx_thread_stack,
K_KERNEL_STACK_SIZEOF(psoc6_bless_rx_thread_stack),
psoc6_bless_rx_thread, NULL, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_RX_PRIO), 0, K_NO_WAIT);
k_thread_name_set(tid, "psoc6_bless_rx_thread");
return 0;
}
static int psoc6_bless_send(const struct device *dev, struct net_buf *buf)
{
cy_en_ble_api_result_t result;
ARG_UNUSED(dev);
memset(&hci_tx_pkt, 0, sizeof(cy_stc_ble_hci_tx_packet_info_t));
hci_tx_pkt.dataLength = buf->len;
hci_tx_pkt.data = buf->data;
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
hci_tx_pkt.packetType = BT_HCI_H4_ACL;
break;
case BT_BUF_CMD:
hci_tx_pkt.packetType = BT_HCI_H4_CMD;
break;
default:
net_buf_unref(buf);
return -ENOTSUP;
}
if (k_sem_take(&psoc6_bless_operation_sem, K_MSEC(BLE_LOCK_TMOUT_MS)) != 0) {
LOG_ERR("Failed to acquire BLE DRV Semaphore");
net_buf_unref(buf);
return -EIO;
}
result = Cy_BLE_SoftHciSendAppPkt(&hci_tx_pkt);
if (result != CY_BLE_SUCCESS) {
LOG_ERR("Error in sending packet reason %d\r\n", result);
}
k_sem_give(&psoc6_bless_operation_sem);
net_buf_unref(buf);
/* Unblock psoc6 bless rx thread to process controller events
* (by calling Cy_BLE_ProcessEvents function)
*/
k_sem_give(&psoc6_bless_rx_sem);
return 0;
}
static int psoc6_bless_setup(const struct device *dev, const struct bt_hci_setup_params *params)
{
ARG_UNUSED(dev);
ARG_UNUSED(params);
struct net_buf *buf;
int err;
uint8_t *addr = (uint8_t *)&SFLASH_BLE_DEVICE_ADDRESS[0];
uint8_t hci_data[] = {
addr[5], addr[4], addr[3], addr[2], addr[1], addr[0], BT_ADDR_LE_PUBLIC,
};
buf = bt_hci_cmd_create(PSOC6_BLESS_OP_SET_PUBLIC_ADDR, sizeof(hci_data));
if (buf == NULL) {
LOG_ERR("Unable to allocate command buffer");
return -ENOMEM;
}
/* Add data part of packet */
net_buf_add_mem(buf, hci_data, sizeof(hci_data));
err = bt_hci_cmd_send_sync(PSOC6_BLESS_OP_SET_PUBLIC_ADDR, buf, NULL);
if (err) {
return err;
}
return 0;
}
static int psoc6_bless_hci_init(const struct device *dev)
{
cy_en_ble_api_result_t result;
ARG_UNUSED(dev);
/* Connect BLE interrupt to ISR */
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), psoc6_bless_isr_handler, 0, 0);
/* Registers the generic callback functions. */
Cy_BLE_RegisterEventCallback(psoc6_bless_events_handler);
/* Initializes the PSoC 6 BLESS Controller. */
result = Cy_BLE_InitController(&psoc6_bless_config);
if (result != CY_BLE_SUCCESS) {
LOG_ERR("Failed to init the BLE Controller");
return -EIO;
}
/* Enables the BLESS controller in HCI only mode. */
result = Cy_BLE_EnableHCIModeController();
if (result != CY_BLE_SUCCESS) {
LOG_ERR("Failed to enable the BLE Controller in hci mode");
return -EIO;
}
/* Enables BLE Low-power mode (LPM)*/
Cy_BLE_EnableLowPowerMode();
return 0;
}
static const struct bt_hci_driver_api drv = {
.open = psoc6_bless_open,
.send = psoc6_bless_send,
.setup = psoc6_bless_setup,
};
#define PSOC6_BLESS_DEVICE_INIT(inst) \
static struct psoc6_bless_data psoc6_bless_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, psoc6_bless_hci_init, NULL, &psoc6_bless_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
/* Only one instance supported */
PSOC6_BLESS_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_ifx_psoc6_bless.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,181 |
```c
/* ipm_stm32wb.c - HCI driver for stm32wb shared ram */
/*
*
*/
#define DT_DRV_COMPAT st_stm32wb_rf
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/bluetooth/addr.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/irq.h>
#include "app_conf.h"
#include "stm32_wpan_common.h"
#include "shci.h"
#include "shci_tl.h"
struct hci_data {
bt_hci_recv_t recv;
};
static const struct stm32_pclken clk_cfg[] = STM32_DT_CLOCKS(DT_DRV_INST(0));
#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH * 4 * \
DIVC((sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE), 4))
/* Private variables ---------------------------------------------------------*/
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t
SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t
BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t
HciAclDataBuffer[sizeof(TL_PacketHeader_t) + 5 + 251];
static void syscmd_status_not(SHCI_TL_CmdStatus_t status);
static void sysevt_received(void *pdata);
#include "common/bt_str.h"
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(hci_ipm);
#define STM32WB_C2_LOCK_TIMEOUT K_MSEC(500)
static K_SEM_DEFINE(c2_started, 0, 1);
static K_SEM_DEFINE(ble_sys_wait_cmd_rsp, 0, 1);
static K_SEM_DEFINE(acl_data_ack, 1, 1);
static K_SEM_DEFINE(ipm_busy, 1, 1);
struct aci_set_tx_power {
uint8_t cmd;
uint8_t value[2];
};
struct aci_set_ble_addr {
uint8_t config_offset;
uint8_t length;
uint8_t value[6];
} __packed;
#ifdef CONFIG_BT_HCI_HOST
#define ACI_WRITE_SET_TX_POWER_LEVEL BT_OP(BT_OGF_VS, 0xFC0F)
#define ACI_HAL_WRITE_CONFIG_DATA BT_OP(BT_OGF_VS, 0xFC0C)
#define ACI_HAL_STACK_RESET BT_OP(BT_OGF_VS, 0xFC3B)
#define HCI_CONFIG_DATA_PUBADDR_OFFSET 0
static bt_addr_t bd_addr_udn;
#endif /* CONFIG_BT_HCI_HOST */
/* Rx thread definitions */
K_FIFO_DEFINE(ipm_rx_events_fifo);
static K_KERNEL_STACK_DEFINE(ipm_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE);
static struct k_thread ipm_rx_thread_data;
static bool c2_started_flag;
static void stm32wb_start_ble(uint32_t rf_clock)
{
SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet = {
{ { 0, 0, 0 } }, /**< Header unused */
{ 0, /** pBleBufferAddress not used */
0, /** BleBufferSize not used */
CFG_BLE_NUM_GATT_ATTRIBUTES,
CFG_BLE_NUM_GATT_SERVICES,
CFG_BLE_ATT_VALUE_ARRAY_SIZE,
CFG_BLE_NUM_LINK,
CFG_BLE_DATA_LENGTH_EXTENSION,
CFG_BLE_PREPARE_WRITE_LIST_SIZE,
CFG_BLE_MBLOCK_COUNT,
CFG_BLE_MAX_ATT_MTU,
CFG_BLE_PERIPHERAL_SCA,
CFG_BLE_CENTRAL_SCA,
(rf_clock == STM32_SRC_LSE) ? CFG_BLE_LS_SOURCE : 0,
CFG_BLE_MAX_CONN_EVENT_LENGTH,
CFG_BLE_HSE_STARTUP_TIME,
CFG_BLE_VITERBI_MODE,
CFG_BLE_OPTIONS,
0 }
};
/**
* Starts the BLE Stack on CPU2
*/
SHCI_C2_BLE_Init(&ble_init_cmd_packet);
}
static void sysevt_received(void *pdata)
{
k_sem_give(&c2_started);
}
static void syscmd_status_not(SHCI_TL_CmdStatus_t status)
{
LOG_DBG("status:%d", status);
}
/*
* path_to_url
* Tested on nucleo_wb55rg (stm32wb55rg) BLE stack (v1.2.0)
* Unresolved Resolvable Private Addresses (RPA)
* is reported in the peer_rpa field, and not in the peer address,
* as it should, when this happens the peer address is set to all FFs
* 0A 00 01 08 01 01 FF FF FF FF FF FF 00 00 00 00 00 00 0C AA C5 B3 3D 6B ...
* If such message is passed to HCI core than pairing will essentially fail.
* Solution: Rewrite the event with the RPA in the PEER address field
*/
static void tryfix_event(TL_Evt_t *tev)
{
struct bt_hci_evt_le_meta_event *mev = (void *)&tev->payload;
if (tev->evtcode != BT_HCI_EVT_LE_META_EVENT ||
mev->subevent != BT_HCI_EVT_LE_ENH_CONN_COMPLETE) {
return;
}
struct bt_hci_evt_le_enh_conn_complete *evt =
(void *)((uint8_t *)mev + (sizeof(*mev)));
if (bt_addr_eq(&evt->peer_addr.a, BT_ADDR_NONE)) {
LOG_WRN("Invalid peer addr %s", bt_addr_le_str(&evt->peer_addr));
bt_addr_copy(&evt->peer_addr.a, &evt->peer_rpa);
evt->peer_addr.type = BT_ADDR_LE_RANDOM;
}
}
void TM_EvtReceivedCb(TL_EvtPacket_t *hcievt)
{
k_fifo_put(&ipm_rx_events_fifo, hcievt);
}
static void bt_ipm_rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct hci_data *hci = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
while (true) {
bool discardable = false;
k_timeout_t timeout = K_FOREVER;
static TL_EvtPacket_t *hcievt;
struct net_buf *buf = NULL;
struct bt_hci_acl_hdr acl_hdr;
TL_AclDataSerial_t *acl;
struct bt_hci_evt_le_meta_event *mev;
size_t buf_tailroom;
size_t buf_add_len;
hcievt = k_fifo_get(&ipm_rx_events_fifo, K_FOREVER);
k_sem_take(&ipm_busy, K_FOREVER);
switch (hcievt->evtserial.type) {
case BT_HCI_H4_EVT:
LOG_DBG("EVT: hcievt->evtserial.evt.evtcode: 0x%02x",
hcievt->evtserial.evt.evtcode);
switch (hcievt->evtserial.evt.evtcode) {
case BT_HCI_EVT_VENDOR:
/* Vendor events are currently unsupported */
LOG_ERR("Unknown evtcode type 0x%02x",
hcievt->evtserial.evt.evtcode);
TL_MM_EvtDone(hcievt);
goto end_loop;
default:
mev = (void *)&hcievt->evtserial.evt.payload;
if (hcievt->evtserial.evt.evtcode == BT_HCI_EVT_LE_META_EVENT &&
(mev->subevent == BT_HCI_EVT_LE_ADVERTISING_REPORT)) {
discardable = true;
timeout = K_NO_WAIT;
}
buf = bt_buf_get_evt(
hcievt->evtserial.evt.evtcode,
discardable, timeout);
if (!buf) {
LOG_DBG("Discard adv report due to insufficient buf");
goto end_loop;
}
}
tryfix_event(&hcievt->evtserial.evt);
buf_tailroom = net_buf_tailroom(buf);
buf_add_len = hcievt->evtserial.evt.plen + 2;
if (buf_tailroom < buf_add_len) {
LOG_ERR("Not enough space in buffer %zu/%zu", buf_add_len,
buf_tailroom);
net_buf_unref(buf);
goto end_loop;
}
net_buf_add_mem(buf, &hcievt->evtserial.evt,
buf_add_len);
break;
case BT_HCI_H4_ACL:
acl = &(((TL_AclDataPacket_t *)hcievt)->AclDataSerial);
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
acl_hdr.handle = acl->handle;
acl_hdr.len = acl->length;
LOG_DBG("ACL: handle %x, len %x", acl_hdr.handle, acl_hdr.len);
net_buf_add_mem(buf, &acl_hdr, sizeof(acl_hdr));
buf_tailroom = net_buf_tailroom(buf);
buf_add_len = acl_hdr.len;
if (buf_tailroom < buf_add_len) {
LOG_ERR("Not enough space in buffer %zu/%zu", buf_add_len,
buf_tailroom);
net_buf_unref(buf);
goto end_loop;
}
net_buf_add_mem(buf, (uint8_t *)&acl->acl_data,
buf_add_len);
break;
default:
LOG_ERR("Unknown BT buf type %d", hcievt->evtserial.type);
TL_MM_EvtDone(hcievt);
goto end_loop;
}
TL_MM_EvtDone(hcievt);
hci->recv(dev, buf);
end_loop:
k_sem_give(&ipm_busy);
}
}
static void TM_AclDataAck(void)
{
k_sem_give(&acl_data_ack);
}
void shci_notify_asynch_evt(void *pdata)
{
shci_user_evt_proc();
}
void shci_cmd_resp_release(uint32_t flag)
{
k_sem_give(&ble_sys_wait_cmd_rsp);
}
void shci_cmd_resp_wait(uint32_t timeout)
{
k_sem_take(&ble_sys_wait_cmd_rsp, K_MSEC(timeout));
}
void ipcc_reset(void)
{
LL_C1_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 |
LL_IPCC_CHANNEL_4 | LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
/* Set IPCC default IRQ handlers */
IRQ_CONNECT(IPCC_C1_RX_IRQn, 0, HW_IPCC_Rx_Handler, NULL, 0);
IRQ_CONNECT(IPCC_C1_TX_IRQn, 0, HW_IPCC_Tx_Handler, NULL, 0);
}
void transport_init(void)
{
TL_MM_Config_t tl_mm_config;
TL_BLE_InitConf_t tl_ble_config;
SHCI_TL_HciInitConf_t shci_init_config;
LOG_DBG("BleCmdBuffer: %p", (void *)&BleCmdBuffer);
LOG_DBG("HciAclDataBuffer: %p", (void *)&HciAclDataBuffer);
LOG_DBG("SystemCmdBuffer: %p", (void *)&SystemCmdBuffer);
LOG_DBG("EvtPool: %p", (void *)&EvtPool);
LOG_DBG("SystemSpareEvtBuffer: %p", (void *)&SystemSpareEvtBuffer);
LOG_DBG("BleSpareEvtBuffer: %p", (void *)&BleSpareEvtBuffer);
/**< Reference table initialization */
TL_Init();
/**< System channel initialization */
shci_init_config.p_cmdbuffer = (uint8_t *)&SystemCmdBuffer;
shci_init_config.StatusNotCallBack = syscmd_status_not;
shci_init(sysevt_received, (void *) &shci_init_config);
/**< Memory Manager channel initialization */
tl_mm_config.p_BleSpareEvtBuffer = BleSpareEvtBuffer;
tl_mm_config.p_SystemSpareEvtBuffer = SystemSpareEvtBuffer;
tl_mm_config.p_AsynchEvtPool = EvtPool;
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
TL_MM_Init(&tl_mm_config);
/**< BLE channel initialization */
tl_ble_config.p_cmdbuffer = (uint8_t *)&BleCmdBuffer;
tl_ble_config.p_AclDataBuffer = HciAclDataBuffer;
tl_ble_config.IoBusEvtCallBack = TM_EvtReceivedCb;
tl_ble_config.IoBusAclDataTxAck = TM_AclDataAck;
TL_BLE_Init((void *)&tl_ble_config);
TL_Enable();
}
static int bt_ipm_send(const struct device *dev, struct net_buf *buf)
{
TL_CmdPacket_t *ble_cmd_buff = &BleCmdBuffer;
ARG_UNUSED(dev);
k_sem_take(&ipm_busy, K_FOREVER);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
LOG_DBG("ACL: buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
k_sem_take(&acl_data_ack, K_FOREVER);
net_buf_push_u8(buf, BT_HCI_H4_ACL);
memcpy((void *)
&((TL_AclDataPacket_t *)HciAclDataBuffer)->AclDataSerial,
buf->data, buf->len);
TL_BLE_SendAclData(NULL, 0);
break;
case BT_BUF_CMD:
LOG_DBG("CMD: buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
ble_cmd_buff->cmdserial.type = BT_HCI_H4_CMD;
ble_cmd_buff->cmdserial.cmd.plen = buf->len;
memcpy((void *)&ble_cmd_buff->cmdserial.cmd, buf->data,
buf->len);
TL_BLE_SendCmd(NULL, 0);
break;
default:
k_sem_give(&ipm_busy);
LOG_ERR("Unsupported type");
return -EINVAL;
}
k_sem_give(&ipm_busy);
net_buf_unref(buf);
return 0;
}
#ifdef CONFIG_BT_HCI_HOST
bt_addr_t *bt_get_ble_addr(void)
{
bt_addr_t *bd_addr;
uint32_t udn;
uint32_t company_id;
uint32_t device_id;
/* Get the 64 bit Unique Device Number UID */
/* The UID is used by firmware to derive */
/* 48-bit Device Address EUI-48 */
udn = LL_FLASH_GetUDN();
if (udn != 0xFFFFFFFF) {
/* Get the ST Company ID */
company_id = LL_FLASH_GetSTCompanyID();
/* Get the STM32 Device ID */
device_id = LL_FLASH_GetDeviceID();
bd_addr_udn.val[0] = (uint8_t)(udn & 0x000000FF);
bd_addr_udn.val[1] = (uint8_t)((udn & 0x0000FF00) >> 8);
bd_addr_udn.val[2] = (uint8_t)((udn & 0x00FF0000) >> 16);
bd_addr_udn.val[3] = (uint8_t)device_id;
bd_addr_udn.val[4] = (uint8_t)(company_id & 0x000000FF);
bd_addr_udn.val[5] = (uint8_t)((company_id & 0x0000FF00) >> 8);
bd_addr = &bd_addr_udn;
} else {
bd_addr = NULL;
}
return bd_addr;
}
static int bt_ipm_set_addr(void)
{
bt_addr_t *uid_addr;
struct aci_set_ble_addr *param;
struct net_buf *buf;
int err;
uid_addr = bt_get_ble_addr();
if (!uid_addr) {
return -ENOMSG;
}
buf = bt_hci_cmd_create(ACI_HAL_WRITE_CONFIG_DATA, sizeof(*param));
if (!buf) {
return -ENOBUFS;
}
param = net_buf_add(buf, sizeof(*param));
param->config_offset = HCI_CONFIG_DATA_PUBADDR_OFFSET;
param->length = 6;
param->value[0] = uid_addr->val[0];
param->value[1] = uid_addr->val[1];
param->value[2] = uid_addr->val[2];
param->value[3] = uid_addr->val[3];
param->value[4] = uid_addr->val[4];
param->value[5] = uid_addr->val[5];
err = bt_hci_cmd_send_sync(ACI_HAL_WRITE_CONFIG_DATA, buf, NULL);
if (err) {
return err;
}
return 0;
}
static int bt_ipm_ble_init(void)
{
struct aci_set_tx_power *param;
struct net_buf *buf;
int err;
err = bt_ipm_set_addr();
if (err) {
LOG_ERR("Can't set BLE UID addr");
}
/* Send ACI_WRITE_SET_TX_POWER_LEVEL */
buf = bt_hci_cmd_create(ACI_WRITE_SET_TX_POWER_LEVEL, 3);
if (!buf) {
return -ENOBUFS;
}
param = net_buf_add(buf, sizeof(*param));
param->cmd = 0x0F;
param->value[0] = 0x18;
param->value[1] = 0x01;
err = bt_hci_cmd_send_sync(ACI_WRITE_SET_TX_POWER_LEVEL, buf, NULL);
if (err) {
return err;
}
return 0;
}
#endif /* CONFIG_BT_HCI_HOST */
static int c2_reset(void)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
int err;
if (!device_is_ready(clk)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
err = clock_control_configure(clk, (clock_control_subsys_t) &clk_cfg[1],
NULL);
if (err < 0) {
LOG_ERR("Could not configure RF Wake up clock");
return err;
}
/* HSI48 clock and CLK48 clock source are enabled using the device tree */
#if !STM32_HSI48_ENABLED
/* Deprecated: enable HSI48 using device tree */
#warning Bluetooth IPM requires HSI48 clock to be enabled using device tree
/* Keeping this sequence for legacy: */
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady()) {
}
#endif /* !STM32_HSI48_ENABLED */
err = clock_control_on(clk, (clock_control_subsys_t) &clk_cfg[0]);
if (err < 0) {
LOG_ERR("Could not enable IPCC clock");
return err;
}
/* Take BLE out of reset */
ipcc_reset();
transport_init();
/* Device will let us know when it's ready */
if (k_sem_take(&c2_started, STM32WB_C2_LOCK_TIMEOUT)) {
return -ETIMEDOUT;
}
LOG_DBG("C2 unlocked");
stm32wb_start_ble(clk_cfg[1].bus);
c2_started_flag = true;
return 0;
}
static int bt_ipm_open(const struct device *dev, bt_hci_recv_t recv)
{
struct hci_data *hci = dev->data;
int err;
if (!c2_started_flag) {
/* C2 has been teared down. Reinit required */
SHCI_C2_Reinit();
while (LL_PWR_IsActiveFlag_C2DS() == 0) {
};
err = c2_reset();
if (err) {
return err;
}
}
/* Start RX thread */
k_thread_create(&ipm_rx_thread_data, ipm_rx_stack,
K_KERNEL_STACK_SIZEOF(ipm_rx_stack),
bt_ipm_rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO),
0, K_NO_WAIT);
hci->recv = recv;
LOG_DBG("IPM Channel Open Completed");
return 0;
}
static int bt_ipm_setup(const struct device *dev, const struct bt_hci_setup_params *params)
{
ARG_UNUSED(params);
ARG_UNUSED(dev);
int err;
#ifdef CONFIG_BT_HCI_HOST
err = bt_ipm_ble_init();
if (err) {
return err;
}
#endif /* CONFIG_BT_HCI_HOST */
LOG_DBG("IPM Channel Setup Completed");
return 0;
}
#ifdef CONFIG_BT_HCI_HOST
static int bt_ipm_close(const struct device *dev)
{
struct hci_data *hci = dev->data;
int err;
err = bt_hci_cmd_send_sync(ACI_HAL_STACK_RESET, NULL, NULL);
if (err) {
LOG_ERR("IPM Channel Close Issue");
return err;
}
/* Wait till C2DS set */
while (LL_PWR_IsActiveFlag_C2DS() == 0) {
};
c2_started_flag = false;
k_thread_abort(&ipm_rx_thread_data);
hci->recv = NULL;
LOG_DBG("IPM Channel Close Completed");
return err;
}
#endif /* CONFIG_BT_HCI_HOST */
static const struct bt_hci_driver_api drv = {
.open = bt_ipm_open,
#ifdef CONFIG_BT_HCI_HOST
.close = bt_ipm_close,
#endif
.send = bt_ipm_send,
.setup = bt_ipm_setup,
};
static int _bt_ipm_init(const struct device *dev)
{
int err;
ARG_UNUSED(dev);
err = c2_reset();
if (err) {
return err;
}
return 0;
}
#define HCI_DEVICE_INIT(inst) \
static struct hci_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, _bt_ipm_init, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/ipm_stm32wb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,173 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
if BT_AIROC
config BT_CYW43XX
bool
default y if BT_AIROC && BT_H4
choice AIROC_PART
prompt "Select AIROC part"
config CYW4343W
bool "CYW4343W"
depends on BT_H4
help
Enable Infineon CYW4343W BLE connectivity,
More information about CYW4343W device you can find on
path_to_url
config CYW4373
bool "CYW4373"
depends on BT_H4
help
Enable Infineon CYW4373 BLE connectivity,
More information about CYW4373 device you can find on
path_to_url
config CYW43012
bool "CYW43012"
depends on BT_H4
help
Enable Infineon CYW43012 BLE connectivity,
More information about CYW43012 device you can find on
path_to_url
config CYW43438
bool "CYW43438"
depends on BT_H4
help
Enable Infineon CYW43438 BLE connectivity,
More information about CYW43438 device you can find on
path_to_url
config CYW43439
bool "CYW43439"
depends on BT_H4
help
Enable Infineon CYW43439 BLE connectivity,
More information about CYW43439 device you can find on
path_to_url
config CYW20829
bool "CYW20829"
depends on BT_CYW208XX
help
Enable Infineon CYW20829 BLE connectivity,
More information about CYW20829 device you can find on
path_to_url
config BT_AIROC_CUSTOM
bool "Custom AIROC device/module"
help
Select Custom AIROC device/module. For this option,
user must to provide path to BT firmware HCD file for
custom or vendor AIROC modules in AIROC_CUSTOM_FIRMWARE_HCD_BLOB.
endchoice
choice CYW43012_MODULE
prompt "Select CYW43012 module"
depends on CYW43012
config CYW43012_MURATA_1LV
bool "MURATA-1LV"
help
Murata Type 1LV module based on Infineon CYW43012 combo chipset
which supports Wi-Fi 802.11a/b/g/n + Bluetooth 5.0 BR/EDR/LE
up to 72.2Mbps PHY data rate on Wi-fi and 3Mbps PHY data rate
on Bluetooth. 2Mbps LE PHY is also supported.
Detailed information about Murata Type 1LV module you can find on
path_to_url
endchoice
choice CYW4343W_MODULE
prompt "Select CYW4343W module"
depends on CYW4343W
config CYW4343W_MURATA_1DX
bool "MURATA-1DX"
help
Murata Type 1DX modules based on Infineon CYW4343W combo chipset
which supports Wi-Fi 802.11b/g/n + Bluetooth 5.1 BR/EDR/LE
up to 65Mbps PHY data rate on Wi-fi and 3Mbps PHY data rate
on Bluetooth.
Detailed information about Type 1DX module you can find on
path_to_url
endchoice
choice CYW4373_MODULE
prompt "Select CYW4373 module"
depends on CYW4373
config CYW4373_STERLING_LWB5PLUS
bool "STERLING-LWB5plus"
help
Ezurio Sterling LWB5+ 802.11ac / Bluetooth 5.0 M.2 Carrier Board
(E-Type Key w/ SDIO/UART)
Detailed information about Type Sterling LWB5+ module you can find on
path_to_url
endchoice
choice CYW43439_MODULE
prompt "Select CYW43439 module"
depends on CYW43439
config CYW43439_MURATA_1YN
bool "MURATA_1YN"
help
Murata Type 1YN module based on Infineon CYW43439 combo chipset
which supports Wi-Fi 802.11b/g/n + Bluetooth 5.2 BR/EDR/LE
up to 65Mbps PHY data rate on Wi-fi and 3Mbps PHY data rate on
Bluetooth.
Detailed information about Murata Type 1YN module you can find on
path_to_url
endchoice
if CYW20829
config CYW20829_BT_FW_TX10DBM_POWER
bool "CYW20829_BT_FW_TX10DBM_POWER"
help
Enable 10dBm TX Power variant of CYW20829 FW patch.
choice CYW20829_BT_FW
prompt "Select variant of default CYW20829 BT FW"
default CYW20829_BT_FW_ISOC_TX10 if BT_ISO && CYW20829_BT_FW_TX10DBM_POWER
default CYW20829_BT_FW_ISOC_TX0 if BT_ISO && !CYW20829_BT_FW_TX10DBM_POWER
default CYW20829_BT_FW_PAWR_TX10 if BT_PER_ADV_RSP && CYW20829_BT_FW_TX10DBM_POWER
default CYW20829_BT_FW_PAWR_TX0 if BT_PER_ADV_RSP && !CYW20829_BT_FW_TX10DBM_POWER
default CYW20829_BT_FW_TX10 if CYW20829_BT_FW_TX10DBM_POWER
default CYW20829_BT_FW_TX0
config CYW20829_BT_FW_TX0
bool "CYW20829_BT_FW_TX0"
help
Enable CYW20829 FW patch for 0dBm TX Power.
This configuration should be used with non-PAWR and non-ISOC applications.
config CYW20829_BT_FW_TX10
bool "CYW20829_BT_FW_TX10"
help
Enable CYW20829 FW patch for 10dBm TX Power.
This configuration should be used with non-PAwR and non-ISOC applications.
config CYW20829_BT_FW_PAWR_TX0
bool "CYW20829_BT_FW_PAWR_TX0"
help
Enable CYW20829 FW patch with PAwR support for 0dBm TX Power.
This configuration should be used with PAwR applications.
config CYW20829_BT_FW_PAWR_TX10
bool "CYW20829_BT_FW_PAWR_TX10"
help
Enable CYW20829 FW patch for 10dBm TX Power.
This configuration should be used with PAwR applications.
config CYW20829_BT_FW_ISOC_TX0
bool "CYW20829_BT_FW_ISOC_TX0"
help
Enable CYW20829 FW patch for 0dBm TX Power.
This configuration should be used with ISOC applications.
config CYW20829_BT_FW_ISOC_TX10
bool "CYW20829_BT_FW_ISOC_TX10"
help
Enable CYW20829 FW patch for 10dBm TX Power.
This configuration should be used with ISOC applications.
endchoice
endif # CYW20829
config AIROC_CUSTOM_FIRMWARE_HCD_BLOB
depends on BT_AIROC_CUSTOM
string "Path to user BT firmware HCD file"
help
Path to BT firmware HCD file for custom or vendor CYW43xx modules.
It can be absolute path, or relative from project folder.
# Change size of command lengths. It for vendor commands related to
# firmware downloading.
config BT_BUF_CMD_TX_SIZE
default $(UINT8_MAX)
endif # BT_AIROC
if BT_PSOC6_BLESS
config BT_PSOC6_BLESS_MAX_TX_PAYLOAD
int "Max Tx payload size"
range 27 251
default 27
config BT_PSOC6_BLESS_MAX_RX_PAYLOAD
int "Max Rx payload size"
range 27 251
default 27
endif # BT_PSOC6_BLESS
``` | /content/code_sandbox/drivers/bluetooth/hci/Kconfig.infineon | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,740 |
```c
/*
*
*/
/**
* @brief Ambiq Apollox Blue SoC extended driver for SPI based HCI.
*/
#define DT_DRV_COMPAT ambiq_bt_hci_spi
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/bluetooth/hci_raw.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_apollox_driver);
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_ambiq.h>
#include <am_mcu_apollo.h>
#include "apollox_blue.h"
#if (CONFIG_SOC_SERIES_APOLLO4X)
#include "am_devices_cooper.h"
#elif (CONFIG_SOC_SERIES_APOLLO3X)
#include "am_apollo3_bt_support.h"
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
#define HCI_SPI_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(ambiq_bt_hci_spi)
#define SPI_DEV_NODE DT_BUS(HCI_SPI_NODE)
#define CLK_32M_NODE DT_NODELABEL(xo32m)
#define CLK_32K_NODE DT_NODELABEL(xo32k)
/* Command/response for SPI operation */
#define SPI_WRITE 0x80
#define SPI_READ 0x04
#define READY_BYTE0 0x68
#define READY_BYTE1 0xA8
/* Maximum attempts of SPI write */
#define SPI_WRITE_TIMEOUT 200
#define SPI_MAX_RX_MSG_LEN 258
#if (CONFIG_SOC_SERIES_APOLLO4X)
static const struct gpio_dt_spec irq_gpio = GPIO_DT_SPEC_GET(HCI_SPI_NODE, irq_gpios);
static const struct gpio_dt_spec rst_gpio = GPIO_DT_SPEC_GET(HCI_SPI_NODE, reset_gpios);
static const struct gpio_dt_spec cs_gpio = GPIO_DT_SPEC_GET(SPI_DEV_NODE, cs_gpios);
static const struct gpio_dt_spec clkreq_gpio = GPIO_DT_SPEC_GET(HCI_SPI_NODE, clkreq_gpios);
static struct gpio_callback irq_gpio_cb;
static struct gpio_callback clkreq_gpio_cb;
static const struct device *clk32m_dev = DEVICE_DT_GET(CLK_32M_NODE);
static const struct device *clk32k_dev = DEVICE_DT_GET(CLK_32K_NODE);
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
extern void bt_packet_irq_isr(const struct device *unused1, struct gpio_callback *unused2,
uint32_t unused3);
void bt_apollo_rcv_isr_preprocess(void)
{
#if (CONFIG_SOC_SERIES_APOLLO3X)
am_apollo3_bt_isr_pre();
#endif /* CONFIG_SOC_SERIES_APOLLO3X */
}
#if (CONFIG_SOC_SERIES_APOLLO4X)
static bool irq_pin_state(void)
{
int pin_state;
pin_state = gpio_pin_get_dt(&irq_gpio);
LOG_DBG("IRQ Pin: %d", pin_state);
return pin_state > 0;
}
static bool clkreq_pin_state(void)
{
int pin_state;
pin_state = gpio_pin_get_dt(&clkreq_gpio);
LOG_DBG("CLKREQ Pin: %d", pin_state);
return pin_state > 0;
}
static void bt_clkreq_isr(const struct device *unused1, struct gpio_callback *unused2,
uint32_t unused3)
{
if (clkreq_pin_state()) {
/* Enable XO32MHz */
clock_control_on(clk32m_dev,
(clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_HFXTAL_BLE);
gpio_pin_interrupt_configure_dt(&clkreq_gpio, GPIO_INT_EDGE_FALLING);
} else {
/* Disable XO32MHz */
clock_control_off(clk32m_dev,
(clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_HFXTAL_BLE);
gpio_pin_interrupt_configure_dt(&clkreq_gpio, GPIO_INT_EDGE_RISING);
}
}
static void bt_apollo_controller_ready_wait(void)
{
/* The CS pin is used to wake up the controller as well. If the controller is not ready
* to receive the SPI packet, need to inactivate the CS at first and reconfigure the pin
* to CS function again before next sending attempt.
*/
gpio_pin_configure_dt(&cs_gpio, GPIO_OUTPUT_INACTIVE);
k_busy_wait(200);
PINCTRL_DT_DEFINE(SPI_DEV_NODE);
pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(SPI_DEV_NODE), PINCTRL_STATE_DEFAULT);
k_busy_wait(2000);
}
static void bt_apollo_controller_reset(void)
{
/* Reset the controller*/
gpio_pin_set_dt(&rst_gpio, 1);
/* Take controller out of reset */
k_sleep(K_MSEC(10));
gpio_pin_set_dt(&rst_gpio, 0);
/* Give the controller some time to boot */
k_sleep(K_MSEC(500));
}
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
int bt_apollo_spi_send(uint8_t *data, uint16_t len, bt_spi_transceive_fun transceive)
{
int ret = -ENOTSUP;
#if (CONFIG_SOC_SERIES_APOLLO4X)
uint8_t command[1] = {SPI_WRITE};
uint8_t response[2] = {0, 0};
uint16_t fail_count = 0;
do {
/* Check if the controller is ready to receive the HCI packets. */
ret = transceive(command, 1, response, 2);
if ((response[0] != READY_BYTE0) || (response[1] != READY_BYTE1) || ret) {
bt_apollo_controller_ready_wait();
} else {
/* Transmit the message */
ret = transceive(data, len, NULL, 0);
if (ret) {
LOG_ERR("SPI write error %d", ret);
}
break;
}
} while (fail_count++ < SPI_WRITE_TIMEOUT);
#elif (CONFIG_SOC_SERIES_APOLLO3X)
ret = transceive(data, len, NULL, 0);
if ((ret) && (ret != AM_HAL_BLE_STATUS_SPI_NOT_READY)) {
LOG_ERR("SPI write error %d", ret);
}
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
return ret;
}
int bt_apollo_spi_rcv(uint8_t *data, uint16_t *len, bt_spi_transceive_fun transceive)
{
int ret = -ENOTSUP;
uint8_t response[2] = {0, 0};
uint16_t read_size = 0;
do {
#if (CONFIG_SOC_SERIES_APOLLO4X)
/* Skip if the IRQ pin is not in high state */
if (!irq_pin_state()) {
ret = -1;
break;
}
/* Check the available packet bytes */
uint8_t command[1] = {SPI_READ};
ret = transceive(command, 1, response, 2);
if (ret) {
break;
}
#elif (CONFIG_SOC_SERIES_APOLLO3X)
/* Skip if the IRQ bit is not set */
if (!BLEIFn(0)->BSTATUS_b.BLEIRQ) {
ret = -1;
break;
}
/* Check the available packet bytes */
ret = transceive(NULL, 0, response, 2);
if (ret) {
break;
}
#else
break;
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
/* Check if the read size is acceptable */
read_size = (uint16_t)(response[0] | response[1] << 8);
if ((read_size == 0) || (read_size > SPI_MAX_RX_MSG_LEN)) {
ret = -1;
break;
}
*len = read_size;
/* Read the HCI data from controller */
ret = transceive(NULL, 0, data, read_size);
if (ret) {
LOG_ERR("SPI read error %d", ret);
break;
}
} while (0);
return ret;
}
bool bt_apollo_vnd_rcv_ongoing(uint8_t *data, uint16_t len)
{
#if (CONFIG_SOC_SERIES_APOLLO4X)
/* The vendor specific handshake command/response is incompatible with
* standard Bluetooth HCI format, need to handle the received packets
* specifically.
*/
if (am_devices_cooper_get_initialize_state() != AM_DEVICES_COOPER_STATE_INITIALIZED) {
am_devices_cooper_handshake_recv(data, len);
return true;
} else {
return false;
}
#else
return false;
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
}
int bt_hci_transport_setup(const struct device *dev)
{
ARG_UNUSED(dev);
int ret = 0;
#if (CONFIG_SOC_SERIES_APOLLO4X)
/* Configure the XO32MHz and XO32kHz clocks.*/
clock_control_configure(clk32k_dev, NULL, NULL);
clock_control_configure(clk32m_dev, NULL, NULL);
/* Enable XO32kHz for Controller */
clock_control_on(clk32k_dev, (clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_LFXTAL);
/* Enable XO32MHz for Controller */
clock_control_on(clk32m_dev, (clock_control_subsys_t)CLOCK_CONTROL_AMBIQ_TYPE_HFXTAL_BLE);
/* Configure RST pin and hold BLE in Reset */
ret = gpio_pin_configure_dt(&rst_gpio, GPIO_OUTPUT_ACTIVE);
if (ret) {
return ret;
}
/* Configure IRQ pin and register the callback */
ret = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
if (ret) {
return ret;
}
gpio_init_callback(&irq_gpio_cb, bt_packet_irq_isr, BIT(irq_gpio.pin));
ret = gpio_add_callback(irq_gpio.port, &irq_gpio_cb);
if (ret) {
return ret;
}
/* Configure CLKREQ pin and register the callback */
ret = gpio_pin_configure_dt(&clkreq_gpio, GPIO_INPUT);
if (ret) {
return ret;
}
gpio_init_callback(&clkreq_gpio_cb, bt_clkreq_isr, BIT(clkreq_gpio.pin));
ret = gpio_add_callback(clkreq_gpio.port, &clkreq_gpio_cb);
if (ret) {
return ret;
}
/* Configure the interrupt edge for CLKREQ pin */
gpio_pin_interrupt_configure_dt(&clkreq_gpio, GPIO_INT_EDGE_RISING);
/* Take controller out of reset */
k_sleep(K_MSEC(10));
gpio_pin_set_dt(&rst_gpio, 0);
/* Give the controller some time to boot */
k_sleep(K_MSEC(500));
/* Configure the interrupt edge for IRQ pin */
gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_RISING);
#elif (CONFIG_SOC_SERIES_APOLLO3X)
IRQ_CONNECT(DT_IRQN(SPI_DEV_NODE), DT_IRQ(SPI_DEV_NODE, priority), bt_packet_irq_isr, 0, 0);
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
return ret;
}
int bt_apollo_controller_init(spi_transmit_fun transmit)
{
int ret = 0;
#if (CONFIG_SOC_SERIES_APOLLO4X)
am_devices_cooper_callback_t cb = {
.write = transmit,
.reset = bt_apollo_controller_reset,
};
/* Initialize the BLE controller */
ret = am_devices_cooper_init(&cb);
if (ret == AM_DEVICES_COOPER_STATUS_SUCCESS) {
am_devices_cooper_set_initialize_state(AM_DEVICES_COOPER_STATE_INITIALIZED);
LOG_INF("BT controller initialized");
} else {
am_devices_cooper_set_initialize_state(AM_DEVICES_COOPER_STATE_INITIALIZE_FAIL);
LOG_ERR("BT controller initialization fail");
}
#elif (CONFIG_SOC_SERIES_APOLLO3X)
ret = am_apollo3_bt_controller_init();
if (ret == AM_HAL_STATUS_SUCCESS) {
LOG_INF("BT controller initialized");
} else {
LOG_ERR("BT controller initialization fail");
}
irq_enable(DT_IRQN(SPI_DEV_NODE));
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
return ret;
}
#if (CONFIG_SOC_SERIES_APOLLO4X)
static int bt_apollo_set_nvds(void)
{
int ret;
struct net_buf *buf;
#if defined(CONFIG_BT_HCI_RAW)
struct bt_hci_cmd_hdr hdr;
hdr.opcode = sys_cpu_to_le16(HCI_VSC_UPDATE_NVDS_CFG_CMD_OPCODE);
hdr.param_len = HCI_VSC_UPDATE_NVDS_CFG_CMD_LENGTH;
buf = bt_buf_get_tx(BT_BUF_CMD, K_NO_WAIT, &hdr, sizeof(hdr));
if (!buf) {
return -ENOBUFS;
}
net_buf_add_mem(buf, &am_devices_cooper_nvds[0], HCI_VSC_UPDATE_NVDS_CFG_CMD_LENGTH);
ret = bt_send(buf);
if (!ret) {
/* Give some time to make NVDS take effect in BLE controller */
k_sleep(K_MSEC(5));
/* Need to send reset command to make the NVDS take effect */
hdr.opcode = sys_cpu_to_le16(BT_HCI_OP_RESET);
hdr.param_len = 0;
buf = bt_buf_get_tx(BT_BUF_CMD, K_NO_WAIT, &hdr, sizeof(hdr));
if (!buf) {
return -ENOBUFS;
}
ret = bt_send(buf);
}
#else
uint8_t *p;
buf = bt_hci_cmd_create(HCI_VSC_UPDATE_NVDS_CFG_CMD_OPCODE,
HCI_VSC_UPDATE_NVDS_CFG_CMD_LENGTH);
if (!buf) {
return -ENOBUFS;
}
p = net_buf_add(buf, HCI_VSC_UPDATE_NVDS_CFG_CMD_LENGTH);
memcpy(p, &am_devices_cooper_nvds[0], HCI_VSC_UPDATE_NVDS_CFG_CMD_LENGTH);
ret = bt_hci_cmd_send_sync(HCI_VSC_UPDATE_NVDS_CFG_CMD_OPCODE, buf, NULL);
if (!ret) {
/* Give some time to make NVDS take effect in BLE controller */
k_sleep(K_MSEC(5));
}
#endif /* defined(CONFIG_BT_HCI_RAW) */
return ret;
}
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
int bt_apollo_vnd_setup(void)
{
int ret = 0;
#if (CONFIG_SOC_SERIES_APOLLO4X)
/* Set the NVDS parameters to BLE controller */
ret = bt_apollo_set_nvds();
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
return ret;
}
int bt_apollo_dev_init(void)
{
#if (CONFIG_SOC_SERIES_APOLLO4X)
if (!gpio_is_ready_dt(&irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&rst_gpio)) {
LOG_ERR("Reset GPIO device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&clkreq_gpio)) {
LOG_ERR("CLKREQ GPIO device not ready");
return -ENODEV;
}
#endif /* CONFIG_SOC_SERIES_APOLLO4X */
return 0;
}
``` | /content/code_sandbox/drivers/bluetooth/hci/apollox_blue.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,259 |
```c
/* hci_spi_st.c - STMicroelectronics HCI SPI Bluetooth driver */
/*
*
*/
#if defined(CONFIG_DT_HAS_ST_HCI_SPI_V1_ENABLED)
#define DT_DRV_COMPAT st_hci_spi_v1
#elif defined(CONFIG_DT_HAS_ST_HCI_SPI_V2_ENABLED)
#define DT_DRV_COMPAT st_hci_spi_v2
#endif /* CONFIG_DT_HAS_ST_HCI_SPI_V1_ENABLED */
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/bluetooth/hci_raw.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_driver);
/* ST Proprietary extended event */
#define HCI_EXT_EVT 0x82
/* Special Values */
#define SPI_WRITE 0x0A
#define SPI_READ 0x0B
#define READY_NOW 0x02
#define EVT_BLUE_INITIALIZED 0x01
#define FW_STARTED_PROPERLY 0X01
/* Offsets */
#define STATUS_HEADER_READY 0
#define STATUS_HEADER_TOREAD 3
#define STATUS_HEADER_TOWRITE 1
#define PACKET_TYPE 0
#define EVT_HEADER_TYPE 0
#define EVT_HEADER_EVENT 1
#define EVT_HEADER_SIZE 2
#define EVT_LE_META_SUBEVENT 3
#define EVT_VENDOR_CODE_LSB 3
#define EVT_VENDOR_CODE_MSB 4
#define REASON_CODE 5
#define CMD_OGF 1
#define CMD_OCF 2
/* packet type (1) + opcode (2) + Parameter Total Length (1) + max parameter length (255) */
#define SPI_MAX_MSG_LEN 259
/* Single byte header denoting the buffer type */
#define H4_HDR_SIZE 1
/* Maximum L2CAP MTU that can fit in a single packet */
#define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
#if CONFIG_BT_L2CAP_TX_MTU > MAX_MTU
#warning CONFIG_BT_L2CAP_TX_MTU is too large and can result in packets that cannot \
be transmitted across this HCI link
#endif /* CONFIG_BT_L2CAP_TX_MTU > MAX_MTU */
static uint8_t __noinit rxmsg[SPI_MAX_MSG_LEN];
static uint8_t __noinit txmsg[SPI_MAX_MSG_LEN];
static const struct gpio_dt_spec irq_gpio = GPIO_DT_SPEC_INST_GET(0, irq_gpios);
static const struct gpio_dt_spec rst_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios);
static struct gpio_callback gpio_cb;
static K_SEM_DEFINE(sem_initialised, 0, 1);
static K_SEM_DEFINE(sem_request, 0, 1);
static K_SEM_DEFINE(sem_busy, 1, 1);
static K_KERNEL_STACK_DEFINE(spi_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE);
static struct k_thread spi_rx_thread_data;
#define BLUENRG_ACI_WRITE_CONFIG_DATA BT_OP(BT_OGF_VS, 0x000C)
#define BLUENRG_CONFIG_PUBADDR_OFFSET 0x00
#define BLUENRG_CONFIG_PUBADDR_LEN 0x06
#define BLUENRG_CONFIG_LL_ONLY_OFFSET 0x2C
#define BLUENRG_CONFIG_LL_ONLY_LEN 0x01
struct bt_spi_data {
bt_hci_recv_t recv;
};
static const struct spi_dt_spec bus = SPI_DT_SPEC_INST_GET(
0, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8) | SPI_LOCK_ON, 0);
static struct spi_buf spi_tx_buf;
static struct spi_buf spi_rx_buf;
static const struct spi_buf_set spi_tx = {
.buffers = &spi_tx_buf,
.count = 1
};
static const struct spi_buf_set spi_rx = {
.buffers = &spi_rx_buf,
.count = 1
};
struct bt_hci_ext_evt_hdr {
uint8_t evt;
uint16_t len;
} __packed;
int bluenrg_bt_reset(bool updater_mode)
{
int err = 0;
/* Assert reset */
if (!updater_mode) {
gpio_pin_set_dt(&rst_gpio, 1);
k_sleep(K_MSEC(DT_INST_PROP_OR(0, reset_assert_duration_ms, 0)));
gpio_pin_set_dt(&rst_gpio, 0);
} else {
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2)
return -ENOTSUP;
#else /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
gpio_pin_set_dt(&rst_gpio, 1);
gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_DISABLE);
/* Configure IRQ pin as output and force it high */
err = gpio_pin_configure_dt(&irq_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
return err;
}
/* Add reset delay and release reset */
k_sleep(K_MSEC(DT_INST_PROP_OR(0, reset_assert_duration_ms, 0)));
gpio_pin_set_dt(&rst_gpio, 0);
/* Give firmware some time to read the IRQ high */
k_sleep(K_MSEC(5));
gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
/* Reconfigure IRQ pin as input */
err = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
if (err) {
return err;
}
/* Emulate possibly missed rising edge IRQ by signaling the IRQ semaphore */
k_sem_give(&sem_request);
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2) */
}
return err;
}
static inline int bt_spi_transceive(void *tx, uint32_t tx_len,
void *rx, uint32_t rx_len)
{
spi_tx_buf.buf = tx;
spi_tx_buf.len = (size_t)tx_len;
spi_rx_buf.buf = rx;
spi_rx_buf.len = (size_t)rx_len;
return spi_transceive_dt(&bus, &spi_tx, &spi_rx);
}
static inline uint16_t bt_spi_get_cmd(uint8_t *msg)
{
return (msg[CMD_OCF] << 8) | msg[CMD_OGF];
}
static inline uint16_t bt_spi_get_evt(uint8_t *msg)
{
return (msg[EVT_VENDOR_CODE_MSB] << 8) | msg[EVT_VENDOR_CODE_LSB];
}
static void bt_spi_isr(const struct device *unused1,
struct gpio_callback *unused2,
uint32_t unused3)
{
LOG_DBG("");
k_sem_give(&sem_request);
}
static bool bt_spi_handle_vendor_evt(uint8_t *msg)
{
bool handled = false;
uint8_t reset_reason;
switch (bt_spi_get_evt(msg)) {
case EVT_BLUE_INITIALIZED: {
reset_reason = msg[REASON_CODE];
if (reset_reason == FW_STARTED_PROPERLY) {
k_sem_give(&sem_initialised);
#if defined(CONFIG_BT_BLUENRG_ACI)
handled = true;
#endif
}
}
default:
break;
}
return handled;
}
#define IS_IRQ_HIGH gpio_pin_get_dt(&irq_gpio)
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1)
/* Define a limit when reading IRQ high */
#define IRQ_HIGH_MAX_READ 15
/* On BlueNRG-MS, host is expected to read */
/* as long as IRQ pin is high */
#define READ_CONDITION IS_IRQ_HIGH
static void release_cs(bool data_transaction)
{
ARG_UNUSED(data_transaction);
spi_release_dt(&bus);
}
static int bt_spi_get_header(uint8_t op, uint16_t *size)
{
uint8_t header_master[5] = {op, 0, 0, 0, 0};
uint8_t header_slave[5];
uint8_t size_offset, attempts;
int ret;
if (op == SPI_READ) {
if (!IS_IRQ_HIGH) {
*size = 0;
return 0;
}
size_offset = STATUS_HEADER_TOREAD;
} else if (op == SPI_WRITE) {
size_offset = STATUS_HEADER_TOWRITE;
} else {
return -EINVAL;
}
attempts = IRQ_HIGH_MAX_READ;
do {
if (op == SPI_READ) {
/* Keep checking that IRQ is still high, if we need to read */
if (!IS_IRQ_HIGH) {
*size = 0;
return 0;
}
}
/* Make sure CS is raised before a new attempt */
gpio_pin_set_dt(&bus.config.cs.gpio, 0);
ret = bt_spi_transceive(header_master, 5, header_slave, 5);
if (ret) {
/* SPI transaction failed */
break;
}
*size = (header_slave[STATUS_HEADER_READY] == READY_NOW) ?
header_slave[size_offset] : 0;
attempts--;
} while ((*size == 0) && attempts);
return ret;
}
#elif DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2)
#define READ_CONDITION false
static void release_cs(bool data_transaction)
{
/* Consume possible event signals */
while (k_sem_take(&sem_request, K_NO_WAIT) == 0) {
}
if (data_transaction) {
/* Wait for IRQ to become low only when data phase has been performed */
while (IS_IRQ_HIGH) {
}
}
gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
spi_release_dt(&bus);
}
static int bt_spi_get_header(uint8_t op, uint16_t *size)
{
uint8_t header_master[5] = {op, 0, 0, 0, 0};
uint8_t header_slave[5];
uint16_t cs_delay;
uint8_t size_offset;
int ret;
if (op == SPI_READ) {
if (!IS_IRQ_HIGH) {
*size = 0;
return 0;
}
cs_delay = 0;
size_offset = STATUS_HEADER_TOREAD;
} else if (op == SPI_WRITE) {
/* To make sure we have a minimum delay from previous release cs */
cs_delay = 100;
size_offset = STATUS_HEADER_TOWRITE;
} else {
return -EINVAL;
}
if (cs_delay) {
k_sleep(K_USEC(cs_delay));
}
/* Perform a zero byte SPI transaction to acquire the SPI lock and lower CS
* while waiting for IRQ to be raised
*/
bt_spi_transceive(header_master, 0, header_slave, 0);
gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_DISABLE);
/* Wait up to a maximum time of 100 ms */
if (!WAIT_FOR(IS_IRQ_HIGH, 100000, k_usleep(100))) {
LOG_ERR("IRQ pin did not raise");
return -EIO;
}
ret = bt_spi_transceive(header_master, 5, header_slave, 5);
*size = header_slave[size_offset] | (header_slave[size_offset + 1] << 8);
return ret;
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
#if defined(CONFIG_BT_BLUENRG_ACI)
static int bt_spi_send_aci_config(uint8_t offset, const uint8_t *value, size_t value_len)
{
struct net_buf *buf;
uint8_t *cmd_data;
size_t data_len = 2 + value_len;
#if defined(CONFIG_BT_HCI_RAW)
struct bt_hci_cmd_hdr hdr;
hdr.opcode = sys_cpu_to_le16(BLUENRG_ACI_WRITE_CONFIG_DATA);
hdr.param_len = data_len;
buf = bt_buf_get_tx(BT_BUF_CMD, K_NO_WAIT, &hdr, sizeof(hdr));
#else
buf = bt_hci_cmd_create(BLUENRG_ACI_WRITE_CONFIG_DATA, data_len);
#endif /* CONFIG_BT_HCI_RAW */
if (!buf) {
return -ENOBUFS;
}
cmd_data = net_buf_add(buf, data_len);
cmd_data[0] = offset;
cmd_data[1] = value_len;
memcpy(&cmd_data[2], value, value_len);
#if defined(CONFIG_BT_HCI_RAW)
return bt_send(buf);
#else
return bt_hci_cmd_send(BLUENRG_ACI_WRITE_CONFIG_DATA, buf);
#endif /* CONFIG_BT_HCI_RAW */
}
#if !defined(CONFIG_BT_HCI_RAW)
static int bt_spi_bluenrg_setup(const struct device *dev,
const struct bt_hci_setup_params *params)
{
int ret;
const bt_addr_t *addr = ¶ms->public_addr;
/* force BlueNRG to be on controller mode */
uint8_t data = 1;
bt_spi_send_aci_config(BLUENRG_CONFIG_LL_ONLY_OFFSET, &data, 1);
if (!bt_addr_eq(addr, BT_ADDR_NONE) && !bt_addr_eq(addr, BT_ADDR_ANY)) {
ret = bt_spi_send_aci_config(
BLUENRG_CONFIG_PUBADDR_OFFSET,
addr->val, sizeof(addr->val));
if (ret != 0) {
LOG_ERR("Failed to set BlueNRG public address (%d)", ret);
return ret;
}
}
return 0;
}
#endif /* !CONFIG_BT_HCI_RAW */
#endif /* CONFIG_BT_BLUENRG_ACI */
static int bt_spi_rx_buf_construct(uint8_t *msg, struct net_buf **bufp, uint16_t size)
{
bool discardable = false;
k_timeout_t timeout = K_FOREVER;
struct bt_hci_acl_hdr acl_hdr;
/* persistent variable to keep packet length in case the HCI packet is split in
* multiple SPI transactions
*/
static uint16_t len;
struct net_buf *buf = *bufp;
int ret = 0;
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1)
if (buf) {
/* Buffer already allocated, waiting to complete event reception */
net_buf_add_mem(buf, msg, MIN(size, len - buf->len));
if (buf->len >= len) {
return 0;
} else {
return -EINPROGRESS;
}
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
switch (msg[PACKET_TYPE]) {
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2)
case HCI_EXT_EVT:
struct bt_hci_ext_evt_hdr *evt = (struct bt_hci_ext_evt_hdr *) (msg + 1);
struct bt_hci_evt_hdr *evt2 = (struct bt_hci_evt_hdr *) (msg + 1);
if (sys_le16_to_cpu(evt->len) > 0xff) {
return -ENOMEM;
}
/* Use memmove instead of memcpy due to buffer overlapping */
memmove(msg + (1 + sizeof(*evt2)), msg + (1 + sizeof(*evt)), evt2->len);
/* Manage event as regular BT_HCI_H4_EVT */
__fallthrough;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2) */
case BT_HCI_H4_EVT:
switch (msg[EVT_HEADER_EVENT]) {
case BT_HCI_EVT_VENDOR:
/* Run event through interface handler */
if (bt_spi_handle_vendor_evt(msg)) {
return -ECANCELED;
}
/* Event has not yet been handled */
__fallthrough;
default:
if (msg[EVT_HEADER_EVENT] == BT_HCI_EVT_LE_META_EVENT &&
(msg[EVT_LE_META_SUBEVENT] == BT_HCI_EVT_LE_ADVERTISING_REPORT)) {
discardable = true;
timeout = K_NO_WAIT;
}
buf = bt_buf_get_evt(msg[EVT_HEADER_EVENT],
discardable, timeout);
if (!buf) {
LOG_DBG("Discard adv report due to insufficient buf");
return -ENOMEM;
}
}
len = sizeof(struct bt_hci_evt_hdr) + msg[EVT_HEADER_SIZE];
if (len > net_buf_tailroom(buf)) {
LOG_ERR("Event too long: %d", len);
net_buf_unref(buf);
return -ENOMEM;
}
/* Skip the first byte (HCI packet indicator) */
size = size - 1;
net_buf_add_mem(buf, &msg[1], size);
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1)
if (size < len) {
ret = -EINPROGRESS;
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
break;
case BT_HCI_H4_ACL:
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
memcpy(&acl_hdr, &msg[1], sizeof(acl_hdr));
len = sizeof(acl_hdr) + sys_le16_to_cpu(acl_hdr.len);
if (len > net_buf_tailroom(buf)) {
LOG_ERR("ACL too long: %d", len);
net_buf_unref(buf);
return -ENOMEM;
}
net_buf_add_mem(buf, &msg[1], len);
break;
#if defined(CONFIG_BT_ISO)
case BT_HCI_H4_ISO:
struct bt_hci_iso_hdr iso_hdr;
buf = bt_buf_get_rx(BT_BUF_ISO_IN, timeout);
if (buf) {
memcpy(&iso_hdr, &msg[1], sizeof(iso_hdr));
len = sizeof(iso_hdr) + bt_iso_hdr_len(sys_le16_to_cpu(iso_hdr.len));
} else {
LOG_ERR("No available ISO buffers!");
return -ENOMEM;
}
if (len > net_buf_tailroom(buf)) {
LOG_ERR("ISO too long: %d", len);
net_buf_unref(buf);
return -ENOMEM;
}
net_buf_add_mem(buf, &msg[1], len);
break;
#endif /* CONFIG_BT_ISO */
default:
LOG_ERR("Unknown BT buf type %d", msg[0]);
return -ENOTSUP;
}
*bufp = buf;
return ret;
}
static void bt_spi_rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct bt_spi_data *hci = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct net_buf *buf = NULL;
uint16_t size = 0U;
int ret;
(void)memset(&txmsg, 0xFF, SPI_MAX_MSG_LEN);
while (true) {
/* Wait for interrupt pin to be active */
k_sem_take(&sem_request, K_FOREVER);
LOG_DBG("");
do {
/* Wait for SPI bus to be available */
k_sem_take(&sem_busy, K_FOREVER);
ret = bt_spi_get_header(SPI_READ, &size);
/* Read data */
if (ret == 0 && size != 0) {
ret = bt_spi_transceive(&txmsg, size, &rxmsg, size);
}
release_cs(size > 0);
k_sem_give(&sem_busy);
if (ret || size == 0) {
if (ret) {
LOG_ERR("Error %d", ret);
}
continue;
}
LOG_HEXDUMP_DBG(rxmsg, size, "SPI RX");
/* Construct net_buf from SPI data */
ret = bt_spi_rx_buf_construct(rxmsg, &buf, size);
if (!ret) {
/* Handle the received HCI data */
hci->recv(dev, buf);
buf = NULL;
}
} while (READ_CONDITION);
}
}
static int bt_spi_send(const struct device *dev, struct net_buf *buf)
{
uint16_t size;
uint8_t rx_first[1];
int ret;
uint8_t *data_ptr;
uint16_t remaining_bytes;
LOG_DBG("");
/* Buffer needs an additional byte for type */
if (buf->len >= SPI_MAX_MSG_LEN) {
LOG_ERR("Message too long (%d)", buf->len);
return -EINVAL;
}
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
net_buf_push_u8(buf, BT_HCI_H4_ACL);
break;
case BT_BUF_CMD:
net_buf_push_u8(buf, BT_HCI_H4_CMD);
break;
#if defined(CONFIG_BT_ISO)
case BT_BUF_ISO_OUT:
net_buf_push_u8(buf, BT_HCI_H4_ISO);
break;
#endif /* CONFIG_BT_ISO */
default:
LOG_ERR("Unsupported type");
return -EINVAL;
}
/* Wait for SPI bus to be available */
k_sem_take(&sem_busy, K_FOREVER);
data_ptr = buf->data;
remaining_bytes = buf->len;
do {
ret = bt_spi_get_header(SPI_WRITE, &size);
size = MIN(remaining_bytes, size);
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2)
if (size < remaining_bytes) {
LOG_WRN("Unable to write full data, skipping");
size = 0;
ret = -ECANCELED;
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v2) */
if (!ret) {
/* Transmit the message */
ret = bt_spi_transceive(data_ptr, size, rx_first, 1);
}
remaining_bytes -= size;
data_ptr += size;
} while (remaining_bytes > 0 && !ret);
release_cs(size > 0);
k_sem_give(&sem_busy);
if (ret) {
LOG_ERR("Error %d", ret);
return ret;
}
LOG_HEXDUMP_DBG(buf->data, buf->len, "SPI TX");
#if DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1)
/*
* Since a RESET has been requested, the chip will now restart.
* Unfortunately the BlueNRG will reply with "reset received" but
* since it does not send back a NOP, we have no way to tell when the
* RESET has actually taken place. Instead, we use the vendor command
* EVT_BLUE_INITIALIZED as an indication that it is safe to proceed.
*/
if (bt_spi_get_cmd(buf->data) == BT_HCI_OP_RESET) {
k_sem_take(&sem_initialised, K_FOREVER);
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
net_buf_unref(buf);
return ret;
}
static int bt_spi_open(const struct device *dev, bt_hci_recv_t recv)
{
struct bt_spi_data *hci = dev->data;
int err;
/* Configure RST pin and hold BLE in Reset */
err = gpio_pin_configure_dt(&rst_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
return err;
}
/* Configure IRQ pin and the IRQ call-back/handler */
err = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
if (err) {
return err;
}
gpio_init_callback(&gpio_cb, bt_spi_isr, BIT(irq_gpio.pin));
err = gpio_add_callback(irq_gpio.port, &gpio_cb);
if (err) {
return err;
}
/* Enable the interrupt line */
err = gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (err) {
return err;
}
hci->recv = recv;
/* Take BLE out of reset */
k_sleep(K_MSEC(DT_INST_PROP_OR(0, reset_assert_duration_ms, 0)));
gpio_pin_set_dt(&rst_gpio, 0);
/* Start RX thread */
k_thread_create(&spi_rx_thread_data, spi_rx_stack,
K_KERNEL_STACK_SIZEOF(spi_rx_stack),
bt_spi_rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO),
0, K_NO_WAIT);
/* Device will let us know when it's ready */
k_sem_take(&sem_initialised, K_FOREVER);
#if defined(CONFIG_BT_HCI_RAW) && defined(CONFIG_BT_BLUENRG_ACI)
/* force BlueNRG to be on controller mode */
uint8_t data = 1;
bt_spi_send_aci_config(BLUENRG_CONFIG_LL_ONLY_OFFSET, &data, 1);
#endif /* CONFIG_BT_HCI_RAW && CONFIG_BT_BLUENRG_ACI */
return 0;
}
static const struct bt_hci_driver_api drv = {
#if defined(CONFIG_BT_BLUENRG_ACI) && !defined(CONFIG_BT_HCI_RAW)
.setup = bt_spi_bluenrg_setup,
#endif /* CONFIG_BT_BLUENRG_ACI && !CONFIG_BT_HCI_RAW */
.open = bt_spi_open,
.send = bt_spi_send,
};
static int bt_spi_init(const struct device *dev)
{
if (!spi_is_ready_dt(&bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
if (!gpio_is_ready_dt(&rst_gpio)) {
LOG_ERR("Reset GPIO device not ready");
return -ENODEV;
}
LOG_DBG("BT SPI initialized");
return 0;
}
#define HCI_DEVICE_INIT(inst) \
static struct bt_spi_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, bt_spi_init, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_BT_SPI_INIT_PRIORITY, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_spi_st.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,533 |
```objective-c
/*
*
*/
/**
* @brief Header file of Ambiq Apollox Blue SoC extended driver
* for SPI based HCI.
*/
#ifndef ZEPHYR_DRIVERS_BLUETOOTH_HCI_APOLLOX_BLUE_H_
#define ZEPHYR_DRIVERS_BLUETOOTH_HCI_APOLLOX_BLUE_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @typedef bt_spi_transceive_fun
* @brief SPI transceive function for Bluetooth packet.
*
* @param tx Pointer of transmission packet.
* @param tx_len Length of transmission packet.
* @param rx Pointer of reception packet.
* @param rx_len Length of reception packet.
*
* @return 0 on success or negative error number on failure.
*/
typedef int (*bt_spi_transceive_fun)(void *tx, uint32_t tx_len, void *rx, uint32_t rx_len);
/**
* @typedef spi_transmit_fun
* @brief Define the SPI transmission function.
*
* @param data Pointer of transmission packet.
* @param len Length of transmission packet.
*
* @return 0 on success or negative error number on failure.
*/
typedef int (*spi_transmit_fun)(uint8_t *data, uint16_t len);
/**
* @brief Initialize the required devices for HCI driver.
*
* The devices mainly include the required gpio (e.g. reset-gpios,
* irq-gpios).
*
* @return 0 on success or negative error number on failure.
*/
int bt_apollo_dev_init(void);
/**
* @brief Send the packets to BLE controller from host via SPI.
*
* @param data Pointer of transmission packet.
* @param len Length of transmission packet.
* @param transceive SPI transceive function for Bluetooth packet.
*
* @return 0 on success or negative error number on failure.
*/
int bt_apollo_spi_send(uint8_t *data, uint16_t len, bt_spi_transceive_fun transceive);
/**
* @brief Receive the packets sent from BLE controller to host via SPI.
*
* @param data Pointer of reception packet.
* @param len Pointer of reception packet length.
* @param transceive SPI transceive function for Bluetooth packet.
*
* @return 0 on success or negative error number on failure.
*/
int bt_apollo_spi_rcv(uint8_t *data, uint16_t *len, bt_spi_transceive_fun transceive);
/**
* @brief Initialize the BLE controller.
*
* This step may do the necessary handshaking with the controller before
* @param transmit SPI transmit function
*
* @return 0 on success or negative error number on failure.
*/
int bt_apollo_controller_init(spi_transmit_fun transmit);
/**
* @brief Vendor specific setup before general HCI command sequence for
* Bluetooth application.
*
* @return 0 on success or negative error number on failure.
*/
int bt_apollo_vnd_setup(void);
/**
* @brief Check if vendor specific receiving handling is ongoing.
*
* @param data Pointer of received packet.
*
* @return true indicates if vendor specific receiving handling is ongoing.
*/
bool bt_apollo_vnd_rcv_ongoing(uint8_t *data, uint16_t len);
/**
* @brief Do the specific preprocessing in HCI packet receiving ISR if needed,
* for example, clear the interrupt status.
*/
void bt_apollo_rcv_isr_preprocess(void);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_BLUETOOTH_HCI_APOLLOX_BLUE_H_ */
``` | /content/code_sandbox/drivers/bluetooth/hci/apollox_blue.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 728 |
```c
/* hci_stm32wba.c - HCI driver for stm32wba */
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/bluetooth/addr.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <linklayer_plat_local.h>
#include <zephyr/sys/byteorder.h>
#include "blestack.h"
#include "app_conf.h"
#include "ll_sys.h"
#include "flash_driver.h"
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(hci_wba);
#define DT_DRV_COMPAT st_hci_stm32wba
struct hci_data {
bt_hci_recv_t recv;
};
static K_SEM_DEFINE(hci_sem, 1, 1);
#define BLE_CTRLR_STACK_BUFFER_SIZE 300
#define MBLOCK_COUNT (BLE_MBLOCKS_CALC(PREP_WRITE_LIST_SIZE, \
CFG_BLE_ATT_MTU_MAX, \
CFG_BLE_NUM_LINK) \
+ CFG_BLE_MBLOCK_COUNT_MARGIN)
#define BLE_DYN_ALLOC_SIZE \
(BLE_TOTAL_BUFFER_SIZE(CFG_BLE_NUM_LINK, MBLOCK_COUNT))
/* GATT buffer size (in bytes)*/
#define BLE_GATT_BUF_SIZE \
BLE_TOTAL_BUFFER_SIZE_GATT(CFG_BLE_NUM_GATT_ATTRIBUTES, \
CFG_BLE_NUM_GATT_SERVICES, \
CFG_BLE_ATT_VALUE_ARRAY_SIZE)
#define DIVC(x, y) (((x)+(y)-1)/(y))
#if defined(CONFIG_BT_HCI_SETUP)
/* Bluetooth LE public STM32WBA default device address (if udn not available) */
static bt_addr_t bd_addr_dflt = {{0x65, 0x43, 0x21, 0x1E, 0x08, 0x00}};
#define ACI_HAL_WRITE_CONFIG_DATA BT_OP(BT_OGF_VS, 0xFC0C)
#define HCI_CONFIG_DATA_PUBADDR_OFFSET 0
static bt_addr_t bd_addr_udn;
struct aci_set_ble_addr {
uint8_t config_offset;
uint8_t length;
uint8_t value[6];
} __packed;
#endif
static uint32_t __noinit buffer[DIVC(BLE_DYN_ALLOC_SIZE, 4)];
static uint32_t __noinit gatt_buffer[DIVC(BLE_GATT_BUF_SIZE, 4)];
extern uint8_t ll_state_busy;
static bool is_hci_event_discardable(const uint8_t *evt_data)
{
uint8_t evt_type = evt_data[0];
switch (evt_type) {
#if defined(CONFIG_BT_CLASSIC)
case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI:
case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT:
return true;
#endif
case BT_HCI_EVT_LE_META_EVENT: {
uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)];
switch (subevt_type) {
case BT_HCI_EVT_LE_ADVERTISING_REPORT:
return true;
default:
return false;
}
}
default:
return false;
}
}
static struct net_buf *treat_evt(const uint8_t *data, size_t len)
{
bool discardable;
struct bt_hci_evt_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (len < sizeof(hdr)) {
LOG_ERR("Not enough data for event header");
return NULL;
}
discardable = is_hci_event_discardable(data);
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
len -= sizeof(hdr);
if (len != hdr.len) {
LOG_ERR("Event payload length is not correct.\n");
LOG_ERR("len: %d, hdr.len: %d\n", len, hdr.len);
return NULL;
}
LOG_DBG("len %u", hdr.len);
buf = bt_buf_get_evt(hdr.evt, discardable, discardable ? K_NO_WAIT : K_SECONDS(3));
if (!buf) {
if (discardable) {
LOG_DBG("Discardable buffer pool full, ignoring event");
} else {
LOG_ERR("No available event buffers!");
}
__ASSERT_NO_MSG(buf);
return buf;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < len) {
LOG_ERR("Not enough space in buffer %zu/%zu", len, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, data, len);
return buf;
}
static struct net_buf *treat_acl(const uint8_t *data, size_t len,
const uint8_t *ext_data, size_t ext_len)
{
struct bt_hci_acl_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (len < sizeof(hdr)) {
LOG_ERR("Not enough data for ACL header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
len -= sizeof(hdr);
} else {
LOG_ERR("No available ACL buffers!");
return NULL;
}
if (ext_len != sys_le16_to_cpu(hdr.len)) {
LOG_ERR("ACL payload length is not correct");
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < len) {
LOG_ERR("Not enough space in buffer %zu/%zu", len, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("ext_len %u", ext_len);
net_buf_add_mem(buf, ext_data, ext_len);
return buf;
}
static struct net_buf *treat_iso(const uint8_t *data, size_t len,
const uint8_t *ext_data, size_t ext_len)
{
struct bt_hci_iso_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (len < sizeof(hdr)) {
LOG_ERR("Not enough data for ISO header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ISO_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
len -= sizeof(hdr);
} else {
LOG_ERR("No available ISO buffers!");
return NULL;
}
if (ext_len != bt_iso_hdr_len(sys_le16_to_cpu(hdr.len))) {
LOG_ERR("ISO payload length is not correct");
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < len) {
LOG_ERR("Not enough space in buffer %zu/%zu", len, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("ext_len %zu", ext_len);
net_buf_add_mem(buf, ext_data, ext_len);
return buf;
}
static int receive_data(const struct device *dev, const uint8_t *data, size_t len,
const uint8_t *ext_data, size_t ext_len)
{
struct hci_data *hci = dev->data;
uint8_t pkt_indicator;
struct net_buf *buf;
int err = 0;
LOG_HEXDUMP_DBG(data, len, "host packet data:");
LOG_HEXDUMP_DBG(ext_data, ext_len, "host packet ext_data:");
pkt_indicator = *data++;
len -= sizeof(pkt_indicator);
switch (pkt_indicator) {
case BT_HCI_H4_EVT:
buf = treat_evt(data, len);
break;
case BT_HCI_H4_ACL:
buf = treat_acl(data, len + 1, ext_data, ext_len);
break;
case BT_HCI_H4_ISO:
case BT_HCI_H4_SCO:
buf = treat_iso(data, len + 1, ext_data, ext_len);
break;
default:
buf = NULL;
LOG_ERR("Unknown HCI type %u", pkt_indicator);
}
if (buf) {
hci->recv(dev, buf);
} else {
err = -ENOMEM;
ll_state_busy = 1;
}
return err;
}
uint8_t BLECB_Indication(const uint8_t *data, uint16_t length,
const uint8_t *ext_data, uint16_t ext_length)
{
const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
int ret = 0;
int err;
LOG_DBG("length: %d", length);
if (ext_length != 0) {
LOG_DBG("ext_length: %d", ext_length);
}
k_sem_take(&hci_sem, K_FOREVER);
err = receive_data(dev, data, (size_t)length - 1,
ext_data, (size_t)ext_length);
k_sem_give(&hci_sem);
HostStack_Process();
if (err) {
ret = 1;
}
return ret;
}
static int bt_hci_stm32wba_send(const struct device *dev, struct net_buf *buf)
{
uint16_t event_length;
uint8_t pkt_indicator;
uint8_t tx_buffer[BLE_CTRLR_STACK_BUFFER_SIZE];
ARG_UNUSED(dev);
k_sem_take(&hci_sem, K_FOREVER);
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
pkt_indicator = BT_HCI_H4_ACL;
break;
case BT_BUF_CMD:
pkt_indicator = BT_HCI_H4_CMD;
break;
case BT_BUF_ISO_OUT:
pkt_indicator = BT_HCI_H4_ISO;
break;
default:
LOG_ERR("Unknown type %u", bt_buf_get_type(buf));
k_sem_give(&hci_sem);
return -EIO;
}
net_buf_push_u8(buf, pkt_indicator);
memcpy(&tx_buffer, buf->data, buf->len);
event_length = BleStack_Request(tx_buffer);
LOG_DBG("event_length: %u", event_length);
if (event_length) {
receive_data(dev, (uint8_t *)&tx_buffer, (size_t)event_length, NULL, 0);
}
k_sem_give(&hci_sem);
net_buf_unref(buf);
return 0;
}
static int bt_ble_ctlr_init(void)
{
BleStack_init_t init_params_p = {0};
init_params_p.numAttrRecord = CFG_BLE_NUM_GATT_ATTRIBUTES;
init_params_p.numAttrServ = CFG_BLE_NUM_GATT_SERVICES;
init_params_p.attrValueArrSize = CFG_BLE_ATT_VALUE_ARRAY_SIZE;
init_params_p.prWriteListSize = CFG_BLE_ATTR_PREPARE_WRITE_VALUE_SIZE;
init_params_p.attMtu = CFG_BLE_ATT_MTU_MAX;
init_params_p.max_coc_nbr = CFG_BLE_COC_NBR_MAX;
init_params_p.max_coc_mps = CFG_BLE_COC_MPS_MAX;
init_params_p.max_coc_initiator_nbr = CFG_BLE_COC_INITIATOR_NBR_MAX;
init_params_p.numOfLinks = CFG_BLE_NUM_LINK;
init_params_p.mblockCount = CFG_BLE_MBLOCK_COUNT;
init_params_p.bleStartRamAddress = (uint8_t *)buffer;
init_params_p.total_buffer_size = BLE_DYN_ALLOC_SIZE;
init_params_p.bleStartRamAddress_GATT = (uint8_t *)gatt_buffer;
init_params_p.total_buffer_size_GATT = BLE_GATT_BUF_SIZE;
init_params_p.options = CFG_BLE_OPTIONS;
init_params_p.debug = 0U;
if (BleStack_Init(&init_params_p) != BLE_STATUS_SUCCESS) {
return -EIO;
}
return 0;
}
static int bt_hci_stm32wba_open(const struct device *dev, bt_hci_recv_t recv)
{
struct hci_data *data = dev->data;
int ret = 0;
link_layer_register_isr();
ll_sys_config_params();
ret = bt_ble_ctlr_init();
if (ret == 0) {
data->recv = recv;
}
/* TODO. Enable Flash manager once available */
if (IS_ENABLED(CONFIG_FLASH)) {
FD_SetStatus(FD_FLASHACCESS_RFTS_BYPASS, LL_FLASH_DISABLE);
}
return ret;
}
#if defined(CONFIG_BT_HCI_SETUP)
bt_addr_t *bt_get_ble_addr(void)
{
bt_addr_t *bd_addr;
uint32_t udn;
uint32_t company_id;
uint32_t device_id;
/* Get the 64 bit Unique Device Number UID */
/* The UID is used by firmware to derive */
/* 48-bit Device Address EUI-48 */
udn = LL_FLASH_GetUDN();
if (udn != 0xFFFFFFFF) {
/* Get the ST Company ID */
company_id = LL_FLASH_GetSTCompanyID();
/* Get the STM32 Device ID */
device_id = LL_FLASH_GetDeviceID();
/*
* Public Address with the ST company ID
* bit[47:24] : 24bits (OUI) equal to the company ID
* bit[23:16] : Device ID.
* bit[15:0] : The last 16bits from the UDN
* Note: In order to use the Public Address in a final product, a dedicated
* 24bits company ID (OUI) shall be bought.
*/
bd_addr_udn.val[0] = (uint8_t)(udn & 0x000000FF);
bd_addr_udn.val[1] = (uint8_t)((udn & 0x0000FF00) >> 8);
bd_addr_udn.val[2] = (uint8_t)device_id;
bd_addr_udn.val[3] = (uint8_t)(company_id & 0x000000FF);
bd_addr_udn.val[4] = (uint8_t)((company_id & 0x0000FF00) >> 8);
bd_addr_udn.val[5] = (uint8_t)((company_id & 0x00FF0000) >> 16);
bd_addr = &bd_addr_udn;
} else {
bd_addr = &bd_addr_dflt;
}
return bd_addr;
}
static int bt_hci_stm32wba_setup(const struct device *dev,
const struct bt_hci_setup_params *params)
{
bt_addr_t *uid_addr;
struct aci_set_ble_addr *param;
struct net_buf *buf;
int err;
uid_addr = bt_get_ble_addr();
if (!uid_addr) {
return -ENOMSG;
}
buf = bt_hci_cmd_create(ACI_HAL_WRITE_CONFIG_DATA, sizeof(*param));
if (!buf) {
return -ENOBUFS;
}
param = net_buf_add(buf, sizeof(*param));
param->config_offset = HCI_CONFIG_DATA_PUBADDR_OFFSET;
param->length = 6;
if (bt_addr_eq(¶ms->public_addr, BT_ADDR_ANY)) {
bt_addr_copy((bt_addr_t *)param->value, uid_addr);
} else {
bt_addr_copy((bt_addr_t *)param->value, &(params->public_addr));
}
err = bt_hci_cmd_send_sync(ACI_HAL_WRITE_CONFIG_DATA, buf, NULL);
if (err) {
return err;
}
return 0;
}
#endif /* CONFIG_BT_HCI_SETUP */
static const struct bt_hci_driver_api drv = {
#if defined(CONFIG_BT_HCI_SETUP)
.setup = bt_hci_stm32wba_setup,
#endif
.open = bt_hci_stm32wba_open,
.send = bt_hci_stm32wba_send,
};
#define HCI_DEVICE_INIT(inst) \
static struct hci_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
/* Only one instance supported */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_stm32wba.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,505 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/bluetooth/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/device.h>
#include <zephyr/ipc/ipc_service.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_hci_driver);
#define DT_DRV_COMPAT zephyr_bt_hci_ipc
#define IPC_BOUND_TIMEOUT_IN_MS K_MSEC(1000)
struct ipc_data {
bt_hci_recv_t recv;
struct ipc_ept hci_ept;
struct ipc_ept_cfg hci_ept_cfg;
struct k_sem bound_sem;
const struct device *ipc;
};
static bool is_hci_event_discardable(const uint8_t *evt_data)
{
uint8_t evt_type = evt_data[0];
switch (evt_type) {
#if defined(CONFIG_BT_CLASSIC)
case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI:
case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT:
return true;
#endif
case BT_HCI_EVT_LE_META_EVENT: {
uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)];
switch (subevt_type) {
case BT_HCI_EVT_LE_ADVERTISING_REPORT:
return true;
#if defined(CONFIG_BT_EXT_ADV)
case BT_HCI_EVT_LE_EXT_ADVERTISING_REPORT:
{
const struct bt_hci_evt_le_ext_advertising_report *ext_adv =
(void *)&evt_data[3];
return (ext_adv->num_reports == 1) &&
((ext_adv->adv_info[0].evt_type &
BT_HCI_LE_ADV_EVT_TYPE_LEGACY) != 0);
}
#endif
default:
return false;
}
}
default:
return false;
}
}
static struct net_buf *bt_ipc_evt_recv(const uint8_t *data, size_t remaining)
{
bool discardable;
struct bt_hci_evt_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for event header");
return NULL;
}
discardable = is_hci_event_discardable(data);
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
if (remaining != hdr.len) {
LOG_ERR("Event payload length is not correct");
return NULL;
}
LOG_DBG("len %u", hdr.len);
do {
buf = bt_buf_get_evt(hdr.evt, discardable, discardable ? K_NO_WAIT : K_SECONDS(10));
if (!buf) {
if (discardable) {
LOG_DBG("Discardable buffer pool full, ignoring event");
return buf;
}
LOG_WRN("Couldn't allocate a buffer after waiting 10 seconds.");
}
} while (!buf);
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, data, remaining);
return buf;
}
static struct net_buf *bt_ipc_acl_recv(const uint8_t *data, size_t remaining)
{
struct bt_hci_acl_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for ACL header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
net_buf_add_mem(buf, &hdr, sizeof(hdr));
} else {
LOG_ERR("No available ACL buffers!");
return NULL;
}
if (remaining != sys_le16_to_cpu(hdr.len)) {
LOG_ERR("ACL payload length is not correct");
net_buf_unref(buf);
return NULL;
}
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("len %u", remaining);
net_buf_add_mem(buf, data, remaining);
return buf;
}
static struct net_buf *bt_ipc_iso_recv(const uint8_t *data, size_t remaining)
{
struct bt_hci_iso_hdr hdr;
static size_t fail_cnt;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for ISO header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ISO_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
net_buf_add_mem(buf, &hdr, sizeof(hdr));
fail_cnt = 0U;
} else {
if ((fail_cnt % 100U) == 0U) {
LOG_ERR("No available ISO buffers (%zu)!", fail_cnt);
}
fail_cnt++;
return NULL;
}
if (remaining != bt_iso_hdr_len(sys_le16_to_cpu(hdr.len))) {
LOG_ERR("ISO payload length is not correct");
net_buf_unref(buf);
return NULL;
}
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("len %zu", remaining);
net_buf_add_mem(buf, data, remaining);
return buf;
}
static void bt_ipc_rx(const struct device *dev, const uint8_t *data, size_t len)
{
struct ipc_data *ipc = dev->data;
uint8_t pkt_indicator;
struct net_buf *buf = NULL;
size_t remaining = len;
LOG_HEXDUMP_DBG(data, len, "ipc data:");
pkt_indicator = *data++;
remaining -= sizeof(pkt_indicator);
switch (pkt_indicator) {
case BT_HCI_H4_EVT:
buf = bt_ipc_evt_recv(data, remaining);
break;
case BT_HCI_H4_ACL:
buf = bt_ipc_acl_recv(data, remaining);
break;
case BT_HCI_H4_ISO:
buf = bt_ipc_iso_recv(data, remaining);
break;
default:
LOG_ERR("Unknown HCI type %u", pkt_indicator);
return;
}
if (buf) {
LOG_DBG("Calling bt_recv(%p)", buf);
ipc->recv(dev, buf);
LOG_HEXDUMP_DBG(buf->data, buf->len, "RX buf payload:");
}
}
static int bt_ipc_send(const struct device *dev, struct net_buf *buf)
{
struct ipc_data *data = dev->data;
int err;
uint8_t pkt_indicator;
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
pkt_indicator = BT_HCI_H4_ACL;
break;
case BT_BUF_CMD:
pkt_indicator = BT_HCI_H4_CMD;
break;
case BT_BUF_ISO_OUT:
pkt_indicator = BT_HCI_H4_ISO;
break;
default:
LOG_ERR("Unknown type %u", bt_buf_get_type(buf));
goto done;
}
net_buf_push_u8(buf, pkt_indicator);
LOG_HEXDUMP_DBG(buf->data, buf->len, "Final HCI buffer:");
err = ipc_service_send(&data->hci_ept, buf->data, buf->len);
if (err < 0) {
LOG_ERR("Failed to send (err %d)", err);
}
done:
net_buf_unref(buf);
return 0;
}
static void hci_ept_bound(void *priv)
{
const struct device *dev = priv;
struct ipc_data *ipc = dev->data;
k_sem_give(&ipc->bound_sem);
}
static void hci_ept_recv(const void *data, size_t len, void *priv)
{
const struct device *dev = priv;
bt_ipc_rx(dev, data, len);
}
int __weak bt_hci_transport_setup(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
int __weak bt_hci_transport_teardown(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static int bt_ipc_open(const struct device *dev, bt_hci_recv_t recv)
{
struct ipc_data *ipc = dev->data;
int err;
err = bt_hci_transport_setup(NULL);
if (err) {
LOG_ERR("HCI transport setup failed with: %d\n", err);
return err;
}
LOG_DBG("");
err = ipc_service_open_instance(ipc->ipc);
if (err && (err != -EALREADY)) {
LOG_ERR("IPC service instance initialization failed: %d\n", err);
return err;
}
err = ipc_service_register_endpoint(ipc->ipc, &ipc->hci_ept, &ipc->hci_ept_cfg);
if (err) {
LOG_ERR("Registering endpoint failed with %d", err);
return err;
}
err = k_sem_take(&ipc->bound_sem, IPC_BOUND_TIMEOUT_IN_MS);
if (err) {
LOG_ERR("Endpoint binding failed with %d", err);
return err;
}
ipc->recv = recv;
return 0;
}
static int bt_ipc_close(const struct device *dev)
{
struct ipc_data *ipc = dev->data;
int err;
if (IS_ENABLED(CONFIG_BT_HCI_HOST)) {
err = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, NULL);
if (err) {
LOG_ERR("Sending reset command failed with: %d", err);
return err;
}
}
err = ipc_service_deregister_endpoint(&ipc->hci_ept);
if (err) {
LOG_ERR("Deregistering HCI endpoint failed with: %d", err);
return err;
}
err = ipc_service_close_instance(ipc->ipc);
if (err) {
LOG_ERR("Closing IPC service failed with: %d", err);
return err;
}
err = bt_hci_transport_teardown(NULL);
if (err) {
LOG_ERR("HCI transport teardown failed with: %d", err);
return err;
}
ipc->recv = NULL;
return 0;
}
static const struct bt_hci_driver_api drv = {
.open = bt_ipc_open,
.close = bt_ipc_close,
.send = bt_ipc_send,
};
#define IPC_DEVICE_INIT(inst) \
static struct ipc_data ipc_data_##inst = { \
.bound_sem = Z_SEM_INITIALIZER(ipc_data_##inst.bound_sem, 0, 1), \
.hci_ept_cfg = { \
.name = DT_INST_PROP(inst, bt_hci_ipc_name), \
.cb = { \
.bound = hci_ept_bound, \
.received = hci_ept_recv, \
}, \
.priv = (void *)DEVICE_DT_INST_GET(inst), \
}, \
.ipc = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
}; \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &ipc_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
DT_INST_FOREACH_STATUS_OKAY(IPC_DEVICE_INIT)
``` | /content/code_sandbox/drivers/bluetooth/hci/ipc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,521 |
```c
/*
*
*/
/**
* @brief Ambiq SPI based Bluetooth HCI driver.
*/
#define DT_DRV_COMPAT ambiq_bt_hci_spi
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_hci_driver);
#include "apollox_blue.h"
/* Offset of special item */
#define PACKET_TYPE 0
#define PACKET_TYPE_SIZE 1
#define EVT_HEADER_TYPE 0
#define EVT_CMD_COMP_OP_LSB 3
#define EVT_CMD_COMP_OP_MSB 4
#define EVT_CMD_COMP_DATA 5
#define EVT_OK 0
#define EVT_DISCARD 1
#define EVT_NOP 2
#define BT_FEAT_SET_BIT(feat, octet, bit) (feat[octet] |= BIT(bit))
#define BT_FEAT_SET_NO_BREDR(feat) BT_FEAT_SET_BIT(feat, 4, 5)
#define BT_FEAT_SET_LE(feat) BT_FEAT_SET_BIT(feat, 4, 6)
/* Max SPI buffer length for transceive operations.
* The maximum TX packet number is 512 bytes data + 12 bytes header.
* The maximum RX packet number is 255 bytes data + 3 header.
*/
#define SPI_MAX_TX_MSG_LEN 524
#define SPI_MAX_RX_MSG_LEN 258
/* The controller may be unavailable to receive packets because it is busy
* on processing something or have packets to send to host. Need to free the
* SPI bus and wait some moment to try again.
*/
#define SPI_BUSY_WAIT_INTERVAL_MS 25
#define SPI_BUSY_TX_ATTEMPTS 200
static uint8_t __noinit rxmsg[SPI_MAX_RX_MSG_LEN];
static struct spi_dt_spec spi_bus =
SPI_DT_SPEC_INST_GET(0,
SPI_OP_MODE_MASTER | SPI_HALF_DUPLEX | SPI_TRANSFER_MSB |
SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8),
0);
static K_KERNEL_STACK_DEFINE(spi_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE);
static struct k_thread spi_rx_thread_data;
static struct spi_buf spi_tx_buf;
static struct spi_buf spi_rx_buf;
static const struct spi_buf_set spi_tx = {.buffers = &spi_tx_buf, .count = 1};
static const struct spi_buf_set spi_rx = {.buffers = &spi_rx_buf, .count = 1};
static K_SEM_DEFINE(sem_irq, 0, 1);
static K_SEM_DEFINE(sem_spi_available, 1, 1);
struct bt_apollo_data {
bt_hci_recv_t recv;
};
void bt_packet_irq_isr(const struct device *unused1, struct gpio_callback *unused2,
uint32_t unused3)
{
bt_apollo_rcv_isr_preprocess();
k_sem_give(&sem_irq);
}
static inline int bt_spi_transceive(void *tx, uint32_t tx_len, void *rx, uint32_t rx_len)
{
spi_tx_buf.buf = tx;
spi_tx_buf.len = (size_t)tx_len;
spi_rx_buf.buf = rx;
spi_rx_buf.len = (size_t)rx_len;
/* Before sending packet to controller the host needs to poll the status of
* controller to know it's ready, or before reading packets from controller
* the host needs to get the payload size of coming packets by sending specific
* command and putting the status or size to the rx buffer, the CS should be
* held at this moment to continue to send or receive packets.
*/
if (tx_len && rx_len) {
spi_bus.config.operation |= SPI_HOLD_ON_CS;
} else {
spi_bus.config.operation &= ~SPI_HOLD_ON_CS;
}
return spi_transceive_dt(&spi_bus, &spi_tx, &spi_rx);
}
static int spi_send_packet(uint8_t *data, uint16_t len)
{
int ret;
uint16_t fail_count = 0;
do {
/* Wait for SPI bus to be available */
k_sem_take(&sem_spi_available, K_FOREVER);
/* Send the SPI packet to controller */
ret = bt_apollo_spi_send(data, len, bt_spi_transceive);
/* Free the SPI bus */
k_sem_give(&sem_spi_available);
if (ret) {
/* Give some chance to controller to complete the processing or
* packets sending.
*/
k_sleep(K_MSEC(SPI_BUSY_WAIT_INTERVAL_MS));
} else {
break;
}
} while (fail_count++ < SPI_BUSY_TX_ATTEMPTS);
return ret;
}
static int spi_receive_packet(uint8_t *data, uint16_t *len)
{
int ret;
/* Wait for SPI bus to be available */
k_sem_take(&sem_spi_available, K_FOREVER);
/* Receive the SPI packet from controller */
ret = bt_apollo_spi_rcv(data, len, bt_spi_transceive);
/* Free the SPI bus */
k_sem_give(&sem_spi_available);
return ret;
}
static int hci_event_filter(const uint8_t *evt_data)
{
uint8_t evt_type = evt_data[EVT_HEADER_TYPE];
switch (evt_type) {
case BT_HCI_EVT_LE_META_EVENT: {
uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)];
switch (subevt_type) {
case BT_HCI_EVT_LE_ADVERTISING_REPORT:
return EVT_DISCARD;
default:
return EVT_OK;
}
}
case BT_HCI_EVT_CMD_COMPLETE: {
uint16_t opcode = (uint16_t)(evt_data[EVT_CMD_COMP_OP_LSB] +
(evt_data[EVT_CMD_COMP_OP_MSB] << 8));
switch (opcode) {
case BT_OP_NOP:
return EVT_NOP;
case BT_HCI_OP_READ_LOCAL_FEATURES: {
/* The BLE controller of some Ambiq Apollox Blue SOC may have issue to
* report the expected supported features bitmask successfully, thought the
* features are actually supportive. Need to correct them before going to
* the host stack.
*/
struct bt_hci_rp_read_local_features *rp =
(void *)&evt_data[EVT_CMD_COMP_DATA];
if (rp->status == 0) {
BT_FEAT_SET_NO_BREDR(rp->features);
BT_FEAT_SET_LE(rp->features);
}
return EVT_OK;
}
default:
return EVT_OK;
}
}
default:
return EVT_OK;
}
}
static struct net_buf *bt_hci_evt_recv(uint8_t *data, size_t len)
{
int evt_filter;
bool discardable = false;
struct bt_hci_evt_hdr hdr = {0};
struct net_buf *buf;
size_t buf_tailroom;
if (len < sizeof(hdr)) {
LOG_ERR("Not enough data for event header");
return NULL;
}
evt_filter = hci_event_filter(data);
if (evt_filter == EVT_NOP) {
/* The controller sends NOP event when wakes up based on
* hardware specific requirement, do not post this event to
* host stack.
*/
return NULL;
} else if (evt_filter == EVT_DISCARD) {
discardable = true;
}
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
len -= sizeof(hdr);
if (len != hdr.len) {
LOG_ERR("Event payload length is not correct");
return NULL;
}
buf = bt_buf_get_evt(hdr.evt, discardable, K_NO_WAIT);
if (!buf) {
if (discardable) {
LOG_DBG("Discardable buffer pool full, ignoring event");
} else {
LOG_ERR("No available event buffers!");
}
return buf;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < len) {
LOG_ERR("Not enough space in buffer %zu/%zu", len, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, data, len);
return buf;
}
static struct net_buf *bt_hci_acl_recv(uint8_t *data, size_t len)
{
struct bt_hci_acl_hdr hdr = {0};
struct net_buf *buf;
size_t buf_tailroom;
if (len < sizeof(hdr)) {
LOG_ERR("Not enough data for ACL header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
len -= sizeof(hdr);
} else {
LOG_ERR("No available ACL buffers!");
return NULL;
}
if (len != sys_le16_to_cpu(hdr.len)) {
LOG_ERR("ACL payload length is not correct");
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < len) {
LOG_ERR("Not enough space in buffer %zu/%zu", len, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, data, len);
return buf;
}
static void bt_spi_rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct bt_apollo_data *hci = dev->data;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct net_buf *buf;
int ret;
uint16_t len = 0;
while (true) {
/* Wait for controller interrupt */
k_sem_take(&sem_irq, K_FOREVER);
do {
/* Recevive the HCI packet via SPI */
ret = spi_receive_packet(&rxmsg[0], &len);
if (ret) {
break;
}
/* Check if needs to handle the vendor specific events which are
* incompatible with the standard Bluetooth HCI format.
*/
if (bt_apollo_vnd_rcv_ongoing(&rxmsg[0], len)) {
break;
}
switch (rxmsg[PACKET_TYPE]) {
case BT_HCI_H4_EVT:
buf = bt_hci_evt_recv(&rxmsg[PACKET_TYPE + PACKET_TYPE_SIZE],
(len - PACKET_TYPE_SIZE));
break;
case BT_HCI_H4_ACL:
buf = bt_hci_acl_recv(&rxmsg[PACKET_TYPE + PACKET_TYPE_SIZE],
(len - PACKET_TYPE_SIZE));
break;
default:
buf = NULL;
LOG_WRN("Unknown BT buf type %d", rxmsg[PACKET_TYPE]);
break;
}
/* Post the RX message to host stack to process */
if (buf) {
hci->recv(dev, buf);
}
} while (0);
}
}
static int bt_apollo_send(const struct device *dev, struct net_buf *buf)
{
int ret = 0;
/* Buffer needs an additional byte for type */
if (buf->len >= SPI_MAX_TX_MSG_LEN) {
LOG_ERR("Message too long");
return -EINVAL;
}
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
net_buf_push_u8(buf, BT_HCI_H4_ACL);
break;
case BT_BUF_CMD:
net_buf_push_u8(buf, BT_HCI_H4_CMD);
break;
default:
LOG_ERR("Unsupported type");
net_buf_unref(buf);
return -EINVAL;
}
/* Send the SPI packet */
ret = spi_send_packet(buf->data, buf->len);
net_buf_unref(buf);
return ret;
}
static int bt_apollo_open(const struct device *dev, bt_hci_recv_t recv)
{
struct bt_apollo_data *hci = dev->data;
int ret;
ret = bt_hci_transport_setup(spi_bus.bus);
if (ret) {
return ret;
}
/* Start RX thread */
k_thread_create(&spi_rx_thread_data, spi_rx_stack, K_KERNEL_STACK_SIZEOF(spi_rx_stack),
(k_thread_entry_t)bt_spi_rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO), 0, K_NO_WAIT);
ret = bt_apollo_controller_init(spi_send_packet);
if (ret == 0) {
hci->recv = recv;
}
return ret;
}
static int bt_apollo_setup(const struct device *dev, const struct bt_hci_setup_params *params)
{
ARG_UNUSED(params);
int ret;
ret = bt_apollo_vnd_setup();
return ret;
}
static const struct bt_hci_driver_api drv = {
.open = bt_apollo_open,
.send = bt_apollo_send,
.setup = bt_apollo_setup,
};
static int bt_apollo_init(const struct device *dev)
{
int ret;
ARG_UNUSED(dev);
if (!device_is_ready(spi_bus.bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
ret = bt_apollo_dev_init();
if (ret) {
return ret;
}
LOG_DBG("BT HCI initialized");
return 0;
}
#define HCI_DEVICE_INIT(inst) \
static struct bt_apollo_data hci_data_##inst = {}; \
DEVICE_DT_INST_DEFINE(inst, bt_apollo_init, NULL, &hci_data_##inst, NULL, POST_KERNEL, \
CONFIG_BT_HCI_INIT_PRIORITY, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,955 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief CYW43xxx HCI extension driver.
*/
#include <errno.h>
#include <stddef.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/bluetooth/bluetooth.h>
#include <zephyr/drivers/bluetooth/hci_driver.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/uart.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(cyw43xxx_driver);
#include <stdint.h>
#define DT_DRV_COMPAT infineon_cyw43xxx_bt_hci
BUILD_ASSERT(DT_PROP(DT_INST_GPARENT(0), hw_flow_control) == 1,
"hw_flow_control must be enabled for HCI H4 UART");
/* BT settling time after power on */
#define BT_POWER_ON_SETTLING_TIME_MS (500u)
#define BT_POWER_CBUCK_DISCHARGE_TIME_MS (300u)
/* Stabilization delay after FW loading */
#define BT_STABILIZATION_DELAY_MS (250u)
/* HCI Command packet from Host to Controller */
#define HCI_COMMAND_PACKET (0x01)
/* Length of UPDATE BAUD RATE command */
#define HCI_VSC_UPDATE_BAUD_RATE_LENGTH (6u)
/* Default BAUDRATE */
#define HCI_UART_DEFAULT_BAUDRATE (115200)
/* Externs for CY43xxx controller FW */
extern const uint8_t brcm_patchram_buf[];
extern const int brcm_patch_ram_length;
enum {
BT_HCI_VND_OP_DOWNLOAD_MINIDRIVER = 0xFC2E,
BT_HCI_VND_OP_WRITE_RAM = 0xFC4C,
BT_HCI_VND_OP_LAUNCH_RAM = 0xFC4E,
BT_HCI_VND_OP_UPDATE_BAUDRATE = 0xFC18,
};
/* bt_h4_vnd_setup function.
* This function executes vendor-specific commands sequence to
* initialize BT Controller before BT Host executes Reset sequence.
* bt_h4_vnd_setup function must be implemented in vendor-specific HCI
* extansion module if CONFIG_BT_HCI_SETUP is enabled.
*/
int bt_h4_vnd_setup(const struct device *dev);
static int bt_hci_uart_set_baudrate(const struct device *bt_uart_dev, uint32_t baudrate)
{
struct uart_config uart_cfg;
int err;
/* Get current UART configuration */
err = uart_config_get(bt_uart_dev, &uart_cfg);
if (err) {
return err;
}
if (uart_cfg.baudrate != baudrate) {
/* Re-configure UART */
uart_cfg.baudrate = baudrate;
err = uart_configure(bt_uart_dev, &uart_cfg);
if (err) {
return err;
}
/* Revert Interrupt options */
uart_irq_rx_enable(bt_uart_dev);
}
return 0;
}
static int bt_update_controller_baudrate(const struct device *bt_uart_dev, uint32_t baudrate)
{
/*
* NOTE from datasheet for update baudrate:
* - To speed up application downloading, the MCU host commands the CYWxxx device
* to communicate at a new, higher rate by issuing the following Vendor Specific
* UPDATE_BAUDRATE command:
* 01 18 FC 06 00 00 xx xx xx xx
* In the above command, the xx xx xx xx bytes specify the 32-bit little-endian
* value of the new rate in bits per second. For example,
* 115200 is represented as 00 C2 01 00.
* The following response to the UPDATE_BAUDRATE command is expected within 100 ms:
* 04 0E 04 01 18 FC 00
* - The host switches to the new baud rate after receiving the response at the old
* baud rate.
*/
struct net_buf *buf;
int err;
uint8_t hci_data[HCI_VSC_UPDATE_BAUD_RATE_LENGTH];
/* Baudrate is loaded LittleEndian */
hci_data[0] = 0;
hci_data[1] = 0;
hci_data[2] = (uint8_t)(baudrate & 0xFFUL);
hci_data[3] = (uint8_t)((baudrate >> 8) & 0xFFUL);
hci_data[4] = (uint8_t)((baudrate >> 16) & 0xFFUL);
hci_data[5] = (uint8_t)((baudrate >> 24) & 0xFFUL);
/* Allocate buffer for update uart baudrate command.
* It will be BT_HCI_OP_RESET with extra parameters.
*/
buf = bt_hci_cmd_create(BT_HCI_VND_OP_UPDATE_BAUDRATE,
HCI_VSC_UPDATE_BAUD_RATE_LENGTH);
if (buf == NULL) {
LOG_ERR("Unable to allocate command buffer");
return -ENOMEM;
}
/* Add data part of packet */
net_buf_add_mem(buf, &hci_data, HCI_VSC_UPDATE_BAUD_RATE_LENGTH);
/* Send update uart baudrate command. */
err = bt_hci_cmd_send_sync(BT_HCI_VND_OP_UPDATE_BAUDRATE, buf, NULL);
if (err) {
return err;
}
/* Re-configure Uart baudrate */
err = bt_hci_uart_set_baudrate(bt_uart_dev, baudrate);
if (err) {
return err;
}
return 0;
}
static int bt_firmware_download(const uint8_t *firmware_image, uint32_t size)
{
uint8_t *data = (uint8_t *)firmware_image;
volatile uint32_t remaining_length = size;
struct net_buf *buf;
int err;
LOG_DBG("Executing Fw downloading for CYW43xx device");
/* Send hci_download_minidriver command */
err = bt_hci_cmd_send_sync(BT_HCI_VND_OP_DOWNLOAD_MINIDRIVER, NULL, NULL);
if (err) {
return err;
}
/* The firmware image (.hcd format) contains a collection of hci_write_ram
* command + a block of the image, followed by a hci_write_ram image at the end.
* Parse and send each individual command and wait for the response. This is to
* ensure the integrity of the firmware image sent to the bluetooth chip.
*/
while (remaining_length) {
size_t data_length = data[2]; /* data length from firmware image block */
uint16_t op_code = *(uint16_t *)data;
/* Allocate buffer for hci_write_ram/hci_launch_ram command. */
buf = bt_hci_cmd_create(op_code, data_length);
if (buf == NULL) {
LOG_ERR("Unable to allocate command buffer");
return err;
}
/* Add data part of packet */
net_buf_add_mem(buf, &data[3], data_length);
/* Send hci_write_ram command. */
err = bt_hci_cmd_send_sync(op_code, buf, NULL);
if (err) {
return err;
}
switch (op_code) {
case BT_HCI_VND_OP_WRITE_RAM:
/* Update remaining length and data pointer:
* content of data length + 2 bytes of opcode and 1 byte of data length.
*/
data += data_length + 3;
remaining_length -= data_length + 3;
break;
case BT_HCI_VND_OP_LAUNCH_RAM:
remaining_length = 0;
break;
default:
return -ENOMEM;
}
}
LOG_DBG("Fw downloading complete");
return 0;
}
int bt_h4_vnd_setup(const struct device *dev)
{
int err;
uint32_t default_uart_speed = DT_PROP(DT_INST_BUS(0), current_speed);
uint32_t hci_operation_speed = DT_INST_PROP_OR(0, hci_operation_speed, default_uart_speed);
uint32_t fw_download_speed = DT_INST_PROP_OR(0, fw_download_speed, default_uart_speed);
/* Check BT Uart instance */
if (!device_is_ready(dev)) {
return -EINVAL;
}
#if DT_INST_NODE_HAS_PROP(0, bt_reg_on_gpios)
struct gpio_dt_spec bt_reg_on = GPIO_DT_SPEC_GET(DT_DRV_INST(0), bt_reg_on_gpios);
/* Check BT REG_ON gpio instance */
if (!gpio_is_ready_dt(&bt_reg_on)) {
LOG_ERR("Error: failed to configure bt_reg_on %s pin %d",
bt_reg_on.port->name, bt_reg_on.pin);
return -EIO;
}
/* Configure bt_reg_on as output */
err = gpio_pin_configure_dt(&bt_reg_on, GPIO_OUTPUT_LOW);
if (err) {
LOG_ERR("Error %d: failed to configure bt_reg_on %s pin %d",
err, bt_reg_on.port->name, bt_reg_on.pin);
return err;
}
/* Allow BT CBUCK regulator to discharge */
(void)k_msleep(BT_POWER_CBUCK_DISCHARGE_TIME_MS);
err = gpio_pin_set_dt(&bt_reg_on, 1);
if (err) {
return err;
}
#endif /* DT_INST_NODE_HAS_PROP(0, bt_reg_on_gpios) */
/* BT settling time after power on */
(void)k_msleep(BT_POWER_ON_SETTLING_TIME_MS);
/* Send HCI_RESET */
err = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, NULL);
if (err) {
return err;
}
/* Re-configure baudrate for BT Controller */
if (fw_download_speed != default_uart_speed) {
err = bt_update_controller_baudrate(dev, fw_download_speed);
if (err) {
return err;
}
}
/* BT firmware download */
err = bt_firmware_download(brcm_patchram_buf, (uint32_t) brcm_patch_ram_length);
if (err) {
return err;
}
/* Stabilization delay */
(void)k_msleep(BT_STABILIZATION_DELAY_MS);
/* When FW launched, HCI UART baudrate should be configured to default */
if (fw_download_speed != default_uart_speed) {
err = bt_hci_uart_set_baudrate(dev, default_uart_speed);
if (err) {
return err;
}
}
/* Send HCI_RESET */
err = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, NULL);
if (err) {
return err;
}
/* Set host controller functionality to user defined baudrate
* after fw downloading.
*/
if (hci_operation_speed != default_uart_speed) {
err = bt_update_controller_baudrate(dev, hci_operation_speed);
if (err) {
return err;
}
}
return 0;
}
``` | /content/code_sandbox/drivers/bluetooth/hci/h4_ifx_cyw43xxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,359 |
```c
/*
*
*/
/* your_sha256_hash---------- */
/* Includes */
/* your_sha256_hash---------- */
#include <zephyr/init.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/bluetooth/hci_types.h>
#include <soc.h>
#include <fwk_platform_ble.h>
#include <fwk_platform.h>
/* your_sha256_hash---------- */
/* Definitions */
/* your_sha256_hash---------- */
#define DT_DRV_COMPAT nxp_hci_ble
struct bt_nxp_data {
bt_hci_recv_t recv;
};
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
LOG_MODULE_REGISTER(bt_driver);
#define HCI_IRQ_N DT_INST_IRQ_BY_NAME(0, hci_int, irq)
#define HCI_IRQ_P DT_INST_IRQ_BY_NAME(0, hci_int, priority)
#define HCI_WAKEUP_IRQ_N DT_INST_IRQ_BY_NAME(0, wakeup_int, irq)
#define HCI_WAKEUP_IRQ_P DT_INST_IRQ_BY_NAME(0, wakeup_int, priority)
/* Vendor specific commands */
#define HCI_CMD_STORE_BT_CAL_DATA_OCF 0x61U
#define HCI_CMD_STORE_BT_CAL_DATA_PARAM_LENGTH 32U
#define HCI_CMD_STORE_BT_CAL_DATA_ANNEX100_OCF 0xFFU
#define HCI_CMD_STORE_BT_CAL_DATA_PARAM_ANNEX100_LENGTH 16U
#define HCI_CMD_SET_BT_SLEEP_MODE_OCF 0x23U
#define HCI_CMD_SET_BT_SLEEP_MODE_PARAM_LENGTH 3U
#define HCI_CMD_BT_HOST_SLEEP_CONFIG_OCF 0x59U
#define HCI_CMD_BT_HOST_SLEEP_CONFIG_PARAM_LENGTH 2U
/* your_sha256_hash---------- */
/* Public prototypes */
/* your_sha256_hash---------- */
extern int32_t ble_hci_handler(void);
extern int32_t ble_wakeup_done_handler(void);
/* your_sha256_hash---------- */
/* Private functions */
/* your_sha256_hash---------- */
#if CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP || CONFIG_HCI_NXP_SET_CAL_DATA
static int nxp_bt_send_vs_command(uint16_t opcode, const uint8_t *params, uint8_t params_len)
{
#if CONFIG_BT_HCI_HOST
struct net_buf *buf;
/* Allocate buffer for the hci command */
buf = bt_hci_cmd_create(opcode, params_len);
if (buf == NULL) {
LOG_ERR("Unable to allocate command buffer");
return -ENOMEM;
}
/* Add data part of packet */
net_buf_add_mem(buf, params, params_len);
/* Send the command */
return bt_hci_cmd_send_sync(opcode, buf, NULL);
#else
return 0;
#endif
}
#endif /* CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP || CONFIG_HCI_NXP_SET_CAL_DATA */
#if CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP
static int nxp_bt_enable_controller_autosleep(void)
{
uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_SET_BT_SLEEP_MODE_OCF);
const uint8_t params[HCI_CMD_SET_BT_SLEEP_MODE_PARAM_LENGTH] = {
0x02U, /* Auto sleep enable */
0x00U, /* Idle timeout LSB */
0x00U /* Idle timeout MSB */
};
/* Send the command */
return nxp_bt_send_vs_command(opcode, params, HCI_CMD_SET_BT_SLEEP_MODE_PARAM_LENGTH);
}
static int nxp_bt_set_host_sleep_config(void)
{
uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_BT_HOST_SLEEP_CONFIG_OCF);
const uint8_t params[HCI_CMD_BT_HOST_SLEEP_CONFIG_PARAM_LENGTH] = {
0xFFU, /* BT_HIU_WAKEUP_INBAND */
0xFFU, /* BT_HIU_WAKE_GAP_WAIT_FOR_IRQ */
};
/* Send the command */
return nxp_bt_send_vs_command(opcode, params, HCI_CMD_BT_HOST_SLEEP_CONFIG_PARAM_LENGTH);
}
#endif /* CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP */
#if CONFIG_HCI_NXP_SET_CAL_DATA
static int bt_nxp_set_calibration_data(void)
{
uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_STORE_BT_CAL_DATA_OCF);
extern const uint8_t hci_cal_data_params[HCI_CMD_STORE_BT_CAL_DATA_PARAM_LENGTH];
/* Send the command */
return nxp_bt_send_vs_command(opcode, hci_cal_data_params,
HCI_CMD_STORE_BT_CAL_DATA_PARAM_LENGTH);
}
#if CONFIG_HCI_NXP_SET_CAL_DATA_ANNEX100
static int bt_nxp_set_calibration_data_annex100(void)
{
uint16_t opcode = BT_OP(BT_OGF_VS, HCI_CMD_STORE_BT_CAL_DATA_ANNEX100_OCF);
extern const uint8_t
hci_cal_data_annex100_params[HCI_CMD_STORE_BT_CAL_DATA_PARAM_ANNEX100_LENGTH];
/* Send the command */
return nxp_bt_send_vs_command(opcode, hci_cal_data_annex100_params,
HCI_CMD_STORE_BT_CAL_DATA_PARAM_ANNEX100_LENGTH);
}
#endif /* CONFIG_HCI_NXP_SET_CAL_DATA_ANNEX100 */
#endif /* CONFIG_HCI_NXP_SET_CAL_DATA */
static bool is_hci_event_discardable(const uint8_t *evt_data)
{
bool ret = false;
uint8_t evt_type = evt_data[0];
switch (evt_type) {
case BT_HCI_EVT_LE_META_EVENT: {
uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)];
switch (subevt_type) {
case BT_HCI_EVT_LE_ADVERTISING_REPORT:
case BT_HCI_EVT_LE_EXT_ADVERTISING_REPORT:
ret = true;
break;
default:
break;
}
} break;
default:
break;
}
return ret;
}
static struct net_buf *bt_evt_recv(uint8_t *data, size_t len)
{
struct net_buf *buf;
uint8_t payload_len;
uint8_t evt_hdr;
bool discardable_evt;
size_t space_in_buffer;
payload_len = data[1];
evt_hdr = data[0];
discardable_evt = false;
/* Data Check */
if (len < BT_HCI_EVT_HDR_SIZE) {
LOG_ERR("Event header is missing");
return NULL;
}
if ((len - BT_HCI_EVT_HDR_SIZE) != payload_len) {
LOG_ERR("Event payload length is incorrect");
return NULL;
}
discardable_evt = is_hci_event_discardable(data);
/* Allocate a buffer for the HCI Event */
buf = bt_buf_get_evt(evt_hdr, discardable_evt, (discardable_evt ? K_NO_WAIT : K_FOREVER));
if (buf) {
space_in_buffer = net_buf_tailroom(buf);
if (len > space_in_buffer) {
LOG_ERR("Buffer size error,INFO : evt_hdr=%d, data_len=%zu, buf_size=%zu",
evt_hdr, len, space_in_buffer);
net_buf_unref(buf);
return NULL;
}
/* Copy the data to the buffer */
net_buf_add_mem(buf, data, len);
} else {
if (discardable_evt) {
LOG_DBG("Discardable buffer pool full, ignoring event");
} else {
LOG_ERR("No available event buffers!");
}
return NULL;
}
return buf;
}
static struct net_buf *bt_acl_recv(uint8_t *data, size_t len)
{
struct net_buf *buf;
uint16_t payload_len;
/* Data Check */
if (len < BT_HCI_ACL_HDR_SIZE) {
LOG_ERR("ACL header is missing");
return NULL;
}
memcpy((void *)&payload_len, (void *)&data[2], 2);
if ((len - BT_HCI_ACL_HDR_SIZE) != payload_len) {
LOG_ERR("ACL payload length is incorrect");
return NULL;
}
/* Allocate a buffer for the received data */
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (buf) {
if (len > net_buf_tailroom(buf)) {
LOG_ERR("Buffer doesn't have enough space to store the data");
net_buf_unref(buf);
return NULL;
}
/* Copy the data to the buffer */
net_buf_add_mem(buf, data, len);
} else {
LOG_ERR("ACL buffer is empty");
return NULL;
}
return buf;
}
static void hci_rx_cb(uint8_t packetType, uint8_t *data, uint16_t len)
{
const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
struct bt_nxp_data *hci = dev->data;
struct net_buf *buf;
switch (packetType) {
case BT_HCI_H4_EVT:
/* create a buffer and fill it out with event data */
buf = bt_evt_recv(data, len);
break;
case BT_HCI_H4_ACL:
/* create a buffer and fill it out with ACL data */
buf = bt_acl_recv(data, len);
break;
default:
buf = NULL;
LOG_ERR("Unknown HCI type");
}
if (buf) {
/* Provide the buffer to the host */
hci->recv(dev, buf);
}
}
static int bt_nxp_send(const struct device *dev, struct net_buf *buf)
{
uint8_t packetType;
ARG_UNUSED(dev);
switch (bt_buf_get_type(buf)) {
case BT_BUF_CMD:
packetType = BT_HCI_H4_CMD;
break;
case BT_BUF_ACL_OUT:
packetType = BT_HCI_H4_ACL;
break;
default:
LOG_ERR("Not supported type");
return -1;
}
net_buf_push_u8(buf, packetType);
PLATFORM_SendHciMessage(buf->data, buf->len);
net_buf_unref(buf);
return 0;
}
static int bt_nxp_open(const struct device *dev, bt_hci_recv_t recv)
{
struct bt_nxp_data *hci = dev->data;
int ret = 0;
do {
ret = PLATFORM_InitBle();
if (ret < 0) {
LOG_ERR("Failed to initialize BLE controller");
break;
}
ret = PLATFORM_SetHciRxCallback(hci_rx_cb);
if (ret < 0) {
LOG_ERR("BLE HCI RX callback registration failed");
break;
}
ret = PLATFORM_StartHci();
if (ret < 0) {
LOG_ERR("HCI open failed");
break;
}
hci->recv = recv;
} while (false);
return ret;
}
int bt_nxp_setup(const struct device *dev, const struct bt_hci_setup_params *params)
{
ARG_UNUSED(dev);
ARG_UNUSED(params);
int ret;
do {
#if CONFIG_HCI_NXP_SET_CAL_DATA
ret = bt_nxp_set_calibration_data();
if (ret < 0) {
LOG_ERR("Failed to set calibration data");
break;
}
#if CONFIG_HCI_NXP_SET_CAL_DATA_ANNEX100
/* After send annex55 to CPU2, CPU2 need reset,
* a delay of at least 20ms is required to continue sending annex100
*/
k_sleep(Z_TIMEOUT_MS(20));
ret = bt_nxp_set_calibration_data_annex100();
if (ret < 0) {
LOG_ERR("Failed to set calibration data");
break;
}
#endif /* CONFIG_HCI_NXP_SET_CAL_DATA_ANNEX100 */
#endif /* CONFIG_HCI_NXP_SET_CAL_DATA */
#if CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP
ret = nxp_bt_set_host_sleep_config();
if (ret < 0) {
LOG_ERR("Failed to set host sleep config");
break;
}
ret = nxp_bt_enable_controller_autosleep();
if (ret < 0) {
LOG_ERR("Failed to configure controller autosleep");
break;
}
#endif /* CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP */
} while (false);
return ret;
}
static int bt_nxp_close(const struct device *dev)
{
struct bt_nxp_data *hci = dev->data;
int ret = 0;
/* Reset the Controller */
#if CONFIG_BT_HCI_HOST
ret = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, NULL);
if (ret) {
LOG_ERR("Failed to reset BLE controller");
}
k_sleep(K_SECONDS(1));
ret = PLATFORM_TerminateBle();
if (ret < 0) {
LOG_ERR("Failed to shutdown BLE controller");
}
#endif
hci->recv = NULL;
return ret;
}
static const struct bt_hci_driver_api drv = {
.open = bt_nxp_open,
.setup = bt_nxp_setup,
.close = bt_nxp_close,
.send = bt_nxp_send,
};
static int bt_nxp_init(const struct device *dev)
{
int status;
int ret = 0;
ARG_UNUSED(dev);
/* HCI Interrupt */
IRQ_CONNECT(HCI_IRQ_N, HCI_IRQ_P, ble_hci_handler, 0, 0);
irq_enable(HCI_IRQ_N);
/* Wake up done interrupt */
IRQ_CONNECT(HCI_WAKEUP_IRQ_N, HCI_WAKEUP_IRQ_P, ble_wakeup_done_handler, 0, 0);
irq_enable(HCI_WAKEUP_IRQ_N);
#if (DT_INST_PROP(0, wakeup_source)) && CONFIG_PM
EnableDeepSleepIRQ(HCI_IRQ_N);
#endif
do {
status = PLATFORM_InitBle();
if (status < 0) {
LOG_ERR("BLE Controller initialization failed");
ret = status;
break;
}
} while (0);
return ret;
}
#define HCI_DEVICE_INIT(inst) \
static struct bt_nxp_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, bt_nxp_init, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_BT_HCI_INIT_PRIORITY, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_nxp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,017 |
```c
/* h4.c - H:4 UART based Bluetooth driver */
/*
*
*/
#include <errno.h>
#include <stddef.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/bluetooth/bluetooth.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_driver);
#include "common/bt_str.h"
#include "../util.h"
#define DT_DRV_COMPAT zephyr_bt_hci_uart
struct h4_data {
struct {
struct net_buf *buf;
struct k_fifo fifo;
uint16_t remaining;
uint16_t discard;
bool have_hdr;
bool discardable;
uint8_t hdr_len;
uint8_t type;
union {
struct bt_hci_evt_hdr evt;
struct bt_hci_acl_hdr acl;
struct bt_hci_iso_hdr iso;
uint8_t hdr[4];
};
} rx;
struct {
uint8_t type;
struct net_buf *buf;
struct k_fifo fifo;
} tx;
bt_hci_recv_t recv;
};
struct h4_config {
const struct device *uart;
k_thread_stack_t *rx_thread_stack;
size_t rx_thread_stack_size;
struct k_thread *rx_thread;
};
static inline void h4_get_type(const struct device *dev)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
/* Get packet type */
if (uart_fifo_read(cfg->uart, &h4->rx.type, 1) != 1) {
LOG_WRN("Unable to read H:4 packet type");
h4->rx.type = BT_HCI_H4_NONE;
return;
}
switch (h4->rx.type) {
case BT_HCI_H4_EVT:
h4->rx.remaining = sizeof(h4->rx.evt);
h4->rx.hdr_len = h4->rx.remaining;
break;
case BT_HCI_H4_ACL:
h4->rx.remaining = sizeof(h4->rx.acl);
h4->rx.hdr_len = h4->rx.remaining;
break;
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
h4->rx.remaining = sizeof(h4->rx.iso);
h4->rx.hdr_len = h4->rx.remaining;
break;
}
__fallthrough;
default:
LOG_ERR("Unknown H:4 type 0x%02x", h4->rx.type);
h4->rx.type = BT_HCI_H4_NONE;
}
}
static void h4_read_hdr(const struct device *dev)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
int bytes_read = h4->rx.hdr_len - h4->rx.remaining;
int ret;
ret = uart_fifo_read(cfg->uart, h4->rx.hdr + bytes_read, h4->rx.remaining);
if (unlikely(ret < 0)) {
LOG_ERR("Unable to read from UART (ret %d)", ret);
} else {
h4->rx.remaining -= ret;
}
}
static inline void get_acl_hdr(const struct device *dev)
{
struct h4_data *h4 = dev->data;
h4_read_hdr(dev);
if (!h4->rx.remaining) {
struct bt_hci_acl_hdr *hdr = &h4->rx.acl;
h4->rx.remaining = sys_le16_to_cpu(hdr->len);
LOG_DBG("Got ACL header. Payload %u bytes", h4->rx.remaining);
h4->rx.have_hdr = true;
}
}
static inline void get_iso_hdr(const struct device *dev)
{
struct h4_data *h4 = dev->data;
h4_read_hdr(dev);
if (!h4->rx.remaining) {
struct bt_hci_iso_hdr *hdr = &h4->rx.iso;
h4->rx.remaining = bt_iso_hdr_len(sys_le16_to_cpu(hdr->len));
LOG_DBG("Got ISO header. Payload %u bytes", h4->rx.remaining);
h4->rx.have_hdr = true;
}
}
static inline void get_evt_hdr(const struct device *dev)
{
struct h4_data *h4 = dev->data;
struct bt_hci_evt_hdr *hdr = &h4->rx.evt;
h4_read_hdr(dev);
if (h4->rx.hdr_len == sizeof(*hdr) && h4->rx.remaining < sizeof(*hdr)) {
switch (h4->rx.evt.evt) {
case BT_HCI_EVT_LE_META_EVENT:
h4->rx.remaining++;
h4->rx.hdr_len++;
break;
#if defined(CONFIG_BT_CLASSIC)
case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI:
case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT:
h4->rx.discardable = true;
break;
#endif
}
}
if (!h4->rx.remaining) {
if (h4->rx.evt.evt == BT_HCI_EVT_LE_META_EVENT &&
(h4->rx.hdr[sizeof(*hdr)] == BT_HCI_EVT_LE_ADVERTISING_REPORT)) {
LOG_DBG("Marking adv report as discardable");
h4->rx.discardable = true;
}
h4->rx.remaining = hdr->len - (h4->rx.hdr_len - sizeof(*hdr));
LOG_DBG("Got event header. Payload %u bytes", hdr->len);
h4->rx.have_hdr = true;
}
}
static inline void copy_hdr(struct h4_data *h4)
{
net_buf_add_mem(h4->rx.buf, h4->rx.hdr, h4->rx.hdr_len);
}
static void reset_rx(struct h4_data *h4)
{
h4->rx.type = BT_HCI_H4_NONE;
h4->rx.remaining = 0U;
h4->rx.have_hdr = false;
h4->rx.hdr_len = 0U;
h4->rx.discardable = false;
}
static struct net_buf *get_rx(struct h4_data *h4, k_timeout_t timeout)
{
LOG_DBG("type 0x%02x, evt 0x%02x", h4->rx.type, h4->rx.evt.evt);
switch (h4->rx.type) {
case BT_HCI_H4_EVT:
return bt_buf_get_evt(h4->rx.evt.evt, h4->rx.discardable, timeout);
case BT_HCI_H4_ACL:
return bt_buf_get_rx(BT_BUF_ACL_IN, timeout);
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
return bt_buf_get_rx(BT_BUF_ISO_IN, timeout);
}
}
return NULL;
}
static void rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
struct net_buf *buf;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
LOG_DBG("started");
while (1) {
LOG_DBG("rx.buf %p", h4->rx.buf);
/* We can only do the allocation if we know the initial
* header, since Command Complete/Status events must use the
* original command buffer (if available).
*/
if (h4->rx.have_hdr && !h4->rx.buf) {
h4->rx.buf = get_rx(h4, K_FOREVER);
LOG_DBG("Got rx.buf %p", h4->rx.buf);
if (h4->rx.remaining > net_buf_tailroom(h4->rx.buf)) {
LOG_ERR("Not enough space in buffer");
h4->rx.discard = h4->rx.remaining;
reset_rx(h4);
} else {
copy_hdr(h4);
}
}
/* Let the ISR continue receiving new packets */
uart_irq_rx_enable(cfg->uart);
buf = k_fifo_get(&h4->rx.fifo, K_FOREVER);
do {
uart_irq_rx_enable(cfg->uart);
LOG_DBG("Calling bt_recv(%p)", buf);
h4->recv(dev, buf);
/* Give other threads a chance to run if the ISR
* is receiving data so fast that rx.fifo never
* or very rarely goes empty.
*/
k_yield();
uart_irq_rx_disable(cfg->uart);
buf = k_fifo_get(&h4->rx.fifo, K_NO_WAIT);
} while (buf);
}
}
static size_t h4_discard(const struct device *uart, size_t len)
{
uint8_t buf[33];
int err;
err = uart_fifo_read(uart, buf, MIN(len, sizeof(buf)));
if (unlikely(err < 0)) {
LOG_ERR("Unable to read from UART (err %d)", err);
return 0;
}
return err;
}
static inline void read_payload(const struct device *dev)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
struct net_buf *buf;
int read;
if (!h4->rx.buf) {
size_t buf_tailroom;
h4->rx.buf = get_rx(h4, K_NO_WAIT);
if (!h4->rx.buf) {
if (h4->rx.discardable) {
LOG_WRN("Discarding event 0x%02x", h4->rx.evt.evt);
h4->rx.discard = h4->rx.remaining;
reset_rx(h4);
return;
}
LOG_WRN("Failed to allocate, deferring to rx_thread");
uart_irq_rx_disable(cfg->uart);
return;
}
LOG_DBG("Allocated rx.buf %p", h4->rx.buf);
buf_tailroom = net_buf_tailroom(h4->rx.buf);
if (buf_tailroom < h4->rx.remaining) {
LOG_ERR("Not enough space in buffer %u/%zu", h4->rx.remaining,
buf_tailroom);
h4->rx.discard = h4->rx.remaining;
reset_rx(h4);
return;
}
copy_hdr(h4);
}
read = uart_fifo_read(cfg->uart, net_buf_tail(h4->rx.buf), h4->rx.remaining);
if (unlikely(read < 0)) {
LOG_ERR("Failed to read UART (err %d)", read);
return;
}
net_buf_add(h4->rx.buf, read);
h4->rx.remaining -= read;
LOG_DBG("got %d bytes, remaining %u", read, h4->rx.remaining);
LOG_DBG("Payload (len %u): %s", h4->rx.buf->len,
bt_hex(h4->rx.buf->data, h4->rx.buf->len));
if (h4->rx.remaining) {
return;
}
buf = h4->rx.buf;
h4->rx.buf = NULL;
if (h4->rx.type == BT_HCI_H4_EVT) {
bt_buf_set_type(buf, BT_BUF_EVT);
} else {
bt_buf_set_type(buf, BT_BUF_ACL_IN);
}
reset_rx(h4);
LOG_DBG("Putting buf %p to rx fifo", buf);
k_fifo_put(&h4->rx.fifo, buf);
}
static inline void read_header(const struct device *dev)
{
struct h4_data *h4 = dev->data;
switch (h4->rx.type) {
case BT_HCI_H4_NONE:
h4_get_type(dev);
return;
case BT_HCI_H4_EVT:
get_evt_hdr(dev);
break;
case BT_HCI_H4_ACL:
get_acl_hdr(dev);
break;
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
get_iso_hdr(dev);
break;
}
__fallthrough;
default:
CODE_UNREACHABLE;
return;
}
if (h4->rx.have_hdr && h4->rx.buf) {
if (h4->rx.remaining > net_buf_tailroom(h4->rx.buf)) {
LOG_ERR("Not enough space in buffer");
h4->rx.discard = h4->rx.remaining;
reset_rx(h4);
} else {
copy_hdr(h4);
}
}
}
static inline void process_tx(const struct device *dev)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
int bytes;
if (!h4->tx.buf) {
h4->tx.buf = k_fifo_get(&h4->tx.fifo, K_NO_WAIT);
if (!h4->tx.buf) {
LOG_ERR("TX interrupt but no pending buffer!");
uart_irq_tx_disable(cfg->uart);
return;
}
}
if (!h4->tx.type) {
switch (bt_buf_get_type(h4->tx.buf)) {
case BT_BUF_ACL_OUT:
h4->tx.type = BT_HCI_H4_ACL;
break;
case BT_BUF_CMD:
h4->tx.type = BT_HCI_H4_CMD;
break;
case BT_BUF_ISO_OUT:
if (IS_ENABLED(CONFIG_BT_ISO)) {
h4->tx.type = BT_HCI_H4_ISO;
break;
}
__fallthrough;
default:
LOG_ERR("Unknown buffer type");
goto done;
}
bytes = uart_fifo_fill(cfg->uart, &h4->tx.type, 1);
if (bytes != 1) {
LOG_WRN("Unable to send H:4 type");
h4->tx.type = BT_HCI_H4_NONE;
return;
}
}
bytes = uart_fifo_fill(cfg->uart, h4->tx.buf->data, h4->tx.buf->len);
if (unlikely(bytes < 0)) {
LOG_ERR("Unable to write to UART (err %d)", bytes);
} else {
net_buf_pull(h4->tx.buf, bytes);
}
if (h4->tx.buf->len) {
return;
}
done:
h4->tx.type = BT_HCI_H4_NONE;
net_buf_unref(h4->tx.buf);
h4->tx.buf = k_fifo_get(&h4->tx.fifo, K_NO_WAIT);
if (!h4->tx.buf) {
uart_irq_tx_disable(cfg->uart);
}
}
static inline void process_rx(const struct device *dev)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
LOG_DBG("remaining %u discard %u have_hdr %u rx.buf %p len %u",
h4->rx.remaining, h4->rx.discard, h4->rx.have_hdr, h4->rx.buf,
h4->rx.buf ? h4->rx.buf->len : 0);
if (h4->rx.discard) {
h4->rx.discard -= h4_discard(cfg->uart, h4->rx.discard);
return;
}
if (h4->rx.have_hdr) {
read_payload(dev);
} else {
read_header(dev);
}
}
static void bt_uart_isr(const struct device *uart, void *user_data)
{
struct device *dev = user_data;
while (uart_irq_update(uart) && uart_irq_is_pending(uart)) {
if (uart_irq_tx_ready(uart)) {
process_tx(dev);
}
if (uart_irq_rx_ready(uart)) {
process_rx(dev);
}
}
}
static int h4_send(const struct device *dev, struct net_buf *buf)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
k_fifo_put(&h4->tx.fifo, buf);
uart_irq_tx_enable(cfg->uart);
return 0;
}
/** Setup the HCI transport, which usually means to reset the Bluetooth IC
*
* @param dev The device structure for the bus connecting to the IC
*
* @return 0 on success, negative error value on failure
*/
int __weak bt_hci_transport_setup(const struct device *uart)
{
h4_discard(uart, 32);
return 0;
}
static int h4_open(const struct device *dev, bt_hci_recv_t recv)
{
const struct h4_config *cfg = dev->config;
struct h4_data *h4 = dev->data;
int ret;
k_tid_t tid;
LOG_DBG("");
uart_irq_rx_disable(cfg->uart);
uart_irq_tx_disable(cfg->uart);
ret = bt_hci_transport_setup(cfg->uart);
if (ret < 0) {
return -EIO;
}
h4->recv = recv;
uart_irq_callback_user_data_set(cfg->uart, bt_uart_isr, (void *)dev);
tid = k_thread_create(cfg->rx_thread, cfg->rx_thread_stack,
cfg->rx_thread_stack_size,
rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_RX_PRIO),
0, K_NO_WAIT);
k_thread_name_set(tid, "bt_rx_thread");
return 0;
}
#if defined(CONFIG_BT_HCI_SETUP)
static int h4_setup(const struct device *dev, const struct bt_hci_setup_params *params)
{
const struct h4_config *cfg = dev->config;
ARG_UNUSED(params);
/* Extern bt_h4_vnd_setup function.
* This function executes vendor-specific commands sequence to
* initialize BT Controller before BT Host executes Reset sequence.
* bt_h4_vnd_setup function must be implemented in vendor-specific HCI
* extansion module if CONFIG_BT_HCI_SETUP is enabled.
*/
extern int bt_h4_vnd_setup(const struct device *dev);
return bt_h4_vnd_setup(cfg->uart);
}
#endif
static const struct bt_hci_driver_api h4_driver_api = {
.open = h4_open,
.send = h4_send,
#if defined(CONFIG_BT_HCI_SETUP)
.setup = h4_setup,
#endif
};
#define BT_UART_DEVICE_INIT(inst) \
static K_KERNEL_STACK_DEFINE(rx_thread_stack_##inst, CONFIG_BT_DRV_RX_STACK_SIZE); \
static struct k_thread rx_thread_##inst; \
static const struct h4_config h4_config_##inst = { \
.uart = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
.rx_thread_stack = rx_thread_stack_##inst, \
.rx_thread_stack_size = K_KERNEL_STACK_SIZEOF(rx_thread_stack_##inst), \
.rx_thread = &rx_thread_##inst, \
}; \
static struct h4_data h4_data_##inst = { \
.rx = { \
.fifo = Z_FIFO_INITIALIZER(h4_data_##inst.rx.fifo), \
}, \
.tx = { \
.fifo = Z_FIFO_INITIALIZER(h4_data_##inst.tx.fifo), \
}, \
}; \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &h4_data_##inst, &h4_config_##inst, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &h4_driver_api)
DT_INST_FOREACH_STATUS_OKAY(BT_UART_DEVICE_INIT)
``` | /content/code_sandbox/drivers/bluetooth/hci/h4.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,285 |
```c
/* hci_da1469x.c - DA1469x CMAC IPC Bluetooth driver */
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <zephyr/bluetooth/hci.h>
#include <zephyr/drivers/bluetooth.h>
#include <zephyr/irq.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/random/random.h>
#include <common/bt_str.h>
#include <DA1469xAB.h>
#include <mbox.h>
#include <shm.h>
#include <rand.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(hci_da1469x);
#define DT_DRV_COMPAT renesas_bt_hci_da1469x
struct hci_data {
bt_hci_recv_t recv;
};
static K_KERNEL_STACK_DEFINE(rng_thread_stack, CONFIG_BT_RX_STACK_SIZE);
static struct k_thread rng_thread_data;
struct k_sem rng_sem;
static K_KERNEL_STACK_DEFINE(rx_thread_stack, CONFIG_BT_RX_STACK_SIZE);
static struct k_thread rx_thread_data;
static struct {
struct net_buf *buf;
struct k_fifo fifo;
uint16_t remaining;
uint16_t discard;
bool have_hdr;
bool discardable;
bool deferred;
uint8_t hdr_len;
uint8_t type;
union {
struct bt_hci_evt_hdr evt;
struct bt_hci_acl_hdr acl;
struct bt_hci_iso_hdr iso;
uint8_t hdr[4];
};
} rx = {
.fifo = Z_FIFO_INITIALIZER(rx.fifo),
};
static void h4_get_type(void)
{
/* Get packet type */
if (cmac_mbox_read(&rx.type, 1) != 1) {
LOG_WRN("Unable to read H:4 packet type");
rx.type = BT_HCI_H4_NONE;
return;
}
switch (rx.type) {
case BT_HCI_H4_EVT:
rx.remaining = sizeof(rx.evt);
rx.hdr_len = rx.remaining;
break;
case BT_HCI_H4_ACL:
rx.remaining = sizeof(rx.acl);
rx.hdr_len = rx.remaining;
break;
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
rx.remaining = sizeof(rx.iso);
rx.hdr_len = rx.remaining;
break;
}
__fallthrough;
default:
LOG_ERR("Unknown H:4 type 0x%02x", rx.type);
rx.type = BT_HCI_H4_NONE;
}
}
static void h4_read_hdr(void)
{
int bytes_read = rx.hdr_len - rx.remaining;
int ret;
ret = cmac_mbox_read(rx.hdr + bytes_read, rx.remaining);
if (unlikely(ret < 0)) {
LOG_ERR("Unable to read from mailbox (ret %d)", ret);
} else {
rx.remaining -= ret;
}
}
static inline void get_acl_hdr(void)
{
h4_read_hdr();
if (!rx.remaining) {
struct bt_hci_acl_hdr *hdr = &rx.acl;
rx.remaining = sys_le16_to_cpu(hdr->len);
LOG_DBG("Got ACL header. Payload %u bytes", rx.remaining);
rx.have_hdr = true;
}
}
static inline void get_iso_hdr(void)
{
h4_read_hdr();
if (!rx.remaining) {
struct bt_hci_iso_hdr *hdr = &rx.iso;
rx.remaining = bt_iso_hdr_len(sys_le16_to_cpu(hdr->len));
LOG_DBG("Got ISO header. Payload %u bytes", rx.remaining);
rx.have_hdr = true;
}
}
static inline void get_evt_hdr(void)
{
struct bt_hci_evt_hdr *hdr = &rx.evt;
h4_read_hdr();
if (rx.hdr_len == sizeof(*hdr) && rx.remaining < sizeof(*hdr)) {
switch (rx.evt.evt) {
case BT_HCI_EVT_LE_META_EVENT:
rx.remaining++;
rx.hdr_len++;
break;
}
}
if (!rx.remaining) {
if (rx.evt.evt == BT_HCI_EVT_LE_META_EVENT &&
(rx.hdr[sizeof(*hdr)] == BT_HCI_EVT_LE_ADVERTISING_REPORT)) {
LOG_DBG("Marking adv report as discardable");
rx.discardable = true;
}
rx.remaining = hdr->len - (rx.hdr_len - sizeof(*hdr));
LOG_DBG("Got event header. Payload %u bytes", hdr->len);
rx.have_hdr = true;
}
}
static inline void copy_hdr(struct net_buf *buf)
{
net_buf_add_mem(buf, rx.hdr, rx.hdr_len);
}
static void reset_rx(void)
{
rx.type = BT_HCI_H4_NONE;
rx.remaining = 0U;
rx.have_hdr = false;
rx.hdr_len = 0U;
rx.discardable = false;
}
static struct net_buf *get_rx(k_timeout_t timeout)
{
LOG_DBG("type 0x%02x, evt 0x%02x", rx.type, rx.evt.evt);
switch (rx.type) {
case BT_HCI_H4_EVT:
return bt_buf_get_evt(rx.evt.evt, rx.discardable, timeout);
case BT_HCI_H4_ACL:
return bt_buf_get_rx(BT_BUF_ACL_IN, timeout);
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
return bt_buf_get_rx(BT_BUF_ISO_IN, timeout);
}
}
return NULL;
}
static void rx_isr_start(void)
{
if (rx.deferred) {
rx.deferred = false;
NVIC_SetPendingIRQ(CMAC2SYS_IRQn);
}
irq_enable(CMAC2SYS_IRQn);
}
static void rx_isr_stop(void)
{
irq_disable(CMAC2SYS_IRQn);
}
static void rx_thread(void *p1, void *p2, void *p3)
{
const struct device *dev = p1;
struct hci_data *hci = dev->data;
struct net_buf *buf;
ARG_UNUSED(p2);
ARG_UNUSED(p3);
LOG_DBG("started");
while (1) {
LOG_DBG("rx.buf %p", rx.buf);
/* We can only do the allocation if we know the initial
* header, since Command Complete/Status events must use the
* original command buffer (if available).
*/
if (rx.have_hdr && !rx.buf) {
rx.buf = get_rx(K_FOREVER);
LOG_DBG("Got rx.buf %p", rx.buf);
if (rx.remaining > net_buf_tailroom(rx.buf)) {
LOG_ERR("Not enough space in buffer");
rx.discard = rx.remaining;
reset_rx();
} else {
copy_hdr(rx.buf);
}
}
/* Let the ISR continue receiving new packets */
rx_isr_start();
buf = k_fifo_get(&rx.fifo, K_FOREVER);
do {
rx_isr_start();
LOG_DBG("Calling bt_recv(%p)", buf);
hci->recv(dev, buf);
/* Give other threads a chance to run if the ISR
* is receiving data so fast that rx.fifo never
* or very rarely goes empty.
*/
k_yield();
rx_isr_stop();
buf = k_fifo_get(&rx.fifo, K_NO_WAIT);
} while (buf);
}
}
static size_t h4_discard(size_t len)
{
uint8_t buf[33];
int err;
err = cmac_mbox_read(buf, MIN(len, sizeof(buf)));
if (unlikely(err < 0)) {
LOG_ERR("Unable to read from mailbox (err %d)", err);
return 0;
}
return err;
}
static inline void read_payload(void)
{
struct net_buf *buf;
int read;
if (!rx.buf) {
size_t buf_tailroom;
rx.buf = get_rx(K_NO_WAIT);
if (!rx.buf) {
if (rx.discardable) {
LOG_WRN("Discarding event 0x%02x", rx.evt.evt);
rx.discard = rx.remaining;
reset_rx();
return;
}
LOG_WRN("Failed to allocate, deferring to rx_thread");
rx.deferred = true;
return;
}
LOG_DBG("Allocated rx.buf %p", rx.buf);
buf_tailroom = net_buf_tailroom(rx.buf);
if (buf_tailroom < rx.remaining) {
LOG_ERR("Not enough space in buffer %u/%zu", rx.remaining, buf_tailroom);
rx.discard = rx.remaining;
reset_rx();
return;
}
copy_hdr(rx.buf);
}
read = cmac_mbox_read(net_buf_tail(rx.buf), rx.remaining);
if (unlikely(read < 0)) {
LOG_ERR("Failed to read mailbox (err %d)", read);
return;
}
net_buf_add(rx.buf, read);
rx.remaining -= read;
LOG_DBG("got %d bytes, remaining %u", read, rx.remaining);
LOG_DBG("Payload (len %u): %s", rx.buf->len, bt_hex(rx.buf->data, rx.buf->len));
if (rx.remaining) {
return;
}
buf = rx.buf;
rx.buf = NULL;
if (rx.type == BT_HCI_H4_EVT) {
bt_buf_set_type(buf, BT_BUF_EVT);
} else {
bt_buf_set_type(buf, BT_BUF_ACL_IN);
}
reset_rx();
LOG_DBG("Putting buf %p to rx fifo", buf);
k_fifo_put(&rx.fifo, buf);
}
static inline void read_header(void)
{
switch (rx.type) {
case BT_HCI_H4_NONE:
h4_get_type();
return;
case BT_HCI_H4_EVT:
get_evt_hdr();
break;
case BT_HCI_H4_ACL:
get_acl_hdr();
break;
case BT_HCI_H4_ISO:
if (IS_ENABLED(CONFIG_BT_ISO)) {
get_iso_hdr();
break;
}
__fallthrough;
default:
CODE_UNREACHABLE;
return;
}
if (rx.have_hdr && rx.buf) {
if (rx.remaining > net_buf_tailroom(rx.buf)) {
LOG_ERR("Not enough space in buffer");
rx.discard = rx.remaining;
reset_rx();
} else {
copy_hdr(rx.buf);
}
}
}
static inline void process_rx(void)
{
LOG_DBG("remaining %u discard %u have_hdr %u rx.buf %p len %u", rx.remaining, rx.discard,
rx.have_hdr, rx.buf, rx.buf ? rx.buf->len : 0);
if (rx.discard) {
rx.discard -= h4_discard(rx.discard);
return;
}
if (rx.have_hdr) {
read_payload();
} else {
read_header();
}
}
/* Called by HAL when data in CMAC mailbox is available to read */
void cmac_read_req(void)
{
while (!rx.deferred && cmac_mbox_has_data()) {
process_rx();
}
}
/* Called by HAL when CMAC requests host to put more data in rng buffer */
void cmac_rng_req(void)
{
k_sem_give(&rng_sem);
}
static void rng_thread(void *p1, void *p2, void *p3)
{
uint32_t word;
ARG_UNUSED(p1);
ARG_UNUSED(p2);
ARG_UNUSED(p3);
while (1) {
k_sem_take(&rng_sem, K_FOREVER);
while (cmac_rand_needs_data()) {
word = sys_rand32_get();
cmac_rand_fill(&word, 1);
}
cmac_signal();
}
}
static int bt_da1469x_open(const struct device *dev, bt_hci_recv_t recv)
{
struct hci_data *hci = dev->data;
k_tid_t tid;
tid = k_thread_create(&rx_thread_data, rx_thread_stack,
K_KERNEL_STACK_SIZEOF(rx_thread_stack),
rx_thread, (void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_RX_PRIO),
0, K_NO_WAIT);
k_thread_name_set(tid, "bt_rx_thread");
k_sem_init(&rng_sem, 0, 1);
tid = k_thread_create(&rng_thread_data, rng_thread_stack,
K_KERNEL_STACK_SIZEOF(rng_thread_stack),
rng_thread, NULL, NULL, NULL,
K_PRIO_COOP(CONFIG_BT_RX_PRIO),
0, K_NO_WAIT);
k_thread_name_set(tid, "bt_rng_thread");
hci->recv = recv;
cmac_enable();
irq_enable(CMAC2SYS_IRQn);
return 0;
}
#ifdef CONFIG_BT_HCI_HOST
static int bt_da1469x_close(const struct device *dev)
{
struct hci_data *hci = dev->data;
irq_disable(CMAC2SYS_IRQn);
cmac_disable();
hci->recv = NULL;
return 0;
}
#endif /* CONFIG_BT_HCI_HOST */
static int bt_da1469x_send(const struct device *dev, struct net_buf *buf)
{
ARG_UNUSED(dev);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
LOG_DBG("ACL: buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
net_buf_push_u8(buf, BT_HCI_H4_ACL);
break;
case BT_BUF_CMD:
LOG_DBG("CMD: buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
net_buf_push_u8(buf, BT_HCI_H4_CMD);
break;
default:
LOG_ERR("Unsupported type");
return -EINVAL;
}
cmac_mbox_write(buf->data, buf->len);
net_buf_unref(buf);
return 0;
}
static const struct bt_hci_driver_api drv = {
.open = bt_da1469x_open,
.close = bt_da1469x_close,
.send = bt_da1469x_send,
};
static int bt_da1469x_init(const struct device *dev)
{
irq_disable(CMAC2SYS_IRQn);
cmac_disable();
cmac_load_image();
cmac_configure_pdc();
cmac_configure_shm();
IRQ_CONNECT(CMAC2SYS_IRQn, 0, cmac_cmac2sys_isr, NULL, 0);
return 0;
}
#define HCI_DEVICE_INIT(inst) \
static struct hci_data hci_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, bt_da1469x_init, NULL, &hci_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
/* Only one instance supported right now */
HCI_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_da1469x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,212 |
```unknown
# Bluetooth drivers configuration options
comment "Bluetooth HCI Driver Options"
config BT_UART
bool
select SERIAL
select UART_INTERRUPT_DRIVEN
config BT_H4
bool "H:4 UART"
select BT_UART
default y
depends on DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED
help
Bluetooth H:4 UART driver. Requires hardware flow control
lines to be available.
config BT_H5
bool "H:5 UART [EXPERIMENTAL]"
select BT_UART
select EXPERIMENTAL
default y
depends on DT_HAS_ZEPHYR_BT_HCI_3WIRE_UART_ENABLED
help
Bluetooth three-wire (H:5) UART driver. Implementation of HCI
Three-Wire UART Transport Layer.
# Removed: Here only to give the user a warning about its removal
# Remove after 3.7.0 is released
config BT_RPMSG
bool "[REMOVED] HCI using RPMsg"
help
Use BT_HCI_IPC instead
config BT_HCI_IPC
bool "HCI using the IPC subsystem"
default y
depends on DT_HAS_ZEPHYR_BT_HCI_IPC_ENABLED
select BT_HAS_HCI_VS
select IPC_SERVICE
select MBOX
help
Bluetooth HCI driver for communication with another CPU
using the IPC subsystem.
config BT_SPI
bool "SPI HCI"
select SPI
help
Supports Bluetooth ICs using SPI as the communication protocol.
HCI packets are sent and received as single Byte transfers,
prepended after a known header. Headers may vary per device, so
additional platform specific knowledge may need to be added as
devices are.
config BT_STM32_IPM
bool "IPM HCI"
default y
depends on DT_HAS_ST_STM32WB_RF_ENABLED
select USE_STM32_HAL_CORTEX
select HAS_STM32LIB
select BT_HCI_SETUP
help
TODO
config BT_STM32WBA
bool "STM32WBA HCI driver"
default y
depends on DT_HAS_ST_HCI_STM32WBA_ENABLED
select HAS_STM32LIB
select BT_HCI_SET_PUBLIC_ADDR
help
ST STM32WBA HCI Bluetooth interface
config BT_SILABS_HCI
bool "Silicon Labs Bluetooth interface"
default y
depends on DT_HAS_SILABS_BT_HCI_ENABLED
depends on !PM || SOC_GECKO_PM_BACKEND_PMGR
select SOC_GECKO_USE_RAIL
select ENTROPY_GENERATOR
select MBEDTLS
select MBEDTLS_PSA_CRYPTO_C
select MBEDTLS_ENTROPY_ENABLED
select MBEDTLS_ZEPHYR_ENTROPY
help
Use Silicon Labs binary Bluetooth library to connect to the
controller.
config BT_USERCHAN
bool "HCI User Channel based driver"
depends on (BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM)
default y
depends on DT_HAS_ZEPHYR_BT_HCI_USERCHAN_ENABLED
help
This driver provides access to the local Linux host's Bluetooth
adapter using a User Channel HCI socket to the Linux kernel. It
is only intended to be used with the native POSIX build of Zephyr.
The Bluetooth adapter must be powered off in order for Zephyr to
be able to use it.
config BT_ESP32
bool "ESP32 HCI driver"
default y
depends on DT_HAS_ESPRESSIF_ESP32_BT_HCI_ENABLED
help
Espressif HCI bluetooth interface
config BT_PSOC6_BLESS
bool "PSOC6 BLESS driver"
default y
depends on DT_HAS_INFINEON_CAT1_BLESS_HCI_ENABLED
select BT_HCI_SETUP
help
PSOC6 BLESS driver with BLE Controller which operates in
Single CPU mode.
config BT_DA1469X
bool "DA1469x HCI driver"
default y
depends on DT_HAS_RENESAS_BT_HCI_DA1469X_ENABLED
help
Bluetooth HCI driver for communication with CMAC core
on DA1469x MCU.
config BT_NXP
bool "NXP HCI driver"
default y
depends on DT_HAS_NXP_HCI_BLE_ENABLED
select BT_HCI_SETUP
select USE_DT_CODE_PARTITION if !NXP_MONOLITHIC_BT
help
NXP HCI bluetooth interface
config BT_CYW208XX
bool "CYW208XX BLE driver"
default y
depends on DT_HAS_INFINEON_CYW208XX_HCI_ENABLED
help
Infineon CYW208XX HCI bluetooth interface
config BT_AMBIQ_HCI
bool "AMBIQ BT HCI driver"
default y
depends on DT_HAS_AMBIQ_BT_HCI_SPI_ENABLED
select SPI
select GPIO if SOC_SERIES_APOLLO4X
select CLOCK_CONTROL if SOC_SERIES_APOLLO4X
select BT_HCI_SETUP
help
Supports Ambiq Bluetooth SoC using SPI as the communication protocol.
HCI packets are sent and received as single Byte transfers.
if BT_SPI
config BT_SPI_INIT_PRIORITY
int "BT SPI init priority"
default 75
config BT_BLUENRG_ACI
bool "ACI message with BlueNRG-based devices"
select BT_HCI_SET_PUBLIC_ADDR
help
Enable support for devices compatible with the BlueNRG Bluetooth
Stack. Current driver supports: ST BLUENRG-MS.
endif # BT_SPI
config BT_HCI_INIT_PRIORITY
int "BT HCI init priority"
default 75 if BT_AMBIQ_HCI
default KERNEL_INIT_PRIORITY_DEVICE
help
The priority of BT HCI driver initialization.
config BT_STM32_IPM_RX_STACK_SIZE
int "STM32 IPM stack size for RX thread"
depends on BT_STM32_IPM
default 512
menuconfig BT_AIROC
bool "AIROC BT connectivity"
default y
select GPIO if BT_H4
select UART if BT_H4
select UART_USE_RUNTIME_CONFIGURE if BT_H4
select BT_HCI_SETUP
select USE_INFINEON_ABSTRACTION_RTOS if BT_CYW208XX
select EVENTS if BT_CYW208XX
depends on DT_HAS_INFINEON_CYW43XXX_BT_HCI_ENABLED || DT_HAS_INFINEON_CYW208XX_HCI_ENABLED
help
Infineon's AIROC Wi-Fi & combos portfolio integrates
IEEE 802.11a/b/g/n/ac/ax Wi-Fi and Bluetooth 5.2 in a single-chip
solution to enable small-form-factor IoT designs.
source "drivers/bluetooth/hci/Kconfig.infineon"
source "drivers/bluetooth/hci/Kconfig.nxp"
config BT_DRIVER_QUIRK_NO_AUTO_DLE
bool "Host auto-initiated Data Length Update quirk"
depends on BT_AUTO_DATA_LEN_UPDATE
default y if BT_HCI_IPC || BT_ESP32
help
Enable the quirk wherein BT Host stack will auto-initiate Data Length
Update procedure for new connections for controllers that do not
auto-initiate the procedure if the default data length parameters are
not equal to the initial parameters.
This has to be enabled when the BLE controller connected is Zephyr
open source controller.
config BT_HCI_SET_PUBLIC_ADDR
bool
select BT_HCI_SETUP
help
Pass the controller's public address to the HCI driver in setup()
This option should be enabled by drivers for controllers that support setting the
public identity through vendor-specific commands. They can then implement the
setup() HCI driver API function and get the address to set from the public_addr field.
From the application side, the public address is set using the first call to
bt_id_create(), before calling bt_enable().
config BT_HCI_SETUP
bool
help
Enable the HCI vendor-specific Setup function.
This option has to be enabled when the BT Controller requires execution
of the vendor-specific commands sequence to initialize the BT Controller
before the BT Host executes a Reset sequence.
The user should generally avoid changing it via menuconfig or in
configuration files. This option are enabled by the vendor-specific
HCI extension, where the Setup function is implemented.
config BT_DRV_TX_STACK_SIZE
int
default 256
help
Stack size for the HCI driver's TX thread.
config BT_DRV_RX_STACK_SIZE
int
default 640 if (BT_SPI || BT_AMBIQ_HCI)
default BT_RX_STACK_SIZE if (BT_H4 || BT_HCI_RAW_H4)
default BT_STM32_IPM_RX_STACK_SIZE if BT_STM32_IPM
default 256
help
Stack size for the HCI driver's RX thread.
config BT_SILABS_HCI_BUFFER_MEMORY
int "Silicon Labs Bluetooth Library memory buffer size"
depends on BT_SILABS_HCI
default 6144
help
Select the size of allocated memory buffer for the Silicon Labs
Bluetooth Library.
config BT_H4_NXP_CTLR
bool "NXP Bluetooth Controller"
select GPIO
depends on BT_H4
select CRC
default y
depends on DT_HAS_NXP_BT_HCI_UART_ENABLED
help
Enables support for NXP Bluetooth Controller.
More inforamtion about NXP Bluetooth profuct could be found on
path_to_url
if BT_H4_NXP_CTLR
config BT_H4_NXP_CTLR_WAIT_HDR_SIG_TIMEOUT
int "Timeout for waiting HDR Signure"
range 1000 60000
default 2500
help
Timeout for waiting HDR Signure. Unit is millisecond.
config BT_H4_NXP_CTLR_WAIT_TIME_AFTER_UPLOAD
int "Waiting time after firmware is uploaded"
range 1000 5000
default 1000
help
Waiting time after firmware is uploaded. Unit is millisecond.
endif #BT_H4_NXP_CTLR
``` | /content/code_sandbox/drivers/bluetooth/hci/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,092 |
```c
/*
*
*/
#include <errno.h>
#include <stddef.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/crc.h>
#include <string.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_nxp_ctlr);
#include "common/bt_str.h"
#include "bt_nxp_ctlr_fw.h"
#define DT_DRV_COMPAT nxp_bt_hci_uart
#define FW_UPLOAD_CHANGE_TIMEOUT_RETRY_COUNT 6
static const struct device *uart_dev = DEVICE_DT_GET(DT_INST_GPARENT(0));
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios)
struct gpio_dt_spec sdio_reset = GPIO_DT_SPEC_GET(DT_DRV_INST(0), sdio_reset_gpios);
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios) */
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios)
struct gpio_dt_spec w_disable = GPIO_DT_SPEC_GET(DT_DRV_INST(0), w_disable_gpios);
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios) */
struct nxp_ctlr_dev_data {
uint32_t primary_speed;
bool primary_flowcontrol;
uint32_t secondary_speed;
bool secondary_flowcontrol;
};
static struct nxp_ctlr_dev_data uart_dev_data;
#define DI 0x07U
#define POLYNOMIAL 0x04c11db7UL
#define CRC32_LEN 4
static unsigned long crc_table[256U];
static bool made_table;
static void fw_upload_gen_crc32_table(void)
{
int i, j;
unsigned long crc_accum;
for (i = 0; i < 256; i++) {
crc_accum = ((unsigned long)i << 24);
for (j = 0; j < 8; j++) {
if (crc_accum & 0x80000000L) {
crc_accum = (crc_accum << 1) ^ POLYNOMIAL;
} else {
crc_accum = (crc_accum << 1);
}
}
crc_table[i] = crc_accum;
}
}
static unsigned char fw_upload_crc8(unsigned char *array, unsigned char len)
{
unsigned char crc_8 = 0xff;
crc_8 = crc8(array, len, DI, crc_8, false);
return crc_8;
}
static unsigned long fw_upload_update_crc32(unsigned long crc_accum, char *data_blk_ptr,
int data_blk_size)
{
unsigned int i, j;
for (j = 0; j < data_blk_size; j++) {
i = ((unsigned int)(crc_accum >> 24) ^ *data_blk_ptr++) & 0xff;
crc_accum = (crc_accum << 8) ^ crc_table[i];
}
return crc_accum;
}
#define CMD4 0x4U
#define CMD6 0x6U
#define CMD7 0x7U
#define V1_HEADER_DATA_REQ 0xa5U
#define V1_START_INDICATION 0xaaU
#define V1_REQUEST_ACK 0x5aU
#define V3_START_INDICATION 0xabU
#define V3_HEADER_DATA_REQ 0xa7U
#define V3_REQUEST_ACK 0x7aU
#define V3_TIMEOUT_ACK 0x7bU
#define V3_CRC_ERROR 0x7cU
#define REQ_HEADER_LEN 1U
#define A6REQ_PAYLOAD_LEN 8U
#define AbREQ_PAYLOAD_LEN 3U
#define CRC_ERR_BIT BIT(0)
#define NAK_REC_BIT BIT(1)
#define TIMEOUT_REC_ACK_BIT BIT(2)
#define TIMEOUT_REC_HEAD_BIT BIT(3)
#define TIMEOUT_REC_DATA_BIT BIT(4)
#define INVALID_CMD_REC_BIT BIT(5)
#define WIFI_MIC_FAIL_BIT BIT(6)
#define BT_MIC_FAIL_BIT BIT(7)
#define CMD_HDR_LEN 16
/* CMD5 Header to change bootloader baud rate */
static uint8_t cmd5_hdrData[CMD_HDR_LEN] = {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x2c, 0x00, 0x00, 0x00, 0x77, 0xdb, 0xfd, 0xe0};
/* CMD7 Header to change timeout of bootloader */
static uint8_t cmd7_hdrData[CMD_HDR_LEN] = {0x07, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x5b, 0x88, 0xf8, 0xba};
enum bt_nxp_ctlr_version {
VER1 = 1,
VER2,
VER3,
};
struct change_speed_config {
uint32_t clk_div_addr;
uint32_t clk_div_val;
uint32_t uart_clk_div_addr;
uint32_t uart_clk_div_val;
uint32_t mcr_addr;
uint32_t mcr_val;
uint32_t reinit_addr;
uint32_t reinit_val;
uint32_t icr_addr;
uint32_t icr_val;
uint32_t fcr_addr;
uint32_t fcr_val;
};
#define SEND_BUFFER_MAX_LENGTH 0xFFFFU /* Maximum 2 byte value */
#define RECV_RING_BUFFER_LENGTH 1024
struct nxp_ctlr_fw_upload_state {
uint8_t version;
uint8_t hdr_sig;
uint8_t buffer[A6REQ_PAYLOAD_LEN + REQ_HEADER_LEN + 1];
uint8_t send_buffer[SEND_BUFFER_MAX_LENGTH + 1];
struct {
uint8_t buffer[RECV_RING_BUFFER_LENGTH];
uint32_t head;
uint32_t tail;
struct k_sem sem;
} rx;
uint16_t length;
uint32_t offset;
uint16_t error;
uint8_t crc8;
uint32_t last_offset;
uint8_t change_speed_buffer[sizeof(struct change_speed_config) + CRC32_LEN];
uint32_t fw_length;
uint32_t current_length;
const uint8_t *fw;
uint32_t cmd7_change_timeout_len;
uint32_t change_speed_buffer_len;
bool wait_hdr_sig;
bool is_hdr_data;
bool is_error_case;
bool is_cmd7_req;
bool is_entry_point_req;
uint8_t last_5bytes_buffer[6];
};
static struct nxp_ctlr_fw_upload_state fw_upload;
static int fw_upload_read_data(uint8_t *buffer, uint32_t len)
{
int err;
while (len > 0) {
err = k_sem_take(&fw_upload.rx.sem,
K_MSEC(CONFIG_BT_H4_NXP_CTLR_WAIT_HDR_SIG_TIMEOUT));
if (err < 0) {
LOG_ERR("Fail to read data");
return err;
}
*buffer = fw_upload.rx.buffer[fw_upload.rx.tail];
buffer++;
fw_upload.rx.tail++;
fw_upload.rx.tail = fw_upload.rx.tail % sizeof(fw_upload.rx.buffer);
len--;
}
return 0;
}
static void fw_upload_read_to_clear(void)
{
uint32_t key;
key = irq_lock();
k_sem_reset(&fw_upload.rx.sem);
fw_upload.rx.head = 0;
fw_upload.rx.tail = 0;
irq_unlock(key);
}
static int fw_upload_wait_for_hdr_sig(void)
{
int err;
int64_t end;
char c;
end = k_uptime_get() + CONFIG_BT_H4_NXP_CTLR_WAIT_HDR_SIG_TIMEOUT;
fw_upload.hdr_sig = 0xFF;
while (k_uptime_get() < end) {
err = fw_upload_read_data(&c, 1);
if (err < 0) {
k_msleep(1);
continue;
}
if ((c == V1_HEADER_DATA_REQ) || (c == V1_START_INDICATION) ||
(c == V3_START_INDICATION) || (c == V3_HEADER_DATA_REQ)) {
LOG_DBG("HDR SIG found 0x%02X", c);
fw_upload.hdr_sig = c;
if (fw_upload.version == 0) {
if ((c == V3_START_INDICATION) || (c == V3_HEADER_DATA_REQ)) {
fw_upload.version = VER3;
} else {
fw_upload.version = VER1;
}
}
return 0;
}
}
LOG_ERR("HDR SIG not found");
return -EIO;
}
static void fw_upload_write_data(const uint8_t *buffer, uint32_t len)
{
for (int i = 0; i < len; i++) {
uart_poll_out(uart_dev, buffer[i]);
}
}
static int fw_upload_request_check_crc(uint8_t *buffer, uint8_t request)
{
uint8_t crc;
if (request == V3_HEADER_DATA_REQ) {
crc = fw_upload_crc8(buffer, A6REQ_PAYLOAD_LEN + REQ_HEADER_LEN);
if (crc != buffer[A6REQ_PAYLOAD_LEN + REQ_HEADER_LEN]) {
LOG_ERR("Request %d, CRC check failed", request);
return -EINVAL;
}
} else if (request == V3_START_INDICATION) {
crc = fw_upload_crc8(buffer, AbREQ_PAYLOAD_LEN + REQ_HEADER_LEN);
if (crc != buffer[AbREQ_PAYLOAD_LEN + REQ_HEADER_LEN]) {
LOG_ERR("Request %d, CRC check failed", request);
return -EINVAL;
}
} else {
LOG_ERR("Invalid request %d", request);
}
return 0;
}
static void fw_upload_send_ack(uint8_t ack)
{
if ((ack == V3_REQUEST_ACK) || (ack == V3_CRC_ERROR)) {
/* prepare crc for 0x7A or 0x7C */
fw_upload.buffer[0] = ack;
fw_upload.buffer[1] = fw_upload_crc8(fw_upload.buffer, 1);
fw_upload_write_data(fw_upload.buffer, 2);
LOG_DBG("ACK = %x, CRC = %x", ack, fw_upload.buffer[1]);
} else if (ack == V3_TIMEOUT_ACK) {
/* prepare crc for 0x7B */
fw_upload.buffer[0] = ack;
sys_put_le32(fw_upload.offset, &fw_upload.buffer[1]);
fw_upload.buffer[5] = fw_upload_crc8(fw_upload.buffer, 5);
fw_upload_write_data(fw_upload.buffer, 6);
LOG_DBG("ACK = %x, CRC = %x", ack, fw_upload.buffer[5]);
} else {
LOG_ERR("Invalid ack");
}
}
static int fw_upload_wait_req(bool secondary_speed)
{
int err;
uint32_t len;
uint8_t buffer[10];
buffer[0] = fw_upload.hdr_sig;
if (fw_upload.hdr_sig == V3_HEADER_DATA_REQ) {
/* CMD LINE: 0xA7 <len><offset><error><CRC8> */
len = A6REQ_PAYLOAD_LEN + 1;
} else if (fw_upload.hdr_sig == V3_START_INDICATION) {
/* CMD LINE: 0xAB <CHIP ID><SW loader REV 1 byte><CRC8> */
len = AbREQ_PAYLOAD_LEN + 1;
} else {
return -EINVAL;
}
err = fw_upload_read_data(&buffer[1], len);
if (err < 0) {
LOG_ERR("Fail to read req");
return err;
}
err = fw_upload_request_check_crc(buffer, fw_upload.hdr_sig);
if (err != 0) {
LOG_ERR("Fail to check CRC");
fw_upload_send_ack(V3_CRC_ERROR);
return err;
}
if (fw_upload.hdr_sig == V3_HEADER_DATA_REQ) {
fw_upload.length = sys_get_le16(&buffer[1]);
fw_upload.offset = sys_get_le32(&buffer[3]);
fw_upload.error = sys_get_le16(&buffer[7]);
fw_upload.crc8 = buffer[9];
LOG_DBG("Req: %hhd, %hd, %d, %hd, %hhd", fw_upload.hdr_sig, fw_upload.length,
fw_upload.offset, fw_upload.error, fw_upload.crc8);
} else if (fw_upload.hdr_sig == V3_START_INDICATION) {
uint16_t chip_id;
fw_upload_send_ack(V3_REQUEST_ACK);
chip_id = sys_get_le16(&buffer[1]);
LOG_DBG("Indicate: %hhd, %hd, %hhd, %hhd", fw_upload.hdr_sig, chip_id, buffer[3],
buffer[4]);
if (!secondary_speed) {
return -EINVAL;
}
}
return 0;
}
static int fw_upload_change_timeout(void)
{
int err = 0;
bool first = true;
uint8_t retry = FW_UPLOAD_CHANGE_TIMEOUT_RETRY_COUNT;
LOG_DBG("");
fw_upload_gen_crc32_table();
while (true) {
err = fw_upload_wait_for_hdr_sig();
if (err) {
continue;
}
if (fw_upload.version == VER1) {
return 0;
} else if (fw_upload.version == VER3) {
err = fw_upload_wait_req(true);
if (err) {
continue;
}
if (fw_upload.length == 0) {
continue;
}
if (fw_upload.error == 0) {
if (first || (fw_upload.last_offset == fw_upload.offset)) {
fw_upload_send_ack(V3_REQUEST_ACK);
fw_upload_write_data(cmd7_hdrData,
fw_upload.length > CMD_HDR_LEN
? CMD_HDR_LEN
: fw_upload.length);
fw_upload.last_offset = fw_upload.offset;
first = false;
} else {
fw_upload.cmd7_change_timeout_len = CMD_HDR_LEN;
fw_upload.wait_hdr_sig = false;
return 0;
}
} else {
if (retry > 0) {
retry--;
fw_upload_send_ack(V3_TIMEOUT_ACK);
} else {
LOG_ERR("Fail to change timeout with response err %d",
fw_upload.error);
return -ENOTSUP;
}
}
} else {
LOG_ERR("Unsupported version %d", fw_upload.version);
return -ENOTSUP;
}
}
return -EINVAL;
}
typedef struct {
uint32_t uartBaudRate;
uint32_t uartDivisio;
uint32_t uartClkDivisor;
} uart_baudrate_clkDiv_map_t;
static const uart_baudrate_clkDiv_map_t clk_div_map[] = {
{115200U, 16U, 0x0075F6FDU},
{1000000U, 2U, 0x00800000U},
{3000000U, 1U, 0x00C00000U},
};
static int fw_upload_change_speed_config(struct change_speed_config *config, uint32_t speed)
{
config->clk_div_addr = 0x7f00008fU;
config->uart_clk_div_addr = 0x7f000090U;
config->mcr_addr = 0x7f000091U;
config->reinit_addr = 0x7f000092U;
config->icr_addr = 0x7f000093U;
config->fcr_addr = 0x7f000094U;
config->mcr_val = 0x00000022U;
config->reinit_val = 0x00000001U;
config->icr_val = 0x000000c7U;
config->fcr_val = 0x000000c7U;
for (int i = 0; i < ARRAY_SIZE(clk_div_map); i++) {
if (speed == clk_div_map[i].uartBaudRate) {
config->clk_div_val = clk_div_map[i].uartClkDivisor;
config->uart_clk_div_val = clk_div_map[i].uartDivisio;
return 0;
}
}
return -ENOTSUP;
}
static uint16_t fw_upload_wait_length(uint8_t flag)
{
uint8_t buffer[4];
uint16_t len;
uint16_t len_comp;
int err;
uint8_t ack;
err = fw_upload_read_data(buffer, sizeof(buffer));
if (err < 0) {
return 0;
}
len = sys_get_le16(buffer);
len_comp = sys_get_le16(buffer);
if ((len ^ len_comp) == 0xFFFF) {
LOG_DBG("remote asks for %d bytes", len);
/* Successful. Send back the ack. */
if ((fw_upload.hdr_sig == V1_HEADER_DATA_REQ) ||
(fw_upload.hdr_sig == V1_START_INDICATION)) {
ack = V1_REQUEST_ACK;
fw_upload_write_data(&ack, 1);
if (fw_upload.hdr_sig == V1_START_INDICATION) {
/* Eliminated longjmp(resync, 1); returning restart status */
return (uint16_t)V1_START_INDICATION;
}
}
} else {
LOG_ERR("remote asks len %d bytes", len);
LOG_ERR("remote asks len_comp %d bytes", len_comp);
/* Failure due to mismatch. */
ack = 0xbf;
fw_upload_write_data(&ack, 1);
/* Start all over again. */
if (flag) {
/* Eliminated longjmp(resync, 1); returning restart status */
return (uint16_t)V1_START_INDICATION;
}
len = 0;
}
return len;
}
static uint32_t fw_upload_get_payload_length(uint8_t *cmd)
{
uint32_t len;
len = sys_get_le32(&cmd[8]);
return len;
}
static void fw_upload_get_hdr_start(uint8_t *buffer)
{
int err;
bool done = false;
uint32_t count = 0;
while (!done) {
err = fw_upload_read_data(&fw_upload.hdr_sig, 1);
if (err >= 0) {
if (fw_upload.hdr_sig == V1_HEADER_DATA_REQ) {
buffer[count++] = fw_upload.hdr_sig;
done = true;
LOG_DBG("Found header %x", fw_upload.hdr_sig);
}
} else {
LOG_ERR("Fail to read HDR sig %d", err);
return;
}
}
err = fw_upload_read_data(&buffer[count], 4);
if (err < 0) {
LOG_ERR("Fail to read HDR payload %d", err);
}
}
static int fw_upload_len_valid(uint8_t *buffer, uint16_t *length)
{
uint16_t len;
uint16_t len_comp;
len = sys_get_le16(&buffer[1]);
len_comp = sys_get_le16(&buffer[3]);
if ((len ^ len_comp) == 0xFFFFU) {
*length = len;
return 0;
} else {
return -EINVAL;
}
}
static int fw_upload_get_last_5bytes(uint8_t *buffer)
{
int err;
uint32_t payload_len;
uint16_t len = 0;
memset(fw_upload.last_5bytes_buffer, 0, sizeof(fw_upload.last_5bytes_buffer));
fw_upload_get_hdr_start(fw_upload.last_5bytes_buffer);
err = fw_upload_len_valid(fw_upload.last_5bytes_buffer, &len);
if (err >= 0) {
LOG_DBG("Valid len %d", len);
} else {
LOG_ERR("Invalid HDR");
return err;
}
payload_len = fw_upload_get_payload_length(buffer);
if ((len == CMD_HDR_LEN) || ((uint32_t)len == payload_len)) {
LOG_DBG("Len valid");
fw_upload.is_error_case = false;
return 0;
}
LOG_DBG("Len invalid");
fw_upload.is_error_case = true;
return -EINVAL;
}
static void fw_upload_update_result(uint32_t payload_len, uint16_t *sending_len,
bool *first_chunk_sent)
{
if (fw_upload.is_cmd7_req || fw_upload.is_entry_point_req) {
*sending_len = CMD_HDR_LEN;
*first_chunk_sent = true;
} else {
*sending_len = payload_len;
*first_chunk_sent = false;
if (*sending_len == CMD_HDR_LEN) {
fw_upload.is_hdr_data = true;
}
}
}
static int fw_upload_write_hdr_and_payload(uint16_t len_to_send, uint8_t *buffer, bool new_speed)
{
int err;
uint32_t payload_len;
bool send_done = false;
uint16_t sending_len = CMD_HDR_LEN;
bool first_chunk_sent = false;
LOG_DBG("");
payload_len = fw_upload_get_payload_length(buffer);
while (!send_done) {
if (sending_len == len_to_send) {
if ((sending_len == CMD_HDR_LEN) && (!fw_upload.is_hdr_data)) {
if ((first_chunk_sent == false) ||
(first_chunk_sent && fw_upload.is_error_case)) {
LOG_DBG("Send first chunk: len %d", sending_len);
fw_upload_write_data(buffer, sending_len);
fw_upload_update_result(payload_len, &sending_len,
&first_chunk_sent);
} else {
send_done = true;
break;
}
} else {
LOG_DBG("Send data: len %d", sending_len);
if (sending_len) {
fw_upload_write_data(&buffer[CMD_HDR_LEN], sending_len);
first_chunk_sent = true;
sending_len = CMD_HDR_LEN;
fw_upload.is_hdr_data = false;
if (new_speed) {
return 0;
}
} else {
LOG_DBG("Download Complete");
return 0;
}
}
} else {
if ((len_to_send & 0x01) == 0x01) {
if (len_to_send == (CMD_HDR_LEN + 1)) {
LOG_DBG("Resending first chunk...");
fw_upload_write_data(buffer, len_to_send - 1);
sending_len = payload_len;
first_chunk_sent = false;
} else if (len_to_send == (payload_len + 1)) {
LOG_DBG("Resending second chunk...");
fw_upload_write_data(&buffer[CMD_HDR_LEN], len_to_send - 1);
sending_len = CMD_HDR_LEN;
first_chunk_sent = true;
}
} else if (len_to_send == CMD_HDR_LEN) {
LOG_DBG("Resending send buffer...");
fw_upload_write_data(buffer, len_to_send);
sending_len = payload_len;
first_chunk_sent = false;
} else if (len_to_send == payload_len) {
LOG_DBG("Resending second chunk...");
fw_upload_write_data(&buffer[CMD_HDR_LEN], len_to_send);
sending_len = CMD_HDR_LEN;
first_chunk_sent = true;
}
}
err = fw_upload_get_last_5bytes(buffer);
if (err < 0) {
LOG_ERR("Fail to get response");
return err;
}
if (fw_upload_len_valid(fw_upload.last_5bytes_buffer, &len_to_send) == 0) {
fw_upload_send_ack(V1_REQUEST_ACK);
LOG_DBG("BOOT_HEADER_ACK 0x5a sent");
}
}
return len_to_send;
}
static int fw_upload_uart_reconfig(uint32_t speed, bool flow_control)
{
struct uart_config config;
int err;
config.baudrate = speed;
config.data_bits = UART_CFG_DATA_BITS_8;
config.flow_ctrl = flow_control ? UART_CFG_FLOW_CTRL_RTS_CTS : UART_CFG_FLOW_CTRL_NONE;
config.parity = UART_CFG_PARITY_NONE;
config.stop_bits = UART_CFG_STOP_BITS_1;
uart_irq_rx_disable(uart_dev);
uart_irq_tx_disable(uart_dev);
fw_upload_read_to_clear();
err = uart_configure(uart_dev, &config);
uart_irq_rx_enable(uart_dev);
return err;
}
static int fw_upload_change_speed(uint8_t hdr)
{
int err;
uint32_t hdr_len;
bool load_payload = false;
bool recovery = false;
uint16_t len_to_send;
uint32_t crc;
err = fw_upload_change_speed_config(
(struct change_speed_config *)fw_upload.change_speed_buffer,
uart_dev_data.secondary_speed);
if (err) {
return err;
}
hdr_len = sizeof(fw_upload.change_speed_buffer);
fw_upload_gen_crc32_table();
crc = sys_cpu_to_le32(hdr_len);
memcpy(cmd5_hdrData + 8, &crc, 4);
crc = fw_upload_update_crc32(0, (char *)cmd5_hdrData, 12);
crc = sys_cpu_to_be32(crc);
memcpy(cmd5_hdrData + 12, &crc, CRC32_LEN);
crc = fw_upload_update_crc32(0, (char *)fw_upload.change_speed_buffer,
(int)sizeof(struct change_speed_config));
crc = sys_cpu_to_be32(crc);
memcpy(&fw_upload.change_speed_buffer[sizeof(struct change_speed_config)], &crc, CRC32_LEN);
while (true) {
err = fw_upload_wait_for_hdr_sig();
if (hdr && (err == 0)) {
if (load_payload) {
if (fw_upload.version == VER3) {
fw_upload.change_speed_buffer_len =
CMD_HDR_LEN + fw_upload.length;
}
return 0;
}
} else {
if (recovery) {
return -ETIME;
}
if (load_payload) {
LOG_ERR("HDR cannot be received by using second speed. receovery "
"speed");
err = fw_upload_uart_reconfig(uart_dev_data.primary_speed,
uart_dev_data.primary_flowcontrol);
if (err) {
return err;
}
load_payload = false;
recovery = true;
continue;
}
}
if (fw_upload.version == VER1) {
len_to_send = fw_upload_wait_length(0);
if (len_to_send == V1_START_INDICATION) {
return -EINVAL;
} else if (len_to_send == 0) {
continue;
} else if (len_to_send == CMD_HDR_LEN) {
memcpy(fw_upload.send_buffer, cmd5_hdrData, CMD_HDR_LEN);
memcpy(&fw_upload.send_buffer[CMD_HDR_LEN],
fw_upload.change_speed_buffer, hdr_len);
err = fw_upload_write_hdr_and_payload(len_to_send,
fw_upload.send_buffer, true);
if (err < 0) {
return err;
}
LOG_DBG("Change speed to %d", uart_dev_data.secondary_speed);
err = fw_upload_uart_reconfig(uart_dev_data.secondary_speed,
uart_dev_data.secondary_flowcontrol);
if (err) {
return err;
}
load_payload = true;
} else {
fw_upload_write_data(fw_upload.change_speed_buffer, hdr_len);
LOG_DBG("Change speed to %d", uart_dev_data.secondary_speed);
err = fw_upload_uart_reconfig(uart_dev_data.secondary_speed,
uart_dev_data.secondary_flowcontrol);
if (err) {
return err;
}
load_payload = true;
}
} else if (fw_upload.version == VER3) {
err = fw_upload_wait_req(true);
if (!(!hdr || (err == 0))) {
continue;
}
if (fw_upload.length && (fw_upload.hdr_sig == V3_HEADER_DATA_REQ)) {
if (fw_upload.error != 0) {
fw_upload_send_ack(V3_TIMEOUT_ACK);
continue;
}
fw_upload_send_ack(V3_REQUEST_ACK);
hdr = true;
if (fw_upload.length == CMD_HDR_LEN) {
LOG_DBG("Send CMD5");
fw_upload_write_data(cmd5_hdrData, fw_upload.length);
fw_upload.last_offset = fw_upload.offset;
} else {
LOG_DBG("Send UA RT config");
fw_upload_write_data(fw_upload.change_speed_buffer,
fw_upload.length);
LOG_DBG("Change speed to %d",
uart_dev_data.secondary_speed);
err = fw_upload_uart_reconfig(
uart_dev_data.secondary_speed,
uart_dev_data.secondary_flowcontrol);
if (err) {
return err;
}
load_payload = true;
}
}
}
}
return 0;
}
static int fw_upload_v1_send_data(uint16_t len)
{
uint32_t cmd;
uint32_t data_len;
int ret_len;
memset(fw_upload.send_buffer, 0, sizeof(fw_upload.send_buffer));
fw_upload.is_cmd7_req = false;
fw_upload.is_entry_point_req = false;
if ((fw_upload.fw_length - fw_upload.current_length) < len) {
len = fw_upload.fw_length - fw_upload.current_length;
}
memcpy(fw_upload.send_buffer, fw_upload.fw + fw_upload.current_length, len);
fw_upload.current_length += len;
cmd = sys_get_le32(fw_upload.send_buffer);
if (cmd == CMD7) {
fw_upload.is_cmd7_req = true;
data_len = 0;
} else {
data_len = fw_upload_get_payload_length(fw_upload.send_buffer);
if ((data_len > (sizeof(fw_upload.send_buffer) - len)) ||
((data_len + fw_upload.current_length) > fw_upload.fw_length)) {
LOG_ERR("Invalid FW at %d/%d", fw_upload.current_length,
fw_upload.fw_length);
return -EINVAL;
}
memcpy(&fw_upload.send_buffer[len], fw_upload.fw + fw_upload.current_length,
data_len);
fw_upload.current_length += data_len;
if ((fw_upload.current_length < fw_upload.fw_length) &&
((cmd == CMD6) || (cmd == CMD4))) {
fw_upload.is_entry_point_req = true;
}
}
ret_len = fw_upload_write_hdr_and_payload(len, fw_upload.send_buffer, false);
LOG_DBG("FW upload %d/%d", fw_upload.current_length, fw_upload.fw_length);
return ret_len;
}
static int fw_upload_v3_send_data(void)
{
uint32_t start;
LOG_DBG("Sending offset %d", fw_upload.offset);
if (fw_upload.offset == fw_upload.last_offset) {
LOG_WRN("Resending offset %d ...", fw_upload.offset);
fw_upload_write_data(fw_upload.send_buffer, fw_upload.length);
return fw_upload.length;
}
memset(fw_upload.send_buffer, 0, sizeof(fw_upload.send_buffer));
start = fw_upload.offset - fw_upload.cmd7_change_timeout_len -
fw_upload.change_speed_buffer_len;
if (start >= fw_upload.fw_length) {
LOG_ERR("Invalid fw offset");
return -EINVAL;
}
if ((fw_upload.length + start) > fw_upload.fw_length) {
fw_upload.length = fw_upload.fw_length - start;
}
memcpy(fw_upload.send_buffer, fw_upload.fw + start, fw_upload.length);
fw_upload.current_length = start + fw_upload.length;
fw_upload_write_data(fw_upload.send_buffer, fw_upload.length);
fw_upload.last_offset = fw_upload.offset;
return fw_upload.length;
}
static int fw_uploading(const uint8_t *fw, uint32_t fw_length)
{
int err;
bool secondary_speed = false;
uint16_t len_to_send;
fw_upload.wait_hdr_sig = true;
fw_upload.is_hdr_data = false;
fw_upload.is_error_case = false;
fw_upload.is_cmd7_req = false;
fw_upload.is_entry_point_req = false;
fw_upload.last_offset = 0xFFFFU;
err = fw_upload_change_timeout();
LOG_DBG("Change timeout hdr flag %d (err %d)", fw_upload.wait_hdr_sig, err);
if (err) {
return err;
}
fw_upload_read_to_clear();
if (uart_dev_data.secondary_speed &&
(uart_dev_data.secondary_speed != uart_dev_data.primary_speed)) {
LOG_DBG("Change speed to %d", uart_dev_data.secondary_speed);
err = fw_upload_change_speed(fw_upload.wait_hdr_sig);
if (err != 0) {
LOG_ERR("Fail to change speed");
return err;
}
secondary_speed = true;
}
fw_upload.fw_length = fw_length;
fw_upload.current_length = 0;
fw_upload.fw = fw;
while (true) {
err = fw_upload_wait_for_hdr_sig();
if (secondary_speed && (err != 0)) {
return -ETIME;
}
secondary_speed = false;
if (fw_upload.version == VER1) {
len_to_send = fw_upload_wait_length(true);
if (len_to_send == V1_START_INDICATION) {
continue;
}
while (len_to_send > 0) {
len_to_send = fw_upload_v1_send_data(len_to_send);
}
if (fw_upload.current_length >= fw_upload.fw_length) {
LOG_DBG("FW download done");
return 0;
}
LOG_ERR("FW download failed");
return len_to_send;
} else if (fw_upload.version == VER3) {
if (fw_upload.hdr_sig == V3_START_INDICATION) {
fw_upload_wait_req(false);
continue;
}
err = fw_upload_wait_req(false);
if (err) {
LOG_ERR("Fail to wait req");
return err;
}
if (fw_upload.length) {
if (fw_upload.error == 0) {
fw_upload_send_ack(V3_REQUEST_ACK);
err = fw_upload_v3_send_data();
if (err < 0) {
LOG_ERR("FW download failed");
return err;
}
} else {
LOG_ERR("Error occurs %d", fw_upload.error);
fw_upload_send_ack(V3_TIMEOUT_ACK);
if (fw_upload.error & BT_MIC_FAIL_BIT) {
fw_upload.change_speed_buffer_len = 0;
fw_upload.current_length = 0;
fw_upload.last_offset = 0;
}
}
} else {
if (fw_upload.error == 0) {
fw_upload_send_ack(V3_REQUEST_ACK);
LOG_DBG("FW download done");
return 0;
}
LOG_ERR("Error occurs %d", fw_upload.error);
fw_upload_send_ack(V3_TIMEOUT_ACK);
if (fw_upload.error & BT_MIC_FAIL_BIT) {
fw_upload.change_speed_buffer_len = 0;
fw_upload.current_length = 0;
fw_upload.last_offset = 0;
}
}
} else {
return -ENOTSUP;
}
}
return -EINVAL;
}
static void bt_nxp_ctlr_uart_isr(const struct device *unused, void *user_data)
{
int err = 0;
int count = 0;
ARG_UNUSED(unused);
ARG_UNUSED(user_data);
while (uart_irq_update(uart_dev) && uart_irq_is_pending(uart_dev)) {
err = uart_poll_in(uart_dev, &fw_upload.rx.buffer[fw_upload.rx.head]);
if (err >= 0) {
fw_upload.rx.head++;
fw_upload.rx.head = fw_upload.rx.head % sizeof(fw_upload.rx.buffer);
count++;
}
}
while (count > 0) {
k_sem_give(&fw_upload.rx.sem);
count--;
}
}
static int bt_nxp_ctlr_init(void)
{
int err;
uint32_t speed;
bool flowcontrol_of_hci;
if (!device_is_ready(uart_dev)) {
return -ENODEV;
}
speed = DT_PROP(DT_INST_GPARENT(0), current_speed);
speed = DT_PROP_OR(DT_DRV_INST(0), hci_operation_speed, speed);
uart_dev_data.primary_speed = DT_PROP_OR(DT_DRV_INST(0), fw_download_primary_speed, speed);
uart_dev_data.secondary_speed =
DT_PROP_OR(DT_DRV_INST(0), fw_download_secondary_speed, speed);
flowcontrol_of_hci = (bool)DT_PROP_OR(DT_DRV_INST(0), hw_flow_control, false);
uart_dev_data.primary_flowcontrol =
(bool)DT_PROP_OR(DT_DRV_INST(0), fw_download_primary_flowcontrol, false);
uart_dev_data.secondary_flowcontrol =
(bool)DT_PROP_OR(DT_DRV_INST(0), fw_download_secondary_flowcontrol, false);
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios) || \
DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios)
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios)
/* Check BT REG_ON gpio instance */
if (!gpio_is_ready_dt(&sdio_reset)) {
LOG_ERR("Error: failed to configure sdio_reset %s pin %d", sdio_reset.port->name,
sdio_reset.pin);
return -EIO;
}
/* Configure sdio_reset as output */
err = gpio_pin_configure_dt(&sdio_reset, GPIO_OUTPUT);
if (err) {
LOG_ERR("Error %d: failed to configure sdio_reset %s pin %d", err,
sdio_reset.port->name, sdio_reset.pin);
return err;
}
err = gpio_pin_set_dt(&sdio_reset, 0);
if (err) {
return err;
}
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios) */
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios)
/* Check BT REG_ON gpio instance */
if (!gpio_is_ready_dt(&w_disable)) {
LOG_ERR("Error: failed to configure w_disable %s pin %d", w_disable.port->name,
w_disable.pin);
return -EIO;
}
/* Configure w_disable as output */
err = gpio_pin_configure_dt(&w_disable, GPIO_OUTPUT);
if (err) {
LOG_ERR("Error %d: failed to configure w_disable %s pin %d", err,
w_disable.port->name, w_disable.pin);
return err;
}
err = gpio_pin_set_dt(&w_disable, 0);
if (err) {
return err;
}
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios) */
/* wait for reset done */
k_sleep(K_MSEC(100));
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios)
err = gpio_pin_set_dt(&sdio_reset, 1);
if (err) {
return err;
}
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), sdio_reset_gpios) */
#if DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios)
err = gpio_pin_set_dt(&w_disable, 1);
if (err) {
return err;
}
#endif /* DT_NODE_HAS_PROP(DT_DRV_INST(0), w_disable_gpios) */
#endif
uart_irq_rx_disable(uart_dev);
uart_irq_tx_disable(uart_dev);
fw_upload.rx.head = 0;
fw_upload.rx.tail = 0;
k_sem_init(&fw_upload.rx.sem, 0, sizeof(fw_upload.rx.buffer));
uart_irq_callback_set(uart_dev, bt_nxp_ctlr_uart_isr);
made_table = false;
err = fw_upload_uart_reconfig(uart_dev_data.primary_speed,
uart_dev_data.primary_flowcontrol);
if (err) {
LOG_ERR("Fail to config uart");
return err;
}
uart_irq_rx_enable(uart_dev);
err = fw_uploading(bt_fw_bin, bt_fw_bin_len);
if (err) {
LOG_ERR("Fail to upload firmware");
return err;
}
(void)fw_upload_uart_reconfig(speed, flowcontrol_of_hci);
uart_irq_rx_disable(uart_dev);
uart_irq_tx_disable(uart_dev);
k_sleep(K_MSEC(CONFIG_BT_H4_NXP_CTLR_WAIT_TIME_AFTER_UPLOAD));
return 0;
}
int bt_hci_transport_setup(const struct device *dev)
{
if (dev != uart_dev) {
return -EINVAL;
}
return bt_nxp_ctlr_init();
}
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_nxp_setup.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,899 |
```unknown
# Miscellaneous drivers not exposing Zephyr Device Driver API
menu "Miscellaneous Drivers"
source "drivers/misc/ft8xx/Kconfig"
source "drivers/misc/grove_lcd_rgb/Kconfig"
source "drivers/misc/pio_rpi_pico/Kconfig"
source "drivers/misc/nxp_s32_emios/Kconfig"
source "drivers/misc/timeaware_gpio/Kconfig"
source "drivers/misc/devmux/Kconfig"
source "drivers/misc/nordic_vpr_launcher/Kconfig"
source "drivers/misc/mcux_flexio/Kconfig"
endmenu
``` | /content/code_sandbox/drivers/misc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```c
/*
*
*/
#include <zephyr/bluetooth/hci.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/bluetooth.h>
#include <esp_bt.h>
#define LOG_LEVEL CONFIG_BT_HCI_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(bt_hci_driver_esp32);
#define DT_DRV_COMPAT espressif_esp32_bt_hci
#define HCI_BT_ESP32_TIMEOUT K_MSEC(2000)
struct bt_esp32_data {
bt_hci_recv_t recv;
};
static K_SEM_DEFINE(hci_send_sem, 1, 1);
static bool is_hci_event_discardable(const uint8_t *evt_data)
{
uint8_t evt_type = evt_data[0];
switch (evt_type) {
#if defined(CONFIG_BT_CLASSIC)
case BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI:
case BT_HCI_EVT_EXTENDED_INQUIRY_RESULT:
return true;
#endif
case BT_HCI_EVT_LE_META_EVENT: {
uint8_t subevt_type = evt_data[sizeof(struct bt_hci_evt_hdr)];
switch (subevt_type) {
case BT_HCI_EVT_LE_ADVERTISING_REPORT:
return true;
default:
return false;
}
}
default:
return false;
}
}
static struct net_buf *bt_esp_evt_recv(uint8_t *data, size_t remaining)
{
bool discardable = false;
struct bt_hci_evt_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for event header");
return NULL;
}
discardable = is_hci_event_discardable(data);
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
if (remaining != hdr.len) {
LOG_ERR("Event payload length is not correct");
return NULL;
}
LOG_DBG("len %u", hdr.len);
buf = bt_buf_get_evt(hdr.evt, discardable, K_NO_WAIT);
if (!buf) {
if (discardable) {
LOG_DBG("Discardable buffer pool full, ignoring event");
} else {
LOG_ERR("No available event buffers!");
}
return buf;
}
net_buf_add_mem(buf, &hdr, sizeof(hdr));
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
net_buf_add_mem(buf, data, remaining);
return buf;
}
static struct net_buf *bt_esp_acl_recv(uint8_t *data, size_t remaining)
{
struct bt_hci_acl_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for ACL header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
net_buf_add_mem(buf, &hdr, sizeof(hdr));
} else {
LOG_ERR("No available ACL buffers!");
return NULL;
}
if (remaining != sys_le16_to_cpu(hdr.len)) {
LOG_ERR("ACL payload length is not correct");
net_buf_unref(buf);
return NULL;
}
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("len %u", remaining);
net_buf_add_mem(buf, data, remaining);
return buf;
}
static struct net_buf *bt_esp_iso_recv(uint8_t *data, size_t remaining)
{
struct bt_hci_iso_hdr hdr;
struct net_buf *buf;
size_t buf_tailroom;
if (remaining < sizeof(hdr)) {
LOG_ERR("Not enough data for ISO header");
return NULL;
}
buf = bt_buf_get_rx(BT_BUF_ISO_IN, K_NO_WAIT);
if (buf) {
memcpy((void *)&hdr, data, sizeof(hdr));
data += sizeof(hdr);
remaining -= sizeof(hdr);
net_buf_add_mem(buf, &hdr, sizeof(hdr));
} else {
LOG_ERR("No available ISO buffers!");
return NULL;
}
if (remaining != bt_iso_hdr_len(sys_le16_to_cpu(hdr.len))) {
LOG_ERR("ISO payload length is not correct");
net_buf_unref(buf);
return NULL;
}
buf_tailroom = net_buf_tailroom(buf);
if (buf_tailroom < remaining) {
LOG_ERR("Not enough space in buffer %zu/%zu", remaining, buf_tailroom);
net_buf_unref(buf);
return NULL;
}
LOG_DBG("len %zu", remaining);
net_buf_add_mem(buf, data, remaining);
return buf;
}
static int hci_esp_host_rcv_pkt(uint8_t *data, uint16_t len)
{
const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
struct bt_esp32_data *hci = dev->data;
uint8_t pkt_indicator;
struct net_buf *buf = NULL;
size_t remaining = len;
LOG_HEXDUMP_DBG(data, len, "host packet data:");
pkt_indicator = *data++;
remaining -= sizeof(pkt_indicator);
switch (pkt_indicator) {
case BT_HCI_H4_EVT:
buf = bt_esp_evt_recv(data, remaining);
break;
case BT_HCI_H4_ACL:
buf = bt_esp_acl_recv(data, remaining);
break;
case BT_HCI_H4_SCO:
buf = bt_esp_iso_recv(data, remaining);
break;
default:
LOG_ERR("Unknown HCI type %u", pkt_indicator);
return -1;
}
if (buf) {
LOG_DBG("Calling bt_recv(%p)", buf);
hci->recv(dev, buf);
}
return 0;
}
static void hci_esp_controller_rcv_pkt_ready(void)
{
k_sem_give(&hci_send_sem);
}
static esp_vhci_host_callback_t vhci_host_cb = {
hci_esp_controller_rcv_pkt_ready,
hci_esp_host_rcv_pkt
};
static int bt_esp32_send(const struct device *dev, struct net_buf *buf)
{
int err = 0;
uint8_t pkt_indicator;
LOG_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);
switch (bt_buf_get_type(buf)) {
case BT_BUF_ACL_OUT:
pkt_indicator = BT_HCI_H4_ACL;
break;
case BT_BUF_CMD:
pkt_indicator = BT_HCI_H4_CMD;
break;
case BT_BUF_ISO_OUT:
pkt_indicator = BT_HCI_H4_ISO;
break;
default:
LOG_ERR("Unknown type %u", bt_buf_get_type(buf));
goto done;
}
net_buf_push_u8(buf, pkt_indicator);
LOG_HEXDUMP_DBG(buf->data, buf->len, "Final HCI buffer:");
if (!esp_vhci_host_check_send_available()) {
LOG_WRN("Controller not ready to receive packets");
}
if (k_sem_take(&hci_send_sem, HCI_BT_ESP32_TIMEOUT) == 0) {
esp_vhci_host_send_packet(buf->data, buf->len);
} else {
LOG_ERR("Send packet timeout error");
err = -ETIMEDOUT;
}
done:
net_buf_unref(buf);
k_sem_give(&hci_send_sem);
return err;
}
static int bt_esp32_ble_init(void)
{
int ret;
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
#if defined(CONFIG_BT_CLASSIC) && defined(CONFIG_SOC_SERIES_ESP32)
esp_bt_mode_t mode = ESP_BT_MODE_BTDM;
#else
esp_bt_mode_t mode = ESP_BT_MODE_BLE;
#endif
ret = esp_bt_controller_init(&bt_cfg);
if (ret) {
LOG_ERR("Bluetooth controller init failed %d", ret);
return ret;
}
ret = esp_bt_controller_enable(mode);
if (ret) {
LOG_ERR("Bluetooth controller enable failed: %d", ret);
return ret;
}
esp_vhci_host_register_callback(&vhci_host_cb);
return 0;
}
static int bt_esp32_ble_deinit(void)
{
int ret;
ret = esp_bt_controller_disable();
if (ret) {
LOG_ERR("Bluetooth controller disable failed %d", ret);
return ret;
}
ret = esp_bt_controller_deinit();
if (ret) {
LOG_ERR("Bluetooth controller deinit failed %d", ret);
return ret;
}
return 0;
}
static int bt_esp32_open(const struct device *dev, bt_hci_recv_t recv)
{
struct bt_esp32_data *hci = dev->data;
int err;
err = bt_esp32_ble_init();
if (err) {
return err;
}
hci->recv = recv;
LOG_DBG("ESP32 BT started");
return 0;
}
static int bt_esp32_close(const struct device *dev)
{
struct bt_esp32_data *hci = dev->data;
int err;
err = bt_esp32_ble_deinit();
if (err) {
return err;
}
hci->recv = NULL;
LOG_DBG("ESP32 BT stopped");
return 0;
}
static const struct bt_hci_driver_api drv = {
.open = bt_esp32_open,
.send = bt_esp32_send,
.close = bt_esp32_close,
};
#define BT_ESP32_DEVICE_INIT(inst) \
static struct bt_esp32_data bt_esp32_data_##inst = { \
}; \
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &bt_esp32_data_##inst, NULL, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &drv)
/* Only one instance supported */
BT_ESP32_DEVICE_INIT(0)
``` | /content/code_sandbox/drivers/bluetooth/hci/hci_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,167 |
```unknown
config MCUX_FLEXIO
bool
depends on DT_HAS_NXP_FLEXIO_ENABLED
depends on CLOCK_CONTROL
help
Enable the FlexIO controller driver.
This driver is not user-selectable,
and should be enabled by other FlexIO drivers so
that they can use it to share the resources of the FlexIO device.
if MCUX_FLEXIO
config MCUX_FLEXIO_INIT_PRIORITY
int "FlexIO controller driver init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
MCUX FlexIO device driver initialization priority.
module = MCUX_FLEXIO
module-str = mcux_flexio
source "subsys/logging/Kconfig.template.log_config"
endif # MCUX_FLEXIO
``` | /content/code_sandbox/drivers/misc/mcux_flexio/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_flexio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/misc/nxp_flexio/nxp_flexio.h>
#include <fsl_flexio.h>
LOG_MODULE_REGISTER(mcux_flexio, CONFIG_MCUX_FLEXIO_LOG_LEVEL);
struct mcux_flexio_config {
FLEXIO_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
void (*irq_config_func)(const struct device *dev);
void (*irq_enable_func)(void);
void (*irq_disable_func)(void);
};
typedef const struct nxp_flexio_child *nxp_flexio_map_child_t;
struct mcux_flexio_data {
struct k_mutex lock;
uint32_t shifter_indexes_used;
uint32_t timer_indexes_used;
nxp_flexio_map_child_t *map_shifter_child;
nxp_flexio_map_child_t *map_timer_child;
uint32_t map_shifter_child_count;
uint32_t map_timer_child_count;
};
static int mcux_flexio_child_take_shifter_idx(const struct device *dev)
{
struct mcux_flexio_data *data = dev->data;
for (uint32_t i = 0; i < data->map_shifter_child_count; i++) {
if ((data->shifter_indexes_used & BIT(i)) == 0) {
WRITE_BIT(data->shifter_indexes_used, i, 1);
return i;
}
}
return -ENOBUFS;
}
static int mcux_flexio_child_take_timer_idx(const struct device *dev)
{
struct mcux_flexio_data *data = dev->data;
for (uint32_t i = 0; i < data->map_timer_child_count; i++) {
if ((data->timer_indexes_used & BIT(i)) == 0) {
WRITE_BIT(data->timer_indexes_used, i, 1);
return i;
}
}
return -ENOBUFS;
}
static void mcux_flexio_isr(const struct device *dev)
{
const struct mcux_flexio_config *config = dev->config;
struct mcux_flexio_data *data = dev->data;
FLEXIO_Type *base = config->base;
nxp_flexio_map_child_t *map_shifter_child = data->map_shifter_child;
uint32_t map_shifter_child_count = data->map_shifter_child_count;
uint32_t shifter_status_flag = FLEXIO_GetShifterStatusFlags(base);
uint32_t shifter_error_flag = FLEXIO_GetShifterErrorFlags(base);
if (shifter_status_flag || shifter_error_flag) {
for (uint32_t idx = 0; idx < map_shifter_child_count; idx++) {
if (((shifter_status_flag | shifter_error_flag) & BIT(idx)) != 0) {
const struct nxp_flexio_child *child = map_shifter_child[idx];
if (child != NULL) {
nxp_flexio_child_isr_t isr = child->isr;
if (isr != NULL) {
isr(child->user_data);
}
}
}
}
}
nxp_flexio_map_child_t *map_timer_child = data->map_timer_child;
uint32_t map_timer_child_count = data->map_timer_child_count;
uint32_t timer_status_flag = FLEXIO_GetTimerStatusFlags(base);
if (timer_status_flag) {
for (uint32_t idx = 0; idx < map_timer_child_count; idx++) {
if ((timer_status_flag & BIT(idx)) != 0) {
const struct nxp_flexio_child *child = map_timer_child[idx];
if (child != NULL) {
nxp_flexio_child_isr_t isr = child->isr;
if (isr != NULL) {
isr(child->user_data);
}
}
}
}
}
SDK_ISR_EXIT_BARRIER;
}
static int mcux_flexio_init(const struct device *dev)
{
const struct mcux_flexio_config *config = dev->config;
struct mcux_flexio_data *data = dev->data;
flexio_config_t flexio_config;
k_mutex_init(&data->lock);
FLEXIO_GetDefaultConfig(&flexio_config);
FLEXIO_Init(config->base, &flexio_config);
config->irq_config_func(dev);
return 0;
}
void nxp_flexio_irq_enable(const struct device *dev)
{
const struct mcux_flexio_config *config = dev->config;
config->irq_enable_func();
}
void nxp_flexio_irq_disable(const struct device *dev)
{
const struct mcux_flexio_config *config = dev->config;
config->irq_disable_func();
}
void nxp_flexio_lock(const struct device *dev)
{
struct mcux_flexio_data *data = dev->data;
k_mutex_lock(&data->lock, K_FOREVER);
}
void nxp_flexio_unlock(const struct device *dev)
{
struct mcux_flexio_data *data = dev->data;
k_mutex_unlock(&data->lock);
}
int nxp_flexio_get_rate(const struct device *dev, uint32_t *rate)
{
const struct mcux_flexio_config *config = dev->config;
return clock_control_get_rate(config->clock_dev, config->clock_subsys, rate);
}
int nxp_flexio_child_attach(const struct device *dev,
const struct nxp_flexio_child *child)
{
struct mcux_flexio_data *data = dev->data;
const struct nxp_flexio_child_res *child_res = &child->res;
for (uint32_t i = 0; i < child_res->shifter_count; i++) {
int shifter_idx = mcux_flexio_child_take_shifter_idx(dev);
if (shifter_idx < 0) {
LOG_ERR("Failed to take shifter index: %d", shifter_idx);
return shifter_idx;
}
child_res->shifter_index[i] = shifter_idx;
data->map_shifter_child[shifter_idx] = child;
LOG_DBG("child %p: shifter_idx[%d] is %d", child, i, shifter_idx);
}
for (uint32_t i = 0; i < child_res->timer_count; i++) {
int timer_idx = mcux_flexio_child_take_timer_idx(dev);
if (timer_idx < 0) {
LOG_ERR("Failed to take timer index: %d", timer_idx);
return timer_idx;
}
child_res->timer_index[i] = timer_idx;
data->map_timer_child[timer_idx] = child;
LOG_DBG("child %p: timer_idx[%d] is %d", child, i, timer_idx);
}
return 0;
}
#define MCUX_FLEXIO_SHIFTER_COUNT_MAX(n) \
ARRAY_SIZE(((FLEXIO_Type *)DT_INST_REG_ADDR(n))->SHIFTCTL)
#define MCUX_FLEXIO_TIMER_COUNT_MAX(n) \
ARRAY_SIZE(((FLEXIO_Type *)DT_INST_REG_ADDR(n))->TIMCTL)
#define MCUX_FLEXIO_INIT(n) \
static void mcux_flexio_irq_config_func_##n(const struct device *dev); \
static void mcux_flexio_irq_enable_func_##n(void); \
static void mcux_flexio_irq_disable_func_##n(void); \
\
static nxp_flexio_map_child_t \
nxp_flexio_map_shifter_child_##n[MCUX_FLEXIO_SHIFTER_COUNT_MAX(n)] = {0}; \
static nxp_flexio_map_child_t \
nxp_flexio_map_timer_child_##n[MCUX_FLEXIO_TIMER_COUNT_MAX(n)] = {0}; \
\
static struct mcux_flexio_data mcux_flexio_data_##n = { \
.map_shifter_child = nxp_flexio_map_shifter_child_##n, \
.map_shifter_child_count = ARRAY_SIZE(nxp_flexio_map_shifter_child_##n), \
.map_timer_child = nxp_flexio_map_timer_child_##n, \
.map_timer_child_count = ARRAY_SIZE(nxp_flexio_map_timer_child_##n), \
}; \
\
static const struct mcux_flexio_config mcux_flexio_config_##n = { \
.base = (FLEXIO_Type *)DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
.irq_config_func = mcux_flexio_irq_config_func_##n, \
.irq_enable_func = mcux_flexio_irq_enable_func_##n, \
.irq_disable_func = mcux_flexio_irq_disable_func_##n, \
}; \
\
DEVICE_DT_INST_DEFINE(n, &mcux_flexio_init, \
NULL, \
&mcux_flexio_data_##n, \
&mcux_flexio_config_##n, \
POST_KERNEL, \
CONFIG_MCUX_FLEXIO_INIT_PRIORITY, \
NULL); \
\
static void mcux_flexio_irq_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
mcux_flexio_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
} \
\
static void mcux_flexio_irq_enable_func_##n(void) \
{ \
irq_enable(DT_INST_IRQN(n)); \
} \
\
static void mcux_flexio_irq_disable_func_##n(void) \
{ \
irq_disable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(MCUX_FLEXIO_INIT)
``` | /content/code_sandbox/drivers/misc/mcux_flexio/mcux_flexio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,255 |
```unknown
config DEVMUX
bool "Device Multiplexer (devmux) [EXPERIMENTAL]"
depends on DT_HAS_ZEPHYR_DEVMUX_ENABLED
depends on DEVICE_MUTABLE
select EXPERIMENTAL
help
Devmux is a pseudo-device that operates as a device switch. It allows
software to select the data, config, and api from a number of linked
devices.
if DEVMUX
config DEVMUX_INIT_PRIORITY
int "Devmux init priority"
default 51
help
Init priority for the devmux driver. It must be
greater than the priority of the initially selected muxed device.
endif
``` | /content/code_sandbox/drivers/misc/devmux/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 141 |
```objective-c
/*
*
*/
/**
* @file
* @brief FT8XX serial driver API
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_DRV_H_
#define ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_DRV_H_
#include <stdint.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif
int ft8xx_drv_init(void);
int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length);
int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length);
int ft8xx_drv_command(uint8_t command);
extern void ft8xx_drv_irq_triggered(const struct device *dev,
struct gpio_callback *cb, uint32_t pins);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_DRV_H_ */
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx_drv.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 201 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_devmux
#include <zephyr/device.h>
#include <zephyr/drivers/misc/devmux/devmux.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
struct devmux_config {
const struct device **devs;
const size_t n_devs;
};
struct devmux_data {
struct k_spinlock lock;
size_t selected;
};
/* The number of devmux devices */
#define N DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)
static const struct device *devmux_devices[N];
static const struct devmux_config *devmux_configs[N];
static struct devmux_data *devmux_datas[N];
static bool devmux_device_is_valid(const struct device *dev)
{
for (size_t i = 0; i < N; ++i) {
if (dev == devmux_devices[i]) {
return true;
}
}
return false;
}
static size_t devmux_inst_get(const struct device *dev)
{
for (size_t i = 0; i < N; i++) {
if (dev == devmux_devices[i]) {
return i;
}
}
return SIZE_MAX;
}
const struct devmux_config *devmux_config_get(const struct device *dev)
{
for (size_t i = 0; i < N; i++) {
if (dev == devmux_devices[i]) {
return devmux_configs[i];
}
}
return NULL;
}
struct devmux_data *devmux_data_get(const struct device *dev)
{
for (size_t i = 0; i < N; i++) {
if (dev == devmux_devices[i]) {
return devmux_datas[i];
}
}
return NULL;
}
ssize_t z_impl_devmux_select_get(const struct device *dev)
{
ssize_t index;
struct devmux_data *const data = devmux_data_get(dev);
if (!devmux_device_is_valid(dev)) {
return -EINVAL;
}
K_SPINLOCK(&data->lock)
{
index = data->selected;
}
return index;
}
#ifdef CONFIG_USERSPACE
ssize_t z_vrfy_devmux_select_get(const struct device *dev)
{
return z_impl_devmux_select_get(dev);
}
#include <zephyr/syscalls/devmux_select_get_mrsh.c>
#endif
int z_impl_devmux_select_set(struct device *dev, size_t index)
{
struct devmux_data *const data = devmux_data_get(dev);
const struct devmux_config *config = devmux_config_get(dev);
if (!devmux_device_is_valid(dev) || index >= config->n_devs) {
return -EINVAL;
}
if (!device_is_ready(config->devs[index])) {
return -ENODEV;
}
K_SPINLOCK(&data->lock)
{
*dev = *config->devs[index];
data->selected = index;
}
return 0;
}
#ifdef CONFIG_USERSPACE
int z_vrfy_devmux_select_set(struct device *dev, size_t index)
{
return z_impl_devmux_select_set(dev, index);
}
#include <zephyr/syscalls/devmux_select_set_mrsh.c>
#endif
static int devmux_init(struct device *const dev)
{
size_t inst = devmux_inst_get(dev);
struct devmux_data *const data = dev->data;
const struct devmux_config *config = dev->config;
size_t sel = data->selected;
devmux_configs[inst] = config;
devmux_datas[inst] = data;
if (!device_is_ready(config->devs[sel])) {
return -ENODEV;
}
*dev = *config->devs[sel];
return 0;
}
#define DEVMUX_PHANDLE_TO_DEVICE(node_id, prop, idx) \
DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx))
#define DEVMUX_PHANDLE_DEVICES(_n) \
DT_INST_FOREACH_PROP_ELEM_SEP(_n, devices, DEVMUX_PHANDLE_TO_DEVICE, (,))
#define DEVMUX_SELECTED(_n) DT_INST_PROP(_n, selected)
#define DEVMUX_DEFINE(_n) \
BUILD_ASSERT(DT_INST_PROP_OR(_n, zephyr_mutable, 0), \
"devmux nodes must contain the 'zephyr,mutable' property"); \
BUILD_ASSERT(DT_INST_PROP_LEN(_n, devices) > 0, "devices array must have non-zero size"); \
BUILD_ASSERT(DEVMUX_SELECTED(_n) >= 0, "selected must be > 0"); \
BUILD_ASSERT(DEVMUX_SELECTED(_n) < DT_INST_PROP_LEN(_n, devices), \
"selected must be within bounds of devices phandle array"); \
static const struct device *demux_devs_##_n[] = {DEVMUX_PHANDLE_DEVICES(_n)}; \
static const struct devmux_config devmux_config_##_n = { \
.devs = demux_devs_##_n, \
.n_devs = DT_INST_PROP_LEN(_n, devices), \
}; \
static struct devmux_data devmux_data_##_n = { \
.selected = DEVMUX_SELECTED(_n), \
}; \
\
DEVICE_DT_INST_DEFINE(_n, devmux_init, NULL, &devmux_data_##_n, &devmux_config_##_n, \
PRE_KERNEL_1, CONFIG_DEVMUX_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(DEVMUX_DEFINE)
#define DEVMUX_DEVICE_GET(_n) DEVICE_DT_INST_GET(_n),
static const struct device *devmux_devices[] = {DT_INST_FOREACH_STATUS_OKAY(DEVMUX_DEVICE_GET)};
``` | /content/code_sandbox/drivers/misc/devmux/devmux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,231 |
```c
/*
*
*/
#include "ft8xx_drv.h"
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#define LOG_MODULE_NAME ft8xx_drv
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define DT_DRV_COMPAT ftdi_ft800
#define NODE_ID DT_INST(0, DT_DRV_COMPAT)
/* SPI device */
static const struct spi_dt_spec spi = SPI_DT_SPEC_INST_GET(0,
SPI_WORD_SET(8) | SPI_OP_MODE_MASTER,
0);
/* GPIO int line */
static const struct gpio_dt_spec irq_gpio = GPIO_DT_SPEC_INST_GET(0, irq_gpios);
static struct gpio_callback irq_cb_data;
__weak void ft8xx_drv_irq_triggered(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
/* Intentionally empty */
}
/* Protocol details */
#define ADDR_SIZE 3
#define DUMMY_READ_SIZE 1
#define COMMAND_SIZE 3
#define MAX_READ_LEN (UINT16_MAX - ADDR_SIZE - DUMMY_READ_SIZE)
#define MAX_WRITE_LEN (UINT16_MAX - ADDR_SIZE)
#define READ_OP 0x00
#define WRITE_OP 0x80
#define COMMAND_OP 0x40
static void insert_addr(uint32_t addr, uint8_t *buff)
{
buff[0] = (addr >> 16) & 0x3f;
buff[1] = (addr >> 8) & 0xff;
buff[2] = (addr) & 0xff;
}
int ft8xx_drv_init(void)
{
int ret;
if (!spi_is_ready_dt(&spi)) {
LOG_ERR("SPI bus %s not ready", spi.bus->name);
return -ENODEV;
}
/* TODO: Verify if such entry in DTS is present.
* If not, use polling mode.
*/
if (!gpio_is_ready_dt(&irq_gpio)) {
LOG_ERR("GPIO device %s is not ready", irq_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
if (ret != 0) {
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
return ret;
}
gpio_init_callback(&irq_cb_data, ft8xx_drv_irq_triggered, BIT(irq_gpio.pin));
gpio_add_callback(irq_gpio.port, &irq_cb_data);
return 0;
}
int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length)
{
int ret;
uint8_t addr_buf[ADDR_SIZE];
insert_addr(address, addr_buf);
addr_buf[0] |= WRITE_OP;
struct spi_buf tx[] = {
{
.buf = addr_buf,
.len = sizeof(addr_buf),
},
{
/* Discard const, it is implicit for TX buffer */
.buf = (uint8_t *)data,
.len = length,
},
};
struct spi_buf_set tx_bufs = {
.buffers = tx,
.count = 2,
};
ret = spi_write_dt(&spi, &tx_bufs);
if (ret < 0) {
LOG_ERR("SPI write error: %d", ret);
}
return ret;
}
int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length)
{
int ret;
uint8_t dummy_read_buf[ADDR_SIZE + DUMMY_READ_SIZE];
uint8_t addr_buf[ADDR_SIZE];
insert_addr(address, addr_buf);
addr_buf[0] |= READ_OP;
struct spi_buf tx = {
.buf = addr_buf,
.len = sizeof(addr_buf),
};
struct spi_buf_set tx_bufs = {
.buffers = &tx,
.count = 1,
};
struct spi_buf rx[] = {
{
.buf = dummy_read_buf,
.len = sizeof(dummy_read_buf),
},
{
.buf = data,
.len = length,
},
};
struct spi_buf_set rx_bufs = {
.buffers = rx,
.count = 2,
};
ret = spi_transceive_dt(&spi, &tx_bufs, &rx_bufs);
if (ret < 0) {
LOG_ERR("SPI transceive error: %d", ret);
}
return ret;
}
int ft8xx_drv_command(uint8_t command)
{
int ret;
/* Most commands include COMMAND_OP bit. ACTIVE power mode command is
* an exception with value 0x00.
*/
uint8_t cmd_buf[COMMAND_SIZE] = {command, 0, 0};
struct spi_buf tx = {
.buf = cmd_buf,
.len = sizeof(cmd_buf),
};
struct spi_buf_set tx_bufs = {
.buffers = &tx,
.count = 1,
};
ret = spi_write_dt(&spi, &tx_bufs);
if (ret < 0) {
LOG_ERR("SPI command error: %d", ret);
}
return ret;
}
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx_drv.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,109 |
```c
/*
*
*/
#define DT_DRV_COMPAT ftdi_ft800
#include <zephyr/drivers/misc/ft8xx/ft8xx.h>
#include <stddef.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_copro.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_common.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_dl.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_memory.h>
#include "ft8xx_drv.h"
#include "ft8xx_host_commands.h"
LOG_MODULE_REGISTER(ft8xx, CONFIG_DISPLAY_LOG_LEVEL);
#define FT8XX_DLSWAP_FRAME 0x02
#define FT8XX_EXPECTED_ID 0x7C
struct ft8xx_config {
uint16_t vsize;
uint16_t voffset;
uint16_t vcycle;
uint16_t vsync0;
uint16_t vsync1;
uint16_t hsize;
uint16_t hoffset;
uint16_t hcycle;
uint16_t hsync0;
uint16_t hsync1;
uint8_t pclk;
uint8_t pclk_pol :1;
uint8_t cspread :1;
uint8_t swizzle :4;
};
struct ft8xx_data {
const struct ft8xx_config *config;
ft8xx_int_callback irq_callback;
};
const static struct ft8xx_config ft8xx_config = {
.pclk = DT_INST_PROP(0, pclk),
.pclk_pol = DT_INST_PROP(0, pclk_pol),
.cspread = DT_INST_PROP(0, cspread),
.swizzle = DT_INST_PROP(0, swizzle),
.vsize = DT_INST_PROP(0, vsize),
.voffset = DT_INST_PROP(0, voffset),
.vcycle = DT_INST_PROP(0, vcycle),
.vsync0 = DT_INST_PROP(0, vsync0),
.vsync1 = DT_INST_PROP(0, vsync1),
.hsize = DT_INST_PROP(0, hsize),
.hoffset = DT_INST_PROP(0, hoffset),
.hcycle = DT_INST_PROP(0, hcycle),
.hsync0 = DT_INST_PROP(0, hsync0),
.hsync1 = DT_INST_PROP(0, hsync1),
};
static struct ft8xx_data ft8xx_data = {
.config = &ft8xx_config,
.irq_callback = NULL,
};
static void host_command(uint8_t cmd)
{
int err;
err = ft8xx_drv_command(cmd);
__ASSERT(err == 0, "Writing FT8xx command failed");
}
static void wait(void)
{
k_sleep(K_MSEC(20));
}
static bool verify_chip(void)
{
uint32_t id = ft8xx_rd32(FT800_REG_ID);
return (id & 0xff) == FT8XX_EXPECTED_ID;
}
static int ft8xx_init(const struct device *dev)
{
int ret;
const struct ft8xx_config *config = dev->config;
ret = ft8xx_drv_init();
if (ret < 0) {
LOG_ERR("FT8xx driver initialization failed with %d", ret);
return ret;
}
/* Reset display controller */
host_command(CORERST);
host_command(ACTIVE);
wait();
host_command(CLKEXT);
host_command(CLK48M);
wait();
host_command(CORERST);
host_command(ACTIVE);
wait();
host_command(CLKEXT);
host_command(CLK48M);
wait();
if (!verify_chip()) {
LOG_ERR("FT8xx chip not recognized");
return -ENODEV;
}
/* Disable LCD */
ft8xx_wr8(FT800_REG_GPIO, 0);
ft8xx_wr8(FT800_REG_PCLK, 0);
/* Configure LCD */
ft8xx_wr16(FT800_REG_HSIZE, config->hsize);
ft8xx_wr16(FT800_REG_HCYCLE, config->hcycle);
ft8xx_wr16(FT800_REG_HOFFSET, config->hoffset);
ft8xx_wr16(FT800_REG_HSYNC0, config->hsync0);
ft8xx_wr16(FT800_REG_HSYNC1, config->hsync1);
ft8xx_wr16(FT800_REG_VSIZE, config->vsize);
ft8xx_wr16(FT800_REG_VCYCLE, config->vcycle);
ft8xx_wr16(FT800_REG_VOFFSET, config->voffset);
ft8xx_wr16(FT800_REG_VSYNC0, config->vsync0);
ft8xx_wr16(FT800_REG_VSYNC1, config->vsync1);
ft8xx_wr8(FT800_REG_SWIZZLE, config->swizzle);
ft8xx_wr8(FT800_REG_PCLK_POL, config->pclk_pol);
ft8xx_wr8(FT800_REG_CSPREAD, config->cspread);
/* Display initial screen */
/* Set the initial color */
ft8xx_wr32(FT800_RAM_DL + 0, FT8XX_CLEAR_COLOR_RGB(0, 0x80, 0));
/* Clear to the initial color */
ft8xx_wr32(FT800_RAM_DL + 4, FT8XX_CLEAR(1, 1, 1));
/* End the display list */
ft8xx_wr32(FT800_RAM_DL + 8, FT8XX_DISPLAY());
ft8xx_wr8(FT800_REG_DLSWAP, FT8XX_DLSWAP_FRAME);
/* Enable LCD */
/* Enable display bit */
ft8xx_wr8(FT800_REG_GPIO_DIR, 0x80);
ft8xx_wr8(FT800_REG_GPIO, 0x80);
/* Enable backlight */
ft8xx_wr16(FT800_REG_PWM_HZ, 0x00FA);
ft8xx_wr8(FT800_REG_PWM_DUTY, 0x10);
/* Enable LCD signals */
ft8xx_wr8(FT800_REG_PCLK, config->pclk);
return 0;
}
DEVICE_DT_INST_DEFINE(0, ft8xx_init, NULL, &ft8xx_data, &ft8xx_config,
POST_KERNEL, CONFIG_FT800_INIT_PRIORITY, NULL);
int ft8xx_get_touch_tag(void)
{
/* Read FT800_REG_INT_FLAGS to clear IRQ */
(void)ft8xx_rd8(FT800_REG_INT_FLAGS);
return (int)ft8xx_rd8(FT800_REG_TOUCH_TAG);
}
void ft8xx_drv_irq_triggered(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
if (ft8xx_data.irq_callback != NULL) {
ft8xx_data.irq_callback();
}
}
void ft8xx_register_int(ft8xx_int_callback callback)
{
if (ft8xx_data.irq_callback != NULL) {
return;
}
ft8xx_data.irq_callback = callback;
ft8xx_wr8(FT800_REG_INT_MASK, 0x04);
ft8xx_wr8(FT800_REG_INT_EN, 0x01);
}
void ft8xx_calibrate(struct ft8xx_touch_transform *data)
{
uint32_t result = 0;
do {
ft8xx_copro_cmd_dlstart();
ft8xx_copro_cmd(FT8XX_CLEAR_COLOR_RGB(0x00, 0x00, 0x00));
ft8xx_copro_cmd(FT8XX_CLEAR(1, 1, 1));
ft8xx_copro_cmd_calibrate(&result);
} while (result == 0);
data->a = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_A);
data->b = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_B);
data->c = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_C);
data->d = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_D);
data->e = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_E);
data->f = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_F);
}
void ft8xx_touch_transform_set(const struct ft8xx_touch_transform *data)
{
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_A, data->a);
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_B, data->b);
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_C, data->c);
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_D, data->d);
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_E, data->e);
ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_F, data->f);
}
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,892 |
```unknown
# FT8xx Embedded Video Engine configuration options
config FT800
bool "FT800 Embedded Video Engine driver"
default y
depends on DT_HAS_FTDI_FT800_ENABLED
select SPI
help
Enable driver for FT800 controller.
config FT800_INIT_PRIORITY
int "FT800 init priority"
default 90
depends on FT800
help
FT800 driver initialization priority in POST_KERNEL.
``` | /content/code_sandbox/drivers/misc/ft8xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```c
/*
*
*/
#include <zephyr/drivers/misc/ft8xx/ft8xx_copro.h>
#include <stdint.h>
#include <string.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_common.h>
#include <zephyr/drivers/misc/ft8xx/ft8xx_memory.h>
#include "ft8xx_drv.h"
#define FT800_RAM_CMD_SIZE 4096UL
enum {
CMD_DLSTART = 0xffffff00,
CMD_SWAP = 0xffffff01,
CMD_TEXT = 0xffffff0c,
CMD_NUMBER = 0xffffff2e,
CMD_CALIBRATE = 0xffffff15,
} ft8xx_cmd;
static uint16_t reg_cmd_read;
static uint16_t reg_cmd_write;
static uint16_t ram_cmd_fullness(void)
{
return (reg_cmd_write - reg_cmd_read) % 4096UL;
}
static uint16_t ram_cmd_freespace(void)
{
return (FT800_RAM_CMD_SIZE - 4UL) - ram_cmd_fullness();
}
static void refresh_reg_cmd_read(void)
{
reg_cmd_read = ft8xx_rd32(FT800_REG_CMD_READ);
}
static void flush_reg_cmd_write(void)
{
ft8xx_wr32(FT800_REG_CMD_WRITE, reg_cmd_write);
}
static void increase_reg_cmd_write(uint16_t value)
{
reg_cmd_write = (reg_cmd_write + value) % FT800_RAM_CMD_SIZE;
}
void ft8xx_copro_cmd(uint32_t cmd)
{
while (ram_cmd_freespace() < sizeof(cmd)) {
refresh_reg_cmd_read();
}
ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, cmd);
increase_reg_cmd_write(sizeof(cmd));
flush_reg_cmd_write();
}
void ft8xx_copro_cmd_dlstart(void)
{
ft8xx_copro_cmd(CMD_DLSTART);
}
void ft8xx_copro_cmd_swap(void)
{
ft8xx_copro_cmd(CMD_SWAP);
}
void ft8xx_copro_cmd_text(int16_t x,
int16_t y,
int16_t font,
uint16_t options,
const char *s)
{
const uint16_t str_bytes = strlen(s) + 1;
const uint16_t padding_bytes = (4 - (str_bytes % 4)) % 4;
const uint16_t cmd_size = sizeof(CMD_TEXT) +
sizeof(x) +
sizeof(y) +
sizeof(font) +
sizeof(options) +
str_bytes +
padding_bytes;
while (ram_cmd_freespace() < cmd_size) {
refresh_reg_cmd_read();
}
ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_TEXT);
increase_reg_cmd_write(sizeof(CMD_TEXT));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, x);
increase_reg_cmd_write(sizeof(x));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, y);
increase_reg_cmd_write(sizeof(y));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, font);
increase_reg_cmd_write(sizeof(font));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, options);
increase_reg_cmd_write(sizeof(options));
(void)ft8xx_drv_write(FT800_RAM_CMD + reg_cmd_write, s, str_bytes);
increase_reg_cmd_write(str_bytes + padding_bytes);
flush_reg_cmd_write();
}
void ft8xx_copro_cmd_number(int16_t x,
int16_t y,
int16_t font,
uint16_t options,
int32_t n)
{
const uint16_t cmd_size = sizeof(CMD_NUMBER) +
sizeof(x) +
sizeof(y) +
sizeof(font) +
sizeof(options) +
sizeof(n);
while (ram_cmd_freespace() < cmd_size) {
refresh_reg_cmd_read();
}
ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_NUMBER);
increase_reg_cmd_write(sizeof(CMD_NUMBER));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, x);
increase_reg_cmd_write(sizeof(x));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, y);
increase_reg_cmd_write(sizeof(y));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, font);
increase_reg_cmd_write(sizeof(font));
ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, options);
increase_reg_cmd_write(sizeof(options));
ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, n);
increase_reg_cmd_write(sizeof(n));
flush_reg_cmd_write();
}
void ft8xx_copro_cmd_calibrate(uint32_t *result)
{
const uint16_t cmd_size = sizeof(CMD_CALIBRATE) + sizeof(uint32_t);
uint32_t result_address;
while (ram_cmd_freespace() < cmd_size) {
refresh_reg_cmd_read();
}
ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_CALIBRATE);
increase_reg_cmd_write(sizeof(CMD_CALIBRATE));
result_address = FT800_RAM_CMD + reg_cmd_write;
ft8xx_wr32(result_address, 1UL);
increase_reg_cmd_write(sizeof(uint32_t));
flush_reg_cmd_write();
/* Wait until calibration is finished. */
while (ram_cmd_fullness() > 0) {
refresh_reg_cmd_read();
}
*result = ft8xx_rd32(result_address);
}
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx_copro.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```objective-c
/*
*
*/
/**
* @file
* @brief FT8XX host commands enumeration
*/
#ifndef ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_HOST_COMMANDS_H_
#define ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_HOST_COMMANDS_H_
#ifdef __cplusplus
extern "C" {
#endif
enum ft800_command_t {
ACTIVE = 0,
STANDBY = 0x41,
SLEEP = 0x42,
PWRDOWN = 0x50,
CLKEXT = 0x44,
CLK48M = 0x62,
CLK36M = 0x61,
CORERST = 0x68
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_DISPLAY_FT8XX_FT8XX_HOST_COMMANDS_H_ */
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx_host_commands.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```c
/*
*
*/
#include <zephyr/drivers/misc/ft8xx/ft8xx_common.h>
#include <zephyr/sys/byteorder.h>
#include "ft8xx_drv.h"
void ft8xx_wr8(uint32_t address, uint8_t data)
{
int err;
err = ft8xx_drv_write(address, &data, sizeof(data));
__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
}
void ft8xx_wr16(uint32_t address, uint16_t data)
{
int err;
uint8_t buffer[2];
*(uint16_t *)buffer = sys_cpu_to_le16(data);
err = ft8xx_drv_write(address, buffer, sizeof(buffer));
__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
}
void ft8xx_wr32(uint32_t address, uint32_t data)
{
int err;
uint8_t buffer[4];
*(uint32_t *)buffer = sys_cpu_to_le32(data);
err = ft8xx_drv_write(address, buffer, sizeof(buffer));
__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
}
uint8_t ft8xx_rd8(uint32_t address)
{
int err;
uint8_t data = 0;
err = ft8xx_drv_read(address, &data, sizeof(data));
__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
return data;
}
uint16_t ft8xx_rd16(uint32_t address)
{
int err;
uint8_t buffer[2] = {0};
err = ft8xx_drv_read(address, buffer, sizeof(buffer));
__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
return sys_le16_to_cpu(*(const uint16_t *)buffer);
}
uint32_t ft8xx_rd32(uint32_t address)
{
int err;
uint8_t buffer[4] = {0};
err = ft8xx_drv_read(address, buffer, sizeof(buffer));
__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
return sys_le32_to_cpu(*(const uint32_t *)buffer);
}
``` | /content/code_sandbox/drivers/misc/ft8xx/ft8xx_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 487 |
```unknown
config GROVE_LCD_RGB
bool "Seeed Grove LCD RGB Backlight"
default y
depends on DT_HAS_SEEED_GROVE_LCD_RGB_ENABLED
help
Setting this value will enable driver support for the Grove-LCD RGB
Backlight.
if GROVE_LCD_RGB
module = GROVE_LCD_RGB
module-str = grove_lcd_rgb
source "subsys/logging/Kconfig.template.log_config"
endif
``` | /content/code_sandbox/drivers/misc/grove_lcd_rgb/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```c
/*
* affiliates <open-source-office@arm.com></text>
*/
#include "zephyr/sys_clock.h"
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#include <ethosu_driver.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ethos_u, CONFIG_ARM_ETHOS_U_LOG_LEVEL);
#define DT_DRV_COMPAT arm_ethos_u
/*******************************************************************************
* Re-implementation/Overrides __((weak)) symbol functions from ethosu_driver.c
* To handle mutex and semaphores
*******************************************************************************/
void *ethosu_mutex_create(void)
{
struct k_mutex *mutex;
mutex = k_malloc(sizeof(*mutex));
if (mutex == NULL) {
LOG_ERR("Failed allocate mutex");
return NULL;
}
k_mutex_init(mutex);
return (void *)mutex;
}
int ethosu_mutex_lock(void *mutex)
{
int status;
status = k_mutex_lock((struct k_mutex *)mutex, K_FOREVER);
if (status != 0) {
LOG_ERR("Failed to lock mutex with error - %d", status);
return -1;
}
return 0;
}
int ethosu_mutex_unlock(void *mutex)
{
k_mutex_unlock((struct k_mutex *)mutex);
return 0;
}
void *ethosu_semaphore_create(void)
{
struct k_sem *sem;
sem = k_malloc(sizeof(*sem));
if (sem == NULL) {
LOG_ERR("Failed to allocate semaphore");
return NULL;
}
k_sem_init(sem, 0, 100);
return (void *)sem;
}
int ethosu_semaphore_take(void *sem, uint64_t timeout)
{
int status;
status = k_sem_take((struct k_sem *)sem, (timeout == ETHOSU_SEMAPHORE_WAIT_FOREVER)
? K_FOREVER
: Z_TIMEOUT_TICKS(timeout));
if (status != 0) {
/* The Ethos-U driver expects the semaphore implementation to never fail except for
* when a timeout occurs, and the current ethosu_semaphore_take implementation makes
* no distinction, in terms of return codes, between a timeout and other semaphore
* take failures. Also, note that a timeout is virtually indistinguishable from
* other failures if the driver logging is disabled. Handling errors other than a
* timeout is therefore not covered here and is deferred to the application
* developer if necessary.
*/
if (status != -EAGAIN) {
LOG_ERR("Failed to take semaphore with error - %d", status);
}
return -1;
}
return 0;
}
int ethosu_semaphore_give(void *sem)
{
k_sem_give((struct k_sem *)sem);
return 0;
}
struct ethosu_dts_info {
void *base_addr;
bool secure_enable;
bool privilege_enable;
void (*irq_config)(void);
};
struct ethosu_data {
struct ethosu_driver drv;
};
void ethosu_zephyr_irq_handler(const struct device *dev)
{
struct ethosu_data *data = dev->data;
struct ethosu_driver *drv = &data->drv;
ethosu_irq_handler(drv);
}
static int ethosu_zephyr_init(const struct device *dev)
{
const struct ethosu_dts_info *config = dev->config;
struct ethosu_data *data = dev->data;
struct ethosu_driver *drv = &data->drv;
struct ethosu_driver_version version;
LOG_DBG("Ethos-U DTS info. base_address=0x%p, secure_enable=%u, privilege_enable=%u",
config->base_addr, config->secure_enable, config->privilege_enable);
ethosu_get_driver_version(&version);
LOG_DBG("Version. major=%u, minor=%u, patch=%u", version.major, version.minor,
version.patch);
if (ethosu_init(drv, config->base_addr, NULL, 0, config->secure_enable,
config->privilege_enable)) {
LOG_ERR("Failed to initialize NPU with ethosu_init().");
return -EINVAL;
}
config->irq_config();
return 0;
}
#define ETHOSU_DEVICE_INIT(n) \
static struct ethosu_data ethosu_data_##n; \
\
static void ethosu_zephyr_irq_config_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), ethosu_zephyr_irq_handler, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
} \
\
static const struct ethosu_dts_info ethosu_dts_info_##n = { \
.base_addr = (void *)DT_INST_REG_ADDR(n), \
.secure_enable = DT_INST_PROP(n, secure_enable), \
.privilege_enable = DT_INST_PROP(n, privilege_enable), \
.irq_config = ðosu_zephyr_irq_config_##n, \
}; \
\
DEVICE_DT_INST_DEFINE(n, ethosu_zephyr_init, NULL, ðosu_data_##n, ðosu_dts_info_##n, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
DT_INST_FOREACH_STATUS_OKAY(ETHOSU_DEVICE_INIT);
``` | /content/code_sandbox/drivers/misc/ethos_u/ethos_u.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,151 |
```c
/*
*
*/
#define DT_DRV_COMPAT seeed_grove_lcd_rgb
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/misc/grove_lcd/grove_lcd.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(grove_lcd, CONFIG_GROVE_LCD_RGB_LOG_LEVEL);
#define GROVE_RGB_BACKLIGHT_ADDR (0x62)
struct glcd_data {
uint8_t input_set;
uint8_t display_switch;
uint8_t function;
};
struct glcd_config {
struct i2c_dt_spec bus;
};
/********************************************
* LCD FUNCTIONS
*******************************************/
/* GLCD_CMD_SCREEN_CLEAR has no options */
/* GLCD_CMD_CURSOR_RETURN has no options */
/* Defines for the GLCD_CMD_CURSOR_SHIFT */
#define GLCD_CS_DISPLAY_SHIFT (1 << 3)
#define GLCD_CS_RIGHT_SHIFT (1 << 2)
/* LCD Display Commands */
#define GLCD_CMD_SCREEN_CLEAR (1 << 0)
#define GLCD_CMD_CURSOR_RETURN (1 << 1)
#define GLCD_CMD_INPUT_SET (1 << 2)
#define GLCD_CMD_DISPLAY_SWITCH (1 << 3)
#define GLCD_CMD_CURSOR_SHIFT (1 << 4)
#define GLCD_CMD_FUNCTION_SET (1 << 5)
#define GLCD_CMD_SET_CGRAM_ADDR (1 << 6)
#define GLCD_CMD_SET_DDRAM_ADDR (1 << 7)
/********************************************
* RGB FUNCTIONS
*******************************************/
#define REGISTER_R 0x04
#define REGISTER_G 0x03
#define REGISTER_B 0x02
static uint8_t color_define[][3] = {
{ 255, 255, 255 }, /* white */
{ 255, 0, 0 }, /* red */
{ 0, 255, 0 }, /* green */
{ 0, 0, 255 }, /* blue */
};
/********************************************
* PRIVATE FUNCTIONS
*******************************************/
static void rgb_reg_set(const struct device *i2c, uint8_t addr, uint8_t dta)
{
uint8_t data[2] = { addr, dta };
i2c_write(i2c, data, sizeof(data), GROVE_RGB_BACKLIGHT_ADDR);
}
/********************************************
* PUBLIC FUNCTIONS
*******************************************/
void glcd_print(const struct device *dev, char *data, uint32_t size)
{
const struct glcd_config *config = dev->config;
uint8_t buf[] = { GLCD_CMD_SET_CGRAM_ADDR, 0 };
int i;
for (i = 0; i < size; i++) {
buf[1] = data[i];
i2c_write_dt(&config->bus, buf, sizeof(buf));
}
}
void glcd_cursor_pos_set(const struct device *dev, uint8_t col, uint8_t row)
{
const struct glcd_config *config = dev->config;
unsigned char data[2];
if (row == 0U) {
col |= 0x80;
} else {
col |= 0xC0;
}
data[0] = GLCD_CMD_SET_DDRAM_ADDR;
data[1] = col;
i2c_write_dt(&config->bus, data, 2);
}
void glcd_clear(const struct device *dev)
{
const struct glcd_config *config = dev->config;
uint8_t clear[] = { 0, GLCD_CMD_SCREEN_CLEAR };
i2c_write_dt(&config->bus, clear, sizeof(clear));
LOG_DBG("clear, delay 20 ms");
k_sleep(K_MSEC(20));
}
void glcd_display_state_set(const struct device *dev, uint8_t opt)
{
const struct glcd_config *config = dev->config;
struct glcd_data *data = dev->data;
uint8_t buf[] = { 0, 0 };
data->display_switch = opt;
buf[1] = (opt | GLCD_CMD_DISPLAY_SWITCH);
i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("set display_state options, delay 5 ms");
k_sleep(K_MSEC(5));
}
uint8_t glcd_display_state_get(const struct device *dev)
{
struct glcd_data *data = dev->data;
return data->display_switch;
}
void glcd_input_state_set(const struct device *dev, uint8_t opt)
{
const struct glcd_config *config = dev->config;
struct glcd_data *data = dev->data;
uint8_t buf[] = { 0, 0 };
data->input_set = opt;
buf[1] = (opt | GLCD_CMD_INPUT_SET);
i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("set the input_set, no delay");
}
uint8_t glcd_input_state_get(const struct device *dev)
{
struct glcd_data *data = dev->data;
return data->input_set;
}
void glcd_color_select(const struct device *dev, uint8_t color)
{
if (color > 3) {
LOG_WRN("selected color is too high a value");
return;
}
glcd_color_set(dev, color_define[color][0], color_define[color][1],
color_define[color][2]);
}
void glcd_color_set(const struct device *dev, uint8_t r, uint8_t g,
uint8_t b)
{
const struct glcd_config *config = dev->config;
rgb_reg_set(config->bus.bus, REGISTER_R, r);
rgb_reg_set(config->bus.bus, REGISTER_G, g);
rgb_reg_set(config->bus.bus, REGISTER_B, b);
}
void glcd_function_set(const struct device *dev, uint8_t opt)
{
const struct glcd_config *config = dev->config;
struct glcd_data *data = dev->data;
uint8_t buf[] = { 0, 0 };
data->function = opt;
buf[1] = (opt | GLCD_CMD_FUNCTION_SET);
i2c_write_dt(&config->bus, buf, sizeof(buf));
LOG_DBG("set function options, delay 5 ms");
k_sleep(K_MSEC(5));
}
uint8_t glcd_function_get(const struct device *dev)
{
struct glcd_data *data = dev->data;
return data->function;
}
static int glcd_initialize(const struct device *dev)
{
const struct glcd_config *config = dev->config;
uint8_t cmd;
LOG_DBG("initialize called");
if (!device_is_ready(config->bus.bus)) {
return -ENODEV;
}
/*
* Initialization sequence from the data sheet:
* 1 - Power on
* - Wait for more than 30 ms AFTER VDD rises to 4.5v
* 2 - Send FUNCTION set
* - Wait for 39 us
* 3 - Send DISPLAY Control
* - wait for 39 us
* 4 - send DISPLAY Clear
* - wait for 1.5 ms
* 5 - send ENTRY Mode
* 6 - Initialization is done
*/
/*
* We're here! Let's just make sure we've had enough time for the
* VDD to power on, so pause a little here, 30 ms min, so we go 50
*/
LOG_DBG("delay 50 ms while the VDD powers on");
k_sleep(K_MSEC(50));
/* Configure everything for the display function first */
cmd = GLCD_CMD_FUNCTION_SET | GLCD_FS_ROWS_2;
glcd_function_set(dev, cmd);
/* turn the display on - by default no cursor and no blinking */
cmd = GLCD_DS_DISPLAY_ON | GLCD_DS_CURSOR_OFF | GLCD_DS_BLINK_OFF;
glcd_display_state_set(dev, cmd);
/* Clear the screen */
glcd_clear(dev);
/* Initialize to the default text direction for romance languages */
cmd = GLCD_IS_ENTRY_LEFT | GLCD_IS_SHIFT_DECREMENT;
glcd_input_state_set(dev, cmd);
/* Now power on the background RGB control */
LOG_INF("configuring the RGB background");
rgb_reg_set(config->bus.bus, 0x00, 0x00);
rgb_reg_set(config->bus.bus, 0x01, 0x05);
rgb_reg_set(config->bus.bus, 0x08, 0xAA);
/* Now set the background color to white */
LOG_DBG("background set to white");
rgb_reg_set(config->bus.bus, REGISTER_R, color_define[GROVE_RGB_WHITE][0]);
rgb_reg_set(config->bus.bus, REGISTER_G, color_define[GROVE_RGB_WHITE][1]);
rgb_reg_set(config->bus.bus, REGISTER_B, color_define[GROVE_RGB_WHITE][2]);
return 0;
}
static const struct glcd_config grove_lcd_config = {
.bus = I2C_DT_SPEC_INST_GET(0),
};
static struct glcd_data grove_lcd_data;
DEVICE_DT_INST_DEFINE(0, glcd_initialize, NULL, &grove_lcd_data,
&grove_lcd_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
``` | /content/code_sandbox/drivers/misc/grove_lcd_rgb/grove_lcd_rgb.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,977 |
```unknown
# Timeaware gpio config options
menuconfig TIMEAWARE_GPIO
bool "Timeaware GPIO driver"
help
Enable config options for timeaware GPIO driver.
if TIMEAWARE_GPIO
module = TIMEAWARE_GPIO
module-str = timeaware_gpio
source "subsys/logging/Kconfig.template.log_config"
config TIMEAWARE_GPIO_INIT_PRIORITY
int "Timeaware GPIO initialization priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
System initialization priority for timeaware GPIO drivers.
source "drivers/misc/timeaware_gpio/Kconfig.timeaware_gpio_intel"
endif # TIMEAWARE_GPIO
``` | /content/code_sandbox/drivers/misc/timeaware_gpio/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```unknown
# INTEL PMC TGPIO configuration options
#
config TIMEAWARE_GPIO_INTEL
bool "Intel Time aware GPIO driver"
default y
depends on DT_HAS_INTEL_TIMEAWARE_GPIO_ENABLED
help
Intel time aware GPIO driver found on Intel PCH subsystem
``` | /content/code_sandbox/drivers/misc/timeaware_gpio/Kconfig.timeaware_gpio_intel | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```c
/*
*
*/
#include <zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h>
#include <zephyr/syscall_handler.h>
static inline int z_vrfy_tgpio_port_get_time(const struct device *port, uint64_t *current_time)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, get_time));
K_OOPS(Z_SYSCALL_MEMORY_WRITE(current_time, sizeof(uint64_t)));
return z_impl_tgpio_port_get_time((const struct device *)port, (uint64_t *)current_time);
}
#include <zephyr/syscalls/tgpio_port_get_time_mrsh.c>
static inline int z_vrfy_tgpio_port_get_cycles_per_second(const struct device *port,
uint32_t *cycles)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, cyc_per_sec));
K_OOPS(Z_SYSCALL_MEMORY_WRITE(cycles, sizeof(uint32_t)));
return z_impl_tgpio_port_get_cycles_per_second((const struct device *)port,
(uint32_t *)cycles);
}
#include <zephyr/syscalls/tgpio_port_get_cycles_per_second_mrsh.c>
static inline int z_vrfy_tgpio_pin_periodic_output(const struct device *port, uint32_t pin,
uint64_t start_time, uint64_t repeat_interval,
bool periodic_enable)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, set_perout));
return z_impl_tgpio_pin_periodic_output((const struct device *)port, pin, start_time,
repeat_interval, periodic_enable);
}
#include <zephyr/syscalls/tgpio_pin_periodic_output_mrsh.c>
static inline int z_vrfy_tgpio_pin_disable(const struct device *port, uint32_t pin)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, pin_disable));
return z_impl_tgpio_pin_disable((const struct device *)port, pin);
}
#include <zephyr/syscalls/tgpio_pin_disable_mrsh.c>
static inline int z_vrfy_tgpio_pin_config_ext_timestamp(const struct device *port, uint32_t pin,
uint32_t event_polarity)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, config_ext_ts));
return z_impl_tgpio_pin_config_ext_timestamp((const struct device *)port, pin,
event_polarity);
}
#include <zephyr/syscalls/tgpio_pin_config_ext_timestamp_mrsh.c>
static inline int z_vrfy_tgpio_pin_read_ts_ec(const struct device *port, uint32_t pin,
uint64_t *timestamp, uint64_t *event_count)
{
K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, read_ts_ec));
return z_impl_tgpio_pin_read_ts_ec((const struct device *)port, pin, (uint64_t *)timestamp,
(uint64_t *)event_count);
}
#include <zephyr/syscalls/tgpio_pin_read_ts_ec_mrsh.c>
``` | /content/code_sandbox/drivers/misc/timeaware_gpio/timeaware_gpio_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 597 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#define DT_DRV_COMPAT raspberrypi_pico_pio
struct pio_rpi_pico_config {
PIO pio;
const struct device *clk_dev;
clock_control_subsys_t clk_id;
const struct reset_dt_spec reset;
};
int pio_rpi_pico_allocate_sm(const struct device *dev, size_t *sm)
{
const struct pio_rpi_pico_config *config = dev->config;
int retval;
retval = pio_claim_unused_sm(config->pio, false);
if (retval < 0) {
return -EBUSY;
}
*sm = (size_t)retval;
return 0;
}
PIO pio_rpi_pico_get_pio(const struct device *dev)
{
const struct pio_rpi_pico_config *config = dev->config;
return config->pio;
}
static int pio_rpi_pico_init(const struct device *dev)
{
const struct pio_rpi_pico_config *config = dev->config;
int ret;
ret = clock_control_on(config->clk_dev, config->clk_id);
if (ret < 0) {
return ret;
}
ret = reset_line_toggle_dt(&config->reset);
if (ret < 0) {
return ret;
}
return 0;
}
#define RPI_PICO_PIO_INIT(idx) \
static const struct pio_rpi_pico_config pio_rpi_pico_config_##idx = { \
.pio = (PIO)DT_INST_REG_ADDR(idx), \
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
.clk_id = (clock_control_subsys_t)DT_INST_PHA_BY_IDX(0, clocks, 0, clk_id), \
.reset = RESET_DT_SPEC_INST_GET(idx), \
}; \
\
DEVICE_DT_INST_DEFINE(idx, &pio_rpi_pico_init, NULL, NULL, &pio_rpi_pico_config_##idx, \
PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
DT_INST_FOREACH_STATUS_OKAY(RPI_PICO_PIO_INIT)
``` | /content/code_sandbox/drivers/misc/pio_rpi_pico/pio_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 515 |
```c
/*
*
*/
#define DT_DRV_COMPAT intel_timeaware_gpio
#include <errno.h>
#include <stdio.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h>
#include <zephyr/devicetree.h>
#include <zephyr/internal/syscall_handler.h>
/* TGPIO Register offsets */
#define ART_L 0x00 /* ART lower 32 bit reg */
#define ART_H 0x04 /* ART higher 32 bit reg */
#define CTL 0x10 /* TGPIO control reg */
#define COMPV31_0 0x20 /* Comparator lower 32 bit reg */
#define COMPV63_32 0x24 /* Comparator higher 32 bit reg */
#define PIV31_0 0x28 /* Periodic Interval lower 32 bit reg */
#define PIV63_32 0x2c /* Periodic Interval higher 32 bit reg */
#define TCV31_0 0x30 /* Time Capture lower 32 bit reg */
#define TCV63_32 0x34 /* Time Capture higher 32 bit reg */
#define ECCV31_0 0x38 /* Event Counter Capture lower 32 bit reg */
#define ECCV63_32 0x3c /* Event Counter Capture higher 32 bit reg */
#define EC31_0 0x40 /* Event Counter lower 32 bit reg */
#define EC63_32 0x44 /* Event Counter higher 32 bit reg */
#define REGSET_SIZE 0x100 /* Difference between 0 and 1 */
#define UINT32_MASK 0xFFFFFFFF /* 32 bit Mask */
#define UINT32_SIZE 32
/* Control Register */
#define CTL_EN BIT(0) /* Control enable */
#define CTL_DIR BIT(1) /* Control disable */
#define CTL_EP GENMASK(3, 2) /* Recerved polarity */
#define CTL_EP_RISING_EDGE (0 << 2) /* Rising edge */
#define CTL_EP_FALLING_EDGE (1 << 2) /* Falling edge */
#define CTL_EP_TOGGLE_EDGE (2 << 2) /* Toggle edge */
#define CTL_PM BIT(4) /* Periodic mode */
/* Macro to get configuration data, required by DEVICE_MMIO_NAMED_* in init */
#define DEV_CFG(_dev) \
((const struct tgpio_config *)(_dev)->config)
/* Macro to get runtime data, required by DEVICE_MMIO_NAMED_* in init */
#define DEV_DATA(_dev) ((struct tgpio_runtime *)(_dev)->data)
/* Macro to individual pin regbase */
#define pin_regs(addr, pin) (addr + (pin * REGSET_SIZE))
struct tgpio_config {
DEVICE_MMIO_NAMED_ROM(reg_base);
uint32_t max_pins;
uint32_t art_clock_freq;
};
struct tgpio_runtime {
DEVICE_MMIO_NAMED_RAM(reg_base);
};
static mm_reg_t regs(const struct device *dev)
{
return DEVICE_MMIO_NAMED_GET(dev, reg_base);
}
static int tgpio_intel_get_time(const struct device *dev,
uint64_t *current_time)
{
*current_time = sys_read32(regs(dev) + ART_L);
*current_time += ((uint64_t)sys_read32(regs(dev) + ART_H) << UINT32_SIZE);
return 0;
}
static int tgpio_intel_cyc_per_sec(const struct device *dev,
uint32_t *cycles)
{
*cycles = DEV_CFG(dev)->art_clock_freq;
return 0;
}
static int tgpio_intel_pin_disable(const struct device *dev,
uint32_t pin)
{
mm_reg_t addr = regs(dev);
if (pin >= DEV_CFG(dev)->max_pins) {
return -EINVAL;
}
addr = pin_regs(addr, pin);
sys_write32(sys_read32(addr + CTL) & ~CTL_EN, addr + CTL);
return 0;
}
static int tgpio_intel_periodic_output(const struct device *dev,
uint32_t pin,
uint64_t start_time,
uint64_t repeat_interval,
bool periodic_enable)
{
mm_reg_t addr = regs(dev);
uint32_t val;
if (pin >= DEV_CFG(dev)->max_pins) {
return -EINVAL;
}
addr = pin_regs(addr, pin);
tgpio_intel_pin_disable(dev, pin);
/* Configure PIV */
val = (repeat_interval >> UINT32_SIZE) & UINT32_MASK;
sys_write32(val, addr + PIV63_32);
val = repeat_interval & UINT32_MASK;
sys_write32(val, addr + PIV31_0);
/* Configure COMPV */
val = (start_time >> UINT32_SIZE) & UINT32_MASK;
sys_write32(val, addr + COMPV63_32);
val = start_time & UINT32_MASK;
sys_write32(val, addr + COMPV31_0);
val = 0;
/* Configure Periodic Mode */
if (periodic_enable) {
val |= CTL_PM;
}
/* Enable the pin */
val |= CTL_EN;
sys_write32(val, addr + CTL);
return 0;
}
static int tgpio_intel_config_external_timestamp(const struct device *dev,
uint32_t pin,
uint32_t event_polarity)
{
mm_reg_t addr = regs(dev);
uint32_t val;
if (pin >= DEV_CFG(dev)->max_pins) {
return -EINVAL;
}
addr = pin_regs(addr, pin);
tgpio_intel_pin_disable(dev, pin);
/* Configure interrupt polarity */
if (event_polarity == 0) {
val = CTL_EP_RISING_EDGE;
} else if (event_polarity == 1) {
val = CTL_EP_FALLING_EDGE;
} else {
val = CTL_EP_TOGGLE_EDGE;
}
/* Configure direction = input */
val |= CTL_DIR;
sys_write32(val, addr + CTL);
/* Enable the pin */
sys_write32(sys_read32(addr + CTL) | CTL_EN, addr + CTL);
return 0;
}
static int tgpio_intel_read_ts_ec(const struct device *dev,
uint32_t pin,
uint64_t *timestamp,
uint64_t *event_count)
{
if (pin >= DEV_CFG(dev)->max_pins) {
return -EINVAL;
}
*timestamp = sys_read32(regs(dev) + TCV31_0);
*timestamp += ((uint64_t)sys_read32(regs(dev) + TCV63_32) << UINT32_SIZE);
*event_count = sys_read32(regs(dev) + ECCV31_0);
*event_count += ((uint64_t)sys_read32(regs(dev) + ECCV63_32) << UINT32_SIZE);
return 0;
}
static const struct tgpio_driver_api api_funcs = {
.pin_disable = tgpio_intel_pin_disable,
.get_time = tgpio_intel_get_time,
.set_perout = tgpio_intel_periodic_output,
.config_ext_ts = tgpio_intel_config_external_timestamp,
.read_ts_ec = tgpio_intel_read_ts_ec,
.cyc_per_sec = tgpio_intel_cyc_per_sec,
};
static int tgpio_init(const struct device *dev)
{
const struct tgpio_config *cfg = DEV_CFG(dev);
struct tgpio_runtime *rt = DEV_DATA(dev);
device_map(&rt->reg_base,
cfg->reg_base.phys_addr & ~0xFFU,
cfg->reg_base.size,
K_MEM_CACHE_NONE);
return 0;
}
#define TGPIO_INTEL_DEV_CFG_DATA(n) \
static const struct tgpio_config \
tgpio_##n##_cfg = { \
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
.max_pins = DT_INST_PROP(n, max_pins), \
.art_clock_freq = DT_INST_PROP(n, timer_clock), \
}; \
\
static struct tgpio_runtime tgpio_##n##_runtime; \
\
DEVICE_DT_INST_DEFINE(n, \
&tgpio_init, \
NULL, \
&tgpio_##n##_runtime, \
&tgpio_##n##_cfg, \
POST_KERNEL, CONFIG_TIMEAWARE_GPIO_INIT_PRIORITY,\
&api_funcs); \
DT_INST_FOREACH_STATUS_OKAY(TGPIO_INTEL_DEV_CFG_DATA)
``` | /content/code_sandbox/drivers/misc/timeaware_gpio/timeaware_gpio_intel.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,786 |
```unknown
config PIO_RPI_PICO
bool "RaspberryPi Pico PIO"
default y
depends on DT_HAS_RASPBERRYPI_PICO_PIO_ENABLED
depends on RESET
select PICOSDK_USE_PIO
``` | /content/code_sandbox/drivers/misc/pio_rpi_pico/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config NORDIC_VPR_LAUNCHER
bool "Nordic VPR coprocessor launcher"
default y
depends on DT_HAS_NORDIC_NRF_VPR_COPROCESSOR_ENABLED
help
When enabled, the VPR coprocessors will be automatically launched
during system initialization.
if NORDIC_VPR_LAUNCHER
module = NORDIC_VPR_LAUNCHER
module-str = Nordic VPR Launcher
source "subsys/logging/Kconfig.template.log_config"
config NORDIC_VPR_LAUNCHER_INIT_PRIORITY
int "Nordic VPR coprocessor launcher init priority"
default 0
help
The init priority of the VPR coprocessor launcher.
endif # NORDIC_VPR_LAUNCHER
``` | /content/code_sandbox/drivers/misc/nordic_vpr_launcher/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_nrf_vpr_coprocessor
#include <string.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/toolchain.h>
#include <hal/nrf_vpr.h>
#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
#include <hal/nrf_spu.h>
#endif
LOG_MODULE_REGISTER(nordic_vpr_launcher, CONFIG_NORDIC_VPR_LAUNCHER_LOG_LEVEL);
struct nordic_vpr_launcher_config {
NRF_VPR_Type *vpr;
uintptr_t exec_addr;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory)
uintptr_t src_addr;
size_t size;
#endif
};
static int nordic_vpr_launcher_init(const struct device *dev)
{
const struct nordic_vpr_launcher_config *config = dev->config;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory)
if (config->size > 0U) {
LOG_DBG("Loading VPR (%p) from %p to %p (%zu bytes)", config->vpr,
(void *)config->src_addr, (void *)config->exec_addr, config->size);
memcpy((void *)config->exec_addr, (void *)config->src_addr, config->size);
}
#endif
#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
nrf_spu_periph_perm_secattr_set(NRF_SPU00, nrf_address_slave_get((uint32_t)config->vpr),
true);
#endif
LOG_DBG("Launching VPR (%p) from %p", config->vpr, (void *)config->exec_addr);
nrf_vpr_initpc_set(config->vpr, config->exec_addr);
nrf_vpr_cpurun_set(config->vpr, true);
return 0;
}
/* obtain VPR address either from memory or partition */
#define VPR_ADDR(node_id) \
(DT_REG_ADDR(node_id) + \
COND_CODE_0(DT_FIXED_PARTITION_EXISTS(node_id), (0), (DT_REG_ADDR(DT_GPARENT(node_id)))))
#define NORDIC_VPR_LAUNCHER_DEFINE(inst) \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \
(BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) <= \
DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \
"Execution memory exceeds source memory size");)) \
\
static const struct nordic_vpr_launcher_config config##inst = { \
.vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \
.exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)), \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \
(.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \
.size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \
\
DEVICE_DT_INST_DEFINE(inst, nordic_vpr_launcher_init, NULL, NULL, &config##inst, \
POST_KERNEL, CONFIG_NORDIC_VPR_LAUNCHER_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(NORDIC_VPR_LAUNCHER_DEFINE)
``` | /content/code_sandbox/drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 755 |
```unknown
config NXP_S32_EMIOS
bool "NXP S32 eMIOS drivers"
depends on DT_HAS_NXP_S32_EMIOS_ENABLED
help
Enable drivers for NXP S32 EMIOS
if NXP_S32_EMIOS
module = NXP_S32_EMIOS
module-str = NXP S32 eMIOS
source "subsys/logging/Kconfig.template.log_config"
config NXP_S32_EMIOS_INIT_PRIORITY
int "NXP S32 eMIOS initialization priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
System initialization priority for NXP S32 eMIOS drivers.
endif
``` | /content/code_sandbox/drivers/misc/nxp_s32_emios/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#define LOG_MODULE_NAME nxp_s32_emios
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_NXP_S32_EMIOS_LOG_LEVEL);
#include <Emios_Mcl_Ip.h>
#include <Emios_Mcl_Ip_Irq.h>
#define DT_DRV_COMPAT nxp_s32_emios
struct nxp_s32_emios_config {
uint8_t instance;
Emios_Mcl_Ip_ConfigType *mcl_info;
void (*irq_config)(void);
};
static int nxp_s32_emios_init(const struct device *dev)
{
const struct nxp_s32_emios_config *config = dev->config;
if (Emios_Mcl_Ip_Init(config->instance, config->mcl_info)) {
LOG_ERR("Could not initialize eMIOS");
return -EINVAL;
}
config->irq_config();
return 0;
}
#define MAX_MASTER_BUS_PERIOD 65535U
#define MIN_MASTER_BUS_PERIOD 2U
#define MAX_GLOB_PRESCALER 256U
#define MIN_GLOB_PRESCALER 1U
#define NXP_S32_EMIOS_MASTER_BUS_MODE(mode) DT_CAT(EMIOS_IP_, mode)
#define NXP_S32_EMIOS_INSTANCE_CHECK(idx, n) \
((DT_INST_REG_ADDR(n) == IP_EMIOS_##idx##_BASE) ? idx : 0)
#define NXP_S32_EMIOS_GET_INSTANCE(n) \
LISTIFY(__DEBRACKET eMIOS_INSTANCE_COUNT, NXP_S32_EMIOS_INSTANCE_CHECK, (|), n)
#define NXP_S32_EMIOS_GENERATE_GLOBAL_CONFIG(n) \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, clock_divider), \
MIN_GLOB_PRESCALER, MAX_GLOB_PRESCALER), \
"Divider for eMIOS global prescaler is out of range"); \
const Emios_Ip_GlobalConfigType nxp_s32_emios_##n##_global_config = { \
.allowDebugMode = true, \
.clkDivVal = DT_INST_PROP(n, clock_divider) - 1U, \
.enableGlobalTimeBase = true \
};
#define NXP_S32_EMIOS_MASTER_BUS_VERIFY(node_id) \
BUILD_ASSERT(IN_RANGE(DT_PROP(node_id, period), \
MIN_MASTER_BUS_PERIOD, MAX_MASTER_BUS_PERIOD), \
"Node "DT_NODE_PATH(node_id)": period is out of range");
#define NXP_S32_EMIOS_MASTER_BUS_CONFIG(node_id) \
{ \
.hwChannel = DT_PROP(node_id, channel), \
.defaultPeriod = DT_PROP(node_id, period), \
.masterBusPrescaler = DT_PROP(node_id, prescaler) - 1, \
.allowDebugMode = DT_PROP(node_id, freeze), \
.masterMode = NXP_S32_EMIOS_MASTER_BUS_MODE(DT_STRING_TOKEN(node_id, mode)), \
.masterBusAltPrescaler = 0, \
},
#define NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n) \
DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
NXP_S32_EMIOS_MASTER_BUS_VERIFY) \
const Emios_Ip_MasterBusConfigType nxp_s32_emios_##n##_master_bus_config[] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
NXP_S32_EMIOS_MASTER_BUS_CONFIG) \
};
#define NXP_S32_EMIOS_GENERATE_CONFIG(n) \
NXP_S32_EMIOS_GENERATE_GLOBAL_CONFIG(n) \
NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n) \
const Emios_Mcl_Ip_ConfigType nxp_s32_emios_##n##_mcl_config = { \
.channelsNumber = ARRAY_SIZE(nxp_s32_emios_##n##_master_bus_config), \
.emiosGlobalConfig = &nxp_s32_emios_##n##_global_config, \
.masterBusConfig = &nxp_s32_emios_##n##_master_bus_config \
};
#define EMIOS_INTERRUPT_NAME(name) DT_CAT3(EMIOS, name, _IRQ)
/*
* The real interrupt handlers only defined in some circumstances, just add
* weak implementations to avoid populating so many preprocessor directives
*/
#define EMIOS_INTERRUPT_DEFINE(node_id, prop, idx) \
__weak void EMIOS_INTERRUPT_NAME(DT_STRING_TOKEN_BY_IDX(node_id, prop, idx))(void) {}
#define NXP_S32_EMIOS_INTERRUPT_DEFINE(n) \
DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, EMIOS_INTERRUPT_DEFINE)
#define EMIOS_INTERRUPT_CONFIG(node_id, prop, idx) \
do { \
IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), \
DT_IRQ_BY_IDX(node_id, idx, priority), \
EMIOS_INTERRUPT_NAME(DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)),\
DEVICE_DT_GET(node_id), \
0); \
irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq)); \
} while (false);
#define NXP_S32_EMIOS_INTERRUPT_CONFIG(n) \
static void nxp_s32_emios_##n##_interrupt_config(void) \
{ \
DT_INST_FOREACH_PROP_ELEM(n, interrupt_names, EMIOS_INTERRUPT_CONFIG) \
}
#define NXP_S32_EMIOS_INIT_DEVICE(n) \
NXP_S32_EMIOS_GENERATE_CONFIG(n) \
NXP_S32_EMIOS_INTERRUPT_DEFINE(n) \
NXP_S32_EMIOS_INTERRUPT_CONFIG(n) \
const struct nxp_s32_emios_config nxp_s32_emios_##n##_config = { \
.instance = NXP_S32_EMIOS_GET_INSTANCE(n), \
.mcl_info = (Emios_Mcl_Ip_ConfigType *)&nxp_s32_emios_##n##_mcl_config, \
.irq_config = nxp_s32_emios_##n##_interrupt_config, \
}; \
DEVICE_DT_INST_DEFINE(n, \
&nxp_s32_emios_init, \
NULL, \
NULL, \
&nxp_s32_emios_##n##_config, \
POST_KERNEL, \
CONFIG_NXP_S32_EMIOS_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(NXP_S32_EMIOS_INIT_DEVICE)
``` | /content/code_sandbox/drivers/misc/nxp_s32_emios/nxp_s32_emios.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,509 |
```unknown
menuconfig COREDUMP_DEVICE
bool "Coredump pseudo-device drivers"
help
Enable support for a pseudo-device to help capturing
desired data into core dumps.
if COREDUMP_DEVICE
config COREDUMP_DEVICE_INIT_PRIORITY
int "Coredump device init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
Coredump pseudo-device driver initialization priority.
module = COREDUMP_DEVICE
module-str = coredump device
source "subsys/logging/Kconfig.template.log_config"
endif # COREDUMP_DEVICE
``` | /content/code_sandbox/drivers/coredump/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```c
/*
*
*/
#include <zephyr/debug/coredump.h>
#include <zephyr/drivers/coredump.h>
#define DT_DRV_COMPAT zephyr_coredump
enum COREDUMP_TYPE {
COREDUMP_TYPE_MEMCPY = 0,
COREDUMP_TYPE_CALLBACK = 1,
};
struct coredump_config {
/* Type of coredump device */
enum COREDUMP_TYPE type;
/* Length of memory_regions array */
int length;
/* Memory regions specified in device tree */
size_t memory_regions[];
};
struct coredump_data {
/* Memory regions registered at run time */
sys_slist_t region_list;
/* Callback to be invoked at time of dump */
coredump_dump_callback_t dump_callback;
};
static void coredump_impl_dump(const struct device *dev)
{
const struct coredump_config *config = dev->config;
struct coredump_data *data = dev->data;
if (config->type == COREDUMP_TYPE_CALLBACK) {
if (data->dump_callback) {
uintptr_t start_address = config->memory_regions[0];
size_t size = config->memory_regions[1];
/* Invoke callback to allow consumer to fill array with desired data */
data->dump_callback(start_address, size);
coredump_memory_dump(start_address, start_address + size);
}
} else { /* COREDUMP_TYPE_MEMCPY */
/*
* Add each memory region specified in device tree to the core dump,
* the memory_regions array should contain two entries per region
* containing the start address and size.
*/
if ((config->length > 0) && ((config->length % 2) == 0)) {
for (int i = 0; i < config->length; i += 2) {
uintptr_t start_address = config->memory_regions[i];
size_t size = config->memory_regions[i+1];
coredump_memory_dump(start_address, start_address + size);
}
}
sys_snode_t *node;
/* Add each memory region registered at runtime to the core dump */
SYS_SLIST_FOR_EACH_NODE(&data->region_list, node) {
struct coredump_mem_region_node *region;
region = CONTAINER_OF(node, struct coredump_mem_region_node, node);
coredump_memory_dump(region->start, region->start + region->size);
}
}
}
static bool coredump_impl_register_memory(const struct device *dev,
struct coredump_mem_region_node *region)
{
const struct coredump_config *config = dev->config;
if (config->type == COREDUMP_TYPE_CALLBACK) {
return false;
}
struct coredump_data *data = dev->data;
sys_slist_append(&data->region_list, ®ion->node);
return true;
}
static bool coredump_impl_unregister_memory(const struct device *dev,
struct coredump_mem_region_node *region)
{
const struct coredump_config *config = dev->config;
if (config->type == COREDUMP_TYPE_CALLBACK) {
return false;
}
struct coredump_data *data = dev->data;
return sys_slist_find_and_remove(&data->region_list, ®ion->node);
}
static bool coredump_impl_register_callback(const struct device *dev,
coredump_dump_callback_t callback)
{
const struct coredump_config *config = dev->config;
if (config->type == COREDUMP_TYPE_MEMCPY) {
return false;
}
struct coredump_data *data = dev->data;
data->dump_callback = callback;
return true;
}
static int coredump_init(const struct device *dev)
{
struct coredump_data *data = dev->data;
sys_slist_init(&data->region_list);
return 0;
}
static const struct coredump_driver_api coredump_api = {
.dump = coredump_impl_dump,
.register_memory = coredump_impl_register_memory,
.unregister_memory = coredump_impl_unregister_memory,
.register_callback = coredump_impl_register_callback,
};
#define INIT_REGION(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx),
#define DT_INST_COREDUMP_IF_TYPE_CALLBACK(n, a, b) \
COND_CODE_1(DT_INST_ENUM_IDX(n, coredump_type), a, b)
#define CREATE_COREDUMP_DEVICE(n) \
/* Statially allocate desired memory for the callback type device */ \
DT_INST_COREDUMP_IF_TYPE_CALLBACK(n, \
( \
BUILD_ASSERT(DT_INST_PROP_LEN(n, memory_regions) == 2, \
"Allow exactly one entry (address and size) in memory_regions"); \
BUILD_ASSERT(DT_INST_PROP_BY_IDX(n, memory_regions, 0) == 0, \
"Verify address is set to 0"); \
static uint8_t coredump_bytes[DT_INST_PROP_BY_IDX(n, memory_regions, 1)] \
__aligned(4); \
), ()) \
static struct coredump_data coredump_data_##n; \
static const struct coredump_config coredump_config##n = { \
.type = DT_INST_STRING_TOKEN_OR(n, coredump_type, COREDUMP_TYPE_MEMCPY), \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, memory_regions), \
( \
.length = DT_INST_PROP_LEN(n, memory_regions), \
DT_INST_COREDUMP_IF_TYPE_CALLBACK(n, \
( \
/* Callback type device has one entry in memory_regions array */ \
.memory_regions = { \
(size_t)&coredump_bytes[0], \
DT_INST_PROP_BY_IDX(n, memory_regions, 1), \
}, \
), \
( \
.memory_regions = { \
DT_INST_FOREACH_PROP_ELEM(n, memory_regions, INIT_REGION) \
}, \
)) \
), \
( \
.length = 0, \
)) \
}; \
DEVICE_DT_INST_DEFINE(n, \
coredump_init, \
NULL, \
&coredump_data_##n, \
&coredump_config##n, \
PRE_KERNEL_1, \
CONFIG_COREDUMP_DEVICE_INIT_PRIORITY, \
&coredump_api);
DT_INST_FOREACH_STATUS_OKAY(CREATE_COREDUMP_DEVICE)
``` | /content/code_sandbox/drivers/coredump/coredump_impl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,415 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/kernel.h>
/* LoRaMac-node specific includes */
#include <radio.h>
#include "sx12xx_common.h"
#define STATE_FREE 0
#define STATE_BUSY 1
#define STATE_CLEANUP 2
LOG_MODULE_REGISTER(sx12xx_common, CONFIG_LORA_LOG_LEVEL);
struct sx12xx_rx_params {
uint8_t *buf;
uint8_t *size;
int16_t *rssi;
int8_t *snr;
};
static struct sx12xx_data {
const struct device *dev;
struct k_poll_signal *operation_done;
lora_recv_cb async_rx_cb;
RadioEvents_t events;
struct lora_modem_config tx_cfg;
atomic_t modem_usage;
struct sx12xx_rx_params rx_params;
} dev_data;
int __sx12xx_configure_pin(const struct gpio_dt_spec *gpio, gpio_flags_t flags)
{
int err;
if (!device_is_ready(gpio->port)) {
LOG_ERR("GPIO device not ready %s", gpio->port->name);
return -ENODEV;
}
err = gpio_pin_configure_dt(gpio, flags);
if (err) {
LOG_ERR("Cannot configure gpio %s %d: %d", gpio->port->name,
gpio->pin, err);
return err;
}
return 0;
}
/**
* @brief Attempt to acquire the modem for operations
*
* @param data common sx12xx data struct
*
* @retval true if modem was acquired
* @retval false otherwise
*/
static inline bool modem_acquire(struct sx12xx_data *data)
{
return atomic_cas(&data->modem_usage, STATE_FREE, STATE_BUSY);
}
/**
* @brief Safely release the modem from any context
*
* This function can be called from any context and guarantees that the
* release operations will only be run once.
*
* @param data common sx12xx data struct
*
* @retval true if modem was released by this function
* @retval false otherwise
*/
static bool modem_release(struct sx12xx_data *data)
{
/* Increment atomic so both acquire and release will fail */
if (!atomic_cas(&data->modem_usage, STATE_BUSY, STATE_CLEANUP)) {
return false;
}
/* Put radio back into sleep mode */
Radio.Sleep();
/* Completely release modem */
data->operation_done = NULL;
atomic_clear(&data->modem_usage);
return true;
}
static void sx12xx_ev_rx_done(uint8_t *payload, uint16_t size, int16_t rssi,
int8_t snr)
{
struct k_poll_signal *sig = dev_data.operation_done;
/* Receiving in asynchronous mode */
if (dev_data.async_rx_cb) {
/* Start receiving again */
Radio.Rx(0);
/* Run the callback */
dev_data.async_rx_cb(dev_data.dev, payload, size, rssi, snr);
/* Don't run the synchronous code */
return;
}
/* Manually release the modem instead of just calling modem_release
* as we need to perform cleanup operations while still ensuring
* others can't use the modem.
*/
if (!atomic_cas(&dev_data.modem_usage, STATE_BUSY, STATE_CLEANUP)) {
return;
}
/* We can make two observations here:
* 1. lora_recv hasn't already exited due to a timeout.
* (modem_release would have been successfully called)
* 2. If the k_poll in lora_recv times out before we raise the signal,
* but while this code is running, it will block on the
* signal again.
* This lets us guarantee that the operation_done signal and pointers
* in rx_params are always valid in this function.
*/
/* Store actual size */
if (size < *dev_data.rx_params.size) {
*dev_data.rx_params.size = size;
}
/* Copy received data to output buffer */
memcpy(dev_data.rx_params.buf, payload,
*dev_data.rx_params.size);
/* Output RSSI and SNR */
if (dev_data.rx_params.rssi) {
*dev_data.rx_params.rssi = rssi;
}
if (dev_data.rx_params.snr) {
*dev_data.rx_params.snr = snr;
}
/* Put radio back into sleep mode */
Radio.Sleep();
/* Completely release modem */
dev_data.operation_done = NULL;
atomic_clear(&dev_data.modem_usage);
/* Notify caller RX is complete */
k_poll_signal_raise(sig, 0);
}
static void sx12xx_ev_tx_done(void)
{
struct k_poll_signal *sig = dev_data.operation_done;
if (modem_release(&dev_data)) {
/* Raise signal if provided */
if (sig) {
k_poll_signal_raise(sig, 0);
}
}
}
static void sx12xx_ev_tx_timed_out(void)
{
/* Just release the modem */
modem_release(&dev_data);
}
static void sx12xx_ev_rx_error(void)
{
struct k_poll_signal *sig = dev_data.operation_done;
/* Receiving in asynchronous mode */
if (dev_data.async_rx_cb) {
/* Start receiving again */
Radio.Rx(0);
/* Don't run the synchronous code */
return;
}
/* Finish synchronous receive with error */
if (modem_release(&dev_data)) {
/* Raise signal if provided */
if (sig) {
k_poll_signal_raise(sig, -EIO);
}
}
}
int sx12xx_lora_send(const struct device *dev, uint8_t *data,
uint32_t data_len)
{
struct k_poll_signal done = K_POLL_SIGNAL_INITIALIZER(done);
struct k_poll_event evt = K_POLL_EVENT_INITIALIZER(
K_POLL_TYPE_SIGNAL,
K_POLL_MODE_NOTIFY_ONLY,
&done);
uint32_t air_time;
int ret;
/* Validate that we have a TX configuration */
if (!dev_data.tx_cfg.frequency) {
return -EINVAL;
}
ret = sx12xx_lora_send_async(dev, data, data_len, &done);
if (ret < 0) {
return ret;
}
/* Calculate expected airtime of the packet */
air_time = Radio.TimeOnAir(MODEM_LORA,
dev_data.tx_cfg.bandwidth,
dev_data.tx_cfg.datarate,
dev_data.tx_cfg.coding_rate,
dev_data.tx_cfg.preamble_len,
0, data_len, true);
LOG_DBG("Expected air time of %d bytes = %dms", data_len, air_time);
/* Wait for the packet to finish transmitting.
* Use twice the tx duration to ensure that we are actually detecting
* a failed transmission, and not some minor timing variation between
* modem and driver.
*/
ret = k_poll(&evt, 1, K_MSEC(2 * air_time));
if (ret < 0) {
LOG_ERR("Packet transmission failed!");
if (!modem_release(&dev_data)) {
/* TX done interrupt is currently running */
k_poll(&evt, 1, K_FOREVER);
}
}
return ret;
}
int sx12xx_lora_send_async(const struct device *dev, uint8_t *data,
uint32_t data_len, struct k_poll_signal *async)
{
/* Ensure available, freed by sx12xx_ev_tx_done */
if (!modem_acquire(&dev_data)) {
return -EBUSY;
}
/* Store signal */
dev_data.operation_done = async;
Radio.SetMaxPayloadLength(MODEM_LORA, data_len);
Radio.Send(data, data_len);
return 0;
}
int sx12xx_lora_recv(const struct device *dev, uint8_t *data, uint8_t size,
k_timeout_t timeout, int16_t *rssi, int8_t *snr)
{
struct k_poll_signal done = K_POLL_SIGNAL_INITIALIZER(done);
struct k_poll_event evt = K_POLL_EVENT_INITIALIZER(
K_POLL_TYPE_SIGNAL,
K_POLL_MODE_NOTIFY_ONLY,
&done);
int ret;
/* Ensure available, decremented by sx12xx_ev_rx_done or on timeout */
if (!modem_acquire(&dev_data)) {
return -EBUSY;
}
dev_data.async_rx_cb = NULL;
/* Store operation signal */
dev_data.operation_done = &done;
/* Set data output location */
dev_data.rx_params.buf = data;
dev_data.rx_params.size = &size;
dev_data.rx_params.rssi = rssi;
dev_data.rx_params.snr = snr;
Radio.SetMaxPayloadLength(MODEM_LORA, 255);
Radio.Rx(0);
ret = k_poll(&evt, 1, timeout);
if (ret < 0) {
if (!modem_release(&dev_data)) {
/* Releasing the modem failed, which means that
* the RX callback is currently running. Wait until
* the RX callback finishes and we get our packet.
*/
k_poll(&evt, 1, K_FOREVER);
/* We did receive a packet */
return size;
}
LOG_INF("Receive timeout");
return ret;
}
if (done.result < 0) {
LOG_ERR("Receive error");
return done.result;
}
return size;
}
int sx12xx_lora_recv_async(const struct device *dev, lora_recv_cb cb)
{
/* Cancel ongoing reception */
if (cb == NULL) {
if (!modem_release(&dev_data)) {
/* Not receiving or already being stopped */
return -EINVAL;
}
return 0;
}
/* Ensure available */
if (!modem_acquire(&dev_data)) {
return -EBUSY;
}
/* Store parameters */
dev_data.async_rx_cb = cb;
/* Start reception */
Radio.SetMaxPayloadLength(MODEM_LORA, 255);
Radio.Rx(0);
return 0;
}
int sx12xx_lora_config(const struct device *dev,
struct lora_modem_config *config)
{
/* Ensure available, decremented after configuration */
if (!modem_acquire(&dev_data)) {
return -EBUSY;
}
Radio.SetChannel(config->frequency);
if (config->tx) {
/* Store TX config locally for airtime calculations */
memcpy(&dev_data.tx_cfg, config, sizeof(dev_data.tx_cfg));
/* Configure radio driver */
Radio.SetTxConfig(MODEM_LORA, config->tx_power, 0,
config->bandwidth, config->datarate,
config->coding_rate, config->preamble_len,
false, true, 0, 0, config->iq_inverted, 4000);
} else {
/* TODO: Get symbol timeout value from config parameters */
Radio.SetRxConfig(MODEM_LORA, config->bandwidth,
config->datarate, config->coding_rate,
0, config->preamble_len, 10, false, 0,
false, 0, 0, config->iq_inverted, true);
}
Radio.SetPublicNetwork(config->public_network);
modem_release(&dev_data);
return 0;
}
int sx12xx_lora_test_cw(const struct device *dev, uint32_t frequency,
int8_t tx_power,
uint16_t duration)
{
/* Ensure available, freed in sx12xx_ev_tx_done */
if (!modem_acquire(&dev_data)) {
return -EBUSY;
}
Radio.SetTxContinuousWave(frequency, tx_power, duration);
return 0;
}
int sx12xx_init(const struct device *dev)
{
atomic_set(&dev_data.modem_usage, 0);
dev_data.dev = dev;
dev_data.events.TxDone = sx12xx_ev_tx_done;
dev_data.events.RxDone = sx12xx_ev_rx_done;
dev_data.events.RxError = sx12xx_ev_rx_error;
/* TX timeout event raises at the end of the test CW transmission */
dev_data.events.TxTimeout = sx12xx_ev_tx_timed_out;
Radio.Init(&dev_data.events);
/*
* Automatically place the radio into sleep mode upon boot.
* The required `lora_config` call before transmission or reception
* will bring the radio out of sleep mode before it is used. The radio
* is automatically placed back into sleep mode upon TX or RX
* completion.
*/
Radio.Sleep();
return 0;
}
``` | /content/code_sandbox/drivers/lora/sx12xx_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,719 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include "sx126x_common.h"
#include <stm32wlxx_ll_exti.h>
#include <stm32wlxx_ll_pwr.h>
#include <stm32wlxx_ll_rcc.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_DECLARE(sx126x, CONFIG_LORA_LOG_LEVEL);
static const enum {
RFO_LP,
RFO_HP,
} pa_output = DT_INST_STRING_UPPER_TOKEN(0, power_amplifier_output);
void sx126x_reset(struct sx126x_data *dev_data)
{
LL_RCC_RF_EnableReset();
k_sleep(K_MSEC(20));
LL_RCC_RF_DisableReset();
k_sleep(K_MSEC(10));
}
bool sx126x_is_busy(struct sx126x_data *dev_data)
{
return LL_PWR_IsActiveFlag_RFBUSYS();
}
uint32_t sx126x_get_dio1_pin_state(struct sx126x_data *dev_data)
{
return 0;
}
void sx126x_dio1_irq_enable(struct sx126x_data *dev_data)
{
NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
irq_enable(DT_INST_IRQN(0));
}
void sx126x_dio1_irq_disable(struct sx126x_data *dev_data)
{
irq_disable(DT_INST_IRQN(0));
}
void sx126x_set_tx_params(int8_t power, RadioRampTimes_t ramp_time)
{
uint8_t buf[2];
if (pa_output == RFO_LP) {
const int8_t max_power = DT_INST_PROP(0, rfo_lp_max_power);
if (power > max_power) {
power = max_power;
}
if (max_power == 15) {
SX126xSetPaConfig(0x07, 0x00, 0x01, 0x01);
power = 14 - (max_power - power);
} else if (max_power == 10) {
SX126xSetPaConfig(0x01, 0x00, 0x01, 0x01);
power = 13 - (max_power - power);
} else { /* default +14 dBm */
SX126xSetPaConfig(0x04, 0x00, 0x01, 0x01);
power = 14 - (max_power - power);
}
if (power < -17) {
power = -17;
}
/* PA overcurrent protection limit 60 mA */
SX126xWriteRegister(REG_OCP, 0x18);
} else { /* RFO_HP */
/* Better Resistance of the RFO High Power Tx to Antenna
* Mismatch, see STM32WL Erratasheet
*/
SX126xWriteRegister(REG_TX_CLAMP_CFG,
SX126xReadRegister(REG_TX_CLAMP_CFG)
| (0x0F << 1));
const int8_t max_power = DT_INST_PROP(0, rfo_hp_max_power);
if (power > max_power) {
power = max_power;
}
if (max_power == 20) {
SX126xSetPaConfig(0x03, 0x05, 0x00, 0x01);
power = 22 - (max_power - power);
} else if (max_power == 17) {
SX126xSetPaConfig(0x02, 0x03, 0x00, 0x01);
power = 22 - (max_power - power);
} else if (max_power == 14) {
SX126xSetPaConfig(0x02, 0x02, 0x00, 0x01);
power = 14 - (max_power - power);
} else { /* default +22 dBm */
SX126xSetPaConfig(0x04, 0x07, 0x00, 0x01);
power = 22 - (max_power - power);
}
if (power < -9) {
power = -9;
}
/* PA overcurrent protection limit 140 mA */
SX126xWriteRegister(REG_OCP, 0x38);
}
buf[0] = power;
buf[1] = (uint8_t)ramp_time;
SX126xWriteCommand(RADIO_SET_TXPARAMS, buf, 2);
}
static void radio_isr(const struct device *dev)
{
struct sx126x_data *dev_data = dev->data;
irq_disable(DT_INST_IRQN(0));
k_work_submit(&dev_data->dio1_irq_work);
}
int sx126x_variant_init(const struct device *dev)
{
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
radio_isr, DEVICE_DT_INST_GET(0), 0);
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
irq_enable(DT_INST_IRQN(0));
return 0;
}
``` | /content/code_sandbox/drivers/lora/sx126x_stm32wl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,119 |
```c
/*
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define DT_DRV_COMPAT reyax_rylrxxx
#include <zephyr/logging/log.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/modem/pipe.h>
#include <zephyr/modem/backend/uart.h>
#include <zephyr/modem/chat.h>
#include <zephyr/sys/atomic.h>
#include <errno.h>
LOG_MODULE_REGISTER(rylr, CONFIG_LORA_LOG_LEVEL);
#define RYLR_CMD_BAND_FORMAT "AT+BAND=%u\r\n"
#define RYLR_CMD_BAND_PARM_CHARS 9U
#define RYLR_CMD_BAND_FORMAT_NUM_WILDCARDS 1U
#define RYLR_CMD_BAND_FORMAT_WILDCARD_CHARS (RYLR_CMD_BAND_FORMAT_NUM_WILDCARDS * 2)
#define RYLR_CMD_BAND_FORMAT_LEN_WITHOUT_WILDCARDS \
(sizeof(RYLR_CMD_BAND_FORMAT) - RYLR_CMD_BAND_FORMAT_WILDCARD_CHARS - 1)
#define RYLR_CMD_BAND_LENGTH (RYLR_CMD_BAND_FORMAT_LEN_WITHOUT_WILDCARDS + RYLR_CMD_BAND_PARM_CHARS)
#define RYLR_CMD_SEND_FORMAT "AT+SEND=0,%u,%s\r\n"
#define RYLR_CMD_SEND_FORMAT_NUM_WILDCARDS 2U
#define RYLR_CMD_SEND_FORMAT_WILDCARD_CHARS (RYLR_CMD_SEND_FORMAT_NUM_WILDCARDS * 2)
#define RYLR_CMD_SEND_FORMAT_LEN_WITHOUT_WILDCARDS \
(sizeof(RYLR_CMD_SEND_FORMAT) - RYLR_CMD_SEND_FORMAT_WILDCARD_CHARS - 1)
#define RYLR_PAYLOAD_LENGTH_FIELD_CHARS(payload_len) \
(payload_len >= 100 ? 3 : (payload_len >= 10 ? 2 : 1))
#define RYLR_CMD_SEND_LENGTH(payload_len) \
(RYLR_CMD_SEND_FORMAT_LEN_WITHOUT_WILDCARDS + \
RYLR_PAYLOAD_LENGTH_FIELD_CHARS(payload_len) + payload_len)
#define RYLR_CMD_RF_SETTINGS_FORMAT "AT+PARAMETER=%u,%u,%u,%u\r\n"
#define RYLR_CMD_RF_SETTINGS_FORMAT_NUM_WILDCARDS 4U
#define RYLR_CMD_RF_SETTINGS_FORMAT_WILDCARD_CHARS (RYLR_CMD_RF_SETTINGS_FORMAT_NUM_WILDCARDS * 2U)
#define RYLR_CMD_RF_SETTINGS_FORMAT_LEN_WITHOUT_WILDCARDS \
(sizeof(RYLR_CMD_RF_SETTINGS_FORMAT) - RYLR_CMD_RF_SETTINGS_FORMAT_WILDCARD_CHARS - 1)
#define RYLR_CMD_RF_SETTINGS_FORMAT_PARAM_CHARS(spread_factor) \
(RYLR_CMD_RF_SETTINGS_FORMAT_NUM_WILDCARDS - 1) + (spread_factor >= 10U ? 2U : 1U)
#define RYLR_CMD_RF_SETTINGS_LEN(spread_factor) \
(RYLR_CMD_RF_SETTINGS_FORMAT_LEN_WITHOUT_WILDCARDS + \
RYLR_CMD_RF_SETTINGS_FORMAT_PARAM_CHARS(spread_factor))
#define RYLR_CMD_POWER_FORMAT "AT+CRFOP=%u\r\n"
#define RYLR_CMD_POWER_FORMAT_NUM_WILDCARDS 1U
#define RYLR_CMD_POWER_FORMAT_WILDCARD_CHARS (RYLR_CMD_POWER_FORMAT_NUM_WILDCARDS * 2U)
#define RYLR_CMD_POWER_FORMAT_LEN_WITHOUT_WILDCARDS \
(sizeof(RYLR_CMD_POWER_FORMAT) - RYLR_CMD_POWER_FORMAT_WILDCARD_CHARS - 1)
#define RYLR_CMD_POWER_FORMAT_PARAM_CHARS(power) (power >= 10U ? 2U : 1U)
#define RYLR_CMD_POWER_LEN(power) \
(RYLR_CMD_POWER_FORMAT_LEN_WITHOUT_WILDCARDS + RYLR_CMD_POWER_FORMAT_PARAM_CHARS(power))
#define RYLR_MAX_RESPONSE 256
#define RYLR_MAX_MSG_BYTES 256
#define RYLR_ALLOC_TIMEOUT K_SECONDS(1)
#define RYLR_TX_PENDING_FLAG_POS (0U)
#define RYLR_RX_PENDING_FLAG_POS (1U)
#define RYLR_IS_TX_PENDING(flags) (flags & (0x01 << RYLR_TX_PENDING_FLAG_POS))
#define RYLR_IS_RX_PENDING(flags) (flags & (0x01 << RYLR_RX_PENDING_FLAG_POS))
#define RYLR_SET_TX_PENDING(flags) (flags |= (0x01 << RYLR_TX_PENDING_FLAG_POS))
#define RYLR_SET_RX_PENDING(flags) (flags |= (0x01 << RYLR_RX_PENDING_FLAG_POS))
#define RYLR_CLEAR_TX_PENDING(flags) (flags &= ~(0x01 << RYLR_TX_PENDING_FLAG_POS))
#define RYLR_CLEAR_RX_PENDING(flags) (flags &= ~(0x01 << RYLR_RX_PENDING_FLAG_POS))
#define RYLR_IS_ASYNC_OP_PENDING(flags) (RYLR_IS_RX_PENDING(flags) || RYLR_IS_TX_PENDING(flags))
#define RYLR_MAX_RESPONSE_ARGS 6U
#define RYLR_MIN_RESET_MSECS (100U)
#define RYLR_RESET_WAIT_MSECS (RYLR_MIN_RESET_MSECS + 10U)
struct rylr_config {
const struct device *uart;
const struct gpio_dt_spec reset;
};
struct rylr_data {
uint8_t cmd_buffer[CONFIG_LORA_RYLRXX_CMD_BUF_SIZE];
size_t curr_cmd_len;
bool is_tx;
int handler_error;
struct k_msgq rx_msgq;
struct k_sem script_sem;
struct k_sem operation_sem;
uint8_t pending_async_flags;
struct k_poll_signal *async_tx_signal;
lora_recv_cb async_rx_cb;
const struct device *dev;
uint8_t msgq_buffer[CONFIG_RYLRXXX_UNSOLICITED_RX_MSGQ_SIZE];
struct modem_pipe *modem_pipe;
uint8_t uart_backend_rx_buff[CONFIG_RYLRXXX_MODEM_BUFFERS_SIZE];
uint8_t uart_backend_tx_buff[CONFIG_RYLRXXX_MODEM_BUFFERS_SIZE];
struct modem_pipe *uart_pipe;
struct modem_backend_uart uart_backend;
uint8_t chat_rx_buf[CONFIG_RYLRXXX_MODEM_BUFFERS_SIZE];
uint8_t chat_tx_buf[CONFIG_RYLRXXX_MODEM_BUFFERS_SIZE];
uint8_t *chat_argv[RYLR_MAX_RESPONSE_ARGS];
struct modem_chat chat;
struct modem_chat_script dynamic_script;
struct modem_chat_script_chat dynamic_chat;
};
struct rylr_recv_msg {
uint16_t addr;
uint8_t length;
uint8_t *data;
uint8_t rssi;
uint8_t snr;
};
static void on_ok(struct modem_chat *chat, char **argv, uint16_t argc, void *user_data)
{
int err = 0;
struct rylr_data *driver_data = user_data;
driver_data->handler_error = err;
}
static void on_err(struct modem_chat *chat, char **argv, uint16_t argc, void *user_data)
{
int radio_err = 0;
struct rylr_data *driver_data = user_data;
driver_data->handler_error = -EIO;
if (argc != 2) {
driver_data->handler_error = -EBADMSG;
LOG_ERR("malformed error message from radio");
return;
}
radio_err = atoi(argv[1]);
LOG_ERR("error from rylr: %d", radio_err);
}
static void on_rx(struct modem_chat *chat, char **argv, uint16_t argc, void *user_data)
{
struct rylr_data *driver_data = user_data;
struct rylr_recv_msg msg;
int err = 0;
driver_data->handler_error = 0;
if (argc != 6) {
driver_data->handler_error = -EBADMSG;
return;
}
msg.addr = atoi(argv[1]);
msg.length = atoi(argv[2]);
msg.data = argv[3];
msg.rssi = atoi(argv[4]);
msg.snr = atoi(argv[5]);
if (RYLR_IS_RX_PENDING(driver_data->pending_async_flags)) {
driver_data->async_rx_cb(driver_data->dev, msg.data, msg.length, msg.rssi, msg.snr);
} else {
err = k_msgq_put(&driver_data->rx_msgq, &msg, K_NO_WAIT);
if (err != 0) {
LOG_ERR("error adding messgae to queue: %d", err);
driver_data->handler_error = err;
}
}
}
static void on_script_finished(struct modem_chat *chat, enum modem_chat_script_result result,
void *user_data)
{
struct rylr_data *driver_data = user_data;
if (RYLR_IS_TX_PENDING(driver_data->pending_async_flags)) {
RYLR_CLEAR_TX_PENDING(driver_data->pending_async_flags);
k_poll_signal_raise(driver_data->async_tx_signal, driver_data->handler_error);
k_sem_give(&driver_data->operation_sem);
}
k_sem_give(&driver_data->script_sem);
}
MODEM_CHAT_MATCH_DEFINE(ok_match, "+OK", "", on_ok);
MODEM_CHAT_MATCHES_DEFINE(abort_matches, MODEM_CHAT_MATCH("+ERR=", "", on_err));
MODEM_CHAT_MATCHES_DEFINE(unsol_matches, MODEM_CHAT_MATCH("+RCV=", ",", on_rx));
MODEM_CHAT_SCRIPT_CMDS_DEFINE(ping_cmd, MODEM_CHAT_SCRIPT_CMD_RESP("AT\r\n", ok_match));
MODEM_CHAT_SCRIPT_DEFINE(ping_script, ping_cmd, abort_matches, on_script_finished,
CONFIG_RYLRXXX_RADIO_CMD_RESPONSE_TIMEOUT_MS);
static void rylr_reset_dynamic_script(struct rylr_data *data)
{
data->dynamic_chat.response_matches = &ok_match;
data->dynamic_chat.response_matches_size = 1;
data->dynamic_chat.timeout = 0;
data->dynamic_script.script_chats = &data->dynamic_chat;
data->dynamic_script.script_chats_size = 1;
data->dynamic_script.abort_matches = abort_matches;
data->dynamic_script.abort_matches_size = 1;
data->dynamic_script.callback = on_script_finished;
data->dynamic_script.timeout = CONFIG_RYLRXXX_RADIO_CMD_RESPONSE_TIMEOUT_MS;
}
static uint32_t rylr_get_bandwidth_index(enum lora_signal_bandwidth bw)
{
switch (bw) {
case BW_125_KHZ:
return 7;
case BW_250_KHZ:
return 8;
case BW_500_KHZ:
return 9;
default:
return 7;
}
}
static int rylr_send_cmd_buffer(const struct device *dev)
{
int err = 0;
struct rylr_data *data = dev->data;
rylr_reset_dynamic_script(data);
data->dynamic_chat.request = data->cmd_buffer;
data->dynamic_chat.request_size = data->curr_cmd_len;
err = modem_chat_run_script(&data->chat, &data->dynamic_script);
if (err != 0) {
LOG_ERR("could not send cmd: %s. err: %d", data->cmd_buffer, err);
return err;
}
err = k_sem_take(&data->script_sem, K_MSEC(CONFIG_RYLRXXX_RADIO_CMD_RESPONSE_TIMEOUT_MS));
if (err) {
LOG_ERR("error waiting for response: %d", err);
return err;
}
return data->handler_error;
}
static int rylr_set_rf_band(const struct device *dev, uint32_t frequency)
{
struct rylr_data *data = dev->data;
if (sprintf(data->cmd_buffer, RYLR_CMD_BAND_FORMAT, frequency) != RYLR_CMD_BAND_LENGTH) {
LOG_ERR("could not create frequency string");
return -EINVAL;
}
data->curr_cmd_len = RYLR_CMD_BAND_LENGTH;
return rylr_send_cmd_buffer(dev);
}
static int rylr_set_rf_parameters(const struct device *dev, uint32_t datarate, uint32_t bandwidth,
uint32_t coding_rate, uint32_t preamble_length)
{
struct rylr_data *data = dev->data;
size_t cmd_len;
if (datarate < 7 || datarate > 12) {
LOG_ERR("datarate/spread factor must be between 7 and 12 inclusive");
return -EINVAL;
}
if (coding_rate < 1 || coding_rate > 4) {
LOG_ERR("coding rate must be between 1 and 4 inclusive");
return -EINVAL;
}
if (preamble_length < 4 || preamble_length > 7) {
LOG_ERR("preamble length must be between 4 and 7 inclusive");
return -EINVAL;
}
cmd_len = sprintf(data->cmd_buffer, RYLR_CMD_RF_SETTINGS_FORMAT, datarate,
rylr_get_bandwidth_index(bandwidth), coding_rate, preamble_length);
if (cmd_len != RYLR_CMD_RF_SETTINGS_LEN(datarate)) {
LOG_ERR("could not create rf settings string");
return -EINVAL;
}
data->curr_cmd_len = cmd_len;
return rylr_send_cmd_buffer(dev);
}
static int rylr_set_power(const struct device *dev, uint32_t power)
{
struct rylr_data *data = dev->data;
size_t cmd_len;
if (power > 15) {
LOG_ERR("power cannot be greater than 15");
return -EINVAL;
}
cmd_len = RYLR_CMD_POWER_LEN(power);
if (sprintf(data->cmd_buffer, RYLR_CMD_POWER_FORMAT, power) != cmd_len) {
LOG_ERR("could not create power string");
return -EINVAL;
}
data->curr_cmd_len = cmd_len;
return rylr_send_cmd_buffer(dev);
}
static int rylr_config(const struct device *dev, struct lora_modem_config *config)
{
int err = 0;
struct rylr_data *data = dev->data;
err = k_sem_take(&data->operation_sem, K_NO_WAIT);
if (err != 0) {
LOG_ERR("error taking operation semaphore: %d", err);
return err;
}
if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
LOG_ERR("pending async opperation");
err = -EBUSY;
goto exit;
}
err = rylr_set_rf_band(dev, config->frequency);
if (err != 0) {
LOG_ERR("could not send frequency cmd: %d", err);
goto exit;
}
err = rylr_set_rf_parameters(dev, config->datarate, config->bandwidth, config->coding_rate,
config->preamble_len);
if (err != 0) {
LOG_ERR("could not send rf params cmd: %d", err);
goto exit;
}
err = rylr_set_power(dev, config->tx_power);
if (err != 0) {
LOG_ERR("could not send power cmd: %d", err);
goto exit;
}
data->is_tx = config->tx;
exit:
k_sem_give(&data->operation_sem);
return err;
}
int rylr_send(const struct device *dev, uint8_t *payload, uint32_t payload_len)
{
int err = 0;
struct rylr_data *data = dev->data;
int cmd_len = RYLR_CMD_SEND_LENGTH(payload_len);
err = k_sem_take(&data->operation_sem, K_NO_WAIT);
if (err != 0) {
LOG_ERR("error taking operation semaphore: %d", err);
return err;
}
if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
LOG_ERR("pending async opperation");
err = -EBUSY;
goto exit;
}
if (!data->is_tx) {
LOG_ERR("radio not configured in tx mode");
err = -EOPNOTSUPP;
goto exit;
}
if (cmd_len > CONFIG_LORA_RYLRXX_CMD_BUF_SIZE) {
LOG_ERR("payload too long");
err = -EINVAL;
goto exit;
}
snprintf(data->cmd_buffer, cmd_len + 1, RYLR_CMD_SEND_FORMAT, payload_len, payload);
data->curr_cmd_len = cmd_len;
err = rylr_send_cmd_buffer(dev);
if (err != 0) {
LOG_ERR("error sending data: %d", err);
goto exit;
}
exit:
k_sem_give(&data->operation_sem);
return err;
}
int rylr_send_async(const struct device *dev, uint8_t *payload, uint32_t payload_len,
struct k_poll_signal *async)
{
int err = 0;
struct rylr_data *data = dev->data;
int cmd_len;
err = k_sem_take(&data->operation_sem, K_NO_WAIT);
if (err != 0) {
LOG_ERR("error taking operation sem: %d", err);
return err;
}
if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
LOG_ERR("pending async opperation");
err = -EBUSY;
goto bail;
}
RYLR_SET_TX_PENDING(data->pending_async_flags);
if (!data->is_tx) {
LOG_ERR("radio not configured in tx mode");
err = -EOPNOTSUPP;
goto bail;
}
cmd_len = RYLR_CMD_SEND_LENGTH(payload_len);
if (cmd_len > CONFIG_LORA_RYLRXX_CMD_BUF_SIZE) {
LOG_ERR("payload too long");
err = -EINVAL;
goto bail;
}
if (async == NULL) {
LOG_ERR("async signal cannot be null");
err = -EINVAL;
goto bail;
}
data->async_tx_signal = async;
data->curr_cmd_len =
snprintf(data->cmd_buffer, cmd_len + 1, RYLR_CMD_SEND_FORMAT, payload_len, payload);
rylr_reset_dynamic_script(data);
data->dynamic_chat.request = data->cmd_buffer;
data->dynamic_chat.request_size = data->curr_cmd_len;
return modem_chat_run_script_async(&data->chat, &data->dynamic_script);
bail:
RYLR_CLEAR_TX_PENDING(data->pending_async_flags);
k_sem_give(&data->operation_sem);
return err;
}
int rylr_recv(const struct device *dev, uint8_t *ret_msg, uint8_t size, k_timeout_t timeout,
int16_t *rssi, int8_t *snr)
{
int ret = 0;
struct rylr_data *data = dev->data;
struct rylr_recv_msg msg;
ret = k_sem_take(&data->operation_sem, K_NO_WAIT);
if (ret != 0) {
LOG_ERR("error taking operation semaphore: %d", ret);
return ret;
}
if (data->is_tx) {
LOG_ERR("radio is configured for tx");
ret = -EOPNOTSUPP;
goto exit;
}
if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
LOG_ERR("pending async opperation");
ret = -EBUSY;
goto exit;
}
ret = k_msgq_get(&data->rx_msgq, &msg, timeout);
if (ret != 0) {
LOG_ERR("error getting msg from queue: %d", ret);
goto exit;
}
ret = data->handler_error;
if (ret != 0) {
LOG_ERR("error in recv cb: %d", ret);
goto exit;
}
if (msg.length > size) {
LOG_ERR("buf len of %u too small for message len of %u", size, msg.length);
ret = -ENOBUFS;
goto exit;
}
*rssi = msg.rssi;
*snr = msg.snr;
memcpy(ret_msg, msg.data, msg.length);
ret = msg.length;
exit:
k_sem_give(&data->operation_sem);
return ret;
}
int rylr_recv_async(const struct device *dev, lora_recv_cb cb)
{
int err = 0;
struct rylr_data *data = dev->data;
err = k_sem_take(&data->operation_sem, K_NO_WAIT);
if (err != 0) {
LOG_ERR("error taking operation semaphore: %d", err);
return err;
}
/* This is not a user error but the documeted way to cancel async reception in lora api*/
if (cb == NULL) {
goto bail;
}
if (data->is_tx) {
LOG_ERR("radio is configured for tx");
err = -EOPNOTSUPP;
goto bail;
}
data->async_rx_cb = cb;
if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
LOG_ERR("pending async opperation");
err = -EBUSY;
goto bail;
}
RYLR_SET_RX_PENDING(data->pending_async_flags);
return err;
bail:
RYLR_CLEAR_RX_PENDING(data->pending_async_flags);
k_sem_give(&data->operation_sem);
return err;
}
int rylr_test_cw(const struct device *dev, uint32_t frequency, int8_t tx_power, uint16_t duration)
{
return -ENOSYS;
}
static int rylr_init(const struct device *dev)
{
int err = 0;
struct rylr_data *data = dev->data;
const struct rylr_config *config = dev->config;
if (!gpio_is_ready_dt(&config->reset)) {
return -ENODEV;
}
if (!device_is_ready(config->uart)) {
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->reset, config->reset.dt_flags);
if (err != 0) {
LOG_ERR("error configuring reset gpio: %d", err);
return err;
}
k_msgq_init(&data->rx_msgq, data->msgq_buffer, sizeof(struct rylr_recv_msg),
ARRAY_SIZE(data->msgq_buffer));
err = k_sem_init(&data->script_sem, 0, 1);
if (err != 0) {
LOG_ERR("error initializing response semaphore. err=%d", err);
}
err = k_sem_init(&data->operation_sem, 1, 1);
if (err != 0) {
LOG_ERR("error initializing operation semaphore. err=%d", err);
}
const struct modem_backend_uart_config uart_backend_config = {
.uart = config->uart,
.receive_buf = data->uart_backend_rx_buff,
.receive_buf_size = ARRAY_SIZE(data->uart_backend_rx_buff),
.transmit_buf = data->uart_backend_tx_buff,
.transmit_buf_size = ARRAY_SIZE(data->uart_backend_tx_buff),
};
data->uart_pipe = modem_backend_uart_init(&data->uart_backend, &uart_backend_config);
const struct modem_chat_config chat_config = {
.user_data = data,
.receive_buf = data->chat_rx_buf,
.receive_buf_size = ARRAY_SIZE(data->chat_rx_buf),
.delimiter = "\r\n",
.delimiter_size = sizeof("\r\n") - 1,
.filter = NULL,
.filter_size = 0,
.argv = data->chat_argv,
.argv_size = ARRAY_SIZE(data->chat_argv),
.unsol_matches = unsol_matches,
.unsol_matches_size = ARRAY_SIZE(unsol_matches),
};
err = modem_chat_init(&data->chat, &chat_config);
if (err != 0) {
LOG_ERR("error initializing chat %d", err);
return err;
}
err = modem_chat_attach(&data->chat, data->uart_pipe);
if (err != 0) {
LOG_ERR("error attaching chat %d", err);
return err;
}
err = modem_pipe_open(data->uart_pipe, K_SECONDS(10));
if (err != 0) {
LOG_ERR("error opening uart pipe %d", err);
return err;
}
err = gpio_pin_set_dt(&config->reset, 1);
if (err != 0) {
LOG_ERR("error setting reset line: %d", err);
return err;
}
k_sleep(K_MSEC(RYLR_RESET_WAIT_MSECS));
err = gpio_pin_set_dt(&config->reset, 0);
if (err != 0) {
LOG_ERR("error unsetting reset line: %d", err);
return err;
}
k_sleep(K_MSEC(RYLR_RESET_WAIT_MSECS)); /* wait a bit more for module to boot up*/
err = modem_chat_run_script(&data->chat, &ping_script);
if (err != 0) {
LOG_ERR("error pinging radio: %d", err);
return err;
}
err = k_sem_take(&data->script_sem, K_MSEC(CONFIG_RYLRXXX_RADIO_CMD_RESPONSE_TIMEOUT_MS));
if (err != 0) {
LOG_ERR("error waiting for ping response from radio %d", err);
return err;
}
LOG_INF("successfully initialized rylr");
return err;
}
static const struct lora_driver_api rylr_lora_api = {
.config = rylr_config,
.send = rylr_send,
.send_async = rylr_send_async,
.recv = rylr_recv,
.recv_async = rylr_recv_async,
.test_cw = rylr_test_cw,
};
#define RYLR_DEVICE_INIT(n) \
static struct rylr_data dev_data_##n; \
static const struct rylr_config dev_config_##n = { \
.uart = DEVICE_DT_GET(DT_INST_BUS(n)), \
.reset = GPIO_DT_SPEC_INST_GET(n, reset_gpios), \
}; \
DEVICE_DT_INST_DEFINE(n, &rylr_init, NULL, &dev_data_##n, &dev_config_##n, POST_KERNEL, \
CONFIG_LORA_INIT_PRIORITY, &rylr_lora_api);
DT_INST_FOREACH_STATUS_OKAY(RYLR_DEVICE_INIT)
``` | /content/code_sandbox/drivers/lora/rylrxxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,557 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SX12XX_COMMON_H_
#define ZEPHYR_DRIVERS_SX12XX_COMMON_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/device.h>
int __sx12xx_configure_pin(const struct gpio_dt_spec *gpio, gpio_flags_t flags);
#define sx12xx_configure_pin(_name, _flags) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(0, _name##_gpios), \
(__sx12xx_configure_pin(&dev_config._name, _flags)),\
(0))
int sx12xx_lora_send(const struct device *dev, uint8_t *data,
uint32_t data_len);
int sx12xx_lora_send_async(const struct device *dev, uint8_t *data,
uint32_t data_len, struct k_poll_signal *async);
int sx12xx_lora_recv(const struct device *dev, uint8_t *data, uint8_t size,
k_timeout_t timeout, int16_t *rssi, int8_t *snr);
int sx12xx_lora_recv_async(const struct device *dev, lora_recv_cb cb);
int sx12xx_lora_config(const struct device *dev,
struct lora_modem_config *config);
int sx12xx_lora_test_cw(const struct device *dev, uint32_t frequency,
int8_t tx_power,
uint16_t duration);
int sx12xx_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_SX12XX_COMMON_H_ */
``` | /content/code_sandbox/drivers/lora/sx12xx_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 353 |
```c
/*
*
*/
#include <zephyr/drivers/lora.h>
#include <inttypes.h>
#include <zephyr/shell/shell.h>
#include <stdlib.h>
#include <string.h>
LOG_MODULE_REGISTER(lora_shell, CONFIG_LORA_LOG_LEVEL);
#define DEFAULT_RADIO_NODE DT_ALIAS(lora0)
BUILD_ASSERT(DT_NODE_HAS_STATUS(DEFAULT_RADIO_NODE, okay),
"No default LoRa radio specified in DT");
static struct lora_modem_config modem_config = {
.frequency = 0,
.bandwidth = BW_125_KHZ,
.datarate = SF_10,
.coding_rate = CR_4_5,
.preamble_len = 8,
.tx_power = 4,
};
static const int bw_table[] = {
[BW_125_KHZ] = 125,
[BW_250_KHZ] = 250,
[BW_500_KHZ] = 500,
};
static int parse_long(long *out, const struct shell *sh, const char *arg)
{
char *eptr;
long lval;
lval = strtol(arg, &eptr, 0);
if (*eptr != '\0') {
shell_error(sh, "'%s' is not an integer", arg);
return -EINVAL;
}
*out = lval;
return 0;
}
static int parse_long_range(long *out, const struct shell *sh,
const char *arg, const char *name, long min,
long max)
{
int ret;
ret = parse_long(out, sh, arg);
if (ret < 0) {
return ret;
}
if (*out < min || *out > max) {
shell_error(sh, "Parameter '%s' is out of range. "
"Valid range is %li -- %li.",
name, min, max);
return -EINVAL;
}
return 0;
}
static int parse_freq(uint32_t *out, const struct shell *sh, const char *arg)
{
char *eptr;
unsigned long val;
val = strtoul(arg, &eptr, 0);
if (*eptr != '\0') {
shell_error(sh, "Invalid frequency, '%s' is not an integer",
arg);
return -EINVAL;
}
if (val == ULONG_MAX) {
shell_error(sh, "Frequency %s out of range", arg);
return -EINVAL;
}
*out = (uint32_t)val;
return 0;
}
static const struct device *get_modem(const struct shell *sh)
{
const struct device *dev;
dev = DEVICE_DT_GET(DEFAULT_RADIO_NODE);
if (!device_is_ready(dev)) {
shell_error(sh, "LORA Radio device not ready");
return NULL;
}
return dev;
}
static const struct device *get_configured_modem(const struct shell *sh)
{
int ret;
const struct device *dev;
dev = get_modem(sh);
if (!dev) {
return NULL;
}
if (modem_config.frequency == 0) {
shell_error(sh, "No frequency specified.");
return NULL;
}
ret = lora_config(dev, &modem_config);
if (ret < 0) {
shell_error(sh, "LoRa config failed");
return NULL;
}
return dev;
}
static int lora_conf_dump(const struct shell *sh)
{
shell_print(sh, " Frequency: %" PRIu32 " Hz",
modem_config.frequency);
shell_print(sh, " TX power: %" PRIi8 " dBm",
modem_config.tx_power);
shell_print(sh, " Bandwidth: %i kHz",
bw_table[modem_config.bandwidth]);
shell_print(sh, " Spreading factor: SF%i",
(int)modem_config.datarate);
shell_print(sh, " Coding rate: 4/%i",
(int)modem_config.coding_rate + 4);
shell_print(sh, " Preamble length: %" PRIu16,
modem_config.preamble_len);
return 0;
}
static int lora_conf_set(const struct shell *sh, const char *param,
const char *value)
{
long lval;
if (!strcmp("freq", param)) {
if (parse_freq(&modem_config.frequency, sh, value) < 0) {
return -EINVAL;
}
} else if (!strcmp("tx-power", param)) {
if (parse_long_range(&lval, sh, value,
"tx-power", INT8_MIN, INT8_MAX) < 0) {
return -EINVAL;
}
modem_config.tx_power = lval;
} else if (!strcmp("bw", param)) {
if (parse_long_range(&lval, sh, value,
"bw", 0, INT16_MAX) < 0) {
return -EINVAL;
}
switch (lval) {
case 125:
modem_config.bandwidth = BW_125_KHZ;
break;
case 250:
modem_config.bandwidth = BW_250_KHZ;
break;
case 500:
modem_config.bandwidth = BW_500_KHZ;
break;
default:
shell_error(sh, "Invalid bandwidth: %ld", lval);
return -EINVAL;
}
} else if (!strcmp("sf", param)) {
if (parse_long_range(&lval, sh, value, "sf", 6, 12) < 0) {
return -EINVAL;
}
modem_config.datarate = SF_6 + (unsigned int)lval - 6;
} else if (!strcmp("cr", param)) {
if (parse_long_range(&lval, sh, value, "cr", 5, 8) < 0) {
return -EINVAL;
}
modem_config.coding_rate = CR_4_5 + (unsigned int)lval - 5;
} else if (!strcmp("pre-len", param)) {
if (parse_long_range(&lval, sh, value,
"pre-len", 0, UINT16_MAX) < 0) {
return -EINVAL;
}
modem_config.preamble_len = lval;
} else {
shell_error(sh, "Unknown parameter '%s'", param);
return -EINVAL;
}
return 0;
}
static int cmd_lora_conf(const struct shell *sh, size_t argc, char **argv)
{
int i;
int ret;
if (argc < 2) {
return lora_conf_dump(sh);
}
for (i = 1; i < argc; i += 2) {
if (i + 1 >= argc) {
shell_error(sh, "'%s' expects an argument",
argv[i]);
return -EINVAL;
}
ret = lora_conf_set(sh, argv[i], argv[i + 1]);
if (ret != 0) {
return ret;
}
}
return 0;
}
static int cmd_lora_send(const struct shell *sh,
size_t argc, char **argv)
{
int ret;
const struct device *dev;
modem_config.tx = true;
dev = get_configured_modem(sh);
if (!dev) {
return -ENODEV;
}
ret = lora_send(dev, argv[1], strlen(argv[1]));
if (ret < 0) {
shell_error(sh, "LoRa send failed: %i", ret);
return ret;
}
return 0;
}
static int cmd_lora_recv(const struct shell *sh, size_t argc, char **argv)
{
static char buf[0xff];
const struct device *dev;
long timeout = 0;
int ret;
int16_t rssi;
int8_t snr;
modem_config.tx = false;
dev = get_configured_modem(sh);
if (!dev) {
return -ENODEV;
}
if (argc >= 2 && parse_long_range(&timeout, sh, argv[1],
"timeout", 0, INT_MAX) < 0) {
return -EINVAL;
}
ret = lora_recv(dev, buf, sizeof(buf),
timeout ? K_MSEC(timeout) : K_FOREVER, &rssi, &snr);
if (ret < 0) {
shell_error(sh, "LoRa recv failed: %i", ret);
return ret;
}
shell_hexdump(sh, buf, ret);
shell_print(sh, "RSSI: %" PRIi16 " dBm, SNR:%" PRIi8 " dBm",
rssi, snr);
return 0;
}
static int cmd_lora_test_cw(const struct shell *sh,
size_t argc, char **argv)
{
const struct device *dev;
int ret;
uint32_t freq;
long power, duration;
dev = get_modem(sh);
if (!dev) {
return -ENODEV;
}
if (parse_freq(&freq, sh, argv[1]) < 0 ||
parse_long_range(&power, sh, argv[2],
"power", INT8_MIN, INT8_MAX) < 0 ||
parse_long_range(&duration, sh, argv[3],
"duration", 0, UINT16_MAX) < 0) {
return -EINVAL;
}
ret = lora_test_cw(dev, (uint32_t)freq, (int8_t)power, (uint16_t)duration);
if (ret < 0) {
shell_error(sh, "LoRa test CW failed: %i", ret);
return ret;
}
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(sub_lora,
SHELL_CMD(config, NULL,
"Configure the LoRa radio\n"
" Usage: config [freq <Hz>] [tx-power <dBm>] [bw <kHz>] "
"[sf <int>] [cr <int>] [pre-len <int>]\n",
cmd_lora_conf),
SHELL_CMD_ARG(send, NULL,
"Send LoRa packet\n"
" Usage: send <data>",
cmd_lora_send, 2, 0),
SHELL_CMD_ARG(recv, NULL,
"Receive LoRa packet\n"
" Usage: recv [timeout (ms)]",
cmd_lora_recv, 1, 1),
SHELL_CMD_ARG(test_cw, NULL,
"Send a continuous wave\n"
" Usage: test_cw <freq (Hz)> <power (dBm)> <duration (s)>",
cmd_lora_test_cw, 4, 0),
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_CMD_REGISTER(lora, &sub_lora, "LoRa commands", NULL);
``` | /content/code_sandbox/drivers/lora/shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,320 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include "sx126x_common.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(sx126x, CONFIG_LORA_LOG_LEVEL);
static const struct gpio_dt_spec sx126x_gpio_reset = GPIO_DT_SPEC_INST_GET(
0, reset_gpios);
static const struct gpio_dt_spec sx126x_gpio_busy = GPIO_DT_SPEC_INST_GET(
0, busy_gpios);
static const struct gpio_dt_spec sx126x_gpio_dio1 = GPIO_DT_SPEC_INST_GET(
0, dio1_gpios);
void sx126x_reset(struct sx126x_data *dev_data)
{
gpio_pin_set_dt(&sx126x_gpio_reset, 1);
k_sleep(K_MSEC(20));
gpio_pin_set_dt(&sx126x_gpio_reset, 0);
k_sleep(K_MSEC(10));
}
bool sx126x_is_busy(struct sx126x_data *dev_data)
{
return gpio_pin_get_dt(&sx126x_gpio_busy);
}
uint32_t sx126x_get_dio1_pin_state(struct sx126x_data *dev_data)
{
return gpio_pin_get_dt(&sx126x_gpio_dio1) > 0 ? 1U : 0U;
}
void sx126x_dio1_irq_enable(struct sx126x_data *dev_data)
{
gpio_pin_interrupt_configure_dt(&sx126x_gpio_dio1,
GPIO_INT_EDGE_TO_ACTIVE);
}
void sx126x_dio1_irq_disable(struct sx126x_data *dev_data)
{
gpio_pin_interrupt_configure_dt(&sx126x_gpio_dio1,
GPIO_INT_DISABLE);
}
static void sx126x_dio1_irq_callback(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
struct sx126x_data *dev_data = CONTAINER_OF(cb, struct sx126x_data,
dio1_irq_callback);
if (pins & BIT(sx126x_gpio_dio1.pin)) {
k_work_submit(&dev_data->dio1_irq_work);
}
}
void sx126x_set_tx_params(int8_t power, RadioRampTimes_t ramp_time)
{
SX126xSetTxParams(power, ramp_time);
}
int sx126x_variant_init(const struct device *dev)
{
struct sx126x_data *dev_data = dev->data;
if (gpio_pin_configure_dt(&sx126x_gpio_reset, GPIO_OUTPUT_ACTIVE) ||
gpio_pin_configure_dt(&sx126x_gpio_busy, GPIO_INPUT) ||
gpio_pin_configure_dt(&sx126x_gpio_dio1, GPIO_INPUT)) {
LOG_ERR("GPIO configuration failed.");
return -EIO;
}
gpio_init_callback(&dev_data->dio1_irq_callback,
sx126x_dio1_irq_callback, BIT(sx126x_gpio_dio1.pin));
if (gpio_add_callback(sx126x_gpio_dio1.port,
&dev_data->dio1_irq_callback) < 0) {
LOG_ERR("Could not set GPIO callback for DIO1 interrupt.");
return -EIO;
}
return 0;
}
``` | /content/code_sandbox/drivers/lora/sx126x_standalone.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 657 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SX126X_COMMON_H_
#define ZEPHYR_DRIVERS_SX126X_COMMON_H_
#include <zephyr/types.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/drivers/spi.h>
#include <sx126x/sx126x.h>
#include <sx126x-board.h>
#if DT_HAS_COMPAT_STATUS_OKAY(semtech_sx1261)
#define DT_DRV_COMPAT semtech_sx1261
#define SX126X_DEVICE_ID SX1261
#elif DT_HAS_COMPAT_STATUS_OKAY(semtech_sx1262)
#define DT_DRV_COMPAT semtech_sx1262
#define SX126X_DEVICE_ID SX1262
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32wl_subghz_radio)
#define DT_DRV_COMPAT st_stm32wl_subghz_radio
#define SX126X_DEVICE_ID SX1262
#else
#error No SX126x instance in device tree.
#endif
#define HAVE_GPIO_ANTENNA_ENABLE \
DT_INST_NODE_HAS_PROP(0, antenna_enable_gpios)
#define HAVE_GPIO_TX_ENABLE DT_INST_NODE_HAS_PROP(0, tx_enable_gpios)
#define HAVE_GPIO_RX_ENABLE DT_INST_NODE_HAS_PROP(0, rx_enable_gpios)
struct sx126x_config {
struct spi_dt_spec bus;
#if HAVE_GPIO_ANTENNA_ENABLE
struct gpio_dt_spec antenna_enable;
#endif
#if HAVE_GPIO_TX_ENABLE
struct gpio_dt_spec tx_enable;
#endif
#if HAVE_GPIO_RX_ENABLE
struct gpio_dt_spec rx_enable;
#endif
};
struct sx126x_data {
struct gpio_callback dio1_irq_callback;
struct k_work dio1_irq_work;
DioIrqHandler *radio_dio_irq;
RadioOperatingModes_t mode;
};
void sx126x_reset(struct sx126x_data *dev_data);
bool sx126x_is_busy(struct sx126x_data *dev_data);
uint32_t sx126x_get_dio1_pin_state(struct sx126x_data *dev_data);
void sx126x_dio1_irq_enable(struct sx126x_data *dev_data);
void sx126x_dio1_irq_disable(struct sx126x_data *dev_data);
void sx126x_set_tx_params(int8_t power, RadioRampTimes_t ramp_time);
int sx126x_variant_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_SX126X_COMMON_H_ */
``` | /content/code_sandbox/drivers/lora/sx126x_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 510 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/kernel.h>
#include <sx126x/sx126x.h>
#include "sx12xx_common.h"
#include "sx126x_common.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(sx126x, CONFIG_LORA_LOG_LEVEL);
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(semtech_sx1261) +
DT_NUM_INST_STATUS_OKAY(semtech_sx1262) +
DT_NUM_INST_STATUS_OKAY(st_stm32wl_subghz_radio) <= 1,
"Multiple SX126x instances in DT");
#define DIO2_TX_ENABLE DT_INST_PROP(0, dio2_tx_enable)
#define HAVE_DIO3_TCXO DT_INST_NODE_HAS_PROP(0, dio3_tcxo_voltage)
#if HAVE_DIO3_TCXO
#define TCXO_DIO3_VOLTAGE DT_INST_PROP(0, dio3_tcxo_voltage)
#endif
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_startup_delay_ms)
#define TCXO_POWER_STARTUP_DELAY_MS \
DT_INST_PROP(0, tcxo_power_startup_delay_ms)
#else
#define TCXO_POWER_STARTUP_DELAY_MS 0
#endif
#define SX126X_CALIBRATION_ALL 0x7f
static const struct sx126x_config dev_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8) | SPI_TRANSFER_MSB, 0),
#if HAVE_GPIO_ANTENNA_ENABLE
.antenna_enable = GPIO_DT_SPEC_INST_GET(0, antenna_enable_gpios),
#endif
#if HAVE_GPIO_TX_ENABLE
.tx_enable = GPIO_DT_SPEC_INST_GET(0, tx_enable_gpios),
#endif
#if HAVE_GPIO_RX_ENABLE
.rx_enable = GPIO_DT_SPEC_INST_GET(0, rx_enable_gpios),
#endif
};
static struct sx126x_data dev_data;
void SX126xWaitOnBusy(void);
#define MODE(m) [MODE_##m] = #m
static const char *const mode_names[] = {
MODE(SLEEP),
MODE(STDBY_RC),
MODE(STDBY_XOSC),
MODE(FS),
MODE(TX),
MODE(RX),
MODE(RX_DC),
MODE(CAD),
};
#undef MODE
static const char *sx126x_mode_name(RadioOperatingModes_t m)
{
static const char *unknown_mode = "unknown";
if (m < ARRAY_SIZE(mode_names) && mode_names[m]) {
return mode_names[m];
} else {
return unknown_mode;
}
}
static int sx126x_spi_transceive(uint8_t *req_tx, uint8_t *req_rx,
size_t req_len, void *data_tx, void *data_rx,
size_t data_len)
{
int ret;
const struct spi_buf tx_buf[] = {
{
.buf = req_tx,
.len = req_len,
},
{
.buf = data_tx,
.len = data_len
}
};
const struct spi_buf rx_buf[] = {
{
.buf = req_rx,
.len = req_len,
},
{
.buf = data_rx,
.len = data_len
}
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf)
};
/* Wake the device if necessary */
SX126xCheckDeviceReady();
if (!req_rx && !data_rx) {
ret = spi_write_dt(&dev_config.bus, &tx);
} else {
ret = spi_transceive_dt(&dev_config.bus, &tx, &rx);
}
if (ret < 0) {
LOG_ERR("SPI transaction failed: %i", ret);
}
if (req_len >= 1 && req_tx[0] != RADIO_SET_SLEEP) {
SX126xWaitOnBusy();
}
return ret;
}
uint8_t SX126xReadRegister(uint16_t address)
{
uint8_t data;
SX126xReadRegisters(address, &data, 1);
return data;
}
void SX126xReadRegisters(uint16_t address, uint8_t *buffer, uint16_t size)
{
uint8_t req[] = {
RADIO_READ_REGISTER,
(address >> 8) & 0xff,
address & 0xff,
0,
};
LOG_DBG("Reading %" PRIu16 " registers @ 0x%" PRIx16, size, address);
sx126x_spi_transceive(req, NULL, sizeof(req), NULL, buffer, size);
LOG_HEXDUMP_DBG(buffer, size, "register_value");
}
void SX126xWriteRegister(uint16_t address, uint8_t value)
{
SX126xWriteRegisters(address, &value, 1);
}
void SX126xWriteRegisters(uint16_t address, uint8_t *buffer, uint16_t size)
{
uint8_t req[] = {
RADIO_WRITE_REGISTER,
(address >> 8) & 0xff,
address & 0xff,
};
LOG_DBG("Writing %" PRIu16 " registers @ 0x%" PRIx16
": 0x%" PRIx8 " , ...",
size, address, buffer[0]);
sx126x_spi_transceive(req, NULL, sizeof(req), buffer, NULL, size);
}
uint8_t SX126xReadCommand(RadioCommands_t opcode,
uint8_t *buffer, uint16_t size)
{
uint8_t tx_req[] = {
opcode,
0x00,
};
uint8_t rx_req[sizeof(tx_req)];
LOG_DBG("Issuing opcode 0x%x (data size: %" PRIx16 ")",
opcode, size);
sx126x_spi_transceive(tx_req, rx_req, sizeof(rx_req),
NULL, buffer, size);
LOG_DBG("-> status: 0x%" PRIx8, rx_req[1]);
return rx_req[1];
}
void SX126xWriteCommand(RadioCommands_t opcode, uint8_t *buffer, uint16_t size)
{
uint8_t req[] = {
opcode,
};
LOG_DBG("Issuing opcode 0x%x w. %" PRIu16 " bytes of data",
opcode, size);
sx126x_spi_transceive(req, NULL, sizeof(req), buffer, NULL, size);
}
void SX126xReadBuffer(uint8_t offset, uint8_t *buffer, uint8_t size)
{
uint8_t req[] = {
RADIO_READ_BUFFER,
offset,
0x00,
};
LOG_DBG("Reading buffers @ 0x%" PRIx8 " (%" PRIu8 " bytes)",
offset, size);
sx126x_spi_transceive(req, NULL, sizeof(req), NULL, buffer, size);
}
void SX126xWriteBuffer(uint8_t offset, uint8_t *buffer, uint8_t size)
{
uint8_t req[] = {
RADIO_WRITE_BUFFER,
offset,
};
LOG_DBG("Writing buffers @ 0x%" PRIx8 " (%" PRIu8 " bytes)",
offset, size);
sx126x_spi_transceive(req, NULL, sizeof(req), buffer, NULL, size);
}
void SX126xAntSwOn(void)
{
#if HAVE_GPIO_ANTENNA_ENABLE
LOG_DBG("Enabling antenna switch");
gpio_pin_set_dt(&dev_config.antenna_enable, 1);
#else
LOG_DBG("No antenna switch configured");
#endif
}
void SX126xAntSwOff(void)
{
#if HAVE_GPIO_ANTENNA_ENABLE
LOG_DBG("Disabling antenna switch");
gpio_pin_set_dt(&dev_config.antenna_enable, 0);
#else
LOG_DBG("No antenna switch configured");
#endif
}
static void sx126x_set_tx_enable(int value)
{
#if HAVE_GPIO_TX_ENABLE
gpio_pin_set_dt(&dev_config.tx_enable, value);
#endif
}
static void sx126x_set_rx_enable(int value)
{
#if HAVE_GPIO_RX_ENABLE
gpio_pin_set_dt(&dev_config.rx_enable, value);
#endif
}
RadioOperatingModes_t SX126xGetOperatingMode(void)
{
return dev_data.mode;
}
void SX126xSetOperatingMode(RadioOperatingModes_t mode)
{
LOG_DBG("SetOperatingMode: %s (%i)", sx126x_mode_name(mode), mode);
dev_data.mode = mode;
/* To avoid inadvertently putting the RF switch in an
* undefined state, first disable the port we don't want to
* use and then enable the other one.
*/
switch (mode) {
case MODE_TX:
sx126x_set_rx_enable(0);
sx126x_set_tx_enable(1);
break;
case MODE_RX:
case MODE_RX_DC:
case MODE_CAD:
sx126x_set_tx_enable(0);
sx126x_set_rx_enable(1);
break;
case MODE_SLEEP:
/* Additionally disable the DIO1 interrupt to save power */
sx126x_dio1_irq_disable(&dev_data);
__fallthrough;
default:
sx126x_set_rx_enable(0);
sx126x_set_tx_enable(0);
break;
}
}
uint32_t SX126xGetBoardTcxoWakeupTime(void)
{
return TCXO_POWER_STARTUP_DELAY_MS;
}
uint8_t SX126xGetDeviceId(void)
{
return SX126X_DEVICE_ID;
}
void SX126xIoIrqInit(DioIrqHandler dioIrq)
{
LOG_DBG("Configuring DIO IRQ callback");
dev_data.radio_dio_irq = dioIrq;
}
void SX126xIoTcxoInit(void)
{
#if HAVE_DIO3_TCXO
CalibrationParams_t cal = {
.Value = SX126X_CALIBRATION_ALL,
};
LOG_DBG("TCXO on DIO3");
/* Delay in units of 15.625 us (1/64 ms) */
SX126xSetDio3AsTcxoCtrl(TCXO_DIO3_VOLTAGE,
TCXO_POWER_STARTUP_DELAY_MS << 6);
SX126xCalibrate(cal);
#else
LOG_DBG("No TCXO configured");
#endif
}
void SX126xIoRfSwitchInit(void)
{
LOG_DBG("Configuring DIO2");
SX126xSetDio2AsRfSwitchCtrl(DIO2_TX_ENABLE);
}
void SX126xReset(void)
{
LOG_DBG("Resetting radio");
sx126x_reset(&dev_data);
/* Device transitions to standby on reset */
dev_data.mode = MODE_STDBY_RC;
}
void SX126xSetRfTxPower(int8_t power)
{
LOG_DBG("power: %" PRIi8, power);
sx126x_set_tx_params(power, RADIO_RAMP_40_US);
}
void SX126xWaitOnBusy(void)
{
while (sx126x_is_busy(&dev_data)) {
k_sleep(K_MSEC(1));
}
}
void SX126xWakeup(void)
{
int ret;
/* Reenable DIO1 when waking up */
sx126x_dio1_irq_enable(&dev_data);
uint8_t req[] = { RADIO_GET_STATUS, 0 };
const struct spi_buf tx_buf = {
.buf = req,
.len = sizeof(req),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
LOG_DBG("Sending GET_STATUS");
ret = spi_write_dt(&dev_config.bus, &tx);
if (ret < 0) {
LOG_ERR("SPI transaction failed: %i", ret);
return;
}
LOG_DBG("Waiting for device...");
SX126xWaitOnBusy();
LOG_DBG("Device ready");
/* This function is only called from sleep mode
* All edges on the SS SPI pin will transition the modem to
* standby mode (via startup)
*/
dev_data.mode = MODE_STDBY_RC;
}
uint32_t SX126xGetDio1PinState(void)
{
return sx126x_get_dio1_pin_state(&dev_data);
}
static void sx126x_dio1_irq_work_handler(struct k_work *work)
{
LOG_DBG("Processing DIO1 interrupt");
if (!dev_data.radio_dio_irq) {
LOG_WRN("DIO1 interrupt without valid HAL IRQ callback.");
return;
}
dev_data.radio_dio_irq(NULL);
if (Radio.IrqProcess) {
Radio.IrqProcess();
}
/* Re-enable the interrupt if we are not in sleep mode */
if (dev_data.mode != MODE_SLEEP) {
sx126x_dio1_irq_enable(&dev_data);
}
}
static int sx126x_lora_init(const struct device *dev)
{
const struct sx126x_config *config = dev->config;
int ret;
LOG_DBG("Initializing sx126x");
if (sx12xx_configure_pin(antenna_enable, GPIO_OUTPUT_INACTIVE) ||
sx12xx_configure_pin(rx_enable, GPIO_OUTPUT_INACTIVE) ||
sx12xx_configure_pin(tx_enable, GPIO_OUTPUT_INACTIVE)) {
return -EIO;
}
k_work_init(&dev_data.dio1_irq_work, sx126x_dio1_irq_work_handler);
ret = sx126x_variant_init(dev);
if (ret) {
LOG_ERR("Variant initialization failed");
return ret;
}
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
ret = sx12xx_init(dev);
if (ret < 0) {
LOG_ERR("Failed to initialize SX12xx common");
return ret;
}
return 0;
}
static const struct lora_driver_api sx126x_lora_api = {
.config = sx12xx_lora_config,
.send = sx12xx_lora_send,
.send_async = sx12xx_lora_send_async,
.recv = sx12xx_lora_recv,
.recv_async = sx12xx_lora_recv_async,
.test_cw = sx12xx_lora_test_cw,
};
DEVICE_DT_INST_DEFINE(0, &sx126x_lora_init, NULL, &dev_data,
&dev_config, POST_KERNEL, CONFIG_LORA_INIT_PRIORITY,
&sx126x_lora_api);
``` | /content/code_sandbox/drivers/lora/sx126x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,102 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <timer.h>
static void timer_work_handler(struct k_work *work);
K_WORK_DEFINE(timer_work, timer_work_handler);
static uint32_t saved_time;
/* TODO: Use Non-volatile memory for backup */
static volatile uint32_t backup_reg[2];
static void timer_work_handler(struct k_work *work)
{
TimerIrqHandler();
}
static void timer_callback(struct k_timer *_timer)
{
ARG_UNUSED(_timer);
k_work_submit(&timer_work);
}
K_TIMER_DEFINE(lora_timer, timer_callback, NULL);
void RtcBkupWrite(uint32_t data0, uint32_t data1)
{
backup_reg[0] = data0;
backup_reg[1] = data1;
}
void RtcBkupRead(uint32_t *data0, uint32_t *data1)
{
*data0 = backup_reg[0];
*data1 = backup_reg[1];
}
uint32_t RtcGetCalendarTime(uint16_t *milliseconds)
{
int64_t now = k_uptime_get();
*milliseconds = now % MSEC_PER_SEC;
/* Return in seconds */
return now / MSEC_PER_SEC;
}
uint32_t RtcGetTimerValue(void)
{
return k_uptime_get_32();
}
uint32_t RtcGetTimerElapsedTime(void)
{
return (k_uptime_get_32() - saved_time);
}
uint32_t RtcGetMinimumTimeout(void)
{
return 1;
}
void RtcStopAlarm(void)
{
k_timer_stop(&lora_timer);
}
void RtcSetAlarm(uint32_t timeout)
{
k_timer_start(&lora_timer, K_MSEC(timeout), K_NO_WAIT);
}
uint32_t RtcSetTimerContext(void)
{
saved_time = k_uptime_get_32();
return saved_time;
}
/* For us, 1 tick = 1 milli second. So no need to do any conversion here */
uint32_t RtcGetTimerContext(void)
{
return saved_time;
}
void DelayMsMcu(uint32_t ms)
{
k_sleep(K_MSEC(ms));
}
uint32_t RtcMs2Tick(uint32_t milliseconds)
{
return milliseconds;
}
uint32_t RtcTick2Ms(uint32_t tick)
{
return tick;
}
void BoardCriticalSectionBegin(uint32_t *mask)
{
*mask = irq_lock();
}
void BoardCriticalSectionEnd(uint32_t *mask)
{
irq_unlock(*mask);
}
``` | /content/code_sandbox/drivers/lora/hal_common.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 519 |
```unknown
#
#
#
# Top-level configuration file for LORA drivers.
menuconfig LORA
bool "LoRa drivers [EXPERIMENTAL]"
select POLL
select EXPERIMENTAL
help
Include LoRa drivers in the system configuration.
if LORA
module = LORA
module-str = lora
source "subsys/logging/Kconfig.template.log_config"
config LORA_SHELL
bool "LoRa Shell"
depends on SHELL
help
Enable LoRa Shell for testing.
config LORA_INIT_PRIORITY
int "LoRa initialization priority"
default 90
help
System initialization priority for LoRa drivers.
source "drivers/lora/Kconfig.sx12xx"
source "drivers/lora/Kconfig.rylrxxx"
endif # LORA
``` | /content/code_sandbox/drivers/lora/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 161 |
```unknown
#
#
#
config LORA_RYLRXXX
bool "Reyax LYLR driver"
depends on DT_HAS_REYAX_RYLRXXX_ENABLED
select MODEM_MODULES
select MODEM_CHAT
select MODEM_PIPE
select MODEM_BACKEND_UART
select GPIO
help
Enable the Reyax LYLR driver
if LORA_RYLRXXX
config LORA_RYLRXX_CMD_BUF_SIZE
int "cmd buffer size"
default 256
help
Configure the cmd buffer size
config RYLRXXX_UNSOLICITED_RX_MSGQ_SIZE
int "number of message to store in message queue"
default 1
help
Configure the size of message queue
config RYLRXXX_RADIO_CMD_RESPONSE_TIMEOUT_MS
int "timeout when waiting for response from radio serial interface after send cmd"
default 500
help
Configure the number of milliseconds before timing out when waiting for acknowledgment from radio after sending cmd
config RYLRXXX_MODEM_BUFFERS_SIZE
int "size of buffers for modem library"
default 512
help
Configure the size of buffers for modem library
endif # LORA_RYLRXXX
``` | /content/code_sandbox/drivers/lora/Kconfig.rylrxxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 243 |
```unknown
#
#
#
config LORA_SX127X
bool "Semtech SX127x driver"
default y
depends on DT_HAS_SEMTECH_SX1272_ENABLED || DT_HAS_SEMTECH_SX1276_ENABLED
select HAS_SEMTECH_SX1272 if DT_HAS_SEMTECH_SX1272_ENABLED
select HAS_SEMTECH_SX1276 if DT_HAS_SEMTECH_SX1276_ENABLED
depends on SPI
help
Enable LoRa driver for Semtech SX1272 and SX1276.
config LORA_SX126X
bool "Semtech SX126x driver"
default y
depends on DT_HAS_SEMTECH_SX1261_ENABLED || DT_HAS_SEMTECH_SX1262_ENABLED
select HAS_SEMTECH_SX126X
depends on SPI
help
Enable LoRa driver for Semtech SX1261 and SX1262.
config LORA_STM32WL_SUBGHZ_RADIO
bool "STM32WL SUBGHZ radio driver"
default y
depends on DT_HAS_ST_STM32WL_SUBGHZ_RADIO_ENABLED
select HAS_SEMTECH_SX126X
depends on SPI
help
Enable LoRa driver for STM32WL SUBGHZ radio.
``` | /content/code_sandbox/drivers/lora/Kconfig.sx12xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 275 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_id
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
struct sam0_uid {
uint32_t id[4];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct sam0_uid dev_id;
dev_id.id[0] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 0));
dev_id.id[1] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 1));
dev_id.id[2] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 2));
dev_id.id[3] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 3));
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
struct numaker_uid {
uint32_t id[3];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct numaker_uid dev_id;
SYS_UnlockReg();
RMC_Open();
dev_id.id[0] = sys_cpu_to_be32(RMC_ReadUID(0));
dev_id.id[1] = sys_cpu_to_be32(RMC_ReadUID(1));
dev_id.id[2] = sys_cpu_to_be32(RMC_ReadUID(2));
length = MIN(length, sizeof(dev_id.id));
memcpy(buffer, dev_id.id, length);
RMC_Close();
SYS_LockReg();
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_numaker_rmc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 176 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam4l_uid
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/init.h>
#include <soc.h>
#include <string.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint8_t *uid_addr = (uint8_t *) DT_INST_REG_ADDR(0);
if (buffer == NULL) {
return 0;
}
if (length > DT_INST_REG_SIZE(0)) {
length = DT_INST_REG_SIZE(0);
}
memcpy(buffer, uid_addr, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_sam4l.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 142 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/lora.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/kernel.h>
#include "sx12xx_common.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(sx127x, CONFIG_LORA_LOG_LEVEL);
#if DT_HAS_COMPAT_STATUS_OKAY(semtech_sx1272)
#include <sx1272/sx1272.h>
#define DT_DRV_COMPAT semtech_sx1272
#define SX127xCheckRfFrequency SX1272CheckRfFrequency
#define SX127xGetBoardTcxoWakeupTime SX1272GetBoardTcxoWakeupTime
#define SX127xSetAntSwLowPower SX1272SetAntSwLowPower
#define SX127xSetBoardTcxo SX1272SetBoardTcxo
#define SX127xSetAntSw SX1272SetAntSw
#define SX127xReset SX1272Reset
#define SX127xIoIrqInit SX1272IoIrqInit
#define SX127xWriteBuffer SX1272WriteBuffer
#define SX127xReadBuffer SX1272ReadBuffer
#define SX127xSetRfTxPower SX1272SetRfTxPower
#define SX127xGetDio1PinState SX1272GetDio1PinState
#define SX127xInit SX1272Init
#define SX127xGetStatus SX1272GetStatus
#define SX127xSetModem SX1272SetModem
#define SX127xSetChannel SX1272SetChannel
#define SX127xIsChannelFree SX1272IsChannelFree
#define SX127xRandom SX1272Random
#define SX127xSetRxConfig SX1272SetRxConfig
#define SX127xSetTxConfig SX1272SetTxConfig
#define SX127xGetTimeOnAir SX1272GetTimeOnAir
#define SX127xSend SX1272Send
#define SX127xSetSleep SX1272SetSleep
#define SX127xSetStby SX1272SetStby
#define SX127xSetRx SX1272SetRx
#define SX127xWrite SX1272Write
#define SX127xRead SX1272Read
#define SX127xSetMaxPayloadLength SX1272SetMaxPayloadLength
#define SX127xSetPublicNetwork SX1272SetPublicNetwork
#define SX127xGetWakeupTime SX1272GetWakeupTime
#define SX127xSetTxContinuousWave SX1272SetTxContinuousWave
#elif DT_HAS_COMPAT_STATUS_OKAY(semtech_sx1276)
#include <sx1276/sx1276.h>
#define DT_DRV_COMPAT semtech_sx1276
#define SX127xCheckRfFrequency SX1276CheckRfFrequency
#define SX127xGetBoardTcxoWakeupTime SX1276GetBoardTcxoWakeupTime
#define SX127xSetAntSwLowPower SX1276SetAntSwLowPower
#define SX127xSetBoardTcxo SX1276SetBoardTcxo
#define SX127xSetAntSw SX1276SetAntSw
#define SX127xReset SX1276Reset
#define SX127xIoIrqInit SX1276IoIrqInit
#define SX127xWriteBuffer SX1276WriteBuffer
#define SX127xReadBuffer SX1276ReadBuffer
#define SX127xSetRfTxPower SX1276SetRfTxPower
#define SX127xGetDio1PinState SX1276GetDio1PinState
#define SX127xInit SX1276Init
#define SX127xGetStatus SX1276GetStatus
#define SX127xSetModem SX1276SetModem
#define SX127xSetChannel SX1276SetChannel
#define SX127xIsChannelFree SX1276IsChannelFree
#define SX127xRandom SX1276Random
#define SX127xSetRxConfig SX1276SetRxConfig
#define SX127xSetTxConfig SX1276SetTxConfig
#define SX127xGetTimeOnAir SX1276GetTimeOnAir
#define SX127xSend SX1276Send
#define SX127xSetSleep SX1276SetSleep
#define SX127xSetStby SX1276SetStby
#define SX127xSetRx SX1276SetRx
#define SX127xWrite SX1276Write
#define SX127xRead SX1276Read
#define SX127xSetMaxPayloadLength SX1276SetMaxPayloadLength
#define SX127xSetPublicNetwork SX1276SetPublicNetwork
#define SX127xGetWakeupTime SX1276GetWakeupTime
#define SX127xSetTxContinuousWave SX1276SetTxContinuousWave
#else
#error No SX127x instance in device tree.
#endif
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(semtech_sx1272) +
DT_NUM_INST_STATUS_OKAY(semtech_sx1276) <= 1,
"Multiple SX127x instances in DT");
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_startup_delay_ms)
#define TCXO_POWER_STARTUP_DELAY_MS \
DT_INST_PROP(0, tcxo_power_startup_delay_ms)
#else
#define TCXO_POWER_STARTUP_DELAY_MS 0
#endif
/*
* Those macros must be in sync with 'power-amplifier-output' dts property.
*/
#define SX127X_PA_RFO 0
#define SX127X_PA_BOOST 1
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios) && \
DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
#define SX127X_PA_OUTPUT(power) \
((power) > 14 ? SX127X_PA_BOOST : SX127X_PA_RFO)
#elif DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios)
#define SX127X_PA_OUTPUT(power) SX127X_PA_RFO
#elif DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
#define SX127X_PA_OUTPUT(power) SX127X_PA_BOOST
#elif DT_INST_NODE_HAS_PROP(0, power_amplifier_output)
#define SX127X_PA_OUTPUT(power) \
DT_INST_ENUM_IDX(0, power_amplifier_output)
#else
BUILD_ASSERT(0, "None of rfo-enable-gpios, pa-boost-enable-gpios and "
"power-amplifier-output has been specified. "
"Look at semtech,sx127x-base.yaml to fix that.");
#endif
#define SX127X_PADAC_20DBM_ON (RF_PADAC_20DBM_ON)
#define SX127X_PADAC_20DBM_OFF (RF_PADAC_20DBM_OFF)
#define SX127X_PADAC_20DBM_MASK (~RF_PADAC_20DBM_MASK)
#define SX127X_PACONFIG_PASELECT_PABOOST (RF_PACONFIG_PASELECT_PABOOST)
#define SX127X_PACONFIG_OUTPUTPOWER_MASK (~RF_PACONFIG_OUTPUTPOWER_MASK)
#ifdef RF_PACONFIG_MAX_POWER_MASK
#define SX127X_PACONFIG_MAX_POWER_SHIFT 4
#endif
extern DioIrqHandler *DioIrq[];
/* Helper macro that UTIL_LISTIFY can use and produces an element with comma */
#define SX127X_DIO_GPIO_LEN(inst) \
DT_INST_PROP_LEN(inst, dio_gpios)
#define SX127X_DIO_GPIO_ELEM(idx, inst) \
GPIO_DT_SPEC_INST_GET_BY_IDX(inst, dio_gpios, idx)
#define SX127X_DIO_GPIO_INIT(n) \
LISTIFY(SX127X_DIO_GPIO_LEN(n), SX127X_DIO_GPIO_ELEM, (,), n)
static const struct gpio_dt_spec sx127x_dios[] = { SX127X_DIO_GPIO_INIT(0) };
#define SX127X_MAX_DIO ARRAY_SIZE(sx127x_dios)
struct sx127x_config {
struct spi_dt_spec bus;
struct gpio_dt_spec reset;
#if DT_INST_NODE_HAS_PROP(0, antenna_enable_gpios)
struct gpio_dt_spec antenna_enable;
#endif
#if DT_INST_NODE_HAS_PROP(0, rfi_enable_gpios)
struct gpio_dt_spec rfi_enable;
#endif
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios)
struct gpio_dt_spec rfo_enable;
#endif
#if DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
struct gpio_dt_spec pa_boost_enable;
#endif
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_gpios)
struct gpio_dt_spec tcxo_power;
#endif
};
static const struct sx127x_config dev_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8) | SPI_TRANSFER_MSB, 0),
.reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
#if DT_INST_NODE_HAS_PROP(0, antenna_enable_gpios)
.antenna_enable = GPIO_DT_SPEC_INST_GET(0, antenna_enable_gpios),
#endif
#if DT_INST_NODE_HAS_PROP(0, rfi_enable_gpios)
.rfi_enable = GPIO_DT_SPEC_INST_GET(0, rfi_enable_gpios),
#endif
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios)
.rfo_enable = GPIO_DT_SPEC_INST_GET(0, rfo_enable_gpios),
#endif
#if DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
.pa_boost_enable = GPIO_DT_SPEC_INST_GET(0, pa_boost_enable_gpios),
#endif
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_gpios)
.tcxo_power = GPIO_DT_SPEC_INST_GET(0, tcxo_power_gpios),
#endif
};
static struct sx127x_data {
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios) && \
DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
uint8_t tx_power;
#endif
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_gpios)
bool tcxo_power_enabled;
#endif
struct k_work dio_work[SX127X_MAX_DIO];
} dev_data;
static int8_t clamp_int8(int8_t x, int8_t min, int8_t max)
{
if (x < min) {
return min;
} else if (x > max) {
return max;
} else {
return x;
}
}
bool SX127xCheckRfFrequency(uint32_t frequency)
{
/* TODO */
return true;
}
uint32_t SX127xGetBoardTcxoWakeupTime(void)
{
return TCXO_POWER_STARTUP_DELAY_MS;
}
static inline void sx127x_antenna_enable(int val)
{
#if DT_INST_NODE_HAS_PROP(0, antenna_enable_gpios)
gpio_pin_set_dt(&dev_config.antenna_enable, val);
#endif
}
static inline void sx127x_rfi_enable(int val)
{
#if DT_INST_NODE_HAS_PROP(0, rfi_enable_gpios)
gpio_pin_set_dt(&dev_config.rfi_enable, val);
#endif
}
static inline void sx127x_rfo_enable(int val)
{
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios)
gpio_pin_set_dt(&dev_config.rfo_enable, val);
#endif
}
static inline void sx127x_pa_boost_enable(int val)
{
#if DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
gpio_pin_set_dt(&dev_config.pa_boost_enable, val);
#endif
}
void SX127xSetAntSwLowPower(bool low_power)
{
if (low_power) {
/* force inactive (low power) state of all antenna paths */
sx127x_rfi_enable(0);
sx127x_rfo_enable(0);
sx127x_pa_boost_enable(0);
sx127x_antenna_enable(0);
} else {
sx127x_antenna_enable(1);
/* rely on SX127xSetAntSw() to configure proper antenna path */
}
}
void SX127xSetBoardTcxo(uint8_t state)
{
#if DT_INST_NODE_HAS_PROP(0, tcxo_power_gpios)
bool enable = state;
if (enable == dev_data.tcxo_power_enabled) {
return;
}
if (enable) {
gpio_pin_set_dt(&dev_config.tcxo_power, 1);
if (TCXO_POWER_STARTUP_DELAY_MS > 0) {
k_sleep(K_MSEC(TCXO_POWER_STARTUP_DELAY_MS));
}
} else {
gpio_pin_set_dt(&dev_config.tcxo_power, 0);
}
dev_data.tcxo_power_enabled = enable;
#endif
}
void SX127xSetAntSw(uint8_t opMode)
{
switch (opMode) {
case RFLR_OPMODE_TRANSMITTER:
sx127x_rfi_enable(0);
if (SX127X_PA_OUTPUT(dev_data.tx_power) == SX127X_PA_BOOST) {
sx127x_rfo_enable(0);
sx127x_pa_boost_enable(1);
} else {
sx127x_pa_boost_enable(0);
sx127x_rfo_enable(1);
}
break;
default:
sx127x_rfo_enable(0);
sx127x_pa_boost_enable(0);
sx127x_rfi_enable(1);
break;
}
}
void SX127xReset(void)
{
SX127xSetBoardTcxo(true);
gpio_pin_set_dt(&dev_config.reset, 1);
k_sleep(K_MSEC(1));
gpio_pin_set_dt(&dev_config.reset, 0);
k_sleep(K_MSEC(6));
}
static void sx127x_dio_work_handle(struct k_work *work)
{
int dio = work - dev_data.dio_work;
(*DioIrq[dio])(NULL);
}
static void sx127x_irq_callback(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
unsigned int i, pin;
pin = find_lsb_set(pins) - 1;
for (i = 0; i < SX127X_MAX_DIO; i++) {
if (dev == sx127x_dios[i].port &&
pin == sx127x_dios[i].pin) {
k_work_submit(&dev_data.dio_work[i]);
}
}
}
void SX127xIoIrqInit(DioIrqHandler **irqHandlers)
{
unsigned int i;
static struct gpio_callback callbacks[SX127X_MAX_DIO];
/* Setup DIO gpios */
for (i = 0; i < SX127X_MAX_DIO; i++) {
if (!irqHandlers[i]) {
continue;
}
if (!gpio_is_ready_dt(&sx127x_dios[i])) {
LOG_ERR("GPIO port %s not ready",
sx127x_dios[i].port->name);
return;
}
k_work_init(&dev_data.dio_work[i], sx127x_dio_work_handle);
gpio_pin_configure_dt(&sx127x_dios[i], GPIO_INPUT);
gpio_init_callback(&callbacks[i],
sx127x_irq_callback,
BIT(sx127x_dios[i].pin));
if (gpio_add_callback(sx127x_dios[i].port, &callbacks[i]) < 0) {
LOG_ERR("Could not set gpio callback.");
return;
}
gpio_pin_interrupt_configure_dt(&sx127x_dios[i],
GPIO_INT_EDGE_TO_ACTIVE);
}
}
static int sx127x_transceive(uint8_t reg, bool write, void *data, size_t length)
{
const struct spi_buf buf[2] = {
{
.buf = ®,
.len = sizeof(reg)
},
{
.buf = data,
.len = length
}
};
struct spi_buf_set tx = {
.buffers = buf,
.count = ARRAY_SIZE(buf),
};
if (!write) {
const struct spi_buf_set rx = {
.buffers = buf,
.count = ARRAY_SIZE(buf)
};
return spi_transceive_dt(&dev_config.bus, &tx, &rx);
}
return spi_write_dt(&dev_config.bus, &tx);
}
int sx127x_read(uint8_t reg_addr, uint8_t *data, uint8_t len)
{
return sx127x_transceive(reg_addr, false, data, len);
}
int sx127x_write(uint8_t reg_addr, uint8_t *data, uint8_t len)
{
return sx127x_transceive(reg_addr | BIT(7), true, data, len);
}
void SX127xWriteBuffer(uint32_t addr, uint8_t *buffer, uint8_t size)
{
int ret;
ret = sx127x_write(addr, buffer, size);
if (ret < 0) {
LOG_ERR("Unable to write address: 0x%x", addr);
}
}
void SX127xReadBuffer(uint32_t addr, uint8_t *buffer, uint8_t size)
{
int ret;
ret = sx127x_read(addr, buffer, size);
if (ret < 0) {
LOG_ERR("Unable to read address: 0x%x", addr);
}
}
void SX127xSetRfTxPower(int8_t power)
{
int ret;
uint8_t pa_config = 0;
uint8_t pa_dac = 0;
ret = sx127x_read(REG_PADAC, &pa_dac, 1);
if (ret < 0) {
LOG_ERR("Unable to read PA dac");
return;
}
pa_dac &= ~SX127X_PADAC_20DBM_MASK;
if (SX127X_PA_OUTPUT(power) == SX127X_PA_BOOST) {
power = clamp_int8(power, 2, 20);
pa_config |= SX127X_PACONFIG_PASELECT_PABOOST;
if (power > 17) {
pa_dac |= SX127X_PADAC_20DBM_ON;
pa_config |= (power - 5) & SX127X_PACONFIG_OUTPUTPOWER_MASK;
} else {
pa_dac |= SX127X_PADAC_20DBM_OFF;
pa_config |= (power - 2) & SX127X_PACONFIG_OUTPUTPOWER_MASK;
}
} else {
#ifdef SX127X_PACONFIG_MAX_POWER_SHIFT
power = clamp_int8(power, -4, 15);
pa_dac |= SX127X_PADAC_20DBM_OFF;
if (power > 0) {
/* Set the power range to 0 -- 10.8+0.6*7 dBm */
pa_config |= 7 << SX127X_PACONFIG_MAX_POWER_SHIFT;
pa_config |= power & SX127X_PACONFIG_OUTPUTPOWER_MASK;
} else {
/* Set the power range to -4.2 -- 10.8+0.6*0 dBm */
pa_config |= (power + 4) & SX127X_PACONFIG_OUTPUTPOWER_MASK;
}
#else
power = clamp_int8(power, -1, 14);
pa_dac |= SX127X_PADAC_20DBM_OFF;
pa_config |= (power + 1) & SX127X_PACONFIG_OUTPUTPOWER_MASK;
#endif
}
#if DT_INST_NODE_HAS_PROP(0, rfo_enable_gpios) && \
DT_INST_NODE_HAS_PROP(0, pa_boost_enable_gpios)
dev_data.tx_power = power;
#endif
ret = sx127x_write(REG_PACONFIG, &pa_config, 1);
if (ret < 0) {
LOG_ERR("Unable to write PA config");
return;
}
ret = sx127x_write(REG_PADAC, &pa_dac, 1);
if (ret < 0) {
LOG_ERR("Unable to write PA dac");
return;
}
}
uint32_t SX127xGetDio1PinState(void)
{
#if SX127X_DIO_GPIO_LEN(0) >= 2
if (gpio_pin_get_dt(&sx127x_dios[1]) > 0) {
return 1U;
}
#endif
return 0U;
}
/* Initialize Radio driver callbacks */
const struct Radio_s Radio = {
.Init = SX127xInit,
.GetStatus = SX127xGetStatus,
.SetModem = SX127xSetModem,
.SetChannel = SX127xSetChannel,
.IsChannelFree = SX127xIsChannelFree,
.Random = SX127xRandom,
.SetRxConfig = SX127xSetRxConfig,
.SetTxConfig = SX127xSetTxConfig,
.CheckRfFrequency = SX127xCheckRfFrequency,
.TimeOnAir = SX127xGetTimeOnAir,
.Send = SX127xSend,
.Sleep = SX127xSetSleep,
.Standby = SX127xSetStby,
.Rx = SX127xSetRx,
.Write = SX127xWrite,
.Read = SX127xRead,
.WriteBuffer = SX127xWriteBuffer,
.ReadBuffer = SX127xReadBuffer,
.SetMaxPayloadLength = SX127xSetMaxPayloadLength,
.SetPublicNetwork = SX127xSetPublicNetwork,
.GetWakeupTime = SX127xGetWakeupTime,
.IrqProcess = NULL,
.RxBoosted = NULL,
.SetRxDutyCycle = NULL,
.SetTxContinuousWave = SX127xSetTxContinuousWave,
};
static int sx127x_antenna_configure(void)
{
int ret;
ret = sx12xx_configure_pin(antenna_enable, GPIO_OUTPUT_INACTIVE);
if (ret) {
return ret;
}
ret = sx12xx_configure_pin(rfi_enable, GPIO_OUTPUT_INACTIVE);
if (ret) {
return ret;
}
ret = sx12xx_configure_pin(rfo_enable, GPIO_OUTPUT_INACTIVE);
if (ret) {
return ret;
}
ret = sx12xx_configure_pin(pa_boost_enable, GPIO_OUTPUT_INACTIVE);
if (ret) {
return ret;
}
return 0;
}
static int sx127x_lora_init(const struct device *dev)
{
int ret;
uint8_t regval;
if (!spi_is_ready_dt(&dev_config.bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
ret = sx12xx_configure_pin(tcxo_power, GPIO_OUTPUT_INACTIVE);
if (ret) {
return ret;
}
/* Setup Reset gpio and perform soft reset */
ret = sx12xx_configure_pin(reset, GPIO_OUTPUT_ACTIVE);
if (ret) {
return ret;
}
k_sleep(K_MSEC(100));
gpio_pin_set_dt(&dev_config.reset, 0);
k_sleep(K_MSEC(100));
ret = sx127x_read(REG_VERSION, ®val, 1);
if (ret < 0) {
LOG_ERR("Unable to read version info");
return -EIO;
}
LOG_INF("SX127x version 0x%02x found", regval);
ret = sx127x_antenna_configure();
if (ret < 0) {
LOG_ERR("Unable to configure antenna");
return -EIO;
}
ret = sx12xx_init(dev);
if (ret < 0) {
LOG_ERR("Failed to initialize SX12xx common");
return ret;
}
return 0;
}
static const struct lora_driver_api sx127x_lora_api = {
.config = sx12xx_lora_config,
.send = sx12xx_lora_send,
.send_async = sx12xx_lora_send_async,
.recv = sx12xx_lora_recv,
.recv_async = sx12xx_lora_recv_async,
.test_cw = sx12xx_lora_test_cw,
};
DEVICE_DT_INST_DEFINE(0, &sx127x_lora_init, NULL, NULL,
NULL, POST_KERNEL, CONFIG_LORA_INIT_PRIORITY,
&sx127x_lora_api);
``` | /content/code_sandbox/drivers/lora/sx127x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,146 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_src_rev2
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#include <fsl_soc_src.h>
#ifdef CONFIG_CPU_CORTEX_M7
#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag
#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag
#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag
#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \
kSRC_M7CoreWdog3ResetFlag | \
kSRC_M7CoreWdog4ResetFlag)
#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag
#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag
#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag
#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag
#elif defined(CONFIG_CPU_CORTEX_M4)
#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag
#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag
#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag
#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \
kSRC_M4CoreWdog3ResetFlag | \
kSRC_M4CoreWdog4ResetFlag)
#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag
#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag
#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag
#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag
#else
/* The SOCs currently supported have an M7 or M4 core */
#error "MCUX SRC driver not supported for this CPU!"
#endif
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
if (reason & (MCUX_RESET_PIN_FLAG)) {
flags |= RESET_PIN;
}
if (reason & (MCUX_RESET_SOFTWARE_FLAG)) {
flags |= RESET_SOFTWARE;
}
if (reason & (MCUX_RESET_POR_FLAG)) {
flags |= RESET_POR;
}
if (reason & (MCUX_RESET_WATCHDOG_FLAG)) {
flags |= RESET_WATCHDOG;
}
if (reason & (MCUX_RESET_DEBUG_FLAG)) {
flags |= RESET_DEBUG;
}
if (reason & (MCUX_RESET_SECURITY_FLAG)) {
flags |= RESET_SECURITY;
}
if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) {
flags |= RESET_TEMPERATURE;
}
if (reason & (MCUX_RESET_USER_FLAG)) {
flags |= RESET_USER;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_WATCHDOG
| RESET_DEBUG
| RESET_TEMPERATURE
| RESET_PIN
| RESET_SOFTWARE
| RESET_POR
| RESET_SECURITY
| RESET_USER
);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_mcux_src_rev2.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 823 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <soc.h>
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
int ret = 0;
uint32_t reason = CRG_TOP->RESET_STAT_REG;
uint32_t flags = 0;
/*
* When POR is detected other bits are not valid.
*/
if (reason & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
flags = RESET_POR;
} else {
if (reason & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
flags |= RESET_PIN;
}
if (reason & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
flags |= RESET_SOFTWARE;
}
if (reason & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
flags |= RESET_WATCHDOG;
}
if (reason & CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk) {
flags |= RESET_WATCHDOG;
}
if (reason & CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk) {
flags |= RESET_DEBUG;
}
}
*cause = flags;
return ret;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
int ret = 0;
CRG_TOP->RESET_STAT_REG = 0;
return ret;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_SOFTWARE
| RESET_POR
| RESET_WATCHDOG
| RESET_DEBUG);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_smartbond.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 356 |
```c
/*
*
*/
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <fsl_sim.h>
#include <zephyr/sys/byteorder.h>
#if defined(SIM_UIDH)
#define HWINFO_DEVICE_ID_LENGTH_H 1
#else
#define HWINFO_DEVICE_ID_LENGTH_H 0
#endif
#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM)
#define HWINFO_DEVICE_ID_LENGTH_M 1
#else
#define HWINFO_DEVICE_ID_LENGTH_M 2
#endif
#define HWINFO_DEVICE_ID_LENGTH_L 1
#define HWINFO_DEVICE_ID_LENGTH_TOTAL (HWINFO_DEVICE_ID_LENGTH_L + \
HWINFO_DEVICE_ID_LENGTH_M + \
HWINFO_DEVICE_ID_LENGTH_H)
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint32_t id[HWINFO_DEVICE_ID_LENGTH_TOTAL];
uint32_t *idp = id;
#if defined(SIM_UIDH)
*idp++ = sys_cpu_to_be32(SIM->UIDH);
#endif /* SIM_UIDH */
#if (defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM)
*idp++ = sys_cpu_to_be32(SIM->UIDM);
#else
*idp++ = sys_cpu_to_be32(SIM->UIDMH);
*idp++ = sys_cpu_to_be32(SIM->UIDML);
#endif /* defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FEATURE_SIM_HAS_UIDM */
*idp++ = sys_cpu_to_be32(SIM->UIDL);
if (length > sizeof(id)) {
length = sizeof(id);
}
memcpy(buffer, id, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_mcux_sim.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 364 |
```c
/*
*
*/
#include <zephyr/drivers/hwinfo.h>
ssize_t __weak z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
return -ENOSYS;
}
int __weak z_impl_hwinfo_get_device_eui64(uint8_t *buffer)
{
return -ENOSYS;
}
int __weak z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
return -ENOSYS;
}
int __weak z_impl_hwinfo_clear_reset_cause(void)
{
return -ENOSYS;
}
int __weak z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
return -ENOSYS;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_weak_impl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 142 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/hwinfo.h>
ssize_t z_vrfy_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, length));
return z_impl_hwinfo_get_device_id((uint8_t *)buffer, (size_t)length);
}
#include <zephyr/syscalls/hwinfo_get_device_id_mrsh.c>
ssize_t z_vrfy_hwinfo_get_device_eui64(uint8_t *buffer)
{
K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, 8));
return z_impl_hwinfo_get_device_eui64((uint8_t *)buffer);
}
#include <zephyr/syscalls/hwinfo_get_device_eui64_mrsh.c>
int z_vrfy_hwinfo_get_reset_cause(uint32_t *cause)
{
int ret;
uint32_t cause_copy;
ret = z_impl_hwinfo_get_reset_cause(&cause_copy);
K_OOPS(k_usermode_to_copy(cause, &cause_copy, sizeof(uint32_t)));
return ret;
}
#include <zephyr/syscalls/hwinfo_get_reset_cause_mrsh.c>
int z_vrfy_hwinfo_clear_reset_cause(void)
{
return z_impl_hwinfo_clear_reset_cause();
}
#include <zephyr/syscalls/hwinfo_clear_reset_cause_mrsh.c>
int z_vrfy_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
int ret;
uint32_t supported_copy;
ret = z_impl_hwinfo_get_supported_reset_cause(&supported_copy);
K_OOPS(k_usermode_to_copy(supported, &supported_copy, sizeof(uint32_t)));
return ret;
}
#include <zephyr/syscalls/hwinfo_get_supported_reset_cause_mrsh.c>
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 381 |
```c
/*
*
*/
#include <am_mcu_apollo.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct ambiq_hwinfo {
/* Ambiq Chip ID0 */
uint32_t chip_id_0;
/* Ambiq Chip ID1 */
uint32_t chip_id_1;
/* Ambiq Factory Trim Revision */
/* Can be used in Ambiq HAL for additional code support */
uint32_t factory_trim_version;
};
struct ambiq_hwinfo dev_hw_info = {0};
/* Contains the HAL hardware information about the device. */
am_hal_mcuctrl_device_t mcu_ctrl_device;
am_hal_mram_info_read(1, AM_REG_INFO1_TRIM_REV_O / 4, 1, &dev_hw_info.factory_trim_version);
am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &mcu_ctrl_device);
dev_hw_info.chip_id_0 = mcu_ctrl_device.ui32ChipID0;
dev_hw_info.chip_id_1 = mcu_ctrl_device.ui32ChipID1;
if (length > sizeof(dev_hw_info)) {
length = sizeof(dev_hw_info);
}
dev_hw_info.chip_id_0 = BSWAP_32(dev_hw_info.chip_id_0);
dev_hw_info.chip_id_1 = BSWAP_32(dev_hw_info.chip_id_1);
dev_hw_info.factory_trim_version = BSWAP_32(dev_hw_info.factory_trim_version);
memcpy(buffer, &dev_hw_info, length);
return length;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reset_status = 0;
am_hal_reset_status_t status = {0};
/* Print out reset status register upon entry */
am_hal_reset_status_get(&status);
reset_status = status.eStatus;
/* EXTERNAL PIN */
if (reset_status & AM_HAL_RESET_STATUS_EXTERNAL) {
flags |= RESET_PIN;
}
/* POWER CYCLE */
if (reset_status & AM_HAL_RESET_STATUS_POR) {
flags |= RESET_POR;
}
/* BROWNOUT DETECTOR */
if (reset_status & AM_HAL_RESET_STATUS_BOD) {
flags |= RESET_BROWNOUT;
}
/* SOFTWARE POR */
if (reset_status & AM_HAL_RESET_STATUS_SWPOR) {
flags |= RESET_SOFTWARE;
}
/* SOFTWARE POI */
if (reset_status & AM_HAL_RESET_STATUS_SWPOI) {
flags |= RESET_SOFTWARE;
}
/* DEBUGGER */
if (reset_status & AM_HAL_RESET_STATUS_DEBUGGER) {
flags |= RESET_DEBUG;
}
/* WATCHDOG */
if (reset_status & AM_HAL_RESET_STATUS_WDT) {
flags |= RESET_WATCHDOG;
}
/* BOUNREG */
if (reset_status & AM_HAL_RESET_STATUS_BOUNREG) {
flags |= RESET_HARDWARE;
}
/* BOCORE */
if (reset_status & AM_HAL_RESET_STATUS_BOCORE) {
flags |= RESET_HARDWARE;
}
/* BOMEM */
if (reset_status & AM_HAL_RESET_STATUS_BOMEM) {
flags |= RESET_HARDWARE;
}
/* BOHPMEM */
if (reset_status & AM_HAL_RESET_STATUS_BOHPMEM) {
flags |= RESET_HARDWARE;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
/* SBL maintains the RSTGEN->STAT register in
* INFO1 space even upon clearing RSTGEN->STAT
* register.
* - INFO1_RESETSTATUS
*/
return -ENOSYS;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = RESET_PIN
| RESET_SOFTWARE
| RESET_POR
| RESET_WATCHDOG
| RESET_HARDWARE
| RESET_BROWNOUT;
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_ambiq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 885 |
```c
/*
*
*/
#include <string.h>
#include <zephyr/drivers/hwinfo.h>
#include <hardware/flash.h>
#include <hardware/structs/vreg_and_chip_reset.h>
#define FLASH_RUID_DATA_BYTES 8
#define HAD_RUN_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB)
#define HAD_PSM_RESTART_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB)
#define HAD_POR_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB)
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint8_t id[FLASH_RUID_DATA_BYTES];
uint32_t key;
/*
* flash_get_unique_id temporarily disables XIP to query the
* flash for its ID. If the CPU is interrupted while XIP is
* disabled, it will halt. Therefore, interrupts must be disabled
* before fetching the ID.
*/
key = irq_lock();
flash_get_unique_id(id);
irq_unlock(key);
if (length > sizeof(id)) {
length = sizeof(id);
}
memcpy(buffer, id, length);
return length;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reset_register = vreg_and_chip_reset_hw->chip_reset;
if (reset_register & HAD_POR_BIT) {
flags |= RESET_POR;
}
if (reset_register & HAD_RUN_BIT) {
flags |= RESET_PIN;
}
if (reset_register & HAD_PSM_RESTART_BIT) {
flags |= RESET_DEBUG;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
/* The reset register can't be modified, nothing to do. */
return -ENOSYS;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = RESET_PIN | RESET_DEBUG | RESET_POR;
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 430 |
```c
/*
*
*/
#include <zephyr/drivers/hwinfo.h>
#include <fsl_ocotp.h>
#include <fsl_power.h>
/* Because of the ROM clearing the reset register and using scratch register
* which cannot be cleared, we have to "fake" this to meet the hwinfo api.
* Technically all the reset causes are already cleared by the ROM, but we will
* still clear them ourselves on the first call to clear them by user.
*/
static bool reset_cleared;
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint32_t id_length = length;
if (OCOTP_ReadUniqueID(buffer, &id_length)) {
return -EINVAL;
}
return (ssize_t)id_length;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (
RESET_SOFTWARE |
RESET_CPU_LOCKUP |
RESET_WATCHDOG |
RESET_SECURITY |
RESET_DEBUG |
RESET_HARDWARE
);
return 0;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
if (reset_cleared) {
*cause = 0;
return 0;
}
uint32_t reset_cause = POWER_GetResetCause();
switch (reset_cause) {
case kPOWER_ResetCauseSysResetReq:
*cause = RESET_SOFTWARE;
break;
case kPOWER_ResetCauseLockup:
*cause = RESET_CPU_LOCKUP;
break;
case kPOWER_ResetCauseWdt:
*cause = RESET_WATCHDOG;
break;
case kPOWER_ResetCauseApResetReq:
*cause = RESET_DEBUG;
break;
case kPOWER_ResetCauseCodeWdt:
case kPOWER_ResetCauseItrc:
*cause = RESET_SECURITY;
break;
case kPOWER_ResetCauseResetB:
*cause = RESET_HARDWARE;
break;
default:
*cause = 0;
break;
}
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
POWER_ClearResetCause(kPOWER_ResetCauseAll);
reset_cleared = true;
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_rw61x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 477 |
```c
/*
*
*/
#include <soc/efuse_reg.h>
#include <soc/reset_reasons.h>
#include "esp_system.h"
#include "rtc.h"
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
#if defined(CONFIG_SOC_SERIES_ESP32C2)
uint32_t rdata1 = sys_read32(EFUSE_RD_BLK2_DATA0_REG);
uint32_t rdata2 = sys_read32(EFUSE_RD_BLK2_DATA1_REG);
#elif !defined(CONFIG_SOC_SERIES_ESP32)
uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG);
uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG);
#else
uint32_t rdata1 = sys_read32(EFUSE_BLK0_RDATA1_REG);
uint32_t rdata2 = sys_read32(EFUSE_BLK0_RDATA2_REG);
#endif
uint8_t id[6];
/* The first word provides the lower 32 bits of the MAC
* address; the low 16 bits of the second word provide the
* upper 16 bytes of the MAC address. The upper 16 bits are
* (apparently) a checksum, and reserved. See ESP32 Technical
* Reference Manual V4.1 section 20.5.
*/
id[0] = (uint8_t)(rdata2 >> 8);
id[1] = (uint8_t)(rdata2 >> 0);
id[2] = (uint8_t)(rdata1 >> 24);
id[3] = (uint8_t)(rdata1 >> 16);
id[4] = (uint8_t)(rdata1 >> 8);
id[5] = (uint8_t)(rdata1 >> 0);
if (length > sizeof(id)) {
length = sizeof(id);
}
memcpy(buffer, id, length);
return length;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_POR
| RESET_PIN
| RESET_SOFTWARE
| RESET_WATCHDOG
| RESET_LOW_POWER_WAKE
| RESET_CPU_LOCKUP
| RESET_BROWNOUT);
return 0;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t reason = esp_reset_reason();
switch (reason) {
case ESP_RST_POWERON:
*cause = RESET_POR;
break;
case ESP_RST_EXT:
*cause = RESET_PIN;
break;
case ESP_RST_SW:
*cause = RESET_SOFTWARE;
break;
case ESP_RST_INT_WDT:
case ESP_RST_TASK_WDT:
case ESP_RST_WDT:
*cause = RESET_WATCHDOG;
break;
case ESP_RST_DEEPSLEEP:
*cause = RESET_LOW_POWER_WAKE;
break;
case ESP_RST_PANIC:
*cause = RESET_CPU_LOCKUP;
case ESP_RST_BROWNOUT:
*cause = RESET_BROWNOUT;
break;
default:
*cause = 0;
break;
}
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_esp32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 696 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
struct numaker_uid {
uint32_t id[3];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct numaker_uid dev_id;
SYS_UnlockReg();
FMC_Open();
dev_id.id[0] = sys_cpu_to_be32(FMC_ReadUID(0));
dev_id.id[1] = sys_cpu_to_be32(FMC_ReadUID(1));
dev_id.id[2] = sys_cpu_to_be32(FMC_ReadUID(2));
length = MIN(length, sizeof(dev_id.id));
memcpy(buffer, dev_id.id, length);
FMC_Close();
SYS_LockReg();
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_numaker.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 176 |
```c
/*
*
*/
#include <em_system.h>
#include <em_rmu.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#if defined(RMU_RSTCAUSE_BODUNREGRST) || defined(RMU_RSTCAUSE_BODREGRST) || \
defined(RMU_RSTCAUSE_AVDDBOD) || defined(RMU_RSTCAUSE_DVDDBOD) || \
defined(RMU_RSTCAUSE_DECBOD) || defined(RMU_RSTCAUSE_BODAVDD0) || \
defined(RMU_RSTCAUSE_BODAVDD1) || \
(defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0))
#define HAS_BROWNOUT 1
#endif
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint64_t unique_id = sys_cpu_to_be64(SYSTEM_GetUnique());
if (length > sizeof(unique_id)) {
length = sizeof(unique_id);
}
memcpy(buffer, &unique_id, length);
return length;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t __maybe_unused rmu_flags = RMU_ResetCauseGet();
#ifdef RMU_RSTCAUSE_PORST
if (rmu_flags & RMU_RSTCAUSE_PORST) {
flags |= RESET_POR;
}
#endif /* RMU_RSTCAUSE_PORST */
#ifdef RMU_RSTCAUSE_EXTRST
if (rmu_flags & RMU_RSTCAUSE_EXTRST) {
flags |= RESET_PIN;
}
#endif /* RMU_RSTCAUSE_EXTRST */
#ifdef RMU_RSTCAUSE_SYSREQRST
if (rmu_flags & RMU_RSTCAUSE_SYSREQRST) {
flags |= RESET_SOFTWARE;
}
#endif /* RMU_RSTCAUSE_SYSREQRST */
#ifdef RMU_RSTCAUSE_LOCKUPRST
if (rmu_flags & RMU_RSTCAUSE_LOCKUPRST) {
flags |= RESET_CPU_LOCKUP;
}
#endif /* RMU_RSTCAUSE_LOCKUPRST */
#ifdef RMU_RSTCAUSE_WDOGRST
if (rmu_flags & RMU_RSTCAUSE_WDOGRST) {
flags |= RESET_WATCHDOG;
}
#endif /* RMU_RSTCAUSE_WDOGRST */
#ifdef RMU_RSTCAUSE_EM4WURST
if (rmu_flags & RMU_RSTCAUSE_EM4WURST) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif /* RMU_RSTCAUSE_EM4WURST */
#ifdef RMU_RSTCAUSE_EM4RST
if (rmu_flags & RMU_RSTCAUSE_EM4RST) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif /* RMU_RSTCAUSE_EM4RST */
#ifdef RMU_RSTCAUSE_BODUNREGRST
if (rmu_flags & RMU_RSTCAUSE_BODUNREGRST) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_BODUNREGRST */
#ifdef RMU_RSTCAUSE_BODREGRST
if (rmu_flags & RMU_RSTCAUSE_BODREGRST) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_BODREGRST */
#ifdef RMU_RSTCAUSE_AVDDBOD
if (rmu_flags & RMU_RSTCAUSE_AVDDBOD) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_AVDDBOD */
#ifdef RMU_RSTCAUSE_DVDDBOD
if (rmu_flags & RMU_RSTCAUSE_DVDDBOD) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_DVDDBOD */
#ifdef RMU_RSTCAUSE_DECBOD
if (rmu_flags & RMU_RSTCAUSE_DECBOD) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_DECBOD */
#ifdef RMU_RSTCAUSE_BODAVDD0
if (rmu_flags & RMU_RSTCAUSE_BODAVDD0) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_BODAVDD0 */
#ifdef RMU_RSTCAUSE_BODAVDD1
if (rmu_flags & RMU_RSTCAUSE_BODAVDD1) {
flags |= RESET_BROWNOUT;
}
#endif /* RMU_RSTCAUSE_BODAVDD1 */
#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
if (rmu_flags & RMU_RSTCAUSE_BUBODVDDDREG) {
flags |= RESET_BROWNOUT;
}
if (rmu_flags & RMU_RSTCAUSE_BUBODBUVIN) {
flags |= RESET_BROWNOUT;
}
if (rmu_flags & RMU_RSTCAUSE_BUBODUNREG) {
flags |= RESET_BROWNOUT;
}
if (rmu_flags & RMU_RSTCAUSE_BUBODREG) {
flags |= RESET_BROWNOUT;
}
if (rmu_flags & RMU_RSTCAUSE_BUMODERST) {
flags |= RESET_BROWNOUT;
}
#elif defined(RMU_RSTCAUSE_BUMODERST)
if (rmu_flags & RMU_RSTCAUSE_BUMODERST) {
flags |= RESET_BROWNOUT;
}
#endif /* defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) */
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
RMU_ResetCauseClear();
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = RESET_PIN
| RESET_SOFTWARE
| RESET_POR
| RESET_WATCHDOG
| RESET_CPU_LOCKUP
#if defined(RMU_RSTCAUSE_EM4WURST) || defined(RMU_RSTCAUSE_EM4RST)
| RESET_LOW_POWER_WAKE
#endif /* defined(RMU_RSTCAUSE_EM4WURST) || defined(RMU_RSTCAUSE_EM4RST) */
#if HAS_BROWNOUT
| RESET_BROWNOUT
#endif /* HAS_BROWNOUT */
;
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_gecko.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,387 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/drivers/syscon.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
/*
* SMU(System Management Unit) Registers for hwinfo driver
*/
/* Register offset*/
#define SMU_SYSTEMVER 0x00
#define SMU_WRSR 0x10
/* Wake-Up and Reset Status Register bitmask */
#define SMU_WRSR_APOR BIT(0)
#define SMU_WRSR_MPOR BIT(1)
#define SMU_WRSR_HW BIT(2)
#define SMU_WRSR_WDT BIT(3)
#define SMU_WRSR_SW BIT(4)
#define ANDES_RESET_STATUS_MASK BIT_MASK(5)
static const struct device *const syscon_dev =
DEVICE_DT_GET(DT_NODELABEL(syscon));
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
int ret = 0;
uint8_t id[3];
uint32_t ver;
if (!device_is_ready(syscon_dev)) {
return -ENODEV;
}
ret = syscon_read_reg(syscon_dev, SMU_SYSTEMVER, &ver);
if (ret < 0) {
return ret;
}
if (length > sizeof(id)) {
length = sizeof(id);
}
sys_put_le24(ver, id);
memcpy(buffer, id, length);
return length;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
int ret = 0;
uint32_t reason, flags = 0;
if (!device_is_ready(syscon_dev)) {
return -ENODEV;
}
ret = syscon_read_reg(syscon_dev, SMU_WRSR, &reason);
if (ret < 0) {
return ret;
}
if (reason & SMU_WRSR_APOR) {
flags |= RESET_POR;
}
if (reason & SMU_WRSR_MPOR) {
flags |= RESET_POR;
}
if (reason & SMU_WRSR_HW) {
flags |= RESET_PIN;
}
if (reason & SMU_WRSR_WDT) {
flags |= RESET_WATCHDOG;
}
if (reason & SMU_WRSR_SW) {
flags |= RESET_SOFTWARE;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
int ret = 0;
uint32_t reason;
if (!device_is_ready(syscon_dev)) {
return -ENODEV;
}
ret = syscon_write_reg(syscon_dev, SMU_WRSR, ANDES_RESET_STATUS_MASK);
if (ret < 0) {
return ret;
}
do {
ret = syscon_read_reg(syscon_dev, SMU_WRSR, &reason);
} while ((reason & ANDES_RESET_STATUS_MASK) && (!ret));
return ret;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_WATCHDOG
| RESET_SOFTWARE
| RESET_POR);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_andes.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 683 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam_rstc
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"No atmel,sam-rstc compatible device found");
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
/* Get reason from Status Register */
uint32_t reason = ((Rstc *)DT_INST_REG_ADDR(0))->RSTC_SR & RSTC_SR_RSTTYP_Msk;
switch (reason) {
case RSTC_SR_RSTTYP_GENERAL_RST:
*cause = RESET_POR;
break;
case RSTC_SR_RSTTYP_BACKUP_RST:
*cause = RESET_LOW_POWER_WAKE;
break;
case RSTC_SR_RSTTYP_WDT_RST:
*cause = RESET_WATCHDOG;
break;
case RSTC_SR_RSTTYP_SOFT_RST:
*cause = RESET_SOFTWARE;
break;
case RSTC_SR_RSTTYP_USER_RST:
*cause = RESET_USER;
break;
default:
break;
}
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = RESET_POR
| RESET_LOW_POWER_WAKE
| RESET_WATCHDOG
| RESET_SOFTWARE
| RESET_USER;
return 0;
}
static int hwinfo_rstc_init(void)
{
Rstc *regs = (Rstc *)DT_INST_REG_ADDR(0);
const struct atmel_sam_pmc_config clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0);
uint32_t mode;
/* Enable RSTC in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t)&clock_cfg);
/* Get current Mode Register value */
mode = regs->RSTC_MR;
/* Enable/disable user reset on NRST */
#if DT_INST_PROP(0, user_nrst)
mode &= ~RSTC_MR_KEY_Msk;
mode |= (RSTC_MR_URSTEN | RSTC_MR_KEY_PASSWD);
#else
mode &= ~(RSTC_MR_URSTEN | RSTC_MR_KEY_Msk);
mode |= RSTC_MR_KEY_PASSWD;
#endif
/* Set Mode Register value */
regs->RSTC_MR = mode;
return 0;
}
SYS_INIT(hwinfo_rstc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_sam_rstc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 557 |
```c
/*
*
*/
#include <soc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_rcc.h>
#if defined(CONFIG_SOC_SERIES_STM32H5X)
#include <stm32_ll_icache.h>
#endif /* CONFIG_SOC_SERIES_STM32H5X */
#include <stm32_ll_pwr.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
struct stm32_uid {
uint32_t id[3];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct stm32_uid dev_id;
#if defined(CONFIG_SOC_SERIES_STM32H5X)
LL_ICACHE_Disable();
#endif /* CONFIG_SOC_SERIES_STM32H5X */
dev_id.id[0] = sys_cpu_to_be32(LL_GetUID_Word2());
dev_id.id[1] = sys_cpu_to_be32(LL_GetUID_Word1());
dev_id.id[2] = sys_cpu_to_be32(LL_GetUID_Word0());
#if defined(CONFIG_SOC_SERIES_STM32H5X)
LL_ICACHE_Enable();
#endif /* CONFIG_SOC_SERIES_STM32H5X */
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
#if defined(CONFIG_SOC_SERIES_STM32WBAX) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX)
struct stm32_eui64 {
uint32_t id[2];
};
int z_impl_hwinfo_get_device_eui64(uint8_t *buffer)
{
struct stm32_eui64 dev_eui64;
dev_eui64.id[0] = sys_cpu_to_be32(READ_REG(*((uint32_t *)UID64_BASE + 1U)));
dev_eui64.id[1] = sys_cpu_to_be32(READ_REG(*((uint32_t *)UID64_BASE)));
memcpy(buffer, dev_eui64.id, sizeof(dev_eui64));
return 0;
}
#endif
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
#if defined(RCC_FLAG_SFTRST)
if (LL_RCC_IsActiveFlag_SFTRST()) {
flags |= RESET_SOFTWARE;
}
#endif
#if defined(RCC_FLAG_PINRST)
if (LL_RCC_IsActiveFlag_PINRST()) {
flags |= RESET_PIN;
}
#endif
#if defined(RCC_FLAG_IWDGRST)
if (LL_RCC_IsActiveFlag_IWDGRST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_RSR_IWDG1RSTF)
if (LL_RCC_IsActiveFlag_IWDG1RST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_RSR_IWDG2RSTF)
if (LL_RCC_IsActiveFlag_IWDG2RST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_FLAG_WWDGRST)
if (LL_RCC_IsActiveFlag_WWDGRST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_RSR_WWDG1RSTF)
if (LL_RCC_IsActiveFlag_WWDG1RST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_RSR_WWDG2RSTF)
if (LL_RCC_IsActiveFlag_WWDG2RST()) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCC_FLAG_FWRST)
if (LL_RCC_IsActiveFlag_FWRST()) {
flags |= RESET_SECURITY;
}
#endif
#if defined(RCC_FLAG_BORRST)
if (LL_RCC_IsActiveFlag_BORRST()) {
flags |= RESET_BROWNOUT;
}
#endif
#if defined(RCC_FLAG_PWRRST)
if (LL_RCC_IsActiveFlag_PWRRST()) {
flags |= RESET_POR;
}
#endif
#if defined(RCC_FLAG_PORRST)
if (LL_RCC_IsActiveFlag_PORRST()) {
flags |= RESET_POR;
}
#endif
#if defined(RCC_FLAG_LPWRRST)
if (LL_RCC_IsActiveFlag_LPWRRST()) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
if (LL_PWR_CPU2_IsActiveFlag_SB()) {
flags |= RESET_LOW_POWER_WAKE;
}
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
if (LL_PWR_CPU_IsActiveFlag_SB()) {
flags |= RESET_LOW_POWER_WAKE;
}
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
if (LL_PWR_MCU_IsActiveFlag_SB()) {
flags |= RESET_LOW_POWER_WAKE;
}
#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
if (LL_PWR_IsActiveFlag_C1SB()) {
flags |= RESET_LOW_POWER_WAKE;
}
#elif defined(PWR_FLAG_SB) || defined(PWR_FLAG_SBF)
if (LL_PWR_IsActiveFlag_SB()) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif /* PWR_FLAG_SB */
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
LL_RCC_ClearResetFlags();
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
LL_PWR_ClearFlag_CPU2();
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
LL_PWR_ClearFlag_CPU();
#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
LL_PWR_ClearFlag_STOP_SB();
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
LL_PWR_ClearFlag_MCU();
#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
LL_PWR_ClearFlag_C1STOP_C1STB();
#elif defined(PWR_FLAG_SB)
LL_PWR_ClearFlag_SB();
#endif /* PWR_FLAG_SB */
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_WATCHDOG
| RESET_SOFTWARE
| RESET_SECURITY
| RESET_LOW_POWER_WAKE
| RESET_POR
| RESET_BROWNOUT);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,389 |
```c
/*
*
*/
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/logging/log.h>
#include <fsl_rcm.h>
LOG_MODULE_REGISTER(hwinfo_rcm, CONFIG_HWINFO_LOG_LEVEL);
/**
* @brief Translate from RCM reset source mask to Zephyr hwinfo sources mask.
*
* Translate bitmask from MCUX RCM reset source bitmask to Zephyr
* hwinfo reset source bitmask.
*
* @param NXP MCUX RCM reset source mask.
* @retval Zephyr hwinfo reset source mask.
*/
static uint32_t hwinfo_mcux_rcm_xlate_reset_sources(uint32_t sources)
{
uint32_t mask = 0;
#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
if (sources & kRCM_SourceWakeup) {
mask |= RESET_LOW_POWER_WAKE;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) */
if (sources & kRCM_SourceLvd) {
mask |= RESET_BROWNOUT;
}
#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
if (sources & kRCM_SourceLoc) {
mask |= RESET_CLOCK;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) */
#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
if (sources & kRCM_SourceLol) {
mask |= RESET_PLL;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) */
if (sources & kRCM_SourceWdog) {
mask |= RESET_WATCHDOG;
}
if (sources & kRCM_SourcePin) {
mask |= RESET_PIN;
}
if (sources & kRCM_SourcePor) {
mask |= RESET_POR;
}
#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
if (sources & kRCM_SourceJtag) {
mask |= RESET_DEBUG;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) */
if (sources & kRCM_SourceLockup) {
mask |= RESET_CPU_LOCKUP;
}
if (sources & kRCM_SourceSw) {
mask |= RESET_SOFTWARE;
}
#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
if (sources & kRCM_SourceMdmap) {
mask |= RESET_DEBUG;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) */
#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
if (sources & kRCM_SourceEzpt) {
mask |= RESET_DEBUG;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) */
return mask;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t sources;
#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
sources = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
#else /* (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) */
sources = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll;
#endif /* !(defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) */
*cause = hwinfo_mcux_rcm_xlate_reset_sources(sources);
LOG_DBG("sources = 0x%08x, cause = 0x%08x", sources, *cause);
return 0;
}
#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
int z_impl_hwinfo_clear_reset_cause(void)
{
uint32_t sources;
sources = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
RCM_ClearStickyResetSources(RCM, sources);
LOG_DBG("sources = 0x%08x", sources);
return 0;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) */
#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM)
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
uint32_t sources;
sources = RCM_GetResetSourceImplementedStatus(RCM);
*supported = hwinfo_mcux_rcm_xlate_reset_sources(sources);
LOG_DBG("sources = 0x%08x, supported = 0x%08x", sources, *supported);
return 0;
}
#endif /* (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) */
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_mcux_rcm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,093 |
```c
/*
*
*/
#include <zephyr/sys/printk.h>
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/types.h>
#include <zephyr/logging/log.h>
static int cmd_get_device_id(const struct shell *sh, size_t argc, char **argv)
{
uint8_t dev_id[16];
ssize_t length;
int i;
length = hwinfo_get_device_id(dev_id, sizeof(dev_id));
if (length == -ENOSYS) {
shell_error(sh, "Not supported by hardware");
return -ENOSYS;
} else if (length < 0) {
shell_error(sh, "Error: %zd", length);
return length;
}
shell_fprintf(sh, SHELL_NORMAL, "Length: %zd\n", length);
shell_fprintf(sh, SHELL_NORMAL, "ID: 0x");
for (i = 0 ; i < length ; i++) {
shell_fprintf(sh, SHELL_NORMAL, "%02x", dev_id[i]);
}
shell_fprintf(sh, SHELL_NORMAL, "\n");
return 0;
}
static int cmd_get_device_eui64(const struct shell *sh, size_t argc, char **argv)
{
uint8_t dev_eui64[8];
int ret;
int i;
ret = hwinfo_get_device_eui64(dev_eui64);
if (ret == -ENOSYS) {
shell_error(sh, "Not supported by hardware");
return -ENOSYS;
} else if (ret < 0) {
shell_error(sh, "Error: %d", ret);
return ret;
}
shell_fprintf(sh, SHELL_NORMAL, "EUI64: 0x");
for (i = 0 ; i < 8 ; i++) {
shell_fprintf(sh, SHELL_NORMAL, "%02x", dev_eui64[i]);
}
shell_fprintf(sh, SHELL_NORMAL, "\n");
return 0;
}
static inline const char *cause_to_string(uint32_t cause)
{
switch (cause) {
case RESET_PIN:
return "pin";
case RESET_SOFTWARE:
return "software";
case RESET_BROWNOUT:
return "brownout";
case RESET_POR:
return "power-on reset";
case RESET_WATCHDOG:
return "watchdog";
case RESET_DEBUG:
return "debug";
case RESET_SECURITY:
return "security";
case RESET_LOW_POWER_WAKE:
return "low power wake-up";
case RESET_CPU_LOCKUP:
return "CPU lockup";
case RESET_PARITY:
return "parity error";
case RESET_PLL:
return "PLL error";
case RESET_CLOCK:
return "clock";
case RESET_HARDWARE:
return "hardware";
case RESET_USER:
return "user";
case RESET_TEMPERATURE:
return "temperature";
default:
return "unknown";
}
}
static void print_all_reset_causes(const struct shell *sh, uint32_t cause)
{
for (uint32_t cause_mask = 1; cause_mask; cause_mask <<= 1) {
if (cause & cause_mask) {
shell_print(sh, "- %s",
cause_to_string(cause & cause_mask));
}
}
}
static int cmd_show_reset_cause(const struct shell *sh, size_t argc,
char **argv)
{
int res;
uint32_t cause;
ARG_UNUSED(argc);
ARG_UNUSED(argv);
res = hwinfo_get_reset_cause(&cause);
if (res == -ENOSYS) {
shell_error(sh, "Not supported by hardware");
return res;
} else if (res != 0) {
shell_error(sh, "Error reading the cause [%d]", res);
return res;
}
if (cause != 0) {
shell_print(sh, "reset caused by:");
print_all_reset_causes(sh, cause);
} else {
shell_print(sh, "No reset cause set");
}
return 0;
}
static int cmd_clear_reset_cause(const struct shell *sh, size_t argc,
char **argv)
{
int res;
ARG_UNUSED(argc);
ARG_UNUSED(argv);
res = hwinfo_clear_reset_cause();
if (res == -ENOSYS) {
shell_error(sh, "Not supported by hardware");
} else if (res != 0) {
shell_error(sh, "Error clearing the reset causes [%d]", res);
return res;
}
return 0;
}
static int cmd_supported_reset_cause(const struct shell *sh, size_t argc,
char **argv)
{
uint32_t cause;
int res;
ARG_UNUSED(argc);
ARG_UNUSED(argv);
res = hwinfo_get_supported_reset_cause(&cause);
if (res == -ENOSYS) {
shell_error(sh, "Not supported by hardware");
} else if (res != 0) {
shell_error(sh, "Could not get the supported reset causes [%d]", res);
return res;
}
if (cause != 0) {
shell_print(sh, "supported reset causes:");
print_all_reset_causes(sh, cause);
} else {
shell_print(sh, "No causes supported");
}
return 0;
}
SHELL_STATIC_SUBCMD_SET_CREATE(sub_reset_cause,
SHELL_CMD_ARG(show, NULL, "Show persistent reset causes",
cmd_show_reset_cause, 1, 0),
SHELL_CMD_ARG(clear, NULL, "Clear all persistent reset causes",
cmd_clear_reset_cause, 1, 0),
SHELL_CMD_ARG(supported, NULL,
"Get a list of all supported reset causes",
cmd_supported_reset_cause, 1, 0),
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_STATIC_SUBCMD_SET_CREATE(sub_hwinfo,
SHELL_CMD_ARG(devid, NULL, "Show device id", cmd_get_device_id, 1, 0),
SHELL_CMD_ARG(deveui64, NULL, "Show device eui64", cmd_get_device_eui64, 1, 0),
SHELL_CMD_ARG(reset_cause, &sub_reset_cause, "Reset cause commands",
cmd_show_reset_cause, 1, 0),
SHELL_SUBCMD_SET_END /* Array terminated. */
);
SHELL_CMD_ARG_REGISTER(hwinfo, &sub_hwinfo, "HWINFO commands", NULL, 2, 0);
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,385 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#if !defined(CONFIG_SOC_SERIES_NRF54HX) && !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
#include <helpers/nrfx_reset_reason.h>
#endif
#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S)
#include <soc_secure.h>
#else
#include <hal/nrf_ficr.h>
#endif
struct nrf_uid {
uint32_t id[2];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct nrf_uid dev_id;
uint32_t buf[2];
#if NRF_FICR_HAS_DEVICE_ID || NRF_FICR_HAS_INFO_DEVICE_ID
/* DEVICEID is accessible, use this */
#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && defined(NRF_FICR_S)
soc_secure_read_deviceid(buf);
#else
buf[0] = nrf_ficr_deviceid_get(NRF_FICR, 0);
buf[1] = nrf_ficr_deviceid_get(NRF_FICR, 1);
#endif
#elif NRF_FICR_HAS_DEVICE_ADDR || NRF_FICR_HAS_BLE_ADDR
/* DEVICEID is not accessible, use device/ble address instead.
* Assume that it is always accessible from the non-secure image.
*/
buf[0] = nrf_ficr_deviceaddr_get(NRF_FICR, 0);
buf[1] = nrf_ficr_deviceaddr_get(NRF_FICR, 1);
/* Assume that ER and IR are available whenever deviceaddr is.
* Use the LSBytes from ER and IR to complete the device id.
*/
buf[1] |= (nrf_ficr_er_get(NRF_FICR, 0) & 0xFF) << 16;
buf[1] |= (nrf_ficr_ir_get(NRF_FICR, 0) & 0xFF) << 24;
#else
#error "No suitable source for hwinfo device_id generation"
#endif
dev_id.id[0] = sys_cpu_to_be32(buf[1]);
dev_id.id[1] = sys_cpu_to_be32(buf[0]);
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
#if !defined(CONFIG_SOC_SERIES_NRF54HX) && !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reason = nrfx_reset_reason_get();
if (reason & NRFX_RESET_REASON_RESETPIN_MASK) {
flags |= RESET_PIN;
}
if (reason & NRFX_RESET_REASON_DOG_MASK) {
flags |= RESET_WATCHDOG;
}
if (reason & NRFX_RESET_REASON_LOCKUP_MASK) {
flags |= RESET_CPU_LOCKUP;
}
if (reason & NRFX_RESET_REASON_OFF_MASK) {
flags |= RESET_LOW_POWER_WAKE;
}
if (reason & NRFX_RESET_REASON_DIF_MASK) {
flags |= RESET_DEBUG;
}
if (reason & NRFX_RESET_REASON_SREQ_MASK) {
flags |= RESET_SOFTWARE;
}
#if NRFX_RESET_REASON_HAS_CTRLAP
if (reason & NRFX_RESET_REASON_CTRLAP_MASK) {
flags |= RESET_DEBUG;
}
#endif
#if NRFX_RESET_REASON_HAS_LPCOMP
if (reason & NRFX_RESET_REASON_LPCOMP_MASK) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif
#if NRFX_RESET_REASON_HAS_NFC
if (reason & NRFX_RESET_REASON_NFC_MASK) {
flags |= RESET_LOW_POWER_WAKE;
}
#endif
#if NRFX_RESET_REASON_HAS_VBUS
if (reason & NRFX_RESET_REASON_VBUS_MASK) {
flags |= RESET_POR;
}
#endif
#if NRFX_RESET_REASON_HAS_CTRLAPSOFT
if (reason & NRFX_RESET_REASON_CTRLAPSOFT_MASK) {
flags |= RESET_DEBUG;
}
#endif
#if NRFX_RESET_REASON_HAS_CTRLAPHARD
if (reason & NRFX_RESET_REASON_CTRLAPHARD_MASK) {
flags |= RESET_DEBUG;
}
#endif
#if NRFX_RESET_REASON_HAS_CTRLAPPIN
if (reason & NRFX_RESET_REASON_CTRLAPPIN_MASK) {
flags |= RESET_DEBUG;
}
#endif
#if !NRF_POWER_HAS_RESETREAS
if (reason & NRFX_RESET_REASON_DOG1_MASK) {
flags |= RESET_WATCHDOG;
}
#endif
#if NRFX_RESET_REASON_HAS_GRTC
if (reason & NRFX_RESET_REASON_GRTC_MASK) {
flags |= RESET_CLOCK;
}
#endif
#if NRFX_RESET_REASON_HAS_NETWORK
if (reason & NRFX_RESET_REASON_LSREQ_MASK) {
flags |= RESET_SOFTWARE;
}
if (reason & NRFX_RESET_REASON_LLOCKUP_MASK) {
flags |= RESET_CPU_LOCKUP;
}
if (reason & NRFX_RESET_REASON_LDOG_MASK) {
flags |= RESET_WATCHDOG;
}
if (reason & NRFX_RESET_REASON_LCTRLAP_MASK) {
flags |= RESET_DEBUG;
}
#endif
#if defined(NRFX_RESET_REASON_TAMPC_MASK)
if (reason & NRFX_RESET_REASON_TAMPC_MASK) {
flags |= RESET_SECURITY;
}
#endif
#if defined(NRFX_RESET_REASON_SECTAMPER_MASK)
if (reason & NRFX_RESET_REASON_SECTAMPER_MASK) {
flags |= RESET_SECURITY;
}
#endif
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
uint32_t reason = -1;
nrfx_reset_reason_clear(reason);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_WATCHDOG
| RESET_SOFTWARE
| RESET_CPU_LOCKUP
| RESET_LOW_POWER_WAKE
| RESET_DEBUG);
return 0;
}
#endif
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_nrf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,313 |
```c
/*
*
*/
#define DT_DRV_COMPAT cypress_psoc6_uid
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/init.h>
#include <soc.h>
#include <string.h>
#include <cy_syslib.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint8_t *uid_addr = (uint8_t *) DT_INST_REG_ADDR(0);
if (buffer == NULL) {
return 0;
}
if (length > DT_INST_REG_SIZE(0)) {
length = DT_INST_REG_SIZE(0);
}
memcpy(buffer, uid_addr, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_psoc6.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 148 |
```c
/*
*
*/
#include <errno.h>
#include <string.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/byteorder.h>
#include <driverlib/sys_ctrl.h>
#include <inc/hw_ccfg.h>
#include <inc/hw_fcfg1.h>
#include <inc/hw_memmap.h>
#ifdef CONFIG_HWINFO_CC13XX_CC26XX_USE_BLE_MAC
#define CC13XX_CC26XX_DEVID_SIZE 6
#else
#define CC13XX_CC26XX_DEVID_SIZE 8
#endif
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint8_t *mac;
if (IS_ENABLED(CONFIG_HWINFO_CC13XX_CC26XX_USE_BLE_MAC)) {
if (IS_ENABLED(CONFIG_HWINFO_CC13XX_CC26XX_ALWAYS_USE_FACTORY_DEFAULT) ||
sys_read32(CCFG_BASE + CCFG_O_IEEE_BLE_0) == 0xFFFFFFFF ||
sys_read32(CCFG_BASE + CCFG_O_IEEE_BLE_1) == 0xFFFFFFFF) {
mac = (uint8_t *)(FCFG1_BASE + FCFG1_O_MAC_BLE_0);
} else {
mac = (uint8_t *)(CCFG_BASE + CCFG_O_IEEE_BLE_0);
}
} else if (IS_ENABLED(CONFIG_HWINFO_CC13XX_CC26XX_USE_IEEE_MAC)) {
if (IS_ENABLED(CONFIG_HWINFO_CC13XX_CC26XX_ALWAYS_USE_FACTORY_DEFAULT) ||
sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_0) == 0xFFFFFFFF ||
sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_1) == 0xFFFFFFFF) {
mac = (uint8_t *)(FCFG1_BASE + FCFG1_O_MAC_15_4_0);
} else {
mac = (uint8_t *)(CCFG_BASE + CCFG_O_IEEE_MAC_0);
}
}
if (length > CC13XX_CC26XX_DEVID_SIZE) {
length = CC13XX_CC26XX_DEVID_SIZE;
}
/* Provide device ID (MAC) in big endian */
sys_memcpy_swap(buffer, mac, length);
return length;
}
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t reset_src;
reset_src = SysCtrlResetSourceGet();
switch (reset_src) {
case RSTSRC_PWR_ON:
*cause = RESET_POR;
break;
case RSTSRC_PIN_RESET:
*cause = RESET_PIN;
break;
case RSTSRC_VDDS_LOSS:
__fallthrough;
case RSTSRC_VDDR_LOSS:
*cause = RESET_BROWNOUT;
break;
case RSTSRC_CLK_LOSS:
*cause = RESET_CLOCK;
break;
case RSTSRC_SYSRESET:
*cause = RESET_SOFTWARE;
break;
}
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
return -ENOSYS;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_SOFTWARE
| RESET_BROWNOUT
| RESET_POR
| RESET_CLOCK);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 707 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/init.h>
#include <soc.h>
#include <string.h>
static uint8_t sam_uid[16];
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
if (length > sizeof(sam_uid)) {
length = sizeof(sam_uid);
}
memcpy(buffer, sam_uid, length);
return length;
}
/* On the Atmel SAM SoC series, the device id is located in the flash
* controller. The controller can either present the flash area containing
* the code, the unique identifier or the user signature area at the flash
* location. Therefore the function reading the device id must be executed
* from RAM with the interrupts disabled. To avoid executing this complex
* code each time the device id is requested, we do this at boot time at save
* the 128-bit value into RAM.
*/
__ramfunc static void hwinfo_sam_read_device_id(void)
{
Efc *efc = (Efc *)DT_REG_ADDR(DT_INST(0, atmel_sam_flash_controller));
uint8_t *flash = (uint8_t *)CONFIG_FLASH_BASE_ADDRESS;
int i;
/* Switch the flash controller to the unique identifier area. The flash
* is not available anymore, hence we have to wait for it to be *NOT*
* ready.
*/
efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_STUI;
while ((efc->EEFC_FSR & EEFC_FSR_FRDY) == EEFC_FSR_FRDY) {
/* Wait */
}
/* Copy the 128-bit unique ID. We cannot use memcpy as it would
* execute code from flash.
*/
for (i = 0; i < sizeof(sam_uid); i++) {
sam_uid[i] = flash[i];
}
/* Switch back the controller to the flash area and wait for it to
* be ready.
*/
efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SPUI;
while ((efc->EEFC_FSR & EEFC_FSR_FRDY) != EEFC_FSR_FRDY) {
/* Wait */
}
}
static int hwinfo_sam_init(void)
{
Efc *efc = (Efc *)DT_REG_ADDR(DT_INST(0, atmel_sam_flash_controller));
uint32_t fmr;
unsigned int key;
/* Disable interrupts. */
key = irq_lock();
/* Disable code loop optimization and sequential code optimization. */
fmr = efc->EEFC_FMR;
#ifndef CONFIG_SOC_SERIES_SAM3X
efc->EEFC_FMR = (fmr & (~EEFC_FMR_CLOE)) | EEFC_FMR_SCOD;
#else
/* SAM3x does not have loop optimization (EEFC_FMR_CLOE) */
efc->EEFC_FMR |= EEFC_FMR_SCOD;
#endif
/* Read the device ID using code in RAM */
hwinfo_sam_read_device_id();
/* Restore code optimization settings. */
efc->EEFC_FMR = fmr;
/* Re-enable interrupts */
irq_unlock(key);
return 0;
}
SYS_INIT(hwinfo_sam_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_sam.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 740 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_imx_src
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#include <fsl_src.h>
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
{
uint32_t flags = 0;
uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && \
FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
if (reason & kSRC_IppResetPinFlag) {
flags |= RESET_PIN;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
if (reason & kSRC_PowerOnResetFlag) {
flags |= RESET_POR;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP)
if (reason & kSRC_CoreLockupResetFlag) {
flags |= RESET_CPU_LOCKUP;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && \
FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
if (reason & kSRC_LockupSysResetFlag) {
flags |= RESET_CPU_LOCKUP | RESET_SOFTWARE;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
if (reason & kSRC_CsuResetFlag) {
flags |= RESET_SECURITY;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
if (reason & kSRC_SNVSFailResetFlag) {
flags |= RESET_HARDWARE;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && \
FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
if (reason & kSRC_IppUserResetFlag) {
flags |= RESET_USER;
}
#endif
if (reason & kSRC_WatchdogResetFlag) {
flags |= RESET_WATCHDOG;
}
if (reason & kSRC_JTAGGeneratedResetFlag) {
flags |= RESET_DEBUG;
}
if (reason & kSRC_JTAGSoftwareResetFlag) {
flags |= RESET_DEBUG;
}
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST)
if (reason & kSRC_JTAGSystemResetFlag) {
flags |= RESET_DEBUG;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
if (reason & kSRC_SoftwareResetFlag) {
flags |= RESET_SOFTWARE;
}
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
if (reason & kSRC_Wdog3ResetFlag) {
flags |= RESET_WATCHDOG;
}
#endif
if (reason & kSRC_TemperatureSensorResetFlag) {
flags |= RESET_TEMPERATURE;
}
#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
if (reason & kSRC_WarmBootIndicationFlag) {
flags |= RESET_SOFTWARE;
}
#endif
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
uint32_t reason = -1;
SRC_ClearResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0), reason);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_WATCHDOG
| RESET_DEBUG
| RESET_TEMPERATURE
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && \
FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
| RESET_PIN
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
| RESET_POR
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST)
| RESET_CPU_LOCKUP
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && \
FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
| RESET_CPU_LOCKUP | RESET_SOFTWARE
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
| RESET_SECURITY
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
| RESET_HARDWARE
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && \
FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
| RESET_USER
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
| RESET_SOFTWARE
#endif
);
return 0;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_mcux_src.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,195 |
```unknown
# HW Info driver configuration options
menuconfig HWINFO
bool "Hardware Information drivers"
help
Enable hwinfo driver.
if HWINFO
module = HWINFO
module-str = HWINFO
source "subsys/logging/Kconfig.template.log_config"
config HWINFO_HAS_DRIVER
bool
help
This is an option enabled by individual drivers to signal that there is a hwinfo driver.
config HWINFO_SHELL
bool "HWINFO Shell"
depends on SHELL
help
Enable hwinfo Shell for testing.
menuconfig HWINFO_CC13XX_CC26XX
bool "TI SimpleLink CC13xx/CC26xx hwinfo driver"
default y
depends on SOC_SERIES_CC13X2_CC26X2 || SOC_SERIES_CC13X2X7_CC26X2X7
select HWINFO_HAS_DRIVER
help
Enable TI SimpleLink CC13xx/CC26xx hwinfo driver.
if HWINFO_CC13XX_CC26XX
config HWINFO_CC13XX_CC26XX_ALWAYS_USE_FACTORY_DEFAULT
bool "Ignore CCFG and always use factory value"
default y
help
Always return factory pre-programmed values, stored in FCFG and ignore
values provided in CCFG (Customer Configuration).
choice
prompt "Select MAC address type for device ID"
default HWINFO_CC13XX_CC26XX_USE_IEEE_MAC
help
Specify the MAC address type to be used as device ID by the driver.
config HWINFO_CC13XX_CC26XX_USE_IEEE_MAC
bool "Use IEEE 802.15.4 extended address"
help
Use 8-bytes length IEEE 802.15.4 extended address as device ID value.
config HWINFO_CC13XX_CC26XX_USE_BLE_MAC
bool "Use BLE MAC address"
help
Use 6-bytes length BLE MAC address as device ID value.
endchoice
endif # HWINFO_CC13XX_CC26XX
config HWINFO_STM32
bool "STM32 hwinfo"
default y
depends on SOC_FAMILY_STM32
select HWINFO_HAS_DRIVER
help
Enable STM32 hwinfo driver.
config HWINFO_NRF
bool "NRF device ID"
default y
depends on SOC_FAMILY_NORDIC_NRF
depends on SOC_SERIES_NRF54HX || NRF_SOC_SECURE_SUPPORTED
select HWINFO_HAS_DRIVER
help
Enable Nordic NRF hwinfo driver.
config HWINFO_MCUX_RCM
bool "NXP kinetis reset cause"
default y
depends on HAS_MCUX_RCM
select HWINFO_HAS_DRIVER
help
Enable NXP kinetis mcux RCM hwinfo driver.
config HWINFO_MCUX_SIM
bool "NXP kinetis SIM device ID"
default y
depends on HAS_MCUX_SIM
select HWINFO_HAS_DRIVER
help
Enable NXP kinetis mcux SIM hwinfo driver.
config HWINFO_MCUX_SRC
bool "NXP SRC reset cause"
default y
depends on HAS_MCUX_SRC
select HWINFO_HAS_DRIVER
help
Enable NXP i.MX mcux SRC hwinfo driver.
config HWINFO_MCUX_SRC_V2
bool "NXP SRC reset cause (multicore devices)"
default y
depends on HAS_MCUX_SRC_V2
select HWINFO_HAS_DRIVER
help
Enable version 2 multicore NXP i.MX mcux SRC hwinfo driver.
config HWINFO_MCUX_SYSCON
bool "NXP LPC device ID"
default y
depends on DT_HAS_NXP_LPC_UID_ENABLED
select HWINFO_HAS_DRIVER
help
Enable NXP LPC mcux hwinfo driver.
config HWINFO_IMXRT
bool "NXP i.mx RT device ID"
default y
depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
select HWINFO_HAS_DRIVER
help
Enable NXP i.mx RT hwinfo driver.
config HWINFO_RPI_PICO
bool "Raspberry Pi Pico hwinfo driver"
default y
depends on SOC_SERIES_RP2XXX
select HWINFO_HAS_DRIVER
select PICOSDK_USE_FLASH
help
Enable Raspberry Pi Pico hwinfo driver.
config HWINFO_SAM_RSTC
bool "Atmel SAM reset cause"
default y
depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
select HWINFO_HAS_DRIVER
help
Enable Atmel SAM reset cause hwinfo driver.
config HWINFO_SAM
bool "Atmel SAM device ID"
default y
depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L
select HWINFO_HAS_DRIVER
help
Enable Atmel SAM device ID hwinfo driver.
config HWINFO_SAM4L
bool "Atmel SAM4L device ID"
default y
depends on SOC_SERIES_SAM4L
select HWINFO_HAS_DRIVER
help
Enable Atmel SAM4L hwinfo driver.
config HWINFO_SAM0
bool "Atmel SAM0 device ID"
default y
depends on SOC_FAMILY_ATMEL_SAM0
select HWINFO_HAS_DRIVER
help
Enable Atmel SAM0 hwinfo driver.
config HWINFO_SMARTBOND
bool "Smartbond device reset cause"
default y
depends on SOC_FAMILY_RENESAS_SMARTBOND
select HWINFO_HAS_DRIVER
help
Enable Smartbond reset cause hwinfo driver.
config HWINFO_ESP32
bool "ESP32 device ID"
default y
depends on SOC_FAMILY_ESPRESSIF_ESP32
select HWINFO_HAS_DRIVER
help
Enable ESP32 hwinfo driver.
config HWINFO_LITEX
bool "LiteX device ID"
default y
depends on SOC_LITEX_VEXRISCV
select HWINFO_HAS_DRIVER
help
Enable LiteX hwinfo driver
config HWINFO_PSOC6
bool "Cypress PSoC-6 unique device ID"
default y
depends on SOC_FAMILY_PSOC6_LEGACY
select HWINFO_HAS_DRIVER
help
Enable Cypress PSoC-6 hwinfo driver.
config HWINFO_GECKO
bool "GECKO hwinfo"
default y
depends on SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2
depends on !SOC_SERIES_EFR32MG21
depends on !SOC_SERIES_EFR32BG22
select HWINFO_HAS_DRIVER
select SOC_GECKO_RMU
help
Enable Silabs GECKO hwinfo driver.
config HWINFO_ANDES
bool "Andes system ID"
default y
depends on SOC_FAMILY_ANDES_V5
depends on SYSCON
select HWINFO_HAS_DRIVER
help
Enable Andes hwinfo driver
config HWINFO_RW61X
bool "RW61X hwinfo"
default y
depends on SOC_SERIES_RW6XX
select HWINFO_HAS_DRIVER
help
Enable RW61X hwinfo driver
config HWINFO_AMBIQ
bool "AMBIQ hwinfo"
default y
depends on SOC_SERIES_APOLLO4X
select HWINFO_HAS_DRIVER
select AMBIQ_HAL
select AMBIQ_HAL_USE_HWINFO
help
Enable AMBIQ hwinfo driver
config HWINFO_NUMAKER
bool "NuMaker hwinfo"
default y
depends on SOC_SERIES_M46X
select HWINFO_HAS_DRIVER
select HAS_NUMAKER_FMC
help
Enable Nuvoton NuMaker hwinfo driver
config HWINFO_NUMAKER_RMC
bool "NuMaker hwinfo backed up by RMC"
default y
depends on SOC_SERIES_M2L31X
select HWINFO_HAS_DRIVER
select HAS_NUMAKER_RMC
help
Enable Nuvoton NuMaker hwinfo driver backed up by RMC
endif
``` | /content/code_sandbox/drivers/hwinfo/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,674 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_dna0
#include <zephyr/drivers/hwinfo.h>
#include <soc.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint32_t addr = DT_INST_REG_ADDR(0);
ssize_t end = MIN(length, DT_INST_REG_ADDR(0) / 4 *
CONFIG_LITEX_CSR_DATA_WIDTH / 8);
for (int i = 0; i < end; i++) {
#if CONFIG_LITEX_CSR_DATA_WIDTH == 8
buffer[i] = litex_read8(addr);
addr += 4;
#elif CONFIG_LITEX_CSR_DATA_WIDTH == 32
buffer[i] = (uint8_t)(litex_read32(addr) >> (addr % 4 * 8));
addr += 1;
#else
#error Unsupported CSR data width
#endif
}
return end;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_litex.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 220 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
struct imxrt_uid {
uint32_t id[2];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
struct imxrt_uid dev_id;
#ifdef CONFIG_SOC_SERIES_IMXRT11XX
dev_id.id[0] = sys_cpu_to_be32(OCOTP->FUSEN[17].FUSE);
dev_id.id[1] = sys_cpu_to_be32(OCOTP->FUSEN[16].FUSE);
#else
dev_id.id[0] = sys_cpu_to_be32(OCOTP->CFG2);
dev_id.id[1] = sys_cpu_to_be32(OCOTP->CFG1);
#endif
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_imxrt.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 214 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc_uid
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#define UID_WORD_COUNT (DT_INST_REG_SIZE(0) / sizeof(uint32_t))
struct uid {
uint32_t id[UID_WORD_COUNT];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
volatile const uint32_t * const uid_addr = (uint32_t *) DT_INST_REG_ADDR(0);
struct uid dev_id;
if (buffer == NULL) {
return 0;
}
for (size_t i = 0 ; i < UID_WORD_COUNT ; i++) {
dev_id.id[i] = sys_cpu_to_be32(uid_addr[i]);
}
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
``` | /content/code_sandbox/drivers/hwinfo/hwinfo_mcux_syscon.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```unknown
config CLOCK_CONTROL_SAM
bool "Atmel SAM clock control"
default y
depends on DT_HAS_ATMEL_SAM_PMC_ENABLED
help
Enable driver for Atmel SAM Clock Control.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
config CLOCK_CONTROL_AST10X0
bool "ASPEED clock control driver"
default y
depends on DT_HAS_ASPEED_AST10X0_CLOCK_ENABLED
help
This option enables the clock driver for ASPEED AST10X0 series SOC.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.aspeed | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_clock
#include <zephyr/drivers/clock_control.h>
#include <Clock_Ip.h>
#define NXP_S32_CLOCK_CONFIG_IDX CONFIG_CLOCK_CONTROL_NXP_S32_CLOCK_CONFIG_IDX
BUILD_ASSERT(CLOCK_IP_GET_FREQUENCY_API == STD_ON,
"Clock Get Frequency API must be enabled");
static int nxp_s32_clock_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
return -EINVAL;
}
Clock_Ip_EnableModuleClock(clock_name);
return 0;
}
static int nxp_s32_clock_off(const struct device *dev,
clock_control_subsys_t sub_system)
{
Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
return -EINVAL;
}
Clock_Ip_DisableModuleClock(clock_name);
return 0;
}
static int nxp_s32_clock_get_rate(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
return -EINVAL;
}
*rate = Clock_Ip_GetClockFrequency(clock_name);
return 0;
}
static int nxp_s32_clock_init(const struct device *dev)
{
Clock_Ip_StatusType status;
status = Clock_Ip_Init(&Clock_Ip_aClockConfig[NXP_S32_CLOCK_CONFIG_IDX]);
return (status == CLOCK_IP_SUCCESS ? 0 : -EIO);
}
static const struct clock_control_driver_api nxp_s32_clock_driver_api = {
.on = nxp_s32_clock_on,
.off = nxp_s32_clock_off,
.get_rate = nxp_s32_clock_get_rate,
};
DEVICE_DT_INST_DEFINE(0,
nxp_s32_clock_init,
NULL, NULL, NULL,
PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&nxp_s32_clock_driver_api);
``` | /content/code_sandbox/drivers/clock_control/clock_control_nxp_s32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 487 |
```unknown
# MCUXpresso SDK PCC
config CLOCK_CONTROL_MCUX_PCC
bool "MCUX PCC driver"
default y
depends on DT_HAS_NXP_KINETIS_PCC_ENABLED
help
Enable support for MCUX PCC driver.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.mcux_pcc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```c
/*
*
* Based on clock_control_rv32m1_pcc.c, which is:
*
*/
#define DT_DRV_COMPAT nxp_kinetis_pcc
#include <errno.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_clock.h>
#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control_mcux_pcc);
struct mcux_pcc_config {
uint32_t base_address;
uint32_t *clocks;
uint32_t clock_num;
};
#define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
#ifndef MAKE_PCC_REGADDR
#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
#endif
static inline int get_clock_encoding(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *clock_encoding)
{
const struct mcux_pcc_config *cfg;
uint32_t clock_name;
cfg = dev->config;
clock_name = POINTER_TO_UINT(sub_system);
if (!cfg->clock_num) {
*clock_encoding = MAKE_PCC_REGADDR(DEV_BASE(dev), clock_name);
return 0;
}
/* sanity check */
if (clock_name >= cfg->clock_num) {
return -EINVAL;
}
*clock_encoding = cfg->clocks[clock_name];
return 0;
}
static int mcux_pcc_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
uint32_t clock_encoding;
int ret;
ret = get_clock_encoding(dev, sub_system, &clock_encoding);
if (ret < 0) {
return ret;
}
CLOCK_EnableClock(clock_encoding);
return 0;
}
static int mcux_pcc_off(const struct device *dev,
clock_control_subsys_t sub_system)
{
uint32_t clock_encoding;
int ret;
ret = get_clock_encoding(dev, sub_system, &clock_encoding);
if (ret < 0) {
return ret;
}
CLOCK_DisableClock(clock_encoding);
return 0;
}
static int mcux_pcc_get_rate(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
uint32_t clock_encoding;
int ret;
ret = get_clock_encoding(dev, sub_system, &clock_encoding);
if (ret < 0) {
return ret;
}
*rate = CLOCK_GetIpFreq(clock_encoding);
return 0;
}
static const struct clock_control_driver_api mcux_pcc_api = {
.on = mcux_pcc_on,
.off = mcux_pcc_off,
.get_rate = mcux_pcc_get_rate,
};
static int mcux_pcc_init(const struct device *dev)
{
#ifdef CONFIG_SOC_MIMX8UD7
/* 8ULP's XTAL is set to 24MHz on EVK9. We keep
* this as SOC level because this should also be
* the case for the EVK board.
*/
CLOCK_SetXtal0Freq(24000000);
#endif /* CONFIG_SOC_MIMX8UD7 */
return 0;
}
#ifdef CONFIG_SOC_MIMX8UD7
static uint32_t clocks[] = {
/* clocks managed through PCC4 */
kCLOCK_Lpuart7,
};
#else
/* this is empty for SOCs which don't need a translation from
* the clock ID passed through the DTS and the clock ID encoding
* from the HAL. For these SOCs, the clock ID will be built based
* on the value passed from the DTS and the PCC base.
*/
static uint32_t clocks[] = {};
#endif /* CONFIG_SOC_MIMX8UD7 */
#define MCUX_PCC_INIT(inst) \
static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
.base_address = DT_INST_REG_ADDR(inst), \
.clocks = clocks, \
.clock_num = ARRAY_SIZE(clocks), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, \
mcux_pcc_init, \
NULL, \
NULL, &mcux_pcc##inst##_config, \
PRE_KERNEL_1, \
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
&mcux_pcc_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_PCC_INIT)
``` | /content/code_sandbox/drivers/clock_control/clock_control_mcux_pcc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 950 |
```unknown
# Ambiq Clock Control Driver configuration options
#
#
#
config CLOCK_CONTROL_AMBIQ
bool "AMBIQ clock control driver"
default y
depends on DT_HAS_AMBIQ_CLKCTRL_ENABLED
select AMBIQ_HAL
help
Enable driver for Ambiq clock control.
``` | /content/code_sandbox/drivers/clock_control/Kconfig.ambiq | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/sys/time_units.h>
#include "clock_stm32_ll_common.h"
#if defined(STM32_PLL_ENABLED)
/**
* @brief Return PLL source
*/
__unused
static uint32_t get_pll_source(void)
{
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
return LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
return LL_RCC_PLLSOURCE_HSE;
}
__ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief get the pll source frequency
*/
__unused
uint32_t get_pllsrc_frequency(void)
{
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
return STM32_HSI_FREQ;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
return STM32_HSE_FREQ;
}
__ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief Set up pll configuration
*/
__unused
void config_pll_sysclock(void)
{
/* set power boost mode for sys clock greater than 150MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
LL_PWR_EnableRange1BoostMode();
}
LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
pllm(STM32_PLL_M_DIVISOR),
STM32_PLL_N_MULTIPLIER,
pllr(STM32_PLL_R_DIVISOR));
LL_RCC_PLL_EnableDomain_SYS();
}
#endif /* defined(STM32_PLL_ENABLED) */
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Enable the power interface clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
}
``` | /content/code_sandbox/drivers/clock_control/clock_stm32g4.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 451 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_numaker_scc
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/logging/log.h>
#include <NuMicro.h>
LOG_MODULE_REGISTER(clock_control_numaker_scc, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
struct numaker_scc_config {
uint32_t clk_base;
int hxt;
int lxt;
int hirc48;
uint32_t clk_pclkdiv;
uint32_t core_clock;
};
static inline int numaker_scc_on(const struct device *dev, clock_control_subsys_t subsys)
{
ARG_UNUSED(dev);
struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
SYS_UnlockReg();
CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx);
SYS_LockReg();
} else {
return -EINVAL;
}
return 0;
}
static inline int numaker_scc_off(const struct device *dev, clock_control_subsys_t subsys)
{
ARG_UNUSED(dev);
struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
SYS_UnlockReg();
CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx);
SYS_LockReg();
} else {
return -EINVAL;
}
return 0;
}
static inline int numaker_scc_get_rate(const struct device *dev, clock_control_subsys_t subsys,
uint32_t *rate)
{
ARG_UNUSED(dev);
ARG_UNUSED(subsys);
ARG_UNUSED(rate);
return -ENOTSUP;
}
static inline int numaker_scc_set_rate(const struct device *dev, clock_control_subsys_t subsys,
clock_control_subsys_rate_t rate)
{
ARG_UNUSED(dev);
ARG_UNUSED(subsys);
ARG_UNUSED(rate);
return -ENOTSUP;
}
static inline int numaker_scc_configure(const struct device *dev, clock_control_subsys_t subsys,
void *data)
{
ARG_UNUSED(dev);
ARG_UNUSED(data);
struct numaker_scc_subsys *scc_subsys = (struct numaker_scc_subsys *)subsys;
if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
SYS_UnlockReg();
CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src,
scc_subsys->pcc.clk_div);
SYS_LockReg();
} else {
return -EINVAL;
}
return 0;
}
/* System clock controller driver registration */
static const struct clock_control_driver_api numaker_scc_api = {
.on = numaker_scc_on,
.off = numaker_scc_off,
.get_rate = numaker_scc_get_rate,
.set_rate = numaker_scc_set_rate,
.configure = numaker_scc_configure,
};
/* At most one compatible with status "okay" */
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
"Requires at most one compatible with status \"okay\"");
#define LOG_OSC_SW(osc, sw) \
if (sw == NUMAKER_SCC_CLKSW_ENABLE) { \
LOG_DBG("Enable " #osc); \
} else if (sw == NUMAKER_SCC_CLKSW_DISABLE) { \
LOG_DBG("Disable " #osc); \
}
static int numaker_scc_init(const struct device *dev)
{
const struct numaker_scc_config *cfg = dev->config;
LOG_DBG("CLK base: 0x%08x", cfg->clk_base);
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
LOG_OSC_SW(HXT, cfg->hxt);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
LOG_OSC_SW(LXT, cfg->lxt);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
LOG_OSC_SW(HIRC48, cfg->hirc48);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
LOG_DBG("CLK_PCLKDIV: 0x%08x", cfg->clk_pclkdiv);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
LOG_DBG("Core clock: %d (Hz)", cfg->core_clock);
#endif
/*
* z_arm_platform_init() will respect above configurations and
* actually take charge of system clock control initialization.
*/
SystemCoreClockUpdate();
LOG_DBG("SystemCoreClock: %d (Hz)", SystemCoreClock);
return 0;
}
#define NUMICRO_SCC_INIT(inst) \
static const struct numaker_scc_config numaker_scc_config_##inst = { \
.clk_base = DT_INST_REG_ADDR(inst), \
.hxt = DT_INST_ENUM_IDX_OR(inst, hxt, NUMAKER_SCC_CLKSW_UNTOUCHED), \
.lxt = DT_INST_ENUM_IDX_OR(inst, lxt, NUMAKER_SCC_CLKSW_UNTOUCHED), \
.hirc48 = DT_INST_ENUM_IDX_OR(inst, hirc48, NUMAKER_SCC_CLKSW_UNTOUCHED), \
.clk_pclkdiv = DT_INST_PROP_OR(inst, clk_pclkdiv, 0), \
.core_clock = DT_INST_PROP_OR(inst, core_clock, 0), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, numaker_scc_init, NULL, NULL, &numaker_scc_config_##inst, \
PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &numaker_scc_api);
DT_INST_FOREACH_STATUS_OKAY(NUMICRO_SCC_INIT);
``` | /content/code_sandbox/drivers/clock_control/clock_control_numaker_scc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,315 |
```unknown
# LPC11U6X MCU clock control driver config
menuconfig CLOCK_CONTROL_LPC11U6X
bool "LPC11U6X Reset and clock control"
default y
depends on DT_HAS_NXP_LPC11U6X_SYSCON_ENABLED
help
Enable driver for reset and clock control used in
LPC11U6X MCUs
if CLOCK_CONTROL_LPC11U6X
config CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1
bool "SRAM1"
help
Enable SRAM1
config CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM
bool "USB RAM"
help
Enable USB RAM
choice CLOCK_CONTROL_LPC11U6X_PLL_SRC
prompt "LPC11U6X PLL Clock source"
config CLOCK_CONTROL_LPC11U6X_PLL_SRC_IRC
bool "IRC"
help
Use the internal oscillator as the clock source for the PLL
config CLOCK_CONTROL_LPC11U6X_PLL_SRC_SYSOSC
bool "SYSOSC"
help
Use the system oscillator as the clock source for the PLL
endchoice # CLOCK_CONTROL_LPC11U6X_PLL_SRC
endif # CLOCK_CONTROL_LPC11U6X
``` | /content/code_sandbox/drivers/clock_control/Kconfig.lpc11u6x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 260 |
```unknown
# LiteX SoC Builder clock control driver
config CLOCK_CONTROL_LITEX
bool "LiteX MMCM clock control"
default y
depends on DT_HAS_LITEX_CLK_ENABLED
help
This option enables LiteX clock control driver.
It gives ability to change clock parameters
such as phase, duty cycle, frequency for up to 7
clock outputs
``` | /content/code_sandbox/drivers/clock_control/Kconfig.litex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```c
/*
*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defined(STM32_PLL_ENABLED)
/**
* @brief Return PLL source
*/
__unused
static uint32_t get_pll_source(void)
{
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
return LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
return LL_RCC_PLLSOURCE_HSE;
}
__ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief get the pll source frequency
*/
__unused
uint32_t get_pllsrc_frequency(void)
{
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
return STM32_HSI_FREQ;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
return STM32_HSE_FREQ;
}
__ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief Set up pll configuration
*/
__unused
void config_pll_sysclock(void)
{
#if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR)
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));
#endif
LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
pllm(STM32_PLL_M_DIVISOR),
STM32_PLL_N_MULTIPLIER,
pllp(STM32_PLL_P_DIVISOR));
#if defined(CONFIG_SOC_SERIES_STM32F7X)
/* Assuming we stay on Power Scale default value: Power Scale 1 */
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
/* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL
* locking phase since the system will be stalled during the switch
* (ODSW) but the PLL clock system will be running during the locking
* phase. See reference manual (RM0431) 4.1.4 Voltage regulator
* Sub section: Entering Over-drive mode.
*/
LL_RCC_PLL_Enable();
/* Set Overdrive if needed before configuring the Flash Latency */
LL_PWR_EnableOverDriveMode();
while (LL_PWR_IsActiveFlag_OD() != 1) {
/* Wait for OverDrive mode ready */
}
LL_PWR_EnableOverDriveSwitching();
while (LL_PWR_IsActiveFlag_ODSW() != 1) {
/* Wait for OverDrive switch ready */
}
/* The PLL could still not be locked when returning to the caller
* function. But the caller doesn't know we've turned on the PLL
* for the overdrive function. The caller will try to turn on the PLL
* And start waiting for the PLL locking phase to complete.
*/
}
#endif /* CONFIG_SOC_SERIES_STM32F7X */
}
#endif /* defined(STM32_PLL_ENABLED) */
#ifdef STM32_PLLI2S_ENABLED
/**
* @brief Set up PLL I2S configuration
*/
__unused
void config_plli2s(void)
{
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_plli2s_clock)
LL_RCC_PLLI2S_ConfigDomain_I2S(get_pll_source(),
pllm(STM32_PLLI2S_M_DIVISOR),
STM32_PLLI2S_N_MULTIPLIER,
plli2sr(STM32_PLLI2S_R_DIVISOR));
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f412_plli2s_clock)
LL_RCC_PLL_ConfigDomain_I2S(get_pll_source(),
plli2sm(STM32_PLLI2S_M_DIVISOR),
STM32_PLLI2S_N_MULTIPLIER,
plli2sr(STM32_PLLI2S_R_DIVISOR));
#endif
}
#endif /* STM32_PLLI2S_ENABLED */
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Power Interface clock enabled by default */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
}
``` | /content/code_sandbox/drivers/clock_control/clock_stm32f2_f4_f7.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 953 |
```c
/*
*
*/
#define DT_DRV_COMPAT raspberrypi_pico_clock_controller
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/dt-bindings/clock/rpi_pico_clock.h>
#include <hardware/clocks.h>
#include <hardware/xosc.h>
#include <hardware/structs/rosc.h>
#include <hardware/pll.h>
#include <hardware/watchdog.h>
#include <hardware/resets.h>
/* Undefine to prevent conflicts with header definitions */
#undef pll_sys
#undef pll_usb
#define CTRL_SRC_LSB CLOCKS_CLK_REF_CTRL_SRC_LSB
#define CTRL_SRC_BITS CLOCKS_CLK_REF_CTRL_SRC_BITS
#define CTRL_AUXSRC_LSB CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB
#define CTRL_AUXSRC_BITS CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS
#define CTRL_ENABLE_BITS CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS
#define DIV_FRAC_BITS CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS
#define DIV_INT_BITS CLOCKS_CLK_GPOUT0_DIV_INT_BITS
#define DIV_INT_LSB CLOCKS_CLK_GPOUT0_DIV_INT_LSB
#define PLL_VCO_FREQ_MIN 750000000
#define PLL_VCO_FREQ_MAX 1600000000
#define PLL_FB_DIV_MIN 16
#define PLL_FB_DIV_MAX 320
#define PLL_POST_DIV_MIN 1
#define PLL_POST_DIV_MAX 7
#define ROSC_PHASE_PASSWD_VALUE_PASS _u(0xAA)
#define STAGE_DS(n) \
(COND_CODE_1( \
DT_PROP_HAS_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n), \
(DT_PROP_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n) & \
ROSC_FREQA_DS0_BITS), \
(0)) \
<< (n * 3))
#define CLK_SRC_IS(clk, src) \
DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
DT_INST_CLOCKS_CTLR_BY_NAME(0, src))
#define REF_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_div)
#define FB_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), fb_div)
#define POST_DIV1(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div1)
#define POST_DIV2(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div2)
#define VCO_FREQ(pll) ((CLOCK_FREQ_xosc / REF_DIV(pll)) * FB_DIV(pll))
/*
* Using the 'clock-names[0]' for expanding macro to frequency value.
* The 'clock-names[0]' is set same as label value that given to the node itself.
* Use it for traverse clock tree to find root of clock source.
*/
#define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk)
#define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \
clock_names, 0)
#define SRC_CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, SRC_CLOCK(clk))
#define PLL_FREQ(pll) \
(DT_PROP(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), 0), clock_frequency) / \
REF_DIV(pll) * FB_DIV(pll) / POST_DIV1(pll) / POST_DIV2(pll))
#define CLOCK_FREQ_clk_gpout0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout0), clock_frequency)
#define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency)
#define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency)
#define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency)
#define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency)
#define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency)
#define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency)
#define CLOCK_FREQ_clk_adc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_adc), clock_frequency)
#define CLOCK_FREQ_clk_rtc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_rtc), clock_frequency)
#define CLOCK_FREQ_clk_peri DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_peri), clock_frequency)
#define CLOCK_FREQ_xosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, xosc), clock_frequency)
#define CLOCK_FREQ_rosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
#define CLOCK_FREQ_rosc_ph DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
#define CLOCK_FREQ_gpin0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0), clock_frequency)
#define CLOCK_FREQ_gpin1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1), clock_frequency)
#define CLOCK_FREQ_pll_sys PLL_FREQ(pll_sys)
#define CLOCK_FREQ_pll_usb PLL_FREQ(pll_usb)
#define CLOCK_AUX_SOURCE(clk) _CONCAT(_CONCAT(AUXSTEM_, clk), _CONCAT(AUXSRC_, SRC_CLOCK(clk)))
#define AUXSRC_xosc XOSC_CLKSRC
#define AUXSRC_rosc ROSC_CLKSRC
#define AUXSRC_rosc_ph ROSC_CLKSRC_PH
#define AUXSRC_pll_sys CLKSRC_PLL_SYS
#define AUXSRC_pll_usb CLKSRC_PLL_USB
#define AUXSRC_clk_ref CLK_REF
#define AUXSRC_clk_sys CLK_SYS
#define AUXSRC_clk_usb CLK_USB
#define AUXSRC_clk_adc CLK_ADC
#define AUXSRC_clk_rtc CLK_RTC
#define AUXSRC_clk_gpin0 CLKSRC_GPIN0
#define AUXSRC_clk_gpin1 CLKSRC_GPIN1
#define AUXSTEM_clk_gpout0 CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_gpout1 CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_gpout2 CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_gpout3 CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_ref CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_
#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
#define TUPLE_ENTRY(n, p, i) \
{ \
_CONCAT(RPI_PICO_CLKID_, DT_INST_STRING_UPPER_TOKEN_BY_IDX(0, clock_names, i)), \
COND_CODE_1( \
DT_PROP_HAS_IDX(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
clocks, 0), \
(_CONCAT(RPI_PICO_CLKID_, \
DT_STRING_UPPER_TOKEN_BY_IDX( \
DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
clock_names, 0))), \
(-1)) \
}
enum rpi_pico_clkid {
rpi_pico_clkid_none = -1,
rpi_pico_clkid_clk_gpout0 = RPI_PICO_CLKID_CLK_GPOUT0,
rpi_pico_clkid_clk_gpout1 = RPI_PICO_CLKID_CLK_GPOUT1,
rpi_pico_clkid_clk_gpout2 = RPI_PICO_CLKID_CLK_GPOUT2,
rpi_pico_clkid_clk_gpout3 = RPI_PICO_CLKID_CLK_GPOUT3,
rpi_pico_clkid_clk_ref = RPI_PICO_CLKID_CLK_REF,
rpi_pico_clkid_clk_sys = RPI_PICO_CLKID_CLK_SYS,
rpi_pico_clkid_clk_peri = RPI_PICO_CLKID_CLK_PERI,
rpi_pico_clkid_clk_usb = RPI_PICO_CLKID_CLK_USB,
rpi_pico_clkid_clk_adc = RPI_PICO_CLKID_CLK_ADC,
rpi_pico_clkid_clk_rtc = RPI_PICO_CLKID_CLK_RTC,
rpi_pico_clkid_pll_sys = RPI_PICO_CLKID_PLL_SYS,
rpi_pico_clkid_pll_usb = RPI_PICO_CLKID_PLL_USB,
rpi_pico_clkid_xosc = RPI_PICO_CLKID_XOSC,
rpi_pico_clkid_rosc = RPI_PICO_CLKID_ROSC,
rpi_pico_clkid_rosc_ph = RPI_PICO_CLKID_ROSC_PH,
rpi_pico_clkid_gpin0 = RPI_PICO_CLKID_GPIN0,
rpi_pico_clkid_gpin1 = RPI_PICO_CLKID_GPIN1,
END_OF_RPI_PICO_CLKID,
};
struct rpi_pico_clkid_tuple {
enum rpi_pico_clkid clk;
enum rpi_pico_clkid parent;
};
struct rpi_pico_clk_config {
uint32_t source;
uint32_t aux_source;
uint32_t rate;
uint32_t source_rate;
};
struct rpi_pico_pll_config {
uint32_t ref_div;
uint32_t fb_div;
uint32_t post_div1;
uint32_t post_div2;
};
struct rpi_pico_rosc_config {
uint32_t phase;
uint32_t range;
uint32_t div;
uint32_t code;
};
struct rpi_pico_gpin_config {
uint32_t frequency;
};
struct clock_control_rpi_pico_config {
clocks_hw_t *const clocks_regs;
xosc_hw_t *const xosc_regs;
pll_hw_t *const pll_sys_regs;
pll_hw_t *const pll_usb_regs;
rosc_hw_t *const rosc_regs;
const struct pinctrl_dev_config *pcfg;
struct rpi_pico_pll_config plls_data[RPI_PICO_PLL_COUNT];
struct rpi_pico_clk_config clocks_data[RPI_PICO_CLOCK_COUNT];
struct rpi_pico_rosc_config rosc_data;
struct rpi_pico_gpin_config gpin_data[RPI_PICO_GPIN_COUNT];
};
struct clock_control_rpi_pico_data {
uint32_t rosc_freq;
uint32_t rosc_ph_freq;
};
uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys_t sys)
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
fc_hw_t *fc0 = &config->clocks_regs->fc0;
uint32_t fc0_id;
switch (clkid) {
case rpi_pico_clkid_clk_ref:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_REF;
break;
case rpi_pico_clkid_clk_sys:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_SYS;
break;
case rpi_pico_clkid_clk_peri:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_PERI;
break;
case rpi_pico_clkid_clk_usb:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_USB;
break;
case rpi_pico_clkid_clk_adc:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC;
break;
case rpi_pico_clkid_clk_rtc:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC;
break;
case rpi_pico_clkid_pll_sys:
fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY;
break;
case rpi_pico_clkid_pll_usb:
fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY;
break;
case rpi_pico_clkid_xosc:
fc0_id = CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC;
break;
case rpi_pico_clkid_rosc:
fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC;
break;
case rpi_pico_clkid_rosc_ph:
fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH;
break;
case rpi_pico_clkid_gpin0:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
break;
case rpi_pico_clkid_gpin1:
fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
break;
default:
return -1;
}
(void)frequency_count_khz(fc0_id);
return ((fc0->result >> CLOCKS_FC0_RESULT_KHZ_LSB) * 1000) +
((fc0->result & CLOCKS_FC0_RESULT_FRAC_BITS) * 1000 / CLOCKS_FC0_RESULT_FRAC_BITS);
}
static int rpi_pico_rosc_write(const struct device *dev, io_rw_32 *addr, uint32_t value)
{
hw_clear_bits(&rosc_hw->status, ROSC_STATUS_BADWRITE_BITS);
if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
return -EINVAL;
}
*addr = value;
if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
return -EINVAL;
}
return 0;
}
/**
* Get source clock id of this clock
*
* @param dev pointer to clock device
* @param id id of this clock
* @return parent clock id
*/
static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid id)
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid srcid = rpi_pico_clkid_none;
if (id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 ||
id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) {
const static enum rpi_pico_clkid table[] = {
rpi_pico_clkid_pll_sys,
rpi_pico_clkid_gpin0,
rpi_pico_clkid_gpin1,
rpi_pico_clkid_pll_usb,
rpi_pico_clkid_rosc_ph,
rpi_pico_clkid_xosc,
rpi_pico_clkid_clk_sys,
rpi_pico_clkid_clk_usb,
rpi_pico_clkid_clk_adc,
rpi_pico_clkid_clk_rtc,
rpi_pico_clkid_clk_ref,
};
clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
srcid = table[aux];
} else if (id == rpi_pico_clkid_clk_ref) {
const static enum rpi_pico_clkid table[] = {
rpi_pico_clkid_pll_usb,
rpi_pico_clkid_gpin0,
rpi_pico_clkid_gpin1,
};
clock_hw_t *clock_hw = &clocks_hw->clk[id];
uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH) {
srcid = rpi_pico_clkid_rosc_ph;
} else if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC) {
srcid = rpi_pico_clkid_xosc;
} else {
srcid = table[aux];
}
} else if (id == rpi_pico_clkid_clk_sys) {
const static enum rpi_pico_clkid table[] = {
rpi_pico_clkid_pll_sys,
rpi_pico_clkid_pll_usb,
rpi_pico_clkid_rosc,
rpi_pico_clkid_xosc,
rpi_pico_clkid_gpin0,
rpi_pico_clkid_gpin1,
};
clock_hw_t *clock_hw = &clocks_hw->clk[id];
uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF) {
srcid = rpi_pico_clkid_clk_ref;
} else {
srcid = table[aux];
}
} else if (id == rpi_pico_clkid_clk_peri) {
const static enum rpi_pico_clkid table[] = {
rpi_pico_clkid_clk_sys,
rpi_pico_clkid_pll_sys,
rpi_pico_clkid_pll_usb,
rpi_pico_clkid_rosc_ph,
rpi_pico_clkid_xosc,
rpi_pico_clkid_gpin0,
rpi_pico_clkid_gpin1,
};
clock_hw_t *clock_hw = &clocks_hw->clk[id];
uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
srcid = table[aux];
} else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc ||
id == rpi_pico_clkid_clk_rtc) {
const static enum rpi_pico_clkid table[] = {
rpi_pico_clkid_pll_usb,
rpi_pico_clkid_pll_sys,
rpi_pico_clkid_rosc_ph,
rpi_pico_clkid_xosc,
rpi_pico_clkid_gpin0,
rpi_pico_clkid_gpin1,
};
clock_hw_t *clock_hw = &clocks_hw->clk[id];
uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
srcid = table[aux];
} else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
srcid = rpi_pico_clkid_xosc;
}
return srcid;
}
/**
* Query clock is enabled or not
*
* @param dev pointer to clock device
* @param id id of clock
* @return true if the clock enabled, otherwith false
*/
static bool rpi_pico_is_clock_enabled(const struct device *dev, enum rpi_pico_clkid id)
{
const struct clock_control_rpi_pico_config *config = dev->config;
if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_ref) {
return true;
} else if (id == rpi_pico_clkid_clk_usb ||
id == rpi_pico_clkid_clk_peri ||
id == rpi_pico_clkid_clk_adc ||
id == rpi_pico_clkid_clk_rtc ||
id == rpi_pico_clkid_clk_gpout0 ||
id == rpi_pico_clkid_clk_gpout1 ||
id == rpi_pico_clkid_clk_gpout2 ||
id == rpi_pico_clkid_clk_gpout3) {
clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
if (clock_hw->ctrl & CTRL_ENABLE_BITS) {
return true;
}
} else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
: config->pll_usb_regs;
if (!(pll->pwr & (PLL_PWR_VCOPD_BITS | PLL_PWR_POSTDIVPD_BITS | PLL_PWR_PD_BITS))) {
return true;
}
} else if (id == rpi_pico_clkid_xosc) {
if (config->xosc_regs->status & XOSC_STATUS_ENABLED_BITS) {
return true;
}
} else if (id == rpi_pico_clkid_rosc || id == rpi_pico_clkid_rosc_ph) {
return true;
}
return false;
}
/**
* Calculate clock frequency with traversing clock tree.
*
* @param dev pointer to clock device
* @param id id of clock
* @return frequency value or 0 if disabled
*/
static float rpi_pico_calc_clock_freq(const struct device *dev, enum rpi_pico_clkid id)
{
const struct clock_control_rpi_pico_config *config = dev->config;
struct clock_control_rpi_pico_data *data = dev->data;
float freq = 0.f;
if (!rpi_pico_is_clock_enabled(dev, id)) {
return freq;
}
if (id == rpi_pico_clkid_clk_sys ||
id == rpi_pico_clkid_clk_usb ||
id == rpi_pico_clkid_clk_adc ||
id == rpi_pico_clkid_clk_rtc ||
id == rpi_pico_clkid_clk_ref ||
id == rpi_pico_clkid_clk_gpout0 ||
id == rpi_pico_clkid_clk_gpout1 ||
id == rpi_pico_clkid_clk_gpout2 ||
id == rpi_pico_clkid_clk_gpout3) {
clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) /
(((clock_hw->div & DIV_INT_BITS) >> DIV_INT_LSB) +
((clock_hw->div & DIV_FRAC_BITS) / (float)DIV_FRAC_BITS));
} else if (id == rpi_pico_clkid_clk_peri) {
freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id));
} else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
: config->pll_usb_regs;
freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) *
(pll->fbdiv_int) / (pll->cs & PLL_CS_REFDIV_BITS) /
((pll->prim & PLL_PRIM_POSTDIV1_BITS) >> PLL_PRIM_POSTDIV1_LSB) /
((pll->prim & PLL_PRIM_POSTDIV2_BITS) >> PLL_PRIM_POSTDIV2_LSB);
} else if (id == rpi_pico_clkid_xosc) {
freq = CLOCK_FREQ_xosc;
} else if (id == rpi_pico_clkid_rosc) {
freq = data->rosc_freq;
} else if (id == rpi_pico_clkid_rosc_ph) {
freq = data->rosc_ph_freq;
}
return freq;
}
static int rpi_pico_is_valid_clock_index(enum rpi_pico_clkid index)
{
if (index >= END_OF_RPI_PICO_CLKID) {
return -EINVAL;
}
return 0;
}
static int clock_control_rpi_pico_on(const struct device *dev, clock_control_subsys_t sys)
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
switch (clkid) {
case rpi_pico_clkid_pll_sys:
hw_clear_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
break;
case rpi_pico_clkid_pll_usb:
hw_clear_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
break;
default:
hw_set_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
}
return 0;
}
static int clock_control_rpi_pico_off(const struct device *dev, clock_control_subsys_t sys)
{
const struct clock_control_rpi_pico_config *config = dev->config;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
switch (clkid) {
case rpi_pico_clkid_pll_sys:
hw_set_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
break;
case rpi_pico_clkid_pll_usb:
hw_set_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
break;
default:
hw_clear_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
}
return 0;
}
static enum clock_control_status clock_control_rpi_pico_get_status(const struct device *dev,
clock_control_subsys_t sys)
{
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
if (rpi_pico_is_clock_enabled(dev, clkid)) {
return CLOCK_CONTROL_STATUS_ON;
}
return CLOCK_CONTROL_STATUS_OFF;
}
static int clock_control_rpi_pico_get_rate(const struct device *dev, clock_control_subsys_t sys,
uint32_t *rate)
{
struct clock_control_rpi_pico_data *data = dev->data;
enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
if (rpi_pico_is_valid_clock_index(clkid) < 0) {
return -EINVAL;
}
if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
if (clkid == rpi_pico_clkid_rosc) {
data->rosc_freq = rpi_pico_frequency_count(dev, sys);
} else if (clkid == rpi_pico_clkid_rosc_ph) {
data->rosc_ph_freq = rpi_pico_frequency_count(dev, sys);
}
}
*rate = (int)rpi_pico_calc_clock_freq(dev, clkid);
return 0;
}
void rpi_pico_clkid_tuple_swap(struct rpi_pico_clkid_tuple *lhs, struct rpi_pico_clkid_tuple *rhs)
{
struct rpi_pico_clkid_tuple tmp = *lhs;
*lhs = *rhs;
*rhs = tmp;
}
void rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple *tuples, size_t len)
{
uint32_t sorted_idx = 0;
uint32_t checked_idx = 0;
uint32_t target = -1;
while (sorted_idx < len) {
for (uint32_t i = sorted_idx; i < len; i++) {
if (tuples[i].parent == target) {
rpi_pico_clkid_tuple_swap(&tuples[sorted_idx], &tuples[i]);
sorted_idx++;
}
}
target = tuples[checked_idx++].clk;
}
}
static int clock_control_rpi_pico_init(const struct device *dev)
{
const struct clock_control_rpi_pico_config *config = dev->config;
struct clock_control_rpi_pico_data *data = dev->data;
clocks_hw_t *clocks_regs = config->clocks_regs;
rosc_hw_t *rosc_regs = config->rosc_regs;
pll_hw_t *plls[] = {config->pll_sys_regs, config->pll_usb_regs};
struct rpi_pico_clkid_tuple tuples[] = {
DT_INST_FOREACH_PROP_ELEM_SEP(0, clock_names, TUPLE_ENTRY, (,))};
uint32_t rosc_div;
int ret;
/* Reset all function before clock configuring */
reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS |
RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS |
RESETS_RESET_PLL_USB_BITS | RESETS_RESET_SYSCFG_BITS |
RESETS_RESET_PLL_SYS_BITS));
unreset_block_wait(RESETS_RESET_BITS &
~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS |
RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
RESETS_RESET_USBCTRL_BITS | RESETS_RESET_PWM_BITS));
/* Start tick in watchdog */
watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS);
clocks_regs->resus.ctrl = 0;
/* Configure xosc */
xosc_init();
/* Before we touch PLLs, switch sys and ref cleanly away from their aux sources. */
clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].ctrl &= ~CTRL_SRC_BITS;
while (clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].selected != 0x1) {
;
}
clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].ctrl &= ~CTRL_SRC_BITS;
while (clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].selected != 0x1) {
;
}
/* Configure pll */
for (uint32_t i = 0; i < RPI_PICO_PLL_COUNT; i++) {
pll_init(plls[i], config->plls_data[i].ref_div,
CLOCK_FREQ_xosc * config->plls_data[i].fb_div,
config->plls_data[i].post_div1, config->plls_data[i].post_div2);
}
/* Configure clocks */
rpi_pico_clkid_tuple_reorder_by_dependencies(tuples, ARRAY_SIZE(tuples));
for (uint32_t i = 0; i < ARRAY_SIZE(tuples); i++) {
if (tuples[i].clk < 0 || tuples[i].clk >= RPI_PICO_CLOCK_COUNT) {
continue;
}
if (!(clock_configure(tuples[i].clk, config->clocks_data[tuples[i].clk].source,
config->clocks_data[tuples[i].clk].aux_source,
config->clocks_data[tuples[i].clk].source_rate,
config->clocks_data[tuples[i].clk].rate))) {
return -EINVAL;
}
}
hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout0].ctrl, CTRL_ENABLE_BITS);
hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout1].ctrl, CTRL_ENABLE_BITS);
hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout2].ctrl, CTRL_ENABLE_BITS);
hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout3].ctrl, CTRL_ENABLE_BITS);
/* Configure rosc */
ret = rpi_pico_rosc_write(dev, &rosc_regs->phase,
(ROSC_PHASE_PASSWD_VALUE_PASS << ROSC_PHASE_PASSWD_LSB) |
config->rosc_data.phase);
if (ret < 0) {
return ret;
}
ret = rpi_pico_rosc_write(dev, &rosc_regs->ctrl,
(ROSC_CTRL_ENABLE_VALUE_ENABLE << ROSC_CTRL_ENABLE_LSB) |
config->rosc_data.range);
if (ret < 0) {
return ret;
}
if (config->rosc_data.div <= 0) {
rosc_div = ROSC_DIV_VALUE_PASS + 1;
} else if (config->rosc_data.div > 31) {
rosc_div = ROSC_DIV_VALUE_PASS;
} else {
rosc_div = ROSC_DIV_VALUE_PASS + config->rosc_data.div;
}
ret = rpi_pico_rosc_write(dev, &rosc_regs->div, rosc_div);
if (ret < 0) {
return ret;
}
ret = rpi_pico_rosc_write(dev, &rosc_regs->freqa,
(ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
(config->rosc_data.code & UINT16_MAX));
if (ret < 0) {
return ret;
}
ret = rpi_pico_rosc_write(dev, &rosc_regs->freqb,
(ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
(config->rosc_data.code >> 16));
if (ret < 0) {
return ret;
}
unreset_block_wait(RESETS_RESET_BITS);
if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
data->rosc_freq =
rpi_pico_frequency_count(dev, (clock_control_subsys_t)rpi_pico_clkid_rosc);
data->rosc_ph_freq = rpi_pico_frequency_count(
dev, (clock_control_subsys_t)rpi_pico_clkid_rosc_ph);
}
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
return 0;
}
static const struct clock_control_driver_api clock_control_rpi_pico_api = {
.on = clock_control_rpi_pico_on,
.off = clock_control_rpi_pico_off,
.get_rate = clock_control_rpi_pico_get_rate,
.get_status = clock_control_rpi_pico_get_status,
};
BUILD_ASSERT((VCO_FREQ(pll_sys) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_sys) <= PLL_VCO_FREQ_MAX) &&
(VCO_FREQ(pll_sys) >= (CLOCK_FREQ_xosc / REF_DIV(pll_sys) * 16)),
"pll_sys: vco_freq is out of range");
BUILD_ASSERT((FB_DIV(pll_sys) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_sys) <= PLL_FB_DIV_MAX),
"pll_sys: fb-div is out of range");
BUILD_ASSERT((POST_DIV1(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_sys) <= PLL_POST_DIV_MAX),
"pll_sys: post-div1 is out of range");
BUILD_ASSERT((POST_DIV2(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_sys) <= PLL_POST_DIV_MAX),
"pll_sys: post-div2 is out of range");
BUILD_ASSERT((VCO_FREQ(pll_usb) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_usb) <= PLL_VCO_FREQ_MAX) &&
(VCO_FREQ(pll_usb) >= (CLOCK_FREQ_xosc / REF_DIV(pll_usb) * 16)),
"pll_usb: vco_freq is out of range");
BUILD_ASSERT((FB_DIV(pll_usb) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_usb) <= PLL_FB_DIV_MAX),
"pll_usb: fb-div is out of range");
BUILD_ASSERT((POST_DIV1(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_usb) <= PLL_POST_DIV_MAX),
"pll_usb: post-div is out of range");
BUILD_ASSERT((POST_DIV2(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_usb) <= PLL_POST_DIV_MAX),
"pll_usb: post-div is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_ref) >= CLOCK_FREQ_clk_ref,
"clk_ref: clock divider is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_sys) >= CLOCK_FREQ_clk_sys,
"clk_sys: clock divider is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb,
"clk_usb: clock divider is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc,
"clk_adc: clock divider is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc,
"clk_rtc: clock divider is out of range");
BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri,
"clk_peri: clock divider is out of range");
BUILD_ASSERT(CLOCK_FREQ(rosc_ph) == CLOCK_FREQ(rosc), "rosc_ph: frequency must be equal to rosc");
PINCTRL_DT_INST_DEFINE(0);
static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config = {
.clocks_regs = (clocks_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, clocks),
.xosc_regs = (xosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, xosc),
.pll_sys_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_sys),
.pll_usb_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_usb),
.rosc_regs = (rosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, rosc),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.clocks_data = {
[RPI_PICO_CLKID_CLK_GPOUT0] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
.source_rate = SRC_CLOCK_FREQ(clk_gpout0),
.rate = CLOCK_FREQ(clk_gpout0),
},
[RPI_PICO_CLKID_CLK_GPOUT1] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
.source_rate = SRC_CLOCK_FREQ(clk_gpout1),
.rate = CLOCK_FREQ(clk_gpout1),
},
[RPI_PICO_CLKID_CLK_GPOUT2] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_gpout2),
.source_rate = SRC_CLOCK_FREQ(clk_gpout2),
.rate = CLOCK_FREQ(clk_gpout2),
},
[RPI_PICO_CLKID_CLK_GPOUT3] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_gpout3),
.source_rate = SRC_CLOCK_FREQ(clk_gpout3),
.rate = CLOCK_FREQ(clk_gpout3),
},
[RPI_PICO_CLKID_CLK_REF] = {
#if CLK_SRC_IS(clk_ref, rosc_ph)
.source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH,
.aux_source = 0,
#elif CLK_SRC_IS(clk_ref, xosc)
.source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
.aux_source = 0,
#else
.source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX,
#endif
.source_rate = SRC_CLOCK_FREQ(clk_ref),
.rate = CLOCK_FREQ(clk_ref),
},
[RPI_PICO_CLKID_CLK_SYS] = {
#if CLK_SRC_IS(clk_sys, clk_ref)
.source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
.aux_source = 0,
#else
.source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
.aux_source = CLOCK_AUX_SOURCE(clk_sys),
#endif
.source_rate = SRC_CLOCK_FREQ(clk_sys),
.rate = CLOCK_FREQ(clk_sys),
},
[RPI_PICO_CLKID_CLK_PERI] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_peri),
.source_rate = SRC_CLOCK_FREQ(clk_peri),
.rate = CLOCK_FREQ(clk_peri),
},
[RPI_PICO_CLKID_CLK_USB] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_usb),
.source_rate = SRC_CLOCK_FREQ(clk_usb),
.rate = CLOCK_FREQ(clk_usb),
},
[RPI_PICO_CLKID_CLK_ADC] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_adc),
.source_rate = SRC_CLOCK_FREQ(clk_adc),
.rate = CLOCK_FREQ(clk_adc),
},
[RPI_PICO_CLKID_CLK_RTC] = {
.source = 0,
.aux_source = CLOCK_AUX_SOURCE(clk_rtc),
.source_rate = SRC_CLOCK_FREQ(clk_rtc),
.rate = CLOCK_FREQ(clk_rtc),
},
},
.plls_data = {
[RPI_PICO_PLL_SYS] = {
.ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), clock_div),
.fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), fb_div),
.post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div1),
.post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div2),
},
[RPI_PICO_PLL_USB] = {
.ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), clock_div),
.fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), fb_div),
.post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div1),
.post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div2),
},
},
.rosc_data = {
.phase = (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
phase_flip),
(ROSC_PHASE_FLIP_BITS), (0x0)) |
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
phase),
((DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), phase) &
ROSC_PHASE_SHIFT_BITS) | ROSC_PHASE_ENABLE_BITS), (0x0))),
.div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_div),
.range = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), range),
.code = (STAGE_DS(0) | STAGE_DS(1) | STAGE_DS(2) | STAGE_DS(3) |
STAGE_DS(4) | STAGE_DS(5) | STAGE_DS(6) | STAGE_DS(7)),
},
.gpin_data = {
[RPI_PICO_GPIN_0] = {
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
clock_frequency),
(.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
clock_frequency),),
(.frequency = 0,))
},
[RPI_PICO_GPIN_1] = {
COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
clock_frequency),
(.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
clock_frequency),),
(.frequency = 0,))
},
},
};
static struct clock_control_rpi_pico_data clock_control_rpi_pico_data = {
.rosc_freq = CLOCK_FREQ(rosc),
.rosc_ph_freq = CLOCK_FREQ(rosc_ph),
};
DEVICE_DT_INST_DEFINE(0, clock_control_rpi_pico_init, NULL, &clock_control_rpi_pico_data,
&clock_control_rpi_pico_config, PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_rpi_pico_api);
``` | /content/code_sandbox/drivers/clock_control/clock_control_rpi_pico.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,778 |
```c
/*
*
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
/**
* @brief fill in AHB/APB buses configuration structure
*/
static inline int stm32_clock_control_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
ARG_UNUSED(dev);
switch (pclken->bus) {
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB5:
LL_APB5_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB5:
LL_AHB5_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB6:
LL_AHB6_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AXI:
LL_AXI_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_MLAHB:
LL_MLAHB_GRP1_EnableClock(pclken->enr);
break;
default:
return -ENOTSUP;
}
return 0;
}
static inline int stm32_clock_control_off(const struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
ARG_UNUSED(dev);
switch (pclken->bus) {
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB5:
LL_APB5_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB5:
LL_AHB5_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB6:
LL_AHB6_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AXI:
LL_AXI_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_MLAHB:
LL_MLAHB_GRP1_DisableClock(pclken->enr);
break;
default:
return -ENOTSUP;
}
return 0;
}
static int stm32_clock_control_get_subsys_rate(const struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
ARG_UNUSED(clock);
switch (pclken->bus) {
case STM32_CLOCK_BUS_APB1:
switch (pclken->enr) {
case LL_APB1_GRP1_PERIPH_TIM2:
case LL_APB1_GRP1_PERIPH_TIM3:
case LL_APB1_GRP1_PERIPH_TIM4:
case LL_APB1_GRP1_PERIPH_TIM5:
case LL_APB1_GRP1_PERIPH_TIM6:
case LL_APB1_GRP1_PERIPH_TIM7:
case LL_APB1_GRP1_PERIPH_TIM12:
case LL_APB1_GRP1_PERIPH_TIM13:
case LL_APB1_GRP1_PERIPH_TIM14:
*rate = LL_RCC_GetTIMGClockFreq(LL_RCC_TIMG1PRES);
break;
case LL_APB1_GRP1_PERIPH_LPTIM1:
*rate = LL_RCC_GetLPTIMClockFreq(
LL_RCC_LPTIM1_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_SPI2:
case LL_APB1_GRP1_PERIPH_SPI3:
*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_USART2:
case LL_APB1_GRP1_PERIPH_UART4:
*rate = LL_RCC_GetUARTClockFreq(
LL_RCC_UART24_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_USART3:
case LL_APB1_GRP1_PERIPH_UART5:
*rate = LL_RCC_GetUARTClockFreq(
LL_RCC_UART35_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_UART7:
case LL_APB1_GRP1_PERIPH_UART8:
*rate = LL_RCC_GetUARTClockFreq(
LL_RCC_UART78_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_I2C1:
case LL_APB1_GRP1_PERIPH_I2C2:
*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_I2C3:
case LL_APB1_GRP1_PERIPH_I2C5:
*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C35_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_SPDIF:
*rate = LL_RCC_GetSPDIFRXClockFreq(
LL_RCC_SPDIFRX_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_CEC:
*rate = LL_RCC_GetCECClockFreq(LL_RCC_CEC_CLKSOURCE);
break;
case LL_APB1_GRP1_PERIPH_WWDG1:
case LL_APB1_GRP1_PERIPH_DAC12:
case LL_APB1_GRP1_PERIPH_MDIOS:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_APB2:
switch (pclken->enr) {
case LL_APB2_GRP1_PERIPH_TIM1:
case LL_APB2_GRP1_PERIPH_TIM8:
case LL_APB2_GRP1_PERIPH_TIM15:
case LL_APB2_GRP1_PERIPH_TIM16:
case LL_APB2_GRP1_PERIPH_TIM17:
*rate = LL_RCC_GetTIMGClockFreq(LL_RCC_TIMG2PRES);
break;
case LL_APB2_GRP1_PERIPH_SPI1:
*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_SPI4:
case LL_APB2_GRP1_PERIPH_SPI5:
*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI45_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_USART6:
*rate = LL_RCC_GetUARTClockFreq(
LL_RCC_USART6_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_SAI1:
*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_SAI2:
*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_SAI3:
*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI3_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_DFSDM1:
*rate = LL_RCC_GetDFSDMClockFreq(
LL_RCC_DFSDM_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_FDCAN:
*rate = LL_RCC_GetFDCANClockFreq(
LL_RCC_FDCAN_CLKSOURCE);
break;
case LL_APB2_GRP1_PERIPH_ADFSDM1:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_APB3:
switch (pclken->enr) {
case LL_APB3_GRP1_PERIPH_LPTIM2:
case LL_APB3_GRP1_PERIPH_LPTIM3:
*rate = LL_RCC_GetLPTIMClockFreq(
LL_RCC_LPTIM23_CLKSOURCE);
break;
case LL_APB3_GRP1_PERIPH_LPTIM4:
case LL_APB3_GRP1_PERIPH_LPTIM5:
*rate = LL_RCC_GetLPTIMClockFreq(
LL_RCC_LPTIM45_CLKSOURCE);
break;
case LL_APB3_GRP1_PERIPH_SAI4:
*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI4_CLKSOURCE);
break;
case LL_APB3_GRP1_PERIPH_SYSCFG:
case LL_APB3_GRP1_PERIPH_VREF:
case LL_APB3_GRP1_PERIPH_TMPSENS:
case LL_APB3_GRP1_PERIPH_HDP:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_APB4:
switch (pclken->enr) {
case LL_APB4_GRP1_PERIPH_LTDC:
*rate = LL_RCC_GetLTDCClockFreq();
break;
case LL_APB4_GRP1_PERIPH_DSI:
*rate = LL_RCC_GetDSIClockFreq(LL_RCC_DSI_CLKSOURCE);
break;
case LL_APB4_GRP1_PERIPH_USBPHY:
*rate = LL_RCC_GetUSBPHYClockFreq(
LL_RCC_USBPHY_CLKSOURCE);
break;
case LL_APB4_GRP1_PERIPH_DDRPERFM:
case LL_APB4_GRP1_PERIPH_STGENRO:
case LL_APB4_GRP1_PERIPH_STGENROSTP:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_APB5:
switch (pclken->enr) {
case LL_APB5_GRP1_PERIPH_SPI6:
*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
break;
case LL_APB5_GRP1_PERIPH_I2C4:
case LL_APB5_GRP1_PERIPH_I2C6:
*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C46_CLKSOURCE);
break;
case LL_APB5_GRP1_PERIPH_USART1:
*rate = LL_RCC_GetUARTClockFreq(
LL_RCC_USART1_CLKSOURCE);
break;
case LL_APB5_GRP1_PERIPH_STGEN:
case LL_APB5_GRP1_PERIPH_STGENSTP:
*rate = LL_RCC_GetSTGENClockFreq(
LL_RCC_STGEN_CLKSOURCE);
break;
case LL_APB5_GRP1_PERIPH_RTCAPB:
*rate = LL_RCC_GetRTCClockFreq();
break;
case LL_APB5_GRP1_PERIPH_TZC1:
case LL_APB5_GRP1_PERIPH_TZC2:
case LL_APB5_GRP1_PERIPH_TZPC:
case LL_APB5_GRP1_PERIPH_BSEC:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_AHB2:
switch (pclken->enr) {
case LL_AHB2_GRP1_PERIPH_ADC12:
*rate = LL_RCC_GetADCClockFreq(LL_RCC_ADC_CLKSOURCE);
break;
case LL_AHB2_GRP1_PERIPH_USBO:
*rate = LL_RCC_GetUSBOClockFreq(LL_RCC_USBO_CLKSOURCE);
break;
case LL_AHB2_GRP1_PERIPH_SDMMC3:
*rate = LL_RCC_GetSDMMCClockFreq(
LL_RCC_SDMMC3_CLKSOURCE);
break;
case LL_AHB2_GRP1_PERIPH_DMA1:
case LL_AHB2_GRP1_PERIPH_DMA2:
case LL_AHB2_GRP1_PERIPH_DMAMUX:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_AHB3:
switch (pclken->enr) {
case LL_AHB3_GRP1_PERIPH_RNG2:
*rate = LL_RCC_GetRNGClockFreq(LL_RCC_RNG2_CLKSOURCE);
break;
case LL_AHB3_GRP1_PERIPH_DCMI:
case LL_AHB3_GRP1_PERIPH_CRYP2:
case LL_AHB3_GRP1_PERIPH_HASH2:
case LL_AHB3_GRP1_PERIPH_CRC2:
case LL_AHB3_GRP1_PERIPH_HSEM:
case LL_AHB3_GRP1_PERIPH_IPCC:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_AHB4:
return -ENOTSUP;
case STM32_CLOCK_BUS_AHB5:
switch (pclken->enr) {
case LL_AHB5_GRP1_PERIPH_RNG1:
*rate = LL_RCC_GetRNGClockFreq(LL_RCC_RNG1_CLKSOURCE);
break;
case LL_AHB5_GRP1_PERIPH_GPIOZ:
case LL_AHB5_GRP1_PERIPH_CRYP1:
case LL_AHB5_GRP1_PERIPH_HASH1:
case LL_AHB5_GRP1_PERIPH_BKPSRAM:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_AHB6:
switch (pclken->enr) {
case LL_AHB6_GRP1_PERIPH_ETH1CK:
case LL_AHB6_GRP1_PERIPH_ETH1TX:
case LL_AHB6_GRP1_PERIPH_ETH1RX:
case LL_AHB6_GRP1_PERIPH_ETH1MAC:
case LL_AHB6_GRP1_PERIPH_ETH1STP:
*rate = LL_RCC_GetETHClockFreq(LL_RCC_ETH_CLKSOURCE);
break;
case LL_AHB6_GRP1_PERIPH_FMC:
*rate = LL_RCC_GetFMCClockFreq(LL_RCC_FMC_CLKSOURCE);
break;
case LL_AHB6_GRP1_PERIPH_QSPI:
*rate = LL_RCC_GetQSPIClockFreq(LL_RCC_QSPI_CLKSOURCE);
break;
case LL_AHB6_GRP1_PERIPH_SDMMC1:
case LL_AHB6_GRP1_PERIPH_SDMMC2:
*rate = LL_RCC_GetSDMMCClockFreq(
LL_RCC_SDMMC12_CLKSOURCE);
break;
case LL_AHB6_GRP1_PERIPH_MDMA:
case LL_AHB6_GRP1_PERIPH_GPU:
case LL_AHB6_GRP1_PERIPH_CRC1:
case LL_AHB6_GRP1_PERIPH_USBH:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_AXI:
switch (pclken->enr) {
case LL_AXI_GRP1_PERIPH_SYSRAMEN:
default:
return -ENOTSUP;
}
break;
case STM32_CLOCK_BUS_MLAHB:
switch (pclken->enr) {
case LL_MLAHB_GRP1_PERIPH_RETRAMEN:
default:
return -ENOTSUP;
}
break;
default:
return -ENOTSUP;
}
return 0;
}
static const struct clock_control_driver_api stm32_clock_control_api = {
.on = stm32_clock_control_on,
.off = stm32_clock_control_off,
.get_rate = stm32_clock_control_get_subsys_rate,
};
static int stm32_clock_control_init(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
/**
* @brief RCC device, note that priority is intentionally set to 1 so
* that the device init runs just after SOC init
*/
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
stm32_clock_control_init,
NULL,
NULL, NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&stm32_clock_control_api);
``` | /content/code_sandbox/drivers/clock_control/clock_stm32_ll_mp1.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,673 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CALIBRATION_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CALIBRATION_H_
#include <zephyr/sys/onoff.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize LFCLK RC calibration.
*
* @param mgrs Pointer to array of onoff managers for HF and LF clocks.
*/
void z_nrf_clock_calibration_init(struct onoff_manager *mgrs);
/**
* @brief Calibration done handler
*
* Must be called from clock event handler.
*/
void z_nrf_clock_calibration_done_handler(void);
/**
* @brief Notify calibration module about LF clock start
*/
void z_nrf_clock_calibration_lfclk_started(void);
/**
* @brief Notify calibration module about LF clock stop
*/
void z_nrf_clock_calibration_lfclk_stopped(void);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CALIBRATION_H_ */
``` | /content/code_sandbox/drivers/clock_control/nrf_clock_calibration.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
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