text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185
values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
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```objective-c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_Config_CDC_0.h
* Purpose: USB Device Communication Device Class (CDC) Configuration
* Rev.: V5.2.0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Communication Device Class (CDC) 0
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CDC0_DEV 0
// <o>Communication Class Subclass
// <i>Specifies the model used by the CDC class.
// <2=>Abstract Control Model (ACM)
// <13=>Network Control Model (NCM)
#define USBD_CDC0_SUBCLASS 2
// <o>Communication Class Protocol
// <i>Specifies the protocol used by the CDC class.
// <0=>No protocol (Virtual COM)
// <255=>Vendor-specific (RNDIS)
#define USBD_CDC0_PROTOCOL 0
// <h>Interrupt Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Interrupt IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_INT_IN 3
// <h>Endpoint Settings
// <i>Parameters are used to create Endpoint Descriptors
// <i>and for memory allocation in the USB component.
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE 16
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
#define USBD_CDC0_BINTERVAL 2
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_CDC0_HS_WMAXPACKETSIZE 16
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_CDC0_HS_BINTERVAL 2
// </h>
// </h>
// </h>
// <h>Bulk Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Bulk IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_IN 4
// <o.0..3>Bulk OUT Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_OUT 4
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors and for memory
// <i>allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE1 64
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
// <i>Specifies the physical packet size used for information exchange.
// <i>Only available value is 512.
#define USBD_CDC0_HS_WMAXPACKETSIZE1 512
// <o.0..7>Maximum NAK Rate <0-255>
// <i>Specifies the interval in which Bulk Endpoint can NAK.
// <i>Value of 0 indicates that Bulk Endpoint never NAKs.
#define USBD_CDC0_HS_BINTERVAL1 0
// </h>
// </h>
// </h>
// <h>Communication Device Class Settings
// <i>Parameters are used to create USB Descriptors and for memory allocation
// <i>in the USB component.
//
// <s.126>Communication Class Interface String
#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0"
// <s.126>Data Class Interface String
#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1"
// <h>Abstract Control Model Settings
// <h>Call Management Capabilities
// <i>Specifies which call management functionality is supported.
// <o.1>Call Management channel
// <0=>Communication Class Interface only
// <1=>Communication and Data Class Interface
// <o.0>Device Call Management handling
// <0=>None
// <1=>All
// </h>
#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
// <h>Abstract Control Management Capabilities
// <i>Specifies which abstract control management functionality is supported.
// <o.3>D3 bit
// <i>Enabled = Supports the notification Network_Connection
// <o.2>D2 bit
// <i>Enabled = Supports the request Send_Break
// <o.1>D1 bit
// <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
// <i> Set_Control_Line_State, and notification Serial_State
// <o.0>D0 bit
// <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
// </h>
#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
// <o>Maximum Communication Device Send Buffer Size
// <i>Specifies size of buffer used for sending of data to USB Host.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024
// <o>Maximum Communication Device Receive Buffer Size
// <i>Specifies size of buffer used for receiving of data from USB Host.
// <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
// <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048
// </h>
// <h>Network Control Model Settings
// <s.12>MAC Address String
// <i>Specifies 48-bit Ethernet MAC address.
#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E"
// <h>Ethernet Statistics
// <i>Specifies Ethernet statistic functions supported.
// <o.0>XMIT_OK
// <i>Frames transmitted without errors
// <o.1>RVC_OK
// <i>Frames received without errors
// <o.2>XMIT_ERROR
// <i>Frames not transmitted, or transmitted with errors
// <o.3>RCV_ERROR
// <i>Frames received with errors that are not delivered to the USB host.
// <o.4>RCV_NO_BUFFER
// <i>Frame missed, no buffers
// <o.5>DIRECTED_BYTES_XMIT
// <i>Directed bytes transmitted without errors
// <o.6>DIRECTED_FRAMES_XMIT
// <i>Directed frames transmitted without errors
// <o.7>MULTICAST_BYTES_XMIT
// <i>Multicast bytes transmitted without errors
// <o.8>MULTICAST_FRAMES_XMIT
// <i>Multicast frames transmitted without errors
// <o.9>BROADCAST_BYTES_XMIT
// <i>Broadcast bytes transmitted without errors
// <o.10>BROADCAST_FRAMES_XMIT
// <i>Broadcast frames transmitted without errors
// <o.11>DIRECTED_BYTES_RCV
// <i>Directed bytes received without errors
// <o.12>DIRECTED_FRAMES_RCV
// <i>Directed frames received without errors
// <o.13>MULTICAST_BYTES_RCV
// <i>Multicast bytes received without errors
// <o.14>MULTICAST_FRAMES_RCV
// <i>Multicast frames received without errors
// <o.15>BROADCAST_BYTES_RCV
// <i>Broadcast bytes received without errors
// <o.16>BROADCAST_FRAMES_RCV
// <i>Broadcast frames received without errors
// <o.17>RCV_CRC_ERROR
// <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
// <o.18>TRANSMIT_QUEUE_LENGTH
// <i>Length of transmit queue
// <o.19>RCV_ERROR_ALIGNMENT
// <i>Frames received with alignment error
// <o.20>XMIT_ONE_COLLISION
// <i>Frames transmitted with one collision
// <o.21>XMIT_MORE_COLLISIONS
// <i>Frames transmitted with more than one collision
// <o.22>XMIT_DEFERRED
// <i>Frames transmitted after deferral
// <o.23>XMIT_MAX_COLLISIONS
// <i>Frames not transmitted due to collisions
// <o.24>RCV_OVERRUN
// <i>Frames not received due to overrun
// <o.25>XMIT_UNDERRUN
// <i>Frames not transmitted due to underrun
// <o.26>XMIT_HEARTBEAT_FAILURE
// <i>Frames transmitted with heartbeat failure
// <o.27>XMIT_TIMES_CRS_LOST
// <i>Times carrier sense signal lost during transmission
// <o.28>XMIT_LATE_COLLISIONS
// <i>Late collisions detected
// </h>
#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003
// <o>Maximum Segment Size
// <i>Specifies maximum segment size that Ethernet device is capable of supporting.
// <i>Typically 1514 bytes.
#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514
// <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
// <i>Specifies multicast filtering type.
// <o.0..14>Number of Multicast Filters
// <i>Specifies number of multicast filters that can be configured by the USB Host.
#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1
// <o.0..7>Number of Power Filters
// <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0
// <h>Network Capabilities
// <i>Specifies which functions are supported.
// <o.4>SetCrcMode/GetCrcMode
// <o.3>SetMaxDatagramSize/GetMaxDatagramSize
// <o.1>SetNetAddress/GetNetAddress
// <o.0>SetEthernetPacketFilter
// </h>
#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B
// <h>NTB Parameters
// <i>Specifies NTB parameters reported by GetNtbParameters function.
// <h>NTB Formats Supported (bmNtbFormatsSupported)
// <i>Specifies NTB formats supported.
// <o.0>16-bit NTB (always supported)
// <o.1>32-bit NTB
// </h>
#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001
// <h>IN Data Pipe
//
// <o>Maximum NTB Size (dwNtbInMaxSize)
// <i>Specifies maximum IN NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
// <i>Specifies divisor used for IN NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
// <i>Specifies remainder used to align input datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4
// </h>
// <h>OUT Data Pipe
//
// <o>Maximum NTB Size (dwNtbOutMaxSize)
// <i>Specifies maximum OUT NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
// <i>Specifies divisor used for OUT NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
// <i>Specifies remainder used to align output datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4
// </h>
// </h>
// <o.0>Raw Data Access API
// <i>Enables or disables Raw Data Access API.
#define USBD_CDC0_NCM_RAW_ENABLE 0
// <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for sending data to USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1
// <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for receiving data from USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1
// </h>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
#define USBD_CDC0_INT_THREAD_STACK_SIZE 512
// Communication Device Class Interrupt Endpoint Thread Priority
#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal
// <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
// Communication Device Class Bulk Endpoints Thread Priority
#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 4,385 |
```c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.2.0
*your_sha256_hash--------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 1
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 1
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF00B
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"MCU-LINK"
// <e.0>Serial Number String
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Default value
// <i>Default device's Serial Number String.
#define USBD0_STR_DESC_SER L"0001A0000000"
// <o.0..7>Maximum Length (in characters) <0-126>
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
#define USBD0_STR_DESC_SER_MAX_LEN 16
// </e>
// </h>
// <h>Microsoft OS Descriptors Settings
// <i>These settings are used to create the Microsoft OS Descriptors.
// <e.0>OS String
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
#define USBD0_OS_DESC_EN 1
// <o.0..7>Vendor Code <0x01-0xFF>
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
#define USBD0_OS_DESC_VENDOR_CODE 0x01
// </e>
// </h>
// <o>Control Transfer Buffer Size <64-65536:64>
// <i>Specifies size of buffer used for Control Transfers.
// <i>It should be at least as big as maximum packet size for Endpoint 0.
#define USBD0_EP0_BUF_SIZE 128
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 1024
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_4
#include "USBD_Config_CDC_4.h"
#endif
#ifdef RTE_USB_Device_CDC_5
#include "USBD_Config_CDC_5.h"
#endif
#ifdef RTE_USB_Device_CDC_6
#include "USBD_Config_CDC_6.h"
#endif
#ifdef RTE_USB_Device_CDC_7
#include "USBD_Config_CDC_7.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,799 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 16. June 2021
* $Revision: V2.1.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: DAP_config.h CMSIS-DAP Configuration File for LPC-Link2
*
*your_sha256_hash-----------*/
#ifndef __DAP_CONFIG_H__
#define __DAP_CONFIG_H__
//**************************************************************************************************
/**
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
\ingroup DAP_ConfigIO_gr
@{
Provides definitions about the hardware and configuration of the Debug Unit.
This information includes:
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- Debug Unit Identification strings (Vendor, Product, Serial Number).
- Debug Unit communication packet size.
- Debug Access Port supported modes and settings (JTAG/SWD and SWO).
- Optional information about a connected Target Device (for Evaluation Boards).
*/
#ifdef _RTE_
#include "RTE_Components.h"
#include CMSIS_device_header
#else
#include "device.h" // Debug Unit Cortex-M Processor Header File
#endif
#ifdef LPC_LINK2_ONBOARD
#include <string.h>
#include "ser_num.h"
#endif
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
/// This value is used to calculate the SWD/JTAG clock speed.
#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz.
/// Number of processor cycles for I/O Port write operations.
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
/// required.
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available.
/// Indicate that JTAG communication mode is available at the Debug Port.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain.
/// Default communication mode on the Debug Access Port.
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
/// Used to initialize the default SWD/JTAG clock frequency.
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
/// Maximum Package Size for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes.
/// Maximum Package Buffers for Command and Response data.
/// This configuration settings is used to optimize the communication performance with the
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
/// setting can be reduced (valid range is 1 .. 255).
#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered.
/// Indicate that UART Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART SWO.
#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#).
/// Maximum SWO UART Baudrate.
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz.
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available.
/// SWO Trace Buffer Size.
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n).
/// SWO Streaming Trace.
#define SWO_STREAM 1 ///< SWO Streaming Trace: 1 = available, 0 = not available.
/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
#define TIMESTAMP_CLOCK 180000000U ///< Timestamp clock in Hz (0 = timestamps not supported).
/// Indicate that UART Communication Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available.
/// USART Driver instance number for the UART Communication Port.
#define DAP_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#).
/// UART Receive Buffer Size.
#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n).
/// UART Transmit Buffer Size.
#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n).
/// Indicate that UART Communication via USB COM Port is available.
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available.
/// Debug Unit is connected to fixed Target Device.
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings
/// are stored and may be used by the debugger or IDE to configure device parameters.
#ifdef LPC_LINK2_ONBOARD
#define TARGET_FIXED 1 ///< Target: 1 = known, 0 = unknown;
#else
#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown;
#endif
#define TARGET_DEVICE_VENDOR "NXP" ///< String indicating the Silicon Vendor
#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device
#define TARGET_BOARD_VENDOR "NXP" ///< String indicating the Board Vendor
#define TARGET_BOARD_NAME "NXP board" ///< String indicating the Board Name
#if TARGET_FIXED != 0
extern const char TargetDeviceVendor [];
extern const char TargetDeviceName [];
extern const char TargetBoardVendor [];
extern const char TargetBoardName [];
#endif
/** Get Vendor Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
(void)str;
return (0U);
}
/** Get Product Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
(void)str;
return (0U);
}
/** Get Serial Number string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
#ifdef LPC_LINK2_ONBOARD
uint8_t len = 0U;
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
strcpy(str, ser_num);
len = (uint8_t)(strlen(ser_num) + 1U);
}
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceVendor);
len = (uint8_t)(strlen(TargetDeviceVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Device Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetDeviceName);
len = (uint8_t)(strlen(TargetDeviceName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Vendor string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardVendor);
len = (uint8_t)(strlen(TargetBoardVendor) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Target Board Name string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) {
#if TARGET_FIXED != 0
uint8_t len;
strcpy(str, TargetBoardName);
len = (uint8_t)(strlen(TargetBoardName) + 1U);
return (len);
#else
(void)str;
return (0U);
#endif
}
/** Get Product Firmware Version string.
\param str Pointer to buffer to store the string (max 60 characters).
\return String length (including terminating NULL character) or 0 (no string).
*/
__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
(void)str;
return (0U);
}
///@}
// LPC43xx peripheral register bit masks (used by macros)
#define CCU_CLK_CFG_RUN (1U << 0)
#define CCU_CLK_CFG_AUTO (1U << 1)
#define CCU_CLK_STAT_RUN (1U << 0)
#define SCU_SFS_EPD (1U << 3)
#define SCU_SFS_EPUN (1U << 4)
#define SCU_SFS_EHS (1U << 5)
#define SCU_SFS_EZI (1U << 6)
#define SCU_SFS_ZIF (1U << 7)
// Debug Port I/O Pins
// SWCLK/TCK Pin P1_17: GPIO0[12]
#define PIN_SWCLK_TCK_PORT 0
#define PIN_SWCLK_TCK_BIT 12
// SWDIO/TMS Pin P1_6: GPIO1[9]
#define PIN_SWDIO_TMS_PORT 1
#define PIN_SWDIO_TMS_BIT 9
// SWDIO Output Enable Pin P1_5: GPIO1[8]
#define PIN_SWDIO_OE_PORT 1
#define PIN_SWDIO_OE_BIT 8
// TDI Pin P1_18: GPIO0[13]
#define PIN_TDI_PORT 0
#define PIN_TDI_BIT 13
// TDO Pin P1_14: GPIO1[7]
#define PIN_TDO_PORT 1
#define PIN_TDO_BIT 7
// nTRST Pin Not available
#define PIN_nTRST_PORT
#define PIN_nTRST_BIT
// nRESET Pin P2_5: GPIO5[5]
#define PIN_nRESET_PORT 5
#define PIN_nRESET_BIT 5
// nRESET Output Enable Pin P2_6: GPIO5[6]
#define PIN_nRESET_OE_PORT 5
#define PIN_nRESET_OE_BIT 6
// Debug Unit LEDs
// Connected LED P1_1: GPIO0[8]
#define LED_CONNECTED_PORT 0
#define LED_CONNECTED_BIT 8
// Target Running LED Not available
//**************************************************************************************************
/**
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
\ingroup DAP_ConfigIO_gr
@{
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
interface of a device. The following I/O Pins are provided:
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
---------------------------- | -------------------- | ---------------------------------------------
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
TDI: Test Data Input | | Output Push/Pull
TDO: Test Data Output | | Input
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
DAP Hardware I/O Pin Access Functions
-------------------------------------
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
these I/O Pins.
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
peripherals that can independently write/read a single I/O pin without affecting any other pins
of the same I/O port. The following SWDIO I/O Pin functions are provided:
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
*/
// Configure DAP I/O pins ------------------------------
// LPC-Link2 HW uses buffers for debug port pins. Therefore it is not
// possible to disable outputs SWCLK/TCK, TDI and they are left active.
// Only SWDIO/TMS output can be disabled but it is also left active.
// nRESET is configured for open drain mode.
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
Configures the DAP Hardware I/O pins for JTAG mode:
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
- TDO to input mode.
*/
__STATIC_INLINE void PORT_JTAG_SETUP (void) {
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
}
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
*/
__STATIC_INLINE void PORT_SWD_SETUP (void) {
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
}
/** Disable JTAG/SWD I/O Pins.
Disables the DAP Hardware I/O pins which configures:
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
*/
__STATIC_INLINE void PORT_OFF (void) {
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
}
// SWCLK/TCK I/O pin -------------------------------------
/** SWCLK/TCK I/O pin: Get Input.
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
}
/** SWCLK/TCK I/O pin: Set Output to High.
Set the SWCLK/TCK DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) {
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
}
/** SWCLK/TCK I/O pin: Set Output to Low.
Set the SWCLK/TCK DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) {
LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
}
// SWDIO/TMS Pin I/O --------------------------------------
/** SWDIO/TMS I/O pin: Get Input.
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
}
/** SWDIO/TMS I/O pin: Set Output to High.
Set the SWDIO/TMS DAP hardware I/O pin to high level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) {
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
}
/** SWDIO/TMS I/O pin: Set Output to Low.
Set the SWDIO/TMS DAP hardware I/O pin to low level.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) {
LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
}
/** SWDIO I/O pin: Get Input (used in SWD mode only).
\return Current status of the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) {
return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
}
/** SWDIO I/O pin: Set Output (used in SWD mode only).
\param bit Output value for the SWDIO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) {
LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
}
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
called prior \ref PIN_SWDIO_OUT function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) {
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
}
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
called prior \ref PIN_SWDIO_IN function calls.
*/
__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) {
LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
}
// TDI Pin I/O ---------------------------------------------
/** TDI I/O pin: Get Input.
\return Current status of the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) {
return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
}
/** TDI I/O pin: Set Output.
\param bit Output value for the TDI DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) {
LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
}
// TDO Pin I/O ---------------------------------------------
/** TDO I/O pin: Get Input.
\return Current status of the TDO DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
}
// nTRST Pin I/O -------------------------------------------
/** nTRST I/O pin: Get Input.
\return Current status of the nTRST DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) {
return (0U); // Not available
}
/** nTRST I/O pin: Set Output.
\param bit JTAG TRST Test Reset pin status:
- 0: issue a JTAG TRST Test Reset.
- 1: release JTAG TRST Test Reset.
*/
__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) {
(void) bit;
// Not available
}
// nRESET Pin I/O------------------------------------------
/** nRESET I/O pin: Get Input.
\return Current status of the nRESET DAP hardware I/O pin.
*/
__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) {
return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
}
/** nRESET I/O pin: Set Output.
\param bit target device hardware reset pin status:
- 0: issue a device hardware reset.
- 1: release device hardware reset.
*/
__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) {
if (bit) {
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
} else {
LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT);
}
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
It is recommended to provide the following LEDs for status indication:
- Connect LED: is active when the DAP hardware is connected to a debugger.
- Running LED: is active when the debugger has put the target device into running state.
*/
/** Debug Unit: Set status of Connected LED.
\param bit status of the Connect LED.
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
*/
__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = (uint8_t)bit;
}
/** Debug Unit: Set status Target Running LED.
\param bit status of the Target Running LED.
- 1: Target Running LED ON: program execution in target started.
- 0: Target Running LED OFF: program execution in target stopped.
*/
__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
(void) bit;
// Not available
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
\ingroup DAP_ConfigIO_gr
@{
Access function for Test Domain Timer.
The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
*/
/** Get timestamp of Test Domain Timer.
\return Current timestamp value.
*/
__STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
return (DWT->CYCCNT);
}
///@}
//**************************************************************************************************
/**
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
\ingroup DAP_ConfigIO_gr
@{
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
*/
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
- I/O clock system enabled.
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
- for nTRST, nRESET a weak pull-up (if available) is enabled.
- LED output pins are enabled and LEDs are turned off.
*/
__STATIC_INLINE void DAP_SETUP (void) {
/* Enable clock and init GPIO outputs */
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
/* Configure I/O pins: function number, input buffer enabled, */
/* no pull-up/down except nRESET (pull-up) */
LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */
LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */
LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */
LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */
LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */
LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */
LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */
LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */
#ifdef TARGET_POWER_EN
LPC_SCU->SFSP3_1 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* Target Power enable P3_1 GPIO5[8] */
#endif
/* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */
/* TDO as input */
/* nRESET as input with output latch set to low level */
/* nRESET_OE as output (low level) */
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT);
LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT);
LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT);
LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT);
LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT);
#ifdef TARGET_POWER_EN
/* Target Power enable as output (turned on) */
LPC_GPIO_PORT->SET[5] = (1U << 8);
LPC_GPIO_PORT->DIR[5] |= (1U << 8);
#endif
/* Configure: LED as output (turned off) */
LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT);
LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT);
/* Configure Peripheral Interrupt Priorities */
NVIC_SetPriority(USB0_IRQn, 1U);
}
/** Reset Target Device with custom specific I/O pin or command sequence.
This function allows the optional implementation of a device specific reset sequence.
It is called when the command \ref DAP_ResetTarget and is for example required
when a device needs a time-critical unlock sequence that enables the debug port.
\return 0 = no device specific reset sequence is implemented.\n
1 = a device specific reset sequence is implemented.
*/
__STATIC_INLINE uint8_t RESET_TARGET (void) {
return (0U); // change to '1' when a device reset sequence is implemented
}
///@}
#endif /* __DAP_CONFIG_H__ */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/DAP_config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 7,252 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 27. May 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: ser_num.h CMSIS-DAP Serial Number module for LPC-Link2
*
*your_sha256_hash-----------*/
#ifndef __SER_NUM_H__
#define __SER_NUM_H__
char *GetSerialNum (void);
#endif /* __SER_NUM_H__ */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 148 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 16. June 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: target.c CMSIS-DAP Target Device/Board information (patchable)
*
*your_sha256_hash-----------*/
#include "DAP_config.h"
#if TARGET_FIXED != 0
const char TargetDeviceVendor [64] = TARGET_DEVICE_VENDOR;
const char TargetDeviceName [64] = TARGET_DEVICE_NAME;
const char TargetBoardVendor [64] = TARGET_BOARD_VENDOR;
const char TargetBoardName [64] = TARGET_BOARD_NAME;
#endif
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/target.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 190 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 27. May 2021
* $Revision: V1.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: ser_num.c CMSIS-DAP Serial Number module for LPC-Link2
*
*your_sha256_hash-----------*/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "ser_num.h"
// Serial Number
#define SER_NUM_PREFIX "00A1"
static char SerialNum[32];
#define IAP_LOCATION *(volatile unsigned int *)(0x10400100)
#define IAP_READ_DEVICE_SERIAL_NUMBER 58U
typedef void (*IAP)(unsigned int [],unsigned int[]);
/**
\brief Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF)
\param[in] data pointer to data
\param[in] len data length (in bytes)
\return CRC32 value
*/
static uint32_t crc32 (const uint8_t *data, uint32_t len) {
uint32_t crc32;
uint32_t n;
crc32 = 0xFFFFFFFFU;
while (len != 0U) {
crc32 ^= ((uint32_t)*data++) << 24U;
for (n = 8U; n; n--) {
if (crc32 & 0x80000000U) {
crc32 <<= 1U;
crc32 ^= 0x04C11DB7U;
} else {
crc32 <<= 1U;
}
}
len--;
}
return (crc32);
}
/**
\brief Get serial number string. First characters are fixed. Last eight
characters are Unique (calculated from devices's unique ID)
\return Serial number string or NULL (callculation of unique ID failed)
*/
char *GetSerialNum (void) {
uint32_t command_param[5];
uint32_t status_result[5];
uint32_t uid;
char *str;
IAP iap_entry;
memset(command_param, 0, sizeof(command_param));
memset(status_result, 0, sizeof(status_result));
iap_entry = (IAP)IAP_LOCATION;
command_param[0] = IAP_READ_DEVICE_SERIAL_NUMBER;
iap_entry(command_param, status_result);
str = NULL;
if (status_result[0] == 0U) {
uid = crc32 ((uint8_t *)&status_result[1], 16U);
snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid);
str = SerialNum;
}
return (str);
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/ser_num.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 647 |
```objective-c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_Config_CustomClass_0.h
* Purpose: USB Device Custom Class Configuration
* Rev.: V5.2.0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Custom Class 0
// <i>Custom Class can be used to make support for Standard or Vendor-Specific Class
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CUSTOM_CLASS0_DEV 0
// <e0.0>Interface Association
// <i>Used for grouping of multiple interfaces to a single class.
#define USBD_CUSTOM_CLASS0_IAD_EN 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF0_EN 1
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF0_NUM 0
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF0_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 0.
#define USBD_CUSTOM_CLASS0_IF0_STR_EN 1
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF0_STR L"MCU-LINK CMSIS-DAP"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR L"{CDB3B5AD-293B-4663-AA36-1AAE46463776}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF1_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF1_NUM 1
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF1_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 1.
#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF1_STR L"USB_CUSTOM_CLASS0_IF1"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF2_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF2_NUM 2
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF2_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 2.
#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF2_STR L"USB_CUSTOM_CLASS0_IF2"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF3_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF3_NUM 3
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF3_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 3.
#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF3_STR L"USB_CUSTOM_CLASS0_IF3"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Endpoint 1 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 1 is enabled.
#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512
// Endpoint 1 Thread Priority
#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 2 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 2 is enabled.
#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512
// Endpoint 2 Thread Priority
#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 3 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 3 is enabled.
#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512
// Endpoint 3 Thread Priority
#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 4 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 4 is enabled.
#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512
// Endpoint 4 Thread Priority
#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 5 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 5 is enabled.
#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512
// Endpoint 5 Thread Priority
#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 6 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 6 is enabled.
#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512
// Endpoint 6 Thread Priority
#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 7 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 7 is enabled.
#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512
// Endpoint 7 Thread Priority
#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 8 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 8 is enabled.
#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512
// Endpoint 8 Thread Priority
#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 9 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 9 is enabled.
#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512
// Endpoint 9 Thread Priority
#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 10 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 10 is enabled.
#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512
// Endpoint 10 Thread Priority
#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 11 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 11 is enabled.
#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512
// Endpoint 11 Thread Priority
#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 12 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 12 is enabled.
#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512
// Endpoint 12 Thread Priority
#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 13 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 13 is enabled.
#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512
// Endpoint 13 Thread Priority
#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 14 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 14 is enabled.
#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512
// Endpoint 14 Thread Priority
#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 15 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 15 is enabled.
#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512
// Endpoint 15 Thread Priority
#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 49,405 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 21. May 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: main.c CMSIS-DAP Main module for LPC-Link2
*
*your_sha256_hash-----------*/
#include "cmsis_os2.h"
#include "osObjects.h"
#include "rl_usb.h"
#include "DAP_config.h"
#include "DAP.h"
// Application Main program
__NO_RETURN void app_main (void *argument) {
(void)argument;
DAP_Setup(); // DAP Setup
USBD_Initialize(0U); // USB Device Initialization
#ifdef LPC_LINK2_ONBOARD
char *ser_num;
ser_num = GetSerialNum();
if (ser_num != NULL) {
USBD_SetSerialNumber(0U, ser_num); // Update Serial Number
}
#endif
USBD_Connect(0U); // USB Device Connect
while (!USBD_Configured(0U)); // Wait for USB Device to configure
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
LED_RUNNING_OUT(1U); // Turn on Target Running LED
Delayms(500U); // Wait for 500ms
LED_RUNNING_OUT(0U); // Turn off Target Running LED
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
// Create DAP Thread
DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
// Create SWO Thread
SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
osDelay(osWaitForever);
for (;;) {}
}
int main (void) {
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
for (;;) {}
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 513 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 11. June 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Examples LPC-Link2
* Title: osObjects.h CMSIS-DAP RTOS2 Objects for LPC-Link2
*
*your_sha256_hash-----------*/
#ifndef __osObjects_h__
#define __osObjects_h__
#include "cmsis_os2.h"
#ifdef osObjectsExternal
extern osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
#else
static const osThreadAttr_t DAP_ThreadAttr = {
.priority = osPriorityNormal
};
static const osThreadAttr_t SWO_ThreadAttr = {
.priority = osPriorityAboveNormal
};
extern osThreadId_t DAP_ThreadId;
osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
osThreadId_t SWO_ThreadId;
#endif
extern void DAP_Thread (void *argument);
extern void SWO_Thread (void *argument);
extern void app_main (void *argument);
#endif /* __osObjects_h__ */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/osObjects.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 285 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* your_sha256_hash-------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
break;
}
for (;;) {}
//return 0U;
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 342 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.5.1
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 32
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <h>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x01U
#endif
// <h>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x01U
#endif
// <h>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x05U
#endif
// <h>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x01U
#endif
// <h>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x01U
#endif
// <h>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x01U
#endif
// <h>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x01U
#endif
// <h>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x01U
#endif
// <h>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
#endif
// <h>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x01U
#endif
// <h>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 4,270 |
```objective-c
/* your_sha256_hash----------
* rights reserved.
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* $Date: 25. April 2016
* $Revision: V2.2.1
*
* Project: RTE Device Configuration for NXP LPC43xx
* your_sha256_hash---------- */
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
#define RTE_USB_USB0 1
// <h> Pin Configuration
// <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
// <i> VBUS drive signal (towards external charge pump or power management unit).
#define RTE_USB0_PPWR_ID 0
#if (RTE_USB0_PPWR_ID == 0)
#define RTE_USB0_PPWR_PIN_EN 0
#elif (RTE_USB0_PPWR_ID == 1)
#define RTE_USB0_PPWR_PORT 1
#define RTE_USB0_PPWR_BIT 7
#define RTE_USB0_PPWR_FUNC 4
#elif (RTE_USB0_PPWR_ID == 2)
#define RTE_USB0_PPWR_PORT 2
#define RTE_USB0_PPWR_BIT 0
#define RTE_USB0_PPWR_FUNC 3
#elif (RTE_USB0_PPWR_ID == 3)
#define RTE_USB0_PPWR_PORT 2
#define RTE_USB0_PPWR_BIT 3
#define RTE_USB0_PPWR_FUNC 7
#elif (RTE_USB0_PPWR_ID == 4)
#define RTE_USB0_PPWR_PORT 6
#define RTE_USB0_PPWR_BIT 3
#define RTE_USB0_PPWR_FUNC 1
#else
#error "Invalid RTE_USB0_PPWR Pin Configuration!"
#endif
#ifndef RTE_USB0_PPWR_PIN_EN
#define RTE_USB0_PPWR_PIN_EN 1
#endif
// <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
// <i> Port power fault signal indicating overcurrent condition.
// <i> This signal monitors over-current on the USB bus
// (external circuitry required to detect over-current condition).
#define RTE_USB0_PWR_FAULT_ID 0
#if (RTE_USB0_PWR_FAULT_ID == 0)
#define RTE_USB0_PWR_FAULT_PIN_EN 0
#elif (RTE_USB0_PWR_FAULT_ID == 1)
#define RTE_USB0_PWR_FAULT_PORT 1
#define RTE_USB0_PWR_FAULT_BIT 5
#define RTE_USB0_PWR_FAULT_FUNC 4
#elif (RTE_USB0_PWR_FAULT_ID == 2)
#define RTE_USB0_PWR_FAULT_PORT 2
#define RTE_USB0_PWR_FAULT_BIT 1
#define RTE_USB0_PWR_FAULT_FUNC 3
#elif (RTE_USB0_PWR_FAULT_ID == 3)
#define RTE_USB0_PWR_FAULT_PORT 2
#define RTE_USB0_PWR_FAULT_BIT 4
#define RTE_USB0_PWR_FAULT_FUNC 7
#elif (RTE_USB0_PWR_FAULT_ID == 4)
#define RTE_USB0_PWR_FAULT_PORT 6
#define RTE_USB0_PWR_FAULT_BIT 6
#define RTE_USB0_PWR_FAULT_FUNC 3
#elif (RTE_USB0_PWR_FAULT_ID == 5)
#define RTE_USB0_PWR_FAULT_PORT 8
#define RTE_USB0_PWR_FAULT_BIT 0
#define RTE_USB0_PWR_FAULT_FUNC 1
#else
#error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
#endif
#ifndef RTE_USB0_PWR_FAULT_PIN_EN
#define RTE_USB0_PWR_FAULT_PIN_EN 1
#endif
// <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
// <i> USB0 port indicator LED control output 0
#define RTE_USB0_IND0_ID 0
#if (RTE_USB0_IND0_ID == 0)
#define RTE_USB0_IND0_PIN_EN 0
#elif (RTE_USB0_IND0_ID == 1)
#define RTE_USB0_IND0_PORT 1
#define RTE_USB0_IND0_BIT 4
#define RTE_USB0_IND0_FUNC 4
#elif (RTE_USB0_IND0_ID == 2)
#define RTE_USB0_IND0_PORT 2
#define RTE_USB0_IND0_BIT 5
#define RTE_USB0_IND0_FUNC 7
#elif (RTE_USB0_IND0_ID == 3)
#define RTE_USB0_IND0_PORT 2
#define RTE_USB0_IND0_BIT 6
#define RTE_USB0_IND0_FUNC 3
#elif (RTE_USB0_IND0_ID == 4)
#define RTE_USB0_IND0_PORT 6
#define RTE_USB0_IND0_BIT 8
#define RTE_USB0_IND0_FUNC 3
#elif (RTE_USB0_IND0_ID == 5)
#define RTE_USB0_IND0_PORT 8
#define RTE_USB0_IND0_BIT 2
#define RTE_USB0_IND0_FUNC 1
#else
#error "Invalid RTE_USB0_IND0 Pin Configuration!"
#endif
#ifndef RTE_USB0_IND0_PIN_EN
#define RTE_USB0_IND0_PIN_EN 1
#endif
// <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
// <i> USB0 port indicator LED control output 1
#define RTE_USB0_IND1_ID 0
#if (RTE_USB0_IND1_ID == 0)
#define RTE_USB0_IND1_PIN_EN 0
#elif (RTE_USB0_IND1_ID == 1)
#define RTE_USB0_IND1_PORT 1
#define RTE_USB0_IND1_BIT 3
#define RTE_USB0_IND1_FUNC 4
#elif (RTE_USB0_IND1_ID == 2)
#define RTE_USB0_IND1_PORT 2
#define RTE_USB0_IND1_BIT 2
#define RTE_USB0_IND1_FUNC 3
#elif (RTE_USB0_IND1_ID == 3)
#define RTE_USB0_IND1_PORT 6
#define RTE_USB0_IND1_BIT 7
#define RTE_USB0_IND1_FUNC 3
#elif (RTE_USB0_IND1_ID == 4)
#define RTE_USB0_IND1_PORT 8
#define RTE_USB0_IND1_BIT 1
#define RTE_USB0_IND1_FUNC 1
#else
#error "Invalid RTE_USB0_IND1 Pin Configuration!"
#endif
#ifndef RTE_USB0_IND1_PIN_EN
#define RTE_USB0_IND1_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> Device [Driver_USBD0]
// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
// <o.0> High-speed
// <i> Enable high-speed functionality
#define RTE_USB_USB0_HS_EN 1
// </h> Device [Driver_USBD0]
// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
#define RTE_USB_USB1 0
// <h> Pin Configuration
// <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
// <i> VBUS drive signal (towards external charge pump or power management unit).
#define RTE_USB1_PPWR_ID 1
#if (RTE_USB1_PPWR_ID == 0)
#define RTE_USB1_PPWR_PIN_EN 0
#elif (RTE_USB1_PPWR_ID == 1)
#define RTE_USB1_PPWR_PORT 9
#define RTE_USB1_PPWR_BIT 5
#define RTE_USB1_PPWR_FUNC 2
#else
#error "Invalid RTE_USB1_PPWR Pin Configuration!"
#endif
#ifndef RTE_USB1_PPWR_PIN_EN
#define RTE_USB1_PPWR_PIN_EN 1
#endif
// <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
// <i> Port power fault signal indicating overcurrent condition.
// <i> This signal monitors over-current on the USB bus
// (external circuitry required to detect over-current condition).
#define RTE_USB1_PWR_FAULT_ID 1
#if (RTE_USB1_PWR_FAULT_ID == 0)
#define RTE_USB1_PWR_FAULT_PIN_EN 0
#elif (RTE_USB1_PWR_FAULT_ID == 1)
#define RTE_USB1_PWR_FAULT_PORT 9
#define RTE_USB1_PWR_FAULT_BIT 6
#define RTE_USB1_PWR_FAULT_FUNC 2
#else
#error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
#endif
#ifndef RTE_USB1_PWR_FAULT_PIN_EN
#define RTE_USB1_PWR_FAULT_PIN_EN 1
#endif
// <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
// <i> USB1 port indicator LED control output 0
#define RTE_USB1_IND0_ID 1
#if (RTE_USB1_IND0_ID == 0)
#define RTE_USB1_IND0_PIN_EN 0
#elif (RTE_USB1_IND0_ID == 1)
#define RTE_USB1_IND0_PORT 3
#define RTE_USB1_IND0_BIT 2
#define RTE_USB1_IND0_FUNC 3
#elif (RTE_USB1_IND0_ID == 2)
#define RTE_USB1_IND0_PORT 9
#define RTE_USB1_IND0_BIT 4
#define RTE_USB1_IND0_FUNC 2
#else
#error "Invalid RTE_USB1_IND0 Pin Configuration!"
#endif
#ifndef RTE_USB1_IND0_PIN_EN
#define RTE_USB1_IND0_PIN_EN 1
#endif
// <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
// <i> USB1 port indicator LED control output 1
#define RTE_USB1_IND1_ID 1
#if (RTE_USB1_IND1_ID == 0)
#define RTE_USB1_IND1_PIN_EN 0
#elif (RTE_USB1_IND1_ID == 1)
#define RTE_USB1_IND1_PORT 3
#define RTE_USB1_IND1_BIT 1
#define RTE_USB1_IND1_FUNC 3
#elif (RTE_USB1_IND1_ID == 2)
#define RTE_USB1_IND1_PORT 9
#define RTE_USB1_IND1_BIT 3
#define RTE_USB1_IND1_FUNC 2
#else
#error "Invalid RTE_USB1_IND1 Pin Configuration!"
#endif
#ifndef RTE_USB1_IND1_PIN_EN
#define RTE_USB1_IND1_PIN_EN 1
#endif
// <e> On-chip full-speed PHY
#define RTE_USB_USB1_FS_PHY_EN 1
// <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
// <i> Monitors the presence of USB1 bus power.
#define RTE_USB1_VBUS_ID 1
#if (RTE_USB1_VBUS_ID == 0)
#define RTE_USB1_VBUS_PIN_EN 0
#elif (RTE_USB1_VBUS_ID == 1)
#define RTE_USB1_VBUS_PORT 2
#define RTE_USB1_VBUS_BIT 5
#define RTE_USB1_VBUS_FUNC 2
#else
#error "Invalid RTE_USB1_VBUS Pin Configuration!"
#endif
#ifndef RTE_USB1_VBUS_PIN_EN
#define RTE_USB1_VBUS_PIN_EN 1
#endif
// </e> On-chip full-speed PHY
// <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
#define RTE_USB_USB1_HS_PHY_EN 0
// <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
// <i> USB1 ULPI link CLK signal.
// <i> 60 MHz clock generated by the PHY.
#define RTE_USB1_ULPI_CLK_ID 0
#if (RTE_USB1_ULPI_CLK_ID == 0)
#define RTE_USB1_ULPI_CLK_PORT 8
#define RTE_USB1_ULPI_CLK_BIT 8
#define RTE_USB1_ULPI_CLK_FUNC 1
#elif (RTE_USB1_ULPI_CLK_ID == 1)
#define RTE_USB1_ULPI_CLK_PORT 0xC
#define RTE_USB1_ULPI_CLK_BIT 0
#define RTE_USB1_ULPI_CLK_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
#endif
// <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
// <i> USB1 ULPI link DIR signal.
// <i> Controls the ULPI data line direction.
#define RTE_USB1_ULPI_DIR_ID 0
#if (RTE_USB1_ULPI_DIR_ID == 0)
#define RTE_USB1_ULPI_DIR_PORT 0xB
#define RTE_USB1_ULPI_DIR_BIT 1
#define RTE_USB1_ULPI_DIR_FUNC 1
#elif (RTE_USB1_ULPI_DIR_ID == 1)
#define RTE_USB1_ULPI_DIR_PORT 0xC
#define RTE_USB1_ULPI_DIR_BIT 11
#define RTE_USB1_ULPI_DIR_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
#endif
// <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
// <i> USB1 ULPI link STP signal.
// <i> Asserted to end or interrupt transfers to the PHY.
#define RTE_USB1_ULPI_STP_ID 0
#if (RTE_USB1_ULPI_STP_ID == 0)
#define RTE_USB1_ULPI_STP_PORT 8
#define RTE_USB1_ULPI_STP_BIT 7
#define RTE_USB1_ULPI_STP_FUNC 1
#elif (RTE_USB1_ULPI_STP_ID == 1)
#define RTE_USB1_ULPI_STP_PORT 0xC
#define RTE_USB1_ULPI_STP_BIT 10
#define RTE_USB1_ULPI_STP_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
#endif
// <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
// <i> USB1 ULPI link NXT signal.
// <i> Data flow control signal from the PHY.
#define RTE_USB1_ULPI_NXT_ID 0
#if (RTE_USB1_ULPI_NXT_ID == 0)
#define RTE_USB1_ULPI_NXT_PORT 8
#define RTE_USB1_ULPI_NXT_BIT 6
#define RTE_USB1_ULPI_NXT_FUNC 1
#elif (RTE_USB1_ULPI_NXT_ID == 1)
#define RTE_USB1_ULPI_NXT_PORT 0xC
#define RTE_USB1_ULPI_NXT_BIT 9
#define RTE_USB1_ULPI_NXT_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
#endif
// <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
// <i> USB1 ULPI link bidirectional data line 0.
#define RTE_USB1_ULPI_D0_ID 0
#if (RTE_USB1_ULPI_D0_ID == 0)
#define RTE_USB1_ULPI_D0_PORT 8
#define RTE_USB1_ULPI_D0_BIT 5
#define RTE_USB1_ULPI_D0_FUNC 1
#elif (RTE_USB1_ULPI_D0_ID == 1)
#define RTE_USB1_ULPI_D0_PORT 0xC
#define RTE_USB1_ULPI_D0_BIT 8
#define RTE_USB1_ULPI_D0_FUNC 1
#elif (RTE_USB1_ULPI_D0_ID == 2)
#define RTE_USB1_ULPI_D0_PORT 0xD
#define RTE_USB1_ULPI_D0_BIT 11
#define RTE_USB1_ULPI_D0_FUNC 5
#else
#error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
#endif
// <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
// <i> USB1 ULPI link bidirectional data line 1.
#define RTE_USB1_ULPI_D1_ID 0
#if (RTE_USB1_ULPI_D1_ID == 0)
#define RTE_USB1_ULPI_D1_PORT 8
#define RTE_USB1_ULPI_D1_BIT 4
#define RTE_USB1_ULPI_D1_FUNC 1
#elif (RTE_USB1_ULPI_D1_ID == 1)
#define RTE_USB1_ULPI_D1_PORT 0xC
#define RTE_USB1_ULPI_D1_BIT 7
#define RTE_USB1_ULPI_D1_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
#endif
// <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
// <i> USB1 ULPI link bidirectional data line 2.
#define RTE_USB1_ULPI_D2_ID 0
#if (RTE_USB1_ULPI_D2_ID == 0)
#define RTE_USB1_ULPI_D2_PORT 8
#define RTE_USB1_ULPI_D2_BIT 3
#define RTE_USB1_ULPI_D2_FUNC 1
#elif (RTE_USB1_ULPI_D2_ID == 1)
#define RTE_USB1_ULPI_D2_PORT 0xC
#define RTE_USB1_ULPI_D2_BIT 6
#define RTE_USB1_ULPI_D2_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
#endif
// <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
// <i> USB1 ULPI link bidirectional data line 3.
#define RTE_USB1_ULPI_D3_ID 0
#if (RTE_USB1_ULPI_D3_ID == 0)
#define RTE_USB1_ULPI_D3_PORT 0xB
#define RTE_USB1_ULPI_D3_BIT 6
#define RTE_USB1_ULPI_D3_FUNC 1
#elif (RTE_USB1_ULPI_D3_ID == 1)
#define RTE_USB1_ULPI_D3_PORT 0xC
#define RTE_USB1_ULPI_D3_BIT 5
#define RTE_USB1_ULPI_D3_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
#endif
// <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
// <i> USB1 ULPI link bidirectional data line 4.
#define RTE_USB1_ULPI_D4_ID 0
#if (RTE_USB1_ULPI_D4_ID == 0)
#define RTE_USB1_ULPI_D4_PORT 0xB
#define RTE_USB1_ULPI_D4_BIT 5
#define RTE_USB1_ULPI_D4_FUNC 1
#elif (RTE_USB1_ULPI_D4_ID == 1)
#define RTE_USB1_ULPI_D4_PORT 0xC
#define RTE_USB1_ULPI_D4_BIT 4
#define RTE_USB1_ULPI_D4_FUNC 1
#else
#error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
#endif
// <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
// <i> USB1 ULPI link bidirectional data line 5.
#define RTE_USB1_ULPI_D5_ID 0
#if (RTE_USB1_ULPI_D5_ID == 0)
#define RTE_USB1_ULPI_D5_PORT 0xB
#define RTE_USB1_ULPI_D5_BIT 4
#define RTE_USB1_ULPI_D5_FUNC 1
#elif (RTE_USB1_ULPI_D5_ID == 1)
#define RTE_USB1_ULPI_D5_PORT 0xC
#define RTE_USB1_ULPI_D5_BIT 3
#define RTE_USB1_ULPI_D5_FUNC 0
#else
#error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
#endif
// <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
// <i> USB1 ULPI link bidirectional data line 6.
#define RTE_USB1_ULPI_D6_ID 0
#if (RTE_USB1_ULPI_D6_ID == 0)
#define RTE_USB1_ULPI_D6_PORT 0xB
#define RTE_USB1_ULPI_D6_BIT 3
#define RTE_USB1_ULPI_D6_FUNC 1
#elif (RTE_USB1_ULPI_D6_ID == 1)
#define RTE_USB1_ULPI_D6_PORT 0xC
#define RTE_USB1_ULPI_D6_BIT 2
#define RTE_USB1_ULPI_D6_FUNC 0
#else
#error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
#endif
// <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
// <i> USB1 ULPI link bidirectional data line 7.
#define RTE_USB1_ULPI_D7_ID 0
#if (RTE_USB1_ULPI_D7_ID == 0)
#define RTE_USB1_ULPI_D7_PORT 0xB
#define RTE_USB1_ULPI_D7_BIT 2
#define RTE_USB1_ULPI_D7_FUNC 1
#elif (RTE_USB1_ULPI_D7_ID == 1)
#define RTE_USB1_ULPI_D7_PORT 0xC
#define RTE_USB1_ULPI_D7_BIT 1
#define RTE_USB1_ULPI_D7_FUNC 0
#else
#error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
#endif
// </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
// </h> Pin Configuration
// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
#define RTE_ENET 0
// <e> MII (Media Independent Interface)
#define RTE_ENET_MII 0
// <o> ENET_TXD0 Pin <0=>P1_18
#define RTE_ENET_MII_TXD0_PORT_ID 0
#if (RTE_ENET_MII_TXD0_PORT_ID == 0)
#define RTE_ENET_MII_TXD0_PORT 1
#define RTE_ENET_MII_TXD0_PIN 18
#define RTE_ENET_MII_TXD0_FUNC 3
#else
#error "Invalid ENET_TXD0 Pin Configuration!"
#endif
// <o> ENET_TXD1 Pin <0=>P1_20
#define RTE_ENET_MII_TXD1_PORT_ID 0
#if (RTE_ENET_MII_TXD1_PORT_ID == 0)
#define RTE_ENET_MII_TXD1_PORT 1
#define RTE_ENET_MII_TXD1_PIN 20
#define RTE_ENET_MII_TXD1_FUNC 3
#else
#error "Invalid ENET_TXD1 Pin Configuration!"
#endif
// <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
#define RTE_ENET_MII_TXD2_PORT_ID 0
#if (RTE_ENET_MII_TXD2_PORT_ID == 0)
#define RTE_ENET_MII_TXD2_PORT 9
#define RTE_ENET_MII_TXD2_PIN 4
#define RTE_ENET_MII_TXD2_FUNC 5
#elif (RTE_ENET_MII_TXD2_PORT_ID == 1)
#define RTE_ENET_MII_TXD2_PORT 0xC
#define RTE_ENET_MII_TXD2_PIN 2
#define RTE_ENET_MII_TXD2_FUNC 3
#else
#error "Invalid ENET_TXD2 Pin Configuration!"
#endif
// <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
#define RTE_ENET_MII_TXD3_PORT_ID 0
#if (RTE_ENET_MII_TXD3_PORT_ID == 0)
#define RTE_ENET_MII_TXD3_PORT 9
#define RTE_ENET_MII_TXD3_PIN 5
#define RTE_ENET_MII_TXD3_FUNC 5
#elif (RTE_ENET_MII_TXD3_PORT_ID == 1)
#define RTE_ENET_MII_TXD3_PORT 0xC
#define RTE_ENET_MII_TXD3_PIN 3
#define RTE_ENET_MII_TXD3_FUNC 3
#else
#error "Invalid ENET_TXD3 Pin Configuration!"
#endif
// <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
#define RTE_ENET_MII_TX_EN_PORT_ID 0
#if (RTE_ENET_MII_TX_EN_PORT_ID == 0)
#define RTE_ENET_MII_TX_EN_PORT 0
#define RTE_ENET_MII_TX_EN_PIN 1
#define RTE_ENET_MII_TX_EN_FUNC 6
#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1)
#define RTE_ENET_MII_TX_EN_PORT 0xC
#define RTE_ENET_MII_TX_EN_PIN 4
#define RTE_ENET_MII_TX_EN_FUNC 3
#else
#error "Invalid ENET_TX_EN Pin Configuration!"
#endif
// <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
#define RTE_ENET_MII_TX_CLK_PORT_ID 0
#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
#define RTE_ENET_MII_TX_CLK_PORT 1
#define RTE_ENET_MII_TX_CLK_PIN 19
#define RTE_ENET_MII_TX_CLK_FUNC 0
#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
#define RTE_ENET_MII_TX_CLK_PORT 0x10
#define RTE_ENET_MII_TX_CLK_PIN 0
#define RTE_ENET_MII_TX_CLK_FUNC 7
#else
#error "Invalid ENET_TX_CLK Pin Configuration!"
#endif
// <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
// <i> Optional signal, rarely used
#define RTE_ENET_MII_TX_ER_PORT_ID 0
#if (RTE_ENET_MII_TX_ER_PORT_ID == 0)
#define RTE_ENET_MII_TX_ER_PIN_EN 0
#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1)
#define RTE_ENET_MII_TX_ER_PORT 0xC
#define RTE_ENET_MII_TX_ER_PIN 5
#define RTE_ENET_MII_TX_ER_FUNC 3
#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2)
#define RTE_ENET_MII_TX_ER_PORT 0xC
#define RTE_ENET_MII_TX_ER_PIN 14
#define RTE_ENET_MII_TX_ER_FUNC 6
#else
#error "Invalid ENET_TX_ER Pin Configuration!"
#endif
#ifndef RTE_ENET_MII_TX_ER_PIN_EN
#define RTE_ENET_MII_TX_ER_PIN_EN 1
#endif
// <o> ENET_RXD0 Pin <0=>P1_15
#define RTE_ENET_MII_RXD0_PORT_ID 0
#if (RTE_ENET_MII_RXD0_PORT_ID == 0)
#define RTE_ENET_MII_RXD0_PORT 1
#define RTE_ENET_MII_RXD0_PIN 15
#define RTE_ENET_MII_RXD0_FUNC 3
#else
#error "Invalid ENET_RXD0 Pin Configuration!"
#endif
// <o> ENET_RXD1 Pin <0=>P0_0
#define RTE_ENET_MII_RXD1_PORT_ID 0
#if (RTE_ENET_MII_RXD1_PORT_ID == 0)
#define RTE_ENET_MII_RXD1_PORT 0
#define RTE_ENET_MII_RXD1_PIN 0
#define RTE_ENET_MII_RXD1_FUNC 2
#else
#error "Invalid ENET_RXD1 Pin Configuration!"
#endif
// <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
#define RTE_ENET_MII_RXD2_PORT_ID 0
#if (RTE_ENET_MII_RXD2_PORT_ID == 0)
#define RTE_ENET_MII_RXD2_PORT 9
#define RTE_ENET_MII_RXD2_PIN 3
#define RTE_ENET_MII_RXD2_FUNC 5
#elif (RTE_ENET_MII_RXD2_PORT_ID == 1)
#define RTE_ENET_MII_RXD2_PORT 0xC
#define RTE_ENET_MII_RXD2_PIN 6
#define RTE_ENET_MII_RXD2_FUNC 3
#else
#error "Invalid ENET_RXD2 Pin Configuration!"
#endif
// <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
#define RTE_ENET_MII_RXD3_PORT_ID 0
#if (RTE_ENET_MII_RXD3_PORT_ID == 0)
#define RTE_ENET_MII_RXD3_PORT 9
#define RTE_ENET_MII_RXD3_PIN 2
#define RTE_ENET_MII_RXD3_FUNC 5
#elif (RTE_ENET_MII_RXD3_PORT_ID == 1)
#define RTE_ENET_MII_RXD3_PORT 0xC
#define RTE_ENET_MII_RXD3_PIN 7
#define RTE_ENET_MII_RXD3_FUNC 3
#else
#error "Invalid ENET_RXD3 Pin Configuration!"
#endif
// <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
#define RTE_ENET_MII_RX_DV_PORT_ID 0
#if (RTE_ENET_MII_RX_DV_PORT_ID == 0)
#define RTE_ENET_MII_RX_DV_PORT 1
#define RTE_ENET_MII_RX_DV_PIN 16
#define RTE_ENET_MII_RX_DV_FUNC 7
#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1)
#define RTE_ENET_MII_RX_DV_PORT 0xC
#define RTE_ENET_MII_RX_DV_PIN 8
#define RTE_ENET_MII_RX_DV_FUNC 3
#else
#error "Invalid ENET_RX_DV Pin Configuration!"
#endif
// <o> ENET_RX_CLK Pin <0=>PC_0
#define RTE_ENET_MII_RX_CLK_PORT_ID 0
#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
#define RTE_ENET_MII_RX_CLK_PORT 0xC
#define RTE_ENET_MII_RX_CLK_PIN 0
#define RTE_ENET_MII_RX_CLK_FUNC 3
#else
#error "Invalid ENET_RX_CLK Pin Configuration!"
#endif
// <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
#define RTE_ENET_MII_RX_ER_PORT_ID 0
#if (RTE_ENET_MII_RX_ER_PORT_ID == 0)
#define RTE_ENET_MII_RX_ER_PORT 9
#define RTE_ENET_MII_RX_ER_PIN 1
#define RTE_ENET_MII_RX_ER_FUNC 5
#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1)
#define RTE_ENET_MII_RX_ER_PORT 0xC
#define RTE_ENET_MII_RX_ER_PIN 9
#define RTE_ENET_MII_RX_ER_FUNC 3
#else
#error "Invalid ENET_RX_ER Pin Configuration!"
#endif
// <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
#define RTE_ENET_MII_COL_PORT_ID 0
#if (RTE_ENET_MII_COL_PORT_ID == 0)
#define RTE_ENET_MII_COL_PORT 0
#define RTE_ENET_MII_COL_PIN 1
#define RTE_ENET_MII_COL_FUNC 2
#elif (RTE_ENET_MII_COL_PORT_ID == 1)
#define RTE_ENET_MII_COL_PORT 4
#define RTE_ENET_MII_COL_PIN 1
#define RTE_ENET_MII_COL_FUNC 7
#elif (RTE_ENET_MII_COL_PORT_ID == 2)
#define RTE_ENET_MII_COL_PORT 9
#define RTE_ENET_MII_COL_PIN 6
#define RTE_ENET_MII_COL_FUNC 5
#else
#error "Invalid ENET_COL Pin Configuration!"
#endif
// <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
#define RTE_ENET_MII_CRS_PORT_ID 0
#if (RTE_ENET_MII_CRS_PORT_ID == 0)
#define RTE_ENET_MII_CRS_PORT 1
#define RTE_ENET_MII_CRS_PIN 16
#define RTE_ENET_MII_CRS_FUNC 3
#elif (RTE_ENET_MII_CRS_PORT_ID == 1)
#define RTE_ENET_MII_CRS_PORT 9
#define RTE_ENET_MII_CRS_PIN 0
#define RTE_ENET_MII_CRS_FUNC 5
#else
#error "Invalid ENET_CRS Pin Configuration!"
#endif
// </e> MII (Media Independent Interface)
// <e> RMII (Reduced Media Independent Interface)
#define RTE_ENET_RMII 0
// <o> ENET_TXD0 Pin <0=>P1_18
#define RTE_ENET_RMII_TXD0_PORT_ID 0
#if (RTE_ENET_RMII_TXD0_PORT_ID == 0)
#define RTE_ENET_RMII_TXD0_PORT 1
#define RTE_ENET_RMII_TXD0_PIN 18
#define RTE_ENET_RMII_TXD0_FUNC 3
#else
#error "Invalid ENET_TXD0 Pin Configuration!"
#endif
// <o> ENET_TXD1 Pin <0=>P1_20
#define RTE_ENET_RMII_TXD1_PORT_ID 0
#if (RTE_ENET_RMII_TXD1_PORT_ID == 0)
#define RTE_ENET_RMII_TXD1_PORT 1
#define RTE_ENET_RMII_TXD1_PIN 20
#define RTE_ENET_RMII_TXD1_FUNC 3
#else
#error "Invalid ENET_TXD1 Pin Configuration!"
#endif
// <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
#define RTE_ENET_RMII_TX_EN_PORT_ID 0
#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
#define RTE_ENET_RMII_TX_EN_PORT 0
#define RTE_ENET_RMII_TX_EN_PIN 1
#define RTE_ENET_RMII_TX_EN_FUNC 6
#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
#define RTE_ENET_RMII_TX_EN_PORT 0xC
#define RTE_ENET_RMII_TX_EN_PIN 4
#define RTE_ENET_RMII_TX_EN_FUNC 3
#else
#error "Invalid ENET_TX_EN Pin Configuration!"
#endif
// <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
#define RTE_ENET_RMII_REF_CLK_PORT_ID 0
#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
#define RTE_ENET_RMII_REF_CLK_PORT 1
#define RTE_ENET_RMII_REF_CLK_PIN 19
#define RTE_ENET_RMII_REF_CLK_FUNC 0
#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
#define RTE_ENET_RMII_REF_CLK_PORT 0x10
#define RTE_ENET_RMII_REF_CLK_PIN 0
#define RTE_ENET_RMII_REF_CLK_FUNC 7
#else
#error "Invalid ENET_REF_CLK Pin Configuration!"
#endif
// <o> ENET_RXD0 Pin <0=>P1_15
#define RTE_ENET_RMII_RXD0_PORT_ID 0
#if (RTE_ENET_RMII_RXD0_PORT_ID == 0)
#define RTE_ENET_RMII_RXD0_PORT 1
#define RTE_ENET_RMII_RXD0_PIN 15
#define RTE_ENET_RMII_RXD0_FUNC 3
#else
#error "Invalid ENET_RXD0 Pin Configuration!"
#endif
// <o> ENET_RXD1 Pin <0=>P0_0
#define RTE_ENET_RMII_RXD1_PORT_ID 0
#if (RTE_ENET_RMII_RXD1_PORT_ID == 0)
#define RTE_ENET_RMII_RXD1_PORT 0
#define RTE_ENET_RMII_RXD1_PIN 0
#define RTE_ENET_RMII_RXD1_FUNC 2
#else
#error "Invalid ENET_RXD1 Pin Configuration!"
#endif
// <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
#define RTE_ENET_RMII_RX_DV_PORT_ID 0
#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
#define RTE_ENET_RMII_RX_DV_PORT 1
#define RTE_ENET_RMII_RX_DV_PIN 16
#define RTE_ENET_RMII_RX_DV_FUNC 7
#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
#define RTE_ENET_RMII_RX_DV_PORT 0xC
#define RTE_ENET_RMII_RX_DV_PIN 8
#define RTE_ENET_RMII_RX_DV_FUNC 3
#else
#error "Invalid ENET_RX_DV Pin Configuration!"
#endif
// </e> RMII (Reduced Media Independent Interface)
// <h> MIIM (Management Data Interface)
// <o> ENET_MDIO Pin <0=>P1_17
#define RTE_ENET_MDI_MDIO_PORT_ID 0
#if (RTE_ENET_MDI_MDIO_PORT_ID == 0)
#define RTE_ENET_MDI_MDIO_PORT 1
#define RTE_ENET_MDI_MDIO_PIN 17
#define RTE_ENET_MDI_MDIO_FUNC 3
#else
#error "Invalid ENET_MDIO Pin Configuration!"
#endif
// <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
#define RTE_ENET_MDI_MDC_PORT_ID 2
#if (RTE_ENET_MDI_MDC_PORT_ID == 0)
#define RTE_ENET_MDI_MDC_PORT 2
#define RTE_ENET_MDI_MDC_PIN 0
#define RTE_ENET_MDI_MDC_FUNC 7
#elif (RTE_ENET_MDI_MDC_PORT_ID == 1)
#define RTE_ENET_MDI_MDC_PORT 7
#define RTE_ENET_MDI_MDC_PIN 7
#define RTE_ENET_MDI_MDC_FUNC 6
#elif (RTE_ENET_MDI_MDC_PORT_ID == 2)
#define RTE_ENET_MDI_MDC_PORT 0xC
#define RTE_ENET_MDI_MDC_PIN 1
#define RTE_ENET_MDI_MDC_FUNC 3
#else
#error "Invalid ENET_MDC Pin Configuration!"
#endif
// </h> MIIM (Management Data Interface)
// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
// <e> SD/MMC Interface [Driver_MCI0]
// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
#define RTE_SDMMC 0
// <h> SD/MMC Peripheral Bus
// <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
#define RTE_SD_CLK_PORT_ID 0
#if (RTE_SD_CLK_PORT_ID == 0)
#define RTE_SD_CLK_PORT 0xC
#define RTE_SD_CLK_PIN 0
#define RTE_SD_CLK_FUNC 7
#elif (RTE_SD_CLK_PORT_ID == 1)
#define RTE_SD_CLK_PORT 0x10
#define RTE_SD_CLK_PIN 0
#define RTE_SD_CLK_FUNC 4
#elif (RTE_SD_CLK_PORT_ID == 2)
#define RTE_SD_CLK_PORT 0x10
#define RTE_SD_CLK_PIN 2
#define RTE_SD_CLK_FUNC 4
#else
#error "Invalid SD_CLK Pin Configuration!"
#endif
// <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
#define RTE_SD_CMD_PORT_ID 0
#if (RTE_SD_CMD_PORT_ID == 0)
#define RTE_SD_CMD_PORT 1
#define RTE_SD_CMD_PIN 6
#define RTE_SD_CMD_FUNC 7
#elif (RTE_SD_CMD_PORT_ID == 1)
#define RTE_SD_CMD_PORT 0xC
#define RTE_SD_CMD_PIN 10
#define RTE_SD_CMD_FUNC 7
#else
#error "Invalid SD_CMD Pin Configuration!"
#endif
// <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
#define RTE_SD_DAT0_PORT_ID 0
#if (RTE_SD_DAT0_PORT_ID == 0)
#define RTE_SD_DAT0_PORT 1
#define RTE_SD_DAT0_PIN 9
#define RTE_SD_DAT0_FUNC 7
#elif (RTE_SD_DAT0_PORT_ID == 1)
#define RTE_SD_DAT0_PORT 0xC
#define RTE_SD_DAT0_PIN 4
#define RTE_SD_DAT0_FUNC 7
#else
#error "Invalid SD_DAT0 Pin Configuration!"
#endif
// <e> SD_DAT[1 .. 3]
#define RTE_SDMMC_BUS_WIDTH_4 0
// <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
#define RTE_SD_DAT1_PORT_ID 0
#if (RTE_SD_DAT1_PORT_ID == 0)
#define RTE_SD_DAT1_PORT 1
#define RTE_SD_DAT1_PIN 10
#define RTE_SD_DAT1_FUNC 7
#elif (RTE_SD_DAT1_PORT_ID == 1)
#define RTE_SD_DAT1_PORT 0xC
#define RTE_SD_DAT1_PIN 5
#define RTE_SD_DAT1_FUNC 7
#else
#error "Invalid SD_DAT1 Pin Configuration!"
#endif
// <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
#define RTE_SD_DAT2_PORT_ID 0
#if (RTE_SD_DAT2_PORT_ID == 0)
#define RTE_SD_DAT2_PORT 1
#define RTE_SD_DAT2_PIN 11
#define RTE_SD_DAT2_FUNC 7
#elif (RTE_SD_DAT2_PORT_ID == 1)
#define RTE_SD_DAT2_PORT 0xC
#define RTE_SD_DAT2_PIN 6
#define RTE_SD_DAT2_FUNC 7
#else
#error "Invalid SD_DAT2 Pin Configuration!"
#endif
// <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
#define RTE_SD_DAT3_PORT_ID 0
#if (RTE_SD_DAT3_PORT_ID == 0)
#define RTE_SD_DAT3_PORT 1
#define RTE_SD_DAT3_PIN 12
#define RTE_SD_DAT3_FUNC 7
#elif (RTE_SD_DAT3_PORT_ID == 1)
#define RTE_SD_DAT3_PORT 0xC
#define RTE_SD_DAT3_PIN 7
#define RTE_SD_DAT3_FUNC 7
#else
#error "Invalid SD_DAT3 Pin Configuration!"
#endif
// </e> SD_DAT[1 .. 3]
// <e> SD_DAT[4 .. 7]
#define RTE_SDMMC_BUS_WIDTH_8 0
// <o> SD_DAT4 Pin <0=>PC_11
#define RTE_SD_DAT4_PORT_ID 0
#if (RTE_SD_DAT4_PORT_ID == 0)
#define RTE_SD_DAT4_PORT 0xC
#define RTE_SD_DAT4_PIN 11
#define RTE_SD_DAT4_FUNC 7
#else
#error "Invalid SD_DAT4 Pin Configuration!"
#endif
// <o> SD_DAT5 Pin <0=>PC_12
#define RTE_SD_DAT5_PORT_ID 0
#if (RTE_SD_DAT5_PORT_ID == 0)
#define RTE_SD_DAT5_PORT 0xC
#define RTE_SD_DAT5_PIN 12
#define RTE_SD_DAT5_FUNC 7
#else
#error "Invalid SD_DAT5 Pin Configuration!"
#endif
// <o> SD_DAT6 Pin <0=>PC_13
#define RTE_SD_DAT6_PORT_ID 0
#if (RTE_SD_DAT6_PORT_ID == 0)
#define RTE_SD_DAT6_PORT 0xC
#define RTE_SD_DAT6_PIN 13
#define RTE_SD_DAT6_FUNC 7
#else
#error "Invalid SD_DAT6 Pin Configuration!"
#endif
// <o> SD_DAT7 Pin <0=>PC_14
#define RTE_SD_DAT7_PORT_ID 0
#if (RTE_SD_DAT7_PORT_ID == 0)
#define RTE_SD_DAT7_PORT 0xC
#define RTE_SD_DAT7_PIN 14
#define RTE_SD_DAT7_FUNC 7
#else
#error "Invalid SD_DAT7 Pin Configuration!"
#endif
// </e> SD_DAT[4 .. 7]
// </h> SD/MMC Peripheral Bus
// <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
// <i> Configure Pin if exists
#define RTE_SD_CD_PORT_ID 0
#if (RTE_SD_CD_PORT_ID == 0)
#define RTE_SD_CD_PIN_EN 0
#elif (RTE_SD_CD_PORT_ID == 1)
#define RTE_SD_CD_PORT 1
#define RTE_SD_CD_PIN 13
#define RTE_SD_CD_FUNC 7
#elif (RTE_SD_CD_PORT_ID == 2)
#define RTE_SD_CD_PORT 0xC
#define RTE_SD_CD_PIN 8
#define RTE_SD_CD_FUNC 7
#else
#error "Invalid SD_CD Pin Configuration!"
#endif
#ifndef RTE_SD_CD_PIN_EN
#define RTE_SD_CD_PIN_EN 1
#endif
// <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
// <i> Configure Pin if exists
#define RTE_SD_WP_PORT_ID 0
#if (RTE_SD_WP_PORT_ID == 0)
#define RTE_SD_WP_PIN_EN 0
#elif (RTE_SD_WP_PORT_ID == 1)
#define RTE_SD_WP_PORT 0xD
#define RTE_SD_WP_PIN 15
#define RTE_SD_WP_FUNC 5
#elif (RTE_SD_WP_PORT_ID == 2)
#define RTE_SD_WP_PORT 0xF
#define RTE_SD_WP_PIN 10
#define RTE_SD_WP_FUNC 6
#else
#error "Invalid SD_WP Pin Configuration!"
#endif
#ifndef RTE_SD_WP_PIN_EN
#define RTE_SD_WP_PIN_EN 1
#endif
// <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
// <i> Configure Pin if exists
#define RTE_SD_POW_PORT_ID 0
#if (RTE_SD_POW_PORT_ID == 0)
#define RTE_SD_POW_PIN_EN 0
#elif (RTE_SD_POW_PORT_ID == 1)
#define RTE_SD_POW_PORT 1
#define RTE_SD_POW_PIN 5
#define RTE_SD_POW_FUNC 7
#elif (RTE_SD_POW_PORT_ID == 2)
#define RTE_SD_POW_PORT 0xC
#define RTE_SD_POW_PIN 9
#define RTE_SD_POW_FUNC 7
#elif (RTE_SD_POW_PORT_ID == 3)
#define RTE_SD_POW_PORT 0xD
#define RTE_SD_POW_PIN 1
#define RTE_SD_POW_FUNC 5
#else
#error "Invalid SD_POW Pin Configuration!"
#endif
#ifndef RTE_SD_POW_PIN_EN
#define RTE_SD_POW_PIN_EN 1
#endif
// <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
// <i> Configure Pin if exists
#define RTE_SD_RST_PORT_ID 0
#if (RTE_SD_RST_PORT_ID == 0)
#define RTE_SD_RST_PIN_EN 0
#elif (RTE_SD_RST_PORT_ID == 1)
#define RTE_SD_RST_PORT 1
#define RTE_SD_RST_PIN 3
#define RTE_SD_RST_FUNC 7
#elif (RTE_SD_RST_PORT_ID == 2)
#define RTE_SD_RST_PORT 0xC
#define RTE_SD_RST_PIN 2
#define RTE_SD_RST_FUNC 7
#else
#error "Invalid SD_RST Pin Configuration!"
#endif
#ifndef RTE_SD_RST_PIN_EN
#define RTE_SD_RST_PIN_EN 1
#endif
// </e> SD/MMC Interface [Driver_MCI0]
// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
#define RTE_I2C0 0
// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
#define RTE_I2C1 0
// <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
#define RTE_I2C1_SCL_PORT_ID 0
#if (RTE_I2C1_SCL_PORT_ID == 0)
#define RTE_I2C1_SCL_PORT 2
#define RTE_I2C1_SCL_PIN 4
#define RTE_I2C1_SCL_FUNC 1
#elif (RTE_I2C1_SCL_PORT_ID == 1)
#define RTE_I2C1_SCL_PORT 0xE
#define RTE_I2C1_SCL_PIN 15
#define RTE_I2C1_SCL_FUNC 2
#else
#error "Invalid I2C1_SCL Pin Configuration!"
#endif
// <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
#define RTE_I2C1_SDA_PORT_ID 0
#if (RTE_I2C1_SDA_PORT_ID == 0)
#define RTE_I2C1_SDA_PORT 2
#define RTE_I2C1_SDA_PIN 3
#define RTE_I2C1_SDA_FUNC 1
#elif (RTE_I2C1_SDA_PORT_ID == 1)
#define RTE_I2C1_SDA_PORT 0xE
#define RTE_I2C1_SDA_PIN 13
#define RTE_I2C1_SDA_FUNC 2
#else
#error "Invalid I2C1_SDA Pin Configuration!"
#endif
// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
#define RTE_USART0 1
// <h> Pin Configuration
// <o> TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10
// <i> USART0 Serial Output pin
#define RTE_USART0_TX_ID 1
#if (RTE_USART0_TX_ID == 0)
#define RTE_USART0_TX_PIN_EN 0
#elif (RTE_USART0_TX_ID == 1)
#define RTE_USART0_TX_PORT 2
#define RTE_USART0_TX_BIT 0
#define RTE_USART0_TX_FUNC 1
#elif (RTE_USART0_TX_ID == 2)
#define RTE_USART0_TX_PORT 6
#define RTE_USART0_TX_BIT 4
#define RTE_USART0_TX_FUNC 2
#elif (RTE_USART0_TX_ID == 3)
#define RTE_USART0_TX_PORT 9
#define RTE_USART0_TX_BIT 5
#define RTE_USART0_TX_FUNC 7
#elif (RTE_USART0_TX_ID == 4)
#define RTE_USART0_TX_PORT 0xF
#define RTE_USART0_TX_BIT 10
#define RTE_USART0_TX_FUNC 1
#else
#error "Invalid USART0_TX Pin Configuration!"
#endif
#ifndef RTE_USART0_TX_PIN_EN
#define RTE_USART0_TX_PIN_EN 1
#endif
// <o> RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11
// <i> USART0 Serial Input pin
#define RTE_USART0_RX_ID 1
#if (RTE_USART0_RX_ID == 0)
#define RTE_USART0_RX_PIN_EN 0
#elif (RTE_USART0_RX_ID == 1)
#define RTE_USART0_RX_PORT 2
#define RTE_USART0_RX_BIT 1
#define RTE_USART0_RX_FUNC 1
#elif (RTE_USART0_RX_ID == 2)
#define RTE_USART0_RX_PORT 6
#define RTE_USART0_RX_BIT 5
#define RTE_USART0_RX_FUNC 2
#elif (RTE_USART0_RX_ID == 3)
#define RTE_USART0_RX_PORT 9
#define RTE_USART0_RX_BIT 6
#define RTE_USART0_RX_FUNC 7
#elif (RTE_USART0_RX_ID == 4)
#define RTE_USART0_RX_PORT 0xF
#define RTE_USART0_RX_BIT 11
#define RTE_USART0_RX_FUNC 1
#else
#error "Invalid USART0_RX Pin Configuration!"
#endif
#ifndef RTE_USART0_RX_PIN_EN
#define RTE_USART0_RX_PIN_EN 1
#endif
// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
// <i> USART0 Serial Clock input/output synchronous mode
#define RTE_USART0_UCLK_ID 0
#if (RTE_USART0_UCLK_ID == 0)
#define RTE_USART0_UCLK_PIN_EN 0
#elif (RTE_USART0_UCLK_ID == 1)
#define RTE_USART0_UCLK_PORT 2
#define RTE_USART0_UCLK_BIT 2
#define RTE_USART0_UCLK_FUNC 1
#elif (RTE_USART0_UCLK_ID == 2)
#define RTE_USART0_UCLK_PORT 6
#define RTE_USART0_UCLK_BIT 1
#define RTE_USART0_UCLK_FUNC 2
#elif (RTE_USART0_UCLK_ID == 3)
#define RTE_USART0_UCLK_PORT 0xF
#define RTE_USART0_UCLK_BIT 8
#define RTE_USART0_UCLK_FUNC 1
#else
#error "Invalid USART0_UCLK Pin Configuration!"
#endif
#ifndef RTE_USART0_UCLK_PIN_EN
#define RTE_USART0_UCLK_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11)
// </e>
#define RTE_USART0_DMA_TX_EN 0
#define RTE_USART0_DMA_TX_CH 0
#define RTE_USART0_DMA_TX_PERI_ID 0
#if (RTE_USART0_DMA_TX_PERI_ID == 0)
#define RTE_USART0_DMA_TX_PERI 1
#define RTE_USART0_DMA_TX_PERI_SEL 1
#elif (RTE_USART0_DMA_TX_PERI_ID == 1)
#define RTE_USART0_DMA_TX_PERI 11
#define RTE_USART0_DMA_TX_PERI_SEL 2
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12)
// </e>
#define RTE_USART0_DMA_RX_EN 0
#define RTE_USART0_DMA_RX_CH 1
#define RTE_USART0_DMA_RX_PERI_ID 0
#if (RTE_USART0_DMA_RX_PERI_ID == 0)
#define RTE_USART0_DMA_RX_PERI 2
#define RTE_USART0_DMA_RX_PERI_SEL 1
#elif (RTE_USART0_DMA_RX_PERI_ID == 1)
#define RTE_USART0_DMA_RX_PERI 12
#define RTE_USART0_DMA_RX_PERI_SEL 2
#endif
// </h> DMA
// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
#define RTE_UART1 1
// <h> Pin Configuration
// <o> TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11
// <i> UART0 Serial Output pin
#define RTE_UART1_TX_ID 0
#if (RTE_UART1_TX_ID == 0)
#define RTE_UART1_TX_PIN_EN 0
#elif (RTE_UART1_TX_ID == 1)
#define RTE_UART1_TX_PORT 1
#define RTE_UART1_TX_BIT 13
#define RTE_UART1_TX_FUNC 1
#elif (RTE_UART1_TX_ID == 2)
#define RTE_UART1_TX_PORT 3
#define RTE_UART1_TX_BIT 4
#define RTE_UART1_TX_FUNC 4
#elif (RTE_UART1_TX_ID == 3)
#define RTE_UART1_TX_PORT 5
#define RTE_UART1_TX_BIT 6
#define RTE_UART1_TX_FUNC 4
#elif (RTE_UART1_TX_ID == 4)
#define RTE_UART1_TX_PORT 0xC
#define RTE_UART1_TX_BIT 13
#define RTE_UART1_TX_FUNC 2
#elif (RTE_UART1_TX_ID == 5)
#define RTE_UART1_TX_PORT 0xE
#define RTE_UART1_TX_BIT 11
#define RTE_UART1_TX_FUNC 2
#else
#error "Invalid UART1_TX Pin Configuration!"
#endif
#ifndef RTE_UART1_TX_PIN_EN
#define RTE_UART1_TX_PIN_EN 1
#endif
// <o> RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12
// <i> UART1 Serial Input pin
#define RTE_UART1_RX_ID 1
#if (RTE_UART1_RX_ID == 0)
#define RTE_UART1_RX_PIN_EN 0
#elif (RTE_UART1_RX_ID == 1)
#define RTE_UART1_RX_PORT 1
#define RTE_UART1_RX_BIT 14
#define RTE_UART1_RX_FUNC 1
#elif (RTE_UART1_RX_ID == 2)
#define RTE_UART1_RX_PORT 3
#define RTE_UART1_RX_BIT 5
#define RTE_UART1_RX_FUNC 4
#elif (RTE_UART1_RX_ID == 3)
#define RTE_UART1_RX_PORT 5
#define RTE_UART1_RX_BIT 7
#define RTE_UART1_RX_FUNC 4
#elif (RTE_UART1_RX_ID == 4)
#define RTE_UART1_RX_PORT 0xC
#define RTE_UART1_RX_BIT 14
#define RTE_UART1_RX_FUNC 2
#elif (RTE_UART1_RX_ID == 5)
#define RTE_UART1_RX_PORT 0xE
#define RTE_UART1_RX_BIT 12
#define RTE_UART1_RX_FUNC 2
#else
#error "Invalid UART1_RX Pin Configuration!"
#endif
#ifndef RTE_UART1_RX_PIN_EN
#define RTE_UART1_RX_PIN_EN 1
#endif
// <h> Modem Lines
// <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
#define RTE_UART1_CTS_ID 0
#if (RTE_UART1_CTS_ID == 0)
#define RTE_UART1_CTS_PIN_EN 0
#elif (RTE_UART1_CTS_ID == 1)
#define RTE_UART1_CTS_PORT 1
#define RTE_UART1_CTS_BIT 11
#define RTE_UART1_CTS_FUNC 1
#elif (RTE_UART1_CTS_ID == 2)
#define RTE_UART1_CTS_PORT 5
#define RTE_UART1_CTS_BIT 4
#define RTE_UART1_CTS_FUNC 4
#elif (RTE_UART1_CTS_ID == 3)
#define RTE_UART1_CTS_PORT 0xC
#define RTE_UART1_CTS_BIT 2
#define RTE_UART1_CTS_FUNC 2
#elif (RTE_UART1_CTS_ID == 4)
#define RTE_UART1_CTS_PORT 0xE
#define RTE_UART1_CTS_BIT 7
#define RTE_UART1_CTS_FUNC 2
#else
#error "Invalid UART1_CTS Pin Configuration!"
#endif
#ifndef RTE_UART1_CTS_PIN_EN
#define RTE_UART1_CTS_PIN_EN 1
#endif
// <o> RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5
#define RTE_UART1_RTS_ID 0
#if (RTE_UART1_RTS_ID == 0)
#define RTE_UART1_RTS_PIN_EN 0
#elif (RTE_UART1_RTS_ID == 1)
#define RTE_UART1_RTS_PORT 1
#define RTE_UART1_RTS_BIT 9
#define RTE_UART1_RTS_FUNC 1
#elif (RTE_UART1_RTS_ID == 2)
#define RTE_UART1_RTS_PORT 5
#define RTE_UART1_RTS_BIT 2
#define RTE_UART1_RTS_FUNC 4
#elif (RTE_UART1_RTS_ID == 3)
#define RTE_UART1_RTS_PORT 0xC
#define RTE_UART1_RTS_BIT 3
#define RTE_UART1_RTS_FUNC 2
#elif (RTE_UART1_RTS_ID == 4)
#define RTE_UART1_RTS_PORT 0xE
#define RTE_UART1_RTS_BIT 5
#define RTE_UART1_RTS_FUNC 2
#else
#error "Invalid UART1_RTS Pin Configuration!"
#endif
#ifndef RTE_UART1_RTS_PIN_EN
#define RTE_UART1_RTS_PIN_EN 1
#endif
// <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
#define RTE_UART1_DCD_ID 0
#if (RTE_UART1_DCD_ID == 0)
#define RTE_UART1_DCD_PIN_EN 0
#elif (RTE_UART1_DCD_ID == 1)
#define RTE_UART1_DCD_PORT 1
#define RTE_UART1_DCD_BIT 12
#define RTE_UART1_DCD_FUNC 1
#elif (RTE_UART1_DCD_ID == 2)
#define RTE_UART1_DCD_PORT 5
#define RTE_UART1_DCD_BIT 5
#define RTE_UART1_DCD_FUNC 4
#elif (RTE_UART1_DCD_ID == 3)
#define RTE_UART1_DCD_PORT 0xC
#define RTE_UART1_DCD_BIT 11
#define RTE_UART1_DCD_FUNC 2
#elif (RTE_UART1_DCD_ID == 4)
#define RTE_UART1_DCD_PORT 0xE
#define RTE_UART1_DCD_BIT 9
#define RTE_UART1_DCD_FUNC 2
#else
#error "Invalid UART1_DCD Pin Configuration!"
#endif
#ifndef RTE_UART1_DCD_PIN_EN
#define RTE_UART1_DCD_PIN_EN 1
#endif
// <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
#define RTE_UART1_DSR_ID 0
#if (RTE_UART1_DSR_ID == 0)
#define RTE_UART1_DSR_PIN_EN 0
#elif (RTE_UART1_DSR_ID == 1)
#define RTE_UART1_DSR_PORT 1
#define RTE_UART1_DSR_BIT 7
#define RTE_UART1_DSR_FUNC 1
#elif (RTE_UART1_DSR_ID == 2)
#define RTE_UART1_DSR_PORT 5
#define RTE_UART1_DSR_BIT 0
#define RTE_UART1_DSR_FUNC 4
#elif (RTE_UART1_DSR_ID == 3)
#define RTE_UART1_DSR_PORT 0xC
#define RTE_UART1_DSR_BIT 10
#define RTE_UART1_DSR_FUNC 2
#elif (RTE_UART1_DSR_ID == 4)
#define RTE_UART1_DSR_PORT 0xE
#define RTE_UART1_DSR_BIT 8
#define RTE_UART1_DSR_FUNC 2
#else
#error "Invalid UART1_DSR Pin Configuration!"
#endif
#ifndef RTE_UART1_DSR_PIN_EN
#define RTE_UART1_DSR_PIN_EN 1
#endif
// <o> DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10
#define RTE_UART1_DTR_ID 0
#if (RTE_UART1_DTR_ID == 0)
#define RTE_UART1_DTR_PIN_EN 0
#elif (RTE_UART1_DTR_ID == 1)
#define RTE_UART1_DTR_PORT 1
#define RTE_UART1_DTR_BIT 8
#define RTE_UART1_DTR_FUNC 1
#elif (RTE_UART1_DTR_ID == 2)
#define RTE_UART1_DTR_PORT 5
#define RTE_UART1_DTR_BIT 1
#define RTE_UART1_DTR_FUNC 4
#elif (RTE_UART1_DTR_ID == 3)
#define RTE_UART1_DTR_PORT 0xC
#define RTE_UART1_DTR_BIT 12
#define RTE_UART1_DTR_FUNC 2
#elif (RTE_UART1_DTR_ID == 4)
#define RTE_UART1_DTR_PORT 0xE
#define RTE_UART1_DTR_BIT 10
#define RTE_UART1_DTR_FUNC 2
#else
#error "Invalid UART1_DTR Pin Configuration!"
#endif
#ifndef RTE_UART1_DTR_PIN_EN
#define RTE_UART1_DTR_PIN_EN 1
#endif
// <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
#define RTE_UART1_RI_ID 0
#if (RTE_UART1_RI_ID == 0)
#define RTE_UART1_RI_PIN_EN 0
#elif (RTE_UART1_RI_ID == 1)
#define RTE_UART1_RI_PORT 1
#define RTE_UART1_RI_BIT 10
#define RTE_UART1_RI_FUNC 1
#elif (RTE_UART1_RI_ID == 2)
#define RTE_UART1_RI_PORT 5
#define RTE_UART1_RI_BIT 3
#define RTE_UART1_RI_FUNC 4
#elif (RTE_UART1_RI_ID == 3)
#define RTE_UART1_RI_PORT 0xC
#define RTE_UART1_RI_BIT 1
#define RTE_UART1_RI_FUNC 2
#elif (RTE_UART1_RI_ID == 4)
#define RTE_UART1_RI_PORT 0xE
#define RTE_UART1_RI_BIT 6
#define RTE_UART1_RI_FUNC 2
#else
#error "Invalid UART1_RI Pin Configuration!"
#endif
#ifndef RTE_UART1_RI_PIN_EN
#define RTE_UART1_RI_PIN_EN 1
#endif
// </h> Modem Lines
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>3 (DMAMUXPER3)
// </e>
#define RTE_UART1_DMA_TX_EN 0
#define RTE_UART1_DMA_TX_CH 0
#define RTE_UART1_DMA_TX_PERI_ID 0
#if (RTE_UART1_DMA_TX_PERI_ID == 0)
#define RTE_UART1_DMA_TX_PERI 3
#define RTE_UART1_DMA_TX_PERI_SEL 1
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>4 (DMAMUXPER4)
// </e>
#define RTE_UART1_DMA_RX_EN 1
#define RTE_UART1_DMA_RX_CH 1
#define RTE_UART1_DMA_RX_PERI_ID 0
#if (RTE_UART1_DMA_RX_PERI_ID == 0)
#define RTE_UART1_DMA_RX_PERI 4
#define RTE_UART1_DMA_RX_PERI_SEL 1
#endif
// </h> DMA
// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
#define RTE_USART2 0
// <h> Pin Configuration
// <o> TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1
// <i> USART2 Serial Output pin
#define RTE_USART2_TX_ID 0
#if (RTE_USART2_TX_ID == 0)
#define RTE_USART2_TX_PIN_EN 0
#elif (RTE_USART2_TX_ID == 1)
#define RTE_USART2_TX_PORT 1
#define RTE_USART2_TX_BIT 15
#define RTE_USART2_TX_FUNC 1
#elif (RTE_USART2_TX_ID == 2)
#define RTE_USART2_TX_PORT 2
#define RTE_USART2_TX_BIT 10
#define RTE_USART2_TX_FUNC 2
#elif (RTE_USART2_TX_ID == 3)
#define RTE_USART2_TX_PORT 7
#define RTE_USART2_TX_BIT 1
#define RTE_USART2_TX_FUNC 6
#elif (RTE_USART2_TX_ID == 4)
#define RTE_USART2_TX_PORT 0xA
#define RTE_USART2_TX_BIT 1
#define RTE_USART2_TX_FUNC 3
#else
#error "Invalid USART2_TX Pin Configuration!"
#endif
#ifndef RTE_USART2_TX_PIN_EN
#define RTE_USART2_TX_PIN_EN 1
#endif
// <o> RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2
// <i> USART2 Serial Input pin
#define RTE_USART2_RX_ID 0
#if (RTE_USART2_RX_ID == 0)
#define RTE_USART2_RX_PIN_EN 0
#elif (RTE_USART2_RX_ID == 1)
#define RTE_USART2_RX_PORT 1
#define RTE_USART2_RX_BIT 16
#define RTE_USART2_RX_FUNC 1
#elif (RTE_USART2_RX_ID == 2)
#define RTE_USART2_RX_PORT 2
#define RTE_USART2_RX_BIT 11
#define RTE_USART2_RX_FUNC 2
#elif (RTE_USART2_RX_ID == 3)
#define RTE_USART2_RX_PORT 7
#define RTE_USART2_RX_BIT 2
#define RTE_USART2_RX_FUNC 6
#elif (RTE_USART2_RX_ID == 4)
#define RTE_USART2_RX_PORT 0xA
#define RTE_USART2_RX_BIT 2
#define RTE_USART2_RX_FUNC 3
#else
#error "Invalid USART2_RX Pin Configuration!"
#endif
#ifndef RTE_USART2_RX_PIN_EN
#define RTE_USART2_RX_PIN_EN 1
#endif
// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
// <i> USART2 Serial Clock input/output synchronous mode
#define RTE_USART2_UCLK_ID 0
#if (RTE_USART2_UCLK_ID == 0)
#define RTE_USART2_UCLK_PIN_EN 0
#elif (RTE_USART2_UCLK_ID == 1)
#define RTE_USART2_UCLK_PORT 1
#define RTE_USART2_UCLK_BIT 17
#define RTE_USART2_UCLK_FUNC 1
#elif (RTE_USART2_UCLK_ID == 2)
#define RTE_USART2_UCLK_PORT 2
#define RTE_USART2_UCLK_BIT 12
#define RTE_USART2_UCLK_FUNC 7
#else
#error "Invalid USART2_UCLK Pin Configuration!"
#endif
#ifndef RTE_USART2_UCLK_PIN_EN
#define RTE_USART2_UCLK_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>5 (DMAMUXPER5)
// </e>
#define RTE_USART2_DMA_TX_EN 0
#define RTE_USART2_DMA_TX_CH 0
#define RTE_USART2_DMA_TX_PERI_ID 0
#if (RTE_USART2_DMA_TX_PERI_ID == 0)
#define RTE_USART2_DMA_TX_PERI 5
#define RTE_USART2_DMA_TX_PERI_SEL 1
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>6 (DMAMUXPER6)
// </e>
#define RTE_USART2_DMA_RX_EN 0
#define RTE_USART2_DMA_RX_CH 1
#define RTE_USART2_DMA_RX_PERI_ID 0
#if (RTE_USART2_DMA_RX_PERI_ID == 0)
#define RTE_USART2_DMA_RX_PERI 6
#define RTE_USART2_DMA_RX_PERI_SEL 1
#endif
// </h> DMA
// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
#define RTE_USART3 0
// <h> Pin Configuration
// <o> TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2
// <i> USART3 Serial Output pin
#define RTE_USART3_TX_ID 0
#if (RTE_USART3_TX_ID == 0)
#define RTE_USART3_TX_PIN_EN 0
#elif (RTE_USART3_TX_ID == 1)
#define RTE_USART3_TX_PORT 2
#define RTE_USART3_TX_BIT 3
#define RTE_USART3_TX_FUNC 2
#elif (RTE_USART3_TX_ID == 2)
#define RTE_USART3_TX_PORT 4
#define RTE_USART3_TX_BIT 1
#define RTE_USART3_TX_FUNC 6
#elif (RTE_USART3_TX_ID == 3)
#define RTE_USART3_TX_PORT 9
#define RTE_USART3_TX_BIT 3
#define RTE_USART3_TX_FUNC 7
#elif (RTE_USART3_TX_ID == 4)
#define RTE_USART3_TX_PORT 0xF
#define RTE_USART3_TX_BIT 2
#define RTE_USART3_TX_FUNC 1
#else
#error "Invalid USART3_TX Pin Configuration!"
#endif
#ifndef RTE_USART3_TX_PIN_EN
#define RTE_USART3_TX_PIN_EN 1
#endif
// <o> RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3
// <i> USART3 Serial Input pin
#define RTE_USART3_RX_ID 0
#if (RTE_USART3_RX_ID == 0)
#define RTE_USART3_RX_PIN_EN 0
#elif (RTE_USART3_RX_ID == 1)
#define RTE_USART3_RX_PORT 2
#define RTE_USART3_RX_BIT 4
#define RTE_USART3_RX_FUNC 2
#elif (RTE_USART3_RX_ID == 2)
#define RTE_USART3_RX_PORT 4
#define RTE_USART3_RX_BIT 2
#define RTE_USART3_RX_FUNC 6
#elif (RTE_USART3_RX_ID == 3)
#define RTE_USART3_RX_PORT 9
#define RTE_USART3_RX_BIT 4
#define RTE_USART3_RX_FUNC 7
#elif (RTE_USART3_RX_ID == 4)
#define RTE_USART3_RX_PORT 0xF
#define RTE_USART3_RX_BIT 3
#define RTE_USART3_RX_FUNC 1
#else
#error "Invalid USART3_RX Pin Configuration!"
#endif
#ifndef RTE_USART3_RX_PIN_EN
#define RTE_USART3_RX_PIN_EN 1
#endif
// <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
// <i> USART3 Serial Clock input/output synchronous mode
#define RTE_USART3_UCLK_ID 0
#if (RTE_USART3_UCLK_ID == 0)
#define RTE_USART3_UCLK_PIN_EN 0
#elif (RTE_USART3_UCLK_ID == 1)
#define RTE_USART3_UCLK_PORT 2
#define RTE_USART3_UCLK_BIT 7
#define RTE_USART3_UCLK_FUNC 2
#elif (RTE_USART3_UCLK_ID == 2)
#define RTE_USART3_UCLK_PORT 4
#define RTE_USART3_UCLK_BIT 0
#define RTE_USART3_UCLK_FUNC 6
#elif (RTE_USART3_UCLK_ID == 3)
#define RTE_USART3_UCLK_PORT 0xF
#define RTE_USART3_UCLK_BIT 5
#define RTE_USART3_UCLK_FUNC 1
#else
#error "Invalid USART3_UCLK Pin Configuration!"
#endif
#ifndef RTE_USART3_UCLK_PIN_EN
#define RTE_USART3_UCLK_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14)
// </e>
#define RTE_USART3_DMA_TX_EN 0
#define RTE_USART3_DMA_TX_CH 0
#define RTE_USART3_DMA_TX_PERI_ID 0
#if (RTE_USART3_DMA_TX_PERI_ID == 0)
#define RTE_USART3_DMA_TX_PERI 7
#define RTE_USART3_DMA_TX_PERI_SEL 1
#elif (RTE_USART3_DMA_TX_PERI_ID == 1)
#define RTE_USART3_DMA_TX_PERI 14
#define RTE_USART3_DMA_TX_PERI_SEL 3
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13)
// </e>
#define RTE_USART3_DMA_RX_EN 0
#define RTE_USART3_DMA_RX_CH 1
#define RTE_USART3_DMA_RX_PERI_ID 0
#if (RTE_USART3_DMA_RX_PERI_ID == 0)
#define RTE_USART3_DMA_RX_PERI 8
#define RTE_USART3_DMA_RX_PERI_SEL 1
#elif (RTE_USART3_DMA_RX_PERI_ID == 1)
#define RTE_USART3_DMA_RX_PERI 13
#define RTE_USART3_DMA_RX_PERI_SEL 3
#endif
// </h> DMA
// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
#define RTE_SSP0 0
// <h> Pin Configuration
// <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
// <i> Slave Select for SSP0
#define RTE_SSP0_SSEL_PIN_SEL 1
#if (RTE_SSP0_SSEL_PIN_SEL == 0)
#define RTE_SSP0_SSEL_PIN_EN 0
#elif (RTE_SSP0_SSEL_PIN_SEL == 1)
#define RTE_SSP0_SSEL_PORT 1
#define RTE_SSP0_SSEL_BIT 0
#define RTE_SSP0_SSEL_FUNC 5
#define RTE_SSP0_SSEL_GPIO_FUNC 0
#define RTE_SSP0_SSEL_GPIO_PORT 0
#define RTE_SSP0_SSEL_GPIO_BIT 4
#elif (RTE_SSP0_SSEL_PIN_SEL == 2)
#define RTE_SSP0_SSEL_PORT 3
#define RTE_SSP0_SSEL_BIT 6
#define RTE_SSP0_SSEL_FUNC 2
#define RTE_SSP0_SSEL_GPIO_FUNC 0
#define RTE_SSP0_SSEL_GPIO_PORT 0
#define RTE_SSP0_SSEL_GPIO_BIT 6
#elif (RTE_SSP0_SSEL_PIN_SEL == 3)
#define RTE_SSP0_SSEL_PORT 3
#define RTE_SSP0_SSEL_BIT 8
#define RTE_SSP0_SSEL_FUNC 5
#define RTE_SSP0_SSEL_GPIO_FUNC 4
#define RTE_SSP0_SSEL_GPIO_PORT 5
#define RTE_SSP0_SSEL_GPIO_BIT 11
#elif (RTE_SSP0_SSEL_PIN_SEL == 4)
#define RTE_SSP0_SSEL_PORT 9
#define RTE_SSP0_SSEL_BIT 0
#define RTE_SSP0_SSEL_FUNC 7
#define RTE_SSP0_SSEL_GPIO_FUNC 0
#define RTE_SSP0_SSEL_GPIO_PORT 4
#define RTE_SSP0_SSEL_GPIO_BIT 12
#elif (RTE_SSP0_SSEL_PIN_SEL == 5)
#define RTE_SSP0_SSEL_PORT 0xF
#define RTE_SSP0_SSEL_BIT 1
#define RTE_SSP0_SSEL_FUNC 2
#define RTE_SSP0_SSEL_GPIO_FUNC 4
#define RTE_SSP0_SSEL_GPIO_PORT 7
#define RTE_SSP0_SSEL_GPIO_BIT 16
#else
#error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
#endif
#ifndef RTE_SSP0_SSEL_PIN_EN
#define RTE_SSP0_SSEL_PIN_EN 1
#endif
// <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
// <i> Serial clock for SSP0
#define RTE_SSP0_SCK_PIN_SEL 0
#if (RTE_SSP0_SCK_PIN_SEL == 0)
#define RTE_SSP0_SCK_PORT 3
#define RTE_SSP0_SCK_BIT 0
#define RTE_SSP0_SCK_FUNC 4
#elif (RTE_SSP0_SCK_PIN_SEL == 1)
#define RTE_SSP0_SCK_PORT 3
#define RTE_SSP0_SCK_BIT 3
#define RTE_SSP0_SCK_FUNC 2
#elif (RTE_SSP0_SCK_PIN_SEL == 2)
#define RTE_SSP0_SCK_PORT 0xF
#define RTE_SSP0_SCK_BIT 0
#define RTE_SSP0_SCK_FUNC 0
#else
#error "Invalid SSP0 SSP0_SCK Pin Configuration!"
#endif
// <o> SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2
// <i> Master In Slave Out for SSP0
#define RTE_SSP0_MISO_PIN_SEL 0
#if (RTE_SSP0_MISO_PIN_SEL == 0)
#define RTE_SSP0_MISO_PIN_EN 0
#elif (RTE_SSP0_MISO_PIN_SEL == 1)
#define RTE_SSP0_MISO_PORT 1
#define RTE_SSP0_MISO_BIT 1
#define RTE_SSP0_MISO_FUNC 5
#elif (RTE_SSP0_MISO_PIN_SEL == 2)
#define RTE_SSP0_MISO_PORT 3
#define RTE_SSP0_MISO_BIT 6
#define RTE_SSP0_MISO_FUNC 5
#elif (RTE_SSP0_MISO_PIN_SEL == 3)
#define RTE_SSP0_MISO_PORT 3
#define RTE_SSP0_MISO_BIT 7
#define RTE_SSP0_MISO_FUNC 2
#elif (RTE_SSP0_MISO_PIN_SEL == 4)
#define RTE_SSP0_MISO_PORT 9
#define RTE_SSP0_MISO_BIT 1
#define RTE_SSP0_MISO_FUNC 7
#elif (RTE_SSP0_MISO_PIN_SEL == 5)
#define RTE_SSP0_MISO_PORT 0xF
#define RTE_SSP0_MISO_BIT 2
#define RTE_SSP0_MISO_FUNC 2
#else
#error "Invalid SSP0 SSP0_MISO Pin Configuration!"
#endif
#ifndef RTE_SSP0_MISO_PIN_EN
#define RTE_SSP0_MISO_PIN_EN 1
#endif
// <o> SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3
// <i> Master Out Slave In for SSP0
#define RTE_SSP0_MOSI_PIN_SEL 0
#if (RTE_SSP0_MOSI_PIN_SEL == 0)
#define RTE_SSP0_MOSI_PIN_EN 0
#elif (RTE_SSP0_MOSI_PIN_SEL == 1)
#define RTE_SSP0_MOSI_PORT 1
#define RTE_SSP0_MOSI_BIT 2
#define RTE_SSP0_MOSI_FUNC 5
#elif (RTE_SSP0_MOSI_PIN_SEL == 2)
#define RTE_SSP0_MOSI_PORT 3
#define RTE_SSP0_MOSI_BIT 7
#define RTE_SSP0_MOSI_FUNC 5
#elif (RTE_SSP0_MOSI_PIN_SEL == 3)
#define RTE_SSP0_MOSI_PORT 3
#define RTE_SSP0_MOSI_BIT 8
#define RTE_SSP0_MOSI_FUNC 2
#elif (RTE_SSP0_MOSI_PIN_SEL == 4)
#define RTE_SSP0_MOSI_PORT 9
#define RTE_SSP0_MOSI_BIT 2
#define RTE_SSP0_MOSI_FUNC 7
#elif (RTE_SSP0_MOSI_PIN_SEL == 5)
#define RTE_SSP0_MOSI_PORT 0xF
#define RTE_SSP0_MOSI_BIT 3
#define RTE_SSP0_MOSI_FUNC 2
#else
#error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
#endif
#ifndef RTE_SSP0_MOSI_PIN_EN
#define RTE_SSP0_MOSI_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>10 (DMAMUXPER10)
// </e>
#define RTE_SSP0_DMA_TX_EN 0
#define RTE_SSP0_DMA_TX_CH 0
#define RTE_SSP0_DMA_TX_PERI_ID 0
#if (RTE_SSP0_DMA_TX_PERI_ID == 0)
#define RTE_SSP0_DMA_TX_PERI 10
#define RTE_SSP0_DMA_TX_PERI_SEL 0
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>9 (DMAMUXPER9)
// </e>
#define RTE_SSP0_DMA_RX_EN 0
#define RTE_SSP0_DMA_RX_CH 1
#define RTE_SSP0_DMA_RX_PERI_ID 0
#if (RTE_SSP0_DMA_RX_PERI_ID == 0)
#define RTE_SSP0_DMA_RX_PERI 9
#define RTE_SSP0_DMA_RX_PERI_SEL 0
#endif
// </h> DMA
// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
#define RTE_SSP1 0
// <h> Pin Configuration
// <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
// <i> Slave Select for SSP1
#define RTE_SSP1_SSEL_PIN_SEL 1
#if (RTE_SSP1_SSEL_PIN_SEL == 0)
#define RTE_SSP1_SSEL_PIN_EN 0
#elif (RTE_SSP1_SSEL_PIN_SEL == 1)
#define RTE_SSP1_SSEL_PORT 1
#define RTE_SSP1_SSEL_BIT 5
#define RTE_SSP1_SSEL_FUNC 5
#define RTE_SSP1_SSEL_GPIO_FUNC 0
#define RTE_SSP1_SSEL_GPIO_PORT 1
#define RTE_SSP1_SSEL_GPIO_BIT 8
#elif (RTE_SSP1_SSEL_PIN_SEL == 2)
#define RTE_SSP1_SSEL_PORT 1
#define RTE_SSP1_SSEL_BIT 20
#define RTE_SSP1_SSEL_FUNC 1
#define RTE_SSP1_SSEL_GPIO_FUNC 0
#define RTE_SSP1_SSEL_GPIO_PORT 0
#define RTE_SSP1_SSEL_GPIO_BIT 15
#elif (RTE_SSP1_SSEL_PIN_SEL == 3)
#define RTE_SSP1_SSEL_PORT 0xF
#define RTE_SSP1_SSEL_BIT 5
#define RTE_SSP1_SSEL_FUNC 2
#define RTE_SSP1_SSEL_GPIO_FUNC 4
#define RTE_SSP1_SSEL_GPIO_PORT 7
#define RTE_SSP1_SSEL_GPIO_BIT 19
#else
#error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
#endif
#ifndef RTE_SSP1_SSEL_PIN_EN
#define RTE_SSP1_SSEL_PIN_EN 1
#endif
// <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
// <i> Serial clock for SSP1
#define RTE_SSP1_SCK_PIN_SEL 0
#if (RTE_SSP1_SCK_PIN_SEL == 0)
#define RTE_SSP1_SCK_PORT 1
#define RTE_SSP1_SCK_BIT 19
#define RTE_SSP1_SCK_FUNC 1
#elif (RTE_SSP1_SCK_PIN_SEL == 1)
#define RTE_SSP1_SCK_PORT 0xF
#define RTE_SSP1_SCK_BIT 4
#define RTE_SSP1_SCK_FUNC 0
#elif (RTE_SSP1_SCK_PIN_SEL == 2)
#define RTE_SSP1_SCK_PORT 0x10
#define RTE_SSP1_SCK_BIT 0
#define RTE_SSP1_SCK_FUNC 6
#else
#error "Invalid SSP1 SSP1_SCK Pin Configuration!"
#endif
// <o> SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6
// <i> Master In Slave Out for SSP1
#define RTE_SSP1_MISO_PIN_SEL 0
#if (RTE_SSP1_MISO_PIN_SEL == 0)
#define RTE_SSP1_MISO_PIN_EN 0
#elif (RTE_SSP1_MISO_PIN_SEL == 1)
#define RTE_SSP1_MISO_PORT 0
#define RTE_SSP1_MISO_BIT 0
#define RTE_SSP1_MISO_FUNC 1
#elif (RTE_SSP1_MISO_PIN_SEL == 2)
#define RTE_SSP1_MISO_PORT 1
#define RTE_SSP1_MISO_BIT 3
#define RTE_SSP1_MISO_FUNC 5
#elif (RTE_SSP1_MISO_PIN_SEL == 3)
#define RTE_SSP1_MISO_PORT 0xF
#define RTE_SSP1_MISO_BIT 6
#define RTE_SSP1_MISO_FUNC 2
#else
#error "Invalid SSP1 SSP1_MISO Pin Configuration!"
#endif
#ifndef RTE_SSP1_MISO_PIN_EN
#define RTE_SSP1_MISO_PIN_EN 1
#endif
// <o> SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7
// <i> Master Out Slave In for SSP1
#define RTE_SSP1_MOSI_PIN_SEL 0
#if (RTE_SSP1_MOSI_PIN_SEL == 0)
#define RTE_SSP1_MOSI_PIN_EN 0
#elif (RTE_SSP1_MOSI_PIN_SEL == 1)
#define RTE_SSP1_MOSI_PORT 0
#define RTE_SSP1_MOSI_BIT 1
#define RTE_SSP1_MOSI_FUNC 1
#elif (RTE_SSP1_MOSI_PIN_SEL == 2)
#define RTE_SSP1_MOSI_PORT 1
#define RTE_SSP1_MOSI_BIT 4
#define RTE_SSP1_MOSI_FUNC 5
#elif (RTE_SSP1_MOSI_PIN_SEL == 3)
#define RTE_SSP1_MOSI_PORT 0xF
#define RTE_SSP1_MOSI_BIT 7
#define RTE_SSP1_MOSI_FUNC 2
#else
#error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
#endif
#ifndef RTE_SSP1_MOSI_PIN_EN
#define RTE_SSP1_MOSI_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
// </e>
#define RTE_SSP1_DMA_TX_EN 0
#define RTE_SSP1_DMA_TX_CH 0
#define RTE_SSP1_DMA_TX_PERI_ID 0
#if (RTE_SSP1_DMA_TX_PERI_ID == 0)
#define RTE_SSP1_DMA_TX_PERI 3
#define RTE_SSP1_DMA_TX_PERI_SEL 3
#elif (RTE_SSP1_DMA_TX_PERI_ID == 1)
#define RTE_SSP1_DMA_TX_PERI 5
#define RTE_SSP1_DMA_TX_PERI_SEL 2
#elif (RTE_SSP1_DMA_TX_PERI_ID == 2)
#define RTE_SSP1_DMA_TX_PERI 12
#define RTE_SSP1_DMA_TX_PERI_SEL 0
#elif (RTE_SSP1_DMA_TX_PERI_ID == 3)
#define RTE_SSP1_DMA_TX_PERI 14
#define RTE_SSP1_DMA_TX_PERI_SEL 2
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
// </e>
#define RTE_SSP1_DMA_RX_EN 0
#define RTE_SSP1_DMA_RX_CH 1
#define RTE_SSP1_DMA_RX_PERI_ID 0
#if (RTE_SSP1_DMA_RX_PERI_ID == 0)
#define RTE_SSP1_DMA_RX_PERI 4
#define RTE_SSP1_DMA_RX_PERI_SEL 3
#elif (RTE_SSP1_DMA_RX_PERI_ID == 1)
#define RTE_SSP1_DMA_RX_PERI 6
#define RTE_SSP1_DMA_RX_PERI_SEL 2
#elif (RTE_SSP1_DMA_RX_PERI_ID == 2)
#define RTE_SSP1_DMA_RX_PERI 11
#define RTE_SSP1_DMA_RX_PERI_SEL 0
#elif (RTE_SSP1_DMA_RX_PERI_ID == 3)
#define RTE_SSP1_DMA_RX_PERI 13
#define RTE_SSP1_DMA_RX_PERI_SEL 2
#endif
// </h> DMA
// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
// <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
#define RTE_SPI 0
// <h> Pin Configuration
// <o> SPI_SSEL <0=>Not used <1=>P3_8
// <i> Slave Select for SPI
#define RTE_SPI_SSEL_PIN_SEL 0
#if (RTE_SPI_SSEL_PIN_SEL == 0)
#define RTE_SPI_SSEL_PIN_EN 0
#elif (RTE_SPI_SSEL_PIN_SEL == 1)
#define RTE_SPI_SSEL_PORT 3
#define RTE_SPI_SSEL_BIT 8
#define RTE_SPI_SSEL_FUNC 1
#define RTE_SPI_SSEL_GPIO_FUNC 4
#define RTE_SPI_SSEL_GPIO_PORT 5
#define RTE_SPI_SSEL_GPIO_BIT 11
#else
#error "Invalid SPI SPI_SSEL Pin Configuration!"
#endif
#ifndef RTE_SPI_SSEL_PIN_EN
#define RTE_SPI_SSEL_PIN_EN 1
#endif
// <o> SPI_SCK <0=>P3_3
// <i> Serial clock for SPI
#define RTE_SPI_SCK_PIN_SEL 0
#if (RTE_SPI_SCK_PIN_SEL == 0)
#define RTE_SPI_SCK_PORT 3
#define RTE_SPI_SCK_BIT 3
#define RTE_SPI_SCK_FUNC 1
#else
#error "Invalid SPI SPI_SCK Pin Configuration!"
#endif
// <o> SPI_MISO <0=>Not used <1=>P3_6
// <i> Master In Slave Out for SPI
#define RTE_SPI_MISO_PIN_SEL 0
#if (RTE_SPI_MISO_PIN_SEL == 0)
#define RTE_SPI_MISO_PIN_EN 0
#elif (RTE_SPI_MISO_PIN_SEL == 1)
#define RTE_SPI_MISO_PORT 3
#define RTE_SPI_MISO_BIT 6
#define RTE_SPI_MISO_FUNC 1
#else
#error "Invalid SPI SPI_MISO Pin Configuration!"
#endif
#ifndef RTE_SPI_MISO_PIN_EN
#define RTE_SPI_MISO_PIN_EN 1
#endif
// <o> SPI_MOSI <0=>Not used <1=>P3_7
// <i> Master Out Slave In for SPI
#define RTE_SPI_MOSI_PIN_SEL 0
#if (RTE_SPI_MOSI_PIN_SEL == 0)
#define RTE_SPI_MOSI_PIN_EN 0
#elif (RTE_SPI_MOSI_PIN_SEL == 1)
#define RTE_SPI_MOSI_PORT 3
#define RTE_SPI_MOSI_BIT 7
#define RTE_SPI_MOSI_FUNC 1
#else
#error "Invalid SPI SPI_MOSI Pin Configuration!"
#endif
#ifndef RTE_SPI_MOSI_PIN_EN
#define RTE_SPI_MOSI_PIN_EN 1
#endif
// </h> Pin Configuration
// </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
#define RTE_I2S0 0
// <h> Pin Configuration
// <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
// <i> Receive clock for I2S0
#define RTE_I2S0_RX_SCK_PIN_SEL 2
#if (RTE_I2S0_RX_SCK_PIN_SEL == 0)
#define RTE_I2S0_RX_SCK_PIN_EN 0
#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1)
#define RTE_I2S0_RX_SCK_PORT 3
#define RTE_I2S0_RX_SCK_BIT 0
#define RTE_I2S0_RX_SCK_FUNC 0
#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2)
#define RTE_I2S0_RX_SCK_PORT 6
#define RTE_I2S0_RX_SCK_BIT 0
#define RTE_I2S0_RX_SCK_FUNC 4
#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3)
#define RTE_I2S0_RX_SCK_PORT 0xF
#define RTE_I2S0_RX_SCK_BIT 4
#define RTE_I2S0_RX_SCK_FUNC 7
#else
#error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
#endif
#ifndef RTE_I2S0_RX_SCK_PIN_EN
#define RTE_I2S0_RX_SCK_PIN_EN 1
#endif
// <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
// <i> Receive word select for I2S0
#define RTE_I2S0_RX_WS_PIN_SEL 2
#if (RTE_I2S0_RX_WS_PIN_SEL == 0)
#define RTE_I2S0_RX_WS_PIN_EN 0
#elif (RTE_I2S0_RX_WS_PIN_SEL == 1)
#define RTE_I2S0_RX_WS_PORT 3
#define RTE_I2S0_RX_WS_BIT 1
#define RTE_I2S0_RX_WS_FUNC 1
#elif (RTE_I2S0_RX_WS_PIN_SEL == 2)
#define RTE_I2S0_RX_WS_PORT 6
#define RTE_I2S0_RX_WS_BIT 1
#define RTE_I2S0_RX_WS_FUNC 3
#else
#error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
#endif
#ifndef RTE_I2S0_RX_WS_PIN_EN
#define RTE_I2S0_RX_WS_PIN_EN 1
#endif
// <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
// <i> Receive master clock for I2S0
#define RTE_I2S0_RX_SDA_PIN_SEL 2
#if (RTE_I2S0_RX_SDA_PIN_SEL == 0)
#define RTE_I2S0_RX_SDA_PIN_EN 0
#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1)
#define RTE_I2S0_RX_SDA_PORT 3
#define RTE_I2S0_RX_SDA_BIT 2
#define RTE_I2S0_RX_SDA_FUNC 1
#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2)
#define RTE_I2S0_RX_SDA_PORT 6
#define RTE_I2S0_RX_SDA_BIT 2
#define RTE_I2S0_RX_SDA_FUNC 3
#else
#error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
#endif
#ifndef RTE_I2S0_RX_SDA_PIN_EN
#define RTE_I2S0_RX_SDA_PIN_EN 1
#endif
// <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
// <i> Receive master clock for I2S0
#define RTE_I2S0_RX_MCLK_PIN_SEL 0
#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
#define RTE_I2S0_RX_MCLK_PIN_EN 0
#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
#define RTE_I2S0_RX_MCLK_PORT 1
#define RTE_I2S0_RX_MCLK_BIT 19
#define RTE_I2S0_RX_MCLK_FUNC 6
#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
#define RTE_I2S0_RX_MCLK_PORT 3
#define RTE_I2S0_RX_MCLK_BIT 0
#define RTE_I2S0_RX_MCLK_FUNC 1
#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
#define RTE_I2S0_RX_MCLK_PORT 6
#define RTE_I2S0_RX_MCLK_BIT 0
#define RTE_I2S0_RX_MCLK_FUNC 1
#else
#error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
#endif
#ifndef RTE_I2S0_RX_MCLK_PIN_EN
#define RTE_I2S0_RX_MCLK_PIN_EN 1
#endif
// <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
// <i> Transmit clock for I2S0
#define RTE_I2S0_TX_SCK_PIN_SEL 1
#if (RTE_I2S0_TX_SCK_PIN_SEL == 0)
#define RTE_I2S0_TX_SCK_PIN_EN 0
#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1)
#define RTE_I2S0_TX_SCK_PORT 3
#define RTE_I2S0_TX_SCK_BIT 0
#define RTE_I2S0_TX_SCK_FUNC 2
#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2)
#define RTE_I2S0_TX_SCK_PORT 4
#define RTE_I2S0_TX_SCK_BIT 7
#define RTE_I2S0_TX_SCK_FUNC 7
#else
#error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
#endif
#ifndef RTE_I2S0_TX_SCK_PIN_EN
#define RTE_I2S0_TX_SCK_PIN_EN 1
#endif
// <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
// <i> Transmit word select for I2S0
#define RTE_I2S0_TX_WS_PIN_SEL 4
#if (RTE_I2S0_TX_WS_PIN_SEL == 0)
#define RTE_I2S0_TX_WS_PIN_EN 0
#elif (RTE_I2S0_TX_WS_PIN_SEL == 1)
#define RTE_I2S0_TX_WS_PORT 0
#define RTE_I2S0_TX_WS_BIT 0
#define RTE_I2S0_TX_WS_FUNC 6
#elif (RTE_I2S0_TX_WS_PIN_SEL == 2)
#define RTE_I2S0_TX_WS_PORT 3
#define RTE_I2S0_TX_WS_BIT 1
#define RTE_I2S0_TX_WS_FUNC 0
#elif (RTE_I2S0_TX_WS_PIN_SEL == 3)
#define RTE_I2S0_TX_WS_PORT 3
#define RTE_I2S0_TX_WS_BIT 4
#define RTE_I2S0_TX_WS_FUNC 5
#elif (RTE_I2S0_TX_WS_PIN_SEL == 4)
#define RTE_I2S0_TX_WS_PORT 7
#define RTE_I2S0_TX_WS_BIT 1
#define RTE_I2S0_TX_WS_FUNC 2
#elif (RTE_I2S0_TX_WS_PIN_SEL == 5)
#define RTE_I2S0_TX_WS_PORT 9
#define RTE_I2S0_TX_WS_BIT 1
#define RTE_I2S0_TX_WS_FUNC 4
#elif (RTE_I2S0_TX_WS_PIN_SEL == 6)
#define RTE_I2S0_TX_WS_PORT 0xC
#define RTE_I2S0_TX_WS_BIT 13
#define RTE_I2S0_TX_WS_FUNC 6
#else
#error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
#endif
#ifndef RTE_I2S0_TX_WS_PIN_EN
#define RTE_I2S0_TX_WS_PIN_EN 1
#endif
// <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12
// <i> Transmit data for I2S0
#define RTE_I2S0_TX_SDA_PIN_SEL 3
#if (RTE_I2S0_TX_SDA_PIN_SEL == 0)
#define RTE_I2S0_TX_SDA_PIN_EN 0
#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1)
#define RTE_I2S0_TX_SDA_PORT 3
#define RTE_I2S0_TX_SDA_BIT 2
#define RTE_I2S0_TX_SDA_FUNC 0
#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2)
#define RTE_I2S0_TX_SDA_PORT 3
#define RTE_I2S0_TX_SDA_BIT 5
#define RTE_I2S0_TX_SDA_FUNC 5
#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3)
#define RTE_I2S0_TX_SDA_PORT 7
#define RTE_I2S0_TX_SDA_BIT 2
#define RTE_I2S0_TX_SDA_FUNC 2
#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4)
#define RTE_I2S0_TX_SDA_PORT 9
#define RTE_I2S0_TX_SDA_BIT 2
#define RTE_I2S0_TX_SDA_FUNC 4
#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5)
#define RTE_I2S0_TX_SDA_PORT 0xC
#define RTE_I2S0_TX_SDA_BIT 12
#define RTE_I2S0_TX_SDA_FUNC 6
#else
#error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
#endif
#ifndef RTE_I2S0_TX_SDA_PIN_EN
#define RTE_I2S0_TX_SDA_PIN_EN 1
#endif
// <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
// <i> Transmit master clock for I2S0
#define RTE_I2S0_TX_MCLK_PIN_SEL 2
#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
#define RTE_I2S0_TX_MCLK_PIN_EN 0
#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
#define RTE_I2S0_TX_MCLK_PORT 3
#define RTE_I2S0_TX_MCLK_BIT 0
#define RTE_I2S0_TX_MCLK_FUNC 3
#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
#define RTE_I2S0_TX_MCLK_PORT 3
#define RTE_I2S0_TX_MCLK_BIT 3
#define RTE_I2S0_TX_MCLK_FUNC 6
#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
#define RTE_I2S0_TX_MCLK_PORT 0xf
#define RTE_I2S0_TX_MCLK_BIT 4
#define RTE_I2S0_TX_MCLK_FUNC 6
#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
#define RTE_I2S0_TX_MCLK_PORT 0x10
#define RTE_I2S0_TX_MCLK_BIT 2
#define RTE_I2S0_TX_MCLK_FUNC 6
#else
#error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
#endif
#ifndef RTE_I2S0_TX_MCLK_PIN_EN
#define RTE_I2S0_TX_MCLK_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>9 (DMAMUXPER9)
// </e>
#define RTE_I2S0_DMA_TX_EN 0
#define RTE_I2S0_DMA_TX_CH 0
#define RTE_I2S0_DMA_TX_PERI_ID 0
#if (RTE_I2S0_DMA_TX_PERI_ID == 0)
#define RTE_I2S0_DMA_TX_PERI 9
#define RTE_I2S0_DMA_TX_PERI_SEL 1
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>10 (DMAMUXPER10)
// </e>
#define RTE_I2S0_DMA_RX_EN 0
#define RTE_I2S0_DMA_RX_CH 1
#define RTE_I2S0_DMA_RX_PERI_ID 0
#if (RTE_I2S0_DMA_RX_PERI_ID == 0)
#define RTE_I2S0_DMA_RX_PERI 10
#define RTE_I2S0_DMA_RX_PERI_SEL 1
#endif
// </h> DMA
// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
#define RTE_I2S1 0
// <h> Pin Configuration
// <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
// <i> Receive clock for I2S1
#define RTE_I2S1_RX_SCK_PIN_SEL 0
#if (RTE_I2S1_RX_SCK_PIN_SEL == 0)
#define RTE_I2S1_RX_SCK_PIN_EN 0
#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1)
#define RTE_I2S1_RX_SCK_PORT 0x10
#define RTE_I2S1_RX_SCK_BIT 2
#define RTE_I2S1_RX_SCK_FUNC 7
#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2)
#define RTE_I2S1_RX_SCK_PORT 0x10
#define RTE_I2S1_RX_SCK_BIT 3
#define RTE_I2S1_RX_SCK_FUNC 7
#else
#error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
#endif
#ifndef RTE_I2S1_RX_SCK_PIN_EN
#define RTE_I2S1_RX_SCK_PIN_EN 1
#endif
// <o> I2S1_RX_WS <0=>Not used <1=>P3_5
// <i> Receive word select for I2S1
#define RTE_I2S1_RX_WS_PIN_SEL 0
#if (RTE_I2S1_RX_WS_PIN_SEL == 0)
#define RTE_I2S1_RX_WS_PIN_EN 0
#elif (RTE_I2S1_RX_WS_PIN_SEL == 1)
#define RTE_I2S1_RX_WS_PORT 3
#define RTE_I2S1_RX_WS_BIT 5
#define RTE_I2S1_RX_WS_FUNC 6
#else
#error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
#endif
#ifndef RTE_I2S1_RX_WS_PIN_EN
#define RTE_I2S1_RX_WS_PIN_EN 1
#endif
// <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
// <i> Receive master clock for I2S1
#define RTE_I2S1_RX_SDA_PIN_SEL 0
#if (RTE_I2S1_RX_SDA_PIN_SEL == 0)
#define RTE_I2S1_RX_SDA_PIN_EN 0
#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1)
#define RTE_I2S1_RX_SDA_PORT 3
#define RTE_I2S1_RX_SDA_BIT 4
#define RTE_I2S1_RX_SDA_FUNC 6
#else
#error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
#endif
#ifndef RTE_I2S1_RX_SDA_PIN_EN
#define RTE_I2S1_RX_SDA_PIN_EN 1
#endif
// <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
// <i> Receive master clock for I2S1
#define RTE_I2S1_RX_MCLK_PIN_SEL 0
#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
#define RTE_I2S1_RX_MCLK_PIN_EN 0
#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
#define RTE_I2S1_RX_MCLK_PORT 0x0A
#define RTE_I2S1_RX_MCLK_BIT 0
#define RTE_I2S1_RX_MCLK_FUNC 5
#else
#error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
#endif
#ifndef RTE_I2S1_RX_MCLK_PIN_EN
#define RTE_I2S1_RX_MCLK_PIN_EN 1
#endif
// <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
// <i> Transmit clock for I2S1
#define RTE_I2S1_TX_SCK_PIN_SEL 0
#if (RTE_I2S1_TX_SCK_PIN_SEL == 0)
#define RTE_I2S1_TX_SCK_PIN_EN 0
#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1)
#define RTE_I2S1_TX_SCK_PORT 1
#define RTE_I2S1_TX_SCK_BIT 19
#define RTE_I2S1_TX_SCK_FUNC 7
#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2)
#define RTE_I2S1_TX_SCK_PORT 3
#define RTE_I2S1_TX_SCK_BIT 3
#define RTE_I2S1_TX_SCK_FUNC 7
#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3)
#define RTE_I2S1_TX_SCK_PORT 4
#define RTE_I2S1_TX_SCK_BIT 7
#define RTE_I2S1_TX_SCK_FUNC 6
#else
#error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
#endif
#ifndef RTE_I2S1_TX_SCK_PIN_EN
#define RTE_I2S1_TX_SCK_PIN_EN 1
#endif
// <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
// <i> Transmit word select for I2S1
#define RTE_I2S1_TX_WS_PIN_SEL 0
#if (RTE_I2S1_TX_WS_PIN_SEL == 0)
#define RTE_I2S1_TX_WS_PIN_EN 0
#elif (RTE_I2S1_TX_WS_PIN_SEL == 1)
#define RTE_I2S1_TX_WS_PORT 0
#define RTE_I2S1_TX_WS_BIT 0
#define RTE_I2S1_TX_WS_FUNC 7
#elif (RTE_I2S1_TX_WS_PIN_SEL == 2)
#define RTE_I2S1_TX_WS_PORT 0x0F
#define RTE_I2S1_TX_WS_BIT 7
#define RTE_I2S1_TX_WS_FUNC 7
#else
#error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
#endif
#ifndef RTE_I2S1_TX_WS_PIN_EN
#define RTE_I2S1_TX_WS_PIN_EN 1
#endif
// <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
// <i> Transmit data for I2S
#define RTE_I2S1_TX_SDA_PIN_SEL 0
#if (RTE_I2S1_TX_SDA_PIN_SEL == 0)
#define RTE_I2S1_TX_SDA_PIN_EN 0
#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1)
#define RTE_I2S1_TX_SDA_PORT 0
#define RTE_I2S1_TX_SDA_BIT 1
#define RTE_I2S1_TX_SDA_FUNC 7
#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2)
#define RTE_I2S1_TX_SDA_PORT 0x0F
#define RTE_I2S1_TX_SDA_BIT 6
#define RTE_I2S1_TX_SDA_FUNC 7
#else
#error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
#endif
#ifndef RTE_I2S1_TX_SDA_PIN_EN
#define RTE_I2S1_TX_SDA_PIN_EN 1
#endif
// <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
// <i> Transmit master clock for I2S1
#define RTE_I2S1_TX_MCLK_PIN_SEL 0
#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
#define RTE_I2S1_TX_MCLK_PIN_EN 0
#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
#define RTE_I2S1_TX_MCLK_PORT 8
#define RTE_I2S1_TX_MCLK_BIT 8
#define RTE_I2S1_TX_MCLK_FUNC 7
#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
#define RTE_I2S1_TX_MCLK_PORT 0x0F
#define RTE_I2S1_TX_MCLK_BIT 0
#define RTE_I2S1_TX_MCLK_FUNC 7
#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
#define RTE_I2S1_TX_MCLK_PORT 0x10
#define RTE_I2S1_TX_MCLK_BIT 1
#define RTE_I2S1_TX_MCLK_FUNC 7
#else
#error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
#endif
#ifndef RTE_I2S1_TX_MCLK_PIN_EN
#define RTE_I2S1_TX_MCLK_PIN_EN 1
#endif
// </h> Pin Configuration
// <h> DMA
// <e> Tx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>3 (DMAMUXPER3)
// </e>
#define RTE_I2S1_DMA_TX_EN 0
#define RTE_I2S1_DMA_TX_CH 0
#define RTE_I2S1_DMA_TX_PERI_ID 0
#if (RTE_I2S1_DMA_TX_PERI_ID == 0)
#define RTE_I2S1_DMA_TX_PERI 3
#define RTE_I2S1_DMA_TX_PERI_SEL 2
#endif
// <e> Rx
// <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <o2> Peripheral <0=>4 (DMAMUXPER4)
// </e>
#define RTE_I2S1_DMA_RX_EN 0
#define RTE_I2S1_DMA_RX_CH 1
#define RTE_I2S1_DMA_RX_PERI_ID 0
#if (RTE_I2S1_DMA_RX_PERI_ID == 0)
#define RTE_I2S1_DMA_RX_PERI 4
#define RTE_I2S1_DMA_RX_PERI_SEL 2
#endif
// </h> DMA
// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
// <e> CAN0 Controller [Driver_CAN0]
// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
#define RTE_CAN_CAN0 0
// <h> Pin Configuration
// <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
// <i> CAN0 receiver input.
#define RTE_CAN0_RD_ID 0
#if (RTE_CAN0_RD_ID == 0)
#define RTE_CAN0_RD_PIN_EN 0
#elif (RTE_CAN0_RD_ID == 1)
#define RTE_CAN0_RD_PORT 3
#define RTE_CAN0_RD_BIT 1
#define RTE_CAN0_RD_FUNC 2
#elif (RTE_CAN0_RD_ID == 2)
#define RTE_CAN0_RD_PORT 0xE
#define RTE_CAN0_RD_BIT 2
#define RTE_CAN0_RD_FUNC 1
#else
#error "Invalid RTE_CAN0_RD Pin Configuration!"
#endif
#ifndef RTE_CAN0_RD_PIN_EN
#define RTE_CAN0_RD_PIN_EN 1
#endif
// <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
// <i> CAN0 transmitter output.
#define RTE_CAN0_TD_ID 0
#if (RTE_CAN0_TD_ID == 0)
#define RTE_CAN0_TD_PIN_EN 0
#elif (RTE_CAN0_TD_ID == 1)
#define RTE_CAN0_TD_PORT 3
#define RTE_CAN0_TD_BIT 2
#define RTE_CAN0_TD_FUNC 2
#elif (RTE_CAN0_TD_ID == 2)
#define RTE_CAN0_TD_PORT 0xE
#define RTE_CAN0_TD_BIT 3
#define RTE_CAN0_TD_FUNC 1
#else
#error "Invalid RTE_CAN0_TD Pin Configuration!"
#endif
#ifndef RTE_CAN0_TD_PIN_EN
#define RTE_CAN0_TD_PIN_EN 1
#endif
// </h> Pin Configuration
// </e> CAN0 Controller [Driver_CAN0]
// <e> CAN1 Controller [Driver_CAN1]
// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
#define RTE_CAN_CAN1 0
// <h> Pin Configuration
// <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
// <i> CAN1 receiver input.
#define RTE_CAN1_RD_ID 0
#if (RTE_CAN1_RD_ID == 0)
#define RTE_CAN1_RD_PIN_EN 0
#elif (RTE_CAN1_RD_ID == 1)
#define RTE_CAN1_RD_PORT 1
#define RTE_CAN1_RD_BIT 18
#define RTE_CAN1_RD_FUNC 5
#elif (RTE_CAN1_RD_ID == 2)
#define RTE_CAN1_RD_PORT 4
#define RTE_CAN1_RD_BIT 9
#define RTE_CAN1_RD_FUNC 6
#elif (RTE_CAN1_RD_ID == 3)
#define RTE_CAN1_RD_PORT 0xE
#define RTE_CAN1_RD_BIT 1
#define RTE_CAN1_RD_FUNC 5
#else
#error "Invalid RTE_CAN1_RD Pin Configuration!"
#endif
#ifndef RTE_CAN1_RD_PIN_EN
#define RTE_CAN1_RD_PIN_EN 1
#endif
// <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
// <i> CAN1 transmitter output.
#define RTE_CAN1_TD_ID 0
#if (RTE_CAN1_TD_ID == 0)
#define RTE_CAN1_TD_PIN_EN 0
#elif (RTE_CAN1_TD_ID == 1)
#define RTE_CAN1_TD_PORT 1
#define RTE_CAN1_TD_BIT 17
#define RTE_CAN1_TD_FUNC 5
#elif (RTE_CAN1_TD_ID == 2)
#define RTE_CAN1_TD_PORT 4
#define RTE_CAN1_TD_BIT 8
#define RTE_CAN1_TD_FUNC 6
#elif (RTE_CAN1_TD_ID == 3)
#define RTE_CAN1_TD_PORT 0xE
#define RTE_CAN1_TD_BIT 0
#define RTE_CAN1_TD_FUNC 5
#else
#error "Invalid RTE_CAN1_TD Pin Configuration!"
#endif
#ifndef RTE_CAN1_TD_PIN_EN
#define RTE_CAN1_TD_PIN_EN 1
#endif
// </h> Pin Configuration
// </e> CAN1 Controller [Driver_CAN1]
#endif /* __RTE_DEVICE_H */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 32,293 |
```gas
;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; * <<< Use Configuration Wizard in Context Menu >>>
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,061 |
```c
/* your_sha256_hash-------------
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
* $Date: 10. September 2018
* $Revision: V1.0.3
*
* Project: NXP LPC43xx System initialization
* your_sha256_hash---------- */
#include "LPC43xx.h"
/*your_sha256_hash------------
This file configures the clocks as follows:
your_sha256_hash-------------
Clock Unit | Output clock | Source clock | Note
your_sha256_hash-------------
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
your_sha256_hash-------------
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
your_sha256_hash-------------
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
your_sha256_hash-------------
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
your_sha256_hash-------------
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
your_sha256_hash-------------
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
your_sha256_hash-------------
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
your_sha256_hash-------------
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
your_sha256_hash-------------*/
/*your_sha256_hash------------
Clock source selection definitions (do not change)
*your_sha256_hash------------*/
#define CLK_SRC_32KHZ 0x00
#define CLK_SRC_IRC 0x01
#define CLK_SRC_ENET_RX 0x02
#define CLK_SRC_ENET_TX 0x03
#define CLK_SRC_GP_CLKIN 0x04
#define CLK_SRC_XTAL 0x06
#define CLK_SRC_PLL0U 0x07
#define CLK_SRC_PLL0A 0x08
#define CLK_SRC_PLL1 0x09
#define CLK_SRC_IDIVA 0x0C
#define CLK_SRC_IDIVB 0x0D
#define CLK_SRC_IDIVC 0x0E
#define CLK_SRC_IDIVD 0x0F
#define CLK_SRC_IDIVE 0x10
/*your_sha256_hash------------
Define external input frequency values
*your_sha256_hash------------*/
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
/*your_sha256_hash------------
Define clock sources
*your_sha256_hash------------*/
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
/*your_sha256_hash------------
Configure integer divider values
*your_sha256_hash------------*/
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
/*your_sha256_hash------------
Define CPU clock input
*your_sha256_hash------------*/
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
/*your_sha256_hash------------
Configure external memory controller options
*your_sha256_hash------------*/
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
/*your_sha256_hash------------
* Configure PLL1
*your_sha256_hash------------
* Integer mode:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT * 2 * P
*
* Non-integer:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
* FCCO = FCLKOUT * 2 * P
*
* Direct mode:
* - PLL1_DIRECT = 1 (Post divider disabled)
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT
*
*your_sha256_hash------------
* PLL1 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 1MHz | 50MHz | |
* | FCCO | 156MHz | 320MHz | |
* | FCLKOUT | 9.75MHz | 320MHz | |
*your_sha256_hash------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
*your_sha256_hash------------
* Relations beetwen PLL dividers and definitions:
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
*your_sha256_hash------------*/
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
/* 1: FCLKOUT is used as PLL feedback */
/*your_sha256_hash------------
* Configure Flash Accelerator
*your_sha256_hash------------
* Flash acces time:
* | CPU clock | FLASHTIM |
* | up to 21MHz | 0 |
* | up to 43MHz | 1 |
* | up to 64MHz | 2 |
* | up to 86MHz | 3 |
* | up to 107MHz | 4 |
* | up to 129MHz | 5 |
* | up to 150MHz | 6 |
* | up to 172MHz | 7 |
* | up to 193MHz | 8 |
* | up to 204MHz | 9 |
*your_sha256_hash------------*/
#define FLASHCFG_FLASHTIM 9
/*your_sha256_hash------------
* Configure PLL0USB
*your_sha256_hash------------
*
* Normal operating mode without post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M
* FCCO = FOUT
*
* Normal operating mode with post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * (M / P)
* FCCO = FOUT * 2 * P
*
* Normal operating mode without post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M / N
* FCCO = FOUT
*
* Normal operating mode with post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * M / (P * N)
* FCCO = FOUT * 2 * P
*your_sha256_hash------------
* PLL0 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 14kHz | 150MHz | |
* | FCCO | 275MHz | 550MHz | |
* | FCLKOUT | 4.3MHz | 550MHz | |
*your_sha256_hash------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
*your_sha256_hash------------*/
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
/*your_sha256_hash------------
End of configuration
*your_sha256_hash------------*/
/* PLL0 Setting Check */
#if (PLL0USB_BYPASS == 0)
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
#define PLL0USB_CLKIN CLK_XTAL
#else
#define PLL0USB_CLKIN CLK_IRC
#endif
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#else /* Mode 1d */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#endif
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
#endif
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
#endif
#endif
/* PLL1 Setting Check */
#if (PLL1_BYPASS == 0)
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
#define PLL1_CLKIN CLK_XTAL
#else
#define PLL1_CLKIN CLK_IRC
#endif
#if (PLL1_DIRECT == 1) /* Direct Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#elif (PLL1_FBSEL == 1) /* Integer Mode */
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#else /* Noninteger Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
#endif
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
#endif
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
#endif
#endif
/*your_sha256_hash------------
System Core Clock variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
/******************************************************************************
* SetClock
******************************************************************************/
void SetClock (void) {
uint32_t x, i;
uint32_t selp, seli;
/* Set flash accelerator configuration for bank A and B to reset value */
LPC_CREG->FLASHCFGA |= (0xF << 12);
LPC_CREG->FLASHCFGB |= (0xF << 12);
/* Set flash wait states to maximum */
LPC_EMC->STATICWAITRD0 = 0x1F;
/* Switch BASE_M4_CLOCK to IRC */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Set clock source */
/* Configure input to crystal oscilator */
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
(0 << 1) | /* Operation with crystal connected */
(0 << 2) ; /* Low-frequency mode */
/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
#if (USE_SPIFI)
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Clock source */
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IDIVA << 24) ; /* Clock source */
#endif
/*your_sha256_hash------------
PLL1 Setup
*your_sha256_hash------------*/
/* Power down PLL */
LPC_CGU->PLL1_CTRL |= 1;
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
/* To run at full speed, CPU must first run at an intermediate speed */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(0 << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(0 << 11)| /* Autoblock Disabled */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* CPU base clock is in the mid frequency range before final clock set */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(PLL1_DIRECT << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(1 << 11)| /* Autoblock En */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* Set CPU base clock source */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CPU_CLK_SEL << 24) ; /* Set clock source */
/* Set flash accelerator configuration for internal flash bank A and B */
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
/*your_sha256_hash------------
PLL0USB Setup
*your_sha256_hash------------*/
/* Power down PLL0USB */
LPC_CGU->PLL0USB_CTRL |= 1;
/* M divider */
x = 0x00004000;
switch (PLL0USB_M) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00018003;
break;
case 2: x = 0x00010003;
break;
default:
for (i = PLL0USB_M; i <= 0x8000; i++) {
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
}
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
else selp = 31;
if (PLL0USB_M > 16384) seli = 1;
else if (PLL0USB_M > 8192) seli = 2;
else if (PLL0USB_M > 2048) seli = 4;
else if (PLL0USB_M >= 501) seli = 8;
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
else seli = (PLL0USB_M & 0x3C) + 4;
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
(seli << 22) |
(x << 0);
/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
/* P divider */
x = 0x10;
switch (PLL0USB_P) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000062;
break;
case 2: x = 0x00000042;
break;
default:
for (i = PLL0USB_P; i <= 0x200; i++) {
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
}
}
LPC_CGU->PLL0USB_NP_DIV |= x;
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
(1 << 11) | /* Autoblock En */
(1 << 4 ) | /* PLL0USB clock en */
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
(0 << 0 ) ; /* PLL0USB Enabled */
while (!(LPC_CGU->PLL0USB_STAT & 1));
/*your_sha256_hash------------
Integer divider Setup
*your_sha256_hash------------*/
/* Configure integer dividers */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVA_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVA_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVB_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVB_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVC_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVC_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVD_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVD_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVE_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVE_CLK_SEL << 24) ; /* Clock source */
}
/*your_sha256_hash------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*your_sha256_hash------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}
/*your_sha256_hash------------
External Memory Controller Definitions
*your_sha256_hash------------*/
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
/* Write Mode register macro */
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
const uint16_t emcdivby2_opc[] = {
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
0xD0FC, /* BEQ loop ; Jump if 0 */
0x4770, /* BX LR ; Exit */
0,
};
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
#define emcdivby2_ram 0x10000000
/*your_sha256_hash------------
Initialize external memory controller
*your_sha256_hash------------*/
void SystemInit_ExtMemCtl (void) {
uint32_t emcdivby2_buf[emcdivby2_szw];
uint32_t div, n;
/* Select and enable EMC branch clock */
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
/* Set EMC clock output delay */
if (SystemCoreClock < 80000000UL) {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
}
else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
}
/* Configure EMC port pins */
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
div = 0;
if (SystemCoreClock > 120000000UL) {
/* Use EMC clock divider and EMC clock output delay */
div = 1;
/* Following code must be executed in RAM to ensure stable operation */
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
/* This code configures EMC clock divider and is executed in RAM */
for (n = 0; n < emcdivby2_szw; n++) {
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
}
__ISB();
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
for (n = 0; n < emcdivby2_szw; n++) {
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
}
}
/* Configure EMC clock-out pins */
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
/* Static memory configuration (chip select 0) */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
(2 << 0) | /* Memory width 32-bit */
(1 << 3); /* Async page mode enable */
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
LPC_EMC->STATICWAITPAGE0 = 2;
/* Set Static Memory Read Delay for 90ns External NOR Flash */
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif
/* Dynamic memory configuration (chip select 0) */
#if (USE_EXT_DYN_MEM_CS0)
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
(0 << 12) | /* AM[12] = 0 */
(2 << 9) | /* AM[11:9] = 2 */
(2 << 7) ; /* AM[8:7] = 2 */
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
WaitUs (100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
WaitUs (1);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (1);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
#endif
}
/*your_sha256_hash------------
Measure frequency using frequency monitor
*your_sha256_hash------------*/
uint32_t MeasureFreq (uint32_t clk_sel) {
uint32_t fcnt, rcnt, fout;
/* Set register values */
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
while (LPC_CGU->FREQ_MON & (1 << 23)) {
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
if (fcnt == 0 && rcnt == 0) {
return (0); /* No input clock present */
}
}
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
return (fout);
}
/*your_sha256_hash------------
Get PLL1 (divider and multiplier) parameters
*your_sha256_hash------------*/
static __inline uint32_t GetPLL1Param (void) {
uint32_t ctrl;
uint32_t p;
uint32_t div, mul;
ctrl = LPC_CGU->PLL1_CTRL;
div = ((ctrl >> 12) & 0x03) + 1;
mul = ((ctrl >> 16) & 0xFF) + 1;
p = 1 << ((ctrl >> 8) & 0x03);
if (ctrl & (1 << 1)) {
/* Bypass = 1, PLL1 input clock sent to post-dividers */
if (ctrl & (1 << 7)) {
div *= (2*p);
}
}
else {
/* Direct and integer mode */
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
/* Non-integer mode */
div *= (2*p);
}
}
return ((div << 8) | (mul));
}
/*your_sha256_hash------------
Get input clock source for specified clock generation block
*your_sha256_hash------------*/
int32_t GetClkSel (uint32_t clk_src) {
uint32_t reg;
int32_t clk_sel = -1;
switch (clk_src) {
case CLK_SRC_IRC:
case CLK_SRC_ENET_RX:
case CLK_SRC_ENET_TX:
case CLK_SRC_GP_CLKIN:
return (clk_src);
case CLK_SRC_32KHZ:
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
case CLK_SRC_XTAL:
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
default:
return (clk_sel);
}
if (!(reg & 1)) {
clk_sel = (reg >> 24) & 0x1F;
}
return (clk_sel);
}
/*your_sha256_hash------------
Get clock frequency for specified clock source
*your_sha256_hash------------*/
uint32_t GetClockFreq (uint32_t clk_src) {
uint32_t tmp;
uint32_t mul = 1;
uint32_t div = 1;
uint32_t main_freq = 0;
int32_t clk_sel = clk_src;
do {
switch (clk_sel) {
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
case CLK_SRC_PLL0U: /* Not implemented */ break;
case CLK_SRC_PLL0A: /* Not implemented */ break;
case CLK_SRC_PLL1:
tmp = GetPLL1Param ();
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
break;
default:
return (0); /* Clock not running or not supported */
}
if (main_freq == 0) {
clk_sel = GetClkSel (clk_sel);
}
}
while (main_freq == 0);
return ((main_freq * mul) / div);
}
/*your_sha256_hash------------
System Core Clock update
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void) {
/* Check BASE_M4_CLK connection */
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
/* Update core clock frequency */
SystemCoreClock = GetClockFreq (base_src);
}
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
/*your_sha256_hash------------
Initialize the system
*your_sha256_hash------------*/
void SystemInit (void) {
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Stop CM0 core */
LPC_RGU->RESET_CTRL1 = (1 << 24);
/* Disable SysTick timer */
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
/* Set vector table pointer */
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */
//SystemInit_ExtMemCtl ();
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 13,036 |
```c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.2.0
*your_sha256_hash--------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 0
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 1
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF00A
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"LPC-Link2"
// <e.0>Serial Number String
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Default value
// <i>Default device's Serial Number String.
#define USBD0_STR_DESC_SER L"0001A0000000"
// <o.0..7>Maximum Length (in characters) <0-126>
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
#define USBD0_STR_DESC_SER_MAX_LEN 16
// </e>
// </h>
// <h>Microsoft OS Descriptors Settings
// <i>These settings are used to create the Microsoft OS Descriptors.
// <e.0>OS String
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
#define USBD0_OS_DESC_EN 1
// <o.0..7>Vendor Code <0x01-0xFF>
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
#define USBD0_OS_DESC_VENDOR_CODE 0x01
// </e>
// </h>
// <o>Control Transfer Buffer Size <64-65536:64>
// <i>Specifies size of buffer used for Control Transfers.
// <i>It should be at least as big as maximum packet size for Endpoint 0.
#define USBD0_EP0_BUF_SIZE 128
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 1024
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_4
#include "USBD_Config_CDC_4.h"
#endif
#ifdef RTE_USB_Device_CDC_5
#include "USBD_Config_CDC_5.h"
#endif
#ifdef RTE_USB_Device_CDC_6
#include "USBD_Config_CDC_6.h"
#endif
#ifdef RTE_USB_Device_CDC_7
#include "USBD_Config_CDC_7.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,799 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 21. May 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Template MDK5
* Title: main.c CMSIS-DAP Main module
*
*your_sha256_hash-----------*/
#include "cmsis_os2.h"
#include "osObjects.h"
#include "rl_usb.h"
#include "DAP_config.h"
#include "DAP.h"
// Application Main program
__NO_RETURN void app_main (void *argument) {
(void)argument;
DAP_Setup(); // DAP Setup
USBD_Initialize(0U); // USB Device Initialization
USBD_Connect(0U); // USB Device Connect
while (!USBD_Configured(0U)); // Wait for USB Device to configure
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
LED_RUNNING_OUT(1U); // Turn on Target Running LED
Delayms(500U); // Wait for 500ms
LED_RUNNING_OUT(0U); // Turn off Target Running LED
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
// Create DAP Thread
DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
// Create SWO Thread
SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
osDelay(osWaitForever);
for (;;) {}
}
int main (void) {
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
for (;;) {}
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Template/MDK5/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 454 |
```c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_User_HID_0.c
* Purpose: USB Device Human Interface Device class (HID) User module
* Rev.: V6.2.3
*your_sha256_hash------------*/
/**
* \addtogroup usbd_hidFunctions
*
* USBD_User_HID_0.c implements the application specific functionality of the
* HID class and is used to receive and send data reports to the USB Host.
*
* The implementation must match the configuration file USBD_Config_HID_0.h.
* The following values in USBD_Config_HID_0.h affect the user code:
*
* - 'Endpoint polling Interval' specifies the frequency of requests
* initiated by USB Host for \ref USBD_HIDn_GetReport.
*
* - 'Number of Output Reports' configures the values for \em rid of
* \ref USBD_HIDn_SetReport.
*
* - 'Number of Input Reports' configures the values for \em rid of
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
*
* - 'Maximum Input Report Size' specifies the maximum value for:
* - return of \ref USBD_HIDn_GetReport
* - len of \ref USBD_HID_GetReportTrigger.
*
* - 'Maximum Output Report Size' specifies the maximum value for \em len
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
*
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
*
*/
//! [code_USBD_User_HID]
#include <stdint.h>
#include <string.h>
#include "cmsis_os2.h"
#define osObjectsExternal
#include "osObjects.h"
#include "rl_usb.h"
#include "RTE\USB\USBD_Config_HID_0.h"
#include "DAP_config.h"
#include "DAP.h"
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
#error "USB HID0 Output Report Size must match DAP Packet Size"
#endif
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
#error "USB HID Input Report Size must match DAP Packet Size"
#endif
static volatile uint16_t USB_RequestIndexI; // Request Index In
static volatile uint16_t USB_RequestIndexO; // Request Index Out
static volatile uint16_t USB_RequestCountI; // Request Count In
static volatile uint16_t USB_RequestCountO; // Request Count Out
static volatile uint16_t USB_ResponseIndexI; // Response Index In
static volatile uint16_t USB_ResponseIndexO; // Response Index Out
static volatile uint16_t USB_ResponseCountI; // Response Count In
static volatile uint16_t USB_ResponseCountO; // Response Count Out
static volatile uint8_t USB_ResponseIdle; // Response Idle Flag
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
// Called during USBD_Initialize to initialize the USB HID class instance.
void USBD_HID0_Initialize (void) {
// Initialize variables
USB_RequestIndexI = 0U;
USB_RequestIndexO = 0U;
USB_RequestCountI = 0U;
USB_RequestCountO = 0U;
USB_ResponseIndexI = 0U;
USB_ResponseIndexO = 0U;
USB_ResponseCountI = 0U;
USB_ResponseCountO = 0U;
USB_ResponseIdle = 1U;
}
// Called during USBD_Uninitialize to de-initialize the USB HID class instance.
void USBD_HID0_Uninitialize (void) {
}
// \brief Prepare HID Report data to send.
// \param[in] rtype report type:
// - HID_REPORT_INPUT = input report requested
// - HID_REPORT_FEATURE = feature report requested
// \param[in] req request type:
// - USBD_HID_REQ_EP_CTRL = control endpoint request
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
// \param[in] rid report ID (0 if only one report exists).
// \param[out] buf buffer containing report data to send.
// \return number of report data bytes prepared to send or invalid report requested.
// - value >= 0: number of report data bytes prepared to send
// - value = -1: invalid report requested
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
(void)rid;
switch (rtype) {
case HID_REPORT_INPUT:
switch (req) {
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
break;
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
return ((int32_t)DAP_PACKET_SIZE);
} else {
USB_ResponseIdle = 1U;
}
break;
}
break;
case HID_REPORT_FEATURE:
break;
}
return (0);
}
// \brief Process received HID Report data.
// \param[in] rtype report type:
// - HID_REPORT_OUTPUT = output report received
// - HID_REPORT_FEATURE = feature report received
// \param[in] req request type:
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
// \param[in] rid report ID (0 if only one report exists).
// \param[in] buf buffer that receives report data.
// \param[in] len length of received report data.
// \return true received report data processed.
// \return false received report data not processed or request not supported.
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
(void)req;
(void)rid;
switch (rtype) {
case HID_REPORT_OUTPUT:
if (len == 0) {
break;
}
if (buf[0] == ID_DAP_TransferAbort) {
DAP_TransferAbort = 1U;
break;
}
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
osThreadFlagsSet(DAP_ThreadId, 0x80U);
break; // Discard packet when buffer is full
}
// Store received data into request buffer
memcpy(USB_Request[USB_RequestIndexI], buf, (uint32_t)len);
USB_RequestIndexI++;
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
USB_RequestIndexI = 0U;
}
USB_RequestCountI++;
osThreadFlagsSet(DAP_ThreadId, 0x01U);
break;
case HID_REPORT_FEATURE:
break;
}
return true;
}
// DAP Thread.
__NO_RETURN void DAP_Thread (void *argument) {
uint32_t flags;
uint32_t n;
(void) argument;
for (;;) {
osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
// Process pending requests
while (USB_RequestCountI != USB_RequestCountO) {
// Handle Queue Commands
n = USB_RequestIndexO;
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
USB_Request[n][0] = ID_DAP_ExecuteCommands;
n++;
if (n == DAP_PACKET_COUNT) {
n = 0U;
}
if (n == USB_RequestIndexI) {
flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
if (flags & 0x80U) {
break;
}
}
}
// Execute DAP Command (process request and prepare response)
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
// Update Request Index and Count
USB_RequestIndexO++;
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
USB_RequestIndexO = 0U;
}
USB_RequestCountO++;
// Update Response Index and Count
USB_ResponseIndexI++;
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
USB_ResponseIndexI = 0U;
}
USB_ResponseCountI++;
if (USB_ResponseIdle) {
if (USB_ResponseCountI != USB_ResponseCountO) {
// Load data from response buffer to be sent back
n = USB_ResponseIndexO++;
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
USB_ResponseIndexO = 0U;
}
USB_ResponseCountO++;
USB_ResponseIdle = 0U;
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
}
}
}
}
}
//! [code_USBD_User_HID]
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Template/MDK5/USBD_User_HID_0.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,215 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 11. June 2021
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Template MDK5
* Title: osObjects.h CMSIS-DAP RTOS2 Objects
*
*your_sha256_hash-----------*/
#ifndef __osObjects_h__
#define __osObjects_h__
#include "cmsis_os2.h"
#ifdef osObjectsExternal
extern osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
#else
static const osThreadAttr_t DAP_ThreadAttr = {
.priority = osPriorityNormal
};
static const osThreadAttr_t SWO_ThreadAttr = {
.priority = osPriorityAboveNormal
};
extern osThreadId_t DAP_ThreadId;
osThreadId_t DAP_ThreadId;
extern osThreadId_t SWO_ThreadId;
osThreadId_t SWO_ThreadId;
#endif
extern void DAP_Thread (void *argument);
extern void SWO_Thread (void *argument);
extern void app_main (void *argument);
#endif /* __osObjects_h__ */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Template/MDK5/osObjects.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 279 |
```batchfile
@ECHO off
REM Usage: test.bat [PATH TO UV4.exe]
IF "%1"=="" (
SET UV4_EXE=C:\Keil_v5\UV4\UV4.exe
) ELSE (
SET UV4_EXE=%1
)
ECHO Using %UV4_EXE%
ECHO.
ECHO Building application...
IF EXIST .\Objects\Validation.axf del .\Objects\Validation.axf
%UV4_EXE% -b Validation.uvprojx
IF EXIST .\Objects\Validation.axf (
ECHO Build succeded
) ELSE (
ECHO Build failed
GOTO :done
)
ECHO.
ECHO Loading application to hardware target...
%UV4_EXE% -f Validation.uvprojx -t"CMSIS_DAP"
IF ERRORLEVEL 1 (
ECHO Flash download failed
GOTO :done
)
ECHO.
ECHO Debugging hardware target...
IF EXIST .\test_results.txt del .\test_results.txt
%UV4_EXE% -d Validation.uvprojx -t"CMSIS_DAP"
IF EXIST .\test_results.txt (
TYPE .\test_results.txt
) ELSE (
ECHO Test ended abnormally - file test_results.txt was not produced
GOTO :done
)
ECHO.
ECHO All tests completed
:done
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Validation/MDK5/test.bat | batchfile | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 293 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 1. December 2017
* $Revision: V2.0.0
*
* Project: CMSIS-DAP Validation
* Title: test.c CMSIS-DAP debug unit test module
*
*your_sha256_hash-----------*/
// Debug Variables
volatile int test_state = 0;
volatile int test_success = 0;
volatile int bpTestCounter = 0;
volatile char mem_rw_success = 0;
int test_array1[256] = {0};
int test_array2[256] = {0};
// Breakpoint Test function
static void BP_Test (void) {
int i;
for (i = 0; i < 10; i++) {
// increment counter so we know on which iteration breakpoint is hit
bpTestCounter++;
test_state++;
}
}
// Test function
static void Test(void) {
int i;
test_state++; // 'test_state' = 11
i = test_success; // 'test_success' read access
test_state++; // 'test_state' = 12
test_success = i; // 'test_success' write access
test_state++; // 'test_state' = 13
// test_array1 should have already been written by debugger
// copy test_array1 into test_array2 for future comparison
mem_rw_success = 1; // assume all values were written correctly
for (i = 0; i < 256; i++) {
if (test_array1[i] != (0x1000+i)) {
mem_rw_success = 0;
}
test_array2[i] = test_array1[i];
}
test_state++; // 'test_state' = 14
test_state++; // 'test_state' = 15
test_state++; // 'test_state' = 16
// execute 'test_state -= 16' from debugger
test_state++; // 'test_state' = 1
if (test_state == 1) {
test_success = 1;
} else {
test_success = 0;
}
}
// 'main' function
int main (void) {
BP_Test();
Test();
for (;;) {};
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Validation/MDK5/test.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 550 |
```objective-c
/*your_sha256_hash--------------
* MDK Middleware - Component ::USB:Device
*your_sha256_hash--------------
* Name: USBD_Config_CustomClass_0.h
* Purpose: USB Device Custom Class Configuration
* Rev.: V5.2.0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Custom Class 0
// <i>Custom Class can be used to make support for Standard or Vendor-Specific Class
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CUSTOM_CLASS0_DEV 0
// <e0.0>Interface Association
// <i>Used for grouping of multiple interfaces to a single class.
#define USBD_CUSTOM_CLASS0_IAD_EN 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF0_EN 1
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF0_NUM 0
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF0_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 1
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 0.
#define USBD_CUSTOM_CLASS0_IF0_STR_EN 1
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF0_STR L"LPC-Link2 CMSIS-DAP"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR L"{CDB3B5AD-293B-4663-AA36-1AAE46463776}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF1_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF1_NUM 1
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF1_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 1.
#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF1_STR L"USB_CUSTOM_CLASS0_IF1"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF2_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF2_NUM 2
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF2_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 2.
#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF2_STR L"USB_CUSTOM_CLASS0_IF2"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <e>Interface
#define USBD_CUSTOM_CLASS0_IF3_EN 0
// <h>Interface Settings
// <i>The Interface Settings are used to create the Interface Descriptor.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about the Interface Descriptor.
// <o>Interface Number <0-255>
// <i>Defines the value for bInterfaceNumber
// <i>Each USB Device Interface has a sequential Interface Number starting with 0.
// <i>Several Interfaces may have the same Interface Number; in this case the value
// <i>of Alternate Setting is used to differ between the Interfaces. For a
// <i>composite device the Interface Numbers of the custom classes must be contiguous.
#define USBD_CUSTOM_CLASS0_IF3_NUM 3
// <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
// <i>Defines the value for bAlternateSetting
// <i>A sequential number starting with 0 to identify the Interface Descriptors
// <i>that share the same value for Interface Number.
#define USBD_CUSTOM_CLASS0_IF3_ALT 0
// <o.0..7>Class Code
// <i>Class Codes are defined by USB-IF. For more information refer to
// <i>path_to_url
// <0x00=>0x00: Indicate a Null Class Code triple
// <0x01=>0x01: Audio
// <0x02=>0x02: Communications and CDC Control
// <0x03=>0x03: HID (Human Interface Device)
// <0x05=>0x05: Physical
// <0x06=>0x06: Image
// <0x07=>0x07: Printer
// <0x08=>0x08: Mass Storage
// <0x0A=>0x0A: CDC-Data
// <0x0B=>0x0B: Smart Card
// <0x0D=>0x0D: Content Security
// <0x0E=>0x0E: Video
// <0x0F=>0x0F: Personal Healthcare
// <0x10=>0x10: Audio/Video Devices
// <0xDC=>0xDC: Diagnostic Device
// <0xE0=>0xE0: Wireless Controller
// <0xEF=>0xEF: Miscellaneous
// <0xFE=>0xFE: Application Specific
// <0xFF=>0xFF: Vendor Specific
#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF
// <o.0..7>Subclass Code <0x00-0xFF>
// <i>The possible values depend on the Class Code:
// <i>Class Code 0x00: Subclass Code must be 0
// <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
// <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00
// <o.0..7>Protocol Code <0x00-0xFF>
// <i>The Protocol Code value defines the protocol used on this interface:
// <i>Protocol Code 0x00: class-specific protocol not used
// <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
// <i>Protocol Code 0xFF: vendor-specific protocol used
#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00
// </h>
// <h>Endpoint Settings
// <i>Following settings are used to create the Endpoint Descriptors.
// <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
// <i>User's Guide for more information about Endpoint Descriptors.
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// <e>Endpoint
// <i>Enable Endpoint for this interface.
#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0
// <o.0..1>Type
// <i>Select Endpoint Type.
// <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
// <i>If required, for Isochronous Endpoint, Synchronization and Usage Type
// <i>can be set by manually editing define value of BMATTRIBUTES.
// <2=>Bulk
// <3=>Interrupt
// <1=>Isochronous
#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02
// <o.0..3>Number
// <i>Select Endpoint Number.
// <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
// <o.7>Direction
// <i>Select Endpoint Direction.
// <i>Endpoint Descriptor: bEndpointAddress field bit 7.
// <0=>OUT
// <1=>IN
#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84
// <h>Speed Settings
// <i>Settings that are different depending on device operating speed.
//
// <h>Full/Low-speed
// <i>Parameters apply when device operates in Full/Low-speed.
//
// <o.0..9>Maximum Packet Size <0-1023>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
// <i>For Interrupt Endpoint set value to 1 .. 64.
// <i>For Isochronous Endpoint set value to 1 .. 1023.
#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in ms).
// <i>Endpoint Descriptor: bInterval field.
// <i>Setting is not used for Bulk Endpoint (set value to 0).
// <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
// <i>(n is the index of device on which this interface will be used) and when
// <i>device operates in High-speed.
//
// <o.0..10>Maximum Packet Size <0-1024>
// <i>Specifies the physical packet size used for information exchange (in bytes).
// <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
// <i>For Bulk Endpoint set value to 512.
// <i>For Interrupt Endpoint set value to 1 .. 1024.
// <i>For Isochronous Endpoint set value to 1 .. 1024.
// <o.11..12>Additional Transactions per Microframe
// <i>Specifies additional transactions per microframe to improve communication performance.
// <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
// <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
// <i>Value: None = 1 transaction per microframe
// <i>Value: 1 additional = 2 transaction per microframe
// <i>Value: 2 additional = 3 transaction per microframe
// <0=>None
// <1=>1 additional
// <2=>2 additional
#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512
// <o.0..7>Endpoint Polling Interval <0-255>
// <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
// <i>Endpoint Descriptor: bInterval field.
// <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
// <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
// <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0
// </h>
// </h>
// </e>
// </h>
// <h>String Settings
// <i>Following settings are used to create String Descriptor(s)
// <e.0>Interface String Enable
// <i>Enable Interface String.
// <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 3.
#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0
// <s.126>Interface String
#define USBD_CUSTOM_CLASS0_IF3_STR L"USB_CUSTOM_CLASS0_IF3"
// </e>
// </h>
// <h>Microsoft OS Descriptor Settings
// <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
// <e.0>Extended Compat ID OS Feature Descriptor Function Section
// <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0
// <s.7>compatibleID
// <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB"
// <s.7>subCompatibleID
// <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID ""
// </e>
// <h>Extended Properties OS Feature Descriptor
// <e.0>Custom Property Section 0
// <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME L"DeviceInterfaceGUID"
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 1
// <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 2
// <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0
// </h>
// </e>
// <e.0>Custom Property Section 3
// <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0
// <o>Data Type
// <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
// <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
// <1=>Unicode String (REG_SZ)
// <2=>Unicode String with environment variables (REG_EXPAND_SZ)
// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
// <6=>Unicode String with symbolic link (REG_LINK)
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1
// <s.512>Name
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME L""
// <h>Data
// <s.1024>Unicode String
// <i>Property Data in case Data Type is selected as Unicode String.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR L""
// <o>32-bit Integer
// <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0
// </h>
// </e>
// </h>
// </h>
// </e>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Endpoint 1 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 1 is enabled.
#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512
// Endpoint 1 Thread Priority
#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 2 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 2 is enabled.
#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512
// Endpoint 2 Thread Priority
#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 3 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 3 is enabled.
#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512
// Endpoint 3 Thread Priority
#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 4 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 4 is enabled.
#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512
// Endpoint 4 Thread Priority
#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 5 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 5 is enabled.
#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512
// Endpoint 5 Thread Priority
#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 6 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 6 is enabled.
#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512
// Endpoint 6 Thread Priority
#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 7 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 7 is enabled.
#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512
// Endpoint 7 Thread Priority
#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 8 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 8 is enabled.
#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512
// Endpoint 8 Thread Priority
#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 9 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 9 is enabled.
#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512
// Endpoint 9 Thread Priority
#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 10 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 10 is enabled.
#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512
// Endpoint 10 Thread Priority
#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 11 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 11 is enabled.
#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512
// Endpoint 11 Thread Priority
#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 12 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 12 is enabled.
#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512
// Endpoint 12 Thread Priority
#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 13 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 13 is enabled.
#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512
// Endpoint 13 Thread Priority
#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 14 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 14 is enabled.
#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512
// Endpoint 14 Thread Priority
#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal
// <o>Endpoint 15 Thread Stack Size <64-65536>
// <i>This setting is used if Endpoint 15 is enabled.
#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512
// Endpoint 15 Thread Priority
#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_CustomClass_0.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 49,405 |
```gas
;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 0: Watchdog Timer
DCD RTC_IRQHandler ; 1: Real Time Clock
DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
DCD MCIA_IRQHandler ; 4: MCIa
DCD MCIB_IRQHandler ; 5: MCIb
DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
DCD UART4_IRQHandler ; 9: UART4 - not connected
DCD AACI_IRQHandler ; 10: AACI / AC97
DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
DCD ENET_IRQHandler ; 12: Ethernet
DCD USBDC_IRQHandler ; 13: USB Device
DCD USBHC_IRQHandler ; 14: USB Host Controller
DCD CHLCD_IRQHandler ; 15: Character LCD
DCD FLEXRAY_IRQHandler ; 16: Flexray
DCD CAN_IRQHandler ; 17: CAN
DCD LIN_IRQHandler ; 18: LIN
DCD I2C_IRQHandler ; 19: I2C ADC/DAC
DCD 0 ; 20: Reserved
DCD 0 ; 21: Reserved
DCD 0 ; 22: Reserved
DCD 0 ; 23: Reserved
DCD 0 ; 24: Reserved
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD 0 ; 27: Reserved
DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
DCD 0 ; 29: Reserved - CPU FPGA
DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TIM0_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MCIA_IRQHandler [WEAK]
EXPORT MCIB_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT AACI_IRQHandler [WEAK]
EXPORT CLCD_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT USBDC_IRQHandler [WEAK]
EXPORT USBHC_IRQHandler [WEAK]
EXPORT CHLCD_IRQHandler [WEAK]
EXPORT FLEXRAY_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT LIN_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CPU_CLCD_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
WDT_IRQHandler
RTC_IRQHandler
TIM0_IRQHandler
TIM2_IRQHandler
MCIA_IRQHandler
MCIB_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
AACI_IRQHandler
CLCD_IRQHandler
ENET_IRQHandler
USBDC_IRQHandler
USBHC_IRQHandler
CHLCD_IRQHandler
FLEXRAY_IRQHandler
CAN_IRQHandler
LIN_IRQHandler
I2C_IRQHandler
CPU_CLCD_IRQHandler
SPI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/startup_ARMCM3.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,905 |
```c
/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V5.00
* @date 07. September 2016
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "ARMCM3.h"
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*your_sha256_hash------------
Externals
*your_sha256_hash------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Validation/MDK5/RTE/Device/ARMCM3/system_ARMCM3.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 335 |
```objective-c
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Validation'
* Target: 'CMSIS_DAP'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM3.h"
#endif /* RTE_COMPONENTS_H */
``` | /content/code_sandbox/CMSIS/DAP/Firmware/Validation/MDK5/RTE/_CMSIS_DAP/RTE_Components.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 81 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 3. April 2023
* $Revision: V2.2.0
*
* Project: CMSIS-RTOS2 API
* Title: cmsis_os2.h header file
*
* Version 2.2.0
* Added support for Process Isolation (Functional Safety):
* - Kernel Management: osKernelProtect, osKernelDestroyClass
* - Thread Management: osThreadGetClass, osThreadGetZone,
* osThreadSuspendClass, osThreadResumeClass
* osThreadTerminateZone,
* osThreadFeedWatchdog,
* osThreadProtectPrivileged
* - Thread attributes: osThreadZone, osThreadUnprivileged/osThreadPrivileged
* - Object attributes: osSafetyClass
* - Handler functions: osWatchdogAlarm_Handler
* - Zone Management: osZoneSetup_Callback
* - Exception Faults: osFaultResume
* Additional functions allowed to be called from Interrupt Service Routines:
* - osThreadGetName, osTimerGetName, osEventFlagsGetName, osMutexGetName,
* osSemaphoreGetName, osMemoryPoolGetName, osMessageQueueGetName
* Version 2.1.3
* Additional functions allowed to be called from Interrupt Service Routines:
* - osThreadGetId
* Version 2.1.2
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetInfo, osKernelGetState
* Version 2.1.1
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetTickCount, osKernelGetTickFreq
* Changed Kernel Tick type to uint32_t:
* - updated: osKernelGetTickCount, osDelayUntil
* Version 2.1.0
* Support for critical and uncritical sections (nesting safe):
* - updated: osKernelLock, osKernelUnlock
* - added: osKernelRestoreLock
* Updated Thread and Event Flags:
* - changed flags parameter and return type from int32_t to uint32_t
* Version 2.0.0
* Initial Release
*your_sha256_hash-----------*/
#ifndef CMSIS_OS2_H_
#define CMSIS_OS2_H_
#ifndef __NO_RETURN
#if defined(__CC_ARM)
#define __NO_RETURN __declspec(noreturn)
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __NO_RETURN __attribute__((__noreturn__))
#elif defined(__GNUC__)
#define __NO_RETURN __attribute__((__noreturn__))
#elif defined(__ICCARM__)
#define __NO_RETURN __noreturn
#else
#define __NO_RETURN
#endif
#endif
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C"
{
#endif
// ==== Enumerations, structures, defines ====
/// Version information.
typedef struct {
uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
} osVersion_t;
/// Kernel state.
typedef enum {
osKernelInactive = 0, ///< Inactive.
osKernelReady = 1, ///< Ready.
osKernelRunning = 2, ///< Running.
osKernelLocked = 3, ///< Locked.
osKernelSuspended = 4, ///< Suspended.
osKernelError = -1, ///< Error.
osKernelReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osKernelState_t;
/// Thread state.
typedef enum {
osThreadInactive = 0, ///< Inactive.
osThreadReady = 1, ///< Ready.
osThreadRunning = 2, ///< Running.
osThreadBlocked = 3, ///< Blocked.
osThreadTerminated = 4, ///< Terminated.
osThreadError = -1, ///< Error.
osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osThreadState_t;
/// Priority values.
typedef enum {
osPriorityNone = 0, ///< No priority (not initialized).
osPriorityIdle = 1, ///< Reserved for Idle thread.
osPriorityLow = 8, ///< Priority: low
osPriorityLow1 = 8+1, ///< Priority: low + 1
osPriorityLow2 = 8+2, ///< Priority: low + 2
osPriorityLow3 = 8+3, ///< Priority: low + 3
osPriorityLow4 = 8+4, ///< Priority: low + 4
osPriorityLow5 = 8+5, ///< Priority: low + 5
osPriorityLow6 = 8+6, ///< Priority: low + 6
osPriorityLow7 = 8+7, ///< Priority: low + 7
osPriorityBelowNormal = 16, ///< Priority: below normal
osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
osPriorityNormal = 24, ///< Priority: normal
osPriorityNormal1 = 24+1, ///< Priority: normal + 1
osPriorityNormal2 = 24+2, ///< Priority: normal + 2
osPriorityNormal3 = 24+3, ///< Priority: normal + 3
osPriorityNormal4 = 24+4, ///< Priority: normal + 4
osPriorityNormal5 = 24+5, ///< Priority: normal + 5
osPriorityNormal6 = 24+6, ///< Priority: normal + 6
osPriorityNormal7 = 24+7, ///< Priority: normal + 7
osPriorityAboveNormal = 32, ///< Priority: above normal
osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
osPriorityHigh = 40, ///< Priority: high
osPriorityHigh1 = 40+1, ///< Priority: high + 1
osPriorityHigh2 = 40+2, ///< Priority: high + 2
osPriorityHigh3 = 40+3, ///< Priority: high + 3
osPriorityHigh4 = 40+4, ///< Priority: high + 4
osPriorityHigh5 = 40+5, ///< Priority: high + 5
osPriorityHigh6 = 40+6, ///< Priority: high + 6
osPriorityHigh7 = 40+7, ///< Priority: high + 7
osPriorityRealtime = 48, ///< Priority: realtime
osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
osPriorityISR = 56, ///< Reserved for ISR deferred thread.
osPriorityError = -1, ///< System cannot determine priority or illegal priority.
osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osPriority_t;
/// Entry point of a thread.
typedef void (*osThreadFunc_t) (void *argument);
/// Timer callback function.
typedef void (*osTimerFunc_t) (void *argument);
/// Timer type.
typedef enum {
osTimerOnce = 0, ///< One-shot timer.
osTimerPeriodic = 1 ///< Repeating timer.
} osTimerType_t;
// Timeout value.
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
#define osFlagsError 0x80000000U ///< Error indicator.
#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
#define osFlagsErrorSafetyClass 0xFFFFFFF9U ///< osErrorSafetyClass (-7).
// Thread attributes (attr_bits in \ref osThreadAttr_t).
#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default)
#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode
#define osThreadUnprivileged 0x00000002U ///< Thread runs in unprivileged mode
#define osThreadPrivileged 0x00000004U ///< Thread runs in privileged mode
#define osThreadZone_Pos 8U ///< MPU protected zone position
#define osThreadZone_Msk (0x3FUL << osThreadZone_Pos) ///< MPU protected zone mask
#define osThreadZone_Valid (0x80UL << osThreadZone_Pos) ///< MPU protected zone valid flag
#define osThreadZone(n) ((((n) << osThreadZone_Pos) & osThreadZone_Msk) | \
osThreadZone_Valid) ///< MPU protected zone
// Mutex attributes (attr_bits in \ref osMutexAttr_t).
#define osMutexRecursive 0x00000001U ///< Recursive mutex.
#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
#define osMutexRobust 0x00000008U ///< Robust mutex.
// Object attributes (attr_bits in all objects)
#define osSafetyClass_Pos 16U ///< Safety class position
#define osSafetyClass_Msk (0x0FUL << osSafetyClass_Pos) ///< Safety class mask
#define osSafetyClass_Valid (0x10UL << osSafetyClass_Pos) ///< Safety class valid flag
#define osSafetyClass(n) ((((n) << osSafetyClass_Pos) & osSafetyClass_Msk) | \
osSafetyClass_Valid) ///< Safety class
// Safety mode (\ref osThreadSuspendClass, \ref osThreadResumeClass and \ref osKernelDestroyClass).
#define osSafetyWithSameClass 0x00000001U ///< Objects with same safety class.
#define osSafetyWithLowerClass 0x00000002U ///< Objects with lower safety class.
// Error indication (returned by \ref osThreadGetClass and \ref osThreadGetZone).
#define osErrorId 0xFFFFFFFFU ///< osError (-1).
/// Status code values returned by CMSIS-RTOS functions.
typedef enum {
osOK = 0, ///< Operation completed successfully.
osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
osErrorTimeout = -2, ///< Operation not completed within the timeout period.
osErrorResource = -3, ///< Resource not available.
osErrorParameter = -4, ///< Parameter error.
osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
osErrorSafetyClass = -7, ///< Operation denied because of safety class violation.
osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osStatus_t;
/// \details Thread ID identifies the thread.
typedef void *osThreadId_t;
/// \details Timer ID identifies the timer.
typedef void *osTimerId_t;
/// \details Event Flags ID identifies the event flags.
typedef void *osEventFlagsId_t;
/// \details Mutex ID identifies the mutex.
typedef void *osMutexId_t;
/// \details Semaphore ID identifies the semaphore.
typedef void *osSemaphoreId_t;
/// \details Memory Pool ID identifies the memory pool.
typedef void *osMemoryPoolId_t;
/// \details Message Queue ID identifies the message queue.
typedef void *osMessageQueueId_t;
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// Attributes structure for thread.
typedef struct {
const char *name; ///< name of the thread
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
void *stack_mem; ///< memory for stack
uint32_t stack_size; ///< size of stack
osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
TZ_ModuleId_t tz_module; ///< TrustZone module identifier
uint32_t reserved; ///< reserved (must be 0)
} osThreadAttr_t;
/// Attributes structure for timer.
typedef struct {
const char *name; ///< name of the timer
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
} osTimerAttr_t;
/// Attributes structure for event flags.
typedef struct {
const char *name; ///< name of the event flags
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
} osEventFlagsAttr_t;
/// Attributes structure for mutex.
typedef struct {
const char *name; ///< name of the mutex
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
} osMutexAttr_t;
/// Attributes structure for semaphore.
typedef struct {
const char *name; ///< name of the semaphore
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
} osSemaphoreAttr_t;
/// Attributes structure for memory pool.
typedef struct {
const char *name; ///< name of the memory pool
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
void *mp_mem; ///< memory for data storage
uint32_t mp_size; ///< size of provided memory for data storage
} osMemoryPoolAttr_t;
/// Attributes structure for message queue.
typedef struct {
const char *name; ///< name of the message queue
uint32_t attr_bits; ///< attribute bits
void *cb_mem; ///< memory for control block
uint32_t cb_size; ///< size of provided memory for control block
void *mq_mem; ///< memory for data storage
uint32_t mq_size; ///< size of provided memory for data storage
} osMessageQueueAttr_t;
// ==== Kernel Management Functions ====
/// Initialize the RTOS Kernel.
/// \return status code that indicates the execution status of the function.
osStatus_t osKernelInitialize (void);
/// Get RTOS Kernel Information.
/// \param[out] version pointer to buffer for retrieving version information.
/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
/// \param[in] id_size size of buffer for kernel identification string.
/// \return status code that indicates the execution status of the function.
osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
/// Get the current RTOS Kernel state.
/// \return current RTOS Kernel state.
osKernelState_t osKernelGetState (void);
/// Start the RTOS Kernel scheduler.
/// \return status code that indicates the execution status of the function.
osStatus_t osKernelStart (void);
/// Lock the RTOS Kernel scheduler.
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
int32_t osKernelLock (void);
/// Unlock the RTOS Kernel scheduler.
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
int32_t osKernelUnlock (void);
/// Restore the RTOS Kernel scheduler lock state.
/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
int32_t osKernelRestoreLock (int32_t lock);
/// Suspend the RTOS Kernel scheduler.
/// \return time in ticks, for how long the system can sleep or power-down.
uint32_t osKernelSuspend (void);
/// Resume the RTOS Kernel scheduler.
/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
void osKernelResume (uint32_t sleep_ticks);
/// Protect the RTOS Kernel scheduler access.
/// \param[in] safety_class safety class.
/// \return status code that indicates the execution status of the function.
osStatus_t osKernelProtect (uint32_t safety_class);
/// Destroy objects for specified safety classes.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
/// \return status code that indicates the execution status of the function.
osStatus_t osKernelDestroyClass (uint32_t safety_class, uint32_t mode);
/// Get the RTOS kernel tick count.
/// \return RTOS kernel current tick count.
uint32_t osKernelGetTickCount (void);
/// Get the RTOS kernel tick frequency.
/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
uint32_t osKernelGetTickFreq (void);
/// Get the RTOS kernel system timer count.
/// \return RTOS kernel current system timer count as 32-bit value.
uint32_t osKernelGetSysTimerCount (void);
/// Get the RTOS kernel system timer frequency.
/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
uint32_t osKernelGetSysTimerFreq (void);
// ==== Thread Management Functions ====
/// Create a thread and add it to Active Threads.
/// \param[in] func thread function.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \param[in] attr thread attributes; NULL: default values.
/// \return thread ID for reference by other functions or NULL in case of error.
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
/// Get name of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return name as null-terminated string.
const char *osThreadGetName (osThreadId_t thread_id);
/// Get safety class of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return safety class of the specified thread.
uint32_t osThreadGetClass (osThreadId_t thread_id);
/// Get MPU protected zone of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return MPU protected zone of the specified thread.
uint32_t osThreadGetZone (osThreadId_t thread_id);
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
osThreadId_t osThreadGetId (void);
/// Get current thread state of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return current thread state of the specified thread.
osThreadState_t osThreadGetState (osThreadId_t thread_id);
/// Get stack size of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return stack size in bytes.
uint32_t osThreadGetStackSize (osThreadId_t thread_id);
/// Get available stack space of a thread based on stack watermark recording during execution.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return remaining stack space in bytes.
uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
/// Change priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
/// Get current priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return current priority value of the specified thread.
osPriority_t osThreadGetPriority (osThreadId_t thread_id);
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadYield (void);
/// Suspend execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadSuspend (osThreadId_t thread_id);
/// Resume execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadResume (osThreadId_t thread_id);
/// Detach a thread (thread storage can be reclaimed when thread terminates).
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadDetach (osThreadId_t thread_id);
/// Wait for specified thread to terminate.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadJoin (osThreadId_t thread_id);
/// Terminate execution of current running thread.
__NO_RETURN void osThreadExit (void);
/// Terminate execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadTerminate (osThreadId_t thread_id);
/// Feed watchdog of the current running thread.
/// \param[in] ticks \ref kernelTimer "time ticks" value until the thread watchdog expires, or 0 to stop the watchdog
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadFeedWatchdog (uint32_t ticks);
/// Protect creation of privileged threads.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadProtectPrivileged (void);
/// Suspend execution of threads for specified safety classes.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadSuspendClass (uint32_t safety_class, uint32_t mode);
/// Resume execution of threads for specified safety classes.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadResumeClass (uint32_t safety_class, uint32_t mode);
/// Terminate execution of threads assigned to a specified MPU protected zone.
/// \param[in] zone MPU protected zone.
/// \return status code that indicates the execution status of the function.
osStatus_t osThreadTerminateZone (uint32_t zone);
/// Get number of active threads.
/// \return number of active threads.
uint32_t osThreadGetCount (void);
/// Enumerate active threads.
/// \param[out] thread_array pointer to array for retrieving thread IDs.
/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
/// \return number of enumerated threads.
uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
// ==== Thread Flags Functions ====
/// Set the specified Thread Flags of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \param[in] flags specifies the flags of the thread that shall be set.
/// \return thread flags after setting or error code if highest bit set.
uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
/// Clear the specified Thread Flags of current running thread.
/// \param[in] flags specifies the flags of the thread that shall be cleared.
/// \return thread flags before clearing or error code if highest bit set.
uint32_t osThreadFlagsClear (uint32_t flags);
/// Get the current Thread Flags of current running thread.
/// \return current thread flags.
uint32_t osThreadFlagsGet (void);
/// Wait for one or more Thread Flags of the current running thread to become signaled.
/// \param[in] flags specifies the flags to wait for.
/// \param[in] options specifies flags options (osFlagsXxxx).
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return thread flags before clearing or error code if highest bit set.
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay).
/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
/// \return status code that indicates the execution status of the function.
osStatus_t osDelay (uint32_t ticks);
/// Wait until specified time.
/// \param[in] ticks absolute time in ticks
/// \return status code that indicates the execution status of the function.
osStatus_t osDelayUntil (uint32_t ticks);
// ==== Timer Management Functions ====
/// Create and Initialize a timer.
/// \param[in] func function pointer to callback function.
/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer callback function.
/// \param[in] attr timer attributes; NULL: default values.
/// \return timer ID for reference by other functions or NULL in case of error.
osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
/// Get name of a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
/// \return name as null-terminated string.
const char *osTimerGetName (osTimerId_t timer_id);
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
/// \return status code that indicates the execution status of the function.
osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
/// Stop a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osTimerStop (osTimerId_t timer_id);
/// Check if a timer is running.
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
/// \return 0 not running, 1 running.
uint32_t osTimerIsRunning (osTimerId_t timer_id);
/// Delete a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osTimerDelete (osTimerId_t timer_id);
// ==== Event Flags Management Functions ====
/// Create and Initialize an Event Flags object.
/// \param[in] attr event flags attributes; NULL: default values.
/// \return event flags ID for reference by other functions or NULL in case of error.
osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
/// Get name of an Event Flags object.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \return name as null-terminated string.
const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
/// Set the specified Event Flags.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \param[in] flags specifies the flags that shall be set.
/// \return event flags after setting or error code if highest bit set.
uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
/// Clear the specified Event Flags.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \param[in] flags specifies the flags that shall be cleared.
/// \return event flags before clearing or error code if highest bit set.
uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
/// Get the current Event Flags.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \return current event flags.
uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
/// Wait for one or more Event Flags to become signaled.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \param[in] flags specifies the flags to wait for.
/// \param[in] options specifies flags options (osFlagsXxxx).
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event flags before clearing or error code if highest bit set.
uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
/// Delete an Event Flags object.
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
// ==== Mutex Management Functions ====
/// Create and Initialize a Mutex object.
/// \param[in] attr mutex attributes; NULL: default values.
/// \return mutex ID for reference by other functions or NULL in case of error.
osMutexId_t osMutexNew (const osMutexAttr_t *attr);
/// Get name of a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
/// \return name as null-terminated string.
const char *osMutexGetName (osMutexId_t mutex_id);
/// Acquire a Mutex or timeout if it is locked.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
/// Release a Mutex that was acquired by \ref osMutexAcquire.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osMutexRelease (osMutexId_t mutex_id);
/// Get Thread which owns a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
/// \return thread ID of owner thread or NULL when mutex was not acquired.
osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
/// Delete a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osMutexDelete (osMutexId_t mutex_id);
// ==== Semaphore Management Functions ====
/// Create and Initialize a Semaphore object.
/// \param[in] max_count maximum number of available tokens.
/// \param[in] initial_count initial number of available tokens.
/// \param[in] attr semaphore attributes; NULL: default values.
/// \return semaphore ID for reference by other functions or NULL in case of error.
osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
/// Get name of a Semaphore object.
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
/// \return name as null-terminated string.
const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
/// Acquire a Semaphore token or timeout if no tokens are available.
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
/// Release a Semaphore token up to the initial maximum count.
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
/// Get current Semaphore token count.
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
/// \return number of tokens available.
uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
/// Delete a Semaphore object.
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
// ==== Memory Pool Management Functions ====
/// Create and Initialize a Memory Pool object.
/// \param[in] block_count maximum number of memory blocks in memory pool.
/// \param[in] block_size memory block size in bytes.
/// \param[in] attr memory pool attributes; NULL: default values.
/// \return memory pool ID for reference by other functions or NULL in case of error.
osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
/// Get name of a Memory Pool object.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return name as null-terminated string.
const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
/// Allocate a memory block from a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return address of the allocated memory block or NULL in case of no memory is available.
void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return status code that indicates the execution status of the function.
osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
/// Get maximum number of memory blocks in a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return maximum number of memory blocks.
uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
/// Get memory block size in a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return memory block size in bytes.
uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
/// Get number of memory blocks used in a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return number of memory blocks used.
uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
/// Get number of memory blocks available in a Memory Pool.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return number of memory blocks available.
uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
/// Delete a Memory Pool object.
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
// ==== Message Queue Management Functions ====
/// Create and Initialize a Message Queue object.
/// \param[in] msg_count maximum number of messages in queue.
/// \param[in] msg_size maximum message size in bytes.
/// \param[in] attr message queue attributes; NULL: default values.
/// \return message queue ID for reference by other functions or NULL in case of error.
osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
/// Get name of a Message Queue object.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return name as null-terminated string.
const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
/// Put a Message into a Queue or timeout if Queue is full.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
/// \param[in] msg_prio message priority.
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
/// Get a Message from a Queue or timeout if Queue is empty.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
/// \param[out] msg_prio pointer to buffer for message priority or NULL.
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
/// Get maximum number of messages in a Message Queue.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return maximum number of messages.
uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
/// Get maximum message size in a Message Queue.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return maximum message size in bytes.
uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
/// Get number of queued messages in a Message Queue.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return number of queued messages.
uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
/// Get number of available slots for messages in a Message Queue.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return number of available slots for messages.
uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
/// Reset a Message Queue to initial empty state.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
/// Delete a Message Queue object.
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
/// \return status code that indicates the execution status of the function.
osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
// ==== Handler Functions ====
/// Handler for expired thread watchdogs.
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
/// \return new watchdog reload value or 0 to stop the watchdog.
uint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id);
// ==== Zone Management Function ====
/// Setup MPU protected zone (called when zone changes).
/// \param[in] zone zone number.
void osZoneSetup_Callback (uint32_t zone);
// ==== Exception Faults ====
/// Resume normal operation when exiting exception faults
void osFaultResume (void);
#ifdef __cplusplus
}
#endif
#endif // CMSIS_OS2_H_
``` | /content/code_sandbox/CMSIS/RTOS2/Include/cmsis_os2.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 9,934 |
```c
/**************************************************************************//**
* @file os_systick.c
* @brief CMSIS OS Tick SysTick implementation
* @version V1.0.4
* @date 20. January 2023
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "os_tick.h"
//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer"
#include "RTE_Components.h"
#include CMSIS_device_header
#ifdef SysTick
#ifndef SYSTICK_IRQ_PRIORITY
#define SYSTICK_IRQ_PRIORITY 0xFFU
#endif
static uint8_t PendST __attribute__((section(".bss.os")));
// Setup OS Tick.
__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
uint32_t load;
(void)handler;
if (freq == 0U) {
//lint -e{904} "Return statement before end of function"
return (-1);
}
load = (SystemCoreClock / freq) - 1U;
if (load > 0x00FFFFFFU) {
//lint -e{904} "Return statement before end of function"
return (-1);
}
// Set SysTick Interrupt Priority
#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \
(defined(__CORTEX_M) && (__CORTEX_M == 7U)))
SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;
#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)))
SCB->SHP[11] = SYSTICK_IRQ_PRIORITY;
#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0))
SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
#else
#error "Unknown ARM Core!"
#endif
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;
SysTick->LOAD = load;
SysTick->VAL = 0U;
PendST = 0U;
return (0);
}
/// Enable OS Tick.
__WEAK void OS_Tick_Enable (void) {
if (PendST != 0U) {
PendST = 0U;
SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
}
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
/// Disable OS Tick.
__WEAK void OS_Tick_Disable (void) {
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {
SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
PendST = 1U;
}
}
// Acknowledge OS Tick IRQ.
__WEAK void OS_Tick_AcknowledgeIRQ (void) {
(void)SysTick->CTRL;
}
// Get OS Tick IRQ number.
__WEAK int32_t OS_Tick_GetIRQn (void) {
return ((int32_t)SysTick_IRQn);
}
// Get OS Tick clock.
__WEAK uint32_t OS_Tick_GetClock (void) {
return (SystemCoreClock);
}
// Get OS Tick interval.
__WEAK uint32_t OS_Tick_GetInterval (void) {
return (SysTick->LOAD + 1U);
}
// Get OS Tick count value.
__WEAK uint32_t OS_Tick_GetCount (void) {
uint32_t val;
uint32_t count;
val = SysTick->VAL;
if (val != 0U) {
count = (SysTick->LOAD - val) + 1U;
} else {
count = 0U;
}
return (count);
}
// Get OS Tick overflow status.
__WEAK uint32_t OS_Tick_GetOverflow (void) {
return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos);
}
#endif // SysTick
``` | /content/code_sandbox/CMSIS/RTOS2/Source/os_systick.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,062 |
```objective-c
/**************************************************************************//**
* @file os_tick.h
* @brief CMSIS OS Tick header file
* @version V1.0.2
* @date 19. March 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef OS_TICK_H
#define OS_TICK_H
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
/// IRQ Handler.
#ifndef IRQHANDLER_T
#define IRQHANDLER_T
typedef void (*IRQHandler_t) (void);
#endif
/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks
/// \param[in] freq tick frequency in Hz
/// \param[in] handler tick IRQ handler
/// \return 0 on success, -1 on error.
int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler);
/// Enable OS Tick timer interrupt
void OS_Tick_Enable (void);
/// Disable OS Tick timer interrupt
void OS_Tick_Disable (void);
/// Acknowledge execution of OS Tick timer interrupt
void OS_Tick_AcknowledgeIRQ (void);
/// Get OS Tick timer IRQ number
/// \return OS Tick IRQ number
int32_t OS_Tick_GetIRQn (void);
/// Get OS Tick timer clock frequency
/// \return OS Tick timer clock frequency in Hz
uint32_t OS_Tick_GetClock (void);
/// Get OS Tick timer interval reload value
/// \return OS Tick timer interval reload value
uint32_t OS_Tick_GetInterval (void);
/// Get OS Tick timer counter value
/// \return OS Tick timer counter value
uint32_t OS_Tick_GetCount (void);
/// Get OS Tick timer overflow status
/// \return OS Tick overflow status (1 - overflow, 0 - no overflow).
uint32_t OS_Tick_GetOverflow (void);
#ifdef __cplusplus
}
#endif
#endif /* OS_TICK_H */
``` | /content/code_sandbox/CMSIS/RTOS2/Include/os_tick.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 433 |
```c
/**************************************************************************//**
* @file os_tick_ptim.c
* @brief CMSIS OS Tick implementation for Private Timer
* @version V1.0.2
* @date 02. March 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#if defined(PTIM)
#include "os_tick.h"
#include "irq_ctrl.h"
#ifndef PTIM_IRQ_PRIORITY
#define PTIM_IRQ_PRIORITY 0xFFU
#endif
static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag
// Setup OS Tick.
int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
uint32_t load;
uint32_t prio;
uint32_t bits;
if (freq == 0U) {
return (-1);
}
PTIM_PendIRQ = 0U;
// Private Timer runs with the system frequency
load = (SystemCoreClock / freq) - 1U;
// Disable Private Timer and set load value
PTIM_SetControl (0U);
PTIM_SetLoadValue (load);
// Disable corresponding IRQ
IRQ_Disable (PrivTimer_IRQn);
IRQ_ClearPending(PrivTimer_IRQn);
// Determine number of implemented priority bits
IRQ_SetPriority (PrivTimer_IRQn, 0xFFU);
prio = IRQ_GetPriority (PrivTimer_IRQn);
// At least bits [7:4] must be implemented
if ((prio & 0xF0U) == 0U) {
return (-1);
}
for (bits = 0; bits < 4; bits++) {
if ((prio & 0x01) != 0) {
break;
}
prio >>= 1;
}
// Adjust configured priority to the number of implemented priority bits
prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL;
// Set Private Timer interrupt priority
IRQ_SetPriority(PrivTimer_IRQn, prio-1U);
// Set edge-triggered IRQ
IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE);
// Register tick interrupt handler function
IRQ_SetHandler(PrivTimer_IRQn, handler);
// Enable corresponding interrupt
IRQ_Enable (PrivTimer_IRQn);
// Set bits: IRQ enable and Auto reload
PTIM_SetControl (0x06U);
return (0);
}
/// Enable OS Tick.
void OS_Tick_Enable (void) {
uint32_t ctrl;
// Set pending interrupt if flag set
if (PTIM_PendIRQ != 0U) {
PTIM_PendIRQ = 0U;
IRQ_SetPending (PrivTimer_IRQn);
}
// Start the Private Timer
ctrl = PTIM_GetControl();
// Set bit: Timer enable
ctrl |= 1U;
PTIM_SetControl (ctrl);
}
/// Disable OS Tick.
void OS_Tick_Disable (void) {
uint32_t ctrl;
// Stop the Private Timer
ctrl = PTIM_GetControl();
// Clear bit: Timer enable
ctrl &= ~1U;
PTIM_SetControl (ctrl);
// Remember pending interrupt flag
if (IRQ_GetPending(PrivTimer_IRQn) != 0) {
IRQ_ClearPending (PrivTimer_IRQn);
PTIM_PendIRQ = 1U;
}
}
// Acknowledge OS Tick IRQ.
void OS_Tick_AcknowledgeIRQ (void) {
PTIM_ClearEventFlag();
}
// Get OS Tick IRQ number.
int32_t OS_Tick_GetIRQn (void) {
return (PrivTimer_IRQn);
}
// Get OS Tick clock.
uint32_t OS_Tick_GetClock (void) {
return (SystemCoreClock);
}
// Get OS Tick interval.
uint32_t OS_Tick_GetInterval (void) {
return (PTIM_GetLoadValue() + 1U);
}
// Get OS Tick count value.
uint32_t OS_Tick_GetCount (void) {
uint32_t load = PTIM_GetLoadValue();
return (load - PTIM_GetCurrentValue());
}
// Get OS Tick overflow status.
uint32_t OS_Tick_GetOverflow (void) {
return (PTIM->ISR & 1);
}
#endif // PTIM
``` | /content/code_sandbox/CMSIS/RTOS2/Source/os_tick_ptim.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 964 |
```c
/**************************************************************************//**
* @file os_tick_gtim.c
* @brief CMSIS OS Tick implementation for Generic Timer
* @version V1.0.1
* @date 24. November 2017
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "os_tick.h"
#include "irq_ctrl.h"
#include "RTE_Components.h"
#include CMSIS_device_header
#ifndef GTIM_IRQ_PRIORITY
#define GTIM_IRQ_PRIORITY 0xFFU
#endif
#ifndef GTIM_IRQ_NUM
#define GTIM_IRQ_NUM SecurePhyTimer_IRQn
#endif
// Timer interrupt pending flag
static uint8_t GTIM_PendIRQ;
// Timer tick frequency
static uint32_t GTIM_Clock;
// Timer load value
static uint32_t GTIM_Load;
// Setup OS Tick.
int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
uint32_t prio, bits;
if (freq == 0U) {
return (-1);
}
GTIM_PendIRQ = 0U;
// Get timer clock
#ifdef SCTR_BASE
GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20);
#else
// FVP REFCLK CNTControl 100MHz
GTIM_Clock = 100000000UL;
#endif
PL1_SetCounterFrequency(GTIM_Clock);
// Calculate load value
GTIM_Load = (GTIM_Clock / freq) - 1U;
// Disable Generic Timer and set load value
PL1_SetControl(0U);
PL1_SetLoadValue(GTIM_Load);
// Disable corresponding IRQ
IRQ_Disable(GTIM_IRQ_NUM);
IRQ_ClearPending(GTIM_IRQ_NUM);
// Determine number of implemented priority bits
IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU);
prio = IRQ_GetPriority(GTIM_IRQ_NUM);
// At least bits [7:4] must be implemented
if ((prio & 0xF0U) == 0U) {
return (-1);
}
for (bits = 0; bits < 4; bits++) {
if ((prio & 0x01) != 0) {
break;
}
prio >>= 1;
}
// Adjust configured priority to the number of implemented priority bits
prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL;
// Set Private Timer interrupt priority
IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U);
// Set edge-triggered IRQ
IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE);
// Register tick interrupt handler function
IRQ_SetHandler(GTIM_IRQ_NUM, handler);
// Enable corresponding interrupt
IRQ_Enable(GTIM_IRQ_NUM);
// Enable system counter and timer control
#ifdef SCTR_BASE
*(uint32_t*)SCTR_BASE |= 3U;
#endif
// Enable timer control
PL1_SetControl(1U);
return (0);
}
/// Enable OS Tick.
void OS_Tick_Enable (void) {
uint32_t ctrl;
// Set pending interrupt if flag set
if (GTIM_PendIRQ != 0U) {
GTIM_PendIRQ = 0U;
IRQ_SetPending (GTIM_IRQ_NUM);
}
// Start the Private Timer
ctrl = PL1_GetControl();
// Set bit: Timer enable
ctrl |= 1U;
PL1_SetControl(ctrl);
}
/// Disable OS Tick.
void OS_Tick_Disable (void) {
uint32_t ctrl;
// Stop the Private Timer
ctrl = PL1_GetControl();
// Clear bit: Timer enable
ctrl &= ~1U;
PL1_SetControl(ctrl);
// Remember pending interrupt flag
if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) {
IRQ_ClearPending(GTIM_IRQ_NUM);
GTIM_PendIRQ = 1U;
}
}
// Acknowledge OS Tick IRQ.
void OS_Tick_AcknowledgeIRQ (void) {
IRQ_ClearPending (GTIM_IRQ_NUM);
PL1_SetLoadValue(GTIM_Load);
}
// Get OS Tick IRQ number.
int32_t OS_Tick_GetIRQn (void) {
return (GTIM_IRQ_NUM);
}
// Get OS Tick clock.
uint32_t OS_Tick_GetClock (void) {
return (GTIM_Clock);
}
// Get OS Tick interval.
uint32_t OS_Tick_GetInterval (void) {
return (GTIM_Load + 1U);
}
// Get OS Tick count value.
uint32_t OS_Tick_GetCount (void) {
return (GTIM_Load - PL1_GetCurrentValue());
}
// Get OS Tick overflow status.
uint32_t OS_Tick_GetOverflow (void) {
CNTP_CTL_Type cntp_ctl;
cntp_ctl.w = PL1_GetControl();
return (cntp_ctl.b.ISTATUS);
}
``` | /content/code_sandbox/CMSIS/RTOS2/Source/os_tick_gtim.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,097 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 10. January 2017
* $Revision: V1.2
*
* Project: CMSIS-RTOS API V1
* Title: cmsis_os_v1.c V1 module file
*your_sha256_hash-----------*/
#include <string.h>
#include "cmsis_os.h"
#if (osCMSIS >= 0x20000U)
// Thread
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
if (thread_def == NULL) {
return (osThreadId)NULL;
}
return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
}
// Signals
#define SignalMask ((1U<<osFeature_Signals)-1U)
int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
uint32_t flags;
flags = osThreadFlagsSet(thread_id, (uint32_t)signals);
if ((flags & 0x80000000U) != 0U) {
return ((int32_t)0x80000000U);
}
return ((int32_t)(flags & ~((uint32_t)signals)));
}
int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
uint32_t flags;
if (thread_id != osThreadGetId()) {
return ((int32_t)0x80000000U);
}
flags = osThreadFlagsClear((uint32_t)signals);
if ((flags & 0x80000000U) != 0U) {
return ((int32_t)0x80000000U);
}
return ((int32_t)flags);
}
osEvent osSignalWait (int32_t signals, uint32_t millisec) {
osEvent event;
uint32_t flags;
if (signals != 0) {
flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);
} else {
flags = osThreadFlagsWait(SignalMask, osFlagsWaitAny, millisec);
}
if ((flags > 0U) && (flags < 0x80000000U)) {
event.status = osEventSignal;
event.value.signals = (int32_t)flags;
} else {
switch ((int32_t)flags) {
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
case osErrorParameter:
event.status = osErrorValue;
break;
default:
event.status = (osStatus)flags;
break;
}
}
return event;
}
// Timer
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
if (timer_def == NULL) {
return (osTimerId)NULL;
}
return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
}
// Mutex
osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
if (mutex_def == NULL) {
return (osMutexId)NULL;
}
return osMutexNew(mutex_def);
}
// Semaphore
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
if (semaphore_def == NULL) {
return (osSemaphoreId)NULL;
}
return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
}
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
osStatus_t status;
uint32_t count;
status = osSemaphoreAcquire(semaphore_id, millisec);
switch (status) {
case osOK:
count = osSemaphoreGetCount(semaphore_id);
return ((int32_t)count + 1);
case osErrorResource:
case osErrorTimeout:
return 0;
default:
break;
}
return -1;
}
#endif // Semaphore
// Memory Pool
#if (defined(osFeature_Pool) && (osFeature_Pool != 0))
osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
if (pool_def == NULL) {
return (osPoolId)NULL;
}
return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr)));
}
void *osPoolAlloc (osPoolId pool_id) {
return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
}
void *osPoolCAlloc (osPoolId pool_id) {
void *block;
uint32_t block_size;
block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
if (block_size == 0U) {
return NULL;
}
block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);
if (block != NULL) {
memset(block, 0, block_size);
}
return block;
}
osStatus osPoolFree (osPoolId pool_id, void *block) {
return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block);
}
#endif // Memory Pool
// Message Queue
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
(void)thread_id;
if (queue_def == NULL) {
return (osMessageQId)NULL;
}
return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr)));
}
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec);
}
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
osStatus_t status;
osEvent event;
uint32_t message;
status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec);
switch (status) {
case osOK:
event.status = osEventMessage;
event.value.v = message;
break;
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
default:
event.status = status;
break;
}
return event;
}
#endif // Message Queue
// Mail Queue
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))
typedef struct os_mail_queue_s {
osMemoryPoolId_t mp_id;
osMessageQueueId_t mq_id;
} os_mail_queue_t;
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
os_mail_queue_t *ptr;
(void)thread_id;
if (queue_def == NULL) {
return (osMailQId)NULL;
}
ptr = queue_def->mail;
if (ptr == NULL) {
return (osMailQId)NULL;
}
ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) {
if (ptr->mp_id != (osMemoryPoolId_t)NULL) {
osMemoryPoolDelete(ptr->mp_id);
}
if (ptr->mq_id != (osMessageQueueId_t)NULL) {
osMessageQueueDelete(ptr->mq_id);
}
return (osMailQId)NULL;
}
return (osMailQId)ptr;
}
void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return NULL;
}
return osMemoryPoolAlloc(ptr->mp_id, millisec);
}
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
void *block;
uint32_t block_size;
if (ptr == NULL) {
return NULL;
}
block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
if (block_size == 0U) {
return NULL;
}
block = osMemoryPoolAlloc(ptr->mp_id, millisec);
if (block != NULL) {
memset(block, 0, block_size);
}
return block;
}
osStatus osMailPut (osMailQId queue_id, const void *mail) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return osErrorParameter;
}
if (mail == NULL) {
return osErrorValue;
}
return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
}
osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
osStatus_t status;
osEvent event;
void *mail;
if (ptr == NULL) {
event.status = osErrorParameter;
return event;
}
status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
switch (status) {
case osOK:
event.status = osEventMail;
event.value.p = mail;
break;
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
default:
event.status = status;
break;
}
return event;
}
osStatus osMailFree (osMailQId queue_id, void *mail) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return osErrorParameter;
}
if (mail == NULL) {
return osErrorValue;
}
return osMemoryPoolFree(ptr->mp_id, mail);
}
#endif // Mail Queue
#endif // osCMSIS
``` | /content/code_sandbox/CMSIS/RTOS2/Template/cmsis_os1.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,433 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 18. June 2018
* $Revision: V2.1.3
*
* Project: CMSIS-RTOS API
* Title: cmsis_os.h template header file
*
* Version 0.02
* Initial Proposal Phase
* Version 0.03
* osKernelStart added, optional feature: main started as thread
* osSemaphores have standard behavior
* osTimerCreate does not start the timer, added osTimerStart
* osThreadPass is renamed to osThreadYield
* Version 1.01
* Support for C++ interface
* - const attribute removed from the osXxxxDef_t typedefs
* - const attribute added to the osXxxxDef macros
* Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
* Added: osKernelInitialize
* Version 1.02
* Control functions for short timeouts in microsecond resolution:
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
* Removed: osSignalGet
* Version 2.0.0
* OS objects creation without macros (dynamic creation and resource allocation):
* - added: osXxxxNew functions which replace osXxxxCreate
* - added: osXxxxAttr_t structures
* - deprecated: osXxxxCreate functions, osXxxxDef_t structures
* - deprecated: osXxxxDef and osXxxx macros
* osStatus codes simplified and renamed to osStatus_t
* osEvent return structure deprecated
* Kernel:
* - added: osKernelInfo_t and osKernelGetInfo
* - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
* - added: osKernelLock, osKernelUnlock
* - added: osKernelSuspend, osKernelResume
* - added: osKernelGetTickCount, osKernelGetTickFreq
* - renamed osKernelSysTick to osKernelGetSysTimerCount
* - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
* - deprecated osKernelSysTickMicroSec
* Thread:
* - extended number of thread priorities
* - renamed osPrioriry to osPrioriry_t
* - replaced osThreadCreate with osThreadNew
* - added: osThreadGetName
* - added: osThreadState_t and osThreadGetState
* - added: osThreadGetStackSize, osThreadGetStackSpace
* - added: osThreadSuspend, osThreadResume
* - added: osThreadJoin, osThreadDetach, osThreadExit
* - added: osThreadGetCount, osThreadEnumerate
* - added: Thread Flags (moved from Signals)
* Signals:
* - renamed osSignals to osThreadFlags (moved to Thread Flags)
* - changed return value of Set/Clear/Wait functions
* - Clear function limited to current running thread
* - extended Wait function (options)
* - added: osThreadFlagsGet
* Event Flags:
* - added new independent object for handling Event Flags
* Delay and Wait functions:
* - added: osDelayUntil
* - deprecated: osWait
* Timer:
* - replaced osTimerCreate with osTimerNew
* - added: osTimerGetName, osTimerIsRunning
* Mutex:
* - extended: attributes (Recursive, Priority Inherit, Robust)
* - replaced osMutexCreate with osMutexNew
* - renamed osMutexWait to osMutexAcquire
* - added: osMutexGetName, osMutexGetOwner
* Semaphore:
* - extended: maximum and initial token count
* - replaced osSemaphoreCreate with osSemaphoreNew
* - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
* - added: osSemaphoreGetName, osSemaphoreGetCount
* Memory Pool:
* - using osMemoryPool prefix instead of osPool
* - replaced osPoolCreate with osMemoryPoolNew
* - extended osMemoryPoolAlloc (timeout)
* - added: osMemoryPoolGetName
* - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
* - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
* - added: osMemoryPoolDelete
* - deprecated: osPoolCAlloc
* Message Queue:
* - extended: fixed size message instead of a single 32-bit value
* - using osMessageQueue prefix instead of osMessage
* - replaced osMessageCreate with osMessageQueueNew
* - updated: osMessageQueuePut, osMessageQueueGet
* - added: osMessageQueueGetName
* - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
* - added: osMessageQueueGetCount, osMessageQueueGetSpace
* - added: osMessageQueueReset, osMessageQueueDelete
* Mail Queue:
* - deprecated (superseded by extended Message Queue functionality)
* Version 2.1.0
* Support for critical and uncritical sections (nesting safe):
* - updated: osKernelLock, osKernelUnlock
* - added: osKernelRestoreLock
* Updated Thread and Event Flags:
* - changed flags parameter and return type from int32_t to uint32_t
* Version 2.1.1
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetTickCount, osKernelGetTickFreq
* Changed Kernel Tick type to uint32_t:
* - updated: osKernelGetTickCount, osDelayUntil
* Version 2.1.2
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetInfo, osKernelGetState
* Version 2.1.3
* Additional functions allowed to be called from Interrupt Service Routines:
* - osThreadGetId
*your_sha256_hash-----------*/
#ifndef CMSIS_OS_H_
#define CMSIS_OS_H_
/// \b osCMSIS identifies the CMSIS-RTOS API version.
#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0])
/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel.
#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string
/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features.
#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
#if (osCMSIS >= 0x20000U)
#include "cmsis_os2.h"
#else
#include <stdint.h>
#include <stddef.h>
#endif
#ifdef __cplusplus
extern "C"
{
#endif
// ==== Enumerations, structures, defines ====
/// Priority values.
#if (osCMSIS < 0x20000U)
typedef enum {
osPriorityIdle = -3, ///< Priority: idle (lowest)
osPriorityLow = -2, ///< Priority: low
osPriorityBelowNormal = -1, ///< Priority: below normal
osPriorityNormal = 0, ///< Priority: normal (default)
osPriorityAboveNormal = +1, ///< Priority: above normal
osPriorityHigh = +2, ///< Priority: high
osPriorityRealtime = +3, ///< Priority: realtime (highest)
osPriorityError = 0x84, ///< System cannot determine priority or illegal priority.
osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osPriority;
#else
#define osPriority osPriority_t
#endif
/// Entry point of a thread.
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
typedef void (*os_ptimer) (void const *argument);
/// Timer type.
#if (osCMSIS < 0x20000U)
typedef enum {
osTimerOnce = 0, ///< One-shot timer.
osTimerPeriodic = 1 ///< Repeating timer.
} os_timer_type;
#else
#define os_timer_type osTimerType_t
#endif
/// Timeout value.
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
/// Status code values returned by CMSIS-RTOS functions.
#if (osCMSIS < 0x20000U)
typedef enum {
osOK = 0, ///< Function completed; no error or event occurred.
osEventSignal = 0x08, ///< Function completed; signal event occurred.
osEventMessage = 0x10, ///< Function completed; message event occurred.
osEventMail = 0x20, ///< Function completed; mail event occurred.
osEventTimeout = 0x40, ///< Function completed; timeout occurred.
osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
osErrorResource = 0x81, ///< Resource not available: a specified resource was not available.
osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period.
osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object.
osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority.
osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
osErrorValue = 0x86, ///< Value of a parameter is out of range.
osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits.
osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osStatus;
#else
typedef int32_t osStatus;
#define osEventSignal (0x08)
#define osEventMessage (0x10)
#define osEventMail (0x20)
#define osEventTimeout (0x40)
#define osErrorOS osError
#define osErrorTimeoutResource osErrorTimeout
#define osErrorISRRecursive (-126)
#define osErrorValue (-127)
#define osErrorPriority (-128)
#endif
// >>> the following data type definitions may be adapted towards a specific RTOS
/// Thread ID identifies the thread.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef void *osThreadId;
#else
#define osThreadId osThreadId_t
#endif
/// Timer ID identifies the timer.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef void *osTimerId;
#else
#define osTimerId osTimerId_t
#endif
/// Mutex ID identifies the mutex.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef void *osMutexId;
#else
#define osMutexId osMutexId_t
#endif
/// Semaphore ID identifies the semaphore.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef void *osSemaphoreId;
#else
#define osSemaphoreId osSemaphoreId_t
#endif
/// Pool ID identifies the memory pool.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
typedef void *osPoolId;
/// Message ID identifies the message queue.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
typedef void *osMessageQId;
/// Mail ID identifies the mail queue.
/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS.
typedef void *osMailQId;
/// Thread Definition structure contains startup information of a thread.
/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osPriority tpriority; ///< initial thread priority
uint32_t instances; ///< maximum number of instances of that thread function
uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
} osThreadDef_t;
#else
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osThreadAttr_t attr; ///< thread attributes
} osThreadDef_t;
#endif
/// Timer Definition structure contains timer parameters.
/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
} osTimerDef_t;
#else
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
osTimerAttr_t attr; ///< timer attributes
} osTimerDef_t;
#endif
/// Mutex Definition structure contains setup information for a mutex.
/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_mutex_def {
uint32_t dummy; ///< dummy value
} osMutexDef_t;
#else
#define osMutexDef_t osMutexAttr_t
#endif
/// Semaphore Definition structure contains setup information for a semaphore.
/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_semaphore_def {
uint32_t dummy; ///< dummy value
} osSemaphoreDef_t;
#else
#define osSemaphoreDef_t osSemaphoreAttr_t
#endif
/// Definition structure for memory block allocation.
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
void *pool; ///< pointer to memory for pool
} osPoolDef_t;
#else
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
osMemoryPoolAttr_t attr; ///< memory pool attributes
} osPoolDef_t;
#endif
/// Definition structure for message queue.
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
void *pool; ///< memory array for messages
} osMessageQDef_t;
#else
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
osMessageQueueAttr_t attr; ///< message queue attributes
} osMessageQDef_t;
#endif
/// Definition structure for mail queue.
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
#if (osCMSIS < 0x20000U)
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for mail
} osMailQDef_t;
#else
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *mail; ///< pointer to mail
osMemoryPoolAttr_t mp_attr; ///< memory pool attributes
osMessageQueueAttr_t mq_attr; ///< message queue attributes
} osMailQDef_t;
#endif
/// Event structure contains detailed information about an event.
typedef struct {
osStatus status; ///< status code: event or error information
union {
uint32_t v; ///< message as 32-bit value
void *p; ///< message or mail as void pointer
int32_t signals; ///< signal flags
} value; ///< event value
union {
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
// ==== Kernel Management Functions ====
/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelInitialize (void);
#endif
/// Start the RTOS Kernel scheduler.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelStart (void);
#endif
/// Check if the RTOS kernel is already started.
/// \return 0 RTOS is not started, 1 RTOS is started.
#if (osCMSIS < 0x20000U)
int32_t osKernelRunning(void);
#endif
#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
/// Get the RTOS kernel system timer counter.
/// \return RTOS kernel system timer as 32-bit value
#if (osCMSIS < 0x20000U)
uint32_t osKernelSysTick (void);
#else
#define osKernelSysTick osKernelGetSysTimerCount
#endif
/// The RTOS kernel system timer frequency in Hz.
/// \note Reflects the system timer setting and is typically defined in a configuration file.
#if (osCMSIS < 0x20000U)
#define osKernelSysTickFrequency 100000000
#endif
/// Convert a microseconds value to a RTOS kernel system timer value.
/// \param microsec time value in microseconds.
/// \return time value normalized to the \ref osKernelSysTickFrequency
#if (osCMSIS < 0x20000U)
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
#else
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
#endif
#endif // System Timer available
// ==== Thread Management Functions ====
/// Create a Thread Definition with function, priority, and stack requirements.
/// \param name name of the thread function.
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
extern const osThreadDef_t os_thread_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osThreadDef(name, priority, instances, stacksz) \
const osThreadDef_t os_thread_def_##name = \
{ (name), (priority), (instances), (stacksz) }
#else
#define osThreadDef(name, priority, instances, stacksz) \
const osThreadDef_t os_thread_def_##name = \
{ (name), \
{ NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } }
#endif
#endif
/// Access a Thread definition.
/// \param name name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name) \
&os_thread_def_##name
/// Create a thread and add it to Active Threads and set it to state READY.
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
#if (osCMSIS < 0x20000U)
osThreadId osThreadGetId (void);
#endif
/// Change priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
#endif
/// Get current priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the specified thread.
#if (osCMSIS < 0x20000U)
osPriority osThreadGetPriority (osThreadId thread_id);
#endif
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadYield (void);
#endif
/// Terminate execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadTerminate (osThreadId thread_id);
#endif
// ==== Signal Management ====
/// Set the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that should be set.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
/// Clear the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event flag information or error code.
osEvent osSignalWait (int32_t signals, uint32_t millisec);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay).
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osDelay (uint32_t millisec);
#endif
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
osEvent osWait (uint32_t millisec);
#endif // Generic Wait available
// ==== Timer Management Functions ====
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
extern const osTimerDef_t os_timer_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osTimerDef(name, function) \
const osTimerDef_t os_timer_def_##name = { (function) }
#else
#define osTimerDef(name, function) \
const osTimerDef_t os_timer_def_##name = \
{ (function), { NULL, 0U, NULL, 0U } }
#endif
#endif
/// Access a Timer definition.
/// \param name name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name
/// Create and Initialize a timer.
/// \param[in] timer_def timer object referenced with \ref osTimer.
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
#endif
/// Stop a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerStop (osTimerId timer_id);
#endif
/// Delete a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerDelete (osTimerId timer_id);
#endif
// ==== Mutex Management Functions ====
/// Define a Mutex.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
extern const osMutexDef_t os_mutex_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMutexDef(name) \
const osMutexDef_t os_mutex_def_##name = { 0 }
#else
#define osMutexDef(name) \
const osMutexDef_t os_mutex_def_##name = \
{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U }
#endif
#endif
/// Access a Mutex definition.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name) \
&os_mutex_def_##name
/// Create and Initialize a Mutex object.
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
/// Wait until a Mutex becomes available.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
#else
#define osMutexWait osMutexAcquire
#endif
/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexRelease (osMutexId mutex_id);
#endif
/// Delete a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexDelete (osMutexId mutex_id);
#endif
// ==== Semaphore Management Functions ====
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
/// Define a Semaphore object.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
extern const osSemaphoreDef_t os_semaphore_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osSemaphoreDef(name) \
const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
#else
#define osSemaphoreDef(name) \
const osSemaphoreDef_t os_semaphore_def_##name = \
{ NULL, 0U, NULL, 0U }
#endif
#endif
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name) \
&os_semaphore_def_##name
/// Create and Initialize a Semaphore object.
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in] count maximum and initial number of available tokens.
/// \return semaphore ID for reference by other functions or NULL in case of error.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
/// Wait until a Semaphore token becomes available.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
/// Release a Semaphore token.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
#endif
/// Delete a Semaphore object.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
#endif
#endif // Semaphore available
// ==== Memory Pool Management Functions ====
#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
/// \brief Define a Memory Pool.
/// \param name name of the memory pool.
/// \param no maximum number of blocks (objects) in the memory pool.
/// \param type data type of a single block (object).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
extern const osPoolDef_t os_pool_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osPoolDef(name, no, type) \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), NULL }
#else
#define osPoolDef(name, no, type) \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } }
#endif
#endif
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name
/// Create and Initialize a Memory Pool object.
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
/// Allocate a memory block from a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a Memory Pool and set memory block to zero.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolCAlloc (osPoolId pool_id);
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return status code that indicates the execution status of the function.
osStatus osPoolFree (osPoolId pool_id, void *block);
#endif // Memory Pool available
// ==== Message Queue Management Functions ====
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
/// \brief Create a Message Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
extern const osMessageQDef_t os_messageQ_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMessageQDef(name, queue_sz, type) \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), NULL }
#else
#define osMessageQDef(name, queue_sz, type) \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } }
#endif
#endif
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name
/// Create and Initialize a Message Queue object.
/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
/// Put a Message to a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] info message information.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
/// Get a Message from a Queue or timeout if Queue is empty.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
#endif // Message Queue available
// ==== Mail Queue Management Functions ====
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
/// \brief Create a Mail Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of mails in the queue.
/// \param type data type of a single mail element.
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
extern const osMailQDef_t os_mailQ_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMailQDef(name, queue_sz, type) \
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof(type), NULL }
#else
#define osMailQDef(name, queue_sz, type) \
static void *os_mail_p_##name[2]; \
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof(type), (&os_mail_p_##name), \
{ NULL, 0U, NULL, 0U, NULL, 0U }, \
{ NULL, 0U, NULL, 0U, NULL, 0U } }
#endif
#endif
/// \brief Access a Mail Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name) \
&os_mailQ_def_##name
/// Create and Initialize a Mail Queue object.
/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
/// Allocate a memory block for mail from a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
/// Put a Mail into a Queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory with mail to put into a queue.
/// \return status code that indicates the execution status of the function.
osStatus osMailPut (osMailQId queue_id, const void *mail);
/// Get a Mail from a Queue or timeout if Queue is empty.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// Free a memory block by returning it to a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queue available
#ifdef __cplusplus
}
#endif
#endif // CMSIS_OS_H_
``` | /content/code_sandbox/CMSIS/RTOS2/Template/cmsis_os.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 9,828 |
```c
/* your_sha256_hash----------
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* Name: main.c
* Purpose: RTX example program
*
*your_sha256_hash-----------*/
#include <stdio.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#include "cmsis_os2.h"
void app_main (void *argument);
void app_msg (void *argument);
typedef struct msg_s {
uint8_t cmd;
uint8_t len;
uint8_t data[8];
} msg_t;
static osMessageQueueId_t msgQueue;
static const osThreadAttr_t msgAttr = {
.stack_size = 400U
};
/*your_sha256_hash------------
* Application main thread
*your_sha256_hash-----------*/
void app_main (void *argument) {
(void)argument;
osStatus_t status;
uint32_t cnt = 0UL;
msg_t msg = {
.cmd = 1U,
.len = 4U,
.data = { 0U }
};
while (1) {
// Produce a new message and put it to the queue
++cnt;
*((uint32_t*)msg.data) = cnt;
status = osMessageQueuePut(msgQueue, &msg, 0U, osWaitForever);
if (status != osOK) {
printf("app_main: osMessageQueuePut failed.\n");
}
// Defer message creation
osDelay(osMessageQueueGetCount(msgQueue)*100U);
}
}
/*your_sha256_hash------------
* Application message receiver thread
*your_sha256_hash-----------*/
void app_msg (void *argument) {
(void)argument;
osStatus_t status;
uint32_t cnt;
msg_t msg;
while (1) {
// Defer message processing
osDelay(osMessageQueueGetSpace(msgQueue)*100U);
// Wait forever until a message could be received
status = osMessageQueueGet(msgQueue, &msg, NULL, osWaitForever);
if (status != osOK) {
printf("app_msg: osMessageQueueGet failed.\n");
} else {
if (msg.len == 4U) {
cnt = *((uint32_t*)msg.data);
}
printf("app_msg: received [cmd = %d, data = 0x%0X]\n", msg.cmd, cnt);
}
}
}
/*your_sha256_hash------------
* Main entry
*your_sha256_hash-----------*/
int main (void) {
// System Initialization
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
osThreadNew(app_msg, NULL, &msgAttr); // Create message receiver thread
// Create message queue for up to 10 messages of type msg_t
msgQueue = osMessageQueueNew(10, sizeof(msg_t), NULL);
osKernelStart(); // Start thread execution
for (;;) {}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 692 |
```c
/* your_sha256_hash----------
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* Name: Blinky.c
* Purpose: RTX example program
*
*your_sha256_hash-----------*/
#include <stdio.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "RTE_Components.h"
#include CMSIS_device_header
osThreadId_t tid_phaseA; /* Thread id of thread: phase_a */
osThreadId_t tid_phaseB; /* Thread id of thread: phase_b */
osThreadId_t tid_phaseC; /* Thread id of thread: phase_c */
osThreadId_t tid_phaseD; /* Thread id of thread: phase_d */
osThreadId_t tid_clock; /* Thread id of thread: clock */
struct phases_t {
int_fast8_t phaseA;
int_fast8_t phaseB;
int_fast8_t phaseC;
int_fast8_t phaseD;
} g_phases;
/*your_sha256_hash------------
* Switch LED on
*your_sha256_hash-----------*/
void Switch_On (unsigned char led) {
printf("LED On: #%d\n\r", led);
}
/*your_sha256_hash------------
* Switch LED off
*your_sha256_hash-----------*/
void Switch_Off (unsigned char led) {
printf("LED Off: #%d\n\r", led);
}
/*your_sha256_hash------------
* Function 'signal_func' called from multiple threads
*your_sha256_hash-----------*/
void signal_func (osThreadId_t tid) {
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
osDelay(500); /* delay 500ms */
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
osDelay(500); /* delay 500ms */
osThreadFlagsSet(tid, 0x0001); /* set signal to thread 'thread' */
osDelay(500); /* delay 500ms */
}
/*your_sha256_hash------------
* Thread 1 'phaseA': Phase A output
*your_sha256_hash-----------*/
void phaseA (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(0);
g_phases.phaseA = 1;
signal_func(tid_phaseB); /* call common signal function */
g_phases.phaseA = 0;
Switch_Off(0);
}
}
/*your_sha256_hash------------
* Thread 2 'phaseB': Phase B output
*your_sha256_hash-----------*/
void phaseB (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(1);
g_phases.phaseB = 1;
signal_func(tid_phaseC); /* call common signal function */
g_phases.phaseB = 0;
Switch_Off(1);
}
}
/*your_sha256_hash------------
* Thread 3 'phaseC': Phase C output
*your_sha256_hash-----------*/
void phaseC (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(2);
g_phases.phaseC = 1;
signal_func(tid_phaseD); /* call common signal function */
g_phases.phaseC = 0;
Switch_Off(2);
}
}
/*your_sha256_hash------------
* Thread 4 'phaseD': Phase D output
*your_sha256_hash-----------*/
void phaseD (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(3);
g_phases.phaseD = 1;
signal_func(tid_phaseA); /* call common signal function */
g_phases.phaseD = 0;
Switch_Off(3);
}
}
/*your_sha256_hash------------
* Thread 5 'clock': Signal Clock
*your_sha256_hash-----------*/
void clock (void *argument) {
for (;;) {
osThreadFlagsWait(0x0100, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0100 */
osDelay(80); /* delay 80ms */
}
}
/*your_sha256_hash------------
* Main: Initialize and start RTX Kernel
*your_sha256_hash-----------*/
void app_main (void *argument) {
tid_phaseA = osThreadNew(phaseA, NULL, NULL);
tid_phaseB = osThreadNew(phaseB, NULL, NULL);
tid_phaseC = osThreadNew(phaseC, NULL, NULL);
tid_phaseD = osThreadNew(phaseD, NULL, NULL);
tid_clock = osThreadNew(clock, NULL, NULL);
osThreadFlagsSet(tid_phaseA, 0x0001); /* set signal to phaseA thread */
osDelay(osWaitForever);
}
int main (void) {
// System Initialization
SystemCoreClockUpdate();
// ...
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
while(1);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,273 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX OS definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_OS_H_
#define RTX_OS_H_
#include <stdint.h>
#include <stddef.h>
#include "cmsis_os2.h"
#include "rtx_def.h"
#ifdef __cplusplus
extern "C"
{
#endif
/// Kernel Information
#define osRtxVersionAPI 20020000 ///< API version (2.2.0)
#define osRtxVersionKernel 50070000 ///< Kernel version (5.7.0)
#define osRtxKernelId "RTX V5.7.0" ///< Kernel identification string
// ==== Common definitions ====
/// Object Identifier definitions
#define osRtxIdInvalid 0x00U
#define osRtxIdThread 0xF1U
#define osRtxIdTimer 0xF2U
#define osRtxIdEventFlags 0xF3U
#define osRtxIdMutex 0xF5U
#define osRtxIdSemaphore 0xF6U
#define osRtxIdMemoryPool 0xF7U
#define osRtxIdMessage 0xF9U
#define osRtxIdMessageQueue 0xFAU
/// Object Flags definitions
#define osRtxFlagSystemObject 0x01U
#define osRtxFlagSystemMemory 0x02U
/// Object Attribute Class definitions
#define osRtxAttrClass_Pos 4U
#define osRtxAttrClass_Msk 0xF0U
// ==== Kernel definitions ====
/// Kernel State definitions
#define osRtxKernelInactive ((uint8_t)osKernelInactive)
#define osRtxKernelReady ((uint8_t)osKernelReady)
#define osRtxKernelRunning ((uint8_t)osKernelRunning)
#define osRtxKernelLocked ((uint8_t)osKernelLocked)
#define osRtxKernelSuspended ((uint8_t)osKernelSuspended)
/// Kernel Protect definitions
#define osRtxKernelProtectPrivileged 0x01U
#define osRtxKernelProtectClass_Pos 4U
#define osRtxKernelProtectClass_Msk 0xF0U
// ==== Thread definitions ====
/// Thread State definitions (extending osThreadState)
#define osRtxThreadStateMask 0x0FU
#define osRtxThreadInactive ((uint8_t)osThreadInactive)
#define osRtxThreadReady ((uint8_t)osThreadReady)
#define osRtxThreadRunning ((uint8_t)osThreadRunning)
#define osRtxThreadBlocked ((uint8_t)osThreadBlocked)
#define osRtxThreadTerminated ((uint8_t)osThreadTerminated)
#define osRtxThreadWaitingDelay ((uint8_t)(osRtxThreadBlocked | 0x10U))
#define osRtxThreadWaitingJoin ((uint8_t)(osRtxThreadBlocked | 0x20U))
#define osRtxThreadWaitingThreadFlags ((uint8_t)(osRtxThreadBlocked | 0x30U))
#define osRtxThreadWaitingEventFlags ((uint8_t)(osRtxThreadBlocked | 0x40U))
#define osRtxThreadWaitingMutex ((uint8_t)(osRtxThreadBlocked | 0x50U))
#define osRtxThreadWaitingSemaphore ((uint8_t)(osRtxThreadBlocked | 0x60U))
#define osRtxThreadWaitingMemoryPool ((uint8_t)(osRtxThreadBlocked | 0x70U))
#define osRtxThreadWaitingMessageGet ((uint8_t)(osRtxThreadBlocked | 0x80U))
#define osRtxThreadWaitingMessagePut ((uint8_t)(osRtxThreadBlocked | 0x90U))
/// Thread Flags definitions
#define osRtxThreadFlagDefStack 0x10U ///< Default Stack flag
/// Stack Marker definitions
#define osRtxStackMagicWord 0xE25A2EA5U ///< Stack Magic Word (Stack Base)
#define osRtxStackFillPattern 0xCCCCCCCCU ///< Stack Fill Pattern
/// Thread Control Block
typedef struct osRtxThread_s {
uint8_t id; ///< Object Identifier
uint8_t state; ///< Object State
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
struct osRtxThread_s *thread_next; ///< Link pointer to next Thread in Object list
struct osRtxThread_s *thread_prev; ///< Link pointer to previous Thread in Object list
struct osRtxThread_s *delay_next; ///< Link pointer to next Thread in Delay list
struct osRtxThread_s *delay_prev; ///< Link pointer to previous Thread in Delay list
struct osRtxThread_s *thread_join; ///< Thread waiting to Join
uint32_t delay; ///< Delay Time/Round Robin Time Tick
int8_t priority; ///< Thread Priority
int8_t priority_base; ///< Base Priority
uint8_t stack_frame; ///< Stack Frame (EXC_RETURN[7..0])
uint8_t flags_options; ///< Thread/Event Flags Options
uint32_t wait_flags; ///< Waiting Thread/Event Flags
uint32_t thread_flags; ///< Thread Flags
struct osRtxMutex_s *mutex_list; ///< Link pointer to list of owned Mutexes
void *stack_mem; ///< Stack Memory
uint32_t stack_size; ///< Stack Size
uint32_t sp; ///< Current Stack Pointer
uint32_t thread_addr; ///< Thread entry address
uint32_t tz_memory; ///< TrustZone Memory Identifier
uint8_t zone; ///< Thread Zone
uint8_t reserved[3];
struct osRtxThread_s *wdog_next; ///< Link pointer to next Thread in Watchdog list
uint32_t wdog_tick; ///< Watchdog tick counter
} osRtxThread_t;
// ==== Timer definitions ====
/// Timer State definitions
#define osRtxTimerInactive 0x00U ///< Timer Inactive
#define osRtxTimerStopped 0x01U ///< Timer Stopped
#define osRtxTimerRunning 0x02U ///< Timer Running
/// Timer attribute definitions
#define osRtxTimerPeriodic 0x01U ///< Timer Periodic mode
/// Timer Function Information
typedef struct {
osTimerFunc_t func; ///< Function Pointer
void *arg; ///< Function Argument
} osRtxTimerFinfo_t;
/// Timer Control Block
typedef struct osRtxTimer_s {
uint8_t id; ///< Object Identifier
uint8_t state; ///< Object State
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
struct osRtxTimer_s *prev; ///< Pointer to previous active Timer
struct osRtxTimer_s *next; ///< Pointer to next active Timer
uint32_t tick; ///< Timer current Tick
uint32_t load; ///< Timer Load value
osRtxTimerFinfo_t finfo; ///< Timer Function Info
} osRtxTimer_t;
// ==== Event Flags definitions ====
/// Event Flags Control Block
typedef struct {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Waiting Threads List
uint32_t event_flags; ///< Event Flags
} osRtxEventFlags_t;
// ==== Mutex definitions ====
/// Mutex Control Block
typedef struct osRtxMutex_s {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Waiting Threads List
osRtxThread_t *owner_thread; ///< Owner Thread
struct osRtxMutex_s *owner_prev; ///< Pointer to previous owned Mutex
struct osRtxMutex_s *owner_next; ///< Pointer to next owned Mutex
uint8_t lock; ///< Lock counter
uint8_t padding[3];
} osRtxMutex_t;
// ==== Semaphore definitions ====
/// Semaphore Control Block
typedef struct {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Waiting Threads List
uint16_t tokens; ///< Current number of tokens
uint16_t max_tokens; ///< Maximum number of tokens
} osRtxSemaphore_t;
// ==== Memory Pool definitions ====
/// Memory Pool Information
typedef struct {
uint32_t max_blocks; ///< Maximum number of Blocks
uint32_t used_blocks; ///< Number of used Blocks
uint32_t block_size; ///< Block Size
void *block_base; ///< Block Memory Base Address
void *block_lim; ///< Block Memory Limit Address
void *block_free; ///< First free Block Address
} osRtxMpInfo_t;
/// Memory Pool Control Block
typedef struct {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Waiting Threads List
osRtxMpInfo_t mp_info; ///< Memory Pool Info
} osRtxMemoryPool_t;
// ==== Message Queue definitions ====
/// Message Control Block
typedef struct osRtxMessage_s {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t priority; ///< Message Priority
struct osRtxMessage_s *prev; ///< Pointer to previous Message
struct osRtxMessage_s *next; ///< Pointer to next Message
} osRtxMessage_t;
/// Message Queue Control Block
typedef struct {
uint8_t id; ///< Object Identifier
uint8_t reserved_state; ///< Object State (not used)
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Waiting Threads List
osRtxMpInfo_t mp_info; ///< Memory Pool Info
uint32_t msg_size; ///< Message Size
uint32_t msg_count; ///< Number of queued Messages
osRtxMessage_t *msg_first; ///< Pointer to first Message
osRtxMessage_t *msg_last; ///< Pointer to last Message
} osRtxMessageQueue_t;
// ==== Generic Object definitions ====
/// Generic Object Control Block
typedef struct {
uint8_t id; ///< Object Identifier
uint8_t state; ///< Object State
uint8_t flags; ///< Object Flags
uint8_t attr; ///< Object Attributes
const char *name; ///< Object Name
osRtxThread_t *thread_list; ///< Threads List
} osRtxObject_t;
// ==== OS Runtime Information definitions ====
/// OS Runtime Information structure
typedef struct {
const char *os_id; ///< OS Identification
uint32_t version; ///< OS Version
struct { ///< Kernel Info
uint8_t state; ///< State
volatile uint8_t blocked; ///< Blocked
uint8_t pendSV; ///< Pending SV
uint8_t protect; ///< Protect options
uint32_t tick; ///< Tick counter
} kernel;
int32_t tick_irqn; ///< Tick Timer IRQ Number
struct { ///< Thread Info
struct { ///< Thread Run Info
osRtxThread_t *curr; ///< Current running Thread
osRtxThread_t *next; ///< Next Thread to Run
} run;
osRtxObject_t ready; ///< Ready List Object
osRtxThread_t *idle; ///< Idle Thread
osRtxThread_t *delay_list; ///< Delay List
osRtxThread_t *wait_list; ///< Wait List (no Timeout)
osRtxThread_t *terminate_list; ///< Terminate Thread List
osRtxThread_t *wdog_list; ///< Watchdog List
struct { ///< Thread Round Robin Info
osRtxThread_t *thread; ///< Round Robin Thread
uint32_t timeout; ///< Round Robin Timeout
} robin;
} thread;
struct { ///< Timer Info
osRtxTimer_t *list; ///< Active Timer List
osRtxThread_t *thread; ///< Timer Thread
osRtxMessageQueue_t *mq; ///< Timer Message Queue
void (*tick)(void); ///< Timer Tick Function
} timer;
struct { ///< ISR Post Processing Queue
uint16_t max; ///< Maximum Items
uint16_t cnt; ///< Item Count
uint16_t in; ///< Incoming Item Index
uint16_t out; ///< Outgoing Item Index
void **data; ///< Queue Data
} isr_queue;
struct { ///< ISR Post Processing functions
void (*thread)(osRtxThread_t*); ///< Thread Post Processing function
void (*event_flags)(osRtxEventFlags_t*); ///< Event Flags Post Processing function
void (*semaphore)(osRtxSemaphore_t*); ///< Semaphore Post Processing function
void (*memory_pool)(osRtxMemoryPool_t*); ///< Memory Pool Post Processing function
void (*message)(osRtxMessage_t*); ///< Message Post Processing function
} post_process;
struct { ///< Memory Pools (Variable Block Size)
void *stack; ///< Stack Memory
void *mp_data; ///< Memory Pool Data Memory
void *mq_data; ///< Message Queue Data Memory
void *common; ///< Common Memory
} mem;
struct { ///< Memory Pools (Fixed Block Size)
osRtxMpInfo_t *stack; ///< Stack for Threads
osRtxMpInfo_t *thread; ///< Thread Control Blocks
osRtxMpInfo_t *timer; ///< Timer Control Blocks
osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks
osRtxMpInfo_t *mutex; ///< Mutex Control Blocks
osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks
osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks
osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks
} mpi;
} osRtxInfo_t;
extern osRtxInfo_t osRtxInfo; ///< OS Runtime Information
/// OS Runtime Object Memory Usage structure
typedef struct {
uint32_t cnt_alloc; ///< Counter for alloc
uint32_t cnt_free; ///< Counter for free
uint32_t max_used; ///< Maximum used
} osRtxObjectMemUsage_t;
/// OS Runtime Object Memory Usage variables
extern osRtxObjectMemUsage_t osRtxThreadMemUsage;
extern osRtxObjectMemUsage_t osRtxTimerMemUsage;
extern osRtxObjectMemUsage_t osRtxEventFlagsMemUsage;
extern osRtxObjectMemUsage_t osRtxMutexMemUsage;
extern osRtxObjectMemUsage_t osRtxSemaphoreMemUsage;
extern osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage;
extern osRtxObjectMemUsage_t osRtxMessageQueueMemUsage;
// ==== OS API definitions ====
// Object Limits definitions
#define osRtxThreadFlagsLimit 31U ///< number of Thread Flags available per thread
#define osRtxEventFlagsLimit 31U ///< number of Event Flags available per object
#define osRtxMutexLockLimit 255U ///< maximum number of recursive mutex locks
#define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore
// Control Block sizes
#define osRtxThreadCbSize sizeof(osRtxThread_t)
#define osRtxTimerCbSize sizeof(osRtxTimer_t)
#define osRtxEventFlagsCbSize sizeof(osRtxEventFlags_t)
#define osRtxMutexCbSize sizeof(osRtxMutex_t)
#define osRtxSemaphoreCbSize sizeof(osRtxSemaphore_t)
#define osRtxMemoryPoolCbSize sizeof(osRtxMemoryPool_t)
#define osRtxMessageQueueCbSize sizeof(osRtxMessageQueue_t)
/// Memory size in bytes for Memory Pool storage.
/// \param block_count maximum number of memory blocks in memory pool.
/// \param block_size memory block size in bytes.
#define osRtxMemoryPoolMemSize(block_count, block_size) \
(4*(block_count)*(((block_size)+3)/4))
/// Memory size in bytes for Message Queue storage.
/// \param msg_count maximum number of messages in queue.
/// \param msg_size maximum message size in bytes.
#define osRtxMessageQueueMemSize(msg_count, msg_size) \
(4*(msg_count)*(3+(((msg_size)+3)/4)))
// ==== OS External Functions ====
// OS Error Codes
#define osRtxErrorStackUnderflow 1U ///< \deprecated Superseded by \ref osRtxErrorStackOverflow.
#define osRtxErrorStackOverflow 1U ///< Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks.
#define osRtxErrorISRQueueOverflow 2U ///< ISR Queue overflow detected when inserting object.
#define osRtxErrorTimerQueueOverflow 3U ///< User Timer Callback Queue overflow detected for timer.
#define osRtxErrorClibSpace 4U ///< Standard C/C++ library libspace not available: increase \c OS_THREAD_LIBSPACE_NUM.
#define osRtxErrorClibMutex 5U ///< Standard C/C++ library mutex initialization failed.
#define osRtxErrorSVC 6U ///< Invalid SVC function called.
/// OS Error Callback function
extern uint32_t osRtxErrorNotify (uint32_t code, void *object_id);
extern uint32_t osRtxKernelErrorNotify (uint32_t code, void *object_id);
/// OS Idle Thread
extern void osRtxIdleThread (void *argument);
/// OS Exception handlers
extern void SVC_Handler (void);
extern void PendSV_Handler (void);
extern void SysTick_Handler (void);
// ==== OS External Configuration ====
/// OS Configuration flags
#define osRtxConfigPrivilegedMode (1UL<<0) ///< Threads in Privileged mode
#define osRtxConfigStackCheck (1UL<<1) ///< Stack overrun checking
#define osRtxConfigStackWatermark (1UL<<2) ///< Stack usage Watermark
#define osRtxConfigSafetyFeatures (1UL<<3) ///< Safety features enabled
#define osRtxConfigSafetyClass (1UL<<4) ///< Safety Class feature enabled
#define osRtxConfigExecutionZone (1UL<<5) ///< Execution Zone enabled
#define osRtxConfigThreadWatchdog (1UL<<6) ///< Thread Watchdog enabled
#define osRtxConfigObjPtrCheck (1UL<<7) ///< Object Pointer Checking enabled
#define osRtxConfigSVCPtrCheck (1UL<<8) ///< SVC Pointer Checking enabled
/// OS Configuration structure
typedef struct {
uint32_t flags; ///< OS Configuration Flags
uint32_t tick_freq; ///< Kernel Tick Frequency
uint32_t robin_timeout; ///< Round Robin Timeout Tick
struct { ///< ISR Post Processing Queue
void **data; ///< Queue Data
uint16_t max; ///< Maximum Items
uint16_t padding;
} isr_queue;
struct { ///< Memory Pools (Variable Block Size)
void *stack_addr; ///< Stack Memory Address
uint32_t stack_size; ///< Stack Memory Size
void *mp_data_addr; ///< Memory Pool Memory Address
uint32_t mp_data_size; ///< Memory Pool Memory Size
void *mq_data_addr; ///< Message Queue Data Memory Address
uint32_t mq_data_size; ///< Message Queue Data Memory Size
void *common_addr; ///< Common Memory Address
uint32_t common_size; ///< Common Memory Size
} mem;
struct { ///< Memory Pools (Fixed Block Size)
osRtxMpInfo_t *stack; ///< Stack for Threads
osRtxMpInfo_t *thread; ///< Thread Control Blocks
osRtxMpInfo_t *timer; ///< Timer Control Blocks
osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks
osRtxMpInfo_t *mutex; ///< Mutex Control Blocks
osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks
osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks
osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks
} mpi;
uint32_t thread_stack_size; ///< Default Thread Stack Size
const
osThreadAttr_t *idle_thread_attr; ///< Idle Thread Attributes
const
osThreadAttr_t *timer_thread_attr; ///< Timer Thread Attributes
void (*timer_thread)(void *); ///< Timer Thread Function
int32_t (*timer_setup)(void); ///< Timer Setup Function
const
osMessageQueueAttr_t *timer_mq_attr; ///< Timer Message Queue Attributes
uint32_t timer_mq_mcnt; ///< Timer Message Queue maximum Messages
} osRtxConfig_t;
extern const osRtxConfig_t osRtxConfig; ///< OS Configuration
#ifdef __cplusplus
}
#endif
#endif // RTX_OS_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Include/rtx_os.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,230 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX derived definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_DEF_H_
#define RTX_DEF_H_
#ifdef _RTE_
#include "RTE_Components.h"
#endif
#include "RTX_Config.h"
#if (defined(OS_SAFETY_FEATURES) && (OS_SAFETY_FEATURES != 0))
#define RTX_SAFETY_FEATURES
#if (defined(OS_SAFETY_CLASS) && (OS_SAFETY_CLASS != 0))
#define RTX_SAFETY_CLASS
#endif
#if (defined(OS_EXECUTION_ZONE) && (OS_EXECUTION_ZONE != 0))
#define RTX_EXECUTION_ZONE
#endif
#if (defined(OS_THREAD_WATCHDOG) && (OS_THREAD_WATCHDOG != 0))
#define RTX_THREAD_WATCHDOG
#endif
#if (defined(OS_OBJ_PTR_CHECK) && (OS_OBJ_PTR_CHECK != 0))
#define RTX_OBJ_PTR_CHECK
#endif
#if (defined(OS_SVC_PTR_CHECK) && (OS_SVC_PTR_CHECK != 0))
#define RTX_SVC_PTR_CHECK
#endif
#endif
#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))
#define RTX_OBJ_MEM_USAGE
#endif
#if (defined(OS_STACK_CHECK) && (OS_STACK_CHECK != 0))
#define RTX_STACK_CHECK
#endif
#if (defined(OS_TZ_CONTEXT) && (OS_TZ_CONTEXT != 0))
#define RTX_TZ_CONTEXT
#endif
#ifndef DOMAIN_NS
#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
#define DOMAIN_NS 1
#else
#define DOMAIN_NS 0
#endif
#endif
#endif // RTX_DEF_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Include/rtx_def.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 447 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Exception handlers (C functions)
*
* your_sha256_hash-------------
*/
#include "RTE_Components.h"
#include CMSIS_device_header
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal
#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal
#define FSR_DEBUG_EVENT 0x02 //internal
#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
#define FSR_LOCKDOWN 0x14 //internal
#define FSR_COPROCESSOR_ABORT 0x1a //internal
#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
uint32_t FS = (DFSR & (1U << 10U)) >> 6U | (DFSR & 0x0FU); //Store Fault Status
(void)DFAR;
(void)LR;
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
case FSR_INSTRUCTION_CACHE_MAINTENANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISSION_FAULT_FIRST:
case FSR_PERMISSION_FAULT_SECOND:
case FSR_DEBUG_EVENT:
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
default:
while(1);
}
}
void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
uint32_t FS = (IFSR & (1U << 10U)) >> 6U | (IFSR & 0x0FU); //Store Fault Status
(void)IFAR;
(void)LR;
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in IFAR is invalid for some fault statuses.
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISSION_FAULT_FIRST:
case FSR_PERMISSION_FAULT_SECOND:
case FSR_DEBUG_EVENT: //IFAR invalid
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
default:
while(1);
}
}
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const uint32_t THUMB = 2U;
const uint32_t ARM = 4U;
(void)LR;
//Lazy VFP/NEON initialisation and switching
// (Arm Architecture Reference Manual section A7.5) VFP data processing instruction?
// (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction?
// (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction?
// (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction?
if ((state == ARM && ((opcode & 0x0C000000U) >> 26U == 0x03U)) ||
(state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) {
if (((opcode & 0x00000E00U) >> 9U) == 5U) {
__FPU_Enable();
return state;
}
}
// (Arm Architecture Reference Manual section A7.4) NEON data processing instruction?
if ((state == ARM && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) ||
(state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) ||
// (Arm Architecture Reference Manual section A7.7) NEON load/store instruction?
(state == ARM && ((opcode >> 24U) == 0xF4U)) ||
(state == THUMB && ((opcode >> 24U) == 0xF9U))) {
__FPU_Enable();
return state;
}
//Add code here for other Undef cases
while(1);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Config/handlers.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,688 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.2.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* your_sha256_hash-------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackOverflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
case osRtxErrorSVC:
// Invalid SVC function called (function=object_id)
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Config/RTX_Config.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 369 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.6.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 32768
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <e>Safety features (Source variant only)
// <i> Enables FuSa related features.
// <i> Requires RTX Source variant.
// <i> Enables:
// <i> - selected features from this group
// <i> - Thread functions: osThreadProtectPrivileged
#ifndef OS_SAFETY_FEATURES
#define OS_SAFETY_FEATURES 0
#endif
// <q>Safety Class
// <i> Threads assigned to lower classes cannot modify higher class threads.
// <i> Enables:
// <i> - Object attributes: osSafetyClass
// <i> - Kernel functions: osKernelProtect, osKernelDestroyClass
// <i> - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass
#ifndef OS_SAFETY_CLASS
#define OS_SAFETY_CLASS 1
#endif
// <q>MPU Protected Zone
// <i> Access protection via MPU (Spatial isolation).
// <i> Enables:
// <i> - Thread attributes: osThreadZone
// <i> - Thread functions: osThreadGetZone, osThreadTerminateZone
// <i> - Zone Management: osZoneSetup_Callback
#ifndef OS_EXECUTION_ZONE
#define OS_EXECUTION_ZONE 1
#endif
// <q>Thread Watchdog
// <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).
// <i> Enables:
// <i> - Thread functions: osThreadFeedWatchdog
// <i> - Handler functions: osWatchdogAlarm_Handler
#ifndef OS_THREAD_WATCHDOG
#define OS_THREAD_WATCHDOG 1
#endif
// <q>Object Pointer checking
// <i> Check object pointer alignment and memory region.
#ifndef OS_OBJ_PTR_CHECK
#define OS_OBJ_PTR_CHECK 0
#endif
// <q>SVC Function Pointer checking
// <i> Check SVC function pointer alignment and memory region.
// <i> User needs to define a linker execution region RTX_SVC_VENEERS
// <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)
#ifndef OS_SVC_PTR_CHECK
#define OS_SVC_PTR_CHECK 0
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 3072
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <o>Idle Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_CLASS
#define OS_IDLE_THREAD_CLASS 0
#endif
// <o>Idle Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_ZONE
#define OS_IDLE_THREAD_ZONE 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Default Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Unprivileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 0
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_CLASS
#define OS_TIMER_THREAD_CLASS 0
#endif
// <o>Timer Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_ZONE
#define OS_TIMER_THREAD_ZONE 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x81U
#endif
// <e.7>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x81U
#endif
// <e.7>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x85U
#endif
// <e.7>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x81U
#endif
// <e.7>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x81U
#endif
// <e.7>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x81U
#endif
// <e.7>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x81U
#endif
// <e.7>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x81U
#endif
// <e.7>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
#endif
// <e.7>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x81U
#endif
// <e.7>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Config/RTX_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,012 |
```shell
#!/bin/bash
VERSION=5.5.5
if [ -z "$JENKINS_FAMILY_ENV" ]; then
ARTIFACTORY_URL=path_to_url
else
ARTIFACTORY_URL=path_to_url
fi
if [ -z "$ARTIFACTORY_API_KEY" ]; then
echo "Please set your Artifactory in ARTIFACTORY_API_KEY"
echo ""
echo "1. Browse to $(dirname $(dirname $ARTIFACTORY_URL))/ui/admin/artifactory/user_profile"
echo "2. Copy the API Key"
echo "3. Add 'export ARTIFACTORY_API_KEY=\"<API Key>\"' to ~/.bashrc"
exit 1
fi
set -o pipefail
function usage {
echo "$(basename $0) [-h|--help] [-f|--force]"
echo ""
echo "Arguments:"
echo " -h|--help Print this usage message and exit."
echo " -f|--force Force (re)download."
echo ""
echo "Environment:"
echo " curl"
echo " sha256sum"
echo ""
}
POSITIONAL=()
while [[ $# -gt 0 ]]
do
key="$1"
case $key in
'-h'|'--help')
usage
exit 1
;;
'-f'|'--force')
FORCE=1
;;
*) # unknown option
POSITIONAL+=("$1") # save it in an array for later
;;
esac
shift # past argument
done
set -- "${POSITIONAL[@]}" # restore positional parameters
pushd $(dirname $0) > /dev/null
ARCHIVE_NAME="RTX5-${VERSION}.zip"
ARCHIVE_URL="${ARTIFACTORY_URL}/CMSIS_5/Libraries/${ARCHIVE_NAME}"
echo "Fetching ${ARCHIVE_URL}..."
if [[ $FORCE == 1 ]]; then
rm ${ARCHIVE_NAME}
fi
if [[ -f ${ARCHIVE_NAME} ]]; then
sha256sum=$(curl -s -I -H "X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}" "${ARCHIVE_URL}" | grep "X-Checksum-Sha256" | cut -d" " -f2)
if echo "${sha256sum} *${ARCHIVE_NAME}" | sha256sum -c --status; then
echo "Already up-to-date"
else
rm ${ARCHIVE_NAME}
fi
fi
if [[ ! -f ${ARCHIVE_NAME} ]]; then
curl -C - -H "X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}" -O "${ARCHIVE_URL}"
fi
unzip -u ${ARCHIVE_NAME}
exit 0
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Library/fetch_libs.sh | shell | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 597 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 10. January 2017
* $Revision: V1.2
*
* Project: CMSIS-RTOS API V1
* Title: cmsis_os_v1.c V1 module file
*your_sha256_hash-----------*/
#include <string.h>
#include "cmsis_os.h"
#if (osCMSIS >= 0x20000U) && !defined(os1_Disable)
// Thread
#if !defined(os1_Disable_Thread)
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
if (thread_def == NULL) {
return NULL;
}
return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
}
#endif
// Signals
#if !defined(os1_Disable_Signal)
#define SignalMask ((1U<<osFeature_Signals)-1U)
int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
uint32_t flags;
flags = osThreadFlagsSet(thread_id, (uint32_t)signals);
if ((flags & 0x80000000U) != 0U) {
return ((int32_t)0x80000000U);
}
return ((int32_t)(flags & ~((uint32_t)signals)));
}
int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
uint32_t flags;
if (thread_id != osThreadGetId()) {
return ((int32_t)0x80000000U);
}
flags = osThreadFlagsClear((uint32_t)signals);
if ((flags & 0x80000000U) != 0U) {
return ((int32_t)0x80000000U);
}
return ((int32_t)flags);
}
os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
osEvent event;
uint32_t flags;
if (signals != 0) {
flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);
} else {
flags = osThreadFlagsWait(SignalMask, osFlagsWaitAny, millisec);
}
if ((flags > 0U) && (flags < 0x80000000U)) {
event.status = osEventSignal;
event.value.signals = (int32_t)flags;
} else {
switch ((int32_t)flags) {
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
case osErrorParameter:
event.status = osErrorValue;
break;
default:
event.status = (osStatus)flags;
break;
}
}
return event;
}
#endif // Signal
// Timer
#if !defined(os1_Disable_Timer)
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
if (timer_def == NULL) {
return NULL;
}
return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
}
#endif
// Mutex
#if !defined(os1_Disable_Mutex)
osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
if (mutex_def == NULL) {
return NULL;
}
return osMutexNew(mutex_def);
}
#endif
// Semaphore
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) && !defined(os1_Disable_Semaphore)
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
if (semaphore_def == NULL) {
return NULL;
}
return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
}
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
osStatus_t status;
uint32_t count;
status = osSemaphoreAcquire(semaphore_id, millisec);
switch (status) {
case osOK:
count = osSemaphoreGetCount(semaphore_id);
return ((int32_t)count + 1);
case osErrorResource:
case osErrorTimeout:
return 0;
default:
break;
}
return -1;
}
#endif // Semaphore
// Memory Pool
#if (defined(osFeature_Pool) && (osFeature_Pool != 0))&& !defined(os1_Disable_Pool)
osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
if (pool_def == NULL) {
return NULL;
}
return osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr);
}
void *osPoolAlloc (osPoolId pool_id) {
return osMemoryPoolAlloc(pool_id, 0U);
}
void *osPoolCAlloc (osPoolId pool_id) {
void *block;
uint32_t block_size;
block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
if (block_size == 0U) {
return NULL;
}
block = osMemoryPoolAlloc(pool_id, 0U);
if (block != NULL) {
memset(block, 0, block_size);
}
return block;
}
osStatus osPoolFree (osPoolId pool_id, void *block) {
return osMemoryPoolFree(pool_id, block);
}
#endif // Memory Pool
// Message Queue
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) && !defined(os1_Disable_MessageQ)
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
(void)thread_id;
if (queue_def == NULL) {
return NULL;
}
return osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr);
}
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
return osMessageQueuePut(queue_id, &info, 0U, millisec);
}
os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
osStatus_t status;
osEvent event;
uint32_t message;
status = osMessageQueueGet(queue_id, &message, NULL, millisec);
switch (status) {
case osOK:
event.status = osEventMessage;
event.value.v = message;
break;
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
default:
event.status = status;
break;
}
return event;
}
#endif // Message Queue
// Mail Queue
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) && !defined(os1_Disable_MailQ)
typedef struct os_mail_queue_s {
osMemoryPoolId_t mp_id;
osMessageQueueId_t mq_id;
} os_mail_queue_t;
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
os_mail_queue_t *ptr;
(void)thread_id;
if (queue_def == NULL) {
return NULL;
}
ptr = queue_def->mail;
if (ptr == NULL) {
return NULL;
}
ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) {
if (ptr->mp_id != NULL) {
osMemoryPoolDelete(ptr->mp_id);
}
if (ptr->mq_id != NULL) {
osMessageQueueDelete(ptr->mq_id);
}
return NULL;
}
return ptr;
}
void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return NULL;
}
return osMemoryPoolAlloc(ptr->mp_id, millisec);
}
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
void *block;
uint32_t block_size;
if (ptr == NULL) {
return NULL;
}
block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
if (block_size == 0U) {
return NULL;
}
block = osMemoryPoolAlloc(ptr->mp_id, millisec);
if (block != NULL) {
memset(block, 0, block_size);
}
return block;
}
osStatus osMailPut (osMailQId queue_id, const void *mail) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return osErrorParameter;
}
if (mail == NULL) {
return osErrorValue;
}
return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
}
os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
osStatus_t status;
osEvent event;
void *mail;
if (ptr == NULL) {
event.status = osErrorParameter;
return event;
}
status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
switch (status) {
case osOK:
event.status = osEventMail;
event.value.p = mail;
break;
case osErrorResource:
event.status = osOK;
break;
case osErrorTimeout:
event.status = osEventTimeout;
break;
default:
event.status = status;
break;
}
return event;
}
osStatus osMailFree (osMailQId queue_id, void *mail) {
os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
if (ptr == NULL) {
return osErrorParameter;
}
if (mail == NULL) {
return osErrorValue;
}
return osMemoryPoolFree(ptr->mp_id, mail);
}
#endif // Mail Queue
#endif // osCMSIS
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Library/cmsis_os1.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,426 |
```python
#!/usr/bin/python3
# -*- coding: utf-8 -*-
from enum import Enum
from matrix_runner import main, matrix_axis, matrix_action, matrix_command
@matrix_axis("device", "d", "Device(s) to be considered.")
class Device(Enum):
CM0 = ('CM0', 'CM0_LE')
CM3 = ('CM3', 'CM3_LE')
CM4F = ('CM4F', 'CM4F_LE')
V8MB = ('V8MB', 'ARMv8MBL_LE')
V8MBN = ('V8MBN', 'ARMv8MBL_NS_LE')
V8MM = ('V8MM', 'ARMv8MML_LE')
V8MMF = ('V8MMF', 'ARMv8MML_SP_LE')
V8MMFN = ('V8MMFN', 'ARMv8MML_SP_NS_LE')
V8MMN = ('V8MMN', 'ARMv8MML_NS_LE')
@matrix_axis("compiler", "c", "Compiler(s) to be considered.")
class CompilerAxis(Enum):
AC6 = ('AC6', 'ArmCompiler6', 'armclang')
GCC = ('GCC',)
@property
def project(self):
return {
CompilerAxis.AC6: "ARM/MDK/RTX_CM.uvprojx",
CompilerAxis.GCC: "GCC/MDK/RTX_CM.uvprojx"
}[self]
@matrix_action
def build(config, results):
"""Build the selected configurations."""
yield uvision(config)
@matrix_command()
def uvision(config):
return ['uvision.com',
'-r', config.compiler.project,
'-t', config.device[1],
'-j0']
if __name__ == "__main__":
main()
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Library/build.py | python | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 394 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.6.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Library Configuration definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <e>Safety features (Source variant only)
// <i> Enables FuSa related features.
// <i> Requires RTX Source variant.
// <i> Enables:
// <i> - selected features from this group
// <i> - Thread functions: osThreadProtectPrivileged
#ifndef OS_SAFETY_FEATURES
#define OS_SAFETY_FEATURES 0
#endif
// <q>Safety Class
// <i> Threads assigned to lower classes cannot modify higher class threads.
// <i> Enables:
// <i> - Object attributes: osSafetyClass
// <i> - Kernel functions: osKernelProtect, osKernelDestroyClass
// <i> - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass
#ifndef OS_SAFETY_CLASS
#define OS_SAFETY_CLASS 1
#endif
// <q>MPU Protected Zone
// <i> Access protection via MPU (Spatial isolation).
// <i> Enables:
// <i> - Thread attributes: osThreadZone
// <i> - Thread functions: osThreadGetZone, osThreadTerminateZone
// <i> - Zone Management: osZoneSetup_Callback
#ifndef OS_EXECUTION_ZONE
#define OS_EXECUTION_ZONE 1
#endif
// <q>Thread Watchdog
// <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).
// <i> Enables:
// <i> - Thread functions: osThreadFeedWatchdog
// <i> - Handler functions: osWatchdogAlarm_Handler
#ifndef OS_THREAD_WATCHDOG
#define OS_THREAD_WATCHDOG 1
#endif
// <q>Object Pointer checking
// <i> Check object pointer alignment and memory region.
#ifndef OS_OBJ_PTR_CHECK
#define OS_OBJ_PTR_CHECK 0
#endif
// <q>SVC Function Pointer checking
// <i> Check SVC function pointer alignment and memory region.
// <i> User needs to define a linker execution region RTX_SVC_VENEERS
// <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)
#ifndef OS_SVC_PTR_CHECK
#define OS_SVC_PTR_CHECK 0
#endif
// </e>
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 0
#endif
// </h>
// <h>Event Recorder Configuration
// ===============================
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Library/RTX_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,242 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX Event Recorder definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_EVR_H_
#define RTX_EVR_H_
#include "rtx_os.h" // RTX OS definitions
// Initial Thread configuration covered also Thread Flags and Generic Wait
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS OS_EVR_THREAD
#endif
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT OS_EVR_THREAD
#endif
#ifdef _RTE_
#include "RTE_Components.h"
#endif
#ifdef RTE_Compiler_EventRecorder
//lint -emacro((835,845),EventID) [MISRA Note 13]
#include "EventRecorder.h"
#include "EventRecorderConf.h"
#if ((defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) || (EVENT_TIMESTAMP_SOURCE == 2))
#ifndef EVR_RTX_KERNEL_GET_STATE_DISABLE
#define EVR_RTX_KERNEL_GET_STATE_DISABLE
#endif
#endif
#if (EVENT_TIMESTAMP_SOURCE == 2)
#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE
#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE
#endif
#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE
#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE
#endif
#endif
/// RTOS component number
#define EvtRtxMemoryNo (0xF0U)
#define EvtRtxKernelNo (0xF1U)
#define EvtRtxThreadNo (0xF2U)
#define EvtRtxThreadFlagsNo (0xF4U)
#define EvtRtxWaitNo (0xF3U)
#define EvtRtxTimerNo (0xF6U)
#define EvtRtxEventFlagsNo (0xF5U)
#define EvtRtxMutexNo (0xF7U)
#define EvtRtxSemaphoreNo (0xF8U)
#define EvtRtxMemoryPoolNo (0xF9U)
#define EvtRtxMessageQueueNo (0xFAU)
#endif // RTE_Compiler_EventRecorder
/// Extended Status codes
#define osRtxErrorKernelNotReady (-8)
#define osRtxErrorKernelNotRunning (-9)
#define osRtxErrorInvalidControlBlock (-10)
#define osRtxErrorInvalidDataMemory (-11)
#define osRtxErrorInvalidThreadStack (-12)
#define osRtxErrorInvalidPriority (-13)
#define osRtxErrorInvalidPrivilegedMode (-14)
#define osRtxErrorThreadNotJoinable (-15)
#define osRtxErrorMutexNotOwned (-16)
#define osRtxErrorMutexNotLocked (-17)
#define osRtxErrorMutexLockLimit (-18)
#define osRtxErrorSemaphoreCountLimit (-19)
#define osRtxErrorTZ_InitContext_S (-20)
#define osRtxErrorTZ_AllocContext_S (-21)
#define osRtxErrorTZ_FreeContext_S (-22)
#define osRtxErrorTZ_LoadContext_S (-23)
#define osRtxErrorTZ_SaveContext_S (-24)
// ==== Memory Events ====
/**
\brief Event on memory initialization (Op)
\param[in] mem pointer to memory pool.
\param[in] size size of a memory pool in bytes.
\param[in] result execution status: 1 - success, 0 - failure.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))
extern void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result);
#else
#define EvrRtxMemoryInit(mem, size, result)
#endif
/**
\brief Event on memory allocate (Op)
\param[in] mem pointer to memory pool.
\param[in] size size of a memory block in bytes.
\param[in] type memory block type: 0 - generic, 1 - control block.
\param[in] block pointer to allocated memory block or NULL in case of no memory is available.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))
extern void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block);
#else
#define EvrRtxMemoryAlloc(mem, size, type, block)
#endif
/**
\brief Event on memory free (Op)
\param[in] mem pointer to memory pool.
\param[in] block memory block to be returned to the memory pool.
\param[in] result execution status: 1 - success, 0 - failure.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))
extern void EvrRtxMemoryFree (void *mem, void *block, uint32_t result);
#else
#define EvrRtxMemoryFree(mem, block, result)
#endif
/**
\brief Event on memory block initialization (Op)
\param[in] mp_info memory pool info.
\param[in] block_count maximum number of memory blocks in memory pool.
\param[in] block_size size of a memory block in bytes.
\param[in] block_mem pointer to memory for block storage.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))
extern void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem);
#else
#define EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem)
#endif
/**
\brief Event on memory block alloc (Op)
\param[in] mp_info memory pool info.
\param[in] block address of the allocated memory block or NULL in case of no memory is available.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))
extern void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block);
#else
#define EvrRtxMemoryBlockAlloc(mp_info, block)
#endif
/**
\brief Event on memory block free (Op)
\param[in] mp_info memory pool info.
\param[in] block address of the allocated memory block to be returned to the memory pool.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))
extern void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status);
#else
#define EvrRtxMemoryBlockFree(mp_info, block, status)
#endif
// ==== Kernel Events ====
/**
\brief Event on RTOS kernel error (Error)
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))
extern void EvrRtxKernelError (int32_t status);
#else
#define EvrRtxKernelError(status)
#endif
/**
\brief Event on RTOS kernel initialize (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))
extern void EvrRtxKernelInitialize (void);
#else
#define EvrRtxKernelInitialize()
#endif
/**
\brief Event on successful RTOS kernel initialize (Op)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE))
extern void EvrRtxKernelInitialized (void);
#else
#define EvrRtxKernelInitialized()
#endif
/**
\brief Event on RTOS kernel information retrieve (API)
\param[in] version pointer to buffer for retrieving version information.
\param[in] id_buf pointer to buffer for retrieving kernel identification string.
\param[in] id_size size of buffer for kernel identification string.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))
extern void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
#else
#define EvrRtxKernelGetInfo(version, id_buf, id_size)
#endif
/**
\brief Event on successful RTOS kernel information retrieve (Op)
\param[in] version pointer to buffer for retrieving version information.
\param[in] id_buf pointer to buffer for retrieving kernel identification string.
\param[in] id_size size of buffer for kernel identification string.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))
extern void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size);
#else
#define EvrRtxKernelInfoRetrieved(version, id_buf, id_size)
#endif
/**
\brief Event on current RTOS Kernel state retrieve (API)
\param[in] state current RTOS Kernel state.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))
extern void EvrRtxKernelGetState (osKernelState_t state);
#else
#define EvrRtxKernelGetState(state)
#endif
/**
\brief Event on RTOS Kernel scheduler start (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))
extern void EvrRtxKernelStart (void);
#else
#define EvrRtxKernelStart()
#endif
/**
\brief Event on successful RTOS Kernel scheduler start (Op)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))
extern void EvrRtxKernelStarted (void);
#else
#define EvrRtxKernelStarted()
#endif
/**
\brief Event on RTOS Kernel scheduler lock (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))
extern void EvrRtxKernelLock (void);
#else
#define EvrRtxKernelLock()
#endif
/**
\brief Event on successful RTOS Kernel scheduler lock (Op)
\param[in] lock previous lock state (1 - locked, 0 - not locked).
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))
extern void EvrRtxKernelLocked (int32_t lock);
#else
#define EvrRtxKernelLocked(lock)
#endif
/**
\brief Event on RTOS Kernel scheduler unlock (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))
extern void EvrRtxKernelUnlock (void);
#else
#define EvrRtxKernelUnlock()
#endif
/**
\brief Event on successful RTOS Kernel scheduler unlock (Op)
\param[in] lock previous lock state (1 - locked, 0 - not locked).
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))
extern void EvrRtxKernelUnlocked (int32_t lock);
#else
#define EvrRtxKernelUnlocked(lock)
#endif
/**
\brief Event on RTOS Kernel scheduler lock state restore (API)
\param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))
extern void EvrRtxKernelRestoreLock (int32_t lock);
#else
#define EvrRtxKernelRestoreLock(lock)
#endif
/**
\brief Event on successful RTOS Kernel scheduler lock state restore (Op)
\param[in] lock new lock state (1 - locked, 0 - not locked).
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))
extern void EvrRtxKernelLockRestored (int32_t lock);
#else
#define EvrRtxKernelLockRestored(lock)
#endif
/**
\brief Event on RTOS Kernel scheduler suspend (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))
extern void EvrRtxKernelSuspend (void);
#else
#define EvrRtxKernelSuspend()
#endif
/**
\brief Event on successful RTOS Kernel scheduler suspend (Op)
\param[in] sleep_ticks time in ticks, for how long the system can sleep or power-down.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))
extern void EvrRtxKernelSuspended (uint32_t sleep_ticks);
#else
#define EvrRtxKernelSuspended(sleep_ticks)
#endif
/**
\brief Event on RTOS Kernel scheduler resume (API)
\param[in] sleep_ticks time in ticks, for how long the system was in sleep or power-down mode.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))
extern void EvrRtxKernelResume (uint32_t sleep_ticks);
#else
#define EvrRtxKernelResume(sleep_ticks)
#endif
/**
\brief Event on successful RTOS Kernel scheduler resume (Op)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))
extern void EvrRtxKernelResumed (void);
#else
#define EvrRtxKernelResumed()
#endif
/**
\brief Event on protect the RTOS Kernel scheduler access (API)
\param[in] safety_class safety class.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECT_DISABLE))
extern void EvrRtxKernelProtect (uint32_t safety_class);
#else
#define EvrRtxKernelProtect(safety_class)
#endif
/**
\brief Event on successful RTOS Kernel scheduler protect (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECTED_DISABLE))
extern void EvrRtxKernelProtected (void);
#else
#define EvrRtxKernelProtected()
#endif
/**
\brief Event on RTOS kernel tick count retrieve (API)
\param[in] count RTOS kernel current tick count.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))
extern void EvrRtxKernelGetTickCount (uint32_t count);
#else
#define EvrRtxKernelGetTickCount(count)
#endif
/**
\brief Event on RTOS kernel tick frequency retrieve (API)
\param[in] freq frequency of the kernel tick.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))
extern void EvrRtxKernelGetTickFreq (uint32_t freq);
#else
#define EvrRtxKernelGetTickFreq(freq)
#endif
/**
\brief Event on RTOS kernel system timer count retrieve (API)
\param[in] count RTOS kernel current system timer count as 32-bit value.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))
extern void EvrRtxKernelGetSysTimerCount (uint32_t count);
#else
#define EvrRtxKernelGetSysTimerCount(count)
#endif
/**
\brief Event on RTOS kernel system timer frequency retrieve (API)
\param[in] freq frequency of the system timer.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))
extern void EvrRtxKernelGetSysTimerFreq (uint32_t freq);
#else
#define EvrRtxKernelGetSysTimerFreq(freq)
#endif
/**
\brief Event on RTOS kernel system error (Error)
\param[in] code error code.
\param[in] object_id object that caused the error.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE))
extern void EvrRtxKernelErrorNotify (uint32_t code, void *object_id);
#else
#define EvrRtxKernelErrorNotify(code, object_id)
#endif
/**
\brief Event on destroy safety class objects (API)
\param[in] safety_class safety class.
\param[in] mode safety mode.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_DESTROY_CLASS_DISABLE))
extern void EvrRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode);
#else
#define EvrRtxKernelDestroyClass(safety_class, mode)
#endif
// ==== Thread Events ====
/**
\brief Event on thread error (Error)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))
extern void EvrRtxThreadError (osThreadId_t thread_id, int32_t status);
#else
#define EvrRtxThreadError(thread_id, status)
#endif
/**
\brief Event on thread create and intialize (API)
\param[in] func thread function.
\param[in] argument pointer that is passed to the thread function as start argument.
\param[in] attr thread attributes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))
extern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
#else
#define EvrRtxThreadNew(func, argument, attr)
#endif
/**
\brief Event on successful thread create (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] thread_addr thread entry address.
\param[in] name pointer to thread object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))
extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name);
#else
#define EvrRtxThreadCreated(thread_id, thread_addr, name)
#endif
/**
\brief Event on thread name retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] name pointer to thread object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))
extern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name);
#else
#define EvrRtxThreadGetName(thread_id, name)
#endif
/**
\brief Event on thread safety class retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] safety_class thread safety class.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_CLASS_DISABLE))
extern void EvrRtxThreadGetClass (osThreadId_t thread_id, uint32_t safety_class);
#else
#define EvrRtxThreadGetClass(thread_id, safety_class)
#endif
/**
\brief Event on thread zone retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] zone thread zone.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ZONE_DISABLE))
extern void EvrRtxThreadGetZone (osThreadId_t thread_id, uint32_t zone);
#else
#define EvrRtxThreadGetZone(thread_id, zone)
#endif
/**
\brief Event on current running thread ID retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))
extern void EvrRtxThreadGetId (osThreadId_t thread_id);
#else
#define EvrRtxThreadGetId(thread_id)
#endif
/**
\brief Event on thread state retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] state current thread state of the specified thread.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))
extern void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state);
#else
#define EvrRtxThreadGetState(thread_id, state)
#endif
/**
\brief Event on thread stack size retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] stack_size stack size in bytes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))
extern void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size);
#else
#define EvrRtxThreadGetStackSize(thread_id, stack_size)
#endif
/**
\brief Event on available stack space retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] stack_space remaining stack space in bytes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))
extern void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space);
#else
#define EvrRtxThreadGetStackSpace(thread_id, stack_space)
#endif
/**
\brief Event on thread priority set (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] priority new priority value for the thread function.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))
extern void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
#else
#define EvrRtxThreadSetPriority(thread_id, priority)
#endif
/**
\brief Event on thread priority updated (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] priority new priority value for the thread function.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE))
extern void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority);
#else
#define EvrRtxThreadPriorityUpdated(thread_id, priority)
#endif
/**
\brief Event on thread priority retrieve (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] priority current priority value of the specified thread.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))
extern void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority);
#else
#define EvrRtxThreadGetPriority(thread_id, priority)
#endif
/**
\brief Event on thread yield (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))
extern void EvrRtxThreadYield (void);
#else
#define EvrRtxThreadYield()
#endif
/**
\brief Event on thread suspend (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))
extern void EvrRtxThreadSuspend (osThreadId_t thread_id);
#else
#define EvrRtxThreadSuspend(thread_id)
#endif
/**
\brief Event on successful thread suspend (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))
extern void EvrRtxThreadSuspended (osThreadId_t thread_id);
#else
#define EvrRtxThreadSuspended(thread_id)
#endif
/**
\brief Event on thread resume (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))
extern void EvrRtxThreadResume (osThreadId_t thread_id);
#else
#define EvrRtxThreadResume(thread_id)
#endif
/**
\brief Event on successful thread resume (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))
extern void EvrRtxThreadResumed (osThreadId_t thread_id);
#else
#define EvrRtxThreadResumed(thread_id)
#endif
/**
\brief Event on thread detach (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))
extern void EvrRtxThreadDetach (osThreadId_t thread_id);
#else
#define EvrRtxThreadDetach(thread_id)
#endif
/**
\brief Event on successful thread detach (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))
extern void EvrRtxThreadDetached (osThreadId_t thread_id);
#else
#define EvrRtxThreadDetached(thread_id)
#endif
/**
\brief Event on thread join (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))
extern void EvrRtxThreadJoin (osThreadId_t thread_id);
#else
#define EvrRtxThreadJoin(thread_id)
#endif
/**
\brief Event on pending thread join (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))
extern void EvrRtxThreadJoinPending (osThreadId_t thread_id);
#else
#define EvrRtxThreadJoinPending(thread_id)
#endif
/**
\brief Event on successful thread join (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))
extern void EvrRtxThreadJoined (osThreadId_t thread_id);
#else
#define EvrRtxThreadJoined(thread_id)
#endif
/**
\brief Event on thread execution block (Detail)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))
extern void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout);
#else
#define EvrRtxThreadBlocked(thread_id, timeout)
#endif
/**
\brief Event on thread execution unblock (Detail)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] ret_val extended execution status of the thread.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))
extern void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val);
#else
#define EvrRtxThreadUnblocked(thread_id, ret_val)
#endif
/**
\brief Event on running thread pre-emption (Detail)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE))
extern void EvrRtxThreadPreempted (osThreadId_t thread_id);
#else
#define EvrRtxThreadPreempted(thread_id)
#endif
/**
\brief Event on running thread switch (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE))
extern void EvrRtxThreadSwitched (osThreadId_t thread_id);
#else
#define EvrRtxThreadSwitched(thread_id)
#endif
/**
\brief Event on thread exit (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))
extern void EvrRtxThreadExit (void);
#else
#define EvrRtxThreadExit()
#endif
/**
\brief Event on thread terminate (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))
extern void EvrRtxThreadTerminate (osThreadId_t thread_id);
#else
#define EvrRtxThreadTerminate(thread_id)
#endif
/**
\brief Event on successful thread terminate (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))
extern void EvrRtxThreadDestroyed (osThreadId_t thread_id);
#else
#define EvrRtxThreadDestroyed(thread_id)
#endif
/**
\brief Event on thread feed watchdog (API)
\param[in] ticks timeout in number of ticks.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DISABLE))
extern void EvrRtxThreadFeedWatchdog (uint32_t ticks);
#else
#define EvrRtxThreadFeedWatchdog(ticks)
#endif
/**
\brief Event on thread feed watchdog done (Op)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DONE_DISABLE))
extern void EvrRtxThreadFeedWatchdogDone (void);
#else
#define EvrRtxThreadFeedWatchdogDone()
#endif
/**
\brief Event on protect the creation of privileged threads (API)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PROTECT_PRIVILEGED_DISABLE))
extern void EvrRtxThreadProtectPrivileged (void);
#else
#define EvrRtxThreadProtectPrivileged()
#endif
/**
\brief Event on successful protect the creation of privileged threads (Op)
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIVILEGED_PROTECTED_DISABLE))
extern void EvrRtxThreadPrivilegedProtected (void);
#else
#define EvrRtxThreadPrivilegedProtected()
#endif
/**
\brief Event on active thread count retrieve (API)
\param[in] count number of active threads.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))
extern void EvrRtxThreadGetCount (uint32_t count);
#else
#define EvrRtxThreadGetCount(count)
#endif
/**
\brief Event on active threads enumerate (API)
\param[in] thread_array pointer to array for retrieving thread IDs.
\param[in] array_items maximum number of items in array for retrieving thread IDs.
\param[in] count number of enumerated threads.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))
extern void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count);
#else
#define EvrRtxThreadEnumerate(thread_array, array_items, count)
#endif
/**
\brief Event on thread safety class suspend (API)
\param[in] safety_class safety class.
\param[in] mode safety mode.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_CLASS_DISABLE))
extern void EvrRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode);
#else
#define EvrRtxThreadSuspendClass(safety_class, mode)
#endif
/**
\brief Event on thread safety class resume (API)
\param[in] safety_class safety class.
\param[in] mode safety mode.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_CLASS_DISABLE))
extern void EvrRtxThreadResumeClass (uint32_t safety_class, uint32_t mode);
#else
#define EvrRtxThreadResumeClass(safety_class, mode)
#endif
/**
\brief Event on thread zone terminate (API)
\param[in] zone thread zone.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_ZONE_DISABLE))
extern void EvrRtxThreadTerminateZone (uint32_t zone);
#else
#define EvrRtxThreadTerminateZone(zone)
#endif
/**
\brief Event on thread watchdog expired (Error)
\param[in] thread_id thread ID obtained by \ref osThreadNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_WATCHDOG_EXPIRED_DISABLE))
extern void EvrRtxThreadWatchdogExpired (osThreadId_t thread_id);
#else
#define EvrRtxThreadWatchdogExpired(thread_id)
#endif
// ==== Thread Flags Events ====
/**
\brief Event on thread flags error (Error)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE))
extern void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status);
#else
#define EvrRtxThreadFlagsError(thread_id, status)
#endif
/**
\brief Event on thread flags set (API)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] flags flags of the thread that shall be set.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))
extern void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
#else
#define EvrRtxThreadFlagsSet(thread_id, flags)
#endif
/**
\brief Event on successful thread flags set (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
\param[in] thread_flags thread flags after setting.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))
extern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags);
#else
#define EvrRtxThreadFlagsSetDone(thread_id, thread_flags)
#endif
/**
\brief Event on thread flags clear (API)
\param[in] flags flags of the thread that shall be cleared.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))
extern void EvrRtxThreadFlagsClear (uint32_t flags);
#else
#define EvrRtxThreadFlagsClear(flags)
#endif
/**
\brief Event on successful thread flags clear (Op)
\param[in] thread_flags thread flags before clearing.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))
extern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags);
#else
#define EvrRtxThreadFlagsClearDone(thread_flags)
#endif
/**
\brief Event on thread flags retrieve (API)
\param[in] thread_flags current thread flags.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))
extern void EvrRtxThreadFlagsGet (uint32_t thread_flags);
#else
#define EvrRtxThreadFlagsGet(thread_flags)
#endif
/**
\brief Event on wait for thread flags (API)
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))
extern void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
#else
#define EvrRtxThreadFlagsWait(flags, options, timeout)
#endif
/**
\brief Event on pending wait for thread flags (Op)
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))
extern void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout);
#else
#define EvrRtxThreadFlagsWaitPending(flags, options, timeout)
#endif
/**
\brief Event on wait timeout for thread flags (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))
extern void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id);
#else
#define EvrRtxThreadFlagsWaitTimeout(thread_id)
#endif
/**
\brief Event on successful wait for thread flags (Op)
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] thread_flags thread flags before clearing.
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))
extern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id);
#else
#define EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread_id)
#endif
/**
\brief Event on unsuccessful wait for thread flags (Op)
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
extern void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options);
#else
#define EvrRtxThreadFlagsWaitNotCompleted(flags, options)
#endif
// ==== Generic Wait Events ====
/**
\brief Event on delay error (Error)
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE))
extern void EvrRtxDelayError (int32_t status);
#else
#define EvrRtxDelayError(status)
#endif
/**
\brief Event on delay for specified time (API)
\param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE))
extern void EvrRtxDelay (uint32_t ticks);
#else
#define EvrRtxDelay(ticks)
#endif
/**
\brief Event on delay until specified time (API)
\param[in] ticks absolute time in ticks.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE))
extern void EvrRtxDelayUntil (uint32_t ticks);
#else
#define EvrRtxDelayUntil(ticks)
#endif
/**
\brief Event on delay started (Op)
\param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE))
extern void EvrRtxDelayStarted (uint32_t ticks);
#else
#define EvrRtxDelayStarted(ticks)
#endif
/**
\brief Event on delay until specified time started (Op)
\param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE))
extern void EvrRtxDelayUntilStarted (uint32_t ticks);
#else
#define EvrRtxDelayUntilStarted(ticks)
#endif
/**
\brief Event on delay completed (Op)
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE))
extern void EvrRtxDelayCompleted (osThreadId_t thread_id);
#else
#define EvrRtxDelayCompleted(thread_id)
#endif
// ==== Timer Events ====
/**
\brief Event on timer error (Error)
\param[in] timer_id timer ID obtained by \ref osTimerNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))
extern void EvrRtxTimerError (osTimerId_t timer_id, int32_t status);
#else
#define EvrRtxTimerError(timer_id, status)
#endif
/**
\brief Event on timer callback call (Op)
\param[in] func start address of a timer call back function.
\param[in] argument argument to the timer call back function.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))
extern void EvrRtxTimerCallback (osTimerFunc_t func, void *argument);
#else
#define EvrRtxTimerCallback(func, argument)
#endif
/**
\brief Event on timer create and initialize (API)
\param[in] func start address of a timer call back function.
\param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
\param[in] argument argument to the timer call back function.
\param[in] attr timer attributes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))
extern void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
#else
#define EvrRtxTimerNew(func, type, argument, attr)
#endif
/**
\brief Event on successful timer create (Op)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
\param[in] name pointer to timer object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))
extern void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name);
#else
#define EvrRtxTimerCreated(timer_id, name)
#endif
/**
\brief Event on timer name retrieve (API)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
\param[in] name pointer to timer object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))
extern void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name);
#else
#define EvrRtxTimerGetName(timer_id, name)
#endif
/**
\brief Event on timer start (API)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
\param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))
extern void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks);
#else
#define EvrRtxTimerStart(timer_id, ticks)
#endif
/**
\brief Event on successful timer start (Op)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))
extern void EvrRtxTimerStarted (osTimerId_t timer_id);
#else
#define EvrRtxTimerStarted(timer_id)
#endif
/**
\brief Event on timer stop (API)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))
extern void EvrRtxTimerStop (osTimerId_t timer_id);
#else
#define EvrRtxTimerStop(timer_id)
#endif
/**
\brief Event on successful timer stop (Op)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))
extern void EvrRtxTimerStopped (osTimerId_t timer_id);
#else
#define EvrRtxTimerStopped(timer_id)
#endif
/**
\brief Event on timer running state check (API)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
\param[in] running running state: 0 not running, 1 running.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))
extern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running);
#else
#define EvrRtxTimerIsRunning(timer_id, running)
#endif
/**
\brief Event on timer delete (API)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))
extern void EvrRtxTimerDelete (osTimerId_t timer_id);
#else
#define EvrRtxTimerDelete(timer_id)
#endif
/**
\brief Event on successful timer delete (Op)
\param[in] timer_id timer ID obtained by \ref osTimerNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))
extern void EvrRtxTimerDestroyed (osTimerId_t timer_id);
#else
#define EvrRtxTimerDestroyed(timer_id)
#endif
// ==== Event Flags Events ====
/**
\brief Event on event flags error (Error)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))
extern void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status);
#else
#define EvrRtxEventFlagsError(ef_id, status)
#endif
/**
\brief Event on event flags create and initialize (API)
\param[in] attr event flags attributes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))
extern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr);
#else
#define EvrRtxEventFlagsNew(attr)
#endif
/**
\brief Event on successful event flags create (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] name pointer to event flags object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))
extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name);
#else
#define EvrRtxEventFlagsCreated(ef_id, name)
#endif
/**
\brief Event on event flags name retrieve (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] name pointer to event flags object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))
extern void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name);
#else
#define EvrRtxEventFlagsGetName(ef_id, name)
#endif
/**
\brief Event on event flags set (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags that shall be set.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))
extern void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
#else
#define EvrRtxEventFlagsSet(ef_id, flags)
#endif
/**
\brief Event on successful event flags set (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] event_flags event flags after setting.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))
extern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags);
#else
#define EvrRtxEventFlagsSetDone(ef_id, event_flags)
#endif
/**
\brief Event on event flags clear (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags that shall be cleared.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))
extern void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
#else
#define EvrRtxEventFlagsClear(ef_id, flags)
#endif
/**
\brief Event on successful event flags clear (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] event_flags event flags before clearing.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))
extern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags);
#else
#define EvrRtxEventFlagsClearDone(ef_id, event_flags)
#endif
/**
\brief Event on event flags retrieve (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] event_flags current event flags.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))
extern void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags);
#else
#define EvrRtxEventFlagsGet(ef_id, event_flags)
#endif
/**
\brief Event on wait for event flags (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))
extern void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
#else
#define EvrRtxEventFlagsWait(ef_id, flags, options, timeout)
#endif
/**
\brief Event on pending wait for event flags (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))
extern void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
#else
#define EvrRtxEventFlagsWaitPending(ef_id, flags, options, timeout)
#endif
/**
\brief Event on wait timeout for event flags (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))
extern void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id);
#else
#define EvrRtxEventFlagsWaitTimeout(ef_id)
#endif
/**
\brief Event on successful wait for event flags (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
\param[in] event_flags event flags before clearing or 0 if specified flags have not been set.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))
extern void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags);
#else
#define EvrRtxEventFlagsWaitCompleted(ef_id, flags, options, event_flags)
#endif
/**
\brief Event on unsuccessful wait for event flags (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
\param[in] flags flags to wait for.
\param[in] options flags options (osFlagsXxxx).
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
extern void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options);
#else
#define EvrRtxEventFlagsWaitNotCompleted(ef_id, flags, options)
#endif
/**
\brief Event on event flags delete (API)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))
extern void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id);
#else
#define EvrRtxEventFlagsDelete(ef_id)
#endif
/**
\brief Event on successful event flags delete (Op)
\param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))
extern void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id);
#else
#define EvrRtxEventFlagsDestroyed(ef_id)
#endif
// ==== Mutex Events ====
/**
\brief Event on mutex error (Error)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))
extern void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status);
#else
#define EvrRtxMutexError(mutex_id, status)
#endif
/**
\brief Event on mutex create and initialize (API)
\param[in] attr mutex attributes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))
extern void EvrRtxMutexNew (const osMutexAttr_t *attr);
#else
#define EvrRtxMutexNew(attr)
#endif
/**
\brief Event on successful mutex create (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] name pointer to mutex object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))
extern void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name);
#else
#define EvrRtxMutexCreated(mutex_id, name)
#endif
/**
\brief Event on mutex name retrieve (API)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] name pointer to mutex object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))
extern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name);
#else
#define EvrRtxMutexGetName(mutex_id, name)
#endif
/**
\brief Event on mutex acquire (API)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))
extern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
#else
#define EvrRtxMutexAcquire(mutex_id, timeout)
#endif
/**
\brief Event on pending mutex acquire (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))
extern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout);
#else
#define EvrRtxMutexAcquirePending(mutex_id, timeout)
#endif
/**
\brief Event on mutex acquire timeout (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))
extern void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id);
#else
#define EvrRtxMutexAcquireTimeout(mutex_id)
#endif
/**
\brief Event on successful mutex acquire (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] lock current number of times mutex object is locked.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))
extern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock);
#else
#define EvrRtxMutexAcquired(mutex_id, lock)
#endif
/**
\brief Event on unsuccessful mutex acquire (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))
extern void EvrRtxMutexNotAcquired (osMutexId_t mutex_id);
#else
#define EvrRtxMutexNotAcquired(mutex_id)
#endif
/**
\brief Event on mutex release (API)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))
extern void EvrRtxMutexRelease (osMutexId_t mutex_id);
#else
#define EvrRtxMutexRelease(mutex_id)
#endif
/**
\brief Event on successful mutex release (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] lock current number of times mutex object is locked.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))
extern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock);
#else
#define EvrRtxMutexReleased(mutex_id, lock)
#endif
/**
\brief Event on mutex owner retrieve (API)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
\param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))
extern void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id);
#else
#define EvrRtxMutexGetOwner(mutex_id, thread_id)
#endif
/**
\brief Event on mutex delete (API)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))
extern void EvrRtxMutexDelete (osMutexId_t mutex_id);
#else
#define EvrRtxMutexDelete(mutex_id)
#endif
/**
\brief Event on successful mutex delete (Op)
\param[in] mutex_id mutex ID obtained by \ref osMutexNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))
extern void EvrRtxMutexDestroyed (osMutexId_t mutex_id);
#else
#define EvrRtxMutexDestroyed(mutex_id)
#endif
// ==== Semaphore Events ====
/**
\brief Event on semaphore error (Error)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))
extern void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status);
#else
#define EvrRtxSemaphoreError(semaphore_id, status)
#endif
/**
\brief Event on semaphore create and initialize (API)
\param[in] max_count maximum number of available tokens.
\param[in] initial_count initial number of available tokens.
\param[in] attr semaphore attributes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))
extern void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
#else
#define EvrRtxSemaphoreNew(max_count, initial_count, attr)
#endif
/**
\brief Event on successful semaphore create (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] name pointer to semaphore object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))
extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name);
#else
#define EvrRtxSemaphoreCreated(semaphore_id, name)
#endif
/**
\brief Event on semaphore name retrieve (API)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] name pointer to semaphore object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))
extern void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name);
#else
#define EvrRtxSemaphoreGetName(semaphore_id, name)
#endif
/**
\brief Event on semaphore acquire (API)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))
extern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
#else
#define EvrRtxSemaphoreAcquire(semaphore_id, timeout)
#endif
/**
\brief Event on pending semaphore acquire (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))
extern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout);
#else
#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout)
#endif
/**
\brief Event on semaphore acquire timeout (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))
extern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id);
#else
#define EvrRtxSemaphoreAcquireTimeout(semaphore_id)
#endif
/**
\brief Event on successful semaphore acquire (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] tokens number of available tokens.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))
extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens);
#else
#define EvrRtxSemaphoreAcquired(semaphore_id, tokens)
#endif
/**
\brief Event on unsuccessful semaphore acquire (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))
extern void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id);
#else
#define EvrRtxSemaphoreNotAcquired(semaphore_id)
#endif
/**
\brief Event on semaphore release (API)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))
extern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id);
#else
#define EvrRtxSemaphoreRelease(semaphore_id)
#endif
/**
\brief Event on successful semaphore release (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] tokens number of available tokens.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))
extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens);
#else
#define EvrRtxSemaphoreReleased(semaphore_id, tokens)
#endif
/**
\brief Event on semaphore token count retrieval (API)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
\param[in] count current number of available tokens.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))
extern void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count);
#else
#define EvrRtxSemaphoreGetCount(semaphore_id, count)
#endif
/**
\brief Event on semaphore delete (API)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))
extern void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id);
#else
#define EvrRtxSemaphoreDelete(semaphore_id)
#endif
/**
\brief Event on successful semaphore delete (Op)
\param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))
extern void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id);
#else
#define EvrRtxSemaphoreDestroyed(semaphore_id)
#endif
// ==== Memory Pool Events ====
/**
\brief Event on memory pool error (Error)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))
extern void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status);
#else
#define EvrRtxMemoryPoolError(mp_id, status)
#endif
/**
\brief Event on memory pool create and initialize (API)
\param[in] block_count maximum number of memory blocks in memory pool.
\param[in] block_size memory block size in bytes.
\param[in] attr memory pool attributes; NULL: default values.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))
extern void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
#else
#define EvrRtxMemoryPoolNew(block_count, block_size, attr)
#endif
/**
\brief Event on successful memory pool create (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] name pointer to memory pool object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))
extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name);
#else
#define EvrRtxMemoryPoolCreated(mp_id, name)
#endif
/**
\brief Event on memory pool name retrieve (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] name pointer to memory pool object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))
extern void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name);
#else
#define EvrRtxMemoryPoolGetName(mp_id, name)
#endif
/**
\brief Event on memory pool allocation (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))
extern void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
#else
#define EvrRtxMemoryPoolAlloc(mp_id, timeout)
#endif
/**
\brief Event on pending memory pool allocation (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))
extern void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout);
#else
#define EvrRtxMemoryPoolAllocPending(mp_id, timeout)
#endif
/**
\brief Event on memory pool allocation timeout (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))
extern void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id);
#else
#define EvrRtxMemoryPoolAllocTimeout(mp_id)
#endif
/**
\brief Event on successful memory pool allocation (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] block address of the allocated memory block.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))
extern void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block);
#else
#define EvrRtxMemoryPoolAllocated(mp_id, block)
#endif
/**
\brief Event on unsuccessful memory pool allocation (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))
extern void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id);
#else
#define EvrRtxMemoryPoolAllocFailed(mp_id)
#endif
/**
\brief Event on memory pool free (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] block address of the allocated memory block to be returned to the memory pool.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))
extern void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
#else
#define EvrRtxMemoryPoolFree(mp_id, block)
#endif
/**
\brief Event on successful memory pool free (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] block address of the allocated memory block to be returned to the memory pool.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))
extern void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block);
#else
#define EvrRtxMemoryPoolDeallocated(mp_id, block)
#endif
/**
\brief Event on unsuccessful memory pool free (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] block address of the allocated memory block to be returned to the memory pool.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))
extern void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block);
#else
#define EvrRtxMemoryPoolFreeFailed(mp_id, block)
#endif
/**
\brief Event on memory pool capacity retrieve (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] capacity maximum number of memory blocks.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))
extern void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity);
#else
#define EvrRtxMemoryPoolGetCapacity(mp_id, capacity)
#endif
/**
\brief Event on memory pool block size retrieve (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] block_size memory block size in bytes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))
extern void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size);
#else
#define EvrRtxMemoryPoolGetBlockSize(mp_id, block_size)
#endif
/**
\brief Event on used memory pool blocks retrieve (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] count number of memory blocks used.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))
extern void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count);
#else
#define EvrRtxMemoryPoolGetCount(mp_id, count)
#endif
/**
\brief Event on available memory pool blocks retrieve (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
\param[in] space number of memory blocks available.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))
extern void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space);
#else
#define EvrRtxMemoryPoolGetSpace(mp_id, space)
#endif
/**
\brief Event on memory pool delete (API)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))
extern void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id);
#else
#define EvrRtxMemoryPoolDelete(mp_id)
#endif
/**
\brief Event on successful memory pool delete (Op)
\param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))
extern void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id);
#else
#define EvrRtxMemoryPoolDestroyed(mp_id)
#endif
// ==== Message Queue Events ====
/**
\brief Event on message queue error (Error)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew or NULL when ID is unknown.
\param[in] status extended execution status.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))
extern void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status);
#else
#define EvrRtxMessageQueueError(mq_id, status)
#endif
/**
\brief Event on message queue create and initialization (API)
\param[in] msg_count maximum number of messages in queue.
\param[in] msg_size maximum message size in bytes.
\param[in] attr message queue attributes; NULL: default values.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))
extern void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
#else
#define EvrRtxMessageQueueNew(msg_count, msg_size, attr)
#endif
/**
\brief Event on successful message queue create (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] name pointer to message queue object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))
extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name);
#else
#define EvrRtxMessageQueueCreated(mq_id, name)
#endif
/**
\brief Event on message queue name retrieve(API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] name pointer to message queue object name.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))
extern void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name);
#else
#define EvrRtxMessageQueueGetName(mq_id, name)
#endif
/**
\brief Event on message put (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer with message to put into a queue.
\param[in] msg_prio message priority.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))
extern void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
#else
#define EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout)
#endif
/**
\brief Event on pending message put (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer with message to put into a queue.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))
extern void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout);
#else
#define EvrRtxMessageQueuePutPending(mq_id, msg_ptr, timeout)
#endif
/**
\brief Event on message put timeout (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))
extern void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueuePutTimeout(mq_id)
#endif
/**
\brief Event on pending message insert (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer with message to put into a queue.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))
extern void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr);
#else
#define EvrRtxMessageQueueInsertPending(mq_id, msg_ptr)
#endif
/**
\brief Event on successful message insert (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer with message to put into a queue.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))
extern void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr);
#else
#define EvrRtxMessageQueueInserted(mq_id, msg_ptr)
#endif
/**
\brief Event on unsuccessful message insert (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer with message to put into a queue.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))
extern void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr);
#else
#define EvrRtxMessageQueueNotInserted(mq_id, msg_ptr)
#endif
/**
\brief Event on message get (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer for message to get from a queue.
\param[in] msg_prio message priority.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))
extern void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
#else
#define EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout)
#endif
/**
\brief Event on pending message get (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer for message to get from a queue.
\param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))
extern void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout);
#else
#define EvrRtxMessageQueueGetPending(mq_id, msg_ptr, timeout)
#endif
/**
\brief Event on message get timeout (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))
extern void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueueGetTimeout(mq_id)
#endif
/**
\brief Event on successful message get (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer for message to get from a queue.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))
extern void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);
#else
#define EvrRtxMessageQueueRetrieved(mq_id, msg_ptr)
#endif
/**
\brief Event on unsuccessful message get (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_ptr pointer to buffer for message to get from a queue.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))
extern void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);
#else
#define EvrRtxMessageQueueNotRetrieved(mq_id, msg_ptr)
#endif
/**
\brief Event on message queue capacity retrieve (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] capacity maximum number of messages.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))
extern void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity);
#else
#define EvrRtxMessageQueueGetCapacity(mq_id, capacity)
#endif
/**
\brief Event on message queue message size retrieve (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] msg_size maximum message size in bytes.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))
extern void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size);
#else
#define EvrRtxMessageQueueGetMsgSize(mq_id, msg_size)
#endif
/**
\brief Event on message queue message count retrieve (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] count number of queued messages.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))
extern void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count);
#else
#define EvrRtxMessageQueueGetCount(mq_id, count)
#endif
/**
\brief Event on message queue message slots retrieve (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
\param[in] space number of available slots for messages.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))
extern void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space);
#else
#define EvrRtxMessageQueueGetSpace(mq_id, space)
#endif
/**
\brief Event on message queue reset (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))
extern void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueueReset(mq_id)
#endif
/**
\brief Event on successful message queue reset (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))
extern void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueueResetDone(mq_id)
#endif
/**
\brief Event on message queue delete (API)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))
extern void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueueDelete(mq_id)
#endif
/**
\brief Event on successful message queue delete (Op)
\param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
*/
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))
extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id);
#else
#define EvrRtxMessageQueueDestroyed(mq_id)
#endif
#endif // RTX_EVR_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Include/rtx_evr.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 22,204 |
```objective-c
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'RTX_CM'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Library/IAR/IDE/RTE_Components.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 52 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX Event Recorder
*
* your_sha256_hash-------------
*/
#include <string.h>
#include "cmsis_compiler.h"
#include "rtx_evr.h" // RTX Event Recorder definitions
#ifdef RTE_Compiler_EventRecorder
//lint -e923 -e9074 -e9078 [MISRA Note 13]
/// Event IDs for "RTX Memory Management"
#define EvtRtxMemoryInit EventID(EventLevelOp, EvtRtxMemoryNo, 0x00U)
#define EvtRtxMemoryAlloc EventID(EventLevelOp, EvtRtxMemoryNo, 0x01U)
#define EvtRtxMemoryFree EventID(EventLevelOp, EvtRtxMemoryNo, 0x02U)
#define EvtRtxMemoryBlockInit EventID(EventLevelOp, EvtRtxMemoryNo, 0x03U)
#define EvtRtxMemoryBlockAlloc EventID(EventLevelOp, EvtRtxMemoryNo, 0x04U)
#define EvtRtxMemoryBlockFree EventID(EventLevelOp, EvtRtxMemoryNo, 0x05U)
/// Event IDs for "RTX Kernel"
#define EvtRtxKernelError EventID(EventLevelError, EvtRtxKernelNo, 0x00U)
#define EvtRtxKernelInitialize EventID(EventLevelAPI, EvtRtxKernelNo, 0x01U)
#define EvtRtxKernelInitialized EventID(EventLevelOp, EvtRtxKernelNo, 0x02U)
#define EvtRtxKernelGetInfo EventID(EventLevelAPI, EvtRtxKernelNo, 0x03U)
#define EvtRtxKernelInfoRetrieved EventID(EventLevelOp, EvtRtxKernelNo, 0x04U)
#define EvtRtxKernelInfoRetrieved_Detail EventID(EventLevelDetail, EvtRtxKernelNo, 0x05U)
#define EvtRtxKernelGetState EventID(EventLevelAPI, EvtRtxKernelNo, 0x06U)
#define EvtRtxKernelStart EventID(EventLevelAPI, EvtRtxKernelNo, 0x07U)
#define EvtRtxKernelStarted EventID(EventLevelOp, EvtRtxKernelNo, 0x08U)
#define EvtRtxKernelLock EventID(EventLevelAPI, EvtRtxKernelNo, 0x09U)
#define EvtRtxKernelLocked EventID(EventLevelOp, EvtRtxKernelNo, 0x0AU)
#define EvtRtxKernelUnlock EventID(EventLevelAPI, EvtRtxKernelNo, 0x0BU)
#define EvtRtxKernelUnlocked EventID(EventLevelOp, EvtRtxKernelNo, 0x0CU)
#define EvtRtxKernelRestoreLock EventID(EventLevelAPI, EvtRtxKernelNo, 0x0DU)
#define EvtRtxKernelLockRestored EventID(EventLevelOp, EvtRtxKernelNo, 0x0EU)
#define EvtRtxKernelSuspend EventID(EventLevelAPI, EvtRtxKernelNo, 0x0FU)
#define EvtRtxKernelSuspended EventID(EventLevelOp, EvtRtxKernelNo, 0x10U)
#define EvtRtxKernelResume EventID(EventLevelAPI, EvtRtxKernelNo, 0x11U)
#define EvtRtxKernelResumed EventID(EventLevelOp, EvtRtxKernelNo, 0x12U)
#define EvtRtxKernelProtect EventID(EventLevelAPI, EvtRtxKernelNo, 0x17U)
#define EvtRtxKernelProtected EventID(EventLevelOp, EvtRtxKernelNo, 0x18U)
#define EvtRtxKernelGetTickCount EventID(EventLevelAPI, EvtRtxKernelNo, 0x13U)
#define EvtRtxKernelGetTickFreq EventID(EventLevelAPI, EvtRtxKernelNo, 0x14U)
#define EvtRtxKernelGetSysTimerCount EventID(EventLevelAPI, EvtRtxKernelNo, 0x15U)
#define EvtRtxKernelGetSysTimerFreq EventID(EventLevelAPI, EvtRtxKernelNo, 0x16U)
#define EvtRtxKernelErrorNotify EventID(EventLevelError, EvtRtxKernelNo, 0x19U)
#define EvtRtxKernelDestroyClass EventID(EventLevelAPI, EvtRtxKernelNo, 0x1AU)
/// Event IDs for "RTX Thread"
#define EvtRtxThreadError EventID(EventLevelError, EvtRtxThreadNo, 0x00U)
#define EvtRtxThreadNew EventID(EventLevelAPI, EvtRtxThreadNo, 0x01U)
#define EvtRtxThreadCreated_Addr EventID(EventLevelOp, EvtRtxThreadNo, 0x03U)
#define EvtRtxThreadCreated_Name EventID(EventLevelOp, EvtRtxThreadNo, 0x2CU)
#define EvtRtxThreadGetName EventID(EventLevelAPI, EvtRtxThreadNo, 0x04U)
#define EvtRtxThreadGetClass EventID(EventLevelAPI, EvtRtxThreadNo, 0x30U)
#define EvtRtxThreadGetZone EventID(EventLevelAPI, EvtRtxThreadNo, 0x31U)
#define EvtRtxThreadGetId EventID(EventLevelAPI, EvtRtxThreadNo, 0x06U)
#define EvtRtxThreadGetState EventID(EventLevelAPI, EvtRtxThreadNo, 0x07U)
#define EvtRtxThreadGetStackSize EventID(EventLevelAPI, EvtRtxThreadNo, 0x08U)
#define EvtRtxThreadGetStackSpace EventID(EventLevelAPI, EvtRtxThreadNo, 0x09U)
#define EvtRtxThreadSetPriority EventID(EventLevelAPI, EvtRtxThreadNo, 0x0AU)
#define EvtRtxThreadPriorityUpdated EventID(EventLevelOp, EvtRtxThreadNo, 0x2DU)
#define EvtRtxThreadGetPriority EventID(EventLevelAPI, EvtRtxThreadNo, 0x0BU)
#define EvtRtxThreadYield EventID(EventLevelAPI, EvtRtxThreadNo, 0x0CU)
#define EvtRtxThreadSuspend EventID(EventLevelAPI, EvtRtxThreadNo, 0x0DU)
#define EvtRtxThreadSuspended EventID(EventLevelOp, EvtRtxThreadNo, 0x0EU)
#define EvtRtxThreadResume EventID(EventLevelAPI, EvtRtxThreadNo, 0x0FU)
#define EvtRtxThreadResumed EventID(EventLevelOp, EvtRtxThreadNo, 0x10U)
#define EvtRtxThreadDetach EventID(EventLevelAPI, EvtRtxThreadNo, 0x11U)
#define EvtRtxThreadDetached EventID(EventLevelOp, EvtRtxThreadNo, 0x12U)
#define EvtRtxThreadJoin EventID(EventLevelAPI, EvtRtxThreadNo, 0x13U)
#define EvtRtxThreadJoinPending EventID(EventLevelOp, EvtRtxThreadNo, 0x14U)
#define EvtRtxThreadJoined EventID(EventLevelOp, EvtRtxThreadNo, 0x15U)
#define EvtRtxThreadBlocked EventID(EventLevelDetail, EvtRtxThreadNo, 0x16U)
#define EvtRtxThreadUnblocked EventID(EventLevelDetail, EvtRtxThreadNo, 0x17U)
#define EvtRtxThreadPreempted EventID(EventLevelDetail, EvtRtxThreadNo, 0x18U)
#define EvtRtxThreadSwitched EventID(EventLevelOp, EvtRtxThreadNo, 0x19U)
#define EvtRtxThreadExit EventID(EventLevelAPI, EvtRtxThreadNo, 0x1AU)
#define EvtRtxThreadTerminate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1BU)
#define EvtRtxThreadDestroyed EventID(EventLevelOp, EvtRtxThreadNo, 0x1CU)
#define EvtRtxThreadFeedWatchdog EventID(EventLevelAPI, EvtRtxThreadNo, 0x2EU)
#define EvtRtxThreadFeedWatchdogDone EventID(EventLevelOp, EvtRtxThreadNo, 0x2FU)
#define EvtRtxThreadProtectPrivileged EventID(EventLevelAPI, EvtRtxThreadNo, 0x32U)
#define EvtRtxThreadPrivilegedProtected EventID(EventLevelOp, EvtRtxThreadNo, 0x33U)
#define EvtRtxThreadGetCount EventID(EventLevelAPI, EvtRtxThreadNo, 0x1DU)
#define EvtRtxThreadEnumerate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1EU)
#define EvtRtxThreadSuspendClass EventID(EventLevelAPI, EvtRtxThreadNo, 0x34U)
#define EvtRtxThreadResumeClass EventID(EventLevelAPI, EvtRtxThreadNo, 0x35U)
#define EvtRtxThreadTerminateZone EventID(EventLevelAPI, EvtRtxThreadNo, 0x36U)
#define EvtRtxThreadWatchdogExpired EventID(EventLevelError, EvtRtxThreadNo, 0x37U)
/// Event IDs for "RTX Thread Flags"
#define EvtRtxThreadFlagsError EventID(EventLevelError, EvtRtxThreadFlagsNo, 0x00U)
#define EvtRtxThreadFlagsSet EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x01U)
#define EvtRtxThreadFlagsSetDone EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x02U)
#define EvtRtxThreadFlagsClear EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x03U)
#define EvtRtxThreadFlagsClearDone EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x04U)
#define EvtRtxThreadFlagsGet EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x05U)
#define EvtRtxThreadFlagsWait EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x06U)
#define EvtRtxThreadFlagsWaitPending EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x07U)
#define EvtRtxThreadFlagsWaitTimeout EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x08U)
#define EvtRtxThreadFlagsWaitCompleted EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x09U)
#define EvtRtxThreadFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x0AU)
/// Event IDs for "RTX Generic Wait"
#define EvtRtxDelayError EventID(EventLevelError, EvtRtxWaitNo, 0x00U)
#define EvtRtxDelay EventID(EventLevelAPI, EvtRtxWaitNo, 0x01U)
#define EvtRtxDelayUntil EventID(EventLevelAPI, EvtRtxWaitNo, 0x02U)
#define EvtRtxDelayStarted EventID(EventLevelOp, EvtRtxWaitNo, 0x03U)
#define EvtRtxDelayUntilStarted EventID(EventLevelOp, EvtRtxWaitNo, 0x04U)
#define EvtRtxDelayCompleted EventID(EventLevelOp, EvtRtxWaitNo, 0x05U)
/// Event IDs for "RTX Timer"
#define EvtRtxTimerError EventID(EventLevelError, EvtRtxTimerNo, 0x00U)
#define EvtRtxTimerCallback EventID(EventLevelOp, EvtRtxTimerNo, 0x01U)
#define EvtRtxTimerNew EventID(EventLevelAPI, EvtRtxTimerNo, 0x02U)
#define EvtRtxTimerCreated EventID(EventLevelOp, EvtRtxTimerNo, 0x04U)
#define EvtRtxTimerGetName EventID(EventLevelAPI, EvtRtxTimerNo, 0x05U)
#define EvtRtxTimerStart EventID(EventLevelAPI, EvtRtxTimerNo, 0x07U)
#define EvtRtxTimerStarted EventID(EventLevelOp, EvtRtxTimerNo, 0x08U)
#define EvtRtxTimerStop EventID(EventLevelAPI, EvtRtxTimerNo, 0x09U)
#define EvtRtxTimerStopped EventID(EventLevelOp, EvtRtxTimerNo, 0x0AU)
#define EvtRtxTimerIsRunning EventID(EventLevelAPI, EvtRtxTimerNo, 0x0BU)
#define EvtRtxTimerDelete EventID(EventLevelAPI, EvtRtxTimerNo, 0x0CU)
#define EvtRtxTimerDestroyed EventID(EventLevelOp, EvtRtxTimerNo, 0x0DU)
/// Event IDs for "RTX Event Flags"
#define EvtRtxEventFlagsError EventID(EventLevelError, EvtRtxEventFlagsNo, 0x00U)
#define EvtRtxEventFlagsNew EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x01U)
#define EvtRtxEventFlagsCreated EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x03U)
#define EvtRtxEventFlagsGetName EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x04U)
#define EvtRtxEventFlagsSet EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x06U)
#define EvtRtxEventFlagsSetDone EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x07U)
#define EvtRtxEventFlagsClear EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x08U)
#define EvtRtxEventFlagsClearDone EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x09U)
#define EvtRtxEventFlagsGet EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x0AU)
#define EvtRtxEventFlagsWait EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x0BU)
#define EvtRtxEventFlagsWaitPending EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0CU)
#define EvtRtxEventFlagsWaitTimeout EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0DU)
#define EvtRtxEventFlagsWaitCompleted EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0EU)
#define EvtRtxEventFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0FU)
#define EvtRtxEventFlagsDelete EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x10U)
#define EvtRtxEventFlagsDestroyed EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x11U)
/// Event IDs for "RTX Mutex"
#define EvtRtxMutexError EventID(EventLevelError, EvtRtxMutexNo, 0x00U)
#define EvtRtxMutexNew EventID(EventLevelAPI, EvtRtxMutexNo, 0x01U)
#define EvtRtxMutexCreated EventID(EventLevelOp, EvtRtxMutexNo, 0x03U)
#define EvtRtxMutexGetName EventID(EventLevelAPI, EvtRtxMutexNo, 0x04U)
#define EvtRtxMutexAcquire EventID(EventLevelAPI, EvtRtxMutexNo, 0x06U)
#define EvtRtxMutexAcquirePending EventID(EventLevelOp, EvtRtxMutexNo, 0x07U)
#define EvtRtxMutexAcquireTimeout EventID(EventLevelOp, EvtRtxMutexNo, 0x08U)
#define EvtRtxMutexAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x09U)
#define EvtRtxMutexNotAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x0AU)
#define EvtRtxMutexRelease EventID(EventLevelAPI, EvtRtxMutexNo, 0x0BU)
#define EvtRtxMutexReleased EventID(EventLevelOp, EvtRtxMutexNo, 0x0CU)
#define EvtRtxMutexGetOwner EventID(EventLevelAPI, EvtRtxMutexNo, 0x0DU)
#define EvtRtxMutexDelete EventID(EventLevelAPI, EvtRtxMutexNo, 0x0EU)
#define EvtRtxMutexDestroyed EventID(EventLevelOp, EvtRtxMutexNo, 0x0FU)
/// Event IDs for "RTX Semaphore"
#define EvtRtxSemaphoreError EventID(EventLevelError, EvtRtxSemaphoreNo, 0x00U)
#define EvtRtxSemaphoreNew EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x01U)
#define EvtRtxSemaphoreCreated EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x03U)
#define EvtRtxSemaphoreGetName EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x04U)
#define EvtRtxSemaphoreAcquire EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x06U)
#define EvtRtxSemaphoreAcquirePending EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x07U)
#define EvtRtxSemaphoreAcquireTimeout EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x08U)
#define EvtRtxSemaphoreAcquired EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x09U)
#define EvtRtxSemaphoreNotAcquired EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0AU)
#define EvtRtxSemaphoreRelease EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0BU)
#define EvtRtxSemaphoreReleased EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0CU)
#define EvtRtxSemaphoreGetCount EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0DU)
#define EvtRtxSemaphoreDelete EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0EU)
#define EvtRtxSemaphoreDestroyed EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0FU)
/// Event IDs for "RTX Memory Pool"
#define EvtRtxMemoryPoolError EventID(EventLevelError, EvtRtxMemoryPoolNo, 0x00U)
#define EvtRtxMemoryPoolNew EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x01U)
#define EvtRtxMemoryPoolCreated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x03U)
#define EvtRtxMemoryPoolGetName EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x04U)
#define EvtRtxMemoryPoolAlloc EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x06U)
#define EvtRtxMemoryPoolAllocPending EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x07U)
#define EvtRtxMemoryPoolAllocTimeout EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x08U)
#define EvtRtxMemoryPoolAllocated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x09U)
#define EvtRtxMemoryPoolAllocFailed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0AU)
#define EvtRtxMemoryPoolFree EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0BU)
#define EvtRtxMemoryPoolDeallocated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0CU)
#define EvtRtxMemoryPoolFreeFailed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0DU)
#define EvtRtxMemoryPoolGetCapacity EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0EU)
#define EvtRtxMemoryPoolGetBlockSize EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0FU)
#define EvtRtxMemoryPoolGetCount EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x10U)
#define EvtRtxMemoryPoolGetSpace EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x11U)
#define EvtRtxMemoryPoolDelete EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x12U)
#define EvtRtxMemoryPoolDestroyed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x13U)
/// Event IDs for "RTX Message Queue"
#define EvtRtxMessageQueueError EventID(EventLevelError, EvtRtxMessageQueueNo, 0x00U)
#define EvtRtxMessageQueueNew EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x01U)
#define EvtRtxMessageQueueCreated EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x03U)
#define EvtRtxMessageQueueGetName EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x04U)
#define EvtRtxMessageQueuePut EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x06U)
#define EvtRtxMessageQueuePutPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x07U)
#define EvtRtxMessageQueuePutTimeout EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x08U)
#define EvtRtxMessageQueueInsertPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x09U)
#define EvtRtxMessageQueueInserted EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0AU)
#define EvtRtxMessageQueueNotInserted EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0BU)
#define EvtRtxMessageQueueGet EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x0CU)
#define EvtRtxMessageQueueGetPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0DU)
#define EvtRtxMessageQueueGetTimeout EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0EU)
#define EvtRtxMessageQueueRetrieved EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0FU)
#define EvtRtxMessageQueueNotRetrieved EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x10U)
#define EvtRtxMessageQueueGetCapacity EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x11U)
#define EvtRtxMessageQueueGetMsgSize EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x12U)
#define EvtRtxMessageQueueGetCount EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x13U)
#define EvtRtxMessageQueueGetSpace EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x14U)
#define EvtRtxMessageQueueReset EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x15U)
#define EvtRtxMessageQueueResetDone EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x16U)
#define EvtRtxMessageQueueDelete EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x17U)
#define EvtRtxMessageQueueDestroyed EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x18U)
#endif // RTE_Compiler_EventRecorder
//lint -esym(522, EvrRtx*) "Functions 'EvrRtx*' can be overridden (do not lack side-effects)"
// ==== Memory Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))
__WEAK void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U);
#else
(void)mem;
(void)size;
(void)result;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))
__WEAK void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block);
#else
(void)mem;
(void)size;
(void)type;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))
__WEAK void EvrRtxMemoryFree (void *mem, void *block, uint32_t result) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U);
#else
(void)mem;
(void)block;
(void)result;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))
__WEAK void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem);
#else
(void)mp_info;
(void)block_count;
(void)block_size;
(void)block_mem;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))
__WEAK void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block);
#else
(void)mp_info;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))
__WEAK void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U);
#else
(void)mp_info;
(void)block;
(void)status;
#endif
}
#endif
// ==== Kernel Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))
__WEAK void EvrRtxKernelError (int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U);
#else
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))
__WEAK void EvrRtxKernelInitialize (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelInitialize, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE))
__WEAK void EvrRtxKernelInitialized (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelInitialized, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))
__WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U);
#else
(void)version;
(void)id_buf;
(void)id_size;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))
__WEAK void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size) {
#if defined(RTE_Compiler_EventRecorder)
if (version != NULL) {
(void)EventRecord2(EvtRtxKernelInfoRetrieved, version->api, version->kernel);
}
if (id_buf != NULL) {
(void)EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, id_size);
}
#else
(void)version;
(void)id_buf;
(void)id_size;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))
__WEAK void EvrRtxKernelGetState (osKernelState_t state) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U);
#else
(void)state;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))
__WEAK void EvrRtxKernelStart (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelStart, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))
__WEAK void EvrRtxKernelStarted (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelStarted, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))
__WEAK void EvrRtxKernelLock (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelLock, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))
__WEAK void EvrRtxKernelLocked (int32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U);
#else
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))
__WEAK void EvrRtxKernelUnlock (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelUnlock, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))
__WEAK void EvrRtxKernelUnlocked (int32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U);
#else
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))
__WEAK void EvrRtxKernelRestoreLock (int32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U);
#else
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))
__WEAK void EvrRtxKernelLockRestored (int32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U);
#else
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))
__WEAK void EvrRtxKernelSuspend (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelSuspend, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))
__WEAK void EvrRtxKernelSuspended (uint32_t sleep_ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U);
#else
(void)sleep_ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))
__WEAK void EvrRtxKernelResume (uint32_t sleep_ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U);
#else
(void)sleep_ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))
__WEAK void EvrRtxKernelResumed (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelResumed, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECT_DISABLE))
__WEAK void EvrRtxKernelProtect (uint32_t safety_class) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelProtect, safety_class, 0U);
#else
(void)safety_class;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECTED_DISABLE))
__WEAK void EvrRtxKernelProtected (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelProtected, 0U, 0U);
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))
__WEAK void EvrRtxKernelGetTickCount (uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelGetTickCount, count, 0U);
#else
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))
__WEAK void EvrRtxKernelGetTickFreq (uint32_t freq) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U);
#else
(void)freq;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))
__WEAK void EvrRtxKernelGetSysTimerCount (uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U);
#else
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))
__WEAK void EvrRtxKernelGetSysTimerFreq (uint32_t freq) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U);
#else
(void)freq;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE))
__WEAK void EvrRtxKernelErrorNotify (uint32_t code, void *object_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelErrorNotify, code, (uint32_t)object_id);
#else
(void)code;
(void)object_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_DESTROY_CLASS_DISABLE))
__WEAK void EvrRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxKernelDestroyClass, safety_class, mode);
#else
(void)safety_class;
(void)mode;
#endif
}
#endif
// ==== Thread Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))
__WEAK void EvrRtxThreadError (osThreadId_t thread_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status);
#else
(void)thread_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))
__WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U);
#else
(void)func;
(void)argument;
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))
__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
if (name != NULL) {
(void)EventRecord2(EvtRtxThreadCreated_Name, (uint32_t)thread_id, (uint32_t)name);
} else {
(void)EventRecord2(EvtRtxThreadCreated_Addr, (uint32_t)thread_id, thread_addr);
}
#else
(void)thread_id;
(void)thread_addr;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))
__WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name);
#else
(void)thread_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_CLASS_DISABLE))
__WEAK void EvrRtxThreadGetClass (osThreadId_t thread_id, uint32_t safety_class) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetClass, (uint32_t)thread_id, safety_class);
#else
(void)thread_id;
(void)safety_class;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ZONE_DISABLE))
__WEAK void EvrRtxThreadGetZone (osThreadId_t thread_id, uint32_t zone) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetZone, (uint32_t)thread_id, zone);
#else
(void)thread_id;
(void)zone;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))
__WEAK void EvrRtxThreadGetId (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))
__WEAK void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state);
#else
(void)thread_id;
(void)state;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))
__WEAK void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size);
#else
(void)thread_id;
(void)stack_size;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))
__WEAK void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space);
#else
(void)thread_id;
(void)stack_space;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))
__WEAK void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority);
#else
(void)thread_id;
(void)priority;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE))
__WEAK void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadPriorityUpdated, (uint32_t)thread_id, (uint32_t)priority);
#else
(void)thread_id;
(void)priority;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))
__WEAK void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority);
#else
(void)thread_id;
(void)priority;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))
__WEAK void EvrRtxThreadYield (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadYield, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))
__WEAK void EvrRtxThreadSuspend (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))
__WEAK void EvrRtxThreadSuspended (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))
__WEAK void EvrRtxThreadResume (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))
__WEAK void EvrRtxThreadResumed (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))
__WEAK void EvrRtxThreadDetach (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))
__WEAK void EvrRtxThreadDetached (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))
__WEAK void EvrRtxThreadJoin (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))
__WEAK void EvrRtxThreadJoinPending (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))
__WEAK void EvrRtxThreadJoined (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))
__WEAK void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout);
#else
(void)thread_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))
__WEAK void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val);
#else
(void)thread_id;
(void)ret_val;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE))
__WEAK void EvrRtxThreadPreempted (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadPreempted, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE))
__WEAK void EvrRtxThreadSwitched (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadSwitched, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))
__WEAK void EvrRtxThreadExit (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadExit, 0U, 0U);
#else
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))
__WEAK void EvrRtxThreadTerminate (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))
__WEAK void EvrRtxThreadDestroyed (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DISABLE))
__WEAK void EvrRtxThreadFeedWatchdog (uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFeedWatchdog, ticks, 0U);
#else
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DONE_DISABLE))
__WEAK void EvrRtxThreadFeedWatchdogDone (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFeedWatchdogDone, 0U, 0U);
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PROTECT_PRIVILEGED_DISABLE))
__WEAK void EvrRtxThreadProtectPrivileged (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadProtectPrivileged, 0U, 0U);
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIVILEGED_PROTECTED_DISABLE))
__WEAK void EvrRtxThreadPrivilegedProtected (void) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadPrivilegedProtected, 0U, 0U);
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))
__WEAK void EvrRtxThreadGetCount (uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadGetCount, count, 0U);
#else
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))
__WEAK void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U);
#else
(void)thread_array;
(void)array_items;
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_CLASS_DISABLE))
__WEAK void EvrRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadSuspendClass, safety_class, (uint32_t)mode);
#else
(void)safety_class;
(void)mode;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_CLASS_DISABLE))
__WEAK void EvrRtxThreadResumeClass (uint32_t safety_class, uint32_t mode) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadResumeClass, safety_class, (uint32_t)mode);
#else
(void)safety_class;
(void)mode;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_ZONE_DISABLE))
__WEAK void EvrRtxThreadTerminateZone (uint32_t zone) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadTerminateZone, zone, 0U);
#else
(void)zone;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_WATCHDOG_EXPIRED_DISABLE))
__WEAK void EvrRtxThreadWatchdogExpired (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadWatchdogExpired, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
// ==== Thread Flags Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE))
__WEAK void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsError, (uint32_t)thread_id, (uint32_t)status);
#else
(void)thread_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))
__WEAK void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags);
#else
(void)thread_id;
(void)flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))
__WEAK void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags);
#else
(void)thread_id;
(void)thread_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))
__WEAK void EvrRtxThreadFlagsClear (uint32_t flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsClear, flags, 0U);
#else
(void)flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))
__WEAK void EvrRtxThreadFlagsClearDone (uint32_t thread_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U);
#else
(void)thread_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))
__WEAK void EvrRtxThreadFlagsGet (uint32_t thread_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U);
#else
(void)thread_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))
__WEAK void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U);
#else
(void)flags;
(void)options;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))
__WEAK void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U);
#else
(void)flags;
(void)options;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))
__WEAK void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsWaitTimeout, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))
__WEAK void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, (uint32_t)thread_id);
#else
(void)flags;
(void)options;
(void)thread_flags;
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
__WEAK void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options);
#else
(void)flags;
(void)options;
#endif
}
#endif
// ==== Generic Wait Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE))
__WEAK void EvrRtxDelayError (int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelayError, (uint32_t)status, 0U);
#else
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE))
__WEAK void EvrRtxDelay (uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelay, ticks, 0U);
#else
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE))
__WEAK void EvrRtxDelayUntil (uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelayUntil, ticks, 0U);
#else
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE))
__WEAK void EvrRtxDelayStarted (uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelayStarted, ticks, 0U);
#else
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE))
__WEAK void EvrRtxDelayUntilStarted (uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelayUntilStarted, ticks, 0U);
#else
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE))
__WEAK void EvrRtxDelayCompleted (osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxDelayCompleted, (uint32_t)thread_id, 0U);
#else
(void)thread_id;
#endif
}
#endif
// ==== Timer Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))
__WEAK void EvrRtxTimerError (osTimerId_t timer_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status);
#else
(void)timer_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))
__WEAK void EvrRtxTimerCallback (osTimerFunc_t func, void *argument) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument);
#else
(void)func;
(void)argument;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))
__WEAK void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr);
#else
(void)func;
(void)type;
(void)argument;
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))
__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, (uint32_t)name);
#else
(void)timer_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))
__WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name);
#else
(void)timer_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))
__WEAK void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks);
#else
(void)timer_id;
(void)ticks;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))
__WEAK void EvrRtxTimerStarted (osTimerId_t timer_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U);
#else
(void)timer_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))
__WEAK void EvrRtxTimerStop (osTimerId_t timer_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U);
#else
(void)timer_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))
__WEAK void EvrRtxTimerStopped (osTimerId_t timer_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U);
#else
(void)timer_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))
__WEAK void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running);
#else
(void)timer_id;
(void)running;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))
__WEAK void EvrRtxTimerDelete (osTimerId_t timer_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U);
#else
(void)timer_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))
__WEAK void EvrRtxTimerDestroyed (osTimerId_t timer_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U);
#else
(void)timer_id;
#endif
}
#endif
// ==== Event Flags Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))
__WEAK void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status);
#else
(void)ef_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))
__WEAK void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U);
#else
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))
__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, (uint32_t)name);
#else
(void)ef_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))
__WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name);
#else
(void)ef_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))
__WEAK void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags);
#else
(void)ef_id;
(void)flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))
__WEAK void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags);
#else
(void)ef_id;
(void)event_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))
__WEAK void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags);
#else
(void)ef_id;
(void)flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))
__WEAK void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags);
#else
(void)ef_id;
(void)event_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))
__WEAK void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags);
#else
(void)ef_id;
(void)event_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))
__WEAK void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout);
#else
(void)ef_id;
(void)flags;
(void)options;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))
__WEAK void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout);
#else
(void)ef_id;
(void)flags;
(void)options;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))
__WEAK void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U);
#else
(void)ef_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))
__WEAK void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags);
#else
(void)ef_id;
(void)flags;
(void)options;
(void)event_flags;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))
__WEAK void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U);
#else
(void)ef_id;
(void)flags;
(void)options;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))
__WEAK void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U);
#else
(void)ef_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))
__WEAK void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U);
#else
(void)ef_id;
#endif
}
#endif
// ==== Mutex Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))
__WEAK void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status);
#else
(void)mutex_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))
__WEAK void EvrRtxMutexNew (const osMutexAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U);
#else
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))
__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, (uint32_t)name);
#else
(void)mutex_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))
__WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name);
#else
(void)mutex_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))
__WEAK void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout);
#else
(void)mutex_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))
__WEAK void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout);
#else
(void)mutex_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))
__WEAK void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U);
#else
(void)mutex_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))
__WEAK void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock);
#else
(void)mutex_id;
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))
__WEAK void EvrRtxMutexNotAcquired (osMutexId_t mutex_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U);
#else
(void)mutex_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))
__WEAK void EvrRtxMutexRelease (osMutexId_t mutex_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U);
#else
(void)mutex_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))
__WEAK void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock);
#else
(void)mutex_id;
(void)lock;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))
__WEAK void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id);
#else
(void)mutex_id;
(void)thread_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))
__WEAK void EvrRtxMutexDelete (osMutexId_t mutex_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U);
#else
(void)mutex_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))
__WEAK void EvrRtxMutexDestroyed (osMutexId_t mutex_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U);
#else
(void)mutex_id;
#endif
}
#endif
// ==== Semaphore Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))
__WEAK void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status);
#else
(void)semaphore_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))
__WEAK void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U);
#else
(void)max_count;
(void)initial_count;
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))
__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, (uint32_t)name);
#else
(void)semaphore_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))
__WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name);
#else
#endif
(void)semaphore_id;
(void)name;
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))
__WEAK void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout);
#else
(void)semaphore_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))
__WEAK void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout);
#else
(void)semaphore_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))
__WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U);
#else
(void)semaphore_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))
__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, tokens);
#else
(void)semaphore_id;
(void)tokens;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))
__WEAK void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U);
#else
(void)semaphore_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))
__WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U);
#else
(void)semaphore_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))
__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, tokens);
#else
(void)semaphore_id;
(void)tokens;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))
__WEAK void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count);
#else
(void)semaphore_id;
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))
__WEAK void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U);
#else
(void)semaphore_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))
__WEAK void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U);
#else
(void)semaphore_id;
#endif
}
#endif
// ==== Memory Pool Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))
__WEAK void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status);
#else
(void)mp_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))
__WEAK void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U);
#else
(void)block_count;
(void)block_size;
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))
__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, (uint32_t)name);
#else
(void)mp_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))
__WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name);
#else
(void)mp_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))
__WEAK void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout);
#else
(void)mp_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))
__WEAK void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout);
#else
(void)mp_id;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))
__WEAK void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U);
#else
(void)mp_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))
__WEAK void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block);
#else
(void)mp_id;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))
__WEAK void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U);
#else
(void)mp_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))
__WEAK void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block);
#else
(void)mp_id;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))
__WEAK void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block);
#else
(void)mp_id;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))
__WEAK void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block);
#else
(void)mp_id;
(void)block;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))
__WEAK void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity);
#else
(void)mp_id;
(void)capacity;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))
__WEAK void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size);
#else
(void)mp_id;
(void)block_size;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))
__WEAK void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count);
#else
(void)mp_id;
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))
__WEAK void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space);
#else
(void)mp_id;
(void)space;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))
__WEAK void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U);
#else
(void)mp_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))
__WEAK void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U);
#else
(void)mp_id;
#endif
}
#endif
// ==== Message Queue Events ====
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))
__WEAK void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status);
#else
(void)mq_id;
(void)status;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))
__WEAK void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U);
#else
(void)msg_count;
(void)msg_size;
(void)attr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))
__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, (uint32_t)name);
#else
(void)mq_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))
__WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name);
#else
(void)mq_id;
(void)name;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))
__WEAK void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);
#else
(void)mq_id;
(void)msg_ptr;
(void)msg_prio;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))
__WEAK void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);
#else
(void)mq_id;
(void)msg_ptr;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))
__WEAK void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))
__WEAK void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr);
#else
(void)mq_id;
(void)msg_ptr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))
__WEAK void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);
#else
(void)mq_id;
(void)msg_ptr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))
__WEAK void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);
#else
(void)mq_id;
(void)msg_ptr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))
__WEAK void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);
#else
(void)mq_id;
(void)msg_ptr;
(void)msg_prio;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))
__WEAK void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);
#else
(void)mq_id;
(void)msg_ptr;
(void)timeout;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))
__WEAK void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))
__WEAK void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);
#else
(void)mq_id;
(void)msg_ptr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))
__WEAK void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);
#else
(void)mq_id;
(void)msg_ptr;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))
__WEAK void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity);
#else
(void)mq_id;
(void)capacity;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))
__WEAK void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size);
#else
(void)mq_id;
(void)msg_size;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))
__WEAK void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count);
#else
(void)mq_id;
(void)count;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))
__WEAK void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space);
#else
(void)mq_id;
(void)space;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))
__WEAK void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))
__WEAK void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))
__WEAK void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))
__WEAK void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id) {
#if defined(RTE_Compiler_EventRecorder)
(void)EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U);
#else
(void)mq_id;
#endif
}
#endif
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_evr.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 26,359 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Memory functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// Memory Pool Header structure
typedef struct {
uint32_t size; // Memory Pool size
uint32_t used; // Used Memory
} mem_head_t;
// Memory Block Header structure
typedef struct mem_block_s {
struct mem_block_s *next; // Next Memory Block in list
uint32_t info; // Block Info or max used Memory (in last block)
} mem_block_t;
// Memory Block Info: Length = <31:2>:'00', Type = <1:0>
#define MB_INFO_LEN_MASK 0xFFFFFFFCU // Length mask
#define MB_INFO_TYPE_MASK 0x00000003U // Type mask
// Memory Head Pointer
__STATIC_INLINE mem_head_t *MemHeadPtr (void *mem) {
//lint -e{9079} -e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
return ((mem_head_t *)mem);
}
// Memory Block Pointer
__STATIC_INLINE mem_block_t *MemBlockPtr (void *mem, uint32_t offset) {
uint32_t addr;
mem_block_t *ptr;
//lint --e{923} --e{9078} "cast between pointer and unsigned int" [MISRA Note 8]
addr = (uint32_t)mem + offset;
ptr = (mem_block_t *)addr;
return ptr;
}
// ==== Library functions ====
/// Initialize Memory Pool with variable block size.
/// \param[in] mem pointer to memory pool.
/// \param[in] size size of a memory pool in bytes.
/// \return 1 - success, 0 - failure.
__WEAK uint32_t osRtxMemoryInit (void *mem, uint32_t size) {
mem_head_t *head;
mem_block_t *ptr;
// Check parameters
//lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7]
if ((mem == NULL) || (((uint32_t)mem & 7U) != 0U) || ((size & 7U) != 0U) ||
(size < (sizeof(mem_head_t) + (2U*sizeof(mem_block_t))))) {
EvrRtxMemoryInit(mem, size, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
// Initialize memory pool header
head = MemHeadPtr(mem);
head->size = size;
head->used = sizeof(mem_head_t) + sizeof(mem_block_t);
// Initialize first and last block header
ptr = MemBlockPtr(mem, sizeof(mem_head_t));
ptr->next = MemBlockPtr(mem, size - sizeof(mem_block_t));
ptr->next->next = NULL;
ptr->next->info = sizeof(mem_head_t) + sizeof(mem_block_t);
ptr->info = 0U;
EvrRtxMemoryInit(mem, size, 1U);
return 1U;
}
/// Allocate a memory block from a Memory Pool.
/// \param[in] mem pointer to memory pool.
/// \param[in] size size of a memory block in bytes.
/// \param[in] type memory block type: 0 - generic, 1 - control block
/// \return allocated memory block or NULL in case of no memory is available.
__WEAK void *osRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type) {
mem_block_t *ptr;
mem_block_t *p, *p_new;
uint32_t block_size;
uint32_t hole_size;
// Check parameters
if ((mem == NULL) || (size == 0U) || ((type & ~MB_INFO_TYPE_MASK) != 0U)) {
EvrRtxMemoryAlloc(mem, size, type, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Add block header to size
block_size = size + sizeof(mem_block_t);
// Make sure that block is 8-byte aligned
block_size = (block_size + 7U) & ~((uint32_t)7U);
// Search for hole big enough
p = MemBlockPtr(mem, sizeof(mem_head_t));
for (;;) {
//lint -e{923} -e{9078} "cast from pointer to unsigned int"
hole_size = (uint32_t)p->next - (uint32_t)p;
hole_size -= p->info & MB_INFO_LEN_MASK;
if (hole_size >= block_size) {
// Hole found
break;
}
p = p->next;
if (p->next == NULL) {
// Failed (end of list)
EvrRtxMemoryAlloc(mem, size, type, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
// Update used memory
(MemHeadPtr(mem))->used += block_size;
// Update max used memory
p_new = MemBlockPtr(mem, (MemHeadPtr(mem))->size - sizeof(mem_block_t));
if (p_new->info < (MemHeadPtr(mem))->used) {
p_new->info = (MemHeadPtr(mem))->used;
}
// Allocate block
if (p->info == 0U) {
// No block allocated, set info of first element
p->info = block_size | type;
ptr = MemBlockPtr(p, sizeof(mem_block_t));
} else {
// Insert new element into the list
p_new = MemBlockPtr(p, p->info & MB_INFO_LEN_MASK);
p_new->next = p->next;
p_new->info = block_size | type;
p->next = p_new;
ptr = MemBlockPtr(p_new, sizeof(mem_block_t));
}
EvrRtxMemoryAlloc(mem, size, type, ptr);
return ptr;
}
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] mem pointer to memory pool.
/// \param[in] block memory block to be returned to the memory pool.
/// \return 1 - success, 0 - failure.
__WEAK uint32_t osRtxMemoryFree (void *mem, void *block) {
const mem_block_t *ptr;
mem_block_t *p, *p_prev;
// Check parameters
if ((mem == NULL) || (block == NULL)) {
EvrRtxMemoryFree(mem, block, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
// Memory block header
ptr = MemBlockPtr(block, 0U);
ptr--;
// Search for block header
p_prev = NULL;
p = MemBlockPtr(mem, sizeof(mem_head_t));
while (p != ptr) {
p_prev = p;
p = p->next;
if (p == NULL) {
// Not found
EvrRtxMemoryFree(mem, block, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
}
// Update used memory
(MemHeadPtr(mem))->used -= p->info & MB_INFO_LEN_MASK;
// Free block
if (p_prev == NULL) {
// Release first block, only set info to 0
p->info = 0U;
} else {
// Discard block from chained list
p_prev->next = p->next;
}
EvrRtxMemoryFree(mem, block, 1U);
return 1U;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_memory.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,835 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Mutex functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxMutexMemUsage \
__attribute__((section(".data.os.mutex.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Verify that Mutex object pointer is valid.
/// \param[in] mutex mutex object.
/// \return true - valid, false - invalid.
static bool_t IsMutexPtrValid (const os_mutex_t *mutex) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_mutex_cb_start__;
uint32_t cb_length = (uint32_t)&__os_mutex_cb_length__;
// Check the section boundaries
if (((uint32_t)mutex - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)mutex - cb_start) % sizeof(os_mutex_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (mutex == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Release Mutex list when owner Thread terminates.
/// \param[in] mutex_list mutex list.
void osRtxMutexOwnerRelease (os_mutex_t *mutex_list) {
os_mutex_t *mutex;
os_mutex_t *mutex_next;
os_thread_t *thread;
mutex = mutex_list;
while (mutex != NULL) {
mutex_next = mutex->owner_next;
// Check if Mutex is Robust
if ((mutex->attr & osMutexRobust) != 0U) {
// Clear Lock counter
mutex->lock = 0U;
EvrRtxMutexReleased(mutex, 0U);
// Check if Thread is waiting for a Mutex
if (mutex->thread_list != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mutex));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
// Thread is the new Mutex owner
mutex->owner_thread = thread;
mutex->owner_prev = NULL;
mutex->owner_next = thread->mutex_list;
if (thread->mutex_list != NULL) {
thread->mutex_list->owner_prev = mutex;
}
thread->mutex_list = mutex;
mutex->lock = 1U;
EvrRtxMutexAcquired(mutex, 1U);
}
}
mutex = mutex_next;
}
}
/// Restore Mutex owner Thread priority.
/// \param[in] mutex mutex object.
/// \param[in] thread_wakeup thread wakeup object.
void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup) {
const os_mutex_t *mutex0;
os_thread_t *thread;
const os_thread_t *thread0;
int8_t priority;
// Restore owner Thread priority
if ((mutex->attr & osMutexPrioInherit) != 0U) {
thread = mutex->owner_thread;
priority = thread->priority_base;
mutex0 = thread->mutex_list;
// Check Mutexes owned by Thread
do {
if ((mutex0->attr & osMutexPrioInherit) != 0U) {
// Check Threads waiting for Mutex
thread0 = mutex0->thread_list;
if (thread0 == thread_wakeup) {
// Skip thread that is waken-up
thread0 = thread0->thread_next;
}
if ((thread0 != NULL) && (thread0->priority > priority)) {
// Higher priority Thread is waiting for Mutex
priority = thread0->priority;
}
}
mutex0 = mutex0->owner_next;
} while (mutex0 != NULL);
if (thread->priority != priority) {
thread->priority = priority;
osRtxThreadListSort(thread);
}
}
}
/// Unlock Mutex owner when mutex is deleted.
/// \param[in] mutex mutex object.
/// \return true - successful, false - not locked.
static bool_t osRtxMutexOwnerUnlock (os_mutex_t *mutex) {
const os_mutex_t *mutex0;
os_thread_t *thread;
int8_t priority;
// Check if Mutex is locked
if (mutex->lock == 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
thread = mutex->owner_thread;
// Remove Mutex from Thread owner list
if (mutex->owner_next != NULL) {
mutex->owner_next->owner_prev = mutex->owner_prev;
}
if (mutex->owner_prev != NULL) {
mutex->owner_prev->owner_next = mutex->owner_next;
} else {
thread->mutex_list = mutex->owner_next;
}
// Restore owner Thread priority
priority = thread->priority_base;
mutex0 = thread->mutex_list;
// Check Mutexes owned by Thread
while (mutex0 != NULL) {
if ((mutex0->attr & osMutexPrioInherit) != 0U) {
if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {
// Higher priority Thread is waiting for Mutex
priority = mutex0->thread_list->priority;
}
}
mutex0 = mutex0->owner_next;
}
if (thread->priority != priority) {
thread->priority = priority;
osRtxThreadListSort(thread);
}
// Unblock waiting threads
while (mutex->thread_list != NULL) {
thread = osRtxThreadListGet(osRtxObject(mutex));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
}
mutex->lock = 0U;
return TRUE;
}
/// Destroy a Mutex object.
/// \param[in] mutex mutex object.
static void osRtxMutexDestroy (os_mutex_t *mutex) {
// Mark object as invalid
mutex->id = osRtxIdInvalid;
// Free object memory
if ((mutex->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex);
#else
if (osRtxInfo.mpi.mutex != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, mutex);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxMutexMemUsage.cnt_free++;
#endif
}
EvrRtxMutexDestroyed(mutex);
}
#ifdef RTX_SAFETY_CLASS
/// Delete a Mutex safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxMutexDeleteClass (uint32_t safety_class, uint32_t mode) {
os_mutex_t *mutex;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
mutex = (os_mutex_t *)(uint32_t)&__os_mutex_cb_start__;
length = (uint32_t)&__os_mutex_cb_length__;
while (length >= sizeof(os_mutex_t)) {
if ( (mutex->id == osRtxIdMutex) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((mutex->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((mutex->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
(void)osRtxMutexOwnerUnlock(mutex);
osRtxMutexDestroy(mutex);
}
length -= sizeof(os_mutex_t);
mutex++;
}
}
#endif
// ==== Service Calls ====
/// Create and Initialize a Mutex object.
/// \note API identical to osMutexNew
static osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) {
os_mutex_t *mutex;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
#endif
uint32_t attr_bits;
uint8_t flags;
const char *name;
// Process attributes
if (attr != NULL) {
name = attr->name;
attr_bits = attr->attr_bits;
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
mutex = attr->cb_mem;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxMutexError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (mutex != NULL) {
if (!IsMutexPtrValid(mutex) || (attr->cb_size != sizeof(os_mutex_t))) {
EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
attr_bits = 0U;
mutex = NULL;
}
// Allocate object memory if not provided
if (mutex == NULL) {
if (osRtxInfo.mpi.mutex != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mutex = osRtxMemoryPoolAlloc(osRtxInfo.mpi.mutex);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mutex = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_mutex_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (mutex != NULL) {
uint32_t used;
osRtxMutexMemUsage.cnt_alloc++;
used = osRtxMutexMemUsage.cnt_alloc - osRtxMutexMemUsage.cnt_free;
if (osRtxMutexMemUsage.max_used < used) {
osRtxMutexMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
if (mutex != NULL) {
// Initialize control block
mutex->id = osRtxIdMutex;
mutex->flags = flags;
mutex->attr = (uint8_t)(attr_bits & ~osRtxAttrClass_Msk);
mutex->name = name;
mutex->thread_list = NULL;
mutex->owner_thread = NULL;
mutex->owner_prev = NULL;
mutex->owner_next = NULL;
mutex->lock = 0U;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
mutex->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
mutex->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
EvrRtxMutexCreated(mutex, mutex->name);
} else {
EvrRtxMutexError(NULL, (int32_t)osErrorNoMemory);
}
return mutex;
}
/// Get name of a Mutex object.
/// \note API identical to osMutexGetName
static const char *svcRtxMutexGetName (osMutexId_t mutex_id) {
os_mutex_t *mutex = osRtxMutexId(mutex_id);
// Check parameters
if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {
EvrRtxMutexGetName(mutex, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxMutexGetName(mutex, mutex->name);
return mutex->name;
}
/// Acquire a Mutex or timeout if it is locked.
/// \note API identical to osMutexAcquire
static osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
os_mutex_t *mutex = osRtxMutexId(mutex_id);
os_thread_t *thread;
osStatus_t status;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
// Check parameters
if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {
EvrRtxMutexError(mutex, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
if ((thread->attr >> osRtxAttrClass_Pos) < (mutex->attr >> osRtxAttrClass_Pos)) {
EvrRtxMutexError(mutex, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check if Mutex is not locked
if (mutex->lock == 0U) {
// Acquire Mutex
mutex->owner_thread = thread;
mutex->owner_prev = NULL;
mutex->owner_next = thread->mutex_list;
if (thread->mutex_list != NULL) {
thread->mutex_list->owner_prev = mutex;
}
thread->mutex_list = mutex;
mutex->lock = 1U;
EvrRtxMutexAcquired(mutex, mutex->lock);
status = osOK;
} else {
// Check if Mutex is recursive and running Thread is the owner
if (((mutex->attr & osMutexRecursive) != 0U) && (mutex->owner_thread == thread)) {
// Try to increment lock counter
if (mutex->lock == osRtxMutexLockLimit) {
EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit);
status = osErrorResource;
} else {
mutex->lock++;
EvrRtxMutexAcquired(mutex, mutex->lock);
status = osOK;
}
} else {
// Check if timeout is specified
if (timeout != 0U) {
// Check if Priority inheritance protocol is enabled
if ((mutex->attr & osMutexPrioInherit) != 0U) {
// Raise priority of owner Thread if lower than priority of running Thread
if (mutex->owner_thread->priority < thread->priority) {
mutex->owner_thread->priority = thread->priority;
osRtxThreadListSort(mutex->owner_thread);
}
}
EvrRtxMutexAcquirePending(mutex, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout)) {
osRtxThreadListPut(osRtxObject(mutex), thread);
} else {
EvrRtxMutexAcquireTimeout(mutex);
}
status = osErrorTimeout;
} else {
EvrRtxMutexNotAcquired(mutex);
status = osErrorResource;
}
}
}
return status;
}
/// Release a Mutex that was acquired by osMutexAcquire.
/// \note API identical to osMutexRelease
static osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) {
os_mutex_t *mutex = osRtxMutexId(mutex_id);
const os_mutex_t *mutex0;
os_thread_t *thread;
int8_t priority;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
// Check parameters
if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {
EvrRtxMutexError(mutex, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Check if Mutex is not locked
if (mutex->lock == 0U) {
EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
// Check if running Thread is not the owner
if (mutex->owner_thread != thread) {
EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
// Decrement Lock counter
mutex->lock--;
EvrRtxMutexReleased(mutex, mutex->lock);
// Check Lock counter
if (mutex->lock == 0U) {
// Remove Mutex from Thread owner list
if (mutex->owner_next != NULL) {
mutex->owner_next->owner_prev = mutex->owner_prev;
}
if (mutex->owner_prev != NULL) {
mutex->owner_prev->owner_next = mutex->owner_next;
} else {
thread->mutex_list = mutex->owner_next;
}
// Restore running Thread priority
priority = thread->priority_base;
mutex0 = thread->mutex_list;
// Check mutexes owned by running Thread
while (mutex0 != NULL) {
if ((mutex0->attr & osMutexPrioInherit) != 0U) {
if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {
// Higher priority Thread is waiting for Mutex
priority = mutex0->thread_list->priority;
}
}
mutex0 = mutex0->owner_next;
}
thread->priority = priority;
// Check if Thread is waiting for a Mutex
if (mutex->thread_list != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mutex));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
// Thread is the new Mutex owner
mutex->owner_thread = thread;
mutex->owner_prev = NULL;
mutex->owner_next = thread->mutex_list;
if (thread->mutex_list != NULL) {
thread->mutex_list->owner_prev = mutex;
}
thread->mutex_list = mutex;
mutex->lock = 1U;
EvrRtxMutexAcquired(mutex, 1U);
}
osRtxThreadDispatch(NULL);
}
return osOK;
}
/// Get Thread which owns a Mutex object.
/// \note API identical to osMutexGetOwner
static osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) {
os_mutex_t *mutex = osRtxMutexId(mutex_id);
// Check parameters
if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {
EvrRtxMutexGetOwner(mutex, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Check if Mutex is not locked
if (mutex->lock == 0U) {
EvrRtxMutexGetOwner(mutex, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxMutexGetOwner(mutex, mutex->owner_thread);
return mutex->owner_thread;
}
/// Delete a Mutex object.
/// \note API identical to osMutexDelete
static osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) {
os_mutex_t *mutex = osRtxMutexId(mutex_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
// Check parameters
if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {
EvrRtxMutexError(mutex, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mutex->attr >> osRtxAttrClass_Pos))) {
EvrRtxMutexError(mutex, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Unlock the mutex owner
if (osRtxMutexOwnerUnlock(mutex)) {
osRtxThreadDispatch(NULL);
}
osRtxMutexDestroy(mutex);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_1(MutexNew, osMutexId_t, const osMutexAttr_t *)
SVC0_1(MutexGetName, const char *, osMutexId_t)
SVC0_2(MutexAcquire, osStatus_t, osMutexId_t, uint32_t)
SVC0_1(MutexRelease, osStatus_t, osMutexId_t)
SVC0_1(MutexGetOwner, osThreadId_t, osMutexId_t)
SVC0_1(MutexDelete, osStatus_t, osMutexId_t)
//lint --flb "Library End"
// ==== Public API ====
/// Create and Initialize a Mutex object.
osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
osMutexId_t mutex_id;
EvrRtxMutexNew(attr);
if (IsException() || IsIrqMasked()) {
EvrRtxMutexError(NULL, (int32_t)osErrorISR);
mutex_id = NULL;
} else {
mutex_id = __svcMutexNew(attr);
}
return mutex_id;
}
/// Get name of a Mutex object.
const char *osMutexGetName (osMutexId_t mutex_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxMutexGetName(mutex_id);
} else {
name = __svcMutexGetName(mutex_id);
}
return name;
}
/// Acquire a Mutex or timeout if it is locked.
osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
osStatus_t status;
EvrRtxMutexAcquire(mutex_id, timeout);
if (IsException() || IsIrqMasked()) {
EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMutexAcquire(mutex_id, timeout);
}
return status;
}
/// Release a Mutex that was acquired by \ref osMutexAcquire.
osStatus_t osMutexRelease (osMutexId_t mutex_id) {
osStatus_t status;
EvrRtxMutexRelease(mutex_id);
if (IsException() || IsIrqMasked()) {
EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMutexRelease(mutex_id);
}
return status;
}
/// Get Thread which owns a Mutex object.
osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
osThreadId_t thread;
if (IsException() || IsIrqMasked()) {
EvrRtxMutexGetOwner(mutex_id, NULL);
thread = NULL;
} else {
thread = __svcMutexGetOwner(mutex_id);
}
return thread;
}
/// Delete a Mutex object.
osStatus_t osMutexDelete (osMutexId_t mutex_id) {
osStatus_t status;
EvrRtxMutexDelete(mutex_id);
if (IsException() || IsIrqMasked()) {
EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMutexDelete(mutex_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_mutex.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,942 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Timer functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxTimerMemUsage \
__attribute__((section(".data.os.timer.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Insert Timer into the Timer List sorted by Time.
/// \param[in] timer timer object.
/// \param[in] tick timer tick.
static void TimerInsert (os_timer_t *timer, uint32_t tick) {
os_timer_t *prev, *next;
prev = NULL;
next = osRtxInfo.timer.list;
while ((next != NULL) && (next->tick <= tick)) {
tick -= next->tick;
prev = next;
next = next->next;
}
timer->tick = tick;
timer->prev = prev;
timer->next = next;
if (next != NULL) {
next->tick -= timer->tick;
next->prev = timer;
}
if (prev != NULL) {
prev->next = timer;
} else {
osRtxInfo.timer.list = timer;
}
}
/// Remove Timer from the Timer List.
/// \param[in] timer timer object.
static void TimerRemove (const os_timer_t *timer) {
if (timer->next != NULL) {
timer->next->tick += timer->tick;
timer->next->prev = timer->prev;
}
if (timer->prev != NULL) {
timer->prev->next = timer->next;
} else {
osRtxInfo.timer.list = timer->next;
}
}
/// Unlink Timer from the Timer List Head.
/// \param[in] timer timer object.
static void TimerUnlink (const os_timer_t *timer) {
if (timer->next != NULL) {
timer->next->prev = timer->prev;
}
osRtxInfo.timer.list = timer->next;
}
/// Verify that Timer object pointer is valid.
/// \param[in] timer timer object.
/// \return true - valid, false - invalid.
static bool_t IsTimerPtrValid (const os_timer_t *timer) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_timer_cb_start__;
uint32_t cb_length = (uint32_t)&__os_timer_cb_length__;
// Check the section boundaries
if (((uint32_t)timer - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)timer - cb_start) % sizeof(os_timer_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (timer == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Timer Tick (called each SysTick).
static void osRtxTimerTick (void) {
os_thread_t *thread_running;
os_timer_t *timer;
osStatus_t status;
timer = osRtxInfo.timer.list;
if (timer == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
thread_running = osRtxThreadGetRunning();
timer->tick--;
while ((timer != NULL) && (timer->tick == 0U)) {
TimerUnlink(timer);
status = osMessageQueuePut(osRtxInfo.timer.mq, &timer->finfo, 0U, 0U);
if (status != osOK) {
const os_thread_t *thread = osRtxThreadGetRunning();
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
(void)osRtxKernelErrorNotify(osRtxErrorTimerQueueOverflow, timer);
if (osRtxThreadGetRunning() == NULL) {
if (thread_running == thread) {
thread_running = NULL;
}
}
}
if ((timer->attr & osRtxTimerPeriodic) != 0U) {
TimerInsert(timer, timer->load);
} else {
timer->state = osRtxTimerStopped;
}
timer = osRtxInfo.timer.list;
}
osRtxThreadSetRunning(thread_running);
}
/// Setup Timer Thread objects.
//lint -esym(714,osRtxTimerSetup) "Referenced from library configuration"
//lint -esym(759,osRtxTimerSetup) "Prototype in header"
//lint -esym(765,osRtxTimerSetup) "Global scope"
int32_t osRtxTimerSetup (void) {
int32_t ret = -1;
if (osRtxMessageQueueTimerSetup() == 0) {
osRtxInfo.timer.tick = osRtxTimerTick;
ret = 0;
}
return ret;
}
/// Timer Thread
//lint -esym(714,osRtxTimerThread) "Referenced from library configuration"
//lint -esym(759,osRtxTimerThread) "Prototype in header"
//lint -esym(765,osRtxTimerThread) "Global scope"
__NO_RETURN void osRtxTimerThread (void *argument) {
os_timer_finfo_t finfo;
osStatus_t status;
osMessageQueueId_t mq = (osMessageQueueId_t)argument;
for (;;) {
//lint -e{934} "Taking address of near auto variable"
status = osMessageQueueGet(mq, &finfo, NULL, osWaitForever);
if (status == osOK) {
EvrRtxTimerCallback(finfo.func, finfo.arg);
(finfo.func)(finfo.arg);
}
}
}
/// Destroy a Timer object.
/// \param[in] timer timer object.
static void osRtxTimerDestroy (os_timer_t *timer) {
// Mark object as inactive and invalid
timer->state = osRtxTimerInactive;
timer->id = osRtxIdInvalid;
// Free object memory
if ((timer->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer);
#else
if (osRtxInfo.mpi.timer != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, timer);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxTimerMemUsage.cnt_free++;
#endif
}
EvrRtxTimerDestroyed(timer);
}
#ifdef RTX_SAFETY_CLASS
/// Delete a Timer safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxTimerDeleteClass (uint32_t safety_class, uint32_t mode) {
os_timer_t *timer;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
timer = (os_timer_t *)(uint32_t)&__os_timer_cb_start__;
length = (uint32_t)&__os_timer_cb_length__;
while (length >= sizeof(os_timer_t)) {
if ( (timer->id == osRtxIdTimer) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((timer->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((timer->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
if (timer->state == osRtxTimerRunning) {
TimerRemove(timer);
}
osRtxTimerDestroy(timer);
}
length -= sizeof(os_timer_t);
timer++;
}
}
#endif
// ==== Service Calls ====
/// Create and Initialize a timer.
/// \note API identical to osTimerNew
static osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
os_timer_t *timer;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
uint32_t attr_bits;
#endif
uint8_t flags;
const char *name;
// Check parameters
if ((func == NULL) || ((type != osTimerOnce) && (type != osTimerPeriodic))) {
EvrRtxTimerError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Process attributes
if (attr != NULL) {
name = attr->name;
#ifdef RTX_SAFETY_CLASS
attr_bits = attr->attr_bits;
#endif
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
timer = attr->cb_mem;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxTimerError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (timer != NULL) {
if (!IsTimerPtrValid(timer) || (attr->cb_size != sizeof(os_timer_t))) {
EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
#ifdef RTX_SAFETY_CLASS
attr_bits = 0U;
#endif
timer = NULL;
}
// Allocate object memory if not provided
if (timer == NULL) {
if (osRtxInfo.mpi.timer != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
timer = osRtxMemoryPoolAlloc(osRtxInfo.mpi.timer);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
timer = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_timer_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (timer != NULL) {
uint32_t used;
osRtxTimerMemUsage.cnt_alloc++;
used = osRtxTimerMemUsage.cnt_alloc - osRtxTimerMemUsage.cnt_free;
if (osRtxTimerMemUsage.max_used < used) {
osRtxTimerMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
if (timer != NULL) {
// Initialize control block
timer->id = osRtxIdTimer;
timer->state = osRtxTimerStopped;
timer->flags = flags;
if (type == osTimerPeriodic) {
timer->attr = osRtxTimerPeriodic;
} else {
timer->attr = 0U;
}
timer->name = name;
timer->prev = NULL;
timer->next = NULL;
timer->tick = 0U;
timer->load = 0U;
timer->finfo.func = func;
timer->finfo.arg = argument;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
timer->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
timer->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
EvrRtxTimerCreated(timer, timer->name);
} else {
EvrRtxTimerError(NULL, (int32_t)osErrorNoMemory);
}
return timer;
}
/// Get name of a timer.
/// \note API identical to osTimerGetName
static const char *svcRtxTimerGetName (osTimerId_t timer_id) {
os_timer_t *timer = osRtxTimerId(timer_id);
// Check parameters
if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {
EvrRtxTimerGetName(timer, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxTimerGetName(timer, timer->name);
return timer->name;
}
/// Start or restart a timer.
/// \note API identical to osTimerStart
static osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {
os_timer_t *timer = osRtxTimerId(timer_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
// Check parameters
if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer) || (ticks == 0U)) {
EvrRtxTimerError(timer, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {
EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
if (timer->state == osRtxTimerRunning) {
timer->load = ticks;
TimerRemove(timer);
} else {
if (osRtxInfo.timer.tick == NULL) {
EvrRtxTimerError(timer, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
} else {
timer->state = osRtxTimerRunning;
timer->load = ticks;
}
}
TimerInsert(timer, ticks);
EvrRtxTimerStarted(timer);
return osOK;
}
/// Stop a timer.
/// \note API identical to osTimerStop
static osStatus_t svcRtxTimerStop (osTimerId_t timer_id) {
os_timer_t *timer = osRtxTimerId(timer_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
// Check parameters
if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {
EvrRtxTimerError(timer, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {
EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object state
if (timer->state != osRtxTimerRunning) {
EvrRtxTimerError(timer, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
timer->state = osRtxTimerStopped;
TimerRemove(timer);
EvrRtxTimerStopped(timer);
return osOK;
}
/// Check if a timer is running.
/// \note API identical to osTimerIsRunning
static uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) {
os_timer_t *timer = osRtxTimerId(timer_id);
uint32_t is_running;
// Check parameters
if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {
EvrRtxTimerIsRunning(timer, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
if (timer->state == osRtxTimerRunning) {
EvrRtxTimerIsRunning(timer, 1U);
is_running = 1U;
} else {
EvrRtxTimerIsRunning(timer, 0U);
is_running = 0;
}
return is_running;
}
/// Delete a timer.
/// \note API identical to osTimerDelete
static osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) {
os_timer_t *timer = osRtxTimerId(timer_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
// Check parameters
if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {
EvrRtxTimerError(timer, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {
EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
if (timer->state == osRtxTimerRunning) {
TimerRemove(timer);
}
osRtxTimerDestroy(timer);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_4(TimerNew, osTimerId_t, osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *)
SVC0_1(TimerGetName, const char *, osTimerId_t)
SVC0_2(TimerStart, osStatus_t, osTimerId_t, uint32_t)
SVC0_1(TimerStop, osStatus_t, osTimerId_t)
SVC0_1(TimerIsRunning, uint32_t, osTimerId_t)
SVC0_1(TimerDelete, osStatus_t, osTimerId_t)
//lint --flb "Library End"
// ==== Public API ====
/// Create and Initialize a timer.
osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
osTimerId_t timer_id;
EvrRtxTimerNew(func, type, argument, attr);
if (IsException() || IsIrqMasked()) {
EvrRtxTimerError(NULL, (int32_t)osErrorISR);
timer_id = NULL;
} else {
timer_id = __svcTimerNew(func, type, argument, attr);
}
return timer_id;
}
/// Get name of a timer.
const char *osTimerGetName (osTimerId_t timer_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxTimerGetName(timer_id);
} else {
name = __svcTimerGetName(timer_id);
}
return name;
}
/// Start or restart a timer.
osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
osStatus_t status;
EvrRtxTimerStart(timer_id, ticks);
if (IsException() || IsIrqMasked()) {
EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcTimerStart(timer_id, ticks);
}
return status;
}
/// Stop a timer.
osStatus_t osTimerStop (osTimerId_t timer_id) {
osStatus_t status;
EvrRtxTimerStop(timer_id);
if (IsException() || IsIrqMasked()) {
EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcTimerStop(timer_id);
}
return status;
}
/// Check if a timer is running.
uint32_t osTimerIsRunning (osTimerId_t timer_id) {
uint32_t is_running;
if (IsException() || IsIrqMasked()) {
EvrRtxTimerIsRunning(timer_id, 0U);
is_running = 0U;
} else {
is_running = __svcTimerIsRunning(timer_id);
}
return is_running;
}
/// Delete a timer.
osStatus_t osTimerDelete (osTimerId_t timer_id) {
osStatus_t status;
EvrRtxTimerDelete(timer_id);
if (IsException() || IsIrqMasked()) {
EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcTimerDelete(timer_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_timer.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,270 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex-M Core definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CORE_CM_H_
#define RTX_CORE_CM_H_
#ifndef RTX_CORE_C_H_
#ifndef RTE_COMPONENTS_H
#include "RTE_Components.h"
#endif
#include CMSIS_device_header
#endif
#include <stdbool.h>
typedef bool bool_t;
#ifndef FALSE
#define FALSE ((bool_t)0)
#endif
#ifndef TRUE
#define TRUE ((bool_t)1)
#endif
#ifndef EXCLUSIVE_ACCESS
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
#define EXCLUSIVE_ACCESS 1
#else
#define EXCLUSIVE_ACCESS 0
#endif
#endif
#define OS_TICK_HANDLER SysTick_Handler
/// xPSR_Initialization Value
/// \param[in] privileged true=privileged, false=unprivileged
/// \param[in] thumb true=Thumb, false=ARM
/// \return xPSR Init Value
__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
(void)privileged;
(void)thumb;
return (0x01000000U);
}
// Stack Frame:
// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR
// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR
/// Stack Frame Initialization Value (EXC_RETURN[7..0])
#if (DOMAIN_NS == 1)
#define STACK_FRAME_INIT_VAL 0xBCU
#else
#define STACK_FRAME_INIT_VAL 0xFDU
#endif
/// Stack Offset of Register R0
/// \param[in] stack_frame Stack Frame (EXC_RETURN[7..0])
/// \return R0 Offset
__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
#if ((__FPU_USED == 1U) || \
(defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0)))
return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U));
#else
(void)stack_frame;
return (8U*4U);
#endif
}
// ==== Core functions ====
//lint -sem(__get_CONTROL, pure)
//lint -sem(__get_IPSR, pure)
//lint -sem(__get_PRIMASK, pure)
//lint -sem(__get_BASEPRI, pure)
/// Check if running Privileged
/// \return true=privileged, false=unprivileged
__STATIC_INLINE bool_t IsPrivileged (void) {
return ((__get_CONTROL() & 1U) == 0U);
}
/// Set thread Privileged mode
/// \param[in] privileged true=privileged, false=unprivileged
__STATIC_INLINE void SetPrivileged (bool_t privileged) {
if (privileged) {
// Privileged Thread mode & PSP
__set_CONTROL(0x02U);
} else {
// Unprivileged Thread mode & PSP
__set_CONTROL(0x03U);
}
}
/// Check if in Exception
/// \return true=exception, false=thread
__STATIC_INLINE bool_t IsException (void) {
return (__get_IPSR() != 0U);
}
/// Check if in Fault
/// \return true, false
__STATIC_INLINE bool_t IsFault (void) {
uint32_t ipsr = __get_IPSR();
return (((int32_t)ipsr < ((int32_t)SVCall_IRQn + 16)) &&
((int32_t)ipsr > ((int32_t)NonMaskableInt_IRQn + 16)));
}
/// Check if in SVCall IRQ
/// \return true, false
__STATIC_INLINE bool_t IsSVCallIrq (void) {
return ((int32_t)__get_IPSR() == ((int32_t)SVCall_IRQn + 16));
}
/// Check if in PendSV IRQ
/// \return true, false
__STATIC_INLINE bool_t IsPendSvIrq (void) {
return ((int32_t)__get_IPSR() == ((int32_t)PendSV_IRQn + 16));
}
/// Check if in Tick Timer IRQ
/// \return true, false
__STATIC_INLINE bool_t IsTickIrq (int32_t tick_irqn) {
return ((int32_t)__get_IPSR() == (tick_irqn + 16));
}
/// Check if IRQ is Masked
/// \return true=masked, false=not masked
__STATIC_INLINE bool_t IsIrqMasked (void) {
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U));
#else
return (__get_PRIMASK() != 0U);
#endif
}
// ==== Core Peripherals functions ====
/// Setup SVC and PendSV System Service Calls
__STATIC_INLINE void SVC_Setup (void) {
#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \
(defined(__CORTEX_M) && (__CORTEX_M == 7U)))
uint32_t p, n;
SCB->SHPR[10] = 0xFFU;
n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));
p = NVIC_GetPriorityGrouping();
if (p >= n) {
n = p + 1U;
}
SCB->SHPR[7] = (uint8_t)(0xFEU << n);
#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
uint32_t n;
SCB->SHPR[1] |= 0x00FF0000U;
n = SCB->SHPR[1];
SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U;
#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)))
uint32_t p, n;
SCB->SHP[10] = 0xFFU;
n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));
p = NVIC_GetPriorityGrouping();
if (p >= n) {
n = p + 1U;
}
SCB->SHP[7] = (uint8_t)(0xFEU << n);
#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0))
uint32_t n;
SCB->SHP[1] |= 0x00FF0000U;
n = SCB->SHP[1];
SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U;
#endif
}
/// Get Pending SV (Service Call) Flag
/// \return Pending SV Flag
__STATIC_INLINE uint8_t GetPendSV (void) {
return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));
}
/// Clear Pending SV (Service Call) Flag
__STATIC_INLINE void ClrPendSV (void) {
SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
}
/// Set Pending SV (Service Call) Flag
__STATIC_INLINE void SetPendSV (void) {
SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
}
// ==== Service Calls definitions ====
//lint -save -e9023 -e9024 -e9026 "Function-like macros using '#/##'" [MISRA Note 10]
#if defined(__CC_ARM)
#if defined(RTX_SVC_PTR_CHECK)
#warning "SVC Function Pointer checking is not supported!"
#endif
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
#define SVC_INDIRECT(n) __svc_indirect(n)
#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
#define SVC_INDIRECT(n) __svc_indirect_r7(n)
#endif
#define SVC0_0N(f,t) \
SVC_INDIRECT(0) t svc##f (t(*)()); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
svc##f(svcRtx##f); \
}
#define SVC0_0(f,t) \
SVC_INDIRECT(0) t svc##f (t(*)()); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
return svc##f(svcRtx##f); \
}
#define SVC0_1N(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
svc##f(svcRtx##f,a1); \
}
#define SVC0_1(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
return svc##f(svcRtx##f,a1); \
}
#define SVC0_2(f,t,t1,t2) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
return svc##f(svcRtx##f,a1,a2); \
}
#define SVC0_3(f,t,t1,t2,t3) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
return svc##f(svcRtx##f,a1,a2,a3); \
}
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
return svc##f(svcRtx##f,a1,a2,a3,a4); \
}
#elif defined(__ICCARM__)
#if defined(RTX_SVC_PTR_CHECK)
#warning "SVC Function Pointer checking is not supported!"
#endif
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
#define SVC_ArgF(f) \
__asm( \
"mov r12,%0\n" \
:: "r"(&f): "r12" \
);
#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
#define SVC_ArgF(f) \
__asm( \
"mov r7,%0\n" \
:: "r"(&f): "r7" \
);
#endif
#define STRINGIFY(a) #a
#define SVC_INDIRECT(n) _Pragma(STRINGIFY(svc_number = n)) __svc
#define SVC0_0N(f,t) \
SVC_INDIRECT(0) t svc##f (); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
svc##f(); \
}
#define SVC0_0(f,t) \
SVC_INDIRECT(0) t svc##f (); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
return svc##f(); \
}
#define SVC0_1N(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t1 a1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgF(svcRtx##f); \
svc##f(a1); \
}
#define SVC0_1(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t1 a1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1); \
}
#define SVC0_2(f,t,t1,t2) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2); \
}
#define SVC0_3(f,t,t1,t2,t3) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2,a3); \
}
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2,a3,a4); \
}
#else // !(defined(__CC_ARM) || defined(__ICCARM__))
//lint -esym(522,__svc*) "Functions '__svc*' are impure (side-effects)"
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
#define SVC_RegF "r12"
#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
#define SVC_RegF "r7"
#endif
#define SVC_ArgN(n) \
register uint32_t __r##n __ASM("r"#n)
#define SVC_ArgR(n,a) \
register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
#if (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))
#define SVC_ArgF(f) \
register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)jmpRtx##f
#else
#define SVC_ArgF(f) \
register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)svcRtx##f
#endif
#define SVC_In0 "r"(__rf)
#define SVC_In1 "r"(__rf),"r"(__r0)
#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1)
#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2)
#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3)
#define SVC_Out0
#define SVC_Out1 "=r"(__r0)
#define SVC_CL0
#define SVC_CL1 "r0"
#define SVC_Call0(in, out, cl) \
__ASM volatile ("svc 0" : out : in : cl)
#if (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
(defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \
(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
(defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))
#define SVC_Jump(f) \
__ASM volatile ( \
".align 2\n\t" \
"b.w %[adr]" : : [adr] "X" (f) \
)
#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \
(defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
#define SVC_Jump(f) \
__ASM volatile ( \
".align 3\n\t" \
"ldr r7,1f\n\t" \
"bx r7\n" \
"1: .word %[adr]" : : [adr] "X" (f) \
)
#endif
#define SVC_Veneer_Prototye(f) \
__STATIC_INLINE void jmpRtx##f (void);
#define SVC_Veneer_Function(f) \
__attribute__((naked,section(".text.os.svc.veneer."#f))) \
__STATIC_INLINE void jmpRtx##f (void) { \
SVC_Jump(svcRtx##f); \
}
#else
#define SVC_Veneer_Prototye(f)
#define SVC_Veneer_Function(f)
#endif
#define SVC0_0N(f,t) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(f); \
SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1); \
} \
SVC_Veneer_Function(f)
#define SVC0_0(f,t) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgN(0); \
SVC_ArgF(f); \
SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_1N(f,t,t1) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(f); \
SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
} \
SVC_Veneer_Function(f)
#define SVC0_1(f,t,t1) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(f); \
SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_2(f,t,t1,t2) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgF(f); \
SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_3(f,t,t1,t2,t3) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgR(2,a3); \
SVC_ArgF(f); \
SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgR(2,a3); \
SVC_ArgR(3,a4); \
SVC_ArgF(f); \
SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#endif
//lint -restore [MISRA Note 10]
// ==== Exclusive Access Operation ====
#if (EXCLUSIVE_ACCESS == 1)
//lint ++flb "Library Begin" [MISRA Note 12]
/// Atomic Access Operation: Write (8-bit)
/// \param[in] mem Memory address
/// \param[in] val Value to write
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
mov r2,r0
1
ldrexb r0,[r2]
strexb r3,r1,[r2]
cbz r3,%F2
b %B1
2
bx lr
}
#else
__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint8_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexb %[ret],[%[mem]]\n\t"
"strexb %[res],%[val],[%[mem]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [ret] "=&l" (ret),
[res] "=&l" (res)
: [mem] "l" (mem),
[val] "l" (val)
: "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Set bits (32-bit)
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return New value
#if defined(__CC_ARM)
static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
mov r2,r0
1
ldrex r0,[r2]
orr r0,r0,r1
strex r3,r0,[r2]
cbz r3,%F2
b %B1
2
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[val],[%[mem]]\n\t"
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
"mov %[ret],%[val]\n\t"
"orrs %[ret],%[bits]\n\t"
#else
"orr %[ret],%[val],%[bits]\n\t"
#endif
"strex %[res],%[ret],[%[mem]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
: "memory", "cc"
#else
: "memory"
#endif
);
return ret;
}
#endif
/// Atomic Access Operation: Clear bits (32-bit)
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
bic r4,r0,r1
strex r3,r4,[r2]
cbz r3,%F2
b %B1
2
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
"mov %[val],%[ret]\n\t"
"bics %[val],%[bits]\n\t"
#else
"bic %[val],%[ret],%[bits]\n\t"
#endif
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
: "memory", "cc"
#else
: "memory"
#endif
);
return ret;
}
#endif
/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Active bits before clearing or 0 if not active
#if defined(__CC_ARM)
static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
and r4,r0,r1
cmp r4,r1
beq %F2
clrex
movs r0,#0
pop {r4,pc}
2
bic r4,r0,r1
strex r3,r4,[r2]
cbz r3,%F3
b %B1
3
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
"mov %[val],%[ret]\n\t"
"ands %[val],%[bits]\n\t"
#else
"and %[val],%[ret],%[bits]\n\t"
#endif
"cmp %[val],%[bits]\n\t"
"beq 2f\n\t"
"clrex\n\t"
"movs %[ret],#0\n\t"
"b 3f\n"
"2:\n\t"
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
"mov %[val],%[ret]\n\t"
"bics %[val],%[bits]\n\t"
#else
"bic %[val],%[ret],%[bits]\n\t"
#endif
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Active bits before clearing or 0 if not active
#if defined(__CC_ARM)
static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
tst r0,r1
bne %F2
clrex
movs r0,#0
pop {r4,pc}
2
bic r4,r0,r1
strex r3,r4,[r2]
cbz r3,%F3
b %B1
3
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"tst %[ret],%[bits]\n\t"
"bne 2f\n\t"
"clrex\n\t"
"movs %[ret],#0\n\t"
"b 3f\n"
"2:\n\t"
#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
"mov %[val],%[ret]\n\t"
"bics %[val],%[bits]\n\t"
#else
"bic %[val],%[ret],%[bits]\n\t"
#endif
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (32-bit)
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_inc32 (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
adds r1,r0,#1
strex r3,r1,[r2]
cbz r3,%F2
b %B1
2
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"adds %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (16-bit) if Less Than
/// \param[in] mem Memory address
/// \param[in] max Maximum value
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
push {r4,lr}
mov r2,r0
1
ldrexh r0,[r2]
cmp r1,r0
bhi %F2
clrex
pop {r4,pc}
2
adds r4,r0,#1
strexh r3,r4,[r2]
cbz r3,%F3
b %B1
3
pop {r4,pc}
}
#else
__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"cmp %[max],%[ret]\n\t"
"bhi 2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"adds %[val],%[ret],#1\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[max] "l" (max)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (16-bit) and clear on Limit
/// \param[in] mem Memory address
/// \param[in] max Maximum value
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
push {r4,lr}
mov r2,r0
1
ldrexh r0,[r2]
adds r4,r0,#1
cmp r1,r4
bhi %F2
movs r4,#0
2
strexh r3,r4,[r2]
cbz r3,%F3
b %B1
3
pop {r4,pc}
}
#else
__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"adds %[val],%[ret],#1\n\t"
"cmp %[lim],%[val]\n\t"
"bhi 2f\n\t"
"movs %[val],#0\n"
"2:\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[lim] "l" (lim)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (32-bit)
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_dec32 (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
subs r1,r0,#1
strex r3,r1,[r2]
cbz r3,%F2
b %B1
2
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"subs %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (32-bit) if Not Zero
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_dec32_nz (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
cbnz r0,%F2
clrex
bx lr
2
subs r1,r0,#1
strex r3,r1,[r2]
cbz r3,%F3
b %B1
3
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"cbnz %[ret],2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"subs %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (16-bit) if Not Zero
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_dec16_nz (uint16_t *mem) {
mov r2,r0
1
ldrexh r0,[r2]
cbnz r0,%F2
clrex
bx lr
2
subs r1,r0,#1
strexh r3,r1,[r2]
cbz r3,%F3
b %B1
3
bx lr
}
#else
__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"cbnz %[ret],2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"subs %[val],%[ret],#1\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Link Get
/// \param[in] root Root address
/// \return Link
#if defined(__CC_ARM)
static __asm void *atomic_link_get (void **root) {
mov r2,r0
1
ldrex r0,[r2]
cbnz r0,%F2
clrex
bx lr
2
ldr r1,[r0]
strex r3,r1,[r2]
cbz r3,%F3
b %B1
3
bx lr
}
#else
__STATIC_INLINE void *atomic_link_get (void **root) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register void *ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[root]]\n\t"
"cbnz %[ret],2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"ldr %[val],[%[ret]]\n\t"
"strex %[res],%[val],[%[root]]\n\t"
"cbz %[res],3f\n\t"
"b 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [root] "l" (root)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Link Put
/// \param[in] root Root address
/// \param[in] lnk Link
#if defined(__CC_ARM)
static __asm void atomic_link_put (void **root, void *link) {
1
ldr r2,[r0]
str r2,[r1]
dmb
ldrex r2,[r0]
ldr r3,[r1]
cmp r3,r2
bne %B1
strex r3,r1,[r0]
cbz r3,%F2
b %B1
2
bx lr
}
#else
__STATIC_INLINE void atomic_link_put (void **root, void *link) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val1, val2, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldr %[val1],[%[root]]\n\t"
"str %[val1],[%[link]]\n\t"
"dmb\n\t"
"ldrex %[val1],[%[root]]\n\t"
"ldr %[val2],[%[link]]\n\t"
"cmp %[val2],%[val1]\n\t"
"bne 1b\n\t"
"strex %[res],%[link],[%[root]]\n\t"
"cbz %[res],2f\n\t"
"b 1b\n"
"2:"
: [val1] "=&l" (val1),
[val2] "=&l" (val2),
[res] "=&l" (res)
: [root] "l" (root),
[link] "l" (link)
: "cc", "memory"
);
}
#endif
//lint --flb "Library End" [MISRA Note 12]
#endif // (EXCLUSIVE_ACCESS == 1)
#endif // RTX_CORE_CM_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 11,596 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Memory Pool functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage \
__attribute__((section(".data.os.mempool.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Verify that Memory Pool object pointer is valid.
/// \param[in] mp memory pool object.
/// \return true - valid, false - invalid.
static bool_t IsMemoryPoolPtrValid (const os_memory_pool_t *mp) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_mempool_cb_start__;
uint32_t cb_length = (uint32_t)&__os_mempool_cb_length__;
// Check the section boundaries
if (((uint32_t)mp - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)mp - cb_start) % sizeof(os_memory_pool_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (mp == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Initialize Memory Pool.
/// \param[in] mp_info memory pool info.
/// \param[in] block_count maximum number of memory blocks in memory pool.
/// \param[in] block_size size of a memory block in bytes.
/// \param[in] block_mem pointer to memory for block storage.
/// \return 1 - success, 0 - failure.
uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {
//lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
void *mem;
void *block;
// Check parameters
if ((mp_info == NULL) || (block_count == 0U) || (block_size == 0U) || (block_mem == NULL)) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
// Initialize information structure
mp_info->max_blocks = block_count;
mp_info->used_blocks = 0U;
mp_info->block_size = block_size;
mp_info->block_base = block_mem;
mp_info->block_free = block_mem;
mp_info->block_lim = &(((uint8_t *)block_mem)[block_count * block_size]);
EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem);
// Link all free blocks
mem = block_mem;
while (--block_count != 0U) {
block = &((uint8_t *)mem)[block_size];
*((void **)mem) = block;
mem = block;
}
*((void **)mem) = NULL;
return 1U;
}
/// Allocate a memory block from a Memory Pool.
/// \param[in] mp_info memory pool info.
/// \return address of the allocated memory block or NULL in case of no memory is available.
void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
void *block;
if (mp_info == NULL) {
EvrRtxMemoryBlockAlloc(NULL, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
block = mp_info->block_free;
if (block != NULL) {
//lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type"
mp_info->block_free = *((void **)block);
mp_info->used_blocks++;
}
if (primask == 0U) {
__enable_irq();
}
#else
block = atomic_link_get(&mp_info->block_free);
if (block != NULL) {
(void)atomic_inc32(&mp_info->used_blocks);
}
#endif
EvrRtxMemoryBlockAlloc(mp_info, block);
return block;
}
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] mp_info memory pool info.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return status code that indicates the execution status of the function.
osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
//lint -e{946} "Relational operator applied to pointers"
if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) {
EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
//lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type"
*((void **)block) = mp_info->block_free;
mp_info->block_free = block;
mp_info->used_blocks--;
if (primask == 0U) {
__enable_irq();
}
#else
atomic_link_put(&mp_info->block_free, block);
(void)atomic_dec32(&mp_info->used_blocks);
#endif
EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osOK);
return osOK;
}
/// Destroy a Memory Pool object.
/// \param[in] mp memory pool object.
static void osRtxMemoryPoolDestroy (os_memory_pool_t *mp) {
// Mark object as invalid
mp->id = osRtxIdInvalid;
// Free data memory
if ((mp->flags & osRtxFlagSystemMemory) != 0U) {
(void)osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base);
}
// Free object memory
if ((mp->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
#else
if (osRtxInfo.mpi.memory_pool != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, mp);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxMemoryPoolMemUsage.cnt_free++;
#endif
}
EvrRtxMemoryPoolDestroyed(mp);
}
#ifdef RTX_SAFETY_CLASS
/// Delete a Memory Pool safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxMemoryPoolDeleteClass (uint32_t safety_class, uint32_t mode) {
os_memory_pool_t *mp;
os_thread_t *thread;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
mp = (os_memory_pool_t *)(uint32_t)&__os_mempool_cb_start__;
length = (uint32_t)&__os_mempool_cb_length__;
while (length >= sizeof(os_memory_pool_t)) {
if ( (mp->id == osRtxIdMemoryPool) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((mp->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((mp->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
while (mp->thread_list != NULL) {
thread = osRtxThreadListGet(osRtxObject(mp));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
}
osRtxMemoryPoolDestroy(mp);
}
length -= sizeof(os_memory_pool_t);
mp++;
}
}
#endif
// ==== Post ISR processing ====
/// Memory Pool post ISR processing.
/// \param[in] mp memory pool object.
static void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) {
void *block;
os_thread_t *thread;
// Check if Thread is waiting to allocate memory
if (mp->thread_list != NULL) {
// Allocate memory
block = osRtxMemoryPoolAlloc(&mp->mp_info);
if (block != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mp));
//lint -e{923} "cast from pointer to unsigned int"
osRtxThreadWaitExit(thread, (uint32_t)block, FALSE);
EvrRtxMemoryPoolAllocated(mp, block);
}
}
}
// ==== Service Calls ====
/// Create and Initialize a Memory Pool object.
/// \note API identical to osMemoryPoolNew
static osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
os_memory_pool_t *mp;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
uint32_t attr_bits;
#endif
void *mp_mem;
uint32_t mp_size;
uint32_t b_count;
uint32_t b_size;
uint32_t size;
uint8_t flags;
const char *name;
// Check parameters
if ((block_count == 0U) || (block_size == 0U) ||
((__CLZ(block_count) + __CLZ(block_size)) < 32U)) {
EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
b_count = block_count;
b_size = (block_size + 3U) & ~3UL;
size = b_count * b_size;
// Process attributes
if (attr != NULL) {
name = attr->name;
#ifdef RTX_SAFETY_CLASS
attr_bits = attr->attr_bits;
#endif
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
mp = attr->cb_mem;
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
mp_mem = attr->mp_mem;
mp_size = attr->mp_size;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxMemoryPoolError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (mp != NULL) {
if (!IsMemoryPoolPtrValid(mp) || (attr->cb_size != sizeof(os_memory_pool_t))) {
EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
if (mp_mem != NULL) {
//lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7]
if ((((uint32_t)mp_mem & 3U) != 0U) || (mp_size < size)) {
EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (mp_size != 0U) {
EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
#ifdef RTX_SAFETY_CLASS
attr_bits = 0U;
#endif
mp = NULL;
mp_mem = NULL;
}
// Allocate object memory if not provided
if (mp == NULL) {
if (osRtxInfo.mpi.memory_pool != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mp = osRtxMemoryPoolAlloc(osRtxInfo.mpi.memory_pool);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mp = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_memory_pool_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (mp != NULL) {
uint32_t used;
osRtxMemoryPoolMemUsage.cnt_alloc++;
used = osRtxMemoryPoolMemUsage.cnt_alloc - osRtxMemoryPoolMemUsage.cnt_free;
if (osRtxMemoryPoolMemUsage.max_used < used) {
osRtxMemoryPoolMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
// Allocate data memory if not provided
if ((mp != NULL) && (mp_mem == NULL)) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mp_mem = osRtxMemoryAlloc(osRtxInfo.mem.mp_data, size, 0U);
if (mp_mem == NULL) {
if ((flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
#else
if (osRtxInfo.mpi.memory_pool != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, mp);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxMemoryPoolMemUsage.cnt_free++;
#endif
}
mp = NULL;
} else {
(void)memset(mp_mem, 0, size);
}
flags |= osRtxFlagSystemMemory;
}
if (mp != NULL) {
// Initialize control block
mp->id = osRtxIdMemoryPool;
mp->flags = flags;
mp->attr = 0U;
mp->name = name;
mp->thread_list = NULL;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
mp->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
mp->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
(void)osRtxMemoryPoolInit(&mp->mp_info, b_count, b_size, mp_mem);
// Register post ISR processing function
osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess;
EvrRtxMemoryPoolCreated(mp, mp->name);
} else {
EvrRtxMemoryPoolError(NULL, (int32_t)osErrorNoMemory);
}
return mp;
}
/// Get name of a Memory Pool object.
/// \note API identical to osMemoryPoolGetName
static const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolGetName(mp, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxMemoryPoolGetName(mp, mp->name);
return mp->name;
}
/// Allocate a memory block from a Memory Pool.
/// \note API identical to osMemoryPoolAlloc
static void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
void *block;
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
#endif
// Allocate memory
block = osRtxMemoryPoolAlloc(&mp->mp_info);
if (block != NULL) {
EvrRtxMemoryPoolAllocated(mp, block);
} else {
// No memory available
if (timeout != 0U) {
EvrRtxMemoryPoolAllocPending(mp, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout)) {
osRtxThreadListPut(osRtxObject(mp), osRtxThreadGetRunning());
} else {
EvrRtxMemoryPoolAllocTimeout(mp);
}
} else {
EvrRtxMemoryPoolAllocFailed(mp);
}
}
return block;
}
/// Return an allocated memory block back to a Memory Pool.
/// \note API identical to osMemoryPoolFree
static osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
void *block0;
os_thread_t *thread;
osStatus_t status;
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Free memory
status = osRtxMemoryPoolFree(&mp->mp_info, block);
if (status == osOK) {
EvrRtxMemoryPoolDeallocated(mp, block);
// Check if Thread is waiting to allocate memory
if (mp->thread_list != NULL) {
// Allocate memory
block0 = osRtxMemoryPoolAlloc(&mp->mp_info);
if (block0 != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mp));
//lint -e{923} "cast from pointer to unsigned int"
osRtxThreadWaitExit(thread, (uint32_t)block0, TRUE);
EvrRtxMemoryPoolAllocated(mp, block0);
}
}
} else {
EvrRtxMemoryPoolFreeFailed(mp, block);
}
return status;
}
/// Get maximum number of memory blocks in a Memory Pool.
/// \note API identical to osMemoryPoolGetCapacity
static uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolGetCapacity(mp, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMemoryPoolGetCapacity(mp, mp->mp_info.max_blocks);
return mp->mp_info.max_blocks;
}
/// Get memory block size in a Memory Pool.
/// \note API identical to osMemoryPoolGetBlockSize
static uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolGetBlockSize(mp, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMemoryPoolGetBlockSize(mp, mp->mp_info.block_size);
return mp->mp_info.block_size;
}
/// Get number of memory blocks used in a Memory Pool.
/// \note API identical to osMemoryPoolGetCount
static uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolGetCount(mp, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMemoryPoolGetCount(mp, mp->mp_info.used_blocks);
return mp->mp_info.used_blocks;
}
/// Get number of memory blocks available in a Memory Pool.
/// \note API identical to osMemoryPoolGetSpace
static uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolGetSpace(mp, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMemoryPoolGetSpace(mp, mp->mp_info.max_blocks - mp->mp_info.used_blocks);
return (mp->mp_info.max_blocks - mp->mp_info.used_blocks);
}
/// Delete a Memory Pool object.
/// \note API identical to osMemoryPoolDelete
static osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
os_thread_t *thread;
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Unblock waiting threads
if (mp->thread_list != NULL) {
do {
thread = osRtxThreadListGet(osRtxObject(mp));
osRtxThreadWaitExit(thread, 0U, FALSE);
} while (mp->thread_list != NULL);
osRtxThreadDispatch(NULL);
}
osRtxMemoryPoolDestroy(mp);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_3(MemoryPoolNew, osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *)
SVC0_1(MemoryPoolGetName, const char *, osMemoryPoolId_t)
SVC0_2(MemoryPoolAlloc, void *, osMemoryPoolId_t, uint32_t)
SVC0_2(MemoryPoolFree, osStatus_t, osMemoryPoolId_t, void *)
SVC0_1(MemoryPoolGetCapacity, uint32_t, osMemoryPoolId_t)
SVC0_1(MemoryPoolGetBlockSize, uint32_t, osMemoryPoolId_t)
SVC0_1(MemoryPoolGetCount, uint32_t, osMemoryPoolId_t)
SVC0_1(MemoryPoolGetSpace, uint32_t, osMemoryPoolId_t)
SVC0_1(MemoryPoolDelete, osStatus_t, osMemoryPoolId_t)
//lint --flb "Library End"
// ==== ISR Calls ====
/// Allocate a memory block from a Memory Pool.
/// \note API identical to osMemoryPoolAlloc
__STATIC_INLINE
void *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
void *block;
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool) || (timeout != 0U)) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Allocate memory
block = osRtxMemoryPoolAlloc(&mp->mp_info);
if (block == NULL) {
EvrRtxMemoryPoolAllocFailed(mp);
} else {
EvrRtxMemoryPoolAllocated(mp, block);
}
return block;
}
/// Return an allocated memory block back to a Memory Pool.
/// \note API identical to osMemoryPoolFree
__STATIC_INLINE
osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);
osStatus_t status;
// Check parameters
if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {
EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Free memory
status = osRtxMemoryPoolFree(&mp->mp_info, block);
if (status == osOK) {
// Register post ISR processing
osRtxPostProcess(osRtxObject(mp));
EvrRtxMemoryPoolDeallocated(mp, block);
} else {
EvrRtxMemoryPoolFreeFailed(mp, block);
}
return status;
}
// ==== Public API ====
/// Create and Initialize a Memory Pool object.
osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
osMemoryPoolId_t mp_id;
EvrRtxMemoryPoolNew(block_count, block_size, attr);
if (IsException() || IsIrqMasked()) {
EvrRtxMemoryPoolError(NULL, (int32_t)osErrorISR);
mp_id = NULL;
} else {
mp_id = __svcMemoryPoolNew(block_count, block_size, attr);
}
return mp_id;
}
/// Get name of a Memory Pool object.
const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxMemoryPoolGetName(mp_id);
} else {
name = __svcMemoryPoolGetName(mp_id);
}
return name;
}
/// Allocate a memory block from a Memory Pool.
void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
void *memory;
EvrRtxMemoryPoolAlloc(mp_id, timeout);
if (IsException() || IsIrqMasked()) {
memory = isrRtxMemoryPoolAlloc(mp_id, timeout);
} else {
memory = __svcMemoryPoolAlloc(mp_id, timeout);
}
return memory;
}
/// Return an allocated memory block back to a Memory Pool.
osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
osStatus_t status;
EvrRtxMemoryPoolFree(mp_id, block);
if (IsException() || IsIrqMasked()) {
status = isrRtxMemoryPoolFree(mp_id, block);
} else {
status = __svcMemoryPoolFree(mp_id, block);
}
return status;
}
/// Get maximum number of memory blocks in a Memory Pool.
uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
uint32_t capacity;
if (IsException() || IsIrqMasked()) {
capacity = svcRtxMemoryPoolGetCapacity(mp_id);
} else {
capacity = __svcMemoryPoolGetCapacity(mp_id);
}
return capacity;
}
/// Get memory block size in a Memory Pool.
uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
uint32_t block_size;
if (IsException() || IsIrqMasked()) {
block_size = svcRtxMemoryPoolGetBlockSize(mp_id);
} else {
block_size = __svcMemoryPoolGetBlockSize(mp_id);
}
return block_size;
}
/// Get number of memory blocks used in a Memory Pool.
uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
count = svcRtxMemoryPoolGetCount(mp_id);
} else {
count = __svcMemoryPoolGetCount(mp_id);
}
return count;
}
/// Get number of memory blocks available in a Memory Pool.
uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
uint32_t space;
if (IsException() || IsIrqMasked()) {
space = svcRtxMemoryPoolGetSpace(mp_id);
} else {
space = __svcMemoryPoolGetSpace(mp_id);
}
return space;
}
/// Delete a Memory Pool object.
osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {
osStatus_t status;
EvrRtxMemoryPoolDelete(mp_id);
if (IsException() || IsIrqMasked()) {
EvrRtxMemoryPoolError(mp_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMemoryPoolDelete(mp_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_mempool.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 7,671 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Delay functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// ==== Service Calls ====
/// Wait for Timeout (Time Delay).
/// \note API identical to osDelay
static osStatus_t svcRtxDelay (uint32_t ticks) {
osStatus_t status;
if (ticks == 0U) {
EvrRtxDelayError((int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) {
EvrRtxDelayStarted(ticks);
status = osOK;
} else {
EvrRtxDelayError((int32_t)osError);
status = osError;
}
return status;
}
/// Wait until specified time.
/// \note API identical to osDelayUntil
static osStatus_t svcRtxDelayUntil (uint32_t ticks) {
osStatus_t status;
ticks -= osRtxInfo.kernel.tick;
if ((ticks == 0U) || (ticks > 0x7FFFFFFFU)) {
EvrRtxDelayError((int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) {
EvrRtxDelayUntilStarted(ticks);
status = osOK;
} else {
EvrRtxDelayError((int32_t)osError);
status = osError;
}
return status;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_1(Delay, osStatus_t, uint32_t)
SVC0_1(DelayUntil, osStatus_t, uint32_t)
//lint --flb "Library End"
// ==== Public API ====
/// Wait for Timeout (Time Delay).
osStatus_t osDelay (uint32_t ticks) {
osStatus_t status;
EvrRtxDelay(ticks);
if (IsException() || IsIrqMasked()) {
EvrRtxDelayError((int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcDelay(ticks);
}
return status;
}
/// Wait until specified time.
osStatus_t osDelayUntil (uint32_t ticks) {
osStatus_t status;
EvrRtxDelayUntil(ticks);
if (IsException() || IsIrqMasked()) {
EvrRtxDelayError((int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcDelayUntil(ticks);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_delay.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 698 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex-A Core definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CORE_CA_H_
#define RTX_CORE_CA_H_
#ifndef RTX_CORE_C_H_
#ifndef RTE_COMPONENTS_H
#include "RTE_Components.h"
#endif
#include CMSIS_device_header
#endif
#include "irq_ctrl.h"
#include "os_tick.h"
#include <stdbool.h>
typedef bool bool_t;
#ifndef FALSE
#define FALSE ((bool_t)0)
#endif
#ifndef TRUE
#define TRUE ((bool_t)1)
#endif
#if defined(RTX_STACK_CHECK)
#warning "Stack overrun checking is not supported!"
#endif
#define EXCLUSIVE_ACCESS 1
#define OS_TICK_HANDLER osRtxTick_Handler
/// xPSR_Initialization Value
/// \param[in] privileged true=privileged, false=unprivileged
/// \param[in] thumb true=Thumb, false=Arm
/// \return xPSR Init Value
__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
uint32_t psr;
if (privileged) {
if (thumb) {
psr = CPSR_M_SYS | CPSR_T_Msk;
} else {
psr = CPSR_M_SYS;
}
} else {
if (thumb) {
psr = CPSR_M_USR | CPSR_T_Msk;
} else {
psr = CPSR_M_USR;
}
}
return psr;
}
// Stack Frame:
// - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
// - VFP-D16: D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
// - Basic: R4-R11, R0-R3, R12, LR, PC, CPSR
/// Stack Frame Initialization Value
#define STACK_FRAME_INIT_VAL 0x00U
/// Stack Offset of Register R0
/// \param[in] stack_frame Stack Frame
/// \return R0 Offset
__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
uint32_t offset;
if ((stack_frame & 0x04U) != 0U) {
offset = (32U*8U) + (2U*4U) + (8U*4U);
} else if ((stack_frame & 0x02U) != 0U) {
offset = (16U*8U) + (2U*4U) + (8U*4U);
} else {
offset = (8U*4U);
}
return offset;
}
// ==== Emulated Cortex-M functions ====
/// Get xPSR Register - emulate M profile: SP_usr - (8*4)
/// \return xPSR Register value
#if defined(__CC_ARM)
#pragma push
#pragma arm
static __asm uint32_t __get_PSP (void) {
sub sp, sp, #4
stm sp, {sp}^
pop {r0}
sub r0, r0, #32
bx lr
}
#pragma pop
#else
#ifdef __ICCARM__
__arm
#else
__attribute__((target("arm")))
#endif
__STATIC_INLINE uint32_t __get_PSP (void) {
register uint32_t ret;
__ASM volatile (
"sub sp,sp,#4\n\t"
"stm sp,{sp}^\n\t"
"pop {%[ret]}\n\t"
"sub %[ret],%[ret],#32\n\t"
: [ret] "=&l" (ret)
:
: "memory"
);
return ret;
}
#endif
extern uint8_t SVC_Active; // SVC Handler Active
extern uint8_t IRQ_PendSV; // Pending SVC flag
// ==== Core functions ====
/// Check if running Privileged
/// \return true=privileged, false=unprivileged
__STATIC_INLINE bool_t IsPrivileged (void) {
return (__get_mode() != CPSR_M_USR);
}
/// Set thread Privileged mode (not needed on Cortex-A)
/// \param[in] privileged true=privileged, false=unprivileged
__STATIC_INLINE void SetPrivileged (bool_t privileged) {
(void)privileged;
}
/// Check if in Exception
/// \return true=exception, false=thread
__STATIC_INLINE bool_t IsException (void) {
return ((__get_mode() != CPSR_M_USR) && (__get_mode() != CPSR_M_SYS));
}
/// Check if in Fault
/// \return true, false
__STATIC_INLINE bool_t IsFault (void) {
return ((__get_mode() == CPSR_M_ABT) || (__get_mode() == CPSR_M_UND));
}
/// Check if in SVCall IRQ
/// \return true, false
__STATIC_INLINE bool_t IsSVCallIrq (void) {
return (SVC_Active != 0U);
}
/// Check if in PendSV IRQ
/// \return true, false
__STATIC_INLINE bool_t IsPendSvIrq (void) {
return ((__get_mode() == CPSR_M_SVC) && (SVC_Active == 0U) && (IRQ_PendSV != 0U));
}
/// Check if in Tick Timer IRQ
/// \return true, false
__STATIC_INLINE bool_t IsTickIrq (int32_t tick_irqn) {
return ((__get_mode() == CPSR_M_SVC) && (IRQ_GetActiveIRQ() == OS_Tick_GetIRQn()));
}
/// Check if IRQ is Masked
/// \return true=masked, false=not masked
__STATIC_INLINE bool_t IsIrqMasked (void) {
return FALSE;
}
// ==== Core Peripherals functions ====
/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A)
__STATIC_INLINE void SVC_Setup (void) {
}
/// Get Pending SV (Service Call) Flag
/// \return Pending SV Flag
__STATIC_INLINE uint8_t GetPendSV (void) {
return (IRQ_PendSV);
}
/// Clear Pending SV (Service Call) Flag
__STATIC_INLINE void ClrPendSV (void) {
IRQ_PendSV = 0U;
}
/// Set Pending SV (Service Call) Flag
__STATIC_INLINE void SetPendSV (void) {
IRQ_PendSV = 1U;
}
// ==== Service Calls definitions ====
//lint -save -e9023 -e9024 -e9026 "Function-like macros using '#/##'" [MISRA Note 10]
#if defined(RTX_SVC_PTR_CHECK)
#warning "SVC Function Pointer checking is not supported!"
#endif
#if defined(__CC_ARM)
#define SVC_INDIRECT(n) __svc_indirect(n)
#define SVC0_0N(f,t) \
SVC_INDIRECT(0) t svc##f (t(*)()); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
svc##f(svcRtx##f); \
}
#define SVC0_0(f,t) \
SVC_INDIRECT(0) t svc##f (t(*)()); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
return svc##f(svcRtx##f); \
}
#define SVC0_1N(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
svc##f(svcRtx##f,a1); \
}
#define SVC0_1(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
return svc##f(svcRtx##f,a1); \
}
#define SVC0_2(f,t,t1,t2) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
return svc##f(svcRtx##f,a1,a2); \
}
#define SVC0_3(f,t,t1,t2,t3) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
return svc##f(svcRtx##f,a1,a2,a3); \
}
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
return svc##f(svcRtx##f,a1,a2,a3,a4); \
}
#elif defined(__ICCARM__)
#define SVC_ArgF(f) \
__asm( \
"mov r12,%0\n" \
:: "r"(&f): "r12" \
);
#define STRINGIFY(a) #a
#define SVC_INDIRECT(n) _Pragma(STRINGIFY(svc_number = n)) __svc
#define SVC0_0N(f,t) \
SVC_INDIRECT(0) t svc##f (); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
svc##f(); \
}
#define SVC0_0(f,t) \
SVC_INDIRECT(0) t svc##f (); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(svcRtx##f); \
return svc##f(); \
}
#define SVC0_1N(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t1 a1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgF(svcRtx##f); \
svc##f(a1); \
}
#define SVC0_1(f,t,t1) \
SVC_INDIRECT(0) t svc##f (t1 a1); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1); \
}
#define SVC0_2(f,t,t1,t2) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2); \
}
#define SVC0_3(f,t,t1,t2,t3) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2,a3); \
}
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
SVC_ArgF(svcRtx##f); \
return svc##f(a1,a2,a3,a4); \
}
#else // !(defined(__CC_ARM) || defined(__ICCARM__))
#define SVC_RegF "r12"
#define SVC_ArgN(n) \
register uint32_t __r##n __ASM("r"#n)
#define SVC_ArgR(n,a) \
register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
#if (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))
#define SVC_ArgF(f) \
register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)jmpRtx##f
#else
#define SVC_ArgF(f) \
register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)svcRtx##f
#endif
#define SVC_In0 "r"(__rf)
#define SVC_In1 "r"(__rf),"r"(__r0)
#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1)
#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2)
#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3)
#define SVC_Out0
#define SVC_Out1 "=r"(__r0)
#define SVC_CL0
#define SVC_CL1 "r0"
#define SVC_Call0(in, out, cl) \
__ASM volatile ("svc 0" : out : in : cl)
#if (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))
#define SVC_Jump(f) \
__ASM volatile ( \
".align 2\n\t" \
"b.w %[adr]" : : [adr] "X" (f) \
)
#define SVC_Veneer_Prototye(f) \
__STATIC_INLINE void jmpRtx##f (void);
#define SVC_Veneer_Function(f) \
__attribute__((naked,section(".text.os.svc.veneer."#f))) \
__STATIC_INLINE void jmpRtx##f (void) { \
SVC_Jump(svcRtx##f); \
}
#else
#define SVC_Veneer_Prototye(f)
#define SVC_Veneer_Function(f)
#endif
#define SVC0_0N(f,t) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgF(f); \
SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1); \
} \
SVC_Veneer_Function(f)
#define SVC0_0(f,t) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (void) { \
SVC_ArgN(0); \
SVC_ArgF(f); \
SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_1N(f,t,t1) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(f); \
SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
} \
SVC_Veneer_Function(f)
#define SVC0_1(f,t,t1) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1) { \
SVC_ArgR(0,a1); \
SVC_ArgF(f); \
SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_2(f,t,t1,t2) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgF(f); \
SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_3(f,t,t1,t2,t3) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgR(2,a3); \
SVC_ArgF(f); \
SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#define SVC0_4(f,t,t1,t2,t3,t4) \
SVC_Veneer_Prototye(f) \
__attribute__((always_inline)) \
__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
SVC_ArgR(0,a1); \
SVC_ArgR(1,a2); \
SVC_ArgR(2,a3); \
SVC_ArgR(3,a4); \
SVC_ArgF(f); \
SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \
return (t) __r0; \
} \
SVC_Veneer_Function(f)
#endif
//lint -restore [MISRA Note 10]
// ==== Exclusive Access Operation ====
#if (EXCLUSIVE_ACCESS == 1)
//lint ++flb "Library Begin" [MISRA Note 12]
/// Atomic Access Operation: Write (8-bit)
/// \param[in] mem Memory address
/// \param[in] val Value to write
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
mov r2,r0
1
ldrexb r0,[r2]
strexb r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint8_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexb %[ret],[%[mem]]\n\t"
"strexb %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n\t"
: [ret] "=&l" (ret),
[res] "=&l" (res)
: [mem] "l" (mem),
[val] "l" (val)
: "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Set bits (32-bit)
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return New value
#if defined(__CC_ARM)
static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
mov r2,r0
1
ldrex r0,[r2]
orr r0,r0,r1
strex r3,r0,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[val],[%[mem]]\n\t"
"orr %[ret],%[val],%[bits]\n\t"
"strex %[res],%[ret],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Clear bits (32-bit)
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
bic r4,r0,r1
strex r3,r4,[r2]
cmp r3,#0
bne %B1
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"bic %[val],%[ret],%[bits]\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Active bits before clearing or 0 if not active
#if defined(__CC_ARM)
static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
and r4,r0,r1
cmp r4,r1
beq %F2
clrex
movs r0,#0
pop {r4,pc}
2
bic r4,r0,r1
strex r3,r4,[r2]
cmp r3,#0
bne %B1
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"and %[val],%[ret],%[bits]\n\t"
"cmp %[val],%[bits]\n\t"
"beq 2f\n\t"
"clrex\n\t"
"movs %[ret],#0\n\t"
"b 3f\n"
"2:\n\t"
"bic %[val],%[ret],%[bits]\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them
/// \param[in] mem Memory address
/// \param[in] bits Bit mask
/// \return Active bits before clearing or 0 if not active
#if defined(__CC_ARM)
static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
push {r4,lr}
mov r2,r0
1
ldrex r0,[r2]
tst r0,r1
bne %F2
clrex
movs r0,#0
pop {r4,pc}
2
bic r4,r0,r1
strex r3,r4,[r2]
cmp r3,#0
bne %B1
pop {r4,pc}
}
#else
__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"tst %[ret],%[bits]\n\t"
"bne 2f\n\t"
"clrex\n\t"
"movs %[ret],#0\n\t"
"b 3f\n"
"2:\n\t"
"bic %[val],%[ret],%[bits]\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[bits] "l" (bits)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (32-bit)
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_inc32 (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
adds r1,r0,#1
strex r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"adds %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (16-bit) if Less Than
/// \param[in] mem Memory address
/// \param[in] max Maximum value
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
push {r4,lr}
mov r2,r0
1
ldrexh r0,[r2]
cmp r1,r0
bhi %F2
clrex
pop {r4,pc}
2
adds r4,r0,#1
strexh r3,r4,[r2]
cmp r3,#0
bne %B1
pop {r4,pc}
}
#else
__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"cmp %[max],%[ret]\n\t"
"bhi 2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"adds %[val],%[ret],#1\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[max] "l" (max)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Increment (16-bit) and clear on Limit
/// \param[in] mem Memory address
/// \param[in] max Maximum value
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
push {r4,lr}
mov r2,r0
1
ldrexh r0,[r2]
adds r4,r0,#1
cmp r1,r4
bhi %F2
movs r4,#0
2
strexh r3,r4,[r2]
cmp r3,#0
bne %B1
pop {r4,pc}
}
#else
__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"adds %[val],%[ret],#1\n\t"
"cmp %[lim],%[val]\n\t"
"bhi 2f\n\t"
"movs %[val],#0\n"
"2:\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem),
[lim] "l" (lim)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (32-bit)
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_dec32 (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
subs r1,r0,#1
strex r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"subs %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (32-bit) if Not Zero
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint32_t atomic_dec32_nz (uint32_t *mem) {
mov r2,r0
1
ldrex r0,[r2]
cmp r0,#0
bne %F2
clrex
bx lr
2
subs r1,r0,#1
strex r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint32_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[mem]]\n\t"
"cmp %[ret],#0\n\t"
"bne 2f\n"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"subs %[val],%[ret],#1\n\t"
"strex %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Decrement (16-bit) if Not Zero
/// \param[in] mem Memory address
/// \return Previous value
#if defined(__CC_ARM)
static __asm uint16_t atomic_dec16_nz (uint16_t *mem) {
mov r2,r0
1
ldrexh r0,[r2]
cmp r0,#0
bne %F2
clrex
bx lr
2
subs r1,r0,#1
strexh r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register uint16_t ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrexh %[ret],[%[mem]]\n\t"
"cmp %[ret],#0\n\t"
"bne 2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"subs %[val],%[ret],#1\n\t"
"strexh %[res],%[val],[%[mem]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [mem] "l" (mem)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Link Get
/// \param[in] root Root address
/// \return Link
#if defined(__CC_ARM)
static __asm void *atomic_link_get (void **root) {
mov r2,r0
1
ldrex r0,[r2]
cmp r0,#0
bne %F2
clrex
bx lr
2
ldr r1,[r0]
strex r3,r1,[r2]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE void *atomic_link_get (void **root) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
register void *ret;
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldrex %[ret],[%[root]]\n\t"
"cmp %[ret],#0\n\t"
"bne 2f\n\t"
"clrex\n\t"
"b 3f\n"
"2:\n\t"
"ldr %[val],[%[ret]]\n\t"
"strex %[res],%[val],[%[root]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
"3:"
: [ret] "=&l" (ret),
[val] "=&l" (val),
[res] "=&l" (res)
: [root] "l" (root)
: "cc", "memory"
);
return ret;
}
#endif
/// Atomic Access Operation: Link Put
/// \param[in] root Root address
/// \param[in] lnk Link
#if defined(__CC_ARM)
static __asm void atomic_link_put (void **root, void *link) {
1
ldr r2,[r0]
str r2,[r1]
dmb
ldrex r2,[r0]
ldr r3,[r1]
cmp r3,r2
bne %B1
strex r3,r1,[r0]
cmp r3,#0
bne %B1
bx lr
}
#else
__STATIC_INLINE void atomic_link_put (void **root, void *link) {
#ifdef __ICCARM__
#pragma diag_suppress=Pe550
#endif
register uint32_t val1, val2, res;
#ifdef __ICCARM__
#pragma diag_default=Pe550
#endif
__ASM volatile (
#ifndef __ICCARM__
".syntax unified\n\t"
#endif
"1:\n\t"
"ldr %[val1],[%[root]]\n\t"
"str %[val1],[%[link]]\n\t"
"dmb\n\t"
"ldrex %[val1],[%[root]]\n\t"
"ldr %[val2],[%[link]]\n\t"
"cmp %[val2],%[val1]\n\t"
"bne 1b\n\t"
"strex %[res],%[link],[%[root]]\n\t"
"cmp %[res],#0\n\t"
"bne 1b\n"
: [val1] "=&l" (val1),
[val2] "=&l" (val2),
[res] "=&l" (res)
: [root] "l" (root),
[link] "l" (link)
: "cc", "memory"
);
}
#endif
//lint --flb "Library End" [MISRA Note 12]
#endif // (EXCLUSIVE_ACCESS == 1)
#endif // RTX_CORE_CA_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 9,842 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX Library definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_LIB_H_
#define RTX_LIB_H_
#include <string.h>
#include "rtx_def.h" // RTX Configuration definitions
#include "rtx_core_c.h" // Cortex core definitions
#ifdef RTX_TZ_CONTEXT
#include "tz_context.h" // TrustZone Context API
#endif
#include "os_tick.h" // CMSIS OS Tick API
#include "cmsis_os2.h" // CMSIS RTOS API
#include "rtx_os.h" // RTX OS definitions
#include "rtx_evr.h" // RTX Event Recorder definitions
// ==== Library defines ====
#define os_thread_t osRtxThread_t
#define os_timer_t osRtxTimer_t
#define os_timer_finfo_t osRtxTimerFinfo_t
#define os_event_flags_t osRtxEventFlags_t
#define os_mutex_t osRtxMutex_t
#define os_semaphore_t osRtxSemaphore_t
#define os_mp_info_t osRtxMpInfo_t
#define os_memory_pool_t osRtxMemoryPool_t
#define os_message_t osRtxMessage_t
#define os_message_queue_t osRtxMessageQueue_t
#define os_object_t osRtxObject_t
// ==== Library sections ====
#if defined(__CC_ARM) || \
(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
// Referenced through linker
//lint -esym(528, __os_thread_cb_start__, __os_thread_cb_length__)
//lint -esym(528, __os_timer_cb_start__, __os_timer_cb_length__)
//lint -esym(528, __os_evflags_cb_start__, __os_evflags_cb_length__)
//lint -esym(528, __os_mutex_cb_start__, __os_mutex_cb_length__)
//lint -esym(528, __os_semaphore_cb_start__, __os_semaphore_cb_length__)
//lint -esym(528, __os_mempool_cb_start__, __os_mempool_cb_length__)
//lint -esym(528, __os_msgqueue_cb_start__, __os_msgqueue_cb_length__)
// Accessed through linker
//lint -esym(551, __os_thread_cb_start__, __os_thread_cb_length__)
//lint -esym(551, __os_timer_cb_start__, __os_timer_cb_length__)
//lint -esym(551, __os_evflags_cb_start__, __os_evflags_cb_length__)
//lint -esym(551, __os_mutex_cb_start__, __os_mutex_cb_length__)
//lint -esym(551, __os_semaphore_cb_start__, __os_semaphore_cb_length__)
//lint -esym(551, __os_mempool_cb_start__, __os_mempool_cb_length__)
//lint -esym(551, __os_msgqueue_cb_start__, __os_msgqueue_cb_length__)
// Initialized through linker
//lint -esym(728, __os_thread_cb_start__, __os_thread_cb_length__)
//lint -esym(728, __os_timer_cb_start__, __os_timer_cb_length__)
//lint -esym(728, __os_evflags_cb_start__, __os_evflags_cb_length__)
//lint -esym(728, __os_mutex_cb_start__, __os_mutex_cb_length__)
//lint -esym(728, __os_semaphore_cb_start__, __os_semaphore_cb_length__)
//lint -esym(728, __os_mempool_cb_start__, __os_mempool_cb_length__)
//lint -esym(728, __os_msgqueue_cb_start__, __os_msgqueue_cb_length__)
// Global scope
//lint -esym(9003, __os_thread_cb_start__, __os_thread_cb_length__)
//lint -esym(9003, __os_timer_cb_start__, __os_timer_cb_length__)
//lint -esym(9003, __os_evflags_cb_start__, __os_evflags_cb_length__)
//lint -esym(9003, __os_mutex_cb_start__, __os_mutex_cb_length__)
//lint -esym(9003, __os_semaphore_cb_start__, __os_semaphore_cb_length__)
//lint -esym(9003, __os_mempool_cb_start__, __os_mempool_cb_length__)
//lint -esym(9003, __os_msgqueue_cb_start__, __os_msgqueue_cb_length__)
static const uint32_t __os_thread_cb_start__ __attribute__((weakref(".bss.os.thread.cb$$Base")));
static const uint32_t __os_thread_cb_length__ __attribute__((weakref(".bss.os.thread.cb$$Length")));
static const uint32_t __os_timer_cb_start__ __attribute__((weakref(".bss.os.timer.cb$$Base")));
static const uint32_t __os_timer_cb_length__ __attribute__((weakref(".bss.os.timer.cb$$Length")));
static const uint32_t __os_evflags_cb_start__ __attribute__((weakref(".bss.os.evflags.cb$$Base")));
static const uint32_t __os_evflags_cb_length__ __attribute__((weakref(".bss.os.evflags.cb$$Length")));
static const uint32_t __os_mutex_cb_start__ __attribute__((weakref(".bss.os.mutex.cb$$Base")));
static const uint32_t __os_mutex_cb_length__ __attribute__((weakref(".bss.os.mutex.cb$$Length")));
static const uint32_t __os_semaphore_cb_start__ __attribute__((weakref(".bss.os.semaphore.cb$$Base")));
static const uint32_t __os_semaphore_cb_length__ __attribute__((weakref(".bss.os.semaphore.cb$$Length")));
static const uint32_t __os_mempool_cb_start__ __attribute__((weakref(".bss.os.mempool.cb$$Base")));
static const uint32_t __os_mempool_cb_length__ __attribute__((weakref(".bss.os.mempool.cb$$Length")));
static const uint32_t __os_msgqueue_cb_start__ __attribute__((weakref(".bss.os.msgqueue.cb$$Base")));
static const uint32_t __os_msgqueue_cb_length__ __attribute__((weakref(".bss.os.msgqueue.cb$$Length")));
#else
extern const uint32_t __os_thread_cb_start__ __attribute__((weak));
extern const uint32_t __os_thread_cb_length__ __attribute__((weak));
extern const uint32_t __os_timer_cb_start__ __attribute__((weak));
extern const uint32_t __os_timer_cb_length__ __attribute__((weak));
extern const uint32_t __os_evflags_cb_start__ __attribute__((weak));
extern const uint32_t __os_evflags_cb_length__ __attribute__((weak));
extern const uint32_t __os_mutex_cb_start__ __attribute__((weak));
extern const uint32_t __os_mutex_cb_length__ __attribute__((weak));
extern const uint32_t __os_semaphore_cb_start__ __attribute__((weak));
extern const uint32_t __os_semaphore_cb_length__ __attribute__((weak));
extern const uint32_t __os_mempool_cb_start__ __attribute__((weak));
extern const uint32_t __os_mempool_cb_length__ __attribute__((weak));
extern const uint32_t __os_msgqueue_cb_start__ __attribute__((weak));
extern const uint32_t __os_msgqueue_cb_length__ __attribute__((weak));
#endif
// ==== Inline functions ====
// Thread ID
__STATIC_INLINE os_thread_t *osRtxThreadId (osThreadId_t thread_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_thread_t *)thread_id);
}
// Timer ID
__STATIC_INLINE os_timer_t *osRtxTimerId (osTimerId_t timer_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_timer_t *)timer_id);
}
// Event Flags ID
__STATIC_INLINE os_event_flags_t *osRtxEventFlagsId (osEventFlagsId_t ef_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_event_flags_t *)ef_id);
}
// Mutex ID
__STATIC_INLINE os_mutex_t *osRtxMutexId (osMutexId_t mutex_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_mutex_t *)mutex_id);
}
// Semaphore ID
__STATIC_INLINE os_semaphore_t *osRtxSemaphoreId (osSemaphoreId_t semaphore_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_semaphore_t *)semaphore_id);
}
// Memory Pool ID
__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolId (osMemoryPoolId_t mp_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_memory_pool_t *)mp_id);
}
// Message Queue ID
__STATIC_INLINE os_message_queue_t *osRtxMessageQueueId (osMessageQueueId_t mq_id) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2]
return ((os_message_queue_t *)mq_id);
}
// Generic Object
__STATIC_INLINE os_object_t *osRtxObject (void *object) {
//lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 3]
return ((os_object_t *)object);
}
// Thread Object
__STATIC_INLINE os_thread_t *osRtxThreadObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_thread_t *)object);
}
// Timer Object
__STATIC_INLINE os_timer_t *osRtxTimerObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_timer_t *)object);
}
// Event Flags Object
__STATIC_INLINE os_event_flags_t *osRtxEventFlagsObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_event_flags_t *)object);
}
// Mutex Object
__STATIC_INLINE os_mutex_t *osRtxMutexObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_mutex_t *)object);
}
// Semaphore Object
__STATIC_INLINE os_semaphore_t *osRtxSemaphoreObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_semaphore_t *)object);
}
// Memory Pool Object
__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_memory_pool_t *)object);
}
// Message Queue Object
__STATIC_INLINE os_message_queue_t *osRtxMessageQueueObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_message_queue_t *)object);
}
// Message Object
__STATIC_INLINE os_message_t *osRtxMessageObject (os_object_t *object) {
//lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4]
return ((os_message_t *)object);
}
// Kernel State
__STATIC_INLINE osKernelState_t osRtxKernelState (void) {
//lint -e{9030} -e{9034} "cast to enum"
return ((osKernelState_t)(osRtxInfo.kernel.state));
}
// Thread State
__STATIC_INLINE osThreadState_t osRtxThreadState (const os_thread_t *thread) {
uint8_t state = thread->state & osRtxThreadStateMask;
//lint -e{9030} -e{9034} "cast to enum"
return ((osThreadState_t)state);
}
// Thread Priority
__STATIC_INLINE osPriority_t osRtxThreadPriority (const os_thread_t *thread) {
//lint -e{9030} -e{9034} "cast to enum"
return ((osPriority_t)thread->priority);
}
// Kernel Get State
__STATIC_INLINE uint8_t osRtxKernelGetState (void) {
return osRtxInfo.kernel.state;
}
// Thread Get/Set Running
__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) {
return osRtxInfo.thread.run.curr;
}
__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) {
osRtxInfo.thread.run.curr = thread;
}
// ==== Library functions ====
// Kernel Library functions
extern void osRtxKernelBeforeInit (void);
// Thread Library functions
extern void osRtxThreadListPut (os_object_t *object, os_thread_t *thread);
extern os_thread_t *osRtxThreadListGet (os_object_t *object);
extern void osRtxThreadListSort (os_thread_t *thread);
extern void osRtxThreadListRemove (os_thread_t *thread);
extern void osRtxThreadReadyPut (os_thread_t *thread);
//lint -esym(759,osRtxThreadDelayRemove) "Prototype in header"
//lint -esym(765,osRtxThreadDelayRemove) "Global scope"
extern void osRtxThreadDelayRemove (os_thread_t *thread);
extern void osRtxThreadDelayTick (void);
extern uint32_t *osRtxThreadRegPtr (const os_thread_t *thread);
extern void osRtxThreadSwitch (os_thread_t *thread);
extern void osRtxThreadDispatch (os_thread_t *thread);
extern void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch);
extern bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout);
#ifdef RTX_STACK_CHECK
extern bool_t osRtxThreadStackCheck (const os_thread_t *thread);
#endif
#ifdef RTX_THREAD_WATCHDOG
//lint -esym(759,osRtxThreadWatchdogRemove) "Prototype in header"
//lint -esym(765,osRtxThreadWatchdogRemove) "Global scope"
extern void osRtxThreadWatchdogRemove(const os_thread_t *thread);
extern void osRtxThreadWatchdogTick (void);
#endif
//lint -esym(759,osRtxThreadJoinWakeup) "Prototype in header"
//lint -esym(765,osRtxThreadJoinWakeup) "Global scope"
extern void osRtxThreadJoinWakeup (const os_thread_t *thread);
//lint -esym(759,osRtxThreadDestroy) "Prototype in header"
//lint -esym(765,osRtxThreadDestroy) "Global scope"
extern void osRtxThreadDestroy (os_thread_t *thread);
extern void osRtxThreadBeforeFree (os_thread_t *thread);
extern bool_t osRtxThreadStartup (void);
// Timer Library functions
extern int32_t osRtxTimerSetup (void);
extern void osRtxTimerThread (void *argument);
#ifdef RTX_SAFETY_CLASS
extern void osRtxTimerDeleteClass (uint32_t safety_class, uint32_t mode);
#endif
// Mutex Library functions
extern void osRtxMutexOwnerRelease (os_mutex_t *mutex_list);
extern void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup);
#ifdef RTX_SAFETY_CLASS
extern void osRtxMutexDeleteClass (uint32_t safety_class, uint32_t mode);
#endif
// Semaphore Library functions
#ifdef RTX_SAFETY_CLASS
extern void osRtxSemaphoreDeleteClass (uint32_t safety_class, uint32_t mode);
#endif
// Event Flags Library functions
#ifdef RTX_SAFETY_CLASS
extern void osRtxEventFlagsDeleteClass(uint32_t safety_class, uint32_t mode);
#endif
// Memory Heap Library functions
extern uint32_t osRtxMemoryInit (void *mem, uint32_t size);
extern void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type);
extern uint32_t osRtxMemoryFree (void *mem, void *block);
// Memory Pool Library functions
extern uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem);
extern void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info);
extern osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block);
#ifdef RTX_SAFETY_CLASS
extern void osRtxMemoryPoolDeleteClass(uint32_t safety_class, uint32_t mode);
#endif
// Message Queue Library functions
extern int32_t osRtxMessageQueueTimerSetup (void);
#ifdef RTX_SAFETY_CLASS
extern void osRtxMessageQueueDeleteClass(uint32_t safety_class, uint32_t mode);
#endif
// System Library functions
extern void osRtxTick_Handler (void);
extern void osRtxPendSV_Handler (void);
extern void osRtxPostProcess (os_object_t *object);
#endif // RTX_LIB_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_lib.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 4,176 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Semaphore functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxSemaphoreMemUsage \
__attribute__((section(".data.os.semaphore.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Decrement Semaphore tokens.
/// \param[in] semaphore semaphore object.
/// \return 1 - success, 0 - failure.
static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t ret;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
if (semaphore->tokens != 0U) {
semaphore->tokens--;
ret = 1U;
} else {
ret = 0U;
}
if (primask == 0U) {
__enable_irq();
}
#else
if (atomic_dec16_nz(&semaphore->tokens) != 0U) {
ret = 1U;
} else {
ret = 0U;
}
#endif
return ret;
}
/// Increment Semaphore tokens.
/// \param[in] semaphore semaphore object.
/// \return 1 - success, 0 - failure.
static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t ret;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
if (semaphore->tokens < semaphore->max_tokens) {
semaphore->tokens++;
ret = 1U;
} else {
ret = 0U;
}
if (primask == 0U) {
__enable_irq();
}
#else
if (atomic_inc16_lt(&semaphore->tokens, semaphore->max_tokens) < semaphore->max_tokens) {
ret = 1U;
} else {
ret = 0U;
}
#endif
return ret;
}
/// Verify that Semaphore object pointer is valid.
/// \param[in] semaphore semaphore object.
/// \return true - valid, false - invalid.
static bool_t IsSemaphorePtrValid (const os_semaphore_t *semaphore) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_semaphore_cb_start__;
uint32_t cb_length = (uint32_t)&__os_semaphore_cb_length__;
// Check the section boundaries
if (((uint32_t)semaphore - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)semaphore - cb_start) % sizeof(os_semaphore_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (semaphore == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Destroy a Semaphore object.
/// \param[in] semaphore semaphore object.
static void osRtxSemaphoreDestroy (os_semaphore_t *semaphore) {
// Mark object as invalid
semaphore->id = osRtxIdInvalid;
// Free object memory
if ((semaphore->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore);
#else
if (osRtxInfo.mpi.semaphore != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, semaphore);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxSemaphoreMemUsage.cnt_free++;
#endif
}
EvrRtxSemaphoreDestroyed(semaphore);
}
#ifdef RTX_SAFETY_CLASS
/// Delete a Semaphore safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxSemaphoreDeleteClass (uint32_t safety_class, uint32_t mode) {
os_semaphore_t *semaphore;
os_thread_t *thread;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
semaphore = (os_semaphore_t *)(uint32_t)&__os_semaphore_cb_start__;
length = (uint32_t)&__os_semaphore_cb_length__;
while (length >= sizeof(os_semaphore_t)) {
if ( (semaphore->id == osRtxIdSemaphore) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((semaphore->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((semaphore->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
while (semaphore->thread_list != NULL) {
thread = osRtxThreadListGet(osRtxObject(semaphore));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
}
osRtxSemaphoreDestroy(semaphore);
}
length -= sizeof(os_semaphore_t);
semaphore++;
}
}
#endif
// ==== Post ISR processing ====
/// Semaphore post ISR processing.
/// \param[in] semaphore semaphore object.
static void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) {
os_thread_t *thread;
// Check if Thread is waiting for a token
if (semaphore->thread_list != NULL) {
// Try to acquire token
if (SemaphoreTokenDecrement(semaphore) != 0U) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(semaphore));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);
}
}
}
// ==== Service Calls ====
/// Create and Initialize a Semaphore object.
/// \note API identical to osSemaphoreNew
static osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
os_semaphore_t *semaphore;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
uint32_t attr_bits;
#endif
uint8_t flags;
const char *name;
// Check parameters
if ((max_count == 0U) || (max_count > osRtxSemaphoreTokenLimit) || (initial_count > max_count)) {
EvrRtxSemaphoreError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Process attributes
if (attr != NULL) {
name = attr->name;
#ifdef RTX_SAFETY_CLASS
attr_bits = attr->attr_bits;
#endif
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
semaphore = attr->cb_mem;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxSemaphoreError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (semaphore != NULL) {
if (!IsSemaphorePtrValid(semaphore) || (attr->cb_size != sizeof(os_semaphore_t))) {
EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
#ifdef RTX_SAFETY_CLASS
attr_bits = 0U;
#endif
semaphore = NULL;
}
// Allocate object memory if not provided
if (semaphore == NULL) {
if (osRtxInfo.mpi.semaphore != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
semaphore = osRtxMemoryPoolAlloc(osRtxInfo.mpi.semaphore);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
semaphore = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_semaphore_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (semaphore != NULL) {
uint32_t used;
osRtxSemaphoreMemUsage.cnt_alloc++;
used = osRtxSemaphoreMemUsage.cnt_alloc - osRtxSemaphoreMemUsage.cnt_free;
if (osRtxSemaphoreMemUsage.max_used < used) {
osRtxSemaphoreMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
if (semaphore != NULL) {
// Initialize control block
semaphore->id = osRtxIdSemaphore;
semaphore->flags = flags;
semaphore->attr = 0U;
semaphore->name = name;
semaphore->thread_list = NULL;
semaphore->tokens = (uint16_t)initial_count;
semaphore->max_tokens = (uint16_t)max_count;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
semaphore->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
semaphore->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
// Register post ISR processing function
osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess;
EvrRtxSemaphoreCreated(semaphore, semaphore->name);
} else {
EvrRtxSemaphoreError(NULL,(int32_t)osErrorNoMemory);
}
return semaphore;
}
/// Get name of a Semaphore object.
/// \note API identical to osSemaphoreGetName
static const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreGetName(semaphore, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxSemaphoreGetName(semaphore, semaphore->name);
return semaphore->name;
}
/// Acquire a Semaphore token or timeout if no tokens are available.
/// \note API identical to osSemaphoreAcquire
static osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
osStatus_t status;
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Try to acquire token
if (SemaphoreTokenDecrement(semaphore) != 0U) {
EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);
status = osOK;
} else {
// No token available
if (timeout != 0U) {
EvrRtxSemaphoreAcquirePending(semaphore, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout)) {
osRtxThreadListPut(osRtxObject(semaphore), osRtxThreadGetRunning());
} else {
EvrRtxSemaphoreAcquireTimeout(semaphore);
}
status = osErrorTimeout;
} else {
EvrRtxSemaphoreNotAcquired(semaphore);
status = osErrorResource;
}
}
return status;
}
/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
/// \note API identical to osSemaphoreRelease
static osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
os_thread_t *thread;
osStatus_t status;
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check if Thread is waiting for a token
if (semaphore->thread_list != NULL) {
EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(semaphore));
osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);
EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);
status = osOK;
} else {
// Try to release token
if (SemaphoreTokenIncrement(semaphore) != 0U) {
EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);
status = osOK;
} else {
EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);
status = osErrorResource;
}
}
return status;
}
/// Get current Semaphore token count.
/// \note API identical to osSemaphoreGetCount
static uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreGetCount(semaphore, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxSemaphoreGetCount(semaphore, semaphore->tokens);
return semaphore->tokens;
}
/// Delete a Semaphore object.
/// \note API identical to osSemaphoreDelete
static osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
os_thread_t *thread;
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Unblock waiting threads
if (semaphore->thread_list != NULL) {
do {
thread = osRtxThreadListGet(osRtxObject(semaphore));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
} while (semaphore->thread_list != NULL);
osRtxThreadDispatch(NULL);
}
osRtxSemaphoreDestroy(semaphore);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_3(SemaphoreNew, osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *)
SVC0_1(SemaphoreGetName, const char *, osSemaphoreId_t)
SVC0_2(SemaphoreAcquire, osStatus_t, osSemaphoreId_t, uint32_t)
SVC0_1(SemaphoreRelease, osStatus_t, osSemaphoreId_t)
SVC0_1(SemaphoreGetCount, uint32_t, osSemaphoreId_t)
SVC0_1(SemaphoreDelete, osStatus_t, osSemaphoreId_t)
//lint --flb "Library End"
// ==== ISR Calls ====
/// Acquire a Semaphore token or timeout if no tokens are available.
/// \note API identical to osSemaphoreAcquire
__STATIC_INLINE
osStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
osStatus_t status;
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore) || (timeout != 0U)) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Try to acquire token
if (SemaphoreTokenDecrement(semaphore) != 0U) {
EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);
status = osOK;
} else {
// No token available
EvrRtxSemaphoreNotAcquired(semaphore);
status = osErrorResource;
}
return status;
}
/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
/// \note API identical to osSemaphoreRelease
__STATIC_INLINE
osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);
osStatus_t status;
// Check parameters
if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {
EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Try to release token
if (SemaphoreTokenIncrement(semaphore) != 0U) {
// Register post ISR processing
osRtxPostProcess(osRtxObject(semaphore));
EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);
status = osOK;
} else {
EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);
status = osErrorResource;
}
return status;
}
// ==== Public API ====
/// Create and Initialize a Semaphore object.
osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
osSemaphoreId_t semaphore_id;
EvrRtxSemaphoreNew(max_count, initial_count, attr);
if (IsException() || IsIrqMasked()) {
EvrRtxSemaphoreError(NULL, (int32_t)osErrorISR);
semaphore_id = NULL;
} else {
semaphore_id = __svcSemaphoreNew(max_count, initial_count, attr);
}
return semaphore_id;
}
/// Get name of a Semaphore object.
const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxSemaphoreGetName(semaphore_id);
} else {
name = __svcSemaphoreGetName(semaphore_id);
}
return name;
}
/// Acquire a Semaphore token or timeout if no tokens are available.
osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
osStatus_t status;
EvrRtxSemaphoreAcquire(semaphore_id, timeout);
if (IsException() || IsIrqMasked()) {
status = isrRtxSemaphoreAcquire(semaphore_id, timeout);
} else {
status = __svcSemaphoreAcquire(semaphore_id, timeout);
}
return status;
}
/// Release a Semaphore token that was acquired by osSemaphoreAcquire.
osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
osStatus_t status;
EvrRtxSemaphoreRelease(semaphore_id);
if (IsException() || IsIrqMasked()) {
status = isrRtxSemaphoreRelease(semaphore_id);
} else {
status = __svcSemaphoreRelease(semaphore_id);
}
return status;
}
/// Get current Semaphore token count.
uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
count = svcRtxSemaphoreGetCount(semaphore_id);
} else {
count = __svcSemaphoreGetCount(semaphore_id);
}
return count;
}
/// Delete a Semaphore object.
osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {
osStatus_t status;
EvrRtxSemaphoreDelete(semaphore_id);
if (IsException() || IsIrqMasked()) {
EvrRtxSemaphoreError(semaphore_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcSemaphoreDelete(semaphore_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,486 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: RTX Library Configuration
*
* your_sha256_hash-------------
*/
#include "rtx_os.h"
#ifdef CMSIS_device_header
#include CMSIS_device_header
#else
#include "cmsis_compiler.h"
#endif
#ifdef RTE_Compiler_EventRecorder
#include "EventRecorder.h"
#include "EventRecorderConf.h"
#endif
#include "rtx_evr.h"
// System Configuration
// ====================
// Dynamic Memory
#if (OS_DYNAMIC_MEM_SIZE != 0)
#if ((OS_DYNAMIC_MEM_SIZE % 8) != 0)
#error "Invalid Dynamic Memory size!"
#endif
static uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \
__attribute__((section(".bss.os")));
#endif
// Kernel Tick Frequency
#if (OS_TICK_FREQ < 1)
#error "Invalid Kernel Tick Frequency!"
#endif
// ISR FIFO Queue
#if (OS_ISR_FIFO_QUEUE < 4)
#error "Invalid ISR FIFO Queue size!"
#endif
static void *os_isr_queue[OS_ISR_FIFO_QUEUE] \
__attribute__((section(".bss.os")));
// Thread Configuration
// ====================
#if (((OS_STACK_SIZE % 8) != 0) || (OS_STACK_SIZE < 72))
#error "Invalid default Thread Stack size!"
#endif
#if (((OS_IDLE_THREAD_STACK_SIZE % 8) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72))
#error "Invalid Idle Thread Stack size!"
#endif
#if (OS_THREAD_OBJ_MEM != 0)
#if (OS_THREAD_NUM == 0)
#error "Invalid number of user Threads!"
#endif
#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE % 8) != 0))
#error "Invalid total Stack size!"
#endif
// Thread Control Blocks
static osRtxThread_t os_thread_cb[OS_THREAD_NUM] \
__attribute__((section(".bss.os.thread.cb")));
// Thread Default Stack
#if (OS_THREAD_DEF_STACK_NUM != 0)
static uint64_t os_thread_def_stack[(OS_THREAD_DEF_STACK_NUM*OS_STACK_SIZE)/8] \
__attribute__((section(".bss.os.thread.stack")));
#endif
// Memory Pool for Thread Control Blocks
static osRtxMpInfo_t os_mpi_thread \
__attribute__((section(".data.os.thread.mpi"))) =
{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb[0], NULL, NULL };
// Memory Pool for Thread Default Stack
#if (OS_THREAD_DEF_STACK_NUM != 0)
static osRtxMpInfo_t os_mpi_def_stack \
__attribute__((section(".data.os.thread.mpi"))) =
{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack[0], NULL, NULL };
#endif
// Memory Pool for Thread Stack
#if (OS_THREAD_USER_STACK_SIZE != 0)
static uint64_t os_thread_stack[(16 + (8*OS_THREAD_NUM) + OS_THREAD_USER_STACK_SIZE)/8] \
__attribute__((section(".bss.os.thread.stack")));
#endif
#endif // (OS_THREAD_OBJ_MEM != 0)
// Idle Thread Control Block
static osRtxThread_t os_idle_thread_cb \
__attribute__((section(".bss.os.thread.cb")));
// Idle Thread Stack
static uint64_t os_idle_thread_stack[OS_IDLE_THREAD_STACK_SIZE/8] \
__attribute__((section(".bss.os.thread.idle.stack")));
// Idle Thread Attributes
static const osThreadAttr_t os_idle_thread_attr = {
//lint -e{835} -e{845} "Zero argument to operator"
#if defined(OS_IDLE_THREAD_NAME)
OS_IDLE_THREAD_NAME,
#else
NULL,
#endif
#ifdef RTX_SAFETY_CLASS
osSafetyClass((uint32_t)OS_IDLE_THREAD_CLASS) |
#endif
#ifdef RTX_EXECUTION_ZONE
osThreadZone((uint32_t)OS_IDLE_THREAD_ZONE) |
#endif
osThreadDetached,
&os_idle_thread_cb,
(uint32_t)sizeof(os_idle_thread_cb),
&os_idle_thread_stack[0],
(uint32_t)sizeof(os_idle_thread_stack),
osPriorityIdle,
#if defined(OS_IDLE_THREAD_TZ_MOD_ID)
(uint32_t)OS_IDLE_THREAD_TZ_MOD_ID,
#else
0U,
#endif
0U
};
// Timer Configuration
// ===================
#if (OS_TIMER_OBJ_MEM != 0)
#if (OS_TIMER_NUM == 0)
#error "Invalid number of Timer objects!"
#endif
// Timer Control Blocks
static osRtxTimer_t os_timer_cb[OS_TIMER_NUM] \
__attribute__((section(".bss.os.timer.cb")));
// Memory Pool for Timer Control Blocks
static osRtxMpInfo_t os_mpi_timer \
__attribute__((section(".data.os.timer.mpi"))) =
{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb[0], NULL, NULL };
#endif // (OS_TIMER_OBJ_MEM != 0)
#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
#if (((OS_TIMER_THREAD_STACK_SIZE % 8) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96))
#error "Invalid Timer Thread Stack size!"
#endif
// Timer Thread Control Block
static osRtxThread_t os_timer_thread_cb \
__attribute__((section(".bss.os.thread.cb")));
// Timer Thread Stack
static uint64_t os_timer_thread_stack[OS_TIMER_THREAD_STACK_SIZE/8] \
__attribute__((section(".bss.os.thread.timer.stack")));
// Timer Thread Attributes
static const osThreadAttr_t os_timer_thread_attr = {
//lint -e{835} -e{845} "Zero argument to operator"
#if defined(OS_TIMER_THREAD_NAME)
OS_TIMER_THREAD_NAME,
#else
NULL,
#endif
#ifdef RTX_SAFETY_CLASS
osSafetyClass((uint32_t)OS_TIMER_THREAD_CLASS) |
#endif
#ifdef RTX_EXECUTION_ZONE
osThreadZone((uint32_t)OS_TIMER_THREAD_ZONE) |
#endif
osThreadDetached,
&os_timer_thread_cb,
(uint32_t)sizeof(os_timer_thread_cb),
&os_timer_thread_stack[0],
(uint32_t)sizeof(os_timer_thread_stack),
//lint -e{9030} -e{9034} "cast from signed to enum"
(osPriority_t)OS_TIMER_THREAD_PRIO,
#if defined(OS_TIMER_THREAD_TZ_MOD_ID)
(uint32_t)OS_TIMER_THREAD_TZ_MOD_ID,
#else
0U,
#endif
0U
};
// Timer Message Queue Control Block
static osRtxMessageQueue_t os_timer_mq_cb \
__attribute__((section(".bss.os.msgqueue.cb")));
// Timer Message Queue Data
static uint32_t os_timer_mq_data[osRtxMessageQueueMemSize(OS_TIMER_CB_QUEUE,8)/4] \
__attribute__((section(".bss.os.msgqueue.mem")));
// Timer Message Queue Attributes
static const osMessageQueueAttr_t os_timer_mq_attr = {
//lint -e{835} -e{845} "Zero argument to operator"
NULL,
#ifdef RTX_SAFETY_CLASS
osSafetyClass((uint32_t)OS_TIMER_THREAD_CLASS) |
#endif
0U,
&os_timer_mq_cb,
(uint32_t)sizeof(os_timer_mq_cb),
&os_timer_mq_data[0],
(uint32_t)sizeof(os_timer_mq_data)
};
extern int32_t osRtxTimerSetup (void);
extern void osRtxTimerThread (void *argument);
#endif // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
// Event Flags Configuration
// =========================
#if (OS_EVFLAGS_OBJ_MEM != 0)
#if (OS_EVFLAGS_NUM == 0)
#error "Invalid number of Event Flags objects!"
#endif
// Event Flags Control Blocks
static osRtxEventFlags_t os_ef_cb[OS_EVFLAGS_NUM] \
__attribute__((section(".bss.os.evflags.cb")));
// Memory Pool for Event Flags Control Blocks
static osRtxMpInfo_t os_mpi_ef \
__attribute__((section(".data.os.evflags.mpi"))) =
{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb[0], NULL, NULL };
#endif // (OS_EVFLAGS_OBJ_MEM != 0)
// Mutex Configuration
// ===================
#if (OS_MUTEX_OBJ_MEM != 0)
#if (OS_MUTEX_NUM == 0)
#error "Invalid number of Mutex objects!"
#endif
// Mutex Control Blocks
static osRtxMutex_t os_mutex_cb[OS_MUTEX_NUM] \
__attribute__((section(".bss.os.mutex.cb")));
// Memory Pool for Mutex Control Blocks
static osRtxMpInfo_t os_mpi_mutex \
__attribute__((section(".data.os.mutex.mpi"))) =
{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb[0], NULL, NULL };
#endif // (OS_MUTEX_OBJ_MEM != 0)
// Semaphore Configuration
// =======================
#if (OS_SEMAPHORE_OBJ_MEM != 0)
#if (OS_SEMAPHORE_NUM == 0)
#error "Invalid number of Semaphore objects!"
#endif
// Semaphore Control Blocks
static osRtxSemaphore_t os_semaphore_cb[OS_SEMAPHORE_NUM] \
__attribute__((section(".bss.os.semaphore.cb")));
// Memory Pool for Semaphore Control Blocks
static osRtxMpInfo_t os_mpi_semaphore \
__attribute__((section(".data.os.semaphore.mpi"))) =
{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb[0], NULL, NULL };
#endif // (OS_SEMAPHORE_OBJ_MEM != 0)
// Memory Pool Configuration
// =========================
#if (OS_MEMPOOL_OBJ_MEM != 0)
#if (OS_MEMPOOL_NUM == 0)
#error "Invalid number of Memory Pool objects!"
#endif
// Memory Pool Control Blocks
static osRtxMemoryPool_t os_mp_cb[OS_MEMPOOL_NUM] \
__attribute__((section(".bss.os.mempool.cb")));
// Memory Pool for Memory Pool Control Blocks
static osRtxMpInfo_t os_mpi_mp \
__attribute__((section(".data.os.mempool.mpi"))) =
{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb[0], NULL, NULL };
// Memory Pool for Memory Pool Data Storage
#if (OS_MEMPOOL_DATA_SIZE != 0)
#if ((OS_MEMPOOL_DATA_SIZE % 8) != 0)
#error "Invalid Data Memory size for Memory Pools!"
#endif
static uint64_t os_mp_data[(16 + (8*OS_MEMPOOL_NUM) + OS_MEMPOOL_DATA_SIZE)/8] \
__attribute__((section(".bss.os.mempool.mem")));
#endif
#endif // (OS_MEMPOOL_OBJ_MEM != 0)
// Message Queue Configuration
// ===========================
#if (OS_MSGQUEUE_OBJ_MEM != 0)
#if (OS_MSGQUEUE_NUM == 0)
#error "Invalid number of Message Queue objects!"
#endif
// Message Queue Control Blocks
static osRtxMessageQueue_t os_mq_cb[OS_MSGQUEUE_NUM] \
__attribute__((section(".bss.os.msgqueue.cb")));
// Memory Pool for Message Queue Control Blocks
static osRtxMpInfo_t os_mpi_mq \
__attribute__((section(".data.os.msgqueue.mpi"))) =
{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb[0], NULL, NULL };
// Memory Pool for Message Queue Data Storage
#if (OS_MSGQUEUE_DATA_SIZE != 0)
#if ((OS_MSGQUEUE_DATA_SIZE % 8) != 0)
#error "Invalid Data Memory size for Message Queues!"
#endif
static uint64_t os_mq_data[(16 + ((8+12)*OS_MSGQUEUE_NUM) + OS_MSGQUEUE_DATA_SIZE + 7)/8] \
__attribute__((section(".bss.os.msgqueue.mem")));
#endif
#endif // (OS_MSGQUEUE_OBJ_MEM != 0)
// Event Recorder Configuration
// ============================
#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0))
#ifdef RTE_Compiler_EventRecorder
// Event Recorder Initialize
__STATIC_INLINE void evr_initialize (void) {
(void)EventRecorderInitialize(OS_EVR_LEVEL, (uint32_t)OS_EVR_START);
#if ((OS_EVR_MEMORY_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_MEMORY_LEVEL & 0x0FU, EvtRtxMemoryNo, EvtRtxMemoryNo);
(void)EventRecorderDisable(~OS_EVR_MEMORY_LEVEL & 0x0FU, EvtRtxMemoryNo, EvtRtxMemoryNo);
#endif
#if ((OS_EVR_KERNEL_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_KERNEL_LEVEL & 0x0FU, EvtRtxKernelNo, EvtRtxKernelNo);
(void)EventRecorderDisable(~OS_EVR_KERNEL_LEVEL & 0x0FU, EvtRtxKernelNo, EvtRtxKernelNo);
#endif
#if ((OS_EVR_THREAD_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_THREAD_LEVEL & 0x0FU, EvtRtxThreadNo, EvtRtxThreadNo);
(void)EventRecorderDisable(~OS_EVR_THREAD_LEVEL & 0x0FU, EvtRtxThreadNo, EvtRtxThreadNo);
#endif
#if ((OS_EVR_WAIT_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_WAIT_LEVEL & 0x0FU, EvtRtxWaitNo, EvtRtxWaitNo);
(void)EventRecorderDisable(~OS_EVR_WAIT_LEVEL & 0x0FU, EvtRtxWaitNo, EvtRtxWaitNo);
#endif
#if ((OS_EVR_THFLAGS_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_THFLAGS_LEVEL & 0x0FU, EvtRtxThreadFlagsNo, EvtRtxThreadFlagsNo);
(void)EventRecorderDisable(~OS_EVR_THFLAGS_LEVEL & 0x0FU, EvtRtxThreadFlagsNo, EvtRtxThreadFlagsNo);
#endif
#if ((OS_EVR_EVFLAGS_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_EVFLAGS_LEVEL & 0x0FU, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo);
(void)EventRecorderDisable(~OS_EVR_EVFLAGS_LEVEL & 0x0FU, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo);
#endif
#if ((OS_EVR_TIMER_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_TIMER_LEVEL & 0x0FU, EvtRtxTimerNo, EvtRtxTimerNo);
(void)EventRecorderDisable(~OS_EVR_TIMER_LEVEL & 0x0FU, EvtRtxTimerNo, EvtRtxTimerNo);
#endif
#if ((OS_EVR_MUTEX_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_MUTEX_LEVEL & 0x0FU, EvtRtxMutexNo, EvtRtxMutexNo);
(void)EventRecorderDisable(~OS_EVR_MUTEX_LEVEL & 0x0FU, EvtRtxMutexNo, EvtRtxMutexNo);
#endif
#if ((OS_EVR_SEMAPHORE_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo);
(void)EventRecorderDisable(~OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo);
#endif
#if ((OS_EVR_MEMPOOL_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_MEMPOOL_LEVEL & 0x0FU, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo);
(void)EventRecorderDisable(~OS_EVR_MEMPOOL_LEVEL & 0x0FU, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo);
#endif
#if ((OS_EVR_MSGQUEUE_LEVEL & 0x80U) != 0U)
(void)EventRecorderEnable( OS_EVR_MSGQUEUE_LEVEL & 0x0FU, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo);
(void)EventRecorderDisable(~OS_EVR_MSGQUEUE_LEVEL & 0x0FU, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo);
#endif
}
#else
#warning "Event Recorder cannot be initialized (Event Recorder component is not selected)!"
#define evr_initialize()
#endif
#endif // (OS_EVR_INIT != 0)
// OS Configuration
// ================
const osRtxConfig_t osRtxConfig \
__USED \
__attribute__((section(".rodata"))) =
{
//lint -e{835} "Zero argument to operator"
0U // Flags
#if (OS_PRIVILEGE_MODE != 0)
| osRtxConfigPrivilegedMode
#endif
#if (OS_STACK_CHECK != 0)
| osRtxConfigStackCheck
#endif
#if (OS_STACK_WATERMARK != 0)
| osRtxConfigStackWatermark
#endif
#ifdef RTX_SAFETY_FEATURES
| osRtxConfigSafetyFeatures
#ifdef RTX_SAFETY_CLASS
| osRtxConfigSafetyClass
#endif
#ifdef RTX_EXECUTION_ZONE
| osRtxConfigExecutionZone
#endif
#ifdef RTX_THREAD_WATCHDOG
| osRtxConfigThreadWatchdog
#endif
#ifdef RTX_OBJ_PTR_CHECK
| osRtxConfigObjPtrCheck
#endif
#ifdef RTX_SVC_PTR_CHECK
| osRtxConfigSVCPtrCheck
#endif
#endif
,
(uint32_t)OS_TICK_FREQ,
#if (OS_ROBIN_ENABLE != 0)
(uint32_t)OS_ROBIN_TIMEOUT,
#else
0U,
#endif
{ &os_isr_queue[0], (uint16_t)(sizeof(os_isr_queue)/sizeof(void *)), 0U },
{
// Memory Pools (Variable Block Size)
#if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0))
&os_thread_stack[0], sizeof(os_thread_stack),
#else
NULL, 0U,
#endif
#if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0))
&os_mp_data[0], sizeof(os_mp_data),
#else
NULL, 0U,
#endif
#if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0))
&os_mq_data[0], sizeof(os_mq_data),
#else
NULL, 0U,
#endif
#if (OS_DYNAMIC_MEM_SIZE != 0)
&os_mem[0], (uint32_t)OS_DYNAMIC_MEM_SIZE,
#else
NULL, 0U
#endif
},
{
// Memory Pools (Fixed Block Size)
#if (OS_THREAD_OBJ_MEM != 0)
#if (OS_THREAD_DEF_STACK_NUM != 0)
&os_mpi_def_stack,
#else
NULL,
#endif
&os_mpi_thread,
#else
NULL,
NULL,
#endif
#if (OS_TIMER_OBJ_MEM != 0)
&os_mpi_timer,
#else
NULL,
#endif
#if (OS_EVFLAGS_OBJ_MEM != 0)
&os_mpi_ef,
#else
NULL,
#endif
#if (OS_MUTEX_OBJ_MEM != 0)
&os_mpi_mutex,
#else
NULL,
#endif
#if (OS_SEMAPHORE_OBJ_MEM != 0)
&os_mpi_semaphore,
#else
NULL,
#endif
#if (OS_MEMPOOL_OBJ_MEM != 0)
&os_mpi_mp,
#else
NULL,
#endif
#if (OS_MSGQUEUE_OBJ_MEM != 0)
&os_mpi_mq,
#else
NULL,
#endif
},
(uint32_t)OS_STACK_SIZE,
&os_idle_thread_attr,
#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))
&os_timer_thread_attr,
osRtxTimerThread,
osRtxTimerSetup,
&os_timer_mq_attr,
(uint32_t)OS_TIMER_CB_QUEUE
#else
NULL,
NULL,
NULL,
NULL,
0U
#endif
};
// Non weak reference to library irq module
//lint -esym(526,irqRtxLib) "Defined by Exception handlers"
//lint -esym(714,irqRtxLibRef) "Non weak reference"
//lint -esym(765,irqRtxLibRef) "Global scope"
extern const uint8_t irqRtxLib;
extern const uint8_t * const irqRtxLibRef;
const uint8_t * const irqRtxLibRef = &irqRtxLib;
// Default User SVC Table
//lint -esym(714,osRtxUserSVC) "Referenced by Exception handlers"
//lint -esym(765,osRtxUserSVC) "Global scope"
//lint -e{9067} "extern array declared without size"
extern void * const osRtxUserSVC[];
__WEAK void * const osRtxUserSVC[1] = { (void *)0 };
#if (defined(RTX_SAFETY_CLASS) && defined(RTX_OBJ_PTR_CHECK) && \
!((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)))
extern void osRtxTimerDeleteClass(uint32_t safety_class, uint32_t mode);
// Default Timer Delete Class Function.
__WEAK void osRtxTimerDeleteClass(uint32_t safety_class, uint32_t mode) {
(void)safety_class;
(void)mode;
}
#endif
#ifdef RTX_THREAD_WATCHDOG
// Default Watchdog Alarm Handler.
__WEAK uint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id) {
(void)thread_id;
return 0U;
}
#endif
#ifdef RTX_EXECUTION_ZONE
// Default Zone Setup Function.
__WEAK void osZoneSetup_Callback (uint32_t zone) {
(void)zone;
}
#endif
// OS Sections
// ===========
#if defined(__CC_ARM) || \
(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
// Initialized through linker
//lint -esym(728, __os_thread_cb_start__, __os_thread_cb_end__)
//lint -esym(728, __os_timer_cb_start__, __os_timer_cb_end__)
//lint -esym(728, __os_evflags_cb_start__, __os_evflags_cb_end__)
//lint -esym(728, __os_mutex_cb_start__, __os_mutex_cb_end__)
//lint -esym(728, __os_semaphore_cb_start__, __os_semaphore_cb_end__)
//lint -esym(728, __os_mempool_cb_start__, __os_mempool_cb_end__)
//lint -esym(728, __os_msgqueue_cb_start__, __os_msgqueue_cb_end__)
static const uint32_t __os_thread_cb_start__ __attribute__((weakref(".bss.os.thread.cb$$Base")));
static const uint32_t __os_thread_cb_end__ __attribute__((weakref(".bss.os.thread.cb$$Limit")));
static const uint32_t __os_timer_cb_start__ __attribute__((weakref(".bss.os.timer.cb$$Base")));
static const uint32_t __os_timer_cb_end__ __attribute__((weakref(".bss.os.timer.cb$$Limit")));
static const uint32_t __os_evflags_cb_start__ __attribute__((weakref(".bss.os.evflags.cb$$Base")));
static const uint32_t __os_evflags_cb_end__ __attribute__((weakref(".bss.os.evflags.cb$$Limit")));
static const uint32_t __os_mutex_cb_start__ __attribute__((weakref(".bss.os.mutex.cb$$Base")));
static const uint32_t __os_mutex_cb_end__ __attribute__((weakref(".bss.os.mutex.cb$$Limit")));
static const uint32_t __os_semaphore_cb_start__ __attribute__((weakref(".bss.os.semaphore.cb$$Base")));
static const uint32_t __os_semaphore_cb_end__ __attribute__((weakref(".bss.os.semaphore.cb$$Limit")));
static const uint32_t __os_mempool_cb_start__ __attribute__((weakref(".bss.os.mempool.cb$$Base")));
static const uint32_t __os_mempool_cb_end__ __attribute__((weakref(".bss.os.mempool.cb$$Limit")));
static const uint32_t __os_msgqueue_cb_start__ __attribute__((weakref(".bss.os.msgqueue.cb$$Base")));
static const uint32_t __os_msgqueue_cb_end__ __attribute__((weakref(".bss.os.msgqueue.cb$$Limit")));
#else
extern const uint32_t __os_thread_cb_start__ __attribute__((weak));
extern const uint32_t __os_thread_cb_end__ __attribute__((weak));
extern const uint32_t __os_timer_cb_start__ __attribute__((weak));
extern const uint32_t __os_timer_cb_end__ __attribute__((weak));
extern const uint32_t __os_evflags_cb_start__ __attribute__((weak));
extern const uint32_t __os_evflags_cb_end__ __attribute__((weak));
extern const uint32_t __os_mutex_cb_start__ __attribute__((weak));
extern const uint32_t __os_mutex_cb_end__ __attribute__((weak));
extern const uint32_t __os_semaphore_cb_start__ __attribute__((weak));
extern const uint32_t __os_semaphore_cb_end__ __attribute__((weak));
extern const uint32_t __os_mempool_cb_start__ __attribute__((weak));
extern const uint32_t __os_mempool_cb_end__ __attribute__((weak));
extern const uint32_t __os_msgqueue_cb_start__ __attribute__((weak));
extern const uint32_t __os_msgqueue_cb_end__ __attribute__((weak));
#endif
//lint -e{9067} "extern array declared without size"
extern const uint32_t * const os_cb_sections[];
//lint -esym(714,os_cb_sections) "Referenced by debugger"
//lint -esym(765,os_cb_sections) "Global scope"
const uint32_t * const os_cb_sections[] \
__USED \
__attribute__((section(".rodata"))) =
{
&__os_thread_cb_start__,
&__os_thread_cb_end__,
&__os_timer_cb_start__,
&__os_timer_cb_end__,
&__os_evflags_cb_start__,
&__os_evflags_cb_end__,
&__os_mutex_cb_start__,
&__os_mutex_cb_end__,
&__os_semaphore_cb_start__,
&__os_semaphore_cb_end__,
&__os_mempool_cb_start__,
&__os_mempool_cb_end__,
&__os_msgqueue_cb_start__,
&__os_msgqueue_cb_end__
};
// OS Initialization
// =================
#if defined(__CC_ARM) || \
(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#ifndef __MICROLIB
//lint -esym(714,_platform_post_stackheap_init) "Referenced by C library"
//lint -esym(765,_platform_post_stackheap_init) "Global scope"
extern void _platform_post_stackheap_init (void);
__WEAK void _platform_post_stackheap_init (void) {
(void)osKernelInitialize();
}
#endif
#elif defined(__GNUC__)
extern void software_init_hook (void);
__WEAK void software_init_hook (void) {
(void)osKernelInitialize();
}
#elif defined(__ICCARM__)
extern void $Super$$__iar_data_init3 (void);
void $Sub$$__iar_data_init3 (void) {
$Super$$__iar_data_init3();
(void)osKernelInitialize();
}
#endif
// OS Hooks
// ========
// RTOS Kernel Pre-Initialization Hook
#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0))
void osRtxKernelBeforeInit (void);
void osRtxKernelBeforeInit (void) {
if (osKernelGetState() == osKernelInactive) {
evr_initialize();
}
}
#endif
// C/C++ Standard Library Floating-point Initialization
// ====================================================
#if ( !defined(RTX_NO_FP_INIT_CLIB) && \
( defined(__CC_ARM) || \
(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
!defined(__MICROLIB))
#if (!defined(__ARM_ARCH_7A__) && \
(defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED ) && (__FPU_USED == 1U)))
extern void $Super$$_fp_init (void);
void $Sub$$_fp_init (void);
void $Sub$$_fp_init (void) {
$Super$$_fp_init();
FPU->FPDSCR = __get_FPSCR();
}
#endif
#endif
// C/C++ Standard Library Multithreading Interface
// ===============================================
#if ( !defined(RTX_NO_MULTITHREAD_CLIB) && \
( defined(__CC_ARM) || \
(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
!defined(__MICROLIB))
#define LIBSPACE_SIZE 96
//lint -esym(714,__user_perthread_libspace,_mutex_*) "Referenced by C library"
//lint -esym(765,__user_perthread_libspace,_mutex_*) "Global scope"
//lint -esym(9003, os_libspace*) "variables 'os_libspace*' defined at module scope"
// Memory for libspace
static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/4] \
__attribute__((section(".bss.os.libspace")));
// Thread IDs for libspace
static osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \
__attribute__((section(".bss.os.libspace")));
// Check if Kernel has been started
static uint32_t os_kernel_is_active (void) {
static uint8_t os_kernel_active = 0U;
if (os_kernel_active == 0U) {
if (osKernelGetState() > osKernelReady) {
os_kernel_active = 1U;
}
}
return (uint32_t)os_kernel_active;
}
// Provide libspace for current thread
void *__user_perthread_libspace (void);
void *__user_perthread_libspace (void) {
osThreadId_t id;
uint32_t n;
if (os_kernel_is_active() != 0U) {
id = osThreadGetId();
for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) {
if (os_libspace_id[n] == NULL) {
os_libspace_id[n] = id;
}
if (os_libspace_id[n] == id) {
break;
}
}
if (n == (uint32_t)OS_THREAD_LIBSPACE_NUM) {
(void)osRtxKernelErrorNotify(osRtxErrorClibSpace, id);
}
} else {
n = OS_THREAD_LIBSPACE_NUM;
}
//lint -e{9087} "cast between pointers to different object types"
return (void *)&os_libspace[n][0];
}
// Free libspace for specified thread
static void user_perthread_libspace_free (osThreadId_t id) {
uint32_t n;
for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) {
if (os_libspace_id[n] == id) {
os_libspace_id[n] = NULL;
break;
}
}
}
/// RTOS Thread Before Free Hook
void osRtxThreadBeforeFree (osThreadId_t id);
void osRtxThreadBeforeFree (osThreadId_t id) {
user_perthread_libspace_free(id);
}
// Mutex identifier
typedef void *mutex;
//lint -save "Function prototypes defined in C library"
//lint -e970 "Use of 'int' outside of a typedef"
//lint -e818 "Pointer 'm' could be declared as pointing to const"
// Initialize mutex
__USED
int _mutex_initialize(mutex *m);
int _mutex_initialize(mutex *m) {
int result;
*m = osMutexNew(NULL);
if (*m != NULL) {
result = 1;
} else {
result = 0;
(void)osRtxKernelErrorNotify(osRtxErrorClibMutex, m);
}
return result;
}
// Acquire mutex
__USED
void _mutex_acquire(mutex *m);
void _mutex_acquire(mutex *m) {
if (os_kernel_is_active() != 0U) {
(void)osMutexAcquire(*m, osWaitForever);
}
}
// Release mutex
__USED
void _mutex_release(mutex *m);
void _mutex_release(mutex *m) {
if (os_kernel_is_active() != 0U) {
(void)osMutexRelease(*m);
}
}
// Free mutex
__USED
void _mutex_free(mutex *m);
void _mutex_free(mutex *m) {
(void)osMutexDelete(*m);
}
//lint -restore
#endif
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_lib.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 7,543 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Message Queue functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxMessageQueueMemUsage \
__attribute__((section(".data.os.msgqueue.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Put a Message into Queue sorted by Priority (Highest at Head).
/// \param[in] mq message queue object.
/// \param[in] msg message object.
static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
os_message_t *prev, *next;
if (mq->msg_last != NULL) {
prev = mq->msg_last;
next = NULL;
while ((prev != NULL) && (prev->priority < msg->priority)) {
next = prev;
prev = prev->prev;
}
msg->prev = prev;
msg->next = next;
if (prev != NULL) {
prev->next = msg;
} else {
mq->msg_first = msg;
}
if (next != NULL) {
next->prev = msg;
} else {
mq->msg_last = msg;
}
} else {
msg->prev = NULL;
msg->next = NULL;
mq->msg_first= msg;
mq->msg_last = msg;
}
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
mq->msg_count++;
if (primask == 0U) {
__enable_irq();
}
#else
(void)atomic_inc32(&mq->msg_count);
#endif
}
/// Get a Message from Queue with Highest Priority.
/// \param[in] mq message queue object.
/// \return message object or NULL.
static os_message_t *MessageQueueGet (os_message_queue_t *mq) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
os_message_t *msg;
uint32_t count;
uint8_t flags;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
count = mq->msg_count;
if (count != 0U) {
mq->msg_count--;
}
if (primask == 0U) {
__enable_irq();
}
#else
count = atomic_dec32_nz(&mq->msg_count);
#endif
if (count != 0U) {
msg = mq->msg_first;
while (msg != NULL) {
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
flags = msg->flags;
msg->flags = 1U;
if (primask == 0U) {
__enable_irq();
}
#else
flags = atomic_wr8(&msg->flags, 1U);
#endif
if (flags == 0U) {
break;
}
msg = msg->next;
}
} else {
msg = NULL;
}
return msg;
}
/// Remove a Message from Queue
/// \param[in] mq message queue object.
/// \param[in] msg message object.
static void MessageQueueRemove (os_message_queue_t *mq, const os_message_t *msg) {
if (msg->prev != NULL) {
msg->prev->next = msg->next;
} else {
mq->msg_first = msg->next;
}
if (msg->next != NULL) {
msg->next->prev = msg->prev;
} else {
mq->msg_last = msg->prev;
}
}
/// Verify that Message Queue object pointer is valid.
/// \param[in] mq message queue object.
/// \return true - valid, false - invalid.
static bool_t IsMessageQueuePtrValid (const os_message_queue_t *mq) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_msgqueue_cb_start__;
uint32_t cb_length = (uint32_t)&__os_msgqueue_cb_length__;
// Check the section boundaries
if (((uint32_t)mq - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)mq - cb_start) % sizeof(os_message_queue_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (mq == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Destroy a Message Queue object.
/// \param[in] mq message queue object.
static void osRtxMessageQueueDestroy (os_message_queue_t *mq) {
// Mark object as invalid
mq->id = osRtxIdInvalid;
// Free data memory
if ((mq->flags & osRtxFlagSystemMemory) != 0U) {
(void)osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base);
}
// Free object memory
if ((mq->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
#else
if (osRtxInfo.mpi.message_queue != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, mq);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxMessageQueueMemUsage.cnt_free++;
#endif
}
EvrRtxMessageQueueDestroyed(mq);
}
#ifdef RTX_SAFETY_CLASS
/// Delete a Message Queue safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxMessageQueueDeleteClass (uint32_t safety_class, uint32_t mode) {
os_message_queue_t *mq;
os_thread_t *thread;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
mq = (os_message_queue_t *)(uint32_t)&__os_msgqueue_cb_start__;
length = (uint32_t)&__os_msgqueue_cb_length__;
while (length >= sizeof(os_message_queue_t)) {
if ( (mq->id == osRtxIdMessageQueue) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((mq->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((mq->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
while (mq->thread_list != NULL) {
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
}
osRtxMessageQueueDestroy(mq);
}
length -= sizeof(os_message_queue_t);
mq++;
}
}
#endif
// ==== Post ISR processing ====
/// Message Queue post ISR processing.
/// \param[in] msg message object.
static void osRtxMessageQueuePostProcess (os_message_t *msg) {
//lint --e{954} "Pointer variable 'reg' is not pointing to const"
os_message_queue_t *mq;
os_message_t *msg0;
os_thread_t *thread;
uint32_t *reg;
const void *ptr_src;
void *ptr_dst;
if (msg->flags != 0U) {
// Remove Message
//lint -e{9079} -e{9087} "cast between pointers to different object types"
mq = *((os_message_queue_t **)(void *)&msg[1]);
MessageQueueRemove(mq, msg);
// Free memory
msg->id = osRtxIdInvalid;
(void)osRtxMemoryPoolFree(&mq->mp_info, msg);
// Check if Thread is waiting to send a Message
if (mq->thread_list != NULL) {
// Try to allocate memory
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
msg0 = osRtxMemoryPoolAlloc(&mq->mp_info);
if (msg0 != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
// Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)
reg = osRtxThreadRegPtr(thread);
//lint -e{923} "cast from unsigned int to pointer"
ptr_src = (const void *)reg[1];
(void)memcpy(&msg0[1], ptr_src, mq->msg_size);
// Store Message into Queue
msg0->id = osRtxIdMessage;
msg0->flags = 0U;
msg0->priority = (uint8_t)reg[2];
MessageQueuePut(mq, msg0);
EvrRtxMessageQueueInserted(mq, ptr_src);
}
}
} else {
// New Message
//lint -e{9079} -e{9087} "cast between pointers to different object types"
mq = (void *)msg->next;
//lint -e{9087} "cast between pointers to different object types"
ptr_src = (const void *)msg->prev;
// Check if Thread is waiting to receive a Message
if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {
EvrRtxMessageQueueInserted(mq, ptr_src);
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
// Copy Message (R1: void *msg_ptr, R2: uint8_t *msg_prio)
reg = osRtxThreadRegPtr(thread);
//lint -e{923} "cast from unsigned int to pointer"
ptr_dst = (void *)reg[1];
(void)memcpy(ptr_dst, &msg[1], mq->msg_size);
if (reg[2] != 0U) {
//lint -e{923} -e{9078} "cast from unsigned int to pointer"
*((uint8_t *)reg[2]) = msg->priority;
}
EvrRtxMessageQueueRetrieved(mq, ptr_dst);
// Free memory
msg->id = osRtxIdInvalid;
(void)osRtxMemoryPoolFree(&mq->mp_info, msg);
} else {
EvrRtxMessageQueueInserted(mq, ptr_src);
MessageQueuePut(mq, msg);
}
}
}
// ==== Service Calls ====
/// Create and Initialize a Message Queue object.
/// \note API identical to osMessageQueueNew
static osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
os_message_queue_t *mq;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
uint32_t attr_bits;
#endif
void *mq_mem;
uint32_t mq_size;
uint32_t block_size;
uint32_t size;
uint8_t flags;
const char *name;
// Check parameters
if ((msg_count == 0U) || (msg_size == 0U) ||
((__CLZ(msg_count) + __CLZ(msg_size)) < 32U)) {
EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
block_size = ((msg_size + 3U) & ~3UL) + sizeof(os_message_t);
size = msg_count * block_size;
// Process attributes
if (attr != NULL) {
name = attr->name;
#ifdef RTX_SAFETY_CLASS
attr_bits = attr->attr_bits;
#endif
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
mq = attr->cb_mem;
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
mq_mem = attr->mq_mem;
mq_size = attr->mq_size;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxMessageQueueError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (mq != NULL) {
if (!IsMessageQueuePtrValid(mq) || (attr->cb_size != sizeof(os_message_queue_t))) {
EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
if (mq_mem != NULL) {
//lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7]
if ((((uint32_t)mq_mem & 3U) != 0U) || (mq_size < size)) {
EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (mq_size != 0U) {
EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
#ifdef RTX_SAFETY_CLASS
attr_bits = 0U;
#endif
mq = NULL;
mq_mem = NULL;
}
// Allocate object memory if not provided
if (mq == NULL) {
if (osRtxInfo.mpi.message_queue != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mq = osRtxMemoryPoolAlloc(osRtxInfo.mpi.message_queue);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mq = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_message_queue_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (mq != NULL) {
uint32_t used;
osRtxMessageQueueMemUsage.cnt_alloc++;
used = osRtxMessageQueueMemUsage.cnt_alloc - osRtxMessageQueueMemUsage.cnt_free;
if (osRtxMessageQueueMemUsage.max_used < used) {
osRtxMessageQueueMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
// Allocate data memory if not provided
if ((mq != NULL) && (mq_mem == NULL)) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
mq_mem = osRtxMemoryAlloc(osRtxInfo.mem.mq_data, size, 0U);
if (mq_mem == NULL) {
if ((flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
#else
if (osRtxInfo.mpi.message_queue != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, mq);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxMessageQueueMemUsage.cnt_free++;
#endif
}
mq = NULL;
} else {
(void)memset(mq_mem, 0, size);
}
flags |= osRtxFlagSystemMemory;
}
if (mq != NULL) {
// Initialize control block
mq->id = osRtxIdMessageQueue;
mq->flags = flags;
mq->attr = 0U;
mq->name = name;
mq->thread_list = NULL;
mq->msg_size = msg_size;
mq->msg_count = 0U;
mq->msg_first = NULL;
mq->msg_last = NULL;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
mq->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
mq->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
(void)osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem);
// Register post ISR processing function
osRtxInfo.post_process.message = osRtxMessageQueuePostProcess;
EvrRtxMessageQueueCreated(mq, mq->name);
} else {
EvrRtxMessageQueueError(NULL, (int32_t)osErrorNoMemory);
}
return mq;
}
/// Get name of a Message Queue object.
/// \note API identical to osMessageQueueGetName
static const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueGetName(mq, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxMessageQueueGetName(mq, mq->name);
return mq->name;
}
/// Put a Message into a Queue or timeout if Queue is full.
/// \note API identical to osMessageQueuePut
static osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
//lint --e{954} "Pointer variable 'reg' is not pointing to const"
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_message_t *msg;
os_thread_t *thread;
uint32_t *reg;
void *ptr;
osStatus_t status;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check if Thread is waiting to receive a Message
if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {
EvrRtxMessageQueueInserted(mq, msg_ptr);
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);
// Copy Message (R1: void *msg_ptr, R2: uint8_t *msg_prio)
reg = osRtxThreadRegPtr(thread);
//lint -e{923} "cast from unsigned int to pointer"
ptr = (void *)reg[1];
(void)memcpy(ptr, msg_ptr, mq->msg_size);
if (reg[2] != 0U) {
//lint -e{923} -e{9078} "cast from unsigned int to pointer"
*((uint8_t *)reg[2]) = msg_prio;
}
EvrRtxMessageQueueRetrieved(mq, ptr);
status = osOK;
} else {
// Try to allocate memory
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
msg = osRtxMemoryPoolAlloc(&mq->mp_info);
if (msg != NULL) {
// Copy Message
(void)memcpy(&msg[1], msg_ptr, mq->msg_size);
// Put Message into Queue
msg->id = osRtxIdMessage;
msg->flags = 0U;
msg->priority = msg_prio;
MessageQueuePut(mq, msg);
EvrRtxMessageQueueInserted(mq, msg_ptr);
status = osOK;
} else {
// No memory available
if (timeout != 0U) {
EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout)) {
osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning());
} else {
EvrRtxMessageQueuePutTimeout(mq);
}
status = osErrorTimeout;
} else {
EvrRtxMessageQueueNotInserted(mq, msg_ptr);
status = osErrorResource;
}
}
}
return status;
}
/// Get a Message from a Queue or timeout if Queue is empty.
/// \note API identical to osMessageQueueGet
static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_message_t *msg;
os_thread_t *thread;
const uint32_t *reg;
const void *ptr;
osStatus_t status;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Get Message from Queue
msg = MessageQueueGet(mq);
if (msg != NULL) {
MessageQueueRemove(mq, msg);
// Copy Message
(void)memcpy(msg_ptr, &msg[1], mq->msg_size);
if (msg_prio != NULL) {
*msg_prio = msg->priority;
}
EvrRtxMessageQueueRetrieved(mq, msg_ptr);
// Free memory
msg->id = osRtxIdInvalid;
(void)osRtxMemoryPoolFree(&mq->mp_info, msg);
// Check if Thread is waiting to send a Message
if (mq->thread_list != NULL) {
// Try to allocate memory
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
msg = osRtxMemoryPoolAlloc(&mq->mp_info);
if (msg != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);
// Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)
reg = osRtxThreadRegPtr(thread);
//lint -e{923} "cast from unsigned int to pointer"
ptr = (const void *)reg[1];
(void)memcpy(&msg[1], ptr, mq->msg_size);
// Store Message into Queue
msg->id = osRtxIdMessage;
msg->flags = 0U;
msg->priority = (uint8_t)reg[2];
MessageQueuePut(mq, msg);
EvrRtxMessageQueueInserted(mq, ptr);
}
}
status = osOK;
} else {
// No Message available
if (timeout != 0U) {
EvrRtxMessageQueueGetPending(mq, msg_ptr, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout)) {
osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning());
} else {
EvrRtxMessageQueueGetTimeout(mq);
}
status = osErrorTimeout;
} else {
EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);
status = osErrorResource;
}
}
return status;
}
/// Get maximum number of messages in a Message Queue.
/// \note API identical to osMessageQueueGetCapacity
static uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueGetCapacity(mq, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMessageQueueGetCapacity(mq, mq->mp_info.max_blocks);
return mq->mp_info.max_blocks;
}
/// Get maximum message size in a Memory Pool.
/// \note API identical to osMessageQueueGetMsgSize
static uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueGetMsgSize(mq, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMessageQueueGetMsgSize(mq, mq->msg_size);
return mq->msg_size;
}
/// Get number of queued messages in a Message Queue.
/// \note API identical to osMessageQueueGetCount
static uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueGetCount(mq, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMessageQueueGetCount(mq, mq->msg_count);
return mq->msg_count;
}
/// Get number of available slots for messages in a Message Queue.
/// \note API identical to osMessageQueueGetSpace
static uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueGetSpace(mq, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxMessageQueueGetSpace(mq, mq->mp_info.max_blocks - mq->msg_count);
return (mq->mp_info.max_blocks - mq->msg_count);
}
/// Reset a Message Queue to initial empty state.
/// \note API identical to osMessageQueueReset
static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_message_t *msg;
os_thread_t *thread;
const uint32_t *reg;
const void *ptr;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Remove Messages from Queue
for (;;) {
// Get Message from Queue
msg = MessageQueueGet(mq);
if (msg == NULL) {
break;
}
MessageQueueRemove(mq, msg);
EvrRtxMessageQueueRetrieved(mq, NULL);
// Free memory
msg->id = osRtxIdInvalid;
(void)osRtxMemoryPoolFree(&mq->mp_info, msg);
}
// Check if Threads are waiting to send Messages
if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) {
do {
// Try to allocate memory
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
msg = osRtxMemoryPoolAlloc(&mq->mp_info);
if (msg != NULL) {
// Wakeup waiting Thread with highest Priority
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);
// Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)
reg = osRtxThreadRegPtr(thread);
//lint -e{923} "cast from unsigned int to pointer"
ptr = (const void *)reg[1];
(void)memcpy(&msg[1], ptr, mq->msg_size);
// Store Message into Queue
msg->id = osRtxIdMessage;
msg->flags = 0U;
msg->priority = (uint8_t)reg[2];
MessageQueuePut(mq, msg);
EvrRtxMessageQueueInserted(mq, ptr);
}
} while ((msg != NULL) && (mq->thread_list != NULL));
osRtxThreadDispatch(NULL);
}
EvrRtxMessageQueueResetDone(mq);
return osOK;
}
/// Delete a Message Queue object.
/// \note API identical to osMessageQueueDelete
static osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_thread_t *thread;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Unblock waiting threads
if (mq->thread_list != NULL) {
do {
thread = osRtxThreadListGet(osRtxObject(mq));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
} while (mq->thread_list != NULL);
osRtxThreadDispatch(NULL);
}
osRtxMessageQueueDestroy(mq);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_3(MessageQueueNew, osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *)
SVC0_1(MessageQueueGetName, const char *, osMessageQueueId_t)
SVC0_4(MessageQueuePut, osStatus_t, osMessageQueueId_t, const void *, uint8_t, uint32_t)
SVC0_4(MessageQueueGet, osStatus_t, osMessageQueueId_t, void *, uint8_t *, uint32_t)
SVC0_1(MessageQueueGetCapacity, uint32_t, osMessageQueueId_t)
SVC0_1(MessageQueueGetMsgSize, uint32_t, osMessageQueueId_t)
SVC0_1(MessageQueueGetCount, uint32_t, osMessageQueueId_t)
SVC0_1(MessageQueueGetSpace, uint32_t, osMessageQueueId_t)
SVC0_1(MessageQueueReset, osStatus_t, osMessageQueueId_t)
SVC0_1(MessageQueueDelete, osStatus_t, osMessageQueueId_t)
//lint --flb "Library End"
// ==== ISR Calls ====
/// Put a Message into a Queue or timeout if Queue is full.
/// \note API identical to osMessageQueuePut
__STATIC_INLINE
osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_message_t *msg;
osStatus_t status;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Try to allocate memory
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
msg = osRtxMemoryPoolAlloc(&mq->mp_info);
if (msg != NULL) {
// Copy Message
(void)memcpy(&msg[1], msg_ptr, mq->msg_size);
msg->id = osRtxIdMessage;
msg->flags = 0U;
msg->priority = msg_prio;
// Register post ISR processing
//lint -e{9079} -e{9087} "cast between pointers to different object types"
*((const void **)(void *)&msg->prev) = msg_ptr;
//lint -e{9079} -e{9087} "cast between pointers to different object types"
*( (void **) &msg->next) = mq;
osRtxPostProcess(osRtxObject(msg));
EvrRtxMessageQueueInsertPending(mq, msg_ptr);
status = osOK;
} else {
// No memory available
EvrRtxMessageQueueNotInserted(mq, msg_ptr);
status = osErrorResource;
}
return status;
}
/// Get a Message from a Queue or timeout if Queue is empty.
/// \note API identical to osMessageQueueGet
__STATIC_INLINE
osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
os_message_queue_t *mq = osRtxMessageQueueId(mq_id);
os_message_t *msg;
osStatus_t status;
// Check parameters
if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {
EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Get Message from Queue
msg = MessageQueueGet(mq);
if (msg != NULL) {
// Copy Message
memcpy(msg_ptr, &msg[1], mq->msg_size);
if (msg_prio != NULL) {
*msg_prio = msg->priority;
}
// Register post ISR processing
//lint -e{9079} -e{9087} "cast between pointers to different object types"
*((os_message_queue_t **)(void *)&msg[1]) = mq;
osRtxPostProcess(osRtxObject(msg));
EvrRtxMessageQueueRetrieved(mq, msg_ptr);
status = osOK;
} else {
// No Message available
EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);
status = osErrorResource;
}
return status;
}
// ==== Library functions ====
/// Create a Message Queue for the Timer Thread.
int32_t osRtxMessageQueueTimerSetup (void) {
int32_t ret = -1;
osRtxInfo.timer.mq = osRtxMessageQueueId(
svcRtxMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr)
);
if (osRtxInfo.timer.mq != NULL) {
ret = 0;
}
return ret;
}
// ==== Public API ====
/// Create and Initialize a Message Queue object.
osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
osMessageQueueId_t mq_id;
EvrRtxMessageQueueNew(msg_count, msg_size, attr);
if (IsException() || IsIrqMasked()) {
EvrRtxMessageQueueError(NULL, (int32_t)osErrorISR);
mq_id = NULL;
} else {
mq_id = __svcMessageQueueNew(msg_count, msg_size, attr);
}
return mq_id;
}
/// Get name of a Message Queue object.
const char *osMessageQueueGetName (osMessageQueueId_t mq_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxMessageQueueGetName(mq_id);
} else {
name = __svcMessageQueueGetName(mq_id);
}
return name;
}
/// Put a Message into a Queue or timeout if Queue is full.
osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
osStatus_t status;
EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
if (IsException() || IsIrqMasked()) {
status = isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
} else {
status = __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
}
return status;
}
/// Get a Message from a Queue or timeout if Queue is empty.
osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
osStatus_t status;
EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
if (IsException() || IsIrqMasked()) {
status = isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
} else {
status = __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
}
return status;
}
/// Get maximum number of messages in a Message Queue.
uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
uint32_t capacity;
if (IsException() || IsIrqMasked()) {
capacity = svcRtxMessageQueueGetCapacity(mq_id);
} else {
capacity = __svcMessageQueueGetCapacity(mq_id);
}
return capacity;
}
/// Get maximum message size in a Memory Pool.
uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
uint32_t msg_size;
if (IsException() || IsIrqMasked()) {
msg_size = svcRtxMessageQueueGetMsgSize(mq_id);
} else {
msg_size = __svcMessageQueueGetMsgSize(mq_id);
}
return msg_size;
}
/// Get number of queued messages in a Message Queue.
uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
count = svcRtxMessageQueueGetCount(mq_id);
} else {
count = __svcMessageQueueGetCount(mq_id);
}
return count;
}
/// Get number of available slots for messages in a Message Queue.
uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
uint32_t space;
if (IsException() || IsIrqMasked()) {
space = svcRtxMessageQueueGetSpace(mq_id);
} else {
space = __svcMessageQueueGetSpace(mq_id);
}
return space;
}
/// Reset a Message Queue to initial empty state.
osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
osStatus_t status;
EvrRtxMessageQueueReset(mq_id);
if (IsException() || IsIrqMasked()) {
EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMessageQueueReset(mq_id);
}
return status;
}
/// Delete a Message Queue object.
osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {
osStatus_t status;
EvrRtxMessageQueueDelete(mq_id);
if (IsException() || IsIrqMasked()) {
EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcMessageQueueDelete(mq_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 10,421 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Kernel functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Information
osRtxInfo_t osRtxInfo __attribute__((section(".data.os"))) =
//lint -e{785} "Initialize only OS ID, OS Version and Kernel State"
{ .os_id = osRtxKernelId, .version = osRtxVersionKernel, .kernel.state = osRtxKernelInactive };
// ==== Helper functions ====
/// Block Kernel (disable: thread switching, time tick, post ISR processing).
static void KernelBlock (void) {
OS_Tick_Disable();
osRtxInfo.kernel.blocked = 1U;
__DSB();
if (GetPendSV() != 0U) {
ClrPendSV();
osRtxInfo.kernel.pendSV = 1U;
}
}
/// Unblock Kernel
static void KernelUnblock (void) {
osRtxInfo.kernel.blocked = 0U;
__DSB();
if (osRtxInfo.kernel.pendSV != 0U) {
osRtxInfo.kernel.pendSV = 0U;
SetPendSV();
}
OS_Tick_Enable();
}
// Get Kernel sleep time
static uint32_t GetKernelSleepTime (void) {
const os_thread_t *thread;
const os_timer_t *timer;
uint32_t delay;
delay = osWaitForever;
// Check Thread Delay list
thread = osRtxInfo.thread.delay_list;
if (thread != NULL) {
delay = thread->delay;
}
#ifdef RTX_THREAD_WATCHDOG
// Check Thread Watchdog list
thread = osRtxInfo.thread.wdog_list;
if (thread != NULL) {
if (thread->wdog_tick < delay) {
delay = thread->wdog_tick;
}
}
#endif
// Check Active Timer list
timer = osRtxInfo.timer.list;
if (timer != NULL) {
if (timer->tick < delay) {
delay = timer->tick;
}
}
return delay;
}
// ==== Service Calls ====
/// Initialize the RTOS Kernel.
/// \note API identical to osKernelInitialize
static osStatus_t svcRtxKernelInitialize (void) {
if (osRtxInfo.kernel.state == osRtxKernelReady) {
EvrRtxKernelInitialized();
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osOK;
}
if (osRtxInfo.kernel.state != osRtxKernelInactive) {
EvrRtxKernelError((int32_t)osError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
#ifdef RTX_TZ_CONTEXT
// Initialize Secure Process Stack
if (TZ_InitContextSystem_S() == 0U) {
EvrRtxKernelError(osRtxErrorTZ_InitContext_S);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
#endif
// Initialize osRtxInfo
(void)memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel));
osRtxInfo.isr_queue.data = osRtxConfig.isr_queue.data;
osRtxInfo.isr_queue.max = osRtxConfig.isr_queue.max;
osRtxInfo.thread.robin.timeout = osRtxConfig.robin_timeout;
// Initialize Memory Pools (Variable Block Size)
if (osRtxMemoryInit(osRtxConfig.mem.common_addr, osRtxConfig.mem.common_size) != 0U) {
osRtxInfo.mem.common = osRtxConfig.mem.common_addr;
}
if (osRtxMemoryInit(osRtxConfig.mem.stack_addr, osRtxConfig.mem.stack_size) != 0U) {
osRtxInfo.mem.stack = osRtxConfig.mem.stack_addr;
} else {
osRtxInfo.mem.stack = osRtxInfo.mem.common;
}
if (osRtxMemoryInit(osRtxConfig.mem.mp_data_addr, osRtxConfig.mem.mp_data_size) != 0U) {
osRtxInfo.mem.mp_data = osRtxConfig.mem.mp_data_addr;
} else {
osRtxInfo.mem.mp_data = osRtxInfo.mem.common;
}
if (osRtxMemoryInit(osRtxConfig.mem.mq_data_addr, osRtxConfig.mem.mq_data_size) != 0U) {
osRtxInfo.mem.mq_data = osRtxConfig.mem.mq_data_addr;
} else {
osRtxInfo.mem.mq_data = osRtxInfo.mem.common;
}
// Initialize Memory Pools (Fixed Block Size)
if (osRtxConfig.mpi.stack != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.stack,
osRtxConfig.mpi.stack->max_blocks,
osRtxConfig.mpi.stack->block_size,
osRtxConfig.mpi.stack->block_base);
osRtxInfo.mpi.stack = osRtxConfig.mpi.stack;
}
if (osRtxConfig.mpi.thread != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.thread,
osRtxConfig.mpi.thread->max_blocks,
osRtxConfig.mpi.thread->block_size,
osRtxConfig.mpi.thread->block_base);
osRtxInfo.mpi.thread = osRtxConfig.mpi.thread;
}
if (osRtxConfig.mpi.timer != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.timer,
osRtxConfig.mpi.timer->max_blocks,
osRtxConfig.mpi.timer->block_size,
osRtxConfig.mpi.timer->block_base);
osRtxInfo.mpi.timer = osRtxConfig.mpi.timer;
}
if (osRtxConfig.mpi.event_flags != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags,
osRtxConfig.mpi.event_flags->max_blocks,
osRtxConfig.mpi.event_flags->block_size,
osRtxConfig.mpi.event_flags->block_base);
osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags;
}
if (osRtxConfig.mpi.mutex != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.mutex,
osRtxConfig.mpi.mutex->max_blocks,
osRtxConfig.mpi.mutex->block_size,
osRtxConfig.mpi.mutex->block_base);
osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex;
}
if (osRtxConfig.mpi.semaphore != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore,
osRtxConfig.mpi.semaphore->max_blocks,
osRtxConfig.mpi.semaphore->block_size,
osRtxConfig.mpi.semaphore->block_base);
osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore;
}
if (osRtxConfig.mpi.memory_pool != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool,
osRtxConfig.mpi.memory_pool->max_blocks,
osRtxConfig.mpi.memory_pool->block_size,
osRtxConfig.mpi.memory_pool->block_base);
osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool;
}
if (osRtxConfig.mpi.message_queue != NULL) {
(void)osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue,
osRtxConfig.mpi.message_queue->max_blocks,
osRtxConfig.mpi.message_queue->block_size,
osRtxConfig.mpi.message_queue->block_base);
osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue;
}
osRtxInfo.kernel.state = osRtxKernelReady;
EvrRtxKernelInitialized();
return osOK;
}
/// Get RTOS Kernel Information.
/// \note API identical to osKernelGetInfo
static osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
uint32_t size;
if (version != NULL) {
version->api = osRtxVersionAPI;
version->kernel = osRtxVersionKernel;
}
if ((id_buf != NULL) && (id_size != 0U)) {
if (id_size > sizeof(osRtxKernelId)) {
size = sizeof(osRtxKernelId);
} else {
size = id_size;
}
(void)memcpy(id_buf, osRtxKernelId, size);
}
EvrRtxKernelInfoRetrieved(version, id_buf, id_size);
return osOK;
}
/// Get the current RTOS Kernel state.
/// \note API identical to osKernelGetState
static osKernelState_t svcRtxKernelGetState (void) {
osKernelState_t state = osRtxKernelState();
EvrRtxKernelGetState(state);
return state;
}
/// Start the RTOS Kernel scheduler.
/// \note API identical to osKernelStart
static osStatus_t svcRtxKernelStart (void) {
os_thread_t *thread;
if (osRtxInfo.kernel.state != osRtxKernelReady) {
EvrRtxKernelError(osRtxErrorKernelNotReady);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
// Thread startup (Idle and Timer Thread)
if (!osRtxThreadStartup()) {
EvrRtxKernelError((int32_t)osError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
// Setup SVC and PendSV System Service Calls
SVC_Setup();
// Setup RTOS Tick
if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0) {
EvrRtxKernelError((int32_t)osError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
osRtxInfo.tick_irqn = OS_Tick_GetIRQn();
// Enable RTOS Tick
OS_Tick_Enable();
// Switch to Ready Thread with highest Priority
thread = osRtxThreadListGet(&osRtxInfo.thread.ready);
osRtxThreadSwitch(thread);
osRtxInfo.kernel.state = osRtxKernelRunning;
EvrRtxKernelStarted();
return osOK;
}
/// Lock the RTOS Kernel scheduler.
/// \note API identical to osKernelLock
static int32_t svcRtxKernelLock (void) {
int32_t lock;
switch (osRtxInfo.kernel.state) {
case osRtxKernelRunning:
#ifdef RTX_SAFETY_CLASS
// Check the safety class
if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <
(osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {
EvrRtxKernelError((int32_t)osErrorSafetyClass);
lock = (int32_t)osErrorSafetyClass;
break;
}
#endif
osRtxInfo.kernel.state = osRtxKernelLocked;
EvrRtxKernelLocked(0);
lock = 0;
break;
case osRtxKernelLocked:
EvrRtxKernelLocked(1);
lock = 1;
break;
default:
EvrRtxKernelError((int32_t)osError);
lock = (int32_t)osError;
break;
}
return lock;
}
/// Unlock the RTOS Kernel scheduler.
/// \note API identical to osKernelUnlock
static int32_t svcRtxKernelUnlock (void) {
int32_t lock;
switch (osRtxInfo.kernel.state) {
case osRtxKernelRunning:
EvrRtxKernelUnlocked(0);
lock = 0;
break;
case osRtxKernelLocked:
osRtxInfo.kernel.state = osRtxKernelRunning;
EvrRtxKernelUnlocked(1);
lock = 1;
break;
default:
EvrRtxKernelError((int32_t)osError);
lock = (int32_t)osError;
break;
}
return lock;
}
/// Restore the RTOS Kernel scheduler lock state.
/// \note API identical to osKernelRestoreLock
static int32_t svcRtxKernelRestoreLock (int32_t lock) {
int32_t lock_new;
switch (osRtxInfo.kernel.state) {
case osRtxKernelRunning:
case osRtxKernelLocked:
#ifdef RTX_SAFETY_CLASS
// Check the safety class
if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <
(osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {
EvrRtxKernelError((int32_t)osErrorSafetyClass);
lock_new = (int32_t)osErrorSafetyClass;
break;
}
#endif
switch (lock) {
case 0:
osRtxInfo.kernel.state = osRtxKernelRunning;
EvrRtxKernelLockRestored(0);
lock_new = 0;
break;
case 1:
osRtxInfo.kernel.state = osRtxKernelLocked;
EvrRtxKernelLockRestored(1);
lock_new = 1;
break;
default:
EvrRtxKernelError((int32_t)osError);
lock_new = (int32_t)osError;
break;
}
break;
default:
EvrRtxKernelError((int32_t)osError);
lock_new = (int32_t)osError;
break;
}
return lock_new;
}
/// Suspend the RTOS Kernel scheduler.
/// \note API identical to osKernelSuspend
static uint32_t svcRtxKernelSuspend (void) {
uint32_t delay;
if (osRtxInfo.kernel.state != osRtxKernelRunning) {
EvrRtxKernelError(osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
#ifdef RTX_SAFETY_CLASS
// Check the safety class
if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <
(osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {
EvrRtxKernelError((int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
#endif
KernelBlock();
osRtxInfo.kernel.state = osRtxKernelSuspended;
delay = GetKernelSleepTime();
EvrRtxKernelSuspended(delay);
return delay;
}
/// Resume the RTOS Kernel scheduler.
/// \note API identical to osKernelResume
static void svcRtxKernelResume (uint32_t sleep_ticks) {
os_thread_t *thread;
os_timer_t *timer;
uint32_t delay;
uint32_t ticks, kernel_tick;
if (osRtxInfo.kernel.state != osRtxKernelSuspended) {
EvrRtxKernelResumed();
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
delay = GetKernelSleepTime();
if (sleep_ticks >= delay) {
ticks = delay - 1U;
} else {
ticks = sleep_ticks;
}
// Update Thread Delay sleep ticks
thread = osRtxInfo.thread.delay_list;
if (thread != NULL) {
thread->delay -= ticks;
}
// Update Timer sleep ticks
timer = osRtxInfo.timer.list;
if (timer != NULL) {
timer->tick -= ticks;
}
#ifdef RTX_THREAD_WATCHDOG
// Update Thread Watchdog sleep ticks
thread = osRtxInfo.thread.wdog_list;
if (thread != NULL) {
thread->wdog_tick -= ticks;
}
#endif
kernel_tick = osRtxInfo.kernel.tick + sleep_ticks;
osRtxInfo.kernel.tick += ticks;
while (osRtxInfo.kernel.tick != kernel_tick) {
osRtxInfo.kernel.tick++;
// Process Thread Delays
osRtxThreadDelayTick();
// Process Timers
if (osRtxInfo.timer.tick != NULL) {
osRtxInfo.timer.tick();
}
#ifdef RTX_THREAD_WATCHDOG
// Process Watchdog Timers
osRtxThreadWatchdogTick();
#endif
}
osRtxInfo.kernel.state = osRtxKernelRunning;
osRtxThreadDispatch(NULL);
KernelUnblock();
EvrRtxKernelResumed();
}
#ifdef RTX_SAFETY_CLASS
/// Protect the RTOS Kernel scheduler access.
/// \note API identical to osKernelProtect
static osStatus_t svcRtxKernelProtect (uint32_t safety_class) {
uint32_t thread_class;
osStatus_t status;
// Check parameters
if (safety_class > 0x0FU) {
EvrRtxKernelError((int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
switch (osRtxInfo.kernel.state) {
case osRtxKernelInactive:
EvrRtxKernelError(osRtxErrorKernelNotReady);
status = osError;
break;
case osRtxKernelReady:
osRtxInfo.kernel.protect &= (uint8_t)~osRtxKernelProtectClass_Msk;
osRtxInfo.kernel.protect |= (uint8_t)(safety_class << osRtxKernelProtectClass_Pos);
EvrRtxKernelProtected();
status = osOK;
break;
case osRtxKernelRunning:
// Check the safety class
thread_class = (uint32_t)osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos;
if ((safety_class > thread_class) ||
(thread_class < ((uint32_t)osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos))) {
EvrRtxKernelError((int32_t)osErrorSafetyClass);
status = osErrorSafetyClass;
break;
}
osRtxInfo.kernel.protect &= (uint8_t)~osRtxKernelProtectClass_Msk;
osRtxInfo.kernel.protect |= (uint8_t)(safety_class << osRtxKernelProtectClass_Pos);
EvrRtxKernelProtected();
status = osOK;
break;
case osRtxKernelLocked:
case osRtxKernelSuspended:
EvrRtxKernelError(osRtxErrorKernelNotRunning);
status = osError;
break;
default:
// Should never come here
status = osError;
break;
}
return status;
}
/// Destroy objects for specified safety classes.
/// \note API identical to osKernelDestroyClass
static osStatus_t svcRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode) {
os_thread_t *thread;
os_thread_t *thread_next;
// Check parameters
if (safety_class > 0x0FU) {
EvrRtxKernelError((int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Check running thread safety class (when called from thread)
thread = osRtxThreadGetRunning();
if ((thread != NULL) && IsSVCallIrq()) {
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
(((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {
EvrRtxKernelError((int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
}
// Delete RTOS objects for safety class
osRtxMutexDeleteClass(safety_class, mode);
osRtxSemaphoreDeleteClass(safety_class, mode);
osRtxMemoryPoolDeleteClass(safety_class, mode);
osRtxMessageQueueDeleteClass(safety_class, mode);
osRtxEventFlagsDeleteClass(safety_class, mode);
osRtxTimerDeleteClass(safety_class, mode);
// Threads in Wait List
thread = osRtxInfo.thread.wait_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Threads in Delay List
thread = osRtxInfo.thread.delay_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Threads in Ready List
thread = osRtxInfo.thread.ready.thread_list;
while (thread != NULL) {
thread_next = thread->thread_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Running Thread
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
if ((osRtxKernelGetState() != osRtxKernelRunning) ||
(osRtxInfo.thread.ready.thread_list == NULL)) {
osRtxThreadDispatch(NULL);
EvrRtxKernelError((int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
// Switch to next Ready Thread
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
// Update Stack Pointer
thread->sp = __get_PSP();
#ifdef RTX_STACK_CHECK
// Check Stack usage
if (!osRtxThreadStackCheck(thread)) {
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
(void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);
}
#endif
// Mark running thread as deleted
osRtxThreadSetRunning(NULL);
// Destroy Thread
osRtxThreadDestroy(thread);
} else {
osRtxThreadDispatch(NULL);
}
return osOK;
}
#endif
/// Get the RTOS kernel tick count.
/// \note API identical to osKernelGetTickCount
static uint32_t svcRtxKernelGetTickCount (void) {
EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick);
return osRtxInfo.kernel.tick;
}
/// Get the RTOS kernel tick frequency.
/// \note API identical to osKernelGetTickFreq
static uint32_t svcRtxKernelGetTickFreq (void) {
EvrRtxKernelGetTickFreq(osRtxConfig.tick_freq);
return osRtxConfig.tick_freq;
}
/// Get the RTOS kernel system timer count.
/// \note API identical to osKernelGetSysTimerCount
static uint32_t svcRtxKernelGetSysTimerCount (void) {
uint32_t tick;
uint32_t count;
tick = (uint32_t)osRtxInfo.kernel.tick;
count = OS_Tick_GetCount();
if (OS_Tick_GetOverflow() != 0U) {
count = OS_Tick_GetCount();
tick++;
}
count += tick * OS_Tick_GetInterval();
EvrRtxKernelGetSysTimerCount(count);
return count;
}
/// Get the RTOS kernel system timer frequency.
/// \note API identical to osKernelGetSysTimerFreq
static uint32_t svcRtxKernelGetSysTimerFreq (void) {
uint32_t freq = OS_Tick_GetClock();
EvrRtxKernelGetSysTimerFreq(freq);
return freq;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_0 (KernelInitialize, osStatus_t)
SVC0_3 (KernelGetInfo, osStatus_t, osVersion_t *, char *, uint32_t)
SVC0_0 (KernelStart, osStatus_t)
SVC0_0 (KernelLock, int32_t)
SVC0_0 (KernelUnlock, int32_t)
SVC0_1 (KernelRestoreLock, int32_t, int32_t)
SVC0_0 (KernelSuspend, uint32_t)
SVC0_1N(KernelResume, void, uint32_t)
#ifdef RTX_SAFETY_CLASS
SVC0_1 (KernelProtect, osStatus_t, uint32_t)
SVC0_2 (KernelDestroyClass, osStatus_t, uint32_t, uint32_t)
#endif
SVC0_0 (KernelGetState, osKernelState_t)
SVC0_0 (KernelGetTickCount, uint32_t)
SVC0_0 (KernelGetTickFreq, uint32_t)
SVC0_0 (KernelGetSysTimerCount, uint32_t)
SVC0_0 (KernelGetSysTimerFreq, uint32_t)
//lint --flb "Library End"
// ==== Library functions ====
/// RTOS Kernel Pre-Initialization Hook
//lint -esym(759,osRtxKernelBeforeInit) "Prototype in header"
//lint -esym(765,osRtxKernelBeforeInit) "Global scope (can be overridden)"
//lint -esym(522,osRtxKernelBeforeInit) "Can be overridden (do not lack side-effects)"
__WEAK void osRtxKernelBeforeInit (void) {
}
/// RTOS Kernel Error Notification Handler
/// \note API identical to osRtxErrorNotify
uint32_t osRtxKernelErrorNotify (uint32_t code, void *object_id) {
EvrRtxKernelErrorNotify(code, object_id);
return osRtxErrorNotify(code, object_id);
}
// ==== Public API ====
/// Initialize the RTOS Kernel.
osStatus_t osKernelInitialize (void) {
osStatus_t status;
osRtxKernelBeforeInit();
EvrRtxKernelInitialize();
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcKernelInitialize();
}
return status;
}
/// Get RTOS Kernel Information.
osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
osStatus_t status;
EvrRtxKernelGetInfo(version, id_buf, id_size);
if (IsException() || IsIrqMasked() || IsPrivileged()) {
status = svcRtxKernelGetInfo(version, id_buf, id_size);
} else {
status = __svcKernelGetInfo(version, id_buf, id_size);
}
return status;
}
/// Get the current RTOS Kernel state.
osKernelState_t osKernelGetState (void) {
osKernelState_t state;
if (IsException() || IsIrqMasked() || IsPrivileged()) {
state = svcRtxKernelGetState();
} else {
state = __svcKernelGetState();
}
return state;
}
/// Start the RTOS Kernel scheduler.
osStatus_t osKernelStart (void) {
osStatus_t status;
EvrRtxKernelStart();
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcKernelStart();
}
return status;
}
/// Lock the RTOS Kernel scheduler.
int32_t osKernelLock (void) {
int32_t lock;
EvrRtxKernelLock();
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
lock = (int32_t)osErrorISR;
} else {
lock = __svcKernelLock();
}
return lock;
}
/// Unlock the RTOS Kernel scheduler.
int32_t osKernelUnlock (void) {
int32_t lock;
EvrRtxKernelUnlock();
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
lock = (int32_t)osErrorISR;
} else {
lock = __svcKernelUnlock();
}
return lock;
}
/// Restore the RTOS Kernel scheduler lock state.
int32_t osKernelRestoreLock (int32_t lock) {
int32_t lock_new;
EvrRtxKernelRestoreLock(lock);
if (IsException() || IsIrqMasked()) {
if (IsFault() || IsSVCallIrq() || IsPendSvIrq() || IsTickIrq(osRtxInfo.tick_irqn)) {
lock_new = svcRtxKernelRestoreLock(lock);
} else {
EvrRtxKernelError((int32_t)osErrorISR);
lock_new = (int32_t)osErrorISR;
}
} else {
lock_new = __svcKernelRestoreLock(lock);
}
return lock_new;
}
/// Suspend the RTOS Kernel scheduler.
uint32_t osKernelSuspend (void) {
uint32_t ticks;
EvrRtxKernelSuspend();
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
ticks = 0U;
} else {
ticks = __svcKernelSuspend();
}
return ticks;
}
/// Resume the RTOS Kernel scheduler.
void osKernelResume (uint32_t sleep_ticks) {
EvrRtxKernelResume(sleep_ticks);
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
} else {
__svcKernelResume(sleep_ticks);
}
}
#ifdef RTX_SAFETY_CLASS
/// Protect the RTOS Kernel scheduler access.
osStatus_t osKernelProtect (uint32_t safety_class) {
osStatus_t status;
EvrRtxKernelProtect(safety_class);
if (IsException() || IsIrqMasked()) {
EvrRtxKernelError((int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcKernelProtect(safety_class);
}
return status;
}
/// Destroy RTOS objects for specified safety classes.
osStatus_t osKernelDestroyClass (uint32_t safety_class, uint32_t mode) {
osStatus_t status;
EvrRtxKernelDestroyClass(safety_class, mode);
if (IsException() || IsIrqMasked()) {
if (IsTickIrq(osRtxInfo.tick_irqn)) {
status = svcRtxKernelDestroyClass(safety_class, mode);
} else {
EvrRtxKernelError((int32_t)osErrorISR);
status = osErrorISR;
}
} else {
status = __svcKernelDestroyClass(safety_class, mode);
}
return status;
}
#endif
/// Get the RTOS kernel tick count.
uint32_t osKernelGetTickCount (void) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
count = svcRtxKernelGetTickCount();
} else {
count = __svcKernelGetTickCount();
}
return count;
}
/// Get the RTOS kernel tick frequency.
uint32_t osKernelGetTickFreq (void) {
uint32_t freq;
if (IsException() || IsIrqMasked()) {
freq = svcRtxKernelGetTickFreq();
} else {
freq = __svcKernelGetTickFreq();
}
return freq;
}
/// Get the RTOS kernel system timer count.
uint32_t osKernelGetSysTimerCount (void) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
count = svcRtxKernelGetSysTimerCount();
} else {
count = __svcKernelGetSysTimerCount();
}
return count;
}
/// Get the RTOS kernel system timer frequency.
uint32_t osKernelGetSysTimerFreq (void) {
uint32_t freq;
if (IsException() || IsIrqMasked()) {
freq = svcRtxKernelGetSysTimerFreq();
} else {
freq = __svcKernelGetSysTimerFreq();
}
return freq;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_kernel.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 7,984 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: System functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// ==== Helper functions ====
/// Put Object into ISR Queue.
/// \param[in] object object.
/// \return 1 - success, 0 - failure.
static uint32_t isr_queue_put (os_object_t *object) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#else
uint32_t n;
#endif
uint16_t max;
uint32_t ret;
max = osRtxInfo.isr_queue.max;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
if (osRtxInfo.isr_queue.cnt < max) {
osRtxInfo.isr_queue.cnt++;
osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.in] = object;
if (++osRtxInfo.isr_queue.in == max) {
osRtxInfo.isr_queue.in = 0U;
}
ret = 1U;
} else {
ret = 0U;
}
if (primask == 0U) {
__enable_irq();
}
#else
if (atomic_inc16_lt(&osRtxInfo.isr_queue.cnt, max) < max) {
n = atomic_inc16_lim(&osRtxInfo.isr_queue.in, max);
osRtxInfo.isr_queue.data[n] = object;
ret = 1U;
} else {
ret = 0U;
}
#endif
return ret;
}
/// Get Object from ISR Queue.
/// \return object or NULL.
static os_object_t *isr_queue_get (void) {
#if (EXCLUSIVE_ACCESS != 0)
uint32_t n;
#endif
uint16_t max;
os_object_t *ret;
max = osRtxInfo.isr_queue.max;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
if (osRtxInfo.isr_queue.cnt != 0U) {
osRtxInfo.isr_queue.cnt--;
ret = osRtxObject(osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out]);
if (++osRtxInfo.isr_queue.out == max) {
osRtxInfo.isr_queue.out = 0U;
}
} else {
ret = NULL;
}
__enable_irq();
#else
if (atomic_dec16_nz(&osRtxInfo.isr_queue.cnt) != 0U) {
n = atomic_inc16_lim(&osRtxInfo.isr_queue.out, max);
ret = osRtxObject(osRtxInfo.isr_queue.data[n]);
} else {
ret = NULL;
}
#endif
return ret;
}
// ==== Library Functions ====
/// Tick Handler.
//lint -esym(714,osRtxTick_Handler) "Referenced by Exception handlers"
//lint -esym(759,osRtxTick_Handler) "Prototype in header"
//lint -esym(765,osRtxTick_Handler) "Global scope"
void osRtxTick_Handler (void) {
os_thread_t *thread;
OS_Tick_AcknowledgeIRQ();
osRtxInfo.kernel.tick++;
// Process Thread Delays
osRtxThreadDelayTick();
osRtxThreadDispatch(NULL);
// Process Timers
if (osRtxInfo.timer.tick != NULL) {
osRtxInfo.timer.tick();
}
#ifdef RTX_THREAD_WATCHDOG
// Process Watchdog Timers
osRtxThreadWatchdogTick();
#endif
// Check Round Robin timeout
if (osRtxInfo.thread.robin.timeout != 0U) {
thread = osRtxInfo.thread.run.next;
if (thread != osRtxInfo.thread.robin.thread) {
osRtxInfo.thread.robin.thread = thread;
if (thread->delay == 0U) {
// Reset Round Robin
thread->delay = osRtxInfo.thread.robin.timeout;
}
}
if (thread->delay != 0U) {
thread->delay--;
}
if (thread->delay == 0U) {
// Round Robin Timeout
if (osRtxKernelGetState() == osRtxKernelRunning) {
thread = osRtxInfo.thread.ready.thread_list;
if ((thread != NULL) && (thread->priority == osRtxInfo.thread.robin.thread->priority)) {
osRtxThreadListRemove(thread);
osRtxThreadReadyPut(osRtxInfo.thread.robin.thread);
EvrRtxThreadPreempted(osRtxInfo.thread.robin.thread);
osRtxThreadSwitch(thread);
osRtxInfo.thread.robin.thread = thread;
thread->delay = osRtxInfo.thread.robin.timeout;
}
}
}
}
}
/// Pending Service Call Handler.
//lint -esym(714,osRtxPendSV_Handler) "Referenced by Exception handlers"
//lint -esym(759,osRtxPendSV_Handler) "Prototype in header"
//lint -esym(765,osRtxPendSV_Handler) "Global scope"
void osRtxPendSV_Handler (void) {
os_object_t *object;
for (;;) {
object = isr_queue_get();
if (object == NULL) {
break;
}
switch (object->id) {
case osRtxIdThread:
osRtxInfo.post_process.thread(osRtxThreadObject(object));
break;
case osRtxIdEventFlags:
osRtxInfo.post_process.event_flags(osRtxEventFlagsObject(object));
break;
case osRtxIdSemaphore:
osRtxInfo.post_process.semaphore(osRtxSemaphoreObject(object));
break;
case osRtxIdMemoryPool:
osRtxInfo.post_process.memory_pool(osRtxMemoryPoolObject(object));
break;
case osRtxIdMessage:
osRtxInfo.post_process.message(osRtxMessageObject(object));
break;
default:
// Should never come here
break;
}
}
osRtxThreadDispatch(NULL);
}
/// Register post ISR processing.
/// \param[in] object generic object.
void osRtxPostProcess (os_object_t *object) {
if (isr_queue_put(object) != 0U) {
if (osRtxInfo.kernel.blocked == 0U) {
SetPendSV();
} else {
osRtxInfo.kernel.pendSV = 1U;
}
} else {
(void)osRtxKernelErrorNotify(osRtxErrorISRQueueOverflow, object);
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_system.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,534 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Event Flags functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxEventFlagsMemUsage \
__attribute__((section(".data.os.evflags.obj"))) =
{ 0U, 0U, 0U };
#endif
// ==== Helper functions ====
/// Set Event Flags.
/// \param[in] ef event flags object.
/// \param[in] flags specifies the flags to set.
/// \return event flags after setting.
static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t event_flags;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
ef->event_flags |= flags;
event_flags = ef->event_flags;
if (primask == 0U) {
__enable_irq();
}
#else
event_flags = atomic_set32(&ef->event_flags, flags);
#endif
return event_flags;
}
/// Clear Event Flags.
/// \param[in] ef event flags object.
/// \param[in] flags specifies the flags to clear.
/// \return event flags before clearing.
static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t event_flags;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
event_flags = ef->event_flags;
ef->event_flags &= ~flags;
if (primask == 0U) {
__enable_irq();
}
#else
event_flags = atomic_clr32(&ef->event_flags, flags);
#endif
return event_flags;
}
/// Check Event Flags.
/// \param[in] ef event flags object.
/// \param[in] flags specifies the flags to check.
/// \param[in] options specifies flags options (osFlagsXxxx).
/// \return event flags before clearing or 0 if specified flags have not been set.
static uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask;
#endif
uint32_t event_flags;
if ((options & osFlagsNoClear) == 0U) {
#if (EXCLUSIVE_ACCESS == 0)
primask = __get_PRIMASK();
__disable_irq();
event_flags = ef->event_flags;
if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||
(((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {
event_flags = 0U;
} else {
ef->event_flags &= ~flags;
}
if (primask == 0U) {
__enable_irq();
}
#else
if ((options & osFlagsWaitAll) != 0U) {
event_flags = atomic_chk32_all(&ef->event_flags, flags);
} else {
event_flags = atomic_chk32_any(&ef->event_flags, flags);
}
#endif
} else {
event_flags = ef->event_flags;
if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||
(((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {
event_flags = 0U;
}
}
return event_flags;
}
/// Verify that Event Flags object pointer is valid.
/// \param[in] ef event flags object.
/// \return true - valid, false - invalid.
static bool_t IsEventFlagsPtrValid (const os_event_flags_t *ef) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_evflags_cb_start__;
uint32_t cb_length = (uint32_t)&__os_evflags_cb_length__;
// Check the section boundaries
if (((uint32_t)ef - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)ef - cb_start) % sizeof(os_event_flags_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (ef == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
// ==== Library functions ====
/// Destroy an Event Flags object.
/// \param[in] ef event flags object.
static void osRtxEventFlagsDestroy (os_event_flags_t *ef) {
// Mark object as invalid
ef->id = osRtxIdInvalid;
// Free object memory
if ((ef->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef);
#else
if (osRtxInfo.mpi.event_flags != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, ef);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxEventFlagsMemUsage.cnt_free++;
#endif
}
EvrRtxEventFlagsDestroyed(ef);
}
#ifdef RTX_SAFETY_CLASS
/// Delete an Event Flags safety class.
/// \param[in] safety_class safety class.
/// \param[in] mode safety mode.
void osRtxEventFlagsDeleteClass (uint32_t safety_class, uint32_t mode) {
os_event_flags_t *ef;
os_thread_t *thread;
uint32_t length;
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
ef = (os_event_flags_t *)(uint32_t)&__os_evflags_cb_start__;
length = (uint32_t)&__os_evflags_cb_length__;
while (length >= sizeof(os_event_flags_t)) {
if ( (ef->id == osRtxIdEventFlags) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((ef->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((ef->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
while (ef->thread_list != NULL) {
thread = osRtxThreadListGet(osRtxObject(ef));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
}
osRtxEventFlagsDestroy(ef);
}
length -= sizeof(os_event_flags_t);
ef++;
}
}
#endif
// ==== Post ISR processing ====
/// Event Flags post ISR processing.
/// \param[in] ef event flags object.
static void osRtxEventFlagsPostProcess (os_event_flags_t *ef) {
os_thread_t *thread;
os_thread_t *thread_next;
uint32_t event_flags;
// Check if Threads are waiting for Event Flags
thread = ef->thread_list;
while (thread != NULL) {
thread_next = thread->thread_next;
event_flags = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);
if (event_flags != 0U) {
osRtxThreadListRemove(thread);
osRtxThreadWaitExit(thread, event_flags, FALSE);
EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags);
}
thread = thread_next;
}
}
// ==== Service Calls ====
/// Create and Initialize an Event Flags object.
/// \note API identical to osEventFlagsNew
static osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {
os_event_flags_t *ef;
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread = osRtxThreadGetRunning();
uint32_t attr_bits;
#endif
uint8_t flags;
const char *name;
// Process attributes
if (attr != NULL) {
name = attr->name;
#ifdef RTX_SAFETY_CLASS
attr_bits = attr->attr_bits;
#endif
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
ef = attr->cb_mem;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxEventFlagsError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (ef != NULL) {
if (!IsEventFlagsPtrValid(ef) || (attr->cb_size != sizeof(os_event_flags_t))) {
EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
#ifdef RTX_SAFETY_CLASS
attr_bits = 0U;
#endif
ef = NULL;
}
// Allocate object memory if not provided
if (ef == NULL) {
if (osRtxInfo.mpi.event_flags != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
ef = osRtxMemoryPoolAlloc(osRtxInfo.mpi.event_flags);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
ef = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_event_flags_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (ef != NULL) {
uint32_t used;
osRtxEventFlagsMemUsage.cnt_alloc++;
used = osRtxEventFlagsMemUsage.cnt_alloc - osRtxEventFlagsMemUsage.cnt_free;
if (osRtxEventFlagsMemUsage.max_used < used) {
osRtxEventFlagsMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
if (ef != NULL) {
// Initialize control block
ef->id = osRtxIdEventFlags;
ef->flags = flags;
ef->attr = 0U;
ef->name = name;
ef->thread_list = NULL;
ef->event_flags = 0U;
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
ef->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread != NULL) {
ef->attr |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);
}
}
#endif
// Register post ISR processing function
osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess;
EvrRtxEventFlagsCreated(ef, ef->name);
} else {
EvrRtxEventFlagsError(NULL, (int32_t)osErrorNoMemory);
}
return ef;
}
/// Get name of an Event Flags object.
/// \note API identical to osEventFlagsGetName
static const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {
EvrRtxEventFlagsGetName(ef, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxEventFlagsGetName(ef, ef->name);
return ef->name;
}
/// Set the specified Event Flags.
/// \note API identical to osEventFlagsSet
static uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
os_thread_t *thread;
os_thread_t *thread_next;
uint32_t event_flags;
uint32_t event_flags0;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||
((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorSafetyClass);
}
#endif
// Set Event Flags
event_flags = EventFlagsSet(ef, flags);
// Check if Threads are waiting for Event Flags
thread = ef->thread_list;
while (thread != NULL) {
thread_next = thread->thread_next;
event_flags0 = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);
if (event_flags0 != 0U) {
if ((thread->flags_options & osFlagsNoClear) == 0U) {
event_flags = event_flags0 & ~thread->wait_flags;
} else {
event_flags = event_flags0;
}
osRtxThreadListRemove(thread);
osRtxThreadWaitExit(thread, event_flags0, FALSE);
EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags0);
}
thread = thread_next;
}
osRtxThreadDispatch(NULL);
EvrRtxEventFlagsSetDone(ef, event_flags);
return event_flags;
}
/// Clear the specified Event Flags.
/// \note API identical to osEventFlagsClear
static uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread;
#endif
uint32_t event_flags;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||
((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorSafetyClass);
}
#endif
// Clear Event Flags
event_flags = EventFlagsClear(ef, flags);
EvrRtxEventFlagsClearDone(ef, event_flags);
return event_flags;
}
/// Get the current Event Flags.
/// \note API identical to osEventFlagsGet
static uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {
EvrRtxEventFlagsGet(ef, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxEventFlagsGet(ef, ef->event_flags);
return ef->event_flags;
}
/// Wait for one or more Event Flags to become signaled.
/// \note API identical to osEventFlagsWait
static uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
os_thread_t *thread;
uint32_t event_flags;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||
((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorSafetyClass);
}
#endif
// Check Event Flags
event_flags = EventFlagsCheck(ef, flags, options);
if (event_flags != 0U) {
EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);
} else {
// Check if timeout is specified
if (timeout != 0U) {
EvrRtxEventFlagsWaitPending(ef, flags, options, timeout);
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout)) {
thread = osRtxThreadGetRunning();
osRtxThreadListPut(osRtxObject(ef), thread);
// Store waiting flags and options
thread->wait_flags = flags;
thread->flags_options = (uint8_t)options;
} else {
EvrRtxEventFlagsWaitTimeout(ef);
}
event_flags = (uint32_t)osErrorTimeout;
} else {
EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);
event_flags = (uint32_t)osErrorResource;
}
}
return event_flags;
}
/// Delete an Event Flags object.
/// \note API identical to osEventFlagsDelete
static osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
os_thread_t *thread;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Unblock waiting threads
if (ef->thread_list != NULL) {
do {
thread = osRtxThreadListGet(osRtxObject(ef));
osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);
} while (ef->thread_list != NULL);
osRtxThreadDispatch(NULL);
}
osRtxEventFlagsDestroy(ef);
return osOK;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_1(EventFlagsNew, osEventFlagsId_t, const osEventFlagsAttr_t *)
SVC0_1(EventFlagsGetName, const char *, osEventFlagsId_t)
SVC0_2(EventFlagsSet, uint32_t, osEventFlagsId_t, uint32_t)
SVC0_2(EventFlagsClear, uint32_t, osEventFlagsId_t, uint32_t)
SVC0_1(EventFlagsGet, uint32_t, osEventFlagsId_t)
SVC0_4(EventFlagsWait, uint32_t, osEventFlagsId_t, uint32_t, uint32_t, uint32_t)
SVC0_1(EventFlagsDelete, osStatus_t, osEventFlagsId_t)
//lint --flb "Library End"
// ==== ISR Calls ====
/// Set the specified Event Flags.
/// \note API identical to osEventFlagsSet
__STATIC_INLINE
uint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
uint32_t event_flags;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||
((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Set Event Flags
event_flags = EventFlagsSet(ef, flags);
// Register post ISR processing
osRtxPostProcess(osRtxObject(ef));
EvrRtxEventFlagsSetDone(ef, event_flags);
return event_flags;
}
/// Wait for one or more Event Flags to become signaled.
/// \note API identical to osEventFlagsWait
__STATIC_INLINE
uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
os_event_flags_t *ef = osRtxEventFlagsId(ef_id);
uint32_t event_flags;
// Check parameters
if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) || (timeout != 0U) ||
((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {
EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Check Event Flags
event_flags = EventFlagsCheck(ef, flags, options);
if (event_flags != 0U) {
EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);
} else {
EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);
event_flags = (uint32_t)osErrorResource;
}
return event_flags;
}
// ==== Public API ====
/// Create and Initialize an Event Flags object.
osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
osEventFlagsId_t ef_id;
EvrRtxEventFlagsNew(attr);
if (IsException() || IsIrqMasked()) {
EvrRtxEventFlagsError(NULL, (int32_t)osErrorISR);
ef_id = NULL;
} else {
ef_id = __svcEventFlagsNew(attr);
}
return ef_id;
}
/// Get name of an Event Flags object.
const char *osEventFlagsGetName (osEventFlagsId_t ef_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxEventFlagsGetName(ef_id);
} else {
name = __svcEventFlagsGetName(ef_id);
}
return name;
}
/// Set the specified Event Flags.
uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
uint32_t event_flags;
EvrRtxEventFlagsSet(ef_id, flags);
if (IsException() || IsIrqMasked()) {
event_flags = isrRtxEventFlagsSet(ef_id, flags);
} else {
event_flags = __svcEventFlagsSet(ef_id, flags);
}
return event_flags;
}
/// Clear the specified Event Flags.
uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
uint32_t event_flags;
EvrRtxEventFlagsClear(ef_id, flags);
if (IsException() || IsIrqMasked()) {
event_flags = svcRtxEventFlagsClear(ef_id, flags);
} else {
event_flags = __svcEventFlagsClear(ef_id, flags);
}
return event_flags;
}
/// Get the current Event Flags.
uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
uint32_t event_flags;
if (IsException() || IsIrqMasked()) {
event_flags = svcRtxEventFlagsGet(ef_id);
} else {
event_flags = __svcEventFlagsGet(ef_id);
}
return event_flags;
}
/// Wait for one or more Event Flags to become signaled.
uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
uint32_t event_flags;
EvrRtxEventFlagsWait(ef_id, flags, options, timeout);
if (IsException() || IsIrqMasked()) {
event_flags = isrRtxEventFlagsWait(ef_id, flags, options, timeout);
} else {
event_flags = __svcEventFlagsWait(ef_id, flags, options, timeout);
}
return event_flags;
}
/// Delete an Event Flags object.
osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {
osStatus_t status;
EvrRtxEventFlagsDelete(ef_id);
if (IsException() || IsIrqMasked()) {
EvrRtxEventFlagsError(ef_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcEventFlagsDelete(ef_id);
}
return status;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_evflags.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 6,606 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex Core definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CORE_C_H_
#define RTX_CORE_C_H_
//lint -emacro((923,9078),SCB) "cast from unsigned long to pointer" [MISRA Note 9]
#ifndef RTE_COMPONENTS_H
#include "RTE_Components.h"
#endif
#include CMSIS_device_header
#if ((!defined(__ARM_ARCH_6M__)) && \
(!defined(__ARM_ARCH_7A__)) && \
(!defined(__ARM_ARCH_7M__)) && \
(!defined(__ARM_ARCH_7EM__)) && \
(!defined(__ARM_ARCH_8M_BASE__)) && \
(!defined(__ARM_ARCH_8M_MAIN__)) && \
(!defined(__ARM_ARCH_8_1M_MAIN__)))
#error "Unknown Arm Architecture!"
#endif
#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))
#include "rtx_core_ca.h"
#else
#include "rtx_core_cm.h"
#endif
#endif // RTX_CORE_C_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_core_c.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 299 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: Thread functions
*
* your_sha256_hash-------------
*/
#include "rtx_lib.h"
// OS Runtime Object Memory Usage
#ifdef RTX_OBJ_MEM_USAGE
osRtxObjectMemUsage_t osRtxThreadMemUsage \
__attribute__((section(".data.os.thread.obj"))) =
{ 0U, 0U, 0U };
#endif
// Runtime Class/Zone assignment table
#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)
static uint8_t ThreadClassTable[64] __attribute__((section(".data.os"))) = { 0U };
#endif
// Watchdog Alarm Flag
#if defined(RTX_THREAD_WATCHDOG) && defined(RTX_EXECUTION_ZONE)
static uint8_t WatchdogAlarmFlag __attribute__((section(".data.os"))) = 0U;
#endif
// ==== Helper functions ====
/// Set Thread Flags.
/// \param[in] thread thread object.
/// \param[in] flags specifies the flags to set.
/// \return thread flags after setting.
static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t thread_flags;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
thread->thread_flags |= flags;
thread_flags = thread->thread_flags;
if (primask == 0U) {
__enable_irq();
}
#else
thread_flags = atomic_set32(&thread->thread_flags, flags);
#endif
return thread_flags;
}
/// Clear Thread Flags.
/// \param[in] thread thread object.
/// \param[in] flags specifies the flags to clear.
/// \return thread flags before clearing.
static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask = __get_PRIMASK();
#endif
uint32_t thread_flags;
#if (EXCLUSIVE_ACCESS == 0)
__disable_irq();
thread_flags = thread->thread_flags;
thread->thread_flags &= ~flags;
if (primask == 0U) {
__enable_irq();
}
#else
thread_flags = atomic_clr32(&thread->thread_flags, flags);
#endif
return thread_flags;
}
/// Check Thread Flags.
/// \param[in] thread thread object.
/// \param[in] flags specifies the flags to check.
/// \param[in] options specifies flags options (osFlagsXxxx).
/// \return thread flags before clearing or 0 if specified flags have not been set.
static uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) {
#if (EXCLUSIVE_ACCESS == 0)
uint32_t primask;
#endif
uint32_t thread_flags;
if ((options & osFlagsNoClear) == 0U) {
#if (EXCLUSIVE_ACCESS == 0)
primask = __get_PRIMASK();
__disable_irq();
thread_flags = thread->thread_flags;
if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||
(((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {
thread_flags = 0U;
} else {
thread->thread_flags &= ~flags;
}
if (primask == 0U) {
__enable_irq();
}
#else
if ((options & osFlagsWaitAll) != 0U) {
thread_flags = atomic_chk32_all(&thread->thread_flags, flags);
} else {
thread_flags = atomic_chk32_any(&thread->thread_flags, flags);
}
#endif
} else {
thread_flags = thread->thread_flags;
if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||
(((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {
thread_flags = 0U;
}
}
return thread_flags;
}
/// Verify that Thread object pointer is valid.
/// \param[in] thread thread object.
/// \return true - valid, false - invalid.
static bool_t IsThreadPtrValid (const os_thread_t *thread) {
#ifdef RTX_OBJ_PTR_CHECK
//lint --e{923} --e{9078} "cast from pointer to unsigned int" [MISRA Note 7]
uint32_t cb_start = (uint32_t)&__os_thread_cb_start__;
uint32_t cb_length = (uint32_t)&__os_thread_cb_length__;
// Check the section boundaries
if (((uint32_t)thread - cb_start) >= cb_length) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check the object alignment
if ((((uint32_t)thread - cb_start) % sizeof(os_thread_t)) != 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#else
// Check NULL pointer
if (thread == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
#endif
return TRUE;
}
#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)
/// Check if Thread Zone to Safety Class mapping is valid.
/// \param[in] attr_bits thread attributes.
/// \param[in] thread running thread.
/// \return true - valid, false - not valid.
static bool_t IsClassMappingValid (uint32_t attr_bits, const os_thread_t *thread) {
uint32_t safety_class;
uint32_t zone;
if ((attr_bits & osThreadZone_Valid) != 0U) {
zone = (attr_bits & osThreadZone_Msk) >> osThreadZone_Pos;
} else if (thread != NULL) {
zone = thread->zone;
} else {
zone = 0U;
}
if ((attr_bits & osSafetyClass_Valid) != 0U) {
safety_class = (attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos;
} else if (thread != NULL) {
safety_class = (uint32_t)thread->attr >> osRtxAttrClass_Pos;
} else {
safety_class = 0U;
}
// Check if zone is free or assigned to class
if ((ThreadClassTable[zone] == 0U) ||
(ThreadClassTable[zone] == (0x80U | safety_class))) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return TRUE;
}
// Invalid class to zone mapping
return FALSE;
}
#endif
// ==== Library functions ====
/// Put a Thread into specified Object list sorted by Priority (Highest at Head).
/// \param[in] object generic object.
/// \param[in] thread thread object.
void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) {
os_thread_t *prev, *next;
int32_t priority;
priority = thread->priority;
prev = osRtxThreadObject(object);
next = prev->thread_next;
while ((next != NULL) && (next->priority >= priority)) {
prev = next;
next = next->thread_next;
}
thread->thread_prev = prev;
thread->thread_next = next;
prev->thread_next = thread;
if (next != NULL) {
next->thread_prev = thread;
}
}
/// Get a Thread with Highest Priority from specified Object list and remove it.
/// \param[in] object generic object.
/// \return thread object.
os_thread_t *osRtxThreadListGet (os_object_t *object) {
os_thread_t *thread;
thread = object->thread_list;
object->thread_list = thread->thread_next;
if (thread->thread_next != NULL) {
thread->thread_next->thread_prev = osRtxThreadObject(object);
}
thread->thread_prev = NULL;
return thread;
}
/// Retrieve Thread list root object.
/// \param[in] thread thread object.
/// \return root object.
static void *osRtxThreadListRoot (os_thread_t *thread) {
os_thread_t *thread0;
thread0 = thread;
while (thread0->id == osRtxIdThread) {
thread0 = thread0->thread_prev;
}
return thread0;
}
/// Re-sort a Thread in linked Object list by Priority (Highest at Head).
/// \param[in] thread thread object.
void osRtxThreadListSort (os_thread_t *thread) {
os_object_t *object;
os_thread_t *thread0;
// Search for object
thread0 = thread;
while ((thread0 != NULL) && (thread0->id == osRtxIdThread)) {
thread0 = thread0->thread_prev;
}
object = osRtxObject(thread0);
if (object != NULL) {
osRtxThreadListRemove(thread);
osRtxThreadListPut(object, thread);
}
}
/// Remove a Thread from linked Object list.
/// \param[in] thread thread object.
void osRtxThreadListRemove (os_thread_t *thread) {
if (thread->thread_prev != NULL) {
thread->thread_prev->thread_next = thread->thread_next;
if (thread->thread_next != NULL) {
thread->thread_next->thread_prev = thread->thread_prev;
}
thread->thread_prev = NULL;
}
}
/// Unlink a Thread from specified linked list.
/// \param[in] thread thread object.
static void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) {
if (thread->thread_next != NULL) {
thread->thread_next->thread_prev = thread->thread_prev;
}
if (thread->thread_prev != NULL) {
thread->thread_prev->thread_next = thread->thread_next;
thread->thread_prev = NULL;
} else {
*thread_list = thread->thread_next;
}
}
/// Mark a Thread as Ready and put it into Ready list (sorted by Priority).
/// \param[in] thread thread object.
void osRtxThreadReadyPut (os_thread_t *thread) {
thread->state = osRtxThreadReady;
osRtxThreadListPut(&osRtxInfo.thread.ready, thread);
}
/// Insert a Thread into the Delay list sorted by Delay (Lowest at Head).
/// \param[in] thread thread object.
/// \param[in] delay delay value.
static void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) {
os_thread_t *prev, *next;
if (delay == osWaitForever) {
prev = NULL;
next = osRtxInfo.thread.wait_list;
while (next != NULL) {
prev = next;
next = next->delay_next;
}
thread->delay = delay;
thread->delay_prev = prev;
thread->delay_next = NULL;
if (prev != NULL) {
prev->delay_next = thread;
} else {
osRtxInfo.thread.wait_list = thread;
}
} else {
prev = NULL;
next = osRtxInfo.thread.delay_list;
while ((next != NULL) && (next->delay <= delay)) {
delay -= next->delay;
prev = next;
next = next->delay_next;
}
thread->delay = delay;
thread->delay_prev = prev;
thread->delay_next = next;
if (prev != NULL) {
prev->delay_next = thread;
} else {
osRtxInfo.thread.delay_list = thread;
}
if (next != NULL) {
next->delay -= delay;
next->delay_prev = thread;
}
}
}
/// Remove a Thread from the Delay list.
/// \param[in] thread thread object.
void osRtxThreadDelayRemove (os_thread_t *thread) {
if (thread->delay == osWaitForever) {
if (thread->delay_next != NULL) {
thread->delay_next->delay_prev = thread->delay_prev;
}
if (thread->delay_prev != NULL) {
thread->delay_prev->delay_next = thread->delay_next;
thread->delay_prev = NULL;
} else {
osRtxInfo.thread.wait_list = thread->delay_next;
}
} else {
if (thread->delay_next != NULL) {
thread->delay_next->delay += thread->delay;
thread->delay_next->delay_prev = thread->delay_prev;
}
if (thread->delay_prev != NULL) {
thread->delay_prev->delay_next = thread->delay_next;
thread->delay_prev = NULL;
} else {
osRtxInfo.thread.delay_list = thread->delay_next;
}
}
thread->delay = 0U;
}
/// Process Thread Delay Tick (executed each System Tick).
void osRtxThreadDelayTick (void) {
os_thread_t *thread;
os_object_t *object;
thread = osRtxInfo.thread.delay_list;
if (thread == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
thread->delay--;
if (thread->delay == 0U) {
do {
switch (thread->state) {
case osRtxThreadWaitingDelay:
EvrRtxDelayCompleted(thread);
break;
case osRtxThreadWaitingThreadFlags:
EvrRtxThreadFlagsWaitTimeout(thread);
break;
case osRtxThreadWaitingEventFlags:
EvrRtxEventFlagsWaitTimeout((osEventFlagsId_t)osRtxThreadListRoot(thread));
break;
case osRtxThreadWaitingMutex:
object = osRtxObject(osRtxThreadListRoot(thread));
osRtxMutexOwnerRestore(osRtxMutexObject(object), thread);
EvrRtxMutexAcquireTimeout(osRtxMutexObject(object));
break;
case osRtxThreadWaitingSemaphore:
EvrRtxSemaphoreAcquireTimeout((osSemaphoreId_t)osRtxThreadListRoot(thread));
break;
case osRtxThreadWaitingMemoryPool:
EvrRtxMemoryPoolAllocTimeout((osMemoryPoolId_t)osRtxThreadListRoot(thread));
break;
case osRtxThreadWaitingMessageGet:
EvrRtxMessageQueueGetTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));
break;
case osRtxThreadWaitingMessagePut:
EvrRtxMessageQueuePutTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));
break;
default:
// Invalid
break;
}
EvrRtxThreadUnblocked(thread, (osRtxThreadRegPtr(thread))[0]);
osRtxThreadListRemove(thread);
osRtxThreadReadyPut(thread);
thread = thread->delay_next;
} while ((thread != NULL) && (thread->delay == 0U));
if (thread != NULL) {
thread->delay_prev = NULL;
}
osRtxInfo.thread.delay_list = thread;
}
}
/// Get pointer to Thread registers (R0..R3)
/// \param[in] thread thread object.
/// \return pointer to registers R0-R3.
uint32_t *osRtxThreadRegPtr (const os_thread_t *thread) {
uint32_t addr = thread->sp + StackOffsetR0(thread->stack_frame);
//lint -e{923} -e{9078} "cast from unsigned int to pointer"
return ((uint32_t *)addr);
}
/// Block running Thread execution and register it as Ready to Run.
/// \param[in] thread running thread object.
static void osRtxThreadBlock (os_thread_t *thread) {
os_thread_t *prev, *next;
int32_t priority;
thread->state = osRtxThreadReady;
priority = thread->priority;
prev = osRtxThreadObject(&osRtxInfo.thread.ready);
next = prev->thread_next;
while ((next != NULL) && (next->priority > priority)) {
prev = next;
next = next->thread_next;
}
thread->thread_prev = prev;
thread->thread_next = next;
prev->thread_next = thread;
if (next != NULL) {
next->thread_prev = thread;
}
EvrRtxThreadPreempted(thread);
}
/// Switch to specified Thread.
/// \param[in] thread thread object.
void osRtxThreadSwitch (os_thread_t *thread) {
thread->state = osRtxThreadRunning;
SetPrivileged((bool_t)((thread->attr & osThreadPrivileged) != 0U));
osRtxInfo.thread.run.next = thread;
EvrRtxThreadSwitched(thread);
}
/// Dispatch specified Thread or Ready Thread with Highest Priority.
/// \param[in] thread thread object or NULL.
void osRtxThreadDispatch (os_thread_t *thread) {
uint8_t kernel_state;
os_thread_t *thread_running;
os_thread_t *thread_ready;
kernel_state = osRtxKernelGetState();
thread_running = osRtxThreadGetRunning();
if (thread == NULL) {
thread_ready = osRtxInfo.thread.ready.thread_list;
if ((kernel_state == osRtxKernelRunning) &&
(thread_ready != NULL) &&
(thread_ready->priority > thread_running->priority)) {
// Preempt running Thread
osRtxThreadListRemove(thread_ready);
osRtxThreadBlock(thread_running);
osRtxThreadSwitch(thread_ready);
}
} else {
if ((kernel_state == osRtxKernelRunning) &&
(thread->priority > thread_running->priority)) {
// Preempt running Thread
osRtxThreadBlock(thread_running);
osRtxThreadSwitch(thread);
} else {
// Put Thread into Ready list
osRtxThreadReadyPut(thread);
}
}
}
/// Exit Thread wait state.
/// \param[in] thread thread object.
/// \param[in] ret_val return value.
/// \param[in] dispatch dispatch flag.
void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch) {
uint32_t *reg;
EvrRtxThreadUnblocked(thread, ret_val);
reg = osRtxThreadRegPtr(thread);
reg[0] = ret_val;
osRtxThreadDelayRemove(thread);
if (dispatch) {
osRtxThreadDispatch(thread);
} else {
osRtxThreadReadyPut(thread);
}
}
/// Enter Thread wait state.
/// \param[in] state new thread state.
/// \param[in] timeout timeout.
/// \return true - success, false - failure.
bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) {
os_thread_t *thread;
// Check if Kernel is running
if (osRtxKernelGetState() != osRtxKernelRunning) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Check if any thread is ready
if (osRtxInfo.thread.ready.thread_list == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
// Get running thread
thread = osRtxThreadGetRunning();
EvrRtxThreadBlocked(thread, timeout);
thread->state = state;
osRtxThreadDelayInsert(thread, timeout);
thread = osRtxThreadListGet(&osRtxInfo.thread.ready);
osRtxThreadSwitch(thread);
return TRUE;
}
#ifdef RTX_STACK_CHECK
/// Check current running Thread Stack.
/// \param[in] thread running thread.
/// \return true - success, false - failure.
//lint -esym(714,osRtxThreadStackCheck) "Referenced by Exception handlers"
//lint -esym(759,osRtxThreadStackCheck) "Prototype in header"
//lint -esym(765,osRtxThreadStackCheck) "Global scope"
bool_t osRtxThreadStackCheck (const os_thread_t *thread) {
//lint -e{923} "cast from pointer to unsigned int"
//lint -e{9079} -e{9087} "cast between pointers to different object types"
if ((thread->sp <= (uint32_t)thread->stack_mem) ||
(*((uint32_t *)thread->stack_mem) != osRtxStackMagicWord)) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return FALSE;
}
return TRUE;
}
#endif
#ifdef RTX_THREAD_WATCHDOG
/// Insert a Thread into the Watchdog list, sorted by tick (lowest at Head).
/// \param[in] thread thread object.
/// \param[in] ticks watchdog timeout.
static void osRtxThreadWatchdogInsert (os_thread_t *thread, uint32_t ticks) {
os_thread_t *prev, *next;
if (ticks == 0U) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
prev = NULL;
next = osRtxInfo.thread.wdog_list;
while ((next != NULL) && ((next->wdog_tick <= ticks))) {
ticks -= next->wdog_tick;
prev = next;
next = next->wdog_next;
}
thread->wdog_tick = ticks;
thread->wdog_next = next;
if (next != NULL) {
next->wdog_tick -= ticks;
}
if (prev != NULL) {
prev->wdog_next = thread;
} else {
osRtxInfo.thread.wdog_list = thread;
}
}
/// Remove a Thread from the Watchdog list.
/// \param[in] thread thread object.
void osRtxThreadWatchdogRemove (const os_thread_t *thread) {
os_thread_t *prev, *next;
prev = NULL;
next = osRtxInfo.thread.wdog_list;
while ((next != NULL) && (next != thread)) {
prev = next;
next = next->wdog_next;
}
if (next == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
if (thread->wdog_next != NULL) {
thread->wdog_next->wdog_tick += thread->wdog_tick;
}
if (prev != NULL) {
prev->wdog_next = thread->wdog_next;
} else {
osRtxInfo.thread.wdog_list = thread->wdog_next;
}
}
/// Process Watchdog Tick (executed each System Tick).
void osRtxThreadWatchdogTick (void) {
os_thread_t *thread_running;
os_thread_t *thread;
#ifdef RTX_SAFETY_CLASS
os_thread_t *next;
#endif
uint32_t ticks;
thread = osRtxInfo.thread.wdog_list;
if (thread == NULL) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
thread->wdog_tick--;
if (thread->wdog_tick == 0U) {
// Call watchdog handler for all expired threads
thread_running = osRtxThreadGetRunning();
do {
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
#ifdef RTX_SAFETY_CLASS
// First the highest safety thread (sorted by Safety Class)
next = thread->wdog_next;
while ((next != NULL) && (next->wdog_tick == 0U)) {
if ((next->attr & osRtxAttrClass_Msk) > (thread->attr & osRtxAttrClass_Msk)) {
thread = next;
}
next = next->wdog_next;
}
#endif
osRtxThreadWatchdogRemove(thread);
EvrRtxThreadWatchdogExpired(thread);
#ifdef RTX_EXECUTION_ZONE
WatchdogAlarmFlag = 1U;
#endif
ticks = osWatchdogAlarm_Handler(thread);
#ifdef RTX_EXECUTION_ZONE
WatchdogAlarmFlag = 0U;
#endif
osRtxThreadWatchdogInsert(thread, ticks);
thread = osRtxInfo.thread.wdog_list;
} while ((thread != NULL) && (thread->wdog_tick == 0U));
osRtxThreadSetRunning(thread_running);
}
}
#endif
static __NO_RETURN void osThreadEntry (void *argument, osThreadFunc_t func) {
func(argument);
osThreadExit();
}
// ==== Post ISR processing ====
/// Thread post ISR processing.
/// \param[in] thread thread object.
static void osRtxThreadPostProcess (os_thread_t *thread) {
uint32_t thread_flags;
// Check if Thread is waiting for Thread Flags
if (thread->state == osRtxThreadWaitingThreadFlags) {
thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);
if (thread_flags != 0U) {
osRtxThreadWaitExit(thread, thread_flags, FALSE);
EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags, thread);
}
}
}
// ==== Service Calls ====
/// Create a thread and add it to Active Threads.
/// \note API identical to osThreadNew
static osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
os_thread_t *thread;
#if defined(RTX_SAFETY_CLASS) || defined(RTX_EXECUTION_ZONE)
const os_thread_t *thread_running = osRtxThreadGetRunning();
#endif
uint32_t attr_bits;
void *stack_mem;
uint32_t stack_size;
osPriority_t priority;
uint8_t flags;
const char *name;
uint32_t *ptr;
uint32_t n;
#ifdef RTX_TZ_CONTEXT
TZ_ModuleId_t tz_module;
TZ_MemoryId_t tz_memory;
#endif
// Check parameters
if (func == NULL) {
EvrRtxThreadError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
// Process attributes
if (attr != NULL) {
name = attr->name;
attr_bits = attr->attr_bits;
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
thread = attr->cb_mem;
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6]
stack_mem = attr->stack_mem;
stack_size = attr->stack_size;
priority = attr->priority;
#ifdef RTX_TZ_CONTEXT
tz_module = attr->tz_module;
#endif
if (((attr_bits & osThreadPrivileged) != 0U) && ((attr_bits & osThreadUnprivileged) != 0U)) {
EvrRtxThreadError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) <
(uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {
EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
if (thread != NULL) {
if (!IsThreadPtrValid(thread) || (attr->cb_size != sizeof(os_thread_t))) {
EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
} else {
if (attr->cb_size != 0U) {
EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
if (stack_mem != NULL) {
//lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7]
if ((((uint32_t)stack_mem & 7U) != 0U) || (stack_size == 0U)) {
EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
if (priority == osPriorityNone) {
priority = osPriorityNormal;
} else {
if ((priority < osPriorityIdle) || (priority > osPriorityISR)) {
EvrRtxThreadError(NULL, osRtxErrorInvalidPriority);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
} else {
name = NULL;
attr_bits = 0U;
thread = NULL;
stack_mem = NULL;
stack_size = 0U;
priority = osPriorityNormal;
#ifdef RTX_TZ_CONTEXT
tz_module = 0U;
#endif
}
// Set default privilege if not specified
if ((attr_bits & (osThreadPrivileged | osThreadUnprivileged)) == 0U) {
if ((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U) {
attr_bits |= osThreadPrivileged;
} else {
attr_bits |= osThreadUnprivileged;
}
}
#ifdef RTX_SAFETY_FEATURES
// Check privilege protection
if ((attr_bits & osThreadPrivileged) != 0U) {
if ((osRtxInfo.kernel.protect & osRtxKernelProtectPrivileged) != 0U) {
EvrRtxThreadError(NULL, osRtxErrorInvalidPrivilegedMode);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
#endif
#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)
// Check class to zone mapping
if (!IsClassMappingValid(attr_bits, thread_running)) {
EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
#endif
// Check stack size
if (stack_size != 0U) {
if (((stack_size & 7U) != 0U) || (stack_size < (64U + 8U)) || (stack_size > 0x7FFFFFFFU)) {
EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
}
// Allocate object memory if not provided
if (thread == NULL) {
if (osRtxInfo.mpi.thread != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread);
#ifndef RTX_OBJ_PTR_CHECK
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
thread = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_thread_t), 1U);
#endif
}
#ifdef RTX_OBJ_MEM_USAGE
if (thread != NULL) {
uint32_t used;
osRtxThreadMemUsage.cnt_alloc++;
used = osRtxThreadMemUsage.cnt_alloc - osRtxThreadMemUsage.cnt_free;
if (osRtxThreadMemUsage.max_used < used) {
osRtxThreadMemUsage.max_used = used;
}
}
#endif
flags = osRtxFlagSystemObject;
} else {
flags = 0U;
}
// Allocate stack memory if not provided
if ((thread != NULL) && (stack_mem == NULL)) {
if (stack_size == 0U) {
stack_size = osRtxConfig.thread_stack_size;
if (osRtxInfo.mpi.stack != NULL) {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
stack_mem = osRtxMemoryPoolAlloc(osRtxInfo.mpi.stack);
if (stack_mem != NULL) {
flags |= osRtxThreadFlagDefStack;
}
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);
}
} else {
//lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5]
stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);
}
if (stack_mem == NULL) {
if ((flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
#else
if (osRtxInfo.mpi.thread != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, thread);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxThreadMemUsage.cnt_free++;
#endif
}
thread = NULL;
}
flags |= osRtxFlagSystemMemory;
}
#ifdef RTX_TZ_CONTEXT
// Allocate secure process stack
if ((thread != NULL) && (tz_module != 0U)) {
tz_memory = TZ_AllocModuleContext_S(tz_module);
if (tz_memory == 0U) {
EvrRtxThreadError(NULL, osRtxErrorTZ_AllocContext_S);
if ((flags & osRtxFlagSystemMemory) != 0U) {
if ((flags & osRtxThreadFlagDefStack) != 0U) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);
}
}
if ((flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
#else
if (osRtxInfo.mpi.thread != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, thread);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxThreadMemUsage.cnt_free++;
#endif
}
thread = NULL;
}
} else {
tz_memory = 0U;
}
#endif
if (thread != NULL) {
// Initialize control block
//lint --e{923} --e{9078} "cast between pointers and unsigned int"
//lint --e{9079} --e{9087} "cast between pointers to different object types"
//lint --e{9074} "conversion between a pointer to function and another type"
thread->id = osRtxIdThread;
thread->state = osRtxThreadReady;
thread->flags = flags;
thread->attr = (uint8_t)(attr_bits & ~osRtxAttrClass_Msk);
thread->name = name;
thread->thread_next = NULL;
thread->thread_prev = NULL;
thread->delay_next = NULL;
thread->delay_prev = NULL;
thread->thread_join = NULL;
thread->delay = 0U;
thread->priority = (int8_t)priority;
thread->priority_base = (int8_t)priority;
thread->stack_frame = STACK_FRAME_INIT_VAL;
thread->flags_options = 0U;
thread->wait_flags = 0U;
thread->thread_flags = 0U;
thread->mutex_list = NULL;
thread->stack_mem = stack_mem;
thread->stack_size = stack_size;
thread->sp = (uint32_t)stack_mem + stack_size - 64U;
thread->thread_addr = (uint32_t)func;
#ifdef RTX_TZ_CONTEXT
thread->tz_memory = tz_memory;
#endif
#ifdef RTX_SAFETY_CLASS
if ((attr_bits & osSafetyClass_Valid) != 0U) {
thread->attr |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>
(osSafetyClass_Pos - osRtxAttrClass_Pos));
} else {
// Inherit safety class from the running thread
if (thread_running != NULL) {
thread->attr |= (uint8_t)(thread_running->attr & osRtxAttrClass_Msk);
}
}
#endif
#ifdef RTX_EXECUTION_ZONE
if ((attr_bits & osThreadZone_Valid) != 0U) {
thread->zone = (uint8_t)((attr_bits & osThreadZone_Msk) >> osThreadZone_Pos);
} else {
// Inherit zone from the running thread
if (thread_running != NULL) {
thread->zone = thread_running->zone;
} else {
thread->zone = 0U;
}
}
#endif
#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)
// Update class to zone assignment table
if (ThreadClassTable[thread->zone] == 0U) {
ThreadClassTable[thread->zone] = (uint8_t)(0x80U | (thread->attr >> osRtxAttrClass_Pos));
}
#endif
#ifdef RTX_THREAD_WATCHDOG
thread->wdog_next = NULL;
thread->wdog_tick = 0U;
#endif
// Initialize stack
//lint --e{613} false detection: "Possible use of null pointer"
ptr = (uint32_t *)stack_mem;
ptr[0] = osRtxStackMagicWord;
if ((osRtxConfig.flags & osRtxConfigStackWatermark) != 0U) {
for (n = (stack_size/4U) - (16U + 1U); n != 0U; n--) {
ptr++;
*ptr = osRtxStackFillPattern;
}
}
ptr = (uint32_t *)thread->sp;
for (n = 0U; n != 14U; n++) {
ptr[n] = 0U; // R4..R11, R0..R3, R12, LR
}
ptr[14] = (uint32_t)osThreadEntry; // PC
ptr[15] = xPSR_InitVal(
(bool_t)((attr_bits & osThreadPrivileged) != 0U),
(bool_t)(((uint32_t)func & 1U) != 0U)
); // xPSR
ptr[8] = (uint32_t)argument; // R0
ptr[9] = (uint32_t)func; // R1
// Register post ISR processing function
osRtxInfo.post_process.thread = osRtxThreadPostProcess;
EvrRtxThreadCreated(thread, thread->thread_addr, thread->name);
} else {
EvrRtxThreadError(NULL, (int32_t)osErrorNoMemory);
}
if (thread != NULL) {
osRtxThreadDispatch(thread);
}
return thread;
}
/// Get name of a thread.
/// \note API identical to osThreadGetName
static const char *svcRtxThreadGetName (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetName(thread, NULL);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return NULL;
}
EvrRtxThreadGetName(thread, thread->name);
return thread->name;
}
#ifdef RTX_SAFETY_CLASS
/// Get safety class of a thread.
/// \note API identical to osThreadGetClass
static uint32_t svcRtxThreadGetClass (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetClass(thread, osErrorId);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorId;
}
EvrRtxThreadGetClass(thread, (uint32_t)thread->attr >> osRtxAttrClass_Pos);
return ((uint32_t)thread->attr >> osRtxAttrClass_Pos);
}
#endif
#ifdef RTX_EXECUTION_ZONE
/// Get zone of a thread.
/// \note API identical to osThreadGetZone
static uint32_t svcRtxThreadGetZone (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetZone(thread, osErrorId);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorId;
}
EvrRtxThreadGetZone(thread, thread->zone);
return thread->zone;
}
#endif
/// Return the thread ID of the current running thread.
/// \note API identical to osThreadGetId
static osThreadId_t svcRtxThreadGetId (void) {
os_thread_t *thread;
thread = osRtxThreadGetRunning();
EvrRtxThreadGetId(thread);
return thread;
}
/// Get current thread state of a thread.
/// \note API identical to osThreadGetState
static osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
osThreadState_t state;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetState(thread, osThreadError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osThreadError;
}
state = osRtxThreadState(thread);
EvrRtxThreadGetState(thread, state);
return state;
}
/// Get stack size of a thread.
/// \note API identical to osThreadGetStackSize
static uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetStackSize(thread, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxThreadGetStackSize(thread, thread->stack_size);
return thread->stack_size;
}
/// Get available stack space of a thread based on stack watermark recording during execution.
/// \note API identical to osThreadGetStackSpace
static uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
const uint32_t *stack;
uint32_t space;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetStackSpace(thread, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
// Check if stack watermark is not enabled
if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) {
EvrRtxThreadGetStackSpace(thread, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
//lint -e{9079} "conversion from pointer to void to pointer to other type"
stack = thread->stack_mem;
if (*stack++ == osRtxStackMagicWord) {
for (space = 4U; space < thread->stack_size; space += 4U) {
if (*stack++ != osRtxStackFillPattern) {
break;
}
}
} else {
space = 0U;
}
EvrRtxThreadGetStackSpace(thread, space);
return space;
}
/// Change priority of a thread.
/// \note API identical to osThreadSetPriority
static osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||
(priority < osPriorityIdle) || (priority > osPriorityISR)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object state
if (thread->state == osRtxThreadTerminated) {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
if (thread->priority != (int8_t)priority) {
thread->priority = (int8_t)priority;
thread->priority_base = (int8_t)priority;
EvrRtxThreadPriorityUpdated(thread, priority);
osRtxThreadListSort(thread);
osRtxThreadDispatch(NULL);
}
return osOK;
}
/// Get current priority of a thread.
/// \note API identical to osThreadGetPriority
static osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
osPriority_t priority;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadGetPriority(thread, osPriorityError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osPriorityError;
}
// Check object state
if (thread->state == osRtxThreadTerminated) {
EvrRtxThreadGetPriority(thread, osPriorityError);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osPriorityError;
}
priority = osRtxThreadPriority(thread);
EvrRtxThreadGetPriority(thread, priority);
return priority;
}
/// Pass control to next thread that is in state READY.
/// \note API identical to osThreadYield
static osStatus_t svcRtxThreadYield (void) {
os_thread_t *thread_running;
os_thread_t *thread_ready;
if (osRtxKernelGetState() == osRtxKernelRunning) {
thread_running = osRtxThreadGetRunning();
thread_ready = osRtxInfo.thread.ready.thread_list;
if ((thread_ready != NULL) &&
(thread_ready->priority == thread_running->priority)) {
osRtxThreadListRemove(thread_ready);
osRtxThreadReadyPut(thread_running);
EvrRtxThreadPreempted(thread_running);
osRtxThreadSwitch(thread_ready);
}
}
return osOK;
}
/// Suspend execution of a thread.
/// \note API identical to osThreadSuspend
static osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
osStatus_t status;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object state
switch (thread->state & osRtxThreadStateMask) {
case osRtxThreadRunning:
if ((osRtxKernelGetState() != osRtxKernelRunning) ||
(osRtxInfo.thread.ready.thread_list == NULL)) {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
status = osErrorResource;
} else {
status = osOK;
}
break;
case osRtxThreadReady:
osRtxThreadListRemove(thread);
status = osOK;
break;
case osRtxThreadBlocked:
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
status = osOK;
break;
case osRtxThreadInactive:
case osRtxThreadTerminated:
default:
EvrRtxThreadError(thread, (int32_t)osErrorResource);
status = osErrorResource;
break;
}
if (status == osOK) {
EvrRtxThreadSuspended(thread);
if (thread->state == osRtxThreadRunning) {
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
}
// Update Thread State and put it into Delay list
thread->state = osRtxThreadBlocked;
osRtxThreadDelayInsert(thread, osWaitForever);
}
return status;
}
/// Resume execution of a thread.
/// \note API identical to osThreadResume
static osStatus_t svcRtxThreadResume (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object state
if ((thread->state & osRtxThreadStateMask) != osRtxThreadBlocked) {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
EvrRtxThreadResumed(thread);
// Wakeup Thread
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
osRtxThreadDispatch(thread);
return osOK;
}
/// Wakeup a thread waiting to join.
/// \param[in] thread thread object.
void osRtxThreadJoinWakeup (const os_thread_t *thread) {
if (thread->thread_join != NULL) {
osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE);
EvrRtxThreadJoined(thread->thread_join);
}
if (thread->state == osRtxThreadWaitingJoin) {
thread->thread_next->thread_join = NULL;
}
}
/// Free Thread resources.
/// \param[in] thread thread object.
static void osRtxThreadFree (os_thread_t *thread) {
osRtxThreadBeforeFree(thread);
// Mark object as inactive and invalid
thread->state = osRtxThreadInactive;
thread->id = osRtxIdInvalid;
#ifdef RTX_TZ_CONTEXT
// Free secure process stack
if (thread->tz_memory != 0U) {
(void)TZ_FreeModuleContext_S(thread->tz_memory);
}
#endif
// Free stack memory
if ((thread->flags & osRtxFlagSystemMemory) != 0U) {
if ((thread->flags & osRtxThreadFlagDefStack) != 0U) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);
}
}
// Free object memory
if ((thread->flags & osRtxFlagSystemObject) != 0U) {
#ifdef RTX_OBJ_PTR_CHECK
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
#else
if (osRtxInfo.mpi.thread != NULL) {
(void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);
} else {
(void)osRtxMemoryFree(osRtxInfo.mem.common, thread);
}
#endif
#ifdef RTX_OBJ_MEM_USAGE
osRtxThreadMemUsage.cnt_free++;
#endif
}
}
/// Destroy a Thread.
/// \param[in] thread thread object.
void osRtxThreadDestroy (os_thread_t *thread) {
if ((thread->attr & osThreadJoinable) == 0U) {
osRtxThreadFree(thread);
} else {
// Update Thread State and put it into Terminate Thread list
thread->state = osRtxThreadTerminated;
thread->thread_prev = NULL;
thread->thread_next = osRtxInfo.thread.terminate_list;
if (osRtxInfo.thread.terminate_list != NULL) {
osRtxInfo.thread.terminate_list->thread_prev = thread;
}
osRtxInfo.thread.terminate_list = thread;
}
EvrRtxThreadDestroyed(thread);
}
/// Detach a thread (thread storage can be reclaimed when thread terminates).
/// \note API identical to osThreadDetach
static osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object attributes
if ((thread->attr & osThreadJoinable) == 0U) {
EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
if (thread->state == osRtxThreadTerminated) {
osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);
osRtxThreadFree(thread);
} else {
thread->attr &= ~osThreadJoinable;
}
EvrRtxThreadDetached(thread);
return osOK;
}
/// Wait for specified thread to terminate.
/// \note API identical to osThreadJoin
static osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
os_thread_t *thread_running;
osStatus_t status;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object attributes
if ((thread->attr & osThreadJoinable) == 0U) {
EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
// Check object state
if (thread->state == osRtxThreadRunning) {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
if (thread->state == osRtxThreadTerminated) {
osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);
osRtxThreadFree(thread);
EvrRtxThreadJoined(thread);
status = osOK;
} else {
// Suspend current Thread
if (osRtxThreadWaitEnter(osRtxThreadWaitingJoin, osWaitForever)) {
thread_running = osRtxThreadGetRunning();
thread_running->thread_next = thread;
thread->thread_join = thread_running;
thread->attr &= ~osThreadJoinable;
EvrRtxThreadJoinPending(thread);
} else {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
}
status = osErrorResource;
}
return status;
}
/// Terminate execution of current running thread.
/// \note API identical to osThreadExit
static void svcRtxThreadExit (void) {
os_thread_t *thread;
// Check if switch to next Ready Thread is possible
if ((osRtxKernelGetState() != osRtxKernelRunning) ||
(osRtxInfo.thread.ready.thread_list == NULL)) {
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return;
}
// Get running thread
thread = osRtxThreadGetRunning();
#ifdef RTX_THREAD_WATCHDOG
// Remove Thread from the Watchdog list
osRtxThreadWatchdogRemove(thread);
#endif
// Release owned Mutexes
osRtxMutexOwnerRelease(thread->mutex_list);
// Wakeup Thread waiting to Join
osRtxThreadJoinWakeup(thread);
// Switch to next Ready Thread
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
// Update Stack Pointer
thread->sp = __get_PSP();
#ifdef RTX_STACK_CHECK
// Check Stack usage
if (!osRtxThreadStackCheck(thread)) {
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
(void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);
}
#endif
// Mark running thread as deleted
osRtxThreadSetRunning(NULL);
// Destroy Thread
osRtxThreadDestroy(thread);
}
/// Terminate execution of a thread.
/// \note API identical to osThreadTerminate
static osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
osStatus_t status;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {
EvrRtxThreadError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
#endif
// Check object state
switch (thread->state & osRtxThreadStateMask) {
case osRtxThreadRunning:
if ((osRtxKernelGetState() != osRtxKernelRunning) ||
(osRtxInfo.thread.ready.thread_list == NULL)) {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
status = osErrorResource;
} else {
status = osOK;
}
break;
case osRtxThreadReady:
osRtxThreadListRemove(thread);
status = osOK;
break;
case osRtxThreadBlocked:
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
status = osOK;
break;
case osRtxThreadInactive:
case osRtxThreadTerminated:
default:
EvrRtxThreadError(thread, (int32_t)osErrorResource);
status = osErrorResource;
break;
}
if (status == osOK) {
#ifdef RTX_THREAD_WATCHDOG
// Remove Thread from the Watchdog list
osRtxThreadWatchdogRemove(thread);
#endif
// Release owned Mutexes
osRtxMutexOwnerRelease(thread->mutex_list);
// Wakeup Thread waiting to Join
osRtxThreadJoinWakeup(thread);
// Switch to next Ready Thread when terminating running Thread
if (thread->state == osRtxThreadRunning) {
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
// Update Stack Pointer
thread->sp = __get_PSP();
#ifdef RTX_STACK_CHECK
// Check Stack usage
if (!osRtxThreadStackCheck(thread)) {
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
(void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);
}
#endif
// Mark running thread as deleted
osRtxThreadSetRunning(NULL);
} else {
osRtxThreadDispatch(NULL);
}
// Destroy Thread
osRtxThreadDestroy(thread);
}
return status;
}
#ifdef RTX_THREAD_WATCHDOG
/// Feed watchdog of the current running thread.
/// \note API identical to osThreadFeedWatchdog
static osStatus_t svcRtxThreadFeedWatchdog (uint32_t ticks) {
os_thread_t *thread;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
osRtxThreadWatchdogRemove(thread);
osRtxThreadWatchdogInsert(thread, ticks);
EvrRtxThreadFeedWatchdogDone();
return osOK;
}
#endif
#ifdef RTX_SAFETY_FEATURES
/// Protect the creation of privileged threads.
/// \note API identical to osThreadProtectPrivileged
static osStatus_t svcRtxThreadProtectPrivileged (void) {
// Check that Kernel is initialized
if (osRtxKernelGetState() == osRtxKernelInactive) {
EvrRtxThreadError(NULL, osRtxErrorKernelNotReady);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osError;
}
osRtxInfo.kernel.protect |= osRtxKernelProtectPrivileged;
EvrRtxThreadPrivilegedProtected();
return osOK;
}
#endif
#ifdef RTX_SAFETY_CLASS
/// Suspend execution of threads for specified safety classes.
/// \note API identical to osThreadSuspendClass
static osStatus_t svcRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode) {
os_thread_t *thread;
os_thread_t *thread_next;
// Check parameters
if (safety_class > 0x0FU) {
EvrRtxThreadError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Check running thread safety class (when called from thread)
thread = osRtxThreadGetRunning();
if ((thread != NULL) && IsSVCallIrq()) {
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
(((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {
EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
}
// Threads in Wait List
thread = osRtxInfo.thread.wait_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
thread->state = osRtxThreadBlocked;
EvrRtxThreadSuspended(thread);
}
thread = thread_next;
}
// Threads in Delay List
thread = osRtxInfo.thread.delay_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
thread->state = osRtxThreadBlocked;
osRtxThreadDelayInsert(thread, osWaitForever);
EvrRtxThreadSuspended(thread);
}
thread = thread_next;
}
// Threads in Ready List
thread = osRtxInfo.thread.ready.thread_list;
while (thread != NULL) {
thread_next = thread->thread_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
osRtxThreadListRemove(thread);
thread->state = osRtxThreadBlocked;
osRtxThreadDelayInsert(thread, osWaitForever);
EvrRtxThreadSuspended(thread);
}
thread = thread_next;
}
// Running Thread
thread = osRtxThreadGetRunning();
if ((thread != NULL) &&
((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)))) {
if ((osRtxKernelGetState() == osRtxKernelRunning) &&
(osRtxInfo.thread.ready.thread_list != NULL)) {
thread->state = osRtxThreadBlocked;
osRtxThreadDelayInsert(thread, osWaitForever);
EvrRtxThreadSuspended(thread);
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
} else {
EvrRtxThreadError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
}
return osOK;
}
/// Resume execution of threads for specified safety classes.
/// \note API identical to osThreadResumeClass
static osStatus_t svcRtxThreadResumeClass (uint32_t safety_class, uint32_t mode) {
os_thread_t *thread;
os_thread_t *thread_next;
// Check parameters
if (safety_class > 0x0FU) {
EvrRtxThreadError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Check running thread safety class (when called from thread)
thread = osRtxThreadGetRunning();
if ((thread != NULL) && IsSVCallIrq()) {
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
(((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {
EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorSafetyClass;
}
}
// Threads in Wait List
thread = osRtxInfo.thread.wait_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
// Wakeup Thread
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
osRtxThreadReadyPut(thread);
EvrRtxThreadResumed(thread);
}
thread = thread_next;
}
// Threads in Delay List
thread = osRtxInfo.thread.delay_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if ((((mode & osSafetyWithSameClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||
(((mode & osSafetyWithLowerClass) != 0U) &&
((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class))) {
// Wakeup Thread
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
osRtxThreadReadyPut(thread);
EvrRtxThreadResumed(thread);
}
thread = thread_next;
}
osRtxThreadDispatch(NULL);
return osOK;
}
#endif
#ifdef RTX_EXECUTION_ZONE
/// Terminate execution of threads assigned to a specified MPU protected zone.
/// \note API identical to osThreadTerminateZone
static osStatus_t svcRtxThreadTerminateZone (uint32_t zone) {
os_thread_t *thread;
os_thread_t *thread_next;
#ifdef RTX_THREAD_WATCHDOG
// Check Watchdog Alarm Flag
if (WatchdogAlarmFlag != 0U) {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorISR;
}
#endif
// Check parameters
if (zone > 0x3FU) {
EvrRtxThreadError(NULL, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorParameter;
}
// Threads in Wait List
thread = osRtxInfo.thread.wait_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if (thread->zone == zone) {
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Threads in Delay List
thread = osRtxInfo.thread.delay_list;
while (thread != NULL) {
thread_next = thread->delay_next;
if (thread->zone == zone) {
osRtxThreadListRemove(thread);
osRtxThreadDelayRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Threads in Ready List
thread = osRtxInfo.thread.ready.thread_list;
while (thread != NULL) {
thread_next = thread->thread_next;
if (thread->zone == zone) {
osRtxThreadListRemove(thread);
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
osRtxThreadDestroy(thread);
}
thread = thread_next;
}
// Running Thread
thread = osRtxThreadGetRunning();
if ((thread != NULL) && (thread->zone == zone)) {
if ((osRtxKernelGetState() != osRtxKernelRunning) ||
(osRtxInfo.thread.ready.thread_list == NULL)) {
osRtxThreadDispatch(NULL);
EvrRtxThreadError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return osErrorResource;
}
#ifdef RTX_THREAD_WATCHDOG
osRtxThreadWatchdogRemove(thread);
#endif
osRtxMutexOwnerRelease(thread->mutex_list);
osRtxThreadJoinWakeup(thread);
// Switch to next Ready Thread
osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));
// Update Stack Pointer
thread->sp = __get_PSP();
#ifdef RTX_STACK_CHECK
// Check Stack usage
if (!osRtxThreadStackCheck(thread)) {
osRtxThreadSetRunning(osRtxInfo.thread.run.next);
(void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);
}
#endif
// Mark running thread as deleted
osRtxThreadSetRunning(NULL);
// Destroy Thread
osRtxThreadDestroy(thread);
} else {
osRtxThreadDispatch(NULL);
}
return osOK;
}
#endif
/// Get number of active threads.
/// \note API identical to osThreadGetCount
static uint32_t svcRtxThreadGetCount (void) {
const os_thread_t *thread;
uint32_t count;
// Running Thread
count = 1U;
// Ready List
for (thread = osRtxInfo.thread.ready.thread_list;
thread != NULL; thread = thread->thread_next) {
count++;
}
// Delay List
for (thread = osRtxInfo.thread.delay_list;
thread != NULL; thread = thread->delay_next) {
count++;
}
// Wait List
for (thread = osRtxInfo.thread.wait_list;
thread != NULL; thread = thread->delay_next) {
count++;
}
EvrRtxThreadGetCount(count);
return count;
}
/// Enumerate active threads.
/// \note API identical to osThreadEnumerate
static uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
os_thread_t *thread;
uint32_t count;
// Check parameters
if ((thread_array == NULL) || (array_items == 0U)) {
EvrRtxThreadEnumerate(thread_array, array_items, 0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
// Running Thread
*thread_array = osRtxThreadGetRunning();
thread_array++;
count = 1U;
// Ready List
for (thread = osRtxInfo.thread.ready.thread_list;
(thread != NULL) && (count < array_items); thread = thread->thread_next) {
*thread_array = thread;
thread_array++;
count++;
}
// Delay List
for (thread = osRtxInfo.thread.delay_list;
(thread != NULL) && (count < array_items); thread = thread->delay_next) {
*thread_array = thread;
thread_array++;
count++;
}
// Wait List
for (thread = osRtxInfo.thread.wait_list;
(thread != NULL) && (count < array_items); thread = thread->delay_next) {
*thread_array = thread;
thread_array++;
count++;
}
EvrRtxThreadEnumerate(thread_array - count, array_items, count);
return count;
}
/// Set the specified Thread Flags of a thread.
/// \note API identical to osThreadFlagsSet
static uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
os_thread_t *thread = osRtxThreadId(thread_id);
#ifdef RTX_SAFETY_CLASS
const os_thread_t *thread_running;
#endif
uint32_t thread_flags;
uint32_t thread_flags0;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||
((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Check object state
if (thread->state == osRtxThreadTerminated) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorResource);
}
#ifdef RTX_SAFETY_CLASS
// Check running thread safety class
thread_running = osRtxThreadGetRunning();
if ((thread_running != NULL) &&
((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorSafetyClass);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorSafetyClass);
}
#endif
// Set Thread Flags
thread_flags = ThreadFlagsSet(thread, flags);
// Check if Thread is waiting for Thread Flags
if (thread->state == osRtxThreadWaitingThreadFlags) {
thread_flags0 = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);
if (thread_flags0 != 0U) {
if ((thread->flags_options & osFlagsNoClear) == 0U) {
thread_flags = thread_flags0 & ~thread->wait_flags;
} else {
thread_flags = thread_flags0;
}
osRtxThreadWaitExit(thread, thread_flags0, TRUE);
EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags0, thread);
}
}
EvrRtxThreadFlagsSetDone(thread, thread_flags);
return thread_flags;
}
/// Clear the specified Thread Flags of current running thread.
/// \note API identical to osThreadFlagsClear
static uint32_t svcRtxThreadFlagsClear (uint32_t flags) {
os_thread_t *thread;
uint32_t thread_flags;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osError);
}
// Check parameters
if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Clear Thread Flags
thread_flags = ThreadFlagsClear(thread, flags);
EvrRtxThreadFlagsClearDone(thread_flags);
return thread_flags;
}
/// Get the current Thread Flags of current running thread.
/// \note API identical to osThreadFlagsGet
static uint32_t svcRtxThreadFlagsGet (void) {
const os_thread_t *thread;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxThreadFlagsGet(0U);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return 0U;
}
EvrRtxThreadFlagsGet(thread->thread_flags);
return thread->thread_flags;
}
/// Wait for one or more Thread Flags of the current running thread to become signaled.
/// \note API identical to osThreadFlagsWait
static uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
os_thread_t *thread;
uint32_t thread_flags;
// Check running thread
thread = osRtxThreadGetRunning();
if (thread == NULL) {
EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osError);
}
// Check parameters
if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Check Thread Flags
thread_flags = ThreadFlagsCheck(thread, flags, options);
if (thread_flags != 0U) {
EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread);
} else {
// Check if timeout is specified
if (timeout != 0U) {
// Store waiting flags and options
EvrRtxThreadFlagsWaitPending(flags, options, timeout);
thread->wait_flags = flags;
thread->flags_options = (uint8_t)options;
// Suspend current Thread
if (!osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout)) {
EvrRtxThreadFlagsWaitTimeout(thread);
}
thread_flags = (uint32_t)osErrorTimeout;
} else {
EvrRtxThreadFlagsWaitNotCompleted(flags, options);
thread_flags = (uint32_t)osErrorResource;
}
}
return thread_flags;
}
// Service Calls definitions
//lint ++flb "Library Begin" [MISRA Note 11]
SVC0_3 (ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *)
SVC0_1 (ThreadGetName, const char *, osThreadId_t)
#ifdef RTX_SAFETY_CLASS
SVC0_1 (ThreadGetClass, uint32_t, osThreadId_t)
#endif
#ifdef RTX_EXECUTION_ZONE
SVC0_1 (ThreadGetZone, uint32_t, osThreadId_t)
#endif
SVC0_0 (ThreadGetId, osThreadId_t)
SVC0_1 (ThreadGetState, osThreadState_t, osThreadId_t)
SVC0_1 (ThreadGetStackSize, uint32_t, osThreadId_t)
SVC0_1 (ThreadGetStackSpace, uint32_t, osThreadId_t)
SVC0_2 (ThreadSetPriority, osStatus_t, osThreadId_t, osPriority_t)
SVC0_1 (ThreadGetPriority, osPriority_t, osThreadId_t)
SVC0_0 (ThreadYield, osStatus_t)
SVC0_1 (ThreadSuspend, osStatus_t, osThreadId_t)
SVC0_1 (ThreadResume, osStatus_t, osThreadId_t)
SVC0_1 (ThreadDetach, osStatus_t, osThreadId_t)
SVC0_1 (ThreadJoin, osStatus_t, osThreadId_t)
SVC0_0N(ThreadExit, void)
SVC0_1 (ThreadTerminate, osStatus_t, osThreadId_t)
#ifdef RTX_THREAD_WATCHDOG
SVC0_1 (ThreadFeedWatchdog, osStatus_t, uint32_t)
#endif
#ifdef RTX_SAFETY_FEATURES
SVC0_0 (ThreadProtectPrivileged, osStatus_t)
#endif
#ifdef RTX_SAFETY_CLASS
SVC0_2 (ThreadSuspendClass, osStatus_t, uint32_t, uint32_t)
SVC0_2 (ThreadResumeClass, osStatus_t, uint32_t, uint32_t)
#endif
SVC0_0 (ThreadGetCount, uint32_t)
SVC0_2 (ThreadEnumerate, uint32_t, osThreadId_t *, uint32_t)
SVC0_2 (ThreadFlagsSet, uint32_t, osThreadId_t, uint32_t)
SVC0_1 (ThreadFlagsClear, uint32_t, uint32_t)
SVC0_0 (ThreadFlagsGet, uint32_t)
SVC0_3 (ThreadFlagsWait, uint32_t, uint32_t, uint32_t, uint32_t)
//lint --flb "Library End"
// ==== ISR Calls ====
/// Set the specified Thread Flags of a thread.
/// \note API identical to osThreadFlagsSet
__STATIC_INLINE
uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
os_thread_t *thread = osRtxThreadId(thread_id);
uint32_t thread_flags;
// Check parameters
if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||
((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorParameter);
}
// Check object state
if (thread->state == osRtxThreadTerminated) {
EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource);
//lint -e{904} "Return statement before end of function" [MISRA Note 1]
return ((uint32_t)osErrorResource);
}
// Set Thread Flags
thread_flags = ThreadFlagsSet(thread, flags);
// Register post ISR processing
osRtxPostProcess(osRtxObject(thread));
EvrRtxThreadFlagsSetDone(thread, thread_flags);
return thread_flags;
}
// ==== Library functions ====
/// RTOS Thread Before Free Hook.
//lint -esym(759,osRtxThreadBeforeFree) "Prototype in header"
//lint -esym(765,osRtxThreadBeforeFree) "Global scope (can be overridden)"
__WEAK void osRtxThreadBeforeFree (os_thread_t *thread) {
(void)thread;
}
/// Thread startup (Idle and Timer Thread).
/// \return true - success, false - failure.
bool_t osRtxThreadStartup (void) {
bool_t ret = FALSE;
// Create Idle Thread
osRtxInfo.thread.idle = osRtxThreadId(
svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr)
);
// Create Timer Thread
if (osRtxConfig.timer_setup != NULL) {
if (osRtxConfig.timer_setup() == 0) {
osRtxInfo.timer.thread = osRtxThreadId(
svcRtxThreadNew(osRtxConfig.timer_thread, osRtxInfo.timer.mq, osRtxConfig.timer_thread_attr)
);
if (osRtxInfo.timer.thread != NULL) {
ret = TRUE;
}
}
} else {
ret = TRUE;
}
return ret;
}
// ==== Public API ====
/// Create a thread and add it to Active Threads.
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
osThreadId_t thread_id;
EvrRtxThreadNew(func, argument, attr);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
thread_id = NULL;
} else {
thread_id = __svcThreadNew(func, argument, attr);
}
return thread_id;
}
/// Get name of a thread.
const char *osThreadGetName (osThreadId_t thread_id) {
const char *name;
if (IsException() || IsIrqMasked()) {
name = svcRtxThreadGetName(thread_id);
} else {
name = __svcThreadGetName(thread_id);
}
return name;
}
#ifdef RTX_SAFETY_CLASS
/// Get safety class of a thread.
uint32_t osThreadGetClass (osThreadId_t thread_id) {
uint32_t safety_class;
if (IsException() || IsIrqMasked()) {
safety_class = svcRtxThreadGetClass(thread_id);
} else {
safety_class = __svcThreadGetClass(thread_id);
}
return safety_class;
}
#endif
#ifdef RTX_EXECUTION_ZONE
/// Get zone of a thread.
uint32_t osThreadGetZone (osThreadId_t thread_id) {
uint32_t zone;
if (IsException() || IsIrqMasked()) {
zone = svcRtxThreadGetZone(thread_id);
} else {
zone = __svcThreadGetZone(thread_id);
}
return zone;
}
#endif
/// Return the thread ID of the current running thread.
osThreadId_t osThreadGetId (void) {
osThreadId_t thread_id;
if (IsException() || IsIrqMasked()) {
thread_id = svcRtxThreadGetId();
} else {
thread_id = __svcThreadGetId();
}
return thread_id;
}
/// Get current thread state of a thread.
osThreadState_t osThreadGetState (osThreadId_t thread_id) {
osThreadState_t state;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadGetState(thread_id, osThreadError);
state = osThreadError;
} else {
state = __svcThreadGetState(thread_id);
}
return state;
}
/// Get stack size of a thread.
uint32_t osThreadGetStackSize (osThreadId_t thread_id) {
uint32_t stack_size;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadGetStackSize(thread_id, 0U);
stack_size = 0U;
} else {
stack_size = __svcThreadGetStackSize(thread_id);
}
return stack_size;
}
/// Get available stack space of a thread based on stack watermark recording during execution.
uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
uint32_t stack_space;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadGetStackSpace(thread_id, 0U);
stack_space = 0U;
} else {
stack_space = __svcThreadGetStackSpace(thread_id);
}
return stack_space;
}
/// Change priority of a thread.
osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
osStatus_t status;
EvrRtxThreadSetPriority(thread_id, priority);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadSetPriority(thread_id, priority);
}
return status;
}
/// Get current priority of a thread.
osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
osPriority_t priority;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadGetPriority(thread_id, osPriorityError);
priority = osPriorityError;
} else {
priority = __svcThreadGetPriority(thread_id);
}
return priority;
}
/// Pass control to next thread that is in state READY.
osStatus_t osThreadYield (void) {
osStatus_t status;
EvrRtxThreadYield();
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadYield();
}
return status;
}
/// Suspend execution of a thread.
osStatus_t osThreadSuspend (osThreadId_t thread_id) {
osStatus_t status;
EvrRtxThreadSuspend(thread_id);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadSuspend(thread_id);
}
return status;
}
/// Resume execution of a thread.
osStatus_t osThreadResume (osThreadId_t thread_id) {
osStatus_t status;
EvrRtxThreadResume(thread_id);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadResume(thread_id);
}
return status;
}
/// Detach a thread (thread storage can be reclaimed when thread terminates).
osStatus_t osThreadDetach (osThreadId_t thread_id) {
osStatus_t status;
EvrRtxThreadDetach(thread_id);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadDetach(thread_id);
}
return status;
}
/// Wait for specified thread to terminate.
osStatus_t osThreadJoin (osThreadId_t thread_id) {
osStatus_t status;
EvrRtxThreadJoin(thread_id);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadJoin(thread_id);
}
return status;
}
/// Terminate execution of current running thread.
__NO_RETURN void osThreadExit (void) {
EvrRtxThreadExit();
__svcThreadExit();
EvrRtxThreadError(NULL, (int32_t)osError);
for (;;) {}
}
/// Terminate execution of a thread.
osStatus_t osThreadTerminate (osThreadId_t thread_id) {
osStatus_t status;
EvrRtxThreadTerminate(thread_id);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadTerminate(thread_id);
}
return status;
}
#ifdef RTX_THREAD_WATCHDOG
/// Feed watchdog of the current running thread.
osStatus_t osThreadFeedWatchdog (uint32_t ticks) {
osStatus_t status;
EvrRtxThreadFeedWatchdog(ticks);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadFeedWatchdog(ticks);
}
return status;
}
#endif
#ifdef RTX_SAFETY_FEATURES
/// Protect the creation of privileged threads.
osStatus_t osThreadProtectPrivileged (void) {
osStatus_t status;
EvrRtxThreadProtectPrivileged();
if (IsException() || IsIrqMasked()) {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
} else {
status = __svcThreadProtectPrivileged();
}
return status;
}
#endif
#ifdef RTX_SAFETY_CLASS
/// Suspend execution of threads for specified safety classes.
osStatus_t osThreadSuspendClass (uint32_t safety_class, uint32_t mode) {
osStatus_t status;
EvrRtxThreadSuspendClass(safety_class, mode);
if (IsException() || IsIrqMasked()) {
if (IsTickIrq(osRtxInfo.tick_irqn)) {
status = svcRtxThreadSuspendClass(safety_class, mode);
} else {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
}
} else {
status = __svcThreadSuspendClass(safety_class, mode);
}
return status;
}
/// Resume execution of threads for specified safety classes.
osStatus_t osThreadResumeClass (uint32_t safety_class, uint32_t mode) {
osStatus_t status;
EvrRtxThreadResumeClass(safety_class, mode);
if (IsException() || IsIrqMasked()) {
if (IsTickIrq(osRtxInfo.tick_irqn)) {
status = svcRtxThreadResumeClass(safety_class, mode);
} else {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
}
} else {
status = __svcThreadResumeClass(safety_class, mode);
}
return status;
}
#endif
#ifdef RTX_EXECUTION_ZONE
/// Terminate execution of threads assigned to a specified MPU protected zone.
osStatus_t osThreadTerminateZone (uint32_t zone) {
osStatus_t status;
EvrRtxThreadTerminateZone(zone);
if (IsException() || IsIrqMasked()) {
if (IsFault() || IsSVCallIrq() || IsPendSvIrq() || IsTickIrq(osRtxInfo.tick_irqn)) {
status = svcRtxThreadTerminateZone(zone);
} else {
EvrRtxThreadError(NULL, (int32_t)osErrorISR);
status = osErrorISR;
}
} else {
EvrRtxThreadError(osRtxThreadGetRunning(), (int32_t)osError);
status = osError;
}
return status;
}
#endif
/// Get number of active threads.
uint32_t osThreadGetCount (void) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadGetCount(0U);
count = 0U;
} else {
count = __svcThreadGetCount();
}
return count;
}
/// Enumerate active threads.
uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
uint32_t count;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadEnumerate(thread_array, array_items, 0U);
count = 0U;
} else {
count = __svcThreadEnumerate(thread_array, array_items);
}
return count;
}
/// Set the specified Thread Flags of a thread.
uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
uint32_t thread_flags;
EvrRtxThreadFlagsSet(thread_id, flags);
if (IsException() || IsIrqMasked()) {
thread_flags = isrRtxThreadFlagsSet(thread_id, flags);
} else {
thread_flags = __svcThreadFlagsSet(thread_id, flags);
}
return thread_flags;
}
/// Clear the specified Thread Flags of current running thread.
uint32_t osThreadFlagsClear (uint32_t flags) {
uint32_t thread_flags;
EvrRtxThreadFlagsClear(flags);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR);
thread_flags = (uint32_t)osErrorISR;
} else {
thread_flags = __svcThreadFlagsClear(flags);
}
return thread_flags;
}
/// Get the current Thread Flags of current running thread.
uint32_t osThreadFlagsGet (void) {
uint32_t thread_flags;
if (IsException() || IsIrqMasked()) {
EvrRtxThreadFlagsGet(0U);
thread_flags = 0U;
} else {
thread_flags = __svcThreadFlagsGet();
}
return thread_flags;
}
/// Wait for one or more Thread Flags of the current running thread to become signaled.
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
uint32_t thread_flags;
EvrRtxThreadFlagsWait(flags, options, timeout);
if (IsException() || IsIrqMasked()) {
EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR);
thread_flags = (uint32_t)osErrorISR;
} else {
thread_flags = __svcThreadFlagsWait(flags, options, timeout);
}
return thread_flags;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/rtx_thread.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 23,965 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv6-M Exception handlers
; *
; * your_sha256_hash-------------
; */
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
ENDIF
IF :DEF:RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
ENDIF
IF :DEF:RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
ENDIF
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP ; Branch if return stack is MSP
MRS R0,PSP ; Get PSP
SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
IF :DEF:RTX_SVC_PTR_CHECK
SUBS R1,R7,#0x01 ; Clear T-bit of function address
LSLS R2,R1,#29 ; Check if 8-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R7 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R2,R3} ; Restore SP and EXC_RETURN
MOV LR,R3 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
ENDIF
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
CMP R1,#0
BEQ SVC_ContextRestore ; Branch if running thread is deleted
SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STR R0,[R1,#TCB_SP_OFS] ; Store SP
IF :DEF:RTX_STACK_CHECK
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CMP R0,#0
BNE SVC_ContextSaveRegs ; Branch when stack check is ok
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
B SVC_ContextRestore ; Branch to context restore handling
SVC_ContextSaveRegs
LDR R0,[R1,#TCB_SP_OFS] ; Load SP
ENDIF
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4
IF :DEF:RTX_EXECUTION_ZONE
MOVS R3,#TCB_ZONE_OFS ; Get TCB.zone offset
LDRB R0,[R2,R3] ; Load osRtxInfo.thread.run.next: zone
CMP R1,#0
BEQ SVC_ZoneSetup ; Branch if running thread is deleted
LDRB R1,[R1,R3] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
BEQ SVC_ContextRestore_N ; Branch if zone has not changed
SVC_ZoneSetup
BL osZoneSetup_Callback ; Setup zone for next thread
ENDIF
SVC_ContextRestore_N
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler
SVC_MSP
MRS R0,MSP ; Get MSP
B SVC_Number
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] ; Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
BX R3 ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
ALIGN
ENDP
IF :DEF:RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
B SVC_Context ; Branch to context handling
ALIGN
ENDP
ENDIF
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,426 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv7-A Exception handlers
; *
; * your_sha256_hash-------------
; */
MODE_FIQ EQU 0x11
MODE_IRQ EQU 0x12
MODE_SVC EQU 0x13
MODE_ABT EQU 0x17
MODE_UND EQU 0x1B
CPSR_BIT_T EQU 0x20
K_STATE_RUNNING EQU 2 ; osKernelState_t::osKernelRunning
I_K_STATE_OFS EQU 8 ; osRtxInfo.kernel.state offset
I_TICK_IRQN_OFS EQU 16 ; osRtxInfo.tick_irqn offset
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_FRAME EQU 34 ; osRtxThread_t.stack_frame offset
TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset
TCB_ZONE_OFS EQU 68 ; osRtxThread_t.zone offset
PRESERVE8
ARM
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.data|, DATA, READWRITE
EXPORT SVC_Active
EXPORT IRQ_PendSV
IRQ_NestLevel DCD 0 ; IRQ nesting level counter
SVC_Active DCB 0 ; SVC Handler Active
IRQ_PendSV DCB 0 ; Pending SVC flag
AREA |.text|, CODE, READONLY
Undef_Handler\
PROC
EXPORT Undef_Handler
IMPORT CUndefHandler
SRSFD SP!, #MODE_UND
PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
MRS R0, SPSR
TST R0, #CPSR_BIT_T ; Check mode
MOVEQ R1, #4 ; R1 = 4 ARM mode
MOVNE R1, #2 ; R1 = 2 Thumb mode
SUB R0, LR, R1
LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
BEQ Undef_Cont
; Thumb instruction
; Determine if it is a 32-bit Thumb instruction
LDRH R0, [R0]
MOV R2, #0x1C
CMP R2, R0, LSR #11
BHS Undef_Cont ; 16-bit Thumb instruction
; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
Undef_Cont
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)
BL CUndefHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
SUB LR, LR, R0
LDR R0, [SP, #28] ; Restore stacked SPSR
MSR SPSR_CXSF, R0
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stacked APCS registers
ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
MOVS PC, LR
ENDP
PAbt_Handler\
PROC
EXPORT PAbt_Handler
IMPORT CPAbtHandler
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 1 ; IFSR
MRC p15, 0, R1, c6, c0, 2 ; IFAR
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CPAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stack APCS registers
RFEFD SP! ; Return from exception
ENDP
DAbt_Handler\
PROC
EXPORT DAbt_Handler
IMPORT CDAbtHandler
SUB LR, LR, #8 ; Pre-adjust LR
SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 0 ; DFSR
MRC p15, 0, R1, c6, c0, 0 ; DFAR
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CDAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
ENDP
IRQ_Handler\
PROC
EXPORT IRQ_Handler
IMPORT IRQ_GetActiveIRQ
IMPORT IRQ_GetHandler
IMPORT IRQ_EndOfInterrupt
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
CPS #MODE_SVC ; Change to SVC mode
PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
ADD R1, R1, #1 ; Increment IRQ nesting level
STR R1, [R0]
MOV R3, SP ; Move SP into R3
AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
SUB SP, SP, R3 ; Adjust stack
PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
MOV R4, R0 ; Move interrupt ID to R4
BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
CMP R0, #0 ; Check if handler address is 0
BEQ IRQ_End ; If 0, end interrupt and return
CPSIE i ; Re-enable interrupts
BLX R0 ; Call IRQ handler
CPSID i ; Disable interrupts
IRQ_End
MOV R0, R4 ; Move interrupt ID to R0
BLX IRQ_EndOfInterrupt ; Signal end of interrupt
POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
ADD SP, SP, R3 ; Unadjust stack
BL osRtxContextSwitch ; Continue in context switcher
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
SUBS R1, R1, #1 ; Decrement IRQ nesting level
STR R1, [R0]
CLREX ; Clear exclusive monitor for interrupted code
POP {R0-R3, R12, LR} ; Restore stacked APCS registers
RFEFD SP! ; Return from IRQ handler
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler
IMPORT IRQ_Disable
IMPORT IRQ_Enable
IMPORT osRtxUserSVC
IMPORT osRtxInfo
SRSFD SP!, #MODE_SVC ; Store SPSR_svc and LR_svc onto SVC stack
PUSH {R12, LR}
MRS R12, SPSR ; Load SPSR
TST R12, #CPSR_BIT_T ; Thumb bit set?
LDRHNE R12, [LR,#-2] ; Thumb: load halfword
BICNE R12, R12, #0xFF00 ; extract SVC number
LDREQ R12, [LR,#-4] ; ARM: load word
BICEQ R12, R12, #0xFF000000 ; extract SVC number
CMP R12, #0 ; Compare SVC number
BNE SVC_User ; Branch if User SVC
PUSH {R0-R3} ; Push arguments to stack
LDR R0, =SVC_Active
MOV R1, #1
STRB R1, [R0] ; Set SVC Handler Active
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
ADD R1, R1, #1 ; Increment IRQ nesting level
STR R1, [R0]
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
BLT SVC_FuncCall ; Continue if kernel is not running
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Disable ; Disable OS Tick interrupt
SVC_FuncCall
LDM SP, {R0-R3, R12} ; Reload R0-R3 and R12 from stack
CPSIE i ; Re-enable interrupts
BLX R12 ; Branch to SVC function
CPSID i ; Disable interrupts
STR R0, [SP] ; Store function return value
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
BLT SVC_ContextCheck ; Continue if kernel is not running
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Enable ; Enable OS Tick interrupt
SVC_ContextCheck
BL osRtxContextSwitch ; Continue in context switcher
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
SUB R1, R1, #1 ; Decrement IRQ nesting level
STR R1, [R0]
LDR R0, =SVC_Active
MOV R1, #0
STRB R1, [R0] ; Clear SVC Handler Active
CLREX ; Clear exclusive monitor
POP {R0-R3, R12, LR} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
SVC_User
PUSH {R4, R5}
LDR R5,=osRtxUserSVC ; Load address of SVC table
LDR R4,[R5] ; Load SVC maximum number
CMP R12,R4 ; Check SVC number range
BHI SVC_Done ; Branch if out of range
LDR R12,[R5,R12,LSL #2] ; Load SVC Function Address
BLX R12 ; Call SVC Function
SVC_Done
CLREX ; Clear exclusive monitor
POP {R4, R5, R12, LR}
RFEFD SP! ; Return from exception
ENDP
osRtxContextSwitch\
PROC
EXPORT osRtxContextSwitch
IMPORT osRtxPendSV_Handler
IMPORT osRtxInfo
IF :DEF:RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
ENDIF
IMPORT IRQ_Disable
IMPORT IRQ_Enable
PUSH {LR}
; Check interrupt nesting level
LDR R0, =IRQ_NestLevel
LDR R1, [R0] ; Load IRQ nest level
CMP R1, #1
BNE osRtxContextExit ; Nesting interrupts, exit context switcher
LDR R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run
LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next
LDR R2, =IRQ_PendSV ; Load address of IRQ_PendSV flag
LDRB R3, [R2] ; Load PendSV flag
CMP R0, R1 ; Check if context switch is required
BNE osRtxContextCheck ; Not equal, check if context save required
CMP R3, #1 ; Compare IRQ_PendSV value
BNE osRtxContextExit ; No post processing (and no context switch requested)
osRtxContextCheck
STR R1, [R12] ; Store run.next as run.curr
; R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run
PUSH {R0-R2, R12}
CMP R0, #0 ; Is osRtxInfo.thread.run.curr == 0
BEQ osRtxPostProcess ; Current deleted, skip context save
osRtxContextSave
MOV LR, R0 ; Move &osRtxInfo.thread.run.curr to LR
MOV R0, SP ; Move SP_svc into R0
ADD R0, R0, #20 ; Adjust SP_svc to R0 of the basic frame
SUB SP, SP, #4
STM SP, {SP}^ ; Save SP_usr to current stack
POP {R1} ; Pop SP_usr into R1
SUB R1, R1, #64 ; Adjust SP_usr to R4 of the basic frame
STMIA R1!, {R4-R11} ; Save R4-R11 to user stack
LDMIA R0!, {R4-R8} ; Load stacked R0-R3,R12 into R4-R8
STMIA R1!, {R4-R8} ; Store them to user stack
STM R1, {LR}^ ; Store LR_usr directly
ADD R1, R1, #4 ; Adjust user sp to PC
LDMIB R0!, {R5-R6} ; Load stacked PC, CPSR
STMIA R1!, {R5-R6} ; Store them to user stack
SUB R1, R1, #64 ; Adjust SP_usr to stacked R4
; Check if VFP state need to be saved
MRC p15, 0, R2, c1, c0, 2 ; VFP/NEON access enabled? (CPACR)
AND R2, R2, #0x00F00000
CMP R2, #0x00F00000
BNE osRtxContextSave1 ; Continue, no VFP
VMRS R2, FPSCR
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
VSTMDB R1!, {D0-D15} ; Save D0-D15
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VSTMDB R1!, {D16-D31} ; Save D16-D31
ENDIF
LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
ORR R2, R2, #4 ; NEON state
ELSE
ORR R2, R2, #2 ; VFP state
ENDIF
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state
osRtxContextSave1
STR R1, [LR, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr
osRtxPostProcess
; RTX IRQ post processing check
POP {R8-R11} ; Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run
LDRB R0, [R10] ; Load PendSV flag
CMP R0, #1 ; Compare PendSV value
BNE osRtxContextRestore ; Skip post processing if not pending
MOV R4, SP ; Move SP_svc into R4
AND R4, R4, #4 ; Get stack adjustment to ensure 8-byte alignment
SUB SP, SP, R4 ; Adjust stack
; Disable OS Tick
LDR R5, =osRtxInfo ; Load address of osRtxInfo
LDR R5, [R5, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
MOV R0, R5 ; Set it as function parameter
BLX IRQ_Disable ; Disable OS Tick interrupt
MOV R6, #0 ; Set PendSV clear value
B osRtxPendCheck
osRtxPendExec
STRB R6, [R10] ; Clear PendSV flag
CPSIE i ; Re-enable interrupts
BLX osRtxPendSV_Handler ; Post process pending objects
CPSID i ; Disable interrupts
osRtxPendCheck
LDR R9, [R11, #4] ; Load osRtxInfo.thread.run.next
STR R9, [R11] ; Store run.next as run.curr
LDRB R0, [R10] ; Load PendSV flag
CMP R0, #1 ; Compare PendSV value
BEQ osRtxPendExec ; Branch to PendExec if PendSV is set
; Re-enable OS Tick
MOV R0, R5 ; Restore irqn as function parameter
BLX IRQ_Enable ; Enable OS Tick interrupt
ADD SP, SP, R4 ; Restore stack adjustment
osRtxContextRestore
IF :DEF:RTX_EXECUTION_ZONE
LDRB R0, [R9, #TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone
CMP R8, #0
BEQ osRtxZoneSetup ; Branch if running thread is deleted
LDRB R1, [R8, #TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone
CMP R0, R1 ; Check if next:zone == curr:zone
BEQ osRtxContextRestoreFrame ; Branch if zone has not changed
osRtxZoneSetup
BL osZoneSetup_Callback ; Setup zone for next thread
ENDIF
osRtxContextRestoreFrame
LDR LR, [R8, #TCB_SP_OFS] ; Load next osRtxThread_t.sp
LDRB R2, [R8, #TCB_SP_FRAME] ; Load next osRtxThread_t.stack_frame
ANDS R2, R2, #0x6 ; Check stack frame for VFP context
MRC p15, 0, R2, c1, c0, 2 ; Read CPACR
ANDEQ R2, R2, #0xFF0FFFFF ; VFP/NEON state not stacked, disable VFP/NEON
ORRNE R2, R2, #0x00F00000 ; VFP/NEON state is stacked, enable VFP/NEON
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VLDMIA LR!, {D16-D31} ; Restore D16-D31
ENDIF
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
ADD LR, LR, #8 ; Adjust sp pointer to R4
osRtxContextRestore1
LDMIA LR!, {R4-R11} ; Restore R4-R11
ADD R12, LR, #32 ; Adjust sp and save it into R12
PUSH {R12} ; Push sp onto stack
LDM SP, {SP}^ ; Restore SP_usr directly
ADD SP, SP, #4 ; Adjust SP_svc
LDMIA LR!, {R0-R3, R12} ; Load user registers R0-R3,R12
STMIB SP!, {R0-R3, R12} ; Store them to SP_svc
LDM LR, {LR}^ ; Restore LR_usr directly
LDMIB LR!, {R0-R1} ; Load user registers PC,CPSR
ADD SP, SP, #4
STMIB SP!, {R0-R1} ; Store them to SP_svc
SUB SP, SP, #32 ; Adjust SP_svc to stacked LR
osRtxContextExit
POP {PC} ; Return
ENDP
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,486 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv7-M Exception handlers
; *
; * your_sha256_hash-------------
; */
IF ({FPU}="FPv4-SP") || ({FPU}="VFPv4_D16") || ({FPU}="VFPv4_SP_D16") || ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
FPU_USED EQU 1
ELSE
FPU_USED EQU 0
ENDIF
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
FPCCR EQU 0xE000EF34 ; FPCCR Address
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
ENDIF
IF :DEF:RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
ENDIF
IF :DEF:RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
ENDIF
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
IF :DEF:RTX_SVC_PTR_CHECK
LDR R12,[R0,#16] ; Load function address from stack
SUB R1,R12,#1 ; Clear T-bit of function address
LSLS R2,R1,#30 ; Check if 4-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R12 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R12,LR} ; Restore SP and EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
ENDIF
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF FPU_USED != 0
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
SVC_FP_LazyState
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
BNE SVC_ContextRestore ; Branch if not extended stack frame
LDR R3,=FPCCR ; FPCCR Address
LDR R0,[R3] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation)
STR R0,[R3] ; Store FPCCR
B SVC_ContextRestore ; Branch to context restore handling
ELSE
CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted
ENDIF
SVC_ContextSave
IF :DEF:RTX_STACK_CHECK
SUB R12,R12,#32 ; Calculate SP: space for R4..R11
IF FPU_USED != 0
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
SUBEQ R12,R12,#64 ; Additional space for S16..S31
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
ENDIF
STR R12,[R1,#TCB_SP_OFS] ; Store SP
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok
IF FPU_USED != 0
MOV R4,R1 ; Assign osRtxInfo.thread.run.curr to R4
ENDIF
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
IF FPU_USED != 0
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
B SVC_FP_LazyState ; Branch to FP lazy state handling
ELSE
B SVC_ContextRestore ; Branch to context restore handling
ENDIF
SVC_ContextSaveRegs
LDR R12,[R1,#TCB_SP_OFS] ; Load SP
IF FPU_USED != 0
LDRSB LR, [R1,#TCB_SF_OFS] ; Load stack frame information
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31
ENDIF
STM R12,{R4-R11} ; Save R4..R11
ELSE
STMDB R12!,{R4-R11} ; Save R4..R11
IF FPU_USED != 0
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
ENDIF
STR R12,[R1,#TCB_SP_OFS] ; Store SP
ENDIF
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag
IF :DEF:RTX_EXECUTION_ZONE
LDRB R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone
CBZ R1,SVC_ZoneSetup ; Branch if running thread is deleted (Z flag unchanged)
LDRB R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
SVC_ZoneSetup
IT NE ; If zone has changed or running thread is deleted
BLNE osZoneSetup_Callback ; Setup zone for next thread
ENDIF
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
IF FPU_USED != 0
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
ELSE
MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
ENDIF
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
ALIGN
ENDP
IF :DEF:RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
ALIGN
ENDP
ENDIF
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,972 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8-M Mainline Exception handlers
; *
; * your_sha256_hash-------------
; */
NAME irq_armv8mml.s
#include "rtx_def.h"
#ifdef __ARMVFP__
FPU_USED EQU 1
#else
FPU_USED EQU 0
#endif
#if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))
MVE_USED EQU 1
#else
MVE_USED EQU 0
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
FPCCR EQU 0xE000EF34 ; FPCCR Address
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
SECTION .text:CODE:NOROOT(2)
THUMB
SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
#endif
#ifdef RTX_TZ_CONTEXT
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
#ifdef RTX_SVC_PTR_CHECK
LDR R12,[R0,#16] ; Load function address from stack
SUB R1,R12,#1 ; Clear T-bit of function address
LSLS R2,R1,#30 ; Check if 4-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R12 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R12,LR} ; Restore SP and EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
#endif
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
#if ((FPU_USED != 0) || (MVE_USED != 0))
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
SVC_FP_LazyState
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
BNE SVC_ContextRestore ; Branch if not extended stack frame
LDR R3,=FPCCR ; FPCCR Address
LDR R0,[R3] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation)
STR R0,[R3] ; Store FPCCR
B SVC_ContextRestore ; Branch to context restore handling
#else
CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted
#endif
SVC_ContextSave
#ifdef RTX_TZ_CONTEXT
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave_NS ; Branch if there is no secure context
PUSH {R1,R2,R12,LR} ; Save registers and EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
POP {R1,R2,R12,LR} ; Restore registers and EXC_RETURN
#endif
SVC_ContextSave_NS
#if (DOMAIN_NS != 0)
TST LR,#0x40 ; Check domain of interrupted thread
BNE SVC_ContextSaveSP ; Branch if secure
#endif
#ifdef RTX_STACK_CHECK
SUB R12,R12,#32 ; Calculate SP: space for R4..R11
#if ((FPU_USED != 0) || (MVE_USED != 0))
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
SUBEQ R12,R12,#64 ; Additional space for S16..S31
#endif
SVC_ContextSaveSP
STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok
#if ((FPU_USED != 0) || (MVE_USED != 0))
MOV R4,R1 ; Assign osRtxInfo.thread.run.curr to R4
#endif
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
#if ((FPU_USED != 0) || (MVE_USED != 0))
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
B SVC_FP_LazyState ; Branch to FP lazy state handling
#else
B SVC_ContextRestore ; Branch to context restore handling
#endif
SVC_ContextSaveRegs
LDRSB LR,[R1,#TCB_SF_OFS] ; Load stack frame information
#if (DOMAIN_NS != 0)
TST LR,#0x40 ; Check domain of interrupted thread
BNE SVC_ContextRestore ; Branch if secure
#endif
LDR R12,[R1,#TCB_SP_OFS] ; Load SP
#if ((FPU_USED != 0) || (MVE_USED != 0))
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31
#endif
STM R12,{R4-R11} ; Save R4..R11
#else
STMDB R12!,{R4-R11} ; Save R4..R11
#if ((FPU_USED != 0) || (MVE_USED != 0))
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
SVC_ContextSaveSP
STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
#endif
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag
#ifdef RTX_EXECUTION_ZONE
LDRB R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone
CBZ R1,SVC_ZoneSetup ; Branch if running thread is deleted (Z flag unchanged)
LDRB R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
SVC_ZoneSetup
IT NE ; If zone has changed or running thread is deleted
BLNE osZoneSetup_Callback ; Setup zone for next thread
#endif
#ifdef RTX_TZ_CONTEXT
LDR R0,[R4,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CMP R0,#0
IT NE ; If TrustZone memory allocated
BLNE TZ_LoadContext_S ; Load secure context
#endif
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
LDR R1,[R4,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R1 ; Set PSPLIM
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
#if (DOMAIN_NS != 0)
TST LR,#0x40 ; Check domain of interrupted thread
ITT NE ; If secure
MSRNE PSP,R0 ; Set PSP
BXNE LR ; Exit from handler
#endif
#if ((FPU_USED != 0) || (MVE_USED != 0))
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
PendSV_Handler
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
SysTick_Handler
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
#ifdef RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
ALIGN
ENDP
#endif
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,465 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8-M Baseline Exception handlers
; *
; * your_sha256_hash-------------
; */
NAME irq_armv8mbl.s
#include "rtx_def.h"
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
SECTION .text:CODE:NOROOT(2)
THUMB
SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
#endif
#ifdef RTX_TZ_CONTEXT
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP ; Branch if return stack is MSP
MRS R0,PSP ; Get PSP
SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
#ifdef RTX_SVC_PTR_CHECK
SUBS R1,R7,#0x01 ; Clear T-bit of function address
LSLS R2,R1,#29 ; Check if 8-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R7 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R2,R3} ; Restore SP and EXC_RETURN
MOV LR,R3 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
#endif
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted
SVC_ContextSave
#ifdef RTX_TZ_CONTEXT
MOV R3,LR ; Get EXC_RETURN
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave_NS ; Branch if there is no secure context
PUSH {R0-R3} ; Save registers
BL TZ_StoreContext_S ; Store secure context
POP {R0-R3} ; Restore registers
MOV LR,R3 ; Set EXC_RETURN
#endif
SVC_ContextSave_NS
MRS R0,PSP ; Get PSP
#if (DOMAIN_NS != 0)
MOV R3,LR ; Get EXC_RETURN
LSLS R3,R3,#25 ; Check domain of interrupted thread
BMI SVC_ContextSaveSP ; Branch if secure
#endif
#ifdef RTX_STACK_CHECK
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
SVC_ContextSaveSP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
MOV R3,LR ; Get EXC_RETURN
MOVS R0,#TCB_SF_OFS ; Get TCB.stack_frame offset
STRB R3,[R1,R0] ; Store stack frame information
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
B SVC_ContextRestore ; Branch to context restore handling
SVC_ContextSaveRegs
#if (DOMAIN_NS != 0)
MOVS R0,#TCB_SF_OFS ; Get TCB.stack_frame offset
LDRSB R3,[R1,R0] ; Load stack frame information
LSLS R3,R3,#25 ; Check domain of interrupted thread
BMI SVC_ContextRestore ; Branch if secure
#endif
LDR R0,[R1,#TCB_SP_OFS] ; Load SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
#else
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SUBS R0,R0,#32 ; Adjust address
SVC_ContextSaveSP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
MOV R3,LR ; Get EXC_RETURN
MOVS R0,#TCB_SF_OFS ; Get TCB.stack_frame offset
STRB R3,[R1,R0] ; Store stack frame information
#endif
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4
#ifdef RTX_EXECUTION_ZONE
MOVS R3,#TCB_ZONE_OFS ; Get TCB.zone offset
LDRB R0,[R2,R3] ; Load osRtxInfo.thread.run.next: zone
CBZ R1,SVC_ZoneSetup ; Branch if running thread is deleted
LDRB R1,[R1,R3] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
BEQ SVC_ContextRestore_S ; Branch if zone has not changed
SVC_ZoneSetup
BL osZoneSetup_Callback ; Setup zone for next thread
#endif
SVC_ContextRestore_S
#ifdef RTX_TZ_CONTEXT
LDR R0,[R4,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore_NS ; Branch if there is no secure context
BL TZ_LoadContext_S ; Load secure context
#endif
SVC_ContextRestore_NS
LDR R0,[R4,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R0 ; Set PSPLIM
MOVS R0,#TCB_SF_OFS ; Get TCB.stack_frame offset
LDRSB R3,[R4,R0] ; Load stack frame information
MOV LR,R3 ; Set EXC_RETURN
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
#if (DOMAIN_NS != 0)
LSLS R3,R3,#25 ; Check domain of interrupted thread
BMI SVC_ContextRestoreSP ; Branch if secure
#endif
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
ADDS R0,R0,#16 ; Adjust address
SVC_ContextRestoreSP
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_MSP
MRS R0,MSP ; Get MSP
B SVC_Number
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] ; Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
BX R3 ; Return from handler
PendSV_Handler
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
SysTick_Handler
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
#ifdef RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
B SVC_Context ; Branch to context handling
ALIGN
ENDP
#endif
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,209 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv6-M Exception handlers
; *
; * your_sha256_hash-------------
; */
NAME irq_armv6m.s
#include "rtx_def.h"
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
THUMB
SECTION .text:CODE:NOROOT(2)
SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
#endif
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP ; Branch if return stack is MSP
MRS R0,PSP ; Get PSP
SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
#ifdef RTX_SVC_PTR_CHECK
SUBS R1,R7,#0x01 ; Clear T-bit of function address
LSLS R2,R1,#29 ; Check if 8-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R7 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R2,R3} ; Restore SP and EXC_RETURN
MOV LR,R3 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
#endif
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
CMP R1,#0
BEQ SVC_ContextRestore ; Branch if running thread is deleted
SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STR R0,[R1,#TCB_SP_OFS] ; Store SP
#ifdef RTX_STACK_CHECK
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CMP R0,#0
BNE SVC_ContextSaveRegs ; Branch when stack check is ok
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
B SVC_ContextRestore ; Branch to context restore handling
SVC_ContextSaveRegs
LDR R0,[R1,#TCB_SP_OFS] ; Load SP
#endif
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4
#ifdef RTX_EXECUTION_ZONE
MOVS R3,#TCB_ZONE_OFS ; Get TCB.zone offset
LDRB R0,[R2,R3] ; Load osRtxInfo.thread.run.next: zone
CMP R1,#0
BEQ SVC_ZoneSetup ; Branch if running thread is deleted
LDRB R1,[R1,R3] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
BEQ SVC_ContextRestore_N ; Branch if zone has not changed
SVC_ZoneSetup
BL osZoneSetup_Callback ; Setup zone for next thread
#endif
SVC_ContextRestore_N
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler
SVC_MSP
MRS R0,MSP ; Get MSP
B SVC_Number
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] ; Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
BX R3 ; Return from handler
PendSV_Handler
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
SysTick_Handler
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context ; Branch to context handling
#ifdef RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
B SVC_Context ; Branch to context handling
ALIGN
ENDP
#endif
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,403 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv7-A Exception handlers
; *
; * your_sha256_hash-------------
; */
NAME irq_armv7a.s
#include "rtx_def.h"
MODE_FIQ EQU 0x11
MODE_IRQ EQU 0x12
MODE_SVC EQU 0x13
MODE_ABT EQU 0x17
MODE_UND EQU 0x1B
CPSR_BIT_T EQU 0x20
K_STATE_RUNNING EQU 2 ; osKernelState_t::osKernelRunning
I_K_STATE_OFS EQU 8 ; osRtxInfo.kernel.state offset
I_TICK_IRQN_OFS EQU 16 ; osRtxInfo.tick_irqn offset
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_FRAME EQU 34 ; osRtxThread_t.stack_frame offset
TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset
TCB_ZONE_OFS EQU 68 ; osRtxThread_t.zone offset
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
SECTION .data:DATA:NOROOT(2)
EXPORT SVC_Active
EXPORT IRQ_PendSV
IRQ_NestLevel DCD 0 ; IRQ nesting level counter
SVC_Active DCB 0 ; SVC Handler Active
IRQ_PendSV DCB 0 ; Pending SVC flag
SECTION .text:CODE:NOROOT(2)
Undef_Handler
EXPORT Undef_Handler
IMPORT CUndefHandler
SRSFD SP!, #MODE_UND
PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
MRS R0, SPSR
TST R0, #CPSR_BIT_T ; Check mode
MOVEQ R1, #4 ; R1 = 4 ARM mode
MOVNE R1, #2 ; R1 = 2 Thumb mode
SUB R0, LR, R1
LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
BEQ Undef_Cont
; Thumb instruction
; Determine if it is a 32-bit Thumb instruction
LDRH R0, [R0]
MOV R2, #0x1C
CMP R2, R0, LSR #11
BHS Undef_Cont ; 16-bit Thumb instruction
; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
Undef_Cont
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)
BL CUndefHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
SUB LR, LR, R0
LDR R0, [SP, #28] ; Restore stacked SPSR
MSR SPSR_CXSF, R0
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stacked APCS registers
ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
MOVS PC, LR
PAbt_Handler
EXPORT PAbt_Handler
IMPORT CPAbtHandler
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 1 ; IFSR
MRC p15, 0, R1, c6, c0, 2 ; IFAR
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CPAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stack APCS registers
RFEFD SP! ; Return from exception
DAbt_Handler
EXPORT DAbt_Handler
IMPORT CDAbtHandler
SUB LR, LR, #8 ; Pre-adjust LR
SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 0 ; DFSR
MRC p15, 0, R1, c6, c0, 0 ; DFAR
MOV R2, LR ; Set LR to third argument
AND R12, SP, #4 ; Ensure stack is 8-byte aligned
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CDAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
CLREX ; Clear exclusive monitor
POP {R0-R4, R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
IRQ_Handler
EXPORT IRQ_Handler
IMPORT IRQ_GetActiveIRQ
IMPORT IRQ_GetHandler
IMPORT IRQ_EndOfInterrupt
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
CPS #MODE_SVC ; Change to SVC mode
PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
ADD R1, R1, #1 ; Increment IRQ nesting level
STR R1, [R0]
MOV R3, SP ; Move SP into R3
AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
SUB SP, SP, R3 ; Adjust stack
PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
MOV R4, R0 ; Move interrupt ID to R4
BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
CMP R0, #0 ; Check if handler address is 0
BEQ IRQ_End ; If 0, end interrupt and return
CPSIE i ; Re-enable interrupts
BLX R0 ; Call IRQ handler
CPSID i ; Disable interrupts
IRQ_End
MOV R0, R4 ; Move interrupt ID to R0
BLX IRQ_EndOfInterrupt ; Signal end of interrupt
POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
ADD SP, SP, R3 ; Unadjust stack
BL osRtxContextSwitch ; Continue in context switcher
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
SUBS R1, R1, #1 ; Decrement IRQ nesting level
STR R1, [R0]
CLREX ; Clear exclusive monitor for interrupted code
POP {R0-R3, R12, LR} ; Restore stacked APCS registers
RFEFD SP! ; Return from IRQ handler
SVC_Handler
EXPORT SVC_Handler
IMPORT IRQ_Disable
IMPORT IRQ_Enable
IMPORT osRtxUserSVC
IMPORT osRtxInfo
SRSFD SP!, #MODE_SVC ; Store SPSR_svc and LR_svc onto SVC stack
PUSH {R12, LR}
MRS R12, SPSR ; Load SPSR
TST R12, #CPSR_BIT_T ; Thumb bit set?
LDRHNE R12, [LR,#-2] ; Thumb: load halfword
BICNE R12, R12, #0xFF00 ; extract SVC number
LDREQ R12, [LR,#-4] ; ARM: load word
BICEQ R12, R12, #0xFF000000 ; extract SVC number
CMP R12, #0 ; Compare SVC number
BNE SVC_User ; Branch if User SVC
PUSH {R0-R3} ; Push arguments to stack
LDR R0, =SVC_Active
MOV R1, #1
STRB R1, [R0] ; Set SVC Handler Active
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
ADD R1, R1, #1 ; Increment IRQ nesting level
STR R1, [R0]
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
BLT SVC_FuncCall ; Continue if kernel is not running
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Disable ; Disable OS Tick interrupt
SVC_FuncCall
LDM SP, {R0-R3, R12} ; Reload R0-R3 and R12 from stack
CPSIE i ; Re-enable interrupts
BLX R12 ; Branch to SVC function
CPSID i ; Disable interrupts
STR R0, [SP] ; Store function return value
LDR R0, =osRtxInfo
LDR R1, [R0, #I_K_STATE_OFS] ; Load RTX5 kernel state
CMP R1, #K_STATE_RUNNING ; Check osKernelRunning
BLT SVC_ContextCheck ; Continue if kernel is not running
LDR R0, [R0, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
BLX IRQ_Enable ; Enable OS Tick interrupt
SVC_ContextCheck
BL osRtxContextSwitch ; Continue in context switcher
LDR R0, =IRQ_NestLevel
LDR R1, [R0]
SUB R1, R1, #1 ; Decrement IRQ nesting level
STR R1, [R0]
LDR R0, =SVC_Active
MOV R1, #0
STRB R1, [R0] ; Clear SVC Handler Active
CLREX ; Clear exclusive monitor
POP {R0-R3, R12, LR} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
SVC_User
PUSH {R4, R5}
LDR R5,=osRtxUserSVC ; Load address of SVC table
LDR R4,[R5] ; Load SVC maximum number
CMP R12,R4 ; Check SVC number range
BHI SVC_Done ; Branch if out of range
LDR R12,[R5,R12,LSL #2] ; Load SVC Function Address
BLX R12 ; Call SVC Function
SVC_Done
CLREX ; Clear exclusive monitor
POP {R4, R5, R12, LR}
RFEFD SP! ; Return from exception
osRtxContextSwitch
EXPORT osRtxContextSwitch
IMPORT osRtxPendSV_Handler
IMPORT osRtxInfo
#ifdef RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
#endif
IMPORT IRQ_Disable
IMPORT IRQ_Enable
PUSH {LR}
; Check interrupt nesting level
LDR R0, =IRQ_NestLevel
LDR R1, [R0] ; Load IRQ nest level
CMP R1, #1
BNE osRtxContextExit ; Nesting interrupts, exit context switcher
LDR R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run
LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next
LDR R2, =IRQ_PendSV ; Load address of IRQ_PendSV flag
LDRB R3, [R2] ; Load PendSV flag
CMP R0, R1 ; Check if context switch is required
BNE osRtxContextCheck ; Not equal, check if context save required
CMP R3, #1 ; Compare IRQ_PendSV value
BNE osRtxContextExit ; No post processing (and no context switch requested)
osRtxContextCheck
STR R1, [R12] ; Store run.next as run.curr
; R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run
PUSH {R0-R2, R12}
CMP R0, #0 ; Is osRtxInfo.thread.run.curr == 0
BEQ osRtxPostProcess ; Current deleted, skip context save
osRtxContextSave
MOV LR, R0 ; Move &osRtxInfo.thread.run.curr to LR
MOV R0, SP ; Move SP_svc into R0
ADD R0, R0, #20 ; Adjust SP_svc to R0 of the basic frame
SUB SP, SP, #4
STM SP, {SP}^ ; Save SP_usr to current stack
POP {R1} ; Pop SP_usr into R1
SUB R1, R1, #64 ; Adjust SP_usr to R4 of the basic frame
STMIA R1!, {R4-R11} ; Save R4-R11 to user stack
LDMIA R0!, {R4-R8} ; Load stacked R0-R3,R12 into R4-R8
STMIA R1!, {R4-R8} ; Store them to user stack
STM R1, {LR}^ ; Store LR_usr directly
ADD R1, R1, #4 ; Adjust user sp to PC
LDMIB R0!, {R5-R6} ; Load stacked PC, CPSR
STMIA R1!, {R5-R6} ; Store them to user stack
SUB R1, R1, #64 ; Adjust SP_usr to stacked R4
; Check if VFP state need to be saved
MRC p15, 0, R2, c1, c0, 2 ; VFP/NEON access enabled? (CPACR)
AND R2, R2, #0x00F00000
CMP R2, #0x00F00000
BNE osRtxContextSave1 ; Continue, no VFP
VMRS R2, FPSCR
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
VSTMDB R1!, {D0-D15} ; Save D0-D15
#ifdef __ARM_ADVANCED_SIMD__
VSTMDB R1!, {D16-D31} ; Save D16-D31
#endif
LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
#ifdef __ARM_ADVANCED_SIMD__
ORR R2, R2, #4 ; NEON state
#else
ORR R2, R2, #2 ; VFP state
#endif
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state
osRtxContextSave1
STR R1, [LR, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr
osRtxPostProcess
; RTX IRQ post processing check
POP {R8-R11} ; Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run
LDRB R0, [R10] ; Load PendSV flag
CMP R0, #1 ; Compare PendSV value
BNE osRtxContextRestore ; Skip post processing if not pending
MOV R4, SP ; Move SP_svc into R4
AND R4, R4, #4 ; Get stack adjustment to ensure 8-byte alignment
SUB SP, SP, R4 ; Adjust stack
; Disable OS Tick
LDR R5, =osRtxInfo ; Load address of osRtxInfo
LDR R5, [R5, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
MOV R0, R5 ; Set it as function parameter
BLX IRQ_Disable ; Disable OS Tick interrupt
MOV R6, #0 ; Set PendSV clear value
B osRtxPendCheck
osRtxPendExec
STRB R6, [R10] ; Clear PendSV flag
CPSIE i ; Re-enable interrupts
BLX osRtxPendSV_Handler ; Post process pending objects
CPSID i ; Disable interrupts
osRtxPendCheck
LDR R9, [R11, #4] ; Load osRtxInfo.thread.run.next
STR R9, [R11] ; Store run.next as run.curr
LDRB R0, [R10] ; Load PendSV flag
CMP R0, #1 ; Compare PendSV value
BEQ osRtxPendExec ; Branch to PendExec if PendSV is set
; Re-enable OS Tick
MOV R0, R5 ; Restore irqn as function parameter
BLX IRQ_Enable ; Enable OS Tick interrupt
ADD SP, SP, R4 ; Restore stack adjustment
osRtxContextRestore
#ifdef RTX_EXECUTION_ZONE
LDRB R0, [R9, #TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone
CMP R8, #0
BEQ osRtxZoneSetup ; Branch if running thread is deleted
LDRB R1, [R8, #TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone
CMP R0, R1 ; Check if next:zone == curr:zone
BEQ osRtxContextRestoreFrame ; Branch if zone has not changed
osRtxZoneSetup
BL osZoneSetup_Callback ; Setup zone for next thread
#endif
osRtxContextRestoreFrame
LDR LR, [R8, #TCB_SP_OFS] ; Load next osRtxThread_t.sp
LDRB R2, [R8, #TCB_SP_FRAME] ; Load next osRtxThread_t.stack_frame
ANDS R2, R2, #0x6 ; Check stack frame for VFP context
MRC p15, 0, R2, c1, c0, 2 ; Read CPACR
ANDEQ R2, R2, #0xFF0FFFFF ; VFP/NEON state not stacked, disable VFP/NEON
ORRNE R2, R2, #0x00F00000 ; VFP/NEON state is stacked, enable VFP/NEON
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
#ifdef __ARM_ADVANCED_SIMD__
VLDMIA LR!, {D16-D31} ; Restore D16-D31
#endif
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
ADD LR, LR, #8 ; Adjust sp pointer to R4
osRtxContextRestore1
LDMIA LR!, {R4-R11} ; Restore R4-R11
ADD R12, LR, #32 ; Adjust sp and save it into R12
PUSH {R12} ; Push sp onto stack
LDM SP, {SP}^ ; Restore SP_usr directly
ADD SP, SP, #4 ; Adjust SP_svc
LDMIA LR!, {R0-R3, R12} ; Load user registers R0-R3,R12
STMIB SP!, {R0-R3, R12} ; Store them to SP_svc
LDM LR, {LR}^ ; Restore LR_usr directly
LDMIB LR!, {R0-R1} ; Load user registers PC,CPSR
ADD SP, SP, #4
STMIB SP!, {R0-R1} ; Store them to SP_svc
SUB SP, SP, #32 ; Adjust SP_svc to stacked LR
osRtxContextExit
POP {PC} ; Return
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,448 |
```gas
;/*
; *
; *
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; *
; * your_sha256_hash-------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv7-M Exception handlers
; *
; * your_sha256_hash-------------
; */
NAME irq_armv7m.s
#include "rtx_def.h"
#ifdef __ARMVFP__
FPU_USED EQU 1
#else
FPU_USED EQU 0
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_ZONE_OFS EQU 68 ; TCB.zone offset
FPCCR EQU 0xE000EF34 ; FPCCR Address
osRtxErrorStackOverflow\
EQU 1 ; Stack overflow
osRtxErrorSVC EQU 6 ; Invalid SVC function called
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
THUMB
SECTION .text:CODE:NOROOT(2)
SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#ifdef RTX_STACK_CHECK
IMPORT osRtxThreadStackCheck
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_SVC_PTR_CHECK
IMPORT |Image$$RTX_SVC_VENEERS$$Base|
IMPORT |Image$$RTX_SVC_VENEERS$$Length|
IMPORT osRtxKernelErrorNotify
#endif
#ifdef RTX_EXECUTION_ZONE
IMPORT osZoneSetup_Callback
#endif
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
#ifdef RTX_SVC_PTR_CHECK
LDR R12,[R0,#16] ; Load function address from stack
SUB R1,R12,#1 ; Clear T-bit of function address
LSLS R2,R1,#30 ; Check if 4-byte aligned
BEQ SVC_PtrBoundsCheck ; Branch if address is aligned
SVC_PtrInvalid
PUSH {R0,LR} ; Save SP and EXC_RETURN
MOVS R0,#osRtxErrorSVC ; Parameter: code
MOV R1,R12 ; Parameter: object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
POP {R12,LR} ; Restore SP and EXC_RETURN
B SVC_Context ; Branch to context handling
SVC_PtrBoundsCheck
LDR R2,=|Image$$RTX_SVC_VENEERS$$Base|
LDR R3,=|Image$$RTX_SVC_VENEERS$$Length|
SUBS R2,R1,R2 ; Subtract SVC table base address
CMP R2,R3 ; Compare with SVC table boundaries
BHS SVC_PtrInvalid ; Branch if address is out of bounds
#endif
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
#if (FPU_USED != 0)
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
SVC_FP_LazyState
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
BNE SVC_ContextRestore ; Branch if not extended stack frame
LDR R3,=FPCCR ; FPCCR Address
LDR R0,[R3] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation)
STR R0,[R3] ; Store FPCCR
B SVC_ContextRestore ; Branch to context restore handling
#else
CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted
#endif
SVC_ContextSave
#ifdef RTX_STACK_CHECK
SUB R12,R12,#32 ; Calculate SP: space for R4..R11
#if (FPU_USED != 0)
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
SUBEQ R12,R12,#64 ; Additional space for S16..S31
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP
PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next
MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr
BL osRtxThreadStackCheck ; Check if thread stack is overrun
POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next
CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok
#if (FPU_USED != 0)
MOV R4,R1 ; Assign osRtxInfo.thread.run.curr to R4
#endif
MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id
BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify
LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run
LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
MOVS R1,#0 ; Simulate deleted running thread
#if (FPU_USED != 0)
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
B SVC_FP_LazyState ; Branch to FP lazy state handling
#else
B SVC_ContextRestore ; Branch to context restore handling
#endif
SVC_ContextSaveRegs
LDR R12,[R1,#TCB_SP_OFS] ; Load SP
#if (FPU_USED != 0)
LDRSB LR, [R1,#TCB_SF_OFS] ; Load stack frame information
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31
#endif
STM R12,{R4-R11} ; Save R4..R11
#else
STMDB R12!,{R4-R11} ; Save R4..R11
#if (FPU_USED != 0)
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP
#endif
SVC_ContextRestore
MOVS R4,R2 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag
#ifdef RTX_EXECUTION_ZONE
LDRB R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone
CBZ R1,SVC_ZoneSetup ; Branch if running thread is deleted (Z flag unchanged)
LDRB R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone
CMP R0,R1 ; Check if next:zone == curr:zone
SVC_ZoneSetup
IT NE ; If zone has changed or running thread is deleted
BLNE osZoneSetup_Callback ; Setup zone for next thread
#endif
LDR R0,[R4,#TCB_SP_OFS] ; Load SP
#if (FPU_USED != 0)
LDRSB LR,[R4,#TCB_SF_OFS] ; Load stack frame information
TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
IT EQ ; If extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#else
MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
PendSV_Handler
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
SysTick_Handler
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
#ifdef RTX_SAFETY_FEATURES
osFaultResume PROC
EXPORT osFaultResume
MRS R12,PSP ; Save PSP to R12
B SVC_Context ; Branch to context handling
ALIGN
ENDP
#endif
END
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,905 |
```c
/* your_sha256_hash----------
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* Name: main.c
* Purpose: RTX example program
*
*your_sha256_hash-----------*/
#include <stdio.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#include "cmsis_os2.h"
void app_main (void *argument);
void app_msg (void *argument);
typedef struct msg_s {
uint8_t cmd;
uint8_t len;
uint8_t data[8];
} msg_t;
static osMessageQueueId_t msgQueue;
static osMemoryPoolId_t memPool;
static const osThreadAttr_t msgAttr = {
.stack_size = 400U
};
/*your_sha256_hash------------
* Application main thread
*your_sha256_hash-----------*/
void app_main (void *argument) {
(void)argument;
osStatus_t status;
uint32_t cnt = 0UL;
msg_t* msg;
while (1) {
// Allocate memory for the message
msg = osMemoryPoolAlloc(memPool, osWaitForever);
if (msg == NULL) {
printf("app_msg: osMemoryPoolAlloc failed.\n");
continue;
}
// Produce a new message and put it to the queue
++cnt;
msg->cmd = 1U;
msg->len = 4U;
*((uint32_t*)(msg->data)) = cnt;
status = osMessageQueuePut(msgQueue, &msg, 0U, osWaitForever);
if (status != osOK) {
printf("app_main: osMessageQueuePut failed.\n");
}
// Defer message creation
osDelay(osMessageQueueGetCount(msgQueue)*100U);
}
}
/*your_sha256_hash------------
* Application message receiver thread
*your_sha256_hash-----------*/
void app_msg (void *argument) {
(void)argument;
osStatus_t status;
uint32_t cnt;
msg_t* msg;
while (1) {
// Defer message processing
osDelay(osMessageQueueGetSpace(msgQueue)*100U);
// Wait forever until a message could be received
status = osMessageQueueGet(msgQueue, &msg, NULL, osWaitForever);
if (status != osOK) {
printf("app_msg: osMessageQueueGet failed.\n");
} else {
if (msg->len == 4U) {
cnt = *((uint32_t*)(msg->data));
}
printf("app_msg: received [cmd = %d, data = 0x%0X]\n", msg->cmd, cnt);
// Free memory of the message
status = osMemoryPoolFree(memPool, msg);
if (status != osOK) {
printf("app_msg: osMemoryPoolFree failed.\n");
}
}
}
}
/*your_sha256_hash------------
* Main entry
*your_sha256_hash-----------*/
int main (void) {
// System Initialization
SystemCoreClockUpdate();
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
osThreadNew(app_msg, NULL, &msgAttr); // Create message receiver thread
// Create message queue used to pass pointers to msg_t
msgQueue = osMessageQueueNew(10U, sizeof(msg_t*), NULL);
// Create memory pool for actual message objects
memPool = osMemoryPoolNew(10U, sizeof(msg_t), NULL);
osKernelStart(); // Start thread execution
for (;;) {}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/MemPool/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 819 |
```objective-c
/*your_sha256_hash--------------
* MDK - Component ::Event Recorder
*your_sha256_hash--------------
* Name: EventRecorderConf.h
* Purpose: Event Recorder Configuration
* Rev.: V1.1.0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Event Recorder
// <o>Number of Records
// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
// <65536=>65536
// <i>Configures size of Event Record Buffer (each record is 16 bytes)
// <i>Must be 2^n (min=8, max=65536)
#define EVENT_RECORD_COUNT 64U
// <o>Time Stamp Source
// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer
// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset)
// <i>Selects source for 32-bit time stamp
#define EVENT_TIMESTAMP_SOURCE 2
// <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
// <i>Defines initial time stamp clock frequency (0 when not used)
#define EVENT_TIMESTAMP_FREQ 0U
// </h>
//------------- <<< end of configuration section >>> ---------------------------
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Compiler/EventRecorderConf.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 352 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.6.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <e>Safety features (Source variant only)
// <i> Enables FuSa related features.
// <i> Requires RTX Source variant.
// <i> Enables:
// <i> - selected features from this group
// <i> - Thread functions: osThreadProtectPrivileged
#ifndef OS_SAFETY_FEATURES
#define OS_SAFETY_FEATURES 0
#endif
// <q>Safety Class
// <i> Threads assigned to lower classes cannot modify higher class threads.
// <i> Enables:
// <i> - Object attributes: osSafetyClass
// <i> - Kernel functions: osKernelProtect, osKernelDestroyClass
// <i> - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass
#ifndef OS_SAFETY_CLASS
#define OS_SAFETY_CLASS 1
#endif
// <q>MPU Protected Zone
// <i> Access protection via MPU (Spatial isolation).
// <i> Enables:
// <i> - Thread attributes: osThreadZone
// <i> - Thread functions: osThreadGetZone, osThreadTerminateZone
// <i> - Zone Management: osZoneSetup_Callback
#ifndef OS_EXECUTION_ZONE
#define OS_EXECUTION_ZONE 1
#endif
// <q>Thread Watchdog
// <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).
// <i> Enables:
// <i> - Thread functions: osThreadFeedWatchdog
// <i> - Handler functions: osWatchdogAlarm_Handler
#ifndef OS_THREAD_WATCHDOG
#define OS_THREAD_WATCHDOG 1
#endif
// <q>Object Pointer checking
// <i> Check object pointer alignment and memory region.
#ifndef OS_OBJ_PTR_CHECK
#define OS_OBJ_PTR_CHECK 0
#endif
// <q>SVC Function Pointer checking
// <i> Check SVC function pointer alignment and memory region.
// <i> User needs to define a linker execution region RTX_SVC_VENEERS
// <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)
#ifndef OS_SVC_PTR_CHECK
#define OS_SVC_PTR_CHECK 0
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 512
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <o>Idle Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_CLASS
#define OS_IDLE_THREAD_CLASS 0
#endif
// <o>Idle Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_ZONE
#define OS_IDLE_THREAD_ZONE 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Default Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Unprivileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 0
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_CLASS
#define OS_TIMER_THREAD_CLASS 0
#endif
// <o>Timer Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_ZONE
#define OS_TIMER_THREAD_ZONE 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 1
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x81U
#endif
// <e.7>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x81U
#endif
// <e.7>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x85U
#endif
// <e.7>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x81U
#endif
// <e.7>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x81U
#endif
// <e.7>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x81U
#endif
// <e.7>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x81U
#endif
// <e.7>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x81U
#endif
// <e.7>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
#endif
// <e.7>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x81U
#endif
// <e.7>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/CMSIS/RTX_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,011 |
```c
/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "ARMCM3.h"
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Device/ARMCM3/system_ARMCM3.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 332 |
```c
/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM3)
#include "ARMCM3.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Device/ARMCM3/startup_ARMCM3.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,201 |
```c
/* your_sha256_hash----------
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* Name: Blinky.c
* Purpose: RTX example program
*
*your_sha256_hash-----------*/
#include <stdio.h>
#include "cmsis_os.h" // ARM::CMSIS:RTOS:Keil RTX5
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "RTE_Components.h"
#include CMSIS_device_header
osThreadId_t tid_phaseA; /* Thread id of thread: phase_a */
osThreadId_t tid_phaseB; /* Thread id of thread: phase_b */
osThreadId_t tid_phaseC; /* Thread id of thread: phase_c */
osThreadId_t tid_phaseD; /* Thread id of thread: phase_d */
osThreadId_t tid_clock; /* Thread id of thread: clock */
struct phases_t {
int_fast8_t phaseA;
int_fast8_t phaseB;
int_fast8_t phaseC;
int_fast8_t phaseD;
} g_phases;
/*your_sha256_hash------------
* Switch LED on
*your_sha256_hash-----------*/
void Switch_On (unsigned char led) {
printf("LED On: #%d\n\r", led);
}
/*your_sha256_hash------------
* Switch LED off
*your_sha256_hash-----------*/
void Switch_Off (unsigned char led) {
printf("LED Off: #%d\n\r", led);
}
/*your_sha256_hash------------
* Function 'signal_func' called from multiple threads
*your_sha256_hash-----------*/
void signal_func (osThreadId_t tid) {
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
osDelay(500); /* delay 500ms */
osThreadFlagsSet(tid_clock, 0x0100); /* set signal to clock thread */
osDelay(500); /* delay 500ms */
osThreadFlagsSet(tid, 0x0001); /* set signal to thread 'thread' */
osDelay(500); /* delay 500ms */
}
/*your_sha256_hash------------
* Thread 1 'phaseA': Phase A output
*your_sha256_hash-----------*/
void phaseA (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(0);
g_phases.phaseA = 1;
signal_func(tid_phaseB); /* call common signal function */
g_phases.phaseA = 0;
Switch_Off(0);
}
}
/*your_sha256_hash------------
* Thread 2 'phaseB': Phase B output
*your_sha256_hash-----------*/
void phaseB (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(1);
g_phases.phaseB = 1;
signal_func(tid_phaseC); /* call common signal function */
g_phases.phaseB = 0;
Switch_Off(1);
}
}
/*your_sha256_hash------------
* Thread 3 'phaseC': Phase C output
*your_sha256_hash-----------*/
void phaseC (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(2);
g_phases.phaseC = 1;
signal_func(tid_phaseD); /* call common signal function */
g_phases.phaseC = 0;
Switch_Off(2);
}
}
/*your_sha256_hash------------
* Thread 4 'phaseD': Phase D output
*your_sha256_hash-----------*/
void phaseD (void *argument) {
for (;;) {
osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */
Switch_On(3);
g_phases.phaseD = 1;
signal_func(tid_phaseA); /* call common signal function */
g_phases.phaseD = 0;
Switch_Off(3);
}
}
/*your_sha256_hash------------
* Thread 5 'clock': Signal Clock
*your_sha256_hash-----------*/
void clock (void const *argument) {
for (;;) {
osSignalWait(0x0100, osWaitForever); /* wait for an event flag 0x0100 */
osDelay(80); /* delay 80ms */
}
}
/* Define the API v1 thread */
osThreadDef(clock, osPriorityNormal, 1, 0);
/*your_sha256_hash------------
* Main: Initialize and start RTX Kernel
*your_sha256_hash-----------*/
void app_main (void *argument) {
tid_phaseA = osThreadNew(phaseA, NULL, NULL);
tid_phaseB = osThreadNew(phaseB, NULL, NULL);
tid_phaseC = osThreadNew(phaseC, NULL, NULL);
tid_phaseD = osThreadNew(phaseD, NULL, NULL);
tid_clock = osThreadCreate(osThread(clock), NULL);
osThreadFlagsSet(tid_phaseA, 0x0001); /* set signal to phaseA thread */
osDelay(osWaitForever);
}
int main (void) {
// System Initialization
SystemCoreClockUpdate();
// ...
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
if (osKernelGetState() == osKernelReady) {
osKernelStart(); // Start thread execution
}
while(1);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,314 |
```objective-c
/*your_sha256_hash--------------
* MDK - Component ::Event Recorder
*your_sha256_hash--------------
* Name: EventRecorderConf.h
* Purpose: Event Recorder Configuration
* Rev.: V1.1.0
*your_sha256_hash------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Event Recorder
// <o>Number of Records
// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
// <65536=>65536
// <i>Configures size of Event Record Buffer (each record is 16 bytes)
// <i>Must be 2^n (min=8, max=65536)
#define EVENT_RECORD_COUNT 64U
// <o>Time Stamp Source
// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer
// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset)
// <i>Selects source for 32-bit time stamp
#define EVENT_TIMESTAMP_SOURCE 2
// <o>Time Stamp Clock Frequency [Hz] <0-1000000000>
// <i>Defines initial time stamp clock frequency (0 when not used)
#define EVENT_TIMESTAMP_FREQ 25000000U
// </h>
//------------- <<< end of configuration section >>> ---------------------------
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Compiler/EventRecorderConf.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 354 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* main_ns.c Non-secure main function - RTOS demo
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "..\CM33_s\interface.h" // Interface API
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
static osStatus_t Status;
static osThreadId_t ThreadA_Id;
static osThreadId_t ThreadB_Id;
static osThreadId_t ThreadC_Id;
void ThreadA (void *argument);
void ThreadB (void *argument);
void ThreadC (void *argument);
extern volatile int counterA;
extern volatile int counterB;
extern volatile int counterC;
volatile int counterA;
volatile int counterB;
volatile int counterC;
static int callbackA (int val) {
return (val);
}
__attribute__((noreturn))
void ThreadA (void *argument) {
(void)argument;
for (;;) {
counterA = func1 (counterA);
counterA = func2 (callbackA, counterA);
osDelay(2U);
}
}
static int callbackB (int val) {
uint32_t flags;
flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
if (flags == 1U) {
return (val+1);
} else {
return (0);
}
}
__attribute__((noreturn))
void ThreadB (void *argument) {
(void)argument;
for (;;) {
counterB = func1 (counterB);
counterB = func2 (callbackB, counterB);
}
}
__attribute__((noreturn))
void ThreadC (void *argument) {
(void)argument;
for (;;) {
counterC = counterC + 1;
if ((counterC % 0x10) == 0) {
osThreadFlagsSet (ThreadB_Id, 1);
}
osDelay(1U);
}
}
static const osThreadAttr_t ThreadAttr = {
.tz_module = 1U, // indicate calls to secure mode
};
int main (void) {
Status = osKernelInitialize();
ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);
ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);
ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);
Status = osKernelStart();
for (;;);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/main_ns.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 587 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* $Revision: V5.6.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* your_sha256_hash-------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <e>Safety features (Source variant only)
// <i> Enables FuSa related features.
// <i> Requires RTX Source variant.
// <i> Enables:
// <i> - selected features from this group
// <i> - Thread functions: osThreadProtectPrivileged
#ifndef OS_SAFETY_FEATURES
#define OS_SAFETY_FEATURES 0
#endif
// <q>Safety Class
// <i> Threads assigned to lower classes cannot modify higher class threads.
// <i> Enables:
// <i> - Object attributes: osSafetyClass
// <i> - Kernel functions: osKernelProtect, osKernelDestroyClass
// <i> - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass
#ifndef OS_SAFETY_CLASS
#define OS_SAFETY_CLASS 1
#endif
// <q>MPU Protected Zone
// <i> Access protection via MPU (Spatial isolation).
// <i> Enables:
// <i> - Thread attributes: osThreadZone
// <i> - Thread functions: osThreadGetZone, osThreadTerminateZone
// <i> - Zone Management: osZoneSetup_Callback
#ifndef OS_EXECUTION_ZONE
#define OS_EXECUTION_ZONE 1
#endif
// <q>Thread Watchdog
// <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).
// <i> Enables:
// <i> - Thread functions: osThreadFeedWatchdog
// <i> - Handler functions: osWatchdogAlarm_Handler
#ifndef OS_THREAD_WATCHDOG
#define OS_THREAD_WATCHDOG 1
#endif
// <q>Object Pointer checking
// <i> Check object pointer alignment and memory region.
#ifndef OS_OBJ_PTR_CHECK
#define OS_OBJ_PTR_CHECK 0
#endif
// <q>SVC Function Pointer checking
// <i> Check SVC function pointer alignment and memory region.
// <i> User needs to define a linker execution region RTX_SVC_VENEERS
// <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)
#ifndef OS_SVC_PTR_CHECK
#define OS_SVC_PTR_CHECK 0
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 512
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <o>Idle Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_CLASS
#define OS_IDLE_THREAD_CLASS 0
#endif
// <o>Idle Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_IDLE_THREAD_ZONE
#define OS_IDLE_THREAD_ZONE 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch (requires RTX source variant).
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Default Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Unprivileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 0
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Thread Safety Class <0-15>
// <i> Defines the Safety Class number.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_CLASS
#define OS_TIMER_THREAD_CLASS 0
#endif
// <o>Timer Thread Zone <0-127>
// <i> Defines Thread Zone.
// <i> Default: 0
#ifndef OS_TIMER_THREAD_ZONE
#define OS_TIMER_THREAD_ZONE 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x81U
#endif
// <e.7>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x81U
#endif
// <e.7>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x85U
#endif
// <e.7>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x81U
#endif
// <e.7>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x81U
#endif
// <e.7>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x81U
#endif
// <e.7>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x81U
#endif
// <e.7>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x81U
#endif
// <e.7>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
#endif
// <e.7>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x81U
#endif
// <e.7>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#define OS_TZ_CONTEXT 1
#endif // RTX_CONFIG_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/CMSIS/RTX_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 5,020 |
```c
/******************************************************************************
* @file startup_ARMCM33.c
* @brief CMSIS-Core Device Startup File for Cortex-M33 Device
* @version V2.1.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM33)
#include "ARMCM33.h"
#elif defined (ARMCM33_TZ)
#include "ARMCM33_TZ.h"
#elif defined (ARMCM33_DSP_FP)
#include "ARMCM33_DSP_FP.h"
#elif defined (ARMCM33_DSP_FP_TZ)
#include "ARMCM33_DSP_FP_TZ.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,412 |
```c
/**************************************************************************//**
* @file system_ARMCM33.c
* @brief CMSIS Device System Source File for
* ARMCM33 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM33)
#include "ARMCM33.h"
#elif defined (ARMCM33_TZ)
#include "ARMCM33_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#elif defined (ARMCM33_DSP_FP)
#include "ARMCM33_DSP_FP.h"
#elif defined (ARMCM33_DSP_FP_TZ)
#include "ARMCM33_DSP_FP_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM33.h"
#endif
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 610 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* interface.c Secure/non-secure callable application code
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include <arm_cmse.h> // CMSE definitions
#include "interface.h" // Header file with secure interface API
/* typedef for non-secure callback functions */
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
/* Non-secure callable (entry) function */
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
return x+3;
}
/* Non-secure callable (entry) function, calling a non-secure callback function */
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
funcptr_NS callback_NS; // non-secure callback function pointer
int y;
/* return function pointer with cleared LSB */
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
y = callback_NS (x+1);
return (y+2);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/interface.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 273 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
*
*your_sha256_hash-----------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/tz_context.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,546 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*your_sha256_hash-----------*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/main_s.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 343 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* interface.h API definition for the non-secure state
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
/* Function pointer declaration */
typedef int (*funcptr)(int);
/* Non-secure callable functions */
extern int func1(int x);
extern int func2(funcptr callback, int x);
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/interface.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 123 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM33.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
* @version V1.1.1
* @date 12. March 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM33_H
#define PARTITION_ARMCM33_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM33_H */
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,184 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* main_ns.c Non-secure main function
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "interface.h" // Interface API
extern volatile int val1, val2;
volatile int val1, val2;
/* Non-secure function */
int func3 (int x);
int func3 (int x) {
return (x+4);
}
/* Non-secure main() */
int main(void) {
/* Call non-secure callable function func1 */
val1 = func1 (1);
/* Call non-secure callable function func2
with callback to non-secure function func3 */
val2 = func2 (func3, 2);
while (1);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/main_ns.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 217 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* main_ns.c Non-secure main function - Security attacks demo
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "..\CM33_s\interface.h" // Interface API
#include "..\CM33_s\IncidentLog_s.h"
#include "..\CM33_s\SysTick_s.h"
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
static osStatus_t Status;
static osThreadId_t ThreadA_Id;
static osThreadId_t ThreadB_Id;
static osThreadId_t ThreadC_Id;
static osThreadId_t ThreadD_Id;
void ThreadA (void *argument);
void ThreadB (void *argument);
void ThreadC (void *argument);
void ThreadD (void *argument);
extern volatile int counterA;
extern volatile int counterB;
extern volatile int counterC;
volatile int counterA;
volatile int counterB;
volatile int counterC;
static int callbackA (int val) {
return (val);
}
__attribute__((noreturn))
void ThreadA (void *argument) {
(void)argument;
for (;;) {
counterA = func1 (counterA);
counterA = func2 (callbackA, counterA);
osDelay(2U);
}
}
static int callbackB (int val) {
uint32_t flags;
flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
if (flags == 1U) {
return (val+1);
} else {
return (0);
}
}
__attribute__((noreturn))
void ThreadB (void *argument) {
(void)argument;
for (;;) {
counterB = func1 (counterB);
counterB = func2 (callbackB, counterB);
}
}
__attribute__((noreturn))
void ThreadC (void *argument) {
(void)argument;
for (;;) {
counterC = counterC + 1;
if ((counterC % 0x10) == 0) {
osThreadFlagsSet (ThreadB_Id, 1);
}
osDelay(1U);
}
}
/*
* by creating a large array, PSPLIM will be exeeded
* PSPLIM was setup by the RTOS according the thread's stack border
*/
void thread_stack_overflow (void);
void thread_stack_overflow (void) {
volatile uint32_t foo [1024];
uint32_t i;
for (i=0; i<1024; i++) {
foo[i] = i+i;
}
}
/*
* trying to call into secure memory directly is not allowed
* address 0x1000 is in secure memory according SAU configuration
*/
void illegal_secure_call (void);
void illegal_secure_call (void)
{
void (*FuncPointer) (void) = (void (*) (void)) 0x1000;
FuncPointer ();
}
/*
* an "example fault" caused ba a division by zero
* only generates the fault when SCB_CCR_DIV_0_TRP is set
*/
void div_by_zero( void );
void div_by_zero( void )
{
volatile unsigned int a, b, c;
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
a = 1;
b = 0;
c = a / b;
}
/*
* try to let secure domain overwrite secure memory
* secure application should detect this with buffer range checks
*/
void getdata_attack (void);
void getdata_attack (void) {
/* provide pointer outsite of non-secure memory */
GetIncidentLog_s ((IncidentLog_t *) (0x20200000 - 0x10));
}
/*
* simulate a broken non-secure application by not returning
* a secure SysTick watchdog can be used to detect this inactivety
*/
void play_dead( void );
__NO_RETURN void play_dead( void )
{
osKernelLock( );
while( 1 )
{
__NOP( );
}
}
typedef struct {
void ( *TestFunc )( void );
const char *TestName;
} TestCase_t;
// array of test cases with test functions
static const TestCase_t TestCases[] = {
{ illegal_secure_call, "illegal secure call" },
{ thread_stack_overflow, "stack overflow" },
{ div_by_zero, "div by zero" },
{ getdata_attack, "getdata attack" },
{ play_dead, "play dead" }
};
extern IncidentLog_t IncidentLogCopy;
IncidentLog_t IncidentLogCopy;
extern volatile uint32_t TestCase;
volatile uint32_t TestCase;
/*
* Test case execution
*/
__NO_RETURN void ThreadD (void *argument) {
uint32_t WatchdogToken;
(void)argument;
TestCase = 0xFFFFFFFF;
WatchdogToken = StartWatchdog_s (); /* start watchdog in secure mode */
GetIncidentLog_s (&IncidentLogCopy); /* get incident log and draw the table */
while (1) {
FeedWatchdog_s (WatchdogToken);
osDelay (50);
if (TestCase < (sizeof (TestCases) / sizeof(TestCases[0]))) {
TestCases [TestCase].TestFunc (); /* execute selected test */
}
}
}
static const osThreadAttr_t ThreadAttr = {
.tz_module = 1U, // indicate calls to secure mode
};
int main (void) {
Status = osKernelInitialize();
ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);
ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);
ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);
ThreadD_Id = osThreadNew(ThreadD, NULL, &ThreadAttr);
Status = osKernelStart();
for (;;);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/main_ns.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,342 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* Project: ARMv8-M System Recovery demo
* Title: SysTick_s.c SysTick handler & timeout based watchdog
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "SysTick_s.h"
#include "IncidentLog_s.h"
#include "Hardfault.h"
#include "RTE_Components.h"
#include CMSIS_device_header
#define TIMEOUT_VALUE (500) /* ms */
static const uint32_t ExpectedToken = 0xAB54AB23;
uint32_t Seconds ;
static uint32_t Timeout ;
// Secure SysTick handler
void SysTick_Handler (void) {
static unsigned int Milliseconds;
Milliseconds++ ;
if (Milliseconds >= 1000) {
Seconds++;
Milliseconds = 0;
}
if (Timeout != 0) {
Timeout-- ;
if (Timeout == 0) {
LogIncident (IR_WDTEXP, 0, IS_SECURE);
PerformReset ();
}
}
}
// Initialize Secure SysTick
// \param StartSeconds setup seconds value
void InitWatchdog (uint32_t StartSeconds) {
Seconds = StartSeconds;
Timeout = 0;
SysTick_Config (SystemCoreClock / 1000); /* 1 ms interval */
}
// Restart Watchdog
// \param Food token obtained by StartWatchdog_s
__attribute__((cmse_nonsecure_entry))
void FeedWatchdog_s (uint32_t Food) {
if( Food == ExpectedToken ) {
Timeout = TIMEOUT_VALUE;
}
}
// Start Watchdog
// \return Food token expected by RestartWatchdog
__attribute__((cmse_nonsecure_entry))
uint32_t StartWatchdog_s (void) {
Timeout = TIMEOUT_VALUE;
return (ExpectedToken);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/SysTick_s.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 441 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*your_sha256_hash-----------*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#include "IncidentLog_s.h"
#include "SysTick_s.h"
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
InitWatchdog (InitIncidentLog ());
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/main_s.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 370 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* Project: ARMv8-M System Recovery demo
* Title: IncidentLog.h record system faults
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#ifndef _INCIDENTLOG_H
#define _INCIDENTLOG_H
#include <stdint.h>
/*
* possible incident reasons used in this test program
*/
typedef enum {
IR_UNKNOW, /* unknown reason */
IR_DIVBY0, /* UsageFault, divide by zero when CCR.DIV_0_TRP is 1 */
IR_STKOF, /* UsageFault, stack overflow */
IR_INVEP, /* SecureFault, invalid Secure state entry point */
IR_WDTEXP, /* secure systick watchdog timeout */
IR_SECDAT /* pointer pointing to secure instead non-secure memory */
} IncidentReason_t;
// incident flag
#define IS_SECURE (1UL << 0) /* incident happened in secure state */
typedef struct {
IncidentReason_t Reason; // incident reason
uint8_t Flags; // secure / non-secure state
uint16_t Reserved; // reserved (not used)
uint32_t Time; // time stamp
uint32_t Location; // PC address of incident
} IncidentLogEntry_t;
#define INCIDENT_LOG_ENTRIES_MAX (4)
#define INCIDENT_LOG_MAGIC_NUMBER (0xABABABAB)
typedef struct {
unsigned int MagicNumber;
unsigned int RecentEntry;
IncidentLogEntry_t Entries [INCIDENT_LOG_ENTRIES_MAX];
} IncidentLog_t;
uint32_t InitIncidentLog (void) ;
void LogIncident_s (IncidentReason_t Reason, uint32_t Location, uint8_t Flags);
void LogIncident (IncidentReason_t Reason, uint32_t Location, uint8_t Flags);
void GetIncidentLog_s (IncidentLog_t *IncidentLog_p);
void PerformReset (void);
void hard_fault_handler_c (uint32_t *hardfault_args);
#endif /* !_INCIDENTLOG_H */
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/IncidentLog_s.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 504 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* Project: ARMv8-M System Recovery demo
* Title: SysTick_s.h SysTick handler & timeout based watchdog
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#ifndef _SYSTICK_S_H
#define _SYSTICK_S_H
#include <stdint.h>
// Initialize Secure SysTick
// \param StartSeconds setup seconds value
extern void InitWatchdog (uint32_t StartSeconds);
// Restart Watchdog
// \param Food token obtained by StartWatchdog_s
extern void FeedWatchdog_s (uint32_t Food);
// Start Watchdog
// \return Food token expected by RestartWatchdog
extern uint32_t StartWatchdog_s (void);
#endif /* !_SYSTICK_S_H */
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/SysTick_s.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 217 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* Project: ARMv8-M System Recovery demo
* Title: IncidentLog_s.c record system faults
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "IncidentLog_s.h"
#include "Hardfault.h"
#include <stdio.h>
#include <string.h>
#include <arm_cmse.h>
#include <arm_compat.h>
// locate IncidentLog buffer in uninitialized section
// and use the linker scatter file to ensure that it is not initialized
static IncidentLog_t __attribute__((section( ".bss.noinit"))) IncidentLog;
// time in seconds is maintained by the SysTick_Handler
// and is captured for each incident that gets logged
extern unsigned int Seconds ;
uint32_t InitIncidentLog (void) {
if (INCIDENT_LOG_MAGIC_NUMBER != IncidentLog.MagicNumber) {
/* magig number not there, so initialization required */
memset( &IncidentLog, 0, sizeof( IncidentLog ));
IncidentLog.MagicNumber = INCIDENT_LOG_MAGIC_NUMBER;
}
return (IncidentLog.Entries[IncidentLog.RecentEntry].Time);
}
void LogIncident (IncidentReason_t Reason, uint32_t Location, uint8_t Flags) {
IncidentLog.Entries[IncidentLog.RecentEntry].Reason = Reason;
IncidentLog.Entries[IncidentLog.RecentEntry].Location = Location;
IncidentLog.Entries[IncidentLog.RecentEntry].Time = Seconds;
IncidentLog.Entries[IncidentLog.RecentEntry].Flags = Flags;
IncidentLog.RecentEntry++;
if (IncidentLog.RecentEntry >= INCIDENT_LOG_ENTRIES_MAX) {
IncidentLog.RecentEntry = 0;
}
}
__attribute__((cmse_nonsecure_entry))
void LogIncident_s (IncidentReason_t Reason, uint32_t Location, uint8_t Flags) {
LogIncident (Reason, Location, Flags);
}
__attribute__((cmse_nonsecure_entry))
void GetIncidentLog_s (IncidentLog_t *IncidentLog_p) {
struct IncidentLog_t *IncidentLog_p_ok;
/* cmse_check_pointed_object */
IncidentLog_p_ok = cmse_check_address_range (IncidentLog_p, sizeof(IncidentLog_t), CMSE_NONSECURE);
if (IncidentLog_p_ok != NULL) {
/* requested copy range is completely in non-secure memory */
memcpy (IncidentLog_p_ok, &IncidentLog, sizeof (IncidentLog_t));
}
else
{ /* requested copy range is not comnpletely in non-secure memory */
LogIncident (IR_SECDAT, __current_pc(), IS_SECURE);
PerformReset ();
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/IncidentLog_s.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 639 |
```objective-c
#ifndef _HARDFAULT_H
#define _HARDFAULT_H
void PerformReset( void ) ;
#endif /* !_HARDFAULT_H */
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/Hardfault.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 31 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* Project: ARMv8-M System Recovery demo
* Title: hardfault.c Hardfault handler with incident log and restart
*
* Version 1.0
* Initial Release
*your_sha256_hash-----------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "IncidentLog_s.h"
// \brief perform a system reset to restart the application
__NO_RETURN void PerformReset (void) {
__DSB( ) ;
SCB->AIRCR = ( SCB->AIRCR & ~SCB_AIRCR_VECTKEY_Msk ) |
( 0x05FAUL << SCB_AIRCR_VECTKEY_Pos ) | SCB_AIRCR_SYSRESETREQ_Msk ;
// code should never reach this (however FVP Model does not reset!)
while(1) {
__NOP() ;
}
}
static volatile uint32_t stacked_r0;
static volatile uint32_t stacked_r1;
static volatile uint32_t stacked_r2;
static volatile uint32_t stacked_r3;
static volatile uint32_t stacked_r12;
static volatile uint32_t stacked_lr;
static volatile uint32_t stacked_pc;
static volatile uint32_t stacked_psr;
// \brief Hardfault handler in C.
// \param[in] hardfault_args address of stack frame
void hard_fault_handler_c (uint32_t *hardfault_args) {
IncidentReason_t Reason;
uint8_t Flags ;
stacked_r0 = hardfault_args[0];
stacked_r1 = hardfault_args[1];
stacked_r2 = hardfault_args[2];
stacked_r3 = hardfault_args[3];
stacked_r12 = hardfault_args[4];
stacked_lr = hardfault_args[5];
stacked_pc = hardfault_args[6];
stacked_psr = hardfault_args[7];
/* log the incident */
Flags = 0 ;
if (SAU->SFSR & SAU_SFSR_INVEP_Msk) {
/* SecureFault, invalid Secure state entry point */
Reason = IR_INVEP ;
Flags |= IS_SECURE ;
}
else if (SCB->CFSR & SCB_CFSR_STKOF_Msk) {
/* UsageFault, stack overflow */
Reason = IR_STKOF ;
Flags |= IS_SECURE ;
}
else if (SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) {
/* UsageFault, divide by zero when CCR.DIV_0_TRP is 1 */
Reason = IR_DIVBY0 ;
Flags |= IS_SECURE ;
}
/* AIRCR.BFHFNMINS not set, so also non-secure faults end here */
else if (SCB_NS->CFSR & SCB_CFSR_STKOF_Msk) {
/* UsageFault, stack overflow */
Reason = IR_STKOF ;
}
else if (SCB_NS->CFSR & SCB_CFSR_DIVBYZERO_Msk) {
/* UsageFault, divide by zero when CCR.DIV_0_TRP is 1 */
Reason = IR_DIVBY0 ;
}
//todo handle SCB->SFSR AUVIOL
else
{
Reason = IR_UNKNOW;
}
LogIncident (Reason, stacked_pc, Flags) ;
PerformReset ();
// code should never reach this (Fast Model does not reset!)
while (1) {
__NOP( ) ;
}
}
// \brief evaluate SP that was active before the exception
void HardFault_Handler (void) {
__ASM volatile (
"TST LR, #0x40\n"
"BEQ from_nonsecure\n"
"from_secure:\n"
"TST LR, #0x04\n"
"ITE EQ\n"
"MRSEQ R0, MSP\n"
"MRSNE R0, PSP\n"
"B hard_fault_handler_c\n"
"from_nonsecure:\n"
"MRS R0, CONTROL_NS\n"
"TST R0, #2\n"
"ITE EQ\n"
"MRSEQ R0, MSP_NS\n"
"MRSNE R0, PSP_NS\n"
"B hard_fault_handler_c\n"
);
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/Hardfault.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 991 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Timer: Sample timer functions
*your_sha256_hash-----------*/
/*----- One-Shoot Timer Example -----*/
osTimerId_t tim_id1; // timer id
static uint32_t exec1; // argument for the timer call back function
// One-Shoot Timer Function
static void Timer1_Callback (void const *arg) {
// add user code here
}
/*----- Periodic Timer Example -----*/
osTimerId_t tim_id2; // timer id
static uint32_t exec2; // argument for the timer call back function
// Periodic Timer Function
static void Timer2_Callback (void const *arg) {
// add user code here
}
// Example: Create and Start timers
int Init_Timers (void) {
osStatus_t status; // function return status
// Create one-shoot timer
exec1 = 1U;
tim_id1 = osTimerNew((osTimerFunc_t)&Timer1_Callback, osTimerOnce, &exec1, NULL);
if (tim_id1 != NULL) { // One-shot timer created
// start timer with delay 100ms
status = osTimerStart(tim_id1, 100U);
if (status != osOK) {
return -1;
}
}
// Create periodic timer
exec2 = 2U;
tim_id2 = osTimerNew((osTimerFunc_t)&Timer2_Callback, osTimerPeriodic, &exec2, NULL);
if (tim_id2 != NULL) { // Periodic timer created
// start timer with periodic 1000ms interval
status = osTimerStart(tim_id2, 1000U);
if (status != osOK) {
return -1;
}
}
return NULL;
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/Timer.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 417 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Mutex creation & usage
*your_sha256_hash-----------*/
osMutexId_t mid_Mutex; // mutex id
osThreadId_t tid_Thread_Mutex; // thread id
void Thread_Mutex (void *argument); // thread function
int Init_Mutex (void) {
mid_Mutex = osMutexNew(NULL);
if (mid_Mutex == NULL) {
; // Mutex object not created, handle failure
}
tid_Thread_Mutex = osThreadNew(Thread_Mutex, NULL, NULL);
if (tid_Thread_Mutex == NULL) {
return(-1);
}
return(0);
}
void Thread_Mutex (void *argument) {
osStatus_t status;
while (1) {
; // Insert thread code here...
status = osMutexAcquire(mid_Mutex, 0U);
switch (status) {
case osOK:
; // Use protected code here...
osMutexRelease(mid_Mutex);
break;
case osErrorResource:
break;
case osErrorParameter:
break;
case osErrorISR:
break;
default:
break;
}
osThreadYield(); // suspend thread
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/Mutex.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 291 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash-------------
*
* Project: CMSIS-RTOS RTX
* Title: SVC User Table
*
* your_sha256_hash-------------
*/
#define USER_SVC_COUNT 0 // Number of user SVC functions
extern void * const osRtxUserSVC[1+USER_SVC_COUNT];
void * const osRtxUserSVC[1+USER_SVC_COUNT] = {
(void *)USER_SVC_COUNT,
//(void *)user_function1,
// ...
};
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/svc_user.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 152 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Memory Pool creation & usage
*your_sha256_hash-----------*/
#define MEMPOOL_OBJECTS 16 // number of Memory Pool Objects
typedef struct { // object data type
uint8_t Buf[32];
uint8_t Idx;
} MEM_BLOCK_t;
osMemoryPoolId_t mpid_MemPool; // memory pool id
osThreadId_t tid_Thread_MemPool; // thread id
void Thread_MemPool (void *argument); // thread function
int Init_MemPool (void) {
mpid_MemPool = osMemoryPoolNew(MEMPOOL_OBJECTS, sizeof(MEM_BLOCK_t), NULL);
if (mpid_MemPool == NULL) {
; // MemPool object not created, handle failure
}
tid_Thread_MemPool = osThreadNew(Thread_MemPool, NULL, NULL);
if (tid_Thread_MemPool == NULL) {
return(-1);
}
return(0);
}
void Thread_MemPool (void *argument) {
MEM_BLOCK_t *pMem;
osStatus_t status;
while (1) {
; // Insert thread code here...
pMem = (MEM_BLOCK_t *)osMemoryPoolAlloc(mpid_MemPool, 0U); // get Mem Block
if (pMem != NULL) { // Mem Block was available
pMem->Buf[0] = 0x55U; // do some work...
pMem->Idx = 0U;
status = osMemoryPoolFree(mpid_MemPool, pMem); // free mem block
switch (status) {
case osOK:
break;
case osErrorParameter:
break;
case osErrorNoMemory:
break;
default:
break;
}
}
osThreadYield(); // suspend thread
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/MemPool.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 438 |
```c
/*your_sha256_hash------------
* CMSIS-RTOS 'main' function template
*your_sha256_hash-----------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "cmsis_os2.h"
/*your_sha256_hash------------
* Application main thread
*your_sha256_hash-----------*/
__NO_RETURN static void app_main (void *argument) {
(void)argument;
// ...
for (;;) {}
}
int main (void) {
// System Initialization
SystemCoreClockUpdate();
// ...
osKernelInitialize(); // Initialize CMSIS-RTOS
osThreadNew(app_main, NULL, NULL); // Create application main thread
osKernelStart(); // Start thread execution
for (;;) {}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 163 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Message Queue creation & usage
*your_sha256_hash-----------*/
#define MSGQUEUE_OBJECTS 16 // number of Message Queue Objects
typedef struct { // object data type
uint8_t Buf[32];
uint8_t Idx;
} MSGQUEUE_OBJ_t;
osMessageQueueId_t mid_MsgQueue; // message queue id
osThreadId_t tid_Thread_MsgQueue1; // thread id 1
osThreadId_t tid_Thread_MsgQueue2; // thread id 2
void Thread_MsgQueue1 (void *argument); // thread function 1
void Thread_MsgQueue2 (void *argument); // thread function 2
int Init_MsgQueue (void) {
mid_MsgQueue = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(MSGQUEUE_OBJ_t), NULL);
if (mid_MsgQueue == NULL) {
; // Message Queue object not created, handle failure
}
tid_Thread_MsgQueue1 = osThreadNew(Thread_MsgQueue1, NULL, NULL);
if (tid_Thread_MsgQueue1 == NULL) {
return(-1);
}
tid_Thread_MsgQueue2 = osThreadNew(Thread_MsgQueue2, NULL, NULL);
if (tid_Thread_MsgQueue2 == NULL) {
return(-1);
}
return(0);
}
void Thread_MsgQueue1 (void *argument) {
MSGQUEUE_OBJ_t msg;
while (1) {
; // Insert thread code here...
msg.Buf[0] = 0x55U; // do some work...
msg.Idx = 0U;
osMessageQueuePut(mid_MsgQueue, &msg, 0U, 0U);
osThreadYield(); // suspend thread
}
}
void Thread_MsgQueue2 (void *argument) {
MSGQUEUE_OBJ_t msg;
osStatus_t status;
while (1) {
; // Insert thread code here...
status = osMessageQueueGet(mid_MsgQueue, &msg, NULL, 0U); // wait for message
if (status == osOK) {
; // process data
}
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/MsgQueue.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 488 |
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