text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185
values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Thread 1 'Thread_Name': Sample thread
*your_sha256_hash-----------*/
osThreadId_t tid_Thread; // thread id
void Thread (void *argument); // thread function
int Init_Thread (void) {
tid_Thread = osThreadNew(Thread, NULL, NULL);
if (tid_Thread == NULL) {
return(-1);
}
return(0);
}
void Thread (void *argument) {
while (1) {
; // Insert thread code here...
osThreadYield(); // suspend thread
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/Thread.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 148 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Event Flags creation & usage
*your_sha256_hash-----------*/
#define FLAGS_MSK1 0x00000001U
osEventFlagsId_t evt_id; // event flasg id
osThreadId_t tid_Thread_EventSender; // thread id 1
osThreadId_t tid_Thread_EventReceiver; // thread id 2
void Thread_EventSender (void *argument); // thread function 1
void Thread_EventReceiver (void *argument); // thread function 2
int Init_Events (void) {
evt_id = osEventFlagsNew(NULL);
if (evt_id == NULL) {
; // Event Flags object not created, handle failure
}
tid_Thread_EventSender = osThreadNew(Thread_EventSender, NULL, NULL);
if (tid_Thread_EventSender == NULL) {
return(-1);
}
tid_Thread_EventReceiver = osThreadNew(Thread_EventReceiver, NULL, NULL);
if (tid_Thread_EventReceiver == NULL) {
return(-1);
}
return(0);
}
void Thread_EventSender (void *argument) {
while (1) {
osEventFlagsSet(evt_id, FLAGS_MSK1);
osThreadYield(); // suspend thread
}
}
void Thread_EventReceiver (void *argument) {
uint32_t flags;
while (1) {
flags = osEventFlagsWait(evt_id, FLAGS_MSK1, osFlagsWaitAny, osWaitForever);
//handle event
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/Events.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 349 |
```c
#include "cmsis_os2.h" // CMSIS RTOS header file
/*your_sha256_hash------------
* Semaphore creation & usage
*your_sha256_hash-----------*/
osSemaphoreId_t sid_Semaphore; // semaphore id
osThreadId_t tid_Thread_Semaphore; // thread id
void Thread_Semaphore (void *argument); // thread function
int Init_Semaphore (void) {
sid_Semaphore = osSemaphoreNew(2U, 2U, NULL);
if (sid_Semaphore == NULL) {
; // Semaphore object not created, handle failure
}
tid_Thread_Semaphore = osThreadNew(Thread_Semaphore, NULL, NULL);
if (tid_Thread_Semaphore == NULL) {
return(-1);
}
return(0);
}
void Thread_Semaphore (void *argument) {
int32_t val;
while (1) {
; // Insert thread code here...
val = osSemaphoreAcquire(sid_Semaphore, 10U); // wait 10 mSec
switch (val) {
case osOK:
; // Use protected code here...
osSemaphoreRelease(sid_Semaphore); // return a token back to a semaphore
break;
case osErrorResource:
break;
case osErrorParameter:
break;
default:
break;
}
osThreadYield(); // suspend thread
}
}
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Template/Semaphore.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 320 |
```objective-c
/*your_sha256_hash-------------
* Name: cmsis_cv.h
* Purpose: cmsis_cv header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __CMSIS_CV_H
#define __CMSIS_CV_H
#include <stdint.h>
#include "CV_Config.h"
/* Expansion macro used to create CMSIS Driver references */
#define EXPAND_SYMBOL(name, port) name##port
#define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
// Simulator counter
#ifndef HW_PRESENT
extern uint32_t SIM_CYCCNT;
#endif
// SVC interrupt callback
extern void (*TST_IRQHandler)(void);
// Test main function
extern void cmsis_cv (void);
extern void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc);
// Test cases
extern void TC_CoreInstr_NOP (void);
extern void TC_CoreInstr_SEV (void);
extern void TC_CoreInstr_BKPT (void);
extern void TC_CoreInstr_ISB (void);
extern void TC_CoreInstr_DSB (void);
extern void TC_CoreInstr_DMB (void);
extern void TC_CoreInstr_WFI (void);
extern void TC_CoreInstr_WFE (void);
extern void TC_CoreInstr_REV (void);
extern void TC_CoreInstr_REV16 (void);
extern void TC_CoreInstr_REVSH (void);
extern void TC_CoreInstr_ROR (void);
extern void TC_CoreInstr_RBIT (void);
extern void TC_CoreInstr_CLZ (void);
extern void TC_CoreInstr_SSAT (void);
extern void TC_CoreInstr_USAT (void);
extern void TC_CoreInstr_RRX (void);
extern void TC_CoreInstr_LoadStoreExclusive (void);
extern void TC_CoreInstr_LoadStoreUnpriv (void);
extern void TC_CoreInstr_LoadStoreAcquire (void);
extern void TC_CoreInstr_LoadStoreAcquireExclusive (void);
extern void TC_CoreInstr_UnalignedUint16 (void);
extern void TC_CoreInstr_UnalignedUint32 (void);
extern void TC_CoreSimd_SatAddSub (void);
extern void TC_CoreSimd_ParSat16 (void);
extern void TC_CoreSimd_PackUnpack (void);
extern void TC_CoreSimd_ParSel (void);
extern void TC_CoreSimd_ParAddSub8 (void);
extern void TC_CoreSimd_AbsDif8 (void);
extern void TC_CoreSimd_ParAddSub16 (void);
extern void TC_CoreSimd_ParMul16 (void);
extern void TC_CoreSimd_Pack16 (void);
extern void TC_CoreSimd_MulAcc32 (void);
#if defined(__CORTEX_M)
extern void TC_CoreFunc_EnDisIRQ (void);
extern void TC_CoreFunc_IRQPrio (void);
extern void TC_CoreFunc_EncDecIRQPrio (void);
extern void TC_CoreFunc_IRQVect (void);
extern void TC_CoreFunc_Control (void);
extern void TC_CoreFunc_IPSR (void);
extern void TC_CoreFunc_APSR (void);
extern void TC_CoreFunc_PSP (void);
extern void TC_CoreFunc_MSP (void);
extern void TC_CoreFunc_PSPLIM (void);
extern void TC_CoreFunc_PSPLIM_NS (void);
extern void TC_CoreFunc_MSPLIM (void);
extern void TC_CoreFunc_MSPLIM_NS (void);
extern void TC_CoreFunc_PRIMASK (void);
extern void TC_CoreFunc_FAULTMASK (void);
extern void TC_CoreFunc_BASEPRI (void);
extern void TC_CoreFunc_FPUType (void);
extern void TC_CoreFunc_FPSCR (void);
#elif defined(__CORTEX_A)
extern void TC_CoreAFunc_IRQ (void);
extern void TC_CoreAFunc_FaultIRQ (void);
extern void TC_CoreAFunc_FPSCR (void);
extern void TC_CoreAFunc_CPSR (void);
extern void TC_CoreAFunc_Mode (void);
extern void TC_CoreAFunc_SP (void);
extern void TC_CoreAFunc_SP_usr (void);
extern void TC_CoreAFunc_FPEXC (void);
extern void TC_CoreAFunc_ACTLR (void);
extern void TC_CoreAFunc_CPACR (void);
extern void TC_CoreAFunc_DFSR (void);
extern void TC_CoreAFunc_IFSR (void);
extern void TC_CoreAFunc_ISR (void);
extern void TC_CoreAFunc_CBAR (void);
extern void TC_CoreAFunc_TTBR0 (void);
extern void TC_CoreAFunc_DACR (void);
extern void TC_CoreAFunc_SCTLR (void);
extern void TC_CoreAFunc_ACTRL (void);
extern void TC_CoreAFunc_MPIDR (void);
extern void TC_CoreAFunc_VBAR (void);
extern void TC_CoreAFunc_MVBAR (void);
extern void TC_CoreAFunc_FPU_Enable (void);
#endif
#if defined(__CORTEX_M)
extern void TC_MPU_SetClear (void);
extern void TC_MPU_Load (void);
#endif
#if defined(__CORTEX_A)
extern void TC_GenTimer_CNTFRQ (void);
extern void TC_GenTimer_CNTP_TVAL (void);
extern void TC_GenTimer_CNTP_CTL (void);
extern void TC_GenTimer_CNTPCT(void);
extern void TC_GenTimer_CNTP_CVAL(void);
#endif
#if defined(__CORTEX_M)
extern void TC_CML1Cache_EnDisableICache(void);
extern void TC_CML1Cache_EnDisableDCache(void);
extern void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void);
#elif defined(__CORTEX_A)
extern void TC_CAL1Cache_EnDisable(void);
extern void TC_CAL1Cache_EnDisableBTAC(void);
extern void TC_CAL1Cache_log2_up(void);
extern void TC_CAL1Cache_InvalidateDCacheAll(void);
extern void TC_CAL1Cache_CleanDCacheAll(void);
extern void TC_CAL1Cache_CleanInvalidateDCacheAll(void);
#endif
#endif /* __CMSIS_CV_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Include/cmsis_cv.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,289 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Typedefs.h
* Purpose: Test framework filetypes and structures description
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __TYPEDEFS_H__
#define __TYPEDEFS_H__
#include <stdint.h>
#include <stdarg.h>
#include <string.h>
#include <stdio.h>
typedef unsigned int BOOL;
#ifndef __TRUE
#define __TRUE 1
#endif
#ifndef __FALSE
#define __FALSE 0
#endif
#ifndef ENABLED
#define ENABLED 1
#endif
#ifndef DISABLED
#define DISABLED 0
#endif
#ifndef NULL
#ifdef __cplusplus // EC++
#define NULL 0
#else
#define NULL ((void *) 0)
#endif
#endif
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))
#if defined( __GNUC__ ) || defined ( __clang__ )
static const int PATH_DELIMITER = '/';
#else
static const int PATH_DELIMITER = '\\';
#endif
//lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename
//lint -emacro(613,__FILENAME__) null pointer is checked
#define __FILENAME__ ((strrchr(__FILE__, PATH_DELIMITER) != NULL) ? (strrchr(__FILE__, PATH_DELIMITER) + 1) : __FILE__)
/* Assertions and test results */
#define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc));
//lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter
//lint -emacro(613,ASSERT_TRUE) null pointer is checked
#define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U)
#endif /* __TYPEDEFS_H__ */
``` | /content/code_sandbox/CMSIS/CoreValidation/Include/CV_Typedefs.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 402 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Framework.h
* Purpose: Framework header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __FRAMEWORK_H__
#define __FRAMEWORK_H__
#include "CV_Typedefs.h"
#include "CV_Report.h"
/*your_sha256_hash-------------
* Test framework global definitions
*your_sha256_hash------------*/
/* Test case definition macro */
#define TCD(x, y) {x, #x, y}
/* Test case description structure */
typedef struct __TestCase {
void (*TestFunc)(void); /* Test function */
const char *TFName; /* Test function name string */
BOOL en; /* Test function enabled */
} TEST_CASE;
/* Test suite description structure */
typedef struct __TestSuite {
const char *FileName; /* Test module file name */
const char *Date; /* Compilation date */
const char *Time; /* Compilation time */
const char *ReportTitle; /* Title or name of module under test */
void (*Init)(void); /* Init function callback */
uint32_t TCBaseNum; /* Base number for test case numbering */
TEST_CASE *TC; /* Array of test cases */
uint32_t NumOfTC; /* Number of test cases (sz of TC array)*/
} TEST_SUITE;
/* Defined in user test module */
extern TEST_SUITE ts;
#endif /* __FRAMEWORK_H__ */
``` | /content/code_sandbox/CMSIS/CoreValidation/Include/CV_Framework.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 323 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Report.h
* Purpose: Report statistics and layout header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __REPORT_H__
#define __REPORT_H__
#include "CV_Config.h"
#include "CV_Typedefs.h"
/*your_sha256_hash-------------
* Test report global definitions
*your_sha256_hash------------*/
#define REP_TC_FAIL 0
#define REP_TC_WARN 1
#define REP_TC_PASS 2
#define REP_TC_NOEX 3
/* Test case result definition */
typedef enum {
PASSED = 0,
WARNING,
FAILED,
NOT_EXECUTED
} TC_RES;
/* Assertion result info */
typedef struct {
const char *module; /* Module name */
uint32_t line; /* Assertion line */
} AS_INFO;
/* Test case callback interface definition */
typedef struct {
BOOL (* Result) (TC_RES res);
BOOL (* Dbgi) (TC_RES res, const char *fn, uint32_t ln, char *desc);
} TC_ITF;
/* Assert interface to the report */
extern TC_ITF tcitf;
/* Assertion result buffer */
typedef struct {
AS_INFO passed[BUFFER_ASSERTIONS];
AS_INFO failed[BUFFER_ASSERTIONS];
AS_INFO warnings[BUFFER_ASSERTIONS];
} AS_T_INFO;
/* Assertion statistics */
typedef struct {
uint32_t passed; /* Total assertions passed */
uint32_t failed; /* Total assertions failed */
uint32_t warnings; /* Total assertions warnings */
AS_T_INFO info; /* Detailed assertion info */
} AS_STAT;
/* Test global statistics */
typedef struct {
uint32_t tests; /* Total test cases count */
uint32_t executed; /* Total test cases executed */
uint32_t passed; /* Total test cases passed */
uint32_t failed; /* Total test cases failed */
uint32_t warnings; /* Total test cases warnings */
AS_STAT assertions; /* Total assertions statistics */
} TEST_REPORT;
/* Test report interface */
typedef struct {
BOOL (* Init) (void);
BOOL (* Open) (const char *title, const char *date, const char *time, const char *fn);
BOOL (* Close) (void);
BOOL (* Open_TC) (uint32_t num, const char *fn);
BOOL (* Close_TC) (void);
} REPORT_ITF;
/* Test report statistics */
extern TEST_REPORT test_report;
/* Test report interface */
extern REPORT_ITF ritf;
/* Assertions and test results */
extern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc);
extern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond);
#endif /* __REPORT_H__ */
``` | /content/code_sandbox/CMSIS/CoreValidation/Include/CV_Report.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 624 |
```yaml
# yaml-language-server: $schema=path_to_url
layer:
# type: Target
description: Target setup
# packs:
# - pack: ARM::CMSIS
components:
# [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
- component: ARM::CMSIS:CORE
- component: Device:Startup&C Startup
misc:
- for-compiler: IAR
Link: [--config generic_cortex.icf]
groups:
- group: VHT/FVP
files:
- file: ./model_config.txt
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 143 |
```objective-c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 30. October 2017
* $Revision: V2.1.2
*
* Project: CMSIS-RTOS API
* Title: cmsis_os.h RTX header file
*
* Version 0.02
* Initial Proposal Phase
* Version 0.03
* osKernelStart added, optional feature: main started as thread
* osSemaphores have standard behavior
* osTimerCreate does not start the timer, added osTimerStart
* osThreadPass is renamed to osThreadYield
* Version 1.01
* Support for C++ interface
* - const attribute removed from the osXxxxDef_t typedefs
* - const attribute added to the osXxxxDef macros
* Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
* Added: osKernelInitialize
* Version 1.02
* Control functions for short timeouts in microsecond resolution:
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
* Removed: osSignalGet
* Version 2.0.0
* OS objects creation without macros (dynamic creation and resource allocation):
* - added: osXxxxNew functions which replace osXxxxCreate
* - added: osXxxxAttr_t structures
* - deprecated: osXxxxCreate functions, osXxxxDef_t structures
* - deprecated: osXxxxDef and osXxxx macros
* osStatus codes simplified and renamed to osStatus_t
* osEvent return structure deprecated
* Kernel:
* - added: osKernelInfo_t and osKernelGetInfo
* - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
* - added: osKernelLock, osKernelUnlock
* - added: osKernelSuspend, osKernelResume
* - added: osKernelGetTickCount, osKernelGetTickFreq
* - renamed osKernelSysTick to osKernelGetSysTimerCount
* - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
* - deprecated osKernelSysTickMicroSec
* Thread:
* - extended number of thread priorities
* - renamed osPrioriry to osPrioriry_t
* - replaced osThreadCreate with osThreadNew
* - added: osThreadGetName
* - added: osThreadState_t and osThreadGetState
* - added: osThreadGetStackSize, osThreadGetStackSpace
* - added: osThreadSuspend, osThreadResume
* - added: osThreadJoin, osThreadDetach, osThreadExit
* - added: osThreadGetCount, osThreadEnumerate
* - added: Thread Flags (moved from Signals)
* Signals:
* - renamed osSignals to osThreadFlags (moved to Thread Flags)
* - changed return value of Set/Clear/Wait functions
* - Clear function limited to current running thread
* - extended Wait function (options)
* - added: osThreadFlagsGet
* Event Flags:
* - added new independent object for handling Event Flags
* Delay and Wait functions:
* - added: osDelayUntil
* - deprecated: osWait
* Timer:
* - replaced osTimerCreate with osTimerNew
* - added: osTimerGetName, osTimerIsRunning
* Mutex:
* - extended: attributes (Recursive, Priority Inherit, Robust)
* - replaced osMutexCreate with osMutexNew
* - renamed osMutexWait to osMutexAcquire
* - added: osMutexGetName, osMutexGetOwner
* Semaphore:
* - extended: maximum and initial token count
* - replaced osSemaphoreCreate with osSemaphoreNew
* - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
* - added: osSemaphoreGetName, osSemaphoreGetCount
* Memory Pool:
* - using osMemoryPool prefix instead of osPool
* - replaced osPoolCreate with osMemoryPoolNew
* - extended osMemoryPoolAlloc (timeout)
* - added: osMemoryPoolGetName
* - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
* - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
* - added: osMemoryPoolDelete
* - deprecated: osPoolCAlloc
* Message Queue:
* - extended: fixed size message instead of a single 32-bit value
* - using osMessageQueue prefix instead of osMessage
* - replaced osMessageCreate with osMessageQueueNew
* - updated: osMessageQueuePut, osMessageQueueGet
* - added: osMessageQueueGetName
* - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
* - added: osMessageQueueGetCount, osMessageQueueGetSpace
* - added: osMessageQueueReset, osMessageQueueDelete
* Mail Queue:
* - deprecated (superseded by extended Message Queue functionality)
* Version 2.1.0
* Support for critical and uncritical sections (nesting safe):
* - updated: osKernelLock, osKernelUnlock
* - added: osKernelRestoreLock
* Updated Thread and Event Flags:
* - changed flags parameter and return type from int32_t to uint32_t
* Version 2.1.1
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetTickCount, osKernelGetTickFreq
* Changed Kernel Tick type to uint32_t:
* - updated: osKernelGetTickCount, osDelayUntil
* Version 2.1.2
* Additional functions allowed to be called from Interrupt Service Routines:
* - osKernelGetInfo, osKernelGetState
*your_sha256_hash-----------*/
#ifndef CMSIS_OS_H_
#define CMSIS_OS_H_
#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
#define osCMSIS_RTX 0x50003U ///< RTOS identification and version (main[31:16].sub[15:0])
#define osKernelSystemId "RTX V5.3" ///< RTOS identification string
#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
#define osFeature_Signals 31U ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
#if defined(__CC_ARM)
#define os_InRegs __value_in_regs
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define os_InRegs __attribute__((value_in_regs))
#else
#define os_InRegs
#endif
#if (osCMSIS >= 0x20000U)
#include "cmsis_os2.h"
#else
#include <stdint.h>
#include <stddef.h>
#endif
#include "rtx_os.h"
#ifdef __cplusplus
extern "C"
{
#endif
// ==== Enumerations, structures, defines ====
/// Priority values.
#if (osCMSIS < 0x20000U)
typedef enum {
osPriorityIdle = -3, ///< Priority: idle (lowest)
osPriorityLow = -2, ///< Priority: low
osPriorityBelowNormal = -1, ///< Priority: below normal
osPriorityNormal = 0, ///< Priority: normal (default)
osPriorityAboveNormal = +1, ///< Priority: above normal
osPriorityHigh = +2, ///< Priority: high
osPriorityRealtime = +3, ///< Priority: realtime (highest)
osPriorityError = 0x84, ///< System cannot determine priority or illegal priority.
osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osPriority;
#else
#define osPriority osPriority_t
#endif
/// Entry point of a thread.
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
typedef void (*os_ptimer) (void const *argument);
/// Timer type.
#if (osCMSIS < 0x20000U)
typedef enum {
osTimerOnce = 0, ///< One-shot timer.
osTimerPeriodic = 1 ///< Repeating timer.
} os_timer_type;
#else
#define os_timer_type osTimerType_t
#endif
/// Timeout value.
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
/// Status code values returned by CMSIS-RTOS functions.
#if (osCMSIS < 0x20000U)
typedef enum {
osOK = 0, ///< Function completed; no error or event occurred.
osEventSignal = 0x08, ///< Function completed; signal event occurred.
osEventMessage = 0x10, ///< Function completed; message event occurred.
osEventMail = 0x20, ///< Function completed; mail event occurred.
osEventTimeout = 0x40, ///< Function completed; timeout occurred.
osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
osErrorResource = 0x81, ///< Resource not available: a specified resource was not available.
osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period.
osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object.
osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority.
osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
osErrorValue = 0x86, ///< Value of a parameter is out of range.
osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits.
osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
} osStatus;
#else
typedef int32_t osStatus;
#define osEventSignal (0x08)
#define osEventMessage (0x10)
#define osEventMail (0x20)
#define osEventTimeout (0x40)
#define osErrorOS osError
#define osErrorTimeoutResource osErrorTimeout
#define osErrorISRRecursive (-126)
#define osErrorValue (-127)
#define osErrorPriority (-128)
#endif
// >>> the following data type definitions may be adapted towards a specific RTOS
/// Thread ID identifies the thread.
#if (osCMSIS < 0x20000U)
typedef void *osThreadId;
#else
#define osThreadId osThreadId_t
#endif
/// Timer ID identifies the timer.
#if (osCMSIS < 0x20000U)
typedef void *osTimerId;
#else
#define osTimerId osTimerId_t
#endif
/// Mutex ID identifies the mutex.
#if (osCMSIS < 0x20000U)
typedef void *osMutexId;
#else
#define osMutexId osMutexId_t
#endif
/// Semaphore ID identifies the semaphore.
#if (osCMSIS < 0x20000U)
typedef void *osSemaphoreId;
#else
#define osSemaphoreId osSemaphoreId_t
#endif
/// Pool ID identifies the memory pool.
typedef void *osPoolId;
/// Message ID identifies the message queue.
typedef void *osMessageQId;
/// Mail ID identifies the mail queue.
typedef void *osMailQId;
/// Thread Definition structure contains startup information of a thread.
#if (osCMSIS < 0x20000U)
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osPriority tpriority; ///< initial thread priority
uint32_t instances; ///< maximum number of instances of that thread function
uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
} osThreadDef_t;
#else
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osThreadAttr_t attr; ///< thread attributes
} osThreadDef_t;
#endif
/// Timer Definition structure contains timer parameters.
#if (osCMSIS < 0x20000U)
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
} osTimerDef_t;
#else
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
osTimerAttr_t attr; ///< timer attributes
} osTimerDef_t;
#endif
/// Mutex Definition structure contains setup information for a mutex.
#if (osCMSIS < 0x20000U)
typedef struct os_mutex_def {
uint32_t dummy; ///< dummy value
} osMutexDef_t;
#else
#define osMutexDef_t osMutexAttr_t
#endif
/// Semaphore Definition structure contains setup information for a semaphore.
#if (osCMSIS < 0x20000U)
typedef struct os_semaphore_def {
uint32_t dummy; ///< dummy value
} osSemaphoreDef_t;
#else
#define osSemaphoreDef_t osSemaphoreAttr_t
#endif
/// Definition structure for memory block allocation.
#if (osCMSIS < 0x20000U)
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
void *pool; ///< pointer to memory for pool
} osPoolDef_t;
#else
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
osMemoryPoolAttr_t attr; ///< memory pool attributes
} osPoolDef_t;
#endif
/// Definition structure for message queue.
#if (osCMSIS < 0x20000U)
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
void *pool; ///< memory array for messages
} osMessageQDef_t;
#else
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
osMessageQueueAttr_t attr; ///< message queue attributes
} osMessageQDef_t;
#endif
/// Definition structure for mail queue.
#if (osCMSIS < 0x20000U)
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for mail
} osMailQDef_t;
#else
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *mail; ///< pointer to mail
osMemoryPoolAttr_t mp_attr; ///< memory pool attributes
osMessageQueueAttr_t mq_attr; ///< message queue attributes
} osMailQDef_t;
#endif
/// Event structure contains detailed information about an event.
typedef struct {
osStatus status; ///< status code: event or error information
union {
uint32_t v; ///< message as 32-bit value
void *p; ///< message or mail as void pointer
int32_t signals; ///< signal flags
} value; ///< event value
union {
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
// ==== Kernel Management Functions ====
/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelInitialize (void);
#endif
/// Start the RTOS Kernel scheduler.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelStart (void);
#endif
/// Check if the RTOS kernel is already started.
/// \return 0 RTOS is not started, 1 RTOS is started.
#if (osCMSIS < 0x20000U)
int32_t osKernelRunning(void);
#endif
#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
/// Get the RTOS kernel system timer counter.
/// \return RTOS kernel system timer as 32-bit value
#if (osCMSIS < 0x20000U)
uint32_t osKernelSysTick (void);
#else
#define osKernelSysTick osKernelGetSysTimerCount
#endif
/// The RTOS kernel system timer frequency in Hz.
/// \note Reflects the system timer setting and is typically defined in a configuration file.
#if (osCMSIS < 0x20000U)
#define osKernelSysTickFrequency 100000000
#endif
/// Convert a microseconds value to a RTOS kernel system timer value.
/// \param microsec time value in microseconds.
/// \return time value normalized to the \ref osKernelSysTickFrequency
#if (osCMSIS < 0x20000U)
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
#else
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
#endif
#endif // System Timer available
// ==== Thread Management Functions ====
/// Create a Thread Definition with function, priority, and stack requirements.
/// \param name name of the thread function.
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
extern const osThreadDef_t os_thread_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osThreadDef(name, priority, instances, stacksz) \
const osThreadDef_t os_thread_def_##name = \
{ (name), (priority), (instances), (stacksz) }
#else
#define osThreadDef(name, priority, instances, stacksz) \
static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \
static osRtxThread_t os_thread_cb_##name __attribute__((section(".bss.os.thread.cb"))); \
const osThreadDef_t os_thread_def_##name = \
{ (name), \
{ NULL, osThreadDetached, \
(instances == 1) ? (&os_thread_cb_##name) : NULL,\
(instances == 1) ? osRtxThreadCbSize : 0U, \
((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
8*((stacksz+7)/8), \
(priority), 0U, 0U } }
#endif
#endif
/// Access a Thread definition.
/// \param name name of the thread definition object.
#define osThread(name) \
&os_thread_def_##name
/// Create a thread and add it to Active Threads and set it to state READY.
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
#if (osCMSIS < 0x20000U)
osThreadId osThreadGetId (void);
#endif
/// Change priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
#endif
/// Get current priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the specified thread.
#if (osCMSIS < 0x20000U)
osPriority osThreadGetPriority (osThreadId thread_id);
#endif
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadYield (void);
#endif
/// Terminate execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadTerminate (osThreadId thread_id);
#endif
// ==== Signal Management ====
/// Set the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that should be set.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
/// Clear the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event flag information or error code.
os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay).
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osDelay (uint32_t millisec);
#endif
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
os_InRegs osEvent osWait (uint32_t millisec);
#endif // Generic Wait available
// ==== Timer Management Functions ====
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
extern const osTimerDef_t os_timer_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osTimerDef(name, function) \
const osTimerDef_t os_timer_def_##name = { (function) }
#else
#define osTimerDef(name, function) \
static osRtxTimer_t os_timer_cb_##name __attribute__((section(".bss.os.timer.cb"))); \
const osTimerDef_t os_timer_def_##name = \
{ (function), { NULL, 0U, (&os_timer_cb_##name), osRtxTimerCbSize } }
#endif
#endif
/// Access a Timer definition.
/// \param name name of the timer object.
#define osTimer(name) \
&os_timer_def_##name
/// Create and Initialize a timer.
/// \param[in] timer_def timer object referenced with \ref osTimer.
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
#endif
/// Stop a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerStop (osTimerId timer_id);
#endif
/// Delete a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerDelete (osTimerId timer_id);
#endif
// ==== Mutex Management Functions ====
/// Define a Mutex.
/// \param name name of the mutex object.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
extern const osMutexDef_t os_mutex_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMutexDef(name) \
const osMutexDef_t os_mutex_def_##name = { 0 }
#else
#define osMutexDef(name) \
static osRtxMutex_t os_mutex_cb_##name __attribute__((section(".bss.os.mutex.cb"))); \
const osMutexDef_t os_mutex_def_##name = \
{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, (&os_mutex_cb_##name), osRtxMutexCbSize }
#endif
#endif
/// Access a Mutex definition.
/// \param name name of the mutex object.
#define osMutex(name) \
&os_mutex_def_##name
/// Create and Initialize a Mutex object.
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
/// Wait until a Mutex becomes available.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
#else
#define osMutexWait osMutexAcquire
#endif
/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexRelease (osMutexId mutex_id);
#endif
/// Delete a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexDelete (osMutexId mutex_id);
#endif
// ==== Semaphore Management Functions ====
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
/// Define a Semaphore object.
/// \param name name of the semaphore object.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
extern const osSemaphoreDef_t os_semaphore_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osSemaphoreDef(name) \
const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
#else
#define osSemaphoreDef(name) \
static osRtxSemaphore_t os_semaphore_cb_##name __attribute__((section(".bss.os.semaphore.cb"))); \
const osSemaphoreDef_t os_semaphore_def_##name = \
{ NULL, 0U, (&os_semaphore_cb_##name), osRtxSemaphoreCbSize }
#endif
#endif
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
#define osSemaphore(name) \
&os_semaphore_def_##name
/// Create and Initialize a Semaphore object.
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in] count maximum and initial number of available tokens.
/// \return semaphore ID for reference by other functions or NULL in case of error.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
/// Wait until a Semaphore token becomes available.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
/// Release a Semaphore token.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
#endif
/// Delete a Semaphore object.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
#endif
#endif // Semaphore available
// ==== Memory Pool Management Functions ====
#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
/// \brief Define a Memory Pool.
/// \param name name of the memory pool.
/// \param no maximum number of blocks (objects) in the memory pool.
/// \param type data type of a single block (object).
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
extern const osPoolDef_t os_pool_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osPoolDef(name, no, type) \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), NULL }
#else
#define osPoolDef(name, no, type) \
static osRtxMemoryPool_t os_mp_cb_##name __attribute__((section(".bss.os.mempool.cb"))); \
static uint32_t os_mp_data_##name[osRtxMemoryPoolMemSize((no),sizeof(type))/4] __attribute__((section(".bss.os.mempool.mem"))); \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), \
{ NULL, 0U, (&os_mp_cb_##name), osRtxMemoryPoolCbSize, \
(&os_mp_data_##name), sizeof(os_mp_data_##name) } }
#endif
#endif
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
#define osPool(name) \
&os_pool_def_##name
/// Create and Initialize a Memory Pool object.
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
/// Allocate a memory block from a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a Memory Pool and set memory block to zero.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolCAlloc (osPoolId pool_id);
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return status code that indicates the execution status of the function.
osStatus osPoolFree (osPoolId pool_id, void *block);
#endif // Memory Pool available
// ==== Message Queue Management Functions ====
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
/// \brief Create a Message Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
extern const osMessageQDef_t os_messageQ_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMessageQDef(name, queue_sz, type) \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), NULL }
#else
#define osMessageQDef(name, queue_sz, type) \
static osRtxMessageQueue_t os_mq_cb_##name __attribute__((section(".bss.os.msgqueue.cb"))); \
static uint32_t os_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(uint32_t))/4] __attribute__((section(".bss.os.msgqueue.mem"))); \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), \
{ NULL, 0U, (&os_mq_cb_##name), osRtxMessageQueueCbSize, \
(&os_mq_data_##name), sizeof(os_mq_data_##name) } }
#endif
#endif
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
#define osMessageQ(name) \
&os_messageQ_def_##name
/// Create and Initialize a Message Queue object.
/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
/// Put a Message to a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] info message information.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
/// Get a Message from a Queue or timeout if Queue is empty.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
#endif // Message Queue available
// ==== Mail Queue Management Functions ====
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
/// \brief Create a Mail Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of mails in the queue.
/// \param type data type of a single mail element.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
extern const osMailQDef_t os_mailQ_def_##name
#else // define the object
#if (osCMSIS < 0x20000U)
#define osMailQDef(name, queue_sz, type) \
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof(type), NULL }
#else
#define osMailQDef(name, queue_sz, type) \
static void *os_mail_p_##name[2] __attribute__((section(".bss.os"))); \
static osRtxMemoryPool_t os_mail_mp_cb_##name __attribute__((section(".bss.os.mempool.cb"))); \
static osRtxMessageQueue_t os_mail_mq_cb_##name __attribute__((section(".bss.os.msgqueue.cb"))); \
static uint32_t os_mail_mp_data_##name[osRtxMemoryPoolMemSize ((queue_sz),sizeof(type) )/4] __attribute__((section(".bss.os.mempool.mem"))); \
static uint32_t os_mail_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(void*))/4] __attribute__((section(".bss.os.msgqueue.mem"))); \
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof(type), (&os_mail_p_##name), \
{ NULL, 0U, (&os_mail_mp_cb_##name), osRtxMemoryPoolCbSize, \
(&os_mail_mp_data_##name), sizeof(os_mail_mp_data_##name) }, \
{ NULL, 0U, (&os_mail_mq_cb_##name), osRtxMessageQueueCbSize, \
(&os_mail_mq_data_##name), sizeof(os_mail_mq_data_##name) } }
#endif
#endif
/// \brief Access a Mail Queue Definition.
/// \param name name of the queue
#define osMailQ(name) \
&os_mailQ_def_##name
/// Create and Initialize a Mail Queue object.
/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
/// Allocate a memory block for mail from a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
/// Put a Mail into a Queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory with mail to put into a queue.
/// \return status code that indicates the execution status of the function.
osStatus osMailPut (osMailQId queue_id, const void *mail);
/// Get a Mail from a Queue or timeout if Queue is empty.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// Free a memory block by returning it to a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queue available
#ifdef __cplusplus
}
#endif
#endif // CMSIS_OS_H_
``` | /content/code_sandbox/CMSIS/RTOS2/RTX/Include1/cmsis_os.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 9,590 |
```c
/**************************************************************************//**
* @file system_ARMCM55.c
* @brief CMSIS Device System Source File for
* ARMCM55 Device
* @version V1.1.0
* @date 28. March 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#else
#error device not specified!
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM55.h"
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL ( 5000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (5U * XTAL)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Set low-power state for PDEPU */
/* 0b00 | ON, PDEPU is not in low-power state */
/* 0b01 | ON, but the clock is off */
/* 0b10 | RET(ention) */
/* 0b11 | OFF */
/* Clear ELPSTATE, value is 0b11 on Cold reset */
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
/* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
/* PDEPU ON, Clock OFF */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
__DSB();
__ISB();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 737 |
```c
/******************************************************************************
* @file startup_ARMCM55.c
* @brief CMSIS-Core Device Startup File for Cortex-M55 Device
* @version V1.1.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM55)
#include "ARMCM55.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,347 |
```c
/**************************************************************************//**
* @file system_ARMCM23.c
* @brief CMSIS Device System Source File for
* ARMCM23 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM23)
#include "ARMCM23.h"
#elif defined (ARMCM23_TZ)
#include "ARMCM23_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM23.h"
#endif
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 436 |
```linker script
/******************************************************************************
* @file gcc_arm.ld
* @brief GNU Linker Script for Cortex-M based device
* @version V2.2.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/*
*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*---------------------- Flash Configuration ----------------------------------
<h> Flash Configuration
<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__ROM_BASE = 0x00000000;
__ROM_SIZE = 0x00200000;
/*--------------------- Embedded RAM Configuration ----------------------------
<h> RAM Configuration
<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__RAM_BASE = 0x20000000;
__RAM_SIZE = 0x00200000;
/*--------------------- Stack / Heap Configuration ----------------------------
<h> Stack / Heap Configuration
<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__STACK_SIZE = 0x00000400;
__HEAP_SIZE = 0x00000C00;
/*
*-------------------- <<< end of configuration section >>> -------------------
*/
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
*/
__STACKSEAL_SIZE = 0;
MEMORY
{
FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __StackSeal (only if ARMv8-M stack sealing is used)
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/*
* SG veneers:
* All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
* must be set, either with the command line option --section-start or in a linker script,
* to indicate where to place these veneers in memory.
*/
/*
.gnu.sgstubs :
{
. = ALIGN(32);
} > FLASH
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
} > FLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
} > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned
*/
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to asure proper
* initialization during startup.
*/
/*
__etext2 = ALIGN (4);
.data2 : AT (__etext2)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;
} > RAM2
*/
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM AT > RAM
/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to asure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM2 AT > RAM2
*/
.heap (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM
.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM
PROVIDE(__stack = __StackTop);
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing uncomment '.stackseal' section
*/
/*
.stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM
*/
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,080 |
```c
/******************************************************************************
* @file startup_ARMCM23.c
* @brief CMSIS-Core Device Startup File for a Cortex-M23 Device
* @version V2.1.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM23)
#include "ARMCM23.h"
#elif defined (ARMCM23_TZ)
#include "ARMCM23_TZ.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,252 |
```linker script
/******************************************************************************
* @file gcc_arm.ld
* @brief GNU Linker Script for Cortex-M based device
* @version V2.2.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/*
*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*---------------------- Flash Configuration ----------------------------------
<h> Flash Configuration
<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__ROM_BASE = 0x00000000;
__ROM_SIZE = 0x00200000;
/*--------------------- Embedded RAM Configuration ----------------------------
<h> RAM Configuration
<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__RAM_BASE = 0x20000000;
__RAM_SIZE = 0x00200000;
/*--------------------- Stack / Heap Configuration ----------------------------
<h> Stack / Heap Configuration
<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__STACK_SIZE = 0x00000400;
__HEAP_SIZE = 0x00000C00;
/*
*-------------------- <<< end of configuration section >>> -------------------
*/
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
*/
__STACKSEAL_SIZE = 8;
MEMORY
{
FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __StackSeal (only if ARMv8-M stack sealing is used)
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/*
* SG veneers:
* All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
* must be set, either with the command line option --section-start or in a linker script,
* to indicate where to place these veneers in memory.
*/
.gnu.sgstubs :
{
. = ALIGN(32);
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
} > FLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
} > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned
*/
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to asure proper
* initialization during startup.
*/
/*
__etext2 = ALIGN (4);
.data2 : AT (__etext2)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;
} > RAM2
*/
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM AT > RAM
/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to asure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM2 AT > RAM2
*/
.heap (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM
.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM
PROVIDE(__stack = __StackTop);
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing uncomment '.stackseal' section
*/
.stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,076 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM55.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
* @version V1.0.0
* @date 20. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM55_H
#define PARTITION_ARMCM55_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point and Vector Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x0000122B
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
(defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM55_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,223 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM23.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM23_H
#define PARTITION_ARMCM23_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of single SysTick
*/
#define SCB_ICSR_INIT 0
/*
// <o> in a single SysTick implementation, SysTick is
// <0=>Secure
// <1=>Non-Secure
// <i> Value for SCB->ICSR register bit STTNS
// <i> only for single SysTick implementation
*/
#define SCB_ICSR_STTNS_VAL 0
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x0000122B
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM23_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 10,036 |
```c
/**************************************************************************//**
* @file system_ARMCM0plus.c
* @brief CMSIS Device System Source File for
* ARMCM0plus Device
* @version V1.0.1
* @date 05. September 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "ARMCM0plus.h"
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 335 |
```groff
/******************************************************************************
* @file startup_ARMCM0plus.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM0P)
#include "ARMCM0plus.h"
#elif defined (ARMCM0P_MPU)
#include "ARMCM0plus_MPU.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,133 |
```batchfile
/****************************************************************************/
/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */
/* */
/* Description: This file is a sample command file that can be used */
/* for linking programs built with the TI Arm Clang */
/* Compiler. Use it as a guideline; you may want to change */
/* the allocation scheme according to the size of your */
/* program and the memory layout of your target system. */
/* */
/****************************************************************************/
-c /* LINK USING C CONVENTIONS */
-stack 0x4000 /* SOFTWARE STACK SIZE */
-heap 0x4000 /* HEAP AREA SIZE */
--args 0x1000
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */
P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */
D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */
}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
SECTIONS
{
.intvecs : {} > 0x0 /* INTERRUPT VECTORS */
.bss : {} > D_MEM /* GLOBAL & STATIC VARS */
.data : {} > D_MEM
.sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */
.stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */
.text : {} > P_MEM /* CODE */
.cinit : {} > P_MEM /* INITIALIZATION TABLES */
.const : {} > P_MEM /* CONSTANT DATA */
.rodata : {} > P_MEM, palign(4)
.init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */
.TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd | batchfile | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 456 |
```c
/******************************************************************************
* @file startup_ARMCM0plus.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM0P)
#include "ARMCM0plus.h"
#elif defined (ARMCM0P_MPU)
#include "ARMCM0plus_MPU.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,133 |
```c
/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device
* @version V1.0.0
* @date 09. July 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "ARMCM0.h"
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 263 |
```c
/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM0)
#include "ARMCM0.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,107 |
```groff
/******************************************************************************
* @file startup_ARMCM0.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM0)
#include "ARMCM0.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10..31 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,107 |
```c
/**************************************************************************//**
* @file system_ARMCM35P.c
* @brief CMSIS Device System Source File for
* ARMCM35P Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM35P)
#include "ARMCM35P.h"
#elif defined (ARMCM35P_TZ)
#include "ARMCM35P_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM35P.h"
#endif
#elif defined (ARMCM35P_DSP_FP)
#include "ARMCM35P_DSP_FP.h"
#elif defined (ARMCM35P_DSP_FP_TZ)
#include "ARMCM35P_DSP_FP_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM35P.h"
#endif
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 622 |
```c
/******************************************************************************
* @file startup_ARMCM35P.c
* @brief CMSIS-Core Device Startup File for Cortex-M35P Device
* @version V2.1.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM35P)
#include "ARMCM35P.h"
#elif defined (ARMCM35P_TZ)
#include "ARMCM35P_TZ.h"
#elif defined (ARMCM35P_DSP_FP)
#include "ARMCM35P_DSP_FP.h"
#elif defined (ARMCM35P_DSP_FP_TZ)
#include "ARMCM35P_DSP_FP_TZ.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,421 |
```c
/******************************************************************************
* @file startup_ARMCM4.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,218 |
```groff
/******************************************************************************
* @file startup_ARMCM4.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,218 |
```c
/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM4)
#include "ARMCM4.h"
#elif defined (ARMCM4_FP)
#include "ARMCM4_FP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 464 |
```yaml
# yaml-language-server: $schema=path_to_url
layer:
# type: Target
description: Target setup
# packs:
# - pack: ARM::CMSIS
components:
# [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]
- component: ARM::CMSIS:CORE
- component: Device:Startup
- component: Device:IRQ Controller:GIC
misc:
- for-compiler: IAR
Link: [--config generic_cortex.icf]
groups:
- group: VHT/FVP
files:
- file: ./model_config.txt
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 153 |
```c
/******************************************************************************
* @file system_ARMCA9.c
* @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System Initialization
*your_sha256_hash------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 461 |
```c
/**************************************************************************//**
* @file mmu_ARMCA9.c
* @brief MMU Configuration for Arm Cortex-A9 Device Series
* @version V1.2.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
| FLAG SYNC | Device Memory
0xfffff000 |--------------------------| ------------
| Fault | Fault
0xfff00000 |--------------------------| ------------
| | Normal
| |
| Daughterboard |
| memory |
| |
0x80505000 |--------------------------| ------------
|TTB (L2 Sync Flags ) 4k | Normal
0x80504C00 |--------------------------| ------------
|TTB (L2 Peripherals-B) 16k| Normal
0x80504800 |--------------------------| ------------
|TTB (L2 Peripherals-A) 16k| Normal
0x80504400 |--------------------------| ------------
|TTB (L2 Priv Periphs) 4k | Normal
0x80504000 |--------------------------| ------------
| TTB (L1 Descriptors) | Normal
0x80500000 |--------------------------| ------------
| Stack | Normal
|--------------------------| ------------
| Heap | Normal
0x80400000 |--------------------------| ------------
| ZI Data | Normal
0x80300000 |--------------------------| ------------
| RW Data | Normal
0x80200000 |--------------------------| ------------
| RO Data | Normal
|--------------------------| ------------
| RO Code | USH Normal
0x80000000 |--------------------------| ------------
| Daughterboard | Fault
| HSB AXI buses |
0x40000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x2c002000 |--------------------------| ------------
| Private Address | Device Memory
0x2c000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x20000000 |--------------------------| ------------
| Peripherals | Device Memory RW/RO
| | & Fault
0x00000000 |--------------------------|
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
#include "ARMCA9.h"
#include "mem_ARMCA9.h"
// TTB base address
#define TTB_BASE ((uint32_t*)__TTB_BASE)
// L2 table pointers
//----------------------------------------
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
//--------------------- PERIPHERALS -------------------
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
//--------------------- SYNC FLAGS --------------------
#define FLAG_SYNC 0xFFFFF000
#define F_SYNC_BASE 0xFFF00000 //1M aligned
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
//Create 4GB of faulting entries
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Define Image
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
//--------------------- PERIPHERALS -------------------
MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define private address space entry.
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry. Uncomment if PL310 is present
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define synchronization space entry.
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x1 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x01 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x0 (Inner WB WA) */
__set_TTBR0(__TTB_BASE | 0x48);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,712 |
```objective-c
/**************************************************************************//**
* @file mem_ARMCA9.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.1.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __MEM_ARMCA9_H
#define __MEM_ARMCA9_H
/*your_sha256_hash------------
User Stack & Heap size definition
*your_sha256_hash------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// </h>
*your_sha256_hash------------*/
#define __ROM_BASE 0x80000000
#define __ROM_SIZE 0x00200000
/*--------------------- RAM Configuration -----------------------------------
// <h> RAM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// <h> Data Sections
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// <h> Stack / Heap Configuration
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Exceptional Modes
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// </h>
// </h>
*your_sha256_hash------------*/
#define __RAM_BASE 0x80200000
#define __RAM_SIZE 0x00200000
#define __RW_DATA_SIZE 0x00100000
#define __ZI_DATA_SIZE 0x000F0000
#define __STACK_SIZE 0x00001000
#define __HEAP_SIZE 0x00008000
#define __UND_STACK_SIZE 0x00000100
#define __ABT_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
/*your_sha256_hash------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
// <i> The TLB L2 entries are placed after the L1 in the MMU config
// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*your_sha256_hash------------*/
#define __TTB_BASE 0x80500000
#define __TTB_SIZE 0x00005000
#endif /* __MEM_ARMCA9_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 925 |
```objective-c
/******************************************************************************
* @file system_ARMCA9.h
* @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __SYSTEM_ARMCA9_H
#define __SYSTEM_ARMCA9_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_ARMCA9_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 262 |
```linker script
#include "mem_ARMCA9.h"
MEMORY
{
ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
Image$$VECTORS$$Base = .;
* (RESET)
KEEP(*(.isr_vector))
Image$$VECTORS$$Limit = .;
*(SVC_TABLE)
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > ROM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
__copy_table_end__ = .;
} > ROM
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > ROM
__etext = .;
.ttb :
{
Image$$TTB$$ZI$$Base = .;
. += __TTB_SIZE;
Image$$TTB$$ZI$$Limit = .;
} > L_TTB
.data :
{
Image$$RW_DATA$$Base = .;
__data_start__ = .;
*(vtable)
*(.data*)
Image$$RW_DATA$$Limit = .;
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss ALIGN(0x400):
{
Image$$ZI_DATA$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$ZI_DATA$$Limit = .;
__end__ = .;
end = __end__;
} > RAM AT > RAM
#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
.heap (NOLOAD):
{
. = ALIGN(8);
Image$$HEAP$$ZI$$Base = .;
. += __HEAP_SIZE;
Image$$HEAP$$ZI$$Limit = .;
__HeapLimit = .;
} > RAM
#endif
.stack (NOLOAD):
{
. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
Image$$SYS_STACK$$ZI$$Base = .;
. += __STACK_SIZE;
Image$$SYS_STACK$$ZI$$Limit = .;
__stack = .;
Image$$FIQ_STACK$$ZI$$Base = .;
. += __FIQ_STACK_SIZE;
Image$$FIQ_STACK$$ZI$$Limit = .;
Image$$IRQ_STACK$$ZI$$Base = .;
. += __IRQ_STACK_SIZE;
Image$$IRQ_STACK$$ZI$$Limit = .;
Image$$SVC_STACK$$ZI$$Base = .;
. += __SVC_STACK_SIZE;
Image$$SVC_STACK$$ZI$$Limit = .;
Image$$ABT_STACK$$ZI$$Base = .;
. += __ABT_STACK_SIZE;
Image$$ABT_STACK$$ZI$$Limit = .;
Image$$UND_STACK$$ZI$$Base = .;
. += __UND_STACK_SIZE;
Image$$UND_STACK$$ZI$$Limit = .;
} > RAM
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,230 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM35P.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P
* @version V1.0.0
* @date 03. September 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM35P_H
#define PARTITION_ARMCM35P_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x0000122B
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM35P_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,190 |
```gas
/******************************************************************************
* @file startup_ARMCA9.s
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 01 Nov 2017
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
MODULE ?startup_ARMCA9
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
PUBLIC Reset_Handler
PUBWEAK Undef_Handler
PUBWEAK SVC_Handler
PUBWEAK PAbt_Handler
PUBWEAK DAbt_Handler
PUBWEAK IRQ_Handler
PUBWEAK FIQ_Handler
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION USR_STACK:DATA:NOROOT(3)
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
section RESET:CODE:NOROOT(2)
PUBLIC Vectors
Vectors:
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
section .text:CODE:NOROOT(2)
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
EXTERN SystemInit
EXTERN __iar_program_start
Reset_Handler:
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5
ANDS R0, R0, #3
goToSleep:
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exception mode
CPS #0x11
LDR SP, =SFE(FIQ_STACK)
CPS #0x12
LDR SP, =SFE(IRQ_STACK)
CPS #0x13
LDR SP, =SFE(SVC_STACK)
CPS #0x17
LDR SP, =SFE(ABT_STACK)
CPS #0x1B
LDR SP, =SFE(UND_STACK)
CPS #0x1F
LDR SP, =SFE(USR_STACK)
// Call SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __iar_program_start
BL __iar_program_start
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
Undef_Handler:
SVC_Handler:
PAbt_Handler:
DAbt_Handler:
IRQ_Handler:
FIQ_Handler:
Default_Handler:
B .
END
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,105 |
```c
/******************************************************************************
* @file startup_ARMCA9.c
* @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
* @version V1.0.1
* @date 10. January 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <ARMCA9.h>
/*your_sha256_hash------------
Definitions
*your_sha256_hash------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
void Default_Handler(void) __attribute__ ((noreturn));
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
#elif defined ( __GNUC__ )
"LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n"
#else
#error Unknown compiler.
#endif
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"BL __main \n"
#elif defined ( __GNUC__ )
"BL _start \n"
#else
#error Unknown compiler.
#endif
);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void) {
while(1);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,536 |
```c
/******************************************************************************
* @file startup_ARMCM7.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,236 |
```c
/**************************************************************************//**
* @file system_ARMCM7.c
* @brief CMSIS Device System Source File for
* ARMCM7 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 482 |
```groff
/******************************************************************************
* @file startup_ARMCM7.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM7)
#include "ARMCM7.h"
#elif defined (ARMCM7_SP)
#include "ARMCM7_SP.h"
#elif defined (ARMCM7_DP)
#include "ARMCM7_DP.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,236 |
```c
/******************************************************************************
* @file startup_ARMCM85.c
* @brief CMSIS Device Startup File for ARMCM85 Device
* @version V1.0.0
* @date 07. February 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM85)
#include "ARMCM85.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
extern uint32_t __STACK_SEAL;
#endif
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
SecureFault_Handler, /* -9 Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 480 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
__set_PSP((uint32_t)(&__INITIAL_SP));
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
__set_PSPLIM((uint32_t)(&__STACK_LIMIT));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
#endif
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,346 |
```c
/**************************************************************************//**
* @file system_ARMCM85.c
* @brief CMSIS Device System Source File for ARMCM85 Device
* @version V1.0.0
* @date 30. March 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM85)
#include "ARMCM85.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM85.h"
#endif
#else
#error device not specified!
#endif
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
#endif
/* Set CPDLPSTATE.RLPSTATE to 0
Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk );
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
/* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
/* PDEPU ON, Clock OFF */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* Enable Loop and branch info cache */
SCB->CCR |= SCB_CCR_LOB_Msk;
/* Enable Branch Prediction */
SCB->CCR |= SCB_CCR_BP_Msk;
__DSB();
__ISB();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 762 |
```groff
/******************************************************************************
* @file system_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System Initialization
*your_sha256_hash------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 461 |
```linker script
#include "mem_ARMCA5.h"
MEMORY
{
ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
Image$$VECTORS$$Base = .;
* (RESET)
KEEP(*(.isr_vector))
Image$$VECTORS$$Limit = .;
*(SVC_TABLE)
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > ROM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
__copy_table_end__ = .;
} > ROM
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > ROM
__etext = .;
.ttb :
{
Image$$TTB$$ZI$$Base = .;
. += __TTB_SIZE;
Image$$TTB$$ZI$$Limit = .;
} > L_TTB
.data :
{
Image$$RW_DATA$$Base = .;
__data_start__ = .;
*(vtable)
*(.data*)
Image$$RW_DATA$$Limit = .;
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss ALIGN(0x400):
{
Image$$ZI_DATA$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$ZI_DATA$$Limit = .;
__end__ = .;
end = __end__;
} > RAM AT > RAM
#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
.heap (NOLOAD):
{
. = ALIGN(8);
Image$$HEAP$$ZI$$Base = .;
. += __HEAP_SIZE;
Image$$HEAP$$ZI$$Limit = .;
__HeapLimit = .;
} > RAM
#endif
.stack (NOLOAD):
{
. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
Image$$SYS_STACK$$ZI$$Base = .;
. += __STACK_SIZE;
Image$$SYS_STACK$$ZI$$Limit = .;
__stack = .;
Image$$FIQ_STACK$$ZI$$Base = .;
. += __FIQ_STACK_SIZE;
Image$$FIQ_STACK$$ZI$$Limit = .;
Image$$IRQ_STACK$$ZI$$Base = .;
. += __IRQ_STACK_SIZE;
Image$$IRQ_STACK$$ZI$$Limit = .;
Image$$SVC_STACK$$ZI$$Base = .;
. += __SVC_STACK_SIZE;
Image$$SVC_STACK$$ZI$$Limit = .;
Image$$ABT_STACK$$ZI$$Base = .;
. += __ABT_STACK_SIZE;
Image$$ABT_STACK$$ZI$$Limit = .;
Image$$UND_STACK$$ZI$$Base = .;
. += __UND_STACK_SIZE;
Image$$UND_STACK$$ZI$$Limit = .;
} > RAM
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,230 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM85.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
* @version V1.0.0
* @date 07. March 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM85_H
#define PARTITION_ARMCM85_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point and Vector Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
(defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM85_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,467 |
```gas
/******************************************************************************
* @file startup_ARMCA9.s
* @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
* @version V1.00
* @date 01 Nov 2017
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
MODULE ?startup_ARMCA5
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
PUBLIC Reset_Handler
PUBWEAK Undef_Handler
PUBWEAK SVC_Handler
PUBWEAK PAbt_Handler
PUBWEAK DAbt_Handler
PUBWEAK IRQ_Handler
PUBWEAK FIQ_Handler
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION USR_STACK:DATA:NOROOT(3)
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
section RESET:CODE:NOROOT(2)
PUBLIC Vectors
Vectors:
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
section .text:CODE:NOROOT(4)
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
EXTERN SystemInit
EXTERN __iar_program_start
Reset_Handler:
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5
ANDS R0, R0, #3
goToSleep:
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exception mode
CPS #0x11
LDR SP, =SFE(FIQ_STACK)
CPS #0x12
LDR SP, =SFE(IRQ_STACK)
CPS #0x13
LDR SP, =SFE(SVC_STACK)
CPS #0x17
LDR SP, =SFE(ABT_STACK)
CPS #0x1B
LDR SP, =SFE(UND_STACK)
CPS #0x1F
LDR SP, =SFE(USR_STACK)
// Call SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __iar_program_start
BL __iar_program_start
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
Undef_Handler:
SVC_Handler:
PAbt_Handler:
DAbt_Handler:
IRQ_Handler:
FIQ_Handler:
Default_Handler:
B .
END
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,106 |
```c
/******************************************************************************
* @file startup_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.0.1
* @date 10. January 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <ARMCA5.h>
/*your_sha256_hash------------
Definitions
*your_sha256_hash------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
void Default_Handler(void) __attribute__ ((noreturn));
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
#elif defined ( __GNUC__ )
"LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n"
#else
#error Unknown compiler.
#endif
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"BL __main \n"
#elif defined ( __GNUC__ )
"BL _start \n"
#else
#error Unknown compiler.
#endif
);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void) {
while(1);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,536 |
```groff
/******************************************************************************
* @file startup_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.0.1
* @date 10. January 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <ARMCA5.h>
/*your_sha256_hash------------
Definitions
*your_sha256_hash------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
void Default_Handler(void) __attribute__ ((noreturn));
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
"BL __main \n"
);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void) {
while(1);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,435 |
```objective-c
/******************************************************************************
* @file system_ARMCA5.h
* @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __SYSTEM_ARMCA5_H
#define __SYSTEM_ARMCA5_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_ARMCA5_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 262 |
```c
/**************************************************************************//**
* @file mmu_ARMCA5.c
* @brief MMU Configuration for ARM Cortex-A5 Device Series
* @version V1.2.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
| FLAG SYNC | Device Memory
0xfffff000 |--------------------------| ------------
| Fault | Fault
0xfff00000 |--------------------------| ------------
| | Normal
| |
| Daughterboard |
| memory |
| |
0x80505000 |--------------------------| ------------
|TTB (L2 Sync Flags ) 4k | Normal
0x80504C00 |--------------------------| ------------
|TTB (L2 Peripherals-B) 16k| Normal
0x80504800 |--------------------------| ------------
|TTB (L2 Peripherals-A) 16k| Normal
0x80504400 |--------------------------| ------------
|TTB (L2 Priv Periphs) 4k | Normal
0x80504000 |--------------------------| ------------
| TTB (L1 Descriptors) | Normal
0x80500000 |--------------------------| ------------
| Stack | Normal
|--------------------------| ------------
| Heap | Normal
0x80400000 |--------------------------| ------------
| ZI Data | Normal
0x80300000 |--------------------------| ------------
| RW Data | Normal
0x80200000 |--------------------------| ------------
| RO Data | Normal
|--------------------------| ------------
| RO Code | USH Normal
0x80000000 |--------------------------| ------------
| Daughterboard | Fault
| HSB AXI buses |
0x40000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x2c002000 |--------------------------| ------------
| Private Address | Device Memory
0x2c000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x20000000 |--------------------------| ------------
| Peripherals | Device Memory RW/RO
| | & Fault
0x00000000 |--------------------------|
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
#include "ARMCA5.h"
#include "mem_ARMCA5.h"
// TTB base address
#define TTB_BASE ((uint32_t*)__TTB_BASE)
// L2 table pointers
//----------------------------------------
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
//--------------------- PERIPHERALS -------------------
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
//--------------------- SYNC FLAGS --------------------
#define FLAG_SYNC 0xFFFFF000
#define F_SYNC_BASE 0xFFF00000 //1M aligned
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
//Create 4GB of faulting entries
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Define Image
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
//--------------------- PERIPHERALS -------------------
MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define private address space entry.
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry. Uncomment if PL310 is present
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define synchronization space entry.
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x1 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x01 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x0 (Inner WB WA) */
__set_TTBR0(__TTB_BASE | 0x48);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,712 |
```c
/******************************************************************************
* @file system_ARMCA5.c
* @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System Initialization
*your_sha256_hash------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 461 |
```objective-c
/**************************************************************************//**
* @file mem_ARMCA5.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.1.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __MEM_ARMCA5_H
#define __MEM_ARMCA5_H
/*your_sha256_hash------------
User Stack & Heap size definition
*your_sha256_hash------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// </h>
*your_sha256_hash------------*/
#define __ROM_BASE 0x80000000
#define __ROM_SIZE 0x00200000
/*--------------------- RAM Configuration -----------------------------------
// <h> RAM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// <h> Data Sections
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// <h> Stack / Heap Configuration
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Exceptional Modes
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// </h>
// </h>
*your_sha256_hash------------*/
#define __RAM_BASE 0x80200000
#define __RAM_SIZE 0x00200000
#define __RW_DATA_SIZE 0x00100000
#define __ZI_DATA_SIZE 0x000F0000
#define __STACK_SIZE 0x00001000
#define __HEAP_SIZE 0x00008000
#define __UND_STACK_SIZE 0x00000100
#define __ABT_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
/*your_sha256_hash------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
// <i> The TLB L2 entries are placed after the L1 in the MMU config
// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*your_sha256_hash------------*/
#define __TTB_BASE 0x80500000
#define __TTB_SIZE 0x00005000
#endif /* __MEM_ARMCA5_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 925 |
```linker script
/******************************************************************************
* @file gcc_arm.ld
* @brief GNU Linker Script for Cortex-M based device
* @version V2.2.0
* @date 16. December 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/*
*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*---------------------- Flash Configuration ----------------------------------
<h> Flash Configuration
<o0> Flash Base Address <0x0-0xFFFFFFFF:8>
<o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__ROM_BASE = 0x00200000;
__ROM_SIZE = 0x00200000;
/*--------------------- Embedded RAM Configuration ----------------------------
<h> RAM Configuration
<o0> RAM Base Address <0x0-0xFFFFFFFF:8>
<o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__RAM_BASE = 0x20200000;
__RAM_SIZE = 0x00200000;
/*--------------------- Stack / Heap Configuration ----------------------------
<h> Stack / Heap Configuration
<o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
</h>
your_sha256_hash-------------*/
__STACK_SIZE = 0x00000400;
__HEAP_SIZE = 0x00000C00;
/*
*-------------------- <<< end of configuration section >>> -------------------
*/
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
*/
__STACKSEAL_SIZE = 0;
MEMORY
{
FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __StackSeal (only if ARMv8-M stack sealing is used)
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
/*
* SG veneers:
* All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
* must be set, either with the command line option --section-start or in a linker script,
* to indicate where to place these veneers in memory.
*/
/*
.gnu.sgstubs :
{
. = ALIGN(32);
} > FLASH
*/
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG ((__data_end__ - __data_start__) / 4)
/* Add each additional data section here */
/*
LONG (__etext2)
LONG (__data2_start__)
LONG ((__data2_end__ - __data2_start__) / 4)
*/
__copy_table_end__ = .;
} > FLASH
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
/* Add each additional bss section here */
/*
LONG (__bss2_start__)
LONG ((__bss2_end__ - __bss2_start__) / 4)
*/
__zero_table_end__ = .;
} > FLASH
/**
* Location counter can end up 2byte aligned with narrow Thumb code but
* __etext is assumed by startup code to be the LMA of a section in RAM
* which must be 4byte aligned
*/
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data)
*(.data.*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
/*
* Secondary data section, optional
*
* Remember to add each additional data section
* to the .copy.table above to asure proper
* initialization during startup.
*/
/*
__etext2 = ALIGN (4);
.data2 : AT (__etext2)
{
. = ALIGN(4);
__data2_start__ = .;
*(.data2)
*(.data2.*)
. = ALIGN(4);
__data2_end__ = .;
} > RAM2
*/
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM AT > RAM
/*
* Secondary bss section, optional
*
* Remember to add each additional bss section
* to the .zero.table above to asure proper
* initialization during startup.
*/
/*
.bss2 :
{
. = ALIGN(4);
__bss2_start__ = .;
*(.bss2)
*(.bss2.*)
. = ALIGN(4);
__bss2_end__ = .;
} > RAM2 AT > RAM2
*/
.heap (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
. = . + __HEAP_SIZE;
. = ALIGN(8);
__HeapLimit = .;
} > RAM
.stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackLimit = .;
. = . + __STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
} > RAM
PROVIDE(__stack = __StackTop);
/* ARMv8-M stack sealing:
to use ARMv8-M stack sealing uncomment '.stackseal' section
*/
/*
.stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
{
. = ALIGN(8);
__StackSeal = .;
. = . + 8;
. = ALIGN(8);
} > RAM
*/
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,080 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM23.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM23_H
#define PARTITION_ARMCM23_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of single SysTick
*/
#define SCB_ICSR_INIT 0
/*
// <o> in a single SysTick implementation, SysTick is
// <0=>Secure
// <1=>Non-Secure
// <i> Value for SCB->ICSR register bit STTNS
// <i> only for single SysTick implementation
*/
#define SCB_ICSR_STTNS_VAL 0
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM23_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 10,035 |
```groff
/**************************************************************************//**
* @file system_ARMCM3.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device
* @version V1.0.1
* @date 15. November 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "ARMCM3.h"
/*your_sha256_hash------------
Define clocks
*your_sha256_hash------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System initialization function
*your_sha256_hash------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
#endif
SystemCoreClock = SYSTEM_CLOCK;
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 332 |
```groff
/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM3)
#include "ARMCM3.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,200 |
```c
/******************************************************************************
* @file startup_ARMCM3.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
* @version V2.0.3
* @date 31. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#if defined (ARMCM3)
#include "ARMCM3.h"
#else
#error device not specified!
#endif
/*your_sha256_hash------------
External References
*your_sha256_hash------------*/
extern uint32_t __INITIAL_SP;
extern __NO_RETURN void __PROGRAM_START(void);
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler (void);
void Default_Handler(void);
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector table
*your_sha256_hash------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
MemManage_Handler, /* -12 MPU Fault Handler */
BusFault_Handler, /* -11 Bus Fault Handler */
UsageFault_Handler, /* -10 Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVC Handler */
DebugMon_Handler, /* -4 Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
__NO_RETURN void Reset_Handler(void)
{
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wmissing-noreturn"
#endif
/*your_sha256_hash------------
Hard Fault Handler
*your_sha256_hash------------*/
void HardFault_Handler(void)
{
while(1);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void)
{
while(1);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,200 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM33.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
* @version V1.1.1
* @date 12. March 2019
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM33_H
#define PARTITION_ARMCM33_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x0000122B
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM33_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,185 |
```groff
/******************************************************************************
* @file system_ARMCA7.c
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System Initialization
*your_sha256_hash------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 461 |
```c
/******************************************************************************
* @file startup_ARMCA7.c
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.0.1
* @date 10. January 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <ARMCA7.h>
/*your_sha256_hash------------
Definitions
*your_sha256_hash------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
void Default_Handler(void) __attribute__ ((noreturn));
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
#elif defined ( __GNUC__ )
"LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n"
#else
#error Unknown compiler.
#endif
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
"BL __main \n"
#elif defined ( __GNUC__ )
"BL _start \n"
#else
#error Unknown compiler.
#endif
);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void) {
while(1);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,536 |
```objective-c
/**************************************************************************//**
* @file mem_ARMCA7.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.1.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __MEM_ARMCA7_H
#define __MEM_ARMCA7_H
/*your_sha256_hash------------
User Stack & Heap size definition
*your_sha256_hash------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// </h>
*your_sha256_hash------------*/
#define __ROM_BASE 0x80000000
#define __ROM_SIZE 0x00200000
/*--------------------- RAM Configuration -----------------------------------
// <h> RAM Configuration
// <i> For compatibility with MMU config the sections must be multiple of 1MB
// <o0> RAM Base Address <0x0-0xFFFFFFFF:0x100000>
// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>
// <h> Data Sections
// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// <h> Stack / Heap Configuration
// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <h> Exceptional Modes
// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
// </h>
// </h>
*your_sha256_hash------------*/
#define __RAM_BASE 0x80200000
#define __RAM_SIZE 0x00200000
#define __RW_DATA_SIZE 0x00100000
#define __ZI_DATA_SIZE 0x000F0000
#define __STACK_SIZE 0x00001000
#define __HEAP_SIZE 0x00008000
#define __UND_STACK_SIZE 0x00000100
#define __ABT_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
/*your_sha256_hash------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned
// <i> The TLB L2 entries are placed after the L1 in the MMU config
// <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*your_sha256_hash------------*/
#define __TTB_BASE 0x80500000
#define __TTB_SIZE 0x00005000
#endif /* __MEM_ARMCA7_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 925 |
```groff
/******************************************************************************
* @file startup_ARMCA7.c
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.0.1
* @date 10. January 2021
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <ARMCA7.h>
/*your_sha256_hash------------
Definitions
*your_sha256_hash------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*your_sha256_hash------------
Internal References
*your_sha256_hash------------*/
void Vectors (void) __attribute__ ((naked, section("RESET")));
void Reset_Handler (void) __attribute__ ((naked));
void Default_Handler(void) __attribute__ ((noreturn));
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
void Vectors(void) {
__ASM volatile(
"LDR PC, =Reset_Handler \n"
"LDR PC, =Undef_Handler \n"
"LDR PC, =SVC_Handler \n"
"LDR PC, =PAbt_Handler \n"
"LDR PC, =DAbt_Handler \n"
"NOP \n"
"LDR PC, =IRQ_Handler \n"
"LDR PC, =FIQ_Handler \n"
);
}
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
void Reset_Handler(void) {
__ASM volatile(
// Mask interrupts
"CPSID if \n"
// Put any cores other than 0 to sleep
"MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
"ANDS R0, R0, #3 \n"
"goToSleep: \n"
"WFINE \n"
"BNE goToSleep \n"
// Reset SCTLR Settings
"MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
"BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
"BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
"BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
"BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
"BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
"MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
"ISB \n"
// Configure ACTLR
"MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
"ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
"MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
"LDR R0, =Vectors \n"
"MCR p15, 0, R0, c12, c0, 0 \n"
// Setup Stack for each exceptional mode
"CPS #0x11 \n"
"LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
"CPS #0x12 \n"
"LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
"CPS #0x13 \n"
"LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
"CPS #0x17 \n"
"LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
"CPS #0x1B \n"
"LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
"CPS #0x1F \n"
"LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
// Call SystemInit
"BL SystemInit \n"
// Unmask interrupts
"CPSIE if \n"
// Call __main
"BL __main \n"
);
}
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
void Default_Handler(void) {
while(1);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 | groff | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,435 |
```linker script
#include "mem_ARMCA7.h"
MEMORY
{
ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE
RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
}
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
Image$$VECTORS$$Base = .;
* (RESET)
KEEP(*(.isr_vector))
Image$$VECTORS$$Limit = .;
*(SVC_TABLE)
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > ROM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
__copy_table_end__ = .;
} > ROM
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > ROM
__etext = .;
.ttb :
{
Image$$TTB$$ZI$$Base = .;
. += __TTB_SIZE;
Image$$TTB$$ZI$$Limit = .;
} > L_TTB
.data :
{
Image$$RW_DATA$$Base = .;
__data_start__ = .;
*(vtable)
*(.data*)
Image$$RW_DATA$$Limit = .;
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss ALIGN(0x400):
{
Image$$ZI_DATA$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$ZI_DATA$$Limit = .;
__end__ = .;
end = __end__;
} > RAM AT > RAM
#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)
.heap (NOLOAD):
{
. = ALIGN(8);
Image$$HEAP$$ZI$$Base = .;
. += __HEAP_SIZE;
Image$$HEAP$$ZI$$Limit = .;
__HeapLimit = .;
} > RAM
#endif
.stack (NOLOAD):
{
. = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
. = ALIGN(8);
__StackTop = .;
Image$$SYS_STACK$$ZI$$Base = .;
. += __STACK_SIZE;
Image$$SYS_STACK$$ZI$$Limit = .;
__stack = .;
Image$$FIQ_STACK$$ZI$$Base = .;
. += __FIQ_STACK_SIZE;
Image$$FIQ_STACK$$ZI$$Limit = .;
Image$$IRQ_STACK$$ZI$$Base = .;
. += __IRQ_STACK_SIZE;
Image$$IRQ_STACK$$ZI$$Limit = .;
Image$$SVC_STACK$$ZI$$Base = .;
. += __SVC_STACK_SIZE;
Image$$SVC_STACK$$ZI$$Limit = .;
Image$$ABT_STACK$$ZI$$Base = .;
. += __ABT_STACK_SIZE;
Image$$ABT_STACK$$ZI$$Limit = .;
Image$$UND_STACK$$ZI$$Base = .;
. += __UND_STACK_SIZE;
Image$$UND_STACK$$ZI$$Limit = .;
} > RAM
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld | linker script | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,230 |
```c
/******************************************************************************
* @file system_ARMCA7.c
* @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
* @version V1.0.1
* @date 13. February 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#define SYSTEM_CLOCK 12000000U
/*your_sha256_hash------------
System Core Clock Variable
*your_sha256_hash------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
/*your_sha256_hash------------
System Core Clock update function
*your_sha256_hash------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*your_sha256_hash------------
System Initialization
*your_sha256_hash------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 461 |
```gas
/******************************************************************************
* @file startup_ARMCA7.s
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 01 Nov 2017
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
MODULE ?startup_ARMCA7
/*your_sha256_hash------------
Exception / Interrupt Handler
*your_sha256_hash------------*/
PUBLIC Reset_Handler
PUBWEAK Undef_Handler
PUBWEAK SVC_Handler
PUBWEAK PAbt_Handler
PUBWEAK DAbt_Handler
PUBWEAK IRQ_Handler
PUBWEAK FIQ_Handler
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION USR_STACK:DATA:NOROOT(3)
/*your_sha256_hash------------
Exception / Interrupt Vector Table
*your_sha256_hash------------*/
section RESET:CODE:NOROOT(2)
PUBLIC Vectors
Vectors:
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
section .text:CODE:NOROOT(4)
/*your_sha256_hash------------
Reset Handler called on controller reset
*your_sha256_hash------------*/
EXTERN SystemInit
EXTERN __iar_program_start
Reset_Handler:
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5
ANDS R0, R0, #3
goToSleep:
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exception mode
CPS #0x11
LDR SP, =SFE(FIQ_STACK)
CPS #0x12
LDR SP, =SFE(IRQ_STACK)
CPS #0x13
LDR SP, =SFE(SVC_STACK)
CPS #0x17
LDR SP, =SFE(ABT_STACK)
CPS #0x1B
LDR SP, =SFE(UND_STACK)
CPS #0x1F
LDR SP, =SFE(USR_STACK)
// Call SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __iar_program_start
BL __iar_program_start
/*your_sha256_hash------------
Default Handler for Exceptions / Interrupts
*your_sha256_hash------------*/
Undef_Handler:
SVC_Handler:
PAbt_Handler:
DAbt_Handler:
IRQ_Handler:
FIQ_Handler:
Default_Handler:
B .
END
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s | gas | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,105 |
```c
/**************************************************************************//**
* @file mmu_ARMCA7.c
* @brief MMU Configuration for Arm Cortex-A7 Device Series
* @version V1.2.0
* @date 15. May 2019
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
Memory Type
0xffffffff |--------------------------| ------------
| FLAG SYNC | Device Memory
0xfffff000 |--------------------------| ------------
| Fault | Fault
0xfff00000 |--------------------------| ------------
| | Normal
| |
| Daughterboard |
| memory |
| |
0x80505000 |--------------------------| ------------
|TTB (L2 Sync Flags ) 4k | Normal
0x80504C00 |--------------------------| ------------
|TTB (L2 Peripherals-B) 16k| Normal
0x80504800 |--------------------------| ------------
|TTB (L2 Peripherals-A) 16k| Normal
0x80504400 |--------------------------| ------------
|TTB (L2 Priv Periphs) 4k | Normal
0x80504000 |--------------------------| ------------
| TTB (L1 Descriptors) | Normal
0x80500000 |--------------------------| ------------
| Stack | Normal
|--------------------------| ------------
| Heap | Normal
0x80400000 |--------------------------| ------------
| ZI Data | Normal
0x80300000 |--------------------------| ------------
| RW Data | Normal
0x80200000 |--------------------------| ------------
| RO Data | Normal
|--------------------------| ------------
| RO Code | USH Normal
0x80000000 |--------------------------| ------------
| Daughterboard | Fault
| HSB AXI buses |
0x40000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x2c002000 |--------------------------| ------------
| Private Address | Device Memory
0x2c000000 |--------------------------| ------------
| Daughterboard | Fault
| test chips peripherals |
0x20000000 |--------------------------| ------------
| Peripherals | Device Memory RW/RO
| | & Fault
0x00000000 |--------------------------|
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
#include "ARMCA7.h"
#include "mem_ARMCA7.h"
// TTB base address
#define TTB_BASE ((uint32_t*)__TTB_BASE)
// L2 table pointers
//----------------------------------------
#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
//--------------------- PERIPHERALS -------------------
#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
//--------------------- SYNC FLAGS --------------------
#define FLAG_SYNC 0xFFFFF000
#define F_SYNC_BASE 0xFFF00000 //1M aligned
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
//Create 4GB of faulting entries
MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Define Image
MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
//--------------------- PERIPHERALS -------------------
MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);
MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C000000-0x1C00FFFF
MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
// Define peripheral range 0x1C100000-0x1C10FFFF
MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define private address space entry.
MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry. Uncomment if PL310 is present
// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
// Define synchronization space entry.
MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x1 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x01 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x0 (Inner WB WA) */
__set_TTBR0(__TTB_BASE | 0x48);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 3,712 |
```objective-c
/******************************************************************************
* @file system_ARMCA7.h
* @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series
* @version V1.00
* @date 10. January 2018
*
* @note
*
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef __SYSTEM_ARMCA7_H
#define __SYSTEM_ARMCA7_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_ARMCA7_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 262 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM55.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
* @version V1.0.0
* @date 20. March 2020
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM55_H
#define PARTITION_ARMCM55_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point and Vector Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
(defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM55_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,222 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM35P.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P
* @version V1.0.0
* @date 03. September 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM35P_H
#define PARTITION_ARMCM35P_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM35P_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,189 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <stdio.h>
#include <stdlib.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#ifdef RTE_Compiler_EventRecorder
#include "EventRecorder.h"
#endif
#include "cmsis_cv.h"
#include "CV_Report.h"
//lint -e970 allow using int for main
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include <arm_cmse.h>
/* Dummy Non-secure callable (entry) function */
__attribute__((cmse_nonsecure_entry)) int validationDummy(int x) {
return x;
}
#endif
int main (void)
{
// System Initialization
SystemCoreClockUpdate();
#ifdef RTE_Compiler_EventRecorder
// Initialize and start Event Recorder
(void)EventRecorderInitialize(EventRecordError, 1U);
(void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);
#endif
cmsis_cv();
#ifdef __MICROLIB
for(;;) {}
#else
exit(0);
#endif
}
#if defined(__CORTEX_A)
#include "irq_ctrl.h"
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
(defined ( __GNUC__ ))
#define __IRQ __attribute__((interrupt("IRQ")))
#elif defined ( __CC_ARM )
#define __IRQ __irq
#elif defined ( __ICCARM__ )
#define __IRQ __irq __arm
#else
#error "Unsupported compiler!"
#endif
__IRQ
void IRQ_Handler(void);
__IRQ
void IRQ_Handler(void) {
const IRQn_ID_t irqn = IRQ_GetActiveIRQ();
IRQHandler_t const handler = IRQ_GetHandler(irqn);
if (handler != NULL) {
__enable_irq();
handler();
__disable_irq();
}
IRQ_EndOfInterrupt(irqn);
}
__IRQ __NO_RETURN
void Undef_Handler (void);
__IRQ __NO_RETURN
void Undef_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!");
exit(0);
}
__IRQ
void SVC_Handler (void);
__IRQ
void SVC_Handler (void) {
}
__IRQ __NO_RETURN
void PAbt_Handler (void);
__IRQ __NO_RETURN
void PAbt_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!");
exit(0);
}
__IRQ __NO_RETURN
void DAbt_Handler (void);
__IRQ __NO_RETURN
void DAbt_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!");
exit(0);
}
__IRQ
void FIQ_Handler (void);
__IRQ
void FIQ_Handler (void) {
}
#endif
#if defined(__CORTEX_M)
__NO_RETURN
void HardFault_Handler(void);
__NO_RETURN
void HardFault_Handler(void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!");
#ifdef __MICROLIB
for(;;) {}
#else
exit(0);
#endif
}
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 728 |
```yaml
# yaml-language-server: $schema=path_to_url
layer:
# type: App
# name: CMSIS-Core_Validation
description: Validation of CMSIS-Core implementation
# packs:
# - pack: ARM::CMSIS
define:
- PRINT_XML_REPORT: 1
add-path:
- ../../../Include
- ../../../Source/Config
misc:
- for-compiler: AC6
C-CPP:
- -Wno-declaration-after-statement
- -Wno-covered-switch-default
- for-compiler: GCC
C-CPP:
- -Wno-declaration-after-statement
- -Wno-covered-switch-default
groups:
- group: Documentation
files:
- file: ../../../README.md
- group: Source Files
files:
- file: ./main.c
- group: CMSIS-Core_Validation
files:
- file: ../../../Source/cmsis_cv.c
- file: ../../../Source/CV_CoreFunc.c
- file: ../../../Source/CV_CoreInstr.c
- file: ../../../Source/CV_CoreSimd.c
- file: ../../../Source/CV_CML1Cache.c
- file: ../../../Source/CV_MPU_ARMv7.c
for-context:
- +CM0
- +CM0plus
- +CM3
- +CM4
- +CM4FP
- +CM7
- +CM7SP
- +CM7DP
- file: ../../../Source/CV_MPU_ARMv8.c
for-context:
- +CM23
- +CM23S
- +CM23NS
- +CM33
- +CM33S
- +CM33NS
- +CM35P
- +CM35PS
- +CM35PNS
- +CM55S
- +CM55NS
- +CM85S
- +CM85NS
- group: Validation Framework
files:
- file: ../../../Source/CV_Framework.c
- file: ../../../Source/CV_Report.c
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 478 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#include <stdio.h>
#include <stdlib.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#ifdef RTE_Compiler_EventRecorder
#include "EventRecorder.h"
#endif
#include "cmsis_cv.h"
#include "CV_Report.h"
//lint -e970 allow using int for main
int main (void)
{
// System Initialization
SystemCoreClockUpdate();
#ifdef RTE_Compiler_EventRecorder
// Initialize and start Event Recorder
(void)EventRecorderInitialize(EventRecordError, 1U);
(void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);
#endif
cmsis_cv();
#ifdef __MICROLIB
for(;;) {}
#else
exit(0);
#endif
}
#if defined(__CORTEX_A)
#include "irq_ctrl.h"
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
(defined ( __GNUC__ ))
#define __IRQ __attribute__((interrupt("IRQ")))
#elif defined ( __CC_ARM )
#define __IRQ __irq
#elif defined ( __ICCARM__ )
#define __IRQ __irq __arm
#else
#error "Unsupported compiler!"
#endif
__IRQ
void IRQ_Handler(void);
__IRQ
void IRQ_Handler(void) {
const IRQn_ID_t irqn = IRQ_GetActiveIRQ();
IRQHandler_t const handler = IRQ_GetHandler(irqn);
if (handler != NULL) {
__enable_irq();
handler();
__disable_irq();
}
IRQ_EndOfInterrupt(irqn);
}
__IRQ __NO_RETURN
void Undef_Handler (void);
__IRQ __NO_RETURN
void Undef_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!");
exit(0);
}
__IRQ
void SVC_Handler (void);
__IRQ
void SVC_Handler (void) {
}
__IRQ __NO_RETURN
void PAbt_Handler (void);
__IRQ __NO_RETURN
void PAbt_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!");
exit(0);
}
__IRQ __NO_RETURN
void DAbt_Handler (void);
__IRQ __NO_RETURN
void DAbt_Handler (void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!");
exit(0);
}
__IRQ
void FIQ_Handler (void);
__IRQ
void FIQ_Handler (void) {
}
#endif
#if defined(__CORTEX_M)
__NO_RETURN
void HardFault_Handler(void);
__NO_RETURN
void HardFault_Handler(void) {
cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!");
#ifdef __MICROLIB
for(;;) {}
#else
exit(0);
#endif
}
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 662 |
```yaml
# yaml-language-server: $schema=path_to_url
layer:
# type: App
# name: CMSIS-Core_Validation
description: Validation of CMSIS-Core implementation
# packs:
# - pack: ARM::CMSIS
define:
- PRINT_XML_REPORT: 1
add-path:
- ../../../Include
- ../../../Source/ConfigA
misc:
- for-compiler: AC6
C-CPP:
- -Wno-declaration-after-statement
- -Wno-covered-switch-default
- for-compiler: GCC
C-CPP:
- -Wno-declaration-after-statement
- -Wno-covered-switch-default
groups:
- group: Documentation
files:
- file: ../../../README.md
- group: Source Files
files:
- file: ./main.c
- group: CMSIS-Core_Validation
files:
- file: ../../../Source/cmsis_cv.c
- file: ../../../Source/CV_CoreAFunc.c
- file: ../../../Source/CV_CoreInstr.c
- file: ../../../Source/CV_CAL1Cache.c
# - file: ../../../Source/ConfigA/mmu.c
- group: Validation Framework
files:
- file: ../../../Source/CV_Framework.c
- file: ../../../Source/CV_Report.c
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 300 |
```c
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
* your_sha256_hash------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*your_sha256_hash-----------*/
#include <stdio.h>
#include <stdlib.h>
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
#if 1
/* Dummy Non-secure callable (entry) function */
__attribute__((cmse_nonsecure_entry)) int validationDummy(int x) {
return x;
}
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
#if defined(__CORTEX_M)
__NO_RETURN
extern void HardFault_Handler(void);
void HardFault_Handler(void) {
printf("Bootloader HardFault!\n");
#ifdef __MICROLIB
for(;;) {}
#else
exit(1);
#endif
}
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 456 |
```yaml
# yaml-language-server: $schema=path_to_url
layer:
# type: App
# name: CMSIS-Core_Validation (Bootloader)
description: Validation of CMSIS-Core implementation (Bootloader part)
# packs:
# - pack: ARM::CMSIS
groups:
- group: Source Files
files:
- file: ./bootloader.c
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 84 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM85.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
* @version V1.0.0
* @date 07. March 2022
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM85_H
#define PARTITION_ARMCM85_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <s>Description
*/
#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <s>Description
*/
#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point and Vector Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x0000122B
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
(defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM85_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,468 |
```yaml
# yaml-language-server: $schema=path_to_url
solution:
packs:
- pack: ARM::CMSIS
path: ../../../
misc:
- for-compiler: AC6
C: [-std=c99, -gdwarf-4, -ffunction-sections]
Link: [--entry=Reset_Handler, --symbols, --map]
- for-compiler: GCC
C: [-std=gnu99, -gdwarf-2, -ffunction-sections, -fdata-sections]
Link: [--specs=nano.specs, --specs=rdimon.specs]
- for-compiler: IAR
Link: [--semihosting]
target-types:
#CM0
- type: CM0
device: ARMCM0
#CM0plus
- type: CM0plus
device: ARMCM0P
#CM3
- type: CM3
device: ARMCM3
#CM4
- type: CM4
device: ARMCM4
#CM4FP
- type: CM4FP
device: ARMCM4_FP
#CM7
- type: CM7
device: ARMCM7
#CM7SP
- type: CM7SP
device: ARMCM7_SP
#CM7DP
- type: CM7DP
device: ARMCM7_DP
#CM23
- type: CM23
device: ARMCM23
processor:
trustzone: off
#CM23S
- type: CM23S
device: ARMCM23_TZ
processor:
trustzone: secure
#CM23NS
- type: CM23NS
device: ARMCM23_TZ
processor:
trustzone: non-secure
#CM33
- type: CM33
device: ARMCM33_DSP_FP
processor:
trustzone: off
#CM33S
- type: CM33S
device: ARMCM33_DSP_FP_TZ
processor:
trustzone: secure
#CM33NS
- type: CM33NS
device: ARMCM33_DSP_FP_TZ
processor:
trustzone: non-secure
#CM35P
- type: CM35P
device: ARMCM35P_DSP_FP
processor:
trustzone: off
#CM35PS
- type: CM35PS
device: ARMCM35P_DSP_FP_TZ
processor:
trustzone: secure
#CM35PNS
- type: CM35PNS
device: ARMCM35P_DSP_FP_TZ
processor:
trustzone: non-secure
#CM55S
- type: CM55S
device: ARMCM55
processor:
trustzone: secure
#CM55NS
- type: CM55NS
device: ARMCM55
processor:
trustzone: non-secure
#CM85S
- type: CM85S
device: ARMCM85
processor:
trustzone: secure
#CM85NS
- type: CM85NS
device: ARMCM85
processor:
trustzone: non-secure
#CA5
- type: CA5
device: ARMCA5
#CA7
- type: CA7
device: ARMCA7
#CA9
- type: CA9
device: ARMCA9
build-types:
#AC6_low, AC6_mid, AC6_high, AC6_size, AC6_OZ,
- type: AC6_low
compiler: AC6
misc:
- for-compiler: AC6
C: [-O1]
- type: AC6_mid
compiler: AC6
misc:
- for-compiler: AC6
C: [-O2]
- type: AC6_high
compiler: AC6
misc:
- for-compiler: AC6
C: [-O3]
- type: AC6_size
compiler: AC6
misc:
- for-compiler: AC6
C: [-Os]
- type: AC6_tiny
compiler: AC6
misc:
- for-compiler: AC6
C: [-Oz]
#GCC_low, GCC_mid, GCC_high, GCC_size, GCC_OZ,
- type: GCC_low
compiler: GCC
misc:
- for-compiler: GCC
C: [-O1]
- type: GCC_mid
compiler: GCC
misc:
- for-compiler: GCC
C: [-O2]
- type: GCC_high
compiler: GCC
misc:
- for-compiler: GCC
C: [-O3]
- type: GCC_size
compiler: GCC
misc:
- for-compiler: GCC
C: [-Os]
- type: GCC_tiny
compiler: GCC
misc:
- for-compiler: GCC
C: [-Ofast]
#IAR_low
- type: IAR_low
compiler: IAR
misc:
- for-compiler: IAR
C: [-Ol, --dlib_config DLib_Config_Full.h]
- type: IAR_mid
compiler: IAR
misc:
- for-compiler: IAR
C: [-Om, --dlib_config DLib_Config_Full.h]
- type: IAR_high
compiler: IAR
misc:
- for-compiler: IAR
C: [-Oh, --dlib_config DLib_Config_Full.h]
- type: IAR_size
compiler: IAR
misc:
- for-compiler: IAR
C: [-Ohz, --dlib_config DLib_Config_Full.h]
- type: IAR_tiny
compiler: IAR
misc:
- for-compiler: IAR
C: [-Ohs, --dlib_config DLib_Config_Full.h]
projects:
- project: ./Validation.cproject.yml
- project: ./Bootloader.cproject.yml
for-context:
- +CM23S
- +CM33S
- +CM35PS
- +CM55S
- +CM85S
output-dirs:
cprjdir: ./$Project$.$BuildType$+$TargetType$
intdir: ./$Project$.$BuildType$+$TargetType$/intdir
outdir: ./$Project$.$BuildType$+$TargetType$/outdir
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/Validation.csolution.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,507 |
```yaml
# yaml-language-server: $schema=path_to_url
project:
layers:
# App: CMSIS-Core Validation for Cortex-M
- layer: ../Layer/App/Validation_Cortex-M/App.clayer.yml
for-context:
- +CM0
- +CM0plus
- +CM3
- +CM4
- +CM4FP
- +CM7
- +CM7SP
- +CM7DP
- +CM23
- +CM23S
- +CM23NS
- +CM33
- +CM33S
- +CM33NS
- +CM35P
- +CM35PS
- +CM35PNS
- +CM55S
- +CM55NS
- +CM85S
- +CM85NS
# App: CMSIS-Core Validation for Cortex-A
- layer: ../Layer/App/Validation_Cortex-A/App.clayer.yml
for-context:
- +CA5
- +CA7
- +CA9
#Target: CM0
- layer: ../Layer/Target/CM0/Target.clayer.yml
for-context:
- .AC6_low+CM0
- .AC6_mid+CM0
- .AC6_high+CM0
- .AC6_size+CM0
- .AC6_tiny+CM0
- .GCC_low+CM0
- .GCC_mid+CM0
- .GCC_high+CM0
- .GCC_size+CM0
- .GCC_tiny+CM0
- .IAR_low+CM0
- .IAR_mid+CM0
- .IAR_high+CM0
- .IAR_size+CM0
- .IAR_tiny+CM0
#Target: CM0plus
- layer: ../Layer/Target/CM0plus/Target.clayer.yml
for-context:
- .AC6_low+CM0plus
- .AC6_mid+CM0plus
- .AC6_high+CM0plus
- .AC6_size+CM0plus
- .AC6_tiny+CM0plus
- .GCC_low+CM0plus
- .GCC_mid+CM0plus
- .GCC_high+CM0plus
- .GCC_size+CM0plus
- .GCC_tiny+CM0plus
- .IAR_low+CM0plus
- .IAR_mid+CM0plus
- .IAR_high+CM0plus
- .IAR_size+CM0plus
- .IAR_tiny+CM0plus
#Target: CM3
- layer: ../Layer/Target/CM3/Target.clayer.yml
for-context:
- .AC6_low+CM3
- .AC6_mid+CM3
- .AC6_high+CM3
- .AC6_size+CM3
- .AC6_tiny+CM3
- .GCC_low+CM3
- .GCC_mid+CM3
- .GCC_high+CM3
- .GCC_size+CM3
- .GCC_tiny+CM3
- .IAR_low+CM3
- .IAR_mid+CM3
- .IAR_high+CM3
- .IAR_size+CM3
- .IAR_tiny+CM3
#Target: CM4
- layer: ../Layer/Target/CM4/Target.clayer.yml
for-context:
- .AC6_low+CM4
- .AC6_mid+CM4
- .AC6_high+CM4
- .AC6_size+CM4
- .AC6_tiny+CM4
- .GCC_low+CM4
- .GCC_mid+CM4
- .GCC_high+CM4
- .GCC_size+CM4
- .GCC_tiny+CM4
- .IAR_low+CM4
- .IAR_mid+CM4
- .IAR_high+CM4
- .IAR_size+CM4
- .IAR_tiny+CM4
#Target: CM4FP
- layer: ../Layer/Target/CM4FP/Target.clayer.yml
for-context:
- .AC6_low+CM4FP
- .AC6_mid+CM4FP
- .AC6_high+CM4FP
- .AC6_size+CM4FP
- .AC6_tiny+CM4FP
- .GCC_low+CM4FP
- .GCC_mid+CM4FP
- .GCC_high+CM4FP
- .GCC_size+CM4FP
- .GCC_tiny+CM4FP
- .IAR_low+CM4FP
- .IAR_mid+CM4FP
- .IAR_high+CM4FP
- .IAR_size+CM4FP
- .IAR_tiny+CM4FP
#Target: CM7
- layer: ../Layer/Target/CM7/Target.clayer.yml
for-context:
- .AC6_low+CM7
- .AC6_mid+CM7
- .AC6_high+CM7
- .AC6_size+CM7
- .AC6_tiny+CM7
- .GCC_low+CM7
- .GCC_mid+CM7
- .GCC_high+CM7
- .GCC_size+CM7
- .GCC_tiny+CM7
- .IAR_low+CM7
- .IAR_mid+CM7
- .IAR_high+CM7
- .IAR_size+CM7
- .IAR_tiny+CM7
#Target: CM7SP
- layer: ../Layer/Target/CM7SP/Target.clayer.yml
for-context:
- .AC6_low+CM7SP
- .AC6_mid+CM7SP
- .AC6_high+CM7SP
- .AC6_size+CM7SP
- .AC6_tiny+CM7SP
- .GCC_low+CM7SP
- .GCC_mid+CM7SP
- .GCC_high+CM7SP
- .GCC_size+CM7SP
- .GCC_tiny+CM7SP
- .IAR_low+CM7SP
- .IAR_mid+CM7SP
- .IAR_high+CM7SP
- .IAR_size+CM7SP
- .IAR_tiny+CM7SP
#Target: CM7DP
- layer: ../Layer/Target/CM7DP/Target.clayer.yml
for-context:
- .AC6_low+CM7DP
- .AC6_mid+CM7DP
- .AC6_high+CM7DP
- .AC6_size+CM7DP
- .AC6_tiny+CM7DP
- .GCC_low+CM7DP
- .GCC_mid+CM7DP
- .GCC_high+CM7DP
- .GCC_size+CM7DP
- .GCC_tiny+CM7DP
- .IAR_low+CM7DP
- .IAR_mid+CM7DP
- .IAR_high+CM7DP
- .IAR_size+CM7DP
- .IAR_tiny+CM7DP
#Target: CM23
- layer: ../Layer/Target/CM23/Target.clayer.yml
for-context:
- .AC6_low+CM23
- .AC6_mid+CM23
- .AC6_high+CM23
- .AC6_size+CM23
- .AC6_tiny+CM23
- .GCC_low+CM23
- .GCC_mid+CM23
- .GCC_high+CM23
- .GCC_size+CM23
- .GCC_tiny+CM23
- .IAR_low+CM23
- .IAR_mid+CM23
- .IAR_high+CM23
- .IAR_size+CM23
- .IAR_tiny+CM23
#Target: CM23S
- layer: ../Layer/Target/CM23S/Target.clayer.yml
for-context:
- .AC6_low+CM23S
- .AC6_mid+CM23S
- .AC6_high+CM23S
- .AC6_size+CM23S
- .AC6_tiny+CM23S
- .GCC_low+CM23S
- .GCC_mid+CM23S
- .GCC_high+CM23S
- .GCC_size+CM23S
- .GCC_tiny+CM23S
- .IAR_low+CM23S
- .IAR_mid+CM23S
- .IAR_high+CM23S
- .IAR_size+CM23S
- .IAR_tiny+CM23S
#Target: CM23NS
- layer: ../Layer/Target/CM23NS/Target.clayer.yml
for-context:
- .AC6_low+CM23NS
- .AC6_mid+CM23NS
- .AC6_high+CM23NS
- .AC6_size+CM23NS
- .AC6_tiny+CM23NS
- .GCC_low+CM23NS
- .GCC_mid+CM23NS
- .GCC_high+CM23NS
- .GCC_size+CM23NS
- .GCC_tiny+CM23NS
- .IAR_low+CM23NS
- .IAR_mid+CM23NS
- .IAR_high+CM23NS
- .IAR_size+CM23NS
- .IAR_tiny+CM23NS
#Target: CM33
- layer: ../Layer/Target/CM33/Target.clayer.yml
for-context:
- .AC6_low+CM33
- .AC6_mid+CM33
- .AC6_high+CM33
- .AC6_size+CM33
- .AC6_tiny+CM33
- .GCC_low+CM33
- .GCC_mid+CM33
- .GCC_high+CM33
- .GCC_size+CM33
- .GCC_tiny+CM33
- .IAR_low+CM33
- .IAR_mid+CM33
- .IAR_high+CM33
- .IAR_size+CM33
- .IAR_tiny+CM33
#Target: CM33S
- layer: ../Layer/Target/CM33S/Target.clayer.yml
for-context:
- .AC6_low+CM33S
- .AC6_mid+CM33S
- .AC6_high+CM33S
- .AC6_size+CM33S
- .AC6_tiny+CM33S
- .GCC_low+CM33S
- .GCC_mid+CM33S
- .GCC_high+CM33S
- .GCC_size+CM33S
- .GCC_tiny+CM33S
- .IAR_low+CM33S
- .IAR_mid+CM33S
- .IAR_high+CM33S
- .IAR_size+CM33S
- .IAR_tiny+CM33S
#Target: CM33NS
- layer: ../Layer/Target/CM33NS/Target.clayer.yml
for-context:
- .AC6_low+CM33NS
- .AC6_mid+CM33NS
- .AC6_high+CM33NS
- .AC6_size+CM33NS
- .AC6_tiny+CM33NS
- .GCC_low+CM33NS
- .GCC_mid+CM33NS
- .GCC_high+CM33NS
- .GCC_size+CM33NS
- .GCC_tiny+CM33NS
- .IAR_low+CM33NS
- .IAR_mid+CM33NS
- .IAR_high+CM33NS
- .IAR_size+CM33NS
- .IAR_tiny+CM33NS
#Target: CM35P
- layer: ../Layer/Target/CM35P/Target.clayer.yml
for-context:
- .AC6_low+CM35P
- .AC6_mid+CM35P
- .AC6_high+CM35P
- .AC6_size+CM35P
- .AC6_tiny+CM35P
- .GCC_low+CM35P
- .GCC_mid+CM35P
- .GCC_high+CM35P
- .GCC_size+CM35P
- .GCC_tiny+CM35P
- .IAR_low+CM35P
- .IAR_mid+CM35P
- .IAR_high+CM35P
- .IAR_size+CM35P
- .IAR_tiny+CM35P
#Target: CM35PS
- layer: ../Layer/Target/CM35PS/Target.clayer.yml
for-context:
- .AC6_low+CM35PS
- .AC6_mid+CM35PS
- .AC6_high+CM35PS
- .AC6_size+CM35PS
- .AC6_tiny+CM35PS
- .GCC_low+CM35PS
- .GCC_mid+CM35PS
- .GCC_high+CM35PS
- .GCC_size+CM35PS
- .GCC_tiny+CM35PS
- .IAR_low+CM35PS
- .IAR_mid+CM35PS
- .IAR_high+CM35PS
- .IAR_size+CM35PS
- .IAR_tiny+CM35PS
#Target: CM35PNS
- layer: ../Layer/Target/CM35PNS/Target.clayer.yml
for-context:
- .AC6_low+CM35PNS
- .AC6_mid+CM35PNS
- .AC6_high+CM35PNS
- .AC6_size+CM35PNS
- .AC6_tiny+CM35PNS
- .GCC_low+CM35PNS
- .GCC_mid+CM35PNS
- .GCC_high+CM35PNS
- .GCC_size+CM35PNS
- .GCC_tiny+CM35PNS
- .IAR_low+CM35PNS
- .IAR_mid+CM35PNS
- .IAR_high+CM35PNS
- .IAR_size+CM35PNS
- .IAR_tiny+CM35PNS
#Target: CM55S
- layer: ../Layer/Target/CM55S/Target.clayer.yml
for-context:
- .AC6_low+CM55S
- .AC6_mid+CM55S
- .AC6_high+CM55S
- .AC6_size+CM55S
- .AC6_tiny+CM55S
- .GCC_low+CM55S
- .GCC_mid+CM55S
- .GCC_high+CM55S
- .GCC_size+CM55S
- .GCC_tiny+CM55S
- .IAR_low+CM55S
- .IAR_mid+CM55S
- .IAR_high+CM55S
- .IAR_size+CM55S
- .IAR_tiny+CM55S
#Target: CM55NS
- layer: ../Layer/Target/CM55NS/Target.clayer.yml
for-context:
- .AC6_low+CM55NS
- .AC6_mid+CM55NS
- .AC6_high+CM55NS
- .AC6_size+CM55NS
- .AC6_tiny+CM55NS
- .GCC_low+CM55NS
- .GCC_mid+CM55NS
- .GCC_high+CM55NS
- .GCC_size+CM55NS
- .GCC_tiny+CM55NS
- .IAR_low+CM55NS
- .IAR_mid+CM55NS
- .IAR_high+CM55NS
- .IAR_size+CM55NS
- .IAR_tiny+CM55NS
#Target: CM85S
- layer: ../Layer/Target/CM85S/Target.clayer.yml
for-context:
- .AC6_low+CM85S
- .AC6_mid+CM85S
- .AC6_high+CM85S
- .AC6_size+CM85S
- .AC6_tiny+CM85S
- .GCC_low+CM85S
- .GCC_mid+CM85S
- .GCC_high+CM85S
- .GCC_size+CM85S
- .GCC_tiny+CM85S
- .IAR_low+CM85S
- .IAR_mid+CM85S
- .IAR_high+CM85S
- .IAR_size+CM85S
- .IAR_tiny+CM85S
#Target: CM85NS
- layer: ../Layer/Target/CM85NS/Target.clayer.yml
for-context:
- .AC6_low+CM85NS
- .AC6_mid+CM85NS
- .AC6_high+CM85NS
- .AC6_size+CM85NS
- .AC6_tiny+CM85NS
- .GCC_low+CM85NS
- .GCC_mid+CM85NS
- .GCC_high+CM85NS
- .GCC_size+CM85NS
- .GCC_tiny+CM85NS
- .IAR_low+CM85NS
- .IAR_mid+CM85NS
- .IAR_high+CM85NS
- .IAR_size+CM85NS
- .IAR_tiny+CM85NS
#Target: CA5
- layer: ../Layer/Target/CA5/Target.clayer.yml
for-context:
- .AC6_low+CA5
- .AC6_mid+CA5
- .AC6_high+CA5
- .AC6_size+CA5
- .AC6_tiny+CA5
- .GCC_low+CA5
- .GCC_mid+CA5
- .GCC_high+CA5
- .GCC_size+CA5
- .GCC_tiny+CA5
- .IAR_low+CA5
- .IAR_mid+CA5
- .IAR_high+CA5
- .IAR_size+CA5
- .IAR_tiny+CA5
#Target: CA7
- layer: ../Layer/Target/CA7/Target.clayer.yml
for-context:
- .AC6_low+CA7
- .AC6_mid+CA7
- .AC6_high+CA7
- .AC6_size+CA7
- .AC6_tiny+CA7
- .GCC_low+CA7
- .GCC_mid+CA7
- .GCC_high+CA7
- .GCC_size+CA7
- .GCC_tiny+CA7
- .IAR_low+CA7
- .IAR_mid+CA7
- .IAR_high+CA7
- .IAR_size+CA7
- .IAR_tiny+CA7
#Target: CA9
- layer: ../Layer/Target/CA9/Target.clayer.yml
for-context:
- .AC6_low+CA9
- .AC6_mid+CA9
- .AC6_high+CA9
- .AC6_size+CA9
- .AC6_tiny+CA9
- .GCC_low+CA9
- .GCC_mid+CA9
- .GCC_high+CA9
- .GCC_size+CA9
- .GCC_tiny+CA9
- .IAR_low+CA9
- .IAR_mid+CA9
- .IAR_high+CA9
- .IAR_size+CA9
- .IAR_tiny+CA9
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/Validation.cproject.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 4,739 |
```yaml
name: "RTOS2 Validation"
workdir: ../../../
backend:
aws:
ami-version: ~=1.3
instance-type: t2.micro
upload:
- ARM.CMSIS.pdsc
- CMSIS/Core/**/*
- CMSIS/Core_A/**/*
- CMSIS/CoreValidation/**/*
- -:CMSIS/CoreValidation/Project/Core_Validation-*.zip
- -:CMSIS/CoreValidation/Project/Core_Validation-*.junit
- -:CMSIS/CoreValidation/Project/Validation.*/**/*
- -:CMSIS/CoreValidation/Project/Bootloader.*/**/*
- Device/ARM/**/*
steps:
- run: |
wget path_to_url
chmod +x cmsis-toolbox.sh
sudo ./cmsis-toolbox.sh <<EOI
/opt/ctools
$CMSIS_PACK_ROOT
$(dirname $(which armclang 2>/dev/null))
$(dirname $(which armcc 2>/dev/null))
$(dirname $(which arm-none-eabi-gcc 2>/dev/null))
EOI
echo "cpackget : $(which cpackget)"
echo "csolution: $(which csolution)"
echo "cbuild : $(which cbuild)"
- run: |
pip install -r requirements.txt 2>&1
- run: |
cd CMSIS/CoreValidation/Project
python build.py --verbose -c AC6 -c GCC -d "CM[047]*" -d "CM[23]3*" build run 2>&1 || echo "Something failed!"
download:
- CMSIS/CoreValidation/Project/Core_Validation-*.zip
- CMSIS/CoreValidation/Project/Core_Validation-*.junit
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/avh.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 379 |
```yaml
# yaml-language-server: $schema=path_to_url
project:
layers:
# App: CMSIS-Core Validation for Cortex-M (Bootloader part)
- layer: ../Layer/App/Bootloader_Cortex-M/App.clayer.yml
for-context:
- .AC6_low
- .AC6_mid
- .AC6_high
- .AC6_size
- .AC6_tiny
- .GCC_low
- .GCC_mid
- .GCC_high
- .GCC_size
- .GCC_tiny
- .IAR_low
- .IAR_mid
- .IAR_high
- .IAR_size
- .IAR_tiny
#Target: CM23S
- layer: ../Layer/Target/CM23S_BL/Target.clayer.yml
for-context:
- .AC6_low+CM23S
- .AC6_mid+CM23S
- .AC6_high+CM23S
- .AC6_size+CM23S
- .AC6_tiny+CM23S
- .GCC_low+CM23S
- .GCC_mid+CM23S
- .GCC_high+CM23S
- .GCC_size+CM23S
- .GCC_tiny+CM23S
- .IAR_low+CM23S
- .IAR_mid+CM23S
- .IAR_high+CM23S
- .IAR_size+CM23S
- .IAR_tiny+CM23S
#Target: CM33S
- layer: ../Layer/Target/CM33S_BL/Target.clayer.yml
for-context:
- .AC6_low+CM33S
- .AC6_mid+CM33S
- .AC6_high+CM33S
- .AC6_size+CM33S
- .AC6_tiny+CM33S
- .GCC_low+CM33S
- .GCC_mid+CM33S
- .GCC_high+CM33S
- .GCC_size+CM33S
- .GCC_tiny+CM33S
- .IAR_low+CM33S
- .IAR_mid+CM33S
- .IAR_high+CM33S
- .IAR_size+CM33S
- .IAR_tiny+CM33S
#Target: CM35PS
- layer: ../Layer/Target/CM35PS_BL/Target.clayer.yml
for-context:
- .AC6_low+CM35PS
- .AC6_mid+CM35PS
- .AC6_high+CM35PS
- .AC6_size+CM35PS
- .AC6_tiny+CM35PS
- .GCC_low+CM35PS
- .GCC_mid+CM35PS
- .GCC_high+CM35PS
- .GCC_size+CM35PS
- .GCC_tiny+CM35PS
- .IAR_low+CM35PS
- .IAR_mid+CM35PS
- .IAR_high+CM35PS
- .IAR_size+CM35PS
- .IAR_tiny+CM35PS
#Target: CM55S
- layer: ../Layer/Target/CM55S_BL/Target.clayer.yml
for-context:
- .AC6_low+CM55S
- .AC6_mid+CM55S
- .AC6_high+CM55S
- .AC6_size+CM55S
- .AC6_tiny+CM55S
- .GCC_low+CM55S
- .GCC_mid+CM55S
- .GCC_high+CM55S
- .GCC_size+CM55S
- .GCC_tiny+CM55S
- .IAR_low+CM55S
- .IAR_mid+CM55S
- .IAR_high+CM55S
- .IAR_size+CM55S
- .IAR_tiny+CM55S
#Target: CM85S
- layer: ../Layer/Target/CM85S_BL/Target.clayer.yml
for-context:
- .AC6_low+CM85S
- .AC6_mid+CM85S
- .AC6_high+CM85S
- .AC6_size+CM85S
- .AC6_tiny+CM85S
- .GCC_low+CM85S
- .GCC_mid+CM85S
- .GCC_high+CM85S
- .GCC_size+CM85S
- .GCC_tiny+CM85S
- .IAR_low+CM85S
- .IAR_mid+CM85S
- .IAR_high+CM85S
- .IAR_size+CM85S
- .IAR_tiny+CM85S
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/Bootloader.cproject.yml | yaml | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,128 |
```xslt
<xsl:stylesheet version="1.0" xmlns:xsl="path_to_url">
<xsl:output method="xml" indent="yes"/>
<xsl:template match="/">
<testsuites>
<xsl:variable name="buildName" select="//report/test/title"/>
<xsl:variable name="numberOfTests" select="//report/test/summary/tcnt"/>
<xsl:variable name="numberOfExecutes" select="//report/test/summary/exec"/>
<xsl:variable name="numberOfPasses" select="//report/test/summary/pass"/>
<xsl:variable name="numberOfFailures" select="//report/test/summary/fail"/>
<xsl:variable name="numberOfSkips" select="$numberOfTests - $numberOfExecutes"/>
<xsl:variable name="numberOfErrors" select="0"/>
<testsuite name="{$buildName}"
tests="{$numberOfTests}" time="0"
failures="{$numberOfFailures}" errors="{$numberOfErrors}"
skipped="{$numberOfSkips}">
<xsl:for-each select="//report/test/test_cases/tc">
<xsl:variable name="testName" select="func"/>
<xsl:variable name="status" select="res"/>
<testcase name="{$testName}">
<xsl:choose>
<xsl:when test="res='PASSED'"/>
<xsl:when test="res='NOT EXECUTED'">
<skipped/>
</xsl:when>
<xsl:otherwise>
<failure>
<xsl:for-each select="dbgi/detail">
<xsl:variable name="file" select="module"/>
<xsl:variable name="line" select="line"/>
<xsl:text> </xsl:text>
<xsl:value-of select="$file"/>:<xsl:value-of select="$line"/>
</xsl:for-each>
<xsl:text> </xsl:text>
</failure>
</xsl:otherwise>
</xsl:choose>
</testcase>
</xsl:for-each>
</testsuite>
</testsuites>
</xsl:template>
</xsl:stylesheet>
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/validation.xsl | xslt | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 500 |
```python
#!/usr/bin/python
# -*- coding: utf-8 -*-
import logging
from datetime import datetime
from enum import Enum
from glob import glob, iglob
from pathlib import Path
from lxml.etree import XMLSyntaxError
from zipfile import ZipFile
from matrix_runner import main, matrix_axis, matrix_action, matrix_command, matrix_filter, \
ConsoleReport, CropReport, TransformReport, JUnitReport
@matrix_axis("device", "d", "Device(s) to be considered.")
class DeviceAxis(Enum):
CM0 = ('Cortex-M0', 'CM0')
CM0plus = ('Cortex-M0plus', 'CM0plus')
CM3 = ('Cortex-M3', 'CM3')
CM4 = ('Cortex-M4', 'CM4')
CM4FP = ('Cortex-M4FP', 'CM4FP')
CM7 = ('Cortex-M7', 'CM7')
CM7SP = ('Cortex-M7SP', 'CM7SP')
CM7DP = ('Cortex-M7DP', 'CM7DP')
CM23 = ('Cortex-M23', 'CM23')
CM23S = ('Cortex-M23S', 'CM23S')
CM23NS = ('Cortex-M23NS', 'CM23NS')
CM33 = ('Cortex-M33', 'CM33')
CM33S = ('Cortex-M33S', 'CM33S')
CM33NS = ('Cortex-M33NS', 'CM33NS')
CM35P = ('Cortex-M35P', 'CM35P')
CM35PS = ('Cortex-M35PS', 'CM35PS')
CM35PNS = ('Cortex-M35PNS', 'CM35PNS')
CM55S = ('Cortex-M55S', 'CM55S')
CM55NS = ('Cortex-M55NS', 'CM55NS')
CM85S = ('Cortex-M85S', 'CM85S')
CM85NS = ('Cortex-M85NS', 'CM85NS')
CA5 = ('Cortex-A5', 'CA5')
CA7 = ('Cortex-A7', 'CA7')
CA9 = ('Cortex-A9', 'CA9')
# CA5NEON = ('Cortex-A5neon', 'CA5neon')
# CA7NEON = ('Cortex-A7neon', 'CA7neon')
# CA9NEON = ('Cortex-A9neon', 'CA9neon')
def has_bl(self):
return self in [
DeviceAxis.CM23NS,
DeviceAxis.CM33NS,
DeviceAxis.CM35PNS,
DeviceAxis.CM55NS,
DeviceAxis.CM85NS
]
@property
def bl_device(self):
bld = {
DeviceAxis.CM23NS: 'CM23S',
DeviceAxis.CM33NS: 'CM33S',
DeviceAxis.CM35PNS: 'CM35PS',
DeviceAxis.CM55NS: 'CM55S',
DeviceAxis.CM85NS: 'CM85S'
}
return bld[self]
@matrix_axis("compiler", "c", "Compiler(s) to be considered.")
class CompilerAxis(Enum):
AC6 = ('AC6')
AC6LTM = ('AC6LTM')
GCC = ('GCC')
IAR = ('IAR')
@property
def image_ext(self):
ext = {
CompilerAxis.AC6: 'axf',
CompilerAxis.AC6LTM: 'axf',
CompilerAxis.GCC: 'elf',
CompilerAxis.IAR: 'elf'
}
return ext[self]
@matrix_axis("optimize", "o", "Optimization level(s) to be considered.")
class OptimizationAxis(Enum):
LOW = ('low', 'O1')
MID = ('mid', 'O2')
HIGH = ('high', 'Ofast')
SIZE = ('size', 'Os')
TINY = ('tiny', 'Oz')
MODEL_EXECUTABLE = {
DeviceAxis.CM0: ("VHT_MPS2_Cortex-M0", []),
DeviceAxis.CM0plus: ("VHT_MPS2_Cortex-M0plus", []),
DeviceAxis.CM3: ("VHT_MPS2_Cortex-M3", []),
DeviceAxis.CM4: ("VHT_MPS2_Cortex-M4", []),
DeviceAxis.CM4FP: ("VHT_MPS2_Cortex-M4", []),
DeviceAxis.CM7: ("VHT_MPS2_Cortex-M7", []),
DeviceAxis.CM7DP: ("VHT_MPS2_Cortex-M7", []),
DeviceAxis.CM7SP: ("VHT_MPS2_Cortex-M7", []),
DeviceAxis.CM23: ("VHT_MPS2_Cortex-M23", []),
DeviceAxis.CM23S: ("VHT_MPS2_Cortex-M23", []),
DeviceAxis.CM23NS: ("VHT_MPS2_Cortex-M23", []),
DeviceAxis.CM33: ("VHT_MPS2_Cortex-M33", []),
DeviceAxis.CM33S: ("VHT_MPS2_Cortex-M33", []),
DeviceAxis.CM33NS: ("VHT_MPS2_Cortex-M33", []),
DeviceAxis.CM35P: ("VHT_MPS2_Cortex-M35P", []),
DeviceAxis.CM35PS: ("VHT_MPS2_Cortex-M35P", []),
DeviceAxis.CM35PNS: ("VHT_MPS2_Cortex-M35P", []),
DeviceAxis.CM55S: ("VHT_MPS2_Cortex-M55", []),
DeviceAxis.CM55NS: ("VHT_MPS2_Cortex-M55", []),
DeviceAxis.CM85S: ("VHT_MPS2_Cortex-M85", []),
DeviceAxis.CM85NS: ("VHT_MPS2_Cortex-M85", []),
DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []),
DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []),
DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []),
# DeviceAxis.CA5NEON: ("FVP_VE_Cortex-A5x1", []),
# DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []),
# DeviceAxis.CA9NEON: ("FVP_VE_Cortex-A9x1", [])
}
def config_suffix(config, timestamp=True):
suffix = f"{config.compiler[0]}-{config.optimize[0]}-{config.device[1]}"
if timestamp:
suffix += f"-{datetime.now().strftime('%Y%m%d%H%M%S')}"
return suffix
def image_name(config):
return f"Validation"
def project_name(config):
return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}"
def bl_image_name(config):
return f"Bootloader"
def bl_project_name(config):
return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}"
def output_dir(config):
return "outdir"
def bl_output_dir(config):
return "outdir"
def model_config(config):
return f"../Layer/Target/{config.device[1]}/model_config.txt"
@matrix_action
def clean(config):
"""Build the selected configurations using CMSIS-Build."""
yield cbuild_clean(f"{project_name(config)}/{project_name(config)}.cprj")
@matrix_action
def build(config, results):
"""Build the selected configurations using CMSIS-Build."""
if config.device.has_bl():
logging.info("Compiling Bootloader...")
yield csolution(f"{bl_project_name(config)}")
yield cbuild(f"{bl_project_name(config)}/{bl_project_name(config)}.cprj")
logging.info("Compiling Tests...")
if config.compiler == CompilerAxis.GCC and config.device.match("CA*"):
ldfile = Path(f"{project_name(config)}/RTE/Device/ARM{config.device[1]}/ARM{config.device[1]}.ld")
infile = ldfile.replace(ldfile.with_suffix('.ld.in'))
yield preprocess(infile, ldfile)
yield csolution(f"{project_name(config)}")
yield cbuild(f"{project_name(config)}/{project_name(config)}.cprj")
if not all(r.success for r in results):
return
file = f"Core_Validation-{config_suffix(config)}.zip"
logging.info(f"Archiving build output to {file}...")
with ZipFile(file, "w") as archive:
for content in iglob(f"{project_name(config)}/**/*", recursive=True):
if Path(content).is_file():
archive.write(content)
@matrix_action
def extract(config):
"""Extract the latest build archive."""
archives = sorted(glob(f"RTOS2_Validation-{config_suffix(config, timestamp=False)}-*.zip"), reverse=True)
yield unzip(archives[0])
@matrix_action
def run(config, results):
"""Run the selected configurations."""
logging.info("Running Core Validation on Arm model ...")
yield model_exec(config)
try:
results[0].test_report.write(f"Core_Validation-{config_suffix(config)}.junit")
except RuntimeError as e:
if isinstance(e.__cause__, XMLSyntaxError):
logging.error("No valid test report found in model output!")
else:
logging.exception(e)
@matrix_command()
def cbuild_clean(project):
return ["cbuild", "-c", project]
@matrix_command()
def unzip(archive):
return ["bash", "-c", f"unzip {archive}"]
@matrix_command()
def preprocess(infile, outfile):
return ["arm-none-eabi-gcc", "-xc", "-E", infile, "-P", "-o", outfile]
@matrix_command()
def csolution(project):
return ["csolution", "convert", "-s", "Validation.csolution.yml", "-c", project]
@matrix_command()
def cbuild(project):
return ["cbuild", project]
@matrix_command(test_report=ConsoleReport() |
CropReport('<\?xml version="1.0"\?>', '</report>') |
TransformReport('validation.xsl') |
JUnitReport(title=lambda title, result: f"{result.command.config.compiler}."
f"{result.command.config.optimize}."
f"{result.command.config.device}."
f"{title}"))
def model_exec(config):
cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)]
cmdline += MODEL_EXECUTABLE[config.device][1]
cmdline += ["-a", f"{project_name(config)}/{output_dir(config)}/{image_name(config)}.{config.compiler.image_ext}"]
if config.device.has_bl():
cmdline += ["-a", f"{bl_project_name(config)}/{bl_output_dir(config)}/{bl_image_name(config)}.{config.compiler.image_ext}"]
return cmdline
if __name__ == "__main__":
main()
``` | /content/code_sandbox/CMSIS/CoreValidation/Project/build.py | python | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,423 |
```c
/*your_sha256_hash-------------
* Name: CV_GenTimer.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_GenTimer_CNTFRQ(void) {
const uint32_t cntfrq1 = __get_CNTFRQ();
__set_CNTFRQ(cntfrq1 + 1U);
const uint32_t cntfrq2 = __get_CNTFRQ();
ASSERT_TRUE((cntfrq1 + 1U) == cntfrq2);
__set_CNTFRQ(cntfrq1);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_GenTimer_CNTP_TVAL(void) {
const uint32_t cntp_tval1 = __get_CNTP_TVAL();
__set_CNTP_TVAL(cntp_tval1 + 1U);
const uint32_t cntp_tval2 = __get_CNTP_TVAL();
ASSERT_TRUE((cntp_tval2 - cntp_tval1) >= 1ULL);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_GenTimer_CNTP_CTL(void) {
static const uint32_t CNTP_CTL_ENABLE = 0x01U;
const uint32_t cntp_ctl = __get_CNTP_CTL();
const uint32_t cntp_ctl_toggled = (cntp_ctl & (~CNTP_CTL_ENABLE)) | ((~cntp_ctl) & CNTP_CTL_ENABLE);
__set_CNTP_CTL(cntp_ctl_toggled);
const uint32_t cntp_ctl_new = __get_CNTP_CTL();
ASSERT_TRUE((cntp_ctl_toggled & CNTP_CTL_ENABLE) == (cntp_ctl_new & CNTP_CTL_ENABLE));
__set_CNTP_CTL(cntp_ctl);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_GenTimer_CNTPCT(void) {
const uint64_t cntpct1 = __get_CNTPCT();
for(int i=0; i<10; i++);
const uint64_t cntpct2 = __get_CNTPCT();
ASSERT_TRUE((cntpct2 - cntpct1) <= 120ULL);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_GenTimer_CNTP_CVAL(void) {
const uint64_t cntp_cval1 = __get_CNTP_CVAL();
__set_CNTP_CVAL(cntp_cval1 + 1ULL);
const uint64_t cntp_cval2 = __get_CNTP_CVAL();
ASSERT_TRUE((cntp_cval2 - cntp_cval1) >= 1ULL);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_GenTimer.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 713 |
```c
/*your_sha256_hash-------------
* Name: CV_CoreFunc.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_IRQ(void) {
uint32_t orig = __get_CPSR();
__enable_irq();
uint32_t cpsr = __get_CPSR();
ASSERT_TRUE((cpsr & CPSR_I_Msk) == 0U);
__disable_irq();
cpsr = __get_CPSR();
ASSERT_TRUE((cpsr & CPSR_I_Msk) == CPSR_I_Msk);
__set_CPSR(orig);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_FaultIRQ(void) {
uint32_t orig = __get_CPSR();
__enable_fault_irq();
uint32_t cpsr = __get_CPSR();
ASSERT_TRUE((cpsr & CPSR_F_Msk) == 0U);
__disable_fault_irq();
cpsr = __get_CPSR();
ASSERT_TRUE((cpsr & CPSR_F_Msk) == CPSR_F_Msk);
__set_CPSR(orig);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_FPSCR(void) {
volatile float f1 = 47.11f;
volatile float f2 = 8.15f;
volatile float f3 = f1 / f2;
uint32_t fpscr = __get_FPSCR();
__set_FPSCR(fpscr);
ASSERT_TRUE(fpscr == __get_FPSCR());
ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f));
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if defined(__CC_ARM)
#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn)
#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn)
#elif defined( __GNUC__ ) && defined(__thumb__)
#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
#else
#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
#endif
void TC_CoreAFunc_CPSR(void) {
uint32_t result;
uint32_t cpsr = __get_CPSR();
__set_CPSR(cpsr & CPSR_M_Msk);
// Check negative flag
int32_t Rm = 5;
int32_t Rn = 7;
__SUBS(Rm, Rm, Rn);
result = __get_CPSR();
ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk);
// Check zero and compare flag
Rm = 5;
__SUBS(Rm, Rm, Rm);
result = __get_CPSR();
ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk);
ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk);
// Check overflow flag
Rm = 5;
Rn = INT32_MAX;
__ADDS(Rm, Rm, Rn);
result = __get_CPSR();
ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_Mode(void) {
uint32_t mode = __get_mode();
__set_mode(mode);
ASSERT_TRUE(mode == __get_mode());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
static uint32_t TC_CoreAFunc_SP_orig;
static uint32_t TC_CoreAFunc_SP_sp;
static uint32_t TC_CoreAFunc_SP_result;
void TC_CoreAFunc_SP(void) {
TC_CoreAFunc_SP_orig = __get_SP();
TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U;
__set_SP(TC_CoreAFunc_SP_sp);
TC_CoreAFunc_SP_result = __get_SP();
__set_SP(TC_CoreAFunc_SP_orig);
ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
static uint32_t TC_CoreAFunc_SP_usr_orig;
static uint32_t TC_CoreAFunc_SP_usr_sp;
static uint32_t TC_CoreAFunc_SP_usr_result;
void TC_CoreAFunc_SP_usr(void) {
TC_CoreAFunc_SP_usr_orig = __get_SP_usr();
TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U;
__set_SP(TC_CoreAFunc_SP_usr_sp);
TC_CoreAFunc_SP_usr_result = __get_SP_usr();
__set_SP(TC_CoreAFunc_SP_usr_orig);
ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_FPEXC(void) {
uint32_t fpexc = __get_FPEXC();
__set_FPEXC(fpexc);
ASSERT_TRUE(fpexc == __get_FPEXC());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_ACTLR(void) {
uint32_t actlr = __get_ACTLR();
__set_ACTLR(actlr);
ASSERT_TRUE(actlr == __get_ACTLR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_CPACR(void) {
uint32_t cpacr = __get_CPACR();
__set_CPACR(cpacr);
ASSERT_TRUE(cpacr == __get_CPACR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_DFSR(void) {
uint32_t dfsr = __get_DFSR();
__set_DFSR(dfsr);
ASSERT_TRUE(dfsr == __get_DFSR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_IFSR(void) {
uint32_t ifsr = __get_IFSR();
__set_IFSR(ifsr);
ASSERT_TRUE(ifsr == __get_IFSR());
}
/*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_ISR(void) {
uint32_t isr = __get_ISR();
ASSERT_TRUE(isr == __get_ISR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_CBAR(void) {
uint32_t cbar = __get_CBAR();
ASSERT_TRUE(cbar == __get_CBAR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_TTBR0(void) {
uint32_t ttbr0 = __get_TTBR0();
__set_TTBR0(ttbr0);
ASSERT_TRUE(ttbr0 == __get_TTBR0());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_DACR(void) {
uint32_t dacr = __get_DACR();
__set_DACR(dacr);
ASSERT_TRUE(dacr == __get_DACR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_SCTLR(void) {
uint32_t sctlr = __get_SCTLR();
__set_SCTLR(sctlr);
ASSERT_TRUE(sctlr == __get_SCTLR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_ACTRL(void) {
uint32_t actrl = __get_ACTRL();
__set_ACTRL(actrl);
ASSERT_TRUE(actrl == __get_ACTRL());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_MPIDR(void) {
uint32_t mpidr = __get_MPIDR();
ASSERT_TRUE(mpidr == __get_MPIDR());
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
static uint8_t vectorRAM[32U] __attribute__((aligned(32U)));
void TC_CoreAFunc_VBAR(void) {
uint32_t vbar = __get_VBAR();
memcpy(vectorRAM, (void*)vbar, sizeof(vectorRAM));
__set_VBAR((uint32_t)vectorRAM);
ASSERT_TRUE(((uint32_t)vectorRAM) == __get_VBAR());
__set_VBAR(vbar);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_MVBAR(void) {
uint32_t mvbar = __get_MVBAR();
memcpy(vectorRAM, (void*)mvbar, sizeof(vectorRAM));
__set_MVBAR((uint32_t)vectorRAM);
ASSERT_TRUE(((uint32_t)vectorRAM) == __get_MVBAR());
__set_MVBAR(mvbar);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CoreAFunc_FPU_Enable(void) {
uint32_t fpexc = __get_FPEXC();
__set_FPEXC(fpexc & ~0x40000000u); // disable FPU
uint32_t cp15;
__get_CP(15, 0, cp15, 1, 0, 2);
cp15 &= ~0x00F00000u;
__set_CP(15, 0, cp15, 1, 0, 2); // disable FPU access
__FPU_Enable();
__get_CP(15, 0, cp15, 1, 0, 2);
ASSERT_TRUE((cp15 & 0x00F00000u) == 0x00F00000u);
fpexc = __get_FPEXC();
ASSERT_TRUE((fpexc & 0x40000000u) == 0x40000000u);
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CoreAFunc.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,717 |
```c
/*your_sha256_hash-------------
* Name: CV_MPU_ARMv7.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static void ClearMpu(void) {
for(uint32_t i = 0U; i < 8U; ++i) {
MPU->RNR = i;
MPU->RBAR = 0U;
MPU->RLAR = 0U;
}
}
#endif
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_MPU_SetClear
\details
- Check if ARM_MPU_Load correctly loads MPU table to registers.
*/
void TC_MPU_SetClear(void)
{
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static const ARM_MPU_Region_t table[] = {
{ .RBAR = 0U, .RLAR = 0U },
{ .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) }
};
#define ASSERT_MPU_REGION(rnr, region) \
MPU->RNR = rnr; \
ASSERT_TRUE(MPU->RBAR == region.RBAR); \
ASSERT_TRUE(MPU->RLAR == region.RLAR)
ClearMpu();
ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR);
ASSERT_MPU_REGION(1U, table[0]);
ASSERT_MPU_REGION(2U, table[1]);
ASSERT_MPU_REGION(3U, table[0]);
ARM_MPU_ClrRegion(2U);
MPU->RNR = 2U;
ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U);
#undef ASSERT_MPU_REGION
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_MPU_Load
\details
- Check if ARM_MPU_Load correctly loads MPU table to registers.
*/
void TC_MPU_Load(void)
{
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static const ARM_MPU_Region_t table[] = {
{ .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) },
{ .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) }
};
#define ASSERT_MPU_REGION(rnr, table) \
MPU->RNR = rnr; \
ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \
ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR)
ClearMpu();
ARM_MPU_Load(0U, &(table[0]), 1U);
ASSERT_MPU_REGION(0U, table);
ARM_MPU_Load(1U, &(table[1]), 5U);
ASSERT_MPU_REGION(0U, table);
ASSERT_MPU_REGION(1U, table);
ASSERT_MPU_REGION(2U, table);
ASSERT_MPU_REGION(3U, table);
ASSERT_MPU_REGION(4U, table);
ASSERT_MPU_REGION(5U, table);
ARM_MPU_Load(6U, &(table[6]), 2U);
ASSERT_MPU_REGION(5U, table);
ASSERT_MPU_REGION(6U, table);
ASSERT_MPU_REGION(7U, table);
#undef ASSERT_MPU_REGION
#endif
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,303 |
```c
/*your_sha256_hash-------------
* Name: CV_CML1Cache.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CML1Cache_EnDisableICache(void) {
#ifdef __ICACHE_PRESENT
SCB_EnableICache();
ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk);
SCB_DisableICache();
ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CML1Cache_EnDisableDCache(void) {
#ifdef __DCACHE_PRESENT
SCB_EnableDCache();
ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk);
SCB_DisableDCache();
ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#ifdef __DCACHE_PRESENT
static uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U };
#endif
void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) {
#ifdef __DCACHE_PRESENT
SCB_DisableDCache();
SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0]));
ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
#endif
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CML1Cache.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 508 |
```c
/*your_sha256_hash-------------
* Name: CV_CAL1Cache.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_EnDisable(void) {
uint32_t orig = __get_SCTLR();
L1C_EnableCaches();
uint32_t sctlr = __get_SCTLR();
ASSERT_TRUE((sctlr & SCTLR_I_Msk) == SCTLR_I_Msk);
ASSERT_TRUE((sctlr & SCTLR_C_Msk) == SCTLR_C_Msk);
L1C_CleanDCacheAll();
L1C_DisableCaches();
sctlr = __get_SCTLR();
ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U);
ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U);
__set_SCTLR(orig);
__ISB();
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_EnDisableBTAC(void) {
uint32_t orig = __get_SCTLR();
L1C_EnableBTAC();
uint32_t sctlr = __get_SCTLR();
ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
L1C_DisableBTAC();
sctlr = __get_SCTLR();
#if __CORTEX_A == 7
// On Cortex-A7 SCTLR_Z is RAO/WI.
ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
#else
ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U);
#endif
__set_SCTLR(orig);
__ISB();
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_log2_up(void) {
uint8_t log2 = __log2_up(0U);
ASSERT_TRUE(log2 == 0U);
log2 = __log2_up(1U);
ASSERT_TRUE(log2 == 0U);
log2 = __log2_up(2U);
ASSERT_TRUE(log2 == 1U);
log2 = __log2_up(3U);
ASSERT_TRUE(log2 == 2U);
log2 = __log2_up(4U);
ASSERT_TRUE(log2 == 2U);
log2 = __log2_up(0x80000000U);
ASSERT_TRUE(log2 == 31U);
log2 = __log2_up(0x80000001U);
ASSERT_TRUE(log2 == 32U);
log2 = __log2_up(0xFFFFFFFFU);
ASSERT_TRUE(log2 == 32U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_InvalidateDCacheAll(void) {
/* setup */
uint32_t orig = __get_SCTLR();
volatile uint32_t value = 0x0815U;
L1C_EnableCaches();
L1C_CleanDCacheAll();
/* test cached value gets lost */
// WHEN a value is written
value = 0x4711U;
// ... and the cache is invalidated
L1C_InvalidateDCacheAll();
// ... and the cache is disabled
L1C_DisableCaches();
// THEN the new value has been lost
ASSERT_TRUE(value == 0x0815U);
/* tear down */
L1C_InvalidateDCacheAll();
__set_SCTLR(orig);
__ISB();
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_CleanDCacheAll(void) {
/* setup */
uint32_t orig = __get_SCTLR();
uint32_t value = 0x0815U;
L1C_EnableCaches();
L1C_CleanDCacheAll();
/* test cached value is preserved */
// WHEN a value is written
value = 0x4711U;
// ... and the cache is cleaned
L1C_CleanDCacheAll();
// ... and the cache is disabled
L1C_DisableCaches();
// THEN the new value is preserved
ASSERT_TRUE(value == 0x4711U);
/* tear down */
L1C_InvalidateDCacheAll();
__set_SCTLR(orig);
__ISB();
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
void TC_CAL1Cache_CleanInvalidateDCacheAll(void) {
/* setup */
uint32_t orig = __get_SCTLR();
uint32_t value = 0x0815U;
L1C_EnableCaches();
L1C_CleanDCacheAll();
/* test cached value is preserved */
// WHEN a value is written
value = 0x4711U;
// ... and the cache is cleaned/invalidated
L1C_CleanInvalidateDCacheAll();
// ... and the cache is disabled
L1C_DisableCaches();
// THEN the new value is preserved
ASSERT_TRUE(value == 0x4711U);
/* tear down */
L1C_InvalidateDCacheAll();
__set_SCTLR(orig);
__ISB();
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CAL1Cache.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,339 |
```c
/*your_sha256_hash-------------
* Name: CV_MPU_ARMv7.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static void ClearMpu(void) {
for(uint32_t i = 0U; i < 8U; ++i) {
MPU->RNR = i;
MPU->RBAR = 0U;
MPU->RASR = 0U;
}
}
#endif
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_MPU_SetClear
\details
- Check if ARM_MPU_Load correctly loads MPU table to registers.
*/
void TC_MPU_SetClear(void)
{
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static const ARM_MPU_Region_t table[] = {
{ .RBAR = 0U, .RASR = 0U },
{ .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
{ .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }
};
#define ASSERT_MPU_REGION(rnr, region) \
MPU->RNR = rnr; \
ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \
ASSERT_TRUE(MPU->RASR == region.RASR)
ClearMpu();
ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR);
ASSERT_MPU_REGION(1U, table[0]);
ASSERT_MPU_REGION(2U, table[1]);
ASSERT_MPU_REGION(3U, table[0]);
ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR);
ASSERT_MPU_REGION(4U, table[0]);
ASSERT_MPU_REGION(5U, table[2]);
ASSERT_MPU_REGION(6U, table[0]);
ARM_MPU_ClrRegion(5U);
MPU->RNR = 5U;
ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U);
#undef ASSERT_MPU_REGION
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_MPU_Load
\details
- Check if ARM_MPU_Load correctly loads MPU table to registers.
*/
void TC_MPU_Load(void)
{
#if defined(__MPU_PRESENT) && __MPU_PRESENT
static const ARM_MPU_Region_t table[] = {
{ .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) },
{ .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) },
{ .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
{ .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) },
{ .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) },
{ .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB) },
{ .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB) },
{ .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB) }
};
#define ASSERT_MPU_REGION(rnr, table) \
MPU->RNR = rnr; \
ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \
ASSERT_TRUE(MPU->RASR == table[rnr].RASR)
ClearMpu();
ARM_MPU_Load(&(table[0]), 1U);
ASSERT_MPU_REGION(0U, table);
ARM_MPU_Load(&(table[1]), 5U);
ASSERT_MPU_REGION(0U, table);
ASSERT_MPU_REGION(1U, table);
ASSERT_MPU_REGION(2U, table);
ASSERT_MPU_REGION(3U, table);
ASSERT_MPU_REGION(4U, table);
ASSERT_MPU_REGION(5U, table);
ARM_MPU_Load(&(table[6]), 2U);
ASSERT_MPU_REGION(5U, table);
ASSERT_MPU_REGION(6U, table);
ASSERT_MPU_REGION(7U, table);
#undef ASSERT_MPU_REGION
#endif
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,616 |
```c
/*your_sha256_hash-------------
* Name: CV_CoreInstr.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
#if defined(__CORTEX_M)
#elif defined(__CORTEX_A)
#include "irq_ctrl.h"
#else
#error __CORTEX_M or __CORTEX_A must be defined!
#endif
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_NOP
\details
- Check if __NOP instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_NOP (void) {
__NOP();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_SEV
\details
- Check if __SEV instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_SEV (void) {
__SEV();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_BKPT
\details
- Check if __BKPT instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_BKPT (void) {
__BKPT(0xABU);
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_ISB
\details
- Check if __ISB instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_ISB (void) {
__ISB();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_DSB
\details
- Check if __DSB instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_DSB (void) {
__DSB();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_DMB
\details
- Check if __DNB instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_DMB (void) {
__DMB();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_WFI
\details
- Check if __WFI instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_WFI (void) {
__WFI();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_WFE
\details
- Check if __WFE instrinsic is available
- No real assertion is deployed, just a compile time check.
*/
void TC_CoreInstr_WFE (void) {
__WFE();
ASSERT_TRUE(1U == 1U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_REV
\details
- Check if __REV instrinsic swaps all bytes in a word.
*/
void TC_CoreInstr_REV (void) {
volatile uint32_t op1_u32;
volatile uint32_t res_u32;
op1_u32 = 0x47110815U;
res_u32 = __REV(op1_u32);
ASSERT_TRUE(res_u32 == 0x15081147U);
op1_u32 = 0x80000000U;
res_u32 = __REV(op1_u32);
ASSERT_TRUE(res_u32 == 0x00000080U);
op1_u32 = 0x00000080U;
res_u32 = __REV(op1_u32);
ASSERT_TRUE(res_u32 == 0x80000000U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_REV16
\details
- Check if __REV16 instrinsic swaps the bytes in both halfwords independendly.
*/
void TC_CoreInstr_REV16(void) {
volatile uint32_t op1_u32;
volatile uint32_t res_u32;
op1_u32 = 0x47110815U;
res_u32 = __REV16(op1_u32);
ASSERT_TRUE(res_u32 == 0x11471508U);
op1_u32 = 0x00001234U;
res_u32 = __REV16(op1_u32);
ASSERT_TRUE(res_u32 == 0x00003412U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_REVSH
\details
- Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign.
*/
void TC_CoreInstr_REVSH(void) {
volatile int16_t value = 0U;
int16_t result = 0U;
value = 0x4711;
result = __REVSH(value);
ASSERT_TRUE(result == 0x1147);
value = (int16_t)0x8000;
result = __REVSH(value);
ASSERT_TRUE(result == 0x0080);
value = 0x0080;
result = __REVSH(value);
ASSERT_TRUE(result == (int16_t)0x8000);
value = -0x1234;
result = __REVSH(value);
ASSERT_TRUE(result == (int16_t)0xcced);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_RBIT
\details
- Check if __RBIT instrinsic revserses the bit order of arbitrary words.
*/
void TC_CoreInstr_RBIT (void) {
volatile uint32_t value = 0U;
uint32_t result = 0U;
value = 0xAAAAAAAAU;
result = __RBIT(value);
ASSERT_TRUE(result == 0x55555555U);
value = 0x55555555U;
result = __RBIT(value);
ASSERT_TRUE(result == 0xAAAAAAAAU);
value = 0x00000001U;
result = __RBIT(value);
ASSERT_TRUE(result == 0x80000000U);
value = 0x80000000U;
result = __RBIT(value);
ASSERT_TRUE(result == 0x00000001U);
value = 0xDEADBEEFU;
result = __RBIT(value);
ASSERT_TRUE(result == 0xF77DB57BU);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_ROR
\details
- Check if __ROR instrinsic moves all bits as expected.
*/
void TC_CoreInstr_ROR(void) {
volatile uint32_t value = 0U;
uint32_t result = 0U;
value = 0x00000001U;
result = __ROR(value, 1U);
ASSERT_TRUE(result == 0x80000000U);
value = 0x80000000U;
result = __ROR(value, 1U);
ASSERT_TRUE(result == 0x40000000U);
value = 0x40000000U;
result = __ROR(value, 30U);
ASSERT_TRUE(result == 0x00000001U);
value = 0x00000001U;
result = __ROR(value, 32U);
ASSERT_TRUE(result == 0x00000001U);
value = 0x08154711U;
result = __ROR(value, 8U);
ASSERT_TRUE(result == 0x11081547U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_CLZ
\details
- Check if __CLZ instrinsic counts leading zeros.
*/
void TC_CoreInstr_CLZ (void) {
volatile uint32_t value = 0U;
uint32_t result = 0U;
value = 0x00000000U;
result = __CLZ(value);
ASSERT_TRUE(result == 32);
value = 0x00000001U;
result = __CLZ(value);
ASSERT_TRUE(result == 31);
value = 0x40000000U;
result = __CLZ(value);
ASSERT_TRUE(result == 1);
value = 0x80000000U;
result = __CLZ(value);
ASSERT_TRUE(result == 0);
value = 0xFFFFFFFFU;
result = __CLZ(value);
ASSERT_TRUE(result == 0);
value = 0x80000001U;
result = __CLZ(value);
ASSERT_TRUE(result == 0);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_SSAT
\details
- Check if __SSAT instrinsic saturates signed integer values.
*/
void TC_CoreInstr_SSAT (void) {
volatile int32_t value = 0;
int32_t result = 0;
value = INT32_MAX;
result = __SSAT(value, 32U);
ASSERT_TRUE(result == INT32_MAX);
value = INT32_MAX;
result = __SSAT(value, 16U);
ASSERT_TRUE(result == INT16_MAX);
value = INT32_MAX;
result = __SSAT(value, 8U);
ASSERT_TRUE(result == INT8_MAX);
value = INT32_MAX;
result = __SSAT(value, 1U);
ASSERT_TRUE(result == 0);
value = INT32_MIN;
result = __SSAT(value, 32U);
ASSERT_TRUE(result == INT32_MIN);
value = INT32_MIN;
result = __SSAT(value, 16U);
ASSERT_TRUE(result == INT16_MIN);
value = INT32_MIN;
result = __SSAT(value, 8U);
ASSERT_TRUE(result == INT8_MIN);
value = INT32_MIN;
result = __SSAT(value, 1U);
ASSERT_TRUE(result == -1);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_USAT
\details
- Check if __USAT instrinsic saturates unsigned integer values.
*/
void TC_CoreInstr_USAT (void) {
volatile int32_t value = 0U;
uint32_t result = 0U;
value = INT32_MAX;
result = __USAT(value, 31U);
ASSERT_TRUE(result == (UINT32_MAX >> 1U));
value = INT32_MAX;
result = __USAT(value, 16U);
ASSERT_TRUE(result == UINT16_MAX);
value = INT32_MAX;
result = __USAT(value, 8U);
ASSERT_TRUE(result == UINT8_MAX);
value = INT32_MAX;
result = __USAT(value, 0U);
ASSERT_TRUE(result == 0U);
value = INT32_MIN;
result = __USAT(value, 31U);
ASSERT_TRUE(result == 0U);
value = INT32_MIN;
result = __USAT(value, 16U);
ASSERT_TRUE(result == 0U);
value = INT32_MIN;
result = __USAT(value, 8U);
ASSERT_TRUE(result == 0U);
value = INT32_MIN;
result = __USAT(value, 0U);
ASSERT_TRUE(result == 0U);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreInstr_RRX
\details
- Check if __USAT instrinsic saturates unsigned integer values.
*/
void TC_CoreInstr_RRX (void) {
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
volatile uint32_t value = 0U;
volatile uint32_t result = 0U;
volatile xPSR_Type xPSR;
value = 0x80000002;
xPSR.w = __get_xPSR();
result = __RRX(value);
ASSERT_TRUE(result == (0x40000001 | (uint32_t)(xPSR.b.C << 31)));
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined(__CORTEX_A) ) )
/// Exclusive byte value
static volatile uint8_t TC_CoreInstr_LoadStoreExclusive_byte = 0x47U;
/// Exclusive halfword value
static volatile uint16_t TC_CoreInstr_LoadStoreExclusive_hword = 0x0815U;
/// Exclusive word value
static volatile uint32_t TC_CoreInstr_LoadStoreExclusive_word = 0x08154711U;
/**
\brief Interrupt function for TC_CoreInstr_LoadStoreExclusive
\details
The interrupt manipulates all the global data
which disrupts the exclusive sequences in the test
*/
static void TC_CoreInstr_LoadStoreExclusive_IRQHandler(void) {
const uint8_t b = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
__STREXB((uint8_t)~b, &TC_CoreInstr_LoadStoreExclusive_byte);
const uint16_t hw = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
__STREXH((uint16_t)~hw, &TC_CoreInstr_LoadStoreExclusive_hword);
const uint32_t w = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
__STREXW((uint32_t)~w, &TC_CoreInstr_LoadStoreExclusive_word);
}
/**
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to enable test interrupt.
\details
This helper function implements interrupt enabling according to target
architecture, i.e. Cortex-A or Cortex-M.
*/
static void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) {
#if defined(__CORTEX_M)
TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler;
NVIC_EnableIRQ(Interrupt0_IRQn);
#elif defined(__CORTEX_A)
IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler);
IRQ_Enable(SGI0_IRQn);
#else
#error __CORTEX_M or __CORTEX_A must be defined!
#endif
__enable_irq();
}
/**
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to set test interrupt pending.
\details
This helper function implements set pending the test interrupt according to target
architecture, i.e. Cortex-A or Cortex-M.
*/
static void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) {
#if defined(__CORTEX_M)
NVIC_SetPendingIRQ(Interrupt0_IRQn);
#elif defined(__CORTEX_A)
IRQ_SetPending(SGI0_IRQn);
#else
#error __CORTEX_M or __CORTEX_A must be defined!
#endif
for(uint32_t i = 10U; i > 0U; --i) {}
}
/**
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to disable test interrupt.
\details
This helper function implements interrupt disabling according to target
architecture, i.e. Cortex-A or Cortex-M.
*/
static void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) {
__disable_irq();
#if defined(__CORTEX_M)
NVIC_DisableIRQ(Interrupt0_IRQn);
TST_IRQHandler = NULL;
#elif defined(__CORTEX_A)
IRQ_Disable(SGI0_IRQn);
IRQ_SetHandler(SGI0_IRQn, NULL);
#else
#error __CORTEX_M or __CORTEX_A must be defined!
#endif
}
#endif
/**
\brief Test case: TC_CoreInstr_LoadStoreExclusive
\details
Checks exclusive load and store instructions:
- LDREXB, LDREXH, LDREXW
- STREXB, STREXH, STREXW
- CLREX
*/
void TC_CoreInstr_LoadStoreExclusive (void) {
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined(__CORTEX_A) ) )
uint8_t u8, u8Inv;
uint16_t u16, u16Inv;
uint32_t u32, u32Inv;
uint32_t result;
/* 1. Test exclusives without interruption */
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8+1U);
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16+1U);
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32+1U);
/* 2. Test exclusives with clear */
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
__CLREX();
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(result == 1U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8);
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
__CLREX();
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(result == 1U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16);
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
__CLREX();
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(result == 1U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32);
/* 3. Test exclusives with interruption */
TC_CoreInstr_LoadStoreExclusive_IRQEnable();
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
TC_CoreInstr_LoadStoreExclusive_IRQPend();
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
ASSERT_TRUE(result == 1U);
u8Inv = (uint8_t)~u8;
ASSERT_TRUE(u8Inv == TC_CoreInstr_LoadStoreExclusive_byte);
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
TC_CoreInstr_LoadStoreExclusive_IRQPend();
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
ASSERT_TRUE(result == 1U);
u16Inv = (uint16_t)~u16;
ASSERT_TRUE(u16Inv == TC_CoreInstr_LoadStoreExclusive_hword);
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
TC_CoreInstr_LoadStoreExclusive_IRQPend();
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
ASSERT_TRUE(result == 1U);
u32Inv = (uint32_t)~u32;
ASSERT_TRUE(u32Inv == TC_CoreInstr_LoadStoreExclusive_word);
TC_CoreInstr_LoadStoreExclusive_IRQDisable();
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
/// byte value unprivileged access
static volatile uint8_t TC_CoreInstr_LoadStoreUnpriv_byte = 0x47U;
/// halfword value unprivileged access
static volatile uint16_t TC_CoreInstr_LoadStoreUnpriv_hword = 0x0815U;
/// word value unprivileged access
static volatile uint32_t TC_CoreInstr_LoadStoreUnpriv_word = 0x08154711U;
#endif
/**
\brief Test case: TC_CoreInstr_LoadStoreUnpriv
\details
Checks load/store unprivileged instructions:
- LDRBT, LDRHT, LDRT
- STRBT, STRHT, STRT
*/
void TC_CoreInstr_LoadStoreUnpriv (void) {
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
uint8_t u8 = 0U;
uint16_t u16 = 0U;
uint32_t u32 = 0U;
/* 1. Test without interruption */
u8 = __LDRBT(&TC_CoreInstr_LoadStoreUnpriv_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreUnpriv_byte);
__STRBT(u8+1U, &TC_CoreInstr_LoadStoreUnpriv_byte);
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_byte == u8+1U);
u16 = __LDRHT(&TC_CoreInstr_LoadStoreUnpriv_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreUnpriv_hword);
__STRHT(u16+1U, &TC_CoreInstr_LoadStoreUnpriv_hword);
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_hword == u16+1U);
u32 = __LDRT(&TC_CoreInstr_LoadStoreUnpriv_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreUnpriv_word);
__STRT(u32+1U, &TC_CoreInstr_LoadStoreUnpriv_word);
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_word == u32+1U);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/// byte value unprivileged access
static volatile uint8_t TC_CoreInstr_LoadStoreAcquire_byte = 0x47U;
/// halfword value unprivileged access
static volatile uint16_t TC_CoreInstr_LoadStoreAcquire_hword = 0x0815U;
/// word value unprivileged access
static volatile uint32_t TC_CoreInstr_LoadStoreAcquire_word = 0x08154711U;
#endif
/**
\brief Test case: TC_CoreInstr_LoadStoreAquire
\details
Checks Load-Acquire and Store-Release instructions:
- LDAB, LDAH, LDA
- STLB, STLH, STL
*/
void TC_CoreInstr_LoadStoreAcquire (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
uint8_t u8 = 0U;
uint16_t u16 = 0U;
uint32_t u32 = 0U;
/* 1. Test without interruption */
u8 = __LDAB(&TC_CoreInstr_LoadStoreAcquire_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquire_byte);
__STLB(u8+1U, &TC_CoreInstr_LoadStoreAcquire_byte);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_byte == u8+1U);
u16 = __LDAH(&TC_CoreInstr_LoadStoreAcquire_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquire_hword);
__STLH(u16+1U, &TC_CoreInstr_LoadStoreAcquire_hword);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_hword == u16+1U);
u32 = __LDA(&TC_CoreInstr_LoadStoreAcquire_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquire_word);
__STL(u32+1U, &TC_CoreInstr_LoadStoreAcquire_word);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_word == u32+1U);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
/// byte value unprivileged access
static volatile uint8_t TC_CoreInstr_LoadStoreAcquireExclusive_byte = 0x47U;
/// halfword value unprivileged access
static volatile uint16_t TC_CoreInstr_LoadStoreAcquireExclusive_hword = 0x0815U;
/// word value unprivileged access
static volatile uint32_t TC_CoreInstr_LoadStoreAcquireExclusive_word = 0x08154711U;
#endif
/**
\brief Test case: TC_CoreInstr_LoadStoreAquire
\details
Checks Load-Acquire and Store-Release exclusive instructions:
- LDAEXB, LDAEXH, LDAEX
- STLEXB, STLEXH, STLEX
*/
void TC_CoreInstr_LoadStoreAcquireExclusive (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
uint8_t u8 = 0U;
uint16_t u16 = 0U;
uint32_t u32 = 0U;
uint32_t result = 0U;
/* 1. Test without interruption */
u8 = __LDAEXB(&TC_CoreInstr_LoadStoreAcquireExclusive_byte);
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquireExclusive_byte);
result = __STLEXB(u8+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_byte);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_byte == u8+1U);
u16 = __LDAEXH(&TC_CoreInstr_LoadStoreAcquireExclusive_hword);
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquireExclusive_hword);
result = __STLEXH(u16+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_hword);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_hword == u16+1U);
u32 = __LDAEX(&TC_CoreInstr_LoadStoreAcquireExclusive_word);
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquireExclusive_word);
result = __STLEX(u32+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_word);
ASSERT_TRUE(result == 0U);
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_word == u32+1U);
#endif
}
/**
\brief Test case: TC_CoreInstr_UnalignedUint16
\details
Checks macro functions to access unaligned uint16_t values:
- __UNALIGNED_UINT16_READ
- __UNALIGNED_UINT16_WRITE
*/
void TC_CoreInstr_UnalignedUint16(void) {
uint8_t buffer[3] = { 0U, 0U, 0U };
uint16_t val;
for(int i=0; i<2; i++) {
__UNALIGNED_UINT16_WRITE(&(buffer[i]), 0x4711U);
ASSERT_TRUE(buffer[i] == 0x11U);
ASSERT_TRUE(buffer[i+1] == 0x47U);
ASSERT_TRUE(buffer[(i+2)%3] == 0x00U);
buffer[i] = 0x12U;
buffer[i+1] = 0x46U;
val = __UNALIGNED_UINT16_READ(&(buffer[i]));
ASSERT_TRUE(val == 0x4612U);
buffer[i] = 0x00U;
buffer[i+1] = 0x00U;
}
}
/**
\brief Test case: TC_CoreInstr_UnalignedUint32
\details
Checks macro functions to access unaligned uint32_t values:
- __UNALIGNED_UINT32_READ
- __UNALIGNED_UINT32_WRITE
*/
void TC_CoreInstr_UnalignedUint32(void) {
uint8_t buffer[7] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U };
uint32_t val;
for(int i=0; i<4; i++) {
__UNALIGNED_UINT32_WRITE(&(buffer[i]), 0x08154711UL);
ASSERT_TRUE(buffer[i+0] == 0x11U);
ASSERT_TRUE(buffer[i+1] == 0x47U);
ASSERT_TRUE(buffer[i+2] == 0x15U);
ASSERT_TRUE(buffer[i+3] == 0x08U);
ASSERT_TRUE(buffer[(i+4)%7] == 0x00U);
ASSERT_TRUE(buffer[(i+5)%7] == 0x00U);
ASSERT_TRUE(buffer[(i+6)%7] == 0x00U);
buffer[i+0] = 0x12U;
buffer[i+1] = 0x46U;
buffer[i+2] = 0x14U;
buffer[i+3] = 0x09U;
val = __UNALIGNED_UINT32_READ(&(buffer[i]));
ASSERT_TRUE(val == 0x09144612UL);
buffer[i+0] = 0x00U;
buffer[i+1] = 0x00U;
buffer[i+2] = 0x00U;
buffer[i+3] = 0x00U;
}
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CoreInstr.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 7,738 |
```c
/*your_sha256_hash-------------
* Name: CV_CoreFunc.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
static volatile uint32_t irqTaken = 0U;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
static volatile uint32_t irqActive = 0U;
#endif
static void TC_CoreFunc_EnDisIRQIRQHandler(void) {
++irqTaken;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
irqActive = NVIC_GetActive(Interrupt0_IRQn);
#endif
}
static volatile uint32_t irqIPSR = 0U;
static volatile uint32_t irqXPSR = 0U;
static void TC_CoreFunc_IPSR_IRQHandler(void) {
irqIPSR = __get_IPSR();
irqXPSR = __get_xPSR();
}
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_EnDisIRQ
\details
Check expected behavior of interrupt related control functions:
- __disable_irq() and __enable_irq()
- NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ
- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ
- NVIC_GetActive (not on Cortex-M0/M0+)
*/
void TC_CoreFunc_EnDisIRQ (void)
{
// Globally disable all interrupt servicing
__disable_irq();
// Enable the interrupt
NVIC_EnableIRQ(Interrupt0_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U);
// Clear its pending state
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
// Register test interrupt handler.
TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
irqTaken = 0U;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
irqActive = UINT32_MAX;
#endif
// Set the interrupt pending state
NVIC_SetPendingIRQ(Interrupt0_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
// Interrupt is not taken
ASSERT_TRUE(irqTaken == 0U);
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
#endif
// Globally enable interrupt servicing
__enable_irq();
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
// Interrupt was taken
ASSERT_TRUE(irqTaken == 1U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(irqActive != 0U);
ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
#endif
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
// Disable interrupt
NVIC_DisableIRQ(Interrupt0_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U);
// Set interrupt pending
NVIC_SetPendingIRQ(Interrupt0_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
// Interrupt is not taken again
ASSERT_TRUE(irqTaken == 1U);
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
// Clear interrupt pending
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
// Globally disable interrupt servicing
__disable_irq();
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_IRQPrio
\details
Check expected behavior of interrupt priority control functions:
- NVIC_SetPriority, NVIC_GetPriority
*/
void TC_CoreFunc_IRQPrio (void)
{
/* Test Exception Priority */
uint32_t orig = NVIC_GetPriority(SVCall_IRQn);
NVIC_SetPriority(SVCall_IRQn, orig+1U);
uint32_t prio = NVIC_GetPriority(SVCall_IRQn);
ASSERT_TRUE(prio == orig+1U);
NVIC_SetPriority(SVCall_IRQn, orig);
/* Test Interrupt Priority */
orig = NVIC_GetPriority(Interrupt0_IRQn);
NVIC_SetPriority(Interrupt0_IRQn, orig+1U);
prio = NVIC_GetPriority(Interrupt0_IRQn);
ASSERT_TRUE(prio == orig+1U);
NVIC_SetPriority(Interrupt0_IRQn, orig);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/** Helper function for TC_CoreFunc_EncDecIRQPrio
\details
The helper encodes and decodes the given priority configuration.
\param[in] prigroup The PRIGROUP setting to be considered for encoding/decoding.
\param[in] pre The preempt priority value.
\param[in] sub The subpriority value.
*/
static void TC_CoreFunc_EncDecIRQPrio_Step(uint32_t prigroup, uint32_t pre, uint32_t sub) {
uint32_t prio = NVIC_EncodePriority(prigroup, pre, sub);
uint32_t ret_pre = UINT32_MAX;
uint32_t ret_sub = UINT32_MAX;
NVIC_DecodePriority(prio, prigroup, &ret_pre, &ret_sub);
ASSERT_TRUE(ret_pre == pre);
ASSERT_TRUE(ret_sub == sub);
}
/**
\brief Test case: TC_CoreFunc_EncDecIRQPrio
\details
Check expected behavior of interrupt priority encoding/decoding functions:
- NVIC_EncodePriority, NVIC_DecodePriority
*/
void TC_CoreFunc_EncDecIRQPrio (void)
{
/* Check only the valid range of PRIGROUP and preempt-/sub-priority values. */
static const uint32_t priobits = (__NVIC_PRIO_BITS > 7U) ? 7U : __NVIC_PRIO_BITS;
for(uint32_t prigroup = 7U-priobits; prigroup<7U; prigroup++) {
for(uint32_t pre = 0U; pre<(128U>>prigroup); pre++) {
for(uint32_t sub = 0U; sub<(256U>>(8U-__NVIC_PRIO_BITS+7U-prigroup)); sub++) {
TC_CoreFunc_EncDecIRQPrio_Step(prigroup, pre, sub);
}
}
}
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_IRQVect
\details
Check expected behavior of interrupt vector relocation functions:
- NVIC_SetVector, NVIC_GetVector
*/
void TC_CoreFunc_IRQVect(void) {
#if defined(__VTOR_PRESENT) && __VTOR_PRESENT
/* relocate vector table */
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
static VECTOR_TABLE_Type vectors[sizeof(__VECTOR_TABLE)/sizeof(__VECTOR_TABLE[0])] __ALIGNED(1024) __NO_INIT;
memcpy(vectors, __VECTOR_TABLE, sizeof(__VECTOR_TABLE));
const uint32_t orig_vtor = SCB->VTOR;
const uint32_t vtor = ((uint32_t)vectors) & SCB_VTOR_TBLOFF_Msk;
SCB->VTOR = vtor;
ASSERT_TRUE(vtor == SCB->VTOR);
/* check exception vectors */
extern void HardFault_Handler(void);
extern void SVC_Handler(void);
extern void PendSV_Handler(void);
extern void SysTick_Handler(void);
ASSERT_TRUE(NVIC_GetVector(HardFault_IRQn) == (uint32_t)HardFault_Handler);
ASSERT_TRUE(NVIC_GetVector(SVCall_IRQn) == (uint32_t)SVC_Handler);
ASSERT_TRUE(NVIC_GetVector(PendSV_IRQn) == (uint32_t)PendSV_Handler);
ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler);
/* reconfigure WDT IRQ vector */
extern void Interrupt0_Handler(void);
const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn);
ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler);
NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U);
ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U));
/* restore vector table */
SCB->VTOR = orig_vtor;
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_GetCtrl
\details
- Check if __set_CONTROL and __get_CONTROL() sets/gets control register
*/
void TC_CoreFunc_Control (void) {
// don't use stack for this variables
static uint32_t orig;
static uint32_t ctrl;
static uint32_t result;
orig = __get_CONTROL();
ctrl = orig;
result = UINT32_MAX;
#ifdef CONTROL_SPSEL_Msk
// SPSEL set to 0 (MSP)
ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U);
// SPSEL set to 1 (PSP)
ctrl |= CONTROL_SPSEL_Msk;
// Move MSP to PSP
__set_PSP(__get_MSP());
#endif
__set_CONTROL(ctrl);
__ISB();
result = __get_CONTROL();
__set_CONTROL(orig);
__ISB();
ASSERT_TRUE(result == ctrl);
ASSERT_TRUE(__get_CONTROL() == orig);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_IPSR
\details
- Check if __get_IPSR intrinsic is available
- Check if __get_xPSR intrinsic is available
- Result differentiates between thread and exception modes
*/
void TC_CoreFunc_IPSR (void) {
uint32_t result = __get_IPSR();
ASSERT_TRUE(result == 0U); // Thread Mode
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode
TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler;
irqIPSR = 0U;
irqXPSR = 0U;
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
NVIC_EnableIRQ(Interrupt0_IRQn);
__enable_irq();
NVIC_SetPendingIRQ(Interrupt0_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
__disable_irq();
NVIC_DisableIRQ(Interrupt0_IRQn);
ASSERT_TRUE(irqIPSR != 0U); // Exception Mode
ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
#if defined(__CC_ARM)
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn)
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn)
#elif defined( __GNUC__ ) && (!defined(__ti__)) && (!defined(__ARMCC_VERSION)) && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
#elif defined(_lint)
//lint -save -e(9026) allow function-like macro
#define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn))
#define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn))
//lint -restore
#else
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
#endif
/**
\brief Test case: TC_CoreFunc_APSR
\details
- Check if __get_APSR intrinsic is available
- Check if __get_xPSR intrinsic is available
- Check negative, zero and overflow flags
*/
void TC_CoreFunc_APSR (void) {
volatile uint32_t result;
//lint -esym(838, Rm) unused values
//lint -esym(438, Rm) unused values
// Check negative flag
volatile int32_t Rm = 5;
volatile int32_t Rn = 7;
SUBS(Rm, Rm, Rn);
result = __get_APSR();
ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk);
Rm = 5;
Rn = 7;
SUBS(Rm, Rm, Rn);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk);
// Check zero and compare flag
Rm = 5;
SUBS(Rm, Rm, Rm);
result = __get_APSR();
ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk);
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
Rm = 5;
SUBS(Rm, Rm, Rm);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk);
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
// Check overflow flag
Rm = 5;
Rn = INT32_MAX;
ADDS(Rm, Rm, Rn);
result = __get_APSR();
ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk);
Rm = 5;
Rn = INT32_MAX;
ADDS(Rm, Rm, Rn);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_PSP
\details
- Check if __get_PSP and __set_PSP intrinsic can be used to manipulate process stack pointer.
*/
void TC_CoreFunc_PSP (void) {
// don't use stack for this variables
static uint32_t orig;
static uint32_t psp;
static uint32_t result;
orig = __get_PSP();
psp = orig + 0x12345678U;
__set_PSP(psp);
result = __get_PSP();
__set_PSP(orig);
ASSERT_TRUE(result == psp);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_MSP
\details
- Check if __get_MSP and __set_MSP intrinsic can be used to manipulate main stack pointer.
*/
void TC_CoreFunc_MSP (void) {
// don't use stack for this variables
static uint32_t orig;
static uint32_t msp;
static uint32_t result;
static uint32_t ctrl;
ctrl = __get_CONTROL();
orig = __get_MSP();
__set_PSP(orig);
__set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP
msp = orig + 0x12345678U;
__set_MSP(msp);
result = __get_MSP();
__set_MSP(orig);
__set_CONTROL(ctrl);
ASSERT_TRUE(result == msp);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_PSPLIM
\details
- Check if __get_PSPLIM and __set_PSPLIM intrinsic can be used to manipulate process stack pointer limit.
*/
void TC_CoreFunc_PSPLIM (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
// don't use stack for this variables
static uint32_t orig;
static uint32_t psplim;
static uint32_t result;
orig = __get_PSPLIM();
psplim = orig + 0x12345678U;
__set_PSPLIM(psplim);
result = __get_PSPLIM();
__set_PSPLIM(orig);
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
ASSERT_TRUE(result == 0U);
#else
ASSERT_TRUE(result == psplim);
#endif
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_PSPLIM_NS
\details
- Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.
*/
void TC_CoreFunc_PSPLIM_NS (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
uint32_t orig;
uint32_t psplim;
uint32_t result;
orig = __TZ_get_PSPLIM_NS();
psplim = orig + 0x12345678U;
__TZ_set_PSPLIM_NS(psplim);
result = __TZ_get_PSPLIM_NS();
__TZ_set_PSPLIM_NS(orig);
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
ASSERT_TRUE(result == 0U);
#else
ASSERT_TRUE(result == psplim);
#endif
#endif
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_MSPLIM
\details
- Check if __get_MSPLIM and __set_MSPLIM intrinsic can be used to manipulate main stack pointer limit.
*/
void TC_CoreFunc_MSPLIM (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
// don't use stack for this variables
static uint32_t orig;
static uint32_t msplim;
static uint32_t result;
static uint32_t ctrl;
ctrl = __get_CONTROL();
__set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP
orig = __get_MSPLIM();
msplim = orig + 0x12345678U;
__set_MSPLIM(msplim);
result = __get_MSPLIM();
__set_MSPLIM(orig);
__set_CONTROL(ctrl);
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
ASSERT_TRUE(result == 0U);
#else
ASSERT_TRUE(result == msplim);
#endif
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_MSPLIM_NS
\details
- Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.
*/
void TC_CoreFunc_MSPLIM_NS (void) {
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
uint32_t orig;
uint32_t msplim;
uint32_t result;
orig = __TZ_get_MSPLIM_NS();
msplim = orig + 0x12345678U;
__TZ_set_MSPLIM_NS(msplim);
result = __TZ_get_MSPLIM_NS();
__TZ_set_MSPLIM_NS(orig);
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
ASSERT_TRUE(result == 0U);
#else
ASSERT_TRUE(result == msplim);
#endif
#endif
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_PRIMASK
\details
- Check if __get_PRIMASK and __set_PRIMASK intrinsic can be used to manipulate PRIMASK.
- Check if __enable_irq and __disable_irq are reflected in PRIMASK.
*/
void TC_CoreFunc_PRIMASK (void) {
uint32_t orig = __get_PRIMASK();
// toggle primask
uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U);
__set_PRIMASK(primask);
uint32_t result = __get_PRIMASK();
ASSERT_TRUE(result == primask);
__disable_irq();
result = __get_PRIMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__enable_irq();
result = __get_PRIMASK();
ASSERT_TRUE((result & 0x01U) == 0U);
__disable_irq();
result = __get_PRIMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__set_PRIMASK(orig);
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_FAULTMASK
\details
- Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK.
- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK.
*/
void TC_CoreFunc_FAULTMASK (void) {
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
uint32_t orig = __get_FAULTMASK();
// toggle faultmask
uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U);
__set_FAULTMASK(faultmask);
uint32_t result = __get_FAULTMASK();
ASSERT_TRUE(result == faultmask);
__disable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__enable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 0U);
__disable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__set_FAULTMASK(orig);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_BASEPRI
\details
- Check if __get_BASEPRI and __set_BASEPRI intrinsic can be used to manipulate BASEPRI.
- Check if __set_BASEPRI_MAX intrinsic can be used to manipulate BASEPRI.
*/
void TC_CoreFunc_BASEPRI(void) {
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
uint32_t orig = __get_BASEPRI();
uint32_t basepri = ~orig & 0x80U;
__set_BASEPRI(basepri);
uint32_t result = __get_BASEPRI();
ASSERT_TRUE(result == basepri);
__set_BASEPRI(orig);
__set_BASEPRI_MAX(basepri);
result = __get_BASEPRI();
ASSERT_TRUE(result == basepri);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_FPUType
\details
Check SCB_GetFPUType returns information.
*/
void TC_CoreFunc_FPUType(void) {
uint32_t fpuType = SCB_GetFPUType();
#if defined(__FPU_PRESENT) && (__FPU_PRESENT != 0)
ASSERT_TRUE(fpuType > 0U);
#else
ASSERT_TRUE(fpuType == 0U);
#endif
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Test case: TC_CoreFunc_FPSCR
\details
- Check if __get_FPSCR and __set_FPSCR intrinsics can be used
*/
void TC_CoreFunc_FPSCR(void) {
uint32_t fpscr = __get_FPSCR();
__ISB();
__DSB();
__set_FPSCR(~fpscr);
__ISB();
__DSB();
uint32_t result = __get_FPSCR();
__set_FPSCR(fpscr);
#if (defined (__FPU_USED ) && (__FPU_USED == 1U))
ASSERT_TRUE(result != fpscr);
#else
ASSERT_TRUE(result == 0U);
#endif
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CoreFunc.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 6,560 |
```c
/*your_sha256_hash-------------
* Name: cv_framework.c
* Purpose: Test framework entry point
*your_sha256_hash------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/* Prototypes */
void ts_cmsis_cv(void);
void closeDebug(void);
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\defgroup framework_funcs Framework Functions
\brief Functions in the Framework software component
\details
@{
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief Close the debug session.
\details
Debug session dead end - debug script should close session here.
*/
void closeDebug(void) {
__NOP();
// Test completed
}
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**
\brief This is CORE Validation test suite.
\details
Program flow:
-# Test report statistics is initialized
-# Test report headers are written to the standard output
-# All defined test cases are executed:
- Test case statistics is initialized
- Test case report header is written to the standard output
- Test case is executed
- Test case results are written to the standard output
- Test case report footer is written to the standard output
- Test case is closed
-# Test report footer is written to the standard output
-# Debug session ends in dead loop
*/
void ts_cmsis_cv () {
const char *fn;
uint32_t tc, no;
(void)ritf.Init (); /* Init test report */
(void)ritf.Open (ts.ReportTitle, /* Write test report title */
ts.Date, /* Write compilation date */
ts.Time, /* Write compilation time */
ts.FileName); /* Write module file name */
/* Execute all test cases */
for (tc = 0; tc < ts.NumOfTC; tc++) {
no = ts.TCBaseNum+tc; /* Test case number */
fn = ts.TC[tc].TFName; /* Test function name string */
(void)ritf.Open_TC (no, fn); /* Open test case #(Base + TC) */
if (ts.TC[tc].en != 0U) {
ts.TC[tc].TestFunc(); /* Execute test case if enabled */
}
(void)ritf.Close_TC (); /* Close test case */
}
(void)ritf.Close (); /* Close test report */
closeDebug(); /* Close debug session */
}
/**
\brief This is the entry point of the test framework.
\details
Program flow:
-# Hardware is first initialized if Init callback function is provided
-# Main thread is initialized
*/
void cmsis_cv (void) {
/* Init test suite */
if (ts.Init != NULL) {
ts.Init(); /* Init hardware */
}
ts_cmsis_cv();
}
void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc) {
(void)__set_result(fn, ln, FAILED, desc);
(void)ritf.Close_TC();
(void)ritf.Close();
closeDebug();
}
/**
@}
*/
// end of group framework_funcs
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_Framework.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 759 |
```c
/*your_sha256_hash-------------
* Name: cmsis_cv.c
* Purpose: Driver validation test cases entry point
*your_sha256_hash------------
*your_sha256_hash------------*/
#include "cmsis_cv.h"
#include "RTE_Components.h"
#include "CV_Framework.h"
#include "CV_Config.h"
/*your_sha256_hash-------------
* Prototypes
*your_sha256_hash------------*/
void Interrupt0_Handler(void);
/*your_sha256_hash-------------
* Variables declarations
*your_sha256_hash------------*/
void (*TST_IRQHandler)(void);
void Interrupt0_Handler(void) {
if (TST_IRQHandler != NULL) TST_IRQHandler();
}
/*your_sha256_hash-------------
* Init test suite
*your_sha256_hash------------*/
static void TS_Init (void) {
TST_IRQHandler = NULL;
#ifdef RTE_CV_MEASURETICKS
StartCortexCycleCounter();
#endif
}
/*your_sha256_hash-------------
* Test cases list
*your_sha256_hash------------*/
static TEST_CASE TC_LIST[] = {
#if defined(RTE_CV_COREINSTR) && RTE_CV_COREINSTR
#if defined(__CORTEX_M)
TCD ( TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ),
TCD ( TC_CoreInstr_WFI, TC_COREINSTR_WFI_EN ),
TCD ( TC_CoreInstr_WFE, TC_COREINSTR_WFE_EN ),
TCD ( TC_CoreInstr_SEV, TC_COREINSTR_SEV_EN ),
TCD ( TC_CoreInstr_BKPT, TC_COREINSTR_BKPT_EN ),
TCD ( TC_CoreInstr_ISB, TC_COREINSTR_ISB_EN ),
TCD ( TC_CoreInstr_DSB, TC_COREINSTR_DSB_EN ),
TCD ( TC_CoreInstr_DMB, TC_COREINSTR_DMB_EN ),
TCD ( TC_CoreInstr_REV, TC_COREINSTR_REV_EN ),
TCD ( TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ),
TCD ( TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ),
TCD ( TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ),
TCD ( TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ),
TCD ( TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ),
TCD ( TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ),
TCD ( TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ),
TCD ( TC_CoreInstr_RRX, TC_COREINSTR_RRX_EN ),
TCD ( TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_LOADSTOREEXCLUSIVE_EN ),
TCD ( TC_CoreInstr_LoadStoreUnpriv, TC_COREINSTR_LOADSTOREUNPRIV_EN ),
TCD ( TC_CoreInstr_LoadStoreAcquire, TC_COREINSTR_LOADSTOREACQUIRE_EN ),
TCD ( TC_CoreInstr_LoadStoreAcquireExclusive, TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN ),
TCD ( TC_CoreInstr_UnalignedUint16, TC_COREINSTR_UNALIGNEDUINT16_EN ),
TCD ( TC_CoreInstr_UnalignedUint32, TC_COREINSTR_UNALIGNEDUINT32_EN ),
#elif defined(__CORTEX_A)
TCD (TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ),
TCD (TC_CoreInstr_REV, TC_COREINSTR_REV_EN ),
TCD (TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ),
TCD (TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ),
TCD (TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ),
TCD (TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ),
TCD (TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ),
TCD (TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ),
TCD (TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ),
TCD (TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_EXCLUSIVES_EN ),
#endif
#endif /* RTE_CV_COREINSTR */
#if defined (RTE_CV_CORESIMD) && RTE_CV_CORESIMD
TCD ( TC_CoreSimd_SatAddSub, TC_CORESIMD_SATADDSUB_EN ),
TCD ( TC_CoreSimd_ParSat16, TC_CORESIMD_PARSAT16_EN ),
TCD ( TC_CoreSimd_PackUnpack, TC_CORESIMD_PACKUNPACK_EN ),
TCD ( TC_CoreSimd_ParSel, TC_CORESIMD_PARSEL_EN ),
TCD ( TC_CoreSimd_ParAddSub8, TC_CORESIMD_PARADDSUB8_EN ),
TCD ( TC_CoreSimd_AbsDif8, TC_CORESIMD_ABSDIF8_EN ),
TCD ( TC_CoreSimd_ParAddSub16, TC_CORESIMD_PARADDSUB16_EN ),
TCD ( TC_CoreSimd_ParMul16, TC_CORESIMD_PARMUL16_EN ),
TCD ( TC_CoreSimd_Pack16, TC_CORESIMD_PACK16_EN ),
TCD ( TC_CoreSimd_MulAcc32, TC_CORESIMD_MULACC32_EN ),
#endif /* RTE_CV_CORESIMD */
#if defined(RTE_CV_COREFUNC) && RTE_CV_COREFUNC
#if defined(__CORTEX_M)
TCD ( TC_CoreFunc_EnDisIRQ, TC_COREFUNC_ENDISIRQ_EN ),
TCD ( TC_CoreFunc_IRQPrio, TC_COREFUNC_IRQPRIO_EN ),
TCD ( TC_CoreFunc_EncDecIRQPrio, TC_COREFUNC_ENCDECIRQPRIO_EN ),
TCD ( TC_CoreFunc_IRQVect, TC_COREFUNC_IRQVECT_EN ),
TCD ( TC_CoreFunc_Control, TC_COREFUNC_CONTROL_EN ),
TCD ( TC_CoreFunc_IPSR, TC_COREFUNC_IPSR_EN ),
TCD ( TC_CoreFunc_APSR, TC_COREFUNC_APSR_EN ),
TCD ( TC_CoreFunc_PSP, TC_COREFUNC_PSP_EN ),
TCD ( TC_CoreFunc_MSP, TC_COREFUNC_MSP_EN ),
TCD ( TC_CoreFunc_PSPLIM, TC_COREFUNC_PSPLIM_EN ),
TCD ( TC_CoreFunc_PSPLIM_NS, TC_COREFUNC_PSPLIM_NS_EN ),
TCD ( TC_CoreFunc_MSPLIM, TC_COREFUNC_MSPLIM_EN ),
TCD ( TC_CoreFunc_MSPLIM_NS, TC_COREFUNC_MSPLIM_NS_EN ),
TCD ( TC_CoreFunc_PRIMASK, TC_COREFUNC_PRIMASK_EN ),
TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ),
TCD ( TC_CoreFunc_BASEPRI, TC_COREFUNC_BASEPRI_EN ),
TCD ( TC_CoreFunc_FPUType, TC_COREFUNC_FPUTYPE_EN ),
TCD ( TC_CoreFunc_FPSCR, TC_COREFUNC_FPSCR_EN ),
#elif defined(__CORTEX_A)
TCD ( TC_CoreAFunc_IRQ, TC_COREAFUNC_IRQ ),
TCD ( TC_CoreAFunc_FaultIRQ, TC_COREAFUNC_FAULTIRQ ),
TCD ( TC_CoreAFunc_FPSCR, TC_COREAFUNC_FPSCR ),
TCD ( TC_CoreAFunc_CPSR, TC_COREAFUNC_CPSR ),
TCD ( TC_CoreAFunc_Mode, TC_COREAFUNC_MODE ),
TCD ( TC_CoreAFunc_SP, TC_COREAFUNC_SP ),
TCD ( TC_CoreAFunc_SP_usr, TC_COREAFUNC_SP_USR ),
TCD ( TC_CoreAFunc_FPEXC, TC_COREAFUNC_FPEXC ),
TCD ( TC_CoreAFunc_ACTLR, TC_COREAFUNC_ACTLR ),
TCD ( TC_CoreAFunc_CPACR, TC_COREAFUNC_CPACR ),
TCD ( TC_CoreAFunc_DFSR, TC_COREAFUNC_DFSR ),
TCD ( TC_CoreAFunc_IFSR, TC_COREAFUNC_IFSR ),
TCD ( TC_CoreAFunc_ISR, TC_COREAFUNC_ISR ),
TCD ( TC_CoreAFunc_CBAR, TC_COREAFUNC_CBAR ),
TCD ( TC_CoreAFunc_TTBR0, TC_COREAFUNC_TTBR0 ),
TCD ( TC_CoreAFunc_DACR, TC_COREAFUNC_DACR ),
TCD ( TC_CoreAFunc_SCTLR, TC_COREAFUNC_SCTLR ),
TCD ( TC_CoreAFunc_ACTRL, TC_COREAFUNC_ACTRL ),
TCD ( TC_CoreAFunc_MPIDR, TC_COREAFUNC_MPIDR ),
TCD ( TC_CoreAFunc_VBAR, TC_COREAFUNC_VBAR ),
TCD ( TC_CoreAFunc_MVBAR, TC_COREAFUNC_MVBAR ),
TCD ( TC_CoreAFunc_FPU_Enable, TC_COREAFUNC_FPU_ENABLE ),
#endif
#endif /* RTE_CV_COREFUNC */
#if defined(RTE_CV_MPUFUNC) && RTE_CV_MPUFUNC
TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ),
TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ),
#endif /* RTE_CV_MPUFUNC */
#if defined(RTE_CV_GENTIMER) && RTE_CV_GENTIMER
TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ),
TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ),
TCD ( TC_GenTimer_CNTP_CTL, TC_GENTIMER_CNTP_CTL ),
TCD ( TC_GenTimer_CNTPCT, TC_GENTIMER_CNTPCT ),
TCD ( TC_GenTimer_CNTP_CVAL, TC_GENTIMER_CNTP_CVAL ),
#endif /* RTE_CV_GENTIMER */
#if defined(RTE_CV_L1CACHE) && RTE_CV_L1CACHE
#if defined(__CORTEX_M)
TCD ( TC_CML1Cache_EnDisableICache, TC_CML1CACHE_ENDISABLE_ICACHE ),
TCD ( TC_CML1Cache_EnDisableDCache, TC_CML1CACHE_ENDISABLE_DCACHE ),
TCD ( TC_CML1Cache_CleanDCacheByAddrWhileDisabled, TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED),
#elif defined(__CORTEX_A)
TCD ( TC_CAL1Cache_EnDisable, TC_CAL1CACHE_ENDISABLE ),
TCD ( TC_CAL1Cache_EnDisableBTAC, TC_CAL1CACHE_ENDISABLEBTAC ),
TCD ( TC_CAL1Cache_log2_up, TC_CAL1CACHE_LOG2_UP ),
TCD ( TC_CAL1Cache_InvalidateDCacheAll, TC_CAL1CACHE_INVALIDATEDCACHEALL ),
TCD ( TC_CAL1Cache_CleanDCacheAll, TC_CAL1CACHE_CLEANDCACHEALL ),
TCD ( TC_CAL1Cache_CleanInvalidateDCacheAll, TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL ),
#endif
#endif /* RTE_CV_L1CACHE */
};
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wdate-time"
#endif
/*your_sha256_hash-------------
* Test suite description
*your_sha256_hash------------*/
TEST_SUITE ts = {
__FILE__, __DATE__, __TIME__,
"CMSIS-CORE Test Suite",
TS_Init,
1,
TC_LIST,
ARRAY_SIZE (TC_LIST),
};
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/cmsis_cv.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,717 |
```c
/*your_sha256_hash-------------
* Name: CV_CoreSimd.c
* Purpose: CMSIS CORE validation tests implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Framework.h"
#include "cmsis_cv.h"
/*your_sha256_hash-------------
* Test implementation
*your_sha256_hash------------*/
/*your_sha256_hash-------------
* Test cases
*your_sha256_hash------------*/
/**
\brief Test case: TC_CoreSimd_SatAddSub
\details
- Check Saturating addition and subtraction:
__QADD
__QSUB
*/
void TC_CoreSimd_SatAddSub (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
/* --- __QADD Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80000003;
op2_s32 = (int32_t)0x00000004;
res_s32 = __QADD(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80000007);
op1_s32 = (int32_t)0x80000000;
op2_s32 = (int32_t)0x80000002;
res_s32 = __QADD(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
/* --- __QSUB Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80000003;
op2_s32 = (int32_t)0x00000004;
res_s32 = __QSUB(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
op1_s32 = (int32_t)0x80000003;
op2_s32 = (int32_t)0x00000002;
res_s32 = __QSUB(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80000001);
#endif
}
/**
\brief Test case: TC_CoreSimd_ParSat16
\details
- Check Parallel 16-bit saturation:
__SSAT16
__USAT16
*/
void TC_CoreSimd_ParSat16 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile int32_t op1_s32;
volatile int32_t res_s32;
/* --- __SSAT16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80030168;
res_s32 = __SSAT16(op1_s32, 8);
ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F);
/* --- __USAT16 Test ---------------------------------------------- */
op1_s32 = 0x0030168;
res_s32 = __USAT16(op1_s32, 8);
ASSERT_TRUE(res_s32 == 0x000300FF);
#endif
}
/**
\brief Test case: TC_CoreSimd_PackUnpack
\details
- Check Packing and unpacking:
__SXTB16
__SXTB16_RORn
__SXTAB16
__SXTAB16__RORn
__UXTB16
__UXTAB16
*/
void TC_CoreSimd_PackUnpack (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
/* --- __SXTB16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80830168;
res_s32 = __SXTB16(op1_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFF830068);
/* --- __SXTB16_ROR8 Test ----------------------------------------- */
op1_s32 = (int32_t)0x80830168;
res_s32 = __SXTB16_RORn(op1_s32, 8);
ASSERT_TRUE(res_s32 == (int32_t)0xFF800001);
/* --- __SXTB16_ROR16 Test ---------------------------------------- */
op1_s32 = (int32_t)0x80830168;
res_s32 = __SXTB16_RORn(op1_s32, 16);
ASSERT_TRUE(res_s32 == (int32_t)0x68FF83);
/* --- __SXTB16_ROR24 Test ---------------------------------------- */
op1_s32 = (int32_t)0x80830168;
res_s32 = __SXTB16_RORn(op1_s32, 24);
ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);
/* --- __SXTAB16 Test --------------------------------------------- */
op1_s32 = (int32_t)0x000D0008;
op2_s32 = (int32_t)0x80830168;
res_s32 = __SXTAB16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFF900070);
/* --- __SXTAB16__ROR8 Test --------------------------------------- */
op1_s32 = (int32_t)0x000A000A;
op2_s32 = (int32_t)0x80830168;
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B);
/* --- __SXTAB16__ROR8 Test --------------------------------------- */
op1_s32 = (int32_t)0xFFF6FFF6;
op2_s32 = (int32_t)0x80830168;
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7);
/* --- __SXTAB16__ROR16 Test -------------------------------------- */
op1_s32 = (int32_t)0xFFF60015;
op2_s32 = (int32_t)0x70880168;
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16);
ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D);
/* --- __SXTAB16__ROR24 Test -------------------------------------- */
op1_s32 = (int32_t)0xFFF60015;
op2_s32 = (int32_t)0x70880168;
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24);
ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085);
/* --- __UXTB16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80830168;
res_s32 = __UXTB16(op1_s32);
ASSERT_TRUE(res_s32 == 0x00830068);
/* --- __UXTAB16 Test --------------------------------------------- */
op1_s32 = 0x000D0008;
op2_s32 = (int32_t)0x80830168;
res_s32 = __UXTAB16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == 0x00900070);
#endif
}
/**
\brief Test case: TC_CoreSimd_ParSel
\details
- Check Parallel selection:
__SEL
*/
void TC_CoreSimd_ParSel (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t res_u32;
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
APSR_Type apsr;
xPSR_Type xpsr;
/* --- __SEL Test ---------------------------------------------- */
op1_s32 = 0x33221100;
op2_s32 = 0x77665544;
res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */
ASSERT_TRUE( res_s32 == 0x77665544);
res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */
ASSERT_TRUE(res_s32 == 0x77665500);
res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */
ASSERT_TRUE(res_s32 == 0x77661144);
#endif
}
/**
\brief Test case: TC_CoreSimd_ParAddSub8
\details
- Check Parallel 8-bit addition and subtraction:
__SADD8 S Signed
__SSUB8 Q Signed Saturating
__SHADD8 SH Signed Halving
__SHSUB8 U Unsigned
__QADD8 UQ Unsigned Saturating
__QSUB8 UH Unsigned Halving
__UADD8
__USUB8
__UHADD8
__UHSUB8
__UQADD8
__UQSUB8
*/
void TC_CoreSimd_ParAddSub8 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t op1_u32, op2_u32;
volatile uint32_t res_u32;
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
/* --- __SADD8 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x87858381;
op2_s32 = (int32_t)0x08060402;
res_s32 = __SADD8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783);
/* --- __SSUB8 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x8F8B8783;
op2_s32 = (int32_t)0x08060402;
res_s32 = __SSUB8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x87858381);
/* --- __SHADD8 Test ---------------------------------------------- */
op1_s32 = 0x07050302;
op2_s32 = 0x08060402;
res_s32 = __SHADD8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == 0x07050302);
/* --- __SHSUB8 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x8F8B8783;
op2_s32 = 0x08060402;
res_s32 = __SHSUB8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0);
/* --- __QADD8 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x8085837F;
op2_s32 = (int32_t)0xFF060402;
res_s32 = __QADD8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x808B877F);
/* --- __QSUB8 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x808B8783;
op2_s32 = (int32_t)0x08060402;
res_s32 = __QSUB8(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80858381);
/* --- __UADD8 Test ---------------------------------------------- */
op1_u32 = 0x07050301;
op2_u32 = 0x08060402;
res_u32 = __UADD8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x0F0B0703);
/* --- __USUB8 Test ---------------------------------------------- */
op1_u32 = 0x0F0B0703;
op2_u32 = 0x08060402;
res_u32 = __USUB8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x07050301);
/* --- __UHADD8 Test ---------------------------------------------- */
op1_u32 = 0x07050302;
op2_u32 = 0x08060402;
res_u32 = __UHADD8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x07050302);
/* --- __UHSUB8 Test ---------------------------------------------- */
op1_u32 = 0x0F0B0703;
op2_u32 = 0x08060402;
res_u32 = __UHSUB8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x03020100);
/* --- __UQADD8 Test ---------------------------------------------- */
op1_u32 = 0xFF050301;
op2_u32 = 0x08060402;
res_u32 = __UQADD8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0xFF0B0703);
/* --- __UQSUB8 Test ---------------------------------------------- */
op1_u32 = 0x080B0702;
op2_u32 = 0x0F060408;
res_u32 = __UQSUB8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00050300);
#endif
}
/**
\brief Test case: TC_CoreSimd_AbsDif8
\details
- Check Sum of 8-bit absolute differences:
__USAD8
__USADA8
*/
void TC_CoreSimd_AbsDif8 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t op1_u32, op2_u32, op3_u32;
volatile uint32_t res_u32;
/* --- __USAD8 Test ---------------------------------------------- */
op1_u32 = 0x87858381;
op2_u32 = 0x08060402;
res_u32 = __USAD8(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x000001FC);
/* --- __USADA8 Test ---------------------------------------------- */
op1_u32 = 0x87858381;
op2_u32 = 0x08060402;
op3_u32 = 0x00008000;
res_u32 = __USADA8(op1_u32, op2_u32, op3_u32);
ASSERT_TRUE(res_u32 == 0x000081FC);
#endif
}
/**
\brief Test case: TC_CoreSimd_ParAddSub16
\details
- Check Parallel 16-bit addition and subtraction:
__SADD16
__SSUB16
__SASX
__SSAX
__SHADD16
__SHSUB16
__SHASX
__SHSAX
__QADD16
__QSUB16
__QASX
__QSAX
__UADD16
__USUB16
__UASX
__USAX
__UHADD16
__UHSUB16
__UHASX
__UHSAX
__UQSUB16
__UQADD16
__UQASX
__UQSAX
*/
void TC_CoreSimd_ParAddSub16 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t op1_u32, op2_u32;
volatile uint32_t res_u32;
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
/* --- __SADD16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038001;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SADD16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80078003);
/* --- __SSUB16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80078003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SSUB16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80038001);
/* --- __SASX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80078003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SASX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF);
/* --- __SSAX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038007;
op2_s32 = (int32_t)0x00020004;
res_s32 = __SSAX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009);
/* --- __SHADD16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038001;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SHADD16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xC003C001);
/* --- __SHSUB16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80078003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SHSUB16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xC001C000);
/* --- __SHASX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80078003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SHASX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF);
/* --- __SHSAX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038007;
op2_s32 = (int32_t)0x00020004;
res_s32 = __SHSAX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004);
/* --- __QADD16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038000;
op2_s32 = (int32_t)0x00048002;
res_s32 = __QADD16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80078000);
/* --- __QSUB16 Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __QSUB16(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80008001);
/* --- __QASX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80078003;
op2_s32 = (int32_t)0x00040002;
res_s32 = __QASX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80098000);
/* --- __QSAX Test ---------------------------------------------- */
op1_s32 = (int32_t)0x80038007;
op2_s32 = (int32_t)0x00020004;
res_s32 = __QSAX(op1_s32, op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x80008009);
/* --- __UADD16 Test ---------------------------------------------- */
op1_u32 = 0x00010002;
op2_u32 = 0x00020004;
res_u32 = __UADD16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00030006);
/* --- __USUB16 Test ---------------------------------------------- */
op1_u32 = 0x00030006;
op2_u32 = 0x00020004;
res_u32 = __USUB16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00010002);
/* --- __UASX Test ---------------------------------------------- */
op1_u32 = 0x80078003;
op2_u32 = 0x00040002;
res_u32 = __UASX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x80097FFF);
/* --- __USAX Test ---------------------------------------------- */
op1_u32 = 0x80038007;
op2_u32 = 0x00020004;
res_u32 = __USAX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x7FFF8009);
/* --- __UHADD16 Test ---------------------------------------------- */
op1_u32 = 0x00010002;
op2_u32 = 0x00020004;
res_u32 = __UHADD16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00010003);
/* --- __UHSUB16 Test ---------------------------------------------- */
op1_u32 = 0x00030006;
op2_u32 = 0x00020004;
res_u32 = __UHSUB16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00000001);
/* --- __UHASX Test ---------------------------------------------- */
op1_u32 = 0x80078003;
op2_u32 = 0x00040002;
res_u32 = __UHASX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x40043FFF);
/* --- __UHSAX Test ---------------------------------------------- */
op1_u32 = 0x80038007;
op2_u32 = 0x00020004;
res_u32 = __UHSAX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x3FFF4004);
/* --- __UQADD16 Test ---------------------------------------------- */
op1_u32 = 0xFFFE0002;
op2_u32 = 0x00020004;
res_u32 = __UQADD16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0xFFFF0006);
/* --- __UQSUB16 Test ---------------------------------------------- */
op1_u32 = 0x00020006;
op2_u32 = 0x00030004;
res_u32 = __UQSUB16(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x00000002);
/* --- __UQASX Test ---------------------------------------------- */
op1_u32 = 0xFFF80003;
op2_u32 = 0x00040009;
res_u32 = __UQASX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0xFFFF0000);
/* --- __UQSAX Test ---------------------------------------------- */
op1_u32 = 0x0003FFF8;
op2_u32 = 0x00090004;
res_u32 = __UQSAX(op1_u32, op2_u32);
ASSERT_TRUE(res_u32 == 0x0000FFFF);
#endif
}
/**
\brief Test case: TC_CoreSimd_ParMul16
\details
- Check Parallel 16-bit multiplication:
__SMLAD
__SMLADX
__SMLALD
__SMLALDX
__SMLSD
__SMLSDX
__SMLSLD
__SMLSLDX
__SMUAD
__SMUADX
__SMUSD
__SMUSDX
*/
void TC_CoreSimd_ParMul16 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile int32_t op1_s32, op2_s32, op3_s32;
volatile int32_t res_s32;
volatile int64_t op1_s64;
volatile int64_t res_s64;
/* --- __SMLAD Test ---------------------------------------------- */
op1_s32 = 0x00030002;
op2_s32 = 0x00050004;
op3_s32 = 0x20000000;
res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x20000017);
/* --- __SMLADX Test ---------------------------------------------- */
op1_s32 = 0x00030002;
op2_s32 = 0x00050004;
op3_s32 = 0x00000800;
res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x00000816);
/* --- __SMLALD Test ---------------------------------------------- */
op1_s32 = 0x00030002;
op2_s32 = 0x00050004;
op1_s64 = 0x00000000200000000LL;
res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64);
ASSERT_TRUE(res_s64 == 0x0000000200000017LL);
/* --- __SMLALDX Test ---------------------------------------------- */
op1_s32 = 0x00030002;
op2_s32 = 0x00050004;
op1_s64 = 0x00000000200000000LL;
res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64);
ASSERT_TRUE(res_s64 == 0x0000000200000016LL);
/* --- __SMLSD Test ---------------------------------------------- */
op1_s32 = 0x00030006;
op2_s32 = 0x00050004;
op3_s32 = 0x00000800;
res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x00000809);
/* --- __SMLSDX Test ---------------------------------------------- */
op1_s32 = 0x00030002;
op2_s32 = 0x00050004;
op3_s32 = 0x00000800;
res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x000007FE);
/* --- __SMLSLD Test ---------------------------------------------- */
op1_s32 = 0x00030006;
op2_s32 = 0x00050004;
op1_s64 = 0x00000000200000000LL;
res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64);
ASSERT_TRUE(res_s64 == 0x0000000200000009LL);
/* --- __SMLSLDX Test ---------------------------------------------- */
op1_s32 = 0x00030006;
op2_s32 = 0x00050004;
op1_s64 = 0x00000000200000000LL;
res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64);
ASSERT_TRUE(res_s64 == 0x0000000200000012LL);
/* --- __SMUAD Test ---------------------------------------------- */
op1_s32 = 0x00030001;
op2_s32 = 0x00040002;
res_s32 = __SMUAD(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == 0x0000000E);
op1_s32 = (int32_t)0xFFFDFFFF;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SMUAD(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2);
/* --- __SMUADX Test ---------------------------------------------- */
op1_s32 = 0x00030001;
op2_s32 = 0x00040002;
res_s32 = __SMUADX(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == 0x0000000A);
op1_s32 = (int32_t)0xFFFDFFFF;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SMUADX(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
/* --- __SMUSD Test ---------------------------------------------- */
op1_s32 = (int32_t)0x00030001;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SMUSD(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
op1_s32 = (int32_t)0xFFFDFFFF;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SMUSD(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == 0x0000000A);
/* --- __SMUSDX Test ---------------------------------------------- */
op1_s32 = 0x00030001;
op2_s32 = 0x00040002;
res_s32 = __SMUSDX(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE);
op1_s32 = (int32_t)0xFFFDFFFF;
op2_s32 = (int32_t)0x00040002;
res_s32 = __SMUSDX(op1_s32,op2_s32);
ASSERT_TRUE(res_s32 == (int32_t)0x00000002);
#endif
}
/**
\brief Test case: TC_CoreSimd_Part9
\details
- Check Packing Halfword:
__PKHBT
__PKHTB
*/
void TC_CoreSimd_Pack16 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t op1_u32, op2_u32;
volatile uint32_t res_u32;
/* --- __PKHBT Test ---------------------------------------------- */
op1_u32 = 0x00000111;
op2_u32 = 0x22200000;
res_u32 = __PKHBT(op1_u32, op2_u32, 0);
ASSERT_TRUE(res_u32 == 0x22200111);
op1_u32 = 0x00000111;
op2_u32 = 0x22200000;
res_u32 = __PKHBT(op1_u32, op2_u32, 4);
ASSERT_TRUE(res_u32 == 0x22000111);
/* --- __PKHTB Test ---------------------------------------------- */
op1_u32 = 0x11100000;
op2_u32 = 0x00000222;
res_u32 = __PKHTB(op1_u32, op2_u32, 0);
ASSERT_TRUE(res_u32 == 0x11100222);
op1_u32 = 0x11100000;
op2_u32 = 0x00000222;
res_u32 = __PKHTB(op1_u32, op2_u32, 4);
ASSERT_TRUE(res_u32 == 0x11100022);
#endif
}
/**
\brief Test case: TC_CoreSimd_MulAcc32
\details
- Check Signed Most Significant Word Multiply Accumulate:
__SMMLA
*/
void TC_CoreSimd_MulAcc32 (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile int32_t op1_s32, op2_s32, op3_s32;
volatile int32_t res_s32;
/* --- __SMMLA Test ---------------------------------------------- */
op1_s32 = 0x00000200;
op2_s32 = 0x00000004;
op3_s32 = 0x00000100;
res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x00000100);
op1_s32 = 0x40000000;
op2_s32 = 0x00000010;
op3_s32 = 0x00000300;
res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
ASSERT_TRUE(res_s32 == 0x00000304);
#endif
}
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_CoreSimd.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 8,227 |
```c
/*your_sha256_hash-------------
* Name: cv_report.c
* Purpose: Report statistics and layout implementation
*your_sha256_hash-------------
*your_sha256_hash------------*/
#include "CV_Report.h"
#include <stdio.h>
#include <string.h>
TEST_REPORT test_report;
static AS_STAT current_assertions; /* Current test case assertions statistics */
#define TAS (&test_report.assertions) /* Total assertions */
#define CAS (¤t_assertions) /* Current assertions */
#ifdef DISABLE_SEMIHOSTING
#if defined (__CC_ARM)
#pragma import __use_no_semihosting
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
__ASM(".global __use_no_semihosting");
#endif
#define PRINT(x)
#define FLUSH()
void _sys_exit(int return_code) {}
#else
#define PRINT(x) MsgPrint x
#define FLUSH() MsgFlush()
#endif // DISABLE_SEMIHOSTING
static uint8_t Passed[] = "PASSED";
static uint8_t Warning[] = "WARNING";
static uint8_t Failed[] = "FAILED";
static uint8_t NotExe[] = "NOT EXECUTED";
/*your_sha256_hash-------------
* Test report function prototypes
*your_sha256_hash------------*/
static BOOL tr_Init (void);
static BOOL tc_Init (void);
static uint8_t *tr_Eval (void);
static uint8_t *tc_Eval (void);
static BOOL StatCount (TC_RES res);
/*your_sha256_hash-------------
* Printer function prototypes
*your_sha256_hash------------*/
static void MsgPrint (const char *msg, ...);
static void MsgFlush (void);
/*your_sha256_hash-------------
* Assert interface function prototypes
*your_sha256_hash------------*/
static BOOL As_File_Result (TC_RES res);
static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc);
TC_ITF tcitf = {
As_File_Result,
As_File_Dbgi,
};
/*your_sha256_hash-------------
* Test report interface function prototypes
*your_sha256_hash------------*/
BOOL tr_File_Init (void);
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn);
BOOL tr_File_Close (void);
BOOL tc_File_Open (uint32_t num, const char *fn);
BOOL tc_File_Close (void);
REPORT_ITF ritf = {
tr_File_Init,
tr_File_Open,
tr_File_Close,
tc_File_Open,
tc_File_Close
};
/*your_sha256_hash-------------
* Init test report
*your_sha256_hash------------*/
BOOL tr_File_Init (void) {
return (tr_Init());
}
/*your_sha256_hash-------------
* Open test report
*your_sha256_hash------------*/
#if (PRINT_XML_REPORT==1)
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) {
PRINT(("<?xml version=\"1.0\"?>\n"));
PRINT(("<?xml-stylesheet href=\"TR_Style.xsl\" type=\"text/xsl\" ?>\n"));
PRINT(("<report>\n"));
PRINT(("<test>\n"));
PRINT(("<title>%s</title>\n", title));
PRINT(("<date>%s</date>\n", date));
PRINT(("<time>%s</time>\n", time));
PRINT(("<file>%s</file>\n", fn));
PRINT(("<test_cases>\n"));
#else
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) {
PRINT(("%s %s %s \n\n", title, date, time));
#endif
return (__TRUE);
}
/*your_sha256_hash-------------
* Open test case
*your_sha256_hash------------*/
BOOL tc_File_Open (uint32_t num, const char *fn) {
(void)tc_Init ();
#if (PRINT_XML_REPORT==1)
PRINT(("<tc>\n"));
PRINT(("<no>%d</no>\n", num));
PRINT(("<func>%s</func>\n", fn));
PRINT(("<req></req>"));
PRINT(("<meth></meth>"));
PRINT(("<dbgi>\n"));
#else
PRINT(("TEST %02d: %-42s ", num, fn));
#endif
return (__TRUE);
}
/*your_sha256_hash-------------
* Close test case
*your_sha256_hash------------*/
BOOL tc_File_Close (void) {
uint8_t *res = tc_Eval();
#if (PRINT_XML_REPORT==1)
PRINT(("</dbgi>\n"));
PRINT(("<res>%s</res>\n", res));
PRINT(("</tc>\n"));
#else
if ((res==Passed)||(res==NotExe)) {
PRINT(("%s\n", res));
} else {
PRINT(("\n"));
}
#endif
FLUSH();
return (__TRUE);
}
/*your_sha256_hash-------------
* Close test report
*your_sha256_hash------------*/
BOOL tr_File_Close (void) {
#if (PRINT_XML_REPORT==1)
PRINT(("</test_cases>\n"));
PRINT(("<summary>\n"));
PRINT(("<tcnt>%d</tcnt>\n", test_report.tests));
PRINT(("<exec>%d</exec>\n", test_report.executed));
PRINT(("<pass>%d</pass>\n", test_report.passed));
PRINT(("<fail>%d</fail>\n", test_report.failed));
PRINT(("<warn>%d</warn>\n", test_report.warnings));
PRINT(("<tres>%s</tres>\n", tr_Eval()));
PRINT(("</summary>\n"));
PRINT(("</test>\n"));
PRINT(("</report>\n"));
#else
PRINT(("\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\n",
test_report.tests,
test_report.executed,
test_report.passed,
test_report.failed,
test_report.warnings));
PRINT(("Test Result: %s\n", tr_Eval()));
#endif
FLUSH();
return (__TRUE);
}
/*your_sha256_hash-------------
* Assertion result counter
*your_sha256_hash------------*/
static BOOL As_File_Result (TC_RES res) {
return (StatCount (res));
}
/*your_sha256_hash-------------
* Set debug information state
*your_sha256_hash------------*/
#if (PRINT_XML_REPORT==1)
static BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) {
PRINT(("<detail>\n"));
if (desc!=NULL) PRINT(("<desc>%s</desc>\n", desc));
PRINT(("<module>%s</module>\n", fn));
PRINT(("<line>%d</line>\n", ln));
PRINT(("</detail>\n"));
#else
static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) {
PRINT(("\n %s (%d)", fn, ln));
if (res==WARNING){ PRINT((" [WARNING]")); }
if (res==FAILED) { PRINT((" [FAILED]")); }
if (desc!=NULL) { PRINT((" %s", desc)); }
#endif
return (__TRUE);
}
/*your_sha256_hash-------------
* Init test report
*your_sha256_hash------------*/
static BOOL tr_Init (void) {
TAS->passed = 0;
TAS->failed = 0;
TAS->warnings = 0;
return (__TRUE);
}
/*your_sha256_hash-------------
* Init test case
*your_sha256_hash------------*/
static BOOL tc_Init (void) {
CAS->passed = 0;
CAS->failed = 0;
CAS->warnings = 0;
return (__TRUE);
}
/*your_sha256_hash-------------
* Evaluate test report results
*your_sha256_hash------------*/
static uint8_t *tr_Eval (void) {
if (test_report.failed > 0U) {
/* Test fails if any test case failed */
return (Failed);
}
else if (test_report.warnings > 0U) {
/* Test warns if any test case warnings */
return (Warning);
}
else if (test_report.passed > 0U) {
/* Test passes if at least one test case passed */
return (Passed);
}
else {
/* No test cases were executed */
return (NotExe);
}
}
/*your_sha256_hash-------------
* Evaluate test case results
*your_sha256_hash------------*/
static uint8_t *tc_Eval (void) {
test_report.tests++;
test_report.executed++;
if (CAS->failed > 0U) {
/* Test case fails if any failed assertion recorded */
test_report.failed++;
return Failed;
}
else if (CAS->warnings > 0U) {
/* Test case warns if any warnings assertion recorded */
test_report.warnings++;
return Warning;
}
else if (CAS->passed > 0U) {
/* Test case passes if at least one assertion passed */
test_report.passed++;
return Passed;
}
else {
/* Assert was not invoked - nothing to evaluate */
test_report.executed--;
return NotExe;
}
}
/*your_sha256_hash-------------
* Statistics result counter
*your_sha256_hash------------*/
static BOOL StatCount (TC_RES res) {
switch (res) {
case PASSED:
CAS->passed++;
TAS->passed++;
break;
case WARNING:
CAS->warnings++;
TAS->warnings++;
break;
case FAILED:
CAS->failed++;
TAS->failed++;
break;
case NOT_EXECUTED:
return (__FALSE);
default:
break;
}
return (__TRUE);
}
/*your_sha256_hash-------------
* Set result
*your_sha256_hash------------*/
TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) {
// save assertion result
switch (res) {
case PASSED:
if (TAS->passed < BUFFER_ASSERTIONS) {
test_report.assertions.info.passed[TAS->passed].module = fn;
test_report.assertions.info.passed[TAS->passed].line = ln;
}
break;
case FAILED:
if (TAS->failed < BUFFER_ASSERTIONS) {
test_report.assertions.info.failed[TAS->failed].module = fn;
test_report.assertions.info.failed[TAS->failed].line = ln;
}
break;
case WARNING:
if (TAS->warnings < BUFFER_ASSERTIONS) {
test_report.assertions.info.warnings[TAS->warnings].module = fn;
test_report.assertions.info.warnings[TAS->warnings].line = ln;
}
break;
case NOT_EXECUTED:
break;
default:
break;
}
// set debug info (if the test case didn't pass)
if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); }
// set result
(void)tcitf.Result (res);
return (res);
}
/*your_sha256_hash-------------
* Assert true
*your_sha256_hash------------*/
TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) {
TC_RES res = FAILED;
if (cond != 0U) { res = PASSED; }
(void)__set_result(fn, ln, res, NULL);
return (res);
}
#ifndef DISABLE_SEMIHOSTING
/*your_sha256_hash-------------
* MsgFlush: Flush the standard output
*your_sha256_hash------------*/
static void MsgFlush(void) {
(void)fflush(stdout);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wformat-nonliteral"
#endif
/*your_sha256_hash-------------
* MsgPrint: Print a message to the standard output
*your_sha256_hash------------*/
static void MsgPrint (const char *msg, ...) {
va_list args;
va_start(args, msg);
vprintf(msg, args);
va_end(args);
}
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#endif
#endif // DISABLE_SEMIHOSTING
/*your_sha256_hash-------------
* End of file
*your_sha256_hash------------*/
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/CV_Report.c | c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 2,738 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Config.h
* Purpose: CV Config header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __CV_CONFIG_H
#define __CV_CONFIG_H
#include "RTE_Components.h"
#include CMSIS_device_header
#define RTE_CV_COREINSTR 1
#define RTE_CV_COREFUNC 1
#define RTE_CV_L1CACHE 1
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h> Common Test Settings
// <o> Print Output Format <0=> Plain Text <1=> XML
// <i> Set the test results output format to plain text or XML
#ifndef PRINT_XML_REPORT
#define PRINT_XML_REPORT 1
#endif
// <o> Buffer size for assertions results
// <i> Set the buffer size for assertions results buffer
#define BUFFER_ASSERTIONS 128U
// </h>
// <h> Disable Test Cases
// <i> Uncheck to disable an individual test case
// <q0> TC_CoreInstr_NOP
#define TC_COREINSTR_NOP_EN 1
// <q0> TC_CoreInstr_REV
#define TC_COREINSTR_REV_EN 1
// <q0> TC_CoreInstr_REV16
#define TC_COREINSTR_REV16_EN 1
// <q0> TC_CoreInstr_REVSH
#define TC_COREINSTR_REVSH_EN 1
// <q0> TC_CoreInstr_ROR
#define TC_COREINSTR_ROR_EN 1
// <q0> TC_CoreInstr_RBIT
#define TC_COREINSTR_RBIT_EN 1
// <q0> TC_CoreInstr_CLZ
#define TC_COREINSTR_CLZ_EN 1
// <q0> TC_CoreInstr_Exclusives
#define TC_COREINSTR_EXCLUSIVES_EN 1
// <q0> TC_CoreInstr_SSAT
#define TC_COREINSTR_SSAT_EN 1
// <q0> TC_CoreInstr_USAT
#define TC_COREINSTR_USAT_EN 1
// <q0> TC_CoreAFunc_IRQ
#define TC_COREAFUNC_IRQ 1
// <q0> TC_CoreAFunc_FaultIRQ
#define TC_COREAFUNC_FAULTIRQ 1
// <q0> TC_CoreAFunc_FPSCR
#define TC_COREAFUNC_FPSCR 1
// <q0> TC_CoreAFunc_CPSR
#define TC_COREAFUNC_CPSR 1
// <q0> TC_CoreAFunc_Mode
#define TC_COREAFUNC_MODE 1
// <q0> TC_CoreAFunc_SP
#define TC_COREAFUNC_SP 1
// <q0> TC_CoreAFunc_SP_usr
#define TC_COREAFUNC_SP_USR 1
// <q0> TC_CoreAFunc_FPEXC
#define TC_COREAFUNC_FPEXC 1
// <q0> TC_CoreAFunc_ACTLR
#define TC_COREAFUNC_ACTLR 1
// <q0> TC_CoreAFunc_CPACR
#define TC_COREAFUNC_CPACR 1
// <q0> TC_CoreAFunc_DFSR
#define TC_COREAFUNC_DFSR 1
// <q0> TC_CoreAFunc_IFSR
#define TC_COREAFUNC_IFSR 1
// <q0> TC_CoreAFunc_ISR
#define TC_COREAFUNC_ISR 1
// <q0> TC_CoreAFunc_CBAR
#define TC_COREAFUNC_CBAR 1
// <q0> TC_CoreAFunc_TTBR0
#define TC_COREAFUNC_TTBR0 1
// <q0> TC_CoreAFunc_DACR
#define TC_COREAFUNC_DACR 1
// <q0> TC_CoreAFunc_SCTLR
#define TC_COREAFUNC_SCTLR 1
// <q0> TC_CoreAFunc_ACTRL
#define TC_COREAFUNC_ACTRL 1
// <q0> TC_CoreAFunc_MPIDR
#define TC_COREAFUNC_MPIDR 1
// <q0> TC_CoreAFunc_VBAR
#define TC_COREAFUNC_VBAR 1
// <q0> TC_CoreAFunc_MVBAR
#define TC_COREAFUNC_MVBAR 1
// <q0> TC_CoreAFunc_FPU_Enable
#define TC_COREAFUNC_FPU_ENABLE 1
// <q0> TC_GenTimer_CNTFRQ
#define TC_GENTIMER_CNTFRQ 1
// <q0> TC_GenTimer_CNTP_TVAL
#define TC_GENTIMER_CNTP_TVAL 1
// <q0> TC_GenTimer_CNTP_CTL
#define TC_GENTIMER_CNTP_CTL 1
// <q0> TC_GenTimer_CNTPCT
#define TC_GENTIMER_CNTPCT 1
// <q0> TC_GenTimer_CNTP_CVAL
#define TC_GENTIMER_CNTP_CVAL 1
// <q0> TC_CAL1Cache_EnDisable
#define TC_CAL1CACHE_ENDISABLE 1
// <q0> TC_CAL1Cache_EnDisableBTAC
#define TC_CAL1CACHE_ENDISABLEBTAC 1
// <q0> TC_CAL1Cache_log2_up
#define TC_CAL1CACHE_LOG2_UP 1
// <q0> TC_CAL1Cache_InvalidateDCacheAll
#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1
// <q0> TC_CAL1Cache_CleanDCacheAll
#define TC_CAL1CACHE_CLEANDCACHEALL 1
// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll
#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1
// </h>
#endif /* __CV_CONFIG_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,275 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Config.h
* Purpose: CV Config header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __CV_CONFIG_H
#define __CV_CONFIG_H
#include "RTE_Components.h"
#include CMSIS_device_header
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h> Common Test Settings
// <o> Print Output Format <0=> Plain Text <1=> XML
// <i> Set the test results output format to plain text or XML
#ifndef PRINT_XML_REPORT
#define PRINT_XML_REPORT 0
#endif
// <o> Buffer size for assertions results
// <i> Set the buffer size for assertions results buffer
#define BUFFER_ASSERTIONS 128U
// </h>
// <h> Disable Test Cases
// <i> Uncheck to disable an individual test case
// <q0> TC_CoreInstr_NOP
#define TC_COREINSTR_NOP_EN 1
// <q0> TC_CoreInstr_REV
#define TC_COREINSTR_REV_EN 1
// <q0> TC_CoreInstr_REV16
#define TC_COREINSTR_REV16_EN 1
// <q0> TC_CoreInstr_REVSH
#define TC_COREINSTR_REVSH_EN 1
// <q0> TC_CoreInstr_ROR
#define TC_COREINSTR_ROR_EN 1
// <q0> TC_CoreInstr_RBIT
#define TC_COREINSTR_RBIT_EN 1
// <q0> TC_CoreInstr_CLZ
#define TC_COREINSTR_CLZ_EN 1
// <q0> TC_CoreInstr_Exclusives
#define TC_COREINSTR_EXCLUSIVES_EN 1
// <q0> TC_CoreInstr_SSAT
#define TC_COREINSTR_SSAT_EN 1
// <q0> TC_CoreInstr_USAT
#define TC_COREINSTR_USAT_EN 1
// <q0> TC_CoreAFunc_IRQ
#define TC_COREAFUNC_IRQ 1
// <q0> TC_CoreAFunc_FaultIRQ
#define TC_COREAFUNC_FAULTIRQ 1
// <q0> TC_CoreAFunc_FPSCR
#define TC_COREAFUNC_FPSCR 1
// <q0> TC_CoreAFunc_CPSR
#define TC_COREAFUNC_CPSR 1
// <q0> TC_CoreAFunc_Mode
#define TC_COREAFUNC_MODE 1
// <q0> TC_CoreAFunc_SP
#define TC_COREAFUNC_SP 1
// <q0> TC_CoreAFunc_SP_usr
#define TC_COREAFUNC_SP_USR 1
// <q0> TC_CoreAFunc_FPEXC
#define TC_COREAFUNC_FPEXC 1
// <q0> TC_CoreAFunc_ACTLR
#define TC_COREAFUNC_ACTLR 1
// <q0> TC_CoreAFunc_CPACR
#define TC_COREAFUNC_CPACR 1
// <q0> TC_CoreAFunc_DFSR
#define TC_COREAFUNC_DFSR 1
// <q0> TC_CoreAFunc_IFSR
#define TC_COREAFUNC_IFSR 1
// <q0> TC_CoreAFunc_ISR
#define TC_COREAFUNC_ISR 1
// <q0> TC_CoreAFunc_CBAR
#define TC_COREAFUNC_CBAR 1
// <q0> TC_CoreAFunc_TTBR0
#define TC_COREAFUNC_TTBR0 1
// <q0> TC_CoreAFunc_DACR
#define TC_COREAFUNC_DACR 1
// <q0> TC_CoreAFunc_SCTLR
#define TC_COREAFUNC_SCTLR 1
// <q0> TC_CoreAFunc_ACTRL
#define TC_COREAFUNC_ACTRL 1
// <q0> TC_CoreAFunc_MPIDR
#define TC_COREAFUNC_MPIDR 1
// <q0> TC_CoreAFunc_VBAR
#define TC_COREAFUNC_VBAR 1
// <q0> TC_CoreAFunc_MVBAR
#define TC_COREAFUNC_MVBAR 1
// <q0> TC_CoreAFunc_FPU_Enable
#define TC_COREAFUNC_FPU_ENABLE 1
// <q0> TC_GenTimer_CNTFRQ
#define TC_GENTIMER_CNTFRQ 1
// <q0> TC_GenTimer_CNTP_TVAL
#define TC_GENTIMER_CNTP_TVAL 1
// <q0> TC_GenTimer_CNTP_CTL
#define TC_GENTIMER_CNTP_CTL 1
// <q0> TC_GenTimer_CNTPCT
#define TC_GENTIMER_CNTPCT 1
// <q0> TC_GenTimer_CNTP_CVAL
#define TC_GENTIMER_CNTP_CVAL 1
// <q0> TC_CAL1Cache_EnDisable
#define TC_CAL1CACHE_ENDISABLE 1
// <q0> TC_CAL1Cache_EnDisableBTAC
#define TC_CAL1CACHE_ENDISABLEBTAC 1
// <q0> TC_CAL1Cache_log2_up
#define TC_CAL1CACHE_LOG2_UP 1
// <q0> TC_CAL1Cache_InvalidateDCacheAll
#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1
// <q0> TC_CAL1Cache_CleanDCacheAll
#define TC_CAL1CACHE_CLEANDCACHEALL 1
// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll
#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1
// </h>
#endif /* __CV_CONFIG_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,243 |
```objective-c
/*your_sha256_hash-------------
* Name: CV_Config.h
* Purpose: CV Config header
*your_sha256_hash------------
*your_sha256_hash------------*/
#ifndef __CV_CONFIG_H
#define __CV_CONFIG_H
#include "RTE_Components.h"
#include CMSIS_device_header
#define RTE_CV_COREINSTR 1
#define RTE_CV_COREFUNC 1
#define RTE_CV_CORESIMD 1
#define RTE_CV_MPUFUNC (__MPU_PRESENT)
#if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT
#define RTE_CV_L1CACHE (__ICACHE_PRESENT || __DCACHE_PRESENT)
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h> Common Test Settings
// <o> Print Output Format <0=> Plain Text <1=> XML
// <i> Set the test results output format to plain text or XML
#ifndef PRINT_XML_REPORT
#define PRINT_XML_REPORT 1
#endif
// <o> Buffer size for assertions results
// <i> Set the buffer size for assertions results buffer
#define BUFFER_ASSERTIONS 128U
// </h>
// <h> Disable Test Cases
// <i> Uncheck to disable an individual test case
// <q0> TC_CoreInstr_NOP
#define TC_COREINSTR_NOP_EN 1
// <q0> TC_CoreInstr_SEV
#define TC_COREINSTR_SEV_EN 1
// <q0> TC_CoreInstr_BKPT
#define TC_COREINSTR_BKPT_EN 1
// <q0> TC_CoreInstr_ISB
#define TC_COREINSTR_ISB_EN 1
// <q0> TC_CoreInstr_DSB
#define TC_COREINSTR_DSB_EN 1
// <q0> TC_CoreInstr_DMB
#define TC_COREINSTR_DMB_EN 1
// <q0> TC_CoreInstr_WFI
#define TC_COREINSTR_WFI_EN 0
// <q0> TC_CoreInstr_WFE
#define TC_COREINSTR_WFE_EN 0
// <q0> TC_CoreInstr_REV
#define TC_COREINSTR_REV_EN 1
// <q0> TC_CoreInstr_REV16
#define TC_COREINSTR_REV16_EN 1
// <q0> TC_CoreInstr_REVSH
#define TC_COREINSTR_REVSH_EN 1
// <q0> TC_CoreInstr_ROR
#define TC_COREINSTR_ROR_EN 1
// <q0> TC_CoreInstr_RBIT
#define TC_COREINSTR_RBIT_EN 1
// <q0> TC_CoreInstr_CLZ
#define TC_COREINSTR_CLZ_EN 1
// <q0> TC_CoreInstr_SSAT
#define TC_COREINSTR_SSAT_EN 1
// <q0> TC_CoreInstr_USAT
#define TC_COREINSTR_USAT_EN 1
// <q0> TC_CoreInstr_RRX
#define TC_COREINSTR_RRX_EN 1
// <q0> TC_CoreInstr_LoadStoreExlusive
#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1
// <q0> TC_CoreInstr_LoadStoreUnpriv
#define TC_COREINSTR_LOADSTOREUNPRIV_EN 1
// <q0> TC_CoreInstr_LoadStoreAcquire
#define TC_COREINSTR_LOADSTOREACQUIRE_EN 1
// <q0> TC_CoreInstr_LoadStoreAcquireExclusive
#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1
// <q0> TC_CoreInstr_UnalignedUint16
#define TC_COREINSTR_UNALIGNEDUINT16_EN 1
// <q0> TC_CoreInstr_UnalignedUint32
#define TC_COREINSTR_UNALIGNEDUINT32_EN 1
// <q0> TC_CoreSimd_SatAddSub
#define TC_CORESIMD_SATADDSUB_EN 1
// <q0> TC_CoreSimd_ParSat16
#define TC_CORESIMD_PARSAT16_EN 1
// <q0> TC_CoreSimd_PackUnpack
#define TC_CORESIMD_PACKUNPACK_EN 1
// <q0> TC_CoreSimd_ParSel
#define TC_CORESIMD_PARSEL_EN 1
// <q0> TC_CoreSimd_ParAddSub8
#define TC_CORESIMD_PARADDSUB8_EN 1
// <q0> TC_CoreSimd_AbsDif8
#define TC_CORESIMD_ABSDIF8_EN 1
// <q0> TC_CoreSimd_ParAddSub16
#define TC_CORESIMD_PARADDSUB16_EN 1
// <q0> TC_CoreSimd_ParMul16
#define TC_CORESIMD_PARMUL16_EN 1
// <q0> TC_CoreSimd_Pack16
#define TC_CORESIMD_PACK16_EN 1
// <q0> TC_CoreSimd_MulAcc32
#define TC_CORESIMD_MULACC32_EN 1
// <q0> TC_CoreFunc_EnDisIRQ
#define TC_COREFUNC_ENDISIRQ_EN 1
// <q0> TC_CoreFunc_IRQPrio
#define TC_COREFUNC_IRQPRIO_EN 1
// <q0> TC_CoreFunc_EncDecIRQPrio
#define TC_COREFUNC_ENCDECIRQPRIO_EN 1
// <q0> TC_CoreFunc_IRQVect
#define TC_COREFUNC_IRQVECT_EN 1
// <q0> TC_CoreFunc_Control
#define TC_COREFUNC_CONTROL_EN 1
// <q0> TC_CoreFunc_IPSR
#define TC_COREFUNC_IPSR_EN 1
// <q0> TC_CoreFunc_APSR
#define TC_COREFUNC_APSR_EN 1
// <q0> TC_CoreFunc_PSP
#define TC_COREFUNC_PSP_EN 1
// <q0> TC_CoreFunc_MSP
#define TC_COREFUNC_MSP_EN 1
// <q0> TC_CoreFunc_PSPLIM
#define TC_COREFUNC_PSPLIM_EN 1
// <q0> TC_CoreFunc_PSPLIM_NS
#define TC_COREFUNC_PSPLIM_NS_EN 1
// <q0> TC_CoreFunc_MSPLIM
#define TC_COREFUNC_MSPLIM_EN 1
// <q0> TC_CoreFunc_MSPLIM_NS
#define TC_COREFUNC_MSPLIM_NS_EN 1
// <q0> TC_CoreFunc_PRIMASK
#define TC_COREFUNC_PRIMASK_EN 1
// <q0> TC_CoreFunc_FAULTMASK
#define TC_COREFUNC_FAULTMASK_EN 1
// <q0> TC_CoreFunc_BASEPRI
#define TC_COREFUNC_BASEPRI_EN 1
// <q0> TC_CoreFunc_FPUType
#define TC_COREFUNC_FPUTYPE_EN 1
// <q0> TC_CoreFunc_FPSCR
#define TC_COREFUNC_FPSCR_EN 1
// <q0> TC_MPU_SetClear
#define TC_MPU_SETCLEAR_EN 1
// <q0> TC_MPU_Load
#define TC_MPU_LOAD_EN 1
// <q0> TC_CML1Cache_EnDisableICache
#define TC_CML1CACHE_ENDISABLE_ICACHE 1
// <q0> TC_CML1Cache_EnDisableDCache
#define TC_CML1CACHE_ENDISABLE_DCACHE 1
// <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled
#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1
// </h>
#endif /* __CV_CONFIG_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/Config/CV_Config.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 1,681 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM33.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM33_H
#define PARTITION_ARMCM33_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM33_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,184 |
```objective-c
/**************************************************************************//**
* @file partition_ARMCM35P.h
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P
* @version V5.4.1
* @date 03. September 2018
******************************************************************************/
/*
*
*
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
#ifndef PARTITION_ARMCM35P_H
#define PARTITION_ARMCM35P_H
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
*/
/*
// <e>Initialize Security Attribution Unit (SAU) CTRL register
*/
#define SAU_INIT_CTRL 1
/*
// <q> Enable SAU
// <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
// <o> When SAU is disabled
// <0=> All Memory is Secure
// <1=> All Memory is Non-Secure
// <i> Value for SAU->CTRL register bit ALLNS
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
/*
// </e>
*/
/*
// <h>Initialize Security Attribution Unit (SAU) Address Regions
// <i>SAU configuration specifies regions to be one of:
// <i> - Secure and Non-Secure Callable
// <i> - Non-Secure
// <i>Note: All memory regions not configured by SAU are Secure
*/
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
/*
// <e>Initialize SAU Region 0
// <i> Setup SAU Region 0 memory attributes
*/
#define SAU_INIT_REGION0 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC0 1
/*
// </e>
*/
/*
// <e>Initialize SAU Region 1
// <i> Setup SAU Region 1 memory attributes
*/
#define SAU_INIT_REGION1 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START1 0x00200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END1 0x003FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC1 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 2
// <i> Setup SAU Region 2 memory attributes
*/
#define SAU_INIT_REGION2 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START2 0x20200000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END2 0x203FFFFF
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC2 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 3
// <i> Setup SAU Region 3 memory attributes
*/
#define SAU_INIT_REGION3 1
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START3 0x40000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END3 0x40040000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC3 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 4
// <i> Setup SAU Region 4 memory attributes
*/
#define SAU_INIT_REGION4 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC4 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 5
// <i> Setup SAU Region 5 memory attributes
*/
#define SAU_INIT_REGION5 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START5 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END5 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC5 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 6
// <i> Setup SAU Region 6 memory attributes
*/
#define SAU_INIT_REGION6 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START6 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END6 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC6 0
/*
// </e>
*/
/*
// <e>Initialize SAU Region 7
// <i> Setup SAU Region 7 memory attributes
*/
#define SAU_INIT_REGION7 0
/*
// <o>Start Address <0-0xFFFFFFE0>
*/
#define SAU_INIT_START7 0x00000000
/*
// <o>End Address <0x1F-0xFFFFFFFF>
*/
#define SAU_INIT_END7 0x00000000
/*
// <o>Region is
// <0=>Non-Secure
// <1=>Secure, Non-Secure Callable
*/
#define SAU_INIT_NSC7 0
/*
// </e>
*/
/*
// </h>
*/
/*
// <e>Setup behaviour of Sleep and Exception Handling
*/
#define SCB_CSR_AIRCR_INIT 1
/*
// <o> Deep Sleep can be enabled by
// <0=>Secure and Non-Secure state
// <1=>Secure state only
// <i> Value for SCB->CSR register bit DEEPSLEEPS
*/
#define SCB_CSR_DEEPSLEEPS_VAL 1
/*
// <o>System reset request accessible from
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
*/
#define SCB_AIRCR_SYSRESETREQS_VAL 1
/*
// <o>Priority of Non-Secure exceptions is
// <0=> Not altered
// <1=> Lowered to 0x80-0xFF
// <i> Value for SCB->AIRCR register bit PRIS
*/
#define SCB_AIRCR_PRIS_VAL 1
/*
// <o>BusFault, HardFault, and NMI target
// <0=> Secure state
// <1=> Non-Secure state
// <i> Value for SCB->AIRCR register bit BFHFNMINS
*/
#define SCB_AIRCR_BFHFNMINS_VAL 0
/*
// </e>
*/
/*
// <e>Setup behaviour of Floating Point Unit
*/
#define TZ_FPU_NS_USAGE 1
/*
// <o>Floating Point Unit usage
// <0=> Secure state only
// <3=> Secure and Non-Secure state
// <i> Value for SCB->NSACR register bits CP10, CP11
*/
#define SCB_NSACR_CP10_11_VAL 3
/*
// <o>Treat floating-point registers as Secure
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit TS
*/
#define FPU_FPCCR_TS_VAL 0
/*
// <o>Clear on return (CLRONRET) accessibility
// <0=> Secure and Non-Secure state
// <1=> Secure state only
// <i> Value for FPU->FPCCR register bit CLRONRETS
*/
#define FPU_FPCCR_CLRONRETS_VAL 0
/*
// <o>Clear floating-point caller saved registers on exception return
// <0=> Disabled
// <1=> Enabled
// <i> Value for FPU->FPCCR register bit CLRONRET
*/
#define FPU_FPCCR_CLRONRET_VAL 1
/*
// </e>
*/
/*
// <h>Setup Interrupt Target
*/
/*
// <e>Initialize ITNS 0 (Interrupts 0..31)
*/
#define NVIC_INIT_ITNS0 1
/*
// Interrupts 0..31
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS0_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 1 (Interrupts 32..63)
*/
#define NVIC_INIT_ITNS1 1
/*
// Interrupts 32..63
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS1_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 2 (Interrupts 64..95)
*/
#define NVIC_INIT_ITNS2 0
/*
// Interrupts 64..95
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS2_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 3 (Interrupts 96..127)
*/
#define NVIC_INIT_ITNS3 0
/*
// Interrupts 96..127
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS3_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 4 (Interrupts 128..159)
*/
#define NVIC_INIT_ITNS4 0
/*
// Interrupts 128..159
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS4_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 5 (Interrupts 160..191)
*/
#define NVIC_INIT_ITNS5 0
/*
// Interrupts 160..191
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS5_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 6 (Interrupts 192..223)
*/
#define NVIC_INIT_ITNS6 0
/*
// Interrupts 192..223
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS6_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 7 (Interrupts 224..255)
*/
#define NVIC_INIT_ITNS7 0
/*
// Interrupts 224..255
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS7_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 8 (Interrupts 256..287)
*/
#define NVIC_INIT_ITNS8 0
/*
// Interrupts 256..287
// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS8_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 9 (Interrupts 288..319)
*/
#define NVIC_INIT_ITNS9 0
/*
// Interrupts 288..319
// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS9_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 10 (Interrupts 320..351)
*/
#define NVIC_INIT_ITNS10 0
/*
// Interrupts 320..351
// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS10_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 11 (Interrupts 352..383)
*/
#define NVIC_INIT_ITNS11 0
/*
// Interrupts 352..383
// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS11_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 12 (Interrupts 384..415)
*/
#define NVIC_INIT_ITNS12 0
/*
// Interrupts 384..415
// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS12_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 13 (Interrupts 416..447)
*/
#define NVIC_INIT_ITNS13 0
/*
// Interrupts 416..447
// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS13_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 14 (Interrupts 448..479)
*/
#define NVIC_INIT_ITNS14 0
/*
// Interrupts 448..479
// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS14_VAL 0x00000000
/*
// </e>
*/
/*
// <e>Initialize ITNS 15 (Interrupts 480..511)
*/
#define NVIC_INIT_ITNS15 0
/*
// Interrupts 480..511
// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
*/
#define NVIC_INIT_ITNS15_VAL 0x00000000
/*
// </e>
*/
/*
// </h>
*/
/*
max 128 SAU regions.
SAU regions are defined in partition.h
*/
#define SAU_INIT_REGION(n) \
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
/**
\brief Setup a SAU Region
\details Writes the region information contained in SAU_Region to the
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
*/
__STATIC_INLINE void TZ_SAU_Setup (void)
{
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
SAU_INIT_REGION(0);
#endif
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
SAU_INIT_REGION(1);
#endif
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
SAU_INIT_REGION(2);
#endif
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
SAU_INIT_REGION(3);
#endif
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
SAU_INIT_REGION(4);
#endif
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
SAU_INIT_REGION(5);
#endif
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
SAU_INIT_REGION(6);
#endif
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
SAU_INIT_REGION(7);
#endif
/* repeat this for all possible SAU regions */
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
#endif
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
#endif
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
#endif
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
#endif
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
#endif
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
#endif
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
#endif
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
#endif
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
#endif
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
#endif
#if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
#endif
#if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
#endif
#if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
#endif
#if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
#endif
#if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
#endif
#if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
#endif
#if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
#endif
#if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
#endif
/* repeat this for all possible ITNS elements */
}
#endif /* PARTITION_ARMCM35P_H */
``` | /content/code_sandbox/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h | objective-c | 2016-02-18T08:04:18 | 2024-08-16T08:24:23 | CMSIS_5 | ARM-software/CMSIS_5 | 1,295 | 17,189 |
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