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/*
* Copyright (C) 2015 Xiongfei Guo <xfguo@credosemi.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License, version 3
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program. If not, see
* <http://www.gnu.org/licenses/>.
*
*
* Send a pulse from one domain to another timing domain.
*
* NOTE: the pulse must be one cycle and cannot be set again when busy_o is
* high.
*/
module xdom_pulse_sender (
input grst_i,
input odom_clk_i,
input odom_pulse_i,
input xdom_clk_i,
output xdom_pulse_o,
output busy_o,
output err_o
);
/* signals in origin domain */
reg odom_pulse_delay_r;
reg odom_pulse_keeper_r;
reg [1:0] odom_feedback_double_flips_r ;
reg err_r;
reg odom_pulse_gen_r;
/* cross-domain signals */
wire xdom_pulse_en;
wire odom_pulse_safe_cancel;
/* signals in cross domain */
reg [1:0] xdom_double_flips_r ;
reg xdom_pulse_en_delay_r ;
reg xdom_pulse_gen_r ;
/* latch input pulse for one cycle */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_delay_r <= 1'b0;
else
odom_pulse_delay_r <= odom_pulse_i;
/* detect pos-edge of odm_pulse_i */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_gen_r <= 1'b0;
else if ((odom_pulse_i == 1'b1) && (odom_pulse_delay_r == 1'b0))
odom_pulse_gen_r <= 1'b1;
else
odom_pulse_gen_r <= 1'b0;
/* keep input pulse signal until feedback signal cancel it */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_keeper_r <= 1'b0;
else if (odom_pulse_keeper_r == 1'b0 && (odom_pulse_gen_r == 1'b1))
odom_pulse_keeper_r <= 1'b1;
else if (odom_pulse_keeper_r == 1'b1 && odom_pulse_safe_cancel == 1'b1)
odom_pulse_keeper_r <= 1'b0;
else
odom_pulse_keeper_r <= odom_pulse_keeper_r;
/* busy signal */
assign busy_o = odom_pulse_keeper_r | odom_pulse_i | odom_pulse_safe_cancel;
/* a new request must wait until last is finished */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
err_r <= 1'b0;
else
err_r <= (odom_pulse_keeper_r == 1'b1) && (odom_pulse_i == 1'b1);
assign err_o = err_r;
/* double flips in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_double_flips_r <= 2'b0;
else
xdom_double_flips_r <= {odom_pulse_keeper_r, xdom_double_flips_r[1]};
assign xdom_pulse_en = xdom_double_flips_r[0];
/* double flips in origin-domain */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_feedback_double_flips_r <= 2'b0;
else
odom_feedback_double_flips_r <= {xdom_pulse_en, odom_feedback_double_flips_r[1]};
assign odom_pulse_safe_cancel = odom_feedback_double_flips_r[0];
/* latch cross domain pulse enable signal for one cycle. */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_en_delay_r <= 1'b0;
else
xdom_pulse_en_delay_r <= xdom_pulse_en;
/* generate pulse in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_gen_r <= 1'b0;
else if (xdom_pulse_en == 1'b1 && xdom_pulse_en_delay_r == 1'b0)
xdom_pulse_gen_r <= 1'b1;
else
xdom_pulse_gen_r <= 1'b0;
assign xdom_pulse_o = xdom_pulse_gen_r;
endmodule
|
/*
* @file name: predecode
* @author: ruige lee
* @email: wut.ruigeli@gmail.com
* @date: 2021-01-05 16:23:28
* @last modified by: ruige lee
* @last modified time: 2021-03-11 11:04:35
*/
/*
copyright (c) 2020 - 2021 ruige lee <wut.ruigeli@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1 ns / 1 ps
module predecode (
input [255:0] instr_load,
input [15:0] iq_instr_mask_load,
output instr_buf_empty,
output isjal,
output isjalr,
output isbranch,
output iscall,
output isreturn,
output isrvc,
output isfencei,
output [63:0] imm
);
assign instr_buf_empty = ((iq_instr_mask_load[1] != 1'b1) & instr_load[1:0] == 2'b11)
|
((iq_instr_mask_load[0] != 1'b1) );
wire [31:0] instr = instr_load[31:0];
assign isrvc = ~instr_buf_empty & (instr[1:0] != 2'b11);
wire isijal = ~isrvc & (instr[6:0] == 7'b1101111);
wire iscjal = instr[1:0] == 2'b01 & instr[15:13] == 3'b101;
wire isijalr = ~isrvc & (instr[6:0] == 7'b1100111);
wire iscjalr = (instr[1:0] == 2'b10 & instr[15:13] == 3'b100)
&
(
(~instr[12] & (instr[6:2] == 0))
|
( instr[12] & (|instr[11:7]) & (&(~instr[6:2])))
);
wire isibranch = ~isrvc & (instr[6:0] == 7'b1100011);
wire iscbranch = instr[1:0] == 2'b01 & instr[15:14] == 2'b11;
wire isicall = (isijalr | isijal) & ((instr[11:7] == 5'd1) | instr[11:7] == 5'd5);
wire isccall = iscjalr & instr[12];
wire isireturn = isijalr & ((instr[19:15] == 5'd1) | instr[19:15] == 5'd5)
& (instr[19:15] != instr[11:7]);
wire iscreturn = iscjalr & ~instr[12]
& ((instr[11:7] == 5'd1) | (instr[11:7] == 5'd5));
wire [63:0] iimm =
({64{isijal}} & {{44{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0})
|
({64{isijalr}} & {{52{instr[31]}},instr[31:20]})
|
({64{isibranch}} & {{52{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0});
wire [63:0] cimm =
({64{iscjal}} & {{52{instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0})
|
({64{iscjalr}} & 64'b0)
|
({64{iscbranch}} & {{55{instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0});
assign isjal = ~instr_buf_empty & (isijal | iscjal);
assign isjalr = ~instr_buf_empty & (isijalr | iscjalr);
assign isbranch = ~instr_buf_empty & (isibranch | iscbranch);
assign iscall = ~instr_buf_empty & (isicall | isccall);
assign isreturn = ~instr_buf_empty & (isireturn | iscreturn);
assign isfencei = (instr[6:0] == 7'b0001111) & (instr[14:12] == 3'b001);
assign imm = isrvc ? cimm : iimm;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_texcache #(
parameter cache_depth = 13, /* < log2 of the capacity in 8-bit words */
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [fml_depth-1-1:0] tadra,
input [fml_depth-1-1:0] tadrb,
input [fml_depth-1-1:0] tadrc,
input [fml_depth-1-1:0] tadrd,
input [5:0] x_frac,
input [5:0] y_frac,
output pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output [15:0] tcolora,
output [15:0] tcolorb,
output [15:0] tcolorc,
output [15:0] tcolord,
output reg [5:0] x_frac_f,
output reg [5:0] y_frac_f,
output reg [21:0] c_req_a,
output reg [21:0] c_hit_a,
output reg [21:0] c_req_b,
output reg [21:0] c_hit_b,
output reg [21:0] c_req_c,
output reg [21:0] c_hit_c,
output reg [21:0] c_req_d,
output reg [21:0] c_hit_d
);
/*
* To make bit index calculations easier,
* we work with 8-bit granularity EVERYWHERE, unless otherwise noted.
*/
/*
* Line length is the burst length, that is 4*64 bits, or 32 bytes
* Addresses are split as follows:
*
* | TAG | INDEX | OFFSET |
* |fml_depth-1 cache_depth|cache_depth-1 5|4 0|
*
*/
/* MEMORIES & HIT HANDLING */
wire [fml_depth-1:0] tadra8 = {tadra, 1'b0};
wire [fml_depth-1:0] tadrb8 = {tadrb, 1'b0};
wire [fml_depth-1:0] tadrc8 = {tadrc, 1'b0};
wire [fml_depth-1:0] tadrd8 = {tadrd, 1'b0};
reg [fml_depth-1:0] tadra8_r;
reg [fml_depth-1:0] tadrb8_r;
reg [fml_depth-1:0] tadrc8_r;
reg [fml_depth-1:0] tadrd8_r;
always @(posedge sys_clk) begin
if(pipe_ack_o) begin
tadra8_r <= tadra8;
tadrb8_r <= tadrb8;
tadrc8_r <= tadrc8;
tadrd8_r <= tadrd8;
end
end
wire retry; /* < retry the old address after a miss */
wire [31:0] datamem_d1;
wire [31:0] datamem_d2;
wire [31:0] datamem_d3;
wire [31:0] datamem_d4;
reg datamem_we;
wire [cache_depth-3-1:0] datamem_aw;
tmu2_qpram32 #(
.depth(cache_depth-2)
) datamem (
.sys_clk(sys_clk),
.a1(retry ? tadra8_r[cache_depth-1:2] : tadra8[cache_depth-1:2]),
.d1(datamem_d1),
.a2(retry ? tadrb8_r[cache_depth-1:2] : tadrb8[cache_depth-1:2]),
.d2(datamem_d2),
.a3(retry ? tadrc8_r[cache_depth-1:2] : tadrc8[cache_depth-1:2]),
.d3(datamem_d3),
.a4(retry ? tadrd8_r[cache_depth-1:2] : tadrd8[cache_depth-1:2]),
.d4(datamem_d4),
.we(datamem_we),
.aw(datamem_aw),
.dw(fml_di)
);
assign tcolora = tadra8_r[1] ? datamem_d1[15:0] : datamem_d1[31:16];
assign tcolorb = tadrb8_r[1] ? datamem_d2[15:0] : datamem_d2[31:16];
assign tcolorc = tadrc8_r[1] ? datamem_d3[15:0] : datamem_d3[31:16];
assign tcolord = tadrd8_r[1] ? datamem_d4[15:0] : datamem_d4[31:16];
wire [1+fml_depth-cache_depth-1:0] tagmem_d1; /* < valid bit + tag */
wire [1+fml_depth-cache_depth-1:0] tagmem_d2;
wire [1+fml_depth-cache_depth-1:0] tagmem_d3;
wire [1+fml_depth-cache_depth-1:0] tagmem_d4;
reg tagmem_we;
wire [cache_depth-1-5:0] tagmem_aw;
wire [1+fml_depth-cache_depth-1:0] tagmem_dw;
tmu2_qpram #(
.depth(cache_depth-5),
.width(1+fml_depth-cache_depth)
) tagmem (
.sys_clk(sys_clk),
.a1(retry ? tadra8_r[cache_depth-1:5] : tadra8[cache_depth-1:5]),
.d1(tagmem_d1),
.a2(retry ? tadrb8_r[cache_depth-1:5] : tadrb8[cache_depth-1:5]),
.d2(tagmem_d2),
.a3(retry ? tadrc8_r[cache_depth-1:5] : tadrc8[cache_depth-1:5]),
.d3(tagmem_d3),
.a4(retry ? tadrd8_r[cache_depth-1:5] : tadrd8[cache_depth-1:5]),
.d4(tagmem_d4),
.we(tagmem_we),
.aw(tagmem_aw),
.dw(tagmem_dw)
);
/* HIT HANDLING */
reg flush_mode;
reg access_requested;
always @(posedge sys_clk) begin
if(sys_rst)
access_requested <= 1'b0;
else if(pipe_ack_o)
access_requested <= pipe_stb_i;
end
/* The cycle after the tag memory has been written, data is invalid */
reg tagmem_we_r;
always @(posedge sys_clk) tagmem_we_r <= tagmem_we;
/* If some coordinates are integer, B, C or D can be ignored
* and safely assumed to be cache hits.
*/
reg ignore_b;
reg ignore_c;
reg ignore_d;
always @(posedge sys_clk) begin
if(pipe_ack_o) begin
ignore_b <= x_frac == 6'd0;
ignore_c <= y_frac == 6'd0;
ignore_d <= (x_frac == 6'd0) | (y_frac == 6'd0);
end
end
wire valid_a = tagmem_d1[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_a = tagmem_d1[fml_depth-cache_depth-1:0];
wire valid_b = tagmem_d2[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_b = tagmem_d2[fml_depth-cache_depth-1:0];
wire valid_c = tagmem_d3[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_c = tagmem_d3[fml_depth-cache_depth-1:0];
wire valid_d = tagmem_d4[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_d = tagmem_d4[fml_depth-cache_depth-1:0];
wire hit_a = ~tagmem_we_r & valid_a & (tag_a == tadra8_r[fml_depth-1:cache_depth]);
wire hit_b = ignore_b | (~tagmem_we_r & valid_b & (tag_b == tadrb8_r[fml_depth-1:cache_depth]));
wire hit_c = ignore_c | (~tagmem_we_r & valid_c & (tag_c == tadrc8_r[fml_depth-1:cache_depth]));
wire hit_d = ignore_d | (~tagmem_we_r & valid_d & (tag_d == tadrd8_r[fml_depth-1:cache_depth]));
assign pipe_stb_o = access_requested & hit_a & hit_b & hit_c & hit_d;
assign pipe_ack_o = ~flush_mode & ((pipe_ack_i & pipe_stb_o) | ~access_requested);
assign retry = ~pipe_ack_o;
/* STATISTICS COLLECTION */
reg pipe_ack_o_r;
always @(posedge sys_clk) begin
if(sys_rst)
pipe_ack_o_r <= 1'b0;
else
pipe_ack_o_r <= pipe_ack_o;
end
always @(posedge sys_clk) begin
if(sys_rst|flush) begin
c_req_a <= 22'd0;
c_hit_a <= 22'd0;
c_req_b <= 22'd0;
c_hit_b <= 22'd0;
c_req_c <= 22'd0;
c_hit_c <= 22'd0;
c_req_d <= 22'd0;
c_hit_d <= 22'd0;
end else begin
if(pipe_ack_o_r & access_requested) begin
c_req_a <= c_req_a + 22'd1;
if(hit_a)
c_hit_a <= c_hit_a + 22'd1;
if(~ignore_b) begin
c_req_b <= c_req_b + 22'd1;
if(hit_b)
c_hit_b <= c_hit_b + 22'd1;
end
if(~ignore_c) begin
c_req_c <= c_req_c + 22'd1;
if(hit_c)
c_hit_c <= c_hit_c + 22'd1;
end
if(~ignore_d) begin
c_req_d <= c_req_d + 22'd1;
if(hit_d)
c_hit_d <= c_hit_d + 22'd1;
end
end
end
end
`ifdef VERIFY_TEXCACHE
integer x, y;
reg [15:0] expected;
always @(posedge sys_clk) begin
if(pipe_stb_o & pipe_ack_i) begin
x = (tadra8_r/2) % 512;
y = (tadra8_r/2) / 512;
$image_get(x, y, expected);
if(tcolora != expected) begin
$display("CACHE TEST FAILED [A]! (%d, %d): expected %x, got %x", x, y, expected, tcolora);
$finish;
end
if(~ignore_b) begin
x = (tadrb8_r/2) % 512;
y = (tadrb8_r/2) / 512;
$image_get(x, y, expected);
if(tcolorb != expected) begin
$display("CACHE TEST FAILED [B]! (%d, %d): expected %x, got %x", x, y, expected, tcolorb);
$finish;
end
end
if(~ignore_c) begin
x = (tadrc8_r/2) % 512;
y = (tadrc8_r/2) / 512;
$image_get(x, y, expected);
if(tcolorc != expected) begin
$display("CACHE TEST FAILED [C]! (%d, %d): expected %x, got %x", x, y, expected, tcolorc);
$finish;
end
end
if(~ignore_d) begin
x = (tadrd8_r/2) % 512;
y = (tadrd8_r/2) / 512;
$image_get(x, y, expected);
if(tcolord != expected) begin
$display("CACHE TEST FAILED [D]! (%d, %d): expected %x, got %x", x, y, expected, tcolord);
$finish;
end
end
end
end
`endif
/* FORWARDING */
always @(posedge sys_clk) begin
if(pipe_ack_o & pipe_stb_i) begin
dadr_f <= dadr;
x_frac_f <= x_frac;
y_frac_f <= y_frac;
end
end
/* MISS HANDLING */
reg fetch_needed;
reg [fml_depth-1:0] fetch_adr;
always @(posedge sys_clk) begin
if(sys_rst)
fetch_needed <= 1'b0;
else begin
if(access_requested) begin
fetch_needed <= ~(hit_a & hit_b & hit_c & hit_d);
if(~hit_a)
fetch_adr <= tadra8_r;
else if(~hit_b)
fetch_adr <= tadrb8_r;
else if(~hit_c)
fetch_adr <= tadrc8_r;
else if(~hit_d)
fetch_adr <= tadrd8_r;
end
end
end
wire flush_done;
reg [cache_depth-1-5:0] flush_counter;
always @(posedge sys_clk) begin
if(flush_mode)
flush_counter <= flush_counter + 1'd1;
else
flush_counter <= {cache_depth-5{1'b0}};
end
assign flush_done = &flush_counter;
reg write_valid;
assign tagmem_aw = flush_mode ? flush_counter : fetch_adr[cache_depth-1:5];
assign tagmem_dw = {write_valid, fetch_adr[fml_depth-1:cache_depth]};
reg burst_count;
reg [1:0] burst_counter;
always @(posedge sys_clk) begin
if(burst_count)
burst_counter <= burst_counter + 2'd1;
else
burst_counter <= 2'd0;
end
assign datamem_aw = {fetch_adr[cache_depth-1:5], burst_counter};
assign fml_adr = {fetch_adr[fml_depth-1:5], 5'd0};
/* FSM controller */
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter DATA1 = 3'd1;
parameter DATA2 = 3'd2;
parameter DATA3 = 3'd3;
parameter DATA4 = 3'd4;
parameter WAIT = 3'd5;
parameter WAIT2 = 3'd6;
parameter FLUSH = 3'd7;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
reg fsm_busy;
always @(*) begin
next_state = state;
tagmem_we = 1'b0;
write_valid = 1'b1;
datamem_we = 1'b0;
burst_count = 1'b0;
flush_mode = 1'b0;
fml_stb = 1'b0;
fsm_busy = 1'b1;
case(state)
IDLE: begin
fsm_busy = 1'b0;
if(fetch_needed)
next_state = DATA1;
if(flush)
next_state = FLUSH;
end
DATA1: begin
fml_stb = 1'b1;
datamem_we = 1'b1;
if(fml_ack) begin
burst_count = 1'b1;
next_state = DATA2;
end
end
DATA2: begin
datamem_we = 1'b1;
burst_count = 1'b1;
next_state = DATA3;
end
DATA3: begin
datamem_we = 1'b1;
burst_count = 1'b1;
next_state = DATA4;
end
DATA4: begin
datamem_we = 1'b1;
tagmem_we = 1'b1; /* write tag last as it may unlock the pipeline */
next_state = WAIT;
end
WAIT: next_state = WAIT2; /* wait for fetch_needed to reflect the updated tag */
WAIT2: next_state = IDLE;
FLUSH: begin
tagmem_we = 1'b1;
write_valid = 1'b0;
flush_mode = 1'b1;
if(flush_done)
next_state = IDLE;
end
endcase
end
assign busy = fsm_busy | access_requested;
endmodule
|
/*
copyright 2018 ali raheem <ali.raheem@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and limitations under the license.
*/
module piso_tb();
reg clk;
reg latch;
reg rst;
reg [7:0] din;
reg ser;
wire dout;
piso #(.width(8)) dut(
.clk(clk),
.latch(latch),
.rst(rst),
.din(din),
.ser(ser),
.dout(dout)
);
initial begin
$dumpfile("piso_test.vcd");
$dumpvars(0, piso_tb);
$dumpfile("piso.vcd");
$dumpvars(0, dut);
rst = 1;
ser = 0;
latch = 0;
clk = 0;
din = 8'b0;
#10
rst = 0;
#5
din = 8'h55;
latch = 1;
#15
latch = 0;
din = 0;
#100
din = 8'haa;
latch = 1;
#7
latch = 0;
din = 0;
#100
din = 8'h0f;
latch = 1;
#10
latch = 0;
din = 0;
#100
din = 8'hcd;
latch = 1;
#7
latch = 0;
din = 0;
#100
#100
din = 8'b10000000;
latch = 1;
#5
latch = 0;
din = 0;
#100
din = 8'hf0;
latch = 1;
#5
latch = 0;
din = 0;
#100
$finish;
end // initial begin
always #5
clk = ~clk;
endmodule // piso_tb
|
`timescale 1ns / 1ps
/* this file is part of jt51.
jt51 program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
jt51 program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with jt51. if not, see <http://www.gnu.org/licenses/>.
author: jose tejada gomez. twitter: @topapate
version: 1.0
date: 27-1-2017
*/
module jt51_kon(
input rst,
input clk,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] cur_op,
input [2:0] cur_ch,
input up_keyon,
input csm,
input overflow_a,
output reg keyon_ii
);
//reg csm_copy;
reg din;
wire drop;
reg [3:0] cur_op_hot;
always @(posedge clk)
keyon_ii <= (csm&&overflow_a) || drop;
always @(*) begin
case( cur_op )
2'd0: cur_op_hot = 4'b0001; // s1 / m1
2'd1: cur_op_hot = 4'b0100; // s3 / m2
2'd2: cur_op_hot = 4'b0010; // s2 / c1
2'd3: cur_op_hot = 4'b1000; // s4 / c2
endcase
din = keyon_ch==cur_ch && up_keyon ? |(keyon_op&cur_op_hot) : drop;
end
jt51_sh #(.width(1),.stages(32)) u_konch(
.clk ( clk ),
.din ( din ),
.drop ( drop )
);
endmodule
|
/*
* mbus copyright 2015 regents of the university of michigan
*
* licensed under the apache license, version 2.0 (the "license");
* you may not use this file except in compliance with the license.
* you may obtain a copy of the license at
*
* http://www.apache.org/licenses/license-2.0
*
* unless required by applicable law or agreed to in writing, software
* distributed under the license is distributed on an "as is" basis,
* without warranties or conditions of any kind, either express or implied.
* see the license for the specific language governing permissions and
* limitations under the license.
*/
//****************************************
//task 0 testbench: comprehensive testbench
//****************************************
task task0;
begin
handle=$fopen("result_task0.txt");
#100000;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task0%d, master node and processor wake up", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_proc_up;
@ (posedge sclk);
c0_req_int = 0;
#50000;
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, query", task_counter);
$fdisplay(handle, "master node sends out query");
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_query;
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h2");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h2;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h3");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h3;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h4");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h4;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h5");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h5;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, all wake", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_all_wakeup;
@ (posedge c0_tx_succ | c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0, bulk write enable is not set, it won't fail but no memory operation");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 0 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h2;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 3 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h5;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1 rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 0;
dest_short_addr = 4'h3;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1 rf address 1-4");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 1;
dest_short_addr = 4'h3;
word_counter = 3;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "read layer 1's rf address 0, and write to layer 2's rf address 0xa");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 0;
rf_read_length = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_rf_write);
rf_relay_loc = 8'ha;
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "bulk read layer 1's rf address 1-4, and write to layer 2's rf address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 1;
rf_read_length = 3;
relay_addr = ((4'h4<<4) | `lc_cmd_rf_write);
rf_relay_loc = 8'h1;
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and write to layer 2's mem, address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 0;
mem_addr = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd1;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-10, bulk active is not set");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 9;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set active, length 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-2, bulk active is set, length is 0, only write 1 word");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 1;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-3, bulk active is set, length is 0, only write 1 word, should fail");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 2;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set active, length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-10");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 9;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 3 default sys register bulk mem message control, set to maximum length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h5;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "bulk read layer 1's mem address 1-10, and write to layer 3's mem, address 0x0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 9;
mem_addr = 1;
relay_addr = ((4'h5<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd0;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 0 ");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg0_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = 24'h00_0004;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg1_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd1
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1010, 20'd15};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 0 ");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg0_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = 24'h190; // 100 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg1_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd100
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1110, 20'd7};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 3's stream channel 0, enable is not set, should fail");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
stream_channel = 0;
word_counter = 2;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 16 word streaming data to layer 1's stream channel 0, cpu should receive a buffer full alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 15;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 1's stream channel 0, nothing happens");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1010, 20'd15};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 1's stream channel 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 10 word streaming data to layer 1's stream channel 0, cpu should receive a double buffer alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 9;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 10 word streaming data to layer 1's stream channel 0, only 5 words are available, tx should fail, and generates alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 9;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 4 word streaming data to layer 1's stream channel 1, generates double buffer alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 3;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 4 word streaming data to layer 1's stream channel 1, generates buffer full alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 3;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 8 word streaming data to layer 1's stream channel 1, generates alert 0xe");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 7;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 16 word streaming data to layer 1's stream channel 1, generates alert 0xf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 15;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1100, 20'd7};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "read layer 3's mem and stream to layer 1's mem, channel 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
mem_read_length = 3;
mem_addr = 0;
relay_addr = {4'd3, 2'b01, 2'b01}; // to layer 1, stream, channel 1
state = tb_short_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer3.tx_succ | layer3.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, select sleep", task_counter);
$fdisplay(handle, "select sleep using long prefix, sleep layer 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
long_addr = 20'hbbbb1;
state = tb_sel_sleep_full_prefix;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0xa");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 30'ha;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 0, read layer 1's rf address 0, and write to layer 2's rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 0;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 1, bulk read layer 1's rf address 2-6, and write to layer 2's rf address 2");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 1;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1 rf address 0-9");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 0;
dest_short_addr = 4'h3;
word_counter = 9;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg0_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = 24'h190; // 100 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg1_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd100
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = {4'b1100, 20'd15}; // maximum length = 16
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg0_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc8; // 50 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg1_idx;
dest_short_addr = 4'h4;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd50
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx;
dest_short_addr = 4'h4;
rf_w_data = {4'b1110, 20'd4}; // maximum length = 5
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 2, bulk read layer 1's rf address 0-9, and stream to layer 2's mem address 100");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 2;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 3, write to layer 1's rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 3;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 4, write to layer 1's rf address 1, and 3");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 4;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 5, write to layer 1's rf address 2, 4, and 6");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 5;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 6, read from layer 1's mem address 0, and write to layer 2's mem, address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 6;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control, set to maximum length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, select sleep", task_counter);
$fdisplay(handle, "select sleep using long prefix, sleep layer 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
long_addr = 20'hbbbb1;
state = tb_sel_sleep_full_prefix;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 7, bulk read from layer 1's mem address 1-5, and write to layer 2's mem, address 2-6");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 7;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 2, interrupt vector 8, read from layer 2's mem address 100, and write to layer 1's rf (address is burried in mem)");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 2; // this is asserted from layer 2
int_vec = 8;
state = tb_single_interrupt;
@ (posedge n2_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 2, interrupt vector 9, read from layer 2's mem address 101-104, and write to layer 1's rf (address is burried in mem)");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 2; // this is asserted from layer 2
int_vec = 9;
state = tb_single_interrupt;
@ (posedge n2_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 10, bulk read from layer 1's mem address 0-9, stream to layer 2's mem, alert should generate");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 10;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, sleep all", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_all_sleep;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 11, wakeup only");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 11;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, master node and processor wake up", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_proc_up;
@ (posedge sclk);
c0_req_int = 0;
#50000;
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "cpu sends a command with an unknown functional id");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = 4'b1100;
word_counter = 1;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "bulk read layer 1's mem address 0-1, and read layer 3's rf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 1;
mem_addr = 0;
relay_addr = ((4'h5<<4) | `lc_cmd_rf_read); // fake rf read
// read rf from 192-197, write to layer 2's rf location 0 <- this is an invalid rf read command
mem_relay_loc = (8'd192<<22 | 8'd5<<14 | 4'h4<<10 | `lc_cmd_rf_write<<6 | 6'h0);
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and read layer 3's rf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 0;
mem_addr = 0;
relay_addr = ((4'h5<<4) | `lc_cmd_rf_read); // fake rf read
// read rf from 192-197 (non-existing location), write to layer 2's rf location 0 <- this is an invalid rf read command
mem_relay_loc = (8'd192<<22 | 8'd5<<14 | 4'h4<<10 | `lc_cmd_rf_write<<6 | 6'h0);
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "read layer 1's rf address 250-4, and send to processor, coverage test");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 8'd250;
rf_read_length = 9;
relay_addr = {4'h1, `lc_cmd_rf_write}; // fuid don't care
rf_relay_loc = 8'ha; // don't care
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem read command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_read;
word_counter = 0;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem read command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_read;
word_counter = 5;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem write command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_write;
word_counter = 0;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 3's stream channel 0. (stream enable = 0, no mem operation)");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
stream_channel = 0;
word_counter = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 12, invalid interrupt command");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 12;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set to maximum length 64");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_003f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control, set to maximum length 64");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc0_003f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 0-63");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 63;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and write to layer 2's mem, address 0x0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 63;
mem_addr = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd0;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#500000;
$display("*************************************");
$display("************task0 complete***********");
$display("*************************************");
$finish;
end
endtask // task0
|
/*
* ravenna - a full example soc using picorv32 in x-fab xh018
*
* copyright (c) 2017 clifford wolf <clifford@clifford.at>
* copyright (c) 2018,2019 tim edwards <tim@efabless.com>
*
* permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* the software is provided "as is" and the author disclaims all warranties
* with regard to this software including all implied warranties of
* merchantability and fitness. in no event shall the author be liable for
* any special, direct, indirect, or consequential damages or any damages
* whatsoever resulting from loss of use, data or profits, whether in an
* action of contract, negligence or other tortious action, arising out of
* or in connection with the use or performance of this software.
*
*/
`timescale 1 ns / 1 ps
`ifndef lvs
// local files
`include "ravenna_soc.v"
`include "ravenna_spi.v"
`include "spi_slave.v"
// marketplace ip
// behavioral verilog components
`include "amux2_3v.v"
`include "amux4_3v.v"
`include "ls_3vx2.v"
// `include "xspramblp_4096x32_m8p.v"
// test: memory increased from 4x32 to 16x32. this represents memory that
// does not actually exist on the chip!
`include "sram_test.v"
`include "xcpf_136x32dp128_vd03.v"
`include "xnvr_136x32p128_vd01.v"
// pdk ip
// 3.3v digital standard cells
`include "d_cells_3v.v"
// 1.8v digital standard cells
`include "d_cells.v"
// 1.8v core / 3.3v i/o padframe cells
`include "io_cells_f3v.v"
// 3.3v core / 3.3v i/o padframe cells (isolate from 1.8v core cells!)
`include "io_cells_fc3v.v"
// 1.8v analog cells
`include "apllc03_1v8.v"
`include "acsoc04_1v8.v"
// 3.3v analog cells
`include "atmpc01_3v3.v"
`include "aadcc01_3v3.v"
`include "adacc01_3v3.v"
`include "aopac01_3v3.v"
`include "abgpc01_3v3.v"
`include "acmpc01_3v3.v"
`include "axtoc02_3v3.v"
`include "arcoc01_3v3.v"
`include "aregc01_3v3.v"
`include "aporc02_3v3.v"
`include "acsoc01_3v3.v"
`include "acsoc02_3v3.v"
`endif
// primitive devices (for lvs, and need (empty) model to prevent error on simulation).
`include "cmm5t.v"
`include "dn.v"
`include "dn3.v"
// ravenna, a picosoc implementation in x-fab xh018
module ravenna (
// padframe i/o
input wire real vdd3v3, // 3v power supply
output wire real vdd1v8, // 1.8v from regulator (for external cap)
input wire real vss, // ground
// crystal
input wire real xi, // crystal oscillator in
output wire real xo, // crystal oscillator out
input xclk, // external clock (pll bypass mode)
// housekeeping spi
input sdi, // spi controller data in
output sdo, // spi controller data out
input csb, // spi controller select
input sck, // spi controller clock
// uart
output ser_tx, // uart transmit
input ser_rx, // uart receive
// i2c
inout i2c_sda,
inout i2c_scl,
// spi master
input spi_sdi,
output spi_csb,
output spi_sck,
output spi_sdo,
// irq
input irq, // dedicated irq pin
// gpio
output [15:0] gpio, // general-purpose i/o
// flash
output flash_csb, // spi flash memory
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
// analog i/o
input wire real adc_high,
input wire real adc_low,
input wire real adc0_in,
input wire real adc1_in,
output wire real analog_out, // test analog port (multiplexed, buffered)
input wire real comp_inp,
input wire real comp_inn,
input wire real nvref_ext // nvram test analog port
);
wire dground;
wire dvdd;
wire reset;
wire resetn;
wire clk;
wire irq;
wire flash_io0_oeb, flash_io0_do, flash_io0_di;
wire flash_io1_oeb, flash_io1_do, flash_io1_di;
wire flash_io2_oeb, flash_io2_do, flash_io2_di;
wire flash_io3_oeb, flash_io3_do, flash_io3_di;
wire flash_clk_oeb;
wire [15:0] gpio_in_core;
wire [15:0] gpio_out_core;
wire irq_pin_core;
wire flash_csb_core;
wire flash_clk_core;
wire ser_rx_core;
wire ser_tx_core;
/* analog values represented by reals */
// wire real vdd3v3;
// wire real vdd1v8;
// wire real vss;
// wire real adc_high;
// wire real adc_low;
// wire real adc0_in;
// wire real adc1_in;
// wire real analog_out;
// wire real comp_inp;
// wire real comp_inn;
// declare bus widths
wire [15:0] gpio_pullupb;
wire [15:0] gpio_pulldownb;
wire [15:0] gpio_outenb;
wire [9:0] adc0_data;
wire [1:0] adc0_inputsrc;
wire [9:0] adc1_data;
wire [1:0] adc1_inputsrc;
wire [9:0] dac_value;
wire [1:0] comp_ninputsrc;
wire [1:0] comp_pinputsrc;
wire [7:0] spi_config;
wire [3:0] spi_pll_trim;
wire [11:0] spi_mfgr_id;
wire [7:0] spi_prod_id;
wire [3:0] spi_mask_rev;
// declare level-shifted signals
wire spi_trap_3v;
wire sck_core_lv;
wire spi_pll_vco_ena_lv;
wire spi_pll_cp_ena_lv;
wire spi_pll_bias_ena_lv;
wire [3:0] spi_pll_trim_lv;
wire spi_irq_lv;
wire spi_reset_lv;
wire spi_pll_bypass_lv;
wire [7:0] spi_config_lv;
wire spi_xtal_ena_lv;
wire spi_reg_ena_lv;
wire [11:0] spi_mfgr_id_lv;
wire [7:0] spi_prod_id_lv;
wire [3:0] spi_mask_rev_lv;
wire opamp_ena_3v;
wire opamp_bias_ena_3v;
wire bg_ena_3v;
wire comp_out_lv;
wire comp_ena_3v;
wire xtal_out_lv;
wire rcosc_ena_3v;
wire rcosc_out_lv;
wire reset_lv;
wire overtemp_ena_3v;
wire overtemp_lv;
/* padframe pads */
/* analog input/output pads */
apr00df adc0_pad (
.gndo(vss),
.gndr(vss),
.pad(adc0_in),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc1_pad (
.gndo(vss),
.gndr(vss),
.pad(adc1_in),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc_low_pad (
.gndo(vss),
.gndr(vss),
.pad(adc_low),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc_high_pad (
.gndo(vss),
.gndr(vss),
.pad(adc_high),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df ana_out_pad (
.gndo(vss),
.gndr(vss),
.pad(analog_out),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df comp_inn_pad (
.gndo(vss),
.gndr(vss),
.pad(comp_inn),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df comp_inp_pad (
.gndo(vss),
.gndr(vss),
.pad(comp_inp),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df nvref_ext_pad (
.gndo(vss),
.gndr(vss),
.pad(nvref_ext),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* power supplies (there are multiple pads that need to be represented) */
vddorpadf vddor_pad [4:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddor(vdd3v3)
);
vddpadf vdd_pad [1:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
vddpadfc vdd3_pad (
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
gndorpadf gndor_pad [6:0] (
.gndor(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
corneresdf padframe_corner [3:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* custom-designed power cut cell isolates the vdd3 and vdd buses */
powercutvdd3fc pwr_cut [1:0] (
.gndo(vss),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* implement bidirectional i/o with x-fab pads */
/* see: /ef/tech/xfab.3/efxh018d/libs.ref/verilog/io_cells_3v/io_cells_3v.v */
bbc4f flash_io_buf_3 (
.pad(flash_io3),
.en(flash_io3_oeb),
.a(flash_io3_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io3_di)
);
bbc4f flash_io_buf_2 (
.pad(flash_io2),
.en(flash_io2_oeb),
.a(flash_io2_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io2_di)
);
bbc4f flash_io_buf_1 (
.pad(flash_io1),
.en(flash_io1_oeb),
.a(flash_io1_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io1_di)
);
bbc4f flash_io_buf_0 (
.pad(flash_io0),
.en(flash_io0_oeb),
.a(flash_io0_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io0_di)
);
/* standalone spi controller (3v) */
icfc sck_buf (
.pad(sck),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(sck_core)
);
icfc csb_buf (
.pad(csb),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(csb_core)
);
icfc sdi_buf (
.pad(sdi),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(sdi_core)
);
bt4fc sdo_buf (
.pad(sdo),
.en(sdo_enb),
.a(sdo_core),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* implement digital input on irq dedicated pin */
icf irq_buf (
.pad(irq),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(irq_pin_core)
);
/* implement digital input on ser_rx */
icf ser_rx_buf (
.pad(ser_rx),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(ser_rx_core)
);
/* implement digital outputs on ser_tx, i2c, leds, csb, and clk */
bt4f ser_tx_buf (
.pad(ser_tx),
.en(reset_lv),
.a(ser_tx_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bbcud4f i2c_scl_pad (
.a(i2c_scl_o),
.en(i2c_scl_oeb),
.gndo(vss),
.gndr(vss),
.pad(i2c_scl),
.pden(dground),
.pi(dground),
.po(),
.puen(dground), // to do: enable pu, optional 5, 10k?
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(i2c_scl_i)
);
bbcud4f i2c_sda_pad (
.a(i2c_sda_o),
.en(i2c_sda_oeb),
.gndo(vss),
.gndr(vss),
.pad(i2c_sda),
.pden(dground),
.pi(dground),
.po(),
.puen(dground), // to do: enable pu, optional 5, 10k?
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(i2c_sda_i)
);
// gpio is digital bidirectional buffer with selectable pull-up and pull-down
bbcud4f gpio_buf_15 (
.a(gpio_out_core[15]),
.en(gpio_outenb[15]),
.gndo(vss),
.gndr(vss),
.pad(gpio[15]),
.pden(gpio_pulldownb[15]),
.pi(dground),
.po(),
.puen(gpio_pullupb[15]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[15])
);
bbcud4f gpio_buf_14 (
.a(gpio_out_core[14]),
.en(gpio_outenb[14]),
.gndo(vss),
.gndr(vss),
.pad(gpio[14]),
.pden(gpio_pulldownb[14]),
.pi(dground),
.po(),
.puen(gpio_pullupb[14]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[14])
);
bbcud4f gpio_buf_13 (
.a(gpio_out_core[13]),
.en(gpio_outenb[13]),
.gndo(vss),
.gndr(vss),
.pad(gpio[13]),
.pden(gpio_pulldownb[13]),
.pi(dground),
.po(),
.puen(gpio_pullupb[13]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[13])
);
bbcud4f gpio_buf_12 (
.a(gpio_out_core[12]),
.en(gpio_outenb[12]),
.gndo(vss),
.gndr(vss),
.pad(gpio[12]),
.pden(gpio_pulldownb[12]),
.pi(dground),
.po(),
.puen(gpio_pullupb[12]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[12])
);
bbcud4f gpio_buf_11 (
.a(gpio_out_core[11]),
.en(gpio_outenb[11]),
.gndo(vss),
.gndr(vss),
.pad(gpio[11]),
.pden(gpio_pulldownb[11]),
.pi(dground),
.po(),
.puen(gpio_pullupb[11]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[11])
);
bbcud4f gpio_buf_10 (
.a(gpio_out_core[10]),
.en(gpio_outenb[10]),
.gndo(vss),
.gndr(vss),
.pad(gpio[10]),
.pden(gpio_pulldownb[10]),
.pi(dground),
.po(),
.puen(gpio_pullupb[10]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[10])
);
bbcud4f gpio_buf_9 (
.a(gpio_out_core[9]),
.en(gpio_outenb[9]),
.gndo(vss),
.gndr(vss),
.pad(gpio[9]),
.pden(gpio_pulldownb[9]),
.pi(dground),
.po(),
.puen(gpio_pullupb[9]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[9])
);
bbcud4f gpio_buf_8 (
.a(gpio_out_core[8]),
.en(gpio_outenb[8]),
.gndo(vss),
.gndr(vss),
.pad(gpio[8]),
.pden(gpio_pulldownb[8]),
.pi(dground),
.po(),
.puen(gpio_pullupb[8]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[8])
);
bbcud4f gpio_buf_7 (
.a(gpio_out_core[7]),
.en(gpio_outenb[7]),
.gndo(vss),
.gndr(vss),
.pad(gpio[7]),
.pden(gpio_pulldownb[7]),
.pi(dground),
.po(),
.puen(gpio_pullupb[7]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[7])
);
bbcud4f gpio_buf_6 (
.a(gpio_out_core[6]),
.en(gpio_outenb[6]),
.gndo(vss),
.gndr(vss),
.pad(gpio[6]),
.pden(gpio_pulldownb[6]),
.pi(dground),
.po(),
.puen(gpio_pullupb[6]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[6])
);
bbcud4f gpio_buf_5 (
.a(gpio_out_core[5]),
.en(gpio_outenb[5]),
.gndo(vss),
.gndr(vss),
.pad(gpio[5]),
.pden(gpio_pulldownb[5]),
.pi(dground),
.po(),
.puen(gpio_pullupb[5]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[5])
);
bbcud4f gpio_buf_4 (
.a(gpio_out_core[4]),
.en(gpio_outenb[4]),
.gndo(vss),
.gndr(vss),
.pad(gpio[4]),
.pden(gpio_pulldownb[4]),
.pi(dground),
.po(),
.puen(gpio_pullupb[4]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[4])
);
bbcud4f gpio_buf_3 (
.a(gpio_out_core[3]),
.en(gpio_outenb[3]),
.gndo(vss),
.gndr(vss),
.pad(gpio[3]),
.pden(gpio_pulldownb[3]),
.pi(dground),
.po(),
.puen(gpio_pullupb[3]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[3])
);
bbcud4f gpio_buf_2 (
.a(gpio_out_core[2]),
.en(gpio_outenb[2]),
.gndo(vss),
.gndr(vss),
.pad(gpio[2]),
.pden(gpio_pulldownb[2]),
.pi(dground),
.po(),
.puen(gpio_pullupb[2]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[2])
);
bbcud4f gpio_buf_1 (
.a(gpio_out_core[1]),
.en(gpio_outenb[1]),
.gndo(vss),
.gndr(vss),
.pad(gpio[1]),
.pden(gpio_pulldownb[1]),
.pi(dground),
.po(),
.puen(gpio_pullupb[1]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[1])
);
bbcud4f gpio_buf_0 (
.a(gpio_out_core[0]),
.en(gpio_outenb[0]),
.gndo(vss),
.gndr(vss),
.pad(gpio[0]),
.pden(gpio_pulldownb[0]),
.pi(dground),
.po(),
.puen(gpio_pullupb[0]),
.vdd(vdd1v8),
.vddr(vdd3v3),
.vddo(vdd3v3),
.y(gpio_in_core[0])
);
bt4f flash_csb_buf (
.pad(flash_csb),
.en(flash_csb_oeb),
.a(flash_csb_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f flash_clk_buf (
.pad(flash_clk),
.en(flash_clk_oeb),
.a(flash_clk_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
icf clk_ext_buf ( // external digital clock for pll bypass mode
.pad(xclk),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(clk_ext_core)
);
icf spi_master_sdi_buf (
.pad(spi_sdi),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(spi_sdi_core)
);
bt4f spi_master_csb_buf (
.pad(spi_csb),
.en(reset_lv),
.a(spi_csb_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f spi_master_sck_buf (
.pad(spi_sck),
.en(reset_lv),
.a(spi_sck_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f spi_master_sdo_buf (
.pad(spi_sdo),
.en(spi_sdoenb),
.a(spi_sdo_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* to avoid antenna violations, each digital pad with inputs a */
/* and en, and gpio pads with puen and pden, have a diode with */
/* minimum area on each of the input pins. */
dn #(
.area(2.025e-13)
) gpio_out_core_tie [15:0] (
.pos(vss),
.neg(gpio_out_core)
);
dn #(
.area(2.025e-13)
) gpio_outenb_tie [15:0] (
.pos(vss),
.neg(gpio_outenb)
);
dn #(
.area(2.025e-13)
) gpio_pulldownb_tie [15:0] (
.pos(vss),
.neg(gpio_pulldownb)
);
dn #(
.area(2.025e-13)
) gpio_pullupb_tie [15:0] (
.pos(vss),
.neg(gpio_pullupb)
);
dn #(
.area(2.025e-13)
) flash_io0_oeb_tie (
.pos(vss),
.neg(flash_io0_oeb)
);
dn #(
.area(2.025e-13)
) flash_io0_do_tie (
.pos(vss),
.neg(flash_io0_do)
);
dn #(
.area(2.025e-13)
) flash_io1_oeb_tie (
.pos(vss),
.neg(flash_io1_oeb)
);
dn #(
.area(2.025e-13)
) flash_io1_do_tie (
.pos(vss),
.neg(flash_io1_do)
);
dn #(
.area(2.025e-13)
) flash_io2_oeb_tie (
.pos(vss),
.neg(flash_io2_oeb)
);
dn #(
.area(2.025e-13)
) flash_io2_do_tie (
.pos(vss),
.neg(flash_io2_do)
);
dn #(
.area(2.025e-13)
) flash_io3_oeb_tie (
.pos(vss),
.neg(flash_io3_oeb)
);
dn #(
.area(2.025e-13)
) flash_io3_do_tie (
.pos(vss),
.neg(flash_io3_do)
);
dn #(
.area(2.025e-13)
) reset_lv_tie [2:0] (
.pos(vss),
.neg(reset_lv)
);
dn #(
.area(2.025e-13)
) ser_tx_core_tie (
.pos(vss),
.neg(ser_tx_core)
);
dn #(
.area(2.025e-13)
) i2c_scl_o_tie (
.pos(vss),
.neg(i2c_scl_o)
);
dn #(
.area(2.025e-13)
) i2c_scl_oeb_tie (
.pos(vss),
.neg(i2c_scl_oeb)
);
dn #(
.area(2.025e-13)
) i2c_sda_o_tie (
.pos(vss),
.neg(i2c_sda_o)
);
dn #(
.area(2.025e-13)
) i2c_sda_oeb_tie (
.pos(vss),
.neg(i2c_sda_oeb)
);
dn #(
.area(2.025e-13)
) flash_csb_oeb_tie (
.pos(vss),
.neg(flash_csb_oeb)
);
dn #(
.area(2.025e-13)
) flash_csb_core_tie (
.pos(vss),
.neg(flash_csb_core)
);
dn #(
.area(2.025e-13)
) flash_clk_oeb_tie (
.pos(vss),
.neg(flash_clk_oeb)
);
dn #(
.area(2.025e-13)
) flash_clk_core_tie (
.pos(vss),
.neg(flash_clk_core)
);
dn #(
.area(2.025e-13)
) spi_csb_core_tie (
.pos(vss),
.neg(spi_csb_core)
);
dn #(
.area(2.025e-13)
) spi_sck_core_tie (
.pos(vss),
.neg(spi_sck_core)
);
dn #(
.area(2.025e-13)
) spi_sdoenb_tie (
.pos(vss),
.neg(spi_sdoenb)
);
dn #(
.area(2.025e-13)
) spi_sdo_core_tie (
.pos(vss),
.neg(spi_sdo_core)
);
/* implement mim capacitors. layout uses 20x20um devices, so a=400um^2, p=80um */
cmm5t #(
.a(4e-10),
.p(8e-05)
) cap_area_fill_0 [468:0] (
.top(vdd1v8),
.bottom(vss),
.subs(vss)
);
cmm5t #(
.a(4e-10),
.p(8e-05)
) cap_area_fill_1 [276:0] (
.top(vdd3v3),
.bottom(vss),
.subs(vss)
);
/* each cap area has an associated tie-down diode */
dn3 #(
.area(2.25e-12)
) vdd3v3_tie [2:0] (
.pos(vss),
.neg(vdd3v3)
);
dn #(
.area(2.25e-12)
) vdd1v8_tie [4:0] (
.pos(vss),
.neg(vdd1v8)
);
wire [3:0] ram_wenb;
// wire [11:0] ram_addr;
wire [13:0] ram_addr;
wire [31:0] ram_wdata;
wire [31:0] ram_rdata;
wire [7:0] nvram_addr;
wire [31:0] nvram_wdata;
wire [31:0] nvram_rdata;
// nvram test mode from housekeeping spi
wire [3:0] tm_nvcp;
wire [3:0] tm_nvcp_lv;
/* note: hardwired digital 0 disallowed in structural netlist. */
/* must generate from tie-low standard cell. */
logic0_3v ground_digital [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(dground)
);
logic1 vdd_digital (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.q(dvdd)
);
/* sck_core is also input to ravenna_soc but needs to be shifted to 1.8v */
/* level shift down */
bu_3vx2 sck_core_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(sck_core),
.q(sck_core_lv)
);
/* due to lack of any spi configuration behavior on the 1st generation */
/* raven chip, the spi_config is just grounded. however, this requires */
/* tie-low inputs. */
logic0_3v spi_config_zero [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(spi_config)
);
/* spi internal registers to be read from memory mapped i/o must also */
/* be shifted down. those that are sent to the pll already have */
/* shifted versions. */
bu_3vx2 spi_config_level [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_config),
.q(spi_config_lv)
);
bu_3vx2 spi_xtal_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_xtal_ena),
.q(spi_xtal_ena_lv)
);
bu_3vx2 spi_reg_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_reg_ena),
.q(spi_reg_ena_lv)
);
/* this is a spare level shift buffer */
bu_3vx2 spare_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(dground),
.q(spare_dg)
);
bu_3vx2 spi_mfgr_id_level [11:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_mfgr_id),
.q(spi_mfgr_id_lv)
);
bu_3vx2 spi_prod_id_level [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_prod_id),
.q(spi_prod_id_lv)
);
bu_3vx2 spi_mask_rev_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_mask_rev),
.q(spi_mask_rev_lv)
);
bu_3vx2 spi_reset_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_reset),
.q(spi_reset_lv)
);
bu_3vx2 spi_pll_bypass_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_bypass),
.q(spi_pll_bypass_lv)
);
ravenna_soc soc (
`ifdef lvs
.gnd (vss ),
.vdd (vdd1v8 ),
`endif
.pll_clk (pll_clk ),
.ext_clk (clk_ext_core),
.ext_clk_sel (spi_pll_bypass_lv),
.reset (reset_lv ),
.ext_reset (spi_reset_lv ),
.pass_thru (pass_thru_lv),
.pass_thru_csb (pass_thru_csb_lv),
.pass_thru_sck (pass_thru_sck_lv),
.pass_thru_sdi (pass_thru_sdi_lv),
.pass_thru_sdo (pass_thru_sdo),
.ram_wenb (ram_wenb ),
.ram_addr (ram_addr ),
.ram_wdata (ram_wdata ),
.ram_rdata (ram_rdata ),
.nvram_ena (nvram_ena ),
.nvram_wen (nvram_wen ),
.nvram_addr (nvram_addr ),
.nvram_wdata (nvram_wdata ),
.nvram_rdata (nvram_rdata ),
.nvram_hs (nvram_hs ),
.nvram_hr (nvram_hr ),
.nvram_mem_all (nvram_mem_all ),
.nvram_mem_sel (nvram_mem_sel ),
.nvram_clk (nvram_clk ),
.nvram_rdy (nvram_rdy ),
.gpio_out (gpio_out_core),
.gpio_in (gpio_in_core),
.gpio_pullupb (gpio_pullupb),
.gpio_pulldownb (gpio_pulldownb),
.gpio_outenb (gpio_outenb),
.adc0_ena (adc0_ena),
.adc0_convert (adc0_convert),
.adc0_data (adc0_data),
.adc0_done (adc0_done),
.adc0_clk (adc0_clk),
.adc0_inputsrc (adc0_inputsrc),
.adc1_ena (adc1_ena),
.adc1_convert (adc1_convert),
.adc1_data (adc1_data),
.adc1_done (adc1_done),
.adc1_clk (adc1_clk),
.adc1_inputsrc (adc1_inputsrc),
.dac_ena (dac_ena),
.dac_value (dac_value),
.analog_out_sel (analog_out_sel),
.opamp_ena (opamp_ena),
.opamp_bias_ena (opamp_bias_ena),
.bg_ena (bg_ena),
.comp_ena (comp_ena),
.comp_ninputsrc (comp_ninputsrc),
.comp_pinputsrc (comp_pinputsrc),
.rcosc_ena (rcosc_ena),
.overtemp_ena (overtemp_ena),
.overtemp (overtemp_lv),
.rcosc_in (rcosc_out_lv),
.xtal_in (xtal_div8),
.comp_in (comp_out_lv),
.spi_sck (sck_core_lv),
.spi_ro_config (spi_config_lv),
.spi_ro_xtal_ena (spi_xtal_ena_lv),
.spi_ro_reg_ena (spi_reg_ena_lv),
.spi_ro_pll_cp_ena (spi_pll_cp_ena_lv),
.spi_ro_pll_vco_ena (spi_pll_vco_ena_lv),
.spi_ro_pll_bias_ena (spi_pll_bias_ena_lv),
.spi_ro_pll_trim (spi_pll_trim_lv),
.spi_ro_mfgr_id (spi_mfgr_id_lv),
.spi_ro_prod_id (spi_prod_id_lv),
.spi_ro_mask_rev (spi_mask_rev_lv),
.ser_tx (ser_tx_core ),
.ser_rx (ser_rx_core ),
.scl_pad_i (i2c_scl_i),
.scl_pad_o (i2c_scl_o),
.scl_padoeb (i2c_scl_oeb),
.sda_pad_i (i2c_sda_i),
.sda_pad_o (i2c_sda_o),
.sda_padoeb (i2c_sda_oeb),
.spi_master_sdi (spi_sdi_core),
.spi_master_csb (spi_csb_core),
.spi_master_sck (spi_sck_core),
.spi_master_sdo (spi_sdo_core),
.spi_master_sdoenb (spi_sdoenb),
.irq_pin (irq_pin_core),
.irq_spi (spi_irq_lv),
.trap (spi_trap),
.flash_csb (flash_csb_core),
.flash_clk (flash_clk_core),
.flash_csb_oeb (flash_csb_oeb),
.flash_clk_oeb (flash_clk_oeb),
.flash_io0_oeb (flash_io0_oeb),
.flash_io1_oeb (flash_io1_oeb),
.flash_io2_oeb (flash_io2_oeb),
.flash_io3_oeb (flash_io3_oeb),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
/* level shift up */
ls_3vx2 spi_trap_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(spi_trap),
.q(spi_trap_3v)
);
ls_3vx2 pass_thru_sdo_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(pass_thru_sdo),
.q(pass_thru_sdo_3v)
);
/* metal programming for mask revision */
wire [3:0] pground;
wire [3:0] ppower;
logic0_3v prog_ground [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(pground)
);
logic1_3v prog_power [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(ppower)
);
/* standalone spi (3v)*/
/* operates at 3v so that it can control the xtal oscillator, pll, */
/* and 1.8v regulator, which cannot be changed from the cpu */
/* without potentially killing it. */
ravenna_spi spi (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.rst(reset),
.sck(sck_core),
.sdi(sdi_core),
.csb(csb_core),
.sdo(sdo_core),
.sdo_enb(sdo_enb),
.xtal_ena(spi_xtal_ena),
.reg_ena(spi_reg_ena),
.pll_vco_ena(spi_pll_vco_ena),
.pll_cp_ena(spi_pll_cp_ena),
.pll_vco_in(spi_pll_vco_in),
.pll_bias_ena(spi_pll_bias_ena),
.pll_trim(spi_pll_trim),
.pll_bypass(spi_pll_bypass),
.tm_nvcp(tm_nvcp),
.irq(spi_irq),
.reset(spi_reset),
.trap(spi_trap_3v),
.pass_thru_reset (pass_thru),
.pass_thru_csb (pass_thru_csb),
.pass_thru_sck (pass_thru_sck),
.pass_thru_sdi (pass_thru_sdi),
.pass_thru_sdo (pass_thru_sdo_3v),
.mask_rev_in(pground), // metal programmed
.mfgr_id(spi_mfgr_id),
.prod_id(spi_prod_id),
.mask_rev(spi_mask_rev)
);
/* level shift down. unfortunately, pll is in 1.8v only or */
/* else this would be easier. */
bu_3vx2 pass_thru_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru),
.q(pass_thru_lv)
);
bu_3vx2 pass_thru_csb_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_csb),
.q(pass_thru_csb_lv)
);
bu_3vx2 pass_thru_sdi_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_sdi),
.q(pass_thru_sdi_lv)
);
bu_3vx2 pass_thru_sck_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_sck),
.q(pass_thru_sck_lv)
);
bu_3vx2 pll_vco_in_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_vco_in),
.q(spi_pll_vco_in_lv)
);
bu_3vx2 pll_vco_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_vco_ena),
.q(spi_pll_vco_ena_lv)
);
bu_3vx2 pll_cp_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_cp_ena),
.q(spi_pll_cp_ena_lv)
);
bu_3vx2 pll_trim_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_trim),
.q(spi_pll_trim_lv)
);
bu_3vx2 pll_bias_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_bias_ena),
.q(spi_pll_bias_ena_lv)
);
bu_3vx2 spi_irq_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_irq),
.q(spi_irq_lv)
);
/* nvram module and charge pump */
/* list of wires passed between nvram and charge pump */
wire nvram_busynvc;
wire [15:0] nvram_trim;
wire nvram_clki;
wire nvram_vsestart;
wire nvram_rclt;
wire nvram_mem1_ent;
wire nvram_mem2_ent;
wire nvram_clk4;
wire nvram_vse1;
wire nvram_vse2;
wire nvram_vsebusy;
wire nvram_vcore;
wire [3:0] nvram_tm_nvcpi;
xnvr_136x32p128_vd01 nvram (
`ifdef lvs
.vdd18m(vdd1v8),
.vssm(vss),
`endif
.busynvc(nvram_busynvc),
.clki(nvram_clki),
.dout(nvram_rdata),
.dso(),
.mem1_ent(nvram_mem1_ent),
.mem2_ent(nvram_mem2_ent),
.rclt(nvram_rclt),
.rdy(nvram_rdy),
.tm_nvcpi(nvram_tm_nvcpi),
.trim(nvram_trim),
.vsestart(nvram_vsestart),
.a(nvram_addr),
.ce(nvram_ena),
.clk(nvram_clk),
.clk4(nvram_clk4),
.din(nvram_wdata),
.drstn(dvdd),
.dsclk(dground),
.dsi(dground),
.dup(dground),
.hr(nvram_hr),
.hs(nvram_hs),
.mem_allc(nvram_mem_all),
.mem_sel(nvram_mem_sel),
.pein(dground),
.por(reset_lv),
.tm_nvcp(tm_nvcp_lv),
.vcore(nvram_vcore),
.vse1(nvram_vse1),
.vse2(nvram_vse2),
.vsebusy(nvram_vsebusy),
.we(nvram_wen)
);
xcpf_136x32dp128_vd03 nvram_cp (
`ifdef lvs
.vdd18m(vdd1v8),
.vdd33m(vdd3v3),
.vssm(vss),
`endif
.clk4(nvram_clk4),
.clk4m(),
.vcore(nvram_vcore),
.vse1(nvram_vse1),
.vse2(nvram_vse2),
.vsebusy(nvram_vsebusy),
.busynvc(nvram_busynvc),
.clki(nvram_clki),
.mem1_ent(nvram_mem1_ent),
.mem2_ent(nvram_mem2_ent),
.nvref_ext(nvref_ext),
.por(reset_lv),
.rclt(nvram_rclt),
.tm_nvcpi(nvram_tm_nvcpi),
.trim(nvram_trim),
.vsestart(nvram_vsestart)
);
/* level shift down */
bu_3vx2 tm_nvcp_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(tm_nvcp),
.q(tm_nvcp_lv)
);
/* ram modules (32 bits x 4k words) */
wire [31:0] ram_wenb_bits;
/* split the four byte-wide write-enable lines into the x-fab sram bit-wide write-enable lines */
assign ram_wenb_bits[31:24] = {ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3]};
assign ram_wenb_bits[23:16] = {ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2]};
assign ram_wenb_bits[15:8] = {ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1]};
assign ram_wenb_bits[7:0] = {ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0]};
// xspramblp_4096x32_m8p xfab_mem0 (
xspramblp_16384x32_m8p xfab_mem0 (
`ifdef lvs
.vssm(vss),
.vdd18m(vdd1v8),
`endif
.q(ram_rdata),
.d(ram_wdata),
.a(ram_addr),
.clk(pll_clk),
.cen(reset_lv), // sram enable
.wen(ram_wenb_bits), // one bit per byte
.rdy() // unused
);
/* analog components (multiplexers) */
wire real adc0_input;
wire real adc1_input;
wire real comp_ninput;
wire real comp_pinput;
wire real opamp_input;
wire real dac_out;
wire real bandgap_out;
amux4_3v adc0_input_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(adc0_in),
.ain2(vdd1v8),
.ain3(dac_out),
.ain4(vss),
.aout(adc0_input),
.sel(adc0_inputsrc)
);
amux4_3v adc1_input_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(adc1_in),
.ain2(vdd3v3),
.ain3(bandgap_out),
.ain4(comp_inp),
.aout(adc1_input),
.sel(adc1_inputsrc)
);
amux4_3v comp_ninput_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(comp_inn),
.ain2(dac_out),
.ain3(bandgap_out),
.ain4(vdd1v8),
.aout(comp_ninput),
.sel(comp_ninputsrc)
);
amux4_3v comp_pinput_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(comp_inp),
.ain2(dac_out),
.ain3(bandgap_out),
.ain4(vdd1v8),
.aout(comp_pinput),
.sel(comp_pinputsrc)
);
amux2_3v analog_out_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(dac_out),
.ain2(bandgap_out),
.aout(opamp_input),
.sel(analog_out_sel)
);
/* adc 0 */
aadcc01_3v3 adc0 (
.vdd(vdd1v8),
.vin(adc0_input),
.clk(adc0_clk),
.vrefh(adc_high),
.en(adc0_ena),
.vssa(vss),
.vdda(vdd3v3),
.vrefl(adc_low),
.start(adc0_convert),
.eoc(adc0_done),
.d(adc0_data),
.vss(vss)
);
/* adc 1 */
aadcc01_3v3 adc1 (
.vdd(vdd1v8),
.vin(adc1_input),
.clk(adc1_clk),
.vrefh(adc_high),
.en(adc1_ena),
.vssa(vss),
.vdda(vdd3v3),
.vrefl(adc_low),
.start(adc1_convert),
.eoc(adc1_done),
.d(adc1_data),
.vss(vss)
);
/* dac */
adacc01_3v3 dac (
.out(dac_out),
.d(dac_value),
.en(dac_ena),
.vdd(vdd1v8),
.vdda(vdd3v3),
.vrefh(adc_high),
.vrefl(adc_low),
.vss(vss),
.vssa(vss)
);
wire real bias3u;
/* opamp (analog output buffer) */
aopac01_3v3 opamp (
.out(analog_out),
.en(opamp_ena_3v),
.ib(bias3u),
.inn(analog_out),
.inp(opamp_input),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift up */
ls_3vx2 opamp_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(opamp_ena),
.q(opamp_ena_3v)
);
ls_3vx2 opamp_bias_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(opamp_bias_ena),
.q(opamp_bias_ena_3v)
);
/* biasing for op-amp */
acsoc02_3v3 opamp_bias (
.en(opamp_bias_ena_3v),
.vdda(vdd3v3),
.vssa(vss),
.cs_8u(),
.cs_4u(),
.cs_2u(bias3u),
.cs_1u(bias3u)
);
/* level shift up */
ls_3vx2 bg_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(bg_ena),
.q(bg_ena_3v)
);
/* bandgap */
abgpc01_3v3 bandgap (
.en(bg_ena_3v),
.vbgp(bandgap_out),
.vssa(vss),
.vdda(vdd3v3),
.vbgvtn()
);
wire real bias400n;
/* comparator */
acmpc01_3v3 comparator (
.out(comp_out),
.en(comp_ena_3v),
.ibn(bias400n),
.inn(comp_ninput), // multiplexed
.inp(comp_pinput), // multiplexed
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 comp_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(comp_out),
.q(comp_out_lv)
);
/* level shift up */
ls_3vx2 comp_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(comp_ena),
.q(comp_ena_3v)
);
/* bias for comparator */
acsoc01_3v3 comp_bias (
.en(comp_ena_3v),
.vssa(vss),
.vdda(vdd3v3),
.cs0_200n(bias400n),
.cs1_200n(bias400n),
.cs2_200n(),
.cs3_200n()
);
/* crystal oscillator (5-12.5 mhz) */
axtoc02_3v3 xtal (
.clk(xtal_out),
.xi(xi),
.xo(xo),
.en(spi_xtal_ena),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* level shift down (because xtal osc is 3v but pll is 1.8v) */
bu_3vx2 xtal_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(xtal_out),
.q(xtal_out_buf)
);
/* buffering of xtal_out clock */
bux4 bux4_1 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(xtal_out_buf),
.q(xtal_out_lv)
);
/* soc core uses xtal_in to drive adc which has a max */
/* clock rate of 2mhz. since crystal clock is */
/* typically 10 to 12.5mhz, divide it by 8. */
dfrx2 clock_div2 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div2_buf),
.c(xtal_out_lv),
.qn(xtal_div2_buf),
.q(xtal_div2)
);
dfrx2 clock_div4 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div4_buf),
.c(xtal_div2),
.qn(xtal_div4_buf),
.q(xtal_div4)
);
dfrx2 clock_div8 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div8_buf),
.c(xtal_div4),
.qn(xtal_div8_buf),
.q(xtal_div8)
);
wire real bias10u, bias5u, pll_vco_in;
/* multiplexer for connecting vco_in */
/* note that this multiplexer is 3.3v. it is the */
/* responsibility of the hardware connected to the */
/* comp_inp pin to limit vco_in to 1.2v max. */
amux2_3v vco_in_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(vss),
.ain2(comp_inp),
.aout(pll_vco_in),
.sel(spi_pll_vco_in_lv)
);
/* 8x clock multiplier pll (note: ip from a_cells_1v8) */
apllc03_1v8 pll (
.vssd(vss),
.en_vco(spi_pll_vco_ena_lv),
.en_cp(spi_pll_cp_ena_lv),
.b_vco(bias5u),
.b_cp(bias10u),
.vssa(vss),
.vddd(vdd1v8),
.vdda(vdd1v8),
.vco_in(pll_vco_in),
.clk(clk), // output (fast) clock
.ref(xtal_out_lv), // input (slow) clock
.b(spi_pll_trim_lv) // 4-bit trim
);
/* buffering of pll clock */
bux4 bux4_0 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(clk),
.q(clk_buf)
);
bux12 bux12_1 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(clk_buf),
.q(pll_clk)
);
/* biasing for pll */
acsoc04_1v8 pll_bias (
.en(spi_pll_bias_ena_lv),
.vdda(vdd1v8),
.vssa(vss),
.cs3_8u(bias10u),
.cs2_4u(bias5u),
.cs1_2u(bias10u),
.cs0_1u(bias5u)
);
/* level shift up */
ls_3vx2 rcosc_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(rcosc_ena),
.q(rcosc_ena_3v)
);
/* rc oscillator */
arcoc01_3v3 rcosc (
.clk(rcosc_out),
.en(rcosc_ena_3v),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 rcosc_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(rcosc_out),
.q(rcosc_out_lv)
);
/* buffering for regulator enables. this is mostly to */
/* isolate an lvs error, but no harm comes of individually */
/* buffering each regulator's enable lines. */
bu_3vx2 reg_ena_buf0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg0_ena)
);
bu_3vx2 reg_ena_buf1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg1_ena)
);
in_3vx2 reg_enb_buf0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg0_enb)
);
in_3vx2 reg_enb_buf1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg1_enb)
);
/* reg1_ena/b has antenna taps due to the length of the wires */
antennacellnp2_3v antennacellnp2_3v_0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(reg1_ena)
);
antennacellnp2_3v antennacellnp2_3v_1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(reg1_enb)
);
/* note: iverilog does not like two devices connected in */
/* parallel to one real-valued driver, so one device is */
/* removed for simulation (hack solution). */
/* 1.8v regulator (x2) */
aregc01_3v3 regulator1 (
.out(vdd1v8),
.vin3(vdd3v3),
.gndo(vss),
.en(reg0_ena),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3),
.vdd(vdd1v8),
.enb(reg0_enb)
);
`ifdef lvs
aregc01_3v3 regulator2 (
.out(vdd1v8),
.vin3(vdd3v3),
.gndo(vss),
.en(reg1_ena),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3),
.vdd(vdd1v8),
.enb(reg1_enb)
);
`endif
/* power-on-reset */
aporc02_3v3 por (
.por(reset),
.porb(resetn),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 por_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(reset),
.q(reset_lv)
);
/* level shift up */
ls_3vx2 temp_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(overtemp_ena),
.q(overtemp_ena_3v)
);
/* over-temperature alarm */
atmpc01_3v3 temp (
.ovt(overtemp),
.en(overtemp_ena_3v),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 overtemp_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(overtemp),
.q(overtemp_lv)
);
endmodule // ravenna
|
/*
* Titor - System - PS/2 controller wrapper
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_WRAPPER_PS2
`else
`define INC_WRAPPER_PS2
`timescale 1 ns / 100 ps
module PS2MemoryWrapper(
dout,
din,
address,
size,
read_write,
enable,
interrupt,
ps2_clock,
ps2_data,
reset,
clk
);
`include "definition/Definition.v"
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg interrupt;
inout ps2_clock;
inout ps2_data;
wire [BYTE-1:0] rx_data;
input reset;
input clk;
reg [WORD-1:0] key_normal;
wire rx_done;
// Memory interface
always @(posedge clk) begin
if(reset) begin
dout <= 0;
end
else if((address==0) && (enable==ENABLE) && (read_write==READ)) begin
dout <= key_normal;
end
end
// Local definitions
localparam UNSPECIAL = 0;
localparam SPECIAL = 224;
localparam EXTRA = 255;
localparam BREAK = 240;
// Key disambiguation
reg ignore;
reg [WORD-1:0] specialc;
reg breakc;
// Key translation
reg [WORD-1:0] try_normalized;
reg try_interrupt;
reg try_ignore;
always @(posedge clk) begin
if(reset) begin
ignore <= 0;
specialc <= UNSPECIAL;
breakc <= 0;
end
else begin
if(!rx_done) begin
ignore <= ignore;
specialc <= specialc;
breakc <= breakc;
end
else begin
case(rx_data)
SPECIAL: begin
ignore <= ignore;
specialc <= SPECIAL;
breakc <= 0;
end
EXTRA: begin
ignore <= ignore;
specialc <= EXTRA;
breakc <= 0;
end
BREAK: begin
ignore <= ignore;
specialc <= specialc;
breakc <= 1;
end
default: begin
ignore <= try_ignore;
specialc <= UNSPECIAL;
breakc <= 0;
end
endcase
end
end
end
// In the lookup table determine the normalized key
always @(*) begin
if(!rx_done) begin
try_normalized <= 0;
try_interrupt <= 0;
try_ignore <= 0;
end
else begin
`include "meta-include/Scan-Code.meta.v"
end
end
// Combine all the information and send an interrupt if necessary
always @(posedge clk) begin
if(reset) begin
interrupt <= 0;
key_normal <= 0;
end
else if(try_interrupt) begin
interrupt <= !ignore;
key_normal <= (breakc<<(WORD-1)) | try_normalized;
end
else begin
interrupt <= 0;
key_normal <= key_normal;
end
end
PS2 hardware(
.ps2_clock(ps2_clock),
.ps2_data(ps2_data),
.rx_data(rx_data),
.rx_done(rx_done),
.reset(reset),
.clk(clk)
);
endmodule
`endif
|
/*copyright 2018-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`define sout tb.uart0_sout
`define sin tb.uart0_sin
module uart_mnt();
//#############################################
// create baud_clk
//#############################################
parameter fcpu = 1000000000/`clk_period;
parameter baud = 19200;
parameter cycle_cunt=fcpu/(baud*16) - 1;
reg[31:0] div_counter;
always @(posedge `clk or negedge `rst_b)
begin
if(!`rst_b)
begin
div_counter[31:0]<=cycle_cunt;
end
else if(div_counter[31:0]==32'b0)
begin
div_counter[31:0]<=cycle_cunt;
end
else
begin
div_counter[31:0]<=div_counter[31:0] - 1'b1;
end
end
assign baud_clk=(div_counter[31:0]>=(cycle_cunt/2))?0:1;
//#############################################
// receive data
//#############################################
reg sout_flop;
reg trig_count_en;
reg [4:0] trig_count;
reg shift_en;
reg [3:0] shift_count;
reg [3:0] capture_time;
reg[7:0] pack_data;
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
sout_flop<=1'b0;
else
sout_flop<=`sout;
end
assign trig = sout_flop && !`sout && !shift_en;
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
trig_count_en<=1'b0;
else if(trig)
trig_count_en<=1'b1;
else if(shift_en)
trig_count_en<=1'b0;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
trig_count[4:0]<=5'b0;
else if(!trig_count_en)
trig_count[4:0]<=5'b0;
else if(trig_count_en)
trig_count[4:0]<= trig_count[4:0] + 1;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
shift_en<=1'b0;
else if(trig_count[4:0]==22)
shift_en<=1'b1;
else if(capture_time[3:0]==8)
shift_en<=1'b0;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
shift_count[3:0]<=4'b0;
else if(trig)
shift_count[3:0]<=4'b0;
else if(shift_en)
shift_count[3:0]<= shift_count[3:0] + 1;
end
assign capture_en = shift_en && (shift_count[3:0]==0);
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
capture_time[3:0]<=4'b0;
else if(trig)
capture_time[3:0]<=4'b0;
else if(capture_en)
capture_time[3:0]<= capture_time[3:0] + 1;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
begin
pack_data[7:0]<=8'b0;
end
else if (capture_en)
begin
pack_data[7:0]<={`sout,pack_data[7:1]};
end
else
begin
pack_data[7:0]<=pack_data[7:0];
end
end
assign print_en = (capture_time[3:0]==8) && shift_en;
//#############################################
// print log
//#############################################
integer output_file;
initial
begin
output_file=$fopen("uart_output.inf","w");
end
always @(posedge baud_clk )
begin
if(print_en)
begin
$fwrite(output_file,"%c",pack_data[7:0]);
$write("\033[0;31m%c\033[0m",pack_data[7:0]);
end
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_streaming #(
parameter PURPOSE = 0,
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// JTAG Signals
input wire tck,
input wire tdi,
output reg tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire reset_n,
// Source Signals
output wire [7:0] source_data,
output wire source_valid,
// Sink Signals
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
// Clock Debug Signals
input wire clock_to_sample,
input wire reset_to_sample,
// Resetrequest signal
output reg resetrequest,
// Debug reset and management channel
output wire debug_reset,
output reg mgmt_valid,
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output reg mgmt_data
);
// function to calculate log2, floored.
function integer flog2;
input [31:0] Depth;
integer i;
begin
i = Depth;
if ( i <= 0 ) flog2 = 0;
else begin
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// IR values determine the operating modes
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
// Operating Modes:
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
// Loopback - To become a JTAG loopback with a bypass register
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
// Control - To set the offset of bit-padding and to do a reset request
// Mgmt - Send management commands (resets mostly) to agents
localparam IRWIDTH = 3;
// State machine encoding for write_state
localparam ST_BYPASS = 'h0;
localparam ST_HEADER_1 = 'h1;
localparam ST_HEADER_2 = 'h2;
localparam ST_WRITE_DATA = 'h3;
// State machine encoding for read_state
localparam ST_HEADER = 'h0;
localparam ST_PADDED = 'h1;
localparam ST_READ_DATA = 'h2;
reg [1:0] write_state = ST_BYPASS;
reg [1:0] read_state = ST_HEADER;
reg [ 7:0] dr_data_in = 'b0;
reg [ 7:0] dr_data_out = 'b0;
reg dr_loopback = 'b0;
reg [ 2:0] dr_debug = 'b0;
reg [10:0] dr_info = 'b0;
reg [ 8:0] dr_control = 'b0;
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
reg [ 8:0] padded_bit_counter = 'b0;
reg [ 7:0] bypass_bit_counter = 'b0;
reg [ 2:0] write_data_bit_counter = 'b0;
reg [ 2:0] read_data_bit_counter = 'b0;
reg [ 3:0] header_in_bit_counter = 'b0;
reg [ 3:0] header_out_bit_counter = 'b0;
reg [18:0] scan_length_byte_counter = 'b0;
reg [18:0] valid_write_data_length_byte_counter = 'b0;
reg write_data_valid = 'b0;
reg read_data_valid = 'b0;
reg read_data_all_valid = 'b0;
reg decode_header_1 = 'b0;
reg decode_header_2 = 'b0;
wire write_data_byte_aligned;
wire read_data_byte_aligned;
wire padded_bit_byte_aligned;
wire bytestream_end;
assign write_data_byte_aligned = (write_data_bit_counter == 1);
assign read_data_byte_aligned = (read_data_bit_counter == 1);
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
assign bytestream_end = (scan_length_byte_counter == 'b0);
reg [ 7:0] offset = 'b0;
reg [15:0] header_in = 'b0;
reg [9:0] scan_length = 'b0;
reg [2:0] read_data_length = 'b0;
reg [2:0] write_data_length = 'b0;
wire [7:0] idle_inserter_sink_data;
wire idle_inserter_sink_valid;
wire idle_inserter_sink_ready;
wire [7:0] idle_inserter_source_data;
reg idle_inserter_source_ready = 'b0;
reg [7:0] idle_remover_sink_data = 'b0;
reg idle_remover_sink_valid = 'b0;
wire [7:0] idle_remover_source_data;
wire idle_remover_source_valid;
assign source_data = idle_remover_source_data;
assign source_valid = idle_remover_source_valid;
assign sink_ready = idle_inserter_sink_ready;
assign idle_inserter_sink_data = sink_data;
assign idle_inserter_sink_valid = sink_valid;
reg clock_sensor = 'b0;
reg clock_to_sample_div2 = 'b0;
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
wire data_available;
assign data_available = sink_valid;
wire [18:0] decoded_scan_length;
wire [18:0] decoded_write_data_length;
wire [18:0] decoded_read_data_length;
assign decoded_scan_length = { scan_length, {8{1'b1}} };
// +-------------------+----------------+---------------------+
// | scan_length | Length (bytes) | decoded_scan_length |
// +-------------------+----------------+---------------------+
// | 0x0 | 256 | 0x0ff (255) |
// | 0x1 | 512 | 0x1ff (511) |
// | 0x2 | 768 | 0x2ff (767) |
// | . | . | . |
// | 0x3ff | 256k | 0x3ff (256k-1) |
// +-------------------+----------------+---------------------+
// TODO: use look up table to save LEs?
// Decoded value is correct except for 0x7
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
// +-------------------+---------------+---------------------------+
// | read_data_length | Length | decoded_read_data_length |
// | write_data_length | (bytes) | decoded_write_data_length |
// +-------------------+---------------+---------------------------+
// | 0x0 | 0 | 0x0000 (0) |
// | 0x1 | 256 | 0x0100 (256) |
// | 0x2 | 512 | 0x0200 (512) |
// | 0x3 | 1k | 0x0400 (1024) |
// | 0x4 | 2k | 0x0800 (2048) |
// | 0x5 | 4k | 0x1000 (4096) |
// | 0x6 | 8k | 0x2000 (8192) |
// | 0x7 | scan_length | invalid |
// +-------------------+---------------+---------------------------+
wire clock_sensor_sync;
wire reset_to_sample_sync;
wire clock_to_sample_div2_sync;
wire clock_sense_reset_n_sync;
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_sensor),
.dout(clock_sensor_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(reset_to_sample),
.dout(reset_to_sample_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_to_sample_div2),
.dout(clock_to_sample_div2_sync));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
.clk(clock_to_sample),
.reset_n(clock_sense_reset_n),
.din(1'b1),
.dout(clock_sense_reset_n_sync));
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
if (~clock_sense_reset_n_sync) begin
clock_sensor <= 1'b0;
end else begin
clock_sensor <= 1'b1;
end
end
always @ (posedge clock_to_sample) begin
clock_to_sample_div2 <= ~clock_to_sample_div2;
end
always @ (posedge tck) begin
idle_remover_sink_valid <= 1'b0;
idle_inserter_source_ready <= 1'b0;
// Data mode sourcing (write)
// offset(rounded 8) m-i i 16 offset
// +------------+-----------+------------------+--------+------------+
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
// +------------+-----------+------------------+--------+------------+
// Data mode DR data stream write format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
if (offset == 'b0) begin
write_state <= ST_HEADER_1;
end else begin
write_state <= ST_BYPASS;
end
// 8-bit bypass_bit_counter
bypass_bit_counter <= offset;
// 4-bit header_in_bit_counter
header_in_bit_counter <= 15;
// 3-bit write_data_bit_counter
write_data_bit_counter <= 0;
// Reset the registers
// TODO: not necessarily all, reduce LE
decode_header_1 <= 1'b0;
decode_header_2 <= 1'b0;
read_data_all_valid <= 1'b0;
valid_write_data_length_byte_counter <= 0;
end
if (virtual_state_sdr) begin
// Discard bypass bits, then decode the 16-bit header
// 3 3 10
// +-------------------+------------------+-------------+
// | write_data_length | read_data_length | scan_length |
// +-------------------+------------------+-------------+
// Header format
case (write_state)
ST_BYPASS: begin
// Discard the bypass bit
bypass_bit_counter <= bypass_bit_counter - 1'b1;
if (bypass_bit_counter == 1) begin
write_state <= ST_HEADER_1;
end
end
// Shift the scan_length and read_data_length
ST_HEADER_1: begin
// TODO: header_in can be shorter
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
if (header_in_bit_counter == 3) begin
read_data_length <= {tdi, header_in[15:14]};
scan_length <= header_in[13:4];
write_state <= ST_HEADER_2;
decode_header_1 <= 1'b1;
end
end
// Shift the write_data_length
ST_HEADER_2: begin
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
// Decode read_data_length and scan_length
if (decode_header_1) begin
decode_header_1 <= 1'b0;
// Set read_data_all_valid
if (read_data_length == 3'b111) begin
read_data_all_valid <= 1'b1;
end
// Load scan_length_byte_counter
scan_length_byte_counter <= decoded_scan_length;
end
if (header_in_bit_counter == 0) begin
write_data_length <= {tdi, header_in[15:14]};
write_state <= ST_WRITE_DATA;
decode_header_2 <= 1'b1;
end
end
// Shift the valid_write_data
ST_WRITE_DATA: begin
// Shift into dr_data_in
dr_data_in <= {tdi, dr_data_in[7:1]};
// Decode write_data_length
if (decode_header_2) begin
decode_header_2 <= 1'b0;
// Load valid_write_data_length_byte_counter
case (write_data_length)
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
3'b000: valid_write_data_length_byte_counter <= 'b0;
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
endcase
end
write_data_bit_counter <= write_data_bit_counter - 1'b1;
write_data_valid <= (valid_write_data_length_byte_counter != 0);
// Feed the data to the idle remover
if (write_data_byte_aligned && write_data_valid) begin
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
idle_remover_sink_valid <= 1'b1;
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
end
end
endcase
end
end
// Data mode sinking (read)
// i m-i offset(rounded 8) 16
// +-----------------+-----------+------------+--------+
// | valid_read_data | undefined | padded_bit | header | -> tdo
// +-----------------+-----------+------------+--------+
// Data mode DR data stream read format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
read_state <= ST_HEADER;
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
// 9-bit padded_bit_counter
if (|offset[2:0]) begin
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
padded_bit_counter[2:0] <= 3'b0;
end else begin
padded_bit_counter <= {1'b0, offset};
end
// 4-bit header_out_bit_counter
header_out_bit_counter <= 0;
// 3-bit read_data_bit_counter
read_data_bit_counter <= 0;
// Load the data_available bit into header
dr_data_out <= {{7{1'b0}}, data_available};
read_data_valid <= 0;
end
if (virtual_state_sdr) begin
// 10 1
// +-----------------------------------+----------------+
// | reserved | data_available |
// +-----------------------------------+----------------+
// Header format
dr_data_out <= {1'b0, dr_data_out[7:1]};
case (read_state)
// Shift the scan_length and read_data_length
ST_HEADER: begin
header_out_bit_counter <= header_out_bit_counter - 1'b1;
// Retrieve data from idle inserter for the next shift if no paddded bits
if (header_out_bit_counter == 2) begin
if (padded_bit_counter == 0) begin
idle_inserter_source_ready <= read_data_all_valid;
end
end
if (header_out_bit_counter == 1) begin
if (padded_bit_counter == 0) begin
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end else begin
read_state <= ST_PADDED;
padded_bit_counter <= padded_bit_counter - 1'b1;
idle_inserter_source_ready <= 1'b0;
dr_data_out <= 8'h4a;
end
end
end
ST_PADDED: begin
padded_bit_counter <= padded_bit_counter - 1'b1;
if (padded_bit_byte_aligned) begin
// Load idle character into data register
dr_data_out <= 8'h4a;
end
// Retrieve data from idle inserter for the next shift when padded bits finish
if (padded_bit_counter == 1) begin
idle_inserter_source_ready <= read_data_all_valid;
end
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end
end
ST_READ_DATA: begin
read_data_bit_counter <= read_data_bit_counter - 1'b1;
// Retrieve data from idle inserter just before read_data_byte_aligned
if (read_data_bit_counter == 2) begin
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
end
if (read_data_byte_aligned) begin
// Note that bytestream_end is driven by scan_length_byte_counter
if (~bytestream_end) begin
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
end
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
// Load idle character if bytestream has ended, else get data from the idle inserter
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
end
end
endcase
end
end
// Loopback mode
if (ir_in == LOOPBACK) begin
if (virtual_state_cdr) begin
dr_loopback <= 1'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_loopback
dr_loopback <= tdi;
end
end
// Debug mode
if (ir_in == DEBUG) begin
if (virtual_state_cdr) begin
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
end
if (virtual_state_udr) begin
clock_sense_reset_n <= 1'b0;
end else begin
clock_sense_reset_n <= 1'b1;
end
end
// Info mode
if (ir_in == INFO) begin
if (virtual_state_cdr) begin
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
end
if (virtual_state_sdr) begin
// Shift dr_info
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
end
end
// Control mode
if (ir_in == CONTROL) begin
if (virtual_state_cdr) begin
dr_control <= 'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_control
dr_control <= {tdi, dr_control[8:1]};
end
if (virtual_state_udr) begin
// Update resetrequest and offset
{resetrequest, offset} <= dr_control;
end
end
end
always @ * begin
if (virtual_state_sdr) begin
case (ir_in)
DATA: tdo <= dr_data_out[0];
LOOPBACK: tdo <= dr_loopback;
DEBUG: tdo <= dr_debug[0];
INFO: tdo <= dr_info[0];
CONTROL: tdo <= dr_control[0];
MGMT: tdo <= dr_mgmt[0];
default: tdo <= 1'b0;
endcase
end else begin
tdo <= 1'b0;
end
end
// Idle Remover
altera_avalon_st_idle_remover idle_remover (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (), // left disconnected
.in_valid (idle_remover_sink_valid),
.in_data (idle_remover_sink_data),
// Interface: ST out
.out_ready (1'b1), // downstream is expected to be always ready
.out_valid (idle_remover_source_valid),
.out_data (idle_remover_source_data)
);
// Idle Inserter
altera_avalon_st_idle_inserter idle_inserter (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (idle_inserter_sink_ready),
.in_valid (idle_inserter_sink_valid),
.in_data (idle_inserter_sink_data),
// Interface: ST out
.out_ready (idle_inserter_source_ready),
.out_valid (),
.out_data (idle_inserter_source_data)
);
generate
if (MGMT_CHANNEL_WIDTH > 0)
begin : has_mgmt
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
reg mgmt_toggle = 1'b0;
wire mgmt_toggle_sync;
reg mgmt_toggle_prev;
always @ (posedge tck) begin
// Debug mode
if (ir_in == MGMT) begin
if (virtual_state_cdr) begin
dr_mgmt <= 'b0;
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
end
if (virtual_state_udr) begin
mgmt_out <= dr_mgmt;
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
end
end
end
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
.dout(debug_reset));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_toggle),
.dout(mgmt_toggle_sync));
always @ (posedge clock_to_sample or posedge debug_reset) begin
if (debug_reset) begin
mgmt_valid <= 1'b0;
mgmt_toggle_prev <= 1'b0;
end else begin
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
mgmt_valid <= 1'b1;
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
mgmt_data <= mgmt_out[0];
end else begin
mgmt_valid <= 1'b0;
end
mgmt_toggle_prev <= mgmt_toggle_sync;
end
end
end
else
begin : no_mgmt
always @ (posedge tck) begin
dr_mgmt[0] <= 1'b0;
end
assign debug_reset = 1'b0;
always @ (posedge clock_to_sample) begin
mgmt_valid <= 1'b0;
mgmt_data <= 'b0;
mgmt_channel <= 'b0;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/*
* simple brainfuck cpu in verilog.
* copyright (c) 2011 sergey gridasov <grindars@gmail.com>
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, either version 3 of the license, or
* (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
module brainfuckwrapper(
clk, reset,
cin, cout, crda, cack, cwr, crdy
);
parameter fast_loopend = 1;
parameter ia_width = 11;
parameter da_width = 11;
parameter dd_width = 8;
parameter stack_depth_pow = 7;
input clk;
input reset;
input [7:0] cin;
output [7:0] cout;
input crda;
output cack;
output cwr;
input crdy;
wire [ia_width - 1:0] ia;
wire [7:0] idin;
wire ien;
// data bus
wire [da_width - 1:0] da;
wire [dd_width - 1:0] ddin;
wire [dd_width - 1:0] ddout;
wire den;
wire dwe;
brainfuckcpu #(
.fast_loopend(fast_loopend),
.ia_width(ia_width),
.da_width(da_width),
.dd_width(dd_width),
.stack_depth_pow(stack_depth_pow)
) cpu (
.clk(clk),
.reset(reset),
.ia(ia),
.idin(idin),
.ien(ien),
.da(da),
.ddin(ddin),
.ddout(ddout),
.den(den),
.dwe(dwe),
.cin(cin),
.cout(cout),
.crda(crda),
.cack(cack),
.cwr(cwr),
.crdy(crdy)
);
iram #(
.ia_width(ia_width)
) iram (
.clk(clk),
.a(ia),
.dout(idin),
.en(ien)
);
dram #(
.da_width(da_width),
.dd_width(dd_width)
) dram (
.clk(clk),
.a(da),
.din(ddout),
.dout(ddin),
.en(den),
.we(dwe)
);
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [5:0] write_address;
wire [5:0] read_address;
wire [0:0] read_data;
wire [0:0] write_data;
wire write_enable;
wire [0:0] rom_read_data;
wire [5:0] rom_read_address;
assign rom_read_data[0] = ^rom_read_address;
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [5:0] error_address;
wire [0:0] expected_data;
wire [0:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(6),
.DATA_WIDTH(1),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(1),
// 64-bit LUT memories are 0-63
.MAX_ADDRESS(63)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
wire [0:0] read_data_pre_ff;
RAM64X1D #(
.INIT(64'b01101001_10010110_10010110_01101001_10010110_01101001_01101001_10010110)
) dram(
.WCLK(clk),
.A5(write_address[5]),
.A4(write_address[4]),
.A3(write_address[3]),
.A2(write_address[2]),
.A1(write_address[1]),
.A0(write_address[0]),
.DPRA5(read_address[5]),
.DPRA4(read_address[4]),
.DPRA3(read_address[3]),
.DPRA2(read_address[2]),
.DPRA1(read_address[1]),
.DPRA0(read_address[0]),
.DPO(read_data_pre_ff[0]),
.D(write_data[0]),
.WE(write_enable)
);
FDRE ram_reg(
.D(read_data_pre_ff),
.Q(read_data[0]),
.C(clk),
.CE(1),
.R(0)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(1),
.ADDR_WIDTH(6)
) output_logic(
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
/*
copyright 2024 purdue university
author: miguel isrrael teran (misrrael@purdue.edu)
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
/* this file is generated, do not edit */
// `timescale 1ns/1ps
`default_nettype none
`define wb_aw 32
// `include "wb_wrapper.vh"
module sample_team_proj_wb (
`wb_slave_ports,
input wire [32-1:0] la_data_in,
output wire [32-1:0] la_data_out,
input wire [32-1:0] la_oenb,
input wire [34-1:0] gpio_in,
output wire [34-1:0] gpio_out,
output wire [34-1:0] gpio_oeb,
input wire nrst
);
localparam en_val_reg_offset = `wb_aw'h30000000;
localparam prescaler_val_reg_offset = `wb_aw'h30000004;
localparam im_reg_offset = `wb_aw'h3000ff00;
localparam mis_reg_offset = `wb_aw'h3000ff04;
localparam ris_reg_offset = `wb_aw'h3000ff08;
localparam ic_reg_offset = `wb_aw'h3000ff0c;
wire clk = clk_i;
`wb_ctrl_signals
wire [1-1:0] en;
wire [14-1:0] prescaler;
wire [1-1:0] done;
// register definitions
reg [0:0] en_val_reg;
assign en = en_val_reg;
`wb_reg(en_val_reg, 0, 1)
reg [13:0] prescaler_val_reg;
assign prescaler = prescaler_val_reg;
`wb_reg(prescaler_val_reg, 0, 14)
reg [0:0] im_reg;
reg [0:0] ic_reg;
reg [0:0] ris_reg;
`wb_mis_reg(1)
`wb_reg(im_reg, 0, 1)
`wb_ic_reg(1)
wire [0:0] done_assert = done;
integer _i_;
`wb_block(ris_reg, 0) else begin
for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
if(ic_reg[_i_]) ris_reg[_i_] <= 1'b0; else if(done_assert[_i_ - 0] == 1'b1) ris_reg[_i_] <= 1'b1;
end
end
assign irq = |mis_reg;
sample_team_proj instance_to_wrap (
.clk(clk),
.nrst(nrst),
.en(en),
.prescaler(prescaler),
.done(done),
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb(la_oenb),
.gpio_in(gpio_in),
.gpio_out(gpio_out),
.gpio_oeb(gpio_oeb)
);
assign dat_o =
(adr_i[`wb_aw-1:0] == en_val_reg_offset) ? en_val_reg :
(adr_i[`wb_aw-1:0] == prescaler_val_reg_offset) ? prescaler_val_reg :
(adr_i[`wb_aw-1:0] == im_reg_offset) ? im_reg :
(adr_i[`wb_aw-1:0] == mis_reg_offset) ? mis_reg :
(adr_i[`wb_aw-1:0] == ris_reg_offset) ? ris_reg :
(adr_i[`wb_aw-1:0] == ic_reg_offset) ? ic_reg :
32'hdeadbeef;
always @ (posedge clk_i or posedge rst_i)
if(rst_i)
ack_o <= 1'b0;
else if(wb_valid & ~ack_o)
ack_o <= 1'b1;
else
ack_o <= 1'b0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o);
parameter width = 16;
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [width-1:0] mask_i;
output pn_o;
reg [width-1:0] shifter;
wire parity = ^(shifter & mask_i);
always @(posedge clk_i)
if (rst_i | ~ena_i)
shifter <= #5 1;
else
if (strobe_i)
shifter <= #5 {shifter[width-2:0],parity};
assign pn_o = shifter[0];
endmodule // lfsr
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
/*
* sdram.v - SDRAM driver
*
* SDRAM driver written from scratch for 128M Alliance Memory (AS4C8M16SA)
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 Intelligent.Toasters@gmail.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`ifndef MODEL_TECH
`default_nettype none
`endif
`define SIZE128M
`define LATENCY2
module sdram (
// State machine clock
input memclk_i,
input reset_i,
// Logical Interface (8M words of 16 bits)
input enable_i,
input rd_i,
input wr_i,
input [22:0] A_i,
input [15:0] D_i,
input [1:0] Dm_i,
output [15:0] D_o,
output reg D_valid,
// Physical SDRAM Interface
input [15:0] Dq_in, // From Ram
output [15:0] Dq_out, // To Ram
output Dq_oe,
output reg [11:0] Addr,
output reg [1:0] Ba,
output Clk,
output Cke,
output reg Cs_n,
output reg Ras_n,
output reg Cas_n,
output reg We_n,
output [1 : 0] Dqm
);
// States
parameter INIT = 0, XXXXX = 1, IDLE = 2, PRECHARGE_ALL = 3, SET_MODE = 4, AUTO_REFRESH2 = 5,
AUTO_REFRESH = 6, COUNT_DOWN = 7, FULL_COUNT_DOWN = 8, PRECHARGE_REFRESH = 9,
CLOSE_ROW = 10, OPEN_ROW = 11, READ = 12, READOUT = 13, WRITE = 14, WRITEIN = 15,
WRITE_SETTLE = 16, STARTUP_REFRESH1 = 17, STARTUP_REFRESH2 = 18;
// Wire definitions ===========================================================================
wire [3:0] wait_timeout; // Waiting for a bank timeout
wire refresh_pending; // Waiting for opportunity to refresh
wire op_pending; // Interface operation pending
wire [1:0] op_bank;
wire [11:0] op_row;
wire [8:0] op_col;
// Registers ==================================================================================
reg [4:0] state = INIT, next_state = IDLE;
reg [15:0] counter; // Used as single counter for start up, or split into 4 for bank cntr
reg [11:0] refresh_ticker;
reg refresh_due, refresh_done;
reg [11:0] lastrow[0:3]; // Last row accessed
reg [3:0] bank_open; // If the lastrow valid for this bank?
reg [3:0] startup_cycles = 0;
// Registered request interface
reg if_rd, if_wr;
reg [22:0] if_A;
// Alternate edge request
reg if_rd_alt, if_wr_alt, op_pending_alt;
reg [22:0] if_A_alt;
// Operation pending
reg op_due, op_done;
// Indicates that we're in a read/write process
reg data_proc_cycle;
// Indicates that the state machine is busy with something OTHER than refresh and should ignore requests
reg fsm_busy;
// Assignments ================================================================================
assign Clk = memclk_i;
assign Cke = 1'b1; // Always enable clock
// Timeout signals
assign wait_timeout[0] = (counter[3:0] == 0); // Set if a timer is ticking for bank 0
assign wait_timeout[1] = (counter[7:4] == 0); // Set if a timer is ticking for bank 1
assign wait_timeout[2] = (counter[11:8] == 0); // Set if a timer is ticking for bank 2
assign wait_timeout[3] = (counter[15:12] == 0); // Set if a timer is ticking for bank 3
assign refresh_pending = refresh_due ^ refresh_done; // XOR
assign op_pending = op_due ^ op_done; // XOR
// Convenience/readability assignments
assign op_bank = if_A_alt[22:21];
assign op_row = if_A_alt[20:9];
assign op_col = if_A_alt[8:0];
// Memory IF Assignments
assign D_o = Dq_in;
assign Dq_out = D_i;
assign Dq_oe = (D_valid & if_wr_alt); // Output enable for DQ
assign Dqm = Dm_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
`ifdef SIM
wire [11:0] debug_bankrow0=lastrow[0];
wire [11:0] debug_bankrow1=lastrow[1];
wire [11:0] debug_bankrow2=lastrow[2];
wire [11:0] debug_bankrow3=lastrow[3];
`endif
// Other logic ================================================================================
// Function definitions ===========================================================================
// Command table attributes (Wait = delay after executing command, A-Banks is a op affecting all)
function [0:5] param_table (
input [3:0] cmd
);
case( cmd )
// A10 CS RAS CAS WE R0/C1
4'd00: param_table = { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0}; // Nop
4'd01: param_table = { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0}; // Precharge all
4'd02: param_table = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; // Set mode
4'd03: param_table = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0}; // Auto refresh
4'd04: param_table = { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0}; // Precharge Bank
4'd05: param_table = { op_row[10], 1'b0, 1'b0, 1'b1, 1'b1, 1'b0}; // Bank Activate
4'd06: param_table = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}; // READ
4'd07: param_table = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1}; // WRITE
default: param_table = -6'd1; // Invalid
endcase
endfunction
// Set the registered signals for the SDRAM
task set_signals ( input [0:5] data );
{Cs_n, Ras_n, Cas_n, We_n, Ba, Addr[11:0]} <=
{data[1:4], op_bank, (~data[5]) ? op_row[11] : 1'b0, data[0], (data[5]) ? {1'b0, op_col} : op_row[9:0]};
endtask
// Set timeout for the specific bank
task set_bank_timeout ( input [1:0] bank, input [3:0] data );
case(bank)
2'd0: counter[3:0] <= data;
2'd1: counter[7:4] <= data;
2'd2: counter[11:8] <= data;
2'd3: counter[15:12] <= data;
endcase
endtask
// Timer expired for bank?
function bank_timeout( input [1:0] bank );
case(bank)
2'd0: bank_timeout = (counter[3:0] == 4'd0);
2'd1: bank_timeout = (counter[7:4] == 4'd0);
2'd2: bank_timeout = (counter[11:8] == 4'd0);
2'd3: bank_timeout = (counter[15:12] == 4'd0);
default: bank_timeout = 0;
endcase
endfunction
// Track the memory request interface signals, rising edge
always @(posedge memclk_i)
if( reset_i ) begin
op_due <= 0;
if_rd <= 0;
if_wr <= 0;
if_A <= 0;
end
else
if( enable_i && ~fsm_busy ) begin // Ignore any requests during processing
if_rd <= rd_i;
if_wr <= wr_i;
if_A <= A_i;
if( ~op_pending ) op_due <= ~op_due;
end
// Capture on alt-edge
always @(negedge memclk_i)
begin
if_rd_alt <= if_rd;
if_wr_alt <= if_wr;
if_A_alt <= if_A;
op_pending_alt <= op_pending;
end
// Manage state machine - set next states
always @(posedge memclk_i)
begin
if( reset_i ) begin
refresh_done <= 0;
op_done <= 0;
lastrow[0] <= 0;
lastrow[1] <= 0;
lastrow[2] <= 0;
lastrow[3] <= 0;
// No banks open
bank_open <= 0;
state <= INIT;
// Not busy
fsm_busy <= 0;
end
else begin
// FSM Machine
case( state )
// Count downs - used by pretty much every command
COUNT_DOWN: begin
// Transition to next state
if( bank_timeout(op_bank) ) state <= next_state;
// Updated counters
if( ~wait_timeout[0] ) counter[3:0] <= counter[3:0] - 1'b1;
if( ~wait_timeout[1] ) counter[7:4] <= counter[7:4] - 1'b1;
if( ~wait_timeout[2] ) counter[11:8] <= counter[11:8] - 1'b1;
if( ~wait_timeout[3] ) counter[15:12] <= counter[15:12] - 1'b1;
end
// Full range count down for start up
FULL_COUNT_DOWN: begin
if( counter == 0 )
state <= next_state;
else
counter <= counter - 1'b1;
end
// Power on initialize
INIT: begin
data_proc_cycle <= 0;
counter <= -16'd1; // Wait for stable clock > 200uS (410uS)
state <= FULL_COUNT_DOWN;
next_state <= PRECHARGE_ALL;
end
// Precharge all banks
PRECHARGE_ALL: begin
counter <= 16'h1111; // Countdown all banks
bank_open <= 0; // No banks open
state <= COUNT_DOWN;
startup_cycles <= 7; // Startup counter - 8 refreshes
next_state <= STARTUP_REFRESH1;
end
// Initial refresh start up required before mode set in some devices
STARTUP_REFRESH1: begin
state <= STARTUP_REFRESH2;
end
STARTUP_REFRESH2: begin
counter <= 16'h7777;
state <= COUNT_DOWN;
if( startup_cycles == 0 ) next_state <= SET_MODE;
else begin
startup_cycles <= startup_cycles - 1'b1;
next_state <= STARTUP_REFRESH1;
end
end
// Precharge all banks then refresh
PRECHARGE_REFRESH: begin
// Only process precharge if an operation is not in progress
if( counter == 0 ) begin
bank_open <= 0; // No banks open
counter <= 16'h1111; // Countdown all banks
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH;
end
end
// Set mode command
SET_MODE: begin
counter <= 4'd0;
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH2;
end
// Auto Refresh 2 - start up double auto refresh
AUTO_REFRESH2: begin
counter <= 16'h8888;
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH;
end
// Auto Refresh
AUTO_REFRESH: begin
counter <= 16'h8888;
state <= COUNT_DOWN;
next_state <= IDLE;
// Clear the refresh pending flag
if( refresh_pending ) refresh_done <= ~refresh_done;
end
// Set mode command
IDLE: begin
if( refresh_pending ) begin
state <= PRECHARGE_REFRESH;
fsm_busy <= 0;
end
else if( op_pending_alt ) begin
// Reset the pending flag, always half a cycle behind _alt, so will be set
if( op_pending ) op_done <= ~op_done;
// Doing something, so set busy flag
fsm_busy <= 1'b1;
// Check row in bank, if not same then close
if( bank_open[op_bank] )
begin
// Is bank correct?
if( lastrow[op_bank] != op_row ) begin
state <= CLOSE_ROW;
end
// Bank open and ready!
else state <= (if_rd_alt) ? READ : (if_wr_alt) ? WRITE : IDLE; //(Failsafe)
end
else state <= OPEN_ROW; // Otherwise open the bank
end
// Otherwise stay in idle
else begin
state <= IDLE;
// Not busy
fsm_busy <= 0;
end
// Can't be in retrieval if idle
data_proc_cycle <= 0;
end
// Close row command
CLOSE_ROW: begin
set_bank_timeout(op_bank, 1);
bank_open[op_bank] <= 0; // Close this bank
state <= COUNT_DOWN;
next_state <= OPEN_ROW;
end
// Open row command
OPEN_ROW: begin
set_bank_timeout(op_bank, 1);
state <= COUNT_DOWN;
next_state <= (if_rd_alt) ? READ : (if_wr_alt) ? WRITE : IDLE; //(Failsafe)
bank_open[op_bank] <= 1; // Indicate bank open
lastrow[op_bank] <= op_row; // Store the row for later comparison
end
// Read command
READ: begin
`ifdef LATENCY2
set_bank_timeout(op_bank, 0);
`else // Latency 3 clocks
set_bank_timeout(op_bank, 1);
`endif
state <= COUNT_DOWN;
next_state <= READOUT;
end
// OUT processing
READOUT: begin
data_proc_cycle <= 1'b1;
set_bank_timeout(op_bank, 6);
state <= COUNT_DOWN;
next_state <= IDLE;
end
// Write command
WRITE: begin
state <= WRITEIN;
data_proc_cycle <= 1'b1;
end
// IN processing (-2)
WRITEIN: begin
set_bank_timeout(op_bank, 5);
state <= COUNT_DOWN;
next_state <= WRITE_SETTLE;
end
WRITE_SETTLE: begin
`ifdef LATENCY2
set_bank_timeout(op_bank, 0);
`else // Latency 3 clocks
set_bank_timeout(op_bank, 1);
`endif
data_proc_cycle <= 0;
state <= COUNT_DOWN;
next_state <= IDLE;
fsm_busy <= 0;
end
// If we lose the state, then self-reset
default: state <= INIT;
endcase
end
end
// Update signals (memory reads in on rising edge)
always @(negedge memclk_i)
begin
if( reset_i ) begin
refresh_ticker <= 0;
refresh_due <= 0;
end
else begin
`ifdef SIZE128M
// Refresh ticker - cycle at 2432, 62.2848ms full cycle (15.20625uS repeats) 4096 Rows
if(refresh_ticker[11:7] == 5'b10011)
`else
// Refresh ticker - cycle at 768, 62.91456ms full cycle (8192 Rows)
if(refresh_ticker[9:8] == 2'b11)
`endif
begin
refresh_ticker <= 12'd0;
// Cause refresh to be due
if( ~refresh_pending ) refresh_due <= ~refresh_due;
end
else refresh_ticker <= (refresh_ticker + 1'b1);
// Set the valid indicator
D_valid <= (data_proc_cycle || (state == READOUT) || (state == WRITE)) && (state != IDLE) && (state != WRITE_SETTLE);
// Set the output state
case( state )
IDLE: set_signals(param_table(0));
INIT: set_signals(param_table(0));
COUNT_DOWN: set_signals(param_table(0));
FULL_COUNT_DOWN: set_signals(param_table(0));
STARTUP_REFRESH2: set_signals(param_table(0));
PRECHARGE_ALL: set_signals(param_table(1));
PRECHARGE_REFRESH: set_signals(param_table(1));
AUTO_REFRESH2: set_signals(param_table(3));
AUTO_REFRESH: set_signals(param_table(3));
STARTUP_REFRESH1: set_signals(param_table(3));
CLOSE_ROW: set_signals(param_table(4));
OPEN_ROW: set_signals(param_table(5));
READ: set_signals(param_table(6));
READOUT: set_signals(param_table(0));
WRITE: set_signals(param_table(7));
WRITEIN: set_signals(param_table(0));
WRITE_SETTLE: set_signals(param_table(0));
SET_MODE: begin
set_signals(param_table(2));
Addr <= 12'h23; // 8-word bursts with 2.latency
end
default: set_signals(param_table(0)); // NOP
endcase
end
end
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_timers(
input clk,
input rst,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input set_run_A,
input set_run_B,
input clr_run_A,
input clr_run_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
jt51_timer #(.mult_width(6), .counter_width(10)) timer_A(
.clk ( clk ),
.rst ( rst ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.set_run ( set_run_A ),
.clr_run ( clr_run_A ),
.flag ( flag_A ),
.overflow ( overflow_A)
);
jt51_timer #(.mult_width(10), .counter_width(8)) timer_B(
.clk ( clk ),
.rst ( rst ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B),
.set_run ( set_run_B ),
.clr_run ( clr_run_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
module jt51_timer #(parameter counter_width = 10, mult_width=5 )
(
input clk,
input rst,
input [counter_width-1:0] start_value,
input load,
input clr_flag,
input set_run,
input clr_run,
output reg flag,
output reg overflow
);
reg run;
reg [ mult_width-1:0] mult;
reg [counter_width-1:0] cnt;
always@(posedge clk)
if( clr_flag || rst)
flag <= 1'b0;
else if(overflow) flag<=1'b1;
always@(posedge clk)
if( clr_run || rst)
run <= 1'b0;
else if(set_run || load) run<=1'b1;
reg [mult_width+counter_width-1:0] next, init;
always @(*) begin
{overflow, next } = { 1'b0, cnt, mult } + 1'b1;
init = { start_value, { (mult_width){1'b0} } };
end
always @(posedge clk) begin : counter
if( load ) begin
mult <= { (mult_width){1'b0} };
cnt <= start_value;
end
else if( run )
{ cnt, mult } <= overflow ? init : next;
end
endmodule
|
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