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/*
* Copyright (C) 2015 Xiongfei Guo <xfguo@credosemi.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License, version 3
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program. If not, see
* <http://www.gnu.org/licenses/>.
*
*
* Send a pulse from one domain to another timing domain.
*
* NOTE: the pulse must be one cycle and cannot be set again when busy_o is
* high.
*/
module xdom_pulse_sender (
input grst_i,
input odom_clk_i,
input odom_pulse_i,
input xdom_clk_i,
output xdom_pulse_o,
output busy_o,
output err_o
);
/* signals in origin domain */
reg odom_pulse_delay_r;
reg odom_pulse_keeper_r;
reg [1:0] odom_feedback_double_flips_r ;
reg err_r;
reg odom_pulse_gen_r;
/* cross-domain signals */
wire xdom_pulse_en;
wire odom_pulse_safe_cancel;
/* signals in cross domain */
reg [1:0] xdom_double_flips_r ;
reg xdom_pulse_en_delay_r ;
reg xdom_pulse_gen_r ;
/* latch input pulse for one cycle */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_delay_r <= 1'b0;
else
odom_pulse_delay_r <= odom_pulse_i;
/* detect pos-edge of odm_pulse_i */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_gen_r <= 1'b0;
else if ((odom_pulse_i == 1'b1) && (odom_pulse_delay_r == 1'b0))
odom_pulse_gen_r <= 1'b1;
else
odom_pulse_gen_r <= 1'b0;
/* keep input pulse signal until feedback signal cancel it */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_pulse_keeper_r <= 1'b0;
else if (odom_pulse_keeper_r == 1'b0 && (odom_pulse_gen_r == 1'b1))
odom_pulse_keeper_r <= 1'b1;
else if (odom_pulse_keeper_r == 1'b1 && odom_pulse_safe_cancel == 1'b1)
odom_pulse_keeper_r <= 1'b0;
else
odom_pulse_keeper_r <= odom_pulse_keeper_r;
/* busy signal */
assign busy_o = odom_pulse_keeper_r | odom_pulse_i | odom_pulse_safe_cancel;
/* a new request must wait until last is finished */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
err_r <= 1'b0;
else
err_r <= (odom_pulse_keeper_r == 1'b1) && (odom_pulse_i == 1'b1);
assign err_o = err_r;
/* double flips in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_double_flips_r <= 2'b0;
else
xdom_double_flips_r <= {odom_pulse_keeper_r, xdom_double_flips_r[1]};
assign xdom_pulse_en = xdom_double_flips_r[0];
/* double flips in origin-domain */
always @(posedge odom_clk_i or posedge grst_i)
if (grst_i)
odom_feedback_double_flips_r <= 2'b0;
else
odom_feedback_double_flips_r <= {xdom_pulse_en, odom_feedback_double_flips_r[1]};
assign odom_pulse_safe_cancel = odom_feedback_double_flips_r[0];
/* latch cross domain pulse enable signal for one cycle. */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_en_delay_r <= 1'b0;
else
xdom_pulse_en_delay_r <= xdom_pulse_en;
/* generate pulse in cross-domain */
always @(posedge xdom_clk_i or posedge grst_i)
if (grst_i)
xdom_pulse_gen_r <= 1'b0;
else if (xdom_pulse_en == 1'b1 && xdom_pulse_en_delay_r == 1'b0)
xdom_pulse_gen_r <= 1'b1;
else
xdom_pulse_gen_r <= 1'b0;
assign xdom_pulse_o = xdom_pulse_gen_r;
endmodule
|
/*
* @file name: predecode
* @author: ruige lee
* @email: wut.ruigeli@gmail.com
* @date: 2021-01-05 16:23:28
* @last modified by: ruige lee
* @last modified time: 2021-03-11 11:04:35
*/
/*
copyright (c) 2020 - 2021 ruige lee <wut.ruigeli@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1 ns / 1 ps
module predecode (
input [255:0] instr_load,
input [15:0] iq_instr_mask_load,
output instr_buf_empty,
output isjal,
output isjalr,
output isbranch,
output iscall,
output isreturn,
output isrvc,
output isfencei,
output [63:0] imm
);
assign instr_buf_empty = ((iq_instr_mask_load[1] != 1'b1) & instr_load[1:0] == 2'b11)
|
((iq_instr_mask_load[0] != 1'b1) );
wire [31:0] instr = instr_load[31:0];
assign isrvc = ~instr_buf_empty & (instr[1:0] != 2'b11);
wire isijal = ~isrvc & (instr[6:0] == 7'b1101111);
wire iscjal = instr[1:0] == 2'b01 & instr[15:13] == 3'b101;
wire isijalr = ~isrvc & (instr[6:0] == 7'b1100111);
wire iscjalr = (instr[1:0] == 2'b10 & instr[15:13] == 3'b100)
&
(
(~instr[12] & (instr[6:2] == 0))
|
( instr[12] & (|instr[11:7]) & (&(~instr[6:2])))
);
wire isibranch = ~isrvc & (instr[6:0] == 7'b1100011);
wire iscbranch = instr[1:0] == 2'b01 & instr[15:14] == 2'b11;
wire isicall = (isijalr | isijal) & ((instr[11:7] == 5'd1) | instr[11:7] == 5'd5);
wire isccall = iscjalr & instr[12];
wire isireturn = isijalr & ((instr[19:15] == 5'd1) | instr[19:15] == 5'd5)
& (instr[19:15] != instr[11:7]);
wire iscreturn = iscjalr & ~instr[12]
& ((instr[11:7] == 5'd1) | (instr[11:7] == 5'd5));
wire [63:0] iimm =
({64{isijal}} & {{44{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0})
|
({64{isijalr}} & {{52{instr[31]}},instr[31:20]})
|
({64{isibranch}} & {{52{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0});
wire [63:0] cimm =
({64{iscjal}} & {{52{instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0})
|
({64{iscjalr}} & 64'b0)
|
({64{iscbranch}} & {{55{instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0});
assign isjal = ~instr_buf_empty & (isijal | iscjal);
assign isjalr = ~instr_buf_empty & (isijalr | iscjalr);
assign isbranch = ~instr_buf_empty & (isibranch | iscbranch);
assign iscall = ~instr_buf_empty & (isicall | isccall);
assign isreturn = ~instr_buf_empty & (isireturn | iscreturn);
assign isfencei = (instr[6:0] == 7'b0001111) & (instr[14:12] == 3'b001);
assign imm = isrvc ? cimm : iimm;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_texcache #(
parameter cache_depth = 13, /* < log2 of the capacity in 8-bit words */
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [fml_depth-1-1:0] tadra,
input [fml_depth-1-1:0] tadrb,
input [fml_depth-1-1:0] tadrc,
input [fml_depth-1-1:0] tadrd,
input [5:0] x_frac,
input [5:0] y_frac,
output pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output [15:0] tcolora,
output [15:0] tcolorb,
output [15:0] tcolorc,
output [15:0] tcolord,
output reg [5:0] x_frac_f,
output reg [5:0] y_frac_f,
output reg [21:0] c_req_a,
output reg [21:0] c_hit_a,
output reg [21:0] c_req_b,
output reg [21:0] c_hit_b,
output reg [21:0] c_req_c,
output reg [21:0] c_hit_c,
output reg [21:0] c_req_d,
output reg [21:0] c_hit_d
);
/*
* To make bit index calculations easier,
* we work with 8-bit granularity EVERYWHERE, unless otherwise noted.
*/
/*
* Line length is the burst length, that is 4*64 bits, or 32 bytes
* Addresses are split as follows:
*
* | TAG | INDEX | OFFSET |
* |fml_depth-1 cache_depth|cache_depth-1 5|4 0|
*
*/
/* MEMORIES & HIT HANDLING */
wire [fml_depth-1:0] tadra8 = {tadra, 1'b0};
wire [fml_depth-1:0] tadrb8 = {tadrb, 1'b0};
wire [fml_depth-1:0] tadrc8 = {tadrc, 1'b0};
wire [fml_depth-1:0] tadrd8 = {tadrd, 1'b0};
reg [fml_depth-1:0] tadra8_r;
reg [fml_depth-1:0] tadrb8_r;
reg [fml_depth-1:0] tadrc8_r;
reg [fml_depth-1:0] tadrd8_r;
always @(posedge sys_clk) begin
if(pipe_ack_o) begin
tadra8_r <= tadra8;
tadrb8_r <= tadrb8;
tadrc8_r <= tadrc8;
tadrd8_r <= tadrd8;
end
end
wire retry; /* < retry the old address after a miss */
wire [31:0] datamem_d1;
wire [31:0] datamem_d2;
wire [31:0] datamem_d3;
wire [31:0] datamem_d4;
reg datamem_we;
wire [cache_depth-3-1:0] datamem_aw;
tmu2_qpram32 #(
.depth(cache_depth-2)
) datamem (
.sys_clk(sys_clk),
.a1(retry ? tadra8_r[cache_depth-1:2] : tadra8[cache_depth-1:2]),
.d1(datamem_d1),
.a2(retry ? tadrb8_r[cache_depth-1:2] : tadrb8[cache_depth-1:2]),
.d2(datamem_d2),
.a3(retry ? tadrc8_r[cache_depth-1:2] : tadrc8[cache_depth-1:2]),
.d3(datamem_d3),
.a4(retry ? tadrd8_r[cache_depth-1:2] : tadrd8[cache_depth-1:2]),
.d4(datamem_d4),
.we(datamem_we),
.aw(datamem_aw),
.dw(fml_di)
);
assign tcolora = tadra8_r[1] ? datamem_d1[15:0] : datamem_d1[31:16];
assign tcolorb = tadrb8_r[1] ? datamem_d2[15:0] : datamem_d2[31:16];
assign tcolorc = tadrc8_r[1] ? datamem_d3[15:0] : datamem_d3[31:16];
assign tcolord = tadrd8_r[1] ? datamem_d4[15:0] : datamem_d4[31:16];
wire [1+fml_depth-cache_depth-1:0] tagmem_d1; /* < valid bit + tag */
wire [1+fml_depth-cache_depth-1:0] tagmem_d2;
wire [1+fml_depth-cache_depth-1:0] tagmem_d3;
wire [1+fml_depth-cache_depth-1:0] tagmem_d4;
reg tagmem_we;
wire [cache_depth-1-5:0] tagmem_aw;
wire [1+fml_depth-cache_depth-1:0] tagmem_dw;
tmu2_qpram #(
.depth(cache_depth-5),
.width(1+fml_depth-cache_depth)
) tagmem (
.sys_clk(sys_clk),
.a1(retry ? tadra8_r[cache_depth-1:5] : tadra8[cache_depth-1:5]),
.d1(tagmem_d1),
.a2(retry ? tadrb8_r[cache_depth-1:5] : tadrb8[cache_depth-1:5]),
.d2(tagmem_d2),
.a3(retry ? tadrc8_r[cache_depth-1:5] : tadrc8[cache_depth-1:5]),
.d3(tagmem_d3),
.a4(retry ? tadrd8_r[cache_depth-1:5] : tadrd8[cache_depth-1:5]),
.d4(tagmem_d4),
.we(tagmem_we),
.aw(tagmem_aw),
.dw(tagmem_dw)
);
/* HIT HANDLING */
reg flush_mode;
reg access_requested;
always @(posedge sys_clk) begin
if(sys_rst)
access_requested <= 1'b0;
else if(pipe_ack_o)
access_requested <= pipe_stb_i;
end
/* The cycle after the tag memory has been written, data is invalid */
reg tagmem_we_r;
always @(posedge sys_clk) tagmem_we_r <= tagmem_we;
/* If some coordinates are integer, B, C or D can be ignored
* and safely assumed to be cache hits.
*/
reg ignore_b;
reg ignore_c;
reg ignore_d;
always @(posedge sys_clk) begin
if(pipe_ack_o) begin
ignore_b <= x_frac == 6'd0;
ignore_c <= y_frac == 6'd0;
ignore_d <= (x_frac == 6'd0) | (y_frac == 6'd0);
end
end
wire valid_a = tagmem_d1[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_a = tagmem_d1[fml_depth-cache_depth-1:0];
wire valid_b = tagmem_d2[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_b = tagmem_d2[fml_depth-cache_depth-1:0];
wire valid_c = tagmem_d3[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_c = tagmem_d3[fml_depth-cache_depth-1:0];
wire valid_d = tagmem_d4[1+fml_depth-cache_depth-1];
wire [fml_depth-1-cache_depth:0] tag_d = tagmem_d4[fml_depth-cache_depth-1:0];
wire hit_a = ~tagmem_we_r & valid_a & (tag_a == tadra8_r[fml_depth-1:cache_depth]);
wire hit_b = ignore_b | (~tagmem_we_r & valid_b & (tag_b == tadrb8_r[fml_depth-1:cache_depth]));
wire hit_c = ignore_c | (~tagmem_we_r & valid_c & (tag_c == tadrc8_r[fml_depth-1:cache_depth]));
wire hit_d = ignore_d | (~tagmem_we_r & valid_d & (tag_d == tadrd8_r[fml_depth-1:cache_depth]));
assign pipe_stb_o = access_requested & hit_a & hit_b & hit_c & hit_d;
assign pipe_ack_o = ~flush_mode & ((pipe_ack_i & pipe_stb_o) | ~access_requested);
assign retry = ~pipe_ack_o;
/* STATISTICS COLLECTION */
reg pipe_ack_o_r;
always @(posedge sys_clk) begin
if(sys_rst)
pipe_ack_o_r <= 1'b0;
else
pipe_ack_o_r <= pipe_ack_o;
end
always @(posedge sys_clk) begin
if(sys_rst|flush) begin
c_req_a <= 22'd0;
c_hit_a <= 22'd0;
c_req_b <= 22'd0;
c_hit_b <= 22'd0;
c_req_c <= 22'd0;
c_hit_c <= 22'd0;
c_req_d <= 22'd0;
c_hit_d <= 22'd0;
end else begin
if(pipe_ack_o_r & access_requested) begin
c_req_a <= c_req_a + 22'd1;
if(hit_a)
c_hit_a <= c_hit_a + 22'd1;
if(~ignore_b) begin
c_req_b <= c_req_b + 22'd1;
if(hit_b)
c_hit_b <= c_hit_b + 22'd1;
end
if(~ignore_c) begin
c_req_c <= c_req_c + 22'd1;
if(hit_c)
c_hit_c <= c_hit_c + 22'd1;
end
if(~ignore_d) begin
c_req_d <= c_req_d + 22'd1;
if(hit_d)
c_hit_d <= c_hit_d + 22'd1;
end
end
end
end
`ifdef VERIFY_TEXCACHE
integer x, y;
reg [15:0] expected;
always @(posedge sys_clk) begin
if(pipe_stb_o & pipe_ack_i) begin
x = (tadra8_r/2) % 512;
y = (tadra8_r/2) / 512;
$image_get(x, y, expected);
if(tcolora != expected) begin
$display("CACHE TEST FAILED [A]! (%d, %d): expected %x, got %x", x, y, expected, tcolora);
$finish;
end
if(~ignore_b) begin
x = (tadrb8_r/2) % 512;
y = (tadrb8_r/2) / 512;
$image_get(x, y, expected);
if(tcolorb != expected) begin
$display("CACHE TEST FAILED [B]! (%d, %d): expected %x, got %x", x, y, expected, tcolorb);
$finish;
end
end
if(~ignore_c) begin
x = (tadrc8_r/2) % 512;
y = (tadrc8_r/2) / 512;
$image_get(x, y, expected);
if(tcolorc != expected) begin
$display("CACHE TEST FAILED [C]! (%d, %d): expected %x, got %x", x, y, expected, tcolorc);
$finish;
end
end
if(~ignore_d) begin
x = (tadrd8_r/2) % 512;
y = (tadrd8_r/2) / 512;
$image_get(x, y, expected);
if(tcolord != expected) begin
$display("CACHE TEST FAILED [D]! (%d, %d): expected %x, got %x", x, y, expected, tcolord);
$finish;
end
end
end
end
`endif
/* FORWARDING */
always @(posedge sys_clk) begin
if(pipe_ack_o & pipe_stb_i) begin
dadr_f <= dadr;
x_frac_f <= x_frac;
y_frac_f <= y_frac;
end
end
/* MISS HANDLING */
reg fetch_needed;
reg [fml_depth-1:0] fetch_adr;
always @(posedge sys_clk) begin
if(sys_rst)
fetch_needed <= 1'b0;
else begin
if(access_requested) begin
fetch_needed <= ~(hit_a & hit_b & hit_c & hit_d);
if(~hit_a)
fetch_adr <= tadra8_r;
else if(~hit_b)
fetch_adr <= tadrb8_r;
else if(~hit_c)
fetch_adr <= tadrc8_r;
else if(~hit_d)
fetch_adr <= tadrd8_r;
end
end
end
wire flush_done;
reg [cache_depth-1-5:0] flush_counter;
always @(posedge sys_clk) begin
if(flush_mode)
flush_counter <= flush_counter + 1'd1;
else
flush_counter <= {cache_depth-5{1'b0}};
end
assign flush_done = &flush_counter;
reg write_valid;
assign tagmem_aw = flush_mode ? flush_counter : fetch_adr[cache_depth-1:5];
assign tagmem_dw = {write_valid, fetch_adr[fml_depth-1:cache_depth]};
reg burst_count;
reg [1:0] burst_counter;
always @(posedge sys_clk) begin
if(burst_count)
burst_counter <= burst_counter + 2'd1;
else
burst_counter <= 2'd0;
end
assign datamem_aw = {fetch_adr[cache_depth-1:5], burst_counter};
assign fml_adr = {fetch_adr[fml_depth-1:5], 5'd0};
/* FSM controller */
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter DATA1 = 3'd1;
parameter DATA2 = 3'd2;
parameter DATA3 = 3'd3;
parameter DATA4 = 3'd4;
parameter WAIT = 3'd5;
parameter WAIT2 = 3'd6;
parameter FLUSH = 3'd7;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
reg fsm_busy;
always @(*) begin
next_state = state;
tagmem_we = 1'b0;
write_valid = 1'b1;
datamem_we = 1'b0;
burst_count = 1'b0;
flush_mode = 1'b0;
fml_stb = 1'b0;
fsm_busy = 1'b1;
case(state)
IDLE: begin
fsm_busy = 1'b0;
if(fetch_needed)
next_state = DATA1;
if(flush)
next_state = FLUSH;
end
DATA1: begin
fml_stb = 1'b1;
datamem_we = 1'b1;
if(fml_ack) begin
burst_count = 1'b1;
next_state = DATA2;
end
end
DATA2: begin
datamem_we = 1'b1;
burst_count = 1'b1;
next_state = DATA3;
end
DATA3: begin
datamem_we = 1'b1;
burst_count = 1'b1;
next_state = DATA4;
end
DATA4: begin
datamem_we = 1'b1;
tagmem_we = 1'b1; /* write tag last as it may unlock the pipeline */
next_state = WAIT;
end
WAIT: next_state = WAIT2; /* wait for fetch_needed to reflect the updated tag */
WAIT2: next_state = IDLE;
FLUSH: begin
tagmem_we = 1'b1;
write_valid = 1'b0;
flush_mode = 1'b1;
if(flush_done)
next_state = IDLE;
end
endcase
end
assign busy = fsm_busy | access_requested;
endmodule
|
/*
copyright 2018 ali raheem <ali.raheem@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and limitations under the license.
*/
module piso_tb();
reg clk;
reg latch;
reg rst;
reg [7:0] din;
reg ser;
wire dout;
piso #(.width(8)) dut(
.clk(clk),
.latch(latch),
.rst(rst),
.din(din),
.ser(ser),
.dout(dout)
);
initial begin
$dumpfile("piso_test.vcd");
$dumpvars(0, piso_tb);
$dumpfile("piso.vcd");
$dumpvars(0, dut);
rst = 1;
ser = 0;
latch = 0;
clk = 0;
din = 8'b0;
#10
rst = 0;
#5
din = 8'h55;
latch = 1;
#15
latch = 0;
din = 0;
#100
din = 8'haa;
latch = 1;
#7
latch = 0;
din = 0;
#100
din = 8'h0f;
latch = 1;
#10
latch = 0;
din = 0;
#100
din = 8'hcd;
latch = 1;
#7
latch = 0;
din = 0;
#100
#100
din = 8'b10000000;
latch = 1;
#5
latch = 0;
din = 0;
#100
din = 8'hf0;
latch = 1;
#5
latch = 0;
din = 0;
#100
$finish;
end // initial begin
always #5
clk = ~clk;
endmodule // piso_tb
|
`timescale 1ns / 1ps
/* this file is part of jt51.
jt51 program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
jt51 program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with jt51. if not, see <http://www.gnu.org/licenses/>.
author: jose tejada gomez. twitter: @topapate
version: 1.0
date: 27-1-2017
*/
module jt51_kon(
input rst,
input clk,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] cur_op,
input [2:0] cur_ch,
input up_keyon,
input csm,
input overflow_a,
output reg keyon_ii
);
//reg csm_copy;
reg din;
wire drop;
reg [3:0] cur_op_hot;
always @(posedge clk)
keyon_ii <= (csm&&overflow_a) || drop;
always @(*) begin
case( cur_op )
2'd0: cur_op_hot = 4'b0001; // s1 / m1
2'd1: cur_op_hot = 4'b0100; // s3 / m2
2'd2: cur_op_hot = 4'b0010; // s2 / c1
2'd3: cur_op_hot = 4'b1000; // s4 / c2
endcase
din = keyon_ch==cur_ch && up_keyon ? |(keyon_op&cur_op_hot) : drop;
end
jt51_sh #(.width(1),.stages(32)) u_konch(
.clk ( clk ),
.din ( din ),
.drop ( drop )
);
endmodule
|
/*
* mbus copyright 2015 regents of the university of michigan
*
* licensed under the apache license, version 2.0 (the "license");
* you may not use this file except in compliance with the license.
* you may obtain a copy of the license at
*
* http://www.apache.org/licenses/license-2.0
*
* unless required by applicable law or agreed to in writing, software
* distributed under the license is distributed on an "as is" basis,
* without warranties or conditions of any kind, either express or implied.
* see the license for the specific language governing permissions and
* limitations under the license.
*/
//****************************************
//task 0 testbench: comprehensive testbench
//****************************************
task task0;
begin
handle=$fopen("result_task0.txt");
#100000;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task0%d, master node and processor wake up", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_proc_up;
@ (posedge sclk);
c0_req_int = 0;
#50000;
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, query", task_counter);
$fdisplay(handle, "master node sends out query");
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_query;
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h2");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h2;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h3");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h3;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h4");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h4;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, enumerate", task_counter);
$fdisplay(handle, "master node enumerate with address 4'h5");
$fdisplay(handle, "-------------------------------------------------------------------------");
enum_short_addr = 4'h5;
state = tb_enum;
@ (posedge c0_rx_req);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, all wake", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_all_wakeup;
@ (posedge c0_tx_succ | c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0, bulk write enable is not set, it won't fail but no memory operation");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 0 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h2;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 3 default sys register bulk mem message control");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h5;
rf_w_data = 24'h80_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1 rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 0;
dest_short_addr = 4'h3;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1 rf address 1-4");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 1;
dest_short_addr = 4'h3;
word_counter = 3;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "read layer 1's rf address 0, and write to layer 2's rf address 0xa");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 0;
rf_read_length = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_rf_write);
rf_relay_loc = 8'ha;
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "bulk read layer 1's rf address 1-4, and write to layer 2's rf address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 1;
rf_read_length = 3;
relay_addr = ((4'h4<<4) | `lc_cmd_rf_write);
rf_relay_loc = 8'h1;
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and write to layer 2's mem, address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 0;
mem_addr = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd1;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-10, bulk active is not set");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 9;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set active, length 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_0000;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-2, bulk active is set, length is 0, only write 1 word");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 1;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-3, bulk active is set, length is 0, only write 1 word, should fail");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 2;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set active, length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 1-10");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 1;
word_counter = 9;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 3 default sys register bulk mem message control, set to maximum length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h5;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "bulk read layer 1's mem address 1-10, and write to layer 3's mem, address 0x0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 9;
mem_addr = 1;
relay_addr = ((4'h5<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd0;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 0 ");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg0_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = 24'h00_0004;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg1_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd1
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1010, 20'd15};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 0 ");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg0_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = 24'h190; // 100 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg1_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd100
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1110, 20'd7};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 3's stream channel 0, enable is not set, should fail");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
stream_channel = 0;
word_counter = 2;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 16 word streaming data to layer 1's stream channel 0, cpu should receive a buffer full alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 15;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 1's stream channel 0, nothing happens");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1010, 20'd15};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 1's stream channel 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 10 word streaming data to layer 1's stream channel 0, cpu should receive a double buffer alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 9;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 10 word streaming data to layer 1's stream channel 0, only 5 words are available, tx should fail, and generates alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 0;
word_counter = 9;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 4 word streaming data to layer 1's stream channel 1, generates double buffer alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 3;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 4 word streaming data to layer 1's stream channel 1, generates buffer full alert");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 3;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 8 word streaming data to layer 1's stream channel 1, generates alert 0xe");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 7;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream mem write", task_counter);
$fdisplay(handle, "cpu sends 16 word streaming data to layer 1's stream channel 1, generates alert 0xf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
stream_channel = 1;
word_counter = 15;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx; // only 2 channels available
dest_short_addr = 4'h3;
rf_w_data = {4'b1100, 20'd7};
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "read layer 3's mem and stream to layer 1's mem, channel 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
mem_read_length = 3;
mem_addr = 0;
relay_addr = {4'd3, 2'b01, 2'b01}; // to layer 1, stream, channel 1
state = tb_short_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer3.tx_succ | layer3.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, select sleep", task_counter);
$fdisplay(handle, "select sleep using long prefix, sleep layer 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
long_addr = 20'hbbbb1;
state = tb_sel_sleep_full_prefix;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu writes random data to layer 1's mem address 0xa");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 30'ha;
word_counter = 0;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 0, read layer 1's rf address 0, and write to layer 2's rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 0;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 1, bulk read layer 1's rf address 2-6, and write to layer 2's rf address 2");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 1;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1 rf address 0-9");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = 0;
dest_short_addr = 4'h3;
word_counter = 9;
state = tb_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg0_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = 24'h190; // 100 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg1_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd100
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 0, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch0_reg2_idx; // only 2 channels available
dest_short_addr = 4'h4;
rf_w_data = {4'b1100, 20'd15}; // maximum length = 16
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg0_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc8; // 50 << 2
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg1_idx;
dest_short_addr = 4'h4;
rf_w_data = {8'hf9, 16'b0}; // stream location 30'd50
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2's stream channel 1, register 2, register 3 should be written by layer controller itself");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = stream_ch1_reg2_idx;
dest_short_addr = 4'h4;
rf_w_data = {4'b1110, 20'd4}; // maximum length = 5
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 2, bulk read layer 1's rf address 0-9, and stream to layer 2's mem address 100");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 2;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 3, write to layer 1's rf address 0");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 3;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 4, write to layer 1's rf address 1, and 3");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 4;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 5, write to layer 1's rf address 2, 4, and 6");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 5;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 6, read from layer 1's mem address 0, and write to layer 2's mem, address 0x1");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 6;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control, set to maximum length 16");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc0_000f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, select sleep", task_counter);
$fdisplay(handle, "select sleep using long prefix, sleep layer 1");
$fdisplay(handle, "-------------------------------------------------------------------------");
long_addr = 20'hbbbb1;
state = tb_sel_sleep_full_prefix;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 7, bulk read from layer 1's mem address 1-5, and write to layer 2's mem, address 2-6");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 7;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 2, interrupt vector 8, read from layer 2's mem address 100, and write to layer 1's rf (address is burried in mem)");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 2; // this is asserted from layer 2
int_vec = 8;
state = tb_single_interrupt;
@ (posedge n2_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 2, interrupt vector 9, read from layer 2's mem address 101-104, and write to layer 1's rf (address is burried in mem)");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 2; // this is asserted from layer 2
int_vec = 9;
state = tb_single_interrupt;
@ (posedge n2_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 10, bulk read from layer 1's mem address 0-9, stream to layer 2's mem, alert should generate");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 10;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
@ (posedge c0_rx_req)
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, sleep all", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_all_sleep;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 11, wakeup only");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 11;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, master node and processor wake up", task_counter);
$fdisplay(handle, "-------------------------------------------------------------------------");
state = tb_proc_up;
@ (posedge sclk);
c0_req_int = 0;
#50000;
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "cpu sends a command with an unknown functional id");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = 4'b1100;
word_counter = 1;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "bulk read layer 1's mem address 0-1, and read layer 3's rf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 1;
mem_addr = 0;
relay_addr = ((4'h5<<4) | `lc_cmd_rf_read); // fake rf read
// read rf from 192-197, write to layer 2's rf location 0 <- this is an invalid rf read command
mem_relay_loc = (8'd192<<22 | 8'd5<<14 | 4'h4<<10 | `lc_cmd_rf_write<<6 | 6'h0);
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and read layer 3's rf");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 0;
mem_addr = 0;
relay_addr = ((4'h5<<4) | `lc_cmd_rf_read); // fake rf read
// read rf from 192-197 (non-existing location), write to layer 2's rf location 0 <- this is an invalid rf read command
mem_relay_loc = (8'd192<<22 | 8'd5<<14 | 4'h4<<10 | `lc_cmd_rf_write<<6 | 6'h0);
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf read", task_counter);
$fdisplay(handle, "read layer 1's rf address 250-4, and send to processor, coverage test");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
rf_addr = 8'd250;
rf_read_length = 9;
relay_addr = {4'h1, `lc_cmd_rf_write}; // fuid don't care
rf_relay_loc = 8'ha; // don't care
state = tb_rf_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ|layer1.tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem read command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_read;
word_counter = 0;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem read command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_read;
word_counter = 5;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, error command test", task_counter);
$fdisplay(handle, "invalid mem write command");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
functional_id = `lc_cmd_mem_write;
word_counter = 0;
state = tb_arbitrary_cmd;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, stream", task_counter);
$fdisplay(handle, "cpu sends 1 word streaming data to layer 3's stream channel 0. (stream enable = 0, no mem operation)");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h5;
stream_channel = 0;
word_counter = 0;
state = tb_streaming;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, interrupt", task_counter);
$fdisplay(handle, "layer 1, interrupt vector 12, invalid interrupt command");
$fdisplay(handle, "-------------------------------------------------------------------------");
layer_number = 1;
int_vec = 12;
state = tb_single_interrupt;
@ (posedge n1_clr_int[int_vec]);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 1 default sys register bulk mem message control, set to maximum length 64");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h3;
rf_w_data = 24'hc0_003f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, rf write", task_counter);
$fdisplay(handle, "cpu configures layer 2 default sys register bulk mem message control, set to maximum length 64");
$fdisplay(handle, "-------------------------------------------------------------------------");
rf_addr = bulk_mem_ctrl_reg_idx;
dest_short_addr = 4'h4;
rf_w_data = 24'hc0_003f;
state = tb_single_rf_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem write", task_counter);
$fdisplay(handle, "cpu bulk writes random data to layer 1's mem address 0-63");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_addr = 0;
word_counter = 63;
state = tb_mem_write;
@ (posedge c0_tx_succ|c0_tx_fail);
#100000;
task_counter = task_counter + 1;
$fdisplay(handle, "\n-------------------------------------------------------------------------");
$fdisplay(handle, "task%d, mem read", task_counter);
$fdisplay(handle, "read layer 1's mem address 0, and write to layer 2's mem, address 0x0");
$fdisplay(handle, "-------------------------------------------------------------------------");
dest_short_addr = 4'h3;
mem_read_length = 63;
mem_addr = 0;
relay_addr = ((4'h4<<4) | `lc_cmd_mem_write);
mem_relay_loc = 30'd0;
state = tb_mem_read;
@ (posedge c0_tx_succ|c0_tx_fail);
@ (posedge layer1.tx_succ | layer1.tx_fail);
#500000;
$display("*************************************");
$display("************task0 complete***********");
$display("*************************************");
$finish;
end
endtask // task0
|
/*
* ravenna - a full example soc using picorv32 in x-fab xh018
*
* copyright (c) 2017 clifford wolf <clifford@clifford.at>
* copyright (c) 2018,2019 tim edwards <tim@efabless.com>
*
* permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* the software is provided "as is" and the author disclaims all warranties
* with regard to this software including all implied warranties of
* merchantability and fitness. in no event shall the author be liable for
* any special, direct, indirect, or consequential damages or any damages
* whatsoever resulting from loss of use, data or profits, whether in an
* action of contract, negligence or other tortious action, arising out of
* or in connection with the use or performance of this software.
*
*/
`timescale 1 ns / 1 ps
`ifndef lvs
// local files
`include "ravenna_soc.v"
`include "ravenna_spi.v"
`include "spi_slave.v"
// marketplace ip
// behavioral verilog components
`include "amux2_3v.v"
`include "amux4_3v.v"
`include "ls_3vx2.v"
// `include "xspramblp_4096x32_m8p.v"
// test: memory increased from 4x32 to 16x32. this represents memory that
// does not actually exist on the chip!
`include "sram_test.v"
`include "xcpf_136x32dp128_vd03.v"
`include "xnvr_136x32p128_vd01.v"
// pdk ip
// 3.3v digital standard cells
`include "d_cells_3v.v"
// 1.8v digital standard cells
`include "d_cells.v"
// 1.8v core / 3.3v i/o padframe cells
`include "io_cells_f3v.v"
// 3.3v core / 3.3v i/o padframe cells (isolate from 1.8v core cells!)
`include "io_cells_fc3v.v"
// 1.8v analog cells
`include "apllc03_1v8.v"
`include "acsoc04_1v8.v"
// 3.3v analog cells
`include "atmpc01_3v3.v"
`include "aadcc01_3v3.v"
`include "adacc01_3v3.v"
`include "aopac01_3v3.v"
`include "abgpc01_3v3.v"
`include "acmpc01_3v3.v"
`include "axtoc02_3v3.v"
`include "arcoc01_3v3.v"
`include "aregc01_3v3.v"
`include "aporc02_3v3.v"
`include "acsoc01_3v3.v"
`include "acsoc02_3v3.v"
`endif
// primitive devices (for lvs, and need (empty) model to prevent error on simulation).
`include "cmm5t.v"
`include "dn.v"
`include "dn3.v"
// ravenna, a picosoc implementation in x-fab xh018
module ravenna (
// padframe i/o
input wire real vdd3v3, // 3v power supply
output wire real vdd1v8, // 1.8v from regulator (for external cap)
input wire real vss, // ground
// crystal
input wire real xi, // crystal oscillator in
output wire real xo, // crystal oscillator out
input xclk, // external clock (pll bypass mode)
// housekeeping spi
input sdi, // spi controller data in
output sdo, // spi controller data out
input csb, // spi controller select
input sck, // spi controller clock
// uart
output ser_tx, // uart transmit
input ser_rx, // uart receive
// i2c
inout i2c_sda,
inout i2c_scl,
// spi master
input spi_sdi,
output spi_csb,
output spi_sck,
output spi_sdo,
// irq
input irq, // dedicated irq pin
// gpio
output [15:0] gpio, // general-purpose i/o
// flash
output flash_csb, // spi flash memory
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
// analog i/o
input wire real adc_high,
input wire real adc_low,
input wire real adc0_in,
input wire real adc1_in,
output wire real analog_out, // test analog port (multiplexed, buffered)
input wire real comp_inp,
input wire real comp_inn,
input wire real nvref_ext // nvram test analog port
);
wire dground;
wire dvdd;
wire reset;
wire resetn;
wire clk;
wire irq;
wire flash_io0_oeb, flash_io0_do, flash_io0_di;
wire flash_io1_oeb, flash_io1_do, flash_io1_di;
wire flash_io2_oeb, flash_io2_do, flash_io2_di;
wire flash_io3_oeb, flash_io3_do, flash_io3_di;
wire flash_clk_oeb;
wire [15:0] gpio_in_core;
wire [15:0] gpio_out_core;
wire irq_pin_core;
wire flash_csb_core;
wire flash_clk_core;
wire ser_rx_core;
wire ser_tx_core;
/* analog values represented by reals */
// wire real vdd3v3;
// wire real vdd1v8;
// wire real vss;
// wire real adc_high;
// wire real adc_low;
// wire real adc0_in;
// wire real adc1_in;
// wire real analog_out;
// wire real comp_inp;
// wire real comp_inn;
// declare bus widths
wire [15:0] gpio_pullupb;
wire [15:0] gpio_pulldownb;
wire [15:0] gpio_outenb;
wire [9:0] adc0_data;
wire [1:0] adc0_inputsrc;
wire [9:0] adc1_data;
wire [1:0] adc1_inputsrc;
wire [9:0] dac_value;
wire [1:0] comp_ninputsrc;
wire [1:0] comp_pinputsrc;
wire [7:0] spi_config;
wire [3:0] spi_pll_trim;
wire [11:0] spi_mfgr_id;
wire [7:0] spi_prod_id;
wire [3:0] spi_mask_rev;
// declare level-shifted signals
wire spi_trap_3v;
wire sck_core_lv;
wire spi_pll_vco_ena_lv;
wire spi_pll_cp_ena_lv;
wire spi_pll_bias_ena_lv;
wire [3:0] spi_pll_trim_lv;
wire spi_irq_lv;
wire spi_reset_lv;
wire spi_pll_bypass_lv;
wire [7:0] spi_config_lv;
wire spi_xtal_ena_lv;
wire spi_reg_ena_lv;
wire [11:0] spi_mfgr_id_lv;
wire [7:0] spi_prod_id_lv;
wire [3:0] spi_mask_rev_lv;
wire opamp_ena_3v;
wire opamp_bias_ena_3v;
wire bg_ena_3v;
wire comp_out_lv;
wire comp_ena_3v;
wire xtal_out_lv;
wire rcosc_ena_3v;
wire rcosc_out_lv;
wire reset_lv;
wire overtemp_ena_3v;
wire overtemp_lv;
/* padframe pads */
/* analog input/output pads */
apr00df adc0_pad (
.gndo(vss),
.gndr(vss),
.pad(adc0_in),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc1_pad (
.gndo(vss),
.gndr(vss),
.pad(adc1_in),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc_low_pad (
.gndo(vss),
.gndr(vss),
.pad(adc_low),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df adc_high_pad (
.gndo(vss),
.gndr(vss),
.pad(adc_high),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df ana_out_pad (
.gndo(vss),
.gndr(vss),
.pad(analog_out),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df comp_inn_pad (
.gndo(vss),
.gndr(vss),
.pad(comp_inn),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df comp_inp_pad (
.gndo(vss),
.gndr(vss),
.pad(comp_inp),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
apr00df nvref_ext_pad (
.gndo(vss),
.gndr(vss),
.pad(nvref_ext),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* power supplies (there are multiple pads that need to be represented) */
vddorpadf vddor_pad [4:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddor(vdd3v3)
);
vddpadf vdd_pad [1:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
vddpadfc vdd3_pad (
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
gndorpadf gndor_pad [6:0] (
.gndor(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
corneresdf padframe_corner [3:0] (
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* custom-designed power cut cell isolates the vdd3 and vdd buses */
powercutvdd3fc pwr_cut [1:0] (
.gndo(vss),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* implement bidirectional i/o with x-fab pads */
/* see: /ef/tech/xfab.3/efxh018d/libs.ref/verilog/io_cells_3v/io_cells_3v.v */
bbc4f flash_io_buf_3 (
.pad(flash_io3),
.en(flash_io3_oeb),
.a(flash_io3_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io3_di)
);
bbc4f flash_io_buf_2 (
.pad(flash_io2),
.en(flash_io2_oeb),
.a(flash_io2_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io2_di)
);
bbc4f flash_io_buf_1 (
.pad(flash_io1),
.en(flash_io1_oeb),
.a(flash_io1_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io1_di)
);
bbc4f flash_io_buf_0 (
.pad(flash_io0),
.en(flash_io0_oeb),
.a(flash_io0_do),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(flash_io0_di)
);
/* standalone spi controller (3v) */
icfc sck_buf (
.pad(sck),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(sck_core)
);
icfc csb_buf (
.pad(csb),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(csb_core)
);
icfc sdi_buf (
.pad(sdi),
.po(),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(sdi_core)
);
bt4fc sdo_buf (
.pad(sdo),
.en(sdo_enb),
.a(sdo_core),
.gndo(vss),
.gndr(vss),
.vdd3(vdd3v3),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* implement digital input on irq dedicated pin */
icf irq_buf (
.pad(irq),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(irq_pin_core)
);
/* implement digital input on ser_rx */
icf ser_rx_buf (
.pad(ser_rx),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(ser_rx_core)
);
/* implement digital outputs on ser_tx, i2c, leds, csb, and clk */
bt4f ser_tx_buf (
.pad(ser_tx),
.en(reset_lv),
.a(ser_tx_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bbcud4f i2c_scl_pad (
.a(i2c_scl_o),
.en(i2c_scl_oeb),
.gndo(vss),
.gndr(vss),
.pad(i2c_scl),
.pden(dground),
.pi(dground),
.po(),
.puen(dground), // to do: enable pu, optional 5, 10k?
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(i2c_scl_i)
);
bbcud4f i2c_sda_pad (
.a(i2c_sda_o),
.en(i2c_sda_oeb),
.gndo(vss),
.gndr(vss),
.pad(i2c_sda),
.pden(dground),
.pi(dground),
.po(),
.puen(dground), // to do: enable pu, optional 5, 10k?
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(i2c_sda_i)
);
// gpio is digital bidirectional buffer with selectable pull-up and pull-down
bbcud4f gpio_buf_15 (
.a(gpio_out_core[15]),
.en(gpio_outenb[15]),
.gndo(vss),
.gndr(vss),
.pad(gpio[15]),
.pden(gpio_pulldownb[15]),
.pi(dground),
.po(),
.puen(gpio_pullupb[15]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[15])
);
bbcud4f gpio_buf_14 (
.a(gpio_out_core[14]),
.en(gpio_outenb[14]),
.gndo(vss),
.gndr(vss),
.pad(gpio[14]),
.pden(gpio_pulldownb[14]),
.pi(dground),
.po(),
.puen(gpio_pullupb[14]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[14])
);
bbcud4f gpio_buf_13 (
.a(gpio_out_core[13]),
.en(gpio_outenb[13]),
.gndo(vss),
.gndr(vss),
.pad(gpio[13]),
.pden(gpio_pulldownb[13]),
.pi(dground),
.po(),
.puen(gpio_pullupb[13]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[13])
);
bbcud4f gpio_buf_12 (
.a(gpio_out_core[12]),
.en(gpio_outenb[12]),
.gndo(vss),
.gndr(vss),
.pad(gpio[12]),
.pden(gpio_pulldownb[12]),
.pi(dground),
.po(),
.puen(gpio_pullupb[12]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[12])
);
bbcud4f gpio_buf_11 (
.a(gpio_out_core[11]),
.en(gpio_outenb[11]),
.gndo(vss),
.gndr(vss),
.pad(gpio[11]),
.pden(gpio_pulldownb[11]),
.pi(dground),
.po(),
.puen(gpio_pullupb[11]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[11])
);
bbcud4f gpio_buf_10 (
.a(gpio_out_core[10]),
.en(gpio_outenb[10]),
.gndo(vss),
.gndr(vss),
.pad(gpio[10]),
.pden(gpio_pulldownb[10]),
.pi(dground),
.po(),
.puen(gpio_pullupb[10]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[10])
);
bbcud4f gpio_buf_9 (
.a(gpio_out_core[9]),
.en(gpio_outenb[9]),
.gndo(vss),
.gndr(vss),
.pad(gpio[9]),
.pden(gpio_pulldownb[9]),
.pi(dground),
.po(),
.puen(gpio_pullupb[9]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[9])
);
bbcud4f gpio_buf_8 (
.a(gpio_out_core[8]),
.en(gpio_outenb[8]),
.gndo(vss),
.gndr(vss),
.pad(gpio[8]),
.pden(gpio_pulldownb[8]),
.pi(dground),
.po(),
.puen(gpio_pullupb[8]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[8])
);
bbcud4f gpio_buf_7 (
.a(gpio_out_core[7]),
.en(gpio_outenb[7]),
.gndo(vss),
.gndr(vss),
.pad(gpio[7]),
.pden(gpio_pulldownb[7]),
.pi(dground),
.po(),
.puen(gpio_pullupb[7]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[7])
);
bbcud4f gpio_buf_6 (
.a(gpio_out_core[6]),
.en(gpio_outenb[6]),
.gndo(vss),
.gndr(vss),
.pad(gpio[6]),
.pden(gpio_pulldownb[6]),
.pi(dground),
.po(),
.puen(gpio_pullupb[6]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[6])
);
bbcud4f gpio_buf_5 (
.a(gpio_out_core[5]),
.en(gpio_outenb[5]),
.gndo(vss),
.gndr(vss),
.pad(gpio[5]),
.pden(gpio_pulldownb[5]),
.pi(dground),
.po(),
.puen(gpio_pullupb[5]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[5])
);
bbcud4f gpio_buf_4 (
.a(gpio_out_core[4]),
.en(gpio_outenb[4]),
.gndo(vss),
.gndr(vss),
.pad(gpio[4]),
.pden(gpio_pulldownb[4]),
.pi(dground),
.po(),
.puen(gpio_pullupb[4]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[4])
);
bbcud4f gpio_buf_3 (
.a(gpio_out_core[3]),
.en(gpio_outenb[3]),
.gndo(vss),
.gndr(vss),
.pad(gpio[3]),
.pden(gpio_pulldownb[3]),
.pi(dground),
.po(),
.puen(gpio_pullupb[3]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[3])
);
bbcud4f gpio_buf_2 (
.a(gpio_out_core[2]),
.en(gpio_outenb[2]),
.gndo(vss),
.gndr(vss),
.pad(gpio[2]),
.pden(gpio_pulldownb[2]),
.pi(dground),
.po(),
.puen(gpio_pullupb[2]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[2])
);
bbcud4f gpio_buf_1 (
.a(gpio_out_core[1]),
.en(gpio_outenb[1]),
.gndo(vss),
.gndr(vss),
.pad(gpio[1]),
.pden(gpio_pulldownb[1]),
.pi(dground),
.po(),
.puen(gpio_pullupb[1]),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.y(gpio_in_core[1])
);
bbcud4f gpio_buf_0 (
.a(gpio_out_core[0]),
.en(gpio_outenb[0]),
.gndo(vss),
.gndr(vss),
.pad(gpio[0]),
.pden(gpio_pulldownb[0]),
.pi(dground),
.po(),
.puen(gpio_pullupb[0]),
.vdd(vdd1v8),
.vddr(vdd3v3),
.vddo(vdd3v3),
.y(gpio_in_core[0])
);
bt4f flash_csb_buf (
.pad(flash_csb),
.en(flash_csb_oeb),
.a(flash_csb_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f flash_clk_buf (
.pad(flash_clk),
.en(flash_clk_oeb),
.a(flash_clk_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
icf clk_ext_buf ( // external digital clock for pll bypass mode
.pad(xclk),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(clk_ext_core)
);
icf spi_master_sdi_buf (
.pad(spi_sdi),
.po(),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3),
.pi(dground),
.y(spi_sdi_core)
);
bt4f spi_master_csb_buf (
.pad(spi_csb),
.en(reset_lv),
.a(spi_csb_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f spi_master_sck_buf (
.pad(spi_sck),
.en(reset_lv),
.a(spi_sck_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
bt4f spi_master_sdo_buf (
.pad(spi_sdo),
.en(spi_sdoenb),
.a(spi_sdo_core),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* to avoid antenna violations, each digital pad with inputs a */
/* and en, and gpio pads with puen and pden, have a diode with */
/* minimum area on each of the input pins. */
dn #(
.area(2.025e-13)
) gpio_out_core_tie [15:0] (
.pos(vss),
.neg(gpio_out_core)
);
dn #(
.area(2.025e-13)
) gpio_outenb_tie [15:0] (
.pos(vss),
.neg(gpio_outenb)
);
dn #(
.area(2.025e-13)
) gpio_pulldownb_tie [15:0] (
.pos(vss),
.neg(gpio_pulldownb)
);
dn #(
.area(2.025e-13)
) gpio_pullupb_tie [15:0] (
.pos(vss),
.neg(gpio_pullupb)
);
dn #(
.area(2.025e-13)
) flash_io0_oeb_tie (
.pos(vss),
.neg(flash_io0_oeb)
);
dn #(
.area(2.025e-13)
) flash_io0_do_tie (
.pos(vss),
.neg(flash_io0_do)
);
dn #(
.area(2.025e-13)
) flash_io1_oeb_tie (
.pos(vss),
.neg(flash_io1_oeb)
);
dn #(
.area(2.025e-13)
) flash_io1_do_tie (
.pos(vss),
.neg(flash_io1_do)
);
dn #(
.area(2.025e-13)
) flash_io2_oeb_tie (
.pos(vss),
.neg(flash_io2_oeb)
);
dn #(
.area(2.025e-13)
) flash_io2_do_tie (
.pos(vss),
.neg(flash_io2_do)
);
dn #(
.area(2.025e-13)
) flash_io3_oeb_tie (
.pos(vss),
.neg(flash_io3_oeb)
);
dn #(
.area(2.025e-13)
) flash_io3_do_tie (
.pos(vss),
.neg(flash_io3_do)
);
dn #(
.area(2.025e-13)
) reset_lv_tie [2:0] (
.pos(vss),
.neg(reset_lv)
);
dn #(
.area(2.025e-13)
) ser_tx_core_tie (
.pos(vss),
.neg(ser_tx_core)
);
dn #(
.area(2.025e-13)
) i2c_scl_o_tie (
.pos(vss),
.neg(i2c_scl_o)
);
dn #(
.area(2.025e-13)
) i2c_scl_oeb_tie (
.pos(vss),
.neg(i2c_scl_oeb)
);
dn #(
.area(2.025e-13)
) i2c_sda_o_tie (
.pos(vss),
.neg(i2c_sda_o)
);
dn #(
.area(2.025e-13)
) i2c_sda_oeb_tie (
.pos(vss),
.neg(i2c_sda_oeb)
);
dn #(
.area(2.025e-13)
) flash_csb_oeb_tie (
.pos(vss),
.neg(flash_csb_oeb)
);
dn #(
.area(2.025e-13)
) flash_csb_core_tie (
.pos(vss),
.neg(flash_csb_core)
);
dn #(
.area(2.025e-13)
) flash_clk_oeb_tie (
.pos(vss),
.neg(flash_clk_oeb)
);
dn #(
.area(2.025e-13)
) flash_clk_core_tie (
.pos(vss),
.neg(flash_clk_core)
);
dn #(
.area(2.025e-13)
) spi_csb_core_tie (
.pos(vss),
.neg(spi_csb_core)
);
dn #(
.area(2.025e-13)
) spi_sck_core_tie (
.pos(vss),
.neg(spi_sck_core)
);
dn #(
.area(2.025e-13)
) spi_sdoenb_tie (
.pos(vss),
.neg(spi_sdoenb)
);
dn #(
.area(2.025e-13)
) spi_sdo_core_tie (
.pos(vss),
.neg(spi_sdo_core)
);
/* implement mim capacitors. layout uses 20x20um devices, so a=400um^2, p=80um */
cmm5t #(
.a(4e-10),
.p(8e-05)
) cap_area_fill_0 [468:0] (
.top(vdd1v8),
.bottom(vss),
.subs(vss)
);
cmm5t #(
.a(4e-10),
.p(8e-05)
) cap_area_fill_1 [276:0] (
.top(vdd3v3),
.bottom(vss),
.subs(vss)
);
/* each cap area has an associated tie-down diode */
dn3 #(
.area(2.25e-12)
) vdd3v3_tie [2:0] (
.pos(vss),
.neg(vdd3v3)
);
dn #(
.area(2.25e-12)
) vdd1v8_tie [4:0] (
.pos(vss),
.neg(vdd1v8)
);
wire [3:0] ram_wenb;
// wire [11:0] ram_addr;
wire [13:0] ram_addr;
wire [31:0] ram_wdata;
wire [31:0] ram_rdata;
wire [7:0] nvram_addr;
wire [31:0] nvram_wdata;
wire [31:0] nvram_rdata;
// nvram test mode from housekeeping spi
wire [3:0] tm_nvcp;
wire [3:0] tm_nvcp_lv;
/* note: hardwired digital 0 disallowed in structural netlist. */
/* must generate from tie-low standard cell. */
logic0_3v ground_digital [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(dground)
);
logic1 vdd_digital (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.q(dvdd)
);
/* sck_core is also input to ravenna_soc but needs to be shifted to 1.8v */
/* level shift down */
bu_3vx2 sck_core_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(sck_core),
.q(sck_core_lv)
);
/* due to lack of any spi configuration behavior on the 1st generation */
/* raven chip, the spi_config is just grounded. however, this requires */
/* tie-low inputs. */
logic0_3v spi_config_zero [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(spi_config)
);
/* spi internal registers to be read from memory mapped i/o must also */
/* be shifted down. those that are sent to the pll already have */
/* shifted versions. */
bu_3vx2 spi_config_level [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_config),
.q(spi_config_lv)
);
bu_3vx2 spi_xtal_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_xtal_ena),
.q(spi_xtal_ena_lv)
);
bu_3vx2 spi_reg_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_reg_ena),
.q(spi_reg_ena_lv)
);
/* this is a spare level shift buffer */
bu_3vx2 spare_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(dground),
.q(spare_dg)
);
bu_3vx2 spi_mfgr_id_level [11:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_mfgr_id),
.q(spi_mfgr_id_lv)
);
bu_3vx2 spi_prod_id_level [7:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_prod_id),
.q(spi_prod_id_lv)
);
bu_3vx2 spi_mask_rev_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_mask_rev),
.q(spi_mask_rev_lv)
);
bu_3vx2 spi_reset_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_reset),
.q(spi_reset_lv)
);
bu_3vx2 spi_pll_bypass_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_bypass),
.q(spi_pll_bypass_lv)
);
ravenna_soc soc (
`ifdef lvs
.gnd (vss ),
.vdd (vdd1v8 ),
`endif
.pll_clk (pll_clk ),
.ext_clk (clk_ext_core),
.ext_clk_sel (spi_pll_bypass_lv),
.reset (reset_lv ),
.ext_reset (spi_reset_lv ),
.pass_thru (pass_thru_lv),
.pass_thru_csb (pass_thru_csb_lv),
.pass_thru_sck (pass_thru_sck_lv),
.pass_thru_sdi (pass_thru_sdi_lv),
.pass_thru_sdo (pass_thru_sdo),
.ram_wenb (ram_wenb ),
.ram_addr (ram_addr ),
.ram_wdata (ram_wdata ),
.ram_rdata (ram_rdata ),
.nvram_ena (nvram_ena ),
.nvram_wen (nvram_wen ),
.nvram_addr (nvram_addr ),
.nvram_wdata (nvram_wdata ),
.nvram_rdata (nvram_rdata ),
.nvram_hs (nvram_hs ),
.nvram_hr (nvram_hr ),
.nvram_mem_all (nvram_mem_all ),
.nvram_mem_sel (nvram_mem_sel ),
.nvram_clk (nvram_clk ),
.nvram_rdy (nvram_rdy ),
.gpio_out (gpio_out_core),
.gpio_in (gpio_in_core),
.gpio_pullupb (gpio_pullupb),
.gpio_pulldownb (gpio_pulldownb),
.gpio_outenb (gpio_outenb),
.adc0_ena (adc0_ena),
.adc0_convert (adc0_convert),
.adc0_data (adc0_data),
.adc0_done (adc0_done),
.adc0_clk (adc0_clk),
.adc0_inputsrc (adc0_inputsrc),
.adc1_ena (adc1_ena),
.adc1_convert (adc1_convert),
.adc1_data (adc1_data),
.adc1_done (adc1_done),
.adc1_clk (adc1_clk),
.adc1_inputsrc (adc1_inputsrc),
.dac_ena (dac_ena),
.dac_value (dac_value),
.analog_out_sel (analog_out_sel),
.opamp_ena (opamp_ena),
.opamp_bias_ena (opamp_bias_ena),
.bg_ena (bg_ena),
.comp_ena (comp_ena),
.comp_ninputsrc (comp_ninputsrc),
.comp_pinputsrc (comp_pinputsrc),
.rcosc_ena (rcosc_ena),
.overtemp_ena (overtemp_ena),
.overtemp (overtemp_lv),
.rcosc_in (rcosc_out_lv),
.xtal_in (xtal_div8),
.comp_in (comp_out_lv),
.spi_sck (sck_core_lv),
.spi_ro_config (spi_config_lv),
.spi_ro_xtal_ena (spi_xtal_ena_lv),
.spi_ro_reg_ena (spi_reg_ena_lv),
.spi_ro_pll_cp_ena (spi_pll_cp_ena_lv),
.spi_ro_pll_vco_ena (spi_pll_vco_ena_lv),
.spi_ro_pll_bias_ena (spi_pll_bias_ena_lv),
.spi_ro_pll_trim (spi_pll_trim_lv),
.spi_ro_mfgr_id (spi_mfgr_id_lv),
.spi_ro_prod_id (spi_prod_id_lv),
.spi_ro_mask_rev (spi_mask_rev_lv),
.ser_tx (ser_tx_core ),
.ser_rx (ser_rx_core ),
.scl_pad_i (i2c_scl_i),
.scl_pad_o (i2c_scl_o),
.scl_padoeb (i2c_scl_oeb),
.sda_pad_i (i2c_sda_i),
.sda_pad_o (i2c_sda_o),
.sda_padoeb (i2c_sda_oeb),
.spi_master_sdi (spi_sdi_core),
.spi_master_csb (spi_csb_core),
.spi_master_sck (spi_sck_core),
.spi_master_sdo (spi_sdo_core),
.spi_master_sdoenb (spi_sdoenb),
.irq_pin (irq_pin_core),
.irq_spi (spi_irq_lv),
.trap (spi_trap),
.flash_csb (flash_csb_core),
.flash_clk (flash_clk_core),
.flash_csb_oeb (flash_csb_oeb),
.flash_clk_oeb (flash_clk_oeb),
.flash_io0_oeb (flash_io0_oeb),
.flash_io1_oeb (flash_io1_oeb),
.flash_io2_oeb (flash_io2_oeb),
.flash_io3_oeb (flash_io3_oeb),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
/* level shift up */
ls_3vx2 spi_trap_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(spi_trap),
.q(spi_trap_3v)
);
ls_3vx2 pass_thru_sdo_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(pass_thru_sdo),
.q(pass_thru_sdo_3v)
);
/* metal programming for mask revision */
wire [3:0] pground;
wire [3:0] ppower;
logic0_3v prog_ground [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(pground)
);
logic1_3v prog_power [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.q(ppower)
);
/* standalone spi (3v)*/
/* operates at 3v so that it can control the xtal oscillator, pll, */
/* and 1.8v regulator, which cannot be changed from the cpu */
/* without potentially killing it. */
ravenna_spi spi (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.rst(reset),
.sck(sck_core),
.sdi(sdi_core),
.csb(csb_core),
.sdo(sdo_core),
.sdo_enb(sdo_enb),
.xtal_ena(spi_xtal_ena),
.reg_ena(spi_reg_ena),
.pll_vco_ena(spi_pll_vco_ena),
.pll_cp_ena(spi_pll_cp_ena),
.pll_vco_in(spi_pll_vco_in),
.pll_bias_ena(spi_pll_bias_ena),
.pll_trim(spi_pll_trim),
.pll_bypass(spi_pll_bypass),
.tm_nvcp(tm_nvcp),
.irq(spi_irq),
.reset(spi_reset),
.trap(spi_trap_3v),
.pass_thru_reset (pass_thru),
.pass_thru_csb (pass_thru_csb),
.pass_thru_sck (pass_thru_sck),
.pass_thru_sdi (pass_thru_sdi),
.pass_thru_sdo (pass_thru_sdo_3v),
.mask_rev_in(pground), // metal programmed
.mfgr_id(spi_mfgr_id),
.prod_id(spi_prod_id),
.mask_rev(spi_mask_rev)
);
/* level shift down. unfortunately, pll is in 1.8v only or */
/* else this would be easier. */
bu_3vx2 pass_thru_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru),
.q(pass_thru_lv)
);
bu_3vx2 pass_thru_csb_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_csb),
.q(pass_thru_csb_lv)
);
bu_3vx2 pass_thru_sdi_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_sdi),
.q(pass_thru_sdi_lv)
);
bu_3vx2 pass_thru_sck_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(pass_thru_sck),
.q(pass_thru_sck_lv)
);
bu_3vx2 pll_vco_in_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_vco_in),
.q(spi_pll_vco_in_lv)
);
bu_3vx2 pll_vco_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_vco_ena),
.q(spi_pll_vco_ena_lv)
);
bu_3vx2 pll_cp_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_cp_ena),
.q(spi_pll_cp_ena_lv)
);
bu_3vx2 pll_trim_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_trim),
.q(spi_pll_trim_lv)
);
bu_3vx2 pll_bias_ena_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_pll_bias_ena),
.q(spi_pll_bias_ena_lv)
);
bu_3vx2 spi_irq_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(spi_irq),
.q(spi_irq_lv)
);
/* nvram module and charge pump */
/* list of wires passed between nvram and charge pump */
wire nvram_busynvc;
wire [15:0] nvram_trim;
wire nvram_clki;
wire nvram_vsestart;
wire nvram_rclt;
wire nvram_mem1_ent;
wire nvram_mem2_ent;
wire nvram_clk4;
wire nvram_vse1;
wire nvram_vse2;
wire nvram_vsebusy;
wire nvram_vcore;
wire [3:0] nvram_tm_nvcpi;
xnvr_136x32p128_vd01 nvram (
`ifdef lvs
.vdd18m(vdd1v8),
.vssm(vss),
`endif
.busynvc(nvram_busynvc),
.clki(nvram_clki),
.dout(nvram_rdata),
.dso(),
.mem1_ent(nvram_mem1_ent),
.mem2_ent(nvram_mem2_ent),
.rclt(nvram_rclt),
.rdy(nvram_rdy),
.tm_nvcpi(nvram_tm_nvcpi),
.trim(nvram_trim),
.vsestart(nvram_vsestart),
.a(nvram_addr),
.ce(nvram_ena),
.clk(nvram_clk),
.clk4(nvram_clk4),
.din(nvram_wdata),
.drstn(dvdd),
.dsclk(dground),
.dsi(dground),
.dup(dground),
.hr(nvram_hr),
.hs(nvram_hs),
.mem_allc(nvram_mem_all),
.mem_sel(nvram_mem_sel),
.pein(dground),
.por(reset_lv),
.tm_nvcp(tm_nvcp_lv),
.vcore(nvram_vcore),
.vse1(nvram_vse1),
.vse2(nvram_vse2),
.vsebusy(nvram_vsebusy),
.we(nvram_wen)
);
xcpf_136x32dp128_vd03 nvram_cp (
`ifdef lvs
.vdd18m(vdd1v8),
.vdd33m(vdd3v3),
.vssm(vss),
`endif
.clk4(nvram_clk4),
.clk4m(),
.vcore(nvram_vcore),
.vse1(nvram_vse1),
.vse2(nvram_vse2),
.vsebusy(nvram_vsebusy),
.busynvc(nvram_busynvc),
.clki(nvram_clki),
.mem1_ent(nvram_mem1_ent),
.mem2_ent(nvram_mem2_ent),
.nvref_ext(nvref_ext),
.por(reset_lv),
.rclt(nvram_rclt),
.tm_nvcpi(nvram_tm_nvcpi),
.trim(nvram_trim),
.vsestart(nvram_vsestart)
);
/* level shift down */
bu_3vx2 tm_nvcp_level [3:0] (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(tm_nvcp),
.q(tm_nvcp_lv)
);
/* ram modules (32 bits x 4k words) */
wire [31:0] ram_wenb_bits;
/* split the four byte-wide write-enable lines into the x-fab sram bit-wide write-enable lines */
assign ram_wenb_bits[31:24] = {ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3], ram_wenb[3]};
assign ram_wenb_bits[23:16] = {ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2], ram_wenb[2]};
assign ram_wenb_bits[15:8] = {ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1], ram_wenb[1]};
assign ram_wenb_bits[7:0] = {ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0], ram_wenb[0]};
// xspramblp_4096x32_m8p xfab_mem0 (
xspramblp_16384x32_m8p xfab_mem0 (
`ifdef lvs
.vssm(vss),
.vdd18m(vdd1v8),
`endif
.q(ram_rdata),
.d(ram_wdata),
.a(ram_addr),
.clk(pll_clk),
.cen(reset_lv), // sram enable
.wen(ram_wenb_bits), // one bit per byte
.rdy() // unused
);
/* analog components (multiplexers) */
wire real adc0_input;
wire real adc1_input;
wire real comp_ninput;
wire real comp_pinput;
wire real opamp_input;
wire real dac_out;
wire real bandgap_out;
amux4_3v adc0_input_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(adc0_in),
.ain2(vdd1v8),
.ain3(dac_out),
.ain4(vss),
.aout(adc0_input),
.sel(adc0_inputsrc)
);
amux4_3v adc1_input_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(adc1_in),
.ain2(vdd3v3),
.ain3(bandgap_out),
.ain4(comp_inp),
.aout(adc1_input),
.sel(adc1_inputsrc)
);
amux4_3v comp_ninput_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(comp_inn),
.ain2(dac_out),
.ain3(bandgap_out),
.ain4(vdd1v8),
.aout(comp_ninput),
.sel(comp_ninputsrc)
);
amux4_3v comp_pinput_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(comp_inp),
.ain2(dac_out),
.ain3(bandgap_out),
.ain4(vdd1v8),
.aout(comp_pinput),
.sel(comp_pinputsrc)
);
amux2_3v analog_out_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(dac_out),
.ain2(bandgap_out),
.aout(opamp_input),
.sel(analog_out_sel)
);
/* adc 0 */
aadcc01_3v3 adc0 (
.vdd(vdd1v8),
.vin(adc0_input),
.clk(adc0_clk),
.vrefh(adc_high),
.en(adc0_ena),
.vssa(vss),
.vdda(vdd3v3),
.vrefl(adc_low),
.start(adc0_convert),
.eoc(adc0_done),
.d(adc0_data),
.vss(vss)
);
/* adc 1 */
aadcc01_3v3 adc1 (
.vdd(vdd1v8),
.vin(adc1_input),
.clk(adc1_clk),
.vrefh(adc_high),
.en(adc1_ena),
.vssa(vss),
.vdda(vdd3v3),
.vrefl(adc_low),
.start(adc1_convert),
.eoc(adc1_done),
.d(adc1_data),
.vss(vss)
);
/* dac */
adacc01_3v3 dac (
.out(dac_out),
.d(dac_value),
.en(dac_ena),
.vdd(vdd1v8),
.vdda(vdd3v3),
.vrefh(adc_high),
.vrefl(adc_low),
.vss(vss),
.vssa(vss)
);
wire real bias3u;
/* opamp (analog output buffer) */
aopac01_3v3 opamp (
.out(analog_out),
.en(opamp_ena_3v),
.ib(bias3u),
.inn(analog_out),
.inp(opamp_input),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift up */
ls_3vx2 opamp_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(opamp_ena),
.q(opamp_ena_3v)
);
ls_3vx2 opamp_bias_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(opamp_bias_ena),
.q(opamp_bias_ena_3v)
);
/* biasing for op-amp */
acsoc02_3v3 opamp_bias (
.en(opamp_bias_ena_3v),
.vdda(vdd3v3),
.vssa(vss),
.cs_8u(),
.cs_4u(),
.cs_2u(bias3u),
.cs_1u(bias3u)
);
/* level shift up */
ls_3vx2 bg_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(bg_ena),
.q(bg_ena_3v)
);
/* bandgap */
abgpc01_3v3 bandgap (
.en(bg_ena_3v),
.vbgp(bandgap_out),
.vssa(vss),
.vdda(vdd3v3),
.vbgvtn()
);
wire real bias400n;
/* comparator */
acmpc01_3v3 comparator (
.out(comp_out),
.en(comp_ena_3v),
.ibn(bias400n),
.inn(comp_ninput), // multiplexed
.inp(comp_pinput), // multiplexed
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 comp_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(comp_out),
.q(comp_out_lv)
);
/* level shift up */
ls_3vx2 comp_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(comp_ena),
.q(comp_ena_3v)
);
/* bias for comparator */
acsoc01_3v3 comp_bias (
.en(comp_ena_3v),
.vssa(vss),
.vdda(vdd3v3),
.cs0_200n(bias400n),
.cs1_200n(bias400n),
.cs2_200n(),
.cs3_200n()
);
/* crystal oscillator (5-12.5 mhz) */
axtoc02_3v3 xtal (
.clk(xtal_out),
.xi(xi),
.xo(xo),
.en(spi_xtal_ena),
.gndo(vss),
.gndr(vss),
.vdd(vdd1v8),
.vddo(vdd3v3),
.vddr(vdd3v3)
);
/* level shift down (because xtal osc is 3v but pll is 1.8v) */
bu_3vx2 xtal_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(xtal_out),
.q(xtal_out_buf)
);
/* buffering of xtal_out clock */
bux4 bux4_1 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(xtal_out_buf),
.q(xtal_out_lv)
);
/* soc core uses xtal_in to drive adc which has a max */
/* clock rate of 2mhz. since crystal clock is */
/* typically 10 to 12.5mhz, divide it by 8. */
dfrx2 clock_div2 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div2_buf),
.c(xtal_out_lv),
.qn(xtal_div2_buf),
.q(xtal_div2)
);
dfrx2 clock_div4 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div4_buf),
.c(xtal_div2),
.qn(xtal_div4_buf),
.q(xtal_div4)
);
dfrx2 clock_div8 (
`ifdef lvs
.gnd(vss),
.vdd(vdd1v8),
`endif
.d(xtal_div8_buf),
.c(xtal_div4),
.qn(xtal_div8_buf),
.q(xtal_div8)
);
wire real bias10u, bias5u, pll_vco_in;
/* multiplexer for connecting vco_in */
/* note that this multiplexer is 3.3v. it is the */
/* responsibility of the hardware connected to the */
/* comp_inp pin to limit vco_in to 1.2v max. */
amux2_3v vco_in_mux (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.ain1(vss),
.ain2(comp_inp),
.aout(pll_vco_in),
.sel(spi_pll_vco_in_lv)
);
/* 8x clock multiplier pll (note: ip from a_cells_1v8) */
apllc03_1v8 pll (
.vssd(vss),
.en_vco(spi_pll_vco_ena_lv),
.en_cp(spi_pll_cp_ena_lv),
.b_vco(bias5u),
.b_cp(bias10u),
.vssa(vss),
.vddd(vdd1v8),
.vdda(vdd1v8),
.vco_in(pll_vco_in),
.clk(clk), // output (fast) clock
.ref(xtal_out_lv), // input (slow) clock
.b(spi_pll_trim_lv) // 4-bit trim
);
/* buffering of pll clock */
bux4 bux4_0 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(clk),
.q(clk_buf)
);
bux12 bux12_1 (
`ifdef lvs
.vdd(vdd1v8),
.gnd(vss),
`endif
.a(clk_buf),
.q(pll_clk)
);
/* biasing for pll */
acsoc04_1v8 pll_bias (
.en(spi_pll_bias_ena_lv),
.vdda(vdd1v8),
.vssa(vss),
.cs3_8u(bias10u),
.cs2_4u(bias5u),
.cs1_2u(bias10u),
.cs0_1u(bias5u)
);
/* level shift up */
ls_3vx2 rcosc_ena_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(rcosc_ena),
.q(rcosc_ena_3v)
);
/* rc oscillator */
arcoc01_3v3 rcosc (
.clk(rcosc_out),
.en(rcosc_ena_3v),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 rcosc_out_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(rcosc_out),
.q(rcosc_out_lv)
);
/* buffering for regulator enables. this is mostly to */
/* isolate an lvs error, but no harm comes of individually */
/* buffering each regulator's enable lines. */
bu_3vx2 reg_ena_buf0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg0_ena)
);
bu_3vx2 reg_ena_buf1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg1_ena)
);
in_3vx2 reg_enb_buf0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg0_enb)
);
in_3vx2 reg_enb_buf1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(spi_reg_ena),
.q(reg1_enb)
);
/* reg1_ena/b has antenna taps due to the length of the wires */
antennacellnp2_3v antennacellnp2_3v_0 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(reg1_ena)
);
antennacellnp2_3v antennacellnp2_3v_1 (
`ifdef lvs
.gnd(vss),
.vdd3(vdd3v3),
`endif
.a(reg1_enb)
);
/* note: iverilog does not like two devices connected in */
/* parallel to one real-valued driver, so one device is */
/* removed for simulation (hack solution). */
/* 1.8v regulator (x2) */
aregc01_3v3 regulator1 (
.out(vdd1v8),
.vin3(vdd3v3),
.gndo(vss),
.en(reg0_ena),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3),
.vdd(vdd1v8),
.enb(reg0_enb)
);
`ifdef lvs
aregc01_3v3 regulator2 (
.out(vdd1v8),
.vin3(vdd3v3),
.gndo(vss),
.en(reg1_ena),
.gndr(vss),
.vddo(vdd3v3),
.vddr(vdd3v3),
.vdd(vdd1v8),
.enb(reg1_enb)
);
`endif
/* power-on-reset */
aporc02_3v3 por (
.por(reset),
.porb(resetn),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 por_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(reset),
.q(reset_lv)
);
/* level shift up */
ls_3vx2 temp_level (
.vdd3v3(vdd3v3),
.vdd1v8(vdd1v8),
.vssa(vss),
.a(overtemp_ena),
.q(overtemp_ena_3v)
);
/* over-temperature alarm */
atmpc01_3v3 temp (
.ovt(overtemp),
.en(overtemp_ena_3v),
.vdda(vdd3v3),
.vssa(vss)
);
/* level shift down */
bu_3vx2 overtemp_level (
`ifdef lvs
.gnd(vss),
.vdd3(vdd1v8),
`endif
.a(overtemp),
.q(overtemp_lv)
);
endmodule // ravenna
|
/*
* Titor - System - PS/2 controller wrapper
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_WRAPPER_PS2
`else
`define INC_WRAPPER_PS2
`timescale 1 ns / 100 ps
module PS2MemoryWrapper(
dout,
din,
address,
size,
read_write,
enable,
interrupt,
ps2_clock,
ps2_data,
reset,
clk
);
`include "definition/Definition.v"
output reg [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg interrupt;
inout ps2_clock;
inout ps2_data;
wire [BYTE-1:0] rx_data;
input reset;
input clk;
reg [WORD-1:0] key_normal;
wire rx_done;
// Memory interface
always @(posedge clk) begin
if(reset) begin
dout <= 0;
end
else if((address==0) && (enable==ENABLE) && (read_write==READ)) begin
dout <= key_normal;
end
end
// Local definitions
localparam UNSPECIAL = 0;
localparam SPECIAL = 224;
localparam EXTRA = 255;
localparam BREAK = 240;
// Key disambiguation
reg ignore;
reg [WORD-1:0] specialc;
reg breakc;
// Key translation
reg [WORD-1:0] try_normalized;
reg try_interrupt;
reg try_ignore;
always @(posedge clk) begin
if(reset) begin
ignore <= 0;
specialc <= UNSPECIAL;
breakc <= 0;
end
else begin
if(!rx_done) begin
ignore <= ignore;
specialc <= specialc;
breakc <= breakc;
end
else begin
case(rx_data)
SPECIAL: begin
ignore <= ignore;
specialc <= SPECIAL;
breakc <= 0;
end
EXTRA: begin
ignore <= ignore;
specialc <= EXTRA;
breakc <= 0;
end
BREAK: begin
ignore <= ignore;
specialc <= specialc;
breakc <= 1;
end
default: begin
ignore <= try_ignore;
specialc <= UNSPECIAL;
breakc <= 0;
end
endcase
end
end
end
// In the lookup table determine the normalized key
always @(*) begin
if(!rx_done) begin
try_normalized <= 0;
try_interrupt <= 0;
try_ignore <= 0;
end
else begin
`include "meta-include/Scan-Code.meta.v"
end
end
// Combine all the information and send an interrupt if necessary
always @(posedge clk) begin
if(reset) begin
interrupt <= 0;
key_normal <= 0;
end
else if(try_interrupt) begin
interrupt <= !ignore;
key_normal <= (breakc<<(WORD-1)) | try_normalized;
end
else begin
interrupt <= 0;
key_normal <= key_normal;
end
end
PS2 hardware(
.ps2_clock(ps2_clock),
.ps2_data(ps2_data),
.rx_data(rx_data),
.rx_done(rx_done),
.reset(reset),
.clk(clk)
);
endmodule
`endif
|
/*copyright 2018-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`define sout tb.uart0_sout
`define sin tb.uart0_sin
module uart_mnt();
//#############################################
// create baud_clk
//#############################################
parameter fcpu = 1000000000/`clk_period;
parameter baud = 19200;
parameter cycle_cunt=fcpu/(baud*16) - 1;
reg[31:0] div_counter;
always @(posedge `clk or negedge `rst_b)
begin
if(!`rst_b)
begin
div_counter[31:0]<=cycle_cunt;
end
else if(div_counter[31:0]==32'b0)
begin
div_counter[31:0]<=cycle_cunt;
end
else
begin
div_counter[31:0]<=div_counter[31:0] - 1'b1;
end
end
assign baud_clk=(div_counter[31:0]>=(cycle_cunt/2))?0:1;
//#############################################
// receive data
//#############################################
reg sout_flop;
reg trig_count_en;
reg [4:0] trig_count;
reg shift_en;
reg [3:0] shift_count;
reg [3:0] capture_time;
reg[7:0] pack_data;
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
sout_flop<=1'b0;
else
sout_flop<=`sout;
end
assign trig = sout_flop && !`sout && !shift_en;
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
trig_count_en<=1'b0;
else if(trig)
trig_count_en<=1'b1;
else if(shift_en)
trig_count_en<=1'b0;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
trig_count[4:0]<=5'b0;
else if(!trig_count_en)
trig_count[4:0]<=5'b0;
else if(trig_count_en)
trig_count[4:0]<= trig_count[4:0] + 1;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
shift_en<=1'b0;
else if(trig_count[4:0]==22)
shift_en<=1'b1;
else if(capture_time[3:0]==8)
shift_en<=1'b0;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
shift_count[3:0]<=4'b0;
else if(trig)
shift_count[3:0]<=4'b0;
else if(shift_en)
shift_count[3:0]<= shift_count[3:0] + 1;
end
assign capture_en = shift_en && (shift_count[3:0]==0);
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
capture_time[3:0]<=4'b0;
else if(trig)
capture_time[3:0]<=4'b0;
else if(capture_en)
capture_time[3:0]<= capture_time[3:0] + 1;
end
always @(posedge baud_clk or negedge `rst_b)
begin
if(!`rst_b)
begin
pack_data[7:0]<=8'b0;
end
else if (capture_en)
begin
pack_data[7:0]<={`sout,pack_data[7:1]};
end
else
begin
pack_data[7:0]<=pack_data[7:0];
end
end
assign print_en = (capture_time[3:0]==8) && shift_en;
//#############################################
// print log
//#############################################
integer output_file;
initial
begin
output_file=$fopen("uart_output.inf","w");
end
always @(posedge baud_clk )
begin
if(print_en)
begin
$fwrite(output_file,"%c",pack_data[7:0]);
$write("\033[0;31m%c\033[0m",pack_data[7:0]);
end
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_streaming #(
parameter PURPOSE = 0,
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// JTAG Signals
input wire tck,
input wire tdi,
output reg tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire reset_n,
// Source Signals
output wire [7:0] source_data,
output wire source_valid,
// Sink Signals
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
// Clock Debug Signals
input wire clock_to_sample,
input wire reset_to_sample,
// Resetrequest signal
output reg resetrequest,
// Debug reset and management channel
output wire debug_reset,
output reg mgmt_valid,
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output reg mgmt_data
);
// function to calculate log2, floored.
function integer flog2;
input [31:0] Depth;
integer i;
begin
i = Depth;
if ( i <= 0 ) flog2 = 0;
else begin
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
i = i >> 1;
end
end
endfunction // flog2
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// IR values determine the operating modes
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
// Operating Modes:
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
// Loopback - To become a JTAG loopback with a bypass register
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
// Control - To set the offset of bit-padding and to do a reset request
// Mgmt - Send management commands (resets mostly) to agents
localparam IRWIDTH = 3;
// State machine encoding for write_state
localparam ST_BYPASS = 'h0;
localparam ST_HEADER_1 = 'h1;
localparam ST_HEADER_2 = 'h2;
localparam ST_WRITE_DATA = 'h3;
// State machine encoding for read_state
localparam ST_HEADER = 'h0;
localparam ST_PADDED = 'h1;
localparam ST_READ_DATA = 'h2;
reg [1:0] write_state = ST_BYPASS;
reg [1:0] read_state = ST_HEADER;
reg [ 7:0] dr_data_in = 'b0;
reg [ 7:0] dr_data_out = 'b0;
reg dr_loopback = 'b0;
reg [ 2:0] dr_debug = 'b0;
reg [10:0] dr_info = 'b0;
reg [ 8:0] dr_control = 'b0;
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
reg [ 8:0] padded_bit_counter = 'b0;
reg [ 7:0] bypass_bit_counter = 'b0;
reg [ 2:0] write_data_bit_counter = 'b0;
reg [ 2:0] read_data_bit_counter = 'b0;
reg [ 3:0] header_in_bit_counter = 'b0;
reg [ 3:0] header_out_bit_counter = 'b0;
reg [18:0] scan_length_byte_counter = 'b0;
reg [18:0] valid_write_data_length_byte_counter = 'b0;
reg write_data_valid = 'b0;
reg read_data_valid = 'b0;
reg read_data_all_valid = 'b0;
reg decode_header_1 = 'b0;
reg decode_header_2 = 'b0;
wire write_data_byte_aligned;
wire read_data_byte_aligned;
wire padded_bit_byte_aligned;
wire bytestream_end;
assign write_data_byte_aligned = (write_data_bit_counter == 1);
assign read_data_byte_aligned = (read_data_bit_counter == 1);
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
assign bytestream_end = (scan_length_byte_counter == 'b0);
reg [ 7:0] offset = 'b0;
reg [15:0] header_in = 'b0;
reg [9:0] scan_length = 'b0;
reg [2:0] read_data_length = 'b0;
reg [2:0] write_data_length = 'b0;
wire [7:0] idle_inserter_sink_data;
wire idle_inserter_sink_valid;
wire idle_inserter_sink_ready;
wire [7:0] idle_inserter_source_data;
reg idle_inserter_source_ready = 'b0;
reg [7:0] idle_remover_sink_data = 'b0;
reg idle_remover_sink_valid = 'b0;
wire [7:0] idle_remover_source_data;
wire idle_remover_source_valid;
assign source_data = idle_remover_source_data;
assign source_valid = idle_remover_source_valid;
assign sink_ready = idle_inserter_sink_ready;
assign idle_inserter_sink_data = sink_data;
assign idle_inserter_sink_valid = sink_valid;
reg clock_sensor = 'b0;
reg clock_to_sample_div2 = 'b0;
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
wire data_available;
assign data_available = sink_valid;
wire [18:0] decoded_scan_length;
wire [18:0] decoded_write_data_length;
wire [18:0] decoded_read_data_length;
assign decoded_scan_length = { scan_length, {8{1'b1}} };
// +-------------------+----------------+---------------------+
// | scan_length | Length (bytes) | decoded_scan_length |
// +-------------------+----------------+---------------------+
// | 0x0 | 256 | 0x0ff (255) |
// | 0x1 | 512 | 0x1ff (511) |
// | 0x2 | 768 | 0x2ff (767) |
// | . | . | . |
// | 0x3ff | 256k | 0x3ff (256k-1) |
// +-------------------+----------------+---------------------+
// TODO: use look up table to save LEs?
// Decoded value is correct except for 0x7
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
// +-------------------+---------------+---------------------------+
// | read_data_length | Length | decoded_read_data_length |
// | write_data_length | (bytes) | decoded_write_data_length |
// +-------------------+---------------+---------------------------+
// | 0x0 | 0 | 0x0000 (0) |
// | 0x1 | 256 | 0x0100 (256) |
// | 0x2 | 512 | 0x0200 (512) |
// | 0x3 | 1k | 0x0400 (1024) |
// | 0x4 | 2k | 0x0800 (2048) |
// | 0x5 | 4k | 0x1000 (4096) |
// | 0x6 | 8k | 0x2000 (8192) |
// | 0x7 | scan_length | invalid |
// +-------------------+---------------+---------------------------+
wire clock_sensor_sync;
wire reset_to_sample_sync;
wire clock_to_sample_div2_sync;
wire clock_sense_reset_n_sync;
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_sensor),
.dout(clock_sensor_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(reset_to_sample),
.dout(reset_to_sample_sync));
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
.clk(tck),
.reset_n(1'b1),
.din(clock_to_sample_div2),
.dout(clock_to_sample_div2_sync));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
.clk(clock_to_sample),
.reset_n(clock_sense_reset_n),
.din(1'b1),
.dout(clock_sense_reset_n_sync));
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
if (~clock_sense_reset_n_sync) begin
clock_sensor <= 1'b0;
end else begin
clock_sensor <= 1'b1;
end
end
always @ (posedge clock_to_sample) begin
clock_to_sample_div2 <= ~clock_to_sample_div2;
end
always @ (posedge tck) begin
idle_remover_sink_valid <= 1'b0;
idle_inserter_source_ready <= 1'b0;
// Data mode sourcing (write)
// offset(rounded 8) m-i i 16 offset
// +------------+-----------+------------------+--------+------------+
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
// +------------+-----------+------------------+--------+------------+
// Data mode DR data stream write format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
if (offset == 'b0) begin
write_state <= ST_HEADER_1;
end else begin
write_state <= ST_BYPASS;
end
// 8-bit bypass_bit_counter
bypass_bit_counter <= offset;
// 4-bit header_in_bit_counter
header_in_bit_counter <= 15;
// 3-bit write_data_bit_counter
write_data_bit_counter <= 0;
// Reset the registers
// TODO: not necessarily all, reduce LE
decode_header_1 <= 1'b0;
decode_header_2 <= 1'b0;
read_data_all_valid <= 1'b0;
valid_write_data_length_byte_counter <= 0;
end
if (virtual_state_sdr) begin
// Discard bypass bits, then decode the 16-bit header
// 3 3 10
// +-------------------+------------------+-------------+
// | write_data_length | read_data_length | scan_length |
// +-------------------+------------------+-------------+
// Header format
case (write_state)
ST_BYPASS: begin
// Discard the bypass bit
bypass_bit_counter <= bypass_bit_counter - 1'b1;
if (bypass_bit_counter == 1) begin
write_state <= ST_HEADER_1;
end
end
// Shift the scan_length and read_data_length
ST_HEADER_1: begin
// TODO: header_in can be shorter
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
if (header_in_bit_counter == 3) begin
read_data_length <= {tdi, header_in[15:14]};
scan_length <= header_in[13:4];
write_state <= ST_HEADER_2;
decode_header_1 <= 1'b1;
end
end
// Shift the write_data_length
ST_HEADER_2: begin
// Shift into header_in
header_in <= {tdi, header_in[15:1]};
header_in_bit_counter <= header_in_bit_counter - 1'b1;
// Decode read_data_length and scan_length
if (decode_header_1) begin
decode_header_1 <= 1'b0;
// Set read_data_all_valid
if (read_data_length == 3'b111) begin
read_data_all_valid <= 1'b1;
end
// Load scan_length_byte_counter
scan_length_byte_counter <= decoded_scan_length;
end
if (header_in_bit_counter == 0) begin
write_data_length <= {tdi, header_in[15:14]};
write_state <= ST_WRITE_DATA;
decode_header_2 <= 1'b1;
end
end
// Shift the valid_write_data
ST_WRITE_DATA: begin
// Shift into dr_data_in
dr_data_in <= {tdi, dr_data_in[7:1]};
// Decode write_data_length
if (decode_header_2) begin
decode_header_2 <= 1'b0;
// Load valid_write_data_length_byte_counter
case (write_data_length)
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
3'b000: valid_write_data_length_byte_counter <= 'b0;
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
endcase
end
write_data_bit_counter <= write_data_bit_counter - 1'b1;
write_data_valid <= (valid_write_data_length_byte_counter != 0);
// Feed the data to the idle remover
if (write_data_byte_aligned && write_data_valid) begin
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
idle_remover_sink_valid <= 1'b1;
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
end
end
endcase
end
end
// Data mode sinking (read)
// i m-i offset(rounded 8) 16
// +-----------------+-----------+------------+--------+
// | valid_read_data | undefined | padded_bit | header | -> tdo
// +-----------------+-----------+------------+--------+
// Data mode DR data stream read format (as seen by hardware)
//
if (ir_in == DATA) begin
if (virtual_state_cdr) begin
read_state <= ST_HEADER;
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
// 9-bit padded_bit_counter
if (|offset[2:0]) begin
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
padded_bit_counter[2:0] <= 3'b0;
end else begin
padded_bit_counter <= {1'b0, offset};
end
// 4-bit header_out_bit_counter
header_out_bit_counter <= 0;
// 3-bit read_data_bit_counter
read_data_bit_counter <= 0;
// Load the data_available bit into header
dr_data_out <= {{7{1'b0}}, data_available};
read_data_valid <= 0;
end
if (virtual_state_sdr) begin
// 10 1
// +-----------------------------------+----------------+
// | reserved | data_available |
// +-----------------------------------+----------------+
// Header format
dr_data_out <= {1'b0, dr_data_out[7:1]};
case (read_state)
// Shift the scan_length and read_data_length
ST_HEADER: begin
header_out_bit_counter <= header_out_bit_counter - 1'b1;
// Retrieve data from idle inserter for the next shift if no paddded bits
if (header_out_bit_counter == 2) begin
if (padded_bit_counter == 0) begin
idle_inserter_source_ready <= read_data_all_valid;
end
end
if (header_out_bit_counter == 1) begin
if (padded_bit_counter == 0) begin
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end else begin
read_state <= ST_PADDED;
padded_bit_counter <= padded_bit_counter - 1'b1;
idle_inserter_source_ready <= 1'b0;
dr_data_out <= 8'h4a;
end
end
end
ST_PADDED: begin
padded_bit_counter <= padded_bit_counter - 1'b1;
if (padded_bit_byte_aligned) begin
// Load idle character into data register
dr_data_out <= 8'h4a;
end
// Retrieve data from idle inserter for the next shift when padded bits finish
if (padded_bit_counter == 1) begin
idle_inserter_source_ready <= read_data_all_valid;
end
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
read_state <= ST_READ_DATA;
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
end
end
ST_READ_DATA: begin
read_data_bit_counter <= read_data_bit_counter - 1'b1;
// Retrieve data from idle inserter just before read_data_byte_aligned
if (read_data_bit_counter == 2) begin
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
end
if (read_data_byte_aligned) begin
// Note that bytestream_end is driven by scan_length_byte_counter
if (~bytestream_end) begin
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
end
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
// Load idle character if bytestream has ended, else get data from the idle inserter
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
end
end
endcase
end
end
// Loopback mode
if (ir_in == LOOPBACK) begin
if (virtual_state_cdr) begin
dr_loopback <= 1'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_loopback
dr_loopback <= tdi;
end
end
// Debug mode
if (ir_in == DEBUG) begin
if (virtual_state_cdr) begin
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
end
if (virtual_state_udr) begin
clock_sense_reset_n <= 1'b0;
end else begin
clock_sense_reset_n <= 1'b1;
end
end
// Info mode
if (ir_in == INFO) begin
if (virtual_state_cdr) begin
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
end
if (virtual_state_sdr) begin
// Shift dr_info
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
end
end
// Control mode
if (ir_in == CONTROL) begin
if (virtual_state_cdr) begin
dr_control <= 'b0; // capture 0
end
if (virtual_state_sdr) begin
// Shift dr_control
dr_control <= {tdi, dr_control[8:1]};
end
if (virtual_state_udr) begin
// Update resetrequest and offset
{resetrequest, offset} <= dr_control;
end
end
end
always @ * begin
if (virtual_state_sdr) begin
case (ir_in)
DATA: tdo <= dr_data_out[0];
LOOPBACK: tdo <= dr_loopback;
DEBUG: tdo <= dr_debug[0];
INFO: tdo <= dr_info[0];
CONTROL: tdo <= dr_control[0];
MGMT: tdo <= dr_mgmt[0];
default: tdo <= 1'b0;
endcase
end else begin
tdo <= 1'b0;
end
end
// Idle Remover
altera_avalon_st_idle_remover idle_remover (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (), // left disconnected
.in_valid (idle_remover_sink_valid),
.in_data (idle_remover_sink_data),
// Interface: ST out
.out_ready (1'b1), // downstream is expected to be always ready
.out_valid (idle_remover_source_valid),
.out_data (idle_remover_source_data)
);
// Idle Inserter
altera_avalon_st_idle_inserter idle_inserter (
// Interface: clk
.clk (tck),
.reset_n (reset_n),
// Interface: ST in
.in_ready (idle_inserter_sink_ready),
.in_valid (idle_inserter_sink_valid),
.in_data (idle_inserter_sink_data),
// Interface: ST out
.out_ready (idle_inserter_source_ready),
.out_valid (),
.out_data (idle_inserter_source_data)
);
generate
if (MGMT_CHANNEL_WIDTH > 0)
begin : has_mgmt
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
reg mgmt_toggle = 1'b0;
wire mgmt_toggle_sync;
reg mgmt_toggle_prev;
always @ (posedge tck) begin
// Debug mode
if (ir_in == MGMT) begin
if (virtual_state_cdr) begin
dr_mgmt <= 'b0;
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
end
if (virtual_state_sdr) begin
// Shift dr_debug
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
end
if (virtual_state_udr) begin
mgmt_out <= dr_mgmt;
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
end
end
end
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
.dout(debug_reset));
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
.clk(clock_to_sample),
.reset_n(1'b1),
.din(mgmt_toggle),
.dout(mgmt_toggle_sync));
always @ (posedge clock_to_sample or posedge debug_reset) begin
if (debug_reset) begin
mgmt_valid <= 1'b0;
mgmt_toggle_prev <= 1'b0;
end else begin
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
mgmt_valid <= 1'b1;
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
mgmt_data <= mgmt_out[0];
end else begin
mgmt_valid <= 1'b0;
end
mgmt_toggle_prev <= mgmt_toggle_sync;
end
end
end
else
begin : no_mgmt
always @ (posedge tck) begin
dr_mgmt[0] <= 1'b0;
end
assign debug_reset = 1'b0;
always @ (posedge clock_to_sample) begin
mgmt_valid <= 1'b0;
mgmt_data <= 'b0;
mgmt_channel <= 'b0;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/*
* simple brainfuck cpu in verilog.
* copyright (c) 2011 sergey gridasov <grindars@gmail.com>
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, either version 3 of the license, or
* (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
module brainfuckwrapper(
clk, reset,
cin, cout, crda, cack, cwr, crdy
);
parameter fast_loopend = 1;
parameter ia_width = 11;
parameter da_width = 11;
parameter dd_width = 8;
parameter stack_depth_pow = 7;
input clk;
input reset;
input [7:0] cin;
output [7:0] cout;
input crda;
output cack;
output cwr;
input crdy;
wire [ia_width - 1:0] ia;
wire [7:0] idin;
wire ien;
// data bus
wire [da_width - 1:0] da;
wire [dd_width - 1:0] ddin;
wire [dd_width - 1:0] ddout;
wire den;
wire dwe;
brainfuckcpu #(
.fast_loopend(fast_loopend),
.ia_width(ia_width),
.da_width(da_width),
.dd_width(dd_width),
.stack_depth_pow(stack_depth_pow)
) cpu (
.clk(clk),
.reset(reset),
.ia(ia),
.idin(idin),
.ien(ien),
.da(da),
.ddin(ddin),
.ddout(ddout),
.den(den),
.dwe(dwe),
.cin(cin),
.cout(cout),
.crda(crda),
.cack(cack),
.cwr(cwr),
.crdy(crdy)
);
iram #(
.ia_width(ia_width)
) iram (
.clk(clk),
.a(ia),
.dout(idin),
.en(ien)
);
dram #(
.da_width(da_width),
.dd_width(dd_width)
) dram (
.clk(clk),
.a(da),
.din(ddout),
.dout(ddin),
.en(den),
.we(dwe)
);
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [5:0] write_address;
wire [5:0] read_address;
wire [0:0] read_data;
wire [0:0] write_data;
wire write_enable;
wire [0:0] rom_read_data;
wire [5:0] rom_read_address;
assign rom_read_data[0] = ^rom_read_address;
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [5:0] error_address;
wire [0:0] expected_data;
wire [0:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(6),
.DATA_WIDTH(1),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(1),
// 64-bit LUT memories are 0-63
.MAX_ADDRESS(63)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
wire [0:0] read_data_pre_ff;
RAM64X1D #(
.INIT(64'b01101001_10010110_10010110_01101001_10010110_01101001_01101001_10010110)
) dram(
.WCLK(clk),
.A5(write_address[5]),
.A4(write_address[4]),
.A3(write_address[3]),
.A2(write_address[2]),
.A1(write_address[1]),
.A0(write_address[0]),
.DPRA5(read_address[5]),
.DPRA4(read_address[4]),
.DPRA3(read_address[3]),
.DPRA2(read_address[2]),
.DPRA1(read_address[1]),
.DPRA0(read_address[0]),
.DPO(read_data_pre_ff[0]),
.D(write_data[0]),
.WE(write_enable)
);
FDRE ram_reg(
.D(read_data_pre_ff),
.Q(read_data[0]),
.C(clk),
.CE(1),
.R(0)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(1),
.ADDR_WIDTH(6)
) output_logic(
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
/*
copyright 2024 purdue university
author: miguel isrrael teran (misrrael@purdue.edu)
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
/* this file is generated, do not edit */
// `timescale 1ns/1ps
`default_nettype none
`define wb_aw 32
// `include "wb_wrapper.vh"
module sample_team_proj_wb (
`wb_slave_ports,
input wire [32-1:0] la_data_in,
output wire [32-1:0] la_data_out,
input wire [32-1:0] la_oenb,
input wire [34-1:0] gpio_in,
output wire [34-1:0] gpio_out,
output wire [34-1:0] gpio_oeb,
input wire nrst
);
localparam en_val_reg_offset = `wb_aw'h30000000;
localparam prescaler_val_reg_offset = `wb_aw'h30000004;
localparam im_reg_offset = `wb_aw'h3000ff00;
localparam mis_reg_offset = `wb_aw'h3000ff04;
localparam ris_reg_offset = `wb_aw'h3000ff08;
localparam ic_reg_offset = `wb_aw'h3000ff0c;
wire clk = clk_i;
`wb_ctrl_signals
wire [1-1:0] en;
wire [14-1:0] prescaler;
wire [1-1:0] done;
// register definitions
reg [0:0] en_val_reg;
assign en = en_val_reg;
`wb_reg(en_val_reg, 0, 1)
reg [13:0] prescaler_val_reg;
assign prescaler = prescaler_val_reg;
`wb_reg(prescaler_val_reg, 0, 14)
reg [0:0] im_reg;
reg [0:0] ic_reg;
reg [0:0] ris_reg;
`wb_mis_reg(1)
`wb_reg(im_reg, 0, 1)
`wb_ic_reg(1)
wire [0:0] done_assert = done;
integer _i_;
`wb_block(ris_reg, 0) else begin
for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
if(ic_reg[_i_]) ris_reg[_i_] <= 1'b0; else if(done_assert[_i_ - 0] == 1'b1) ris_reg[_i_] <= 1'b1;
end
end
assign irq = |mis_reg;
sample_team_proj instance_to_wrap (
.clk(clk),
.nrst(nrst),
.en(en),
.prescaler(prescaler),
.done(done),
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb(la_oenb),
.gpio_in(gpio_in),
.gpio_out(gpio_out),
.gpio_oeb(gpio_oeb)
);
assign dat_o =
(adr_i[`wb_aw-1:0] == en_val_reg_offset) ? en_val_reg :
(adr_i[`wb_aw-1:0] == prescaler_val_reg_offset) ? prescaler_val_reg :
(adr_i[`wb_aw-1:0] == im_reg_offset) ? im_reg :
(adr_i[`wb_aw-1:0] == mis_reg_offset) ? mis_reg :
(adr_i[`wb_aw-1:0] == ris_reg_offset) ? ris_reg :
(adr_i[`wb_aw-1:0] == ic_reg_offset) ? ic_reg :
32'hdeadbeef;
always @ (posedge clk_i or posedge rst_i)
if(rst_i)
ack_o <= 1'b0;
else if(wb_valid & ~ack_o)
ack_o <= 1'b1;
else
ack_o <= 1'b0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o);
parameter width = 16;
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [width-1:0] mask_i;
output pn_o;
reg [width-1:0] shifter;
wire parity = ^(shifter & mask_i);
always @(posedge clk_i)
if (rst_i | ~ena_i)
shifter <= #5 1;
else
if (strobe_i)
shifter <= #5 {shifter[width-2:0],parity};
assign pn_o = shifter[0];
endmodule // lfsr
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
/*
* sdram.v - SDRAM driver
*
* SDRAM driver written from scratch for 128M Alliance Memory (AS4C8M16SA)
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 Intelligent.Toasters@gmail.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`ifndef MODEL_TECH
`default_nettype none
`endif
`define SIZE128M
`define LATENCY2
module sdram (
// State machine clock
input memclk_i,
input reset_i,
// Logical Interface (8M words of 16 bits)
input enable_i,
input rd_i,
input wr_i,
input [22:0] A_i,
input [15:0] D_i,
input [1:0] Dm_i,
output [15:0] D_o,
output reg D_valid,
// Physical SDRAM Interface
input [15:0] Dq_in, // From Ram
output [15:0] Dq_out, // To Ram
output Dq_oe,
output reg [11:0] Addr,
output reg [1:0] Ba,
output Clk,
output Cke,
output reg Cs_n,
output reg Ras_n,
output reg Cas_n,
output reg We_n,
output [1 : 0] Dqm
);
// States
parameter INIT = 0, XXXXX = 1, IDLE = 2, PRECHARGE_ALL = 3, SET_MODE = 4, AUTO_REFRESH2 = 5,
AUTO_REFRESH = 6, COUNT_DOWN = 7, FULL_COUNT_DOWN = 8, PRECHARGE_REFRESH = 9,
CLOSE_ROW = 10, OPEN_ROW = 11, READ = 12, READOUT = 13, WRITE = 14, WRITEIN = 15,
WRITE_SETTLE = 16, STARTUP_REFRESH1 = 17, STARTUP_REFRESH2 = 18;
// Wire definitions ===========================================================================
wire [3:0] wait_timeout; // Waiting for a bank timeout
wire refresh_pending; // Waiting for opportunity to refresh
wire op_pending; // Interface operation pending
wire [1:0] op_bank;
wire [11:0] op_row;
wire [8:0] op_col;
// Registers ==================================================================================
reg [4:0] state = INIT, next_state = IDLE;
reg [15:0] counter; // Used as single counter for start up, or split into 4 for bank cntr
reg [11:0] refresh_ticker;
reg refresh_due, refresh_done;
reg [11:0] lastrow[0:3]; // Last row accessed
reg [3:0] bank_open; // If the lastrow valid for this bank?
reg [3:0] startup_cycles = 0;
// Registered request interface
reg if_rd, if_wr;
reg [22:0] if_A;
// Alternate edge request
reg if_rd_alt, if_wr_alt, op_pending_alt;
reg [22:0] if_A_alt;
// Operation pending
reg op_due, op_done;
// Indicates that we're in a read/write process
reg data_proc_cycle;
// Indicates that the state machine is busy with something OTHER than refresh and should ignore requests
reg fsm_busy;
// Assignments ================================================================================
assign Clk = memclk_i;
assign Cke = 1'b1; // Always enable clock
// Timeout signals
assign wait_timeout[0] = (counter[3:0] == 0); // Set if a timer is ticking for bank 0
assign wait_timeout[1] = (counter[7:4] == 0); // Set if a timer is ticking for bank 1
assign wait_timeout[2] = (counter[11:8] == 0); // Set if a timer is ticking for bank 2
assign wait_timeout[3] = (counter[15:12] == 0); // Set if a timer is ticking for bank 3
assign refresh_pending = refresh_due ^ refresh_done; // XOR
assign op_pending = op_due ^ op_done; // XOR
// Convenience/readability assignments
assign op_bank = if_A_alt[22:21];
assign op_row = if_A_alt[20:9];
assign op_col = if_A_alt[8:0];
// Memory IF Assignments
assign D_o = Dq_in;
assign Dq_out = D_i;
assign Dq_oe = (D_valid & if_wr_alt); // Output enable for DQ
assign Dqm = Dm_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
`ifdef SIM
wire [11:0] debug_bankrow0=lastrow[0];
wire [11:0] debug_bankrow1=lastrow[1];
wire [11:0] debug_bankrow2=lastrow[2];
wire [11:0] debug_bankrow3=lastrow[3];
`endif
// Other logic ================================================================================
// Function definitions ===========================================================================
// Command table attributes (Wait = delay after executing command, A-Banks is a op affecting all)
function [0:5] param_table (
input [3:0] cmd
);
case( cmd )
// A10 CS RAS CAS WE R0/C1
4'd00: param_table = { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0}; // Nop
4'd01: param_table = { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0}; // Precharge all
4'd02: param_table = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; // Set mode
4'd03: param_table = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0}; // Auto refresh
4'd04: param_table = { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0}; // Precharge Bank
4'd05: param_table = { op_row[10], 1'b0, 1'b0, 1'b1, 1'b1, 1'b0}; // Bank Activate
4'd06: param_table = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1}; // READ
4'd07: param_table = { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1}; // WRITE
default: param_table = -6'd1; // Invalid
endcase
endfunction
// Set the registered signals for the SDRAM
task set_signals ( input [0:5] data );
{Cs_n, Ras_n, Cas_n, We_n, Ba, Addr[11:0]} <=
{data[1:4], op_bank, (~data[5]) ? op_row[11] : 1'b0, data[0], (data[5]) ? {1'b0, op_col} : op_row[9:0]};
endtask
// Set timeout for the specific bank
task set_bank_timeout ( input [1:0] bank, input [3:0] data );
case(bank)
2'd0: counter[3:0] <= data;
2'd1: counter[7:4] <= data;
2'd2: counter[11:8] <= data;
2'd3: counter[15:12] <= data;
endcase
endtask
// Timer expired for bank?
function bank_timeout( input [1:0] bank );
case(bank)
2'd0: bank_timeout = (counter[3:0] == 4'd0);
2'd1: bank_timeout = (counter[7:4] == 4'd0);
2'd2: bank_timeout = (counter[11:8] == 4'd0);
2'd3: bank_timeout = (counter[15:12] == 4'd0);
default: bank_timeout = 0;
endcase
endfunction
// Track the memory request interface signals, rising edge
always @(posedge memclk_i)
if( reset_i ) begin
op_due <= 0;
if_rd <= 0;
if_wr <= 0;
if_A <= 0;
end
else
if( enable_i && ~fsm_busy ) begin // Ignore any requests during processing
if_rd <= rd_i;
if_wr <= wr_i;
if_A <= A_i;
if( ~op_pending ) op_due <= ~op_due;
end
// Capture on alt-edge
always @(negedge memclk_i)
begin
if_rd_alt <= if_rd;
if_wr_alt <= if_wr;
if_A_alt <= if_A;
op_pending_alt <= op_pending;
end
// Manage state machine - set next states
always @(posedge memclk_i)
begin
if( reset_i ) begin
refresh_done <= 0;
op_done <= 0;
lastrow[0] <= 0;
lastrow[1] <= 0;
lastrow[2] <= 0;
lastrow[3] <= 0;
// No banks open
bank_open <= 0;
state <= INIT;
// Not busy
fsm_busy <= 0;
end
else begin
// FSM Machine
case( state )
// Count downs - used by pretty much every command
COUNT_DOWN: begin
// Transition to next state
if( bank_timeout(op_bank) ) state <= next_state;
// Updated counters
if( ~wait_timeout[0] ) counter[3:0] <= counter[3:0] - 1'b1;
if( ~wait_timeout[1] ) counter[7:4] <= counter[7:4] - 1'b1;
if( ~wait_timeout[2] ) counter[11:8] <= counter[11:8] - 1'b1;
if( ~wait_timeout[3] ) counter[15:12] <= counter[15:12] - 1'b1;
end
// Full range count down for start up
FULL_COUNT_DOWN: begin
if( counter == 0 )
state <= next_state;
else
counter <= counter - 1'b1;
end
// Power on initialize
INIT: begin
data_proc_cycle <= 0;
counter <= -16'd1; // Wait for stable clock > 200uS (410uS)
state <= FULL_COUNT_DOWN;
next_state <= PRECHARGE_ALL;
end
// Precharge all banks
PRECHARGE_ALL: begin
counter <= 16'h1111; // Countdown all banks
bank_open <= 0; // No banks open
state <= COUNT_DOWN;
startup_cycles <= 7; // Startup counter - 8 refreshes
next_state <= STARTUP_REFRESH1;
end
// Initial refresh start up required before mode set in some devices
STARTUP_REFRESH1: begin
state <= STARTUP_REFRESH2;
end
STARTUP_REFRESH2: begin
counter <= 16'h7777;
state <= COUNT_DOWN;
if( startup_cycles == 0 ) next_state <= SET_MODE;
else begin
startup_cycles <= startup_cycles - 1'b1;
next_state <= STARTUP_REFRESH1;
end
end
// Precharge all banks then refresh
PRECHARGE_REFRESH: begin
// Only process precharge if an operation is not in progress
if( counter == 0 ) begin
bank_open <= 0; // No banks open
counter <= 16'h1111; // Countdown all banks
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH;
end
end
// Set mode command
SET_MODE: begin
counter <= 4'd0;
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH2;
end
// Auto Refresh 2 - start up double auto refresh
AUTO_REFRESH2: begin
counter <= 16'h8888;
state <= COUNT_DOWN;
next_state <= AUTO_REFRESH;
end
// Auto Refresh
AUTO_REFRESH: begin
counter <= 16'h8888;
state <= COUNT_DOWN;
next_state <= IDLE;
// Clear the refresh pending flag
if( refresh_pending ) refresh_done <= ~refresh_done;
end
// Set mode command
IDLE: begin
if( refresh_pending ) begin
state <= PRECHARGE_REFRESH;
fsm_busy <= 0;
end
else if( op_pending_alt ) begin
// Reset the pending flag, always half a cycle behind _alt, so will be set
if( op_pending ) op_done <= ~op_done;
// Doing something, so set busy flag
fsm_busy <= 1'b1;
// Check row in bank, if not same then close
if( bank_open[op_bank] )
begin
// Is bank correct?
if( lastrow[op_bank] != op_row ) begin
state <= CLOSE_ROW;
end
// Bank open and ready!
else state <= (if_rd_alt) ? READ : (if_wr_alt) ? WRITE : IDLE; //(Failsafe)
end
else state <= OPEN_ROW; // Otherwise open the bank
end
// Otherwise stay in idle
else begin
state <= IDLE;
// Not busy
fsm_busy <= 0;
end
// Can't be in retrieval if idle
data_proc_cycle <= 0;
end
// Close row command
CLOSE_ROW: begin
set_bank_timeout(op_bank, 1);
bank_open[op_bank] <= 0; // Close this bank
state <= COUNT_DOWN;
next_state <= OPEN_ROW;
end
// Open row command
OPEN_ROW: begin
set_bank_timeout(op_bank, 1);
state <= COUNT_DOWN;
next_state <= (if_rd_alt) ? READ : (if_wr_alt) ? WRITE : IDLE; //(Failsafe)
bank_open[op_bank] <= 1; // Indicate bank open
lastrow[op_bank] <= op_row; // Store the row for later comparison
end
// Read command
READ: begin
`ifdef LATENCY2
set_bank_timeout(op_bank, 0);
`else // Latency 3 clocks
set_bank_timeout(op_bank, 1);
`endif
state <= COUNT_DOWN;
next_state <= READOUT;
end
// OUT processing
READOUT: begin
data_proc_cycle <= 1'b1;
set_bank_timeout(op_bank, 6);
state <= COUNT_DOWN;
next_state <= IDLE;
end
// Write command
WRITE: begin
state <= WRITEIN;
data_proc_cycle <= 1'b1;
end
// IN processing (-2)
WRITEIN: begin
set_bank_timeout(op_bank, 5);
state <= COUNT_DOWN;
next_state <= WRITE_SETTLE;
end
WRITE_SETTLE: begin
`ifdef LATENCY2
set_bank_timeout(op_bank, 0);
`else // Latency 3 clocks
set_bank_timeout(op_bank, 1);
`endif
data_proc_cycle <= 0;
state <= COUNT_DOWN;
next_state <= IDLE;
fsm_busy <= 0;
end
// If we lose the state, then self-reset
default: state <= INIT;
endcase
end
end
// Update signals (memory reads in on rising edge)
always @(negedge memclk_i)
begin
if( reset_i ) begin
refresh_ticker <= 0;
refresh_due <= 0;
end
else begin
`ifdef SIZE128M
// Refresh ticker - cycle at 2432, 62.2848ms full cycle (15.20625uS repeats) 4096 Rows
if(refresh_ticker[11:7] == 5'b10011)
`else
// Refresh ticker - cycle at 768, 62.91456ms full cycle (8192 Rows)
if(refresh_ticker[9:8] == 2'b11)
`endif
begin
refresh_ticker <= 12'd0;
// Cause refresh to be due
if( ~refresh_pending ) refresh_due <= ~refresh_due;
end
else refresh_ticker <= (refresh_ticker + 1'b1);
// Set the valid indicator
D_valid <= (data_proc_cycle || (state == READOUT) || (state == WRITE)) && (state != IDLE) && (state != WRITE_SETTLE);
// Set the output state
case( state )
IDLE: set_signals(param_table(0));
INIT: set_signals(param_table(0));
COUNT_DOWN: set_signals(param_table(0));
FULL_COUNT_DOWN: set_signals(param_table(0));
STARTUP_REFRESH2: set_signals(param_table(0));
PRECHARGE_ALL: set_signals(param_table(1));
PRECHARGE_REFRESH: set_signals(param_table(1));
AUTO_REFRESH2: set_signals(param_table(3));
AUTO_REFRESH: set_signals(param_table(3));
STARTUP_REFRESH1: set_signals(param_table(3));
CLOSE_ROW: set_signals(param_table(4));
OPEN_ROW: set_signals(param_table(5));
READ: set_signals(param_table(6));
READOUT: set_signals(param_table(0));
WRITE: set_signals(param_table(7));
WRITEIN: set_signals(param_table(0));
WRITE_SETTLE: set_signals(param_table(0));
SET_MODE: begin
set_signals(param_table(2));
Addr <= 12'h23; // 8-word bursts with 2.latency
end
default: set_signals(param_table(0)); // NOP
endcase
end
end
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_timers(
input clk,
input rst,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input set_run_A,
input set_run_B,
input clr_run_A,
input clr_run_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
jt51_timer #(.mult_width(6), .counter_width(10)) timer_A(
.clk ( clk ),
.rst ( rst ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.set_run ( set_run_A ),
.clr_run ( clr_run_A ),
.flag ( flag_A ),
.overflow ( overflow_A)
);
jt51_timer #(.mult_width(10), .counter_width(8)) timer_B(
.clk ( clk ),
.rst ( rst ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B),
.set_run ( set_run_B ),
.clr_run ( clr_run_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
module jt51_timer #(parameter counter_width = 10, mult_width=5 )
(
input clk,
input rst,
input [counter_width-1:0] start_value,
input load,
input clr_flag,
input set_run,
input clr_run,
output reg flag,
output reg overflow
);
reg run;
reg [ mult_width-1:0] mult;
reg [counter_width-1:0] cnt;
always@(posedge clk)
if( clr_flag || rst)
flag <= 1'b0;
else if(overflow) flag<=1'b1;
always@(posedge clk)
if( clr_run || rst)
run <= 1'b0;
else if(set_run || load) run<=1'b1;
reg [mult_width+counter_width-1:0] next, init;
always @(*) begin
{overflow, next } = { 1'b0, cnt, mult } + 1'b1;
init = { start_value, { (mult_width){1'b0} } };
end
always @(posedge clk) begin : counter
if( load ) begin
mult <= { (mult_width){1'b0} };
cnt <= start_value;
end
else if( run )
{ cnt, mult } <= overflow ? init : next;
end
endmodule
|
/*
copyright (c) 2014 adapteva, inc.
contributed by fred huettig <fred@adapteva.com>
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program (see the file copying). if not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
epiphany elink axi master module
########################################################################
*/
`define write_bit 102
`define datamode_range 101:100
`define ctrlmode_range 99:96
`define dstaddr_range 95:64
`define dstaddr_lsb 64
`define srcaddr_range 63:32
`define srcaddr_lsb 32
`define data_range 31:0
`define data_lsb 0
`timescale 1 ns / 1 ps
module emaxi_v1_0_m00_axi #
(
// users to add parameters here
// user parameters ends
// do not modify the parameters beyond this line
// base address of targeted slave
parameter c_m_target_slave_base_addr = 32'h40000000,
// burst length. supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer c_m_axi_burst_len = 16,
// thread id width
parameter integer c_m_axi_id_width = 1,
// width of address bus
parameter integer c_m_axi_addr_width = 32,
// width of data bus
parameter integer c_m_axi_data_width = 64,
// width of user write address bus
parameter integer c_m_axi_awuser_width = 0,
// width of user read address bus
parameter integer c_m_axi_aruser_width = 0,
// width of user write data bus
parameter integer c_m_axi_wuser_width = 0,
// width of user read data bus
parameter integer c_m_axi_ruser_width = 0,
// width of user response bus
parameter integer c_m_axi_buser_width = 0
)
(
// users to add ports here
// fifo read-master port, writes from rx channel
input wire [102:0] emwr_rd_data,
output wire emwr_rd_en,
input wire emwr_empty,
// fifo read-master port, read requests from rx channel
input wire [102:0] emrq_rd_data,
output wire emrq_rd_en,
input wire emrq_empty,
// fifo write-master port, read responses to tx channel
output reg [102:0] emrr_wr_data,
output reg emrr_wr_en,
input wire emrr_full,
input wire emrr_prog_full,
// user ports ends
// do not modify the ports beyond this line
// global clock signal.
input wire m_axi_aclk,
// global reset singal. this signal is active low
input wire m_axi_aresetn,
// master interface write address id
output wire [c_m_axi_id_width-1 : 0] m_axi_awid,
// master interface write address
output wire [c_m_axi_addr_width-1 : 0] m_axi_awaddr,
// burst length. the burst length gives the exact number of transfers in a burst
output wire [7 : 0] m_axi_awlen,
// burst size. this signal indicates the size of each transfer in the burst
output wire [2 : 0] m_axi_awsize,
// burst type. the burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] m_axi_awburst,
// lock type. provides additional information about the
// atomic characteristics of the transfer.
output wire m_axi_awlock,
// memory type. this signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] m_axi_awcache,
// protection type. this signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] m_axi_awprot,
// quality of service, qos identifier sent for each write transaction.
output wire [3 : 0] m_axi_awqos,
// optional user-defined signal in the write address channel.
output wire [c_m_axi_awuser_width-1 : 0] m_axi_awuser,
// write address valid. this signal indicates that
// the channel is signaling valid write address and control information.
output wire m_axi_awvalid,
// write address ready. this signal indicates that
// the slave is ready to accept an address and associated control signals
input wire m_axi_awready,
// master interface write data.
output wire [c_m_axi_data_width-1 : 0] m_axi_wdata,
// write strobes. this signal indicates which byte
// lanes hold valid data. there is one write strobe
// bit for each eight bits of the write data bus.
output wire [c_m_axi_data_width/8-1 : 0] m_axi_wstrb,
// write last. this signal indicates the last transfer in a write burst.
output wire m_axi_wlast,
// optional user-defined signal in the write data channel.
output wire [c_m_axi_wuser_width-1 : 0] m_axi_wuser,
// write valid. this signal indicates that valid write
// data and strobes are available
output wire m_axi_wvalid,
// write ready. this signal indicates that the slave
// can accept the write data.
input wire m_axi_wready,
// master interface write response.
input wire [c_m_axi_id_width-1 : 0] m_axi_bid,
// write response. this signal indicates the status of the write transaction.
input wire [1 : 0] m_axi_bresp,
// optional user-defined signal in the write response channel
input wire [c_m_axi_buser_width-1 : 0] m_axi_buser,
// write response valid. this signal indicates that the
// channel is signaling a valid write response.
input wire m_axi_bvalid,
// response ready. this signal indicates that the master
// can accept a write response.
output wire m_axi_bready,
// master interface read address.
output wire [c_m_axi_id_width-1 : 0] m_axi_arid,
// read address. this signal indicates the initial
// address of a read burst transaction.
output wire [c_m_axi_addr_width-1 : 0] m_axi_araddr,
// burst length. the burst length gives the exact number of transfers in a burst
output wire [7 : 0] m_axi_arlen,
// burst size. this signal indicates the size of each transfer in the burst
output wire [2 : 0] m_axi_arsize,
// burst type. the burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] m_axi_arburst,
// lock type. provides additional information about the
// atomic characteristics of the transfer.
output wire m_axi_arlock,
// memory type. this signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] m_axi_arcache,
// protection type. this signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] m_axi_arprot,
// quality of service, qos identifier sent for each read transaction
output wire [3 : 0] m_axi_arqos,
// optional user-defined signal in the read address channel.
output wire [c_m_axi_aruser_width-1 : 0] m_axi_aruser,
// write address valid. this signal indicates that
// the channel is signaling valid read address and control information
output wire m_axi_arvalid,
// read address ready. this signal indicates that
// the slave is ready to accept an address and associated control signals
input wire m_axi_arready,
// read id tag. this signal is the identification tag
// for the read data group of signals generated by the slave.
input wire [c_m_axi_id_width-1 : 0] m_axi_rid,
// master read data
input wire [c_m_axi_data_width-1 : 0] m_axi_rdata,
// read response. this signal indicates the status of the read transfer
input wire [1 : 0] m_axi_rresp,
// read last. this signal indicates the last transfer in a read burst
input wire m_axi_rlast,
// optional user-defined signal in the read address channel.
input wire [c_m_axi_ruser_width-1 : 0] m_axi_ruser,
// read valid. this signal indicates that the channel
// is signaling the required read data.
input wire m_axi_rvalid,
// read ready. this signal indicates that the master can
// accept the read data and response information.
output wire m_axi_rready
);
// function called clogb2 that returns an integer which has the
//value of the ceiling of the log base 2
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction // clogb2
// axi4lite signals
//axi4 internal temp signals
reg [c_m_axi_addr_width-1 : 0] axi_awaddr;
reg [7:0] axi_awlen;
reg [2:0] axi_awsize;
reg axi_awvalid;
reg [c_m_axi_data_width-1 : 0] axi_wdata;
reg [c_m_axi_data_width/8-1 : 0] axi_wstrb;
reg axi_wlast;
reg axi_wvalid;
//reg axi_bready;
wire [c_m_axi_addr_width-1 : 0] axi_araddr;
wire [7:0] axi_arlen;
wire [2:0] axi_arsize;
wire axi_arvalid;
wire axi_rready;
// i/o connections assignments
//i/o connections. write address (aw)
assign m_axi_awid = 'b0;
//the axi address is a concatenation of the target base address + active offset range
assign m_axi_awaddr = axi_awaddr;
//burst length is number of transaction beats, minus 1
assign m_axi_awlen = axi_awlen;
//size should be c_m_axi_data_width, in 2^size bytes, otherwise narrow bursts are used
assign m_axi_awsize = axi_awsize;
//incr burst type is usually used, except for keyhole bursts
assign m_axi_awburst = 2'b01;
assign m_axi_awlock = 1'b0;
//update value to 4'b0011 if coherent accesses to be used via the zynq acp port. not allocated, modifiable, not bufferable. not bufferable since this example is meant to test memory, not intermediate cache.
assign m_axi_awcache = 4'b0010;
assign m_axi_awprot = 3'h0;
assign m_axi_awqos = 4'h0;
assign m_axi_awuser = 'b1;
assign m_axi_awvalid = axi_awvalid;
//write data(w)
assign m_axi_wdata = axi_wdata;
//all bursts are complete and aligned in this example
assign m_axi_wstrb = axi_wstrb;
assign m_axi_wlast = axi_wlast;
assign m_axi_wuser = 'b0;
assign m_axi_wvalid = axi_wvalid;
//write response (b)
assign m_axi_bready = 1'b1; // axi_bready;
//read address (ar)
assign m_axi_arid = 'b0;
assign m_axi_araddr = axi_araddr;
//burst length is number of transaction beats, minus 1
assign m_axi_arlen = axi_arlen;
//size should be c_m_axi_data_width, in 2^n bytes, otherwise narrow bursts are used
assign m_axi_arsize = axi_arsize;
//incr burst type is usually used, except for keyhole bursts
assign m_axi_arburst = 2'b01;
assign m_axi_arlock = 1'b0;
//update value to 4'b0011 if coherent accesses to be used via the zynq acp port. not allocated, modifiable, not bufferable. not bufferable since this example is meant to test memory, not intermediate cache.
assign m_axi_arcache = 4'b0010;
assign m_axi_arprot = 3'h0;
assign m_axi_arqos = 4'h0;
assign m_axi_aruser = 'b1;
assign m_axi_arvalid = axi_arvalid;
//read and read response (r)
assign m_axi_rready = axi_rready;
//--------------------
//write address channel
//--------------------
// holding buffers for aw and w channels
reg awvalid_b;
reg [c_m_axi_addr_width-1 : 0] awaddr_b;
reg [2:0] awsize_b;
reg [7:0] awlen_b;
reg wvalid_b;
reg [c_m_axi_data_width-1 : 0] wdata_b;
reg [c_m_axi_data_width/8-1 : 0] wstrb_b;
wire aw_go = axi_awvalid & m_axi_awready;
wire w_go = axi_wvalid & m_axi_wready;
assign emwr_rd_en = ( ~emwr_empty & ~awvalid_b & ~wvalid_b);
// generate write-address signals
always @( posedge m_axi_aclk ) begin
if( m_axi_aresetn == 1'b0 ) begin
axi_awvalid <= 1'b0;
axi_awaddr <= 'd0;
axi_awlen <= 'd0;
axi_awsize <= 'd0;
awvalid_b <= 1'b0;
awaddr_b <= 'd0;
awlen_b <= 'd0;
awsize_b <= 'd0;
end else begin
if( ~axi_awvalid | aw_go ) begin
if( awvalid_b ) begin
axi_awvalid <= 1'b1;
axi_awaddr <= awaddr_b;
axi_awlen <= awlen_b;
axi_awsize <= awsize_b;
end else begin
axi_awvalid <= emwr_rd_en;
axi_awaddr <= emwr_rd_data[`dstaddr_range];
axi_awlen <= 'd0;
axi_awsize <= { 1'b0, emwr_rd_data[`datamode_range] };
end // else: !if(awvalid_b)
end // if (~axi_awvalid | aw_go)
if( emwr_rd_en & axi_awvalid & ~aw_go )
awvalid_b <= 1'b1;
else if( aw_go )
awvalid_b <= 1'b0;
if( emwr_rd_en ) begin
awaddr_b <= emwr_rd_data[`dstaddr_range];
awlen_b <= 'd0;
awsize_b <= { 1'b0, emwr_rd_data[`datamode_range] };
end
end // else: !if( m_axi_aresetn == 1'b0 )
end // always @ ( posedge m_axi_aclk )
reg [c_m_axi_data_width-1 : 0] wdata_aligned;
reg [c_m_axi_data_width/8-1 : 0] wstrb_aligned;
always @ ( emwr_rd_data ) begin
// place data of stated size in all legal positions
case( emwr_rd_data[`datamode_range] )
2'd0: wdata_aligned = { 8{emwr_rd_data[`data_lsb+7 -: 8]}};
2'd1: wdata_aligned = { 4{emwr_rd_data[`data_lsb+15 -: 16]}};
2'd2: wdata_aligned = { 2{emwr_rd_data[`data_lsb+31 -: 32]}};
default: wdata_aligned = { emwr_rd_data[`srcaddr_range],
emwr_rd_data[`data_range]};
endcase // case ( emwr_rd_data[`datamode_range] )
// create write strobes
case( emwr_rd_data[`datamode_range] )
2'd0: // byte
case( emwr_rd_data[`dstaddr_lsb+2 -: 3] )
3'd0: wstrb_aligned = 8'h01;
3'd1: wstrb_aligned = 8'h02;
3'd2: wstrb_aligned = 8'h04;
3'd3: wstrb_aligned = 8'h08;
3'd4: wstrb_aligned = 8'h10;
3'd5: wstrb_aligned = 8'h20;
3'd6: wstrb_aligned = 8'h40;
default: wstrb_aligned = 8'h80;
endcase
2'd1: // 16b hword
case( emwr_rd_data[`dstaddr_lsb+2 -: 2] )
2'd0: wstrb_aligned = 8'h03;
2'd1: wstrb_aligned = 8'h0c;
2'd2: wstrb_aligned = 8'h30;
default: wstrb_aligned = 8'hc0;
endcase
2'd2: // 32b word
if( emwr_rd_data[`dstaddr_lsb+2] )
wstrb_aligned = 8'hf0;
else
wstrb_aligned = 8'h0f;
default: // 64b dword
wstrb_aligned = 8'hff;
endcase // case ( emwr_rd_data[`datamode_range] )
end // always @ (...
// generate the write-data signals
always @( posedge m_axi_aclk ) begin
if( m_axi_aresetn == 1'b0 ) begin
axi_wvalid <= 1'b0;
axi_wdata <= 'd0;
axi_wstrb <= 'd0;
axi_wlast <= 1'b1; // todo: no bursts for now
wvalid_b <= 1'b0;
wdata_b <= 'd0;
wstrb_b <= 'd0;
end else begin // if ( m_axi_aresetn == 1'b0 )
if( ~axi_wvalid | w_go ) begin
if( wvalid_b ) begin
axi_wvalid <= 1'b1;
axi_wdata <= wdata_b;
axi_wstrb <= wstrb_b;
end else begin
axi_wvalid <= emwr_rd_en;
axi_wdata <= wdata_aligned;
axi_wstrb <= wstrb_aligned;
end
end // if ( ~axi_wvalid | w_go )
if( emwr_rd_en & axi_wvalid & ~w_go )
wvalid_b <= 1'b1;
else if( w_go )
wvalid_b <= 1'b0;
if( emwr_rd_en ) begin
wdata_b <= wdata_aligned;
wstrb_b <= wstrb_aligned;
end
end // else: !if( m_axi_aresetn == 1'b0 )
end // always @ ( posedge m_axi_aclk )
//----------------------------
// read handler
// elink read requests generate a transaction on the ar channel,
// buffer the src info to generate an elink write when the
// read data comes back.
//----------------------------
`define ri_dstaddr_range 40:38
`define ri_dstaddr_lsb 38
`define ri_datamode_range 37:36
`define ri_ctrlmode_range 35:32
`define ri_srcaddr_range 31:0
wire readinfo_wren;
wire readinfo_rden;
wire readinfo_full;
wire [40:0] readinfo_out;
wire [40:0] readinfo_in =
{
emrq_rd_data[`dstaddr_lsb+2 -: 3],
emrq_rd_data[`datamode_range],
emrq_rd_data[`ctrlmode_range],
emrq_rd_data[`srcaddr_range]
};
syncfifo
#(
// parameters
.aw (5),
.dw (41))
fifo_readinfo_i
(
// outputs
.rdata (readinfo_out),
.empty (),
.full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wdata (readinfo_in),
.wen (readinfo_wren),
.ren (readinfo_rden));
//----------------------------
// read address channel
//----------------------------
assign axi_araddr = emrq_rd_data[`dstaddr_range];
assign axi_arsize = {1'b0, emrq_rd_data[`datamode_range]};
assign axi_arlen = 8'd0;
assign axi_arvalid = ~emrq_empty & ~readinfo_full;
assign emrq_rd_en = axi_arvalid & m_axi_arready;
assign readinfo_wren = emrq_rd_en;
//--------------------------------
// read data (and response) channel
//--------------------------------
assign axi_rready = ~emrr_prog_full;
assign readinfo_rden = axi_rready & m_axi_rvalid;
always @( posedge m_axi_aclk ) begin
if( ~m_axi_aresetn ) begin
emrr_wr_data <= 'd0;
emrr_wr_en <= 1'b0;
end else begin
emrr_wr_en <= axi_rready & m_axi_rvalid;
emrr_wr_data[`write_bit] <= 1'b1;
emrr_wr_data[`datamode_range] <= readinfo_out[`ri_datamode_range];
emrr_wr_data[`ctrlmode_range] <= readinfo_out[`ri_ctrlmode_range];
emrr_wr_data[`dstaddr_range] <= readinfo_out[`ri_srcaddr_range];
emrr_wr_data[`srcaddr_range] <= 32'd0;
emrr_wr_data[`data_range] <= 32'd0;
// steer read data according to size & host address lsbs
case( readinfo_out[`ri_datamode_range] )
2'd0: // byte read
case( readinfo_out[`ri_dstaddr_range] )
3'd0: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[7:0];
3'd1: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[15:8];
3'd2: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[23:16];
3'd3: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[31:24];
3'd4: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[39:32];
3'd5: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[47:40];
3'd6: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[55:48];
default: emrr_wr_data[`data_lsb+7 -: 8] <= m_axi_rdata[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[`ri_dstaddr_lsb+2 -: 2] )
2'd0: emrr_wr_data[`data_lsb+15 -: 16] <= m_axi_rdata[15:0];
2'd1: emrr_wr_data[`data_lsb+15 -: 16] <= m_axi_rdata[31:16];
2'd2: emrr_wr_data[`data_lsb+15 -: 16] <= m_axi_rdata[47:32];
default: emrr_wr_data[`data_lsb+15 -: 16] <= m_axi_rdata[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[`ri_dstaddr_lsb+2] )
emrr_wr_data[`data_range] <= m_axi_rdata[63:32];
else
emrr_wr_data[`data_range] <= m_axi_rdata[31:0];
// 64b word already defined by defaults above
2'd3: begin // 64b dword
emrr_wr_data[`data_range] <= m_axi_rdata[31:0];
emrr_wr_data[`srcaddr_range] <= m_axi_rdata[63:32];
end
endcase
end // else: !if( ~m_axi_aresetn )
end // always @ ( posedge m_axi_aclk )
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module csrbrg(
input sys_clk,
input sys_rst,
/* WB */
input [3:1] wb_adr_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* CSR */
output reg [2:0] csr_a,
output reg csr_we,
output reg [15:0] csr_do,
input [15:0] csr_di
);
/* Datapath: WB <- CSR */
always @(posedge sys_clk) begin
wb_dat_o <= csr_di;
end
/* Datapath: CSR -> WB */
reg next_csr_we;
always @(posedge sys_clk) begin
csr_a <= wb_adr_i[3:1];
csr_we <= next_csr_we;
csr_do <= wb_dat_i;
end
/* Controller */
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter DELAYACK1 = 2'd1;
parameter DELAYACK2 = 2'd2;
parameter ACK = 2'd3;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
wb_ack_o = 1'b0;
next_csr_we = 1'b0;
case(state)
IDLE: begin
if(wb_cyc_i & wb_stb_i) begin
/* We have a request for us */
next_csr_we = wb_we_i;
if(wb_we_i)
next_state = ACK;
else
next_state = DELAYACK1;
end
end
DELAYACK1: next_state = DELAYACK2;
DELAYACK2: next_state = ACK;
ACK: begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
/*
*
* Copyright (c) 2011 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (osc_clk, MISO, MOSI, SCLK, eth_nRESET, eth_nSCS);
input osc_clk;
input MISO;
output MOSI, SCLK, eth_nRESET, eth_nSCS;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (osc_clk, hash_clk);
`endif
//// Simulation Timer
`ifdef SIM
reg gen_clk = 0;
wire clk = gen_clk;
`else
wire clk = hash_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg is_golden_ticket = 0;
sha256_transform uut (clk, state, data, hash);
sha256_transform uut2 (clk, 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667, {256'h0000010000000000000000000000000000000000000000000000000080000000, hash}, hash2);
//// Controller
reg [31:0] golden_nonce = 0;
wire [255:0] midstate_vw;
wire [95:0] data2_vw;
minercontroller minercontroller_inst
(
.altpll_0_c0_out (),
.clk_0 (osc_clk),
.in_port_to_the_MISO (MISO),
.in_port_to_the_pio_nonce (golden_nonce),
.locked_from_the_altpll_0 (),
.out_port_from_the_MOSI (MOSI),
.out_port_from_the_SCLK (SCLK),
.out_port_from_the_eth_nRESET (eth_nRESET),
.out_port_from_the_eth_nSCS (eth_nSCS),
.out_port_from_the_pio_data_0 (data2_vw[31:0]),
.out_port_from_the_pio_data_1 (data2_vw[63:32]),
.out_port_from_the_pio_data_2 (data2_vw[95:64]),
.out_port_from_the_pio_midstate_0 (midstate_vw[31:0]),
.out_port_from_the_pio_midstate_1 (midstate_vw[63:32]),
.out_port_from_the_pio_midstate_2 (midstate_vw[95:64]),
.out_port_from_the_pio_midstate_3 (midstate_vw[127:96]),
.out_port_from_the_pio_midstate_4 (midstate_vw[159:128]),
.out_port_from_the_pio_midstate_5 (midstate_vw[191:160]),
.out_port_from_the_pio_midstate_6 (midstate_vw[223:192]),
.out_port_from_the_pio_midstate_7 (midstate_vw[255:224]),
.phasedone_from_the_altpll_0 (),
.reset_n (1'b1)
);
reg [255:0] midstate_buf = 0, data_buf = 0;
//wire [255:0] midstate_vw, data2_vw;
//virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("STAT")) midstate_vw_blk(.probe(), .source(midstate_vw));
//virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
//// Virtual Wire Output
//reg [31:0] golden_nonce = 0;
// Note that the nonce reported to the external world will always be
// larger than the real nonce. Currently it is 132 bigger. So an
// external controller (like scripts/mine.tcl) needs to do:
// golden_nonce = golden_nonce - 132
// to get the real nonce.
//virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce), .source());
//// Control Unit
always @ (posedge clk)
begin
`ifdef SIM
midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data_buf[95:0]};
//nonce <= nonce + 32'd1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2[255:224] == 32'h00000000;
if(is_golden_ticket)
begin
golden_nonce <= nonce;
end
end
//// Simulation Clock
`ifdef SIM
initial begin
#100
while(1)
begin
#6 gen_clk = 1; #6 gen_clk = 0;
end
end
`endif
endmodule
|
/* this file is part of jt51.
jt51 is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
jt51 is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with jt51. if not, see <http://www.gnu.org/licenses/>.
author: jose tejada gomez. twitter: @topapate
version: 1.0
date: 27-10-2016
*/
`timescale 1ns / 1ps
/*
tab size 4
*/
module jt51_eg(
`ifdef test_support
input test_eg,
`endif
input rst,
input clk,
input zero,
// envelope configuration
input [4:0] keycode_iii,
input [4:0] arate_ii,
input [4:0] rate1_ii,
input [4:0] rate2_ii,
input [3:0] rrate_ii,
input [3:0] d1l_i,
input [1:0] ks_iii,
// envelope operation
input keyon_ii,
output reg pg_rst_iii,
// envelope number
input [6:0] tl_vii,
input [6:0] am,
input [1:0] ams_vii,
input amsen_vii,
output [9:0] eg_xi
);
// eg[9:6] -> direct attenuation (divide by 2)
// eg[5:0] -> mantisa attenuation (uses lut)
// 1 lsb of eg is -0.09257 db
parameter attack=2'd0, decay1=2'd1, decay2=2'd2, release=2'd3;
reg [4:0] d1level_ii;
reg [2:0] cnt_v;
reg [5:0] rate_iv;
wire [9:0] eg_vi;
reg [9:0] eg_vii, eg_viii;
wire [9:0] eg_ii;
reg [11:0] sum_eg_tl_vii;
reg step_v, step_vi;
reg sum_up;
reg [5:0] rate_v;
reg [5:1] rate_vi;
// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };
reg [1:0] eg_cnt_base;
reg [14:0] eg_cnt /*verilator public*/;
reg [8:0] am_final_vii;
always @(posedge clk) begin : envelope_counter
if( rst ) begin
eg_cnt_base <= 2'd0;
eg_cnt <=15'd0;
end
else begin
if( zero ) begin
// envelope counter increases every 3 output samples,
// there is one sample every 32 clock ticks
if( eg_cnt_base == 2'd2 ) begin
eg_cnt <= eg_cnt + 1'b1;
eg_cnt_base <= 2'd0;
end
else eg_cnt_base <= eg_cnt_base + 1'b1;
end
end
end
wire cnt_out; // = all_cnt_last[3*31-1:3*30];
reg [6:0] pre_rate_iii;
reg [4:0] cfg_iii;
always @(*) begin : pre_rate_calc
if( cfg_iii == 5'd0 )
pre_rate_iii = 6'd0;
else
case( ks_iii )
2'd3: pre_rate_iii = { cfg_iii, 1'b0 } + keycode_iii;
2'd2: pre_rate_iii = { cfg_iii, 1'b0 } + { 1'b0, keycode_iii[4:1] };
2'd1: pre_rate_iii = { cfg_iii, 1'b0 } + { 2'b0, keycode_iii[4:2] };
2'd0: pre_rate_iii = { cfg_iii, 1'b0 } + { 3'b0, keycode_iii[4:3] };
endcase
end
reg [7:0] step_idx;
reg [1:0] state_in_iii, state_in_iv, state_in_v, state_in_vi;
always @(*) begin : rate_step
if( rate_v[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate_v[5:2]==4'hf && state_in_v == attack)
step_idx = 8'b11111111; // maximum attack speed, rates 60&61
else
case( rate_v[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate_v[5:2]==4'd0 && state_in_v != attack)
step_idx = 8'b11111110; // limit slowest decay rate_iv
else
case( rate_v[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate_iv of zero keeps the level still
step_v = rate_v[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_v ];
end
wire ar_off_vi;
always @(posedge clk) begin
// i
if( d1l_i == 4'd15 )
d1level_ii <= 5'h10; // 48db
else
d1level_ii <= d1l_i;
end
// ii
wire keyon_last_ii;
wire keyon_now_ii = !keyon_last_ii && keyon_ii;
wire keyoff_now_ii = keyon_last_ii && !keyon_ii;
wire ar_off_ii = keyon_now_ii && (arate_ii == 5'h1f);
wire [1:0] state_ii;
always @(posedge clk) begin
pg_rst_iii <= keyon_now_ii;
// trigger release
if( keyoff_now_ii ) begin
cfg_iii <= { rrate_ii, 1'b1 };
state_in_iii <= release;
end
else begin
// trigger 1st decay
if( keyon_now_ii ) begin
cfg_iii <= arate_ii;
state_in_iii <= attack;
end
else begin : sel_rate
case ( state_ii )
attack: begin
if( eg_ii==10'd0 ) begin
state_in_iii <= decay1;
cfg_iii <= rate1_ii;
end
else begin
state_in_iii <= state_ii; // attack
cfg_iii <= arate_ii;
end
end
decay1: begin
if( eg_ii[9:5] >= d1level_ii ) begin
cfg_iii <= rate2_ii;
state_in_iii <= decay2;
end
else begin
cfg_iii <= rate1_ii;
state_in_iii <= state_ii; // decay1
end
end
decay2: begin
cfg_iii <= rate2_ii;
state_in_iii <= state_ii; // decay2
end
release: begin
cfg_iii <= { rrate_ii, 1'b1 };
state_in_iii <= state_ii; // release
end
endcase
end
end
end
// iii
always @(posedge clk) begin
state_in_iv <= state_in_iii;
rate_iv <= pre_rate_iii[6] ? 6'd63 : pre_rate_iii[5:0];
end
// iv
always @(posedge clk) begin
state_in_v <= state_in_iv;
rate_v <= rate_iv;
if( state_in_iv == attack )
casex( rate_iv[5:2] )
4'h0: cnt_v <= eg_cnt[13:11];
4'h1: cnt_v <= eg_cnt[12:10];
4'h2: cnt_v <= eg_cnt[11: 9];
4'h3: cnt_v <= eg_cnt[10: 8];
4'h4: cnt_v <= eg_cnt[ 9: 7];
4'h5: cnt_v <= eg_cnt[ 8: 6];
4'h6: cnt_v <= eg_cnt[ 7: 5];
4'h7: cnt_v <= eg_cnt[ 6: 4];
4'h8: cnt_v <= eg_cnt[ 5: 3];
4'h9: cnt_v <= eg_cnt[ 4: 2];
4'ha: cnt_v <= eg_cnt[ 3: 1];
default: cnt_v <= eg_cnt[ 2: 0];
endcase
else
casex( rate_iv[5:2] )
4'h0: cnt_v <= eg_cnt[14:12];
4'h1: cnt_v <= eg_cnt[13:11];
4'h2: cnt_v <= eg_cnt[12:10];
4'h3: cnt_v <= eg_cnt[11: 9];
4'h4: cnt_v <= eg_cnt[10: 8];
4'h5: cnt_v <= eg_cnt[ 9: 7];
4'h6: cnt_v <= eg_cnt[ 8: 6];
4'h7: cnt_v <= eg_cnt[ 7: 5];
4'h8: cnt_v <= eg_cnt[ 6: 4];
4'h9: cnt_v <= eg_cnt[ 5: 3];
4'ha: cnt_v <= eg_cnt[ 4: 2];
4'hb: cnt_v <= eg_cnt[ 3: 1];
default: cnt_v <= eg_cnt[ 2: 0];
endcase
end
// v
always @(posedge clk) begin
state_in_vi <= state_in_v;
rate_vi <= rate_v[5:1];
sum_up <= cnt_v[0] != cnt_out;
step_vi <= step_v;
end
///////////////////////////////////////
// vi
reg [8:0] ar_sum0_vi;
reg [9:0] ar_result_vi, ar_sum_vi;
always @(*) begin : ar_calculation
casex( rate_vi[5:2] )
default: ar_sum0_vi = eg_vi[9:4] + 1'd1;
4'b1100: ar_sum0_vi = eg_vi[9:4] + 1'd1;
4'b1101: ar_sum0_vi = eg_vi[9:3] + 1'd1;
4'b111x: ar_sum0_vi = eg_vi[9:2] + 1'd1;
endcase
if( rate_vi[5:4] == 2'b11 )
ar_sum_vi = step_vi ? { ar_sum0_vi, 1'b0 } : { 1'b0, ar_sum0_vi };
else
ar_sum_vi = step_vi ? { 1'b0, ar_sum0_vi } : 10'd0;
ar_result_vi = ar_sum_vi<eg_vi ? eg_vi-ar_sum_vi : 10'd0;
end
always @(posedge clk) begin
if( ar_off_vi )
eg_vii <= 10'd0;
else
if( state_in_vi == attack ) begin
if( sum_up && eg_vi != 10'd0 )
if( rate_vi[5:1]==4'hf )
eg_vii <= 10'd0;
else
eg_vii <= ar_result_vi;
else
eg_vii <= eg_vi;
end
else begin : decay_sum
if( sum_up ) begin
if ( eg_vi<= (10'd1023-10'd8) )
case( rate_vi[5:2] )
4'b1100: eg_vii <= eg_vi + { step_vi, ~step_vi }; // 12
4'b1101: eg_vii <= eg_vi + { step_vi, ~step_vi, 1'b0 }; // 13
4'b1110: eg_vii <= eg_vi + { step_vi, ~step_vi, 2'b0 }; // 14
4'b1111: eg_vii <= eg_vi + 4'd8;// 15
default: eg_vii <= eg_vi + { step_vi, 1'b0 };
endcase
else eg_vii <= 10'h3ff;
end
else eg_vii <= eg_vi;
end
end
// vii
always @(*) begin : sum_eg_and_tl
casex( {amsen_vii, ams_vii } )
3'b0xx,3'b100: am_final_vii = 9'd0;
3'b101: am_final_vii = { 2'b00, am };
3'b110: am_final_vii = { 1'b0, am, 1'b0};
3'b111: am_final_vii = { am, 2'b0 };
endcase
`ifdef test_support
if( test_eg && tl_vii!=7'd0 )
sum_eg_tl_vii = 11'd0;
else
`endif
sum_eg_tl_vii = { tl_vii, 3'd0 }
+ eg_vii
+ { am_final_vii, 1'b0 };
end
always @(posedge clk) begin
eg_viii <= sum_eg_tl_vii[11:10] > 2'b0 ? {10{1'b1}} : sum_eg_tl_vii[9:0];
end
jt51_sh #( .width(10), .stages(3) ) u_egpadding (
.clk ( clk ),
.din ( eg_viii ),
.drop ( eg_xi )
);
// shift registers
jt51_sh #( .width(10), .stages(32-7+2) ) u_eg1sh(
.clk ( clk ),
.din ( eg_vii ),
.drop ( eg_ii )
);
jt51_sh #( .width(10), .stages(4) ) u_eg2sh(
.clk ( clk ),
.din ( eg_ii ),
.drop ( eg_vi )
);
jt51_sh #( .width(1), .stages(4) ) u_aroffsh(
.clk ( clk ),
.din ( ar_off_ii ),
.drop ( ar_off_vi )
);
jt51_sh #( .width(1), .stages(32) ) u_konsh(
.clk ( clk ),
.din ( keyon_ii ),
.drop ( keyon_last_ii )
);
jt51_sh #( .width(1), .stages(32) ) u_cntsh(
.clk ( clk ),
.din ( cnt_v[0] ),
.drop ( cnt_out )
);
jt51_sh #( .width(2), .stages(32-3+2) ) u_statesh(
.clk ( clk ),
.din ( state_in_iii ),
.drop ( state_ii )
);
`ifdef simulation
/* verilator lint_off pinmissing */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt));
sep32 #(.width(10),.stg(11)) sep_eg(
.clk ( clk ),
.mixed ( eg_xi ),
.cnt ( cnt )
);
sep32 #(.width(7),.stg(7)) sep_tl(
.clk ( clk ),
.mixed ( tl_vii ),
.cnt ( cnt )
);
sep32 #(.width(2),.stg(2)) sep_state(
.clk ( clk ),
.mixed ( state_ii ),
.cnt ( cnt )
);
sep32 #(.width(5),.stg(6)) sep_rate(
.clk ( clk ),
.mixed ( rate_vi ),
.cnt ( cnt )
);
sep32 #(.width(9),.stg(7)) sep_amfinal(
.clk ( clk ),
.mixed ( am_final_vii ),
.cnt ( cnt )
);
/* verilator lint_on pinmissing */
`endif
endmodule
|
/*
* lzw - Simple, Logarithmic Left Shift Unit Test
* Copyright (C) 2015 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_TEST_LEFT_SHIFT
`else
`define INC_TEST_LEFT_SHIFT
`timescale 1 ns / 100 ps
module sub_test_LeftShift();
localparam LOGWORD = 7;
localparam WORD = (1<<LOGWORD);
localparam TEST_MIN_SHIFT = 0;
localparam TEST_MAX_SHIFT = WORD;
localparam TEST_MIN_IVALUE = 0;
localparam TEST_MAX_IVALUE = 32; // this range will be shifted down to -16 to 15
wire [WORD-1:0] test_ovalue;
reg [WORD+1-1:0] test_ivalue; // +1 just for good measure
reg [LOGWORD+1-1:0] test_shift; // +1 just for good measure
reg [LOGWORD+1-1:0] test_step; // +1 just for good measure
reg [WORD-1:0] test_validate;
reg test_error;
initial begin
test_error = 0;
for(test_shift=TEST_MIN_SHIFT; test_shift<TEST_MAX_SHIFT; test_shift=test_shift+1) begin
for(test_step=0; test_step<TEST_MAX_IVALUE; test_step=test_step+1) begin
test_ivalue <= (test_step - (TEST_MAX_IVALUE/2));
#5;
test_validate = test_ivalue;
test_validate = test_validate<<test_shift;
if(test_ovalue !== test_validate) begin
$display(
"ERROR: Input:(shift:%d ivalue:%x) => Actual:(ovalue:%x) Expected(ovalue:%x)",
test_shift[LOGWORD-1:0],
test_ivalue[WORD-1:0],
test_ovalue[WORD-1:0],
test_validate[WORD-1:0]
);
test_error = 1;
end
#5;
end
end
if(test_error) begin
$display("TEST FAILED");
$exit(-1);
end
else begin
$display("TEST PASSED");
$finish();
end
end
LeftShift #(
.LOGWORD(LOGWORD)
)
i_leftshift (
.ovalue (test_ovalue[WORD-1:0] ),
.ivalue (test_ivalue[WORD-1:0] ),
.amount (test_shift[LOGWORD-1:0] )
);
endmodule
module test_LeftShift();
sub_test_LeftShift i_test();
initial begin
$dumpfile("test_LeftShift.vcd");
$dumpvars(0, i_test);
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
/*
Copyright (C) {2014} {James Thomas} <jamesjoethomas@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//////////////////////////////////////////////////////////////////////////////////
/*
output starts on same cycle start is asserted
high-order bits produced first
input only needs to be supplied on the cycle that start is high
produces zeros if input exhausted
assume W > 1
*/
module par_to_ser #(parameter W=8)
(input clk /* device clock */, input[W-1:0] par,
input start, output ser);
reg[W-1:0] par_reg = 0;
always @(posedge clk) begin
if (start) begin
par_reg <= {par[W-2:0], 1'b0};
end
else begin
par_reg <= {par_reg[W-2:0], 1'b0};
end
end
assign ser = start ? par[W-1] : par_reg[W-1];
endmodule
/*
output appears W-1 clock cycles after first serial bit sent
assume high-order bits are input first
assume W > 2
*/
module ser_to_par #(parameter W=8)
(input clk /* device clock */, input ser,
output[W-1:0] par);
reg[W-2:0] par_reg = 0;
always @(posedge clk) begin
par_reg <= {par_reg[W-3:0], ser};
end
assign par = {par_reg, ser};
endmodule
/*
reduces the system clock by a factor of 6
*/
module acc_clk(input clk /* system clock */, output dev_clk);
parameter TICKS = 9;
reg [3:0] count = 0;
reg sig_reg = 0;
always @(posedge clk) begin
if (count == TICKS) begin
// flip at half period
sig_reg <= ~sig_reg;
count <= 0;
end
else begin
count <= count + 1;
end
end
assign dev_clk = sig_reg;
endmodule
/*
assert in_ready when a new datapoint is available, avg_ready will
be signalled after 32 data points have been folded into the average
*/
module moving_avg(
input clock, in_ready, reset,
input signed [15:0] data,
output signed [15:0] avg,
output avg_ready
);
// circular buffer
reg signed [15:0] samples [31:0];
reg [4:0] offset = 0;
reg signed [15:0] accum = 0;
reg [5:0] num_samples = 0;
reg signed [15:0] data_right_shift;
always @(*) begin
data_right_shift = {data[15], data[15], data[15], data[15],
data[15], data[15:5]};
end
always @(posedge clock) begin
if (reset) begin
accum <= 0;
num_samples <= 0;
offset <= 0;
end
else if (in_ready) begin
num_samples <= (num_samples == 6'd32) ? num_samples : num_samples + 1;
samples[offset] <= data_right_shift;
if (num_samples == 6'd32) begin
accum <= accum + data_right_shift - samples[offset];
end
else begin
accum <= accum + data_right_shift;
end
offset <= offset + 1;
end
end
assign avg = accum;
assign avg_ready = (num_samples == 6'd32) ? 1 : 0;
endmodule
/*
ready permanently asserted after initialization completed
acc operates completely with the slowed accelerometer clock
*/
module acc(input clk /* system clock */, sdo, reset,
output ncs, sda, scl, ready, output signed [15:0] x, y);
// TODO use state machine -- transition through all of the initiatialization states (each
// register), then rotate through the value reading states
// one cycle gap between states to allow for CS deassertion
parameter MEASURE_INIT = 0;
parameter X_READ = 1;
parameter Y_READ = 2;
reg[1:0] state = MEASURE_INIT; // TODO: set the right number of bits for this
reg[4:0] count = 0; // TODO: set the right number of bits for this
reg ncs_reg;
wire dev_clk;
acc_clk ac(.clk(clk), .dev_clk(dev_clk));
reg[7:0] par_in;
reg pts_start;
par_to_ser pts(.clk(dev_clk), .par(par_in), .start(pts_start), .ser(sda));
wire[7:0] par_out;
ser_to_par stp(.clk(dev_clk), .ser(sdo), .par(par_out));
reg ma_x_in_ready;
reg [7:0] x_low_bits = 0;
reg signed [15:0] ma_x_in;
wire ma_x_avg_ready;
wire signed [15:0] ma_x_avg;
moving_avg ma_x(
.clock(dev_clk), .in_ready(ma_x_in_ready), .reset(reset),
.data(ma_x_in),
.avg(ma_x_avg),
.avg_ready(ma_x_avg_ready)
);
reg ma_y_in_ready;
reg [7:0] y_low_bits = 0;
reg signed [15:0] ma_y_in;
wire ma_y_avg_ready;
wire signed [15:0] ma_y_avg;
moving_avg ma_y(
.clock(dev_clk), .in_ready(ma_y_in_ready), .reset(reset),
.data(ma_y_in),
.avg(ma_y_avg),
.avg_ready(ma_y_avg_ready)
);
// invariants: when transitioning out of a state always set counter to 0
always @(posedge dev_clk) begin
case (state)
MEASURE_INIT: begin
if (count == 5'd18) begin
count <= 0;
state <= X_READ;
end
else begin
count <= count + 1;
end
end
X_READ: begin
if (count == 5'd25) begin
count <= 0;
state <= Y_READ;
end
else begin
count <= count + 1;
end
if (count == 5'd17) begin
x_low_bits <= par_out;
end
end
Y_READ: begin
if (count == 5'd25) begin
count <= 0;
state <= X_READ;
end
else begin
count <= count + 1;
end
if (count == 5'd17) begin
y_low_bits <= par_out;
end
end
endcase
end
always @(*) begin
case (state)
MEASURE_INIT: begin
pts_start = (count == 5'd2 || count == 5'd10) ? 1 : 0;
if (count == 5'd2) begin
par_in = 8'h2D; // 0 for W, 0 for MB
end
else if (count == 5'd10) begin
par_in = 8'h08; // set measure bit
end
else begin
par_in = 0;
end
ma_x_in_ready = 0; ma_x_in = 0;
ma_y_in_ready = 0; ma_y_in = 0;
ncs_reg = (count == 5'd18 || count == 5'd0) ? 1 : 0;
end
X_READ: begin
pts_start = (count == 5'd1) ? 1 : 0;
par_in = (count == 5'd1) ? 8'hF2 : 0; // 1 for R, 1 for MB
ma_x_in_ready = (count == 5'd25) ? 1 : 0;
ma_x_in = (count == 5'd25) ? {par_out, x_low_bits} : 0;
ma_y_in_ready = 0; ma_y_in = 0;
ncs_reg = (count == 5'd25) ? 1 : 0;
end
Y_READ: begin
pts_start = (count == 5'd1) ? 1 : 0;
par_in = (count == 5'd1) ? 8'hF4 : 0; // 1 for R, 1 for MB
ma_y_in_ready = (count == 5'd25) ? 1 : 0;
ma_y_in = (count == 5'd25) ? {par_out, y_low_bits} : 0;
ma_x_in_ready = 0; ma_x_in = 0;
ncs_reg = (count == 5'd25) ? 1 : 0;
end
endcase
end
assign scl = (ncs_reg == 1 || (state == MEASURE_INIT && count == 5'd1
|| state != MEASURE_INIT && count == 5'd0)) ? 1 : dev_clk;
assign ncs = ncs_reg;
assign ready = ma_x_avg_ready && ma_y_avg_ready;
assign x = ma_x_avg;
assign y = ma_y_avg;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg ack,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd4;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd3;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0
* 6 cycles when tim_cas = 1
*/
reg ack_read3;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack_read3 <= 1'b0;
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
if(tim_cas) begin
ack_read3 <= read;
ack_read2 <= ack_read3;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0|write;
ack <= ack0;
end
end
/* during a 4-word write, we drive the pins for 5 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg write_d;
reg [2:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 3'd0;
direction <= 1'b0;
end else begin
if(write_d) begin
counter_writedirection <= 3'b101;
direction <= 1'b1;
end else begin
if(counter_writedirection == 3'b001)
direction <= 1'b0;
if(direction)
counter_writedirection <= counter_writedirection - 3'd1;
end
end
end
assign direction_r = write_d|(|counter_writedirection);
always @(posedge sys_clk) begin
if(sdram_rst)
write_d <= 1'b0;
else
write_d <= write;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]),
.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
|
// copyright 2017 eth zurich and university of bologna.
// copyright and related rights are licensed under the solderpad hardware
// license, version 0.51 (the “license”); you may not use this file except in
// compliance with the license. you may obtain a copy of the license at
// http://solderpad.org/licenses/shl-0.51. unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this license is distributed on an “as is” basis, without warranties or
// conditions of any kind, either express or implied. see the license for the
// specific language governing permissions and limitations under the license.
module dc_token_ring_fifo_din(clk, rstn, data, valid, ready, write_token, read_pointer, data_async);
parameter data_width = 10;
parameter buffer_depth = 8;
input clk;
input rstn;
input [data_width - 1 : 0] data;
input valid;
output ready;
output [buffer_depth - 1 : 0] write_token;
input [buffer_depth - 1 : 0] read_pointer;
output [data_width - 1 : 0] data_async;
wire stall;
wire write_enable;
wire [buffer_depth - 1 : 0] write_pointer;
assign ready = ~stall;
// fifo read/write enable
assign write_enable = (valid & ready);
// actual fifo
dc_data_buffer
#(
.data_width ( data_width ),
.buffer_depth ( buffer_depth )
)
buffer
(
.clk ( clk ),
.rstn ( rstn ),
.write_pointer ( write_pointer ),
.write_data ( data ),
.read_pointer ( read_pointer ),
.read_data ( data_async )
);
// logic to compute the read, write pointers
dc_token_ring
#(
.buffer_depth ( buffer_depth ),
.reset_value ( 'hc )
)
write_tr
(
.clk ( clk ),
.rstn ( rstn ),
.enable ( write_enable ),
.state ( write_token )
);
// pointers to the write, read addresses (semi-accurate, leveraging the two-hot encoding for extra robustness)
assign write_pointer = {write_token[buffer_depth - 2 : 0], write_token[buffer_depth - 1]} & write_token;
// full detector
dc_full_detector
#(
.buffer_depth ( buffer_depth )
)
full
(
.clk ( clk ),
.rstn ( rstn ),
.read_pointer ( read_pointer ),
.write_pointer ( write_pointer ),
.valid ( valid ),
.full ( stall )
);
endmodule
|
/*
ddr3 dram controller
(c) copyright 2012 silicon on inspiration
www.sioi.com.au
86 longueville road
lane cove 2066
new south wales
australia
slightly modified by chris pavlina to fit pinout changes
in c4-0.
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu lesser general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu lesser general public license for more details.
you should have received a copy of the gnu lesser general public license
along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module drac_ddr3
(
input ckin,
output ckout,
output ckouthalf,
output reset,
inout [63:0] ddq,
inout [7:0] dqsp,
inout [7:0] dqsn,
output [7:0] ddm,
output [15:0] da,
output [2:0] dba,
output [2:0] dcmd,
output [1:0] dce,
output [1:0] dcs,
output [1:0] dckp,
output [1:0] dckn,
output [1:0] dodt,
input srd,
input swr,
input [33:5] sa,
input [255:0] swdat,
input [31:0] smsk,
output [255:0] srdat,
output srdy,
input [2:0] dbg_out,
output [7:0] dbg_in
);
reg read;
reg read2;
reg ack;
reg [15:0] rddr_addr;
reg [2:0] rddr_bankaddr;
reg [1:0] rddr_cs_n;
reg [2:0] rddr_cmd;
reg [1:0] rddr_cke;
reg [1:0] rddr_odt;
reg [2:0] state;
reg [2:0] rtn;
reg [5:0] dly;
reg [10:0] rfcntr;
reg refresh;
reg rpulse0;
reg rpulse1;
reg rpulse2;
reg rpulse3;
reg rpulse4;
reg rpulse5;
reg rpulse6;
reg rpulse7;
reg wpulse0;
reg [255:0] q;
wire [7:0] dm;
wire [7:0] dm_t;
wire [7:0] wddr_dm;
wire [7:0] wddr_dqs;
wire [63:0] dq_i;
wire [63:0] dq_i_dly;
wire [255:0] wq;
wire [63:0] dq_o;
wire [63:0] dq_t;
wire [63:0] wddr_dq;
reg [255:0] rwdat;
reg [31:0] rsmsk;
reg [13:0] rlock = 0;
reg rclrpll = 1;
reg [13:0] rstart = 0;
reg rstarted = 0;
reg [63:0] rchgdelay;
reg [63:0] rincdelay;
reg [63:0] rcaldelay;
reg [63:0] rcaldelay2;
reg [63:0] rrstdelay;
// set up clocks for ddr3. use circuitry based on ug382 ch 1 pp33,34
// generate the following clocks:
//
// ck600 600mhz clock for dq ioserdes2 high speed clock
// ck600_180 600mhz clock for dqs oserdes2 high speed clock
// dqs clocking lags dq clocking by half of one bit time
// ck150 1/4 speed clock for ioserdes2 parallel side and control logic
// ck75 clock for microblaze cpu
//
// create two copies of the 600mhz clocks, providing separate copies for
// bank 1 and bank 3. this is necessary as each bufpll reaches only a
// single bank. the other clocks are global (bufg).
wire ck600raw;
wire ck600_180raw;
wire ck150;
wire ck150raw;
wire ck75;
wire ck75raw;
wire [1:0] ck600;
wire [1:0] ck600_180;
wire [1:0] strobe;
wire [1:0] strobe180;
// ddr3 dimm byte lane levelling is achieved with these iodelay2 settings:
parameter lvl_wslope = 3;
parameter lvl_wphase = 6;
bufg bufg_main
(
.o (ckinb),
.i (ckin)
);
pll_base
#(
.bandwidth ("optimized"),
.clk_feedback ("clkfbout"),
.compensation ("internal"),
.divclk_divide (3),
.clkfbout_mult (29),
.clkfbout_phase (0.000),
.clkout0_divide (1),
.clkout0_phase (0.000),
.clkout0_duty_cycle (0.500),
.clkout1_divide (1),
.clkout1_phase (180.000),
.clkout1_duty_cycle (0.500),
.clkout2_divide (4),
.clkout2_phase (0.000),
.clkout2_duty_cycle (0.500),
.clkout3_divide (8),
.clkout3_phase (0.0),
.clkout3_duty_cycle (0.500),
.clkout4_divide (8),
.clkout4_phase (0.0),
.clkout4_duty_cycle (0.500),
.clkout5_divide (8),
.clkout5_phase (0.000),
.clkout5_duty_cycle (0.500),
.clkin_period (16.000)
)
pll_base_main
(
.clkfbout (pllfb0),
.clkout0 (ck600raw),
.clkout1 (ck600_180raw),
.clkout2 (ck150raw),
.clkout3 (ck75raw),
.clkout4 (),
.clkout5 (),
.locked (locked),
.rst (rclrpll),
.clkfbin (pllfb0),
.clkin (ckinb)
);
bufg bufg_150
(
.o (ck150),
.i (ck150raw)
);
bufg bufg_75
(
.o (ck75),
.i (ck75raw)
);
genvar i;
generate
for (i = 0; i <= 1; i = i + 1) begin: bufplls
bufpll
#(
.divide (4),
.enable_sync ("true")
)
bufpll_600
(
.ioclk (ck600[i]),
.lock (dbg_in[i]),
.serdesstrobe (strobe[i]),
.gclk (ck150),
.locked (locked),
.pllin (ck600raw)
);
bufpll
#(
.divide (4),
.enable_sync ("true")
)
bufpll_600_18
(
.ioclk (ck600_180[i]),
.lock (dbg_in[2 + i]),
.serdesstrobe (strobe180[i]),
.gclk (ck150),
.locked (locked),
.pllin (ck600_180raw)
);
end
// clocks, two
wire [1:0] ckp;
wire [1:0] ckn;
for (i = 0; i <= 1; i = i + 1) begin: ddro_clks
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dckp
(
.d1 (1'b0),
.d2 (1'b1),
.d3 (1'b0),
.d4 (1'b1),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[1]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (ckp[i]),
.tq (),
.ioce (strobe180[1]),
.tce (1'b1),
.rst (reset)
);
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dckn
(
.d1 (1'b1),
.d2 (1'b0),
.d3 (1'b1),
.d4 (1'b0),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[1]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (ckn[i]),
.tq (),
.ioce (strobe180[1]),
.tce (1'b1),
.rst (reset)
);
obuf obuft_ckp
(
.o(dckp[i]),
.i(ckp[i])
);
obuf obuf_ckn
(
.o(dckn[i]),
.i(ckn[i])
);
end
// address, bank address
// nb isim can't grok parameter arrays, hence the following sim/synth bifurcation
`ifdef xilinx_isim
`else
// bank id here are backwards from the sioi original, as i mirrored the pcb
// layout. bank 1 (bufpll_x2y3) is '1'; bank 3 (bufpll_x0y3) is '0'.
parameter integer bank_a[15:0] = {0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 1};
// f e d c b a 9 8 7 6 5 4 3 2 1 0
parameter integer bank_ba[2:0] = {0, 1, 1};
// 2 1 0
`endif
wire [15:0] wa;
for (i = 0; i <= 15; i = i + 1) begin: ddro_a
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_a
(
.d1 (rddr_addr[i]),
.d2 (rddr_addr[i]),
.d3 (rddr_addr[i]),
.d4 (rddr_addr[i]),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
`ifdef xilinx_isim
.clk0 (ck600_180[0]),
`else
.clk0 (ck600_180[bank_a[i]]),
`endif
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wa[i]),
.tq (),
`ifdef xilinx_isim
.ioce (strobe180[0]),
`else
.ioce (strobe180[bank_a[i]]),
`endif
.tce (1'b1),
.rst (reset)
);
obuf obuf_a
(
.o(da[i]),
.i(wa[i])
);
end
wire [2:0] wba;
for (i = 0; i <= 2; i = i + 1) begin: ddro_ba
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_ba
(
.d1 (rddr_bankaddr[i]),
.d2 (rddr_bankaddr[i]),
.d3 (rddr_bankaddr[i]),
.d4 (rddr_bankaddr[i]),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
`ifdef xilinx_isim
.clk0 (ck600_180[0]),
`else
.clk0 (ck600_180[bank_ba[i]]),
`endif
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wba[i]),
.tq (),
`ifdef xilinx_isim
.ioce (strobe180[0]),
`else
.ioce (strobe180[bank_ba[i]]),
`endif
.tce (1'b1),
.rst (reset)
);
obuf obuf_ba
(
.o(dba[i]),
.i(wba[i])
);
end
// command, chipselect
wire [2:0] wkmd;
for (i = 0; i <= 2; i = i + 1) begin: ddro_kmd
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_kmd
(
.d1 (rddr_cmd[i]), // command for 1 cycle
.d2 (rddr_cmd[i]),
.d3 (1'b1), // nop thereafter
.d4 (1'b1),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[1]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wkmd[i]),
.tq (),
.ioce (strobe180[1]),
.tce (1'b1),
.rst (reset)
);
obuf obuf_kmd
(
.o(dcmd[i]),
.i(wkmd[i])
);
end
wire [1:0] wcs;
for (i = 0; i <= 1; i = i + 1) begin: ddro_cs
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_cs
(
.d1 (rddr_cs_n[i]),
.d2 (rddr_cs_n[i]),
.d3 (rddr_cs_n[i]),
.d4 (rddr_cs_n[i]),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[1]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wcs[i]),
.tq (),
.ioce (strobe180[1]),
.tce (1'b1),
.rst (reset)
);
obuf obuf_cs
(
.o(dcs[i]),
.i(wcs[i])
);
end
// cke, odt
wire [1:0] wcke;
for (i = 0; i <= 1; i = i + 1) begin: ddro_cke
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_cke
(
.d1 (rddr_cke[i]),
.d2 (rddr_cke[i]),
.d3 (rddr_cke[i]),
.d4 (rddr_cke[i]),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[0]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wcke[i]),
.tq (),
.ioce (strobe180[0]),
.tce (1'b1),
.rst (reset)
);
obuf obuf_cke
(
.o(dce[i]),
.i(wcke[i])
);
end
wire [1:0] wodt;
for (i = 0; i <= 1; i = i + 1) begin: ddro_odt
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_odt
(
.d1 (rddr_odt[i]),
.d2 (rddr_odt[i]),
.d3 (rddr_odt[i]),
.d4 (rddr_odt[i]),
.t1 (1'b0),
.t2 (1'b0),
.t3 (1'b0),
.t4 (1'b0),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[1]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (wodt[i]),
.tq (),
.ioce (strobe180[1]),
.tce (1'b1),
.rst (reset)
);
obuf obuf_odt
(
.o(dodt[i]),
.i(wodt[i])
);
end
// dq strobes, 8 differential pairs
wire [7:0] dqso;
wire [7:0] dqso_d;
wire [7:0] dqst;
wire [7:0] dqst_d;
wire [7:0] dqson;
wire [7:0] dqson_d;
wire [7:0] dqstn;
wire [7:0] dqstn_d;
wire [7:0] dummy;
wire [7:0] dummyp;
wire [7:0] dummyn;
for (i = 0; i <= 7; i = i + 1) begin: ddrio_dqs
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dqsp
(
.d1 (1'b0),
.d2 (1'b1),
.d3 (1'b0),
.d4 (1'b1),
.t1 (read),
.t2 (read),
.t3 (read),
.t4 (read),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[i >> 2]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (dqso[i]),
.tq (dqst[i]),
.ioce (strobe180[i >> 2]),
.tce (1'b1),
.rst (reset)
);
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dqsn
(
.d1 (1'b1),
.d2 (1'b0),
.d3 (1'b1),
.d4 (1'b0),
.t1 (read),
.t2 (read),
.t3 (read),
.t4 (read),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600_180[i >> 2]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (dqson[i]),
.tq (dqstn[i]),
.ioce (strobe180[i >> 2]),
.tce (1'b1),
.rst (reset)
);
iodelay2
#(
.data_rate ("sdr"),
.odelay_value (lvl_wphase + i * lvl_wslope),
.idelay_value (lvl_wphase + i * lvl_wslope),
.idelay_type ("fixed"),
.delay_src ("io")
)
iodelay2_dqsp
(
.odatain (dqso[i]),
.dout (dqso_d[i]),
.t (dqst[i]),
.tout (dqst_d[i]),
.idatain (dummyp[i])
);
iodelay2
#(
.data_rate ("sdr"),
.odelay_value (lvl_wphase + i * lvl_wslope),
.idelay_value (lvl_wphase + i * lvl_wslope),
.idelay_type ("fixed"),
.delay_src ("io")
)
iodelay2_dqsn
(
.odatain (dqson[i]),
.dout (dqson_d[i]),
.t (dqstn[i]),
.tout (dqstn_d[i]),
.idatain (dummyn[i])
);
iobuf iobuf_dqsp
(
.o(dummyp[i]),
.io(dqsp[i]),
.i(dqso_d[i]),
.t(dqst_d[i])
);
iobuf iobuf_dqsn
(
.o(dummyn[i]),
.io(dqsn[i]),
.i(dqson_d[i]),
.t(dqstn_d[i])
);
end
// data masks, 8
wire [7:0] dmo;
wire [7:0] dmo_d;
wire [7:0] dmt;
wire [7:0] dmt_d;
for (i = 0; i <= 7; i = i + 1) begin: ddro_dm
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dm
(
.d1 (rsmsk[i]),
.d2 (rsmsk[i + 8]),
.d3 (rsmsk[i + 16]),
.d4 (rsmsk[i + 24]),
.t1 (read),
.t2 (read),
.t3 (read),
.t4 (read),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600[i >> 2]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (dmo[i]),
.tq (dmt[i]),
.ioce (strobe[i >> 2]),
.tce (1'b1),
.rst (reset)
);
iodelay2
#(
.data_rate ("sdr"),
.odelay_value (lvl_wphase + i * lvl_wslope),
.idelay_value (lvl_wphase + i * lvl_wslope),
.idelay_type ("fixed"),
.delay_src ("io")
)
iodelay2_dm
(
.odatain (dmo[i]),
.dout (dmo_d[i]),
.t (dmt[i]),
.tout (dmt_d[i]),
.idatain (dummy[i])
);
iobuf iobuf_dm
(
.o(dummy[i]),
.io(ddm[i]),
.i(dmo_d[i]),
.t(dmt_d[i])
);
end
// dq lines, 64
wire [63:0] dqo;
wire [63:0] dqo_d;
wire [63:0] dqt;
wire [63:0] dqt_d;
wire [63:0] dqi;
wire [63:0] dqi_d;
for (i = 0; i <= 63; i = i + 1) begin: ddrio_dq
oserdes2
#(
.data_rate_oq ("sdr"),
.data_rate_ot ("sdr"),
.train_pattern (0),
.data_width (4),
.serdes_mode ("none"),
.output_mode ("single_ended")
)
oserdes2_dq
(
.d1 (rwdat[i]),
.d2 (rwdat[i + 64]),
.d3 (rwdat[i + 128]),
.d4 (rwdat[i + 192]),
.t1 (read),
.t2 (read),
.t3 (read),
.t4 (read),
.shiftin1 (1'b1),
.shiftin2 (1'b1),
.shiftin3 (1'b1),
.shiftin4 (1'b1),
.shiftout1 (),
.shiftout2 (),
.shiftout3 (),
.shiftout4 (),
.train (1'b0),
.oce (1'b1),
.clk0 (ck600[i >> 5]),
.clk1 (1'b0),
.clkdiv (ck150),
.oq (dqo[i]),
.tq (dqt[i]),
.ioce (strobe[i >> 5]),
.tce (1'b1),
.rst (reset)
);
iodelay2
#(
.data_rate ("sdr"),
.idelay_value (0),
.odelay_value (lvl_wphase + ((i * lvl_wslope) >> 3)),
.idelay_type ("variable_from_zero"),
.delay_src ("io")
)
iodelay2_dq
(
.odatain (dqo[i]),
.dout (dqo_d[i]),
.t (dqt[i]),
.tout (dqt_d[i]),
.idatain (dqi[i]),
.dataout (dqi_d[i]),
.ce (rchgdelay[i]),
.inc (rincdelay[i]),
.clk (ck150),
.cal (rcaldelay2[i]),
.rst (rrstdelay[i]),
.ioclk0 (ck600[i >> 5])
);
iobuf iobuf_dq
(
.o(dqi[i]),
.io(ddq[i]),
.i(dqo_d[i]),
.t(dqt_d[i])
);
iserdes2
#(
.bitslip_enable ("false"),
.data_rate ("sdr"),
.data_width (4),
.interface_type ("retimed"),
.serdes_mode ("none")
)
iserdes2_dq
(
.q1 (wq[i]),
.q2 (wq[i + 64]),
.q3 (wq[i + 128]),
.q4 (wq[i + 192]),
.shiftout (),
.incdec (),
.valid (),
.bitslip (),
.ce0 (read),
.clk0 (ck600[i >> 5]),
.clk1 (1'b0),
.clkdiv (ck150),
.d (dqi_d[i]),
.ioce (strobe[i >> 5]),
.rst (reset),
.shiftin (),
.fabricout (),
.cfb0 (),
.cfb1 (),
.dfb ()
);
end
endgenerate
// ddr commands
parameter k_lmr = 3'h0; // load mode register (mode register set)
parameter k_rfsh = 3'h1; // refresh (auto or self)
parameter k_close = 3'h2; // aka precharge
parameter k_open = 3'h3; // aka activate
parameter k_write = 3'h4;
parameter k_read = 3'h5;
parameter k_zqcal = 3'h6; // zq calibration
parameter k_nop = 3'h7;
// states
parameter s_init = 3'h3;
parameter s_init2 = 3'h5;
parameter s_idle = 3'h0;
parameter s_read = 3'h1;
parameter s_write = 3'h2;
parameter s_pause = 3'h4;
// main ddr3 timings spec @150mhz
// tras ras time 37.5 ns 6 clks open to close
// trc ras cycle 50.6 ns 8 clks open to next open
// trp ras precharge 13.1 ns 2 clks close to open
// trrd ras to ras delay 4 clks 4 clks
// trcd ras to cas delay 13.2 ns 2 clks
// cl cas latency 5 clks 5 clks
// twr write time 15 ns 3 clks write finished to close issued
// twtr write to read 4 clks 4 clks write finished to read issued
// trfc refresh command 1gb 110ns 17 clks refresh command time for 1gb parts
// trfc refresh command 2gb 160ns 24 clks refresh command time for 2gb parts
// trfc refresh command 4gb 260ns 39 clks refresh command time for 4gb parts
// trefi refresh interval 7.8 us 1170 clks
// tdqss dqs start +-0.25 clks time from ddr_clk to dqs
parameter trfc = 39;
parameter trcd = 3;
parameter trp = 3;
// provide the pll with a good long start up reset
always @ (posedge ckinb) begin
if (rlock[13] == 1'b1) begin
rclrpll <= 1'b0;
end else begin
rclrpll <= 1'b1;
rlock <= rlock + 14'b1;
end
end
// hold the rest of the system in reset until the pll has been locked for
// a good long while
always @ (posedge ckinb) begin
if (rstart[13] == 1'b1) begin
rstarted <= 1'b1;
end else begin
rstarted <= 1'b0;
if (locked) begin
rstart <= rstart + 14'b1;
end else begin
rstart <= 0;
end
end
end
// add pipeline delays as required to make it easy for par to meet timing
always @ (posedge ck150) begin
q <= wq;
rwdat <= swdat;
rsmsk <= smsk;
rcaldelay2 <= rcaldelay;
end
always @ (posedge reset or posedge ck150)
if (reset) begin
rddr_cke <= 2'b00;
rddr_cs_n <= 2'b11;
rddr_odt <= 2'b00;
rddr_cmd <= k_nop;
state <= s_init;
dly <= 0;
rtn <= 0;
rfcntr <= 0;
refresh <= 0;
ack <= 0;
rpulse0 <= 0;
wpulse0 <= 0;
rchgdelay <= 64'd0;
rincdelay <= 64'd0;
rcaldelay <= 64'd0;
rrstdelay <= 64'd0;
end else begin
if (rfcntr[10:7] == 4'b1001) begin // 1153/150mhz ~7.7us
rfcntr <= 0;
refresh <= 1;
end else
rfcntr <= rfcntr + 11'b1;
rpulse1 <= rpulse0;
rpulse2 <= rpulse1;
rpulse3 <= rpulse2;
rpulse4 <= rpulse3;
rpulse5 <= rpulse4;
rpulse6 <= rpulse5;
rpulse7 <= rpulse6;
case (dbg_out[2:0])
3'd0: begin
ack <= wpulse0 | rpulse4;
end
3'd1: begin
ack <= wpulse0 | rpulse5;
end
3'd2: begin
ack <= wpulse0 | rpulse6;
end
3'd3: begin
ack <= wpulse0 | rpulse7;
end
3'd4: begin
ack <= wpulse0 | rpulse4;
end
3'd5: begin
ack <= wpulse0 | rpulse5;
end
3'd6: begin
ack <= wpulse0 | rpulse6;
end
3'd7: begin
ack <= wpulse0 | rpulse7;
end
endcase
case (state)
s_init: begin
rddr_cke <= 2'b11;
read <= 0;
rddr_bankaddr <= sa[15:13];
rddr_addr <= sa[31:16];
if (swr) begin
rddr_cs_n <= sa[32] ? 2'b01 : 2'b10;
state <= s_init2;
rddr_cmd <= sa[10:8];
wpulse0 <= 1;
end
end
s_init2: begin
rtn <= sa[33] ? s_init : s_idle;
rddr_cmd <= k_nop;
state <= s_pause;
dly <= 20;
wpulse0 <= 0;
end
s_idle: begin
read <= 0;
rddr_odt <= 2'b00;
if (swr) begin
rddr_cmd <= k_open;
state <= s_pause;
rtn <= s_write;
dly <= trcd - 1;
rddr_addr <= sa[31:16];
rddr_bankaddr <= sa[15:13];
rddr_cs_n <= sa[32] ? 2'b01 : 2'b10;
end else if (srd) begin
rddr_cmd <= k_open;
state <= s_pause;
rtn <= s_read;
dly <= trcd - 1;
rddr_addr <= sa[31:16];
rddr_bankaddr <= sa[15:13];
rddr_cs_n <= sa[32] ? 2'b01 : 2'b10;
end else if (refresh) begin
rddr_cmd <= k_rfsh;
state <= s_pause;
rtn <= s_idle;
dly <= trfc - 1;
refresh <= 0;
rddr_cs_n <= 2'b00;
end else begin
rddr_cmd <= k_nop;
rddr_cs_n <= 2'b00;
end
end
// address bits
// ============
// mb pg lwd sa row col bnk cs
// [x] - - - - - - -
// [x] - - - - - - -
// 2 - 0 - - - - -
// 3 - 1 [l] - 0 - -
// 4 - 2 [l] - 1 - -
// 5 - - 5 - 2 - -
// 6 - - 6 - 3 - -
// 7 - - 7 - 4 - -
// 8 - - 8 - 5 - -
// 9 - - 9 - 6 - -
// 10 - - 10 - 7 - -
// 11 - - 11 - 8 - -
// 12 - - 12 - 9 - -
// 13 - - 13 - [p] 0 -
// 14 - - 14 - - 1 -
// 15 - - 15 - - 2 -
// 16 - - 16 0 - - -
// 17 - - 17 1 - - -
// 18 - - 18 2 - - -
// 19 - - 19 3 - - -
// 20 - - 20 4 - - -
// 21 - - 21 5 - - -
// 22 - - 22 6 - - -
// 23 - - 23 7 - - -
// 24 - - 24 8 - - -
// 25 - - 25 9 - - -
// 26 - - 26 10 - - -
// 27 - - 27 11 - - -
// 28 - - 28 12 - - -
// 29 - - 29 13 - - -
// [h] 0 - 30 14 - - -
// [h] 1 - 31 15 - - -
// - 2 - 32 - - - 0
// - 3 - 33 - - - extra address bit for dram init register space
s_write: begin
rddr_cmd <= k_write;
state <= s_pause;
rtn <= s_idle;
dly <= 14; // cwl + 2xfer + twr + trp
rddr_addr[10:0] <= {1'b1, sa[12:5], 2'b00}; // nb two lsbs ignored by ddr3 during write
rddr_addr[12] <= dbg_out[2];
rddr_bankaddr <= sa[15:13];
rddr_odt <= sa[16] ? 2'b10 : 2'b01; // use odt only in one rank, otherwise 40r || 40r -> 20r
wpulse0 <= 1;
if (sa[33]) begin
rchgdelay <= rwdat[63:0];
rincdelay <= rwdat[127:64];
rcaldelay <= rwdat[191:128];
rrstdelay <= rwdat[255:192];
end else begin
rchgdelay <= 64'd0;
rincdelay <= 64'd0;
rcaldelay <= 64'd0;
rrstdelay <= 64'd0;
end
end
s_read: begin
rddr_cmd <= k_read;
state <= s_pause;
rtn <= s_idle;
dly <= 10; // cl + 2xfer + 1 + trp
rddr_addr[10:0] <= {1'b1, sa[12:5], 2'b00};
rddr_addr[12] <= dbg_out[2];
rddr_bankaddr <= sa[15:13];
read <= 1;
rpulse0 <= 1;
end
s_pause: begin
rddr_cmd <= k_nop;
dly <= dly - 6'b000001;
if (dly == 6'b000001)
state <= rtn;
else
state <= s_pause;
rpulse0 <= 0;
wpulse0 <= 0;
rchgdelay <= 64'd0;
rincdelay <= 64'd0;
rcaldelay <= 64'd0;
rrstdelay <= 64'd0;
end
endcase
end
assign srdat = q;
assign srdy = ack;
assign ckouthalf = ck75;
assign ckout = ck150;
assign reset = ~rstarted;
assign dbg_in[4] = locked;
assign dbg_in[7:5] = rddr_cmd;
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <gajjanagadde@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
///////////////////////////////////////////////////////////////////////////////////////////////////
// vga: Generate XVGA display signals (640 x 480 @ 60Hz)
// essentially a copy of staff xvga module with different timings
// Credits: timings from Jose's project (Fall 2011),
// general code from staff xvga module (e.g Lab 3 - pong game)
///////////////////////////////////////////////////////////////////////////////////////////////////
module vga(input vclock,
output reg [9:0] hcount, // pixel number on current line
output reg [9:0] vcount, // line number
output reg vsync,hsync,blank);
// VGA (640x480) @ 60 Hz
parameter VGA_HBLANKON = 10'd639;
parameter VGA_HSYNCON = 10'd655;
parameter VGA_HSYNCOFF = 10'd751;
parameter VGA_HRESET = 10'd799;
parameter VGA_VBLANKON = 10'd479;
parameter VGA_VSYNCON = 10'd490;
parameter VGA_VSYNCOFF = 10'd492;
parameter VGA_VRESET = 10'd523;
// horizontal: 800 pixels total
// display 640 pixels per line
reg hblank,vblank;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = (hcount == VGA_HBLANKON);
assign hsyncon = (hcount == VGA_HSYNCON);
assign hsyncoff = (hcount == VGA_HSYNCOFF);
assign hreset = (hcount == VGA_HRESET);
// vertical: 524 lines total
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == VGA_VBLANKON);
assign vsyncon = hreset & (vcount == VGA_VSYNCON);
assign vsyncoff = hreset & (vcount == VGA_VSYNCOFF);
assign vreset = hreset & (vcount == VGA_VRESET);
// sync and blanking
wire next_hblank,next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule
|
/*
* milkymist vj soc
* copyright (c) 2007, 2008, 2009 sebastien bourdeauducq
* adjusted to fml 8x16 by zeus gomez marmolejo <zeus@aluzina.org>
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, version 3 of the license.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
/* simple fml interface for hpdmc */
module hpdmc_busif #(
parameter sdram_depth = 23
) (
input sys_clk,
input sdram_rst,
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
output mgmt_stb,
output mgmt_we,
output [sdram_depth-1-1:0] mgmt_address, /* in 16-bit words */
input mgmt_ack,
input data_ack
);
reg mgmt_stb_en;
assign mgmt_stb = fml_stb & mgmt_stb_en;
assign mgmt_we = fml_we;
assign mgmt_address = fml_adr[sdram_depth-1:1];
assign fml_ack = data_ack;
always @(posedge sys_clk) begin
if(sdram_rst)
mgmt_stb_en = 1'b1;
else begin
if(mgmt_ack)
mgmt_stb_en = 1'b0;
if(data_ack)
mgmt_stb_en = 1'b1;
end
end
endmodule
|
// spdx-filecopyrighttext: 2020 efabless corporation
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_proj_example
*
* this is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
* analyzer, the wishbone bus, and the i/o pads.
*
* this project generates an integer count, which is output
* on the user area gpio pads (digital output only). the
* wishbone connection allows the project to be controlled
* (start and stop) from the management soc program.
*
* see the testbenches in directory "mprj_counter" for the
* example programs that drive this user project. the three
* testbenches are "io_ports", "la_test1", and "la_test2".
*
*-------------------------------------------------------------
*/
module user_proj_mac #(
parameter bits = 38
)(
`ifdef use_power_pins
inout vccd1, // user area 1 1.8v supply
inout vssd1, // user area 1 digital ground
`endif
// wishbone slave ports (wb mi a)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg [31:0] wbs_dat_o,
// logic analyzer signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// ios
input [bits-1:0] io_in,
output [bits-1:0] io_out,
output [bits-1:0] io_oeb,
// independent clock (on independent integer divider)
input user_clock2,
// irq
output [2:0] irq
);
wire clk,rst;
assign clk = wb_clk_i;
assign rst = wb_rst_i;
wire [255:0] data_in;
wire [27:0] data_out;
wire xor_output;
assign xor_output = io_in[0] ^ io_in[1] ^ io_in[2] ^ io_in[3] ^ io_in[4] ^ io_in[5] ^ io_in[6]
^ io_in[7] ^ io_in[8] ^ io_in[9] ^ io_in[10] ^ io_in[11] ^ io_in[12] ^ io_in[13]
^ io_in[14] ^ io_in[15] ^ io_in[16] ^ io_in[17] ^ io_in[18] ^ io_in[19] ^ io_in[20]
^ io_in[21] ^ io_in[22] ^ io_in[23] ^ io_in[24] ^ io_in[25] ^ io_in[26] ^ io_in[27]
^ io_in[28] ^ io_in[29] ^ io_in[30] ^ io_in[31] ^ io_in[32] ^ io_in[33] ^ io_in[34]
^ io_in[35] ^ io_in[36] ^ io_in[37];
assign io_out = {xor_output,5'b0,wbs_sel_i,data_out};
assign io_oeb = {38{1'b1}};
assign la_data_out =user_clock2? la_oenb:{wbs_adr, wbs_dat, wbs_dat, wbs_dat};
// register to store the wishbone slave address.
reg [31:0] wbs_adr;
// register to store the wishbone slave data.
reg [31:0] wbs_dat;
// register to store the wishbone slave write enable signal.
reg wbs_we;
// wire to connect the wishbone slave acknowledge signal.
// wire wbs_ack;
// assign wbs_ack_o=wbs_ack;
// wire to connect the wishbone slave data output signal.
// wire [31:0] wbs_dat_o;
// always block to write data to the wishbone slave.
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbs_adr <= 0;
wbs_dat <= 0;
wbs_we <= 0;
end else if (wbs_stb_i && wbs_cyc_i && !wbs_ack_o) begin
wbs_adr <= wbs_adr_i;
wbs_dat <= wbs_dat_i;
wbs_we <= wbs_we_i;
end
end
// always block to read data from the wishbone slave.
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbs_dat_o <= 0;
end else wbs_ack_o <= (wbs_stb_i && wbs_cyc_i && !wbs_we && !wbs_ack_o) ? 1'b1 : 1'b0;
if (wbs_stb_i && wbs_cyc_i && !wbs_we && !wbs_ack_o) begin
wbs_dat_o <= wbs_dat;
end
end
// assign the wishbone slave acknowledge signal.
// assign wbs_ack_o = (wbs_stb_i && wbs_cyc_i && !wbs_we && !wbs_ack_o) ? 1'b1 : 1'b0;
// irq
assign irq = 3'b000; // unused
assign data_in ={la_data_in,la_data_in};
// mac mac_unit( .data_in(data_in), .clk(clk),.reset(rst), .data_out(data_out));
endmodule
`default_nettype wire
|
/*
*
* Copyright (c) 2011-2012 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 50;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 100;
//// Clock Buffer
`ifndef SIM
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
`endif
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [30:0] nonce = 31'd254, nonce2 = 31'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Dual-Hasher
wire [255:0] hash0, hash1;
wire [31:0] hash2_w0, hash2_w1;
dual_sha256_transform first_hash_blk (
.clk (hash_clk),
.rx_state (midstate),
.rx_nonce (nonce),
.rx_input (data),
.tx_hash0 (hash0),
.tx_hash1 (hash1)
);
second_sha256_transform second_hash0_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash0}),
.tx_hash (hash2_w0)
);
second_sha256_transform second_hash1_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash1}),
.tx_hash (hash2_w1)
);
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~254 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 31'd127;
nonce2 <= 31'd0;
end
else
begin
nonce <= nonce + 31'd1;
nonce2 <= nonce2 + 31'd1;
end
`ifndef SIM
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
`endif
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 31'h7FFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
if (hash2_w0 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b0, nonce2};
end
else if (hash2_w1 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b1, nonce2};
end
else
is_golden_ticket <= 1'b0;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
/*
* ravenna - a full example soc using picorv32 in x-fab xh018
*
* copyright (c) 2017 clifford wolf <clifford@clifford.at>
* copyright (c) 2018 tim edwards <tim@efabless.com>
*
* permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* the software is provided "as is" and the author disclaims all warranties
* with regard to this software including all implied warranties of
* merchantability and fitness. in no event shall the author be liable for
* any special, direct, indirect, or consequential damages or any damages
* whatsoever resulting from loss of use, data or profits, whether in an
* action of contract, negligence or other tortious action, arising out of
* or in connection with the use or performance of this software.
*
*/
`timescale 1 ns / 1 ps
`include "../ravenna.v"
`include "../spiflash.v"
`include "../tbuart.v"
module ravenna_pass_thru_tb;
reg xclk;
reg real vdd3v3;
reg real xi;
wire real xo;
reg real adc_h, adc_l;
reg real adc_0, adc_1;
reg real comp_n, comp_p;
wire real ana_out;
integer i;
always #100 xclk <= (xclk === 1'b0);
always #50 xi = vdd3v3 - xo;
initial begin
xclk <= 1'b0;
xi = 0.0;
#150;
xi = vdd3v3 / 2 - 0.1;
end
initial begin
// ramp vdd3v3 from 0 to 3.3v
vdd3v3 = 0.0;
#50;
repeat (33) begin
#3;
vdd3v3 = vdd3v3 + 0.1;
end
end
initial begin
// analog input pin values (static)
adc_h = 0.0;
adc_l = 0.0;
adc_0 = 0.0;
adc_1 = 0.0;
comp_n = 0.0;
comp_p = 0.0;
end
wire [15:0] gpio;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire flash_io2;
wire flash_io3;
reg sdi, csb, sck;
wire sdo;
// the main testbench is here. put the housekeeping spi into
// pass-thru mode and read several bytes from the flash spi.
// first define tasks for spi functions
task start_csb;
begin
sck <= 1'b0;
sdi <= 1'b0;
csb <= 1'b0;
#50;
end
endtask
task end_csb;
begin
sck <= 1'b0;
sdi <= 1'b0;
csb <= 1'b1;
#50;
end
endtask
task write_byte;
input [7:0] odata;
begin
sck <= 1'b0;
for (i=7; i >= 0; i--) begin
#50;
sdi <= odata[i];
#50;
sck <= 1'b1;
#100;
sck <= 1'b0;
end
end
endtask
task read_byte;
output [7:0] idata;
begin
sck <= 1'b0;
sdi <= 1'b0;
for (i=7; i >= 0; i--) begin
#50;
idata[i] = sdo;
#50;
sck <= 1'b1;
#100;
sck <= 1'b0;
end
end
endtask
task read_write_byte
(input [7:0] odata,
output [7:0] idata);
begin
sck <= 1'b0;
for (i=7; i >= 0; i--) begin
#50;
sdi <= odata[i];
idata[i] = sdo;
#50;
sck <= 1'b1;
#100;
sck <= 1'b0;
end
end
endtask
// now drive the digital signals on the housekeeping spi
reg [7:0] tbdata;
initial begin
$dumpfile("ravenna_pass_thru.vcd");
$dumpvars(0, ravenna_pass_thru_tb);
csb <= 1'b1;
sck <= 1'b0;
sdi <= 1'b0;
// chip does not come out of reset until 20us.
#21000;
// first do a normal read from the housekeeping spi to
// make sure the housekeeping spi works.
start_csb();
write_byte(8'h40); // read stream command
write_byte(8'h03); // address (register 3 = product id)
read_byte(tbdata);
end_csb();
#10;
$display("read data = 0x%02x (should be 0x03)", tbdata);
start_csb();
write_byte(8'hc4); // pass-thru mode
write_byte(8'h03); // command 03 (read values w/3-byte address)
write_byte(8'h10); // address is next 3 bytes (0x100000)
write_byte(8'h00);
write_byte(8'h00);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
read_byte(tbdata);
$display("read flash data = 0x%02x", tbdata);
end_csb();
// run longer to check processor restart.
#10000;
$finish;
end
wire real vdd1v8;
wire real vss;
assign vss = 0.0;
ravenna uut (
.vdd3v3 (vdd3v3 ),
.vdd1v8 (vdd1v8),
.vss (vss),
.xi (xi),
.xo (xo),
.xclk (xclk),
.sdi (sdi),
.sdo (sdo),
.csb (csb),
.sck (sck),
.ser_rx (1'b0 ),
.ser_tx (tbuart_rx),
.i2c_sda ( ),
.i2c_scl ( ),
.spi_sdi (1'b0 ),
.spi_csb ( ),
.spi_sck ( ),
.spi_sdo ( ),
.irq (1'b0 ),
.gpio (gpio ),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.flash_io2(flash_io2),
.flash_io3(flash_io3),
.adc_high (adc_h),
.adc_low (adc_l),
.adc0_in (adc_0),
.adc1_in (adc_1),
.analog_out(ana_out),
.comp_inp (comp_p),
.comp_inn (comp_n)
);
spiflash #(
.filename("ravenna_pass_thru.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(flash_io2),
.io3(flash_io3)
);
// testbench uart
tbuart tbuart (
.ser_rx(tbuart_rx)
);
endmodule
|
// spdx-filecopyrighttext: 2020 efabless corporation
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* this wrapper enumerates all of the pins available to the
* user for the user project.
*
* an example user project is provided in this wrapper. the
* example should be removed and replaced with the actual
* user project.
*
*-------------------------------------------------------------
*/
module user_project_wrapper #(
parameter bits = 32
) (
`ifdef use_power_pins
inout vdda1, // user area 1 3.3v supply
inout vdda2, // user area 2 3.3v supply
inout vssa1, // user area 1 analog ground
inout vssa2, // user area 2 analog ground
inout vccd1, // user area 1 1.8v supply
inout vccd2, // user area 2 1.8v supply
inout vssd1, // user area 1 digital ground
inout vssd2, // user area 2 digital ground
`endif
// wishbone slave ports (wb mi a)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// logic analyzer signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// ios
input [`mprj_io_pads-1:0] io_in,
output [`mprj_io_pads-1:0] io_out,
output [`mprj_io_pads-1:0] io_oeb,
// analog (direct connection to gpio pad---use with caution)
// note that analog i/o is not available on the 7 lowest-numbered
// gpio pads, and so the analog_io indexing is offset from the
// gpio indexing by 7 (also upper 2 gpios do not have analog_io).
inout [`mprj_io_pads-10:0] analog_io,
// independent clock (on independent integer divider)
input user_clock2,
// user maskable interrupt signals
output [2:0] user_irq
);
/*--------------------------------------*/
/* user project is instantiated here */
/*--------------------------------------*/
user_proj_example mprj (
`ifdef use_power_pins
.vccd1(vccd1), // user area 1 1.8v power
.vssd1(vssd1), // user area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// mgmt soc wishbone slave
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
// logic analyzer
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb (la_oenb),
// io pads
.io_in ({io_in[37:30],io_in[7:0]}),
.io_out({io_out[37:30],io_out[7:0]}),
.io_oeb({io_oeb[37:30],io_oeb[7:0]}),
// irq
.irq(user_irq)
);
endmodule // user_project_wrapper
`default_nettype wire
|
/*
* picorv32 -- a small risc-v (rv32i) processor core
*
* copyright (c) 2015 clifford wolf <clifford@clifford.at>
*
* permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* the software is provided "as is" and the author disclaims all warranties
* with regard to this software including all implied warranties of
* merchantability and fitness. in no event shall the author be liable for
* any special, direct, indirect, or consequential damages or any damages
* whatsoever resulting from loss of use, data or profits, whether in an
* action of contract, negligence or other tortious action, arising out of
* or in connection with the use or performance of this software.
*
*/
// `timescale 1 ns / 1 ps
// `default_nettype none
// `define debugnets
// `define debugregs
// `define debugasm
// `define debug
`include "l15.h"
`ifdef debug
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef formal
`define formal_keep (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef debugnets
`define formal_keep (* keep *)
`else
`define formal_keep
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define picorv32_regs picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define picorv32_v
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] enable_counters = 1,
parameter [ 0:0] enable_counters64 = 1,
parameter [ 0:0] enable_regs_16_31 = 1,
parameter [ 0:0] enable_regs_dualport = 1,
parameter [ 0:0] latched_mem_rdata = 0,
parameter [ 0:0] two_stage_shift = 1,
parameter [ 0:0] barrel_shifter = 0,
parameter [ 0:0] two_cycle_compare = 0,
parameter [ 0:0] two_cycle_alu = 0,
parameter [ 0:0] compressed_isa = 0,
parameter [ 0:0] catch_misalign = 1,
parameter [ 0:0] catch_illinsn = 1,
parameter [ 0:0] enable_pcpi = 0,
`ifdef piton_fpga_synth
parameter [ 0:0] enable_mul = 0,
`else
parameter [ 0:0] enable_mul = 1,
`endif
parameter [ 0:0] enable_fast_mul = 0,
`ifdef piton_fpga_synth
parameter [ 0:0] enable_div = 0,
`else
parameter [ 0:0] enable_div = 1,
`endif
parameter [ 0:0] enable_irq = 0,
parameter [ 0:0] enable_irq_qregs = 1,
parameter [ 0:0] enable_irq_timer = 1,
parameter [ 0:0] enable_trace = 0,
parameter [ 0:0] regs_init_zero = 0,
parameter [31:0] masked_irq = 32'h 0000_0000,
parameter [31:0] latched_irq = 32'h ffff_ffff,
`ifdef piton_fpga_synth
parameter [31:0] progaddr_reset = 32'h f020_0000,
`else
parameter [31:0] progaddr_reset = 32'h 4000_0000,
`endif
parameter [31:0] progaddr_irq = 32'h 0000_0010,
parameter [31:0] stackaddr = 32'h ffff_ffff
) (
input clk, reset_l,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
output reg [`l15_amo_op_width-1:0] mem_amo_op,
input [31:0] mem_rdata,
input wire pico_int,
// look-ahead interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
output reg [`l15_amo_op_width-1:0] mem_la_amo_op,
// pico co-processor interface (pcpi)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// irq interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef riscv_formal
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// trace interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = enable_regs_16_31 ? 32 : 16;
localparam integer regfile_size = (enable_regs_16_31 ? 32 : 16) + 4*enable_irq*enable_irq_qregs;
localparam integer regindex_bits = (enable_regs_16_31 ? 5 : 4) + enable_irq*enable_irq_qregs;
localparam with_pcpi = enable_pcpi || enable_mul || enable_fast_mul || enable_div;
localparam [35:0] trace_branch = {4'b 0001, 32'b 0};
localparam [35:0] trace_addr = {4'b 0010, 32'b 0};
localparam [35:0] trace_irq = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc;
reg [31:0] reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg resetn;
always @ (posedge clk) begin
if(!reset_l) begin
resetn <= 1'b0;
end
else if (mem_la_write & (mem_la_addr == 32'hffffffff)) begin
resetn <= 1'b0;
end
else if (pico_int) begin
resetn <= 1'b1;
end
end
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef picorv32_regs
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (regs_init_zero) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// this task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain verilog syntax).
begin end
endtask
`ifdef debugregs
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// internal pcpi cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
generate if (enable_fast_mul) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (enable_mul) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (enable_div) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{enable_pcpi && pcpi_wait, (enable_mul || enable_fast_mul) && pcpi_mul_wait, enable_div && pcpi_div_wait};
pcpi_int_ready = |{enable_pcpi && pcpi_ready, (enable_mul || enable_fast_mul) && pcpi_mul_ready, enable_div && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
enable_pcpi && pcpi_ready: begin
pcpi_int_wr = enable_pcpi ? pcpi_wr : 0;
pcpi_int_rd = enable_pcpi ? pcpi_rd : 0;
end
(enable_mul || enable_fast_mul) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
enable_div && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// memory interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
reg [`l15_amo_op_width-1:0] instr_amo_op;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = compressed_isa && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = compressed_isa && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = compressed_isa && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(compressed_isa && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : reg_op1[31:0];
assign mem_rdata_latched_noshuffle = (mem_xfer || latched_mem_rdata) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = compressed_isa && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
compressed_isa && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
compressed_isa && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
mem_la_amo_op = instr_amo_op;
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= compressed_isa ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= compressed_isa ? mem_rdata_latched : mem_rdata;
end
if (compressed_isa && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // c.addi4spn
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // c.lw
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // c.sw
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // c.addi
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // c.li
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // c.addi16sp
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // c.lui
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // c.srli
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // c.srai
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // c.andi
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // c.sub, c.xor, c.or, c.and
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // c.beqz
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // c.bnez
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // c.slli
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // c.lwsp
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // c.jr
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // c.mv
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // c.jalr
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // c.add
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // c.swsp
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
mem_amo_op <= mem_la_amo_op;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
if (mem_la_addr == 32'hffffffff) begin
mem_valid <= 0;
mem_instr <= 0;
mem_state <= 0;
end
else begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (compressed_isa && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (compressed_isa && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// instruction decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_uj;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
reg is_amo;
assign instr_trap = (catch_illinsn || with_pcpi) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer, |instr_amo_op};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`formal_keep reg [63:0] dbg_ascii_instr;
`formal_keep reg [31:0] dbg_insn_imm;
`formal_keep reg [4:0] dbg_insn_rs1;
`formal_keep reg [4:0] dbg_insn_rs2;
`formal_keep reg [4:0] dbg_insn_rd;
`formal_keep reg [31:0] dbg_rs1val;
`formal_keep reg [31:0] dbg_rs2val;
`formal_keep reg dbg_rs1val_valid;
`formal_keep reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
if (instr_amo_op) new_ascii_instr = "amo_op";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef debugasm
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef debug
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("decode: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "unknown");
else
$display("decode: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "unknown");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && enable_irq;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && enable_irq;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
is_amo <= mem_rdata_latched[6:0] == 7'b0101111;
{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= {{12{mem_rdata_latched[31]}}, mem_rdata_latched[31:12], 1'b0};
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && enable_irq && enable_irq_qregs)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && enable_irq)
decoded_rs1 <= enable_irq_qregs ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (compressed_isa && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // c.addi4spn
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // c.lw
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // c.sw
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // c.nop / c.addi
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // c.jal
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // c.li
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // c.addi16sp
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // c.lui
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // c.srli, c.srai
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // c.andi
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // c.sub, c.xor, c.or, c.and
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // c.j
instr_jal <= 1;
end
3'b110: begin // c.beqz
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // c.bnez
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // c.slli
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // c.lwsp
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // c.jr
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // c.mv
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // c.jalr
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // c.add
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // c.swsp
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= with_pcpi ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
if (is_amo) begin
case (mem_rdata_q[31:27])
5'b00001: begin
instr_amo_op <= `l15_amo_op_swap;
end
5'b00000: begin
instr_amo_op <= `l15_amo_op_add;
end
5'b00100: begin
instr_amo_op <= `l15_amo_op_xor;
end
5'b01100: begin
instr_amo_op <= `l15_amo_op_and;
end
5'b01000: begin
instr_amo_op <= `l15_amo_op_or;
end
5'b10000: begin
instr_amo_op <= `l15_amo_op_min;
end
5'b10100: begin
instr_amo_op <= `l15_amo_op_max;
end
5'b11000: begin
instr_amo_op <= `l15_amo_op_minu;
end
5'b11100: begin
instr_amo_op <= `l15_amo_op_maxu;
end
default: begin
instr_amo_op <= {`l15_amo_op_width{1'bx}};
end
endcase
end
else begin
instr_amo_op <= `l15_amo_op_none;
end
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && enable_counters;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && enable_counters && enable_counters64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && enable_counters;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && enable_counters && enable_counters64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(compressed_isa && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && enable_irq && enable_irq_qregs;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && enable_irq && enable_irq_qregs;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && enable_irq;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && enable_irq && enable_irq_timer;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_uj;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
instr_amo_op <= `l15_amo_op_none;
end
end
// main state machine
localparam cpu_state_trap = 9'b100000000;
localparam cpu_state_fetch = 9'b010000000;
localparam cpu_state_ld_rs1 = 9'b001000000;
localparam cpu_state_ld_rs2 = 9'b000100000;
localparam cpu_state_exec = 9'b000010000;
localparam cpu_state_shift = 9'b000001000;
localparam cpu_state_stmem = 9'b000000100;
localparam cpu_state_ldmem = 9'b000000010;
localparam cpu_state_amo = 9'b000000001;
reg [9:0] cpu_state;
reg [1:0] irq_state;
`formal_keep reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
if (cpu_state == cpu_state_amo) dbg_ascii_state = "amo";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (two_cycle_alu) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!two_cycle_compare || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!two_cycle_compare || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
barrel_shifter && (instr_sll || instr_slli):
alu_out = alu_shl;
barrel_shifter && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef riscv_formal_blackbox_alu
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = compressed_isa;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
enable_irq && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
enable_irq && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef picorv32_regs
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (enable_regs_dualport) begin
`ifndef riscv_formal_blackbox_regs
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef riscv_formal_blackbox_regs
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire[31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = enable_regs_dualport ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = enable_regs_dualport ? decoded_rs2 : 0;
`picorv32_regs cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (enable_regs_dualport) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!enable_irq || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
$display("current pc: 0x%08x, next pc: 0x%08x", reg_pc, reg_next_pc);
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (with_pcpi && catch_illinsn) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (enable_counters) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!enable_counters64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = enable_irq ? irq_pending & latched_irq : 'bx;
if (enable_irq && enable_irq_timer && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (enable_irq) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!enable_trace)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= progaddr_reset;
reg_next_pc <= progaddr_reset;
if (enable_counters)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~stackaddr) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= stackaddr;
end
cpu_state <= cpu_state_fetch;
end else
`ifndef _vcp //mps2538
(* parallel_case, full_case *)
`endif
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("st_rd: %2d 0x%08x, branch 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("st_rd: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
enable_irq && irq_state[0]: begin
current_pc = progaddr_irq;
irq_active <= 1;
mem_do_rinst <= 1;
end
enable_irq && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (enable_trace && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? trace_irq : 0) | trace_branch | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? trace_irq : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (enable_irq && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (enable_irq_qregs)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (enable_irq && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (enable_trace)
latched_trace <= 1;
if (enable_counters) begin
count_instr <= count_instr + 1;
if (!enable_counters64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_uj;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(catch_illinsn || with_pcpi) && instr_trap: begin
if (with_pcpi) begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (enable_regs_dualport) begin
pcpi_valid <= 1;
`debug($display("ld_rs2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (catch_illinsn && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("ebreak or unsupported insn at 0x%08x", reg_pc);)
if (enable_irq && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("ebreak or unsupported insn at 0x%08x", reg_pc);)
if (enable_irq && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
enable_counters && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && enable_counters64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && enable_counters64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (two_cycle_alu)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
enable_irq && enable_irq_qregs && instr_getq: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
enable_irq && enable_irq_qregs && instr_setq: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
enable_irq && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= catch_misalign ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
enable_irq && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | masked_irq;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
enable_irq && enable_irq_timer && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !barrel_shifter: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && barrel_shifter: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && barrel_shifter ? decoded_rs2 : decoded_imm;
if (two_cycle_alu)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("ld_rs1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (enable_regs_dualport) begin
`debug($display("ld_rs2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_amo: begin
cpu_state <= cpu_state_amo;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !barrel_shifter: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (two_cycle_alu || (two_cycle_compare && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= two_cycle_alu && (two_cycle_compare && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("ld_rs2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
with_pcpi && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (catch_illinsn && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("ebreak or unsupported insn at 0x%08x", reg_pc);)
if (enable_irq && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !barrel_shifter: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (two_cycle_alu || (two_cycle_compare && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= two_cycle_alu && (two_cycle_compare && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((two_cycle_alu || two_cycle_compare) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= two_cycle_compare ? alu_out_0_q : alu_out_0;
latched_branch <= two_cycle_compare ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (two_cycle_compare ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (two_stage_shift && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (enable_trace)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (enable_trace) begin
trace_valid <= 1;
trace_data <= (irq_active ? trace_irq : 0) | trace_addr | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_amo: begin
latched_store <= 1;
if (enable_trace) begin
reg_out <= reg_op2;
end
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
mem_wordsize <= 0;
if (enable_trace) begin
trace_valid <= 1;
trace_data <= (irq_active ? trace_irq : 0) | trace_addr | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
reg_out <= mem_rdata_word;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (enable_trace) begin
trace_valid <= 1;
trace_data <= (irq_active ? trace_irq : 0) | trace_addr | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (catch_misalign && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("misaligned word: 0x%08x", reg_op1);)
if (enable_irq && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("misaligned halfword: 0x%08x", reg_op1);)
if (enable_irq && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (catch_misalign && resetn && mem_do_rinst && (compressed_isa ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("misaligned instruction: 0x%08x", reg_pc);)
if (enable_irq && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!catch_illinsn && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~masked_irq;
if (!catch_misalign) begin
if (compressed_isa) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef riscv_formal
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// formal verification
`ifdef formal
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !enable_regs_dualport;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
// this is a simple example implementation of picorv32_regs.
// use the picorv32_regs mechanism if you want to use custom
// memory resources to implement the processor register file.
// note that your implementation must match the requirements of
// the picorv32 configuration. (e.g. qregs, etc)
module picorv32_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:30];
always @(posedge clk)
if (wen) regs[~waddr[4:0]] <= wdata;
assign rdata1 = regs[~raddr1[4:0]];
assign rdata2 = regs[~raddr2[4:0]];
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
parameter steps_at_once = 1,
parameter carry_chain = 4
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg pcpi_wait_q;
wire mul_start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_mul <= 0;
instr_mulh <= 0;
instr_mulhsu <= 0;
instr_mulhu <= 0;
if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b000: instr_mul <= 1;
3'b001: instr_mulh <= 1;
3'b010: instr_mulhsu <= 1;
3'b011: instr_mulhu <= 1;
endcase
end
pcpi_wait <= instr_any_mul;
pcpi_wait_q <= pcpi_wait;
end
reg [63:0] rs1, rs2, rd, rdx;
reg [63:0] next_rs1, next_rs2, this_rs2;
reg [63:0] next_rd, next_rdx, next_rdt;
reg [6:0] mul_counter;
reg mul_waiting;
reg mul_finish;
integer i, j;
// carry save accumulator
always @* begin
next_rd = rd;
next_rdx = rdx;
next_rs1 = rs1;
next_rs2 = rs2;
for (i = 0; i < steps_at_once; i=i+1) begin
this_rs2 = next_rs1[0] ? next_rs2 : 0;
if (carry_chain == 0) begin
next_rdt = next_rd ^ next_rdx ^ this_rs2;
next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
next_rd = next_rdt;
end else begin
next_rdt = 0;
for (j = 0; j < 64; j = j + carry_chain)
{next_rdt[j+carry_chain-1], next_rd[j +: carry_chain]} =
next_rd[j +: carry_chain] + next_rdx[j +: carry_chain] + this_rs2[j +: carry_chain];
next_rdx = next_rdt << 1;
end
next_rs1 = next_rs1 >> 1;
next_rs2 = next_rs2 << 1;
end
end
always @(posedge clk) begin
mul_finish <= 0;
if (!resetn) begin
mul_waiting <= 1;
end else
if (mul_waiting) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
rd <= 0;
rdx <= 0;
mul_counter <= (instr_any_mulh ? 63 - steps_at_once : 31 - steps_at_once);
mul_waiting <= !mul_start;
end else begin
rd <= next_rd;
rdx <= next_rdx;
rs1 <= next_rs1;
rs2 <= next_rs2;
mul_counter <= mul_counter - steps_at_once;
if (mul_counter[6]) begin
mul_finish <= 1;
mul_waiting <= 1;
end
end
end
always @(posedge clk) begin
pcpi_wr <= 0;
pcpi_ready <= 0;
if (mul_finish && resetn) begin
pcpi_wr <= 1;
pcpi_ready <= 1;
pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
end
end
endmodule
module picorv32_pcpi_fast_mul #(
parameter extra_mul_ffs = 0,
parameter extra_insn_ffs = 0,
parameter mul_clkgate = 0
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output pcpi_wr,
output [31:0] pcpi_rd,
output pcpi_wait,
output pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg shift_out;
reg [3:0] active;
reg [32:0] rs1, rs2, rs1_q, rs2_q;
reg [63:0] rd, rd_q;
wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
reg pcpi_insn_valid_q;
always @* begin
instr_mul = 0;
instr_mulh = 0;
instr_mulhsu = 0;
instr_mulhu = 0;
if (resetn && (extra_insn_ffs ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
case (pcpi_insn[14:12])
3'b000: instr_mul = 1;
3'b001: instr_mulh = 1;
3'b010: instr_mulhsu = 1;
3'b011: instr_mulhu = 1;
endcase
end
end
always @(posedge clk) begin
pcpi_insn_valid_q <= pcpi_insn_valid;
if (!mul_clkgate || active[0]) begin
rs1_q <= rs1;
rs2_q <= rs2;
end
if (!mul_clkgate || active[1]) begin
rd <= $signed(extra_mul_ffs ? rs1_q : rs1) * $signed(extra_mul_ffs ? rs2_q : rs2);
end
if (!mul_clkgate || active[2]) begin
rd_q <= rd;
end
end
always @(posedge clk) begin
if (instr_any_mul && !(extra_mul_ffs ? active[3:0] : active[1:0])) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
active[0] <= 1;
end else begin
active[0] <= 0;
end
active[3:1] <= active;
shift_out <= instr_any_mulh;
if (!resetn)
active <= 0;
end
assign pcpi_wr = active[extra_mul_ffs ? 3 : 1];
assign pcpi_wait = 0;
assign pcpi_ready = active[extra_mul_ffs ? 3 : 1];
`ifdef riscv_formal_altops
assign pcpi_rd =
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
`else
assign pcpi_rd = shift_out ? (extra_mul_ffs ? rd_q : rd) >> 32 : (extra_mul_ffs ? rd_q : rd);
`endif
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_div, instr_divu, instr_rem, instr_remu;
wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
reg pcpi_wait_q;
wire start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_div <= 0;
instr_divu <= 0;
instr_rem <= 0;
instr_remu <= 0;
if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b100: instr_div <= 1;
3'b101: instr_divu <= 1;
3'b110: instr_rem <= 1;
3'b111: instr_remu <= 1;
endcase
end
pcpi_wait <= instr_any_div_rem && resetn;
pcpi_wait_q <= pcpi_wait && resetn;
end
reg [31:0] dividend;
reg [62:0] divisor;
reg [31:0] quotient;
reg [31:0] quotient_msk;
reg running;
reg outsign;
always @(posedge clk) begin
pcpi_ready <= 0;
pcpi_wr <= 0;
pcpi_rd <= 'bx;
if (!resetn) begin
running <= 0;
end else
if (start) begin
running <= 1;
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
quotient <= 0;
quotient_msk <= 1 << 31;
end else
if (!quotient_msk && running) begin
running <= 0;
pcpi_ready <= 1;
pcpi_wr <= 1;
`ifdef riscv_formal_altops
case (1)
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
endcase
`else
if (instr_div || instr_divu)
pcpi_rd <= outsign ? -quotient : quotient;
else
pcpi_rd <= outsign ? -dividend : dividend;
`endif
end else begin
if (divisor <= dividend) begin
dividend <= dividend - divisor;
quotient <= quotient | quotient_msk;
end
divisor <= divisor >> 1;
`ifdef riscv_formal_altops
quotient_msk <= quotient_msk >> 5;
`else
quotient_msk <= quotient_msk >> 1;
`endif
end
end
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
parameter [ 0:0] enable_counters = 1,
parameter [ 0:0] enable_counters64 = 1,
parameter [ 0:0] enable_regs_16_31 = 1,
parameter [ 0:0] enable_regs_dualport = 1,
parameter [ 0:0] two_stage_shift = 1,
parameter [ 0:0] barrel_shifter = 0,
parameter [ 0:0] two_cycle_compare = 0,
parameter [ 0:0] two_cycle_alu = 0,
parameter [ 0:0] compressed_isa = 0,
parameter [ 0:0] catch_misalign = 1,
parameter [ 0:0] catch_illinsn = 1,
parameter [ 0:0] enable_pcpi = 0,
parameter [ 0:0] enable_mul = 0,
parameter [ 0:0] enable_fast_mul = 0,
parameter [ 0:0] enable_div = 0,
parameter [ 0:0] enable_irq = 0,
parameter [ 0:0] enable_irq_qregs = 1,
parameter [ 0:0] enable_irq_timer = 1,
parameter [ 0:0] enable_trace = 0,
parameter [ 0:0] regs_init_zero = 0,
parameter [31:0] masked_irq = 32'h 0000_0000,
parameter [31:0] latched_irq = 32'h ffff_ffff,
parameter [31:0] progaddr_reset = 32'h 0000_0000,
parameter [31:0] progaddr_irq = 32'h 0000_0010,
parameter [31:0] stackaddr = 32'h ffff_ffff
) (
input clk, resetn,
output trap,
// axi4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// pico co-processor interface (pcpi)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// irq interface
input [31:0] irq,
output [31:0] eoi,
`ifdef riscv_formal
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// trace interface
output trace_valid,
output [35:0] trace_data
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_rdata;
picorv32_axi_adapter axi_adapter (
.clk (clk ),
.resetn (resetn ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
picorv32 #(
.enable_counters (enable_counters ),
.enable_counters64 (enable_counters64 ),
.enable_regs_16_31 (enable_regs_16_31 ),
.enable_regs_dualport(enable_regs_dualport),
.two_stage_shift (two_stage_shift ),
.barrel_shifter (barrel_shifter ),
.two_cycle_compare (two_cycle_compare ),
.two_cycle_alu (two_cycle_alu ),
.compressed_isa (compressed_isa ),
.catch_misalign (catch_misalign ),
.catch_illinsn (catch_illinsn ),
.enable_pcpi (enable_pcpi ),
.enable_mul (enable_mul ),
.enable_fast_mul (enable_fast_mul ),
.enable_div (enable_div ),
.enable_irq (enable_irq ),
.enable_irq_qregs (enable_irq_qregs ),
.enable_irq_timer (enable_irq_timer ),
.enable_trace (enable_trace ),
.regs_init_zero (regs_init_zero ),
.masked_irq (masked_irq ),
.latched_irq (latched_irq ),
.progaddr_reset (progaddr_reset ),
.progaddr_irq (progaddr_irq ),
.stackaddr (stackaddr )
) picorv32_core (
.clk (clk ),
.reset_l (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef riscv_formal
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
input clk, resetn,
// axi4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// native picorv32 memory interface
input mem_valid,
input mem_instr,
output mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
always @(posedge clk) begin
if (!resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_valid && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_valid) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
parameter [ 0:0] enable_counters = 1,
parameter [ 0:0] enable_counters64 = 1,
parameter [ 0:0] enable_regs_16_31 = 1,
parameter [ 0:0] enable_regs_dualport = 1,
parameter [ 0:0] two_stage_shift = 1,
parameter [ 0:0] barrel_shifter = 0,
parameter [ 0:0] two_cycle_compare = 0,
parameter [ 0:0] two_cycle_alu = 0,
parameter [ 0:0] compressed_isa = 0,
parameter [ 0:0] catch_misalign = 1,
parameter [ 0:0] catch_illinsn = 1,
parameter [ 0:0] enable_pcpi = 0,
parameter [ 0:0] enable_mul = 0,
parameter [ 0:0] enable_fast_mul = 0,
parameter [ 0:0] enable_div = 0,
parameter [ 0:0] enable_irq = 0,
parameter [ 0:0] enable_irq_qregs = 1,
parameter [ 0:0] enable_irq_timer = 1,
parameter [ 0:0] enable_trace = 0,
parameter [ 0:0] regs_init_zero = 0,
parameter [31:0] masked_irq = 32'h 0000_0000,
parameter [31:0] latched_irq = 32'h ffff_ffff,
parameter [31:0] progaddr_reset = 32'h 0000_0000,
parameter [31:0] progaddr_irq = 32'h 0000_0010,
parameter [31:0] stackaddr = 32'h ffff_ffff
) (
output trap,
// wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// pico co-processor interface (pcpi)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// irq interface
input [31:0] irq,
output [31:0] eoi,
`ifdef riscv_formal
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// trace interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.enable_counters (enable_counters ),
.enable_counters64 (enable_counters64 ),
.enable_regs_16_31 (enable_regs_16_31 ),
.enable_regs_dualport(enable_regs_dualport),
.two_stage_shift (two_stage_shift ),
.barrel_shifter (barrel_shifter ),
.two_cycle_compare (two_cycle_compare ),
.two_cycle_alu (two_cycle_alu ),
.compressed_isa (compressed_isa ),
.catch_misalign (catch_misalign ),
.catch_illinsn (catch_illinsn ),
.enable_pcpi (enable_pcpi ),
.enable_mul (enable_mul ),
.enable_fast_mul (enable_fast_mul ),
.enable_div (enable_div ),
.enable_irq (enable_irq ),
.enable_irq_qregs (enable_irq_qregs ),
.enable_irq_timer (enable_irq_timer ),
.enable_trace (enable_trace ),
.regs_init_zero (regs_init_zero ),
.masked_irq (masked_irq ),
.latched_irq (latched_irq ),
.progaddr_reset (progaddr_reset ),
.progaddr_irq (progaddr_irq ),
.stackaddr (stackaddr )
) picorv32_core (
.clk (clk ),
.reset_l (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef riscv_formal
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam idle = 2'b00;
localparam wbstart = 2'b01;
localparam wbend = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= idle;
end else begin
case (state)
idle: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= wbstart;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
wbstart:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= wbend;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
wbend: begin
mem_ready <= 1'b0;
state <= idle;
end
default:
state <= idle;
endcase
end
end
endmodule
|
// spdx-filecopyrighttext: 2022 piotr wegrzyn
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
`include "config.v"
module wb_cross_clk (
`ifdef use_power_pins
inout vccd1,
inout vssd1,
`endif
input clk_m,
input clk_s,
input m_rst,
input s_rst,
input m_wb_cyc,
input m_wb_stb,
input [`wb_addr_w-1:0] m_wb_adr,
input [`rw-1:0] m_wb_o_dat,
output [`rw-1:0] m_wb_i_dat,
input m_wb_we,
input [1:0] m_wb_sel,
input m_wb_8_burst, m_wb_4_burst,
output m_wb_ack,
output m_wb_err,
output s_wb_cyc,
output s_wb_stb,
output [`wb_addr_w-1:0] s_wb_adr,
output [`rw-1:0] s_wb_o_dat,
input [`rw-1:0] s_wb_i_dat,
output s_wb_we,
output [1:0] s_wb_sel,
output s_wb_8_burst, s_wb_4_burst,
input s_wb_ack,
input s_wb_err
);
reg prev_stb, prev_ack;
always @(posedge clk_m) begin
if (m_rst) begin
prev_stb <= 1'b0;
prev_ack <= 1'b0;
end else begin
prev_stb <= m_wb_stb;
prev_ack <= (msy_flag_ack | msy_flag_err);
end
end
wire m_new_req = m_wb_stb & (~prev_stb | prev_ack) & ~ignored_addr;
wire ignored_addr = m_wb_adr < `wb_addr_w'h002000;
`define max_burst_log 4
reg [`max_burst_log-1:0] m_burst_cnt;
reg m_new_req_flag;
always @(posedge clk_m) begin
if (m_rst) begin
m_new_req_flag <= 1'b0;
m_burst_cnt <= `max_burst_log'b0;
end else if (m_new_req & ~(|m_burst_cnt)) begin
m_new_req_flag <= ~m_new_req_flag;
if (m_wb_we)
m_burst_cnt <= `max_burst_log'd1; // burst write is not possible, as new data must be transmitted after each ack, which causes delay
// although burst signal is passed for later optimization of compressed bus write
else
m_burst_cnt <= (m_wb_8_burst ? `max_burst_log'd8 : (m_wb_4_burst ? `max_burst_log'd4 : `max_burst_log'd1));
end else if (msy_flag_ack | msy_flag_err) begin
m_burst_cnt <= m_burst_cnt - `max_burst_log'b1;
end
end
reg ack_next_hold;
reg [`max_burst_log-1:0] s_burst_cnt;
wire burst_in_progress = (|s_burst_cnt);
always @(posedge clk_s) begin
if (s_rst) begin
ack_next_hold <= 1'b0;
s_burst_cnt <= `max_burst_log'b0;
end else if ((s_wb_ack | s_wb_err) & burst_in_progress) begin
s_burst_cnt <= s_burst_cnt - `max_burst_log'b1;
ack_next_hold <= 1'b0;
end else if ((s_wb_ack | s_wb_err) & ~burst_in_progress) begin
ack_next_hold <= 1'b1;
end else if (ssy_newreq) begin
ack_next_hold <= 1'b0;
if (m_wb_we)
s_burst_cnt <= 'b0;
else
s_burst_cnt <= (s_wb_8_burst ? `max_burst_log'd7 : (s_wb_4_burst ? `max_burst_log'd3 : `max_burst_log'd0));
end
end
assign s_wb_stb = s_wb_cyc & ~ack_next_hold;
// xor strobe setup
reg ack_xor_flag;
reg err_xor_flag;
always @(posedge clk_s) begin
if(s_rst) begin
ack_xor_flag <= 1'b0;
err_xor_flag <= 1'b0;
end else begin
if(s_wb_ack)
ack_xor_flag <= ~ack_xor_flag;
if(s_wb_err)
err_xor_flag <= ~err_xor_flag;
end
end
reg prev_xor_ack, prev_xor_err;
always @(posedge clk_m) begin
if(m_rst) begin
prev_xor_ack <= 1'b0;
prev_xor_err <= 1'b0;
end else begin
prev_xor_ack <= msy_xor_ack;
prev_xor_err <= msy_xor_err;
end
end
wire msy_flag_ack = prev_xor_ack ^ msy_xor_ack;
wire msy_flag_err = prev_xor_err ^ msy_xor_err;
reg prev_xor_newreq;
always @(posedge clk_s) begin
if(s_rst)
prev_xor_newreq <= 1'b0;
else
prev_xor_newreq <= ssy_flag_newreq;
end
wire ssy_newreq = prev_xor_newreq ^ ssy_flag_newreq;
// s->m ff sync
`define sm_sync_w 2+16
wire [`sm_sync_w-1:0] smsync1;
ff_mb_sync #(.data_w(`sm_sync_w)) s_m_sync (
`ifdef use_power_pins
.vccd1(vccd1), .vssd1(vssd1),
`endif
.src_clk(clk_s),
.dst_clk(clk_m),
.src_rst(s_rst),
.dst_rst(m_rst),
.i_data({s_wb_i_dat, err_xor_flag^s_wb_err, ack_xor_flag^s_wb_ack}),
.o_data(smsync1),
.i_xfer_req(s_wb_ack | s_wb_err) // note: clock must be divided by >4 to not violate 3 cycle delay (to dst clock)
);
assign m_wb_i_dat = smsync1[17:2];
assign m_wb_ack = msy_flag_ack;
assign m_wb_err = msy_flag_err;
wire msy_xor_ack = smsync1[0];
wire msy_xor_err = smsync1[1];
// m->s ff sync
`define ms_sync_w 1+24+16+1+2+2+1
wire [`ms_sync_w-1:0] mssync1;
ff_mb_sync #(.data_w(`ms_sync_w)) m_s_sync (
`ifdef use_power_pins
.vccd1(vccd1), .vssd1(vssd1),
`endif
.src_clk(clk_m),
.dst_clk(clk_s),
.src_rst(m_rst),
.dst_rst(s_rst),
.i_data({m_wb_cyc, m_wb_adr, m_wb_o_dat, m_wb_we, m_wb_sel, m_wb_4_burst, m_wb_8_burst, ~m_new_req_flag}),
.o_data(mssync1),
.i_xfer_req(m_new_req & ~(|m_burst_cnt))
);
wire ssy_flag_newreq = mssync1[0];
assign s_wb_8_burst = mssync1[1];
assign s_wb_4_burst = mssync1[2];
assign s_wb_sel = mssync1[4:3];
assign s_wb_we = mssync1[5];
assign s_wb_o_dat = mssync1[21:6];
assign s_wb_adr = mssync1[45:22];
assign s_wb_cyc = mssync1[46];
endmodule
|
/*
*
* Copyright (c) 2011-2012 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module comm (
input hash_clk,
input rx_new_nonce,
input [31:0] rx_golden_nonce,
output [255:0] tx_midstate,
output [95:0] tx_data
);
reg [351:0] jtag_data_shift = 352'd0;
reg [255:0] midstate = 256'd0;
reg [95:0] data = 96'd0;
assign tx_midstate = midstate;
assign tx_data = data;
reg [31:0] golden_out = 32'd0;
reg [3:0] golden_count = 3'd0;
reg read = 1'b0;
wire [8:0] jtag_data;
wire full, empty;
reg [5:0] jtag_data_count = 6'd0;
wire golden_writing = golden_count[0];
jtag_fifo jtag_fifo_blk (
.rx_clk (hash_clk),
.rx_data ({golden_count, golden_out[7:0]}),
.wr_en (golden_writing & ~full),
.rd_en (read),
.tx_data (jtag_data),
.tx_full (full),
.tx_empty (empty)
);
always @ (posedge hash_clk)
begin
// Writing to JTAG
if (!golden_writing & rx_new_nonce)
begin
golden_out <= rx_golden_nonce;
golden_count <= 4'b1111;
end
else if (golden_writing & !full)
begin
golden_out <= golden_out >> 8;
golden_count <= {1'b0, golden_count[3:1]};
end
// Reading from JTAG
if (!empty & !read)
read <= 1'b1;
if (read)
begin
read <= 1'b0;
jtag_data_shift <= {jtag_data_shift[343:0], jtag_data[7:0]};
if (jtag_data[8] == 1'b0)
jtag_data_count <= 6'd1;
else if (jtag_data_count == 6'd43)
begin
jtag_data_count <= 6'd0;
{midstate, data} <= {jtag_data_shift[343:0], jtag_data[7:0]};
end
else
jtag_data_count <= jtag_data_count + 6'd1;
end
end
endmodule
|
/*
* @file name: gen_bypassfifo
* @author: ruige lee
* @email: wut.ruigeli@gmail.com
* @date: 2021-01-05 14:33:30
* @last modified by: ruige lee
* @last modified time: 2021-01-07 11:45:19
*/
/*
copyright (c) 2020 - 2021 ruige lee <wut.ruigeli@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1 ns / 1 ps
//this module is used at where the data is not a pineline stage ff but may be stalled by pineline
module gen_bypassfifo #
(
parameter dw = 64
)
(
input valid_i,
input [dw-1:0] data_i,
output ready_i,
output valid_o,
output [dw-1:0] data_o,
input ready_o,
input flush,
input clk,
input rstn
);
wire fifo_empty;
wire fifo_full;
wire [dw-1:0] data_pop;
wire isload_set;
wire isload_rst;
wire isload_qout;
assign isload_set = valid_i & ~ready_o;
assign isload_rst = (ready_o & ~fifo_empty) | flush;
assign fifo_empty = ~isload_qout;
assign fifo_full = isload_qout;
gen_dffren # ( .dw(dw)) fifo_bypass ( .dnxt(data_i), .qout(data_pop), .en(isload_set), .clk(clk), .rstn(rstn));
gen_rsffr # ( .dw(1) ) isload ( .set_in(isload_set), .rst_in(isload_rst), .qout(isload_qout), .clk(clk), .rstn(rstn));
assign data_o = fifo_empty ? data_i : data_pop;
assign ready_i = ~fifo_full | flush;
assign valid_o = valid_i | ~fifo_empty;
//assert
always @( posedge clk ) begin
if ( fifo_full & valid_i ) begin
$display("assert fail at bypass fifo");
$finish;
end
end
endmodule
|
/*
*
* Copyright (c) 2011-2012 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 200;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 250;
//// Clock Buffer
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// ZTEX Hashers
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd253;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
golden_nonce <= nonce2;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
/* salsa_slowsixteen.v
*
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, B, Bx, Bo, X0out, Xaddr);
// Latency 16 clock cycles, approx 20nS propagation delay (SLOW!)
input clk;
// input feedback;
input [511:0]B;
input [511:0]Bx;
// output reg [511:0]Bo; // Output is registered
output [511:0]Bo; // Output is async
output [511:0]X0out; // Becomes new X0
output [9:0] Xaddr;
wire [9:0] xa1, xa2, xa3, xa4, ya1, ya2, ya3, ya4;
reg [511:0]x1d1, x1d1a;
reg [511:0]x1d2, x1d2a;
reg [511:0]x1d3, x1d3a;
reg [511:0]x1d4, x1d4a;
reg [511:0]Xod1, Xod1a;
reg [511:0]Xod2, Xod2a;
reg [511:0]Xod3, Xod3a;
reg [511:0]Xod4, X0out;
reg [511:0]xxd1, xxd1a;
reg [511:0]xxd2, xxd2a;
reg [511:0]xxd3, xxd3a;
reg [511:0]xxd4, xxd4a;
reg [511:0]yyd1, yyd1a;
reg [511:0]yyd2, yyd2a;
reg [511:0]yyd3, yyd3a;
reg [511:0]yyd4, yyd4a;
wire [511:0]xx; // Initial xor
wire [511:0]x1; // Salasa core outputs
wire [511:0]x2;
wire [511:0]x3;
wire [511:0]xr;
wire [511:0]Xo;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsax1 (clk, xx, x1, xa1);
salsa_core salsax2 (clk, x1, x2, xa2);
salsa_core salsax3 (clk, x2, x3, xa3);
salsa_core salsax4 (clk, x3, xr, xa4);
wire [511:0]yy; // Initial xor
wire [511:0]y1; // Salasa core outputs
wire [511:0]y2;
wire [511:0]y3;
wire [511:0]yr;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsay1 (clk, yy, y1, ya1);
salsa_core salsay2 (clk, y1, y2, ya2);
salsa_core salsay3 (clk, y2, y3, ya3);
salsa_core salsay4 (clk, y3, yr, ya4);
assign Xaddr = yyd4[9:0] + ya4;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to the propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Xo[`IDX(i)] = xxd4a[`IDX(i)] + xr[`IDX(i)];
assign yy[`IDX(i)] = x1d4a[`IDX(i)] ^ Xo[`IDX(i)];
assign Bo[`IDX(i)] = yyd4a[`IDX(i)] + yr[`IDX(i)]; // Async output
end
endgenerate
always @ (posedge clk)
begin
x1d1 <= Bx;
x1d1a <= x1d1;
x1d2 <= x1d1a;
x1d2a <= x1d2;
x1d3 <= x1d2a;
x1d3a <= x1d3;
x1d4 <= x1d3a;
x1d4a <= x1d4;
Xod1 <= Xo;
Xod1a <= Xod1;
Xod2 <= Xod1a;
Xod2a <= Xod2;
Xod3 <= Xod2a;
Xod3a <= Xod3;
Xod4 <= Xod3a;
X0out <= Xod4; // We output this to become new X0
xxd1 <= xx;
xxd1a <= xxd1;
xxd2 <= xxd1a;
xxd2a <= xxd2;
xxd3 <= xxd2a;
xxd3a <= xxd3;
xxd4 <= xxd3a;
xxd4a <= xxd4;
yyd1 <= yy;
yyd1a <= yyd1;
yyd2 <= yyd1a;
yyd2a <= yyd2;
yyd3 <= yyd2a;
yyd3a <= yyd3;
yyd4 <= yyd3a;
yyd4a <= yyd4;
end
endmodule
module salsa_core (clk, xx, out, Xaddr);
input clk;
input [511:0]xx;
output reg [511:0]out; // Output is registered
output [9:0] Xaddr; // Address output unregistered
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00; // Row results
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
reg [31:0]c00d; // Column results registered
reg [31:0]c01d;
reg [31:0]c02d;
reg [31:0]c03d;
reg [31:0]c04d;
reg [31:0]c05d;
reg [31:0]c06d;
reg [31:0]c07d;
reg [31:0]c08d;
reg [31:0]c09d;
reg [31:0]c10d;
reg [31:0]c11d;
reg [31:0]c12d;
reg [31:0]c13d;
reg [31:0]c14d;
reg [31:0]c15d;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
// rows
assign r01s = c00d + c03d;
assign r01 = c01d ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05d + c04d;
assign r06 = c06d ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10d + c09d;
assign r11 = c11d ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15d + c14d;
assign r12 = c12d ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00d;
assign r02 = c02d ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05d;
assign r07 = c07d ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10d;
assign r08 = c08d ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15d;
assign r13 = c13d ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03d ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04d ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09d ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14d ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00d ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05d ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10d ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15d ^ { r15s[13:0], r15s[31:14] };
wire [511:0]xo; // Rename row results
assign xo = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
assign Xaddr = xo[9:0]; // Unregistered output
always @ (posedge clk)
begin
c00d <= c00;
c01d <= c01;
c02d <= c02;
c03d <= c03;
c04d <= c04;
c05d <= c05;
c06d <= c06;
c07d <= c07;
c08d <= c08;
c09d <= c09;
c10d <= c10;
c11d <= c11;
c12d <= c12;
c13d <= c13;
c14d <= c14;
c15d <= c15;
out <= xo; // Registered output
end
endmodule
|
/*
* @file name: gen_syn
* @author: ruige lee
* @email: wut.ruigeli@gmail.com
* @date: 2020-12-04 19:25:48
* @last modified by: ruige lee
* @last modified time: 2021-03-10 15:44:28
*/
/*
copyright (c) 2020 - 2021 ruige lee <wut.ruigeli@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1 ns / 1 ps
module gen_syn #
(
parameter lever = 2
)
(
input data_asyn,
output data_syn,
input clk,
input rstn
);
wire [lever-1 : 0] syn_dnxt;
wire [lever-1 : 0] syn_qout;
assign syn_dnxt = {syn_qout[lever-2:0], data_asyn};
assign data_syn = syn_qout[lever-1];
gen_dffr # ( .dw(lever) ) syn ( .dnxt(syn_dnxt), .qout(syn_qout), .clk(clk), .rstn(rstn) );
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_timer(
input usb_clk,
input usb_rst,
input io_we,
input [5:0] io_a,
output reg [7:0] io_do
);
reg [31:0] counter;
always @(posedge usb_clk) begin
if(usb_rst) begin
counter <= 32'd0;
io_do <= 32'd0;
end else begin
io_do <= 32'd0;
case(io_a)
6'h11: io_do <= counter[7:0];
6'h12: io_do <= counter[15:8];
6'h13: io_do <= counter[23:16];
6'h14: io_do <= counter[31:24];
endcase
if(io_we & ((io_a == 6'h11)|(io_a == 6'h12)|(io_a == 6'h13)|(io_a == 6'h14)))
counter <= 32'd0;
else
counter <= counter + 32'd1;
end
end
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module main(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
input [15:0] din;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
wire[15:0] EPP_dataword = {EPP_datain, lowbyte};
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) vel0 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd3) vel1 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd5) vel2 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd7) vel3 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[5:0], lowbyte };
end
else if(addr_reg[3:0] == 4'd11) begin
tap <= lowbyte[7:6];
steptime <= lowbyte[T-1:0];
Spolarity <= EPP_datain[7];
// EPP_datain[6] is do_enable_wdt
dirtime <= EPP_datain[T-1:0];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= pos0;
else if(addr_reg[4:2] == 3'd1) data_buf <= pos1;
else if(addr_reg[4:2] == 3'd2) data_buf <= pos2;
else if(addr_reg[4:2] == 3'd3) data_buf <= pos3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= din;
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
// assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
// assign led = do_tristate ? 1'BZ : (real_step[0] ^ real_dir[0]);
assign led = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign nConfig = epp_nReset; // 1'b1;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
endmodule
|
`timescale 1ns / 1ps
/*
generate small cryptonight / cryptonote / monero buffer.
copyright 2018 yuli stremovsky <stremovsky@gmail.com>
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, version 3 of the license.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
`define h(hashname,pos) hashname[(pos+1)*128-1:pos*128]
module gen_small_buffer #
(
parameter num_rounds = 'h020
)
(input clk, input rstn, input [31:0] start_mem_offset, input prev_buf_done, input read_done,
input [255:0] hs2, input [1023:0] hs3,
input [127:0] mem0, input [127:0] mem1, input [127:0] mem2, input [127:0] mem3,
input [127:0] mem4, input [127:0] mem5, input [127:0] mem6, input [127:0] mem7,
output reg start_read, output reg [31:0] mem_offset, output buf_done, output [1023:0] newhash);
localparam nrounds = num_rounds;
(* keep = "true" *) reg [127:0] xout0, xout1, xout2, xout3, xout4, xout5, xout6, xout7;
wire [127:0] k0, k1, k2, k3, k4, k5, k6, k7, k8, k9;
wire keygen_done;
wire [127:0] xout0_w, xout1_w, xout2_w, xout3_w, xout4_w, xout5_w, xout6_w, xout7_w;
(* keep = "true" *) reg [clogb2(num_rounds*8-1)-1:0] total;
(* keep = "true" *) reg [2:0] counter;
reg start_round;
wire aes_round_done0;
wire aes_round_done1;
wire aes_round_done2;
wire aes_round_done3;
wire aes_round_done4;
wire aes_round_done5;
wire aes_round_done6;
wire aes_round_done7;
aes_genkey genkey(.clk(clk), .rstn(rstn), .input0( `h(hs2,0) ), .input1( `h(hs2,1) ), .keygen_done(keygen_done),
.k0(k0), .k1(k1), .k2(k2), .k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9));
aes_round round0(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout0), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout0_w));
aes_round round1(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout1), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout1_w));
aes_round round2(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout2), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout2_w));
aes_round round3(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout3), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout3_w));
aes_round round4(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout4), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout4_w));
aes_round round5(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout5), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout5_w));
aes_round round6(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout6), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout6_w));
aes_round round7(.clk(clk), .rstn(rstn), .start_round(start_round), .xin(xout7), .k0(k0), .k1(k1), .k2(k2),
.k3(k3), .k4(k4), .k5(k5), .k6(k6), .k7(k7), .k8(k8), .k9(k9), .aes_round_done(aes_round_done0), .xout(xout7_w));
function integer clogb2;
input integer depth;
for (clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
endfunction
initial begin
start_read <= 0;
mem_offset <= 0;
counter <= 0;
total <= 0;
start_round <= 0;
end
assign buf_done = (total == nrounds);
// prev_buf_ready => start_read
// read_ready => gen xout
always @(posedge clk)
begin
if (rstn == 0 || total == nrounds)
begin
start_read <= 0;
mem_offset <= 0;
end
else if (start_read == 0 && prev_buf_done && counter == 0 && total == 0)
begin
start_read <= 1;
mem_offset <= start_mem_offset;
end
else if (start_read == 0 && prev_buf_done && counter == 1 && total != 0 && total < nrounds)
begin
start_read <= 1;
mem_offset <= mem_offset + 16*8;
end
else if (read_done && counter == 1)
begin
start_read <= 0;
end
end
always @(posedge clk)
begin
if (rstn == 0 || total == nrounds)
begin
start_round <= 0;
end
else if (read_done && counter == 1 && prev_buf_done && total < nrounds)
begin
start_round <= 1;
end
else if (aes_round_done0)
begin
start_round <= 0;
end
end
always @(posedge clk)
begin
if (rstn == 0)
begin
total <= 0;
end
else if (prev_buf_done && aes_round_done0 && counter == 2 && total < nrounds)
begin
total <= total + 1;
end
end
always @(posedge clk)
begin
if (rstn == 0)
begin
counter <= 0;
end
else if (counter == 0 && total == 0 && start_round == 0 && prev_buf_done)
begin
//initial setup
xout0 <= `h(hs3,0); // input 4
xout1 <= `h(hs3,1); // input 5
xout2 <= `h(hs3,2); // input 6
xout3 <= `h(hs3,3); // input 7
xout4 <= `h(hs3,4); // input 8
xout5 <= `h(hs3,5); // input 9
xout6 <= `h(hs3,6); // input 10
xout7 <= `h(hs3,7); // input 11
counter <= 1;
end
// check if we got data from memory
else if (read_done && counter == 1)
begin
xout0 <= mem0 ^ xout0;
xout1 <= mem1 ^ xout1;
xout2 <= mem2 ^ xout2;
xout3 <= mem3 ^ xout3;
xout4 <= mem4 ^ xout4;
xout5 <= mem5 ^ xout5;
xout6 <= mem6 ^ xout6;
xout7 <= mem7 ^ xout7;
counter <= 2;
end
else if (aes_round_done0 && counter == 2 && total < nrounds)
begin
xout0 <= xout0_w;
xout1 <= xout1_w;
xout2 <= xout2_w;
xout3 <= xout3_w;
xout4 <= xout4_w;
xout5 <= xout5_w;
xout6 <= xout6_w;
xout7 <= xout7_w;
counter <= 1;
end
end
assign newhash = {xout0,xout1,xout2,xout3,xout4,xout5,xout6,xout7};
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg #(
parameter fml_depth = 26,
parameter cache_depth = 14, /* 16kB cache */
parameter invalidate_bit = fml_depth
) (
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [2:0] wb_cti_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input [3:0] wb_sel_i,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
output reg fml_we,
input fml_ack,
output [7:0] fml_sel,
output [63:0] fml_do,
input [63:0] fml_di,
/* Direct Cache Bus */
input dcb_stb,
input [fml_depth-1:0] dcb_adr,
output [63:0] dcb_dat,
output dcb_hit
);
/*
* Line length is the burst length, that is 4*64 bits, or 32 bytes
* Address split up :
*
* | TAG | INDEX | OFFSET |
* |fml_depth-1 cache_depth|cache_depth-1 5|4 0|
*
*/
wire [4:0] offset = wb_adr_i[4:0];
wire [cache_depth-1-5:0] index = wb_adr_i[cache_depth-1:5];
wire [fml_depth-cache_depth-1:0] tag = wb_adr_i[fml_depth-1:cache_depth];
wire [4:0] dcb_offset = dcb_adr[4:0];
wire [cache_depth-1-5:0] dcb_index = dcb_adr[cache_depth-1:5];
wire [fml_depth-cache_depth-1:0] dcb_tag = dcb_adr[fml_depth-1:cache_depth];
wire coincidence = index == dcb_index;
/*
* TAG MEMORY
*
* Addressed by index (length cache_depth-5)
* Contains valid bit + dirty bit + tag
*/
wire [cache_depth-1-5:0] tagmem_a;
reg tagmem_we;
wire [fml_depth-cache_depth-1+2:0] tagmem_di;
wire [fml_depth-cache_depth-1+2:0] tagmem_do;
wire [cache_depth-1-5:0] tagmem_a2;
wire [fml_depth-cache_depth-1+2:0] tagmem_do2;
fmlbrg_tagmem #(
.depth(cache_depth-5),
.width(fml_depth-cache_depth+2)
) tagmem (
.sys_clk(sys_clk),
.a(tagmem_a),
.we(tagmem_we),
.di(tagmem_di),
.do(tagmem_do),
.a2(tagmem_a2),
.do2(tagmem_do2)
);
assign tagmem_a = index;
assign tagmem_a2 = dcb_index;
reg di_valid;
reg di_dirty;
assign tagmem_di = {di_valid, di_dirty, tag};
wire do_valid;
wire do_dirty;
wire [fml_depth-cache_depth-1:0] do_tag;
wire cache_hit;
wire do2_valid;
wire [fml_depth-cache_depth-1:0] do2_tag;
assign do_valid = tagmem_do[fml_depth-cache_depth-1+2];
assign do_dirty = tagmem_do[fml_depth-cache_depth-1+1];
assign do_tag = tagmem_do[fml_depth-cache_depth-1:0];
assign do2_valid = tagmem_do2[fml_depth-cache_depth-1+2];
assign do2_tag = tagmem_do2[fml_depth-cache_depth-1:0];
always @(posedge sys_clk)
fml_adr <= {do_tag, index, 5'd0};
/*
* DATA MEMORY
*
* Addressed by index+offset in 64-bit words (length cache_depth-3)
* 64-bit memory with 8-bit write granularity
*/
wire [cache_depth-3-1:0] datamem_a;
reg [7:0] datamem_we;
wire [63:0] datamem_di;
wire [63:0] datamem_do;
wire [cache_depth-3-1:0] datamem_a2;
wire [63:0] datamem_do2;
fmlbrg_datamem #(
.depth(cache_depth-3)
) datamem (
.sys_clk(sys_clk),
.a(datamem_a),
.we(datamem_we),
.di(datamem_di),
.do(datamem_do),
.a2(datamem_a2),
.do2(datamem_do2)
);
reg [1:0] bcounter;
reg [1:0] bcounter_next;
always @(posedge sys_clk) begin
if(sys_rst)
bcounter <= 2'd0;
else
bcounter <= bcounter_next;
end
reg [1:0] bcounter_sel;
localparam BCOUNTER_RESET = 2'd0;
localparam BCOUNTER_KEEP = 2'd1;
localparam BCOUNTER_LOAD = 2'd2;
localparam BCOUNTER_INC = 2'd3;
always @(*) begin
case(bcounter_sel)
BCOUNTER_RESET: bcounter_next <= 2'd0;
BCOUNTER_KEEP: bcounter_next <= bcounter;
BCOUNTER_LOAD: bcounter_next <= offset[4:3];
BCOUNTER_INC: bcounter_next <= bcounter + 2'd1;
default: bcounter_next <= 2'bxx;
endcase
end
assign datamem_a = {index, bcounter_next};
assign datamem_a2 = {dcb_index, dcb_offset[4:3]};
reg wordsel;
reg next_wordsel;
always @(posedge sys_clk)
wordsel <= next_wordsel;
reg datamem_we_wb;
reg datamem_we_fml;
always @(*) begin
if(datamem_we_fml)
datamem_we = 8'hff;
else if(datamem_we_wb) begin
if(wordsel)
datamem_we = {4'h0, wb_sel_i};
else
datamem_we = {wb_sel_i, 4'h0};
end else
datamem_we = 8'h00;
end
assign datamem_di = datamem_we_wb ? {wb_dat_i, wb_dat_i} : fml_di;
assign wb_dat_o = wordsel ? datamem_do[31:0] : datamem_do[63:32];
assign fml_do = datamem_do;
assign fml_sel = 8'hff;
assign dcb_dat = datamem_do2;
/* FSM */
reg [fml_depth-cache_depth-1:0] tag_r;
always @(posedge sys_clk)
tag_r = tag;
assign cache_hit = do_valid & (do_tag == tag_r);
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter TEST_HIT = 4'd1;
parameter WB_BURST = 4'd2;
parameter EVICT = 4'd3;
parameter EVICT2 = 4'd4;
parameter EVICT3 = 4'd5;
parameter EVICT4 = 4'd6;
parameter REFILL = 4'd7;
parameter REFILL_WAIT = 4'd8;
parameter REFILL1 = 4'd9;
parameter REFILL2 = 4'd10;
parameter REFILL3 = 4'd11;
parameter REFILL4 = 4'd12;
parameter TEST_INVALIDATE = 4'd13;
parameter INVALIDATE = 4'd14;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state <= next_state;
end
end
always @(*) begin
tagmem_we = 1'b0;
di_valid = 1'b0;
di_dirty = 1'b0;
bcounter_sel = BCOUNTER_KEEP;
next_wordsel = 1'bx;
datamem_we_wb = 1'b0;
datamem_we_fml = 1'b0;
wb_ack_o = 1'b0;
fml_stb = 1'b0;
fml_we = 1'b0;
next_state = state;
case(state)
IDLE: begin
bcounter_sel = BCOUNTER_LOAD;
next_wordsel = wb_adr_i[2];
if(wb_cyc_i & wb_stb_i) begin
if(wb_adr_i[invalidate_bit])
next_state = TEST_INVALIDATE;
else
next_state = TEST_HIT;
end
end
TEST_HIT: begin
next_wordsel = ~wordsel;
if(cache_hit) begin
wb_ack_o = 1'b1;
if(wb_we_i) begin
di_valid = 1'b1;
di_dirty = 1'b1;
tagmem_we = 1'b1;
datamem_we_wb = 1'b1;
end
if(wb_cti_i == 3'b010)
next_state = WB_BURST;
else
next_state = IDLE;
end else begin
if(do_dirty)
next_state = EVICT;
else
next_state = REFILL;
end
end
WB_BURST: begin
next_wordsel = ~wordsel;
if(wordsel ^ wb_we_i)
bcounter_sel = BCOUNTER_INC;
if(wb_we_i)
datamem_we_wb = 1'b1;
wb_ack_o = 1'b1;
if(wb_cti_i != 3'b010)
next_state = IDLE;
end
EVICT: begin
fml_stb = 1'b1;
fml_we = 1'b1;
if(fml_ack) begin
bcounter_sel = BCOUNTER_INC;
next_state = EVICT2;
end else
bcounter_sel = BCOUNTER_RESET;
end
EVICT2: begin
bcounter_sel = BCOUNTER_INC;
next_state = EVICT3;
end
EVICT3: begin
bcounter_sel = BCOUNTER_INC;
next_state = EVICT4;
end
EVICT4: begin
bcounter_sel = BCOUNTER_INC;
if(wb_adr_i[invalidate_bit])
next_state = INVALIDATE;
else
next_state = REFILL;
end
REFILL: begin
/* Write the tag first. This will also set the FML address. */
di_valid = 1'b1;
if(wb_we_i)
di_dirty = 1'b1;
else
di_dirty = 1'b0;
if(~(dcb_stb & coincidence)) begin
tagmem_we = 1'b1;
next_state = REFILL_WAIT;
end
end
REFILL_WAIT: next_state = REFILL1; /* one cycle latency for the FML address */
REFILL1: begin
bcounter_sel = BCOUNTER_RESET;
fml_stb = 1'b1;
datamem_we_fml = 1'b1;
if(fml_ack)
next_state = REFILL2;
end
REFILL2: begin
datamem_we_fml = 1'b1;
bcounter_sel = BCOUNTER_INC;
next_state = REFILL3;
end
REFILL3: begin
datamem_we_fml = 1'b1;
bcounter_sel = BCOUNTER_INC;
next_state = REFILL4;
end
REFILL4: begin
datamem_we_fml = 1'b1;
bcounter_sel = BCOUNTER_INC;
next_state = IDLE;
end
TEST_INVALIDATE: begin
if(do_dirty)
next_state = EVICT;
else
next_state = INVALIDATE;
end
INVALIDATE: begin
di_valid = 1'b0;
di_dirty = 1'b0;
tagmem_we = 1'b1;
wb_ack_o = 1'b1;
next_state = IDLE;
end
endcase
end
/* Do not hit on a line being refilled */
reg dcb_can_hit;
always @(posedge sys_clk) begin
dcb_can_hit <= 1'b0;
if(dcb_stb) begin
if((state != REFILL_WAIT)
|| (state != REFILL2)
|| (state != REFILL3)
|| (state != REFILL4))
dcb_can_hit <= 1'b1;
if(~coincidence)
dcb_can_hit <= 1'b1;
end
end
reg [fml_depth-cache_depth-1:0] dcb_tag_r;
always @(posedge sys_clk)
dcb_tag_r = dcb_tag;
assign dcb_hit = dcb_can_hit & do2_valid & (do2_tag == dcb_tag_r);
endmodule
|
// spdx-filecopyrighttext: 2020 efabless corporation
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_proj_example
*
* this is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
* analyzer, the wishbone bus, and the i/o pads.
*
* this project generates an integer count, which is output
* on the user area gpio pads (digital output only). the
* wishbone connection allows the project to be controlled
* (start and stop) from the management soc program.
*
* see the testbenches in directory "mprj_counter" for the
* example programs that drive this user project. the three
* testbenches are "io_ports", "la_test1", and "la_test2".
*
*-------------------------------------------------------------
*/
module prediction #(
parameter bits = 32
)(
`ifdef use_power_pins
inout vccd1, // user area 1 1.8v supply
inout vssd1, // user area 1 digital ground
`endif
// wishbone slave ports (wb mi a)
input wb_clk_i,
//input wb_rst_i,
//input wbs_stb_i,
//input wbs_cyc_i,
//input wbs_we_i,
//input [3:0] wbs_sel_i,
//input [31:0] wbs_dat_i,
//input [31:0] wbs_adr_i,
//output wbs_ack_o,
output [31:0] wbs_dat_o,
// logic analyzer signals
//input [127:0] la_data_in,
//output [127:0] la_data_out,
//input [127:0] la_oenb,
// ios
input [`mprj_io_pads-1:0] io_in,
output [`mprj_io_pads-1:0] io_out
//output [`mprj_io_pads-1:0] io_oeb,
// irq
//output [2:0] irq
);
wire clk;
//wire rst;
//wire rd_en;
//wire wr_en;
wire [1:0] mat_sel;
wire [1:0] adr;
//wire [10:0] in_or_w1;
wire [20:0] w2;
wire [2:0] decision;
wire [`mprj_io_pads-1:0] io_in;
wire [`mprj_io_pads-1:0] io_out;
//wire [`mprj_io_pads-1:0] io_oeb;
// wire [7:0] rout_data;
//wire [7:0] wdata;
//wire [2:0] addr;
//wire [bits-1:0] count;
//wire valid;
//wire [3:0] wstrb;
//wire [31:0] la_write;
// wb mi a
//assign valid = wbs_cyc_i && wbs_stb_i;
//assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign clk=wb_clk_i;
//assign wdata = wbs_dat_i;
//assign addr= wbs_adr_i;
//assign wdata = io_in[15:8];
assign mat_sel= io_in[26:25];
assign adr=io_in[23:22];
//assign in_or_w1=io_in[10:0];
assign w2=io_in[20:0];
//assign addr=io_in[7:5];
//assign addr= wbs_adr_i;
//assign wbs_dat_i=wdata;
//assign io_in=wdata[7:0];
assign io_out[31:29]=decision;
assign wbs_dat_o = decision;
// io
//assign io_out = count;
//assign io_oeb = {(`mprj_io_pads-1){rst}};
// irq
//assign irq = 3'b000; // unused
// la
//assign la_data_out = {{(127-bits){1'b0}}, count};
// assuming la probes [63:32] are for controlling the count register
//assign la_write = ~la_oenb[63:32] & ~{bits{valid}};
// assuming la probes [65:64] are for controlling the count clk & reset
//assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
//assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
mul_matr #(
.bits(bits)
) mul_matr(
.clk(clk),
//.reset(rst),
//.ready(wbs_ack_o)
//.valid(valid),
.mat_sel(mat_sel),
.adr(adr),
//.in_or_w1(in_or_w1),
.w2(w2),
.decision(decision)
//.rout_data(rout_data),
//.rd_en(rd_en),
//.wr_en(wr_en)
//.wstrb(wstrb),
//.la_write(la_write),
//.la_input(la_data_in[63:32]),
//.count(count)
);
endmodule
module mul_matr #(
parameter bits =32
) (
input clk,
input [1:0] mat_sel,
input [1:0]adr,
//input[10:0] in_or_w1,
input signed [20:0] w2,
output reg [2:0] decision
);
reg signed [10:0] mem1 [2:0][2:0]; //input matrix
reg signed [10:0] mem2 [2:0][2:0]; //weight matrix/hiddenlayer
reg signed [20:0] mem3 [2:0][2:0]; //product matrix/hidden layer
reg signed [20:0] mem4 [2:0][2:0]; //output matrix of hidden layer
reg signed [20:0] mem5 [2:0][2:0]; //weight matrix/outputlayer
reg signed [40:0] mem6 [2:0][2:0]; // product matrix/output layer
integer i;
integer j;
integer k;
integer p;
integer q;
integer r;
integer s;
integer a,b,c;
integer e,f;
//integer u,v, ready;
reg [2:0] index;
reg signed [40:0] temp;
reg [2:0] temp1;
reg [2:0] new;
always@(posedge clk)
begin
//input matrix
//mem1[0][0]=-4;
//mem1[0][1]= 15;
//mem1[1][0]=2;
//mem1[1][1]= 4;
if(mat_sel==2'b00)
begin
mem1[adr[1]][adr[0]]=w2;
end
if(mat_sel==2'b01)
begin
mem2[adr[1]][adr[0]]=w2;
end
if(mat_sel==2'b10)
begin
mem5[adr[1]][adr[0]]=w2;
end
// weight matrix hidden layer
//mem2[0][0]=20;
//mem2[0][1]= 15;
//mem2[1][0]=2;
//mem2[1][1]= 3;
// weight matrix output layer
//mem5[0][0]=100;
//mem5[0][1]= -25;
//mem5[1][0]=25;
//mem5[1][1]= 3;
//hidden layer calculations
//matrix initilization
for (p=0;p<=1;p=p+1)begin
for(q=0;q<=1;q=q+1)begin
mem3[p][q]=0;
mem6[p][q]=0;
end
end
//matrix multiplication
for (k=0;k<=1;k=k+1) begin
for (i=0; i<=1;i=i+1)begin
for (j=0;j<=1;j=j+1) begin
mem3[k][i]=mem3[k][i]+(mem1[k][j]*mem2[j][i]);
end
end
end
//out1=mem3[x][y];
//relu
for(r=0;r<=1;r=r+1)begin
for (s=0;s<=1;s=s+1) begin
if(mem3[r][s]<=0)
mem4[r][s]=0;
else if(mem3[r][s]>=0)
mem4[r][s]=mem3[r][s];
end
end
//out2=mem4[x][y];
// output layer calculations
//matrix multiplication
for (a=0;a<=1;a=a+1) begin
for (b=0; b<=1;b=b+1)begin
for (c=0;c<=1;c=c+1) begin
mem6[a][b]=mem6[a][b]+(mem4[a][c]*mem5[c][b]);
end
end
end
//out3=mem6[x][y];
// decision using comparison
temp=mem6[0][0];
index=0;
for (e=0;e<=1;e=e+1) begin
for(f=0;f<=1;f=f+1) begin
index=index+1;
if (temp<=mem6[e][f]) begin
//temp=mem6[e][f];
temp1=index;
end
else if(temp>=mem6[e][f]) begin
temp=temp;
end
end
end
//decision=temp1;
//out4=temp;
new=temp;
decision=temp1;
end
endmodule
`default_nettype wire
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module test_tiny;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [`WIDTH_D0:0] data;
// Outputs
wire [`WIDTH_D0:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(5, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
write(6, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(7, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1006'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
read(10);
check(1006'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
read(11);
check(1006'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
read(12);
check(1006'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
read(13);
check(1006'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
read(14);
check(1006'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [`WIDTH_D0:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error! %h %h", out, wish); end
end
endtask
endmodule
|
/*
// spdx-filecopyrighttext: 2020 efabless corporation
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
*-------------------------------------------------------------
*
* user_proj_impact_head
*
* this head was built by liamoswald for the university of south alabama's sram research into various sram banks
* if liam isn't lazy, he will update this comment with real information at a later date... don't bet on it.
* email him: wdo1621@jagmail.southalabama.edu
*
*-------------------------------------------------------------
*/
`default_nettype none
`include "user_defines.v"
module user_proj_impact_head (
`ifdef use_power_pins
inout vccd1, // user area 1 1.8v supply
inout vssd1, // user area 1 digital ground
`endif
output [32:0] io_oeb,
// irq
output wire [2:0] user_irq,
input wire [7:0] data_in, //sram byte input gpio pins 5-12
output wire [7:0] data_out, //sram byte output gpio pins 13-20
input wire [9:0] word_select, //sram word select gpio pins 21 - 30
input wire [1:0] byte_select, //select byte from word gpio pins 31 & 32
input wire writeenable, //sram write enable signal gpio pin 33
input wire readenable, // gpio pin 34
input wire wl_enable, //sram read enable signal gpio pin 35
input wire precharge, // gpio pin 36
input clk //precharge gpio pin 37
);
//assign io_oeb = 38'b11111111_00000000_1111111111_11_1_1_1_1_1;
assign io_oeb = 33'b1_1_1_1_1_11_1111111111_00000000_11111111;
assign user_irq = 3'b000; // unused
wire [31:0] sram_in;
wire [1023:0] wl; ///////////////////////////changed 1023 to 31 if 32 by 32 sram
wire [31:0] sram_out;
//################################################
//creates the four word decoders instences for the four memory banks
//################################################
// bank 01 wordline decoder
bankworddecoder worddecoder_bank01 (
.clk(clk),
.sel(word_select),
.wl_enable(wl_enable),
.address(wl)
);
//data out mux! this mux takes 4 32bit values from the 4 memory banks, and mux's the output down to a single byte ready for the output pins
onebankmux data_out_mux(
.clk(clk),
.read_enable(readenable),
.bank01_reading(sram_out),
.byte_sel(byte_select),
.data_out(data_out)
);
data_in_decoder datain_decoder(
.clk(clk),
.write_enable(writeenable),
.data_in(data_in),
.sel(byte_select),
.data_out(sram_in)
);
//bankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbank
//bankbankbankbankbankba bank nkbankbankbankbankbankbankbankbankbankbank
//bankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbankbank
//bank01 sram block
full_sram bank01(
`ifdef use_power_pins
.vccd1(vccd1), // user area 1 1.8v supply
.vssd1(vssd1), // user area 1 digital ground
`endif
.pre(precharge),
.readen(readenable),
.writeen(writeenable),
.datain0(sram_in [0]),
.datain1(sram_in [1]),
.datain2(sram_in [2]),
.datain3(sram_in [3]),
.datain4(sram_in [4]),
.datain5(sram_in [5]),
.datain6(sram_in [6]),
.datain7(sram_in [7]),
.datain8(sram_in [8]),
.datain9(sram_in [9]),
.datain10(sram_in [10]),
.datain11(sram_in [11]),
.datain12(sram_in [12]),
.datain13(sram_in [13]),
.datain14(sram_in [14]),
.datain15(sram_in [15]),
.datain16(sram_in [16]),
.datain17(sram_in [17]),
.datain18(sram_in [18]),
.datain19(sram_in [19]),
.datain20(sram_in [20]),
.datain21(sram_in [21]),
.datain22(sram_in [22]),
.datain23(sram_in [23]),
.datain24(sram_in [24]),
.datain25(sram_in [25]),
.datain26(sram_in [26]),
.datain27(sram_in [27]),
.datain28(sram_in [28]),
.datain29(sram_in [29]),
.datain30(sram_in [30]),
.datain31(sram_in [31]),
.dataout0(sram_out [0]),
.dataout1(sram_out [1]),
.dataout2(sram_out [2]),
.dataout3(sram_out [3]),
.dataout4(sram_out [4]),
.dataout5(sram_out [5]),
.dataout6(sram_out [6]),
.dataout7(sram_out [7]),
.dataout8(sram_out [8]),
.dataout9(sram_out [9]),
.dataout10(sram_out [10]),
.dataout11(sram_out [11]),
.dataout12(sram_out [12]),
.dataout13(sram_out [13]),
.dataout14(sram_out [14]),
.dataout15(sram_out [15]),
.dataout16(sram_out [16]),
.dataout17(sram_out [17]),
.dataout18(sram_out [18]),
.dataout19(sram_out [19]),
.dataout20(sram_out [20]),
.dataout21(sram_out [21]),
.dataout22(sram_out [22]),
.dataout23(sram_out [23]),
.dataout24(sram_out [24]),
.dataout25(sram_out [25]),
.dataout26(sram_out [26]),
.dataout27(sram_out [27]),
.dataout28(sram_out [28]),
.dataout29(sram_out [29]),
.dataout30(sram_out [30]),
.dataout31(sram_out [31]),
.wl0(wl [0]),
.wl1(wl [1]),
.wl2(wl [2]),
.wl3(wl [3]),
.wl4(wl [4]),
.wl5(wl [5]),
.wl6(wl [6]),
.wl7(wl [7]),
.wl8(wl [8]),
.wl9(wl [9]),
.wl10(wl [10]),
.wl11(wl [11]),
.wl12(wl [12]),
.wl13(wl [13]),
.wl14(wl [14]),
.wl15(wl [15]),
.wl16(wl [16]),
.wl17(wl [17]),
.wl18(wl [18]),
.wl19(wl [19]),
.wl20(wl [20]),
.wl21(wl [21]),
.wl22(wl [22]),
.wl23(wl [23]),
.wl24(wl [24]),
.wl25(wl [25]),
.wl26(wl [26]),
.wl27(wl [27]),
.wl28(wl [28]),
.wl29(wl [29]),
.wl30(wl [30]),
.wl31(wl [31]),
.wl32(wl [32]),
.wl33(wl [33]),
.wl34(wl [34]),
.wl35(wl [35]),
.wl36(wl [36]),
.wl37(wl [37]),
.wl38(wl [38]),
.wl39(wl [39]),
.wl40(wl [40]),
.wl41(wl [41]),
.wl42(wl [42]),
.wl43(wl [43]),
.wl44(wl [44]),
.wl45(wl [45]),
.wl46(wl [46]),
.wl47(wl [47]),
.wl48(wl [48]),
.wl49(wl [49]),
.wl50(wl [50]),
.wl51(wl [51]),
.wl52(wl [52]),
.wl53(wl [53]),
.wl54(wl [54]),
.wl55(wl [55]),
.wl56(wl [56]),
.wl57(wl [57]),
.wl58(wl [58]),
.wl59(wl [59]),
.wl60(wl [60]),
.wl61(wl [61]),
.wl62(wl [62]),
.wl63(wl [63]),
.wl64(wl [64]),
.wl65(wl [65]),
.wl66(wl [66]),
.wl67(wl [67]),
.wl68(wl [68]),
.wl69(wl [69]),
.wl70(wl [70]),
.wl71(wl [71]),
.wl72(wl [72]),
.wl73(wl [73]),
.wl74(wl [74]),
.wl75(wl [75]),
.wl76(wl [76]),
.wl77(wl [77]),
.wl78(wl [78]),
.wl79(wl [79]),
.wl80(wl [80]),
.wl81(wl [81]),
.wl82(wl [82]),
.wl83(wl [83]),
.wl84(wl [84]),
.wl85(wl [85]),
.wl86(wl [86]),
.wl87(wl [87]),
.wl88(wl [88]),
.wl89(wl [89]),
.wl90(wl [90]),
.wl91(wl [91]),
.wl92(wl [92]),
.wl93(wl [93]),
.wl94(wl [94]),
.wl95(wl [95]),
.wl96(wl [96]),
.wl97(wl [97]),
.wl98(wl [98]),
.wl99(wl [99]),
.wl100(wl [100]),
.wl101(wl [101]),
.wl102(wl [102]),
.wl103(wl [103]),
.wl104(wl [104]),
.wl105(wl [105]),
.wl106(wl [106]),
.wl107(wl [107]),
.wl108(wl [108]),
.wl109(wl [109]),
.wl110(wl [110]),
.wl111(wl [111]),
.wl112(wl [112]),
.wl113(wl [113]),
.wl114(wl [114]),
.wl115(wl [115]),
.wl116(wl [116]),
.wl117(wl [117]),
.wl118(wl [118]),
.wl119(wl [119]),
.wl120(wl [120]),
.wl121(wl [121]),
.wl122(wl [122]),
.wl123(wl [123]),
.wl124(wl [124]),
.wl125(wl [125]),
.wl126(wl [126]),
.wl127(wl [127]),
.wl128(wl [128]),
.wl129(wl [129]),
.wl130(wl [130]),
.wl131(wl [131]),
.wl132(wl [132]),
.wl133(wl [133]),
.wl134(wl [134]),
.wl135(wl [135]),
.wl136(wl [136]),
.wl137(wl [137]),
.wl138(wl [138]),
.wl139(wl [139]),
.wl140(wl [140]),
.wl141(wl [141]),
.wl142(wl [142]),
.wl143(wl [143]),
.wl144(wl [144]),
.wl145(wl [145]),
.wl146(wl [146]),
.wl147(wl [147]),
.wl148(wl [148]),
.wl149(wl [149]),
.wl150(wl [150]),
.wl151(wl [151]),
.wl152(wl [152]),
.wl153(wl [153]),
.wl154(wl [154]),
.wl155(wl [155]),
.wl156(wl [156]),
.wl157(wl [157]),
.wl158(wl [158]),
.wl159(wl [159]),
.wl160(wl [160]),
.wl161(wl [161]),
.wl162(wl [162]),
.wl163(wl [163]),
.wl164(wl [164]),
.wl165(wl [165]),
.wl166(wl [166]),
.wl167(wl [167]),
.wl168(wl [168]),
.wl169(wl [169]),
.wl170(wl [170]),
.wl171(wl [171]),
.wl172(wl [172]),
.wl173(wl [173]),
.wl174(wl [174]),
.wl175(wl [175]),
.wl176(wl [176]),
.wl177(wl [177]),
.wl178(wl [178]),
.wl179(wl [179]),
.wl180(wl [180]),
.wl181(wl [181]),
.wl182(wl [182]),
.wl183(wl [183]),
.wl184(wl [184]),
.wl185(wl [185]),
.wl186(wl [186]),
.wl187(wl [187]),
.wl188(wl [188]),
.wl189(wl [189]),
.wl190(wl [190]),
.wl191(wl [191]),
.wl192(wl [192]),
.wl193(wl [193]),
.wl194(wl [194]),
.wl195(wl [195]),
.wl196(wl [196]),
.wl197(wl [197]),
.wl198(wl [198]),
.wl199(wl [199]),
.wl200(wl [200]),
.wl201(wl [201]),
.wl202(wl [202]),
.wl203(wl [203]),
.wl204(wl [204]),
.wl205(wl [205]),
.wl206(wl [206]),
.wl207(wl [207]),
.wl208(wl [208]),
.wl209(wl [209]),
.wl210(wl [210]),
.wl211(wl [211]),
.wl212(wl [212]),
.wl213(wl [213]),
.wl214(wl [214]),
.wl215(wl [215]),
.wl216(wl [216]),
.wl217(wl [217]),
.wl218(wl [218]),
.wl219(wl [219]),
.wl220(wl [220]),
.wl221(wl [221]),
.wl222(wl [222]),
.wl223(wl [223]),
.wl224(wl [224]),
.wl225(wl [225]),
.wl226(wl [226]),
.wl227(wl [227]),
.wl228(wl [228]),
.wl229(wl [229]),
.wl230(wl [230]),
.wl231(wl [231]),
.wl232(wl [232]),
.wl233(wl [233]),
.wl234(wl [234]),
.wl235(wl [235]),
.wl236(wl [236]),
.wl237(wl [237]),
.wl238(wl [238]),
.wl239(wl [239]),
.wl240(wl [240]),
.wl241(wl [241]),
.wl242(wl [242]),
.wl243(wl [243]),
.wl244(wl [244]),
.wl245(wl [245]),
.wl246(wl [246]),
.wl247(wl [247]),
.wl248(wl [248]),
.wl249(wl [249]),
.wl250(wl [250]),
.wl251(wl [251]),
.wl252(wl [252]),
.wl253(wl [253]),
.wl254(wl [254]),
.wl255(wl [255]),
.wl256(wl [256]),
.wl257(wl [257]),
.wl258(wl [258]),
.wl259(wl [259]),
.wl260(wl [260]),
.wl261(wl [261]),
.wl262(wl [262]),
.wl263(wl [263]),
.wl264(wl [264]),
.wl265(wl [265]),
.wl266(wl [266]),
.wl267(wl [267]),
.wl268(wl [268]),
.wl269(wl [269]),
.wl270(wl [270]),
.wl271(wl [271]),
.wl272(wl [272]),
.wl273(wl [273]),
.wl274(wl [274]),
.wl275(wl [275]),
.wl276(wl [276]),
.wl277(wl [277]),
.wl278(wl [278]),
.wl279(wl [279]),
.wl280(wl [280]),
.wl281(wl [281]),
.wl282(wl [282]),
.wl283(wl [283]),
.wl284(wl [284]),
.wl285(wl [285]),
.wl286(wl [286]),
.wl287(wl [287]),
.wl288(wl [288]),
.wl289(wl [289]),
.wl290(wl [290]),
.wl291(wl [291]),
.wl292(wl [292]),
.wl293(wl [293]),
.wl294(wl [294]),
.wl295(wl [295]),
.wl296(wl [296]),
.wl297(wl [297]),
.wl298(wl [298]),
.wl299(wl [299]),
.wl300(wl [300]),
.wl301(wl [301]),
.wl302(wl [302]),
.wl303(wl [303]),
.wl304(wl [304]),
.wl305(wl [305]),
.wl306(wl [306]),
.wl307(wl [307]),
.wl308(wl [308]),
.wl309(wl [309]),
.wl310(wl [310]),
.wl311(wl [311]),
.wl312(wl [312]),
.wl313(wl [313]),
.wl314(wl [314]),
.wl315(wl [315]),
.wl316(wl [316]),
.wl317(wl [317]),
.wl318(wl [318]),
.wl319(wl [319]),
.wl320(wl [320]),
.wl321(wl [321]),
.wl322(wl [322]),
.wl323(wl [323]),
.wl324(wl [324]),
.wl325(wl [325]),
.wl326(wl [326]),
.wl327(wl [327]),
.wl328(wl [328]),
.wl329(wl [329]),
.wl330(wl [330]),
.wl331(wl [331]),
.wl332(wl [332]),
.wl333(wl [333]),
.wl334(wl [334]),
.wl335(wl [335]),
.wl336(wl [336]),
.wl337(wl [337]),
.wl338(wl [338]),
.wl339(wl [339]),
.wl340(wl [340]),
.wl341(wl [341]),
.wl342(wl [342]),
.wl343(wl [343]),
.wl344(wl [344]),
.wl345(wl [345]),
.wl346(wl [346]),
.wl347(wl [347]),
.wl348(wl [348]),
.wl349(wl [349]),
.wl350(wl [350]),
.wl351(wl [351]),
.wl352(wl [352]),
.wl353(wl [353]),
.wl354(wl [354]),
.wl355(wl [355]),
.wl356(wl [356]),
.wl357(wl [357]),
.wl358(wl [358]),
.wl359(wl [359]),
.wl360(wl [360]),
.wl361(wl [361]),
.wl362(wl [362]),
.wl363(wl [363]),
.wl364(wl [364]),
.wl365(wl [365]),
.wl366(wl [366]),
.wl367(wl [367]),
.wl368(wl [368]),
.wl369(wl [369]),
.wl370(wl [370]),
.wl371(wl [371]),
.wl372(wl [372]),
.wl373(wl [373]),
.wl374(wl [374]),
.wl375(wl [375]),
.wl376(wl [376]),
.wl377(wl [377]),
.wl378(wl [378]),
.wl379(wl [379]),
.wl380(wl [380]),
.wl381(wl [381]),
.wl382(wl [382]),
.wl383(wl [383]),
.wl384(wl [384]),
.wl385(wl [385]),
.wl386(wl [386]),
.wl387(wl [387]),
.wl388(wl [388]),
.wl389(wl [389]),
.wl390(wl [390]),
.wl391(wl [391]),
.wl392(wl [392]),
.wl393(wl [393]),
.wl394(wl [394]),
.wl395(wl [395]),
.wl396(wl [396]),
.wl397(wl [397]),
.wl398(wl [398]),
.wl399(wl [399]),
.wl400(wl [400]),
.wl401(wl [401]),
.wl402(wl [402]),
.wl403(wl [403]),
.wl404(wl [404]),
.wl405(wl [405]),
.wl406(wl [406]),
.wl407(wl [407]),
.wl408(wl [408]),
.wl409(wl [409]),
.wl410(wl [410]),
.wl411(wl [411]),
.wl412(wl [412]),
.wl413(wl [413]),
.wl414(wl [414]),
.wl415(wl [415]),
.wl416(wl [416]),
.wl417(wl [417]),
.wl418(wl [418]),
.wl419(wl [419]),
.wl420(wl [420]),
.wl421(wl [421]),
.wl422(wl [422]),
.wl423(wl [423]),
.wl424(wl [424]),
.wl425(wl [425]),
.wl426(wl [426]),
.wl427(wl [427]),
.wl428(wl [428]),
.wl429(wl [429]),
.wl430(wl [430]),
.wl431(wl [431]),
.wl432(wl [432]),
.wl433(wl [433]),
.wl434(wl [434]),
.wl435(wl [435]),
.wl436(wl [436]),
.wl437(wl [437]),
.wl438(wl [438]),
.wl439(wl [439]),
.wl440(wl [440]),
.wl441(wl [441]),
.wl442(wl [442]),
.wl443(wl [443]),
.wl444(wl [444]),
.wl445(wl [445]),
.wl446(wl [446]),
.wl447(wl [447]),
.wl448(wl [448]),
.wl449(wl [449]),
.wl450(wl [450]),
.wl451(wl [451]),
.wl452(wl [452]),
.wl453(wl [453]),
.wl454(wl [454]),
.wl455(wl [455]),
.wl456(wl [456]),
.wl457(wl [457]),
.wl458(wl [458]),
.wl459(wl [459]),
.wl460(wl [460]),
.wl461(wl [461]),
.wl462(wl [462]),
.wl463(wl [463]),
.wl464(wl [464]),
.wl465(wl [465]),
.wl466(wl [466]),
.wl467(wl [467]),
.wl468(wl [468]),
.wl469(wl [469]),
.wl470(wl [470]),
.wl471(wl [471]),
.wl472(wl [472]),
.wl473(wl [473]),
.wl474(wl [474]),
.wl475(wl [475]),
.wl476(wl [476]),
.wl477(wl [477]),
.wl478(wl [478]),
.wl479(wl [479]),
.wl480(wl [480]),
.wl481(wl [481]),
.wl482(wl [482]),
.wl483(wl [483]),
.wl484(wl [484]),
.wl485(wl [485]),
.wl486(wl [486]),
.wl487(wl [487]),
.wl488(wl [488]),
.wl489(wl [489]),
.wl490(wl [490]),
.wl491(wl [491]),
.wl492(wl [492]),
.wl493(wl [493]),
.wl494(wl [494]),
.wl495(wl [495]),
.wl496(wl [496]),
.wl497(wl [497]),
.wl498(wl [498]),
.wl499(wl [499]),
.wl500(wl [500]),
.wl501(wl [501]),
.wl502(wl [502]),
.wl503(wl [503]),
.wl504(wl [504]),
.wl505(wl [505]),
.wl506(wl [506]),
.wl507(wl [507]),
.wl508(wl [508]),
.wl509(wl [509]),
.wl510(wl [510]),
.wl511(wl [511]),
.wl512(wl [512]),
.wl513(wl [513]),
.wl514(wl [514]),
.wl515(wl [515]),
.wl516(wl [516]),
.wl517(wl [517]),
.wl518(wl [518]),
.wl519(wl [519]),
.wl520(wl [520]),
.wl521(wl [521]),
.wl522(wl [522]),
.wl523(wl [523]),
.wl524(wl [524]),
.wl525(wl [525]),
.wl526(wl [526]),
.wl527(wl [527]),
.wl528(wl [528]),
.wl529(wl [529]),
.wl530(wl [530]),
.wl531(wl [531]),
.wl532(wl [532]),
.wl533(wl [533]),
.wl534(wl [534]),
.wl535(wl [535]),
.wl536(wl [536]),
.wl537(wl [537]),
.wl538(wl [538]),
.wl539(wl [539]),
.wl540(wl [540]),
.wl541(wl [541]),
.wl542(wl [542]),
.wl543(wl [543]),
.wl544(wl [544]),
.wl545(wl [545]),
.wl546(wl [546]),
.wl547(wl [547]),
.wl548(wl [548]),
.wl549(wl [549]),
.wl550(wl [550]),
.wl551(wl [551]),
.wl552(wl [552]),
.wl553(wl [553]),
.wl554(wl [554]),
.wl555(wl [555]),
.wl556(wl [556]),
.wl557(wl [557]),
.wl558(wl [558]),
.wl559(wl [559]),
.wl560(wl [560]),
.wl561(wl [561]),
.wl562(wl [562]),
.wl563(wl [563]),
.wl564(wl [564]),
.wl565(wl [565]),
.wl566(wl [566]),
.wl567(wl [567]),
.wl568(wl [568]),
.wl569(wl [569]),
.wl570(wl [570]),
.wl571(wl [571]),
.wl572(wl [572]),
.wl573(wl [573]),
.wl574(wl [574]),
.wl575(wl [575]),
.wl576(wl [576]),
.wl577(wl [577]),
.wl578(wl [578]),
.wl579(wl [579]),
.wl580(wl [580]),
.wl581(wl [581]),
.wl582(wl [582]),
.wl583(wl [583]),
.wl584(wl [584]),
.wl585(wl [585]),
.wl586(wl [586]),
.wl587(wl [587]),
.wl588(wl [588]),
.wl589(wl [589]),
.wl590(wl [590]),
.wl591(wl [591]),
.wl592(wl [592]),
.wl593(wl [593]),
.wl594(wl [594]),
.wl595(wl [595]),
.wl596(wl [596]),
.wl597(wl [597]),
.wl598(wl [598]),
.wl599(wl [599]),
.wl600(wl [600]),
.wl601(wl [601]),
.wl602(wl [602]),
.wl603(wl [603]),
.wl604(wl [604]),
.wl605(wl [605]),
.wl606(wl [606]),
.wl607(wl [607]),
.wl608(wl [608]),
.wl609(wl [609]),
.wl610(wl [610]),
.wl611(wl [611]),
.wl612(wl [612]),
.wl613(wl [613]),
.wl614(wl [614]),
.wl615(wl [615]),
.wl616(wl [616]),
.wl617(wl [617]),
.wl618(wl [618]),
.wl619(wl [619]),
.wl620(wl [620]),
.wl621(wl [621]),
.wl622(wl [622]),
.wl623(wl [623]),
.wl624(wl [624]),
.wl625(wl [625]),
.wl626(wl [626]),
.wl627(wl [627]),
.wl628(wl [628]),
.wl629(wl [629]),
.wl630(wl [630]),
.wl631(wl [631]),
.wl632(wl [632]),
.wl633(wl [633]),
.wl634(wl [634]),
.wl635(wl [635]),
.wl636(wl [636]),
.wl637(wl [637]),
.wl638(wl [638]),
.wl639(wl [639]),
.wl640(wl [640]),
.wl641(wl [641]),
.wl642(wl [642]),
.wl643(wl [643]),
.wl644(wl [644]),
.wl645(wl [645]),
.wl646(wl [646]),
.wl647(wl [647]),
.wl648(wl [648]),
.wl649(wl [649]),
.wl650(wl [650]),
.wl651(wl [651]),
.wl652(wl [652]),
.wl653(wl [653]),
.wl654(wl [654]),
.wl655(wl [655]),
.wl656(wl [656]),
.wl657(wl [657]),
.wl658(wl [658]),
.wl659(wl [659]),
.wl660(wl [660]),
.wl661(wl [661]),
.wl662(wl [662]),
.wl663(wl [663]),
.wl664(wl [664]),
.wl665(wl [665]),
.wl666(wl [666]),
.wl667(wl [667]),
.wl668(wl [668]),
.wl669(wl [669]),
.wl670(wl [670]),
.wl671(wl [671]),
.wl672(wl [672]),
.wl673(wl [673]),
.wl674(wl [674]),
.wl675(wl [675]),
.wl676(wl [676]),
.wl677(wl [677]),
.wl678(wl [678]),
.wl679(wl [679]),
.wl680(wl [680]),
.wl681(wl [681]),
.wl682(wl [682]),
.wl683(wl [683]),
.wl684(wl [684]),
.wl685(wl [685]),
.wl686(wl [686]),
.wl687(wl [687]),
.wl688(wl [688]),
.wl689(wl [689]),
.wl690(wl [690]),
.wl691(wl [691]),
.wl692(wl [692]),
.wl693(wl [693]),
.wl694(wl [694]),
.wl695(wl [695]),
.wl696(wl [696]),
.wl697(wl [697]),
.wl698(wl [698]),
.wl699(wl [699]),
.wl700(wl [700]),
.wl701(wl [701]),
.wl702(wl [702]),
.wl703(wl [703]),
.wl704(wl [704]),
.wl705(wl [705]),
.wl706(wl [706]),
.wl707(wl [707]),
.wl708(wl [708]),
.wl709(wl [709]),
.wl710(wl [710]),
.wl711(wl [711]),
.wl712(wl [712]),
.wl713(wl [713]),
.wl714(wl [714]),
.wl715(wl [715]),
.wl716(wl [716]),
.wl717(wl [717]),
.wl718(wl [718]),
.wl719(wl [719]),
.wl720(wl [720]),
.wl721(wl [721]),
.wl722(wl [722]),
.wl723(wl [723]),
.wl724(wl [724]),
.wl725(wl [725]),
.wl726(wl [726]),
.wl727(wl [727]),
.wl728(wl [728]),
.wl729(wl [729]),
.wl730(wl [730]),
.wl731(wl [731]),
.wl732(wl [732]),
.wl733(wl [733]),
.wl734(wl [734]),
.wl735(wl [735]),
.wl736(wl [736]),
.wl737(wl [737]),
.wl738(wl [738]),
.wl739(wl [739]),
.wl740(wl [740]),
.wl741(wl [741]),
.wl742(wl [742]),
.wl743(wl [743]),
.wl744(wl [744]),
.wl745(wl [745]),
.wl746(wl [746]),
.wl747(wl [747]),
.wl748(wl [748]),
.wl749(wl [749]),
.wl750(wl [750]),
.wl751(wl [751]),
.wl752(wl [752]),
.wl753(wl [753]),
.wl754(wl [754]),
.wl755(wl [755]),
.wl756(wl [756]),
.wl757(wl [757]),
.wl758(wl [758]),
.wl759(wl [759]),
.wl760(wl [760]),
.wl761(wl [761]),
.wl762(wl [762]),
.wl763(wl [763]),
.wl764(wl [764]),
.wl765(wl [765]),
.wl766(wl [766]),
.wl767(wl [767]),
.wl768(wl [768]),
.wl769(wl [769]),
.wl770(wl [770]),
.wl771(wl [771]),
.wl772(wl [772]),
.wl773(wl [773]),
.wl774(wl [774]),
.wl775(wl [775]),
.wl776(wl [776]),
.wl777(wl [777]),
.wl778(wl [778]),
.wl779(wl [779]),
.wl780(wl [780]),
.wl781(wl [781]),
.wl782(wl [782]),
.wl783(wl [783]),
.wl784(wl [784]),
.wl785(wl [785]),
.wl786(wl [786]),
.wl787(wl [787]),
.wl788(wl [788]),
.wl789(wl [789]),
.wl790(wl [790]),
.wl791(wl [791]),
.wl792(wl [792]),
.wl793(wl [793]),
.wl794(wl [794]),
.wl795(wl [795]),
.wl796(wl [796]),
.wl797(wl [797]),
.wl798(wl [798]),
.wl799(wl [799]),
.wl800(wl [800]),
.wl801(wl [801]),
.wl802(wl [802]),
.wl803(wl [803]),
.wl804(wl [804]),
.wl805(wl [805]),
.wl806(wl [806]),
.wl807(wl [807]),
.wl808(wl [808]),
.wl809(wl [809]),
.wl810(wl [810]),
.wl811(wl [811]),
.wl812(wl [812]),
.wl813(wl [813]),
.wl814(wl [814]),
.wl815(wl [815]),
.wl816(wl [816]),
.wl817(wl [817]),
.wl818(wl [818]),
.wl819(wl [819]),
.wl820(wl [820]),
.wl821(wl [821]),
.wl822(wl [822]),
.wl823(wl [823]),
.wl824(wl [824]),
.wl825(wl [825]),
.wl826(wl [826]),
.wl827(wl [827]),
.wl828(wl [828]),
.wl829(wl [829]),
.wl830(wl [830]),
.wl831(wl [831]),
.wl832(wl [832]),
.wl833(wl [833]),
.wl834(wl [834]),
.wl835(wl [835]),
.wl836(wl [836]),
.wl837(wl [837]),
.wl838(wl [838]),
.wl839(wl [839]),
.wl840(wl [840]),
.wl841(wl [841]),
.wl842(wl [842]),
.wl843(wl [843]),
.wl844(wl [844]),
.wl845(wl [845]),
.wl846(wl [846]),
.wl847(wl [847]),
.wl848(wl [848]),
.wl849(wl [849]),
.wl850(wl [850]),
.wl851(wl [851]),
.wl852(wl [852]),
.wl853(wl [853]),
.wl854(wl [854]),
.wl855(wl [855]),
.wl856(wl [856]),
.wl857(wl [857]),
.wl858(wl [858]),
.wl859(wl [859]),
.wl860(wl [860]),
.wl861(wl [861]),
.wl862(wl [862]),
.wl863(wl [863]),
.wl864(wl [864]),
.wl865(wl [865]),
.wl866(wl [866]),
.wl867(wl [867]),
.wl868(wl [868]),
.wl869(wl [869]),
.wl870(wl [870]),
.wl871(wl [871]),
.wl872(wl [872]),
.wl873(wl [873]),
.wl874(wl [874]),
.wl875(wl [875]),
.wl876(wl [876]),
.wl877(wl [877]),
.wl878(wl [878]),
.wl879(wl [879]),
.wl880(wl [880]),
.wl881(wl [881]),
.wl882(wl [882]),
.wl883(wl [883]),
.wl884(wl [884]),
.wl885(wl [885]),
.wl886(wl [886]),
.wl887(wl [887]),
.wl888(wl [888]),
.wl889(wl [889]),
.wl890(wl [890]),
.wl891(wl [891]),
.wl892(wl [892]),
.wl893(wl [893]),
.wl894(wl [894]),
.wl895(wl [895]),
.wl896(wl [896]),
.wl897(wl [897]),
.wl898(wl [898]),
.wl899(wl [899]),
.wl900(wl [900]),
.wl901(wl [901]),
.wl902(wl [902]),
.wl903(wl [903]),
.wl904(wl [904]),
.wl905(wl [905]),
.wl906(wl [906]),
.wl907(wl [907]),
.wl908(wl [908]),
.wl909(wl [909]),
.wl910(wl [910]),
.wl911(wl [911]),
.wl912(wl [912]),
.wl913(wl [913]),
.wl914(wl [914]),
.wl915(wl [915]),
.wl916(wl [916]),
.wl917(wl [917]),
.wl918(wl [918]),
.wl919(wl [919]),
.wl920(wl [920]),
.wl921(wl [921]),
.wl922(wl [922]),
.wl923(wl [923]),
.wl924(wl [924]),
.wl925(wl [925]),
.wl926(wl [926]),
.wl927(wl [927]),
.wl928(wl [928]),
.wl929(wl [929]),
.wl930(wl [930]),
.wl931(wl [931]),
.wl932(wl [932]),
.wl933(wl [933]),
.wl934(wl [934]),
.wl935(wl [935]),
.wl936(wl [936]),
.wl937(wl [937]),
.wl938(wl [938]),
.wl939(wl [939]),
.wl940(wl [940]),
.wl941(wl [941]),
.wl942(wl [942]),
.wl943(wl [943]),
.wl944(wl [944]),
.wl945(wl [945]),
.wl946(wl [946]),
.wl947(wl [947]),
.wl948(wl [948]),
.wl949(wl [949]),
.wl950(wl [950]),
.wl951(wl [951]),
.wl952(wl [952]),
.wl953(wl [953]),
.wl954(wl [954]),
.wl955(wl [955]),
.wl956(wl [956]),
.wl957(wl [957]),
.wl958(wl [958]),
.wl959(wl [959]),
.wl960(wl [960]),
.wl961(wl [961]),
.wl962(wl [962]),
.wl963(wl [963]),
.wl964(wl [964]),
.wl965(wl [965]),
.wl966(wl [966]),
.wl967(wl [967]),
.wl968(wl [968]),
.wl969(wl [969]),
.wl970(wl [970]),
.wl971(wl [971]),
.wl972(wl [972]),
.wl973(wl [973]),
.wl974(wl [974]),
.wl975(wl [975]),
.wl976(wl [976]),
.wl977(wl [977]),
.wl978(wl [978]),
.wl979(wl [979]),
.wl980(wl [980]),
.wl981(wl [981]),
.wl982(wl [982]),
.wl983(wl [983]),
.wl984(wl [984]),
.wl985(wl [985]),
.wl986(wl [986]),
.wl987(wl [987]),
.wl988(wl [988]),
.wl989(wl [989]),
.wl990(wl [990]),
.wl991(wl [991]),
.wl992(wl [992]),
.wl993(wl [993]),
.wl994(wl [994]),
.wl995(wl [995]),
.wl996(wl [996]),
.wl997(wl [997]),
.wl998(wl [998]),
.wl999(wl [999]),
.wl1000(wl [1000]),
.wl1001(wl [1001]),
.wl1002(wl [1002]),
.wl1003(wl [1003]),
.wl1004(wl [1004]),
.wl1005(wl [1005]),
.wl1006(wl [1006]),
.wl1007(wl [1007]),
.wl1008(wl [1008]),
.wl1009(wl [1009]),
.wl1010(wl [1010]),
.wl1011(wl [1011]),
.wl1012(wl [1012]),
.wl1013(wl [1013]),
.wl1014(wl [1014]),
.wl1015(wl [1015]),
.wl1016(wl [1016]),
.wl1017(wl [1017]),
.wl1018(wl [1018]),
.wl1019(wl [1019]),
.wl1020(wl [1020]),
.wl1021(wl [1021]),
.wl1022(wl [1022]),
.wl1023(wl [1023])
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd3;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd4;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
reg [1:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 2'd0;
end else begin
if(write)
counter_writedirection <= 2'd3;
else if(|counter_writedirection)
counter_writedirection <= counter_writedirection - 2'd1;
end
end
reg direction0;
always @(posedge sys_clk) begin
direction0 <= ~(write | (|counter_writedirection));
direction <= direction0;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]), .precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fetchtexel #(
parameter depth = 2,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-5-1:0] fetch_adr,
output pipe_stb_o,
input pipe_ack_i,
output [255:0] fetch_dat,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di
);
/* Generate FML requests */
wire fetch_en;
always @(posedge sys_clk) begin
if(sys_rst)
fml_stb <= 1'b0;
else begin
if(fml_ack)
fml_stb <= 1'b0;
if(pipe_ack_o) begin
fml_stb <= pipe_stb_i;
fml_adr <= {fetch_adr, 5'd0};
end
end
end
assign pipe_ack_o = fetch_en & (~fml_stb | fml_ack);
/* Gather received data */
wire fifo_we;
tmu2_fifo64to256 #(
.depth(depth)
) fifo64to256 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.w8avail(fetch_en),
.we(fifo_we),
.wd(fml_di),
.ravail(pipe_stb_o),
.re(pipe_ack_i),
.rd(fetch_dat)
);
reg [1:0] bcount;
assign fifo_we = fml_ack | (|bcount);
always @(posedge sys_clk) begin
if(sys_rst)
bcount <= 2'd0;
else if(fml_ack)
bcount <= 2'd3;
else if(|bcount)
bcount <= bcount - 2'd1;
end
assign busy = pipe_stb_o | fml_stb | fifo_we;
endmodule
|
`default_nettype none
/*
* spdx-filecopyrighttext: 2017 clifford wolf, 2018 tim edwards
*
* strive - a full example soc using picorv32 in skywater s8
*
* copyright (c) 2017 clifford wolf <clifford@clifford.at>
* copyright (c) 2018 tim edwards <tim@efabless.com>
*
* permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* the software is provided "as is" and the author disclaims all warranties
* with regard to this software including all implied warranties of
* merchantability and fitness. in no event shall the author be liable for
* any special, direct, indirect, or consequential damages or any damages
* whatsoever resulting from loss of use, data or profits, whether in an
* action of contract, negligence or other tortious action, arising out of
* or in connection with the use or performance of this software.
*
* spdx-license-identifier: isc
*/
`timescale 1 ns / 1 ps
module timer_tb;
reg rstb;
reg clock;
reg power1, power2;
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef enable_sdf
initial begin
$sdf_annotate("../../../../sdf/dffram.sdf", uut.dffram_0 );
$sdf_annotate("../../../../sdf/mgmt_core.sdf", uut.core);
end
`endif
initial begin
$dumpfile("timer.vcd");
$dumpvars(0, timer_tb);
// repeat cycles of 1000 clock edges as needed to complete testbench
repeat (50) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef gl
$display ("monitor: timeout, test gpio (gl) failed");
`else
$display ("monitor: timeout, test gpio (rtl) failed");
`endif
$display("%c[0m",27);
$finish;
end
wire [127:0] la_output; // most of these are no-connects
wire [5:0] checkbits;
wire [31:0] countbits;
assign checkbits = la_output[37:32];
assign countbits = la_output[31:0];
// assign mprj_io[3] = 1'b1; // force csb high.
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire gpio;
// monitor
initial begin
wait(checkbits == 6'h0a);
`ifdef gl
$display("monitor: test timer (gl) started");
`else
$display("monitor: test timer (rtl) started");
`endif
/* add checks here */
wait(checkbits == 6'h01);
$display(" countbits = 0x%x (should be < 0xdcba9876)", countbits);
if(countbits >= 32'hdcba9876) begin
$display("monitor: test timer failed");
$finish;
end
// wait(checkbits == 6'h02);
// $display(" countbits = 0x%x (should be 0x19)", countbits);
// if(countbits !== 32'h19) begin
// $display("monitor: test timer failed");
// $finish;
// end
// wait(checkbits == 6'h03);
// $display(" countbits = %x (should be 0x0f)", countbits);
// if(countbits !== ((32'h0f) | (3'b100))) begin
// $display("monitor: test timer failed");
// $finish;
// end
// wait(checkbits == 6'h04);
// $display(" countbits = %x (should be 0x0f)", countbits);
// if(countbits !== ((32'h0f) | (3'b100))) begin
// $display("monitor: test timer failed");
// $finish;
// end
// wait(checkbits == 6'h05);
// $display(" countbits = %x (should be 0x12bc)", countbits);
// if(countbits !== 32'h12bc) begin
// $display("monitor: test timer failed");
// $finish;
// end
`ifdef gl
$display("monitor: test timer (gl) passed");
`else
$display("monitor: test timer (rtl) passed");
`endif
$finish;
end
initial begin
rstb <= 1'b0;
#1000;
rstb <= 1'b1; // release reset
end
initial begin // power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
always @(checkbits) begin
#1 $display("timer state = %b (%d)", countbits, countbits);
end
wire vdd3v3;
wire vdd1v8;
wire vss;
assign vdd3v3 = power1;
assign vdd1v8 = power2;
assign vss = 1'b0;
// these are the mappings of mprj_io gpio pads that are set to
// specific functions on startup:
//
// jtag = mgmt_gpio_io[0] (inout)
// sdo = mgmt_gpio_io[1] (output)
// sdi = mgmt_gpio_io[2] (input)
// csb = mgmt_gpio_io[3] (input)
// sck = mgmt_gpio_io[4] (input)
// ser_rx = mgmt_gpio_io[5] (input)
// ser_tx = mgmt_gpio_io[6] (output)
// irq = mgmt_gpio_io[7] (input)
mgmt_core_wrapper uut (
`ifdef use_power_pins
.vpwr (vdd1v8),
.vgnd (vss),
`endif
.core_clk (clock),
.core_rstn (rstb),
.debug_in(1'b0),
.debug_mode(),
.debug_oeb(),
.debug_out(),
.gpio_out_pad(gpio),
.gpio_in_pad(1'b0),
.gpio_inenb_pad(),
.gpio_mode0_pad(),
.gpio_mode1_pad(),
.gpio_outenb_pad(),
.la_output (la_output),
.la_iena(),
.la_input(128'b0),
.la_oenb(),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0_oeb(),
.flash_io1_oeb(),
.flash_io2_oeb(),
.flash_io3_oeb(),
.flash_io0_do(flash_io0),
.flash_io0_di(1'b0),
.flash_io1_do(),
.flash_io1_di(flash_io1),
.flash_io2_do(),
.flash_io2_di(1'b0),
.flash_io3_do(),
.flash_io3_di(1'b0),
.mprj_adr_o(),
.mprj_sel_o(),
.mprj_dat_i(32'b0),
.mprj_ack_i(1'b0),
.mprj_cyc_o(),
.mprj_stb_o(),
.mprj_wb_iena(),
.mprj_we_o(),
.hk_dat_i(32'b0),
.hk_ack_i(1'b0),
.hk_cyc_o(),
.hk_stb_o(),
.ser_rx(1'b1),
.ser_tx(),
.qspi_enabled(),
.spi_csb(),
.spi_enabled(),
.spi_sck(),
.spi_sdi(1'b0),
.spi_sdo(),
.spi_sdoenb(),
.sram_ro_csb(),
.sram_ro_clk(),
.sram_ro_addr(8'b0),
.sram_ro_data(),
.trap(),
.uart_enabled(),
.irq(6'b0),
.user_irq_ena()
);
spiflash #(
.filename("timer.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
`default_nettype wire
|
// copyright 2022 globalfoundries pdk authors
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
module gf180mcu_fd_sc_mcu9t5v0__aoi221_2( zn, c, b2, b1, a1, a2, vdd, vss );
input a1, a2, b1, b2, c;
inout vdd, vss;
output zn;
`ifdef functional // functional //
gf180mcu_fd_sc_mcu9t5v0__aoi221_2_func gf180mcu_fd_sc_mcu9t5v0__aoi221_2_behav_inst(.zn(zn),.c(c),.b2(b2),.b1(b1),.a1(a1),.a2(a2),.vdd(vdd),.vss(vss));
`else
gf180mcu_fd_sc_mcu9t5v0__aoi221_2_func gf180mcu_fd_sc_mcu9t5v0__aoi221_2_inst(.zn(zn),.c(c),.b2(b2),.b1(b1),.a1(a1),.a2(a2),.vdd(vdd),.vss(vss));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(b1===1'b0 && b2===1'b0)
// comb arc a1 --> zn
(a1 => zn) = (1.0,1.0);
if(b1===1'b0 && b2===1'b1)
// comb arc a1 --> zn
(a1 => zn) = (1.0,1.0);
if(b1===1'b1 && b2===1'b0)
// comb arc a1 --> zn
(a1 => zn) = (1.0,1.0);
ifnone
// comb arc a1 --> zn
(a1 => zn) = (1.0,1.0);
if(b1===1'b0 && b2===1'b0)
// comb arc a2 --> zn
(a2 => zn) = (1.0,1.0);
if(b1===1'b0 && b2===1'b1)
// comb arc a2 --> zn
(a2 => zn) = (1.0,1.0);
if(b1===1'b1 && b2===1'b0)
// comb arc a2 --> zn
(a2 => zn) = (1.0,1.0);
ifnone
// comb arc a2 --> zn
(a2 => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b0)
// comb arc b1 --> zn
(b1 => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b1)
// comb arc b1 --> zn
(b1 => zn) = (1.0,1.0);
if(a1===1'b1 && a2===1'b0)
// comb arc b1 --> zn
(b1 => zn) = (1.0,1.0);
ifnone
// comb arc b1 --> zn
(b1 => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b0)
// comb arc b2 --> zn
(b2 => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b1)
// comb arc b2 --> zn
(b2 => zn) = (1.0,1.0);
if(a1===1'b1 && a2===1'b0)
// comb arc b2 --> zn
(b2 => zn) = (1.0,1.0);
ifnone
// comb arc b2 --> zn
(b2 => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b0 && b1===1'b0 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b0 && b1===1'b0 && b2===1'b1)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b0 && b1===1'b1 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b1 && b1===1'b0 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b1 && b1===1'b0 && b2===1'b1)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b0 && a2===1'b1 && b1===1'b1 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b1 && a2===1'b0 && b1===1'b0 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b1 && a2===1'b0 && b1===1'b0 && b2===1'b1)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
if(a1===1'b1 && a2===1'b0 && b1===1'b1 && b2===1'b0)
// comb arc c --> zn
(c => zn) = (1.0,1.0);
ifnone
// comb arc c --> zn
(c => zn) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
|
// this program was cloned from: https://github.com/t-head-semi/openc910
// license: apache license 2.0
/*copyright 2019-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
// &modulebeg; @23
module ct_vfmau_lza_42(
lza_p0,
lza_p1,
lza_precod,
lza_vld
);
// &ports; @24
input [3:0] lza_precod;
output lza_p0;
output lza_p1;
output lza_vld;
// ®s; @25
// &wires; @26
wire lza_p0;
wire lza_p1;
wire [3:0] lza_precod;
wire lza_vld;
assign lza_vld = |lza_precod[3:0];
assign lza_p0 = !lza_precod[3] && (lza_precod[2] || !lza_precod[1]);
assign lza_p1 = !(lza_precod[2] || lza_precod[3]);
// &moduleend; @32
endmodule
|
// spdx-filecopyrighttext: 2020 efabless corporation
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
// spdx-license-identifier: apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_adder
*
* this is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
* analyzer, the wishbone bus, and the i/o pads.
*
* this project generates an integer count, which is output
* on the user area gpio pads (digital output only). the
* wishbone connection allows the project to be controlled
* (start and stop) from the management soc program.
*
* see the testbenches in directory "mprj_counter" for the
* example programs that drive this user project. the three
* testbenches are "io_ports", "la_test1", and "la_test2".
*
*-------------------------------------------------------------
*/
module user_adder #(
parameter bits = 32
)(
`ifdef use_power_pins
inout vccd1, // user area 1 1.8v supply
inout vssd1, // user area 1 digital ground
`endif
// wishbone slave ports (wb mi a)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// logic analyzer signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// ios
input [`mprj_io_pads-1:0] io_in,
output [`mprj_io_pads-1:0] io_out,
output [`mprj_io_pads-1:0] io_oeb,
// irq
output [2:0] irq
);
wire clk;
wire rst;
wire [`mprj_io_pads-1:0] io_in;
wire [`mprj_io_pads-1:0] io_out;
wire [`mprj_io_pads-1:0] io_oeb;
wire [31:0] rdata;
wire [31:0] wdata;
wire [bits-1:0] prev_result;
wire valid;
wire [3:0] wstrb;
wire [31:0] la_write;
// wb mi a
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
// io
assign io_out = prev_result;
assign io_oeb = {(`mprj_io_pads-1){rst}};
// irq
assign irq = 3'b000; // unused
// la
// place 'prev_result' data on last 32-bits of la
assign la_data_out = {{(127-bits){1'b0}}, prev_result};
// assuming la probes [63:32] are for controlling the prev_result register
assign la_write = ~la_oenb[63:32] & ~{bits{valid}};
// assuming la probes [65:64] are for controlling the prev_result clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
add_sub_accum #(
.bits(bits)
) add_sub_accum(
.clk(clk),
.reset(rst),
.ready(wbs_ack_o),
.valid(valid),
.wb_we(wbs_we_i),
.use_prev_result(la_data_in[94]),
.nadd_sub(la_data_in[95]),
.rdata(rdata),
.wdata(wbs_dat_i),
.la_write(la_write),
.la_input(la_data_in[63:32]),
.prev_result(prev_result)
);
endmodule
module add_sub_accum #(
parameter bits = 32
)(
input clk,
input reset,
input valid,
input wb_we, // wb write enable (use together with valid to determine read/write)
input use_prev_result, // boolean for using previous result in computation
input nadd_sub, // la probe 95 controls nadd_sub
input [bits-1:0] wdata, // packed data stream (upper 16-bits i_x; lower 16-bits i_y)
input [bits-1:0] la_write, // used for masking la_input of previous result of adder
input [bits-1:0] la_input, // used as the previous result of the adder
output ready, // acknowledge of wb slave (output)
output [bits-1:0] rdata, // sum/difference of adder/sub
output [bits-1:0] prev_result // previous result of add/sub
);
reg ready;
reg [bits-1:0] rdata;
reg [bits-1:0] wb_data_reg;
reg [bits-1:0] prev_result;
wire [bits-1:0] res_added;
wire [bits-1:0] res_subtracted;
assign res_added = use_prev_result ? (prev_result + wb_data_reg) : (wb_data_reg[31:16] + wb_data_reg[15:0]);
assign res_subtracted = use_prev_result ? (prev_result - wb_data_reg) : (wb_data_reg[31:16] - wb_data_reg[15:0]);
always @(posedge clk) begin
// reset outputs
if (reset) begin
ready <= 0;
rdata <= 0;
wb_data_reg <= 0;
prev_result <= 0;
end else begin
ready <= 1'b0;
// valid read/write to wb and ready (user defined)
if (valid && !ready) begin
ready <= 1'b1;
if (wb_we) begin
// read wb input into register
wb_data_reg <= wdata;
end else begin
// write output to wb. add/sub operation with previous result if desired
if (nadd_sub) begin
rdata <= res_subtracted;
end else begin
rdata <= res_added;
end
end
end else if (|la_write) begin
// fw control previous result. can store result from wb and can write prev_result
prev_result <= la_write & la_input;
end
end
end
endmodule
`default_nettype wire
|
/*copyright 2018-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
module cr_clic_sel(
// input
data_in,
sel_in_onehot,
// output
data_out
);
parameter data_width = 32;
parameter sel_num = 256;
input [data_width*sel_num-1:0] data_in;
input [sel_num-1:0] sel_in_onehot;
output [data_width-1:0] data_out;
wire [data_width-1:0] data_in_2d[sel_num-1:0];
wire [sel_num-1:0] data_in_2d_rev[data_width-1:0];
wire [data_width-1:0] data_out;
//==========================================================
// generate 2d signal
//==========================================================
genvar i;
genvar j;
generate
for (i = 0; i < sel_num; i = i+1) begin: expand
assign data_in_2d[i][data_width-1:0] = data_in[i*data_width+:data_width] & {data_width{sel_in_onehot[i]}};
end
endgenerate
//==========================================================
// reverse 2d signal
//==========================================================
generate
for (i = 0; i < sel_num; i = i+1) begin: reversei
for (j = 0; j < data_width; j = j+1) begin: reversej
assign data_in_2d_rev[j][i] = data_in_2d[i][j];
end
end
endgenerate
//==========================================================
// do or to sel
//==========================================================
generate
for (i = 0; i < data_width; i = i+1) begin: or_sel
assign data_out[i] = |data_in_2d_rev[i][sel_num-1:0];
end
endgenerate
endmodule
|
/*copyright 2019-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
// &modulebeg; @24
module ct_rtu_encode_96(
x_num,
x_num_expand
);
// &ports; @25
input [95:0] x_num_expand;
output [6 :0] x_num;
// ®s; @26
// &wires; @27
wire [6 :0] x_num;
wire [95:0] x_num_expand;
//==========================================================
// encode 96 bits one-hot number to 7 bits binary number
//==========================================================
assign x_num[6:0] =
{7{x_num_expand[0]}} & 7'd0
| {7{x_num_expand[1]}} & 7'd1
| {7{x_num_expand[2]}} & 7'd2
| {7{x_num_expand[3]}} & 7'd3
| {7{x_num_expand[4]}} & 7'd4
| {7{x_num_expand[5]}} & 7'd5
| {7{x_num_expand[6]}} & 7'd6
| {7{x_num_expand[7]}} & 7'd7
| {7{x_num_expand[8]}} & 7'd8
| {7{x_num_expand[9]}} & 7'd9
| {7{x_num_expand[10]}} & 7'd10
| {7{x_num_expand[11]}} & 7'd11
| {7{x_num_expand[12]}} & 7'd12
| {7{x_num_expand[13]}} & 7'd13
| {7{x_num_expand[14]}} & 7'd14
| {7{x_num_expand[15]}} & 7'd15
| {7{x_num_expand[16]}} & 7'd16
| {7{x_num_expand[17]}} & 7'd17
| {7{x_num_expand[18]}} & 7'd18
| {7{x_num_expand[19]}} & 7'd19
| {7{x_num_expand[20]}} & 7'd20
| {7{x_num_expand[21]}} & 7'd21
| {7{x_num_expand[22]}} & 7'd22
| {7{x_num_expand[23]}} & 7'd23
| {7{x_num_expand[24]}} & 7'd24
| {7{x_num_expand[25]}} & 7'd25
| {7{x_num_expand[26]}} & 7'd26
| {7{x_num_expand[27]}} & 7'd27
| {7{x_num_expand[28]}} & 7'd28
| {7{x_num_expand[29]}} & 7'd29
| {7{x_num_expand[30]}} & 7'd30
| {7{x_num_expand[31]}} & 7'd31
| {7{x_num_expand[32]}} & 7'd32
| {7{x_num_expand[33]}} & 7'd33
| {7{x_num_expand[34]}} & 7'd34
| {7{x_num_expand[35]}} & 7'd35
| {7{x_num_expand[36]}} & 7'd36
| {7{x_num_expand[37]}} & 7'd37
| {7{x_num_expand[38]}} & 7'd38
| {7{x_num_expand[39]}} & 7'd39
| {7{x_num_expand[40]}} & 7'd40
| {7{x_num_expand[41]}} & 7'd41
| {7{x_num_expand[42]}} & 7'd42
| {7{x_num_expand[43]}} & 7'd43
| {7{x_num_expand[44]}} & 7'd44
| {7{x_num_expand[45]}} & 7'd45
| {7{x_num_expand[46]}} & 7'd46
| {7{x_num_expand[47]}} & 7'd47
| {7{x_num_expand[48]}} & 7'd48
| {7{x_num_expand[49]}} & 7'd49
| {7{x_num_expand[50]}} & 7'd50
| {7{x_num_expand[51]}} & 7'd51
| {7{x_num_expand[52]}} & 7'd52
| {7{x_num_expand[53]}} & 7'd53
| {7{x_num_expand[54]}} & 7'd54
| {7{x_num_expand[55]}} & 7'd55
| {7{x_num_expand[56]}} & 7'd56
| {7{x_num_expand[57]}} & 7'd57
| {7{x_num_expand[58]}} & 7'd58
| {7{x_num_expand[59]}} & 7'd59
| {7{x_num_expand[60]}} & 7'd60
| {7{x_num_expand[61]}} & 7'd61
| {7{x_num_expand[62]}} & 7'd62
| {7{x_num_expand[63]}} & 7'd63
| {7{x_num_expand[64]}} & 7'd64
| {7{x_num_expand[65]}} & 7'd65
| {7{x_num_expand[66]}} & 7'd66
| {7{x_num_expand[67]}} & 7'd67
| {7{x_num_expand[68]}} & 7'd68
| {7{x_num_expand[69]}} & 7'd69
| {7{x_num_expand[70]}} & 7'd70
| {7{x_num_expand[71]}} & 7'd71
| {7{x_num_expand[72]}} & 7'd72
| {7{x_num_expand[73]}} & 7'd73
| {7{x_num_expand[74]}} & 7'd74
| {7{x_num_expand[75]}} & 7'd75
| {7{x_num_expand[76]}} & 7'd76
| {7{x_num_expand[77]}} & 7'd77
| {7{x_num_expand[78]}} & 7'd78
| {7{x_num_expand[79]}} & 7'd79
| {7{x_num_expand[80]}} & 7'd80
| {7{x_num_expand[81]}} & 7'd81
| {7{x_num_expand[82]}} & 7'd82
| {7{x_num_expand[83]}} & 7'd83
| {7{x_num_expand[84]}} & 7'd84
| {7{x_num_expand[85]}} & 7'd85
| {7{x_num_expand[86]}} & 7'd86
| {7{x_num_expand[87]}} & 7'd87
| {7{x_num_expand[88]}} & 7'd88
| {7{x_num_expand[89]}} & 7'd89
| {7{x_num_expand[90]}} & 7'd90
| {7{x_num_expand[91]}} & 7'd91
| {7{x_num_expand[92]}} & 7'd92
| {7{x_num_expand[93]}} & 7'd93
| {7{x_num_expand[94]}} & 7'd94
| {7{x_num_expand[95]}} & 7'd95;
// &moduleend; @130
endmodule
|
/*copyright 2020-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
// &modulebeg; @22
module pa_spsram_1024x36(
a,
cen,
clk,
d,
gwen,
q,
wen
);
// &ports; @23
input [9 :0] a;
input cen;
input clk;
input [35:0] d;
input gwen;
input [35:0] wen;
output [35:0] q;
// ®s; @24
// &wires; @25
wire [9 :0] a;
wire cen;
wire clk;
wire [35:0] d;
wire gwen;
wire [35:0] q;
wire [35:0] wen;
//**********************************************************
// parameter definition
//**********************************************************
parameter addr_width = 10;
parameter data_width = 36;
parameter we_width = 36;
// &force("bus","q",data_width-1,0); @34
// &force("bus","wen",we_width-1,0); @35
// &force("bus","a",addr_width-1,0); @36
// &force("bus","d",data_width-1,0); @37
// //********************************************************
// //* fpga memory *
// //********************************************************
// &instance("pa_f_spsram_1024x36"); @43
pa_f_spsram_1024x36 x_pa_f_spsram_1024x36 (
.a (a ),
.cen (cen ),
.clk (clk ),
.d (d ),
.gwen (gwen),
.q (q ),
.wen (wen )
);
// &instance("pa_tsmc_spsram_1024x36"); @49
// &moduleend; @65
endmodule
|
/**
* copyright 2020 google llc
*
* licensed under the apache license, version 2.0 (the "license");
* you may not use this file except in compliance with the license.
* you may obtain a copy of the license at
*
* https://www.apache.org/licenses/license-2.0
*
* unless required by applicable law or agreed to in writing, software
* distributed under the license is distributed on an "as is" basis,
* without warranties or conditions of any kind, either express or implied.
* see the license for the specific language governing permissions and
* limitations under the license.
*/
module top(
input clk100mhz,
output [3:0] jd,
output [3:0] led,
input [3:0] sw
);
// set up the signal path to link the speaker to the
// pwm generator.
parameter clkspeed = 100000000;
wire speaker;
reg [4:0] level; // only using 5 of the 7 bits will lower the volume by 4x
pwm spwm(.clk(clk100mhz), .pwm_in(level), .pwm_out(speaker));
// create a 440hz square wave signal
parameter clkdivider = clkspeed/440/2;
reg [16:0] counter;
always @(posedge clk100mhz) if(counter==0) counter <= clkdivider-1; else counter <= counter-1;
always @(posedge clk100mhz) if(counter==0) level <= ~level;
assign jd[0] = speaker; // connect speaker wire to output
assign jd[1] = 1; // gain control. set to 1 (low gain)
assign jd[3] = sw[3]; // turn amp on / off
// leds to help with debugging
assign led[0] = speaker; // current wave form
endmodule
module pwm(
input clk,
input [7:0] pwm_in,
output pwm_out
);
// making the cnt register an extra bit wide will reduce
// the volume by 50%, as the maximum duty cycle will only
// be 50%.
reg [8:0] cnt = 0;
always @(posedge clk) cnt <= cnt + 1'b1;
assign pwm_out = (pwm_in > cnt);
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
/*
* <-- pr4m0d -->
* https://pram0d.com
* https://twitter.com/pr4m0d
* https://github.com/psomashekar
*
* copyright (c) 2022 pramod somashekar
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, either version 3 of the license, or
* (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <https://www.gnu.org/licenses/>.
*/
module raizing_colmix (
input clk,
input clk96,
input reset,
input reset96,
input pixel_cen,
input [10:0] extratext_pixel,
input [14:0] scroll0_pixel,
input [14:0] scroll1_pixel,
input [14:0] scroll2_pixel,
input [14:0] obj_pixel,
output reg [10:0] final_pixel,
input active
);
wire [10:0] blank_pixel = 11'd0;
wire [4:0] prio = {extratext_pixel>0, obj_pixel[10:0]>0, scroll2_pixel[10:0]>0, scroll1_pixel[10:0]>0, scroll0_pixel[10:0]>0};
integer i;
function [10:0] pixel_priority_mux;
input [4:0] pri;
input [10:0] et;
input [14:0] obj,scr2,scr1,scr0;
begin
pixel_priority_mux = blank_pixel;
for(i=0;i<16;i=i+1) begin
if(pri[0] && scr0[14:11] == i[3:0]) pixel_priority_mux = scr0[10:0];
if(pri[1] && scr1[14:11] == i[3:0]) pixel_priority_mux = scr1[10:0];
if(pri[2] && scr2[14:11] == i[3:0]) pixel_priority_mux = scr2[10:0];
if(pri[3] && obj[14:11] == i[3:0]) pixel_priority_mux = obj[10:0];
end
// if(pri[0]) pixel_priority_mux = scr0[10:0];
// if(pri[1]) pixel_priority_mux = scr1[10:0];
// if(pri[2]) pixel_priority_mux = scr2[10:0];
// if(pri[3]) pixel_priority_mux = obj[10:0];
//remux
// if(pri[3] && obj[14:11] >= scr0[14:11] && obj[14:11] >= scr1[14:11] && obj[14:11] >= scr2[14:11]) pixel_priority_mux = obj[10:0];
// else begin
// if(pri[0] && scr0[14:11] > scr1[14:11] && scr0[14:11] > scr2[14:11] && scr0 > obj[14:11]) pixel_priority_mux = scr0[10:0];
// if(pri[1] && scr1[14:11] > scr0[14:11] && scr1[14:11] > scr2[14:11] && scr1 > obj[14:11]) pixel_priority_mux = scr1[10:0];
// if(pri[2] && scr2[14:11] > scr0[14:11] && scr2[14:11] > scr1[14:11] && scr2 > obj[14:11]) pixel_priority_mux = scr2[10:0];
// end
// if(pri[3]) pixel_priority_mux = obj[10:0];
if(pri[4]) pixel_priority_mux = et;
// $display("%h", pixel_priority_mux);
end
endfunction
always @(posedge clk96) begin
if(pixel_cen) begin
if(prio==5'b00000) begin //no layer has pixels in this dot, it will be set to clear frame in palette
final_pixel<=blank_pixel;
end else begin
final_pixel<=pixel_priority_mux(prio, extratext_pixel, obj_pixel, scroll2_pixel, scroll1_pixel, scroll0_pixel);
end
end
end
endmodule
|
/*
* copyright (c) 2023 matthew harlum <matt@harlum.net>
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation; version 2.
*
* this program is distributed in the hope that it will be useful, but
* without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose.
* see the gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program; if not, write to the free software foundation,
* inc., 51 franklin street, fifth floor, boston, ma 02110-1301, usa.
*/
module autoconfig (
input [23:1] addr,
input as_n,
input uds_n,
input clk,
input rw,
input [3:0] din,
input reset_n,
input ide_enabled,
input cfgin_n,
output cfgout_n,
output ide_access,
output autoconfig_cycle,
output reg [3:0] dout,
output reg dtack
);
// autoconfig
localparam [15:0] mfg_id = 16'd5194;
localparam [7:0] prod_id = 8'd7;
localparam [31:0] serial = `serial;
reg ide_configured = 0;
reg [7:0] ide_base;
reg cfgout;
reg shutup;
assign cfgout_n = !cfgout;
assign autoconfig_cycle = (addr[23:16] == 8'he8) && ~cfgin_n && !cfgout;
// these need to be registered at the end of a bus cycle
always @(posedge as_n or negedge reset_n) begin
if (!reset_n) begin
cfgout <= 0;
end else begin
cfgout <= ide_configured || shutup;
end
end
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
dout <= 'b0;
dtack <= 0;
ide_base <= 8'b0;
ide_configured <= 0;
shutup <= 0;
end else if (autoconfig_cycle && rw && !as_n) begin
dtack <= 1;
case (addr[8:1])
8'h00: dout <= {3'b110, ide_enabled}; // io / read from autoboot rom
`ifdef size_64k
8'h01: dout <= 4'b0001; // size:64k
`else
8'h01: dout <= 4'b0010; // size:128k
`endif
8'h02: dout <= ~prod_id[7:4]; // product number
8'h03: dout <= ~prod_id[3:0]; // product number
8'h04: dout <= ~4'b0000;
8'h05: dout <= ~4'b0000;
8'h08: dout <= ~mfg_id[15:12]; // manufacturer id
8'h09: dout <= ~mfg_id[11:8]; // manufacturer id
8'h0a: dout <= ~mfg_id[7:4]; // manufacturer id
8'h0b: dout <= ~mfg_id[3:0]; // manufacturer id
8'h0c: dout <= ~serial[31:28]; // serial number
8'h0d: dout <= ~serial[27:24]; // serial number
8'h0e: dout <= ~serial[23:20]; // serial number
8'h0f: dout <= ~serial[19:16]; // serial number
8'h10: dout <= ~serial[15:12]; // serial number
8'h11: dout <= ~serial[11:8]; // serial number
8'h12: dout <= ~serial[7:4]; // serial number
8'h13: dout <= ~serial[3:0]; // serial number
8'h14: dout <= ~4'h0; // rom offset high byte high nibble
8'h15: dout <= ~4'h0; // rom offset high byte low nibble
8'h16: dout <= ~4'h0; // rom offset low byte high nibble
8'h17: dout <= ~4'h8; // rom offset low byte low nibble
8'h20: dout <= 4'b0;
8'h21: dout <= 4'b0;
default: dout <= 4'hf;
endcase
end else if (autoconfig_cycle && !rw && !as_n && !uds_n && !dtack) begin
dtack <= 1;
if (addr[8:1] == 8'h26 && !shutup) begin
// we've been told to shut up (not enough space)
shutup <= 1;
end else if (addr[8:1] == 8'h25 && !ide_configured) begin
ide_base[3:0] <= din[3:0];
end else if (addr[8:1] == 8'h24 && !ide_configured) begin
ide_base[7:4] <= din[3:0];
ide_configured <= 1'b1;
end
end else if (as_n) begin
dtack <= 0;
end
end
`ifdef size_64k
assign ide_access = ((addr[23:16] == ide_base) && ide_configured && cfgout);
`else
assign ide_access = ((addr[23:17] == ide_base[7:1]) && ide_configured && cfgout);
`endif
endmodule
|
/*
* milkymist soc
* copyright (c) 2007, 2008, 2009, 2010 sebastien bourdeauducq
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, version 3 of the license.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iddr32 #(
parameter ddr_alignment = "c0",
parameter init_q0 = 1'b0,
parameter init_q1 = 1'b0,
parameter srtype = "async"
) (
output [31:0] q0,
output [31:0] q1,
input c0,
input c1,
input ce,
input [31:0] d,
input r,
input s
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr0 (
.q0(q0[0]),
.q1(q1[0]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[0]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr1 (
.q0(q0[1]),
.q1(q1[1]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[1]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr2 (
.q0(q0[2]),
.q1(q1[2]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[2]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr3 (
.q0(q0[3]),
.q1(q1[3]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[3]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr4 (
.q0(q0[4]),
.q1(q1[4]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[4]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr5 (
.q0(q0[5]),
.q1(q1[5]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[5]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr6 (
.q0(q0[6]),
.q1(q1[6]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[6]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr7 (
.q0(q0[7]),
.q1(q1[7]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[7]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr8 (
.q0(q0[8]),
.q1(q1[8]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[8]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr9 (
.q0(q0[9]),
.q1(q1[9]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[9]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr10 (
.q0(q0[10]),
.q1(q1[10]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[10]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr11 (
.q0(q0[11]),
.q1(q1[11]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[11]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr12 (
.q0(q0[12]),
.q1(q1[12]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[12]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr13 (
.q0(q0[13]),
.q1(q1[13]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[13]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr14 (
.q0(q0[14]),
.q1(q1[14]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[14]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr15 (
.q0(q0[15]),
.q1(q1[15]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[15]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr16 (
.q0(q0[16]),
.q1(q1[16]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[16]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr17 (
.q0(q0[17]),
.q1(q1[17]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[17]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr18 (
.q0(q0[18]),
.q1(q1[18]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[18]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr19 (
.q0(q0[19]),
.q1(q1[19]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[19]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr20 (
.q0(q0[20]),
.q1(q1[20]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[20]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr21 (
.q0(q0[21]),
.q1(q1[21]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[21]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr22 (
.q0(q0[22]),
.q1(q1[22]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[22]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr23 (
.q0(q0[23]),
.q1(q1[23]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[23]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr24 (
.q0(q0[24]),
.q1(q1[24]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[24]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr25 (
.q0(q0[25]),
.q1(q1[25]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[25]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr26 (
.q0(q0[26]),
.q1(q1[26]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[26]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr27 (
.q0(q0[27]),
.q1(q1[27]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[27]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr28 (
.q0(q0[28]),
.q1(q1[28]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[28]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr29 (
.q0(q0[29]),
.q1(q1[29]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[29]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr30 (
.q0(q0[30]),
.q1(q1[30]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[30]),
.r(r),
.s(s)
);
iddr2 #(
.ddr_alignment(ddr_alignment),
.init_q0(init_q0),
.init_q1(init_q1),
.srtype(srtype)
) iddr31 (
.q0(q0[31]),
.q1(q1[31]),
.c0(c0),
.c1(c1),
.ce(ce),
.d(d[31]),
.r(r),
.s(s)
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <support@dreamsourcelab.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module sample(
// -- clock & reset
input core_clk,
input int_clk,
input int_clk_2x,
input ext_clk,
output sample_clk,
input core_rst,
input sample_rst,
// --
input sample_en,
input ext_clk_mode,
input test_mode,
input ext_test_mode,
input falling_mode,
input half_mode,
input wireless_mode,
input quarter_mode,
input cons_mode,
input [23:0] sample_divider,
input ext_trig_in,
// --
output ledn,
input [15:0] ext_data,
output [15:0] sample_data,
output reg sample_valid
);
// --
// internal signals definition
// --
wire [15:0] pos_sync_data;
wire [15:0] neg_sync_data;
reg [15:0] pos_data;
reg [15:0] neg_data;
reg [15:0] pos_data_1T;
reg [15:0] neg_data_1T;
reg [15:0] pos_data_2T;
reg [15:0] neg_data_2T;
reg [15:0] pos_data_final;
reg [15:0] neg_data_final;
reg sample_en_1T;
reg [23:0] sample_cnt;
wire [23:0] sample_cnt_nxt;
reg sample_rd;
wire sample_rd_nxt;
wire sample_valid_nxt;
// --
// Select between internal and external sampling clock...
// --
//wire sample_clk;
wire int_clk_mux;
BUFGMUX BUFGMUX_sample_2x(
.O(int_clk_mux), // Clock MUX output
.I0(int_clk), // Clock0 input
.I1(int_clk_2x), // Clock1 input
.S(quarter_mode)
);
BUFGMUX BUFGMUX_sample(
.O(sample_clk), // Clock MUX output
.I0(int_clk_mux), // Clock0 input
.I1(ext_clk), // Clock1 input
.S(ext_clk_mode)
);
// --
// Synchronize ext_data guarantees use of iob ff on spartan 3
// --
IDDR2 ext_sync0(.Q0(pos_sync_data[0]), .Q1(neg_sync_data[0]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[0]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync1(.Q0(pos_sync_data[1]), .Q1(neg_sync_data[1]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[1]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync2(.Q0(pos_sync_data[2]), .Q1(neg_sync_data[2]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[2]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync3(.Q0(pos_sync_data[3]), .Q1(neg_sync_data[3]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[3]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync4(.Q0(pos_sync_data[4]), .Q1(neg_sync_data[4]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[4]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync5(.Q0(pos_sync_data[5]), .Q1(neg_sync_data[5]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[5]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync6(.Q0(pos_sync_data[6]), .Q1(neg_sync_data[6]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[6]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync7(.Q0(pos_sync_data[7]), .Q1(neg_sync_data[7]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[7]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync8(.Q0(pos_sync_data[8]), .Q1(neg_sync_data[8]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[8]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync9(.Q0(pos_sync_data[9]), .Q1(neg_sync_data[9]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[9]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync10(.Q0(pos_sync_data[10]), .Q1(neg_sync_data[10]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[10]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync11(.Q0(pos_sync_data[11]), .Q1(neg_sync_data[11]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[11]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync12(.Q0(pos_sync_data[12]), .Q1(neg_sync_data[12]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[12]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync13(.Q0(pos_sync_data[13]), .Q1(neg_sync_data[13]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[13]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync14(.Q0(pos_sync_data[14]), .Q1(neg_sync_data[14]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[14]), .R(1'b0), .S(1'b0));
IDDR2 ext_sync15(.Q0(pos_sync_data[15]), .Q1(neg_sync_data[15]), .C0(sample_clk), .C1(~sample_clk), .CE(1'b1), .D(ext_data[15]), .R(1'b0), .S(1'b0));
always @(posedge sample_clk or posedge sample_rst)
begin
if (sample_rst)
pos_data <= `D 16'b0;
else
// pos_data <= `D half_mode ? ext_data :
// cons_mode ? {pos_sync_data[15:8], neg_sync_data[7:0]} : pos_sync_data;
pos_data <= `D ext_clk_mode ? ext_data : pos_sync_data;
end
always @(negedge sample_clk or posedge sample_rst)
begin
if (sample_rst)
neg_data <= `D 16'b0;
else
neg_data <= `D neg_sync_data;
end
always @(posedge sample_clk)
begin
pos_data_1T <= `D pos_data;
pos_data_2T <= `D pos_data_1T;
// pos_data_final <= `D (((pos_data ^ pos_data_1T) | (pos_data_1T ^ pos_data_2T)) & pos_data_final) |
// (~((pos_data ^ pos_data_1T) | (pos_data_1T ^ pos_data_2T))& pos_data_1T);
pos_data_final <= `D ((pos_data ^ pos_data_1T) & pos_data_final) |
(~(pos_data ^ pos_data_1T) & pos_data_1T);
end
always @(negedge sample_clk or posedge sample_rst)
begin
neg_data_1T <= `D neg_data;
neg_data_2T <= `D neg_data_1T;
// neg_data_final <= `D (((neg_data ^ neg_data_1T) | (neg_data_1T ^ neg_data_2T)) & neg_data_final) |
// (~((neg_data ^ neg_data_1T) | (neg_data_1T ^ neg_data_2T))& neg_data_1T);
neg_data_final <= `D ((neg_data ^ neg_data_1T) & neg_data_final) |
(~(neg_data ^ neg_data_1T) & neg_data_1T);
end
// --
// sample data mux: external/test data
// --
wire [15:0] pre_data;
reg [15:0] half_data;
wire [15:0] half_data_nxt;
reg [15:0] neg_data_pos;
//assign half_data_nxt = {2{(((neg_data_pos[7:0] ^ pos_data[7:0]) | (pos_data[7:0] ^ pos_data_1T[7:0])) & half_data[7:0]) |
// (~((neg_data_pos[7:0] ^ pos_data[7:0]) | (pos_data[7:0] ^ pos_data_1T[7:0])) & pos_data[7:0])}};
//assign half_data_nxt = {neg_data[7:0], pos_data[7:0]};
assign half_data_nxt = wireless_mode ? {neg_data[7:0], pos_data[7:0]} :
{2{((neg_data_pos[7:0] ^ pos_data[7:0]) & half_data[7:0]) |
(~(neg_data_pos[7:0] ^ pos_data[7:0]) & pos_data[7:0])}};
always @(posedge sample_clk or posedge sample_rst)
begin
if (sample_rst) begin
half_data <= `D 16'b0;
end else begin
half_data <= `D half_data_nxt;
end
end
always @(posedge sample_clk)
begin
neg_data_pos <= `D neg_data;
end
reg [15:0] quarter_data;
wire [15:0] quarter_data_nxt;
//assign quarter_data_nxt[15:8] = quarter_data[7:0];
//assign quarter_data_nxt[7:0] = {2{(((neg_data_pos[3:0] ^ pos_data[3:0]) | (pos_data[3:0] ^ pos_data_1T[3:0])) & quarter_data[3:0]) |
// (~((neg_data_pos[3:0] ^ pos_data[3:0]) | (pos_data[3:0] ^ pos_data_1T[3:0])) & pos_data[3:0])}};
//assign quarter_data_nxt = {quarter_data[7:0], neg_data[3:0], pos_data[3:0]};
assign quarter_data_nxt[15:8] = quarter_data[7:0];
assign quarter_data_nxt[7:0] = {2{((neg_data_pos[3:0] ^ pos_data[3:0]) & quarter_data[3:0]) |
(~(neg_data_pos[3:0] ^ pos_data[3:0]) & pos_data[3:0])}};
always @(posedge sample_clk or posedge sample_rst)
begin
if (sample_rst) begin
quarter_data <= `D 16'b0;
end else begin
quarter_data <= `D quarter_data_nxt;
end
end
reg quarter_valid;
wire quarter_valid_nxt;
assign quarter_valid_nxt = ~quarter_valid;
always @(posedge sample_clk or posedge sample_rst)
begin
if (sample_rst)
quarter_valid <= `D 1'b0;
else
quarter_valid <= `D quarter_valid_nxt;
end
// --
// Internal test mode. a 16-bit test pattern
// --
wire rempty;
wire pempty;
wire wfull;
reg stable_valid;
wire stable_valid_nxt;
reg [15:0] test_data;
wire [15:0] test_data_nxt;
assign test_data_nxt = (wfull | (quarter_mode & ~quarter_valid)) ? test_data :
~sample_en ? 16'b0 : test_data + 1'b1;
always @(posedge sample_clk or posedge sample_rst)
begin
if (sample_rst)
test_data <= `D 16'b0;
else
test_data <= `D test_data_nxt;
end
assign pre_data = test_mode ? test_data :
half_mode ? half_data :
quarter_mode ? quarter_data :
(ext_clk_mode & falling_mode) ? neg_data :
(ext_clk_mode | cons_mode) ? pos_data :
(falling_mode) ? neg_data_final : pos_data_final;
//assign pre_data = test_mode ? test_data :
// half_mode ? half_data :
// quarter_mode ? quarter_data :
// (ext_clk_mode & falling_mode) ? neg_data : pos_data;
// --
// Transfer from input clock (whatever it may be) to the core clock
// --
assign stable_valid_nxt = ~pempty;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
stable_valid <= `D 1'b0;
else
stable_valid <= `D stable_valid_nxt;
end
//async_fifo async_fifo(
// .clkw(sample_clk),
// .rstw(sample_rst),
// .wfull(),
// .wr_en(sample_en),
// .wdata(pre_data),
//
// .clkr(core_clk),
// .rstr(core_rst),
// .rd_en(1'b1),
// .rempty(rempty),
// .rdata(sample_data)
//);
wire [15:0] sync_dout;
wire sample_wr_en = quarter_mode ? sample_en & quarter_valid : sample_en;
asyncfifo asyncfifo(
.wr_clk(sample_clk), // input wr_clk
.wr_rst(sample_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din(pre_data), // input [15 : 0] din
.wr_en(sample_wr_en), // input wr_en
.rd_en(sample_rd), // input rd_en
.dout(sample_data), // output [15 : 0] dout
.full(wfull), // output full
.empty(rempty), // output empty
.prog_empty(pempty) // output prog_empty
);
// --
// Sample data according to various sample rate
// --
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
sample_en_1T <= `D 1'b0;
else
sample_en_1T <= `D sample_en;
end
assign sample_cnt_nxt = ~sample_en ? 24'b0 :
(~ext_clk_mode & sample_en & ~sample_en_1T) ? sample_divider :
(~ext_clk_mode & (sample_cnt == 24'b1)) ? sample_divider :
(~ext_clk_mode) ? sample_cnt - 1'b1 : sample_cnt;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
sample_cnt <= `D 24'b0;
else
sample_cnt <= `D sample_cnt_nxt;
end
// --
// sample data out
// --
//assign sample_rd_nxt = ext_clk_mode ? stable_valid : (~rempty & sample_cnt_nxt == 24'b1);
assign sample_rd_nxt = stable_valid;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
sample_rd <= `D 1'b0;
else
sample_rd <= `D sample_rd_nxt;
end
assign sample_valid_nxt = sample_rd & (ext_clk_mode | (sample_cnt_nxt == 24'b1));
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
sample_valid <= `D 1'b0;
else
sample_valid <= `D sample_valid_nxt;
end
//always @(posedge core_clk or posedge core_rst)
//begin
// if (core_rst)
// sample_data <= `D 16'b0;
// else
// sample_data <= `D sync_dout;
//end
// --
// LED control
// --
assign ledn = ext_test_mode ? ~test_ledn_cnt[25] : ~ledn_cnt[19];
reg [19:0] ledn_cnt;
wire [19:0] ledn_cnt_nxt;
assign ledn_cnt_nxt = ~sample_en ? 20'hfffff :
sample_valid ? ledn_cnt + 1 + (sample_divider >> 1) : ledn_cnt;
always @(posedge core_clk)
begin
ledn_cnt <= `D ledn_cnt_nxt;
end
reg [25:0] test_ledn_cnt;
wire [25:0] test_ledn_cnt_nxt;
assign test_ledn_cnt_nxt = test_ledn_cnt + 1;
always @(posedge ext_clk)
begin
test_ledn_cnt <= `D test_ledn_cnt_nxt;
end
endmodule
|
/*
* this ip is the atmega 8bit timer simulation.
*
* copyright (c) 2020 iulian gheorghiu (morgoth@devboard.tech)
*
* this program is free software; you can redistribute it and/or
* modify it under the terms of the gnu general public license
* as published by the free software foundation; either version 2
* of the license, or (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program; if not, write to the free software
* foundation, inc., 51 franklin street, fifth floor, boston, ma 02110-1301, usa.
*/
`timescale 1ns / 1ps
module atmega_tim_8bit_sim(
);
reg clk = 1;
reg rst = 1;
always #(1) clk <= ~clk;
reg [5:0]io_addr = 0;
reg [7:0]io_bus_in = 0;
reg io_wr;
reg io_rd;
reg [7:0]data_addr = 0;
reg [7:0]data_bus_in = 0;
wire [7:0]data_bus_out;
reg data_wr;
reg data_rd;
wire tov_int;
reg tov_int_rst;
wire ocra_int;
reg ocra_int_rst;
wire ocrb_int;
reg ocrb_int_rst;
wire oca;
wire ocb;
initial begin
io_addr <= 0;
io_bus_in <= 8'h00;
io_rd <= 1'b0;
io_wr <= 1'b0;
tov_int_rst <= 1'b0;
ocra_int_rst <= 1'b0;
ocrb_int_rst <= 1'b0;
wait(clk);
wait(~clk);
rst = 1;
wait(~clk);
wait(clk);
#0.1; // insert real logick delay because, always signals arrive after clock.
rst = 0;
#10;
io_addr <= 'h27; // ocra
io_bus_in <= 8'h1f;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
io_addr <= 'h28; // ocrb
io_bus_in <= 8'h0f;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
data_addr <= 'h6e; // timsk
data_bus_in <= 8'b00000111;
data_wr <= 1'b1;
#2;
data_wr <= 1'b0;
#4;
io_addr <= 'h24; // tccra
io_bus_in <= 8'b10100001;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
io_addr <= 'h25; // tccrb
io_bus_in <= 8'b00000010;
io_wr <= 1'b1;
#2;
io_wr <= 1'b0;
#4;
while(1)
begin
if(tov_int)
begin
#2;
tov_int_rst <= 1'b1;
#2;
tov_int_rst <= 1'b0;
end
if(ocra_int)
begin
#2;
ocra_int_rst <= 1'b1;
#2;
ocra_int_rst <= 1'b0;
end
if(ocrb_int)
begin
#2;
ocrb_int_rst <= 1'b1;
#2;
ocrb_int_rst <= 1'b0;
end
#2;
end
end
wire clk8;
wire clk64;
wire clk256;
wire clk1024;
tim_013_prescaller tim_013_prescaller_inst(
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024)
);
wire [7:0]io_tim0_d_out;
wire [7:0]dat_tim0_d_out;
atmega_tim_8bit # (
.platform("xilinx"),
.use_ocrb("true"),
.bus_addr_io_len(6),
.bus_addr_data_len(8),
.gtccr_addr('h23),
.tccra_addr('h24),
.tccrb_addr('h25),
.tcnt_addr('h26),
.ocra_addr('h27),
.ocrb_addr('h28),
.timsk_addr('h6e),
.tifr_addr('h15),
.dinamic_baudrate("true"),
.baudrate_divider(1)
)tim_0_sim(
.rst(rst),
.clk(clk),
.clk8(clk8),
.clk64(clk64),
.clk256(clk256),
.clk1024(clk1024),
.addr_io(io_addr),
.wr_io(io_wr),
.rd_io(io_rd),
.bus_io_in(io_bus_in),
.bus_io_out(io_tim0_d_out),
.addr_dat(data_addr[7:0]),
.wr_dat(data_wr),
.rd_dat(data_rd),
.bus_dat_in(data_bus_in),
.bus_dat_out(dat_tim0_d_out),
.tov_int(tov_int),
.tov_int_rst(tov_int_rst),
.ocra_int(ocra_int),
.ocra_int_rst(ocra_int_rst),
.ocrb_int(ocrb_int),
.ocrb_int_rst(ocrb_int_rst),
.t(),
.oca(oca),
.ocb(ocb),
.oca_io_connect(),
.ocb_io_connect()
);
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// manages ZX-bus IORQ-IORQGE stuff and free bus content
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zbus(
input iorq_n,
input rd_n,
input wr_n,
input m1_n,
output iorq1_n,
output iorq2_n,
input iorqge1,
input iorqge2,
input porthit,
output drive_ff
);
assign iorq1_n = iorq_n | porthit;
assign iorq2_n = iorq1_n | iorqge1;
assign drive_ff = ( (~(iorq2_n|iorqge2)) & (~rd_n) ) | (~(m1_n|iorq_n));
endmodule
|
/*
copyright 2020 mohamed shalan
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at:
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
/*
a testbench for example-3.v (a simple ahb system with 4 slaves)
*/
`include "include/ahb_util.vh"
module example_3_tb;
reg hclk;
reg hresetn;
reg [31:0] haddr;
reg [1:0] htrans;
reg [2:0] hsize;
reg hwrite;
reg [31:0] hwdata;
wire hready;
wire [31:0] hrdata;
ahb_sys duv (
.hclk(hclk),
.hresetn(hresetn),
.haddr(haddr),
.htrans(htrans),
.hsize(hsize),
.hwrite(hwrite),
.hwdata(hwdata),
.hready(hready),
.hrdata(hrdata)
);
`include "ahb_tasks.vh"
always #5 hclk = !hclk;
initial begin
$dumpfile("example_3_tb.vcd");
$dumpvars;
# 1_500 $finish;
end
// reset
initial begin
hclk = 0;
hresetn = 1;
//hready = 1;
#10;
@(posedge hclk);
hresetn = 0;
#100;
@(posedge hclk);
hresetn = 1;
end
// text case
reg [31:0] rdata;
initial begin
#1000;
ahb_write_word(32'h4000_0020, 32'h000d_eeee);
#25;
ahb_write_word(32'h4200_0020, 32'h000d_dddd);
#25;
ahb_read_word(32'h4000_0020, rdata);
#25;
if(rdata == 32'h000d_eeee) $display("test 1 passed"); else $display("test 1 failed");
#25;
ahb_read_word(32'h4200_0020, rdata);
#25;
if(rdata == 32'h000d_dddd) $display("test 2 passed"); else $display("test 2 failed");
end
endmodule
|
/*
* hififo: harmon instruments pci express to fifo
* copyright (c) 2014 harmon instruments, llc
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, either version 3 of the license, or
* (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/
*/
/*
* first word fall through fifo
* copyright 2014 harmon instruments
* author: darrell harmon
*/
module fwft_fifo
(
input reset, // async
input i_clock,
input [nbits-1:0] i_data,
input i_valid,
output i_ready,
input o_clock,
input o_read,
output [nbits-1:0] o_data,
output o_valid,
output o_almost_empty
);
parameter nbits = 64; // 1 to 72 valid
parameter full_offset = 9'h080;
`ifdef sim
// this is for simulation only!!!
reg [nbits-1:0] fifo[0:511];
reg [nbits-1:0] a_d, b_d;
reg a_v, b_v;
wire a_cken = (p_out != p_in) && (~a_v | ~b_v | c_cken);
wire b_cken = a_v && (~b_v | c_cken);
wire c_cken = o_read;
reg [8:0] p_in, p_out;
wire [8:0] count = p_in - p_out;
assign o_valid = b_v;
assign o_data = b_d;
assign i_ready = (count < 384);
assign o_almost_empty = ((count + a_v + b_v) < 16);
always @ (posedge i_clock)
begin
if(i_valid)
fifo[p_in] <= i_data;
p_in <= reset ? 1'b0 : p_in + i_valid;
end
always @ (posedge o_clock)
begin
p_out <= reset ? 1'b0 : p_out + a_cken;
a_v <= reset ? 1'b0 : a_cken | (a_v && ~b_cken);
if(a_cken)
a_d <= fifo[p_out];
b_v <= reset ? 1'b0 : b_cken | (b_v && ~c_cken);
if(b_cken)
b_d <= a_d;
end
`else
wire empty, almostfull;
assign i_ready = ~almostfull;
assign o_valid = ~empty;
generate
if(nbits>36) begin : fifo_36
fifo_dualclock_macro
#(
.almost_empty_offset(9'h00f),
.almost_full_offset(full_offset),
.data_width(nbits),
.device("7series"),
.fifo_size ("36kb"),
.first_word_fall_through ("true")
)
fifo_dualclock_macro_inst
(
.almostempty(o_almost_empty),
.almostfull(almostfull),
.do(o_data),
.empty(empty),
.full(),
.rdcount(),
.rderr(),
.wrcount(),
.wrerr(),
.di(i_data),
.rdclk(o_clock),
.rden(o_read),
.rst(reset),
.wrclk(i_clock),
.wren(i_valid)
);
end
else begin : fifo_18
fifo_dualclock_macro
#(
.almost_empty_offset(9'h00f),
.almost_full_offset(full_offset),
.data_width(nbits),
.device("7series"),
.fifo_size ("18kb"),
.first_word_fall_through ("true")
)
fifo_dualclock_macro_inst
(
.almostempty(o_almost_empty),
.almostfull(almostfull),
.do(o_data),
.empty(empty),
.full(),
.rdcount(),
.rderr(),
.wrcount(),
.wrerr(),
.di(i_data),
.rdclk(o_clock),
.rden(o_read),
.rst(reset),
.wrclk(i_clock),
.wren(i_valid)
);
end
endgenerate
`endif
endmodule
|
/**
* components-shiftreg.v - Shift register(s)
*
* Verilib - A Verilog HDL development framework
* Copyright (c) 2014, Patrick Dear, All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3.0 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library.
*/
`ifndef _COMPONENTS_SHIFTREG_V
`define _COMPONENTS_SHIFTREG_V
/**
* Shift register. Yep.
*/
module components_shiftreg #(
/**
* Width of shift register
*/
parameter WIDTH = 8,
/**
* Value to reset to
*/
parameter RESET_VAL = 0
) (
input clk,
input rst,
input sh_en,
input load,
input [WIDTH-1:0] d,
input sh_in,
output [WIDTH-1:0] q,
output sh_out
);
reg [WIDTH-1:0] contents;
always @(posedge clk) begin
if (rst == 1'b1)
contents <= RESET_VAL;
else if (load == 1'b1)
contents <= d;
else if (sh_en == 1'b1)
contents <= (contents << 1) | sh_in;
end
assign q = contents;
assign sh_out = contents[WIDTH-1];
endmodule
`endif
|
// this program was cloned from: https://github.com/t-head-semi/openc906
// license: apache license 2.0
/*copyright 2020-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
module aq_f_spsram_1024x16(
a,
cen,
clk,
d,
gwen,
q,
wen
);
parameter addr_width = 10;
parameter data_width = 16;
parameter wrap_size = 1;
input [addr_width-1:0] a;
input cen;
input clk;
input [data_width-1:0] d;
input gwen;
input [data_width-1:0] wen;
output [data_width-1:0] q;
reg [addr_width-1:0] addr_holding;
wire [addr_width-1:0] a;
wire cen;
wire clk;
wire [data_width-1:0] d;
wire gwen;
wire [data_width-1:0] wen;
wire [data_width-1:0] q;
wire [addr_width-1:0] addr;
always@(posedge clk)
begin
if(!cen) begin
addr_holding[addr_width-1:0] <= a[addr_width-1:0];
end
end
assign addr[addr_width-1:0] = cen ? addr_holding[addr_width-1:0]
: a[addr_width-1:0];
wire [data_width-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<data_width; i=i+1) begin: ram_din_vec
assign ram_wen_vec[i] = !cen & !wen[i] & !gwen;
fpga_ram #(wrap_size,addr_width) ram_instance(
.portaclk (clk),
.portaaddr(addr),
.portadatain (d[i]),
.portawriteenable(ram_wen_vec[i]),
.portadataout(q[i]));
end
endgenerate
endmodule
|
//
// Copyright (c) 2002 Steven Wilson (steve@ka6s.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic reg form
//
//
module basicreg ( clk, d, q);
input clk, d;
output q;
reg q;
(* ivl_synthesis_on *)
always @(posedge clk)
q <= d;
endmodule
module tbench ;
reg clk, d;
basicreg u_reg (clk,d,q);
(* ivl_synthesis_off *)
initial
begin
clk = 0;
d = 0;
# 1;
clk = 1;
# 1;
if (q !== 0)
begin
$display("FAILED - Q isn't 0 on first edge");
$finish;
end
d = 1;
# 1;
clk = 0;
# 1;
if (q !== 0)
begin
$display("FAILED - Q isn't 0 after first falling edge");
$finish;
end
# 1;
d = 1;
clk = 1;
# 1;
if (q !== 1)
begin
$display("FAILED - Q isn't 1 2nd raising edge");
$finish;
end
# 1;
clk = 0;
# 1;
if (q !== 1)
begin
$display("FAILED - Q isn't 1 after 2nd falling edge");
$finish;
end
$display("PASSED");
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* 17-bit, 17-cycle unsigned integer divider, non pipelined */
module tmu2_divider17(
input sys_clk,
input sys_rst,
input start,
input [16:0] dividend,
input [16:0] divisor,
output ready,
output [16:0] quotient,
output [16:0] remainder
);
reg [33:0] qr;
assign remainder = qr[33:17];
assign quotient = qr[16:0];
reg [4:0] counter;
assign ready = (counter == 5'd0);
reg [16:0] divisor_r;
wire [17:0] diff = qr[33:16] - {1'b0, divisor_r};
always @(posedge sys_clk) begin
if(sys_rst)
counter = 5'd0;
else begin
if(start) begin
counter = 5'd17;
qr = {17'd0, dividend};
divisor_r = divisor;
end else begin
if(~ready) begin
if(diff[17])
qr = {qr[32:0], 1'b0};
else
qr = {diff[16:0], qr[15:0], 1'b1};
counter = counter - 5'd1;
end
end
end
end
endmodule
|
// this program was cloned from: https://github.com/whutddk/riftcore
// license: apache license 2.0
/*
* @file name: gen_slffr
* @author: ruige lee
* @email: wut.ruigeli@gmail.com
* @date: 2021-01-18 11:43:15
* @last modified by: ruige lee
* @last modified time: 2021-01-18 11:53:19
*/
/*
copyright (c) 2020 - 2021 ruige lee <wut.ruigeli@gmail.com>
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1 ns / 1 ps
module gen_slffr # (
parameter dw = 1,
parameter rstvalue = 1'b0
)
(
input [dw-1:0] set_in,
input [dw-1:0] rst_in,
output [dw-1:0] qout,
input clk,
input rstn
);
wire [dw-1:0] rsffr_qout;
gen_rsffr # ( .dw(dw), .rstvalue(rstvalue)) rsffr ( .set_in(set_in), .rst_in(rst_in), .qout(rsffr_qout), .clk(clk), .rstn(rstn));
assign qout = set_in | rsffr_qout;
//assert
always @( posedge clk ) begin
if ( set_in & rst_in ) begin
$display("assert fail at gen_slff");
$finish;
end
end
endmodule
|
//
// Copyright (c) 2000 Paul Campbell (paul@verifarm.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module compl1001;
reg [104:86]r0;
reg [261:230]r1;
reg [101:78]r2;
reg [216:215]r3;
reg [140:123]r4;
reg [70:53]r5;
reg [150:150]r6;
reg [143:133]r7;
reg [261:239]r8;
reg [228:211]r9;
reg [273:244]r10;
reg [42:21]r11;
reg [137:130]r12;
reg [103:96]r13;
reg [257:239]r14;
reg [230:205]r15;
reg [216:212]r16;
reg [64:40]r17;
reg [156:155]r18;
reg [103:94]r19;
reg [216:204]r20;
reg [170:165]r21;
reg [25:22]r22;
reg [125:105]r23;
reg [57:32]r24;
reg [261:250]r25;
reg [32:13]r26;
reg [251:246]r27;
reg [210:209]r28;
reg [121:119]r29;
reg [57:55]r30;
reg [255:253]r31;
reg [196:174]r32;
reg [26:26]r33;
reg [216:215]r34;
reg [238:224]r35;
reg [212:207]r36;
reg [32:11]r37;
reg [89:60]r38;
reg [246:237]r39;
reg [50:25]r40;
reg [43:29]r41;
reg [94:66]r42;
reg [235:222]r43;
reg [213:190]r44;
reg [102:81]r45;
reg [211:208]r46;
reg [108:91]r47;
reg [189:188]r48;
reg [97:84]r49;
reg [108:90]r50;
reg [124:116]r51;
reg [113:92]r52;
reg [278:254]r53;
reg [98:94]r54;
reg [43:42]r55;
reg [191:178]r56;
reg [230:211]r57;
reg [250:233]r58;
reg [236:229]r59;
reg [65:34]r60;
reg [155:132]r61;
reg [32:18]r62;
reg [253:253]r63;
reg [243:215]r64;
reg [133:109]r65;
reg [133:124]r66;
reg [66:51]r67;
reg [94:75]r68;
reg [31:23]r69;
reg [230:214]r70;
reg [75:55]r71;
reg [209:196]r72;
reg [200:181]r73;
reg [101:92]r74;
reg [43:34]r75;
reg [228:211]r76;
reg [171:169]r77;
reg [112:86]r78;
reg [257:252]r79;
reg [214:214]r80;
reg [279:254]r81;
reg [149:149]r82;
reg [80:53]r83;
reg [140:117]r84;
reg [265:238]r85;
reg [277:251]r86;
reg [71:45]r87;
reg [56:38]r88;
reg [95:91]r89;
reg [271:242]r90;
reg [187:174]r91;
reg [176:171]r92;
reg [100:88]r93;
reg [273:242]r94;
reg [137:111]r95;
reg [148:144]r96;
reg [168:159]r97;
reg [269:254]r98;
reg [149:145]r99;
reg [202:176]r100;
reg [37:26]r101;
reg [62:37]r102;
reg [47:36]r103;
reg [195:176]r104;
reg [124:93]r105;
reg [8:4]r106;
reg [170:161]r107;
reg [150:129]r108;
reg [54:40]r109;
reg [86:64]r110;
reg [132:111]r111;
reg [224:224]r112;
reg [262:232]r113;
reg [27:14]r114;
reg [99:97]r115;
reg [234:214]r116;
reg [66:52]r117;
reg [178:173]r118;
reg [83:52]r119;
reg [67:58]r120;
reg [110:82]r121;
reg [255:232]r122;
reg [41:19]r123;
reg [67:45]r124;
reg [179:178]r125;
reg [173:151]r126;
reg [35:20]r127;
reg [168:155]r128;
reg [129:112]r129;
reg [47:29]r130;
reg [199:186]r131;
reg [217:190]r132;
reg [241:212]r133;
reg [256:233]r134;
reg [129:116]r135;
reg [168:157]r136;
reg [230:211]r137;
reg [261:248]r138;
reg [39:27]r139;
reg [137:135]r140;
reg [169:142]r141;
reg [103:79]r142;
reg [118:118]r143;
reg [156:154]r144;
reg [234:208]r145;
reg [154:131]r146;
reg [211:183]r147;
reg [74:65]r148;
reg [161:145]r149;
reg [58:51]r150;
reg [268:253]r151;
reg [193:175]r152;
reg [148:120]r153;
reg [169:138]r154;
reg [213:210]r155;
reg [119:103]r156;
reg [104:83]r157;
reg [212:193]r158;
reg [172:172]r159;
reg [206:182]r160;
reg [176:159]r161;
reg [172:153]r162;
reg [119:110]r163;
reg [75:53]r164;
reg [5:5]r165;
reg [238:226]r166;
reg [258:230]r167;
reg [95:74]r168;
reg [231:216]r169;
reg [252:248]r170;
reg [98:79]r171;
reg [191:166]r172;
reg [161:154]r173;
reg [67:67]r174;
reg [214:207]r175;
reg [204:198]r176;
reg [131:118]r177;
reg [212:181]r178;
reg [258:248]r179;
reg [141:116]r180;
reg [201:198]r181;
reg [108:78]r182;
reg [83:72]r183;
reg [81:69]r184;
reg [144:140]r185;
reg [174:154]r186;
reg [191:171]r187;
reg [48:27]r188;
reg [260:251]r189;
reg [69:47]r190;
reg [259:246]r191;
reg [167:162]r192;
reg [245:237]r193;
reg [67:49]r194;
reg [133:108]r195;
reg [224:213]r196;
reg [126:108]r197;
reg [230:208]r198;
reg [80:59]r199;
reg [136:120]r200;
reg [62:44]r201;
reg [206:198]r202;
reg [284:254]r203;
reg [184:158]r204;
reg [32:13]r205;
reg [233:220]r206;
reg [69:59]r207;
reg [46:34]r208;
reg [181:156]r209;
reg [105:100]r210;
reg [240:228]r211;
reg [51:48]r212;
reg [149:144]r213;
reg [201:190]r214;
reg [234:215]r215;
reg [212:188]r216;
reg [98:79]r217;
reg [237:214]r218;
reg [105:96]r219;
reg [10:7]r220;
reg [134:105]r221;
reg [192:162]r222;
reg [202:180]r223;
reg [50:31]r224;
reg [50:26]r225;
reg [181:166]r226;
reg [146:117]r227;
reg [118:93]r228;
reg [222:202]r229;
reg [135:114]r230;
reg [78:51]r231;
reg [260:231]r232;
reg [172:142]r233;
reg [58:32]r234;
reg [245:232]r235;
reg [51:46]r236;
reg [198:167]r237;
reg [217:217]r238;
reg [130:121]r239;
reg [130:111]r240;
reg [28:0]r241;
reg [87:79]r242;
reg [60:58]r243;
reg [59:53]r244;
reg [200:178]r245;
reg [81:67]r246;
reg [110:104]r247;
reg [233:211]r248;
reg [139:129]r249;
reg [262:254]r250;
reg [177:175]r251;
reg [262:236]r252;
reg [111:94]r253;
reg [230:218]r254;
reg [191:164]r255;
initial begin
r0 = 32'h2eec;
r1 = 32'h1584;
r2 = 32'h47e5;
r3 = 32'h587f;
r4 = 32'hab8;
r5 = 32'h71e9;
r6 = 32'h4e49;
r7 = 32'h6794;
r8 = 32'h5c8e;
r9 = 32'h1a61;
r10 = 32'h55df;
r11 = 32'h2da5;
r12 = 32'h3d89;
r13 = 32'h76ab;
r14 = 32'h6d8e;
r15 = 32'h66ed;
r16 = 32'hc57;
r17 = 32'h615c;
r18 = 32'h29c0;
r19 = 32'h7ed1;
r20 = 32'h11c7;
r21 = 32'h5f7a;
r22 = 32'h59cc;
r23 = 32'h36df;
r24 = 32'h6217;
r25 = 32'h35da;
r26 = 32'h2827;
r27 = 32'h418b;
r28 = 32'h6fb;
r29 = 32'h7839;
r30 = 32'h114b;
r31 = 32'h4ca3;
r32 = 32'h3e6d;
r33 = 32'h6e1d;
r34 = 32'h5d63;
r35 = 32'h3797;
r36 = 32'h5a38;
r37 = 32'h6969;
r38 = 32'h8bb;
r39 = 32'h716b;
r40 = 32'hc42;
r41 = 32'h6ac3;
r42 = 32'h46ea;
r43 = 32'h3a78;
r44 = 32'h2b9c;
r45 = 32'h2fa6;
r46 = 32'hcbc;
r47 = 32'h45e6;
r48 = 32'h3e4b;
r49 = 32'h646;
r50 = 32'h4ce2;
r51 = 32'h76e9;
r52 = 32'h53d4;
r53 = 32'h327;
r54 = 32'h5359;
r55 = 32'h35be;
r56 = 32'h7c89;
r57 = 32'h747c;
r58 = 32'h6b9a;
r59 = 32'h1864;
r60 = 32'h6996;
r61 = 32'h2f40;
r62 = 32'h3d86;
r63 = 32'h5b1b;
r64 = 32'h1ca;
r65 = 32'h1216;
r66 = 32'hd10;
r67 = 32'h649e;
r68 = 32'h7727;
r69 = 32'h59e1;
r70 = 32'h48a8;
r71 = 32'h521f;
r72 = 32'h2928;
r73 = 32'h2423;
r74 = 32'h126b;
r75 = 32'h4707;
r76 = 32'h5fd4;
r77 = 32'h3b16;
r78 = 32'h300c;
r79 = 32'h7c6a;
r80 = 32'h2b87;
r81 = 32'h78c;
r82 = 32'hd80;
r83 = 32'h4c4c;
r84 = 32'h757b;
r85 = 32'h4487;
r86 = 32'h3e6c;
r87 = 32'h3496;
r88 = 32'hd19;
r89 = 32'h5098;
r90 = 32'h2a4f;
r91 = 32'hdd6;
r92 = 32'h3e02;
r93 = 32'h38f8;
r94 = 32'h4f6f;
r95 = 32'h71ba;
r96 = 32'h3adc;
r97 = 32'h5a68;
r98 = 32'h4884;
r99 = 32'hd4a;
r100 = 32'h68dd;
r101 = 32'h33c8;
r102 = 32'h127;
r103 = 32'h5ae8;
r104 = 32'h5818;
r105 = 32'h4679;
r106 = 32'h44f9;
r107 = 32'h9;
r108 = 32'h748a;
r109 = 32'h2074;
r110 = 32'h1593;
r111 = 32'h4ab1;
r112 = 32'h3be4;
r113 = 32'h6c27;
r114 = 32'h7331;
r115 = 32'hab0;
r116 = 32'h416;
r117 = 32'h2213;
r118 = 32'h41d;
r119 = 32'h429e;
r120 = 32'h1ea0;
r121 = 32'h3827;
r122 = 32'h46dd;
r123 = 32'h6c97;
r124 = 32'h6497;
r125 = 32'h6ada;
r126 = 32'h3b1c;
r127 = 32'h4eb7;
r128 = 32'h7779;
r129 = 32'h7c0a;
r130 = 32'h2d59;
r131 = 32'h1b54;
r132 = 32'h42b2;
r133 = 32'h397;
r134 = 32'h1151;
r135 = 32'h58fe;
r136 = 32'h9ea;
r137 = 32'h2dbe;
r138 = 32'h172d;
r139 = 32'h4e38;
r140 = 32'h1015;
r141 = 32'h337;
r142 = 32'h676c;
r143 = 32'h6cf3;
r144 = 32'h2338;
r145 = 32'h170f;
r146 = 32'h318e;
r147 = 32'h79ce;
r148 = 32'h18fc;
r149 = 32'h3643;
r150 = 32'h7986;
r151 = 32'h6b10;
r152 = 32'h7f4;
r153 = 32'h7520;
r154 = 32'h4fdd;
r155 = 32'h3b61;
r156 = 32'h49ae;
r157 = 32'h365d;
r158 = 32'h60a6;
r159 = 32'h2c4b;
r160 = 32'h117b;
r161 = 32'h7f4;
r162 = 32'h525;
r163 = 32'h3475;
r164 = 32'h23fe;
r165 = 32'h71c5;
r166 = 32'h443e;
r167 = 32'h1599;
r168 = 32'h7b77;
r169 = 32'h11ea;
r170 = 32'h6d9f;
r171 = 32'h564a;
r172 = 32'h64cd;
r173 = 32'h22d8;
r174 = 32'h3bad;
r175 = 32'h1b68;
r176 = 32'h615d;
r177 = 32'h473a;
r178 = 32'h282f;
r179 = 32'h1d5e;
r180 = 32'h5985;
r181 = 32'h378d;
r182 = 32'h5fbd;
r183 = 32'h3522;
r184 = 32'h6bef;
r185 = 32'h2d7c;
r186 = 32'h7fe6;
r187 = 32'h3cea;
r188 = 32'h659d;
r189 = 32'h28f9;
r190 = 32'hc24;
r191 = 32'h40af;
r192 = 32'h2eb9;
r193 = 32'h6b1f;
r194 = 32'h4581;
r195 = 32'h3a63;
r196 = 32'h381a;
r197 = 32'h42cb;
r198 = 32'h5105;
r199 = 32'h55f1;
r200 = 32'h3596;
r201 = 32'h6f4;
r202 = 32'h58e6;
r203 = 32'h78f8;
r204 = 32'h310a;
r205 = 32'h5ace;
r206 = 32'h146f;
r207 = 32'ha48;
r208 = 32'h422a;
r209 = 32'h17a3;
r210 = 32'h62ac;
r211 = 32'h3518;
r212 = 32'h7709;
r213 = 32'h786c;
r214 = 32'h63db;
r215 = 32'h240d;
r216 = 32'h3967;
r217 = 32'h6332;
r218 = 32'h3d92;
r219 = 32'h6fec;
r220 = 32'h3cbe;
r221 = 32'h6c27;
r222 = 32'h75af;
r223 = 32'h3e19;
r224 = 32'h410b;
r225 = 32'h6e83;
r226 = 32'h1004;
r227 = 32'h4ad7;
r228 = 32'h365d;
r229 = 32'h5720;
r230 = 32'h5abf;
r231 = 32'h5b3e;
r232 = 32'hd1f;
r233 = 32'h7cd4;
r234 = 32'h159b;
r235 = 32'h52fb;
r236 = 32'h3f25;
r237 = 32'h2292;
r238 = 32'h5fc9;
r239 = 32'h69ca;
r240 = 32'h5d77;
r241 = 32'h7f3f;
r242 = 32'h189c;
r243 = 32'h3cb5;
r244 = 32'h2ee1;
r245 = 32'h6755;
r246 = 32'h1ef7;
r247 = 32'h370a;
r248 = 32'h2b36;
r249 = 32'h743a;
r250 = 32'h1b77;
r251 = 32'hf1d;
r252 = 32'h5f68;
r253 = 32'h455e;
r254 = 32'h415f;
r255 = 32'h52c2;
#10; r73 = r189;
#10; r132 = 11'h783;
#10; r86 = ( ( & ( (14'h1136 ^ ((25'hd6c == $time) * r2)))) != 26'h1ef2);
#10; r246 = ( | ( 22'h6337));
#10; r35 = (r155 * ((r190 > (((((((r127 % ( | ( r81))) & r150) | r11) !== (((r207 <= (22'h4d2b ? ((r158 == ( - ( r219))) | 13'hdae) : r43)) != ((r97 > ((r240 != ((26'h259a * 13'h465) >= (5'h2 * 11'h7ed))) % (((12'h279 < 28'h3026) || 4'h1) && r111))) & ( ! ( ( ! ( (16'h7a99 <= 4'h6))))))) & 26'h5fa4)) && (((r15 | (( ( | ( ( ~ ( (r235 && 31'h2eeb))))) / r90) !== r56)) <= ((22'h640f !== r182) <= (31'h1b37 !== ( ( | ( (((9'hc9 / 32'h7c3b) - (8'ha6 - 3'h2)) == ((12'h36b - 9'h171) < ( + ( 23'h425)))))) % r72)))) + $time)) > r1) !== 18'h6d7b)) >= 28'h6e25));
#10; r144 = 4'h9;
#10; r206 = ( ( | ( 12'h4ff)) | 17'h43ef);
#10; r138 = $time;
#10; r74 = 22'h38ad;
#10; r49 = r2;
#10; r50 = ((31'h744c ? ((r164 && r191) >= 16'h6c50) : ((r137 / ((1'h0 ^ ((r169 >= (((20'h5ab3 == ( & ( ( & ( (21'hb12 < (7'h16 || 10'h24e))))))) != r155) - ( | ( ( + ( ( ( ! ( r166)) % (26'h296c > 32'h62ed)))))))) === ( + ( ( | ( r187)))))) - r92)) * r99)) >= r189);
#10; r150 = ((12'h24d != r248) / ( & ( (((r34 - ( ! ( 20'h40cd))) === (((7'h52 > (25'h7f1d || 1'h1)) && 5'h12) ? ( ^ ( (r61 && ( ~ ( ( ( + ( ( ! ( (r73 <= ( | ( ( ( & ( 28'h57c)) / (24'h60a8 < 28'h7acc))))))))) | (8'h61 < ( ! ( (r184 === ( ~ ( (r72 == (15'h508 / 24'h5073)))))))))))))) : r24)) | r86))));
#10; r73 = ( ( + ( ( ( ~ ( ((((20'h23e2 === ((11'h649 ^ 21'hfee) | ((r35 % 30'h856) <= r67))) !== ((r183 || (((r19 / (15'h304d + 25'h523a)) && 17'h7692) - r178)) - (((((25'h34f5 || r199) === r255) <= r12) !== (((((5'hb / 5'h11) == (5'h17 | 24'h408)) / (r255 ^ r181)) && ( & ( 14'h2e37))) === ((17'h1e79 <= r84) / (r0 !== ( ^ ( (26'h587b <= 20'h7403))))))) >= ( - ( r184))))) !== ( - ( r248))) === $time))) * 12'h5))) || r191);
#10; r134 = (1'h1 === 24'h12a0);
#10; r214 = 30'h3839;
#10; r255 = 30'h242b;
#10; r7 = 9'h132;
#10; r130 = r65;
#10; r64 = r162;
#10; r174 = ((r91 <= (r231 + ( - ( 1'h1)))) <= ((((r93 <= (r183 / ( ( & ( ( ^ ( ( ^ ( 1'h1)))))) <= r75))) * 12'ha95) & r27) | ((((((20'hf1f === ((r175 >= 20'h3632) | ((r109 & (r88 < r248)) < 10'h2e5))) & r37) % $stime) || ( ( + ( ( ! ( r160)))) & r17)) > ( ( | ( (r124 & ( - ( ( - ( (22'hd2b != ( ! ( r196)))))))))) && r84)) | (r51 / 16'h5f0d))));
#10; r41 = ( ( ^ ( ( ( ^ ( ((3'h6 >= (r215 & (31'h3d8b && ( ^ ( 5'h11))))) <= $time))) & ( & ( r7))))) * ( ( - ( (12'he7e ? ( + ( ((3'h2 ^ r250) & (r214 <= (r19 - r249))))) : (r140 | r104)))) || r250));
#10; r195 = 9'h1ac;
#10; r242 = 21'h527c;
#10; r143 = ((((((r68 ? (6'h1e ? ( ^ ( 26'h4f04)) : ( - ( ( ( - ( $time)) - (( ( + ( r96)) !== (r185 / 6'h22)) ? r133 : r2))))) : r20) * ((28'h20ec % r109) / ( + ( ( ( & ( 1'h0)) | (13'h13f1 === ((r96 - r204) * ( | ( 1'h0))))))))) === ((23'h4c6b / (20'h7a3b === r184)) == (( ( ! ( ( ( + ( (((7'h59 ? ((3'h4 <= 13'had1) | 15'h1a5c) : r123) % $stime) == ( + ( (((15'h74fe === 2'h0) == ( + ( 3'h0))) <= ((26'h2e1 | 8'h3b) + (16'h76a4 == 26'h645a)))))))) + ( + ( ((r123 & (r37 != (r211 >= (21'hcee < 18'h2845)))) >= (27'h5efd ^ r116))))))) | ((25'h4cd6 + r74) ? r115 : ((r133 - ((r198 ? r55 : (($stime % 17'h38a5) | $time)) === ( ~ ( r217)))) ? (r250 !== 19'h49e1) : ( ! ( r15))))) == r224))) - ((r244 > (r229 - ( & ( (( ( + ( r244)) != ( ! ( ((29'h6d1b === 10'h364) - ((17'h43c9 & ( + ( r238))) == r113))))) % 30'h7539))))) & ( | ( 23'h4205)))) | 5'h19) <= ( ! ( r92)));
#10; r74 = r232;
#10; r31 = ( ( ~ ( r181)) && ( - ( 7'h8)));
#10; r75 = (6'h10 === r188);
#10; r75 = ( ( & ( $stime)) + ( - ( ((( ( | ( (16'h1c8a % 32'h503f))) ? ((r161 ^ r59) == ( ! ( ( - ( (((r191 === r182) == ( ( + ( ( | ( r168)))) > ( ( | ( 1'h1)) * (( ( ^ ( 32'h2923)) != (14'h3cd7 * 24'h1162)) > (25'h7bc2 - 6'hd))))) - r31)))))) : ((4'hd & ( ^ ( (r130 - ((r96 === r154) == (32'h2fba >= ( | ( 4'h3)))))))) >= ( & ( (((r253 !== 18'h4189) >= (11'h679 < r133)) * r109))))) != $time) !== ( ( ~ ( (((21'h5dd3 / (10'h22e ^ (( ( ! ( ( + ( ( & ( (21'h5c32 * 12'h7e))))))) - ((((16'h132e || 23'hf58) <= 21'h1302) ^ ((2'h1 | 4'hb) - r113)) & (r207 || 24'h1190))) || ((r224 && r246) > 7'h19)))) % ( ( ~ ( r150)) - ((1'h1 & 24'h7aa2) | ($stime !== r24)))) >= 14'h29de))) !== ( + ( 10'h207)))))));
#10; r195 = 4'h7;
#10; r129 = r208;
#10; r152 = r144;
#10; r9 = (( ( ! ( ( & ( (r39 >= r176))))) - 5'h6) ^ 12'h837);
#10; r159 = ( + ( ((r132 <= (((( ( + ( (24'h5c17 + r12))) == 24'h3ca7) > r164) >= ( ( ^ ( r114)) > r126)) < ((r0 & ( ~ ( (22'h7ece <= (((2'h3 % (r90 + ( ( + ( 6'h1)) | $stime))) | r51) !== (27'h1d94 == (r189 & r252))))))) ? 2'h0 : r110))) <= ((r124 % r178) <= ( ( & ( $time)) - (((r22 == 27'h4da6) != 19'h14be) ^ (r155 / r52)))))));
#10; r92 = (28'h4175 + ( - ( ((( ( ~ ( (4'hf % (($stime ? 5'hf : ((((4'h8 | (r118 !== 10'h222)) != ($time / r53)) ? ( ~ ( r49)) : ((r251 > r162) - r163)) == 17'h72a0)) && (16'h486b === r203))))) + r130) + 14'h3094) ? (((r153 | 12'h53b) + (((r97 ^ (28'h6257 > 4'h5)) !== ( & ( ( ( ^ ( ( | ( ( & ( 13'h1537)))))) != ((18'h18c7 != r154) & r105))))) != r241)) - r193) : ((14'hcba !== (r26 | ($time && ((22'h643d ^ ( ( ~ ( r117)) < (r206 === ( ^ ( ( ! ( ( ! ( (11'h3b3 >= 27'h6d33)))))))))) / 6'h2c)))) > ((25'h6f8d >= 26'h4258) == ( ( & ( (( ( ! ( ( ~ ( ( ( | ( 32'h41ba)) + ( ( ! ( 14'h2b91)) + r190)))))) <= (26'h5532 + 14'h12cb)) == (r232 % ((21'h2891 / r76) + ( + ( ( ( & ( ((8'h43 <= 24'h19c2) > ( & ( 25'h70d2))))) + ((31'h65e0 !== (10'h18a ^ 1'h1)) < r191))))))))) / ((16'h16d0 ? 26'h5ce4 : (r66 ? ( ! ( r127)) : ((((((18'h6d90 ^ 19'h2911) % (18'h5898 * 3'h0)) && $stime) !== ( ( & ( ( ~ ( 25'h56ef)))) - ( | ( r124)))) * ( | ( ( ! ( (r62 ? r238 : (22'h5c72 <= 28'h4c3))))))) != ( | ( 22'h388d))))) | (((( ( + ( r248)) !== ((r240 % 30'h5a83) - r4)) + 31'h131) || r147) & ((r36 | (((((15'h5184 > 29'h7846) + 15'h4959) ^ (r123 * r200)) / ($time & ( + ( (8'hc8 & 9'h1db))))) > 5'hd)) / ((r86 > 29'h4da1) !== r118)))))))))));
#10; r222 = (r106 * 32'h1826);
#10; r88 = ( ( ! ( ((((r249 != 18'h6b91) > ( ! ( ((r65 == r236) & 7'h59)))) ? r146 : ((r162 === $time) <= r135)) > (( ( + ( 32'h2513)) !== r252) || r147)))) <= ((32'h371b == r72) < 5'h1f));
#10; r131 = r22;
#10; r48 = ( ( & ( (((( ( - ( ((r9 - 30'h63a0) * r22))) | ( - ( r212))) ^ 10'h1d5) === ( ^ ( 14'h2dbb))) % (9'h178 % (r241 !== ( ( | ( ( ~ ( (((21'h280 !== ((29'h1c0a - (1'h0 + 2'h3)) / (26'h2be2 * (r98 && ( & ( 22'hac0)))))) | (17'h5864 || r147)) <= (r51 ? ( ^ ( r226)) : (r15 != ( | ( (8'hb6 && 6'h34)))))))))) < (9'h1bb != r114))))))) === r208);
#10; r217 = ( | ( (r7 || ((r98 === (r212 === ( ( ! ( $time)) | (6'h3 + 23'h6819)))) / (r154 >= ( & ( r135)))))));
#10; r145 = ((7'h5d > r79) != ( - ( r98)));
#10; r22 = ( ~ ( 22'h43eb));
#10; r115 = r221;
#10; r239 = (r198 !== (10'h79 !== (12'h444 ^ ((r204 && r214) % ( ~ ( r7))))));
#10; r170 = ((r185 % 25'h5b50) - r104);
#10; r139 = (( ( ^ ( (((29'h158a && r170) ? r64 : 26'h4955) - (r100 >= r61)))) * r136) | r122);
#10; r78 = 7'h10;
#10; r72 = r70;
#10; r145 = ( | ( (8'h86 && r159)));
#10; r123 = $stime;
#10; r220 = ( ! ( ( ~ ( ((((r79 === 12'hd3) && r55) % ((r1 <= ((r226 % (( ( | ( r107)) != r227) < (($stime < r242) != ( ! ( ( ( ! ( 29'h6b4e)) * (r221 || ( ( ! ( 29'h162a)) > 25'h45be)))))))) !== ((( ( ! ( ( | ( (r179 <= $stime))))) && 20'h7a52) & r249) < 29'h58eb))) & 25'h4a32)) == (r63 == r136))))));
#10; r31 = 32'h3c62;
#10; r216 = (r148 != r198);
#10; r140 = r215;
#10; r227 = ((r246 ? $stime : r163) && (((( ( ~ ( r157)) + 13'h1de6) / 2'h1) !== (($time <= (r195 & ( ^ ( r121)))) && ( ( ~ ( r165)) * ((r124 !== 13'h9f1) && (r226 == (r79 <= ((r188 | ((((r70 >= (29'h4a7 % 2'h3)) < ((8'hba >= 4'h5) || 24'h394b)) !== r140) + $time)) / r68))))))) && r193));
#10; r168 = 2'h3;
#10; r208 = r211;
#10; r196 = ((((r227 < 24'h299e) != 10'hac) && (((r16 && ((r10 ? ($time / $stime) : r229) >= ( & ( (( ( | ( ( ( | ( 15'h5c9d)) / ( ^ ( (r242 !== r117)))))) && r200) <= ( & ( ( + ( ( ! ( r228))))))))))) - (7'h2c != (( ( & ( 17'hd65)) ^ $time) + (r82 >= r124)))) ? ( ^ ( r222)) : ( & ( ( ^ ( ((r146 != $stime) ^ ( ! ( (r4 % ( ^ ( r114)))))))))))) ^ r88);
#10; r200 = 12'h3e9;
#10; r158 = (24'h2147 - 4'h4);
#10; r72 = r219;
#10; r101 = ( | ( (r104 + r252)));
#10; r98 = (27'h401a ^ ( | ( ( ( ~ ( 13'h74a)) * (( ( ^ ( r121)) ? 5'hf : ( ( ^ ( 17'h6a2d)) % 2'h3)) != (r43 === (32'h2ec9 % ( - ( ( ~ ( (($time !== ((21'h583a + ( & ( r117))) * r30)) <= r167))))))))))));
#10; r57 = ( ^ ( r87));
#10; r54 = ( ( + ( ((( ( - ( r109)) ? 6'h9 : r99) - 28'h6c8c) + ((((((25'h46be && 14'h16f3) > r158) / r249) % (r168 || (r95 === ( + ( (((((r204 % $stime) <= ( + ( (27'hb65 != 6'h1b)))) <= ((r139 && (11'h577 || 27'h5dbd)) + 1'h1)) || ((((13'h9d1 !== 22'h14cf) | (26'h101a + 23'h31a9)) | ((7'h4b - 26'h63f8) | (30'ha4d * 32'h760))) < ( ( ^ ( 3'h1)) < r111))) < (((r215 & 32'h4838) / ( ( ^ ( (24'h2d6f || 28'h4fde))) && ((4'hb <= 9'h24) & r112))) | (r97 === (r76 < 8'h76))))))))) ^ ( ^ ( ((26'h3743 || ( ( - ( ( ! ( ((3'h4 * ((7'h66 !== 32'h4200) & 14'h2b24)) ? ( - ( r57)) : 21'h6ef))))) <= r70)) | ((r159 <= r181) - ( ( + ( (r36 || (r49 != (r185 === ( ^ ( ( ! ( 10'h2dc))))))))) === r150)))))) >= ( | ( ( ( & ( ( ! ( 22'h416f)))) !== (r137 + ( | ( $time)))))))))) ^ r148);
#10; r44 = (11'h11 || 13'h99d);
#10; r213 = r254;
#10; r101 = 31'h6ed;
#10; r190 = ( ^ ( r133));
#10; r222 = (32'h2008 >= 24'h68a3);
#10; r12 = r13;
#10; r235 = ( + ( (r42 / $stime)));
#10; r50 = ( ( ^ ( ((r251 <= ((27'h6eee > ( & ( (($time ? r43 : $time) !== (7'h36 !== ((((((23'h6f4 != 26'h7c8b) & (32'h5eeb < 25'h6227)) | $stime) * (((29'h6a61 === 11'h6bf) & (30'h6956 / 21'h637d)) > r209)) + ( | ( (($time % (22'h3516 ? 11'h405 : 6'h5)) % (11'h49d >= (4'he ^ 17'h9e1)))))) + r82)))))) & r152)) * ((((((r53 & r240) != ((((r146 === ((14'h1ccc - r221) % 1'h0)) !== ((( ( | ( 23'h24bd)) & r79) >= (26'h2a62 / 23'h59d6)) !== r94)) < ( ( ! ( ( ~ ( ((26'h1762 / 12'h3bb) === ( ~ ( 20'h2582))))))) > r104)) * r190)) != (21'h5a98 >= r53)) && ($time * 13'h1dc3)) / $time) - r217)))) < (( ( - ( ( + ( (2'h2 !== r32))))) != ( ( ~ ( ( & ( (r130 != ((29'hc97 - $time) ^ ( - ( r18)))))))) - r102)) + r33));
#10; r224 = r199;
#10; r74 = 31'he64;
#10; r92 = ((( ( ^ ( ((r138 ? (((((r82 == (r128 * (r32 % (15'h7083 <= r219)))) > ( + ( ( ~ ( 31'h75c7))))) && $time) <= 2'h3) | 23'h7c7b) : r20) + ((25'h4238 >= (( ( ~ ( r30)) < r97) ? (((((24'h5cda + r34) === 31'h60c9) != r72) == 11'h5c8) | (r92 / r77)) : (r26 != r174))) % (( ( + ( (((13'h507 + $time) < (r230 < r79)) / (( ( - ( ( & ( (21'h77de >= 21'h595c))))) & (6'h29 == r159)) == r120)))) ? (( ( ^ ( ($stime % ( & ( (r44 ^ 19'h4868)))))) || 29'h425) != ((((((27'h3be5 <= 21'h73b3) >= 5'h1e) - ( ! ( (24'h14b5 | 12'h81f)))) != (((31'h6c1a >= 7'h66) != (21'h2b37 * 5'hc)) | 26'h1e08)) ? $time : ((r238 && 9'he4) | $time)) / $time)) : ($stime || 10'h2af)) | 30'h6f3b))))) != ( & ( ( & ( (30'h2102 - (r214 ^ (r148 != r173)))))))) || r12) + $time);
#10; r20 = (r109 ? (((((r205 * r142) - ($time && (14'h12d7 & (25'h300a ^ $stime)))) != 8'h46) || ( ~ ( ( ( + ( ( ~ ( ($stime < ( ! ( ( ^ ( (r127 + r51)))))))))) == (r175 % ( ! ( (((r70 == r189) > (((r1 !== 9'h40) != (5'h3 !== r198)) + (r221 ^ 30'h283b))) || 29'h1a0c)))))))) + (((r220 + (26'h5440 != (2'h1 == 6'h2e))) & r219) & 28'h5a06)) : (14'h1a0a < 6'h15));
#10; r253 = ( ! ( 32'h3419));
#10; r95 = 16'h3cbd;
#10; r49 = 2'h1;
#10; r17 = (r251 <= r61);
#10; r151 = 4'h7;
#10; r136 = (r253 || ((r68 <= 30'h5ad3) != (3'h0 % ( + ( 27'h5cc2)))));
#10; r35 = (r153 & (r74 | ( ( & ( r94)) <= r72)));
#10; r120 = (30'h3c55 + ((r48 || r173) & r231));
#10; r214 = ( ( & ( (r168 % ((((28'h55b2 ^ ( ( ! ( 8'h4b)) === 11'h221)) < r217) != ( ( ~ ( ((r213 / ( + ( ( ( | ( (((18'h5f95 * 8'h91) || (7'h17 & 16'h8ab)) && r127))) == 16'h5aae)))) * ( + ( ((r109 == ((((18'h3972 + 25'h7165) == (4'h4 >= 7'h58)) * (6'h2a - (28'h4a9a + 16'h768d))) != (r130 !== ((11'h36b < 17'h7bb9) / 31'h65db)))) ? ( | ( r139)) : ( - ( 28'h5d29)))))))) !== (((15'h7581 < 5'hd) + ((((20'h61ac ^ r219) < 1'h0) | (r79 ^ r25)) * (r90 < $time))) - ( ^ ( ( - ( (( ( + ( ( + ( r130)))) == (( ( ~ ( r200)) >= 24'h433) < 1'h1)) + 17'h7ce2)))))))) ^ (( ( & ( ((r161 + ( & ( ( ( ^ ( r63)) * (((r201 & (13'h1fa9 || 2'h3)) * ( ^ ( r103))) * r28))))) | 1'h1))) === $stime) > ( ^ ( ( ! ( r165))))))))) >= ((( ( | ( 3'h6)) | r66) | 5'h8) ? ( - ( r24)) : (r227 / ( ^ ( ((( ( ~ ( (((r63 * ( ( & ( (r92 / (24'h565a + 12'h647)))) - (r124 < r138))) || ( - ( (18'h1d84 | ((r186 - 28'h4f76) | ( ( - ( 4'h5)) != 25'h57d1)))))) ^ ((r196 >= ( | ( r186))) ? ((32'h15b6 & (26'h458a > ( ! ( r103)))) / r171) : r99)))) || (($stime - (((((r64 | r129) / 18'h31eb) | $stime) & (1'h0 / r226)) != ( + ( r173)))) != r3)) % (r109 >= 9'h119)) + (((((20'hf4b ? ( & ( (16'h394b > ($time * ( + ( (16'h480 === 32'h42fb))))))) : 24'h56a7) ? 22'h5ab9 : r136) === 14'h2f0a) <= r83) % r134)))))));
#10; r223 = (r227 ^ ( ! ( ((28'heb ? ( + ( (r213 | (20'h18bc >= r78)))) : ( & ( 10'h333))) | ((r132 != r21) - (r23 | r235))))));
#10; r70 = $time;
#10; r76 = (r49 / (((( ( - ( r188)) && r46) <= (r73 * r159)) || (r109 ^ ( & ( 13'h12a8)))) / (( ( - ( $stime)) > (r165 / ((25'h7b9e * ( - ( ( ^ ( (((r28 + (r247 > ( - ( (2'h0 % 10'h360))))) % 13'h48d) ? (29'h6a6f - 27'h5199) : 22'h2db7)))))) < 17'h6a8e))) >= ( ^ ( ( - ( 5'h3)))))));
#10; r184 = ( & ( ( & ( r95))));
#10; r244 = ( | ( (12'hb7 / 9'hb9)));
#10; r239 = 19'h7f7c;
#10; r246 = (r224 != ((($time < 11'h493) !== (18'h148b - r178)) == (7'h4c < (r198 && ( | ( ((((((r140 & ( ~ ( (( ( - ( 15'h988)) | r21) || ( ( ^ ( 11'h5c4)) <= (20'h7942 >= 15'hca5)))))) % r6) && (($stime + 6'h16) > ( & ( 13'h76d)))) > ( ( - ( r13)) >= ( ( + ( 13'hc6a)) / (r247 * r180)))) >= (7'h20 || (( ( ! ( (((12'haae > 10'h15a) && 16'h4261) > r16))) & ((r100 / (r60 + (r99 / (27'h2093 - 8'hd5)))) - r234)) & ( ( ! ( $time)) === $stime)))) >= r31)))))));
#10; r208 = r57;
#10; r120 = 26'h5f9c;
#10; r176 = 5'h2;
#10; r205 = ( ^ ( 31'h6209));
#10; r219 = (1'h0 * ( | ( r56)));
#10; r9 = 19'h2d05;
#10; r112 = ( ( ~ ( ( + ( ( ^ ( r163)))))) <= ( - ( ( | ( (r78 % ( ( + ( ( ! ( $time)))) != (31'h4aff * r79))))))));
#10; r163 = r143;
#10; r20 = (((r127 | 17'h3217) ^ r11) || (8'ha2 != (r189 === r201)));
#10; r45 = ((r171 ^ ( ! ( (r42 === 5'he)))) >= 13'h1b72);
#10; r72 = ( ( | ( ( + ( r110)))) - 10'h189);
#10; r238 = $stime;
#10; r234 = r199;
#10; r247 = r34;
#10; r138 = r206;
#10; r245 = ( | ( r167));
#10; r253 = (( ( | ( 14'h394d)) != (( ( ^ ( (((10'h1c6 == r212) ? ( + ( ( ~ ( r148)))) : r51) ? ( ( ^ ( $time)) < r233) : (7'h3c ^ ( ^ ( 17'h7cde)))))) !== ( ( | ( r155)) !== r64)) <= r224)) % (( ( + ( (r79 === ((1'h1 <= (r81 / r68)) + (r139 != ((r180 ? ( + ( ( ! ( ( ~ ( r46)))))) : (r171 % r237)) * r102)))))) % ( ^ ( ( | ( r78))))) <= (17'h2b1f ^ ((17'h3160 ^ r59) > (((6'h3 + $time) * ((7'h3f !== $stime) ^ 3'h2)) ^ ((r181 > (r221 | (((r187 != ( - ( (((14'h3871 - 31'h1261) < (8'had / 6'ha)) & r192)))) || $time) ? ( + ( r154)) : $stime))) + ( & ( 21'hfbf))))))));
#10; r193 = ( & ( 15'h1a54));
#10; r143 = r132;
#10; r161 = ($time & ( ~ ( (r107 ^ $stime))));
#10; r47 = r197;
#10; r72 = ((($time == 14'h3eb9) !== r242) < 12'hee0);
#10; r167 = ( ( ! ( ( + ( r50)))) + ( ^ ( (r231 * ((6'h26 <= ( ( ~ ( ( ( + ( ( - ( ((( ( + ( (2'h1 != 19'h3fa5))) === ((6'h11 % 4'h1) / (10'h37a / 30'h1e1c))) * 9'h1b6) != ( ( & ( (8'h22 === 2'h1))) * $stime)))))) * 13'h1daa))) * r192)) === 26'h5f03)))));
#10; r99 = ( ~ ( ( ~ ( r218))));
#10; r66 = ( ( ~ ( ((( ( ^ ( ((11'h73f ? ($stime === ( ~ ( r187))) : ((((20'h4125 + $stime) | r85) == r13) === ((22'h47f0 & (r164 % ( & ( ( + ( (23'h1879 + 19'h28f2))))))) >= 4'hf))) * $stime))) === ( ^ ( 29'h67cf))) || ( | ( r240))) > ( - ( (r78 + (23'h272f && (r132 != (( ( & ( (($stime === (((16'hed3 * 1'h0) < $time) && ((6'h2 / 9'h101) ? (21'h637d - 26'h4190) : r63))) * ((((9'haf & 14'h2ce7) ? (2'h2 & 9'h197) : 9'hd5) <= ( ( + ( 27'h32c1)) && (9'h147 - 5'h11))) >= (r159 == (r200 <= 28'h3218)))))) ^ ( - ( ( + ( (r202 ? ( ( - ( 14'h190e)) % ((16'hffb >= 26'ha6d) + (23'h3a46 | 3'h4))) : r83)))))) % r246))))))))) ? ( ( ! ( ( ^ ( ((r117 === r65) & (r92 & r196)))))) / ((((((16'h4c37 !== ((r124 * r17) < (r161 + ((r55 === ( ( ~ ( r209)) & 10'h3fc)) % ( ( & ( ((7'h2f + 18'h274a) * (31'h4de5 < 12'hb26)))) >= ( ^ ( ((14'h3161 >= 25'h7632) * (25'h2a76 * 8'he))))))))) > ( ! ( ((10'h390 - r60) % (((13'h649 + ( - ( r187))) !== r61) | 19'h40eb))))) >= (19'h49d9 <= r1)) & (( ( & ( r174)) == r111) / 18'h4732)) - ( ( ! ( ( | ( (r232 > r110))))) + (r73 < $stime))) <= r163)) : ( ^ ( ( ! ( ((((r195 | ( ( | ( 22'h41f9)) ? (23'h754e / 6'h28) : (25'h7d32 == (4'h6 < 5'h1f)))) & ( | ( ( ( ! ( r87)) - r71)))) - ( ^ ( r179))) | ( ( & ( (3'h2 > $stime))) + ( ! ( r165)))))))));
#10; r9 = (26'h2a2e != 15'h83d);
#10; r125 = 15'h6f76;
#10; r245 = ( | ( 28'h74c2));
#10; r157 = r203;
#10; r166 = ((21'h29d6 != (($time - r242) == ( ( & ( (((11'h323 && ( ~ ( (1'h1 + ((r68 / (((13'h18c8 + 15'h2554) % r147) === (9'h40 === (4'he || 1'h0)))) ^ ($time & r189)))))) | 30'h4919) <= r151))) < (r137 ? (r50 % (( ( - ( $time)) >= 19'hbdc) * r216)) : ( ( ~ ( (6'h3d | $stime))) <= 1'h0))))) <= ( ( - ( r229)) >= 22'h3540));
#10; r138 = r246;
#10; r163 = 32'h357d;
#10; r251 = ( & ( ( - ( r85))));
#10; r83 = ((23'h34a0 <= r246) === 11'h66b);
#10; r183 = (r152 || (($time ? (21'h6ca4 > 28'h650) : r140) != ($stime !== 27'h1214)));
#10; r171 = 32'h6d44;
#10; r180 = 9'h180;
#10; r167 = (r199 ? ( | ( r212)) : 23'h3844);
#10; r221 = 12'h1b;
#10; r198 = (r72 ? ( ! ( r4)) : ( - ( r213)));
#10; r97 = ( & ( 14'h290e));
#10; r164 = 5'h3;
#10; r33 = ((($stime || (7'h9 >= 9'h1bf)) < 14'hb12) < ((r246 / ((r116 ? 20'h1b7c : ((r189 + 17'h6013) - $time)) % $stime)) == (r100 ^ ( ( ~ ( (r189 !== r96))) & r40))));
#10; r154 = ( ( - ( ((26'h562a && r20) && (r167 | ( ( & ( (r219 | (r185 ? (r114 || ($time / r206)) : (1'h0 < $stime))))) ^ 21'h4aae))))) / ( ~ ( (r253 % ($stime * 15'h5c88)))));
#10; r25 = (r5 & r139);
#10; r205 = ( ( ! ( ( ! ( 29'h4196)))) && ((13'h19ed != (r149 != (24'h3ba0 !== ((r142 != (30'h3f71 || r189)) - ((((r109 / ((8'h1b % ( ( | ( r115)) === ( & ( ( | ( 30'h3325)))))) || ( + ( 6'h6)))) !== r180) || 26'h3874) - ((((15'h26a5 - ((((10'h36c % 18'h1c8) && (3'h0 <= 1'h0)) !== ( & ( (30'h1ae9 - 29'h35cf)))) > 23'h24e9)) || ( & ( (r194 * r105)))) & $stime) % ( ! ( (( ( + ( ( | ( r76)))) | ( ( ! ( ((3'h5 - 10'h2ec) + (32'h73bf & 20'h6da1)))) <= r79)) / r48))))))))) % r32));
#10; r180 = ( ( | ( ((12'hc2a % ( + ( (((4'he < r151) >= ( ! ( r53))) >= (((( ( ! ( ((7'h1a ? ((21'h60e7 / 26'h652f) / ( ! ( 16'h3871))) : (29'h69c9 && (29'h415d >= 15'h4e98))) && (((27'h4d27 === 5'h11) == (5'h7 / 27'h23f2)) > ( + ( ( ~ ( 18'h3e82)))))))) != ( ( ! ( ( ( - ( r245)) != r141))) < (((r169 && 18'h2377) * ((19'hf5c && 21'h6ee0) || 2'h3)) / r178))) * ((((((16'h46dc >= 13'h54) >= (17'h793b >= 25'h35db)) < ((27'h7f99 > 23'h7718) != (12'hc9e == 3'h3))) || ( ( & ( (17'h2856 !== 18'h357))) * r241)) && ( ( ~ ( ((12'hfd6 * 14'h2446) / r102))) || ( ^ ( (r18 ? r25 : r123))))) == 5'h13)) ^ r185) | r245))))) !== (((r52 && ($time == r43)) !== ((14'h101e < ( ( + ( ( & ( ( ( + ( r195)) !== r50))))) || ( - ( 20'h140)))) != ((r48 != (r78 >= 6'h1c)) | (9'h8c ^ ( | ( 29'h4eb7)))))) < (((r199 + 11'h4f4) || r190) != 19'h5fcb))))) !== (((($time == ( + ( 4'hf))) / ( + ( (24'h4ff8 * ( ( ! ( ( - ( (((((r11 | (11'h26b - 6'h39)) ^ r52) & (($stime % (15'h3778 == 15'h3a4a)) % $stime)) ? ( ^ ( (r49 > r191))) : ( ^ ( ( & ( ((15'h721d >= 11'h498) !== 13'h113c)))))) == r247))))) !== 15'h3ec5))))) === r154) | ( & ( ((31'h5377 && ((r11 || ((((r70 > (r202 !== r43)) ? (r221 >= (((r255 == $stime) < ( | ( ( - ( 23'h36a7))))) != (13'h1664 !== 32'h669a))) : r32) | (((7'h56 && 5'h1b) && (r106 == r168)) !== ( & ( ((22'h15c7 && (r210 ^ ( - ( 30'h3a9c)))) ^ (((6'h12 | 1'h0) - (24'h3128 * 26'h265)) === (31'h947 | (28'h7be5 & 31'h336f)))))))) & ((r91 + ( + ( 17'h1d47))) & (( ( | ( 28'h2f2)) && ( ^ ( 26'h663d))) <= ( ~ ( ( ! ( ( ! ( (19'h5235 % (19'h3511 - 32'h5628)))))))))))) || (13'h82e | (r15 || (20'h145c != ( ( & ( r228)) == ( ( - ( (((2'h3 ? 10'h31f : 8'h32) + ( & ( 13'h567))) % ( ( ^ ( 5'h2)) <= r117)))) != (r138 == ( & ( 14'h2b3a)))))))))) && (8'h99 ^ ( & ( (((((r157 + (30'h3c00 || $stime)) / r106) === ($stime !== ( + ( ((9'h1b1 > ((19'h62e4 * 22'h2f20) - r190)) / 25'h38aa))))) != r200) % 1'h1)))))))));
#10; r29 = ( + ( 8'h46));
#10; r70 = (r45 ? ((2'h0 > ( & ( ((((28'h54b0 != ((r240 <= r248) - ((r123 <= 20'h4d70) ^ (r183 == (r182 == ( + ( ( + ( (11'h50f && 24'h6d05)))))))))) == (9'h45 % ( & ( (20'h5daa | (((( ( + ( 7'h66)) && (23'h2117 && 5'h15)) ? r134 : 14'h2f50) > r236) != r231)))))) ? 8'hbc : ( ( ! ( (( ( | ( ((r70 * (18'h58fb ? r227 : (19'h4843 <= 23'h461d))) === ( ( + ( (7'h30 ? 13'h163e : 8'hb2))) & ((16'h7ef || 18'hef9) > (28'h3502 < 25'h15a7)))))) - 9'h1ad) - (((r129 | r81) > r41) || (r76 <= 17'h6b6e))))) & ( | ( r125)))) < ( + ( r6)))))) | ((r75 === (4'h3 !== (24'h4381 <= r157))) + r112)) : r244);
#10; r146 = (( ( + ( ( ( - ( 16'h6078)) + (r112 - ( | ( 26'h4c17)))))) <= (( ( - ( ((r203 | (((12'h954 ? ($stime | ( ! ( ( - ( ($time && (9'h1b3 !== 19'h3078))))))) : $time) == 19'h4592) >= ( ( - ( $stime)) > ( - ( 12'h242))))) >= ( | ( ( ( & ( 32'h6a4c)) <= r3)))))) * (6'h14 == ( | ( r84)))) * (((((((11'h412 - r64) === ( | ( ((r141 || ( ^ ( ($time !== $time)))) ^ ( ~ ( $stime)))))) * r242) ? (31'h4adf | (r170 && (($stime * (r75 ^ (4'h3 < 23'h1faa))) >= 14'h2445))) : ( + ( r186))) === r215) % r60) % ( ( & ( (4'h0 || $time))) ^ r179)))) > r82);
#10; r219 = ( | ( (9'h14b * ( ^ ( ($stime ^ 12'h40c))))));
#10; r164 = ( + ( ( - ( 5'h18))));
#10; r197 = (r243 % (( ( & ( r105)) && 25'h3a96) * (23'h1425 | $stime)));
#10; r50 = (((r217 & r223) !== $time) + r81);
#10; r185 = (5'h6 | (r31 >= r194));
#10; r133 = (r210 / r112);
#10; r203 = $stime;
#10; r178 = (14'h258f <= 14'h1fb1);
#10; r235 = ((12'h62a == ((r235 - r30) ^ 11'h49b)) ? ( & ( 13'h1647)) : r237);
#10; r46 = (r241 !== (((((13'h1466 === ( ~ ( (((r106 - r139) >= ( ^ ( r97))) + 12'h69d)))) >= ( & ( ((r94 ^ r251) <= 10'h389)))) && 28'h116b) <= ( | ( ((( ( ! ( ((20'h14cc != ( & ( r45))) != r97))) + $time) == (( ( + ( ( ~ ( (11'h166 % (r79 ^ 15'h4c0a)))))) % ((27'h4742 + (r109 !== ( ! ( (r238 >= ((13'h1bc2 ? 27'h21ab : 12'h85d) / r65)))))) ? (( ( - ( 22'h3a77)) && (r24 === (( ( + ( 24'h42f9)) <= (17'h1d1c >= 30'hed9)) - ( - ( 31'h3f78))))) <= (r57 * (r252 !== r239))) : r117)) % r175)) === r66)))) ? ((r105 - r24) >= ( & ( 6'h3f))) : ( ~ ( ((((r27 || ((r72 != r105) === 30'h5332)) <= r58) < $time) > (r11 ^ ( & ( 28'h5de6))))))));
#10; r14 = r60;
#10; r158 = 3'h0;
#10; r92 = 16'h5cb0;
#10; r168 = (22'h238a == ((29'h737d % ((($stime || (r170 & ((((30'h2570 ? r246 : (r90 == (((2'h2 <= 11'hb6) > (20'h333a ? 3'h0 : 19'h4cae)) ? 8'he0 : ((16'h63a % 19'h22bd) - 12'h78c)))) != (r152 ? (r232 ? (((29'h7a19 >= 28'h28d5) ? (12'hdd9 + 19'h6d4d) : 16'h2ab9) ^ (r196 / (5'h6 >= 31'h55a4))) : r35) : r73)) <= (20'h4ff2 - ( - ( ( + ( ( | ( 3'h0)))))))) % 5'h15))) * r34) !== $time)) || ( & ( 17'h1c43))));
#10; r31 = ( + ( ((3'h6 ^ ( ^ ( (r30 * r118)))) % ( ( - ( ((r131 <= r109) | ( ( - ( ($time % ( ! ( 1'h1))))) + $time)))) / r228))));
#10; r227 = r113;
#10; r69 = ( + ( ( | ( ((r175 * r252) >= 32'h458)))));
#10; r160 = r171;
#10; r99 = r171;
#10; r26 = ($time >= (14'h3a77 ^ r235));
#10; r188 = (( ( ! ( 19'hce0)) ^ (r32 ? (($stime <= (r90 * 15'h5bc5)) < r45) : (30'h7f25 == ( ( & ( ( ( ~ ( ((r137 / 22'h505) && r114))) || r72))) != r210)))) === (r220 | r130));
#10; r210 = r221;
#10; r241 = ( ( + ( r24)) + 10'h16e);
#10; r24 = ( + ( (3'h1 + 27'h6ef2)));
#10; r104 = ( + ( ( ~ ( r45))));
#10; r39 = 12'h75f;
#10; r136 = ( - ( 5'h18));
#10; r186 = $stime;
#10; r202 = 3'h6;
#10; r216 = 25'h70bd;
#10; r208 = r211;
#10; r143 = ( + ( (r114 < r197)));
#10; r118 = ((r187 * r55) <= ( & ( ( - ( ( - ( ((( ( ~ ( 14'h3306)) % (((15'h67f + ($stime ^ ($stime % ( ^ ( ((11'h82 < 18'h7222) ^ ( + ( 25'h1c3b)))))))) - (($stime <= ( ! ( ( ( | ( (29'h166e % 7'h22))) >= 21'h608)))) <= ( ^ ( ($time > r232))))) | r5)) > 2'h2) !== r89))))))));
#10; r234 = 9'h1f5;
#10; r254 = r6;
#10; r39 = ( & ( $stime));
#10; r238 = ((15'h7bb7 >= 29'h70ec) & 22'hf47);
#10; r65 = ((1'h1 - r123) + 12'h583);
#10; r27 = (r221 == (r115 < r95));
#10; r204 = ( | ( 19'h10b));
#10; r232 = (r78 / ( ~ ( (((((8'hfa < r34) * ( + ( (r91 != ($time + (3'h2 ? (21'h3c7a / r249) : (r205 * ((r71 % r26) && r39)))))))) | (1'h0 >= 21'h4545)) != 31'h1e16) !== (((5'hc / $time) == 27'h150d) !== 5'h1)))));
#10; r213 = (r116 || ( ( ~ ( 9'h1cc)) !== (((23'h10fb == (((((21'h5703 * $time) >= ((29'h1274 !== ( ( - ( 11'h56d)) | ( & ( ( + ( (6'h2 + 17'h129b))))))) >= ((( ( - ( r163)) > ((23'h2857 != 30'h64e4) / 5'h5)) || (((23'h7345 <= 21'hdf7) == r154) | r189)) > r117))) > (( ( + ( ( + ( r118)))) / 26'h7e4) <= ( + ( ( - ( ( + ( (( ( ^ ( 16'h3752)) & (11'h2b && 4'he)) != ( & ( r63))))))))))) < ( ( ^ ( r82)) == ( ( ^ ( (( ( + ( $time)) ? ( ( ~ ( $stime)) > r142) : (13'h19ae | ((25'hced != 12'h2ff) !== 30'h290b))) && (r108 > r38)))) || (29'h7ef2 | r0)))) * $stime)) == ($time ? r49 : ((30'h1631 != (r225 - r55)) - (27'h3be0 ^ ($time ? 14'h2bb1 : r25))))) | 9'h1b9)));
#10; r198 = ($stime <= ((2'h0 || (r230 * r145)) || ((r31 !== 20'h7fd3) !== (r98 % ( ~ ( ( + ( (r110 <= $time)))))))));
#10; r8 = 19'h16e0;
#10; r145 = r147;
#10; r125 = r193;
#10; r182 = 1'h0;
#10; r253 = ((10'h2de <= (25'h4a1d & r188)) < r181);
#10; r44 = (24'h2e9a * (((( ( | ( ((r29 & r182) == r131))) / (15'h6295 | 3'h7)) > 14'had2) & r100) & (((7'h1b !== $time) % ((( ( - ( ( ( & ( ( + ( (r208 | ( & ( ( + ( (1'h0 + 30'h6481)))))))))) / 10'h170))) != r170) === ((r216 && 20'h7e5a) || ((r115 && ( ~ ( ( & ( (r68 | (r149 < (r233 < r186)))))))) | r213))) || 15'h789)) && (r59 !== 8'hfc))));
#10; r229 = ( + ( r72));
#10; r155 = 19'h69ae;
#10; r56 = r65;
#10; r84 = $stime;
#10; r76 = $stime;
#10; r235 = ((( ( ! ( r97)) | (29'h463 >= (( ( - ( r73)) | (r115 + $stime)) % 5'h15))) & ((r67 * ((( ( + ( ( ~ ( ( | ( (2'h0 !== ( + ( (((6'h37 === 20'h7815) - (8'h25 & 26'h1ee9)) != 26'h152d)))))))))) % (r128 || (r140 * ( - ( ((1'h0 > r41) == 17'h2448)))))) !== (12'h312 * ( ( ! ( r17)) > 6'h36))) + ((r172 ^ r139) / ( & ( r127))))) || 29'h6f45)) ? (((r63 ^ ((($stime === 15'h3fb7) != (( ( ~ ( ((( ( ~ ( r77)) != ($time <= ( | ( (19'h51cb != 19'hea0))))) ^ ( | ( (((27'h7fb1 ^ 22'h2e65) !== 8'h56) !== r60)))) + (8'h5b === (((10'h93 == r244) <= (14'h2620 && 3'h5)) <= ((22'h77e0 >= 13'hb60) && ( ^ ( ( ~ ( 20'h754a)))))))))) % ((((r106 & r242) | (9'h1a <= 17'h67c)) + ((r119 ^ (r206 < (r194 + (1'h1 <= 4'ha)))) ^ ( ~ ( r34)))) | ( & ( $stime)))) + ( ~ ( (r166 != 13'h147d))))) * ( - ( ( ( ~ ( 3'h0)) % ( ! ( r53))))))) ? (r102 == 3'h7) : (r60 * ( ( & ( ((r30 > (r33 <= ( | ( $stime)))) ? ((r17 <= ( ( - ( 22'h7b0a)) ? ( & ( (( ( - ( ( & ( 3'h0)))) & (r90 != (3'h1 !== 7'h2c))) / (((5'h14 ? 9'h1f : 21'h5421) & 27'h6fd6) || ( - ( r105)))))) : ((7'h52 + (r82 & (20'h218f !== (19'hca5 > 28'h7ddb)))) && ( | ( 15'h5da5))))) === 2'h1) : r187))) || 15'h3aa5))) & r178) : 16'h50d3);
#10; r104 = r197;
#10; r173 = 31'h818;
#10; r205 = (((r254 >= ( & ( (r51 || 10'h2bd)))) | ((12'h778 ? (4'h3 && ((r82 == r40) < ((r68 <= ( ! ( ($time % r254)))) - ( ^ ( ( - ( r179))))))) : (((r196 ^ ( ! ( ( + ( r61))))) == (18'h6246 < r0)) !== ( | ( 23'h7fe)))) ^ r0)) & ( ( & ( ( | ( (10'h31a ? ((15'h5a76 != ((r49 > ( ( | ( (r106 % (( ( ~ ( 28'h4fd6)) - ( + ( 29'h7066))) > ((27'hc41 === 28'hd4b) | (6'h2d & 8'h64)))))) && ((r242 <= 24'h2822) | $stime))) && r169)) != $stime) : r56))))) ^ ( | ( (r180 ^ r203)))));
#10; r237 = (((((4'h5 - ( ^ ( (((((((6'h27 ? ((2'h0 & 25'h3301) < (6'h25 | 9'h1ec)) : r223) | 31'h65e1) >= ((((31'h4659 + 17'h5965) < ( | ( 11'h631))) !== ( ~ ( $time))) * (($time / (10'h7d && 1'h1)) ^ 3'h1))) & 15'h5e87) ^ ( ( ^ ( r233)) && ( | ( 24'h3d10)))) == r49) > ( - ( 2'h0)))))) - 5'h8) && 32'h3aa2) ? r27 : 27'h7c25) ? (25'h6fc1 !== (r8 & (((r82 >= 27'h5432) === ((25'h1d79 < ( ^ ( 22'h53a7))) < r44)) / 2'h1))) : (r98 <= ((18'h56be === 13'h1971) % (r188 | r126))));
#10; r72 = (r29 / ((4'ha - (( ( - ( ((r110 == (r68 != r28)) && 23'h1d5d))) !== $time) & ( ! ( ((32'h122 >= r161) | 16'h36a9))))) < $stime));
#10; r215 = r150;
#10; r32 = (23'h22ba & r68);
#10; r251 = ((((((((( ( & ( ((( ( + ( r230)) || ( ~ ( (10'h214 - 8'hca)))) & 29'h64fb) * r148))) <= $stime) == $time) - ((((((r247 >= r170) > ((r209 - r248) | ( ( - ( 15'h2d06)) ? 1'h1 : (14'h2f73 | 25'h3e87)))) % ( ( | ( r170)) > (r2 === ($stime > $time)))) !== r98) / ( + ( ( | ( r156))))) + ( + ( 30'h1f05)))) != r171) === (23'h16f4 & (((( ( + ( ( ( + ( ((10'h176 % 27'h709d) !== r155))) || ( ^ ( ( ( & ( 8'hbc)) != ( ^ ( 18'h426a)))))))) === r80) !== 23'h72f3) != r118) ^ (r122 - ( ! ( (r57 * (25'h14f1 === (r168 / r149))))))))) | (r65 / $time)) == r250) ? r193 : r163) && 32'h1880);
#10; r16 = ( - ( ( - ( ( - ( r182))))));
#10; r82 = r63;
#10; r173 = 30'h254b;
#10; r120 = (14'hd78 ^ r193);
#10; r133 = ((r37 != r131) ^ r221);
#10; r215 = ((25'hb1f || ( ( & ( (((((r198 | ((28'h6191 / 4'h2) > ( & ( ((((25'h4f79 | 26'h5a16) ^ (3'h2 > 21'h51e3)) * 21'h31e8) >= (r25 / 26'h3a40)))))) !== (r33 % ( - ( (((((15'h2a8c % 1'h0) + 32'h5653) + r172) || $time) ^ 23'h5215))))) == r173) != (23'h1aaa == (13'hccb ? r24 : (r86 && ((( ( ! ( (r126 !== (28'h2588 == 29'h7d09)))) == (24'h10c2 > 22'h5f23)) || ( ! ( ( - ( r16))))) % ( ( & ( r0)) ^ r129)))))) <= 3'h0))) - r115)) && ( ^ ( ( + ( ( ^ ( $stime)))))));
#10; r98 = r156;
#10; r129 = (((r44 <= (((r14 > ( - ( r236))) < ((23'h5704 > (r163 === ((r136 != ( ( | ( 16'h7a29)) >= 21'h19b8)) !== (31'h53bd <= r38)))) != ( & ( 24'h332a)))) > (((((((r75 >= 23'h659f) !== (29'h2824 > r29)) <= ( + ( r103))) - (r69 * ((r222 != ( & ( r11))) <= $time))) || (r252 - r29)) >= (9'h0 != 30'h7bb1)) || ( ^ ( (r204 != r33)))))) + $time) & (( ( ~ ( r161)) == 18'h371b) - ( ( + ( ( + ( ( + ( ($stime > 10'h349))))))) == $time)));
#10; r224 = (25'h3bb6 ^ ((r169 !== ( + ( (($time <= r231) ? 12'h7e7 : ( ( ^ ( ( ~ ( r186)))) >= ( ~ ( ((r202 && ( & ( (11'h3f4 > (r148 < 24'h6a71))))) <= r104)))))))) == (((2'h2 % (((r226 < 2'h3) | (((2'h0 + (8'h1 || 7'h52)) !== ((r234 | ((( ( ! ( 12'h2fa)) + 23'h54ed) >= ( ! ( ( - ( 6'h1e))))) >= r230)) != 20'h7209)) - (14'hc55 % (r243 != r235)))) & (10'h110 > r103))) == ( ! ( r102))) || $time)));
#10; r15 = r135;
#10; r18 = r148;
#10; r179 = 13'h807;
#10; r144 = r116;
#10; r100 = r116;
#10; r44 = $time;
#10; r133 = 8'h67;
#10; r119 = $time;
#10; r155 = ( ! ( ( + ( r55))));
#10; r241 = (r252 == ($time || r154));
#10; r162 = 21'h4542;
#10; r154 = 25'h3c0a;
#10; r172 = ( & ( r130));
#10; r152 = ( ~ ( r25));
#10; r229 = r1;
#10; r238 = $stime;
#10; r180 = 21'h942;
#10; r231 = r199;
#10; r39 = r247;
#10; r46 = (23'h5bc != 3'h0);
#10; r166 = ( | ( ( | ( (13'h8cd ^ (((r12 || ( ( | ( 10'h14b)) && 12'h430)) === r195) & (30'h28c0 % ( ~ ( 27'h521b)))))))));
#10; r23 = r20;
#10; r102 = ( ( | ( r216)) | 27'h7337);
#10; r223 = ((1'h0 > $time) % r228);
#10; r42 = ( ^ ( ((r181 === r129) && ((r204 !== ((r112 ^ ( ( | ( 9'h199)) <= (r75 == ( ( ! ( 28'h5b63)) < ( ~ ( ((r96 <= (((15'h6ad0 !== 13'h5a1) <= ( ~ ( 24'h2def))) == ( ( ^ ( 24'h146e)) / (28'h13b1 >= 11'h94)))) || ( + ( (( ( ! ( 27'h51f3)) > ( & ( 10'h2c7))) - ( ^ ( ( ! ( 1'h0)))))))))))))) == ( ( ^ ( (( ( ^ ( (((32'h4dc3 - (r216 - 27'h503c)) <= 11'h1fd) | ( | ( r46))))) && 22'h5f72) === r74))) !== (r190 / ((r33 || ( | ( ( ( + ( r53)) !== (28'h1cb9 || ( ( | ( (1'h1 && 27'h699))) * ( & ( (16'h3dd0 === 17'h5fae))))))))) ^ ( | ( 12'h1de))))))) < r38))));
#10; r174 = ( & ( 12'h666));
#10; r79 = ((r135 && r189) != ( | ( r186)));
#10; r150 = (3'h3 * ((r251 !== ((9'h1ef - $stime) - (( ( - ( ( - ( r49)))) || r241) == ((( ( - ( 32'h4db1)) == ((r247 !== ((($stime + ((16'h42ad != 23'h2b27) ? r203 : (17'h2b91 % 27'h7fd3))) + ( ( & ( ( | ( 12'ha1b)))) !== ((21'h4286 % 22'h536e) ^ 16'h6608))) ? $stime : 14'h380a)) | ( ~ ( ((r115 & ((r16 + (30'h5605 & 17'h245)) - 19'h4ee4)) !== 14'h899))))) != ( ( ! ( r204)) >= (r58 + ((1'h0 === 8'h8b) + ((((9'h10 === r7) / r217) <= 5'ha) * r254))))) == ( ( & ( 6'hd)) && 11'h440))))) ^ ( - ( (r27 & ((r177 === (r226 != $stime)) | 9'hf))))));
#10; r248 = r209;
#10; r5 = r51;
#10; r21 = 12'h97c;
#10; r51 = ( ( | ( ( ! ( (r174 > ( ( - ( 8'h2a)) >= ( ( + ( (( ( ~ ( r65)) + 8'h41) ^ 28'h7bc3))) / (13'hf60 * r126)))))))) >= ( ( - ( $stime)) <= ((r14 ^ (r25 >= 10'h344)) & ( ( - ( 21'h2549)) <= ((22'h7049 > 4'hd) ^ r172)))));
#10; r158 = (r89 !== (( ( ^ ( ((r215 <= r205) * ((r142 % 15'hce6) < r253)))) | r84) + ( & ( (r75 > ( - ( ( ( ! ( ( | ( (r183 > 26'h7d82))))) >= ( ~ ( (((r79 % ((r124 === ((r168 * ( ~ ( 19'h6332))) <= ( + ( ( + ( 32'h4365)))))) & ( ( ! ( ( - ( ( + ( 31'h67f5)))))) && r70))) >= (1'h1 & ( ( | ( ( ! ( $time)))) != ( & ( 7'h57))))) + r71)))))))))));
#10; r180 = ((r27 ? ($time - ( - ( ( ^ ( r86))))) : r20) - (( ( ~ ( (( ( ~ ( (30'h1d1e == ($time == (23'h196b === r86))))) & (21'h7750 >= ( ( ~ ( ( ( ! ( ($stime == 25'h47c6))) % ($stime && r93)))) / ($stime && ((r237 || r84) ^ ( | ( ( + ( r121))))))))) % ( - ( ( ( + ( r158)) + r54)))))) == ( ( | ( 16'h315f)) >= ((((( ( + ( ( ~ ( r74)))) + 20'h7b7f) || ( & ( ( + ( 23'h4708))))) | (( ( & ( (4'h6 === r209))) || 13'h9c8) / r229)) ^ ( | ( ((4'hf ? 24'h4865 : 16'h6051) > (10'h250 <= 16'h354))))) || (r139 === (6'h3e <= 16'h59a))))) || (r80 ? (($time != ( ~ ( ( ~ ( (r243 ? ((28'h741c % r164) + ( & ( ((( ( & ( r252)) || 26'h14dd) && r76) % r123)))) : 12'h35b)))))) ? (18'h36a6 === r202) : (((((27'h473b | r219) * r121) | (r30 >= (( ( ! ( 21'h52b8)) != (3'h0 <= (r38 % (((4'hf === 17'h45ca) % ( - ( 15'haa3))) === ((20'h6ddf > 31'h6ad1) !== $stime))))) < r48))) > r110) >= 6'h3d)) : r163)));
#10; r72 = (( ( ~ ( ( ( ~ ( ( ( - ( ( & ( ( ^ ( r217)))))) | (r180 == r234)))) <= 24'h480a))) % $stime) !== (24'h5c74 > ((r244 | ( ( ~ ( (((((23'h971 / ( | ( (13'h121f <= ( ( - ( 28'h6b51)) >= (12'hcfc || 2'h1)))))) ? ((r11 | ( - ( 32'h450d))) > r254) : ( ~ ( $stime))) + (r74 & r104)) || ( - ( r235))) | ((12'hafb % r158) - 17'h7d6b)))) ^ r225)) ? ( ! ( ( ~ ( ((((((((((29'h532 <= 16'h3d4b) ? r138 : r213) || (16'h52cf > (10'hc9 + 1'h1))) || $time) >= 16'h2a91) | ( & ( ( ^ ( r43))))) < ( ^ ( ( | ( (r91 | 2'h3)))))) / r186) * ($time / (r182 != r171))) < (( ( ! ( 19'hf53)) % r173) ^ r90)))))) : $stime)));
#10; r162 = (13'h1684 !== 20'h5bae);
#10; r125 = $time;
#10; r65 = ((21'h5040 % ( & ( (r168 / (r250 * r214))))) <= (21'h5bf != ( ~ ( $time))));
#10; r132 = 14'h1f62;
#10; r35 = ( ! ( ( - ( (((((((8'h0 % ((( ( - ( ((17'h4f6 || 23'h241d) * (24'h3ec2 <= 31'h7ec8)))) / $time) >= (r114 & r213)) == (10'h33f === r79))) ? ( ~ ( 16'h7540)) : ($stime || ((r144 - 20'h7607) !== ( & ( 6'h7))))) == ( ( ~ ( ( ^ ( (r251 / ( ( ~ ( $stime)) < (((12'hcdd & 7'h6f) && (18'h7be < 16'h51a7)) || ( ( ! ( 31'h5b74)) ^ r127)))))))) + r254)) - r158) === ( | ( 11'h317))) ^ (r88 - ( ^ ( (( ( ^ ( r179)) | ((r137 <= r77) === ($stime == ( ( + ( (r190 !== ( ! ( 24'h667d))))) ^ $time)))) / r135))))) | (((r151 || ( ^ ( $stime))) >= r38) == (((( ( + ( ( ( - ( 3'h5)) > (((((11'h7ed > 23'h4848) + (12'hbf8 / 5'hb)) ^ r115) && ((32'h4a9d | (30'h66c5 & 30'h3e62)) >= 22'h14fe)) > (((r54 | (19'h3af4 ? 20'h63c8 : 3'h6)) | ((5'h19 | 2'h0) >= ( ~ ( 2'h2)))) === ( ( ^ ( ( ~ ( 5'h1d)))) != (r8 == (27'h69be % 32'h3b05)))))))) > 17'h6896) <= $time) * 9'h17e) >= (r253 | r11))))))));
#10; r42 = 16'hf15;
#10; r139 = ((( ( & ( (14'h3f9d === ( ^ ( 21'h5f2f))))) + 2'h2) % 22'h5b3c) !== ( | ( ((( ( ! ( r51)) / r88) ? 9'h1a3 : $stime) > 9'h194))));
#10; r8 = ( ( & ( 20'h40b8)) ? ( ( + ( (( ( + ( ($time | ((3'h4 <= r197) == r234)))) != r4) - (r114 * 23'h46dc)))) % r68) : r172);
#10; r181 = ( - ( ($stime % (23'h1d8f && ( - ( ( ( ^ ( $time)) | (r108 & r26))))))));
#10; r159 = (((18'h535a % r30) * r65) >= ((( ( & ( ((((((r105 || 31'h4634) * ((r174 == (r61 || ( & ( ( + ( 6'he)))))) <= r233)) / $stime) || (((20'h55e8 * 20'h57da) != 27'h10ab) && (((( ( ^ ( (25'h574b != 25'h59bb))) % ((5'h13 === 17'h4256) !== (28'h5ecc !== 1'h1))) <= ( | ( r173))) !== $stime) || (( ( ! ( ($time >= (12'h42c | 23'h60eb)))) % (($stime >= 14'h23de) == r219)) > r65)))) && (18'h7c43 !== r96)) != (( ( - ( ( ( - ( ((r100 ? ( & ( r142)) : ( - ( r30))) === r236))) < ( ! ( r38))))) | $stime) - (( ( | ( r68)) < ( ^ ( (29'h6ea5 === ((((10'h243 === 31'h625f) > ( ~ ( 26'h75a))) - r95) <= ( | ( (r92 === $stime)))))))) > ( & ( ($stime >= r76)))))))) | r92) ^ (10'h2f2 !== $stime)) >= r103));
#10; r35 = (31'h1e3a * 13'h289);
#10; r50 = ( ( + ( ( ( - ( 13'h1945)) & ( | ( ( ! ( r128))))))) * (((($stime >= 7'h61) || (((( ( ! ( (r180 > r44))) * (($stime >= (( ( + ( r106)) == ( ~ ( 32'h59e7))) || 5'h9)) && 13'hcd)) < ( ( & ( 15'h5791)) === ( + ( ($time - (((( ( ~ ( 30'h6092)) & r184) + 31'h27e1) == ((31'h1dfa + 7'h68) != ( ~ ( 22'h10ab)))) & (16'h30ab / r158))))))) ? 12'hcb7 : (31'h4c6d !== (26'h4e33 < ((20'h1dcd / ((( ( & ( (23'h3c7c < 4'h6))) % ( ( | ( 18'h6b37)) / (31'h56e7 - 9'h1b5))) - r174) >= 12'h281)) !== (r100 * r11))))) ^ r201)) * ( | ( 21'h41a0))) <= r130));
#10; r17 = ( & ( ( + ( r76))));
#10; r99 = ( ~ ( ((((r50 + (((r49 / (($stime * $stime) >= ( | ( r137)))) > (r27 <= 9'h151)) / ((((((r222 > r101) % r93) + ( ^ ( (3'h2 || ( - ( 28'h2340)))))) == ( ( ^ ( (r62 | (r201 === $time)))) <= 18'h6c9e)) > ( | ( r235))) <= ( ( ^ ( (((22'h402 | 12'h9b) | r92) * (r181 / ((r17 & $time) > r160))))) != r20)))) & (((r109 >= ((r237 == ( ( + ( ((((27'h7c62 > 5'h10) || 28'h4e87) | ((17'h62af === 21'h4f4) < ( ! ( 22'h4838)))) >= $stime))) && 23'h2eb3)) ^ ( ( ^ ( (r112 < (r212 > 6'h3d)))) ^ ((( ( + ( 8'hcc)) && 22'h6bf5) >= (r109 <= (((8'h3a == 25'h11d) == 19'h19b8) / ( & ( $time))))) ^ (32'h174d % 31'h75c7))))) / ((r37 >= ( ( ! ( ( ~ ( (r0 <= ((r215 * 27'h649a) + 20'h7c51)))))) < r221)) !== ( ^ ( r159)))) === r133)) + (23'h38d1 ? ((($stime ? ( - ( ( - ( ( ( & ( ($time < r66))) ? r170 : (( ( ^ ( ((20'h6ff5 * 26'h4341) - r78))) / r196) < r246)))))) : ( ( + ( ( ( | ( ( ^ ( 18'h3e9)))) ? r129 : r245))) % ( ! ( r128)))) / $time) * r156) : 16'h1426)) == 9'h114)));
#10; r102 = ( ^ ( ( ^ ( ((r211 ^ (r229 === r249)) < (((r17 * r174) * r229) <= ( ( & ( 26'h56cf)) || $time)))))));
#10; r7 = r109;
#10; r195 = (r100 - r246);
#10; r248 = ( ! ( ((r14 === (((r120 > ( ( | ( r100)) !== ( ! ( 2'h2)))) > (( ( & ( 6'h18)) % ( | ( 1'h0))) && ( + ( r251)))) / ( ~ ( ((r233 - 24'h7a6a) / r56))))) === ( ( - ( r104)) != ( ^ ( 1'h0))))));
#10; r160 = r14;
#10; r164 = r57;
#10; r26 = ( ~ ( r63));
#10; r20 = 27'h7948;
#10; r33 = (((r235 > ( ( + ( ((22'h4078 % 28'h43d5) ^ ( ( | ( ( + ( r216)))) == r196)))) || (((14'h3a11 - $stime) == ((r45 - 5'h5) ^ ( ~ ( ( ( + ( (((((11'h70b | 19'h604f) > (29'h2b8 * 4'h8)) ^ r130) && ( ( & ( (13'h2b5 - 14'h34f9))) ^ ($stime < 10'ha5))) < r19))) * (((( ( ^ ( (7'h51 === 9'h7d))) / ( & ( r242))) * ( + ( (r120 * (31'h3f97 != 27'h5c58))))) & 6'h2f) < ( ( & ( r148)) ^ ( + ( 14'hfd5))))))))) == ( ! ( r231))))) + r248) && ((r48 | (r187 | (r221 == ((r42 & r204) == r140)))) < r15));
#10; r221 = (16'h49d1 || (r58 + ( ( + ( ( ^ ( r240)))) > r5)));
#10; r245 = ($time | $time);
#10; r80 = r72;
#10; r47 = $stime;
#10; r43 = r104;
#10; r128 = r105;
#10; r253 = r67;
#10; r145 = r81;
#10; r126 = 15'h9eb;
#10; r24 = r162;
#10; r233 = $time;
#10; r182 = ( ! ( (($time ^ (r171 === 11'h452)) - r95)));
#10; r94 = r219;
#10; r231 = (((((r234 == r75) - ( ^ ( $time))) | ( ( & ( ((((( ( + ( ((((19'h3cbc != 29'h50b3) === r179) === $time) >= 31'h7c7b))) > ( ( & ( ((r174 & (3'h0 - 18'h4c8f)) / 23'h16fc))) !== ( | ( ( ^ ( ((32'h1b5c * 24'h1c03) > r120))))))) || (( ( ^ ( r53)) != ((((8'hec <= 9'h169) !== $stime) === ( ( - ( 16'h304e)) < (26'h3834 <= 18'h58bc))) ? 25'h6ca3 : 27'h60a2)) >= 7'h74)) - $stime) !== ( ( & ( (r193 <= r106))) && ( & ( ((9'hc || r173) != r85))))) / ( ~ ( ((r82 / 25'h5809) <= ((r166 % (10'he3 - ( ! ( ( ( ~ ( ( + ( 21'h5ea1)))) ? 32'h6caa : $stime))))) === (($time !== 15'h2f0c) > ((r134 && r13) & r131))))))))) < ((19'h706d && ($time & (($time === 18'h786a) <= 13'h1ed6))) ? (r176 == r217) : (r15 < (19'h4b23 ^ 20'h3584))))) ? 19'h46f1 : 16'h10bc) ^ (28'h57a5 >= ( | ( $stime))));
#10; r64 = (((( ( & ( ((((19'h1c36 >= 27'h1fc7) ^ r191) <= 18'h479f) && ((((((17'h38f5 / 16'h7871) > r19) < ( ^ ( ( ( ! ( r255)) <= ((r196 / $time) ? ( & ( r91)) : $stime))))) - (15'hc67 ^ ( ( ! ( (( ( | ( 10'h2bd)) == (9'hba > 4'h8)) + r104))) >= ( & ( r46))))) !== ( ( & ( r158)) - (( ( & ( 27'h5bca)) ^ ( ~ ( r185))) === (r208 | ( ! ( (((31'h3393 && 24'h16f4) <= (14'he7a / 15'h3c50)) & r73))))))) != ( ( ! ( 5'h14)) >= ( ( ^ ( 25'h2f7f)) / r25)))))) + ((7'h32 ^ (( ( + ( ((((r171 == ( - ( (24'h24c9 != 27'h188c)))) % (21'h1cd3 !== ((21'h4f82 !== 5'h5) !== (30'h592c && 31'h4d6)))) & ( ( | ( 32'h10e6)) * (r51 < (2'h3 && ( ! ( 9'hb5)))))) >= ((( ( - ( r100)) + (r94 < (4'h9 - 19'h7687))) / 30'h3d99) < ((22'h1717 <= (30'h7a58 ? 23'h26de : (2'h3 * 32'h15f2))) + r226))))) || r220) ^ r147)) & r163)) && 25'h4a4b) === r71) | 13'h13da);
#10; r247 = ((r64 >= (6'h6 - 30'h1466)) < 10'h89);
#10; r80 = 19'h4198;
#10; r186 = r249;
#10; r95 = r153;
#10; r32 = 17'h76a7;
#10; r81 = ((r230 & r127) >= ( ( ^ ( r166)) == (20'h625d % r106)));
#10; r150 = r47;
#10; r16 = ( ( ! ( ( - ( r127)))) == (20'h2d74 ^ ((( ( & ( ( + ( ($time === ( | ( r121))))))) - r238) | ((26'h7f81 | r147) || (16'h564f & r121))) | 29'h30a3)));
#10; r159 = 7'h5;
#10; r50 = r178;
#10; r198 = (( ( ! ( $stime)) <= 30'h3341) >= ( ~ ( (14'h2cc8 && ((((r238 === ( - ( ((18'h3731 || (21'h6044 > r225)) + $stime)))) && $stime) < ( ( - ( ( & ( ( ( + ( ( ~ ( 31'h5c4f)))) * r224))))) / (( ( | ( 17'h3bc0)) / r141) & r154))) ^ ((r176 + ((18'h3d71 === r214) ^ ((($stime >= r179) | ( + ( 6'h28))) % ((r91 + ((r10 <= ($stime % ( ! ( $stime)))) & (( ( & ( (24'h274b + 5'h1e))) == 30'h4efa) - (r23 > r185)))) !== (((r236 <= ( ~ ( ($time ? (20'h6978 > 25'he4c) : (29'h18de | 13'h19a7))))) & (($time > ((27'h7cd5 || 10'h2d1) / ( | ( 7'h69)))) != (((18'h6172 | 19'h59d4) == (30'h4c9b && 19'h2001)) !== ((15'h73ea % 20'h1953) ? r244 : r76)))) % (r143 ? (r59 > ( ^ ( r141))) : ((19'h13f7 < ( ^ ( (26'h7eda ^ 1'h1)))) != r136))))))) && $stime))))));
#10; r100 = (((($stime ? r212 : ((r115 >= 13'hd24) === (( ( & ( ( + ( (( ( + ( r7)) != ((((17'h3105 ^ 16'h5f7b) != 28'h7cd2) && 7'h2) / ((r122 ? (20'h5bb0 != 26'h66d1) : (32'h251d * 30'h1913)) === r221))) / 4'h6))))) ? ((r54 && (24'h50eb / 3'h0)) - (r249 | r87)) : (( ( ^ ( ( ( ~ ( ( - ( ((18'h165 !== 18'h7eb7) || (29'h26d4 && 5'h6)))))) && (r36 <= (r140 % ((13'h1b93 && 10'h97) - (9'he6 % 10'h30e))))))) * ( ! ( ((((4'h3 && (14'h151b || 32'h7a7e)) * r208) % ( ^ ( r215))) < ( ^ ( 29'h2bb1)))))) + ((r123 <= 29'h381e) >= ((r177 <= $time) && 22'h6707)))) > r183))) <= (((30'h2485 > (7'h5b * (((r8 != 27'h4ad2) & r75) == r104))) & ((r222 + r255) + 2'h1)) > 7'h48)) < r195) & (r232 + ( - ( ( | ( 5'hc))))));
#10; r111 = $time;
#10; r220 = ( ( & ( 32'h47c4)) != ( ( ~ ( (($stime <= $stime) >= (r22 !== ( ( | ( 15'h82b)) | r125))))) - 20'h65a5));
#10; r103 = ((r212 & (r10 != (2'h2 | (r201 - ( ! ( ( ^ ( (r100 && (r69 % (r86 + 25'h2418))))))))))) % ((5'h5 || 3'h7) & (( ( + ( ( & ( (r236 + ((r25 & ( & ( ( ( ~ ( (29'h682e + ( ~ ( (23'h4ffa % 5'h7)))))) == 32'h6eb2)))) < r202)))))) == ( ^ ( 7'h56))) % (32'h14d5 + ( - ( ((3'h7 | ((((( ( - ( 27'h237d)) != ( | ( ( | ( 25'h1e5a))))) ^ ( ( ^ ( (r244 === (28'h502d - 32'h2e48)))) / (r147 < r167))) && r42) > (( ( ^ ( (((18'h3679 === 24'h3b03) * (1'h1 - 17'h6b4)) | 3'h1))) != r141) < ( ( + ( 30'h1484)) & ( | ( (((6'h3b === 20'h4cb9) % (23'h7809 !== 5'h7)) > 23'h79ca)))))) <= ( ( ! ( r254)) - r79))) <= ( ( + ( (r25 && $time))) % ((((22'h51e6 && (r206 * $stime)) !== r38) | r148) - r127)))))))));
#10; r55 = r221;
#10; r206 = r156;
#10; r180 = ( ~ ( 16'h2225));
#10; r67 = ( + ( (((r203 && r69) === r123) != r202)));
#10; r75 = (( ( | ( ( ( | ( r9)) < (11'h3d9 === ( ! ( ( ( ^ ( r99)) === r224))))))) == 28'h2fb6) && ((30'h8c3 - r134) < 23'h5849));
#10; r217 = (18'h2761 % (r56 | (($time < (20'h6ce0 * ( - ( (r235 * (( ( - ( ( | ( ((((6'h3a + 29'h3b2e) == 12'h6d5) + r79) > (r156 && ((26'h257f == 2'h2) || (9'h72 == 16'h41d9)))))))) * ( ( ! ( ((r48 - ( + ( (2'h3 + 14'hb38)))) ? r166 : r136))) !== ( | ( ( + ( r74)))))) != ($stime > ((26'h39cb !== r112) % ( ( - ( r124)) == r221))))))))) < r23)));
#10; r14 = (r167 <= ( ! ( (r106 >= r22))));
#10; r254 = (r246 + ((((r132 && ((( ( + ( 6'h0)) < r228) === (25'h5358 === ($stime % 15'h7d8d))) == r28)) || $stime) ^ (r24 * ( ^ ( 13'h402)))) && ( ( | ( ((r100 + $time) === r249))) != ((19'h52e8 - 16'ha15) & (((1'h0 <= 23'h39c8) % ((19'h3f6b > ($time & r181)) >= r47)) + (( ( + ( ( | ( 2'h2)))) === r63) == r48))))));
#10; r231 = $stime;
#10; r198 = ((13'he17 === (( ( ~ ( ( ^ ( (r249 === ( | ( ((( ( ~ ( ( | ( ( ( ! ( 24'h53e3)) & (21'h3e5d != 22'h7f09)))))) >= r72) == r147) > ( & ( ( ~ ( (7'h5c == r217))))))))))))) != r206) && ( ( - ( ( & ( (r203 / r196))))) & ($stime ^ ((7'hf && 6'h13) < 31'h2e8e))))) <= ((r29 >= r103) == 29'h4b73));
#10; r208 = (r245 * 21'h176);
#10; r232 = ( ! ( ( ^ ( (r195 <= r240)))));
#10; r120 = $stime;
#10; r25 = $stime;
#10; r36 = (( ( | ( ( - ( ( ( | ( r63)) & (( ( | ( 10'h279)) % ($stime != r51)) != ((( ( ! ( r108)) ? (r28 && (r75 / 13'h302)) : ( | ( (r19 == 27'h2750)))) - (r135 + r97)) || $stime))))))) && ( & ( 29'h78e2))) >= 9'h9c);
#10; r126 = 27'h5db1;
#10; r7 = 27'h61d3;
#10; r254 = ( ^ ( 6'h32));
#10; r76 = r9;
#10; r106 = r11;
#10; r115 = ((r69 > r37) && (r35 == r169));
#10; r190 = r31;
#10; r39 = ( + ( (15'h2c29 ? r216 : ((13'h928 != ((r216 | r94) / ( ! ( (r8 !== (r209 & 8'hc6)))))) + 29'h1e5d))));
#10; r77 = r166;
#10; r211 = r156;
#10; r229 = (8'h6d >= ( ~ ( $time)));
#10; r219 = ((r171 ? r116 : 25'h2ba2) | r103);
#10; r178 = ( ( - ( (( ( - ( (r111 || r145))) ? ((( ( & ( r207)) + (r100 + (r85 / (29'h7a89 == 29'h73df)))) != (r191 === 30'h24b3)) >= (r163 == ((r136 % ( ( | ( (11'h78f && ( | ( (2'h1 >= ( ( - ( 10'h1d4)) > (7'h39 % 26'h14d3)))))))) + r43)) / ($stime >= r192)))) : (r211 === 10'h381)) != ( - ( 6'h1f))))) > (r63 !== ( ~ ( (r71 / 15'h32a7)))));
#10; r235 = ($stime === r52);
#10; r181 = ( ! ( (( ( & ( (r72 | ((r82 - (r122 - r110)) / 3'h1)))) > (1'h0 != ( & ( r117)))) % r35)));
#10; r115 = 31'h222c;
#10; r21 = 10'hbc;
#10; r202 = (( ( & ( $time)) > ((r141 || (28'h91 || ( - ( 25'ha3e)))) || ((r78 & ((r252 > ( ~ ( 2'h1))) > (r235 ^ $stime))) && ( & ( 9'hbc))))) == $time);
#10; r255 = ( & ( 30'h67f1));
#10; r65 = 13'h342;
#10; r208 = ( & ( (9'h148 !== ((((r86 - r205) | 16'h10c7) + $stime) / (r145 / ( ^ ( ( & ( 24'h4f19)))))))));
#10; r25 = (r242 ? ( ( | ( (((((9'hab + (r120 & ((( ( + ( ( - ( r5)))) ? r90 : r232) % ( ( | ( (11'h6ec ? r150 : r41))) && 22'h5c1a)) !== ((12'hd86 * ((4'h5 + r76) * $stime)) != ((( ( | ( 28'h378b)) === 5'h11) != r235) >= 5'hb))))) != (((r232 !== ((r240 * r116) * ( ^ ( (((18'h6629 < 31'h6fe7) * (28'h76b ^ 11'h18d)) > 32'h79d2))))) % (17'h4ad6 ? r19 : 29'h25f7)) | 28'h695e)) <= r176) !== 3'h2) === (9'h14f !== ((r71 % ( - ( (r82 > ((6'h1b ^ ( & ( 22'h355c))) | 21'h4af7))))) != ( + ( (( ( & ( ( ( + ( $stime)) | r247))) <= 12'h5ff) | 5'h1a)))))))) < r124) : ( + ( 25'h1324)));
#10; r216 = 16'h6943;
#10; r223 = $time;
#10; r182 = r155;
#10; r64 = (r73 - 31'h2134);
#10; r254 = 9'hfb;
#10; r180 = ( ( & ( ((r246 < (( ( ! ( r9)) <= r190) >= r25)) % (r150 != 6'hf)))) + 13'h1361);
#10; r26 = (( ( | ( r12)) | r21) - ( ~ ( ( ( ~ ( r129)) % (r99 < (r227 != (17'h1614 && ((r18 >= ((r85 % (r91 | r23)) <= 21'h2add)) === ( ( - ( r175)) === 15'h60cd)))))))));
#10; r58 = (((26'h4eb6 >= r67) & ( ( - ( ((($stime < ( ^ ( 24'h5968))) != ( ( & ( ( ^ ( r173)))) <= (($stime * (( ( + ( ((r216 > $stime) & r144))) || r153) & ( | ( ( ^ ( $stime)))))) <= 22'h5feb))) % ( ( ^ ( r192)) + ( + ( 9'h140)))))) | 16'h6670)) === ( ! ( ( - ( ( - ( ( ( | ( ( + ( ( + ( r128)))))) / ((( ( - ( (4'h3 !== r13))) | r212) >= (r48 + (18'h2621 != ( ( ! ( (6'h2b | r84))) / ((( ( ! ( ( - ( 1'h1)))) + r38) && ( ! ( r39))) == 21'h46a))))) != $stime)))))))));
#10; r227 = 4'ha;
#10; r151 = r208;
#10; r180 = (((r193 || r112) & (r198 !== r202)) | r46);
#10; r81 = (((r224 <= 27'h4c16) ? ((r96 == ((($time % (r59 && r245)) !== 28'h5b91) < ( | ( ( ^ ( 22'h78)))))) + 30'h1c62) : (r225 < ((18'h2d37 < ( ( ~ ( ( ^ ( 25'h73f9)))) == 4'h5)) ? ((r158 & r216) - (r243 !== r243)) : 24'h2bb7))) > 1'h1);
#10; r143 = r52;
#10; r222 = (( ( ^ ( r10)) + (22'h3a15 && ( ( ^ ( r163)) < 4'h8))) != ( ! ( ((r119 % ((r184 || ((((((18'h62e0 ? ((r123 > r7) * ( ^ ( r81))) : ( + ( ( & ( r60))))) === ( ^ ( (2'h2 ? ((18'h261a - 14'h226f) !== (10'h88 / 25'h5b0e)) : ((16'h4605 * 22'h6ac6) == 14'h32ee))))) % ((r135 * 25'h303b) && 13'h143b)) % r94) & ( ^ ( r16))) * ( - ( ((((((r183 & r178) && ( ( ! ( 19'h2f4b)) * (31'h7e35 + 12'h73e))) > (((18'h5c0c === 28'hb1c) > (1'h1 || 5'h1a)) ^ r54)) ? r222 : 25'h54cf) | (r131 - (r248 & r78))) == 18'h5932))))) % r73)) < r194))));
#10; r241 = $stime;
#10; r4 = ( ( & ( r125)) <= (r41 ? ((23'h312d != r35) > r184) : ((19'h2838 + r31) == 25'h25bc)));
#10; r65 = r4;
#10; r68 = r86;
#10; r46 = 2'h2;
#10; r123 = ((((r247 || ($stime | r248)) ? ( ~ ( ($time & (r73 === r43)))) : 5'h16) > 25'h4e87) == r2);
#10; r177 = $time;
#10; r15 = ( ^ ( r236));
#10; r236 = 25'hdf4;
#10; r186 = ( ( ^ ( (r163 % ((r186 ^ ( ( ! ( $stime)) * $time)) && r104)))) | 21'h3b98);
#10; r238 = (r170 + 1'h0);
#10; r167 = r11;
#10; r47 = ( ~ ( (r164 !== (27'h2b93 | 19'h3f3))));
#10; r152 = 13'h1ae6;
#10; r136 = 11'h27f;
#10; r87 = r50;
#10; r44 = (r105 && ( ~ ( (((( ( | ( $stime)) / ( - ( 21'h58a3))) * 18'h2973) > ( ( - ( $time)) ? (((15'h3f4c ^ (r180 - ((r233 * $stime) !== r28))) | 15'h4cb7) - (r234 * ( ( ^ ( 7'h4d)) > (((r200 && 23'h14a0) != r159) <= ((( ( & ( ( ~ ( $time)))) - r226) | 16'h45eb) - r22))))) : r232)) === r165))));
#10; r85 = (r147 > r18);
#10; r231 = ((8'h94 ^ 4'h5) ? (((r200 || ((($stime & r75) && 11'h0) & 32'h44a8)) || r49) - ( ^ ( (r204 | r161)))) : ( ( + ( (14'h1ec9 === ( - ( ( & ( (16'h1ac3 == r40)))))))) <= (( ( - ( r196)) % ( | ( ((30'h5eb9 | ( ( ^ ( ( ^ ( (((((15'ha3e + 3'h1) & r235) & (31'ha50 ^ ( + ( 21'h1246)))) != 4'ha) != ( ^ ( (6'h11 != r84)))))))) / ( ( ~ ( (r199 - ((((19'h6553 + 29'h2692) - 11'h87) & r215) != r247)))) & r129))) <= 10'h2d8)))) ^ (r63 == r161))));
#10; r243 = ( + ( ( ! ( ( ! ( ($stime >= r141)))))));
#10; r225 = ((r227 ^ ( ^ ( (((r211 != r246) != 1'h0) / ((r151 / (r189 - ((2'h0 ? ( | ( ((17'h15be != 25'h57cd) || r18))) : r130) <= r133))) > ( ( - ( r177)) & r100)))))) ^ (30'h29af ? r155 : r154));
#10; r188 = r9;
#10; r20 = 7'h30;
#10; r47 = r47;
#10; r58 = r172;
#10; r25 = 14'h2732;
#10; r120 = r209;
#10; r234 = r122;
#10; r109 = 32'h6179;
#10; r220 = $stime;
#10; r62 = 20'hf98;
#10; r123 = 30'h434c;
#10; r157 = ((9'hdf !== r221) != (r158 ^ 27'h7b5b));
#10; r118 = r28;
#10; r225 = $stime;
#10; r144 = (r5 == ( ( & ( $time)) < ( ( + ( 19'h1ed0)) != 2'h1)));
#10; r134 = ( ^ ( 4'h6));
#10; r6 = ( - ( 21'h63eb));
#10; r81 = ( + ( ((((( ( + ( (($stime != (( ( - ( (30'h417 * 9'hd2))) !== (r98 && (31'h2b9b >= ( - ( ( | ( 4'h2))))))) / ( ! ( 21'h3fae)))) * r7))) !== ( ! ( r89))) + (32'h6ea2 + r41)) % (6'h2b === ($stime - ((12'h589 || 3'h4) | (((31'h73e9 ? ( ( | ( ( ( - ( r222)) >= ($time + (13'h126a * 30'h491b))))) ? r80 : ( ! ( ( ( + ( (20'h15ba >= 20'ha2))) >= (1'h0 === 32'h7b25))))) : ( + ( ( ( + ( r171)) / 14'h2d54)))) === 20'h2b36) ^ r30))))) !== ( ( ^ ( (r242 - $time))) && ( | ( r56)))) * ( ( + ( ( ! ( 6'h35)))) >= (r1 - r197)))));
#10; r156 = 18'h31e3;
#10; r11 = ( ~ ( r46));
#10; r140 = r153;
#10; r230 = $time;
#10; r221 = ( ( ! ( 4'hb)) >= 11'h400);
#10; r228 = 10'haa;
#10; r125 = ((17'h2e5c > ( ~ ( (r130 - r65)))) > ((r27 - (((r7 == ( | ( (((r242 || ( ~ ( r127))) * ( + ( ((((r163 >= (18'h76bb == 3'h1)) & r140) ? (r137 == ((19'h1a8 && 20'h4b97) == 22'h44f5)) : r210) ? ($time / 23'h2b69) : r56)))) <= (16'h5540 + ( ! ( r90))))))) !== r76) & ( ! ( (r21 < 31'hbd9))))) + r248));
#10; r160 = ((25'h1e99 & ( - ( (((r104 & (r27 | (((17'h320e || r91) - (r111 != 31'h23ab)) !== r116))) % (( ( ! ( r132)) <= 21'h7a3d) || (((r78 != ( ( ! ( ( ~ ( ( ! ( ( ( ^ ( 8'h8)) != 3'h6))))))) < ((((r197 == $time) + ( | ( ( ^ ( 17'h4d54))))) && 6'h9) - ( ^ ( (( ( ! ( 7'h48)) % ( ! ( 8'h7e))) != (24'h38e3 || r47))))))) + r108) >= r183))) ^ r103)))) && 20'h1ff0);
$displayb("r0 = ",r0);
$displayb("r1 = ",r1);
$displayb("r2 = ",r2);
$displayb("r3 = ",r3);
$displayb("r4 = ",r4);
$displayb("r5 = ",r5);
$displayb("r6 = ",r6);
$displayb("r7 = ",r7);
$displayb("r8 = ",r8);
$displayb("r9 = ",r9);
$displayb("r10 = ",r10);
$displayb("r11 = ",r11);
$displayb("r12 = ",r12);
$displayb("r13 = ",r13);
$displayb("r14 = ",r14);
$displayb("r15 = ",r15);
$displayb("r16 = ",r16);
$displayb("r17 = ",r17);
$displayb("r18 = ",r18);
$displayb("r19 = ",r19);
$displayb("r20 = ",r20);
$displayb("r21 = ",r21);
$displayb("r22 = ",r22);
$displayb("r23 = ",r23);
$displayb("r24 = ",r24);
$displayb("r25 = ",r25);
$displayb("r26 = ",r26);
$displayb("r27 = ",r27);
$displayb("r28 = ",r28);
$displayb("r29 = ",r29);
$displayb("r30 = ",r30);
$displayb("r31 = ",r31);
$displayb("r32 = ",r32);
$displayb("r33 = ",r33);
$displayb("r34 = ",r34);
$displayb("r35 = ",r35);
$displayb("r36 = ",r36);
$displayb("r37 = ",r37);
$displayb("r38 = ",r38);
$displayb("r39 = ",r39);
$displayb("r40 = ",r40);
$displayb("r41 = ",r41);
$displayb("r42 = ",r42);
$displayb("r43 = ",r43);
$displayb("r44 = ",r44);
$displayb("r45 = ",r45);
$displayb("r46 = ",r46);
$displayb("r47 = ",r47);
$displayb("r48 = ",r48);
$displayb("r49 = ",r49);
$displayb("r50 = ",r50);
$displayb("r51 = ",r51);
$displayb("r52 = ",r52);
$displayb("r53 = ",r53);
$displayb("r54 = ",r54);
$displayb("r55 = ",r55);
$displayb("r56 = ",r56);
$displayb("r57 = ",r57);
$displayb("r58 = ",r58);
$displayb("r59 = ",r59);
$displayb("r60 = ",r60);
$displayb("r61 = ",r61);
$displayb("r62 = ",r62);
$displayb("r63 = ",r63);
$displayb("r64 = ",r64);
$displayb("r65 = ",r65);
$displayb("r66 = ",r66);
$displayb("r67 = ",r67);
$displayb("r68 = ",r68);
$displayb("r69 = ",r69);
$displayb("r70 = ",r70);
$displayb("r71 = ",r71);
$displayb("r72 = ",r72);
$displayb("r73 = ",r73);
$displayb("r74 = ",r74);
$displayb("r75 = ",r75);
$displayb("r76 = ",r76);
$displayb("r77 = ",r77);
$displayb("r78 = ",r78);
$displayb("r79 = ",r79);
$displayb("r80 = ",r80);
$displayb("r81 = ",r81);
$displayb("r82 = ",r82);
$displayb("r83 = ",r83);
$displayb("r84 = ",r84);
$displayb("r85 = ",r85);
$displayb("r86 = ",r86);
$displayb("r87 = ",r87);
$displayb("r88 = ",r88);
$displayb("r89 = ",r89);
$displayb("r90 = ",r90);
$displayb("r91 = ",r91);
$displayb("r92 = ",r92);
$displayb("r93 = ",r93);
$displayb("r94 = ",r94);
$displayb("r95 = ",r95);
$displayb("r96 = ",r96);
$displayb("r97 = ",r97);
$displayb("r98 = ",r98);
$displayb("r99 = ",r99);
$displayb("r100 = ",r100);
$displayb("r101 = ",r101);
$displayb("r102 = ",r102);
$displayb("r103 = ",r103);
$displayb("r104 = ",r104);
$displayb("r105 = ",r105);
$displayb("r106 = ",r106);
$displayb("r107 = ",r107);
$displayb("r108 = ",r108);
$displayb("r109 = ",r109);
$displayb("r110 = ",r110);
$displayb("r111 = ",r111);
$displayb("r112 = ",r112);
$displayb("r113 = ",r113);
$displayb("r114 = ",r114);
$displayb("r115 = ",r115);
$displayb("r116 = ",r116);
$displayb("r117 = ",r117);
$displayb("r118 = ",r118);
$displayb("r119 = ",r119);
$displayb("r120 = ",r120);
$displayb("r121 = ",r121);
$displayb("r122 = ",r122);
$displayb("r123 = ",r123);
$displayb("r124 = ",r124);
$displayb("r125 = ",r125);
$displayb("r126 = ",r126);
$displayb("r127 = ",r127);
$displayb("r128 = ",r128);
$displayb("r129 = ",r129);
$displayb("r130 = ",r130);
$displayb("r131 = ",r131);
$displayb("r132 = ",r132);
$displayb("r133 = ",r133);
$displayb("r134 = ",r134);
$displayb("r135 = ",r135);
$displayb("r136 = ",r136);
$displayb("r137 = ",r137);
$displayb("r138 = ",r138);
$displayb("r139 = ",r139);
$displayb("r140 = ",r140);
$displayb("r141 = ",r141);
$displayb("r142 = ",r142);
$displayb("r143 = ",r143);
$displayb("r144 = ",r144);
$displayb("r145 = ",r145);
$displayb("r146 = ",r146);
$displayb("r147 = ",r147);
$displayb("r148 = ",r148);
$displayb("r149 = ",r149);
$displayb("r150 = ",r150);
$displayb("r151 = ",r151);
$displayb("r152 = ",r152);
$displayb("r153 = ",r153);
$displayb("r154 = ",r154);
$displayb("r155 = ",r155);
$displayb("r156 = ",r156);
$displayb("r157 = ",r157);
$displayb("r158 = ",r158);
$displayb("r159 = ",r159);
$displayb("r160 = ",r160);
$displayb("r161 = ",r161);
$displayb("r162 = ",r162);
$displayb("r163 = ",r163);
$displayb("r164 = ",r164);
$displayb("r165 = ",r165);
$displayb("r166 = ",r166);
$displayb("r167 = ",r167);
$displayb("r168 = ",r168);
$displayb("r169 = ",r169);
$displayb("r170 = ",r170);
$displayb("r171 = ",r171);
$displayb("r172 = ",r172);
$displayb("r173 = ",r173);
$displayb("r174 = ",r174);
$displayb("r175 = ",r175);
$displayb("r176 = ",r176);
$displayb("r177 = ",r177);
$displayb("r178 = ",r178);
$displayb("r179 = ",r179);
$displayb("r180 = ",r180);
$displayb("r181 = ",r181);
$displayb("r182 = ",r182);
$displayb("r183 = ",r183);
$displayb("r184 = ",r184);
$displayb("r185 = ",r185);
$displayb("r186 = ",r186);
$displayb("r187 = ",r187);
$displayb("r188 = ",r188);
$displayb("r189 = ",r189);
$displayb("r190 = ",r190);
$displayb("r191 = ",r191);
$displayb("r192 = ",r192);
$displayb("r193 = ",r193);
$displayb("r194 = ",r194);
$displayb("r195 = ",r195);
$displayb("r196 = ",r196);
$displayb("r197 = ",r197);
$displayb("r198 = ",r198);
$displayb("r199 = ",r199);
$displayb("r200 = ",r200);
$displayb("r201 = ",r201);
$displayb("r202 = ",r202);
$displayb("r203 = ",r203);
$displayb("r204 = ",r204);
$displayb("r205 = ",r205);
$displayb("r206 = ",r206);
$displayb("r207 = ",r207);
$displayb("r208 = ",r208);
$displayb("r209 = ",r209);
$displayb("r210 = ",r210);
$displayb("r211 = ",r211);
$displayb("r212 = ",r212);
$displayb("r213 = ",r213);
$displayb("r214 = ",r214);
$displayb("r215 = ",r215);
$displayb("r216 = ",r216);
$displayb("r217 = ",r217);
$displayb("r218 = ",r218);
$displayb("r219 = ",r219);
$displayb("r220 = ",r220);
$displayb("r221 = ",r221);
$displayb("r222 = ",r222);
$displayb("r223 = ",r223);
$displayb("r224 = ",r224);
$displayb("r225 = ",r225);
$displayb("r226 = ",r226);
$displayb("r227 = ",r227);
$displayb("r228 = ",r228);
$displayb("r229 = ",r229);
$displayb("r230 = ",r230);
$displayb("r231 = ",r231);
$displayb("r232 = ",r232);
$displayb("r233 = ",r233);
$displayb("r234 = ",r234);
$displayb("r235 = ",r235);
$displayb("r236 = ",r236);
$displayb("r237 = ",r237);
$displayb("r238 = ",r238);
$displayb("r239 = ",r239);
$displayb("r240 = ",r240);
$displayb("r241 = ",r241);
$displayb("r242 = ",r242);
$displayb("r243 = ",r243);
$displayb("r244 = ",r244);
$displayb("r245 = ",r245);
$displayb("r246 = ",r246);
$displayb("r247 = ",r247);
$displayb("r248 = ",r248);
$displayb("r249 = ",r249);
$displayb("r250 = ",r250);
$displayb("r251 = ",r251);
$displayb("r252 = ",r252);
$displayb("r253 = ",r253);
$displayb("r254 = ",r254);
$finish(0);
end
endmodule
|
// cog_ctr
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ctr
(
input clk_cog,
input clk_pll,
input ena,
input setctr,
input setfrq,
input setphs,
input [31:0] data,
input [31:0] pin_in,
output reg [32:0] phs,
output [31:0] pin_out,
output pll
);
// control
reg [31:0] ctr;
reg [31:0] frq;
always @(posedge clk_cog or negedge ena)
if (!ena)
ctr <= 32'b0;
else if (setctr)
ctr <= data;
always @(posedge clk_cog)
if (setfrq)
frq <= data;
always @(posedge clk_cog)
if (setphs || trig)
phs <= setphs ? {1'b0, data} : {1'b0, phs[31:0]} + {1'b0, frq};
// input pins
reg [1:0] dly;
always @(posedge clk_cog)
if (|ctr[30:29])
dly <= {ctr[30] ? pin_in[ctr[13:9]] : dly[0], pin_in[ctr[4:0]]};
// trigger, outputs
// trigger outb outa
wire [15:0][2:0] tp = { dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
dly == 2'b10, 1'b0, 1'b0, // neg edge
!dly[0], !dly[0], 1'b0, // neg w/feedback
!dly[0], 1'b0, 1'b0, // neg
dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
dly == 2'b01, 1'b0, 1'b0, // pos edge
dly[0], !dly[0], 1'b0, // pos w/feedback
dly[0], 1'b0, 1'b0, // pos
1'b1, !phs[32], phs[32], // duty differential
1'b1, 1'b0, phs[32], // duty single
1'b1, !phs[31], phs[31], // nco differential
1'b1, 1'b0, phs[31], // nco single
1'b1, !pll, pll, // pll differential
1'b1, 1'b0, pll, // pll single
1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0 }; // off
wire [3:0] pick = ctr[29:26];
wire [2:0] tba = tp[pick];
wire trig = ctr[30] ? pick[dly] : tba[2]; // trigger
wire outb = ctr[30] ? 1'b0 : tba[1]; // outb
wire outa = ctr[30] ? 1'b0 : tba[0]; // outa
// output pins
assign pin_out = outb << ctr[13:9] | outa << ctr[4:0];
// pll simulator
reg [35:0] pll_fake;
always @(posedge clk_pll)
if (~&ctr[30:28] && |ctr[27:26])
pll_fake <= pll_fake + {4'b0, frq};
wire [7:0] pll_taps = pll_fake[35:28];
assign pll = pll_taps[~ctr[25:23]];
endmodule
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <grindars@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "pack.v"
module BrainfuckCPU(
CLK, RESET,
IA, IDIN, IEN,
DA, DDIN, DDOUT, DEN, DWE,
CIN, COUT, CRDA, CACK, CWR, CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
// Instruction bus
output reg [IA_WIDTH - 1:0] IA;
input [7:0] IDIN;
output reg IEN;
// Data bus
output [DA_WIDTH - 1:0] DA;
input [DD_WIDTH - 1:0] DDIN;
output [DD_WIDTH - 1:0] DDOUT;
output reg DEN;
output reg DWE;
// Console interface
input [7:0] CIN;
output reg [7:0] COUT;
input CRDA;
output reg CACK;
output reg CWR;
input CRDY;
reg [3:0] STATE;
wire [IA_WIDTH - 1:0] PC;
reg [DA_WIDTH - 1:0] DC;
wire [IA_WIDTH - 1:0] STACK_PC, LOOP_PC;
wire [8:0] DECODED;
wire ZERO;
reg STACK_PUSH, STACK_POP, LOOPSEEK;
reg [STACK_DEPTH_POW - 1:0] LOOP_DEPTH;
wire CONLOAD, PCLOAD;
InstructionDecoder decoder(
.OPCODE(IDIN),
.DECODED(DECODED)
);
GenericCounter #(
.WIDTH(DD_WIDTH)
) dcnt (
.CLK(CLK),
.RESET(RESET),
.D(CONLOAD ? CIN : DDIN),
.Q(DDOUT),
.EN((STATE == `STATE_DFETCH2) || (STATE == `STATE_DUPDATE) || CONLOAD),
.LOAD(STATE == `STATE_DFETCH2 || CONLOAD),
.DOWN(DECODED[`OP_DEC])
);
GenericCounter #(
.WIDTH(IA_WIDTH)
) pcnt (
.CLK(CLK),
.RESET(RESET),
.D(LOOP_PC),
.Q(PC),
.EN((STATE == `STATE_IFETCH) || PCLOAD),
.LOAD(PCLOAD),
.DOWN(1'b0)
);
Stack #(
.WIDTH(IA_WIDTH),
.DEPTH_POW(STACK_DEPTH_POW)
) stack (
.CLK(CLK),
.RESET(RESET),
.PUSH(STACK_PUSH),
.POP(STACK_POP),
.D(PC),
.Q(STACK_PC)
);
always @ (posedge CLK)
if(RESET)
begin
STATE <= `STATE_IFETCH;
IA <= 0;
DC <= 0;
IEN <= 1'b0;
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
STACK_POP <= 1'b0;
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= 0;
COUT <= 8'b0;
CWR <= 1'b0;
CACK <= 1'b0;
end
else
case(STATE)
`STATE_IFETCH:
begin
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
CWR <= 1'b0;
IA <= PC;
IEN <= 1'b1;
STATE <= `STATE_IFETCH2;
end
`STATE_IFETCH2:
begin
IEN <= 1'b0;
if(LOOPSEEK)
STATE <= `STATE_LOOPSEEK;
else
STATE <= `STATE_DECODE;
end
`STATE_DECODE:
begin
if(DECODED[`OP_ILLEGAL])
STATE <= `STATE_IFETCH;
else if(DECODED[`OP_INC] || DECODED[`OP_DEC] || DECODED[`OP_LOOPBEGIN] ||
(DECODED[`OP_LOOPEND] && FAST_LOOPEND) || DECODED[`OP_COUT])
begin
DEN <= 1'b1;
STATE <= `STATE_DFETCH;
end
else if(!FAST_LOOPEND && DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_INCPTR])
begin
DC <= DC + 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_DECPTR])
begin
DC <= DC - 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_CIN])
STATE <= `STATE_CIN;
else
STATE <= `STATE_DECODE;
end
`STATE_DFETCH:
begin
DEN <= 1'b0;
STATE <= `STATE_DFETCH2;
end
`STATE_DFETCH2:
begin
if(DECODED[`OP_LOOPBEGIN])
STATE <= `STATE_LOOPBEGIN;
else if(DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_COUT])
STATE <= `STATE_COUT;
else
STATE <= `STATE_DUPDATE;
end
`STATE_DUPDATE:
begin
STATE <= `STATE_WRITEBACK;
end
`STATE_WRITEBACK:
begin
CACK <= 1'b0;
DEN <= 1'b1;
DWE <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPBEGIN:
begin
if(ZERO)
begin
LOOPSEEK <= 1'b1;
LOOP_DEPTH <= 1;
end
else
STACK_PUSH <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPEND:
begin
STACK_POP <= 1'b1;
STATE <= `STATE_LOOPEND2;
end
`STATE_LOOPEND2:
begin
STACK_POP <= 1'b0;
STATE <= `STATE_LOOPEND3;
end
`STATE_LOOPEND3:
begin
STATE <= `STATE_IFETCH;
end
`STATE_LOOPSEEK:
begin
if(DECODED[`OP_LOOPBEGIN])
LOOP_DEPTH <= LOOP_DEPTH + 1;
else if(DECODED[`OP_LOOPEND])
begin
if(LOOP_DEPTH == 1)
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= LOOP_DEPTH - 1;
end
STATE <= `STATE_IFETCH;
end
`STATE_COUT:
begin
if(CRDY)
begin
COUT <= DDOUT;
CWR <= 1'b1;
STATE <= `STATE_IFETCH;
end
else
STATE <= `STATE_COUT;
end
`STATE_CIN:
if(CRDA)
begin
CACK <= 1'b1;
STATE <= `STATE_WRITEBACK;
end
else
STATE <= `STATE_CIN;
endcase
assign DA = DC;
assign CONLOAD = (STATE == `STATE_CIN) && CRDA;
assign PCLOAD = (!ZERO || !FAST_LOOPEND) && STATE == `STATE_LOOPEND3;
assign LOOP_PC = STACK_PC - 1;
assign ZERO = DDOUT == 0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// Simualtion only memory controller
module mem_ctrl(
CLK,
RESETn,
ADDR,
DATA_IN,
MEM_REQ,
MEM_WRITE,
DATA_OUT,
MEM_ACK_OUT
);
parameter MEM_DEPTH = 65536;
parameter LC_MEM_DATA_WIDTH = 32;
parameter LC_MEM_ADDR_WIDTH = 32;
input CLK;
input RESETn;
input [LC_MEM_ADDR_WIDTH-3:0] ADDR;
input [LC_MEM_DATA_WIDTH-1:0] DATA_IN;
input MEM_REQ;
input MEM_WRITE;
output reg [LC_MEM_DATA_WIDTH-1:0] DATA_OUT;
output reg MEM_ACK_OUT;
`include "include/mbus_func.v"
wire [log2(MEM_DEPTH-1)-1:0] addr_equal = ADDR[log2(MEM_DEPTH-1)-1:0];
reg [LC_MEM_DATA_WIDTH-1:0] mem_array [0:MEM_DEPTH-1];
reg [1:0] fsm;
parameter IDLE = 2'b00;
parameter CLEAR = 2'b01;
parameter WRITE = 2'b10;
parameter READ = 2'b11;
integer idx;
initial
begin
for (idx=0; idx<(MEM_DEPTH); idx=idx+1)
begin
mem_array[idx] <= 0;
end
end
always @ (posedge CLK or negedge RESETn)
begin
if (~RESETn)
begin
fsm <= IDLE;
MEM_ACK_OUT <= 0;
DATA_OUT <= 0;
end
else
begin
case (fsm)
IDLE:
begin
if (MEM_REQ)
begin
if (MEM_WRITE)
fsm <= WRITE;
else
fsm <= READ;
end
end
WRITE:
begin
mem_array[addr_equal] <= DATA_IN;
MEM_ACK_OUT <= 1;
fsm <= CLEAR;
end
READ:
begin
DATA_OUT <= mem_array[addr_equal];
MEM_ACK_OUT <= 1;
fsm <= CLEAR;
end
CLEAR:
begin
if (~MEM_REQ)
begin
fsm <= IDLE;
MEM_ACK_OUT <= 0;
end
end
endcase
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
input dbg_i;
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
input [15:0] pulse_num_i;
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output reg rx_strobe_o;
reg [15:0] count;
always @(posedge clk_i)
if (rst_i | ~ena_i)
count <= 16'b0;
else
count <= count + 16'b1;
wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i};
// Buffer incoming samples every clock
wire [31:0] fifo_out;
reg fifo_ack;
wire fifo_empty;
// Use model if simulating, otherwise Altera Megacell
`ifdef SIMULATION
fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`else
fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`endif
// Write samples to rx_fifo every third clock
`define ST_FIFO_IDLE 3'b001
`define ST_FIFO_STROBE 3'b010
`define ST_FIFO_ACK 3'b100
reg [2:0] state;
always @(posedge clk_i)
if (rst_i)
begin
state <= `ST_FIFO_IDLE;
rx_strobe_o <= 1'b0;
fifo_ack <= 1'b0;
end
else
case (state)
`ST_FIFO_IDLE:
if (!fifo_empty)
begin
// Tell rx_fifo sample is ready
rx_strobe_o <= 1'b1;
state <= `ST_FIFO_STROBE;
end
`ST_FIFO_STROBE:
begin
rx_strobe_o <= 1'b0;
// Ack our FIFO
fifo_ack <= 1'b1;
state <= `ST_FIFO_ACK;
end
`ST_FIFO_ACK:
begin
fifo_ack <= 1'b0;
state <= `ST_FIFO_IDLE;
end
endcase // case(state)
assign rx_i_o = fifo_out[31:16];
assign rx_q_o = fifo_out[15:0];
endmodule // radar_rx
|
//----------------------------------------------------------------------
// Copyright 2007-2010 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
//This is dummy DUT.
module dut_dummy(
input wire ubus_req_master_0,
output reg ubus_gnt_master_0,
input wire ubus_req_master_1,
output reg ubus_gnt_master_1,
input wire ubus_clock,
input wire ubus_reset,
input wire [15:0] ubus_addr,
input wire [1:0] ubus_size,
output reg ubus_read,
output reg ubus_write,
output reg ubus_start,
input wire ubus_bip,
inout wire [7:0] ubus_data,
input wire ubus_wait,
input wire ubus_error);
bit[2:0] st;
// Basic arbiter, supports two masters, 0 has priority over 1
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_start <= 1'b0;
st<=3'h0;
end
else
case(st)
0: begin //Begin out of Reset
ubus_start <= 1'b1;
st<=3'h3;
end
3: begin //Start state
ubus_start <= 1'b0;
if((ubus_gnt_master_0==0) && (ubus_gnt_master_1==0)) begin
st<=3'h4;
end
else
st<=3'h1;
end
4: begin // No-op state
ubus_start <= 1'b1;
st<=3'h3;
end
1: begin // Addr state
st<=3'h2;
ubus_start <= 1'b0;
end
2: begin // Data state
if((ubus_error==1) || ((ubus_bip==0) && (ubus_wait==0))) begin
st<=3'h3;
ubus_start <= 1'b1;
end
else begin
st<=3'h2;
ubus_start <= 1'b0;
end
end
endcase
end
always @(negedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset == 1'b1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
else begin
if(ubus_start && ubus_req_master_0) begin
ubus_gnt_master_0 <= 1;
ubus_gnt_master_1 <= 0;
end
else if(ubus_start && !ubus_req_master_0 && ubus_req_master_1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 1;
end
else begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
end
end
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
else if(ubus_start && !ubus_gnt_master_0 && !ubus_gnt_master_1) begin
ubus_read <= 1'b0;
ubus_write <= 1'b0;
end
else begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
end
endmodule
|
module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <dtysky@outlook.com>
This library is free software;you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
dtysky@outlook.com
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
clk,
rst_n,
in_count_x,
in_count_y,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
Delay for multiplier.
::range
Depend on your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
|
/*
whirlwind nes - nes compatible fpga core
copyright (c) 2020 anthony westbrook (twestbrook@oursyntheticdreams.com)
this program is free software; you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation; either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program; if not, write to the free software foundation,
inc., 51 franklin street, fifth floor, boston, ma 02110-1301 usa
*/
module ram_controller(
input ram_clk_in,
input ram_read_in,
input ram_write_in,
input [15:0] ram_address_in,
input [7:0] ram_data_in,
output [7:0] ram_data_out,
input [9:0] switches_in,
output reg [15:0] debug_out
);
// io addresses
localparam ram_start = 16'h0000;
localparam ram_size = 16'h2000;
// private registers and wires
wire ram_enable;
assign ram_enable = (ram_address_in >= ram_start) && (ram_address_in < (ram_start + ram_size));
ram ram_controller_ram(.address(ram_address_in[10:0]), .clock(ram_clk_in), .data(ram_data_in), .rden(ram_read_in), .wren(ram_enable && ram_write_in), .q(ram_data_out));
endmodule
|
/*
* pci express to fifo - xilinx adc interface
* copyright (c) 2014 harmon instruments, llc
*
* this program is free software: you can redistribute it and/or modify
* it under the terms of the gnu general public license as published by
* the free software foundation, either version 3 of the license, or
* (at your option) any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the
* gnu general public license for more details.
*
* you should have received a copy of the gnu general public license
* along with this program. if not, see <http://www.gnu.org/licenses/
*
* din[15:0] drp data
* din[22:16] drp address
* din[31] drp write enable
*
* dout[15:0] drp data
* dout[16] busy
*
*/
`timescale 1ns / 1ps
module xadc
(
input clock,
input write,
input [63:0] din,
output reg [16:0] dout = 0
);
`ifndef sim
reg [1:0] state = 0;
reg [2:0] clkdiv = 0;
reg [23:0] drp_in;
reg drp_en = 0;
wire [15:0] drp_do;
wire drp_drdy;
always @ (posedge clock)
begin
clkdiv <= clkdiv + 1'b1;
dout[16] <= state != 0;
state <= write ? 2'd1 :
(state == 1) && (clkdiv == 0) ? 2'd2 :
(clkdiv == 0) && drp_drdy ? 2'd0 :
(state == 2) && (clkdiv == 0) ? 2'd3 :
state;
drp_en <= (state == 1) && (clkdiv == 0) ? 1'b1 :
(state == 2) && (clkdiv == 0) ? 1'b0 :
drp_en;
if(write)
drp_in <= {din[31], din[22:0]};
if((clkdiv == 0) && drp_drdy)
dout[15:0] <= drp_do;
end
xadc #(.init_42(16'h0400)) xadc_i
(
.alm(),
.ot(),
.busy(),
.channel(),
.eoc(),
.eos(),
.jtagbusy(),
.jtaglocked(),
.jtagmodified(),
.muxaddr(),
.vauxn(),
.vauxp(),
.vn(),
.vp(), // analog
.convst(1'b0),
.convstclk(1'b0),
.reset(1'b0),
// drp outputs
.do(drp_do),
.drdy(drp_drdy),
// drp inputs
.daddr(drp_in[22:16]),
.dclk(clkdiv[2]),
.den(drp_en),
.di(drp_in[15:0]),
.dwe(drp_in[23])
);
`endif
endmodule
|
/*
* testbench for zet-ng decoder
* copyright (c) 2013 charley picker <charleypicker@yahoo.com>
*
* this file is part of the zet processor. this processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the gnu general public license as published by the free software
* foundation; either version 3, or (at your option) any later version.
*
* zet is distrubuted in the hope that it will be useful, but without
* any warranty; without even the implied warranty of merchantability
* or fitness for a particular purpose. see the gnu general public
* license for more details.
*
* you should have received a copy of the gnu general public license
* along with zet; see the file copying. if not, see
* <http://www.gnu.org/licenses/>.
*/
`define enable_vcd
`include "defines.v"
module test_decode();
// testbench regs and wires
reg clk;
initial clk = 1'b0;
always #1.5 clk = ~clk;
reg rst;
// device under test regs and wires
reg [7:0] instruction;
reg instruction_valid;
wire instruction_next;
// current cs and ip of instruction
wire [15:0] instruction_cs_o;
wire [15:0] instruction_ip_o;
// {prefix_decoded, repe_repz, repne_repnz, lock}
wire [3:0] inst_pr_o;
// {prefix_decoded, x, x, address size override}
wire [3:0] adrs_pr_o;
// {prefix_decoded, x, x, operand size override}
wire [3:0] oper_pr_o;
// {prefix_decoded, segment override register}
wire [3:0] sovr_pr_o;
wire [7:0] opcode_o;
wire need_modrm_o;
wire [7:0] modrm_o;
wire need_off_o;
wire off_size_o;
wire [15:0] offset_o;
wire need_imm_o;
wire imm_size_o;
wire [15:0] immediate_o;
// to sequencer
wire [`micro_addr_width-1:0] seq_addr_o;
wire [3:0] src_o;
wire [3:0] dst_o;
wire [3:0] base_o;
wire [3:0] index_o;
wire [1:0] seg_o;
wire decoded_valid_o;
reg next_decoded_i;
// storage for data.rtlrom
reg [15:0] ram[0:2**19-1];
// stimulus regs and wires
reg [19:0] count;
wire [15:0] do16;
assign do16 = ram[count[19:1]];
// testbench task
task waitclock;
begin
@(posedge clk);
#1.5;
end
endtask
// device under test module instantiation
zet_decode dut (
.clk(clk),
.rst_i(rst),
.flush_i(1'b0),
.instruction_i(instruction),
.instruction_valid_i(instruction_valid),
.next_instruction_o(instruction_next),
// current cs and ip of instruction
.instruction_cs_o(instruction_cs_o),
.instruction_ip_o(instruction_ip_o),
// {prefix_decoded, repe_repz, repne_repnz, lock}
.inst_pr_o(inst_pr_o),
// {prefix_decoded, x, x, address size override}
.adrs_pr_o(adrs_pr_o),
// {prefix_decoded, x, x, operand size override}
.oper_pr_o(oper_pr_o),
// {prefix_decoded, segment override register}
.sovr_pr_o(sovr_pr_o),
.opcode_o(opcode_o),
.need_modrm_o(need_modrm_o),
.modrm_o(modrm_o),
.need_off_o(need_off_o),
.off_size_o(off_size_o),
.offset_o(offset_o),
.need_imm_o(need_imm_o),
.imm_size_o(imm_size_o),
.immediate_o(immediate_o),
// to sequencer
.seq_addr_o(seq_addr_o),
.src_o(src_o),
.dst_o(dst_o),
.base_o(base_o),
.index_o(index_o),
.seg_o(seg_o),
.decoded_valid_o(decoded_valid_o),
.next_decoded_i(next_decoded_i)
);
// behaviour
always @(*) begin
case(count[0])
1'd0: instruction <= do16[7:0];
1'd1: instruction <= do16[15:8];
endcase
end
always @(posedge clk)
if (rst)
begin
instruction_valid <= 1'b0;
count <= 20'd0;
end
else
begin
instruction_valid <= 1'b1;
if (instruction_next)
begin
$display("address: %h data byte: %h", count, instruction);
count <= count + 20'd1;
end
if (decoded_valid_o & !next_decoded_i)
begin
$display("instruction_cs: %h", instruction_cs_o);
$display("instruction_ip: %h", instruction_ip_o);
$display(" ");
$display("instruction prefix {prefix_decoded, repe_repz, repne_repnz, lock}: %b", inst_pr_o);
$display("address size override prefix {prefix_decoded, x, x, address size override}: %b", adrs_pr_o);
$display("operand size override prefix {prefix_decoded, x, x, operand size override}: %b", oper_pr_o);
$display("segment override prefix {prefix_decoded, segment override register}: %b", sovr_pr_o);
$display(" ");
$display("opcode: %h", opcode_o);
$display(" ");
$display("need modrm: %b", need_modrm_o);
$display("modrm: %h", modrm_o);
$display(" ");
$display("need offset: %b",need_off_o);
$display("offset size: %b", off_size_o);
$display("offset: %h", offset_o);
$display(" ");
$display("need immediate: %b", need_imm_o);
$display("immediate size: %b", imm_size_o);
$display("immediate: %h", immediate_o);
$display(" ");
$display("sequencer address in hex: %h, bit: %b", seq_addr_o, seq_addr_o);
$display("sequencer source in hex: %h, bit: %b", src_o, src_o);
$display("sequencer destination in hex: %h, bit: %b", dst_o, dst_o);
$display("sequencer base in hex: %h, bit: %b", base_o, base_o);
$display("sequencer index in hex: %h, bit: %b", index_o, index_o);
$display("sequencer segment in hex: %h, bit: %b", seg_o, seg_o);
$display(" ");
$display("instruction finished decoding");
$display(" ");
$display(" ");
$display(" ");
$display(" ");
$display("########## sending next byte sequence: ##########");
$display(" ");
next_decoded_i <= 1'b1;
end
else
next_decoded_i <= 1'b0;
end
always begin
`ifdef enable_vcd
$dumpfile("decode.vcd");
$dumpvars(0, dut);
`endif
clk <= 1'b1;
rst <= 1'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
waitclock;
$display(" ");
$display("########## sending first byte sequence: ##########");
$display(" ");
#1000 rst <= 1'b1;
//$stop;
end
initial
begin
//$readmemh("data.rtlrom", ram, 19'h78000);
$readmemh("../data.rtlrom", ram);
end
endmodule
|
// this program was cloned from: https://github.com/t-head-semi/openc906
// license: apache license 2.0
/*copyright 2020-2021 t-head semiconductor co., ltd.
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
// &modulebeg; @22
module aq_spsram_128x8(
a,
cen,
clk,
d,
gwen,
q,
wen
);
// &ports; @23
input [6:0] a;
input cen;
input clk;
input [7:0] d;
input gwen;
input [7:0] wen;
output [7:0] q;
// ®s; @24
// &wires; @25
wire [6:0] a;
wire cen;
wire clk;
wire [7:0] d;
wire gwen;
wire [7:0] q;
wire [7:0] wen;
//**********************************************************
// parameter definition
//**********************************************************
parameter addr_width = 7;
parameter data_width = 8;
parameter we_width = 8;
// &force("bus","q",data_width-1,0); @34
// &force("bus","wen",we_width-1,0); @35
// &force("bus","a",addr_width-1,0); @36
// &force("bus","d",data_width-1,0); @37
// //********************************************************
// //* fpga memory *
// //********************************************************
// &instance("aq_f_spsram_128x8"); @43
aq_f_spsram_128x8 x_aq_f_spsram_128x8 (
.a (a ),
.cen (cen ),
.clk (clk ),
.d (d ),
.gwen (gwen),
.q (q ),
.wen (wen )
);
// &instance("aq_umc_spsram_128x8"); @49
// &instance("aq_tsmc_spsram_128x8"); @55
// &moduleend; @58
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module rx_chain_dual
(input clock,
input clock_2x,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
input wire [31:0] freq0,
input wire [15:0] i_in0,
input wire [15:0] q_in0,
output wire [15:0] i_out0,
output wire [15:0] q_out0,
input wire [31:0] freq1,
input wire [15:0] i_in1,
input wire [15:0] q_in1,
output wire [15:0] i_out1,
output wire [15:0] q_out1
);
wire [15:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] i_in, q_in;
wire [31:0] phase0;
wire [31:0] phase1;
reg [15:0] bb_i0, bb_q0;
reg [15:0] bb_i1, bb_q1;
// We want to time-share the CORDIC by double-clocking it
phase_acc rx_phase_acc_0
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
phase_acc rx_phase_acc_1
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
assign phase = clock ? phase0[31:16] : phase1[31:16];
assign i_in = clock ? i_in0 : i_in1;
assign q_in = clock ? q_in0 : q_in1;
// This appears reversed because of the number of CORDIC stages
always @(posedge clock_2x)
if(clock)
begin
bb_i1 <= #1 bb_i;
bb_q1 <= #1 bb_q;
end
else
begin
bb_i0 <= #1 bb_i;
bb_q0 <= #1 bb_q;
end
cordic rx_cordic
( .clock(clock_2x),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase),
.xo(bb_i),.yo(bb_q),.zo() );
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i0),.signal_out(i_out0) );
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q0),.signal_out(q_out0) );
cic_decim cic_decim_i_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i1),.signal_out(i_out1) );
cic_decim cic_decim_q_1
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q1),.signal_out(q_out1) );
endmodule // rx_chain
|
// this program was cloned from: https://github.com/aucohl/lighter
// license: apache license 2.0
/*
copyright 2022 auc open source hardware lab
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at:
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
(* blackbox *)
module sky130_fd_sc_ms__dlclkp_1 (
input gate,
input clk,
output gclk);
endmodule
(* blackbox *)
module sky130_fd_sc_ms__dlclkp_2 (
input gate,
input clk,
output gclk);
endmodule
(* blackbox *)
module sky130_fd_sc_ms__dlclkp_4 (
input gate,
input clk,
output gclk);
endmodule
|
/**
* sseg_driver.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* seven segment display driver */
module sseg_driver(
input wire [ 3 : 0] digit, /* digit to show */
input wire [ 1 : 0] sel, /* place to show */
output reg [ 3 : 0] anode, /* common anode enable */
output reg [ 6 : 0] cathode /* cathode enable */
);
/* decode anode enable signal */
always @(sel) begin
case(sel)
2'b00: anode = 4'b1110;
2'b01: anode = 4'b1101;
2'b10: anode = 4'b1011;
2'b11: anode = 4'b0111;
endcase
end
/* decode digit into 7-segment driver output */
always @(digit) begin
case(digit) /* ABCDEFG */
4'h0: cathode = 7'b0000001;
4'h1: cathode = 7'b1001111;
4'h2: cathode = 7'b0010010;
4'h3: cathode = 7'b0000110;
4'h4: cathode = 7'b1001100;
4'h5: cathode = 7'b0100100;
4'h6: cathode = 7'b0100000;
4'h7: cathode = 7'b0001111;
4'h8: cathode = 7'b0000000;
4'h9: cathode = 7'b0000100;
4'ha: cathode = 7'b0001000;
4'hb: cathode = 7'b1100000;
4'hc: cathode = 7'b0110001;
4'hd: cathode = 7'b1000010;
4'he: cathode = 7'b0110000;
4'hf: cathode = 7'b0111000;
endcase
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Following defines conditionally include RX path circuitry
`include "config.vh" // resolved relative to project root
module rx_chain
(input clock,
input reset,
input enable,
input wire [7:0] decim_rate,
input sample_strobe,
input decimator_strobe,
output wire hb_strobe,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debugdata,output wire [15:0] debugctrl
);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
wire [31:0] phase;
wire [15:0] bb_i, bb_q;
wire [15:0] hb_in_i, hb_in_q;
assign debugdata = hb_in_i;
`ifdef RX_NCO_ON
phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.strobe(sample_strobe),.phase(phase) );
cordic rx_cordic
( .clock(clock),.reset(reset),.enable(enable),
.xi(i_in),.yi(q_in),.zi(phase[31:16]),
.xo(bb_i),.yo(bb_q),.zo() );
`else
assign bb_i = i_in;
assign bb_q = q_in;
assign sample_strobe = 1;
`endif // !`ifdef RX_NCO_ON
`ifdef RX_INTEG_ON
integrator integ_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(i_out) );
assign hb_strobe = decimator_strobe;
`else
`ifdef RX_CIC_ON
cic_decim cic_decim_i_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_i),.signal_out(hb_in_i) );
`else
assign hb_in_i = bb_i;
assign decimator_strobe = sample_strobe;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_i_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
`else
assign i_out = hb_in_i;
assign hb_strobe = decimator_strobe;
`endif
`endif // RX_INTEG_ON
`ifdef RX_INTEG_ON
integrator integ_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(q_out) );
`else
`ifdef RX_CIC_ON
cic_decim cic_decim_q_0
( .clock(clock),.reset(reset),.enable(enable),
.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
.signal_in(bb_q),.signal_out(hb_in_q) );
`else
assign hb_in_q = bb_q;
`endif
`ifdef RX_HB_ON
halfband_decim hbd_q_0
( .clock(clock),.reset(reset),.enable(enable),
.strobe_in(decimator_strobe),.strobe_out(),
.data_in(hb_in_q),.data_out(q_out) );
`else
assign q_out = hb_in_q;
`endif
`endif // RX_INTEG_ON
endmodule // rx_chain
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iddr32 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [31:0] Q0,
output [31:0] Q1,
input C0,
input C1,
input CE,
input [31:0] D,
input R,
input S
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr0 (
.Q0(Q0[0]),
.Q1(Q1[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr1 (
.Q0(Q0[1]),
.Q1(Q1[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr2 (
.Q0(Q0[2]),
.Q1(Q1[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr3 (
.Q0(Q0[3]),
.Q1(Q1[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr4 (
.Q0(Q0[4]),
.Q1(Q1[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr5 (
.Q0(Q0[5]),
.Q1(Q1[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr6 (
.Q0(Q0[6]),
.Q1(Q1[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr7 (
.Q0(Q0[7]),
.Q1(Q1[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr8 (
.Q0(Q0[8]),
.Q1(Q1[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr9 (
.Q0(Q0[9]),
.Q1(Q1[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr10 (
.Q0(Q0[10]),
.Q1(Q1[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr11 (
.Q0(Q0[11]),
.Q1(Q1[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr12 (
.Q0(Q0[12]),
.Q1(Q1[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr13 (
.Q0(Q0[13]),
.Q1(Q1[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr14 (
.Q0(Q0[14]),
.Q1(Q1[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr15 (
.Q0(Q0[15]),
.Q1(Q1[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr16 (
.Q0(Q0[16]),
.Q1(Q1[16]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[16]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr17 (
.Q0(Q0[17]),
.Q1(Q1[17]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[17]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr18 (
.Q0(Q0[18]),
.Q1(Q1[18]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[18]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr19 (
.Q0(Q0[19]),
.Q1(Q1[19]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[19]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr20 (
.Q0(Q0[20]),
.Q1(Q1[20]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[20]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr21 (
.Q0(Q0[21]),
.Q1(Q1[21]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[21]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr22 (
.Q0(Q0[22]),
.Q1(Q1[22]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[22]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr23 (
.Q0(Q0[23]),
.Q1(Q1[23]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[23]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr24 (
.Q0(Q0[24]),
.Q1(Q1[24]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[24]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr25 (
.Q0(Q0[25]),
.Q1(Q1[25]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[25]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr26 (
.Q0(Q0[26]),
.Q1(Q1[26]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[26]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr27 (
.Q0(Q0[27]),
.Q1(Q1[27]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[27]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr28 (
.Q0(Q0[28]),
.Q1(Q1[28]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[28]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr29 (
.Q0(Q0[29]),
.Q1(Q1[29]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[29]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr30 (
.Q0(Q0[30]),
.Q1(Q1[30]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[30]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr31 (
.Q0(Q0[31]),
.Q1(Q1[31]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[31]),
.R(R),
.S(S)
);
endmodule
|
/*!
memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
/*
Top level module: glues everything together.
*/
`define IDX(x) (((x)+1)*(8)-1):((x)*(8))
module memfifo (
input fxclk_in,
input ifclk_in,
input reset,
input [1:0] mode,
// debug
output [9:0] led1,
output [19:0] led2,
input SW8,
input SW10,
// ddr3
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p,
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [1:0] ddr3_dm,
output [0:0] ddr3_odt,
// ez-usb
inout [15:0] fd,
output SLWR, SLRD,
output SLOE, FIFOADDR0, FIFOADDR1, PKTEND,
input FLAGA, FLAGB
);
wire reset_mem, reset_usb;
wire ifclk;
reg reset_ifclk;
wire [24:0] mem_free;
wire [9:0] status;
wire [3:0] if_status;
reg [1:0] mode_buf;
// input fifo
reg [127:0] DI;
wire FULL, WRERR, USB_DO_valid;
reg WREN, wrerr_buf;
wire [15:0] USB_DO;
reg [127:0] in_data;
reg [3:0] wr_cnt;
reg [6:0] test_cnt;
reg [13:0] test_cs;
reg in_valid;
wire test_sync;
reg [1:0] clk_div;
// output fifo
wire [127:0] DO;
wire EMPTY, RDERR, USB_DI_ready;
reg RDEN, rderr_buf, USB_DI_valid;
reg [127:0] rd_buf;
reg [2:0] rd_cnt;
dram_fifo #(
.FIRST_WORD_FALL_THROUGH("TRUE"), // Sets the FIFO FWFT to FALSE, TRUE
.ALMOST_EMPTY_OFFSET2(13'h0008),
) dram_fifo_inst (
.fxclk_in(fxclk_in), // 48 MHz input clock pin
.reset(reset || reset_usb),
.reset_out(reset_mem), // reset output
.clkout2(), // PLL clock outputs not used for memory interface
.clkout3(),
.clkout4(),
.clkout5(),
// Memory interface ports
.ddr3_dq(ddr3_dq),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_addr(ddr3_addr),
.ddr3_ba(ddr3_ba),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_ck_p(ddr3_ck_p),
.ddr3_ck_n(ddr3_ck_n),
.ddr3_cke(ddr3_cke),
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
// input fifo interface, see "7 Series Memory Resources" user guide (ug743)
.DI(DI),
.FULL(FULL), // 1-bit output: Full flag
.ALMOSTFULL1(), // 1-bit output: Almost full flag
.ALMOSTFULL2(), // 1-bit output: Almost full flag
.WRERR(WRERR), // 1-bit output: Write error
.WREN(WREN), // 1-bit input: Write enable
.WRCLK(ifclk), // 1-bit input: Rising edge write clock.
// output fifo interface, see "7 Series Memory Resources" user guide (ug743)
.DO(DO),
.EMPTY(EMPTY), // 1-bit output: Empty flag
.ALMOSTEMPTY1(), // 1-bit output: Almost empty flag
.ALMOSTEMPTY2(), // 1-bit output: Almost empty flag
.RDERR(RDERR), // 1-bit output: Read error
.RDCLK(ifclk), // 1-bit input: Read clock
.RDEN(RDEN), // 1-bit input: Read enable
// free memory
.mem_free_out(mem_free),
// for debugging
.status(status)
);
ezusb_io #(
.OUTEP(2), // EP for FPGA -> EZ-USB transfers
.INEP(6), // EP for EZ-USB -> FPGA transfers
) ezusb_io_inst (
.ifclk(ifclk),
.reset(reset), // asynchronous reset input
.reset_out(reset_usb), // synchronous reset output
// pins
.ifclk_in(ifclk_in),
.fd(fd),
.SLWR(SLWR),
.SLRD(SLRD),
.SLOE(SLOE),
.PKTEND(PKTEND),
.FIFOADDR({FIFOADDR1, FIFOADDR0}),
.EMPTY_FLAG(FLAGA),
.FULL_FLAG(FLAGB),
// signals for FPGA -> EZ-USB transfer
.DI(rd_buf[15:0]), // data written to EZ-USB
.DI_valid(USB_DI_valid), // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
.DI_ready(USB_DI_ready), // 1 if new data are accepted
.DI_enable(1'b1), // setting to 0 disables FPGA -> EZ-USB transfers
.pktend_timeout(16'd73), // timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed
// setting to 0 disables this feature
// signals for EZ-USB -> FPGA transfer
.DO(USB_DO), // data read from EZ-USB
.DO_valid(USB_DO_valid), // 1 indicated valid data
.DO_ready((mode_buf==2'd0) && !reset_ifclk && !FULL), // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
// debug output
.status(if_status)
);
/* BUFR ifclkin_buf (
.I(ifclk_in),
.O(ifclk)
); */
// assign ifclk = ifclk_in;
// debug board LEDs
assign led1 = SW10 ? status : { EMPTY, FULL, wrerr_buf, rderr_buf, if_status, FLAGB, FLAGA };
assign led2[0] = mem_free != { 1'b1, 24'd0 };
assign led2[1] = mem_free[23:19] < 5'd30;
assign led2[2] = mem_free[23:19] < 5'd29;
assign led2[3] = mem_free[23:19] < 5'd27;
assign led2[4] = mem_free[23:19] < 5'd25;
assign led2[5] = mem_free[23:19] < 5'd24;
assign led2[6] = mem_free[23:19] < 5'd22;
assign led2[7] = mem_free[23:19] < 5'd20;
assign led2[8] = mem_free[23:19] < 5'd19;
assign led2[9] = mem_free[23:19] < 5'd17;
assign led2[10] = mem_free[23:19] < 5'd15;
assign led2[11] = mem_free[23:19] < 5'd13;
assign led2[12] = mem_free[23:19] < 5'd12;
assign led2[13] = mem_free[23:19] < 5'd10;
assign led2[14] = mem_free[23:19] < 5'd8;
assign led2[15] = mem_free[23:19] < 5'd7;
assign led2[16] = mem_free[23:19] < 5'd5;
assign led2[17] = mem_free[23:19] < 5'd3;
assign led2[18] = mem_free[23:19] < 5'd2;
assign led2[19] = mem_free == 25'd0;
assign test_sync = wr_cnt[0] || (wr_cnt == 4'd14);
always @ (posedge ifclk)
begin
reset_ifclk <= reset || reset_usb || reset_mem;
if ( reset_ifclk )
begin
rderr_buf <= 1'b0;
wrerr_buf <= 1'b0;
end else
begin
rderr_buf <= rderr_buf || RDERR;
wrerr_buf <= wrerr_buf || WRERR;
end
// FPGA -> EZ-USB FIFO
if ( reset_ifclk )
begin
rd_cnt <= 3'd0;
USB_DI_valid <= 1'd0;
end else if ( USB_DI_ready )
begin
USB_DI_valid <= !EMPTY;
if ( !EMPTY )
begin
if ( rd_cnt == 3'd0 )
begin
rd_buf <= DO;
end else
begin
rd_buf[111:0] <= rd_buf[127:16];
end
rd_cnt <= rd_cnt+1;
end
end
RDEN <= !reset_ifclk && USB_DI_ready && !EMPTY && (rd_cnt==3'd0);
if ( reset_ifclk )
begin
in_data <= 128'd0;
in_valid <= 1'b0;
wr_cnt <= 4'd0;
test_cnt <= 7'd0;
test_cs <= 12'd47;
WREN <= 1'b0;
clk_div <= 2'd3;
end else if ( !FULL )
begin
if ( in_valid ) DI <= in_data;
if ( mode_buf == 2'd0 ) // input from USB
begin
if ( USB_DO_valid )
begin
in_data <= { USB_DO, in_data[127:16] };
in_valid <= wr_cnt[2:0] == 3'd7;
wr_cnt <= wr_cnt + 1;
end else
begin
in_valid <= 1'b0;
end
end else if ( clk_div == 2'd0 ) // test data generator
begin
if ( wr_cnt == 4'd15 )
begin
test_cs <= 12'd47;
in_data[126:120] <= test_cs[6:0] ^ test_cs[13:7];
in_valid <= 1'b1;
end else
begin
test_cnt <= test_cnt + 7'd111;
test_cs <= test_cs + { test_sync, test_cnt };
in_data[126:120] <= test_cnt;
in_valid <= 1'b0;
end
in_data[127] <= test_sync;
in_data[119:0] <= in_data[127:8];
wr_cnt <= wr_cnt + 1;
end else
begin
in_valid <= 1'b0;
end
if ( (mode_buf==2'd1) || ((mode_buf==2'd3) && SW8 ) )
begin
clk_div <= 2'd0; // data rate: 48 MByte/s
end else
begin
clk_div <= clk_div + 1; // data rate: 12 MByte/s
end
end
WREN <= !reset_ifclk && in_valid && !FULL;
mode_buf<=mode;
end
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
instruction fetch phase
*/
module cpu_if(rst, clk, cpu_stall, imem_addr, p_pc, pc_j,
pc_b, b_addr, j_addr, iin, p_inst, stall, int, int_ack, int_flush, int_pc);
input rst, clk, cpu_stall, int;
input pc_j;
input pc_b;
input [31:0] b_addr;
input [31:0] j_addr;
input stall;
output reg [31:0] p_pc;
output [31:0] imem_addr;
input [31:0] iin;
output reg [31:0] p_inst;
output int_ack, int_flush;
input [31:0] int_pc;
reg [31:0] pc;
wire [31:0] next_pc;
/* flush logic (for branches and jumps) */
wire flush = pc_b | pc_j;
/* interrupt logic */
/* we're guaranteed not to get an interrupt when
* handling one already, as interrupts disable
* in the interrupt controller automatically.
*
* state machine:
* 00 - idle, waiting for interrupt
* 01 - wait 1 cycle for branch delay slot
* 10 - injecting interrupt
* 11 - injecting nop (branch delay slot)
*/
reg [1:0] int_state = 2'b00;
wire cycle_wait = pc - int_pc != 8;
wire [1:0] next_int_state =
int_state == 2'b00 && int && cycle_wait ? 2'b01 : /* wait 1 cycle */
int_state == 2'b00 && int && !cycle_wait ? 2'b10 : /* go! */
int_state == 2'b01 && !cycle_wait ? 2'b10 : /* ...go */
int_state == 2'b10 ? 2'b11 :
int_state == 2'b11 ? 2'b00 : int_state; /* default case is invalid */
wire [31:0] next_inst =
int_state == 2'b10 ? 32'h0380f009 : /* jalr $ir, $iv - 0000_0011_1000_0000_1111_0000_0000_1001 */
int_state == 2'b11 ? 32'h00000000 : /* nop */
iin;
assign int_ack = int_state != 2'b00;
assign int_flush = next_int_state == 2'b10;
always @(posedge clk) begin
if (!cpu_stall) begin
if (rst) begin
p_pc <= 0;
pc <= 0;
p_inst <= 0;
int_state <= 0;
end else if (stall && !flush && !rst) begin
p_pc <= p_pc;
pc <= pc;
p_inst <= p_inst;
int_state <= next_int_state;
end else if ((flush || int_flush) && !rst && !stall) begin
p_pc <= 0;
p_inst <= 0;
pc <= next_pc;
int_state <= next_int_state;
end else begin
p_pc <= pc;
pc <= next_pc;
p_inst <= next_inst;
int_state <= next_int_state;
end
/* debug code, not synthesized by Xilinx */
$display("IF: PC: %x INST: %x", p_pc, p_inst);
end
end
assign next_pc =
(next_int_state == 2'b10) ? int_pc - 8:
(pc_b & next_int_state != 2'b10) ? b_addr :
(pc_j & !pc_b & next_int_state != 2'b10) ? j_addr :
pc + 4;
assign imem_addr = pc;
endmodule
|
/* copyright 2023 desrep
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
// fixed point multiplier
module mulxbit(in1,in2,out,done);
parameter width = 24;
input wire [width-1:0] in1,in2;
output reg [2*width-1:0] out;
output reg done;
reg [2*width-1:0] out0;
reg [2*width-1:0] partprod0 [width-1:0];
reg [2*width-1:0] partprod1 [width-1:0];
reg done0;
integer i;
wire [2*width-1:0] temp;
assign temp = in1;
always @*
begin
for(i= 0; i<width/4;i=i+1) begin
if( in2[i] == 1'b1)
partprod0[i] = (temp<<i);
if(in2[i+(width/4)]==1'b1)
partprod0[i+(width/4)] = (temp << (i+(width/4)));
if(in2[i+2*(width/4)]==1'b1)
partprod0[i+2*(width/4)] = (temp << (i+2*(width/4)));
if(in2[i+3*(width/4)]==1'b1)
partprod0[i+3*(width/4)] = (temp << (i+3*(width/4)));
if (in2[i] == 1'b0)
partprod0[i] = 1'b0;
if(in2[i+(width/4)]== 1'b0)
partprod0[i+(width/4)] = 1'b0;
if(in2[i+2*(width/4)]== 1'b0)
partprod0[i+2*(width/4)] = 1'b0;
if(in2[i+3*(width/4)]== 1'b0)
partprod0[i+3*(width/4)] = 1'b0;
end
end
always @* begin
out0=0;
done0 = 0;
for(i = 0;i<width/6;i= i+1) begin
out0 = out0 + partprod0[i]+partprod0[i+(width/6)]+ partprod0[i+2*(width/6)]+partprod0[i+3*(width/6)]+partprod0[i+4*(width/6)]+partprod0[i+5*(width/6)];
if(i == (width/6)-1)
done0 = 1;
end
end
always @* begin
out =out0;
done = done0;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../lib/radar_config.vh"
module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Control and configuration outputs
output reset_o;
output tx_side_o;
output dbg_o;
output tx_strobe_o;
output tx_ctrl_o;
output rx_ctrl_o;
output [15:0] ampl_o;
output [31:0] fstart_o;
output [31:0] fincr_o;
output [15:0] pulse_num_o;
output io_tx_ena_o;
// Internal configuration
wire lp_ena;
wire md_ena;
wire dr_ena;
wire [1:0] chirps;
wire [15:0] t_on;
wire [15:0] t_sw;
wire [15:0] t_look;
wire [31:0] t_idle;
wire [31:0] atrdel;
// Configuration from host
wire [31:0] mode;
setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(mode));
assign reset_o = mode[0];
assign tx_side_o = mode[1];
assign lp_ena = mode[2];
assign md_ena = mode[3];
assign dr_ena = mode[4];
assign chirps = mode[6:5];
assign dbg_o = mode[7];
setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_on));
setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_sw));
setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_look));
setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_idle));
setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(ampl_o));
setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fstart_o));
setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fincr_o));
setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(atrdel));
// Pulse state machine
`define ST_ON 4'b0001
`define ST_SW 4'b0010
`define ST_LOOK 4'b0100
`define ST_IDLE 4'b1000
reg [3:0] state;
reg [31:0] count;
reg [15:0] pulse_num_o;
always @(posedge clk_i)
if (reset_o)
begin
state <= `ST_ON;
count <= 32'b0;
pulse_num_o <= 16'b0;
end
else
case (state)
`ST_ON:
if (count == {16'b0,t_on})
begin
state <= `ST_SW;
count <= 32'b0;
pulse_num_o <= pulse_num_o + 16'b1;
end
else
count <= count + 32'b1;
`ST_SW:
if (count == {16'b0,t_sw})
begin
state <= `ST_LOOK;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_LOOK:
if (count == {16'b0,t_look})
begin
state <= `ST_IDLE;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_IDLE:
if (count == t_idle)
begin
state <= `ST_ON;
count <= 32'b0;
end
else
count <= count + 32'b1;
default: // Invalid state, reset state machine
begin
state <= `ST_ON;
count <= 32'b0;
end
endcase
assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
assign tx_ctrl_o = (state == `ST_ON);
assign rx_ctrl_o = (state == `ST_LOOK);
// Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
.tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
.atr_tx_o(io_tx_ena_o));
endmodule // radar_control
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module ERROR_OUTPUT_LOGIC #(
parameter [7:0] DATA_WIDTH = 1,
parameter [7:0] ADDR_WIDTH = 6
) (
input rst,
input clk,
input loop_complete,
input error_detected,
input [7:0] error_state,
input [ADDR_WIDTH-1:0] error_address,
input [DATA_WIDTH-1:0] expected_data,
input [DATA_WIDTH-1:0] actual_data,
// Output to UART
input tx_data_accepted,
output reg tx_data_ready,
output reg [7:0] tx_data
);
reg reg_error_detected;
reg [7:0] reg_error_state;
reg [ADDR_WIDTH-1:0] reg_error_address;
reg [DATA_WIDTH-1:0] reg_expected_data;
reg [DATA_WIDTH-1:0] reg_actual_data;
reg [7:0] error_count;
reg [7:0] output_shift;
wire [7:0] next_output_shift = output_shift + 8;
wire count_shift_done = next_output_shift >= 8'd16;
wire address_shift_done = next_output_shift >= ADDR_WIDTH;
wire data_shift_done = next_output_shift >= DATA_WIDTH;
reg loop_ready;
reg [7:0] latched_error_count;
reg [7:0] errors;
reg [10:0] state;
reg [15:0] loop_count;
reg [15:0] latched_loop_count;
localparam START = (1 << 0),
ERROR_COUNT_HEADER = (1 << 1),
ERROR_COUNT_COUNT = (1 << 2),
CR = (1 << 3),
LF = (1 << 4),
ERROR_HEADER = (1 << 5),
ERROR_STATE = (1 << 6),
ERROR_ADDRESS = (1 << 7),
ERROR_EXPECTED_DATA = (1 << 8),
ERROR_ACTUAL_DATA = (1 << 9),
LOOP_COUNT = (1 << 10);
initial begin
tx_data_ready <= 1'b0;
tx_data <= 8'b0;
state <= START;
reg_error_detected <= 1'b0;
end
always @(posedge clk) begin
if(rst) begin
state <= START;
error_count <= 0;
reg_error_detected <= 0;
tx_data_ready <= 0;
tx_data <= 8'b0;
loop_count <= 0;
loop_ready <= 0;
end else begin
if(error_detected) begin
if(error_count < 255) begin
error_count <= error_count + 1;
end
if(!reg_error_detected) begin
reg_error_detected <= 1;
reg_error_state <= error_state;
reg_error_address <= error_address;
reg_expected_data <= expected_data;
reg_actual_data <= actual_data;
end
end
if(tx_data_accepted) begin
tx_data_ready <= 0;
end
if(loop_complete) begin
loop_count <= loop_count + 1;
if(!loop_ready) begin
loop_ready <= 1;
latched_error_count <= error_count;
latched_loop_count <= loop_count;
error_count <= 0;
end
end
case(state)
START: begin
if(reg_error_detected) begin
state <= ERROR_HEADER;
end else if(loop_ready) begin
state <= ERROR_COUNT_HEADER;
end
end
ERROR_COUNT_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "L";
tx_data_ready <= 1;
state <= ERROR_COUNT_COUNT;
end
end
ERROR_COUNT_COUNT: begin
if(!tx_data_ready) begin
tx_data <= latched_error_count;
tx_data_ready <= 1;
output_shift <= 0;
state <= LOOP_COUNT;
end
end
LOOP_COUNT: begin
if(!tx_data_ready) begin
tx_data <= (latched_loop_count >> output_shift);
tx_data_ready <= 1;
if(count_shift_done) begin
output_shift <= 0;
loop_ready <= 0;
state <= CR;
end else begin
output_shift <= next_output_shift;
end
end
end
CR: begin
if(!tx_data_ready) begin
tx_data <= 8'h0D; // "\r"
tx_data_ready <= 1;
state <= LF;
end
end
LF: begin
if(!tx_data_ready) begin
tx_data <= 8'h0A; // "\n"
tx_data_ready <= 1;
state <= START;
end
end
ERROR_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "E";
tx_data_ready <= 1;
state <= ERROR_STATE;
end
end
ERROR_STATE: begin
if(!tx_data_ready) begin
tx_data <= reg_error_state;
tx_data_ready <= 1;
output_shift <= 0;
state <= ERROR_ADDRESS;
end
end
ERROR_ADDRESS: begin
if(!tx_data_ready) begin
tx_data <= (reg_error_address >> output_shift);
tx_data_ready <= 1;
if(address_shift_done) begin
output_shift <= 0;
state <= ERROR_EXPECTED_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_EXPECTED_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_expected_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
output_shift <= 0;
state <= ERROR_ACTUAL_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_ACTUAL_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_actual_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
state <= CR;
reg_error_detected <= 0;
end else begin
output_shift <= output_shift + 8;
end
end
end
default: begin
state <= START;
end
endcase
end
end
endmodule
|
// copyright 2021 cpu-dev
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
`default_nettype none
module computer(
`ifdef use_power_pins
inout vdd, // user area 1 1.8v supply
inout vss, // user area 1 digital ground
`endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_adr_i,
input [31:0] wbs_dat_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
input [63:0] la_data_in,
output [63:0] la_data_out,
input [63:0] la_oenb,
input [`mprj_io_pads-1:0] io_in,
output [`mprj_io_pads-1:0] io_out,
output [`mprj_io_pads-1:0] io_oeb,
output [2:0] irq
);
wire rx;
wire tx;
assign io_oeb[37:0] = 38'h00_0000_0000;
// uart - gpio
assign io_out[37] = tx;
assign rx = io_in[36];
wire [7:0] instr;
wire [7:0] pc;
wire [7:0] rd_data;
wire [7:0] rs_data;
wire mem_w_en;
wire [7:0] mem_r_data;
wire [7:0] _mem_r_data;
wire busy_flag;
wire receive_flag;
reg tx_en;
reg rx_en;
wire begin_flag;
reg [7:0] tx_data;
wire [7:0] rx_data;
reg [7:0] int_vec;
reg [7:0] int_en;
wire int_req;
wire reg_w_en;
wire [7:0] instr_mem_addr;
wire [7:0] instr_mem_data;
wire instr_mem_en;
wire [7:0] wb_instr_req_addr;
wire [31:0] uart_clk_freq;
assign instr_mem_addr = reset ? wb_instr_req_addr: pc;
reg [7:0] gpio_out;
wire [7:0] gpio_in;
assign io_out[35:28] = gpio_out;
assign gpio_in = io_out[27:20];
wire reset;
assign reset = la_data_in[0];
wire clock;
assign clock = wb_clk_i;
wishbone wb(.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
.instr_mem_addr(wb_instr_req_addr),
.instr_mem_data(instr_mem_data),
.instr_mem_en(instr_mem_en),
.uart_freq(uart_clk_freq)
);
instr_mem instr_mem(.addr(instr_mem_addr),
.w_data(instr_mem_data),
.w_en(instr_mem_en),
.r_data(instr),
.clock(wb_clk_i),
.reset(reset));
cpu cpu(.clock(clock),
.reset(reset),
.instr(instr),
.pc(pc),
.rd_data(rd_data),
.rs_data(rs_data),
.mem_w_en(mem_w_en),
.mem_r_data(mem_r_data),
.int_req(int_req),
.int_en(int_en),
.int_vec(int_vec),
.reg_w_en(reg_w_en));
always @(posedge clock) begin
if(reset) begin
tx_en <= 1'b0;
rx_en <= 1'b0;
end else if(rs_data == 8'd255 && mem_w_en == 1) begin
tx_en <= rd_data[0];
rx_en <= rd_data[1];
end
end
always @(posedge clock) begin
if(reset) begin
tx_data <= 8'b0;
end else if(rs_data == 8'd253 && mem_w_en == 1) begin
tx_data <= rd_data;
end else begin
tx_data <= tx_data;
end
end
always @(posedge clock) begin
if(reset) begin
gpio_out <= 8'b0;
end else if(rs_data == 8'd251 && mem_w_en == 1) begin
gpio_out <= rd_data;
end else begin
gpio_out <= gpio_out;
end
end
assign begin_flag = (rs_data == 8'd253) & (mem_w_en == 1);
data_mem data_mem(.addr(rs_data),
.w_data(rd_data),
.w_en(mem_w_en),
.r_data(_mem_r_data),
.clock(clock));
assign mem_r_data = (rs_data == 8'd254) ? {6'b0, receive_flag, busy_flag}
: (rs_data == 8'd252) ? rx_data
: (rs_data == 8'd251) ? gpio_out
: (rs_data == 8'd250) ? int_vec
: (rs_data == 8'd249) ? gpio_in
: _mem_r_data;
always @(posedge clock) begin
if(reset) begin
int_en <= 8'b0;
end else if(int_req == 1'b1) begin
int_en <= 8'h00;
end else if(int_req == 1'b0) begin
int_en <= 8'h01;
end
end
always @(posedge clock) begin
if(reset) begin
int_vec <= 8'b0;
end else if(rs_data == 8'd250 && mem_w_en == 1'b1) begin
int_vec <= rd_data;
end else begin
int_vec <= int_vec;
end
end
uart uart(.clk(clock),
.reset(reset),
.tx_en(tx_en),
.rx_en(rx_en),
.begin_flag(begin_flag),
.rx(rx),
.tx_data(tx_data),
.tx(tx),
.rx_data(rx_data),
.busy_flag(busy_flag),
.receive_flag(receive_flag),
.int_req(int_req),
.access_addr(rs_data),
.reg_w_en(reg_w_en),
.clk_freq(uart_clk_freq)
);
endmodule
|
`timescale 1ns / 1ps
/*
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF530 (Terrible Fire 030 Accelerator).
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module tf530_bus(
// clocks
input CLKCPU,
input CLK7M,
// internal signals
input INTSIG,
// address bus / spec
input [2:0] FC,
input [1:0] SIZ,
input A0,
input [23:12] A,
// 68030 ASync bus
input AS20,
input DS20,
input RW20,
output [1:0] DSACK,
// exception handling.
output AVEC,
output BERR,
// FPU signals.
output CPCS,
input CPSENSE,
// IDE signals
//input INT2,
input IDEWAIT,
output [1:0] IDECS, // IDE Chip Selects
output IOR, // IDE Read Strobe
output IOW, // IDE Write Strobe
output OVR, // Disable Gary Decode.
// 68000 ASync Bus
output AS,
output LDS,
output UDS,
output RW00,
input DTACK,
// bus arbitration
input BG20,
output BG,
input BGACK,
// synchronous bus
output VMA,
input VPA,
output reg E
);
wire DS20DLY;
wire AS20DLY;
reg SYSDSACK1 = 1'b1;
reg RW20DLY = 1'b1;
reg CLK7MB2 = 1'b1;
reg BGACKD1 = 1'b1;
reg BGACKD2 = 1'b1;
reg DTQUAL = 1'b1;
reg [3:0] Q = 'hF;
reg VMA_SYNC = 1'b1;
initial begin
E = 'b0;
end
wire DTRIG;
wire CPUSPACE = &FC;
wire FPUOP = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});
wire DTACKPRELIM = CLK7M | CLK7MB2;
wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20 | FPUOP;
assign CPCS = ~FPUOP | AS20;
FDCP #(.INIT(1'b1))
AS20DLY_FF (
.Q(AS20DLY), // Data output
.C(CLK7M), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(AS20), // Data input
.PRE(AS20 | FPUOP | ~INTSIG) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
ASDLY_FF (
.Q(ASDLY), // Data output
.C(CLK7M), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(AS), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
DS20DLY_FF (
.Q(DS20DLY), // Data output
.C(CLK7M), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(DS20), // Data input
.PRE(DS20 | FPUOP | ~INTSIG) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
DTTRIG1_FF (
.Q(DSACK1INT), // Data output
.C(~DTRIG), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(AS | ~INTSIG), // Data input
.PRE(AS) // Asynchronous set input
);
// hold off DTACK until the IDE device is ready.
wire DTACKMOO = AS | ASDLY | DTACK | ~IDEWAIT;
FDCP #(.INIT(1'b1))
DTTACK1_FF (
.Q(DTACK_INT1), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(DTACKMOO), // Data input
.PRE(DTACKMOO | ~INTSIG) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
DTTACK2_FF (
.Q(DTACK_INT2), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(DTACK_INT1), // Data input
.PRE(DTACK_INT1) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
DTTACK3_FF (
.Q(DTACK_INT3), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(DTACK_INT2), // Data input
.PRE(DTACK_INT2) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
DTTACK4_FF (
.Q(DTACK_INT4), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(DTACK_INT3), // Data input
.PRE(DTACK_INT3) // Asynchronous set input
);
reg DTRIG_SYNC = 1'b1;
reg DTRIG_SYNC_D = 1'b1;
reg DTRIG_SYNC_D2 = 1'b1;
reg DTRIG_SYNC_D3 = 1'b1;
reg DTRIG_SYNC_D4 = 1'b1;
reg DTRIG_SYNC_D5 = 1'b1;
always @(posedge CLKCPU) begin
SYSDSACK1 <= DSACK1INT | FPUOP ;
DTRIG_SYNC <= ~Q[3] | VMA_SYNC | ~DTRIG_SYNC | ~DTRIG_SYNC_D | ~DTRIG_SYNC_D2 | ~DTRIG_SYNC_D3 | ~DTRIG_SYNC_D4 | ~DTRIG_SYNC_D5;
DTRIG_SYNC_D <= DTRIG_SYNC;
DTRIG_SYNC_D2 <= DTRIG_SYNC_D;
DTRIG_SYNC_D3 <= DTRIG_SYNC_D2;
DTRIG_SYNC_D4 <= DTRIG_SYNC_D3;
DTRIG_SYNC_D5 <= DTRIG_SYNC_D4;
end
always @(posedge CLK7M) begin
DTQUAL <= AS20 | FPUOP;
RW20DLY <= RW20;
BGACKD1 <= BGACK;
BGACKD2 <= BGACKD1;
// 7Mhz Clock divided by 2
CLK7MB2 <= ~CLK7MB2;
if (Q == 'd9) begin
VMA_SYNC <= 1'b1;
Q <= 'd0;
end else begin
Q <= Q + 'd1;
if (Q == 'd4) begin
E <= 'b1;
end
if (Q == 'd8) begin
E <= 'b0;
end
if (Q == 'd2) begin
VMA_SYNC <= (VPA | CPUSPACE);
end
end
end
//wire HIGHZ = BG20 | //(BG20 & (AS20DLY | AS20)) | CPUSPACE;
wire DSHOLD = {ASDLY,AS, RW00} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW00 | GAYLE_IDE | DSHOLD;
wire IOW_INT = RW00 | GAYLE_IDE | DSHOLD;
FDCP #(.INIT(1'b1))
IOR_FF (
.Q(IOR), // Data output
.C(~CLK7M), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOR_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
IOW_FF (
.Q(IOW), // Data output
.C(~CLK7M), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOW_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
wire HIGHZ = ~BGACK;
wire AS_INT = AS20DLY | AS20;
wire UDS_INT = DS20 | AS | DSHOLD | A0;
wire LDS_INT = DS20 | AS | DSHOLD | ({A0, SIZ[1:0]} == 3'b001);
wire VMA_INT = VMA_SYNC;
assign RW00 = HIGHZ ? 1'bz : AS | RW20;
assign AS = HIGHZ ? 1'bz : AS_INT;
assign UDS = HIGHZ ? 1'bz : UDS_INT;
assign LDS = HIGHZ ? 1'bz : LDS_INT;
assign VMA = HIGHZ ? 1'bz : VMA_INT;
assign DTRIG = (DTACK_INT3| DTQUAL) & DTRIG_SYNC_D5;
assign DSACK[1] = (AS20DLY | AS20 | SYSDSACK1);
assign DSACK[0] = 1'b1; // | ~INTSIG | DSACK[1];
assign BG = AS ? BG20 : 1'bz;
assign BERR = CPCS | ~CPSENSE;
assign AVEC = ~IACK | VPA;
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE};
assign OVR = INTSIG;
endmodule
|
/*
copyright 2023 efabless corp.
author: mohamed shalan (mshalan@efabless.com)
this file is auto-generated by wrapper_gen.py
licensed under the apache license, version 2.0 (the "license");
you may not use this file except in compliance with the license.
you may obtain a copy of the license at
http://www.apache.org/licenses/license-2.0
unless required by applicable law or agreed to in writing, software
distributed under the license is distributed on an "as is" basis,
without warranties or conditions of any kind, either express or implied.
see the license for the specific language governing permissions and
limitations under the license.
*/
`timescale 1ns/1ns
`default_nettype none
module ef_acmp_di_ahbl (
output wire sela,
output wire selb,
input wire vo,
input wire hclk,
input wire hresetn,
input wire [31:0] haddr,
input wire hwrite,
input wire [1:0] htrans,
input wire hready,
input wire hsel,
input wire [2:0] hsize,
input wire [31:0] hwdata,
output wire [31:0] hrdata,
output wire hreadyout,
output wire irq
);
localparam[15:0] sel_reg_addr = 16'h0000;
localparam[15:0] icr_reg_addr = 16'h0f00;
localparam[15:0] ris_reg_addr = 16'h0f04;
localparam[15:0] im_reg_addr = 16'h0f08;
localparam[15:0] mis_reg_addr = 16'h0f0c;
reg last_hsel;
reg [31:0] last_haddr;
reg last_hwrite;
reg [1:0] last_htrans;
always@ (posedge hclk) begin
if(hready) begin
last_hsel <= hsel;
last_haddr <= haddr;
last_hwrite <= hwrite;
last_htrans <= htrans;
end
end
reg [1:0] sel_reg;
reg [0:0] ris_reg;
reg [0:0] icr_reg;
reg [0:0] im_reg;
wire di_sela = sel_reg[0:0];
wire di_selb = sel_reg[1:1];
wire di_vo;
wire _hi_flag_ = di_vo;
wire mis_reg = ris_reg & im_reg;
wire ahbl_valid = last_hsel & last_htrans[1];
wire ahbl_we = last_hwrite & ahbl_valid;
wire ahbl_re = ~last_hwrite & ahbl_valid;
wire _clk_ = hclk;
wire _rst_ = ~hresetn;
ef_acmp_di inst_to_wrap (
.sela(sela),
.selb(selb),
.vo(vo),
.di_sela(di_sela),
.di_selb(di_selb),
.di_vo(di_vo)
);
always @(posedge hclk or negedge hresetn) if(~hresetn) sel_reg <= 0; else if(ahbl_we & (last_haddr==sel_reg_addr)) sel_reg <= hwdata;
always @(posedge hclk or negedge hresetn) if(~hresetn) im_reg <= 0; else if(ahbl_we & (last_haddr==im_reg_addr)) im_reg <= hwdata;
always @(posedge hclk or negedge hresetn) if(~hresetn) icr_reg <= 1'b0; else if(ahbl_we & (last_haddr==icr_reg_addr)) icr_reg <= hwdata; else icr_reg <= 1'd0;
always @(posedge hclk or negedge hresetn)
if(~hresetn) ris_reg <= 32'd0;
else begin
if(_hi_flag_) ris_reg[0] <= 1'b1; else if(icr_reg[0]) ris_reg[0] <= 1'b0;
end
assign irq = |mis_reg;
assign hrdata =
(last_haddr == sel_reg_addr) ? sel_reg :
(last_haddr == ris_reg_addr) ? ris_reg :
(last_haddr == icr_reg_addr) ? icr_reg :
(last_haddr == im_reg_addr) ? im_reg :
(last_haddr == mis_reg_addr) ? mis_reg :
32'hdeadbeef;
assign hreadyout = 1'b1;
endmodule
|
// copyright 2022 globalfoundries pdk authors
//
// licensed under the apache license, version 2.0 (the "license");
// you may not use this file except in compliance with the license.
// you may obtain a copy of the license at
//
// http://www.apache.org/licenses/license-2.0
//
// unless required by applicable law or agreed to in writing, software
// distributed under the license is distributed on an "as is" basis,
// without warranties or conditions of any kind, either express or implied.
// see the license for the specific language governing permissions and
// limitations under the license.
module gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1( se, si, d, clk, rn, q, vdd, vss );
input clk, d, rn, se, si;
inout vdd, vss;
output q;
reg notifier;
`ifdef functional // functional //
gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1_func gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1_behav_inst(.se(se),.si(si),.d(d),.clk(clk),.rn(rn),.q(q),.vdd(vdd),.vss(vss),.notifier(notifier));
`else
gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1_func gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1_inst(.se(se),.si(si),.d(d),.clk(clk),.rn(rn),.q(q),.vdd(vdd),.vss(vss),.notifier(notifier));
// spec_gates_begin
not mgm_g0(mgm_w0,d);
and mgm_g1(mgm_w1,rn,mgm_w0);
not mgm_g2(mgm_w2,se);
and mgm_g3(mgm_w3,mgm_w2,mgm_w1);
not mgm_g4(mgm_w4,si);
and mgm_g5(enable_not_d_and_rn_and_not_se_and_not_si,mgm_w4,mgm_w3);
not mgm_g6(mgm_w5,d);
and mgm_g7(mgm_w6,rn,mgm_w5);
not mgm_g8(mgm_w7,se);
and mgm_g9(mgm_w8,mgm_w7,mgm_w6);
and mgm_g10(enable_not_d_and_rn_and_not_se_and_si,si,mgm_w8);
not mgm_g11(mgm_w9,d);
and mgm_g12(mgm_w10,rn,mgm_w9);
and mgm_g13(mgm_w11,se,mgm_w10);
not mgm_g14(mgm_w12,si);
and mgm_g15(enable_not_d_and_rn_and_se_and_not_si,mgm_w12,mgm_w11);
not mgm_g16(mgm_w13,d);
and mgm_g17(mgm_w14,rn,mgm_w13);
and mgm_g18(mgm_w15,se,mgm_w14);
and mgm_g19(enable_not_d_and_rn_and_se_and_si,si,mgm_w15);
and mgm_g20(mgm_w16,rn,d);
not mgm_g21(mgm_w17,se);
and mgm_g22(mgm_w18,mgm_w17,mgm_w16);
not mgm_g23(mgm_w19,si);
and mgm_g24(enable_d_and_rn_and_not_se_and_not_si,mgm_w19,mgm_w18);
and mgm_g25(mgm_w20,rn,d);
not mgm_g26(mgm_w21,se);
and mgm_g27(mgm_w22,mgm_w21,mgm_w20);
and mgm_g28(enable_d_and_rn_and_not_se_and_si,si,mgm_w22);
and mgm_g29(mgm_w23,rn,d);
and mgm_g30(mgm_w24,se,mgm_w23);
not mgm_g31(mgm_w25,si);
and mgm_g32(enable_d_and_rn_and_se_and_not_si,mgm_w25,mgm_w24);
and mgm_g33(mgm_w26,rn,d);
and mgm_g34(mgm_w27,se,mgm_w26);
and mgm_g35(enable_d_and_rn_and_se_and_si,si,mgm_w27);
not mgm_g36(mgm_w28,se);
and mgm_g37(mgm_w29,mgm_w28,rn);
not mgm_g38(mgm_w30,si);
and mgm_g39(enable_rn_and_not_se_and_not_si,mgm_w30,mgm_w29);
not mgm_g40(mgm_w31,se);
and mgm_g41(mgm_w32,mgm_w31,rn);
and mgm_g42(enable_rn_and_not_se_and_si,si,mgm_w32);
not mgm_g43(mgm_w33,d);
and mgm_g44(mgm_w34,se,mgm_w33);
and mgm_g45(enable_not_d_and_se_and_si,si,mgm_w34);
not mgm_g46(mgm_w35,se);
and mgm_g47(mgm_w36,mgm_w35,d);
not mgm_g48(mgm_w37,si);
and mgm_g49(enable_d_and_not_se_and_not_si,mgm_w37,mgm_w36);
not mgm_g50(mgm_w38,se);
and mgm_g51(mgm_w39,mgm_w38,d);
and mgm_g52(enable_d_and_not_se_and_si,si,mgm_w39);
and mgm_g53(mgm_w40,se,d);
and mgm_g54(enable_d_and_se_and_si,si,mgm_w40);
not mgm_g55(mgm_w41,clk);
not mgm_g56(mgm_w42,d);
and mgm_g57(mgm_w43,mgm_w42,mgm_w41);
not mgm_g58(mgm_w44,se);
and mgm_g59(mgm_w45,mgm_w44,mgm_w43);
not mgm_g60(mgm_w46,si);
and mgm_g61(enable_not_clk_and_not_d_and_not_se_and_not_si,mgm_w46,mgm_w45);
not mgm_g62(mgm_w47,clk);
not mgm_g63(mgm_w48,d);
and mgm_g64(mgm_w49,mgm_w48,mgm_w47);
not mgm_g65(mgm_w50,se);
and mgm_g66(mgm_w51,mgm_w50,mgm_w49);
and mgm_g67(enable_not_clk_and_not_d_and_not_se_and_si,si,mgm_w51);
not mgm_g68(mgm_w52,clk);
not mgm_g69(mgm_w53,d);
and mgm_g70(mgm_w54,mgm_w53,mgm_w52);
and mgm_g71(mgm_w55,se,mgm_w54);
not mgm_g72(mgm_w56,si);
and mgm_g73(enable_not_clk_and_not_d_and_se_and_not_si,mgm_w56,mgm_w55);
not mgm_g74(mgm_w57,clk);
not mgm_g75(mgm_w58,d);
and mgm_g76(mgm_w59,mgm_w58,mgm_w57);
and mgm_g77(mgm_w60,se,mgm_w59);
and mgm_g78(enable_not_clk_and_not_d_and_se_and_si,si,mgm_w60);
not mgm_g79(mgm_w61,clk);
and mgm_g80(mgm_w62,d,mgm_w61);
not mgm_g81(mgm_w63,se);
and mgm_g82(mgm_w64,mgm_w63,mgm_w62);
not mgm_g83(mgm_w65,si);
and mgm_g84(enable_not_clk_and_d_and_not_se_and_not_si,mgm_w65,mgm_w64);
not mgm_g85(mgm_w66,clk);
and mgm_g86(mgm_w67,d,mgm_w66);
not mgm_g87(mgm_w68,se);
and mgm_g88(mgm_w69,mgm_w68,mgm_w67);
and mgm_g89(enable_not_clk_and_d_and_not_se_and_si,si,mgm_w69);
not mgm_g90(mgm_w70,clk);
and mgm_g91(mgm_w71,d,mgm_w70);
and mgm_g92(mgm_w72,se,mgm_w71);
not mgm_g93(mgm_w73,si);
and mgm_g94(enable_not_clk_and_d_and_se_and_not_si,mgm_w73,mgm_w72);
not mgm_g95(mgm_w74,clk);
and mgm_g96(mgm_w75,d,mgm_w74);
and mgm_g97(mgm_w76,se,mgm_w75);
and mgm_g98(enable_not_clk_and_d_and_se_and_si,si,mgm_w76);
not mgm_g99(mgm_w77,d);
and mgm_g100(mgm_w78,mgm_w77,clk);
not mgm_g101(mgm_w79,se);
and mgm_g102(mgm_w80,mgm_w79,mgm_w78);
not mgm_g103(mgm_w81,si);
and mgm_g104(enable_clk_and_not_d_and_not_se_and_not_si,mgm_w81,mgm_w80);
not mgm_g105(mgm_w82,d);
and mgm_g106(mgm_w83,mgm_w82,clk);
not mgm_g107(mgm_w84,se);
and mgm_g108(mgm_w85,mgm_w84,mgm_w83);
and mgm_g109(enable_clk_and_not_d_and_not_se_and_si,si,mgm_w85);
not mgm_g110(mgm_w86,d);
and mgm_g111(mgm_w87,mgm_w86,clk);
and mgm_g112(mgm_w88,se,mgm_w87);
not mgm_g113(mgm_w89,si);
and mgm_g114(enable_clk_and_not_d_and_se_and_not_si,mgm_w89,mgm_w88);
not mgm_g115(mgm_w90,d);
and mgm_g116(mgm_w91,mgm_w90,clk);
and mgm_g117(mgm_w92,se,mgm_w91);
and mgm_g118(enable_clk_and_not_d_and_se_and_si,si,mgm_w92);
and mgm_g119(mgm_w93,d,clk);
not mgm_g120(mgm_w94,se);
and mgm_g121(mgm_w95,mgm_w94,mgm_w93);
not mgm_g122(mgm_w96,si);
and mgm_g123(enable_clk_and_d_and_not_se_and_not_si,mgm_w96,mgm_w95);
and mgm_g124(mgm_w97,d,clk);
not mgm_g125(mgm_w98,se);
and mgm_g126(mgm_w99,mgm_w98,mgm_w97);
and mgm_g127(enable_clk_and_d_and_not_se_and_si,si,mgm_w99);
and mgm_g128(mgm_w100,d,clk);
and mgm_g129(mgm_w101,se,mgm_w100);
not mgm_g130(mgm_w102,si);
and mgm_g131(enable_clk_and_d_and_se_and_not_si,mgm_w102,mgm_w101);
and mgm_g132(mgm_w103,d,clk);
and mgm_g133(mgm_w104,se,mgm_w103);
and mgm_g134(enable_clk_and_d_and_se_and_si,si,mgm_w104);
not mgm_g135(mgm_w105,d);
and mgm_g136(mgm_w106,rn,mgm_w105);
and mgm_g137(enable_not_d_and_rn_and_si,si,mgm_w106);
and mgm_g138(mgm_w107,rn,d);
not mgm_g139(mgm_w108,si);
and mgm_g140(enable_d_and_rn_and_not_si,mgm_w108,mgm_w107);
not mgm_g141(mgm_w109,d);
and mgm_g142(mgm_w110,rn,mgm_w109);
and mgm_g143(enable_not_d_and_rn_and_se,se,mgm_w110);
and mgm_g144(mgm_w111,rn,d);
and mgm_g145(enable_d_and_rn_and_se,se,mgm_w111);
// spec_gates_end
specify
// specify_block_begin
if(d===1'b0 && si===1'b1)
// seq arc clk --> q
(posedge clk => (q : se)) = (1.0,1.0);
if(se===1'b0 && si===1'b0)
// seq arc clk --> q
(posedge clk => (q : d)) = (1.0,1.0);
if(d===1'b1 && se===1'b0 && si===1'b1 || d===1'b0 && se===1'b1 && si===1'b0)
// seq arc clk --> q
(posedge clk => (q : d)) = (1.0,1.0);
if(d===1'b1 && se===1'b1)
// seq arc clk --> q
(posedge clk => (q : si)) = (1.0,1.0);
ifnone
// seq arc clk --> q
(posedge clk => (q : d)) = (1.0,1.0);
if(clk===1'b0 && d===1'b0 && se===1'b0 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b0 && se===1'b0 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b0 && se===1'b1 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b0 && se===1'b1 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b1 && se===1'b0 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b1 && se===1'b0 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b1 && se===1'b1 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b0 && d===1'b1 && se===1'b1 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b0 && se===1'b0 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b0 && se===1'b0 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b0 && se===1'b1 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b0 && se===1'b1 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b1 && se===1'b0 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b1 && se===1'b0 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b1 && se===1'b1 && si===1'b0)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
if(clk===1'b1 && d===1'b1 && se===1'b1 && si===1'b1)
// seq arc rn --> q
(rn => q) = (1.0,1.0);
ifnone
// seq arc rn --> q
(rn => q) = (1.0,1.0);
$width(negedge clk &&& (enable_not_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_not_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_not_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_not_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_not_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_not_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_not_d_and_rn_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_not_d_and_rn_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge clk &&& (enable_d_and_rn_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(posedge clk &&& (enable_d_and_rn_and_se_and_si === 1'b1)
,1.0,0,notifier);
// hold d-hl clk-lh
$hold(posedge clk &&& (enable_rn_and_not_se_and_not_si === 1'b1),
negedge d &&& (enable_rn_and_not_se_and_not_si === 1'b1),1.0,notifier);
// hold d-lh clk-lh
$hold(posedge clk &&& (enable_rn_and_not_se_and_not_si === 1'b1),
posedge d &&& (enable_rn_and_not_se_and_not_si === 1'b1),1.0,notifier);
// setup d-hl clk-lh
$setup(negedge d &&& (enable_rn_and_not_se_and_not_si === 1'b1),
posedge clk &&& (enable_rn_and_not_se_and_not_si === 1'b1),1.0,notifier);
// setup d-lh clk-lh
$setup(posedge d &&& (enable_rn_and_not_se_and_not_si === 1'b1),
posedge clk &&& (enable_rn_and_not_se_and_not_si === 1'b1),1.0,notifier);
// hold d-hl clk-lh
$hold(posedge clk &&& (enable_rn_and_not_se_and_si === 1'b1),
negedge d &&& (enable_rn_and_not_se_and_si === 1'b1),1.0,notifier);
// hold d-lh clk-lh
$hold(posedge clk &&& (enable_rn_and_not_se_and_si === 1'b1),
posedge d &&& (enable_rn_and_not_se_and_si === 1'b1),1.0,notifier);
// setup d-hl clk-lh
$setup(negedge d &&& (enable_rn_and_not_se_and_si === 1'b1),
posedge clk &&& (enable_rn_and_not_se_and_si === 1'b1),1.0,notifier);
// setup d-lh clk-lh
$setup(posedge d &&& (enable_rn_and_not_se_and_si === 1'b1),
posedge clk &&& (enable_rn_and_not_se_and_si === 1'b1),1.0,notifier);
// recovery rn-lh clk-lh
$recovery(posedge rn &&& (enable_not_d_and_se_and_si === 1'b1),
posedge clk &&& (enable_not_d_and_se_and_si === 1'b1),1.0,notifier);
// removal rn-lh clk-lh
$removal(posedge rn &&& (enable_not_d_and_se_and_si === 1'b1),
posedge clk &&& (enable_not_d_and_se_and_si === 1'b1),1.0,notifier);
// recovery rn-lh clk-lh
$recovery(posedge rn &&& (enable_d_and_not_se_and_not_si === 1'b1),
posedge clk &&& (enable_d_and_not_se_and_not_si === 1'b1),1.0,notifier);
// removal rn-lh clk-lh
$removal(posedge rn &&& (enable_d_and_not_se_and_not_si === 1'b1),
posedge clk &&& (enable_d_and_not_se_and_not_si === 1'b1),1.0,notifier);
// recovery rn-lh clk-lh
$recovery(posedge rn &&& (enable_d_and_not_se_and_si === 1'b1),
posedge clk &&& (enable_d_and_not_se_and_si === 1'b1),1.0,notifier);
// removal rn-lh clk-lh
$removal(posedge rn &&& (enable_d_and_not_se_and_si === 1'b1),
posedge clk &&& (enable_d_and_not_se_and_si === 1'b1),1.0,notifier);
// recovery rn-lh clk-lh
$recovery(posedge rn &&& (enable_d_and_se_and_si === 1'b1),
posedge clk &&& (enable_d_and_se_and_si === 1'b1),1.0,notifier);
// removal rn-lh clk-lh
$removal(posedge rn &&& (enable_d_and_se_and_si === 1'b1),
posedge clk &&& (enable_d_and_se_and_si === 1'b1),1.0,notifier);
$width(negedge rn &&& (enable_not_clk_and_not_d_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_not_d_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_not_d_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_not_d_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_d_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_d_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_d_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_not_clk_and_d_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_not_d_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_not_d_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_not_d_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_not_d_and_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_d_and_not_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_d_and_not_se_and_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_d_and_se_and_not_si === 1'b1)
,1.0,0,notifier);
$width(negedge rn &&& (enable_clk_and_d_and_se_and_si === 1'b1)
,1.0,0,notifier);
// hold se-hl clk-lh
$hold(posedge clk &&& (enable_not_d_and_rn_and_si === 1'b1),
negedge se &&& (enable_not_d_and_rn_and_si === 1'b1),1.0,notifier);
// hold se-lh clk-lh
$hold(posedge clk &&& (enable_not_d_and_rn_and_si === 1'b1),
posedge se &&& (enable_not_d_and_rn_and_si === 1'b1),1.0,notifier);
// setup se-hl clk-lh
$setup(negedge se &&& (enable_not_d_and_rn_and_si === 1'b1),
posedge clk &&& (enable_not_d_and_rn_and_si === 1'b1),1.0,notifier);
// setup se-lh clk-lh
$setup(posedge se &&& (enable_not_d_and_rn_and_si === 1'b1),
posedge clk &&& (enable_not_d_and_rn_and_si === 1'b1),1.0,notifier);
// hold se-hl clk-lh
$hold(posedge clk &&& (enable_d_and_rn_and_not_si === 1'b1),
negedge se &&& (enable_d_and_rn_and_not_si === 1'b1),1.0,notifier);
// hold se-lh clk-lh
$hold(posedge clk &&& (enable_d_and_rn_and_not_si === 1'b1),
posedge se &&& (enable_d_and_rn_and_not_si === 1'b1),1.0,notifier);
// setup se-hl clk-lh
$setup(negedge se &&& (enable_d_and_rn_and_not_si === 1'b1),
posedge clk &&& (enable_d_and_rn_and_not_si === 1'b1),1.0,notifier);
// setup se-lh clk-lh
$setup(posedge se &&& (enable_d_and_rn_and_not_si === 1'b1),
posedge clk &&& (enable_d_and_rn_and_not_si === 1'b1),1.0,notifier);
// hold si-hl clk-lh
$hold(posedge clk &&& (enable_not_d_and_rn_and_se === 1'b1),
negedge si &&& (enable_not_d_and_rn_and_se === 1'b1),1.0,notifier);
// hold si-lh clk-lh
$hold(posedge clk &&& (enable_not_d_and_rn_and_se === 1'b1),
posedge si &&& (enable_not_d_and_rn_and_se === 1'b1),1.0,notifier);
// setup si-hl clk-lh
$setup(negedge si &&& (enable_not_d_and_rn_and_se === 1'b1),
posedge clk &&& (enable_not_d_and_rn_and_se === 1'b1),1.0,notifier);
// setup si-lh clk-lh
$setup(posedge si &&& (enable_not_d_and_rn_and_se === 1'b1),
posedge clk &&& (enable_not_d_and_rn_and_se === 1'b1),1.0,notifier);
// hold si-hl clk-lh
$hold(posedge clk &&& (enable_d_and_rn_and_se === 1'b1),
negedge si &&& (enable_d_and_rn_and_se === 1'b1),1.0,notifier);
// hold si-lh clk-lh
$hold(posedge clk &&& (enable_d_and_rn_and_se === 1'b1),
posedge si &&& (enable_d_and_rn_and_se === 1'b1),1.0,notifier);
// setup si-hl clk-lh
$setup(negedge si &&& (enable_d_and_rn_and_se === 1'b1),
posedge clk &&& (enable_d_and_rn_and_se === 1'b1),1.0,notifier);
// setup si-lh clk-lh
$setup(posedge si &&& (enable_d_and_rn_and_se === 1'b1),
posedge clk &&& (enable_d_and_rn_and_se === 1'b1),1.0,notifier);
// mpw clk_lh
$width(posedge clk,1.0,0,notifier);
// mpw clk_hl
$width(negedge clk,1.0,0,notifier);
// mpw rn_hl
$width(negedge rn,1.0,0,notifier);
// period clk
$period(posedge clk &&& (enable_not_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_not_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_not_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_not_d_and_rn_and_se_and_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_d_and_rn_and_not_se_and_not_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_d_and_rn_and_not_se_and_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_d_and_rn_and_se_and_not_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk &&& (enable_d_and_rn_and_se_and_si === 1'b1)
,1.0,notifier);
// period clk
$period(posedge clk,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
|
/*
* yet another dynamic memory controller
* copyright (c) 2008 sebastien bourdeauducq - http://lekernel.net
* this file is part of milkymist.
*
* milkymist is free software; you can redistribute it and/or modify it
* under the terms of the gnu library general public license as published
* by the free software foundation; either version 2, or (at your option)
* any later version.
*
* this program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* merchantability or fitness for a particular purpose. see the gnu
* library general public license for more details.
*
* you should have received a copy of the gnu library general public
* license along with this program; if not, write to the free software
* foundation, inc., 51 franklin street, fifth floor, boston, ma 02110-1301,
* usa.
*/
`timescale 1ns / 1ps
module yadmc_test();
reg sys_clk;
reg sys_rst;
reg sdram_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg [3:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [1:0] sdram_dqm;
wire [12:0] sdram_adr;
wire [1:0] sdram_ba;
wire [15:0] sdram_dq;
yadmc dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.sdram_clk(sdram_clk),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dqm(sdram_dqm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq)
);
mt48lc16m16a2 sdram(
.dq(sdram_dq),
.addr(sdram_adr),
.ba(sdram_ba),
.clk(sdram_clk),
.cke(sdram_cke),
.cs_n(sdram_cs_n),
.ras_n(sdram_ras_n),
.cas_n(sdram_cas_n),
.we_n(sdram_we_n),
.dqm(sdram_dqm)
);
/* generate 125 mhz sdram clock */
initial sdram_clk <= 0;
always #4 sdram_clk <= ~sdram_clk;
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_sel_i = 4'hf;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 1;
while(~wb_ack_o) begin
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
i = i + 1;
end
$display("write address %h completed in %d cycles", address, i);
/* let the core release its ack */
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
wb_we_i = 1'b1;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_sel_i = 4'hf;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 1;
while(~wb_ack_o) begin
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
i = i + 1;
end
$display("read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
/* let the core release its ack */
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
integer i;
initial begin
sys_rst = 1'b1;
sys_clk = 1'b0;
wb_adr_i = 32'h00044000;
wb_dat_i = 32'h00000000;
wb_sel_i = 4'hf;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b0;
wb_we_i = 1'b1;
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
sys_rst = 1'b0;
for(i=0;i<6000;i=i+1) begin
#10 sys_clk = 1'b1;
#10 sys_clk = 1'b0;
end
/*wbwrite(32'h00044000, 32'hcafebabe);
wbwrite(32'h00044004, 32'hdeadbeef);
wbwrite(32'h00064000, 32'h12345678);
wbwrite(32'h00064004, 32'habcd4241);
wbread(32'h00044000);
wbread(32'h00044004);
$display("contents of the cache line:");
wbread(32'h00044000);
wbread(32'h00044004);
wbread(32'h00044008);
wbread(32'h0004400c);*/
for(i=0;i<800;i=i+1)
wbwrite(4*i, i);
//wbread(32'b000000000000000000010110000);
//wbwrite(32'h00000010, 32'hcafebabe);
//wbwrite(32'h00000050, 32'hcafebabe);
//wbwrite(32'h00000090, 32'hcafebabe);
$finish;
end
endmodule
/**************************************************************************
*
* file name: mt48lc16m16a2.v
* version: 2.1
* date: june 6th, 2002
* model: bus functional
* simulator: model technology
*
* dependencies: none
*
* email: modelsupport@micron.com
* company: micron technology, inc.
* model: mt48lc16m16a2 (4meg x 16 x 4 banks)
*
* description: micron 256mb sdram verilog model
*
* limitation: - doesn't check for 8192 cycle refresh
*
* note: - set simulator resolution to "ps" accuracy
* - set debug = 0 to disable $display messages
*
* disclaimer: these designs are provided "as is" with no warranty
* whatsoever and micron specifically disclaims any
* implied warranties of merchantability, fitness for
* a particular purpose, or against infringement.
*
* copyright � 2001 micron semiconductor products, inc.
* all rights researved
*
* rev author date changes
* --- -------------------------- ---------------------------------------
* 2.1 sh 06/06/2002 - typo in bank multiplex
* micron technology inc.
*
* 2.0 sh 04/30/2002 - second release
* micron technology inc.
*
**************************************************************************/
`timescale 1ns / 1ps
module mt48lc16m16a2 (dq, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm);
parameter addr_bits = 13;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 4194303;
inout [data_bits - 1 : 0] dq;
input [addr_bits - 1 : 0] addr;
input [1 : 0] ba;
input clk;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
input [1 : 0] dqm;
reg [data_bits - 1 : 0] bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] bank3 [0 : mem_sizes];
reg [1 : 0] bank_addr [0 : 3]; // bank address pipeline
reg [col_bits - 1 : 0] col_addr [0 : 3]; // column address pipeline
reg [3 : 0] command [0 : 3]; // command operation pipeline
reg [1 : 0] dqm_reg0, dqm_reg1; // dqm operation pipeline
reg [addr_bits - 1 : 0] b0_row_addr, b1_row_addr, b2_row_addr, b3_row_addr;
reg [addr_bits - 1 : 0] mode_reg;
reg [data_bits - 1 : 0] dq_reg, dq_dqm;
reg [col_bits - 1 : 0] col_temp, burst_counter;
reg act_b0, act_b1, act_b2, act_b3; // bank activate
reg pc_b0, pc_b1, pc_b2, pc_b3; // bank precharge
reg [1 : 0] bank_precharge [0 : 3]; // precharge command
reg a10_precharge [0 : 3]; // addr[10] = 1 (all banks)
reg auto_precharge [0 : 3]; // rw auto precharge (bank)
reg read_precharge [0 : 3]; // r auto precharge
reg write_precharge [0 : 3]; // w auto precharge
reg rw_interrupt_read [0 : 3]; // rw interrupt read with auto precharge
reg rw_interrupt_write [0 : 3]; // rw interrupt write with auto precharge
reg [1 : 0] rw_interrupt_bank; // rw interrupt bank
integer rw_interrupt_counter [0 : 3]; // rw interrupt counter
integer count_precharge [0 : 3]; // rw auto precharge counter
reg data_in_enable;
reg data_out_enable;
reg [1 : 0] bank, prev_bank;
reg [addr_bits - 1 : 0] row;
reg [col_bits - 1 : 0] col, col_brst;
// internal system clock
reg ckez, sys_clk;
// commands decode
wire active_enable = ~cs_n & ~ras_n & cas_n & we_n;
wire aref_enable = ~cs_n & ~ras_n & ~cas_n & we_n;
wire burst_term = ~cs_n & ras_n & cas_n & ~we_n;
wire mode_reg_enable = ~cs_n & ~ras_n & ~cas_n & ~we_n;
wire prech_enable = ~cs_n & ~ras_n & cas_n & ~we_n;
wire read_enable = ~cs_n & ras_n & ~cas_n & we_n;
wire write_enable = ~cs_n & ras_n & ~cas_n & ~we_n;
// burst length decode
wire burst_length_1 = ~mode_reg[2] & ~mode_reg[1] & ~mode_reg[0];
wire burst_length_2 = ~mode_reg[2] & ~mode_reg[1] & mode_reg[0];
wire burst_length_4 = ~mode_reg[2] & mode_reg[1] & ~mode_reg[0];
wire burst_length_8 = ~mode_reg[2] & mode_reg[1] & mode_reg[0];
wire burst_length_f = mode_reg[2] & mode_reg[1] & mode_reg[0];
// cas latency decode
wire cas_latency_2 = ~mode_reg[6] & mode_reg[5] & ~mode_reg[4];
wire cas_latency_3 = ~mode_reg[6] & mode_reg[5] & mode_reg[4];
// write burst mode
wire write_burst_mode = mode_reg[9];
wire debug = 1'b1; // debug messages : 1 = on
wire dq_chk = sys_clk & data_in_enable; // check setup/hold time for dq
assign dq = dq_reg; // dq buffer
/* dump the content of the memory after some delay */
/*
integer dumpi;
initial begin
#206640
$display("contents of bank 0");
for(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
$display("%h: %h", dumpi, bank0[dumpi]);
end
$display("contents of bank 1");
for(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
$display("%h: %h", dumpi, bank1[dumpi]);
end
$display("contents of bank 2");
for(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
$display("%h: %h", dumpi, bank2[dumpi]);
end
$display("contents of bank 3");
for(dumpi=0;dumpi<20;dumpi=dumpi+1) begin
$display("%h: %h", dumpi, bank3[dumpi]);
end
end
*/
// commands operation
`define act 0
`define nop 1
`define read 2
`define write 3
`define prech 4
`define a_ref 5
`define bst 6
`define lmr 7
// timing parameters for -7e pc133 cl2
parameter tac = 5.4;
parameter thz = 5.4;
parameter toh = 3.0;
parameter tmrd = 2.0; // 2 clk cycles
parameter tras = 37.0;
parameter trc = 60.0;
parameter trcd = 15.0;
parameter trfc = 66.0;
parameter trp = 15.0;
parameter trrd = 14.0;
parameter twra = 7.0; // a2 version - auto precharge mode (1 clk + 7 ns)
parameter twrm = 14.0; // a2 version - manual precharge mode (14 ns)
// timing check variable
time mrd_chk;
time wr_chkm [0 : 3];
time rfc_chk, rrd_chk;
time rc_chk0, rc_chk1, rc_chk2, rc_chk3;
time ras_chk0, ras_chk1, ras_chk2, ras_chk3;
time rcd_chk0, rcd_chk1, rcd_chk2, rcd_chk3;
time rp_chk0, rp_chk1, rp_chk2, rp_chk3;
initial begin
dq_reg = {data_bits{1'bz}};
data_in_enable = 0; data_out_enable = 0;
act_b0 = 1; act_b1 = 1; act_b2 = 1; act_b3 = 1;
pc_b0 = 0; pc_b1 = 0; pc_b2 = 0; pc_b3 = 0;
wr_chkm[0] = 0; wr_chkm[1] = 0; wr_chkm[2] = 0; wr_chkm[3] = 0;
rw_interrupt_read[0] = 0; rw_interrupt_read[1] = 0; rw_interrupt_read[2] = 0; rw_interrupt_read[3] = 0;
rw_interrupt_write[0] = 0; rw_interrupt_write[1] = 0; rw_interrupt_write[2] = 0; rw_interrupt_write[3] = 0;
mrd_chk = 0; rfc_chk = 0; rrd_chk = 0;
ras_chk0 = 0; ras_chk1 = 0; ras_chk2 = 0; ras_chk3 = 0;
rcd_chk0 = 0; rcd_chk1 = 0; rcd_chk2 = 0; rcd_chk3 = 0;
rc_chk0 = 0; rc_chk1 = 0; rc_chk2 = 0; rc_chk3 = 0;
rp_chk0 = 0; rp_chk1 = 0; rp_chk2 = 0; rp_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// system clock generator
always begin
@ (posedge clk) begin
sys_clk = ckez;
ckez = cke;
end
@ (negedge clk) begin
sys_clk = 1'b0;
end
end
always @ (posedge sys_clk) begin
// internal commamd pipelined
command[0] = command[1];
command[1] = command[2];
command[2] = command[3];
command[3] = `nop;
col_addr[0] = col_addr[1];
col_addr[1] = col_addr[2];
col_addr[2] = col_addr[3];
col_addr[3] = {col_bits{1'b0}};
bank_addr[0] = bank_addr[1];
bank_addr[1] = bank_addr[2];
bank_addr[2] = bank_addr[3];
bank_addr[3] = 2'b0;
bank_precharge[0] = bank_precharge[1];
bank_precharge[1] = bank_precharge[2];
bank_precharge[2] = bank_precharge[3];
bank_precharge[3] = 2'b0;
a10_precharge[0] = a10_precharge[1];
a10_precharge[1] = a10_precharge[2];
a10_precharge[2] = a10_precharge[3];
a10_precharge[3] = 1'b0;
// dqm pipeline for read
dqm_reg0 = dqm_reg1;
dqm_reg1 = dqm;
// read or write with auto precharge counter
if (auto_precharge[0] === 1'b1) begin
count_precharge[0] = count_precharge[0] + 1;
end
if (auto_precharge[1] === 1'b1) begin
count_precharge[1] = count_precharge[1] + 1;
end
if (auto_precharge[2] === 1'b1) begin
count_precharge[2] = count_precharge[2] + 1;
end
if (auto_precharge[3] === 1'b1) begin
count_precharge[3] = count_precharge[3] + 1;
end
// read or write interrupt counter
if (rw_interrupt_write[0] === 1'b1) begin
rw_interrupt_counter[0] = rw_interrupt_counter[0] + 1;
end
if (rw_interrupt_write[1] === 1'b1) begin
rw_interrupt_counter[1] = rw_interrupt_counter[1] + 1;
end
if (rw_interrupt_write[2] === 1'b1) begin
rw_interrupt_counter[2] = rw_interrupt_counter[2] + 1;
end
if (rw_interrupt_write[3] === 1'b1) begin
rw_interrupt_counter[3] = rw_interrupt_counter[3] + 1;
end
// tmrd counter
mrd_chk = mrd_chk + 1;
// auto refresh
if (aref_enable === 1'b1) begin
if (debug) begin
$display ("%m : at time %t aref : auto refresh", $time);
end
// auto refresh to auto refresh
if ($time - rfc_chk < trfc) begin
$display ("%m : at time %t error: trfc violation during auto refresh", $time);
end
// precharge to auto refresh
if (($time - rp_chk0 < trp) || ($time - rp_chk1 < trp) ||
($time - rp_chk2 < trp) || ($time - rp_chk3 < trp)) begin
$display ("%m : at time %t error: trp violation during auto refresh", $time);
end
// precharge to refresh
if (pc_b0 === 1'b0 || pc_b1 === 1'b0 || pc_b2 === 1'b0 || pc_b3 === 1'b0) begin
$display ("%m : at time %t error: all banks must be precharge before auto refresh", $time);
end
// load mode register to auto refresh
if (mrd_chk < tmrd) begin
$display ("%m : at time %t error: tmrd violation during auto refresh", $time);
end
// record current trfc time
rfc_chk = $time;
end
// load mode register
if (mode_reg_enable === 1'b1) begin
// register mode
mode_reg = addr;
// decode cas latency, burst length, burst type, and write burst mode
if (debug) begin
$display ("%m : at time %t lmr : load mode register", $time);
// cas latency
case (addr[6 : 4])
3'b010 : $display ("%m : cas latency = 2");
3'b011 : $display ("%m : cas latency = 3");
default : $display ("%m : cas latency = reserved");
endcase
// burst length
case (addr[2 : 0])
3'b000 : $display ("%m : burst length = 1");
3'b001 : $display ("%m : burst length = 2");
3'b010 : $display ("%m : burst length = 4");
3'b011 : $display ("%m : burst length = 8");
3'b111 : $display ("%m : burst length = full");
default : $display ("%m : burst length = reserved");
endcase
// burst type
if (addr[3] === 1'b0) begin
$display ("%m : burst type = sequential");
end else if (addr[3] === 1'b1) begin
$display ("%m : burst type = interleaved");
end else begin
$display ("%m : burst type = reserved");
end
// write burst mode
if (addr[9] === 1'b0) begin
$display ("%m : write burst mode = programmed burst length");
end else if (addr[9] === 1'b1) begin
$display ("%m : write burst mode = single location access");
end else begin
$display ("%m : write burst mode = reserved");
end
end
// precharge to load mode register
if (pc_b0 === 1'b0 && pc_b1 === 1'b0 && pc_b2 === 1'b0 && pc_b3 === 1'b0) begin
$display ("%m : at time %t error: all banks must be precharge before load mode register", $time);
end
// precharge to load mode register
if (($time - rp_chk0 < trp) || ($time - rp_chk1 < trp) ||
($time - rp_chk2 < trp) || ($time - rp_chk3 < trp)) begin
$display ("%m : at time %t error: trp violation during load mode register", $time);
end
// auto refresh to load mode register
if ($time - rfc_chk < trfc) begin
$display ("%m : at time %t error: trfc violation during load mode register", $time);
end
// load mode register to load mode register
if (mrd_chk < tmrd) begin
$display ("%m : at time %t error: tmrd violation during load mode register", $time);
end
// reset mrd counter
mrd_chk = 0;
end
// active block (latch bank address and row address)
if (active_enable === 1'b1) begin
// activate an open bank can corrupt data
if ((ba === 2'b00 && act_b0 === 1'b1) || (ba === 2'b01 && act_b1 === 1'b1) ||
(ba === 2'b10 && act_b2 === 1'b1) || (ba === 2'b11 && act_b3 === 1'b1)) begin
$display ("%m : at time %t error: bank already activated -- data can be corrupted", $time);
end
// activate bank 0
if (ba === 2'b00 && pc_b0 === 1'b1) begin
// debug message
if (debug) begin
$display ("%m : at time %t act : bank = 0 row = %d", $time, addr);
end
// active to active command period
if ($time - rc_chk0 < trc) begin
$display ("%m : at time %t error: trc violation during activate bank 0", $time);
end
// precharge to activate bank 0
if ($time - rp_chk0 < trp) begin
$display ("%m : at time %t error: trp violation during activate bank 0", $time);
end
// record variables
act_b0 = 1'b1;
pc_b0 = 1'b0;
b0_row_addr = addr [addr_bits - 1 : 0];
ras_chk0 = $time;
rc_chk0 = $time;
rcd_chk0 = $time;
end
if (ba == 2'b01 && pc_b1 == 1'b1) begin
// debug message
if (debug) begin
$display ("%m : at time %t act : bank = 1 row = %d", $time, addr);
end
// active to active command period
if ($time - rc_chk1 < trc) begin
$display ("%m : at time %t error: trc violation during activate bank 1", $time);
end
// precharge to activate bank 1
if ($time - rp_chk1 < trp) begin
$display ("%m : at time %t error: trp violation during activate bank 1", $time);
end
// record variables
act_b1 = 1'b1;
pc_b1 = 1'b0;
b1_row_addr = addr [addr_bits - 1 : 0];
ras_chk1 = $time;
rc_chk1 = $time;
rcd_chk1 = $time;
end
if (ba == 2'b10 && pc_b2 == 1'b1) begin
// debug message
if (debug) begin
$display ("%m : at time %t act : bank = 2 row = %d", $time, addr);
end
// active to active command period
if ($time - rc_chk2 < trc) begin
$display ("%m : at time %t error: trc violation during activate bank 2", $time);
end
// precharge to activate bank 2
if ($time - rp_chk2 < trp) begin
$display ("%m : at time %t error: trp violation during activate bank 2", $time);
end
// record variables
act_b2 = 1'b1;
pc_b2 = 1'b0;
b2_row_addr = addr [addr_bits - 1 : 0];
ras_chk2 = $time;
rc_chk2 = $time;
rcd_chk2 = $time;
end
if (ba == 2'b11 && pc_b3 == 1'b1) begin
// debug message
if (debug) begin
$display ("%m : at time %t act : bank = 3 row = %d", $time, addr);
end
// active to active command period
if ($time - rc_chk3 < trc) begin
$display ("%m : at time %t error: trc violation during activate bank 3", $time);
end
// precharge to activate bank 3
if ($time - rp_chk3 < trp) begin
$display ("%m : at time %t error: trp violation during activate bank 3", $time);
end
// record variables
act_b3 = 1'b1;
pc_b3 = 1'b0;
b3_row_addr = addr [addr_bits - 1 : 0];
ras_chk3 = $time;
rc_chk3 = $time;
rcd_chk3 = $time;
end
// active bank a to active bank b
if ((prev_bank != ba) && ($time - rrd_chk < trrd)) begin
$display ("%m : at time %t error: trrd violation during activate bank = %d", $time, ba);
end
// auto refresh to activate
if ($time - rfc_chk < trfc) begin
$display ("%m : at time %t error: trfc violation during activate bank = %d", $time, ba);
end
// load mode register to active
if (mrd_chk < tmrd ) begin
$display ("%m : at time %t error: tmrd violation during activate bank = %d", $time, ba);
end
// record variables for checking violation
rrd_chk = $time;
prev_bank = ba;
end
// precharge block
if (prech_enable == 1'b1) begin
// load mode register to precharge
if ($time - mrd_chk < tmrd) begin
$display ("%m : at time %t error: tmrd violaiton during precharge", $time);
end
// precharge bank 0
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b00)) && act_b0 === 1'b1) begin
act_b0 = 1'b0;
pc_b0 = 1'b1;
rp_chk0 = $time;
// activate to precharge
if ($time - ras_chk0 < tras) begin
$display ("%m : at time %t error: tras violation during precharge", $time);
end
// twr violation check for write
if ($time - wr_chkm[0] < twrm) begin
$display ("%m : at time %t error: twr violation during precharge", $time);
end
end
// precharge bank 1
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b01)) && act_b1 === 1'b1) begin
act_b1 = 1'b0;
pc_b1 = 1'b1;
rp_chk1 = $time;
// activate to precharge
if ($time - ras_chk1 < tras) begin
$display ("%m : at time %t error: tras violation during precharge", $time);
end
// twr violation check for write
if ($time - wr_chkm[1] < twrm) begin
$display ("%m : at time %t error: twr violation during precharge", $time);
end
end
// precharge bank 2
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b10)) && act_b2 === 1'b1) begin
act_b2 = 1'b0;
pc_b2 = 1'b1;
rp_chk2 = $time;
// activate to precharge
if ($time - ras_chk2 < tras) begin
$display ("%m : at time %t error: tras violation during precharge", $time);
end
// twr violation check for write
if ($time - wr_chkm[2] < twrm) begin
$display ("%m : at time %t error: twr violation during precharge", $time);
end
end
// precharge bank 3
if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b11)) && act_b3 === 1'b1) begin
act_b3 = 1'b0;
pc_b3 = 1'b1;
rp_chk3 = $time;
// activate to precharge
if ($time - ras_chk3 < tras) begin
$display ("%m : at time %t error: tras violation during precharge", $time);
end
// twr violation check for write
if ($time - wr_chkm[3] < twrm) begin
$display ("%m : at time %t error: twr violation during precharge", $time);
end
end
// terminate a write immediately (if same bank or all banks)
if (data_in_enable === 1'b1 && (bank === ba || addr[10] === 1'b1)) begin
data_in_enable = 1'b0;
end
// precharge command pipeline for read
if (cas_latency_3 === 1'b1) begin
command[2] = `prech;
bank_precharge[2] = ba;
a10_precharge[2] = addr[10];
end else if (cas_latency_2 === 1'b1) begin
command[1] = `prech;
bank_precharge[1] = ba;
a10_precharge[1] = addr[10];
end
end
// burst terminate
if (burst_term === 1'b1) begin
// terminate a write immediately
if (data_in_enable == 1'b1) begin
data_in_enable = 1'b0;
end
// terminate a read depend on cas latency
if (cas_latency_3 === 1'b1) begin
command[2] = `bst;
end else if (cas_latency_2 == 1'b1) begin
command[1] = `bst;
end
// display debug message
if (debug) begin
$display ("%m : at time %t bst : burst terminate",$time);
end
end
// read, write, column latch
if (read_enable === 1'b1) begin
// check to see if bank is open (act)
if ((ba == 2'b00 && pc_b0 == 1'b1) || (ba == 2'b01 && pc_b1 == 1'b1) ||
(ba == 2'b10 && pc_b2 == 1'b1) || (ba == 2'b11 && pc_b3 == 1'b1)) begin
$display("%m : at time %t error: bank is not activated for read", $time);
end
// activate to read or write
if ((ba == 2'b00) && ($time - rcd_chk0 < trcd) ||
(ba == 2'b01) && ($time - rcd_chk1 < trcd) ||
(ba == 2'b10) && ($time - rcd_chk2 < trcd) ||
(ba == 2'b11) && ($time - rcd_chk3 < trcd)) begin
$display("%m : at time %t error: trcd violation during read", $time);
end
// cas latency pipeline
if (cas_latency_3 == 1'b1) begin
command[2] = `read;
col_addr[2] = addr;
bank_addr[2] = ba;
end else if (cas_latency_2 == 1'b1) begin
command[1] = `read;
col_addr[1] = addr;
bank_addr[1] = ba;
end
// read interrupt write (terminate write immediately)
if (data_in_enable == 1'b1) begin
data_in_enable = 1'b0;
// interrupting a write with autoprecharge
if (auto_precharge[rw_interrupt_bank] == 1'b1 && write_precharge[rw_interrupt_bank] == 1'b1) begin
rw_interrupt_write[rw_interrupt_bank] = 1'b1;
rw_interrupt_counter[rw_interrupt_bank] = 0;
// display debug message
if (debug) begin
$display ("%m : at time %t note : read interrupt write with autoprecharge", $time);
end
end
end
// write with auto precharge
if (addr[10] == 1'b1) begin
auto_precharge[ba] = 1'b1;
count_precharge[ba] = 0;
rw_interrupt_bank = ba;
read_precharge[ba] = 1'b1;
end
end
// write command
if (write_enable == 1'b1) begin
// activate to write
if ((ba == 2'b00 && pc_b0 == 1'b1) || (ba == 2'b01 && pc_b1 == 1'b1) ||
(ba == 2'b10 && pc_b2 == 1'b1) || (ba == 2'b11 && pc_b3 == 1'b1)) begin
$display("%m : at time %t error: bank is not activated for write", $time);
end
// activate to read or write
if ((ba == 2'b00) && ($time - rcd_chk0 < trcd) ||
(ba == 2'b01) && ($time - rcd_chk1 < trcd) ||
(ba == 2'b10) && ($time - rcd_chk2 < trcd) ||
(ba == 2'b11) && ($time - rcd_chk3 < trcd)) begin
$display("%m : at time %t error: trcd violation during read", $time);
end
// latch write command, bank, and column
command[0] = `write;
col_addr[0] = addr;
bank_addr[0] = ba;
// write interrupt write (terminate write immediately)
if (data_in_enable == 1'b1) begin
data_in_enable = 1'b0;
// interrupting a write with autoprecharge
if (auto_precharge[rw_interrupt_bank] == 1'b1 && write_precharge[rw_interrupt_bank] == 1'b1) begin
rw_interrupt_write[rw_interrupt_bank] = 1'b1;
// display debug message
if (debug) begin
$display ("%m : at time %t note : read bank %d interrupt write bank %d with autoprecharge", $time, ba, rw_interrupt_bank);
end
end
end
// write interrupt read (terminate read immediately)
if (data_out_enable == 1'b1) begin
data_out_enable = 1'b0;
// interrupting a read with autoprecharge
if (auto_precharge[rw_interrupt_bank] == 1'b1 && read_precharge[rw_interrupt_bank] == 1'b1) begin
rw_interrupt_read[rw_interrupt_bank] = 1'b1;
// display debug message
if (debug) begin
$display ("%m : at time %t note : write bank %d interrupt read bank %d with autoprecharge", $time, ba, rw_interrupt_bank);
end
end
end
// write with auto precharge
if (addr[10] == 1'b1) begin
auto_precharge[ba] = 1'b1;
count_precharge[ba] = 0;
rw_interrupt_bank = ba;
write_precharge[ba] = 1'b1;
end
end
/*
write with auto precharge calculation
the device start internal precharge when:
1. meet minimum tras requirement
and 2. twr cycle(s) after last valid data
or 3. interrupt by a read or write (with or without auto precharge)
note: model is starting the internal precharge 1 cycle after they meet all the
requirement but trp will be compensate for the time after the 1 cycle.
*/
if ((auto_precharge[0] == 1'b1) && (write_precharge[0] == 1'b1)) begin
if ((($time - ras_chk0 >= tras) && // case 1
(((burst_length_1 == 1'b1 || write_burst_mode == 1'b1) && count_precharge [0] >= 1) || // case 2
(burst_length_2 == 1'b1 && count_precharge [0] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge [0] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge [0] >= 8))) ||
(rw_interrupt_write[0] == 1'b1 && rw_interrupt_counter[0] >= 1)) begin // case 3
auto_precharge[0] = 1'b0;
write_precharge[0] = 1'b0;
rw_interrupt_write[0] = 1'b0;
pc_b0 = 1'b1;
act_b0 = 1'b0;
rp_chk0 = $time + twra;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 0", $time);
end
end
end
if ((auto_precharge[1] == 1'b1) && (write_precharge[1] == 1'b1)) begin
if ((($time - ras_chk1 >= tras) && // case 1
(((burst_length_1 == 1'b1 || write_burst_mode == 1'b1) && count_precharge [1] >= 1) || // case 2
(burst_length_2 == 1'b1 && count_precharge [1] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge [1] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge [1] >= 8))) ||
(rw_interrupt_write[1] == 1'b1 && rw_interrupt_counter[1] >= 1)) begin // case 3
auto_precharge[1] = 1'b0;
write_precharge[1] = 1'b0;
rw_interrupt_write[1] = 1'b0;
pc_b1 = 1'b1;
act_b1 = 1'b0;
rp_chk1 = $time + twra;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 1", $time);
end
end
end
if ((auto_precharge[2] == 1'b1) && (write_precharge[2] == 1'b1)) begin
if ((($time - ras_chk2 >= tras) && // case 1
(((burst_length_1 == 1'b1 || write_burst_mode == 1'b1) && count_precharge [2] >= 1) || // case 2
(burst_length_2 == 1'b1 && count_precharge [2] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge [2] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge [2] >= 8))) ||
(rw_interrupt_write[2] == 1'b1 && rw_interrupt_counter[2] >= 1)) begin // case 3
auto_precharge[2] = 1'b0;
write_precharge[2] = 1'b0;
rw_interrupt_write[2] = 1'b0;
pc_b2 = 1'b1;
act_b2 = 1'b0;
rp_chk2 = $time + twra;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 2", $time);
end
end
end
if ((auto_precharge[3] == 1'b1) && (write_precharge[3] == 1'b1)) begin
if ((($time - ras_chk3 >= tras) && // case 1
(((burst_length_1 == 1'b1 || write_burst_mode == 1'b1) && count_precharge [3] >= 1) || // case 2
(burst_length_2 == 1'b1 && count_precharge [3] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge [3] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge [3] >= 8))) ||
(rw_interrupt_write[3] == 1'b1 && rw_interrupt_counter[3] >= 1)) begin // case 3
auto_precharge[3] = 1'b0;
write_precharge[3] = 1'b0;
rw_interrupt_write[3] = 1'b0;
pc_b3 = 1'b1;
act_b3 = 1'b0;
rp_chk3 = $time + twra;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 3", $time);
end
end
end
// read with auto precharge calculation
// the device start internal precharge:
// 1. meet minimum tras requirement
// and 2. cas latency - 1 cycles before last burst
// or 3. interrupt by a read or write (with or without autoprecharge)
if ((auto_precharge[0] == 1'b1) && (read_precharge[0] == 1'b1)) begin
if ((($time - ras_chk0 >= tras) && // case 1
((burst_length_1 == 1'b1 && count_precharge[0] >= 1) || // case 2
(burst_length_2 == 1'b1 && count_precharge[0] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge[0] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge[0] >= 8))) ||
(rw_interrupt_read[0] == 1'b1)) begin // case 3
pc_b0 = 1'b1;
act_b0 = 1'b0;
rp_chk0 = $time;
auto_precharge[0] = 1'b0;
read_precharge[0] = 1'b0;
rw_interrupt_read[0] = 1'b0;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 0", $time);
end
end
end
if ((auto_precharge[1] == 1'b1) && (read_precharge[1] == 1'b1)) begin
if ((($time - ras_chk1 >= tras) &&
((burst_length_1 == 1'b1 && count_precharge[1] >= 1) ||
(burst_length_2 == 1'b1 && count_precharge[1] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge[1] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge[1] >= 8))) ||
(rw_interrupt_read[1] == 1'b1)) begin
pc_b1 = 1'b1;
act_b1 = 1'b0;
rp_chk1 = $time;
auto_precharge[1] = 1'b0;
read_precharge[1] = 1'b0;
rw_interrupt_read[1] = 1'b0;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 1", $time);
end
end
end
if ((auto_precharge[2] == 1'b1) && (read_precharge[2] == 1'b1)) begin
if ((($time - ras_chk2 >= tras) &&
((burst_length_1 == 1'b1 && count_precharge[2] >= 1) ||
(burst_length_2 == 1'b1 && count_precharge[2] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge[2] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge[2] >= 8))) ||
(rw_interrupt_read[2] == 1'b1)) begin
pc_b2 = 1'b1;
act_b2 = 1'b0;
rp_chk2 = $time;
auto_precharge[2] = 1'b0;
read_precharge[2] = 1'b0;
rw_interrupt_read[2] = 1'b0;
if (debug) begin
$display ("%m : at time %t note : start internal auto precharge for bank 2", $time);
end
end
end
if ((auto_precharge[3] == 1'b1) && (read_precharge[3] == 1'b1)) begin
if ((($time - ras_chk3 >= tras) &&
((burst_length_1 == 1'b1 && count_precharge[3] >= 1) ||
(burst_length_2 == 1'b1 && count_precharge[3] >= 2) ||
(burst_length_4 == 1'b1 && count_precharge[3] >= 4) ||
(burst_length_8 == 1'b1 && count_precharge[3] >= 8))) ||
(rw_interrupt_read[3] == 1'b1)) begin
pc_b3 = 1'b1;
act_b3 = 1'b0;
rp_chk3 = $time;
auto_precharge[3] = 1'b0;
read_precharge[3] = 1'b0;
rw_interrupt_read[3] = 1'b0;
if (debug) begin
$display("%m : at time %t note : start internal auto precharge for bank 3", $time);
end
end
end
// internal precharge or bst
if (command[0] == `prech) begin // precharge terminate a read with same bank or all banks
if (bank_precharge[0] == bank || a10_precharge[0] == 1'b1) begin
if (data_out_enable == 1'b1) begin
data_out_enable = 1'b0;
end
end
end else if (command[0] == `bst) begin // bst terminate a read to current bank
if (data_out_enable == 1'b1) begin
data_out_enable = 1'b0;
end
end
if (data_out_enable == 1'b0) begin
dq_reg <= #toh {data_bits{1'bz}};
end
// detect read or write command
if (command[0] == `read) begin
bank = bank_addr[0];
col = col_addr[0];
col_brst = col_addr[0];
case (bank_addr[0])
2'b00 : row = b0_row_addr;
2'b01 : row = b1_row_addr;
2'b10 : row = b2_row_addr;
2'b11 : row = b3_row_addr;
endcase
burst_counter = 0;
data_in_enable = 1'b0;
data_out_enable = 1'b1;
end else if (command[0] == `write) begin
bank = bank_addr[0];
col = col_addr[0];
col_brst = col_addr[0];
case (bank_addr[0])
2'b00 : row = b0_row_addr;
2'b01 : row = b1_row_addr;
2'b10 : row = b2_row_addr;
2'b11 : row = b3_row_addr;
endcase
burst_counter = 0;
data_in_enable = 1'b1;
data_out_enable = 1'b0;
end
// dq buffer (driver/receiver)
if (data_in_enable == 1'b1) begin // writing data to memory
// array buffer
case (bank)
2'b00 : dq_dqm = bank0 [{row, col}];
2'b01 : dq_dqm = bank1 [{row, col}];
2'b10 : dq_dqm = bank2 [{row, col}];
2'b11 : dq_dqm = bank3 [{row, col}];
endcase
// dqm operation
if (dqm[0] == 1'b0) begin
dq_dqm [ 7 : 0] = dq [ 7 : 0];
end
if (dqm[1] == 1'b0) begin
dq_dqm [15 : 8] = dq [15 : 8];
end
// write to memory
case (bank)
2'b00 : bank0 [{row, col}] = dq_dqm;
2'b01 : bank1 [{row, col}] = dq_dqm;
2'b10 : bank2 [{row, col}] = dq_dqm;
2'b11 : bank3 [{row, col}] = dq_dqm;
endcase
// display debug message
if (dqm !== 2'b11) begin
// record twr for manual precharge
wr_chkm [bank] = $time;
if (debug) begin
$display("%m : at time %t write: bank = %d row = %d, col = %d, data = %d", $time, bank, row, col, dq_dqm);
end
end else begin
if (debug) begin
$display("%m : at time %t write: bank = %d row = %d, col = %d, data = hi-z due to dqm", $time, bank, row, col);
end
end
// advance burst counter subroutine
#thz burst_decode;
end else if (data_out_enable == 1'b1) begin // reading data from memory
// array buffer
case (bank)
2'b00 : dq_dqm = bank0[{row, col}];
2'b01 : dq_dqm = bank1[{row, col}];
2'b10 : dq_dqm = bank2[{row, col}];
2'b11 : dq_dqm = bank3[{row, col}];
endcase
// dqm operation
if (dqm_reg0 [0] == 1'b1) begin
dq_dqm [ 7 : 0] = 8'bz;
end
if (dqm_reg0 [1] == 1'b1) begin
dq_dqm [15 : 8] = 8'bz;
end
// display debug message
if (dqm_reg0 !== 2'b11) begin
dq_reg = #tac dq_dqm; //xxx
if (debug) begin
$display("%m : at time %t read : bank = %d row = %d, col = %d, data = %d", $time, bank, row, col, dq_reg);
end
end else begin
dq_reg = #thz {data_bits{1'bz}};
if (debug) begin
$display("%m : at time %t read : bank = %d row = %d, col = %d, data = hi-z due to dqm", $time, bank, row, col);
end
end
// advance burst counter subroutine
burst_decode;
end
end
// burst counter decode
task burst_decode;
begin
// advance burst counter
burst_counter = burst_counter + 1;
// burst type
if (mode_reg[3] == 1'b0) begin // sequential burst
col_temp = col + 1;
end else if (mode_reg[3] == 1'b1) begin // interleaved burst
col_temp[2] = burst_counter[2] ^ col_brst[2];
col_temp[1] = burst_counter[1] ^ col_brst[1];
col_temp[0] = burst_counter[0] ^ col_brst[0];
end
// burst length
if (burst_length_2) begin // burst length = 2
col [0] = col_temp [0];
end else if (burst_length_4) begin // burst length = 4
col [1 : 0] = col_temp [1 : 0];
end else if (burst_length_8) begin // burst length = 8
col [2 : 0] = col_temp [2 : 0];
end else begin // burst length = full
col = col_temp;
end
// burst read single write
if (write_burst_mode == 1'b1) begin
data_in_enable = 1'b0;
end
// data counter
if (burst_length_1 == 1'b1) begin
if (burst_counter >= 1) begin
data_in_enable = 1'b0;
data_out_enable = 1'b0;
end
end else if (burst_length_2 == 1'b1) begin
if (burst_counter >= 2) begin
data_in_enable = 1'b0;
data_out_enable = 1'b0;
end
end else if (burst_length_4 == 1'b1) begin
if (burst_counter >= 4) begin
data_in_enable = 1'b0;
data_out_enable = 1'b0;
end
end else if (burst_length_8 == 1'b1) begin
if (burst_counter >= 8) begin
data_in_enable = 1'b0;
data_out_enable = 1'b0;
end
end
end
endtask
// timing parameters for -7e (133 mhz @ cl2)
specify
specparam
tah = 0.8, // addr, ba hold time
tas = 1.5, // addr, ba setup time
tch = 2.5, // clock high-level width
tcl = 2.5, // clock low-level width
tck = 7.0, // clock cycle time
tdh = 0.8, // data-in hold time
tds = 1.5, // data-in setup time
tckh = 0.8, // cke hold time
tcks = 1.5, // cke setup time
tcmh = 0.8, // cs#, ras#, cas#, we#, dqm# hold time
tcms = 1.5; // cs#, ras#, cas#, we#, dqm# setup time
$width (posedge clk, tch);
$width (negedge clk, tcl);
$period (negedge clk, tck);
$period (posedge clk, tck);
$setuphold(posedge clk, cke, tcks, tckh);
$setuphold(posedge clk, cs_n, tcms, tcmh);
$setuphold(posedge clk, cas_n, tcms, tcmh);
$setuphold(posedge clk, ras_n, tcms, tcmh);
$setuphold(posedge clk, we_n, tcms, tcmh);
$setuphold(posedge clk, addr, tas, tah);
$setuphold(posedge clk, ba, tas, tah);
$setuphold(posedge clk, dqm, tcms, tcmh);
$setuphold(posedge dq_chk, dq, tds, tdh);
endspecify
initial begin
$dumpfile(`dump_file_name);
$dumpvars(1);
end
endmodule
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