code
string |
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// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
// (c) 2001-2015 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
module altera_avalon_mailbox #(
parameter dwidth = 32,
parameter awidth = 2
)(
input clk,
input rst_n,
output irq_msg,
output irq_space,
input [awidth-1:0] avmm_snd_address,
input [dwidth-1:0] avmm_snd_writedata,
input avmm_snd_write,
input avmm_snd_read,
output [dwidth-1:0] avmm_snd_readdata,
output avmm_snd_waitrequest,
input [awidth-1:0] avmm_rcv_address,
input [dwidth-1:0] avmm_rcv_writedata,
input avmm_rcv_write,
input avmm_rcv_read,
output [dwidth-1:0] avmm_rcv_readdata
);
// status register bit definition
localparam full_bit = 1;
localparam msg_pending_bit = 0;
localparam snd_int_bit = 1;
localparam rcv_int_bit = 0;
// wires & registers declaration
reg [dwidth-1:0] command_reg;
reg [dwidth-1:0] pointer_reg;
reg [dwidth-1:0] status_reg;
reg [dwidth-1:0] mask_reg;
wire [dwidth-1:0] command_comb;
wire [dwidth-1:0] pointer_comb;
wire [dwidth-1:0] status_comb;
wire [dwidth-1:0] mask_comb;
wire [dwidth-1:0] snd_act_readdata;
wire [dwidth-1:0] snd_int_readdata;
wire [dwidth-1:0] snd_cmd_reg_rddata;
wire [dwidth-1:0] snd_ptr_reg_rddata;
wire [dwidth-1:0] snd_sts_reg_rddata;
wire [dwidth-1:0] snd_msk_reg_rddata;
wire [dwidth-1:0] rcv_act_readdata;
wire [dwidth-1:0] rcv_int_readdata;
wire [dwidth-1:0] rcv_cmd_reg_rddata;
wire [dwidth-1:0] rcv_ptr_reg_rddata;
wire [dwidth-1:0] rcv_sts_reg_rddata;
wire [dwidth-1:0] rcv_msk_reg_rddata;
reg [dwidth-1:0] readdata_with_waitstate;
wire cmd_reg_snd_access;
wire ptr_reg_snd_access;
wire sts_reg_snd_access;
wire msk_reg_snd_access;
wire cmd_reg_rcv_access;
wire ptr_reg_rcv_access;
wire sts_reg_rcv_access;
wire msk_reg_rcv_access;
wire snd_wr_valid;
wire snd_rd_valid;
wire rcv_rd_valid;
wire rcv_wr_valid;
wire full;
wire pending;
wire snd_mask, rcv_mask;
reg rst_for_bp;
// decoding of address for register target
assign cmd_reg_snd_access = (avmm_snd_address == 2'b00);
assign ptr_reg_snd_access = (avmm_snd_address == 2'b01);
assign sts_reg_snd_access = (avmm_snd_address == 2'b10);
assign msk_reg_snd_access = (avmm_snd_address == 2'b11);
assign cmd_reg_rcv_access = (avmm_rcv_address == 2'b00);
assign ptr_reg_rcv_access = (avmm_rcv_address == 2'b01);
assign sts_reg_rcv_access = (avmm_rcv_address == 2'b10);
assign msk_reg_rcv_access = (avmm_rcv_address == 2'b11);
// registers assignment
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
command_reg <= {(dwidth){1'b0}};
pointer_reg <= {(dwidth){1'b0}};
status_reg <= {(dwidth){1'b0}};
mask_reg <= {(dwidth){1'b0}};
end
else begin
command_reg <= command_comb;
pointer_reg <= pointer_comb;
status_reg <= status_comb;
mask_reg <= mask_comb;
end
end
assign command_comb = (snd_wr_valid & cmd_reg_snd_access) ?
avmm_snd_writedata :
command_reg;
assign pointer_comb = (snd_wr_valid & ptr_reg_snd_access) ?
avmm_snd_writedata :
pointer_reg;
assign mask_comb = {{30{1'b0}},snd_mask, rcv_mask};
assign snd_mask = (snd_wr_valid & msk_reg_snd_access) ?
avmm_snd_writedata[snd_int_bit]:
mask_reg[snd_int_bit];
assign rcv_mask = (rcv_wr_valid & msk_reg_rcv_access) ?
avmm_rcv_writedata[rcv_int_bit]:
mask_reg[rcv_int_bit];
assign status_comb = {30'b0, full, pending};
assign full = status_reg[full_bit] ? !(cmd_reg_rcv_access & rcv_rd_valid): /*(read from rcv will set 0)*/
(cmd_reg_snd_access & snd_wr_valid); /*(write of cmd_reg will set 1)*/
assign pending = status_reg[msg_pending_bit] ? !(cmd_reg_rcv_access & rcv_rd_valid): /*(read from rcv will set 0)*/
(cmd_reg_snd_access & snd_wr_valid); /*(write of cmd_reg will set 1)*/
// for time being, with 1 message mailbox availability, full and pending logic is the same.
// however, if a message queue >1 is implemented, full and pending condition will be different.
// the pending logic will then honor the empty status of the queue.
// avalon mm interface handling
// avalon mm slave interfaces of the sender has backpressure flow control with waitrequest signal
// avalon mm slave interfaces of the receiver has readwaittime = 1, and has write capability only to the mask_reg
// assert waitreq during reset to avoid lockup
assign snd_wr_valid = avmm_snd_write & !avmm_snd_waitrequest;
assign snd_rd_valid = avmm_snd_read & !avmm_snd_waitrequest;
assign avmm_snd_waitrequest = (avmm_snd_write & cmd_reg_snd_access & status_reg[full_bit]) |
(avmm_snd_write & ptr_reg_snd_access & status_reg[full_bit]) |
// add condition for read transaction if location being read is empty, no need for now, but maybe for future
rst_for_bp;
assign avmm_snd_readdata = snd_act_readdata;
assign snd_act_readdata = snd_rd_valid ? snd_int_readdata : {(dwidth){1'b0}};
assign snd_int_readdata = snd_cmd_reg_rddata |
snd_ptr_reg_rddata |
snd_sts_reg_rddata |
snd_msk_reg_rddata ;
assign snd_cmd_reg_rddata = command_reg & {(dwidth){cmd_reg_snd_access}};
assign snd_ptr_reg_rddata = pointer_reg & {(dwidth){ptr_reg_snd_access}};
assign snd_sts_reg_rddata = status_reg & {(dwidth){sts_reg_snd_access}};
assign snd_msk_reg_rddata = mask_reg & {(dwidth){msk_reg_snd_access}};
assign rcv_wr_valid = avmm_rcv_write;
assign rcv_rd_valid = avmm_rcv_read;
assign avmm_rcv_readdata = readdata_with_waitstate;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_for_bp <= 1'b1;
else rst_for_bp <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) readdata_with_waitstate <= {(dwidth){1'b0}};
else readdata_with_waitstate <= rcv_act_readdata;
end
assign rcv_act_readdata = rcv_rd_valid ? rcv_int_readdata : {(dwidth){1'b0}};
assign rcv_int_readdata = rcv_cmd_reg_rddata |
rcv_ptr_reg_rddata |
rcv_sts_reg_rddata |
rcv_msk_reg_rddata ;
assign rcv_cmd_reg_rddata = command_reg & {(dwidth){cmd_reg_rcv_access}};
assign rcv_ptr_reg_rddata = pointer_reg & {(dwidth){ptr_reg_rcv_access}};
assign rcv_sts_reg_rddata = status_reg & {(dwidth){sts_reg_rcv_access}};
assign rcv_msk_reg_rddata = mask_reg & {(dwidth){msk_reg_rcv_access}};
assign irq_space = ~status_reg[full_bit] & mask_reg[snd_int_bit];
assign irq_msg = status_reg[msg_pending_bit] & mask_reg[rcv_int_bit];
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
module UBCSe_11_0_10_1 (S, X, Y);
output [12:0] S;
input [11:0] X;
input [10:1] Y;
wire [11:1] Z;
UBExtender_10_1_1000 U0 (Z[11:1], Y[10:1]);
UBPureCSe_11_1 U1 (S[12:1], X[11:1], Z[11:1]);
UB1DCON_0 U2 (S[0], X[0]);
endmodule
|
module hi_us_3( // @[tage.scala:89:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:89:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:89:27]
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Write Data FIFO
//
// File : alt_ddrx_wdata_fifo.v
//
// Abstract : Store write data
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_wdata_fifo
#(parameter WDATA_BEATS_WIDTH = 9,
LOCAL_DATA_WIDTH = 32,
LOCAL_SIZE_WIDTH = 6,
DWIDTH_RATIO = 2,
FAMILY = "Stratix"
)(
// input
ctl_clk,
ctl_reset_n,
write_req_to_wfifo,
wdata_to_wfifo,
be_to_wfifo,
wdata_fifo_read,
//output
wdata_fifo_full,
wdata_fifo_wdata,
wdata_fifo_be,
beats_in_wfifo
);
localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8;
localparam LOCAL_WFIFO_Q_WIDTH = LOCAL_DATA_WIDTH + LOCAL_BE_WIDTH;
input ctl_clk; // controller clock
input ctl_reset_n; // controller reset_n, synchronous to ctl_clk
input write_req_to_wfifo;
input wdata_fifo_read;
input [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
input [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
output [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
output [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
output wdata_fifo_full;
output [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
wire ctl_clk;
wire ctl_reset_n;
wire reset;
wire write_req_to_wfifo;
wire wdata_fifo_read;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
wire [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_data;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_q;
wire wdata_fifo_full;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
wire [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
reg [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
assign wfifo_data = {be_to_wfifo,wdata_to_wfifo};
assign wdata_fifo_be = wfifo_q[LOCAL_WFIFO_Q_WIDTH-1 : LOCAL_DATA_WIDTH];
assign wdata_fifo_wdata = wfifo_q[LOCAL_DATA_WIDTH-1 : 0];
assign reset = !ctl_reset_n; // scfifo has an active high async reset
//We fix the fifo depth to 256 in order to match the depth of the M9k memories that has the maximum data width (256 depth x 36 width),
//by doing this, we can minimize the usage of M9k.
//Currently, we need at lease 18 M9k (256 x 36)
//Calculation : Maximum data width that we support, 72 (with ecc) * 8 (quarter rate) = 576, byteen bit = 576 / 8 = 72, LOCAL_WFIFO_Q_WIDTH = 576 + 72 = 648
//Number of M9k we need = 648 / 36 = 18.
scfifo #(
.intended_device_family (FAMILY),
.lpm_width (LOCAL_WFIFO_Q_WIDTH), // one BE per byte, not per DQS
.lpm_numwords (256),
.lpm_widthu (log2 (256)),
.almost_full_value (256-16), // a bit of slack to avoid overflowing
.lpm_type ("scfifo"),
.lpm_showahead ("OFF"), // Always OFF at the moment
.overflow_checking ("OFF"),
.underflow_checking ("OFF"),
.use_eab ("ON"),
.add_ram_output_register ("ON") // Always ON at the moment
) wdata_fifo (
.rdreq (wdata_fifo_read),
.aclr (reset),
.clock (ctl_clk),
.wrreq (write_req_to_wfifo),
.data (wfifo_data),
.full (),
.q (wfifo_q),
.sclr (1'b0),
.usedw (),
.empty (),
.almost_full (wdata_fifo_full),
.almost_empty ()
);
// Tell the state machine how many data entry is in the write data fifo
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (~ctl_reset_n) begin
beats_in_wfifo <= 0;
end
else if(write_req_to_wfifo) begin
if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo;
end
else begin
beats_in_wfifo <= beats_in_wfifo + 1'b1;
end
end
else if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo - 1'b1;
end
end
function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
ctl_list_width = 3, // number of dram commands that can be tracked at a time
ctl_list_depth = 8,
ctl_list_init_value_type = "incr", // incr, zero
ctl_list_init_valid = "valid" // valid, invalid
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [ctl_list_width-1:0] list_get_entry_id;
output [ctl_list_depth-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [ctl_list_width-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [ctl_list_width-1:0] list_get_entry_id;
reg [ctl_list_depth-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [ctl_list_width-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [ctl_list_width-1:0] list [ctl_list_depth-1:0];
reg list_v [ctl_list_depth-1:0];
reg [ctl_list_depth-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[ctl_list_depth-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < ctl_list_depth; i = i + 1'b1)
begin
// initialize every entry
if (ctl_list_init_value_type == "incr")
begin
list [i] <= i;
end
else
begin
list [i] <= {ctl_list_width{1'b0}};
end
if (ctl_list_init_valid == "valid")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {ctl_list_depth{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [ctl_list_depth-1] <= 0;
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// $file: //acds/rel/16.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $revision: #1 $
// $date: 2016/08/07 $
// $author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter symbols_per_beat = 1;
parameter bits_per_symbol = 8;
parameter pipeline_ready = 1;
localparam data_width = symbols_per_beat * bits_per_symbol;
input clk;
input reset;
output in_ready;
input in_valid;
input [data_width-1:0] in_data;
input out_ready;
output out_valid;
output [data_width-1:0] out_data;
reg full0;
reg full1;
reg [data_width-1:0] data0;
reg [data_width-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (pipeline_ready == 1)
begin : registered_ready_pline
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {data_width{1'b0}};
data1 <= {data_width{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : unregistered_ready_pline
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** reset logic for application layer (app_rstn) triggered by hip reset behavior +
//*/
module altpcierd_hip_rs # (
parameter hiprst_use_ltssm_hotreset = 1,
parameter hiprst_use_ltssm_disable = 1,
parameter hiprst_use_l2 = 1,
parameter hiprst_use_dlup_exit = 1
) (
input dlup_exit,
input hotrst_exit,
input l2_exit,
input [ 4: 0] ltssm,
input npor,
input pld_clk,
input test_sim,
output reg app_rstn
);
localparam [4:0] ltssm_pol = 5'b00010;
localparam [4:0] ltssm_cpl = 5'b00011;
localparam [4:0] ltssm_det = 5'b00000;
localparam [4:0] ltssm_rcv = 5'b01100;
localparam [4:0] ltssm_dis = 5'b10000;
localparam [23:0] rcv_timeout = 24'd6000000;
localparam [10:0] rstn_cnt_max = 11'h400;
localparam [10:0] rstn_cnt_maxsim = 11'h20;
//synthesis translate_off
localparam altpcie_sv_hip_ast_hwtcl_sim_only = 1;
//synthesis translate_on
//synthesis read_comments_as_hdl on
//localparam altpcie_sv_hip_ast_hwtcl_sim_only = 0;
//synthesis read_comments_as_hdl off
reg [1:0] npor_syncr ;
reg npor_sync_pld_clk;
reg app_rstn0;
reg crst0;
reg [ 4: 0] ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
reg [ 10: 0] rsnt_cntn;
reg [23:0] recovery_cnt;
reg recovery_rst;
reg ltssm_disable;
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
dlup_exit_r <= 1'b1;
hotrst_exit_r <= 1'b1;
l2_exit_r <= 1'b1;
exits_r <= 1'b0;
ltssm_r <= 5'h0;
app_rstn <= 1'b0;
ltssm_disable <= 1'b0;
end
else begin
ltssm_r <= ltssm;
dlup_exit_r <= (hiprst_use_dlup_exit==0) ?1'b1:dlup_exit;
hotrst_exit_r <= (hiprst_use_ltssm_hotreset==0)?1'b1:hotrst_exit;
l2_exit_r <= (hiprst_use_l2==0) ?1'b1:l2_exit;
ltssm_disable <= (hiprst_use_ltssm_disable==0) ?1'b0:(ltssm_r == ltssm_dis)?1'b1:1'b0;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (ltssm_disable == 1'b1)| (recovery_rst == 1'b1);
app_rstn <= app_rstn0;
end
end
//reset synchronizer npor --> npor_sync_pld_clk
always @(posedge pld_clk or negedge npor) begin
if (npor == 1'b0) begin
npor_syncr <= 2'b00;
npor_sync_pld_clk <= 1'b0;
end
else begin
npor_syncr[0] <= 1'b1;
npor_syncr[1] <= npor_syncr[0];
npor_sync_pld_clk <= npor_syncr[1];
end
end
//delay hip reset upon npor
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
app_rstn0 <= 1'b0;
rsnt_cntn <= 11'h0;
end
else if (exits_r == 1'b1) begin
app_rstn0 <= 1'b0;
rsnt_cntn <= 11'h3f0;
end
else begin
rsnt_cntn <= rsnt_cntn + 11'h1;
if ((test_sim == 1'b1) &&
(rsnt_cntn >= rstn_cnt_maxsim) &&
(altpcie_sv_hip_ast_hwtcl_sim_only==1)) begin
app_rstn0 <= 1'b1;
end
else if (rsnt_cntn == rstn_cnt_max) begin
app_rstn0 <= 1'b1;
end
end
end
// monitor if ltssm is frozen in recovery state
// issue reset if timeout rcv_timeout
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
recovery_cnt <= {24{1'b0}};
recovery_rst <= 1'b0;
end
else begin
if (ltssm_r != ltssm_rcv) begin
recovery_cnt <= {24{1'b0}};
end
else if (recovery_cnt == rcv_timeout) begin
recovery_cnt <= recovery_cnt;
end
else if (ltssm_r == ltssm_rcv) begin
recovery_cnt <= recovery_cnt + 24'h1;
end
if (recovery_cnt == rcv_timeout) begin
recovery_rst <= 1'b1;
end
else if (ltssm_r != ltssm_rcv) begin
recovery_rst <= 1'b0;
end
end
end
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_arbiter #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_REG_REQ = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_DISABLE_PRIORITY = 1
)
(
ctl_clk,
ctl_reset_n,
// Common
stall_row_arbiter,
stall_col_arbiter,
// Sideband Interface
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
// TBP Interface
row_req,
col_req,
act_req,
pch_req,
rd_req,
wr_req,
row_grant,
col_grant,
act_grant,
pch_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_activate,
tbp_precharge,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_rmw_correct,
tbp_rmw_partial,
tbp_age,
tbp_priority,
// Rank Timer Interface
can_activate,
can_precharge,
can_write,
can_read,
// Arbiter Output Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// Common
input stall_row_arbiter;
input stall_col_arbiter;
// Sideband Interface
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
// TBP Interface
input [CFG_CTL_TBP_NUM - 1 : 0] row_req;
input [CFG_CTL_TBP_NUM - 1 : 0] col_req;
input [CFG_CTL_TBP_NUM - 1 : 0] act_req;
input [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
input [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
input [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
output [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
output or_row_grant;
output or_col_grant;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
input [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
input [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
input [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
input [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
// Rank Timer Interface
input [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] can_write;
input [CFG_CTL_TBP_NUM - 1 : 0] can_read;
// Arbiter Output Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
wire one = 1'b1;
wire zero = 1'b0;
// TBP Interface
reg [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
reg or_row_grant;
reg or_col_grant;
// Arbiter Output Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// Common
reg granted_read [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_write [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_c ;
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_INT_SIZE_WIDTH - 1 : 0] granted_size [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_DATA_ID_WIDTH - 1 : 0] granted_dataid [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] granted_localid [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_ap [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_burst_chop [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
// Arbiter
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
reg int_or_row_grant;
reg int_or_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Granted logic specific grant signals
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
granted_row_grant = row_grant;
granted_col_grant = col_grant;
granted_act_grant = act_grant;
granted_pch_grant = pch_grant;
granted_rd_grant = rd_grant;
granted_wr_grant = wr_grant;
log2_granted_row_grant = log2_row_grant;
log2_granted_col_grant = log2_col_grant;
log2_granted_act_grant = log2_act_grant;
log2_granted_pch_grant = log2_pch_grant;
log2_granted_rd_grant = log2_rd_grant;
log2_granted_wr_grant = log2_wr_grant;
end
//----------------------------------------------------------------------------------------------------
// Sideband outputs
//----------------------------------------------------------------------------------------------------
// Precharge all
always @ (*)
begin
arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
end
// Refresh
always @ (*)
begin
arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
end
// Self refresh
always @ (*)
begin
arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
end
// Power down
always @ (*)
begin
arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
end
// Power down
always @ (*)
begin
arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
end
// ZQ calibration
always @ (*)
begin
arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
end
// LMR
always @ (*)
begin
arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
end
//----------------------------------------------------------------------------------------------------
// Non arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
// Burst chop
always @ (*)
begin
arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
end
// Burst terminate
always @ (*)
begin
arb_do_burst_terminate = 0;
end
// RMW Correct
always @ (*)
begin
arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
end
// RMW Partial
always @ (*)
begin
arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
end
// LMR
always @ (*)
begin
arb_do_lmr = 0;
end
// Local ID
always @ (*)
begin
arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
end
// Data ID
always @ (*)
begin
arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
end
// Size
always @ (*)
begin
arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
end
// Column address
// column command will only require column address, therefore there will be no conflcting column addresses
always @ (*)
begin
arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
end
//----------------------------------------------------------------------------------------------------
// Arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_LOW_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_LOW_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_HIGH_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_HIGH_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_r [CFG_CTL_TBP_NUM - 1], granted_chipsel_c [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
end
end
else
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_c [CFG_CTL_TBP_NUM - 1], granted_chipsel_r [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Granted outputs
//----------------------------------------------------------------------------------------------------
// Chip address
always @ (*)
begin
granted_chipsel_r [0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
granted_chipsel_c [0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
end
// Bank address
always @ (*)
begin
granted_bank_r [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
granted_bank_c [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
end
// Row address
always @ (*)
begin
granted_row_r [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
granted_row_c [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
end
// Column address
always @ (*)
begin
granted_col [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col [CFG_MEM_IF_COL_WIDTH - 1 : 0];
end
// Size
always @ (*)
begin
granted_size [0] = {CFG_INT_SIZE_WIDTH {granted_col_grant [0]}} & tbp_size [CFG_INT_SIZE_WIDTH - 1 : 0];
end
// Local ID
always @ (*)
begin
granted_localid [0] = {CFG_LOCAL_ID_WIDTH {granted_col_grant [0]}} & tbp_localid [CFG_LOCAL_ID_WIDTH - 1 : 0];
end
// Data ID
always @ (*)
begin
granted_dataid [0] = {CFG_DATA_ID_WIDTH {granted_col_grant [0]}} & tbp_dataid [CFG_DATA_ID_WIDTH - 1 : 0];
end
// Auto precharge
always @ (*)
begin
granted_ap [0] = granted_col_grant [0] & tbp_ap [ 0];
end
// Burst Chop
always @ (*)
begin
granted_burst_chop [0] = granted_col_grant [0] & tbp_burst_chop [ 0];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [0] = granted_col_grant [0] & tbp_rmw_correct [ 0];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [0] = granted_col_grant [0] & tbp_rmw_partial [ 0];
end
generate
begin
genvar j_tbp;
for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : granted_information_per_tbp
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] chipsel_addr = tbp_chipsel [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] bank_addr = tbp_bank [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr = tbp_row [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr = tbp_col [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
wire [CFG_INT_SIZE_WIDTH - 1 : 0] size = tbp_size [(j_tbp + 1) * CFG_INT_SIZE_WIDTH - 1 : j_tbp * CFG_INT_SIZE_WIDTH ];
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] localid = tbp_localid [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH - 1 : j_tbp * CFG_LOCAL_ID_WIDTH ];
wire [CFG_DATA_ID_WIDTH - 1 : 0] dataid = tbp_dataid [(j_tbp + 1) * CFG_DATA_ID_WIDTH - 1 : j_tbp * CFG_DATA_ID_WIDTH ];
wire ap = tbp_ap [(j_tbp + 1) - 1 : j_tbp ];
wire burst_chop = tbp_burst_chop [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_correct = tbp_rmw_correct [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_partial = tbp_rmw_partial [(j_tbp + 1) - 1 : j_tbp ];
// Chip address
always @ (*)
begin
granted_chipsel_r [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r [j_tbp - 1];
granted_chipsel_c [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c [j_tbp - 1];
end
// Bank address
always @ (*)
begin
granted_bank_r [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr ) | granted_bank_r [j_tbp - 1];
granted_bank_c [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr ) | granted_bank_c [j_tbp - 1];
end
// Row address
always @ (*)
begin
granted_row_r [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr ) | granted_row_r [j_tbp - 1];
granted_row_c [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr ) | granted_row_c [j_tbp - 1];
end
// Column address
always @ (*)
begin
granted_col [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr ) | granted_col [j_tbp - 1];
end
// Size
always @ (*)
begin
granted_size [j_tbp] = ({CFG_INT_SIZE_WIDTH {granted_col_grant [j_tbp]}} & size ) | granted_size [j_tbp - 1];
end
// Local ID
always @ (*)
begin
granted_localid [j_tbp] = ({CFG_LOCAL_ID_WIDTH {granted_col_grant [j_tbp]}} & localid ) | granted_localid [j_tbp - 1];
end
// Data ID
always @ (*)
begin
granted_dataid [j_tbp] = ({CFG_DATA_ID_WIDTH {granted_col_grant [j_tbp]}} & dataid ) | granted_dataid [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_ap [j_tbp] = ( granted_col_grant [j_tbp] & ap ) | granted_ap [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_burst_chop [j_tbp] = ( granted_col_grant [j_tbp] & burst_chop ) | granted_burst_chop [j_tbp - 1];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [j_tbp] = ( granted_col_grant [j_tbp] & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [j_tbp] = ( granted_col_grant [j_tbp] & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Arbiter
//
// Arbitration Rules (Priority Command-Aging Arbiter):
//
// - If only one master is requesting, grant that master immediately ELSE
// - If two of more masters are requesting:
// - Grant the request with priority ELSE
// - Grant read request over write request ELSE
// - Grant oldest request
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common logic
//----------------------------------------------------------------------------------------------------
// Indicate OR of both grant signal
assign all_grant = row_grant | col_grant;
//----------------------------------------------------------------------------------------------------
// Priority Command-aging logic
//----------------------------------------------------------------------------------------------------
// ==========Command-Aging==========
//
// The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies will have the following value:
// TBP0 age - 0000
// TBP1 age - 0001
// TBP2 age - 0011
// TBP3 age - 0111
// Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
// TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
// TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
// So the oldest_req signal will have "0010"
//
// ==========Priority==========
//
// The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
// if there are more than 1 priority command, it will pick the oldest priority command
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies and priority bit will have the following value:
// TBP0 age - 0000 priority - 0
// TBP1 age - 0001 priority - 1
// TBP2 age - 0011 priority - 1
// TBP3 age - 0111 priority - 0
// Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
// and the rest will be set to '0'
// If there is/are priority command/s, we need to select between those priority command
// if there is no priority command, we set int_priority to all '1'
// this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
always @ (*)
begin
int_act_priority = {CFG_CTL_TBP_NUM{one}};
int_pch_priority = {CFG_CTL_TBP_NUM{one}};
if (CFG_DISABLE_PRIORITY == 1)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
if ((tbp_priority & col_req) == 0)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
int_col_priority = tbp_priority;
end
end
end
generate
begin
genvar k_tbp;
for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
begin : priority_request_per_tbp
wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
reg pre_calculated_act_info;
reg pre_calculated_pch_info;
reg pre_calculated_rd_info;
reg pre_calculated_wr_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
if (CFG_REG_REQ)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_info <= 1'b0;
pre_calculated_pch_info <= 1'b0;
pre_calculated_rd_info <= 1'b0;
pre_calculated_wr_info <= 1'b0;
end
else
begin
pre_calculated_act_info <= int_act_priority [k_tbp];
pre_calculated_pch_info <= int_pch_priority [k_tbp];
pre_calculated_rd_info <= int_col_priority [k_tbp];
pre_calculated_wr_info <= int_col_priority [k_tbp];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_age_info <= 0;
pre_calculated_pch_age_info <= 0;
pre_calculated_rd_age_info <= 0;
pre_calculated_wr_age_info <= 0;
end
else
begin
pre_calculated_act_age_info <= current_age & int_act_priority;
pre_calculated_pch_age_info <= current_age & int_pch_priority;
pre_calculated_rd_age_info <= current_age & int_col_priority;
pre_calculated_wr_age_info <= current_age & int_col_priority;
end
end
end
else
begin
always @ (*)
begin
pre_calculated_act_info = int_act_priority [k_tbp];
pre_calculated_pch_info = int_pch_priority [k_tbp];
pre_calculated_rd_info = int_col_priority [k_tbp];
pre_calculated_wr_info = int_col_priority [k_tbp];
end
always @ (*)
begin
pre_calculated_act_age_info = current_age & int_act_priority;
pre_calculated_pch_age_info = current_age & int_pch_priority;
pre_calculated_rd_age_info = current_age & int_col_priority;
pre_calculated_wr_age_info = current_age & int_col_priority;
end
end
always @ (*)
begin
oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
oldest_rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp] & ~|(pre_calculated_rd_age_info & rd_req & can_read );
oldest_wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp] & ~|(pre_calculated_wr_age_info & wr_req & can_write );
end
always @ (*)
begin
act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp];
pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp];
wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp];
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Arbiter logic
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
// Full rate arbiter
always @ (*)
begin
int_row_grant = 0;
int_col_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_row_grant = 1'b0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
end
else
begin
// Half and quarter rate arbiter
// Row arbiter
always @ (*)
begin
int_row_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_or_row_grant = 1'b0;
if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
// Column arbiter
always @ (*)
begin
int_col_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
end
end
end
endgenerate
generate
begin
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_grant <= 0;
col_grant <= 0;
act_grant <= 0;
pch_grant <= 0;
rd_grant <= 0;
wr_grant <= 0;
or_row_grant <= 0;
or_col_grant <= 0;
end
else
begin
row_grant <= int_row_grant;
col_grant <= int_col_grant;
act_grant <= int_act_grant;
pch_grant <= int_pch_grant;
rd_grant <= int_rd_grant;
wr_grant <= int_wr_grant;
or_row_grant <= int_or_row_grant;
or_col_grant <= int_or_col_grant;
end
end
always @ (*)
begin
log2_row_grant = log2(row_grant);
log2_col_grant = log2(col_grant);
log2_act_grant = log2(act_grant);
log2_pch_grant = log2(pch_grant);
log2_rd_grant = log2(rd_grant );
log2_wr_grant = log2(wr_grant );
end
end
else
begin
always @ (*)
begin
row_grant = int_row_grant;
col_grant = int_col_grant;
act_grant = int_act_grant;
pch_grant = int_pch_grant;
rd_grant = int_rd_grant;
wr_grant = int_wr_grant;
log2_row_grant = log2(int_row_grant);
log2_col_grant = log2(int_col_grant);
log2_act_grant = log2(int_act_grant);
log2_pch_grant = log2(int_pch_grant);
log2_rd_grant = log2(int_rd_grant );
log2_wr_grant = log2(int_wr_grant );
or_row_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
or_col_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Arbiter
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
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// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500011272 : 255;
endmodule
|
module Router_20( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_5_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_5_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_2_to_8_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_2_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_5_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [36:0] _ingress_unit_2_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_5_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
|
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: v_sync.v
//
// Description:
// This is the VSYNC signal generator. It generates
// the appropriate VSYNC signal for the target TFT display. The core
// of this module is a state machine that controls 4 counters and the
// VSYNC and V_DE signals.
//
// Design Notes:
// -- Input clock is (~HSYNC)
// -- Input rst is vsync_rst signal generated from the h_sync.v module
// -- V_DE is and with H_DE to generate DE signal for the TFT display
// -- v_bp_cnt_tc is the terminal count of the back porch time counter. Used to
// -- generate get_line_start pulse.
// -- v_l_cnt_tc is the terminal count of the line time counter. Used to not
// -- generate get_line_start pulse.
//
//-----------------------------------------------------------------------------
// Structure:
// -- v_sync.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/ 100 ps
module v_sync(
clk, // I
clk_stb, // I
rst, // I
VSYNC, // O
V_DE, // O
v_bp_cnt_tc, // O
v_l_cnt_tc); // O
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input clk_stb;
input rst;
output VSYNC;
output V_DE;
output v_bp_cnt_tc;
output v_l_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg V_DE;
reg VSYNC;
reg [0:1] v_p_cnt; // 2-bit counter (2 HSYNCs for pulse time)
reg [0:4] v_bp_cnt; // 5-bit counter (31 HSYNCs for back porch time)
reg [0:8] v_l_cnt; // 9-bit counter (480 HSYNCs for line time)
reg [0:3] v_fp_cnt; // 4-bit counter (12 HSYNCs for front porch time)
reg v_p_cnt_ce;
reg v_bp_cnt_ce;
reg v_l_cnt_ce;
reg v_fp_cnt_ce;
reg v_p_cnt_clr;
reg v_bp_cnt_clr;
reg v_l_cnt_clr;
reg v_fp_cnt_clr;
reg v_p_cnt_tc;
reg v_bp_cnt_tc;
reg v_l_cnt_tc;
reg v_fp_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - State Declaration
///////////////////////////////////////////////////////////////////////////////
parameter [0:4] SET_COUNTERS = 5'b00001;
parameter [0:4] PULSE = 5'b00010;
parameter [0:4] BACK_PORCH = 5'b00100;
parameter [0:4] LINE = 5'b01000;
parameter [0:4] FRONT_PORCH = 5'b10000;
reg [0:4] VSYNC_cs /*synthesis syn_encoding="onehot"*/;
reg [0:4] VSYNC_ns;
///////////////////////////////////////////////////////////////////////////////
// clock enable State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
reg clk_stb_d1;
reg clk_ce_neg;
reg clk_ce_pos;
always @ (posedge clk)
begin
clk_stb_d1 <= clk_stb;
clk_ce_pos <= clk_stb & ~clk_stb_d1;
clk_ce_neg <= ~clk_stb & clk_stb_d1;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (rst) VSYNC_cs = SET_COUNTERS;
else if (clk_ce_pos) VSYNC_cs = VSYNC_ns;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Combinatorial Block
///////////////////////////////////////////////////////////////////////////////
always @ (VSYNC_cs or v_p_cnt_tc or v_bp_cnt_tc or v_l_cnt_tc or v_fp_cnt_tc)
begin
case (VSYNC_cs)
/////////////////////////////////////////////////////////////////////////
// SET COUNTERS STATE
// -- Clear and de-enable all counters on frame_start signal
/////////////////////////////////////////////////////////////////////////
SET_COUNTERS: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// PULSE STATE
// -- Enable pulse counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
PULSE: begin
v_p_cnt_ce = 1;
v_p_cnt_clr = 0;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 0;
V_DE = 0;
if (v_p_cnt_tc == 0) VSYNC_ns = PULSE;
else VSYNC_ns = BACK_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// BACK PORCH STATE
// -- Enable back porch counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
BACK_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 1;
v_bp_cnt_clr = 0;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
if (v_bp_cnt_tc == 0) VSYNC_ns = BACK_PORCH;
else VSYNC_ns = LINE;
end
/////////////////////////////////////////////////////////////////////////
// LINE STATE
// -- Enable line counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
LINE: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 1;
v_l_cnt_clr = 0;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 1;
if (v_l_cnt_tc == 0) VSYNC_ns = LINE;
else VSYNC_ns = FRONT_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// FRONT PORCH STATE
// -- Enable front porch counter
// -- De-enable others
// -- Wraps to PULSE state
/////////////////////////////////////////////////////////////////////////
FRONT_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
if (v_fp_cnt_tc == 0) VSYNC_ns = FRONT_PORCH;
else VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// DEFAULT STATE
/////////////////////////////////////////////////////////////////////////
default: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = SET_COUNTERS;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Pulse Counter - Counts 2 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_p_cnt_clr) begin
v_p_cnt = 2'b0;
v_p_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_p_cnt_ce) begin
if (v_p_cnt == 1) begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 1;
end
else begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Back Porch Counter - Counts 31 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_bp_cnt_clr) begin
v_bp_cnt = 5'b0;
v_bp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_bp_cnt_ce) begin
if (v_bp_cnt == 30) begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 1;
end
else begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Line Counter - Counts 480 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_l_cnt_clr) begin
v_l_cnt = 9'b0;
v_l_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_l_cnt_ce) begin
if (v_l_cnt == 479) begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 1;
end
else begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Front Porch Counter - Counts 12 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_fp_cnt_clr) begin
v_fp_cnt = 4'b0;
v_fp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_fp_cnt_ce) begin
if (v_fp_cnt == 11) begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 1;
end
else begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 0;
end
end
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_core
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
// MIF Streaming parameters
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata,
//other
output wire mif_start_out,
output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr
);
localparam mode_WR = 1'b0;
localparam mode_POLL = 1'b1;
localparam MODE_REG = 6'b000000;
localparam STATUS_REG = 6'b000001;
localparam START_REG = 6'b000010;
localparam N_REG = 6'b000011;
localparam M_REG = 6'b000100;
localparam C_COUNTERS_REG = 6'b000101;
localparam DPS_REG = 6'b000110;
localparam DSM_REG = 6'b000111;
localparam BWCTRL_REG = 6'b001000;
localparam CP_CURRENT_REG = 6'b001001;
localparam ANY_DPRIO = 6'b100000;
localparam CNT_BASE = 5'b001010;
localparam MIF_REG = 6'b011111;
//C Counters
localparam number_of_counters = 5'd18;
localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
//C counter addresses
localparam C_CNT_0_DIV_ADDR = 5'h00;
localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
//N counter addresses
localparam N_CNT_DIV_ADDR = 5'h13;
localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
//M counter addresses
localparam M_CNT_DIV_ADDR = 5'h12;
localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
//DSM address
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
localparam DSM_K_READY_ADDR = 5'h17;
localparam DSM_K_DITHER_ADDR = 5'h17;
localparam DSM_OUT_SEL_ADDR = 6'h30;
//Other DSM params
localparam DSM_K_READY_BIT_INDEX = 4'd11;
//BWCTRL address
//Bit 0-3 of addr
localparam BWCTRL_ADDR = 6'h30;
//CP_CURRENT address
//Bit 0-2 of addr
localparam CP_CURRENT_ADDR = 6'h31;
localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
wire clk;
wire reset;
wire gnd;
wire [5: 0] slave_address;
wire slave_read;
wire slave_write;
wire [31: 0] slave_writedata;
reg [31: 0] slave_readdata_d;
reg [31: 0] slave_readdata_q;
wire slave_waitrequest;
assign clk = mgmt_clk;
assign slave_address = mgmt_address;
assign slave_read = mgmt_read;
assign slave_write = mgmt_write;
assign slave_writedata = mgmt_writedata;
// Outputs
assign mgmt_readdata = slave_readdata_q;
assign mgmt_waitrequest = slave_waitrequest;
//internal signals
wire locked;
wire pll_start;
wire pll_start_valid;
reg status_read;
wire read_slave_mode_asserted;
wire pll_start_asserted;
reg [1:0] current_state;
reg [1:0] next_state;
reg slave_mode;
reg status;//0=busy, 1=ready
//user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
//declaring the init wires. These will have 0 on them for 64 clk cycles
wire [ 5:0] init_dprio_address;
wire init_dprio_read;
wire [ 1:0] init_dprio_byteen;
wire init_dprio_write;
wire [15:0] init_dprio_writedata;
wire init_atpgmode;
wire init_mdio_dis;
wire init_scanen;
wire init_ser_shift_load;
wire dprio_init_done;
//DPRIO output signals after initialization is done
wire dprio_clk;
reg avmm_dprio_write;
reg avmm_dprio_read;
reg [5:0] avmm_dprio_address;
reg [15:0] avmm_dprio_writedata;
reg [1:0] avmm_dprio_byteen;
wire avmm_atpgmode;
wire avmm_mdio_dis;
wire avmm_scanen;
//Final output wires that are muxed between the init and avmm wires.
wire dprio_init_reset;
wire [5:0] dprio_address /*synthesis keep*/;
wire dprio_read/*synthesis keep*/;
wire [1:0] dprio_byteen/*synthesis keep*/;
wire dprio_write/*synthesis keep*/;
wire [15:0] dprio_writedata/*synthesis keep*/;
wire dprio_mdio_dis/*synthesis keep*/;
wire dprio_ser_shift_load/*synthesis keep*/;
wire dprio_atpgmode/*synthesis keep*/;
wire dprio_scanen/*synthesis keep*/;
//other PLL signals for dyn ph shift
wire phase_done/*synthesis keep*/;
wire phase_en/*synthesis keep*/;
wire up_dn/*synthesis keep*/;
wire [4:0] cnt_sel;
//DPRIO input signals
wire [15:0] dprio_readdata;
//internal logic signals
//storage registers for user sent data
reg dprio_temp_read_1;
reg dprio_temp_read_2;
reg dprio_start;
reg mif_start_assert;
reg dps_start_assert;
wire usr_valid_changes;
reg [3:0] dprio_cur_state;
reg [3:0] dprio_next_state;
reg [15:0] dprio_temp_m_n_c_readdata_1_d;
reg [15:0] dprio_temp_m_n_c_readdata_2_d;
reg [15:0] dprio_temp_m_n_c_readdata_1_q;
reg [15:0] dprio_temp_m_n_c_readdata_2_q;
reg dprio_write_done;
//C counters signals
reg [7:0] usr_c_cnt_lo;
reg [7:0] usr_c_cnt_hi;
reg usr_c_cnt_bypass_en;
reg usr_c_cnt_odd_duty_div_en;
reg [7:0] temp_c_cnt_lo [0:17];
reg [7:0] temp_c_cnt_hi [0:17];
reg temp_c_cnt_bypass_en [0:17];
reg temp_c_cnt_odd_duty_div_en [0:17];
reg any_c_cnt_changed;
reg all_c_cnt_done_q;
reg all_c_cnt_done_d;
reg [17:0] c_cnt_changed;
reg [17:0] c_cnt_done_d;
reg [17:0] c_cnt_done_q;
//N counter signals
reg [7:0] usr_n_cnt_lo;
reg [7:0] usr_n_cnt_hi;
reg usr_n_cnt_bypass_en;
reg usr_n_cnt_odd_duty_div_en;
reg n_cnt_changed;
reg n_cnt_done_d;
reg n_cnt_done_q;
//M counter signals
reg [7:0] usr_m_cnt_lo;
reg [7:0] usr_m_cnt_hi;
reg usr_m_cnt_bypass_en;
reg usr_m_cnt_odd_duty_div_en;
reg m_cnt_changed;
reg m_cnt_done_d;
reg m_cnt_done_q;
//dyn phase regs
reg [15:0] usr_num_shifts;
reg [4:0] usr_cnt_sel /*synthesis preserve*/;
reg usr_up_dn;
reg dps_changed;
wire dps_changed_valid;
wire dps_done;
//DSM Signals
reg [31:0] usr_k_value;
reg dsm_k_changed;
reg dsm_k_done_d;
reg dsm_k_done_q;
reg dsm_k_ready_false_done_d;
//BW signals
reg [3:0] usr_bwctrl_value;
reg bwctrl_changed;
reg bwctrl_done_d;
reg bwctrl_done_q;
//CP signals
reg [2:0] usr_cp_current_value;
reg cp_current_changed;
reg cp_current_done_d;
reg cp_current_done_q;
//Manual DPRIO signals
reg manual_dprio_done_q;
reg manual_dprio_done_d;
reg manual_dprio_changed;
reg [5:0] usr_dprio_address;
reg [15:0] usr_dprio_writedata_0;
reg usr_r_w;
//keeping track of which operation happened last
reg [5:0] operation_address;
// Address wires for all C_counter DPRIO registers
// These are outputs of LUTS, changing depending
// on whether PLL_0 or PLL_1 being used
//Fitter will tell if FPLL1 is being used
wire fpll_1;
// other
reg mif_reg_asserted;
// MAIN FSM
always @(posedge clk)
begin
if (reset)
begin
dprio_cur_state <= DPRIO_IDLE;
current_state <= IDLE;
end
else
begin
current_state <= next_state;
dprio_cur_state <= dprio_next_state;
end
end
always @(*)
begin
case(current_state)
IDLE:
begin
if (pll_start & !slave_waitrequest & usr_valid_changes)
next_state = WAIT_ON_LOCK;
else
next_state = IDLE;
end
WAIT_ON_LOCK:
begin
if (locked & dps_done & dprio_write_done) // received locked high from PLL
begin
if (slave_mode==mode_WR) //if the mode is waitrequest, then
// goto IDLE state directly
next_state = IDLE;
else
next_state = LOCKED; //otherwise go the locked state
end
else
next_state = WAIT_ON_LOCK;
end
LOCKED:
begin
if (status_read) // stay in LOCKED until user reads status
next_state = IDLE;
else
next_state = LOCKED;
end
default: next_state = 2'bxx;
endcase
end
// ask the pll to start reconfig
assign pll_start = (pll_start_asserted & (current_state==IDLE)) ;
assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ;
// WRITE OPERATIONS
assign pll_start_asserted = slave_write & (slave_address == START_REG);
assign mif_start_out = pll_start & mif_reg_asserted;
//reading the mode register to determine what mode the slave will operate
//in.
always @(posedge clk)
begin
if (reset)
slave_mode <= mode_WR;
else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
slave_mode <= slave_writedata[0];
end
//record which values user wants to change.
//reading in the actual values that need to be reconfigged and sending
//them to the PLL
always @(posedge clk)
begin
if (reset)
begin
//reset all regs here
//BW signals reset
usr_bwctrl_value <= 0;
bwctrl_changed <= 0;
bwctrl_done_q <= 0;
//CP signals reset
usr_cp_current_value <= 0;
cp_current_changed <= 0;
cp_current_done_q <= 0;
//DSM signals reset
usr_k_value <= 0;
dsm_k_changed <= 0;
dsm_k_done_q <= 0;
//N counter signals reset
usr_n_cnt_lo <= 0;
usr_n_cnt_hi <= 0;
usr_n_cnt_bypass_en <= 0;
usr_n_cnt_odd_duty_div_en <= 0;
n_cnt_changed <= 0;
n_cnt_done_q <= 0;
//M counter signals reset
usr_m_cnt_lo <= 0;
usr_m_cnt_hi <= 0;
usr_m_cnt_bypass_en <= 0;
usr_m_cnt_odd_duty_div_en <= 0;
m_cnt_changed <= 0;
m_cnt_done_q <= 0;
//C counter signals reset
usr_c_cnt_lo <= 0;
usr_c_cnt_hi <= 0;
usr_c_cnt_bypass_en <= 0;
usr_c_cnt_odd_duty_div_en <= 0;
any_c_cnt_changed <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
//generic signals
dprio_start <= 0;
mif_start_assert <= 0;
dps_start_assert <= 0;
dprio_temp_m_n_c_readdata_1_q <= 0;
dprio_temp_m_n_c_readdata_2_q <= 0;
c_cnt_done_q <= 0;
//DPS signals
usr_up_dn <= 0;
usr_cnt_sel <= 0;
usr_num_shifts <= 0;
dps_changed <= 0;
//manual DPRIO signals
manual_dprio_changed <= 0;
usr_dprio_address <= 0;
usr_dprio_writedata_0 <= 0;
usr_r_w <= 0;
operation_address <= 0;
mif_reg_asserted <= 0;
mif_base_addr <= 0;
end
else
begin
if (dprio_temp_read_1)
begin
dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d;
end
if (dprio_temp_read_2)
begin
dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d;
end
if ((dps_done)) dps_changed <= 0;
if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
if (mif_start_out == 1'b1)
mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
if (dps_done != 1'b1)
dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
if (dprio_next_state == ONE)
dprio_start <= 0;
if (dprio_write_done)
begin
bwctrl_done_q <= 0;
cp_current_done_q <= 0;
dsm_k_done_q <= 0;
dsm_k_done_q <= 0;
n_cnt_done_q <= 0;
m_cnt_done_q <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
dsm_k_changed <= 0;
n_cnt_changed <= 0;
m_cnt_changed <= 0;
any_c_cnt_changed <= 0;
bwctrl_changed <= 0;
cp_current_changed <= 0;
manual_dprio_changed <= 0;
manual_dprio_done_q <= 0;
if (dps_changed | dps_changed_valid | !dps_done )
begin
usr_cnt_sel <= usr_cnt_sel;
end
else
begin
usr_cnt_sel <= 0;
end
mif_reg_asserted <= 0;
end
else
begin
dsm_k_changed <= dsm_k_changed;
n_cnt_changed <= n_cnt_changed;
m_cnt_changed <= m_cnt_changed;
any_c_cnt_changed <= any_c_cnt_changed;
manual_dprio_changed <= manual_dprio_changed;
mif_reg_asserted <= mif_reg_asserted;
usr_cnt_sel <= usr_cnt_sel;
end
if(slave_write & !slave_waitrequest)
begin
case(slave_address)
//read in the values here from the user and act on them
DSM_REG:
begin
operation_address <= DSM_REG;
usr_k_value <= slave_writedata[31:0];
dsm_k_changed <= 1'b1;
dsm_k_done_q <= 0;
dprio_start <= 1'b1;
end
N_REG:
begin
operation_address <= N_REG;
usr_n_cnt_lo <= slave_writedata[7:0];
usr_n_cnt_hi <= slave_writedata[15:8];
usr_n_cnt_bypass_en <= slave_writedata[16];
usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
n_cnt_changed <= 1'b1;
n_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
M_REG:
begin
operation_address <= M_REG;
usr_m_cnt_lo <= slave_writedata[7:0];
usr_m_cnt_hi <= slave_writedata[15:8];
usr_m_cnt_bypass_en <= slave_writedata[16];
usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
m_cnt_changed <= 1'b1;
m_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
DPS_REG:
begin
operation_address <= DPS_REG;
usr_num_shifts <= slave_writedata[15:0];
usr_cnt_sel <= slave_writedata[20:16];
usr_up_dn <= slave_writedata[21];
dps_changed <= 1;
dps_start_assert <= 1;
end
C_COUNTERS_REG:
begin
operation_address <= C_COUNTERS_REG;
usr_c_cnt_lo <= slave_writedata[7:0];
usr_c_cnt_hi <= slave_writedata[15:8];
usr_c_cnt_bypass_en <= slave_writedata[16];
usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
usr_cnt_sel <= slave_writedata[22:18];
any_c_cnt_changed <= 1'b1;
all_c_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
BWCTRL_REG:
begin
usr_bwctrl_value <= slave_writedata[3:0];
bwctrl_changed <= 1'b1;
bwctrl_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= BWCTRL_REG;
end
CP_CURRENT_REG:
begin
usr_cp_current_value <= slave_writedata[2:0];
cp_current_changed <= 1'b1;
cp_current_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= CP_CURRENT_REG;
end
ANY_DPRIO:
begin
operation_address <= ANY_DPRIO;
manual_dprio_changed <= 1'b1;
usr_dprio_address <= slave_writedata[5:0];
usr_dprio_writedata_0 <= slave_writedata[21:6];
usr_r_w <= slave_writedata[22];
manual_dprio_done_q <= 0;
dprio_start <= 1'b1;
end
MIF_REG:
begin
mif_reg_asserted <= 1'b1;
mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
mif_start_assert <= 1'b1;
end
endcase
end
end
end
//C Counter assigning values to the 2-d array of values for each C counter
reg [4:0] j;
always @(posedge clk)
begin
if (reset)
begin
c_cnt_changed[17:0] <= 0;
for (j = 0; j < number_of_counters; j = j + 1'b1)
begin : c_cnt_reset
temp_c_cnt_bypass_en[j] <= 0;
temp_c_cnt_odd_duty_div_en[j] <= 0;
temp_c_cnt_lo[j][7:0] <= 0;
temp_c_cnt_hi[j][7:0] <= 0;
end
end
else
begin
if (dprio_write_done)
begin
c_cnt_changed <= 0;
end
if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
begin
case (cnt_sel)
CNT_0:
begin
temp_c_cnt_lo [0] <= usr_c_cnt_lo;
temp_c_cnt_hi [0] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [0] <= 1'b1;
end
CNT_1:
begin
temp_c_cnt_lo [1] <= usr_c_cnt_lo;
temp_c_cnt_hi [1] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [1] <= 1'b1;
end
CNT_2:
begin
temp_c_cnt_lo [2] <= usr_c_cnt_lo;
temp_c_cnt_hi [2] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [2] <= 1'b1;
end
CNT_3:
begin
temp_c_cnt_lo [3] <= usr_c_cnt_lo;
temp_c_cnt_hi [3] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [3] <= 1'b1;
end
CNT_4:
begin
temp_c_cnt_lo [4] <= usr_c_cnt_lo;
temp_c_cnt_hi [4] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [4] <= 1'b1;
end
CNT_5:
begin
temp_c_cnt_lo [5] <= usr_c_cnt_lo;
temp_c_cnt_hi [5] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [5] <= 1'b1;
end
CNT_6:
begin
temp_c_cnt_lo [6] <= usr_c_cnt_lo;
temp_c_cnt_hi [6] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [6] <= 1'b1;
end
CNT_7:
begin
temp_c_cnt_lo [7] <= usr_c_cnt_lo;
temp_c_cnt_hi [7] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [7] <= 1'b1;
end
CNT_8:
begin
temp_c_cnt_lo [8] <= usr_c_cnt_lo;
temp_c_cnt_hi [8] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [8] <= 1'b1;
end
CNT_9:
begin
temp_c_cnt_lo [9] <= usr_c_cnt_lo;
temp_c_cnt_hi [9] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [9] <= 1'b1;
end
CNT_10:
begin
temp_c_cnt_lo [10] <= usr_c_cnt_lo;
temp_c_cnt_hi [10] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [10] <= 1'b1;
end
CNT_11:
begin
temp_c_cnt_lo [11] <= usr_c_cnt_lo;
temp_c_cnt_hi [11] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [11] <= 1'b1;
end
CNT_12:
begin
temp_c_cnt_lo [12] <= usr_c_cnt_lo;
temp_c_cnt_hi [12] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [12] <= 1'b1;
end
CNT_13:
begin
temp_c_cnt_lo [13] <= usr_c_cnt_lo;
temp_c_cnt_hi [13] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [13] <= 1'b1;
end
CNT_14:
begin
temp_c_cnt_lo [14] <= usr_c_cnt_lo;
temp_c_cnt_hi [14] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [14] <= 1'b1;
end
CNT_15:
begin
temp_c_cnt_lo [15] <= usr_c_cnt_lo;
temp_c_cnt_hi [15] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [15] <= 1'b1;
end
CNT_16:
begin
temp_c_cnt_lo [16] <= usr_c_cnt_lo;
temp_c_cnt_hi [16] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [16] <= 1'b1;
end
CNT_17:
begin
temp_c_cnt_lo [17] <= usr_c_cnt_lo;
temp_c_cnt_hi [17] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [17] <= 1'b1;
end
endcase
end
end
end
//logic to handle which writes the user indicated and wants to start.
assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed;
//start the reconfig operations by writing to the DPRIO
reg break_loop;
reg [4:0] i;
always @(*)
begin
dprio_temp_read_1 = 0;
dprio_temp_read_2 = 0;
dprio_temp_m_n_c_readdata_1_d = 0;
dprio_temp_m_n_c_readdata_2_d = 0;
break_loop = 0;
dprio_next_state = DPRIO_IDLE;
avmm_dprio_write = 0;
avmm_dprio_read = 0;
avmm_dprio_address = 0;
avmm_dprio_writedata = 0;
avmm_dprio_byteen = 0;
dprio_write_done = 1;
manual_dprio_done_d = 0;
n_cnt_done_d = 0;
dsm_k_done_d = 0;
dsm_k_ready_false_done_d = 0;
m_cnt_done_d = 0;
c_cnt_done_d[17:0] = 0;
all_c_cnt_done_d = 0;
bwctrl_done_d = 0;
cp_current_done_d = 0;
i = 0;
// Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes)
if (dprio_start | mif_start_assert)
dprio_write_done = 0;
if (current_state == WAIT_ON_LOCK)
begin
case (dprio_cur_state)
ONE:
begin
if (n_cnt_changed & !n_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = N_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = M_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_hilo
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
//To break from the loop, since only one counter
//is addressed at a time
break_loop = 1'b1;
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (cp_current_changed & !cp_current_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_write = usr_r_w;
avmm_dprio_address = usr_dprio_address;
avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
end
else dprio_next_state = DPRIO_IDLE;
end
TWO:
begin
//handle reading the two setting bits on n_cnt, then
//writing them back while preserving other bits.
//Issue two consecutive reads then wait; readLatency=3
dprio_write_done = 0;
dprio_next_state = THREE;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
//reading the K ready 16 bit word. Need to write 0 to it
//afterwards to indicate that K has not been done writing
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
dprio_next_state = FOUR;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
dprio_next_state = FOUR;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
dprio_next_state = FOUR;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
avmm_dprio_read = ~usr_r_w;
avmm_dprio_address = usr_dprio_address;
dprio_next_state = DPRIO_DONE;
end
else dprio_next_state = DPRIO_IDLE;
end
THREE:
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
dprio_next_state = FOUR;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
else dprio_next_state = DPRIO_IDLE;
end
FOUR:
begin
dprio_temp_read_1 = 1'b1;
dprio_write_done = 0;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
dprio_next_state = FIVE;
end
else dprio_next_state = DPRIO_IDLE;
end
FIVE:
begin
dprio_write_done = 0;
dprio_temp_read_2 = 1'b1;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
//this is where DSM ready value comes.
//Need to store in a register to be used later
dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
dprio_next_state = SIX;
end
else dprio_next_state = DPRIO_IDLE;
end
SIX:
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = SEVEN;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_write = 0;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_write = 0;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_write = 0;
end
else dprio_next_state = DPRIO_IDLE;
end
SEVEN:
begin
dprio_write_done = 0;
dprio_next_state = EIGHT;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
n_cnt_done_d = 1'b1;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
m_cnt_done_d = 1'b1;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
dsm_k_ready_false_done_d = 1'b1;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
avmm_dprio_writedata[3:0] = usr_bwctrl_value;
bwctrl_done_d = 1'b1;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
avmm_dprio_writedata[2:0] = usr_cp_current_value;
cp_current_done_d = 1'b1;
end
//if all C_cnt that were changed are done, then assert all_c_cnt_done
if (c_cnt_done_d == c_cnt_changed)
all_c_cnt_done_d = 1'b1;
if (n_cnt_changed & n_cnt_done_d)
dprio_next_state = DPRIO_DONE;
if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
dprio_next_state = ONE;
else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
dprio_next_state = ONE;
else if (dsm_k_changed & !dsm_k_ready_false_done_d)
dprio_next_state = TWO;
else if (dsm_k_changed & !dsm_k_done_q)
dprio_next_state = EIGHT;
else if (bwctrl_changed & !bwctrl_done_d)
dprio_next_state = TWO;
else if (cp_current_changed & !cp_current_done_d)
dprio_next_state = TWO;
else
begin
dprio_next_state = DPRIO_DONE;
dprio_write_done = 1'b1;
end
end
//finish the rest of the DSM reads/writes
//writing k value, writing k_ready to 1.
EIGHT:
begin
dprio_write_done = 0;
dprio_next_state = NINE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
avmm_dprio_writedata[15:0] = usr_k_value[15:0];
end
end
NINE:
begin
dprio_write_done = 0;
dprio_next_state = TEN;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
avmm_dprio_writedata[15:0] = usr_k_value[31:16];
end
end
TEN:
begin
dprio_write_done = 0;
dprio_next_state = ONE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
//already have the readdata for DSM_K_READY_ADDR since we read it
//earlier. Just reuse here
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
dsm_k_done_d = 1'b1;
end
end
DPRIO_DONE:
begin
dprio_write_done = 1'b1;
if (dprio_start) dprio_next_state = DPRIO_IDLE;
else dprio_next_state = DPRIO_DONE;
end
DPRIO_IDLE:
begin
if (dprio_start) dprio_next_state = ONE;
else dprio_next_state = DPRIO_IDLE;
end
default: dprio_next_state = 4'bxxxx;
endcase
end
end
//assert the waitreq signal according to the state of the slave
assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
// Read operations
always @(*)
begin
status = 0;
if (slave_mode == mode_POLL)
//asserting status to 1 if the slave is done.
status = (current_state == LOCKED);
end
//************************************************************//
//************************************************************//
//******************** READ STATE MACHINE ********************//
//************************************************************//
//************************************************************//
reg [1:0] current_read_state;
reg [1:0] next_read_state;
reg [5:0] slave_address_int_d;
reg [5:0] slave_address_int_q;
reg dprio_read_1;
reg [5:0] dprio_address_1;
reg [1:0] dprio_byteen_1;
reg [4:0] usr_cnt_sel_1;
localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10;
always @(posedge clk)
begin
if (reset)
begin
current_read_state <= READ_IDLE;
slave_address_int_q <= 0;
slave_readdata_q <= 0;
end
else
begin
current_read_state <= next_read_state;
slave_address_int_q <= slave_address_int_d;
slave_readdata_q <= slave_readdata_d;
end
end
always @(*)
begin
dprio_read_1 = 0;
dprio_address_1 = 0;
dprio_byteen_1 = 0;
slave_address_int_d = 0;
slave_readdata_d = 0;
status_read = 0;
usr_cnt_sel_1 = 0;
case(current_read_state)
READ_IDLE:
begin
slave_address_int_d = 0;
next_read_state = READ_IDLE;
if ((current_state != WAIT_ON_LOCK) && slave_read)
begin
slave_address_int_d = slave_address;
if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
begin
next_read_state = READ_WAIT;
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
end
else
begin
case (slave_address)
MODE_REG:
begin
next_read_state = READ_WAIT;
slave_readdata_d = slave_mode;
end
STATUS_REG:
begin
next_read_state = READ_WAIT;
status_read = 1'b1;
slave_readdata_d = status;
end
N_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = N_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
M_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = M_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
BWCTRL_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = BWCTRL_ADDR;
next_read_state = READ_WAIT;
end
CP_CURRENT_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = CP_CURRENT_ADDR;
next_read_state = READ_WAIT;
end
default : next_read_state = READ_IDLE;
endcase
end
end
else
next_read_state = READ_IDLE;
end
READ_WAIT:
begin
next_read_state = READ;
slave_address_int_d = slave_address_int_q;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
endcase
end
READ:
begin
next_read_state = READ_IDLE;
slave_address_int_d = slave_address_int_q;
slave_readdata_d = dprio_readdata;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
BWCTRL_REG:
begin
slave_readdata_d = dprio_readdata[3:0];
end
CP_CURRENT_REG:
begin
slave_readdata_d = dprio_readdata[2:0];
end
endcase
end
default: next_read_state = 2'bxx;
endcase
end
dyn_phase_shift dyn_phase_shift_inst (
.clk(clk),
.reset(reset),
.phase_done(phase_done),
.pll_start_valid(pll_start_valid),
.dps_changed(dps_changed),
.dps_changed_valid(dps_changed_valid),
.dprio_write_done(dprio_write_done),
.usr_num_shifts(usr_num_shifts),
.usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
.usr_up_dn(usr_up_dn),
.locked(locked),
.dps_done(dps_done),
.phase_en(phase_en),
.up_dn(up_dn),
.cnt_sel(cnt_sel));
defparam dyn_phase_shift_inst.device_family = device_family;
assign dprio_clk = clk;
self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
dprio_mux dprio_mux_inst (
.init_dprio_address(init_dprio_address),
.init_dprio_read(init_dprio_read),
.init_dprio_byteen(init_dprio_byteen),
.init_dprio_write(init_dprio_write),
.init_dprio_writedata(init_dprio_writedata),
.init_atpgmode(init_atpgmode),
.init_mdio_dis(init_mdio_dis),
.init_scanen(init_scanen),
.init_ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done),
// Inputs from avmm master
.avmm_dprio_address(avmm_dprio_address | dprio_address_1),
.avmm_dprio_read(avmm_dprio_read | dprio_read_1),
.avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
.avmm_dprio_write(avmm_dprio_write),
.avmm_dprio_writedata(avmm_dprio_writedata),
.avmm_atpgmode(avmm_atpgmode),
.avmm_mdio_dis(avmm_mdio_dis),
.avmm_scanen(avmm_scanen),
// Outputs to fpll
.dprio_address(dprio_address),
.dprio_read(dprio_read),
.dprio_byteen(dprio_byteen),
.dprio_write(dprio_write),
.dprio_writedata(dprio_writedata),
.atpgmode(dprio_atpgmode),
.mdio_dis(dprio_mdio_dis),
.scanen(dprio_scanen),
.ser_shift_load(dprio_ser_shift_load)
);
fpll_dprio_init fpll_dprio_init_inst (
.clk(clk),
.reset_n(~reset),
.locked(locked),
//outputs
.dprio_address(init_dprio_address),
.dprio_read(init_dprio_read),
.dprio_byteen(init_dprio_byteen),
.dprio_write(init_dprio_write),
.dprio_writedata(init_dprio_writedata),
.atpgmode(init_atpgmode),
.mdio_dis(init_mdio_dis),
.scanen(init_scanen),
.ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done));
//address luts, to be reconfigged by the Fitter
//FPLL_1 or 0 address lut
generic_lcell_comb lcell_fpll_0_1 (
.dataa(1'b0),
.combout (fpll_1));
defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_fpll_0_1.dont_touch = "on";
defparam lcell_fpll_0_1.family = device_family;
wire dprio_read_combout;
generic_lcell_comb lcell_dprio_read (
.dataa(fpll_1),
.datab(dprio_read),
.datac(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.combout (dprio_read_combout));
defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_dprio_read.dont_touch = "on";
defparam lcell_dprio_read.family = device_family;
//assign reconfig_to_pll signals
assign reconfig_to_pll[0] = dprio_clk;
assign reconfig_to_pll[1] = ~dprio_init_reset;
assign reconfig_to_pll[2] = dprio_write;
assign reconfig_to_pll[3] = dprio_read_combout;
assign reconfig_to_pll[9:4] = dprio_address;
assign reconfig_to_pll[25:10] = dprio_writedata;
assign reconfig_to_pll[27:26] = dprio_byteen;
assign reconfig_to_pll[28] = dprio_ser_shift_load;
assign reconfig_to_pll[29] = dprio_mdio_dis;
assign reconfig_to_pll[30] = phase_en;
assign reconfig_to_pll[31] = up_dn;
assign reconfig_to_pll[36:32] = cnt_sel;
assign reconfig_to_pll[37] = dprio_scanen;
assign reconfig_to_pll[38] = dprio_atpgmode;
//assign reconfig_to_pll[40:37] = clken;
assign reconfig_to_pll[63:39] = 0;
//assign reconfig_from_pll signals
assign dprio_readdata = reconfig_from_pll [15:0];
assign locked = reconfig_from_pll [16];
assign phase_done = reconfig_from_pll [17];
endmodule
module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0]counter;
reg local_reset;
reg usr_mode_init_wait;
initial
begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk)
begin
if (mgmt_reset)
begin
counter <= 0;
end
else
begin
if (!usr_mode_init_wait)
begin
if (counter == INITIAL_WAIT_VALUE)
begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
end
end
else
begin
if (counter == RESET_COUNTER_VALUE)
local_reset <= 0;
else
counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load ;
endmodule
module fpll_dprio_init (
input clk,
input reset_n,
input locked,
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output reg atpgmode,
output reg mdio_dis,
output reg scanen,
output reg ser_shift_load,
output reg dprio_init_done
);
reg [1:0] rst_n = 2'b00;
reg [6:0] count = 7'd0;
reg init_done_forever;
// Internal versions of control signals
wire int_mdio_dis;
wire int_ser_shift_load;
wire int_dprio_init_done;
wire int_atpgmode/*synthesis keep*/;
wire int_scanen/*synthesis keep*/;
assign dprio_address = count[6] ? 5'b0 : count[5:0] ;
assign dprio_byteen = 2'b11; // always enabled
assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles
assign dprio_read = 1'b0;
assign dprio_writedata = 16'd0;
assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1;
assign int_mdio_dis = count[6] ? ~count[2] : 1'b1;
assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0)
: 1'b1;
assign int_atpgmode = 0;
assign int_scanen = 0;
initial begin
count = 7'd0;
init_done_forever = 0;
mdio_dis = 1'b1;
ser_shift_load = 1'b1;
dprio_init_done = 1'b0;
scanen = 1'b0;
atpgmode = 1'b0;
end
// reset synch.
always @(posedge clk or negedge reset_n)
if(!reset_n) rst_n <= 2'b00;
else rst_n <= {rst_n[0],1'b1};
// counter
always @(posedge clk)
begin
if (!rst_n[1])
init_done_forever <= 1'b0;
else
begin
if (count[6] && &count[1:0])
init_done_forever <= 1'b1;
end
end
always @(posedge clk or negedge rst_n[1])
begin
if(!rst_n[1])
begin
count <= 7'd0;
end
else if(~int_dprio_init_done)
begin
count <= count + 7'd1;
end
else
begin
count <= count;
end
end
// outputs
always @(posedge clk) begin
mdio_dis <= int_mdio_dis;
ser_shift_load <= int_ser_shift_load;
dprio_init_done <= int_dprio_init_done;
atpgmode <= int_atpgmode;
scanen <= int_scanen;
end
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
) (
input wire clk,
input wire reset,
input wire phase_done,
input wire pll_start_valid,
input wire dps_changed,
input wire dprio_write_done,
input wire [15:0] usr_num_shifts,
input wire [4:0] usr_cnt_sel,
input wire usr_up_dn,
input wire locked,
//output
output wire dps_done,
output reg phase_en,
output wire up_dn,
output wire dps_changed_valid,
output wire [4:0] cnt_sel);
reg first_phase_shift_d;
reg first_phase_shift_q;
reg [15:0] phase_en_counter;
reg [3:0] dps_current_state;
reg [3:0] dps_next_state;
localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5;
localparam PHASE_EN_WAIT_COUNTER = 5'd1;
reg [15:0] shifts_done_counter;
reg phase_done_final;
wire gnd /*synthesis keep*/;
//fsm
//always block controlling the state regs
always @(posedge clk)
begin
if (reset)
begin
dps_current_state <= DPS_DONE;
end
else
begin
dps_current_state <= dps_next_state;
end
end
//the combinational part. assigning the next state
//this turns on the phase_done_final signal when phase_done does this:
//_____ ______
// |______|
always @(*)
begin
phase_done_final = 0;
first_phase_shift_d = 0;
phase_en = 0;
dps_next_state = DPS_DONE;
case (dps_current_state)
DPS_START:
begin
phase_en = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
DPS_WAIT_PHASE_EN:
begin
phase_en = 1'b1;
if (first_phase_shift_q)
begin
first_phase_shift_d = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
else
begin
if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
dps_next_state = DPS_WAIT_PHASE_DONE;
else dps_next_state = DPS_WAIT_PHASE_EN;
end
end
DPS_WAIT_PHASE_DONE:
begin
if (!phase_done | !locked)
begin
dps_next_state = DPS_WAIT_PHASE_DONE;
end
else
begin
if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
begin
dps_next_state = DPS_START;
phase_done_final = 1'b1;
end
else
begin
dps_next_state = DPS_DONE;
end
end
end
DPS_DONE:
begin
phase_done_final = 0;
if (dps_changed)
dps_next_state = DPS_CHANGED;
else dps_next_state = DPS_DONE;
end
DPS_CHANGED:
begin
if (pll_start_valid)
dps_next_state = DPS_WAIT_DPRIO_WRITING;
else
dps_next_state = DPS_CHANGED;
end
DPS_WAIT_DPRIO_WRITING:
begin
if (dprio_write_done)
dps_next_state = DPS_START;
else
dps_next_state = DPS_WAIT_DPRIO_WRITING;
end
default: dps_next_state = 4'bxxxx;
endcase
end
always @(posedge clk)
begin
if (dps_current_state == DPS_WAIT_PHASE_DONE)
phase_en_counter <= 0;
else if (dps_current_state == DPS_WAIT_PHASE_EN)
phase_en_counter <= phase_en_counter + 1'b1;
if (reset)
begin
phase_en_counter <= 0;
shifts_done_counter <= 1'b1;
first_phase_shift_q <= 1;
end
else
begin
if (first_phase_shift_d)
first_phase_shift_q <= 0;
if (dps_done)
begin
shifts_done_counter <= 1'b1;
end
else
begin
if (phase_done_final & (dps_next_state!= DPS_DONE))
shifts_done_counter <= shifts_done_counter + 1'b1;
else
shifts_done_counter <= shifts_done_counter;
end
end
end
assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
assign up_dn = usr_up_dn;
assign gnd = 1'b0;
//cnt select luts (5)
generic_lcell_comb lcell_cnt_sel_0 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[0]));
defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_cnt_sel_0.dont_touch = "on";
defparam lcell_cnt_sel_0.family = device_family;
generic_lcell_comb lcell_cnt_sel_1 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[1]));
defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_cnt_sel_1.dont_touch = "on";
defparam lcell_cnt_sel_1.family = device_family;
generic_lcell_comb lcell_cnt_sel_2 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[2]));
defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam lcell_cnt_sel_2.dont_touch = "on";
defparam lcell_cnt_sel_2.family = device_family;
generic_lcell_comb lcell_cnt_sel_3 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[3]));
defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
defparam lcell_cnt_sel_3.dont_touch = "on";
defparam lcell_cnt_sel_3.family = device_family;
generic_lcell_comb lcell_cnt_sel_4 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[4]));
defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
defparam lcell_cnt_sel_4.dont_touch = "on";
defparam lcell_cnt_sel_4.family = device_family;
endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V")
begin
stratixv_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V")
begin
arriav_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V GZ")
begin
arriavgz_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Cyclone V")
begin
cyclonev_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram_csr #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 2,
parameter NUM_WORDS = 4
) (
input csr_clk,
input csr_ena,
input csr_din,
input ram_clk,
input wren,
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] wraddress,
input [(ADDR_WIDTH-1):0] rdaddress,
output reg [(DATA_WIDTH-1):0] q,
output reg csr_dout
);
localparam integer DATA_COUNT = DATA_WIDTH*NUM_WORDS;
reg [DATA_COUNT-1:0] all_data;
wire [DATA_COUNT-1:0] load_data;
wire [DATA_WIDTH-1:0] row_data [NUM_WORDS-1:0];
wire int_clk;
assign int_clk = (~csr_ena)? csr_clk : ram_clk;
always @(posedge int_clk)
begin
if (~csr_ena)
all_data <= {all_data[DATA_COUNT-2:0], csr_din};
else if (wren)
all_data <= load_data;
else
all_data <= all_data;
q <= row_data[rdaddress];
end
always @(negedge csr_clk)
begin
csr_dout <= all_data[DATA_COUNT-1];
end
generate
genvar i;
for (i = 0; i < (NUM_WORDS); i = i + 1)
begin: row_assign
assign row_data[i] = all_data[(DATA_WIDTH*(i+1)-1) : (DATA_WIDTH*i)];
end
endgenerate
generate
genvar j,k;
for (j = 0; j < (NUM_WORDS); j = j + 1)
begin: row
for (k = 0; k < (DATA_WIDTH); k = k + 1)
begin: column
assign load_data[(DATA_WIDTH*j)+k] = (wraddress == j)? data[k] : all_data[(DATA_WIDTH*j)+k];
end
end
endgenerate
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting write master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted when enough data has been buffered and then the done bit
will be asserted.
To use this master you must simply drive the control signals into this block,
and also write the data to the exposed write FIFO. To read from the exposed FIFO
use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
You should not attempt to write data to the exposed FIFO if it is full.
*/
// altera message_off 10230
module burst_write_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
// user logic inputs and outputs
user_write_buffer,
user_buffer_data,
user_buffer_full,
// master inputs and outputs
master_address,
master_write,
master_byteenable,
master_writedata,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32; // must be at least twice MAXBURSTCOUNT in order to be efficient
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
input [ADDRESSWIDTH-1:0] control_write_base;
input [ADDRESSWIDTH-1:0] control_write_length;
input control_go;
output wire control_done;
// user logic inputs and outputs
input user_write_buffer;
input [DATAWIDTH-1:0] user_buffer_data;
output wire user_buffer_full;
// master inputs and outputs
input master_waitrequest;
output reg [ADDRESSWIDTH-1:0] master_address;
output wire master_write;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [DATAWIDTH-1:0] master_writedata;
output reg [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] length;
wire final_short_burst_enable; // when the length is less than MAXBURSTCOUNT * # of bytes per word (BYTEENABLEWIDTH) (i.e. end of the transfer)
wire final_short_burst_ready; // when there is enough data in the FIFO for the final burst
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address; // represents the word offset within the burst boundary
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire first_short_burst_enable; // when the transfer doesn't start on a burst boundary
wire first_short_burst_ready; // when there is enough data in the FIFO to get the master back into burst alignment
wire full_burst_ready; // when there is enough data in the FIFO for a full burst
wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
wire burst_begin; // used to register the registers 'burst_address' and 'burst_count_d1' as well as drive the master_address and burst_count muxes
wire read_fifo;
wire [FIFODEPTH_LOG2-1:0] fifo_used; // going to combined used with the full bit
wire [BURSTCOUNTWIDTH-1:0] burst_count; // watermark of the FIFO, it has a latency of 2 cycles
reg [BURSTCOUNTWIDTH-1:0] burst_counter;
reg first_transfer; // need to keep track of the first burst so that we don't incorrectly increment the address
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// set when control_go fires, and reset once the first burst starts
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_transfer <= 0;
end
else
begin
if (control_go == 1)
begin
first_transfer <= 1;
end
else if (burst_begin == 1)
begin
first_transfer <= 0;
end
end
end
// master address (held constant during burst)
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
master_address <= 0;
end
else
begin
if (control_go == 1)
begin
master_address <= control_write_base;
end
else if ((first_transfer == 0) & (burst_begin == 1) & (control_fixed_location_d1 == 0))
begin
master_address <= master_address + (master_burstcount * BYTEENABLEWIDTH); // we don't want address + BYTEENABLEWIDTH for the first access
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if (control_go == 1)
begin
length <= control_write_length;
end
else if (increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// register the master burstcount (held constant during burst)
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
master_burstcount <= 0;
end
else
begin
if (burst_begin == 1)
begin
master_burstcount <= burst_count;
end
end
end
// burst counter. This is set to the burst count being posted then counts down when each word
// of data goes out. If it reaches 0 (i.e. not reloaded after 1) then the master stalls due to
// a lack of data to post a new burst.
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
burst_counter <= 0;
end
else
begin
if (control_go == 1)
begin
burst_counter <= 0;
end
else if (burst_begin == 1)
begin
burst_counter <= burst_count;
end
else if (increment_address == 1) // decrements each write, burst_counter will only hit 0 if burst begin doesn't fire on the next cycle
begin
burst_counter <= burst_counter - 1;
end
end
end
// burst boundaries are on the master "width * maximum burst count". The burst boundary word address will be used to determine how far off the boundary the transfer starts from.
assign burst_boundary_word_address = ((master_address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
// first short burst enable will only be active on the first transfer (if applicable). It will either post the amount of words remaining to reach the end of the burst
// boundary or post the remainder of the transfer whichever is shorter. If the transfer is very short and not aligned on a burst boundary then the same logic as the final short transfer is used
assign first_short_burst_enable = (burst_boundary_word_address != 0) & (first_transfer == 1);
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : final_short_burst_count);
assign first_short_burst_ready = (fifo_used > first_short_burst_count) | ((fifo_used == first_short_burst_count) & (burst_counter == 0));
// when there isn't enough data for a full burst at the end of the transfer a short burst is sent out instead
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign final_short_burst_count = (length/BYTEENABLEWIDTH);
assign final_short_burst_ready = (fifo_used > final_short_burst_count) | ((fifo_used == final_short_burst_count) & (burst_counter == 0)); // this will add a one cycle stall between bursts, since fifo_used has a cycle of latency, this only affects the last burst
// since the fifo has a latency of 1 we need to make sure we don't under flow
assign full_burst_ready = (fifo_used > MAXBURSTCOUNT) | ((fifo_used == MAXBURSTCOUNT) & (burst_counter == 0)); // when fifo used watermark equals the burst count the statemachine must stall for one cycle, this will make sure that when a burst begins there really is enough data present in the FIFO
assign master_byteenable = -1; // all ones, always performing word size accesses
assign control_done = (length == 0);
assign master_write = (control_done == 0) & (burst_counter != 0); // burst_counter = 0 means the transfer is done, or not enough data in the fifo for a new burst
// fifo controls and the burst_begin responsible for timing most of the circuit, burst_begin starts the writing statemachine
assign burst_begin = (((first_short_burst_enable == 1) & (first_short_burst_ready == 1))
| ((final_short_burst_enable == 1) & (final_short_burst_ready == 1))
| (full_burst_ready == 1))
& (control_done == 0) // since the FIFO can have data before the master starts we need to disable this bit from firing when length = 0
& ((burst_counter == 0) | ((burst_counter == 1) & (master_waitrequest == 0) & (length > (MAXBURSTCOUNT * BYTEENABLEWIDTH)))); // need to make a short final burst doesn't start right after a full burst completes.
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // alignment correction gets priority, if the transfer is short and unaligned this will cover both
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (master_write == 1) & (master_waitrequest == 0); // writing is occuring without wait states
assign read_fifo = increment_address;
// write data feed by user logic
scfifo the_user_to_master_fifo (
.aclr (reset),
.usedw (fifo_used),
.clock (clk),
.data (user_buffer_data),
.almost_full (user_buffer_full),
.q (master_writedata),
.rdreq (read_fifo),
.wrreq (user_write_buffer)
);
defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
defparam the_user_to_master_fifo.lpm_showahead = "ON";
defparam the_user_to_master_fifo.almost_full_value = (FIFODEPTH - 2);
defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_user_to_master_fifo.add_ram_output_register = "OFF"; // makes timing the burst begin single simplier
defparam the_user_to_master_fifo.underflow_checking = "OFF";
defparam the_user_to_master_fifo.overflow_checking = "OFF";
endmodule
|
//-----------------------------------------------------------------
// usb to axi bridge
// v0.1
// ultra-embedded.com
// copyright 2019
//
// email: admin@ultra-embedded.com
//
// license: lgpl
//-----------------------------------------------------------------
//
// this source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// this source file is free software; you can redistribute it
// and/or modify it under the terms of the gnu lesser general
// public license as published by the free software foundation;
// either version 2.1 of the license, or (at your option) any
// later version.
//
// this source is distributed in the hope that it will be
// useful, but without any warranty; without even the implied
// warranty of merchantability or fitness for a particular
// purpose. see the gnu lesser general public license for more
// details.
//
// you should have received a copy of the gnu lesser general
// public license along with this source; if not, write to the
// free software foundation, inc., 59 temple place, suite 330,
// boston, ma 02111-1307 usa
//-----------------------------------------------------------------
module usb_bridge
(
// inputs
input clk_i
,input rst_i
,input [ 7:0] utmi_data_in_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [ 1:0] utmi_linestate_i
,input mem_awready_i
,input mem_wready_i
,input mem_bvalid_i
,input [ 1:0] mem_bresp_i
,input [ 3:0] mem_bid_i
,input mem_arready_i
,input mem_rvalid_i
,input [ 31:0] mem_rdata_i
,input [ 1:0] mem_rresp_i
,input [ 3:0] mem_rid_i
,input mem_rlast_i
,input [ 31:0] gpio_inputs_i
// outputs
,output [ 7:0] utmi_data_out_o
,output utmi_txvalid_o
,output [ 1:0] utmi_op_mode_o
,output [ 1:0] utmi_xcvrselect_o
,output utmi_termselect_o
,output utmi_dppulldown_o
,output utmi_dmpulldown_o
,output mem_awvalid_o
,output [ 31:0] mem_awaddr_o
,output [ 3:0] mem_awid_o
,output [ 7:0] mem_awlen_o
,output [ 1:0] mem_awburst_o
,output mem_wvalid_o
,output [ 31:0] mem_wdata_o
,output [ 3:0] mem_wstrb_o
,output mem_wlast_o
,output mem_bready_o
,output mem_arvalid_o
,output [ 31:0] mem_araddr_o
,output [ 3:0] mem_arid_o
,output [ 7:0] mem_arlen_o
,output [ 1:0] mem_arburst_o
,output mem_rready_o
,output [ 31:0] gpio_outputs_o
);
//-----------------------------------------------------------------
// config
//-----------------------------------------------------------------
parameter clk_freq = 48000000;
parameter gpio_address = 32'hf0000000 + 32'h0;
parameter sts_address = 32'hf0000000 + 32'h4;
parameter axi_id = 4'd0;
//-----------------------------------------------------------------
// defines
//-----------------------------------------------------------------
localparam req_write = 8'h10;
localparam req_read = 8'h11;
`define state_w 4
`define state_r 3:0
localparam state_idle = 4'd0;
localparam state_len = 4'd2;
localparam state_addr0 = 4'd3;
localparam state_addr1 = 4'd4;
localparam state_addr2 = 4'd5;
localparam state_addr3 = 4'd6;
localparam state_write = 4'd7;
localparam state_read = 4'd8;
localparam state_data0 = 4'd9;
localparam state_data1 = 4'd10;
localparam state_data2 = 4'd11;
localparam state_data3 = 4'd12;
//-----------------------------------------------------------------
// wires / regs
//-----------------------------------------------------------------
wire uart_wr_w;
wire [7:0] uart_wr_data_w;
wire uart_tx_pop_w;
wire uart_rd_w;
wire [7:0] uart_rd_data_w;
wire uart_rd_valid_w;
wire uart_rx_error_w;
wire tx_valid_w;
wire [7:0] tx_data_w;
wire tx_accept_w;
wire read_skip_w;
wire rx_valid_w;
wire [7:0] rx_data_w;
wire rx_accept_w;
reg [31:0] mem_addr_q;
reg mem_busy_q;
reg mem_wr_q;
reg [7:0] len_q;
// byte index
reg [1:0] data_idx_q;
// word storage
reg [31:0] data_q;
wire magic_addr_w = (mem_addr_q == gpio_address || mem_addr_q == sts_address);
//-----------------------------------------------------------------
// usb core
//-----------------------------------------------------------------
usb_cdc_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.enable_i(1'b1),
.utmi_data_in_i(utmi_data_in_i),
.utmi_txready_i(utmi_txready_i),
.utmi_rxvalid_i(utmi_rxvalid_i),
.utmi_rxactive_i(utmi_rxactive_i),
.utmi_rxerror_i(utmi_rxerror_i),
.utmi_linestate_i(utmi_linestate_i),
.utmi_data_out_o(utmi_data_out_o),
.utmi_txvalid_o(utmi_txvalid_o),
.utmi_op_mode_o(utmi_op_mode_o),
.utmi_xcvrselect_o(utmi_xcvrselect_o),
.utmi_termselect_o(utmi_termselect_o),
.utmi_dppulldown_o(utmi_dppulldown_o),
.utmi_dmpulldown_o(utmi_dmpulldown_o),
// device -> host
.inport_valid_i(uart_wr_w),
.inport_data_i(uart_wr_data_w),
.inport_accept_o(uart_tx_pop_w),
// host -> device
.outport_valid_o(uart_rd_valid_w),
.outport_data_o(uart_rd_data_w),
.outport_accept_i(uart_rd_w)
);
//-----------------------------------------------------------------
// output fifo
//-----------------------------------------------------------------
usb_bridge_fifo
#(
.width(8),
.depth(64),
.addr_w(6)
)
u_fifo_tx
(
.clk_i(clk_i),
.rst_i(rst_i),
// in
.push_i(tx_valid_w),
.data_in_i(tx_data_w),
.accept_o(tx_accept_w),
// out
.pop_i(uart_tx_pop_w),
.data_out_o(uart_wr_data_w),
.valid_o(uart_wr_w)
);
//-----------------------------------------------------------------
// input fifo
//-----------------------------------------------------------------
usb_bridge_fifo
#(
.width(8),
.depth(64),
.addr_w(6)
)
u_fifo_rx
(
.clk_i(clk_i),
.rst_i(rst_i),
// in
.push_i(uart_rd_valid_w),
.data_in_i(uart_rd_data_w),
.accept_o(uart_rd_w),
// out
.pop_i(rx_accept_w),
.data_out_o(rx_data_w),
.valid_o(rx_valid_w)
);
//-----------------------------------------------------------------
// states
//-----------------------------------------------------------------
reg [`state_r] state_q;
reg [`state_r] next_state_r;
always @ *
begin
next_state_r = state_q;
case (next_state_r)
//-------------------------------------------------------------
// idle:
//-------------------------------------------------------------
state_idle:
begin
if (rx_valid_w)
begin
case (rx_data_w)
req_write,
req_read:
next_state_r = state_len;
default:
;
endcase
end
end
//-----------------------------------------
// state_len
//-----------------------------------------
state_len :
begin
if (rx_valid_w)
next_state_r = state_addr0;
end
//-----------------------------------------
// state_addr
//-----------------------------------------
state_addr0 : if (rx_valid_w) next_state_r = state_addr1;
state_addr1 : if (rx_valid_w) next_state_r = state_addr2;
state_addr2 : if (rx_valid_w) next_state_r = state_addr3;
state_addr3 :
begin
if (rx_valid_w && mem_wr_q)
next_state_r = state_write;
else if (rx_valid_w)
next_state_r = state_read;
end
//-----------------------------------------
// state_write
//-----------------------------------------
state_write :
begin
if (len_q == 8'b0 && (mem_bvalid_i || magic_addr_w))
next_state_r = state_idle;
else
next_state_r = state_write;
end
//-----------------------------------------
// state_read
//-----------------------------------------
state_read :
begin
// data ready
if (mem_rvalid_i || magic_addr_w)
next_state_r = state_data0;
end
//-----------------------------------------
// state_data
//-----------------------------------------
state_data0 :
begin
if (read_skip_w)
next_state_r = state_data1;
else if (tx_accept_w && (len_q == 8'b0))
next_state_r = state_idle;
else if (tx_accept_w)
next_state_r = state_data1;
end
state_data1 :
begin
if (read_skip_w)
next_state_r = state_data2;
else if (tx_accept_w && (len_q == 8'b0))
next_state_r = state_idle;
else if (tx_accept_w)
next_state_r = state_data2;
end
state_data2 :
begin
if (read_skip_w)
next_state_r = state_data3;
else if (tx_accept_w && (len_q == 8'b0))
next_state_r = state_idle;
else if (tx_accept_w)
next_state_r = state_data3;
end
state_data3 :
begin
if (tx_accept_w && (len_q != 8'b0))
next_state_r = state_read;
else if (tx_accept_w)
next_state_r = state_idle;
end
default:
;
endcase
end
// state storage
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= state_idle;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// rd/wr to and from uart
//-----------------------------------------------------------------
// write to uart tx buffer in the following states
assign tx_valid_w = ((state_q == state_data0) |
(state_q == state_data1) |
(state_q == state_data2) |
(state_q == state_data3)) && !read_skip_w;
// accept data in the following states
assign rx_accept_w = (state_q == state_idle) |
(state_q == state_len) |
(state_q == state_addr0) |
(state_q == state_addr1) |
(state_q == state_addr2) |
(state_q == state_addr3) |
(state_q == state_write && !mem_busy_q);
//-----------------------------------------------------------------
// capture length
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
len_q <= 8'd0;
else if (state_q == state_len && rx_valid_w)
len_q[7:0] <= rx_data_w;
else if (state_q == state_write && rx_valid_w && !mem_busy_q)
len_q <= len_q - 8'd1;
else if (state_q == state_read && ((mem_busy_q && mem_rvalid_i) || magic_addr_w))
len_q <= len_q - 8'd1;
else if (((state_q == state_data0) || (state_q == state_data1) || (state_q == state_data2)) && (tx_accept_w && !read_skip_w))
len_q <= len_q - 8'd1;
//-----------------------------------------------------------------
// capture addr
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_addr_q <= 'd0;
else if (state_q == state_addr0 && rx_valid_w)
mem_addr_q[31:24] <= rx_data_w;
else if (state_q == state_addr1 && rx_valid_w)
mem_addr_q[23:16] <= rx_data_w;
else if (state_q == state_addr2 && rx_valid_w)
mem_addr_q[15:8] <= rx_data_w;
else if (state_q == state_addr3 && rx_valid_w)
mem_addr_q[7:0] <= rx_data_w;
// address increment on every access issued
else if (state_q == state_write && (mem_busy_q && mem_bvalid_i))
mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
else if (state_q == state_read && (mem_busy_q && mem_rvalid_i))
mem_addr_q <= {mem_addr_q[31:2], 2'b0} + 'd4;
//-----------------------------------------------------------------
// data index
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_idx_q <= 2'b0;
else if (state_q == state_addr3)
data_idx_q <= rx_data_w[1:0];
else if (state_q == state_write && rx_valid_w && !mem_busy_q)
data_idx_q <= data_idx_q + 2'd1;
else if (((state_q == state_data0) || (state_q == state_data1) || (state_q == state_data2)) && tx_accept_w && (data_idx_q != 2'b0))
data_idx_q <= data_idx_q - 2'd1;
assign read_skip_w = (data_idx_q != 2'b0);
//-----------------------------------------------------------------
// data sample
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_q <= 32'b0;
// write to memory
else if (state_q == state_write && rx_valid_w && !mem_busy_q)
begin
case (data_idx_q)
2'd0: data_q[7:0] <= rx_data_w;
2'd1: data_q[15:8] <= rx_data_w;
2'd2: data_q[23:16] <= rx_data_w;
2'd3: data_q[31:24] <= rx_data_w;
endcase
end
// read from gpio input?
else if (state_q == state_read && mem_addr_q == gpio_address)
begin
data_q <= {{(32-32){1'b0}}, gpio_inputs_i};
end
// read from status register?
else if (state_q == state_read && mem_addr_q == sts_address)
data_q <= {16'hcafe, 15'd0, mem_busy_q};
// read from memory
else if (state_q == state_read && mem_rvalid_i)
data_q <= mem_rdata_i;
// shift data out (read response -> uart)
else if (((state_q == state_data0) || (state_q == state_data1) || (state_q == state_data2)) && (tx_accept_w || read_skip_w))
data_q <= {8'b0, data_q[31:8]};
assign tx_data_w = data_q[7:0];
assign mem_wdata_o = data_q;
//-----------------------------------------------------------------
// axi: write request
//-----------------------------------------------------------------
reg mem_awvalid_q;
reg mem_awvalid_r;
reg mem_wvalid_q;
reg mem_wvalid_r;
always @ *
begin
mem_awvalid_r = 1'b0;
mem_wvalid_r = 1'b0;
// hold
if (mem_awvalid_o && !mem_awready_i)
mem_awvalid_r = mem_awvalid_q;
else if (mem_awvalid_o)
mem_awvalid_r = 1'b0;
// every 4th byte, issue bus access
else if (state_q == state_write && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
mem_awvalid_r = !magic_addr_w;
// hold
if (mem_wvalid_o && !mem_wready_i)
mem_wvalid_r = mem_wvalid_q;
else if (mem_wvalid_o)
mem_wvalid_r = 1'b0;
// every 4th byte, issue bus access
else if (state_q == state_write && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
mem_wvalid_r = !magic_addr_w;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_awvalid_q <= 1'b0;
mem_wvalid_q <= 1'b0;
end
else
begin
mem_awvalid_q <= mem_awvalid_r;
mem_wvalid_q <= mem_wvalid_r;
end
assign mem_awvalid_o = mem_awvalid_q;
assign mem_wvalid_o = mem_wvalid_q;
assign mem_awaddr_o = {mem_addr_q[31:2], 2'b0};
assign mem_awid_o = axi_id;
assign mem_awlen_o = 8'b0;
assign mem_awburst_o = 2'b01;
assign mem_wlast_o = 1'b1;
assign mem_bready_o = 1'b1;
//-----------------------------------------------------------------
// axi: read request
//-----------------------------------------------------------------
reg mem_arvalid_q;
reg mem_arvalid_r;
always @ *
begin
mem_arvalid_r = 1'b0;
// hold
if (mem_arvalid_o && !mem_arready_i)
mem_arvalid_r = mem_arvalid_q;
else if (mem_arvalid_o)
mem_arvalid_r = 1'b0;
else if (state_q == state_read && !mem_busy_q)
mem_arvalid_r = !magic_addr_w;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_arvalid_q <= 1'b0;
else
mem_arvalid_q <= mem_arvalid_r;
assign mem_arvalid_o = mem_arvalid_q;
assign mem_araddr_o = {mem_addr_q[31:2], 2'b0};
assign mem_arid_o = axi_id;
assign mem_arlen_o = 8'b0;
assign mem_arburst_o = 2'b01;
assign mem_rready_o = 1'b1;
//-----------------------------------------------------------------
// write mask
//-----------------------------------------------------------------
reg [3:0] mem_sel_q;
reg [3:0] mem_sel_r;
always @ *
begin
mem_sel_r = 4'b1111;
case (data_idx_q)
2'd0: mem_sel_r = 4'b0001;
2'd1: mem_sel_r = 4'b0011;
2'd2: mem_sel_r = 4'b0111;
2'd3: mem_sel_r = 4'b1111;
endcase
case (mem_addr_q[1:0])
2'd0: mem_sel_r = mem_sel_r & 4'b1111;
2'd1: mem_sel_r = mem_sel_r & 4'b1110;
2'd2: mem_sel_r = mem_sel_r & 4'b1100;
2'd3: mem_sel_r = mem_sel_r & 4'b1000;
endcase
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_sel_q <= 4'b0;
// idle - reset for read requests
else if (state_q == state_idle)
mem_sel_q <= 4'b1111;
// every 4th byte, issue bus access
else if (state_q == state_write && rx_valid_w && (data_idx_q == 2'd3 || len_q == 8'd1))
mem_sel_q <= mem_sel_r;
assign mem_wstrb_o = mem_sel_q;
//-----------------------------------------------------------------
// write enable
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_wr_q <= 1'b0;
else if (state_q == state_idle && rx_valid_w)
mem_wr_q <= (rx_data_w == req_write);
//-----------------------------------------------------------------
// access in progress
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i == 1'b1)
mem_busy_q <= 1'b0;
else if (mem_arvalid_o || mem_awvalid_o)
mem_busy_q <= 1'b1;
else if (mem_bvalid_i || mem_rvalid_i)
mem_busy_q <= 1'b0;
//-----------------------------------------------------------------
// gpio outputs
//-----------------------------------------------------------------
reg gpio_wr_q;
reg [31:0] gpio_output_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
gpio_wr_q <= 1'b0;
else if (mem_addr_q == gpio_address && state_q == state_write && rx_valid_w && (data_idx_q == 2'd3 || len_q == 1))
gpio_wr_q <= 1'b1;
else
gpio_wr_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
gpio_output_q <= 32'h0;
else if (gpio_wr_q)
gpio_output_q <= data_q[31:0];
assign gpio_outputs_o = gpio_output_q;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [CFG_LOCAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr_combi;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr_combi;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr_combi;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr_combi;
reg ecc_read_combi;
reg ecc_write_combi;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size_combi;
reg ecc_autopch_combi;
reg ecc_multicast_combi;
reg ecc_priority_combi;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid_combi;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_int_combi;
reg errcmd_ready_combi;
reg partial_combi;
reg correct_combi;
reg partial_opr_combi;
reg ecc_int;
reg ecc_int_r;
reg errcmd_ready;
reg partial;
reg correct;
reg partial_opr;
wire mux_busy;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_0;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_1;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_2;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_3;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg proc_busy_sig;
reg proc_ecc_busy_sig;
reg proc_load_sig;
reg proc_load_dataid_sig;
reg proc_write_sig;
reg proc_read_sig;
reg [CFG_INT_SIZE_WIDTH-1:0] proc_size_sig;
reg [CFG_LOCAL_ID_WIDTH-1:0] proc_localid_sig;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
// === merging signals
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
reg [CFG_INT_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [CFG_INT_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last2_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last2_col_addr;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_empty;
wire queue_full;
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//======================= TBP info ===========================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
if (tbp_load[p])
begin
read [p] = cmd_gen_read;
write [p] = cmd_gen_write;
chipsel[p] = cmd_gen_chipsel;
bank [p] = cmd_gen_bank;
row [p] = cmd_gen_row;
col [p] = cmd_gen_col;
end
else
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================= Address Remapping ===========================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//===================== end of address remapping =========================
//======================= burst splitting logic ===========================
assign cmd_gen_full = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full & cmd_valid; // Copy current input command info into a register
assign require_gen = (cmd_size > native_size | unaligned_burst + cmd_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = cfg_burst_length / CFG_DWIDTH_RATIO; // 1 for bl2 FR, 2 for bl8 HR, ...
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size*2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered <= 0;
end
else
begin
if (copy && require_gen)
begin
registered <= 1;
end
else
begin
registered <= 0;
end
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size*2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((unaligned_burst + cmd_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
split_size = cmd_size;
end
else
begin
split_size = native_size - unaligned_burst;
end
end
else
begin
if (decrmntd_size > native_size - 1)
begin
split_size = native_size;
end
else
begin
split_size = decrmntd_size;
end
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
split_read = cmd_read & cmd_valid & ~registered;
split_write = cmd_write & cmd_valid & ~registered;
split_autopch = cmd_autoprecharge;
split_multicast = cmd_multicast;
split_priority = cmd_priority;
split_localid = cmd_id;
split_cs_addr = int_cs_addr;
split_bank_addr = int_bank_addr;
split_row_addr = int_row_addr;
split_col_addr = int_col_addr;
end
else // generating cmd so process buffer content
begin
split_read = buf_read_req;
split_write = buf_write_req;
split_autopch = buf_autopch_req;
split_multicast = buf_multicast;
split_priority = buf_priority;
split_localid = buf_localid;
split_cs_addr = incrmntd_cs_addr;
split_bank_addr = incrmntd_bank_addr;
split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1],1'b0};
end
else if (cfg_burst_length == 4)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2],2'b00};
end
else if (cfg_burst_length == 8)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3],3'b000};
end
else // if (cfg_burst_length == 16)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4],4'b0000};
end
end
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read;
buf_write_req <= cmd_write;
buf_autopch_req <= cmd_autoprecharge;
buf_multicast <= cmd_multicast;
buf_priority <= cmd_priority;
buf_localid <= cmd_id;
end
end
end
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size + unaligned_burst;
end
else if (!registered && buf_size > native_size && ~mux_busy)
begin
buf_size <= buf_size - native_size;
end
end
end
always @(*)
begin
decrmntd_size = buf_size - native_size;
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (generating && ~mux_busy))
if ((cfg_burst_length == 16 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
if (cfg_burst_length == 16)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] <= 0;
else if (cfg_burst_length == 8)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] <= 0;
else if (cfg_burst_length == 4)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] <= 0;
else // if (cfg_burst_length == 2)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] <= 0;
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
begin
buf_cs_addr <= 0;
if (buf_row_addr == max_row_from_csr)
buf_row_addr <= 0;
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
buf_col_addr <= buf_col_addr + cfg_burst_length;
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
//======================= end of burst splitting logic ===========================
//====================== ecc mux start ========================
// ECC process info
always @ (*)
begin
ecc_int_combi = ecc_int;
correct_combi = correct;
partial_combi = partial;
errcmd_ready_combi = errcmd_ready;
ecc_dataid_combi = ecc_dataid;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert partial after ECC write was sent to TBP
begin
partial_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (correct)
begin
errcmd_ready_combi = 1'b0;
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert correct after ECC write was sent to TBP
begin
correct_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // if there is a auto correction request
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b1;
partial_combi = 1'b0;
errcmd_ready_combi = 1'b1;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // if there is a write request in no-DM or ECC case
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b0;
partial_combi = 1'b1;
ecc_dataid_combi = wdatap_free_id_dataid;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int <= 0;
correct <= 0;
partial <= 0;
errcmd_ready <= 0;
ecc_dataid <= 0;
end
else
begin
ecc_int <= ecc_int_combi;
correct <= correct_combi;
partial <= partial_combi;
errcmd_ready <= errcmd_ready_combi;
ecc_dataid <= ecc_dataid_combi;
end
end
// Buffer for ECC command information
always @ (*)
begin
if (partial || correct)
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
else if (cfg_enable_ecc && errcmd_valid) // take in error command info
begin
ecc_cs_addr_combi = errcmd_chipsel;
ecc_bank_addr_combi = errcmd_bank;
ecc_row_addr_combi = errcmd_row;
ecc_col_addr_combi = errcmd_column;
ecc_size_combi = errcmd_size;
ecc_autopch_combi = 1'b0;
ecc_multicast_combi = 1'b0;
ecc_localid_combi = errcmd_localid;
ecc_priority_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // take in command info from split logic
begin
ecc_cs_addr_combi = split_cs_addr;
ecc_bank_addr_combi = split_bank_addr;
ecc_row_addr_combi = split_row_addr;
ecc_col_addr_combi = split_col_addr;
ecc_size_combi = split_size;
ecc_autopch_combi = split_autopch;
ecc_multicast_combi = split_multicast;
ecc_localid_combi = split_localid;
ecc_priority_combi = split_priority;
end
else
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
ecc_cs_addr <= ecc_cs_addr_combi;
ecc_bank_addr <= ecc_bank_addr_combi;
ecc_row_addr <= ecc_row_addr_combi;
ecc_col_addr <= ecc_col_addr_combi;
ecc_size <= ecc_size_combi;
ecc_autopch <= ecc_autopch_combi;
ecc_multicast <= ecc_multicast_combi;
ecc_localid <= ecc_localid_combi;
ecc_priority <= ecc_priority_combi;
end
end
// Logic to determine when to issue ECC read/write request
// based on partial_be info from wdata path
// if partial_be is high, it issues a read-modify-write command
// else issues normal write command
always @ (*)
begin
ecc_read_combi = ecc_read;
ecc_write_combi = ecc_write;
partial_opr_combi = partial_opr;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
partial_opr_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (data_complete[0]) // wait for data_complete from wdata path
begin
if (!data_partial_be) // if not partial_be, issues normal write
begin
ecc_write_combi = 1'b1;
end
else // else issues a RMW's read
begin
ecc_read_combi = 1'b1;
partial_opr_combi = 1'b1;
end
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
begin
ecc_write_combi = 1'b1;
end
else
begin
ecc_write_combi = 1'b0;
end
end
end
else if (correct)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
ecc_write_combi = 1'b1;
else
ecc_write_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // issues a RMW's read when there is a error correction
begin
ecc_read_combi = 1'b1;
ecc_write_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy)
begin
ecc_read_combi = 1'b0;
ecc_write_combi = 1'b0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_read <= 1'b0;
ecc_write <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_read <= ecc_read_combi;
ecc_write <= ecc_write_combi;
partial_opr <= partial_opr_combi;
end
end
// We only need to gate split_read/write in non cmd_gen registered output mode
assign mux_busy = (
queue_full |
errcmd_valid |
(
(cfg_enable_no_dm | cfg_enable_ecc) &
(
ecc_int |
(
!(CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE) &
(
(split_read & ~rdatap_free_id_valid) |
(split_write & ~wdatap_free_id_valid)
)
)
)
)
);
assign muxed_cs_addr = ecc_int ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = ecc_int ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = ecc_int ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = ecc_int ? ecc_col_addr : split_col_addr;
assign muxed_read = ecc_int ? (CFG_CMD_GEN_OUTPUT_REG ? (ecc_read & rdatap_free_id_valid) : ecc_read) : split_read & ~errcmd_valid; // We only need to check for free ID valid in CMD_GEN_OUTPUT_REG mode
assign muxed_write = (cfg_enable_no_dm || cfg_enable_ecc) ? ecc_write : split_write & ~errcmd_valid;
assign muxed_size = ecc_int ? ecc_size : split_size;
assign muxed_autopch = ecc_int ? ecc_autopch : split_autopch;
assign muxed_multicast = ecc_int ? ecc_multicast : split_multicast;
assign muxed_localid = ecc_int ? ecc_localid : split_localid;
assign muxed_priority = ecc_int ? ecc_priority : split_priority;
assign muxed_dataid = ecc_int ? ecc_dataid : rdatap_free_id_dataid;
assign muxed_complete = ecc_int ? 1'b1 : split_read;
assign muxed_correct = ecc_int ? correct : 1'b0;
assign muxed_partial = ecc_int ? partial_opr : 1'b0;
assign muxed_same_chipsel_addr = ecc_int_r ? ecc_same_chipsel_addr : split_same_chipsel_addr;
assign muxed_same_bank_addr = ecc_int_r ? ecc_same_bank_addr : split_same_bank_addr;
assign muxed_same_row_addr_0 = ecc_int_r ? ecc_same_row_addr_0 : split_same_row_addr_0;
assign muxed_same_row_addr_1 = ecc_int_r ? ecc_same_row_addr_1 : split_same_row_addr_1;
assign muxed_same_row_addr_2 = ecc_int_r ? ecc_same_row_addr_2 : split_same_row_addr_2;
assign muxed_same_row_addr_3 = ecc_int_r ? ecc_same_row_addr_3 : split_same_row_addr_3;
assign muxed_same_col_addr = ecc_int_r ? ecc_same_col_addr : split_same_col_addr;
assign muxed_same_read_cmd = ecc_int_r ? ecc_same_read_cmd : split_same_read_cmd;
assign muxed_same_write_cmd = ecc_int_r ? ecc_same_write_cmd : split_same_write_cmd;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int_r <= 1'b0;
end
else
begin
ecc_int_r <= ecc_int;
end
end
// Address comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (split_cs_addr == chipsel[j])
begin
split_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
split_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (split_bank_addr == bank[j])
begin
split_same_bank_addr_combi[j] = 1'b1;
end
else
begin
split_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (split_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_0_combi[j] = 1'b0;
end
if (split_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_1_combi[j] = 1'b0;
end
if (split_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_2_combi[j] = 1'b0;
end
if (split_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (split_col_addr == col[j])
begin
split_same_col_addr_combi[j] = 1'b1;
end
else
begin
split_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (split_read == read[j])
begin
split_same_read_cmd_combi[j] = 1'b1;
end
else
begin
split_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (split_write == write[j])
begin
split_same_write_cmd_combi[j] = 1'b1;
end
else
begin
split_same_write_cmd_combi[j] = 1'b0;
end
end
end
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (ecc_cs_addr == chipsel[j])
begin
ecc_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (ecc_bank_addr == bank[j])
begin
ecc_same_bank_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (ecc_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_0_combi[j] = 1'b0;
end
if (ecc_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_1_combi[j] = 1'b0;
end
if (ecc_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_2_combi[j] = 1'b0;
end
if (ecc_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (ecc_col_addr == col[j])
begin
ecc_same_col_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (ecc_read == read[j])
begin
ecc_same_read_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (ecc_write == write[j])
begin
ecc_same_write_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_write_cmd_combi[j] = 1'b0;
end
end
end
generate
if (CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE)
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
proc_write_sig <= 0;
proc_read_sig <= 0;
proc_size_sig <= 0;
proc_localid_sig <= 0;
proc_load_dataid_sig <= 0;
proc_ecc_busy_sig <= 0;
end
else
begin
if (proc_busy_sig)
begin
// Do nothing, keep old value
end
else
begin
proc_load_dataid_sig <= ~(ecc_int & (ecc_read | ecc_write));
if (ecc_int)
begin
proc_write_sig <= ecc_write & correct;
proc_read_sig <= ecc_read;
proc_size_sig <= ecc_size;
proc_localid_sig <= ecc_localid;
proc_ecc_busy_sig <= (ecc_read & ~rdatap_free_id_valid) | ((ecc_write & correct) & ~wdatap_free_id_valid);
end
else
begin
proc_write_sig <= split_write & ~errcmd_valid;
proc_read_sig <= split_read & ~errcmd_valid;
proc_size_sig <= split_size;
proc_localid_sig <= split_localid;
proc_ecc_busy_sig <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_same_chipsel_addr <= 0;
split_same_bank_addr <= 0;
split_same_row_addr_0 <= 0;
split_same_row_addr_1 <= 0;
split_same_row_addr_2 <= 0;
split_same_row_addr_3 <= 0;
split_same_col_addr <= 0;
split_same_read_cmd <= 0;
split_same_write_cmd <= 0;
ecc_same_chipsel_addr <= 0;
ecc_same_bank_addr <= 0;
ecc_same_row_addr_0 <= 0;
ecc_same_row_addr_1 <= 0;
ecc_same_row_addr_2 <= 0;
ecc_same_row_addr_3 <= 0;
ecc_same_col_addr <= 0;
ecc_same_read_cmd <= 0;
ecc_same_write_cmd <= 0;
end
else
begin
split_same_chipsel_addr <= split_same_chipsel_addr_combi;
split_same_bank_addr <= split_same_bank_addr_combi;
split_same_row_addr_0 <= split_same_row_addr_0_combi;
split_same_row_addr_1 <= split_same_row_addr_1_combi;
split_same_row_addr_2 <= split_same_row_addr_2_combi;
split_same_row_addr_3 <= split_same_row_addr_3_combi;
split_same_col_addr <= split_same_col_addr_combi;
split_same_read_cmd <= split_same_read_cmd_combi;
split_same_write_cmd <= split_same_write_cmd_combi;
ecc_same_chipsel_addr <= ecc_same_chipsel_addr_combi;
ecc_same_bank_addr <= ecc_same_bank_addr_combi;
ecc_same_row_addr_0 <= ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 <= ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 <= ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 <= ecc_same_row_addr_3_combi;
ecc_same_col_addr <= ecc_same_col_addr_combi;
ecc_same_read_cmd <= ecc_same_read_cmd_combi;
ecc_same_write_cmd <= ecc_same_write_cmd_combi;
end
end
end
else
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_ecc_busy_sig = zero;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
proc_load_dataid_sig = ~(ecc_int & (ecc_read | ecc_write));
proc_write_sig = ecc_int ? ecc_write & correct : split_write & ~errcmd_valid;
proc_read_sig = ecc_int ? ecc_read : split_read & ~errcmd_valid;
proc_size_sig = ecc_int ? ecc_size : split_size;
proc_localid_sig = ecc_int ? ecc_localid : split_localid;
end
always @ (*)
begin
split_same_chipsel_addr = split_same_chipsel_addr_combi;
split_same_bank_addr = split_same_bank_addr_combi;
split_same_row_addr_0 = split_same_row_addr_0_combi;
split_same_row_addr_1 = split_same_row_addr_1_combi;
split_same_row_addr_2 = split_same_row_addr_2_combi;
split_same_row_addr_3 = split_same_row_addr_3_combi;
split_same_col_addr = split_same_col_addr_combi;
split_same_read_cmd = split_same_read_cmd_combi;
split_same_write_cmd = split_same_write_cmd_combi;
ecc_same_chipsel_addr = ecc_same_chipsel_addr_combi;
ecc_same_bank_addr = ecc_same_bank_addr_combi;
ecc_same_row_addr_0 = ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 = ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 = ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 = ecc_same_row_addr_3_combi;
ecc_same_col_addr = ecc_same_col_addr_combi;
ecc_same_read_cmd = ecc_same_read_cmd_combi;
ecc_same_write_cmd = ecc_same_write_cmd_combi;
end
end
endgenerate
//====================== ecc mux end ========================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n)
begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last_read_req <= muxed_read;
last_write_req <= muxed_write;
last_multicast <= muxed_multicast;
last_chip_addr <= muxed_cs_addr;
last_bank_addr <= muxed_bank_addr;
last_row_addr <= muxed_row_addr;
last_col_addr <= muxed_col_addr;
last_size <= muxed_size;
end
else if (can_merge)
begin
last_size <= 2;
end
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last2_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
if (write_to_queue)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (write_to_queue) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
// do nothing
end
else if (!queue_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
// Merging logic
assign can_merge = (CFG_ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3]) )
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
generate
if (CFG_ENABLE_QUEUE == 1)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr = muxed_same_row_addr_0 & muxed_same_row_addr_1 & muxed_same_row_addr_2 & muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
// Chipselect address
if (cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_empty = !pipefull[0];
assign queue_full = pipefull[CFG_CTL_QUEUE_DEPTH-1] | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
assign cmd_gen_load = pipefull[0] & ((cfg_enable_no_dm | cfg_enable_ecc) | ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid)));
assign cmd_gen_read = pipe[0][BUFFER_WIDTH-1];
assign cmd_gen_write = pipe[0][BUFFER_WIDTH-2];
assign cmd_gen_multicast = pipe[0][BUFFER_WIDTH-3];
assign cmd_gen_autopch = pipe[0][BUFFER_WIDTH-4];
assign cmd_gen_priority = pipe[0][BUFFER_WIDTH-5];
assign cmd_gen_complete = pipe[0][BUFFER_WIDTH-6];
assign cmd_gen_rmw_correct = pipe[0][BUFFER_WIDTH-7];
assign cmd_gen_rmw_partial = pipe[0][BUFFER_WIDTH-8];
assign cmd_gen_dataid = cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid;
assign cmd_gen_localid = pipe[0][CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_size = pipe[0][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_chipsel = pipe[0][CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row = pipe[0][CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_bank = pipe[0][CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_col = pipe[0][CFG_MEM_IF_COL_WIDTH - 1 : 0];
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
else
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid_mux;
// TBP address and command comparison logic
always @ (*)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr_0 = muxed_same_row_addr_0;
int_same_row_addr_1 = muxed_same_row_addr_1;
int_same_row_addr_2 = muxed_same_row_addr_2;
int_same_row_addr_3 = muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
if (CFG_CMD_GEN_OUTPUT_REG)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr_r;
reg int_ecc_int;
reg int_queue_full_r;
assign int_queue_full = (tbp_full & int_register_valid) | ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid));
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_queue_full_r <= 1'b0;
end
else
begin
int_queue_full_r <= int_queue_full;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 0;
int_cmd_gen_write <= 0;
int_cmd_gen_multicast <= 0;
int_cmd_gen_autopch <= 0;
int_cmd_gen_priority <= 0;
int_cmd_gen_complete <= 0;
int_cmd_gen_rmw_correct <= 0;
int_cmd_gen_rmw_partial <= 0;
int_cmd_gen_dataid <= 0;
int_cmd_gen_localid <= 0;
int_cmd_gen_size <= 0;
int_cmd_gen_chipsel <= 0;
int_cmd_gen_row <= 0;
int_cmd_gen_bank <= 0;
int_cmd_gen_col <= 0;
int_ecc_int <= 0;
end
else
begin
if (fetch)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 1'b0;
int_cmd_gen_write <= 1'b0;
end
if (!int_queue_full)
begin
if (muxed_read || muxed_write)
begin
int_register_valid <= 1'b1;
end
int_cmd_gen_read <= muxed_read;
int_cmd_gen_write <= muxed_write;
int_cmd_gen_multicast <= muxed_multicast;
int_cmd_gen_autopch <= muxed_autopch;
int_cmd_gen_priority <= muxed_priority;
int_cmd_gen_complete <= muxed_complete;
int_cmd_gen_rmw_correct <= muxed_correct;
int_cmd_gen_rmw_partial <= muxed_partial;
int_cmd_gen_dataid <= muxed_dataid;
int_cmd_gen_localid <= muxed_localid;
int_cmd_gen_size <= muxed_size;
int_cmd_gen_chipsel <= muxed_cs_addr;
int_cmd_gen_row <= muxed_row_addr;
int_cmd_gen_bank <= muxed_bank_addr;
int_cmd_gen_col <= muxed_col_addr;
int_ecc_int <= ecc_int;
end
end
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_ecc_int ? int_cmd_gen_dataid : rdatap_free_id_dataid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_same_chipsel_addr_r <= 0;
int_same_bank_addr_r <= 0;
int_same_row_addr_0_r <= 0;
int_same_row_addr_1_r <= 0;
int_same_row_addr_2_r <= 0;
int_same_row_addr_3_r <= 0;
int_same_col_addr_r <= 0;
int_same_read_cmd_r <= 0;
int_same_write_cmd_r <= 0;
int_same_shadow_chipsel_addr_r <= 0;
int_same_shadow_bank_addr_r <= 0;
int_same_shadow_row_addr_r <= 0;
end
else
begin
if (int_queue_full & !int_queue_full_r) // positive edge detector
begin
int_same_chipsel_addr_r <= int_same_chipsel_addr;
int_same_bank_addr_r <= int_same_bank_addr;
int_same_row_addr_0_r <= int_same_row_addr_0;
int_same_row_addr_1_r <= int_same_row_addr_1;
int_same_row_addr_2_r <= int_same_row_addr_2;
int_same_row_addr_3_r <= int_same_row_addr_3;
int_same_col_addr_r <= int_same_col_addr;
int_same_read_cmd_r <= int_same_read_cmd;
int_same_write_cmd_r <= int_same_write_cmd;
end
int_same_shadow_chipsel_addr_r <= int_same_shadow_chipsel_addr;
int_same_shadow_bank_addr_r <= int_same_shadow_bank_addr;
int_same_shadow_row_addr_r <= int_same_shadow_row_addr;
end
end
always @ (*)
begin
if (!int_queue_full_r)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
end
else
begin
same_chipsel_addr = int_same_chipsel_addr_r;
same_bank_addr = int_same_bank_addr_r;
same_row_addr = int_same_row_addr_0_r & int_same_row_addr_1_r & int_same_row_addr_2_r & int_same_row_addr_3_r;
same_col_addr = int_same_col_addr_r;
same_read_cmd = int_same_read_cmd_r;
same_write_cmd = int_same_write_cmd_r;
end
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr_r;
same_shadow_bank_addr = int_same_shadow_bank_addr_r;
same_shadow_row_addr = int_same_shadow_row_addr_r;
end
end
else
begin
assign int_queue_full = tbp_full | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_cmd_gen_dataid;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
end
assign queue_empty = 1;
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read | cmd_gen_write) & ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid));
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = (cfg_enable_no_dm || cfg_enable_ecc) ? int_cmd_gen_dataid_mux : (cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
// proc signals to datapath
assign proc_busy = (cfg_enable_no_dm || cfg_enable_ecc) ? (proc_busy_sig | proc_ecc_busy_sig) : tbp_full;
assign proc_load = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_sig : cmd_gen_load;
assign proc_load_dataid= (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_dataid_sig : cmd_gen_load;
assign proc_write = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_write_sig : cmd_gen_write;
assign proc_read = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_read_sig : cmd_gen_read;
assign proc_size = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_size_sig : cmd_gen_size;
assign proc_localid = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_localid_sig : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_no_dm || cfg_enable_ecc) ? 1 : tbp_load;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else if (j == last_minus_two)
begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe[CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else
begin
pipefull[j] <= pipefull[j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
end
end
//============================ end of queue ===============================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
//altera message_off 10230
module alt_mem_ddrx_csr #
( parameter
DWIDTH_RATIO = 2,
CTL_CSR_ENABLED = 1,
CTL_ECC_CSR_ENABLED = 1,
CTL_CSR_READ_ONLY = 0,
CTL_ECC_CSR_READ_ONLY = 0,
CFG_AVALON_ADDR_WIDTH = 8,
CFG_AVALON_DATA_WIDTH = 32,
MEM_IF_CLK_PAIR_COUNT = 1,
MEM_IF_DQS_WIDTH = 72,
CFG_CS_ADDR_WIDTH = 1, // same as MEM_IF_CHIP
CFG_ROW_ADDR_WIDTH = 13, // max supported row bits
CFG_COL_ADDR_WIDTH = 10, // max supported column bits
CFG_BANK_ADDR_WIDTH = 3, // max supported bank bits
CFG_ENABLE_ECC = 1,
CFG_ENABLE_AUTO_CORR = 1,
CFG_REGDIMM_ENABLE = 0,
// timing parameter width
CAS_WR_LAT_BUS_WIDTH = 4, // max will be 8 in DDR3
ADD_LAT_BUS_WIDTH = 3, // max will be 6 in DDR2
TCL_BUS_WIDTH = 4, // max will be 11 in DDR3
BL_BUS_WIDTH = 5, //
TRRD_BUS_WIDTH = 4, // 2 - 8
TFAW_BUS_WIDTH = 6, // 6 - 32
TRFC_BUS_WIDTH = 8, // 12 - 140?
TREFI_BUS_WIDTH = 13, // 780 - 6240
TRCD_BUS_WIDTH = 4, // 2 - 11
TRP_BUS_WIDTH = 4, // 2 - 11
TWR_BUS_WIDTH = 4, // 2 - 12
TWTR_BUS_WIDTH = 4, // 1 - 10
TRTP_BUS_WIDTH = 4, // 2 - 8
TRAS_BUS_WIDTH = 5, // 4 - 29
TRC_BUS_WIDTH = 6, // 8 - 40
AUTO_PD_BUS_WIDTH = 16, // same as CSR interface
STARVE_LIMIT_BUS_WIDTH = 8,
// timing parameter
CFG_CAS_WR_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_ADD_LAT = 0, // these timing parameter must be set properly for controller to work
CFG_TCL = 0, // these timing parameter must be set properly for controller to work
CFG_BURST_LENGTH = 0, // these timing parameter must be set properly for controller to work
CFG_TRRD = 0, // these timing parameter must be set properly for controller to work
CFG_TFAW = 0, // these timing parameter must be set properly for controller to work
CFG_TRFC = 0, // these timing parameter must be set properly for controller to work
CFG_TREFI = 0, // these timing parameter must be set properly for controller to work
CFG_TRCD = 0, // these timing parameter must be set properly for controller to work
CFG_TRP = 0, // these timing parameter must be set properly for controller to work
CFG_TWR = 0, // these timing parameter must be set properly for controller to work
CFG_TWTR = 0, // these timing parameter must be set properly for controller to work
CFG_TRTP = 0, // these timing parameter must be set properly for controller to work
CFG_TRAS = 0, // these timing parameter must be set properly for controller to work
CFG_TRC = 0, // these timing parameter must be set properly for controller to work
CFG_AUTO_PD_CYCLES = 0, // these timing parameter must be set properly for controller to work
// parameters used by input interface
CFG_ADDR_ORDER = 1, // normally we will use '1' for chip, bank, row, column arrangement
CFG_REORDER_DATA = 0,
CFG_STARVE_LIMIT = 0,
MEM_IF_CSR_COL_WIDTH = 5,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 3,
MEM_IF_CSR_CS_WIDTH = 3
)
(
ctl_clk,
ctl_rst_n,
// csr interface (Avalon)
avalon_mm_addr,
avalon_mm_be,
avalon_mm_write,
avalon_mm_wdata,
avalon_mm_read,
avalon_mm_rdata,
avalon_mm_rdata_valid,
avalon_mm_waitrequest,
// input from PHY
sts_cal_success,
sts_cal_fail,
// input from state machine
local_power_down_ack,
local_self_rfsh_ack,
// input from ecc
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
// output to PHY
cfg_cal_req,
cfg_clock_off,
ctl_cal_byte_lane_sel_n,
// output to timer
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_burst_length,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_auto_pd_cycles,
// output to input interface
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// output to ecc
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// output to others
cfg_regdimm_enable,
cfg_reorder_data,
cfg_starve_limit
);
localparam integer CFG_MEM_IF_CS_WIDTH = (2**CFG_CS_ADDR_WIDTH);
input ctl_clk;
input ctl_rst_n;
input avalon_mm_write;
input avalon_mm_read;
input [CFG_AVALON_ADDR_WIDTH - 1 : 0] avalon_mm_addr;
input [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_wdata;
input [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] avalon_mm_be;
output avalon_mm_waitrequest;
output avalon_mm_rdata_valid;
output [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
// input from AFI
input sts_cal_success;
input sts_cal_fail;
// input from state machine
input local_power_down_ack;
input local_self_rfsh_ack;
// input from ecc
input sts_sbe_error;
input sts_dbe_error;
input sts_corr_dropped;
input [7 : 0] sts_sbe_count;
input [7 : 0] sts_dbe_count;
input [7 : 0] sts_corr_dropped_count;
input [31 : 0] sts_err_addr;
input [31 : 0] sts_corr_dropped_addr;
// output to PHY
output cfg_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
output [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
output [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
output [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
output [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
output [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
output [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
output [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
output [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
output [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
output [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
output [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
output [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
output [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
output [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
output [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
output [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
output [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
output [1 : 0] cfg_addr_order;
output cfg_reorder_data;
output [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
output [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
output [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
output [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
output [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
output cfg_enable_ecc;
output cfg_enable_auto_corr;
output cfg_gen_sbe;
output cfg_gen_dbe;
output cfg_enable_intr;
output cfg_mask_sbe_intr;
output cfg_mask_dbe_intr;
output cfg_mask_corr_dropped_intr;
output cfg_clr_intr;
output cfg_regdimm_enable;
wire avalon_mm_waitrequest;
wire avalon_mm_rdata_valid;
wire [CFG_AVALON_DATA_WIDTH - 1 : 0] avalon_mm_rdata;
reg int_write_req;
reg int_read_req;
reg int_rdata_valid;
reg [8 - 1 : 0] int_addr; // hard-coded to only 8 bits
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_wdata;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] int_rdata;
reg [(CFG_AVALON_DATA_WIDTH / 8) - 1 : 0] int_be;
reg int_mask_avalon_mm_write;
reg int_mask_avalon_mm_read;
reg int_mask_ecc_avalon_mm_write;
reg int_mask_ecc_avalon_mm_read;
// output to PHY
wire cfg_cal_req;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] cfg_clock_off;
wire [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// output to timer
wire [CAS_WR_LAT_BUS_WIDTH - 1 : 0] cfg_cas_wr_lat;
wire [ADD_LAT_BUS_WIDTH - 1 : 0] cfg_add_lat;
wire [TCL_BUS_WIDTH - 1 : 0] cfg_tcl;
wire [BL_BUS_WIDTH - 1 : 0] cfg_burst_length;
wire [TRRD_BUS_WIDTH - 1 : 0] cfg_trrd;
wire [TFAW_BUS_WIDTH - 1 : 0] cfg_tfaw;
wire [TRFC_BUS_WIDTH - 1 : 0] cfg_trfc;
wire [TREFI_BUS_WIDTH - 1 : 0] cfg_trefi;
wire [TRCD_BUS_WIDTH - 1 : 0] cfg_trcd;
wire [TRP_BUS_WIDTH - 1 : 0] cfg_trp;
wire [TWR_BUS_WIDTH - 1 : 0] cfg_twr;
wire [TWTR_BUS_WIDTH - 1 : 0] cfg_twtr;
wire [TRTP_BUS_WIDTH - 1 : 0] cfg_trtp;
wire [TRAS_BUS_WIDTH - 1 : 0] cfg_tras;
wire [TRC_BUS_WIDTH - 1 : 0] cfg_trc;
wire [AUTO_PD_BUS_WIDTH - 1 : 0] cfg_auto_pd_cycles;
// output to input interface
wire [1 : 0] cfg_addr_order;
wire cfg_reorder_data;
wire [STARVE_LIMIT_BUS_WIDTH-1: 0] cfg_starve_limit;
wire [MEM_IF_CSR_COL_WIDTH - 1 : 0] cfg_col_addr_width;
wire [MEM_IF_CSR_ROW_WIDTH - 1 : 0] cfg_row_addr_width;
wire [MEM_IF_CSR_BANK_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [MEM_IF_CSR_CS_WIDTH - 1 : 0] cfg_cs_addr_width;
//output to ecc
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_mask_corr_dropped_intr;
wire cfg_clr_intr;
// output to others
wire cfg_regdimm_enable;
// CSR read registers
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_100;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_110;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_120;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_121;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_122;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_123;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_124;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_125;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_126;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_130;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_131;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_132;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_133;
reg [CFG_AVALON_DATA_WIDTH - 1 : 0] read_csr_register_134;
/*------------------------------------------------------------------------------
CSR Interface
------------------------------------------------------------------------------*/
// Assign waitrequest signal to '0'
assign avalon_mm_waitrequest = 1'b0;
generate
if (!CTL_CSR_ENABLED && !CTL_ECC_CSR_ENABLED)
begin
// when both csr and ecc csr is disabled
assign avalon_mm_rdata = 0;
assign avalon_mm_rdata_valid = 0;
end
else
begin
// register all inputs
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_write_req <= 0;
int_read_req <= 0;
int_addr <= 0;
int_wdata <= 0;
int_be <= 0;
end
else
begin
int_addr <= avalon_mm_addr [7 : 0]; // we only need the bottom 8 bits
int_wdata <= avalon_mm_wdata;
int_be <= avalon_mm_be;
if (avalon_mm_write)
int_write_req <= 1'b1;
else
int_write_req <= 1'b0;
if (avalon_mm_read)
int_read_req <= 1'b1;
else
int_read_req <= 1'b0;
end
end
// Write and read request mask
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
if (CTL_CSR_READ_ONLY)
begin
int_mask_avalon_mm_write <= 1'b1;
int_mask_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_avalon_mm_write <= 1'b0;
int_mask_avalon_mm_read <= 1'b0;
end
if (CTL_ECC_CSR_READ_ONLY)
begin
int_mask_ecc_avalon_mm_write <= 1'b1;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
else
begin
int_mask_ecc_avalon_mm_write <= 1'b0;
int_mask_ecc_avalon_mm_read <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Read Interface
------------------------------------------------------------------------------*/
assign avalon_mm_rdata = int_rdata;
assign avalon_mm_rdata_valid = int_rdata_valid;
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
int_rdata <= 0;
int_rdata_valid <= 0;
end
else
begin
if (int_read_req)
begin
if (int_addr == 8'h00)
int_rdata <= read_csr_register_100;
else if (int_addr == 8'h10)
int_rdata <= read_csr_register_110;
else if (int_addr == 8'h20)
int_rdata <= read_csr_register_120;
else if (int_addr == 8'h21)
int_rdata <= read_csr_register_121;
else if (int_addr == 8'h22)
int_rdata <= read_csr_register_122;
else if (int_addr == 8'h23)
int_rdata <= read_csr_register_123;
else if (int_addr == 8'h24)
int_rdata <= read_csr_register_124;
else if (int_addr == 8'h25)
int_rdata <= read_csr_register_125;
else if (int_addr == 8'h26)
int_rdata <= read_csr_register_126;
else if (int_addr == 8'h30)
int_rdata <= read_csr_register_130;
else if (int_addr == 8'h31)
int_rdata <= read_csr_register_131;
else if (int_addr == 8'h32)
int_rdata <= read_csr_register_132;
else if (int_addr == 8'h33)
int_rdata <= read_csr_register_133;
else if (int_addr == 8'h34)
int_rdata <= read_csr_register_134;
end
if (int_read_req)
int_rdata_valid <= 1'b1;
else
int_rdata_valid <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
CSR Registers
------------------------------------------------------------------------------*/
generate
genvar i;
if (!CTL_CSR_ENABLED) // when csr is disabled
begin
// assigning values to the top
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_cs_addr_width = CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_cal_req = 0;
assign cfg_clock_off = 0;
assign ctl_cal_byte_lane_sel_n = 0;
assign cfg_regdimm_enable = 1'b1; // udimm or rdimm determined by parameter CFG_REGDIMM_ENABLE
end
else
begin
/*------------------------------------------------------------------------------
0x100 ALTMEPHY Status and Control Register
------------------------------------------------------------------------------*/
reg csr_cal_success;
reg csr_cal_fail;
reg csr_cal_req;
reg [5 : 0] csr_clock_off;
// assign value back to top
assign cfg_cal_req = csr_cal_req;
assign cfg_clock_off = csr_clock_off [MEM_IF_CLK_PAIR_COUNT - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_req <= 0;
csr_clock_off <= 0;
end
else
begin
// write request
if (int_write_req && int_addr == 8'h00)
begin
if (int_be [0])
begin
csr_cal_req <= int_wdata [2] ;
end
if (int_be [1])
begin
csr_clock_off <= int_wdata [13 : 8];
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_cal_success <= 0;
csr_cal_fail <= 0;
end
else
begin
csr_cal_success <= sts_cal_success;
csr_cal_fail <= sts_cal_fail;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_100 = 0;
// then we set individual bits
read_csr_register_100 [0] = csr_cal_success;
read_csr_register_100 [1] = csr_cal_fail;
read_csr_register_100 [2] = csr_cal_req;
read_csr_register_100 [13 : 8] = csr_clock_off;
end
/*------------------------------------------------------------------------------
0x110 Controller Status and Control Register
------------------------------------------------------------------------------*/
reg [15 : 0] csr_auto_pd_cycles;
reg csr_auto_pd_ack;
reg csr_self_rfsh; // yyong: remember to handle this
reg csr_self_rfsh_ack;
reg csr_ganged_arf; // yyong: remember to handle this
reg [1 : 0] csr_addr_order;
reg csr_reg_dimm; // yyong: remember to handle this
reg [1 : 0] csr_drate;
// assign value back to top
assign cfg_auto_pd_cycles = csr_auto_pd_cycles;
assign cfg_addr_order = csr_addr_order;
assign cfg_regdimm_enable = csr_reg_dimm;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_cycles <= CFG_AUTO_PD_CYCLES; // reset to default value
csr_self_rfsh <= 0;
csr_ganged_arf <= 0;
csr_addr_order <= CFG_ADDR_ORDER; // reset to default value
csr_reg_dimm <= CFG_REGDIMM_ENABLE; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h10)
begin
if (int_be [0])
begin
csr_auto_pd_cycles [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_auto_pd_cycles [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_self_rfsh <= int_wdata [17] ;
csr_ganged_arf <= int_wdata [19] ;
csr_addr_order <= int_wdata [21 : 20];
csr_reg_dimm <= int_wdata [22] ;
end
end
end
end
// read only registers
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_auto_pd_ack <= 0;
csr_self_rfsh_ack <= 0;
csr_drate <= 0;
end
else
begin
csr_auto_pd_ack <= local_power_down_ack;
csr_self_rfsh_ack <= local_self_rfsh_ack;
csr_drate <= (DWIDTH_RATIO == 2) ? 2'b00 : 2'b01; // Fullrate - 00, Halfrate - 01
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_110 = 0;
// then we set individual bits
read_csr_register_110 [15 : 0 ] = csr_auto_pd_cycles;
read_csr_register_110 [16] = csr_auto_pd_ack;
read_csr_register_110 [17] = csr_self_rfsh;
read_csr_register_110 [18] = csr_self_rfsh_ack;
read_csr_register_110 [19] = csr_ganged_arf;
read_csr_register_110 [21 : 20] = csr_addr_order;
read_csr_register_110 [22] = csr_reg_dimm;
read_csr_register_110 [24 : 23] = csr_drate;
end
/*------------------------------------------------------------------------------
0x120 Memory Address Sizes 0
------------------------------------------------------------------------------*/
reg [7 : 0] csr_col_width;
reg [7 : 0] csr_row_width;
reg [3 : 0] csr_bank_width;
reg [3 : 0] csr_chip_width;
// assign value back to top
assign cfg_cs_addr_width = csr_chip_width [MEM_IF_CSR_CS_WIDTH - 1 : 0];
assign cfg_bank_addr_width = csr_bank_width [MEM_IF_CSR_BANK_WIDTH - 1 : 0];
assign cfg_row_addr_width = csr_row_width [MEM_IF_CSR_ROW_WIDTH - 1 : 0];
assign cfg_col_addr_width = csr_col_width [MEM_IF_CSR_COL_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_col_width <= CFG_COL_ADDR_WIDTH; // reset to default value
csr_row_width <= CFG_ROW_ADDR_WIDTH; // reset to default value
csr_bank_width <= CFG_BANK_ADDR_WIDTH; // reset to default value
csr_chip_width <= CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h20)
begin
if (int_be [0])
begin
if (int_wdata [7 : 0] <= CFG_COL_ADDR_WIDTH)
begin
csr_col_width <= int_wdata [7 : 0 ];
end
end
if (int_be [1])
begin
if (int_wdata [15 : 8] <= CFG_ROW_ADDR_WIDTH)
begin
csr_row_width <= int_wdata [15 : 8 ];
end
end
if (int_be [2])
begin
if (int_wdata [19 : 16] <= CFG_BANK_ADDR_WIDTH)
begin
csr_bank_width <= int_wdata [19 : 16];
end
if (int_wdata [23 : 20] <= (CFG_MEM_IF_CS_WIDTH > 1 ? CFG_CS_ADDR_WIDTH : 0))
begin
csr_chip_width <= int_wdata [23 : 20];
end
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_120 = 0;
// then we set individual bits
read_csr_register_120 [7 : 0 ] = csr_col_width;
read_csr_register_120 [15 : 8 ] = csr_row_width;
read_csr_register_120 [19 : 16] = csr_bank_width;
read_csr_register_120 [23 : 20] = csr_chip_width;
end
/*------------------------------------------------------------------------------
0x121 Memory Address Sizes 1
------------------------------------------------------------------------------*/
reg [31 : 0] csr_data_binary_representation;
reg [7 : 0] csr_chip_binary_representation;
reg [MEM_IF_DQS_WIDTH * CFG_MEM_IF_CS_WIDTH - 1 : 0] cal_byte_lane;
// assign value back to top
assign ctl_cal_byte_lane_sel_n = ~cal_byte_lane;
// determine cal_byte_lane base on csr data
for (i = 0;i < CFG_MEM_IF_CS_WIDTH;i = i + 1)
begin : ctl_cal_byte_lane_per_chip
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= {MEM_IF_DQS_WIDTH{1'b1}}; // setting to all ones
else
begin
if (csr_chip_binary_representation[i])
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= csr_data_binary_representation [MEM_IF_DQS_WIDTH - 1 : 0];
else
cal_byte_lane [(i + 1) * MEM_IF_DQS_WIDTH - 1 : i * MEM_IF_DQS_WIDTH] <= 0;
end
end
end
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_data_binary_representation <= {MEM_IF_DQS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h21)
begin
if (int_be [0])
begin
csr_data_binary_representation [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_data_binary_representation [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_data_binary_representation [23 : 16] <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_data_binary_representation [31 : 24] <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_121 = 0;
// then we set individual bits
read_csr_register_121 [31 : 0 ] = csr_data_binary_representation;
end
/*------------------------------------------------------------------------------
0x122 Memory Address Sizes 2
------------------------------------------------------------------------------*/
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_chip_binary_representation <= {CFG_MEM_IF_CS_WIDTH{1'b1}};
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h22)
begin
if (int_be [0])
begin
csr_chip_binary_representation [ 7 : 0] <= int_wdata [7 : 0 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_122 = 0;
// then we set individual bits
read_csr_register_122 [7 : 0 ] = csr_chip_binary_representation;
end
/*------------------------------------------------------------------------------
0x123 Memory Timing Parameters Registers 0
------------------------------------------------------------------------------*/
reg [3 : 0] csr_trcd;
reg [3 : 0] csr_trrd;
reg [3 : 0] csr_trp;
reg [3 : 0] csr_tmrd; // yyong: might remove this
reg [7 : 0] csr_tras;
reg [7 : 0] csr_trc;
// assign value back to top
assign cfg_trcd = csr_trcd [TRCD_BUS_WIDTH - 1 : 0];
assign cfg_trrd = csr_trrd [TRRD_BUS_WIDTH - 1 : 0];
assign cfg_trp = csr_trp [TRP_BUS_WIDTH - 1 : 0];
assign cfg_tras = csr_tras [TRAS_BUS_WIDTH - 1 : 0];
assign cfg_trc = csr_trc [TRC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trcd <= CFG_TRCD; // reset to default value
csr_trrd <= CFG_TRRD; // reset to default value
csr_trp <= CFG_TRP; // reset to default value
csr_tmrd <= 0; // yyong: might remove this
csr_tras <= CFG_TRAS; // reset to default value
csr_trc <= CFG_TRC; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h23)
begin
if (int_be [0])
begin
csr_trcd <= int_wdata [3 : 0 ];
csr_trrd <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_trp <= int_wdata [11 : 8 ];
csr_tmrd <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_tras <= int_wdata [23 : 16];
end
if (int_be [3])
begin
csr_trc <= int_wdata [31 : 24];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_123 = 0;
// then we set individual bits
read_csr_register_123 [3 : 0 ] = csr_trcd;
read_csr_register_123 [7 : 4 ] = csr_trrd;
read_csr_register_123 [11 : 8 ] = csr_trp;
read_csr_register_123 [15 : 12] = csr_tmrd;
read_csr_register_123 [23 : 16] = csr_tras;
read_csr_register_123 [31 : 24] = csr_trc;
end
/*------------------------------------------------------------------------------
0x124 Memory Timing Parameters Registers 1
------------------------------------------------------------------------------*/
reg [3 : 0] csr_twtr;
reg [3 : 0] csr_trtp;
reg [5 : 0] csr_tfaw;
// assign value back to top
assign cfg_twtr = csr_twtr [TWTR_BUS_WIDTH - 1 : 0];
assign cfg_trtp = csr_trtp [TRTP_BUS_WIDTH - 1 : 0];
assign cfg_tfaw = csr_tfaw [TFAW_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_twtr <= CFG_TWTR;
csr_trtp <= CFG_TRTP;
csr_tfaw <= CFG_TFAW;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h24)
begin
if (int_be [0])
begin
csr_twtr <= int_wdata [3 : 0 ];
csr_trtp <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_tfaw <= int_wdata [13 : 8 ];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_124 = 0;
// then we set individual bits
read_csr_register_124 [3 : 0 ] = csr_twtr;
read_csr_register_124 [7 : 4 ] = csr_trtp;
read_csr_register_124 [15 : 8 ] = csr_tfaw;
end
/*------------------------------------------------------------------------------
0x125 Memory Timing Parameters Registers 2
------------------------------------------------------------------------------*/
reg [15 : 0] csr_trefi;
reg [7 : 0] csr_trfc;
// assign value back to top
assign cfg_trefi = csr_trefi [TREFI_BUS_WIDTH - 1 : 0];
assign cfg_trfc = csr_trfc [TRFC_BUS_WIDTH - 1 : 0];
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_trefi <= CFG_TREFI;
csr_trfc <= CFG_TRFC;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h25)
begin
if (int_be [0])
begin
csr_trefi [ 7 : 0] <= int_wdata [ 7 : 0];
end
if (int_be [1])
begin
csr_trefi [15 : 8] <= int_wdata [15 : 8];
end
if (int_be [2])
begin
csr_trfc <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_125 = 0;
// then we set individual bits
read_csr_register_125 [15 : 0 ] = csr_trefi;
read_csr_register_125 [23 : 16] = csr_trfc;
end
/*------------------------------------------------------------------------------
0x126 Memory Timing Parameters Registers 3
------------------------------------------------------------------------------*/
reg [3 : 0] csr_tcl;
reg [3 : 0] csr_al;
reg [3 : 0] csr_cwl;
reg [3 : 0] csr_twr;
reg [3 : 0] csr_bl;
// assign value back to top
assign cfg_tcl = csr_tcl [TCL_BUS_WIDTH - 1 : 0];
assign cfg_add_lat = csr_al [ADD_LAT_BUS_WIDTH - 1 : 0];
assign cfg_cas_wr_lat = csr_cwl [CAS_WR_LAT_BUS_WIDTH - 1 : 0];
assign cfg_twr = csr_twr [TWR_BUS_WIDTH - 1 : 0];
assign cfg_burst_length = {{(BL_BUS_WIDTH - 4){1'b0}}, csr_bl};
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_tcl <= CFG_TCL;
csr_al <= CFG_ADD_LAT;
csr_cwl <= CFG_CAS_WR_LAT;
csr_twr <= CFG_TWR;
csr_bl <= CFG_BURST_LENGTH;
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h26)
begin
if (int_be [0])
begin
csr_tcl <= int_wdata [3 : 0 ];
csr_al <= int_wdata [7 : 4 ];
end
if (int_be [1])
begin
csr_cwl <= int_wdata [11 : 8 ];
csr_twr <= int_wdata [15 : 12];
end
if (int_be [2])
begin
csr_bl <= int_wdata [19 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_126 = 0;
// then we set individual bits
read_csr_register_126 [3 : 0 ] = csr_tcl;
read_csr_register_126 [7 : 4 ] = csr_al;
read_csr_register_126 [11 : 8 ] = csr_cwl;
read_csr_register_126 [15 : 12] = csr_twr;
read_csr_register_126 [19 : 16] = csr_bl;
end
end
if (!CTL_ECC_CSR_ENABLED)
begin
assign cfg_enable_ecc = 1'b1; // default value
assign cfg_enable_auto_corr = 1'b1; // default value
assign cfg_gen_sbe = 0;
assign cfg_gen_dbe = 0;
assign cfg_enable_intr = 1'b1; // default value
assign cfg_mask_sbe_intr = 0;
assign cfg_mask_dbe_intr = 0;
assign cfg_clr_intr = 0;
assign cfg_mask_corr_dropped_intr=0;
end
else
begin
/*------------------------------------------------------------------------------
0x130 ECC Control Register
------------------------------------------------------------------------------*/
reg csr_enable_ecc;
reg csr_enable_auto_corr;
reg csr_gen_sbe;
reg csr_gen_dbe;
reg csr_enable_intr;
reg csr_mask_sbe_intr;
reg csr_mask_dbe_intr;
reg csr_ecc_clear;
reg csr_mask_corr_dropped_intr;
// assign value back to top
assign cfg_enable_ecc = csr_enable_ecc;
assign cfg_enable_auto_corr = csr_enable_auto_corr;
assign cfg_gen_sbe = csr_gen_sbe;
assign cfg_gen_dbe = csr_gen_dbe;
assign cfg_enable_intr = csr_enable_intr;
assign cfg_mask_sbe_intr = csr_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_mask_dbe_intr;
assign cfg_clr_intr = csr_ecc_clear;
assign cfg_mask_corr_dropped_intr = csr_mask_corr_dropped_intr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_enable_ecc <= CFG_ENABLE_ECC;
csr_enable_auto_corr <= CFG_ENABLE_AUTO_CORR;
csr_gen_sbe <= 0;
csr_gen_dbe <= 0;
csr_enable_intr <= 1'b1;
csr_mask_sbe_intr <= 0;
csr_mask_dbe_intr <= 0;
csr_ecc_clear <= 0;
csr_mask_corr_dropped_intr <= 0;
end
else
begin
// write request
if (!int_mask_ecc_avalon_mm_write && int_write_req && int_addr == 8'h30)
begin
if (int_be [0])
begin
csr_enable_ecc <= int_wdata [0];
csr_enable_auto_corr <= int_wdata [1];
csr_gen_sbe <= int_wdata [2];
csr_gen_dbe <= int_wdata [3];
csr_enable_intr <= int_wdata [4];
csr_mask_sbe_intr <= int_wdata [5];
csr_mask_dbe_intr <= int_wdata [6];
csr_ecc_clear <= int_wdata [7];
end
if (int_be [1])
begin
csr_mask_corr_dropped_intr <= int_wdata [8];
end
end
// set csr_clear to zero after one clock cycle
if (csr_ecc_clear)
csr_ecc_clear <= 1'b0;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_130 = 0;
// then we set individual bits
read_csr_register_130 [0] = csr_enable_ecc;
read_csr_register_130 [1] = csr_enable_auto_corr;
read_csr_register_130 [2] = csr_gen_sbe;
read_csr_register_130 [3] = csr_gen_dbe;
read_csr_register_130 [4] = csr_enable_intr;
read_csr_register_130 [5] = csr_mask_sbe_intr;
read_csr_register_130 [6] = csr_mask_dbe_intr;
read_csr_register_130 [7] = csr_ecc_clear;
read_csr_register_130 [8] = csr_mask_corr_dropped_intr;
end
/*------------------------------------------------------------------------------
0x131 ECC Status Register (Read Only)
------------------------------------------------------------------------------*/
reg csr_sbe_error;
reg csr_dbe_error;
reg csr_corr_dropped;
reg [7 : 0] csr_sbe_count;
reg [7 : 0] csr_dbe_count;
reg [7 : 0] csr_corr_dropped_count;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
begin
csr_sbe_error <= 0;
csr_dbe_error <= 0;
csr_sbe_count <= 0;
csr_dbe_count <= 0;
csr_corr_dropped <= 0;
csr_corr_dropped_count <= 0;
end
else
begin
csr_sbe_error <= sts_sbe_error;
csr_dbe_error <= sts_dbe_error;
csr_sbe_count <= sts_sbe_count;
csr_dbe_count <= sts_dbe_count;
csr_corr_dropped <= sts_corr_dropped;
csr_corr_dropped_count <= sts_corr_dropped_count;
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_131 = 0;
// then we set individual bits
read_csr_register_131 [0 ] = csr_sbe_error;
read_csr_register_131 [1 ] = csr_dbe_error;
read_csr_register_131 [2 ] = csr_corr_dropped;
read_csr_register_131 [15 : 8 ] = csr_sbe_count;
read_csr_register_131 [23 : 16] = csr_dbe_count;
read_csr_register_131 [31 : 24] = csr_corr_dropped_count;
end
/*------------------------------------------------------------------------------
0x132 ECC Error Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_error_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_error_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_error_addr <= 0;
else
csr_error_addr <= sts_err_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_132 = csr_error_addr;
end
/*------------------------------------------------------------------------------
0x133 ECC Correction Dropped Address Register (Read Only)
------------------------------------------------------------------------------*/
reg [31 : 0] csr_corr_dropped_addr;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_corr_dropped_addr <= 0;
end
else
begin
// all registers are read only registers
if (csr_ecc_clear)
csr_corr_dropped_addr <= 0;
else
csr_corr_dropped_addr <= sts_corr_dropped_addr;
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// then we set individual bits
read_csr_register_133 = csr_corr_dropped_addr;
end
/*------------------------------------------------------------------------------
0x134 Controller Status and Control Register - Advanced Features
------------------------------------------------------------------------------*/
reg csr_reorder_data;
reg [7 : 0] csr_starve_limit;
// assign value back to top
assign cfg_reorder_data = csr_reorder_data;
assign cfg_starve_limit = csr_starve_limit;
// register arrays to store CSR informations
always @ (posedge ctl_clk or negedge ctl_rst_n)
begin
if (!ctl_rst_n)
begin
csr_reorder_data <= CFG_REORDER_DATA;
csr_starve_limit <= CFG_STARVE_LIMIT; // reset to default value
end
else
begin
// write request
if (!int_mask_avalon_mm_write && int_write_req && int_addr == 8'h34)
begin
if (int_be [0])
begin
csr_reorder_data <= int_wdata [ 0];
end
if (int_be [2])
begin
csr_starve_limit <= int_wdata [23 : 16];
end
end
end
end
// assigning read datas back to 32 bit bus
always @ (*)
begin
// first, set all to zeros
read_csr_register_134 = 0;
// then we set individual bits
read_csr_register_134 [ 0 ] = csr_reorder_data;
read_csr_register_134 [ 23 : 16 ] = csr_starve_limit;
end
end
endgenerate
endmodule
|
// (c) 2001-2011 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
//altera message_off 10230
//altera message_off 10762
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_sideband
# (parameter
// parameters
cfg_port_width_type = 3,
cfg_dwidth_ratio = 2, //2-fr,4-hr,8-qr
cfg_reg_grant = 1,
cfg_ctl_tbp_num = 4,
cfg_mem_if_cs_width = 1,
cfg_mem_if_chip = 1, // one hot
cfg_mem_if_ba_width = 3,
cfg_port_width_tcl = 4,
cfg_mem_if_clk_pair_count = 2,
cfg_rank_timer_output_reg = 0,
t_param_arf_to_valid_width = 10,
t_param_arf_period_width = 13,
t_param_pch_all_to_valid_width = 10,
t_param_srf_to_valid_width = 10,
t_param_srf_to_zq_cal_width = 10,
t_param_pdn_to_valid_width = 6,
bank_timer_counter_offset = 2, //used to be 4
t_param_pdn_period_width = 16 // temporary
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
// local interface
rfsh_req,
rfsh_chip,
rfsh_ack,
self_rfsh_req,
self_rfsh_chip,
self_rfsh_ack,
deep_powerdn_req,
deep_powerdn_chip,
deep_powerdn_ack,
power_down_ack,
// sideband output
stall_row_arbiter,
stall_col_arbiter,
stall_chip,
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
sb_tbp_precharge_all,
ctl_mem_clk_disable,
// tbp & cmd gen
cmd_gen_chipsel,
tbp_chipsel,
tbp_load,
// timing
t_param_arf_to_valid,
t_param_arf_period,
t_param_pch_all_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_pdn_to_valid,
t_param_pdn_period,
// block status
tbp_empty,
tbp_bank_active,
tbp_timer_ready,
row_grant,
col_grant,
// dqs tracking
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
// config ports
cfg_enable_dqs_tracking,
cfg_user_rfsh,
cfg_type,
cfg_tcl,
cfg_regdimm_enable
);
// states for our dqs bus monitor state machine
localparam idle = 32'h49444c45;
localparam arf = 32'h20415246;
localparam pdn = 32'h2050444e;
localparam srf = 32'h20535246;
localparam init = 32'h696e6974;
localparam pchall = 32'h70636861;
localparam refresh = 32'h72667368;
localparam pdown = 32'h7064776e;
localparam selfrfsh = 32'h736c7266;
localparam deeppdn = 32'h64656570;
localparam zqcal = 32'h7a63616c;
localparam dqstrk = 32'h6471746b;
localparam dqslong = 32'h64716c6e;
localparam power_saving_counter_width = t_param_srf_to_valid_width;
localparam arf_counter_width = t_param_arf_period_width;
localparam pdn_counter_width = t_param_pdn_period_width;
localparam integer cfg_mem_if_ba_width_sqrd = 2**cfg_mem_if_ba_width;
localparam integer cfg_port_width_tcl_sqrd = 2**cfg_port_width_tcl;
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
input rfsh_req;
input [cfg_mem_if_chip-1:0] rfsh_chip;
output rfsh_ack;
input self_rfsh_req;
input [cfg_mem_if_chip-1:0] self_rfsh_chip;
output self_rfsh_ack;
input deep_powerdn_req;
input [cfg_mem_if_chip-1:0] deep_powerdn_chip;
output deep_powerdn_ack;
output power_down_ack;
output stall_row_arbiter;
output stall_col_arbiter;
output [cfg_mem_if_chip-1:0] stall_chip;
output [cfg_mem_if_chip-1:0] sb_do_precharge_all;
output [cfg_mem_if_chip-1:0] sb_do_refresh;
output [cfg_mem_if_chip-1:0] sb_do_self_refresh;
output [cfg_mem_if_chip-1:0] sb_do_power_down;
output [cfg_mem_if_chip-1:0] sb_do_deep_pdown;
output [cfg_mem_if_chip-1:0] sb_do_zq_cal;
output [cfg_ctl_tbp_num-1:0] sb_tbp_precharge_all;
output [cfg_mem_if_clk_pair_count-1:0] ctl_mem_clk_disable;
input [cfg_mem_if_cs_width-1:0] cmd_gen_chipsel;
input [(cfg_ctl_tbp_num*cfg_mem_if_cs_width)-1:0] tbp_chipsel;
input [cfg_ctl_tbp_num-1:0] tbp_load;
input [t_param_arf_to_valid_width - 1 : 0] t_param_arf_to_valid;
input [t_param_arf_period_width - 1 : 0] t_param_arf_period;
input [t_param_pch_all_to_valid_width - 1 : 0] t_param_pch_all_to_valid;
input [t_param_srf_to_valid_width - 1 : 0] t_param_srf_to_valid;
input [t_param_srf_to_zq_cal_width - 1 : 0] t_param_srf_to_zq_cal;
input [t_param_pdn_to_valid_width - 1 : 0] t_param_pdn_to_valid;
input [t_param_pdn_period_width - 1 : 0] t_param_pdn_period;
input tbp_empty;
input [cfg_mem_if_chip-1:0] tbp_bank_active;
input [cfg_mem_if_chip-1:0] tbp_timer_ready;
input row_grant;
input col_grant;
output [cfg_mem_if_chip-1:0] afi_ctl_refresh_done;
input [cfg_mem_if_chip-1:0] afi_seq_busy;
output [cfg_mem_if_chip-1:0] afi_ctl_long_idle;
input cfg_enable_dqs_tracking;
input cfg_user_rfsh;
input [cfg_port_width_type - 1 : 0] cfg_type;
input [cfg_port_width_tcl - 1 : 0] cfg_tcl;
input cfg_regdimm_enable;
// end of port declaration
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire [cfg_mem_if_clk_pair_count-1:0] ctl_mem_clk_disable;
reg [cfg_mem_if_chip-1:0] sb_do_precharge_all;
reg [cfg_mem_if_chip-1:0] sb_do_refresh;
reg [cfg_mem_if_chip-1:0] sb_do_self_refresh;
reg [cfg_mem_if_chip-1:0] sb_do_power_down;
reg [cfg_mem_if_chip-1:0] sb_do_deep_pdown;
reg [cfg_mem_if_chip-1:0] sb_do_zq_cal;
reg [cfg_ctl_tbp_num-1:0] sb_tbp_precharge_all;
reg [cfg_mem_if_chip-1:0] do_refresh;
reg [cfg_mem_if_chip-1:0] do_power_down;
reg [cfg_mem_if_chip-1:0] do_deep_pdown;
reg [cfg_mem_if_chip-1:0] do_self_rfsh;
reg [cfg_mem_if_chip-1:0] do_self_rfsh_r;
reg [cfg_mem_if_chip-1:0] do_precharge_all;
reg [cfg_mem_if_chip-1:0] do_zqcal;
reg [cfg_mem_if_chip-1:0] stall_chip;
reg [cfg_mem_if_chip-1:0] int_stall_chip;
reg [cfg_mem_if_chip-1:0] int_stall_chip_combi;
reg [cfg_mem_if_chip-1:0] stall_arbiter;
reg [cfg_mem_if_chip-1:0] afi_ctl_refresh_done;
reg [cfg_mem_if_chip-1:0] afi_ctl_long_idle;
reg [cfg_mem_if_chip-1:0] dqstrk_exit;
reg [cfg_mem_if_chip-1:0] dqslong_exit;
reg [cfg_mem_if_chip-1:0] doing_zqcal;
reg [cfg_mem_if_chip-1:0] refresh_chip_req;
reg [cfg_mem_if_chip-1:0] self_refresh_chip_req;
reg self_rfsh_req_r;
reg [cfg_mem_if_chip-1:0] deep_pdown_chip_req;
reg [cfg_mem_if_chip-1:0] power_down_chip_req;
wire [cfg_mem_if_chip-1:0] power_down_chip_req_combi;
wire [cfg_mem_if_chip-1:0] all_banks_closed;
wire [cfg_mem_if_chip-1:0] tcom_not_running;
reg [cfg_port_width_tcl_sqrd-1:0] tcom_not_running_pipe [cfg_mem_if_chip-1:0];
reg [cfg_mem_if_chip-1:0] can_refresh;
reg [cfg_mem_if_chip-1:0] can_self_rfsh;
reg [cfg_mem_if_chip-1:0] can_deep_pdown;
reg [cfg_mem_if_chip-1:0] can_power_down;
reg [cfg_mem_if_chip-1:0] can_exit_power_saving_mode;
reg [cfg_mem_if_chip-1:0] cs_refresh_req;
wire grant;
wire [cfg_mem_if_chip-1:0] cs_zq_cal_req;
wire [cfg_mem_if_chip-1:0] power_saving_enter_ready;
wire [cfg_mem_if_chip-1:0] power_saving_exit_ready;
reg [pdn_counter_width - 1 : 0] power_down_cnt;
reg no_command_r1;
reg [cfg_mem_if_chip-1:0] afi_seq_busy_r; // synchronizer
reg [cfg_mem_if_chip-1:0] afi_seq_busy_r2; // synchronizer
//new! to avoid contention
reg [cfg_mem_if_chip-1:0] do_refresh_req;
reg refresh_req_ack;
reg dummy_do_refresh;
reg dummy_do_refresh_r;
reg do_refresh_r;
reg [cfg_mem_if_chip-1:0] do_self_rfsh_req;
reg self_rfsh_req_ack;
reg dummy_do_self_rfsh;
reg [cfg_mem_if_chip-1:0] do_zqcal_req;
reg zqcal_req_ack;
reg dummy_do_zqcal;
reg [cfg_mem_if_chip-1:0] do_pch_all_req;
reg pch_all_req_ack;
reg dummy_do_pch_all;
integer i;
assign ctl_mem_clk_disable = {cfg_mem_if_clk_pair_count{1'b0}};
//generate *_chip_ok signals by checking can_*[chip], only when for_chip[chip] is 1
generate
genvar chip;
for (chip = 0; chip < cfg_mem_if_chip; chip = chip + 1)
begin : gen_chip_ok
// check can_* only for chips that we'd like to precharge_all to, ^~ is xnor
assign tcom_not_running[chip] = tbp_timer_ready[chip];
assign all_banks_closed[chip] = ~tbp_bank_active[chip];
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
tcom_not_running_pipe[chip] <= 0;
end
else
begin
if (!tcom_not_running[chip])
tcom_not_running_pipe[chip] <= 0;
else
tcom_not_running_pipe[chip] <= {tcom_not_running_pipe[chip][cfg_port_width_tcl_sqrd -2 :0],tcom_not_running[chip]};
end
end
end
endgenerate
assign rfsh_ack = (!(cfg_regdimm_enable && cfg_type == `mmr_type_ddr3 && cfg_mem_if_chip != 1)) ? |do_refresh : ((|do_refresh | do_refresh_r) & refresh_req_ack);
assign self_rfsh_ack = |do_self_rfsh;
assign deep_powerdn_ack = |do_deep_pdown;
assign power_down_ack = |do_power_down;
// register sideband signals when cfg_reg_grant is '1'
// to prevent sideband request going out on the same cycle as tbp request
generate
begin
genvar j;
if (cfg_reg_grant == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_do_precharge_all <= 0;
sb_do_refresh <= 0;
sb_do_self_refresh <= 0;
sb_do_power_down <= 0;
sb_do_deep_pdown <= 0;
sb_do_zq_cal <= 0;
end
else
begin
sb_do_precharge_all <= do_precharge_all;
sb_do_refresh <= do_refresh;
sb_do_self_refresh <= do_self_rfsh;
sb_do_power_down <= do_power_down;
sb_do_deep_pdown <= do_deep_pdown;
sb_do_zq_cal <= do_zqcal;
end
end
for (j = 0;j < cfg_ctl_tbp_num;j = j + 1)
begin : tbp_loop_1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_tbp_precharge_all [j] <= 1'b0;
end
else
begin
if (tbp_load[j])
begin
sb_tbp_precharge_all [j] <= do_precharge_all [cmd_gen_chipsel];
end
else
begin
sb_tbp_precharge_all [j] <= do_precharge_all [tbp_chipsel [(j + 1) * cfg_mem_if_cs_width - 1 : j * cfg_mem_if_cs_width]];
end
end
end
end
end
else
begin
always @ (*)
begin
sb_do_precharge_all = do_precharge_all;
sb_do_refresh = do_refresh;
sb_do_self_refresh = do_self_rfsh;
sb_do_power_down = do_power_down;
sb_do_deep_pdown = do_deep_pdown;
sb_do_zq_cal = do_zqcal;
end
for (j = 0;j < cfg_ctl_tbp_num;j = j + 1)
begin : tbp_loop_2
always @ (*)
begin
sb_tbp_precharge_all [j] = do_precharge_all [tbp_chipsel [(j + 1) * cfg_mem_if_cs_width - 1 : j * cfg_mem_if_cs_width]];
end
end
end
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_req_ack <= 0;
zqcal_req_ack <= 0;
pch_all_req_ack <= 0;
self_rfsh_req_ack <= 0;
dummy_do_refresh_r <= dummy_do_refresh;
do_refresh_r <= 0;
end
else
begin
refresh_req_ack <= dummy_do_refresh;
zqcal_req_ack <= dummy_do_zqcal;
pch_all_req_ack <= dummy_do_pch_all;
self_rfsh_req_ack <= dummy_do_self_rfsh;
dummy_do_refresh_r <= dummy_do_refresh;
if (dummy_do_refresh && !dummy_do_refresh_r)
do_refresh_r <= |do_refresh;
else
do_refresh_r <= 0;
end
end
always @(*)
begin
i = 0;
dummy_do_refresh = 0;
dummy_do_pch_all = 0;
dummy_do_zqcal = 0;
if (|do_refresh_req)
begin
if (!(cfg_regdimm_enable && cfg_type == `mmr_type_ddr3 && cfg_mem_if_chip != 1)) // if not (regdimm and ddr3), normal refresh
do_refresh = do_refresh_req;
else
begin
for (i = 0;i < cfg_mem_if_chip;i = i + 1)
begin
if (i%2 == 0)
begin
do_refresh[i] = do_refresh_req[i];
dummy_do_refresh= |do_refresh_req;
end
else if (i%2 == 1 && refresh_req_ack)
do_refresh[i] = do_refresh_req[i];
else
do_refresh[i] = 0;
end
end
do_precharge_all = 0;
do_zqcal = 0;
end
else if (|do_pch_all_req)
begin
do_refresh = 0;
if (!(cfg_regdimm_enable && cfg_type == `mmr_type_ddr3 && cfg_mem_if_chip != 1))
do_precharge_all = do_pch_all_req;
else
begin
for (i = 0;i < cfg_mem_if_chip;i = i + 1)
begin
if (i%2 == 0)
begin
do_precharge_all[i] = do_pch_all_req[i];
dummy_do_pch_all = |do_pch_all_req;
end
else if (i%2 == 1 && pch_all_req_ack)
do_precharge_all[i] = do_pch_all_req[i];
else
do_precharge_all[i] = 0;
end
end
do_zqcal = 0;
end
else if (|do_zqcal_req)
begin
do_refresh = 0;
do_precharge_all = 0;
if (!(cfg_regdimm_enable && cfg_type == `mmr_type_ddr3 && cfg_mem_if_chip != 1))
do_zqcal = do_zqcal_req;
else
begin
for (i = 0;i < cfg_mem_if_chip;i = i + 1)
begin
if (i%2 == 0)
begin
do_zqcal[i] = do_zqcal_req[i];
dummy_do_zqcal= |do_zqcal_req;
end
else if (i%2 == 1 && zqcal_req_ack)
do_zqcal[i] = do_zqcal_req[i];
else
do_zqcal[i] = 0;
end
end
end
else
begin
do_refresh = 0;
dummy_do_refresh = 0;
do_precharge_all = 0;
dummy_do_pch_all = 0;
do_zqcal = 0;
dummy_do_zqcal = 0;
end
end
always @(*)
begin
i = 0;
dummy_do_self_rfsh = 1'b0;
if (|do_refresh || |do_precharge_all || |do_zqcal)
begin
if (|do_self_rfsh_r)
begin
do_self_rfsh = do_self_rfsh_req;
dummy_do_self_rfsh = 1'b1;
end
else
do_self_rfsh = 0;
end
else
begin
if (!(cfg_regdimm_enable && cfg_type == `mmr_type_ddr3 && cfg_mem_if_chip != 1))
do_self_rfsh = do_self_rfsh_req;
else
begin
for (i = 0;i < cfg_mem_if_chip;i = i + 1)
begin
if (i%2 == 0)
begin
do_self_rfsh[i] = do_self_rfsh_req[i];
dummy_do_self_rfsh= |do_self_rfsh_req;
end
else if (i%2 == 1 && self_rfsh_req_ack)
do_self_rfsh[i] = do_self_rfsh_req[i];
else
do_self_rfsh[i] = 0;
end
end
end
end
assign stall_row_arbiter = |stall_arbiter;
assign stall_col_arbiter = |stall_arbiter;
assign grant = (cfg_reg_grant == 1) ? (row_grant | col_grant) : 1'b0;
//register self_rfsh_req and deep_powerdn_req
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
self_refresh_chip_req <= 0;
deep_pdown_chip_req <= 0;
self_rfsh_req_r <= 0;
do_self_rfsh_r <= 0;
end
else
begin
if (self_rfsh_req)
self_refresh_chip_req <= self_rfsh_chip;
else
self_refresh_chip_req <= 0;
self_rfsh_req_r <= self_rfsh_req & |self_rfsh_chip;
do_self_rfsh_r <= do_self_rfsh;
if (deep_powerdn_req)
deep_pdown_chip_req <= deep_powerdn_chip;
else
deep_pdown_chip_req <= 0;
end
end
//combi user refresh
always @(*)
begin
if (cfg_user_rfsh)
begin
if (rfsh_req)
refresh_chip_req = rfsh_chip;
else
refresh_chip_req = 0;
end
else
refresh_chip_req = cs_refresh_req;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_seq_busy_r <= 0;
afi_seq_busy_r2 <= 0;
end
else
begin
afi_seq_busy_r <= afi_seq_busy;
afi_seq_busy_r2 <= afi_seq_busy_r;
end
end
// cans
generate
genvar w_cs;
for (w_cs = 0;w_cs < cfg_mem_if_chip;w_cs = w_cs + 1)
begin : can_signal_per_chip
// can refresh signal for each rank
always @ (*)
begin
can_refresh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// can self refresh signal for each rank
always @ (*)
begin
can_self_rfsh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
always @ (*)
begin
can_deep_pdown [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & ~grant;
end
// can power down signal for each rank
always @ (*)
begin
can_power_down [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed[w_cs] & tcom_not_running[w_cs] & tcom_not_running_pipe[w_cs][cfg_tcl] & ~grant;
end
// can exit power saving mode signal for each rank
always @ (*)
begin
can_exit_power_saving_mode [w_cs] = power_saving_exit_ready [w_cs];
end
end
endgenerate
/*------------------------------------------------------------------------------
[start] power saving rank monitor
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
power saving state machine
------------------------------------------------------------------------------*/
generate
genvar u_cs;
for (u_cs = 0;u_cs < cfg_mem_if_chip;u_cs = u_cs + 1)
begin : power_saving_logic_per_chip
reg [power_saving_counter_width - 1 : 0] power_saving_cnt;
reg [31:0] state;
reg [31 : 0] sideband_state;
reg int_enter_power_saving_ready;
reg int_exit_power_saving_ready;
reg registered_reset;
reg int_zq_cal_req;
reg int_do_power_down;
reg int_do_power_down_r1;
reg int_do_power_down_r2;
reg int_do_self_refresh;
reg int_do_self_refresh_r1;
reg int_do_self_refresh_r2;
reg int_do_self_refresh_r3;
// assignment
assign power_saving_enter_ready [u_cs] = int_enter_power_saving_ready;
assign power_saving_exit_ready [u_cs] = int_exit_power_saving_ready & ~((int_do_power_down & ~int_do_power_down_r1) | (int_do_self_refresh & ~int_do_self_refresh_r1));
assign cs_zq_cal_req [u_cs] = int_zq_cal_req;
// counter for power saving state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
power_saving_cnt <= 0;
else
begin
if (do_precharge_all[u_cs] || do_refresh[u_cs] || do_self_rfsh[u_cs] || do_power_down[u_cs])
power_saving_cnt <= bank_timer_counter_offset;
else if (power_saving_cnt != {power_saving_counter_width{1'b1}})
power_saving_cnt <= power_saving_cnt + 1'b1;
end
end
// do power down and self refresh register
always @ (*)
begin
int_do_power_down = do_power_down[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_power_down_r1 <= 1'b0;
int_do_power_down_r2 <= 1'b0;
end
else
begin
int_do_power_down_r1 <= int_do_power_down;
int_do_power_down_r2 <= int_do_power_down_r1;
end
end
always @ (*)
begin
int_do_self_refresh = do_self_rfsh[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_self_refresh_r1 <= 1'b0;
int_do_self_refresh_r2 <= 1'b0;
int_do_self_refresh_r3 <= 1'b0;
end
else
begin
int_do_self_refresh_r1 <= int_do_self_refresh;
int_do_self_refresh_r2 <= int_do_self_refresh_r1;
int_do_self_refresh_r3 <= int_do_self_refresh_r2;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
registered_reset <= 0;
else
registered_reset <= 1;
end
// exit power saving mode, power down and self refresh need to be at least 3 clock cycle before exiting
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_exit_power_saving_ready <= 1'b0;
end
else
begin
if (!registered_reset) // we want to reset to high
int_exit_power_saving_ready <= 1'b1;
else if (( int_do_power_down) && (!int_do_power_down_r1)) // positive edge detector but late by one clock cycle
int_exit_power_saving_ready <= 1'b0;
else if (( int_do_power_down_r1) && (!int_do_power_down_r2))
int_exit_power_saving_ready <= 1'b1;
else if (( int_do_self_refresh ) && (!int_do_self_refresh_r1 )) // positive edge detector
int_exit_power_saving_ready <= 1'b0;
else if (( int_do_self_refresh_r1 ) && (!int_do_self_refresh_r2 ))
int_exit_power_saving_ready <= 1'b0;
else if (( int_do_self_refresh_r2 ) && (!int_do_self_refresh_r3 ))
int_exit_power_saving_ready <= 1'b1;
end
end
// stall_chip output signal
always @ (*)
begin
if (cfg_rank_timer_output_reg)
begin
stall_chip[u_cs] = int_stall_chip[u_cs] | int_stall_chip_combi[u_cs];
end
else
begin
stall_chip[u_cs] = int_stall_chip[u_cs];
end
end
// int_stall_chip_combi signal, we need to issue stall chip one clock cycle earlier to rank timer
// because rank timer is using a register output
always @ (*)
begin
if (state == idle)
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
// command issuing state machine
always @(posedge ctl_clk, negedge ctl_reset_n)
begin : fsm
if (!ctl_reset_n)
begin
state <= init;
int_stall_chip[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
do_power_down[u_cs] <= 1'b0;
do_deep_pdown[u_cs] <= 1'b0;
do_self_rfsh_req[u_cs] <= 1'b0;
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
do_pch_all_req[u_cs] <= 1'b0;
do_refresh_req[u_cs] <= 1'b0;
afi_ctl_refresh_done[u_cs] <= 1'b0;
afi_ctl_long_idle[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
end
else
case(state)
init :
if (ctl_cal_success == 1'b1)
begin
state <= idle;
int_stall_chip[u_cs] <= 1'b0;
end
else
begin
state <= init;
int_stall_chip[u_cs] <= 1'b1;
end
idle :
begin
do_pch_all_req[u_cs] <= 1'b0;
if (do_zqcal_req[u_cs])
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
else if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= refresh;
else
state <= pchall;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= selfrfsh;
else
state <= pchall;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= deeppdn;
else
state <= pchall;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
state <= pdown;
else
state <= pchall;
end
else if (int_stall_chip[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
int_stall_chip[u_cs] <= 1'b0;
end
pchall :
begin
if (refresh_chip_req[u_cs] | self_refresh_chip_req[u_cs] | power_down_chip_req_combi[u_cs])
begin
if (do_precharge_all[u_cs] || all_banks_closed[u_cs])
begin
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (refresh_chip_req[u_cs])
state <= refresh;
else if (self_refresh_chip_req[u_cs])
state <= selfrfsh;
else state <= pdown;
end
else if (refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&refresh_chip_req)==(~all_banks_closed&tcom_not_running&refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (self_refresh_chip_req[u_cs])
begin
if ((~all_banks_closed&self_refresh_chip_req)==(~all_banks_closed&tcom_not_running&self_refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (&tcom_not_running && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= idle;
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
refresh :
begin
if (do_refresh[u_cs])
begin
do_refresh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking && &do_refresh)
state <= dqstrk;
else if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= pdown;
else
state <= idle;
end
else if (refresh_chip_req[u_cs])
begin
if (!all_banks_closed[u_cs])
state <= pchall;
else if (refresh_chip_req==(can_refresh&refresh_chip_req))
begin
do_refresh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= idle;
stall_arbiter[u_cs] <= 1'b0;
end
end
dqstrk :
begin
if (!dqstrk_exit[u_cs] && !afi_ctl_refresh_done[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_refresh_done[u_cs] <= 1'b1;
else if (!dqstrk_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_refresh_done[u_cs]) // stall until seq_busy is deasserted
dqstrk_exit[u_cs] <= 1;
else if (dqstrk_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_refresh_done[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
if (!refresh_chip_req[u_cs] && power_down_chip_req_combi[u_cs])
state <= pdown;
else
state <= idle;
end
end
dqslong :
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
if (!dqslong_exit[u_cs] && !afi_ctl_long_idle[u_cs] && power_saving_enter_ready[u_cs])
afi_ctl_long_idle[u_cs] <= 1'b1;
else if (!dqslong_exit[u_cs] && afi_seq_busy_r2[u_cs] && afi_ctl_long_idle[u_cs])
dqslong_exit[u_cs] <= 1;
else if (dqslong_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_long_idle[u_cs] <= 1'b0;
dqslong_exit[u_cs] <= 1'b0;
state <= idle;
end
end
pdown :
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs] && can_exit_power_saving_mode[u_cs])
begin
state <= refresh;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (!power_down_chip_req_combi[u_cs] && can_exit_power_saving_mode[u_cs])
begin
if (self_refresh_chip_req[u_cs])
state <= selfrfsh;
else
state <= idle;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (&can_power_down && !(|refresh_chip_req))
begin
do_power_down[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
else
state <= pdown;
end
deeppdn :
begin
if (!deep_pdown_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking)
state <= dqslong;
else
state <= idle;
end
else if (can_deep_pdown[u_cs] && !do_precharge_all[u_cs])
begin
do_deep_pdown[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
selfrfsh :
begin
if (!all_banks_closed[u_cs])
state <= pchall;
else if (!self_refresh_chip_req[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_self_rfsh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_type == `mmr_type_ddr3) // ddr3
begin
state <= zqcal;
doing_zqcal[u_cs] <= 1'b1;
end
else if (cfg_enable_dqs_tracking && &do_self_rfsh)
state <= dqslong;
else
state <= idle;
end
else if (self_refresh_chip_req==(can_self_rfsh&self_refresh_chip_req) && !(|do_precharge_all))
begin
do_self_rfsh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
zqcal :
begin
if (cs_zq_cal_req[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
if (cfg_enable_dqs_tracking && &cs_zq_cal_req)
state <= dqslong;
else
state <= idle;
end
end
default : state <= idle;
endcase
end
// sideband state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sideband_state <= idle;
int_enter_power_saving_ready <= 1'b0;
int_zq_cal_req <= 1'b0;
end
else
begin
case (sideband_state)
idle :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_pch_all_to_valid)
int_enter_power_saving_ready <= 1'b1;
else
int_enter_power_saving_ready <= 1'b0;
if (do_precharge_all[u_cs])
begin
int_enter_power_saving_ready <= 1'b0;
end
if (do_refresh[u_cs])
begin
sideband_state <= arf;
int_enter_power_saving_ready <= 1'b0;
end
if (do_self_rfsh[u_cs])
begin
sideband_state <= srf;
int_enter_power_saving_ready <= 1'b0;
end
if (do_power_down[u_cs])
begin
sideband_state <= pdn;
int_enter_power_saving_ready <= 1'b0;
end
end
arf :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_arf_to_valid)
begin
sideband_state <= idle;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= arf;
int_enter_power_saving_ready <= 1'b0;
end
end
srf :
begin
// zq request to state machine
if (power_saving_cnt == t_param_srf_to_zq_cal) // only one cycle
int_zq_cal_req <= 1'b1;
else
int_zq_cal_req <= 1'b0;
if (!do_self_rfsh[u_cs] && power_saving_cnt >= t_param_srf_to_valid)
begin
sideband_state <= idle;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= srf;
int_enter_power_saving_ready <= 1'b0;
end
end
pdn :
begin
int_zq_cal_req <= 1'b0;
if (!do_power_down[u_cs] && power_saving_cnt >= t_param_pdn_to_valid)
begin
sideband_state <= idle;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= pdn;
int_enter_power_saving_ready <= 1'b0;
end
end
default :
begin
sideband_state <= idle;
end
endcase
end
end
end
endgenerate
/*------------------------------------------------------------------------------
refresh request
------------------------------------------------------------------------------*/
generate
genvar s_cs;
for (s_cs = 0;s_cs < cfg_mem_if_chip;s_cs = s_cs + 1)
begin : auto_refresh_logic_per_chip
reg [arf_counter_width - 1 : 0] refresh_cnt;
// refresh counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_cnt <= 0;
end
else
begin
if (do_refresh[s_cs])
refresh_cnt <= 3;
else if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
refresh_cnt <= {arf_counter_width{1'b1}};
else if (refresh_cnt != {arf_counter_width{1'b1}})
refresh_cnt <= refresh_cnt + 1'b1;
end
end
// refresh request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cs_refresh_req [s_cs] <= 1'b0;
end
else
begin
if (do_refresh[s_cs] || do_self_rfsh[s_cs])
cs_refresh_req [s_cs] <= 1'b0;
else if (refresh_cnt >= t_param_arf_period)
cs_refresh_req [s_cs] <= 1'b1;
else if (self_rfsh_req && |self_rfsh_chip && !self_rfsh_req_r)
cs_refresh_req [s_cs] <= 1'b1;
else
cs_refresh_req [s_cs] <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
power down request
------------------------------------------------------------------------------*/
// register no command signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
no_command_r1 <= 1'b0;
end
else
begin
no_command_r1 <= tbp_empty;
end
end
// power down counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_cnt <= 0;
end
else
begin
if ((!tbp_empty && no_command_r1) || self_rfsh_req) // negative edge detector
power_down_cnt <= 3;
else if (tbp_empty && power_down_cnt != {pdn_counter_width{1'b1}} && ctl_cal_success)
power_down_cnt <= power_down_cnt + 1'b1;
end
end
// power down request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_chip_req <= 0;
end
else
begin
if (t_param_pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
power_down_chip_req <= 0;
else
begin
if (!tbp_empty || self_rfsh_req) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
power_down_chip_req <= 0;
else if (power_down_chip_req == 0)
begin
if (power_down_cnt >= t_param_pdn_period && !(|doing_zqcal))
power_down_chip_req <= {cfg_mem_if_chip{1'b1}};
else
power_down_chip_req <= 0;
end
else if (!(power_down_cnt >= t_param_pdn_period))
power_down_chip_req <= 0;
end
end
end
assign power_down_chip_req_combi = power_down_chip_req & {cfg_mem_if_chip{tbp_empty}} & {cfg_mem_if_chip{~(|refresh_chip_req)}};
/*------------------------------------------------------------------------------
[end] power saving rank monitor
------------------------------------------------------------------------------*/
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//
//
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_pcie_hard_ip_reset_controller
#(
parameter link_width = 4,
parameter cyclone4 = 0
)
(
input pld_clk,
input pcie_rstn, // npor
input [39:0] test_in,
input [4:0] ltssm,
input pll_locked,
input busy_altgxb_reconfig,
output reg srst,
output reg crst,
input l2_exit,
input hotrst_exit,
input dlup_exit,
output reset_n_out,
input [link_width-1:0] rx_pll_locked,
input [link_width-1:0] rx_freqlocked,
input [link_width-1:0] rx_signaldetect,
input rc_inclk_eq_125mhz,
output txdigitalreset,
output rxanalogreset,
output rx_digitalreset_serdes,
input refclk,
output clk250_out,
output clk500_out,
output clk250_export,
output clk500_export,
output clk125_export
);
wire reset_n;
wire npor;
reg [ 10: 0] rsnt_cntn;
reg [4:0] ltssm_reg;
reg reset_n_rr; /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */
reg reset_n_r; /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */
reg [ 4: 0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
reg app_rstn;
reg app_rstn0;
reg srst0;
reg crst0;
wire test_sim;
wire [7:0] rx_pll_locked_8;
wire [7:0] rx_freqlocked_8;
wire [7:0] rx_signaldetect_8;
wire use_c4gx_serdes;
wire otb0;
wire otb1;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign test_sim = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge reset_n_rr)
begin
if (reset_n_rr == 0)
begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end
else
begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge reset_n_rr)
begin
if (reset_n_rr == 0)
dl_ltssm_r <= 0;
else
dl_ltssm_r <= ltssm;
end
assign rx_pll_locked_8 = {{(8-link_width){1'b1}}, rx_pll_locked[link_width-1:0]};
assign rx_freqlocked_8 = {{(8-link_width){1'b1}}, rx_freqlocked[link_width-1:0]};
assign rx_signaldetect_8 = {{(8-link_width){1'b0}}, rx_signaldetect[link_width-1:0]};
assign npor = pcie_rstn;
generate if (cyclone4 == 1)
assign use_c4gx_serdes = 1'b1;
else
assign use_c4gx_serdes = 1'b0;
endgenerate
assign reset_n_out = app_rstn;
assign reset_n = npor;
//reset counter
always @(posedge pld_clk or negedge reset_n_rr)
begin
if (reset_n_rr == 0)
rsnt_cntn <= 0;
else if (exits_r == 1'b1)
rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024)
rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge reset_n_rr)
begin
if (reset_n_rr == 0)
begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end
else if (exits_r == 1'b1)
begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end
else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32))
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
else // synthesis translate_on
if (rsnt_cntn == 11'd1024)
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//reset Synchronizer to PCIe clock
always @(posedge pld_clk or negedge reset_n)
begin
if (reset_n == 0)
begin
reset_n_r <= 0;
reset_n_rr <= 0;
end
else
begin
reset_n_r <= 1;
reset_n_rr <= reset_n_r;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge reset_n_rr)
begin
if (reset_n_rr == 0)
begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end
else
begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
/// Instantiate the reset controller
altpcie_rs_serdes altgx_reset(
.pld_clk(pld_clk),
.test_in(test_in),
.ltssm(ltssm),
.npor(pcie_rstn),
.pll_locked(pll_locked),
.busy_altgxb_reconfig(busy_altgxb_reconfig),
.rx_pll_locked(rx_pll_locked_8),
.rx_freqlocked(rx_freqlocked_8),
.rx_signaldetect(rx_signaldetect_8),
.use_c4gx_serdes(use_c4gx_serdes),
.fifo_err(1'b0),
.rc_inclk_eq_125mhz(rc_inclk_eq_125mhz),
.txdigitalreset(txdigitalreset),
.rxanalogreset(rxanalogreset),
.rxdigitalreset(rx_digitalreset_serdes),
.detect_mask_rxdrst(1'b0)
);
//////////////// SIMULATION-ONLY CONTENTS
//synthesis translate_off
altpcie_pll_100_250 refclk_to_250mhz
(
.areset (1'b0),
.c0 (clk250_out),
.inclk0 (refclk)
);
altpcie_pll_125_250 pll_250mhz_to_500mhz
(
.areset (1'b0),
.c0 (clk500_out),
.inclk0 (clk250_out)
);
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign pipe_mode_int = 0;
//synthesis read_comments_as_HDL off
assign clk250_export = clk250_out;
assign clk500_export = clk500_out;
endmodule
|
// (c) 2001-2018 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altera_avalon_i2c_fifo #(
parameter dsize = 8,
parameter fifo_depth = 256,
parameter fifo_depth_log2 = 8,
parameter latency = 2
) (
input clk,
input rst_n,
input s_rst,
input [dsize-1:0] wdata,
input put,
input get,
output full,
output empty,
output empty_dly,
output [fifo_depth_log2:0] navail,
output [dsize-1:0] rdata
);
reg [fifo_depth_log2-1:0] write_address;
reg [fifo_depth_log2-1:0] read_address;
reg [fifo_depth_log2:0] internal_used;
reg empty_d1;
reg empty_d2;
wire internal_full;
wire internal_empty;
wire [(dsize/8)-1:0] write_byteenables;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
write_address <= 0;
end
else
begin
if (s_rst)
begin
write_address <= 0;
end
else if (put == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
read_address <= 0;
end
else
begin
if (s_rst)
begin
read_address <= 0;
end
else if (get == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
assign write_byteenables = {(dsize/8){1'b1}};
// todo: change this to an inferrered ram when quartus ii supports byte enables for inferred ram
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (put),
.byteena_a (write_byteenables),
.data_a (wdata),
.address_a (write_address),
.q_b (rdata),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "dual_port"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "dont_care";
defparam the_dp_ram.power_up_uninitialized = "true";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = dsize;
defparam the_dp_ram.width_b = dsize;
defparam the_dp_ram.widthad_a = fifo_depth_log2;
defparam the_dp_ram.widthad_b = fifo_depth_log2;
defparam the_dp_ram.width_byteena_a = (dsize/8);
defparam the_dp_ram.numwords_a = fifo_depth;
defparam the_dp_ram.numwords_b = fifo_depth;
defparam the_dp_ram.address_reg_b = "clock0";
defparam the_dp_ram.outdata_reg_b = (latency == 2)? "clock0" : "unregistered";
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
internal_used <= 0;
end
else
begin
if (s_rst)
begin
internal_used <= 0;
end
else
begin
case ({put, get})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign navail = internal_used; // this signal reflects the number of words in the fifo
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
empty_d1 <= 1'b1;
empty_d2 <= 1'b1;
end
else begin
empty_d1 <= empty;
empty_d2 <= empty_d1;
end
end
assign empty_dly = empty | empty_d1 | empty_d2;
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = "",
parameter ENABLE_BYTEENABLE = 0,
parameter BYTEENABLE_WIDTH = 4,
parameter WAIT_FOR_LOCK = 1
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
//conditional input
input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
);
localparam NM28_START_REG = 6'b000010;
localparam NM20_START_REG = 9'b000000000;
localparam NM20_MIFSTART_ADDR = 9'b000010000;
localparam MIF_STATE_DONE = 2'b00;
localparam MIF_STATE_START = 2'b01;
localparam MIF_STATE_BUSY = 2'b10;
wire mgmt_byteenable_write;
assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
mgmt_write;
generate
if (device_family == "Arria 10")
begin:nm20_reconfig
if(ENABLE_MIF == 1)
begin:mif_reconfig_20nm // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
//wire mif_user_start; // start signal provided by user to start mif
//reg user_start;
reg [1:0] mif_curstate;
reg [1:0] mif_nextstate;
wire mif_start; //start signal to mif reader
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
//mif base addr is initially specified by the user
assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
//MIF statemachine
always @(posedge mgmt_clk)
begin
if(mgmt_reset)
mif_curstate <= MIF_STATE_DONE;
else
mif_curstate <= mif_nextstate;
end
always @(*)
begin
case (mif_curstate)
MIF_STATE_DONE:
begin
if(mif_start)
mif_nextstate <= MIF_STATE_START;
else
mif_nextstate <= MIF_STATE_DONE;
end
MIF_STATE_START:
begin
mif_nextstate <= MIF_STATE_BUSY;
end
MIF_STATE_BUSY:
begin
if(mif_busy)
mif_nextstate <= MIF_STATE_BUSY;
else
mif_nextstate <= MIF_STATE_DONE;
end
endcase
end
//Mif muxes
always @(*)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
//user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
end
end
twentynm_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) twentynm_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_waitrequest(reconfig_mgmt_waitrequest),
//.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(mif_start),
//outputs
.mif_busy(mif_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_address(reconfig_mgmt_addr),
.mgmt_writedata(reconfig_mgmt_writedata),
// Outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end // End generate reconfig with MIF
else
begin:reconfig_core_20nm
twentynm_iopll_reconfig_core
#(
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
) twentynm_iopll_reconfig_core_inst (
// Inputs
.mgmt_clk(mgmt_clk),
.mgmt_rst_n(~mgmt_reset),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_address(mgmt_address),
.mgmt_writedata(mgmt_writedata),
// Outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
// PLL Conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
end
end // 20nm reconfig
else
begin:NM28_reconfig
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_byteenable_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
end // End 28nm Reconfig
endgenerate
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reset_out
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
wire merged_reset;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out)
);
end
endgenerate
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title :
//
// File : alt_ddrx_bank_timer_info.v
//
// Abstract :
///////////////////////////////////////////////////////////////////////////////
module alt_ddrx_bank_timer_info #
( parameter
ACT_TO_RDWR_WIDTH = 0, // these parameters need to be set for this module to work correctly
ACT_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
ACT_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
RD_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
WR_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
RD_AP_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
WR_AP_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
PCH_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
BANK_TIMER_COUNTER_OFFSET = 3,
MEM_IF_ROW_WIDTH = 16,
CLOSE_PAGE_POLICY = 1
)
(
ctl_clk,
ctl_reset_n,
// timing information
act_to_rdwr,
act_to_act,
act_to_pch,
rd_to_pch,
wr_to_pch,
rd_ap_to_act,
wr_ap_to_act,
pch_to_act,
less_than_x2_act_to_rdwr,
// inputs
open,
close,
read,
write,
row_addr,
// outputs
current_state,
current_row,
rdwr_ready,
act_ready,
pch_ready
);
input ctl_clk;
input ctl_reset_n;
// timing information
input [ACT_TO_RDWR_WIDTH - 1 : 0] act_to_rdwr;
input [ACT_TO_ACT_WIDTH - 1 : 0] act_to_act;
input [ACT_TO_PCH_WIDTH - 1 : 0] act_to_pch;
input [RD_TO_PCH_WIDTH - 1 : 0] rd_to_pch;
input [WR_TO_PCH_WIDTH - 1 : 0] wr_to_pch;
input [RD_AP_TO_ACT_WIDTH - 1 : 0] rd_ap_to_act;
input [WR_AP_TO_ACT_WIDTH - 1 : 0] wr_ap_to_act;
input [PCH_TO_ACT_WIDTH - 1 : 0] pch_to_act;
input less_than_x2_act_to_rdwr;
// inputs
input open;
input close;
input read;
input write;
input [MEM_IF_ROW_WIDTH - 1 : 0] row_addr;
// outputs
output current_state; // 0/1 represents IDLE/ACTIVE state
output [MEM_IF_ROW_WIDTH - 1 : 0] current_row;
output rdwr_ready;
output act_ready;
output pch_ready;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Registers & Wires
------------------------------------------------------------------------------*/
localparam ACT_COUNTER_WIDTH = ACT_TO_ACT_WIDTH; // similar to act_to_act width
localparam GENERAL_COUNTER_WIDTH = 6; // 0 - 63, should be enough for all timing values
reg current_state;
reg [MEM_IF_ROW_WIDTH - 1 : 0] current_row;
reg rdwr_ready;
reg act_ready;
reg pch_ready;
reg doing_read;
reg doing_auto_precharge;
reg doing_precharge;
reg int_act_to_act_ready;
reg int_act_to_pch_ready;
reg int_rdwr_to_valid_ready;
reg [ACT_COUNTER_WIDTH - 1 : 0] act_counter;
reg [GENERAL_COUNTER_WIDTH - 1 : 0] general_counter;
/*------------------------------------------------------------------------------
[END] Registers & Wires
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] General Logics
------------------------------------------------------------------------------*/
// General counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_counter <= 0;
end
else
begin
if (open)
act_counter <= BANK_TIMER_COUNTER_OFFSET;
else if (act_counter != {ACT_COUNTER_WIDTH{1'b1}})
act_counter <= act_counter + 1'b1;
end
end
// Read write counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
general_counter <= 0;
end
else
begin
if (read || write || close)
general_counter <= BANK_TIMER_COUNTER_OFFSET;
else if (general_counter != {GENERAL_COUNTER_WIDTH{1'b1}})
general_counter <= general_counter + 1'b1;
end
end
// keep track of read/write command
// '1' during read
// '0' during write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read <= 1'b0;
else
begin
if (write)
doing_read <= 1'b0;
else if (read)
doing_read <= 1'b1;
end
end
// keep track of precharge command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
else
begin
if (close)
begin
if (read || write)
begin
doing_auto_precharge <= 1'b1;
doing_precharge <= 1'b0;
end
else
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b1;
end
end
else if (open)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Bank Status
------------------------------------------------------------------------------*/
// Store current state, 0 for IDLE and 1 for ACTIVE
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_state <= 1'b0;
end
else
begin
if (open)
current_state <= 1'b1;
else if (close)
current_state <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT to RD/WR (tRCD)
------------------------------------------------------------------------------*/
// keep track of tRCD
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_ready <= 1'b0;
end
else
begin
if (close)
rdwr_ready <= 1'b0;
else if (open && less_than_x2_act_to_rdwr)
rdwr_ready <= 1'b1;
else if (current_state && act_counter >= act_to_rdwr) // only enable after page opened
rdwr_ready <= 1'b1;
else
rdwr_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT to ACT (tRC)
------------------------------------------------------------------------------*/
// keep track of tRC
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_act_ready <= 1'b1;
end
else
begin
if (open) // immediately de-assert act_ready after an activate is issued to a bank
int_act_to_act_ready <= 1'b0;
else if (act_counter >= act_to_act)
int_act_to_act_ready <= 1'b1;
else
int_act_to_act_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
RD/WR(AP) to VALID
------------------------------------------------------------------------------*/
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_rdwr_to_valid_ready <= 1'b0;
end
else
begin
if (close)
int_rdwr_to_valid_ready <= 1'b0; // deassert immediately after close signal detected
else
begin
if (doing_precharge && general_counter >= pch_to_act) // PCH to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_precharge)
begin
if (!doing_read && doing_auto_precharge && general_counter >= wr_ap_to_act) // WRAP to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && doing_auto_precharge && general_counter >= rd_ap_to_act) // RDAP to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_read && !doing_auto_precharge && general_counter >= wr_to_pch) // WR to PCH
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && !doing_auto_precharge && general_counter >= rd_to_pch) // RD to PCH
int_rdwr_to_valid_ready <= 1'b1;
else
int_rdwr_to_valid_ready <= 1'b0;
end
else
int_rdwr_to_valid_ready <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
ACT to PCH (tRAS)
------------------------------------------------------------------------------*/
// keep track of tRAS
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_pch_ready <= 1'b0;
end
else
begin
if (open) // immediately de-assert pch_ready after an activate is issued to a bank
int_act_to_pch_ready <= 1'b0;
else if (act_counter >= act_to_pch)
int_act_to_pch_ready <= 1'b1;
else
int_act_to_pch_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT/PCH Ready
------------------------------------------------------------------------------*/
always @ (*)
begin
act_ready = int_act_to_act_ready & int_rdwr_to_valid_ready;
end
always @ (*)
begin
pch_ready = int_act_to_pch_ready & int_rdwr_to_valid_ready;
end
/*------------------------------------------------------------------------------
[END] General Logics
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
// OPP /*------------------------------------------------------------------------------
// OPP
// OPP [START] Open Page Policy Logics
// OPP
// OPP ------------------------------------------------------------------------------*/
// OPP generate
// OPP if (!CLOSE_PAGE_POLICY) // only enable during open page policy
// OPP begin
// OPP // Store row information
// OPP always @ (posedge ctl_clk or negedge ctl_reset_n)
// OPP begin
// OPP if (!ctl_reset_n)
// OPP begin
// OPP current_row <= 0;
// OPP end
// OPP else
// OPP begin
// OPP // update when there is an activate
// OPP if (open)
// OPP current_row <= row_addr;
// OPP end
// OPP end
// OPP end
// OPP endgenerate
// OPP /*------------------------------------------------------------------------------
// OPP
// OPP [END] Open Page Policy Logics
// OPP
// OPP ------------------------------------------------------------------------------*/
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash (
// To/From System
clock,
reset_n,
// To/From Avalon_MM data slave interface
avmm_data_read,
avmm_data_write,
avmm_data_addr,
avmm_data_writedata,
avmm_data_burstcount,
avmm_data_waitrequest,
avmm_data_readdatavalid,
avmm_data_readdata,
// To/From Avalon_MM csr slave interface
avmm_csr_read,
avmm_csr_write,
avmm_csr_addr,
avmm_csr_writedata,
avmm_csr_readdata
);
parameter DEVICE_FAMILY = "MAX 10";
parameter PART_NAME = "Unknown";
parameter IS_DUAL_BOOT = "False";
parameter IS_ERAM_SKIP = "False";
parameter IS_COMPRESSED_IMAGE = "False";
parameter INIT_FILENAME = "";
// simulation only start
parameter DEVICE_ID = "08";
parameter INIT_FILENAME_SIM = "";
// simulation only end
parameter PARALLEL_MODE = 0;
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter AVMM_CSR_DATA_WIDTH = 32;
parameter AVMM_DATA_DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
parameter FLASH_DATA_WIDTH = 32;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read. only need in parallel mode.
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read. only need in parallel mode.
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment. only need in parallel mode.
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter MIN_UFM_VALID_ADDR = 1;
parameter MAX_UFM_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
// To/From System
input clock;
input reset_n;
// To/From Avalon_MM data slave interface
input avmm_data_read;
input avmm_data_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
input [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
output avmm_data_waitrequest;
output avmm_data_readdatavalid;
output [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
// To/From Avalon_MM csr slave interface
input avmm_csr_read;
input avmm_csr_write;
input avmm_csr_addr;
input [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
output [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
wire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
wire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
wire [31:0] csr_control_wire;
wire [9:0] csr_status_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
wire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
wire flash_busy;
wire flash_se_pass;
wire flash_sp_pass;
wire flash_osc;
wire flash_xe_ye;
wire flash_se;
wire flash_arclk;
wire flash_arshft;
wire flash_drclk;
wire flash_drshft;
wire flash_drdin;
wire flash_nprogram;
wire flash_nerase;
wire flash_par_en;
wire flash_xe_ye_wire;
wire flash_se_wire;
assign avmm_data_readdata = avmm_data_readdata_wire;
generate
if (READ_AND_WRITE_MODE == 0) begin
assign avmm_csr_readdata = 32'hffffffff;
assign csr_control_wire = 32'h3fffffff;
end
else begin
assign avmm_csr_readdata = avmm_csr_readdata_wire;
end
endgenerate
generate
if (DEVICE_ID == "02" || DEVICE_ID == "01") begin
assign flash_par_en = 1'b1;
assign flash_xe_ye = 1'b1;
assign flash_se = 1'b1;
end
else begin
assign flash_par_en = PARALLEL_MODE[0];
assign flash_xe_ye = flash_xe_ye_wire;
assign flash_se = flash_se_wire;
end
endgenerate
generate
if (READ_AND_WRITE_MODE) begin
// -------------------------------------------------------------------
// Instantiate a Avalon_MM csr slave controller
// -------------------------------------------------------------------
altera_onchip_flash_avmm_csr_controller avmm_csr_controller (
// To/From System
.clock(clock),
.reset_n(reset_n),
// To/From Avalon_MM csr slave interface
.avmm_read(avmm_csr_read),
.avmm_write(avmm_csr_write),
.avmm_addr(avmm_csr_addr),
.avmm_writedata(avmm_csr_writedata),
.avmm_readdata(avmm_csr_readdata_wire),
// To/From Avalon_MM data slave interface
.csr_control(csr_control_wire),
.csr_status(csr_status_wire)
);
end
endgenerate
// -------------------------------------------------------------------
// Instantiate a Avalon_MM data slave controller
// -------------------------------------------------------------------
altera_onchip_flash_avmm_data_controller # (
.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
.MIN_VALID_ADDR (MIN_VALID_ADDR),
.MAX_VALID_ADDR (MAX_VALID_ADDR),
.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
.SECTOR1_MAP (SECTOR1_MAP),
.SECTOR2_MAP (SECTOR2_MAP),
.SECTOR3_MAP (SECTOR3_MAP),
.SECTOR4_MAP (SECTOR4_MAP),
.SECTOR5_MAP (SECTOR5_MAP),
.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET)
) avmm_data_controller (
// To/From System
.clock(clock),
.reset_n(reset_n),
// To/From Flash IP interface
.flash_busy(flash_busy),
.flash_se_pass(flash_se_pass),
.flash_sp_pass(flash_sp_pass),
.flash_osc(flash_osc),
.flash_drdout(flash_drdout_wire),
.flash_xe_ye(flash_xe_ye_wire),
.flash_se(flash_se_wire),
.flash_arclk(flash_arclk),
.flash_arshft(flash_arshft),
.flash_drclk(flash_drclk),
.flash_drshft(flash_drshft),
.flash_drdin(flash_drdin),
.flash_nprogram(flash_nprogram),
.flash_nerase(flash_nerase),
.flash_ardin(flash_ardin_wire),
// To/From Avalon_MM data slave interface
.avmm_read(avmm_data_read),
.avmm_write(avmm_data_write),
.avmm_addr(avmm_data_addr),
.avmm_writedata(avmm_data_writedata),
.avmm_burstcount(avmm_data_burstcount),
.avmm_waitrequest(avmm_data_waitrequest),
.avmm_readdatavalid(avmm_data_readdatavalid),
.avmm_readdata(avmm_data_readdata_wire),
// To/From Avalon_MM csr slave interface
.csr_control(csr_control_wire),
.csr_status(csr_status_wire)
);
// -------------------------------------------------------------------
// Instantiate wysiwyg for onchip flash block
// -------------------------------------------------------------------
altera_onchip_flash_block # (
.DEVICE_FAMILY (DEVICE_FAMILY),
.PART_NAME (PART_NAME),
.IS_DUAL_BOOT (IS_DUAL_BOOT),
.IS_ERAM_SKIP (IS_ERAM_SKIP),
.IS_COMPRESSED_IMAGE (IS_COMPRESSED_IMAGE),
.INIT_FILENAME (INIT_FILENAME),
.MIN_VALID_ADDR (MIN_VALID_ADDR),
.MAX_VALID_ADDR (MAX_VALID_ADDR),
.MIN_UFM_VALID_ADDR (MIN_UFM_VALID_ADDR),
.MAX_UFM_VALID_ADDR (MAX_UFM_VALID_ADDR),
.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
// simulation only start
.DEVICE_ID (DEVICE_ID),
.INIT_FILENAME_SIM (INIT_FILENAME_SIM)
// simulation only end
) altera_onchip_flash_block (
.xe_ye(flash_xe_ye),
.se(flash_se),
.arclk(flash_arclk),
.arshft(flash_arshft),
.ardin(flash_ardin_wire),
.drclk(flash_drclk),
.drshft(flash_drshft),
.drdin(flash_drdin),
.nprogram(flash_nprogram),
.nerase(flash_nerase),
.nosc_ena(1'b0),
.par_en(flash_par_en),
.drdout(flash_drdout_wire),
.busy(flash_busy),
.se_pass(flash_se_pass),
.sp_pass(flash_sp_pass),
.osc(flash_osc)
);
endmodule //altera_onchip_flash
//VALID FILE
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module counts which bits for serial audio transfers. the module *
* assume that the data format is i2s, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module altera_up_audio_bit_counter (
// inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// bidirectionals
// outputs
counting
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
parameter bit_counter_init = 5'h0f;
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// bidirectionals
// outputs
output reg counting;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
wire reset_bit_counter;
// internal registers
reg [ 4: 0] bit_counter;
// state machine registers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= bit_counter_init;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* combinational logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* internal modules *
*****************************************************************************/
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 13410
module alt_mem_ddrx_controller #
( parameter
// Local interface parameters
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_LOCAL_DATA_WIDTH = 80, // Maximum DQ width of 40
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_IF_TYPE = "AVALON",
// Memory interface parameters
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 15,
CFG_MEM_IF_COL_WIDTH = 12,
CFG_MEM_IF_ADDR_WIDTH = 15,
CFG_MEM_IF_CKE_WIDTH = 2,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_MEM_IF_DM_WIDTH = 5,
// Controller parameters
CFG_DWIDTH_RATIO = 2,
CFG_ODT_ENABLED = 1, // NOTICE: required?
CFG_OUTPUT_REGD = 0, // NOTICE: un-used and will be removed
CFG_CTL_TBP_NUM = 4,
CFG_LPDDR2_ENABLED = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_ECC_MULTIPLES_16_24_40_72 = 1,
// Data path buffer & fifo parameters
CFG_WRBUFFER_ADDR_WIDTH = 6,
CFG_RDBUFFER_ADDR_WIDTH = 10,
// MMR port width
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_DEVICE_WIDTH = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
// cfg: address mapping signals
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// cfg: control signals
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_USER_RFSH = 1,
CFG_PORT_WIDTH_SELF_RFSH = 1,
CFG_PORT_WIDTH_REGDIMM_ENABLE = 1,
CFG_ENABLE_CMD_SPLIT = 1'b1, // disable this (set to 0) when using the controller with hard MPFE
// cfg: ecc signals
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
// cfg: odt
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
// cfg: ecc signals
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8,
// PHY parameters
CFG_WLAT_BUS_WIDTH = 4,
// controller read data return mode
CFG_RDATA_RETURN_MODE = "PASSTHROUGH"
)
(
// Clock and reset
ctl_clk,
ctl_reset_n,
// Command channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// Write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// Read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
itf_rd_data_id_early_valid, // only valid when CFG_RDATA_RETURN_MODE == PASSTHROUGH
// Sideband signals
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_chip,
local_deep_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
// Controller commands to the AFI interface
afi_rst_n,
afi_ba,
afi_addr,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_odt,
// Controller read and write data to the AFI interface
afi_wlat,
afi_dqs_burst,
afi_dm,
afi_wdata,
afi_wdata_valid,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
// Status and control signal to the AFI interface
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
// cfg: general
cfg_type,
cfg_interface_width, // not sure where this signal is used
cfg_burst_length,
cfg_device_width, // not sure where this signal is used
cfg_output_regd,
// cfg: address mapping signals
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// cfg: timing parameters
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_auto_pd_cycles,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_tmrd,
// cfg: extra timing parameters
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// cfg: control signals
cfg_reorder_data, // enable data reordering
cfg_starve_limit, // starvation counter limit
cfg_user_rfsh,
cfg_regdimm_enable,
// cfg: ecc signals
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_ecc_code_overwrites,
cfg_enable_no_dm,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// cfg: odt
cfg_write_odt_chip,
cfg_read_odt_chip,
// sts: ecc signals
ecc_interrupt,
sts_sbe_error,
sts_dbe_error,
sts_corr_dropped,
sts_sbe_count,
sts_dbe_count,
sts_corr_dropped_count,
sts_err_addr,
sts_corr_dropped_addr,
//calibration
cfg_cal_req,
sts_cal_fail,
sts_cal_success,
// DQS enable tracking
cfg_enable_dqs_tracking, //enable DQS enable tracking support in controller
afi_ctl_refresh_done, // Controller asserts this after tRFC is done, also acts as stall ack to phy
afi_seq_busy, // Sequencer busy signal to controller, also acts as stall request to ctlr
afi_ctl_long_idle // Controller asserts this after long period of no refresh, protocol is the same as rfsh_done
);
// General parameters
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_INT_SIZE_WIDTH = (CFG_DWIDTH_RATIO == 2) ? 4 : ((CFG_DWIDTH_RATIO == 4) ? 3 : ((CFG_DWIDTH_RATIO == 8) ? 2 : 4));
localparam CFG_CTL_QUEUE_DEPTH = 8;
localparam CFG_ENABLE_QUEUE = 0;
localparam CFG_ENABLE_BURST_MERGE = 0;
localparam CFG_CMD_GEN_OUTPUT_REG = 1; // only in effect when CFG_ENABLE_QUEUE is set to '0'
localparam CFG_CTL_ARBITER_TYPE = "ROWCOL";
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ENABLE_BURST_INTERRUPT = 0;
localparam CFG_ENABLE_BURST_TERMINATE = 0;
localparam CFG_ECC_CODE_WIDTH = 8;
localparam CFG_ECC_MULTIPLES = CFG_DWIDTH_RATIO * CFG_ECC_MULTIPLES_16_24_40_72;
localparam CFG_PARTIAL_BE_PER_WORD_ENABLE = 1;
localparam CFG_ENABLE_BURST_GEN_OUTPUT_REG = 1;
localparam CFG_DISABLE_PRIORITY = 1;
localparam CFG_REG_GRANT = (CFG_DWIDTH_RATIO == 8) ? 0 : 1; // disable grant register for better efficiency in quarter rate
localparam CFG_REG_REQ = 0;
localparam CFG_RANK_TIMER_OUTPUT_REG = 1;
localparam CFG_ECC_DEC_REG = 1;
localparam CFG_ECC_RDATA_REG = 1;
localparam CFG_ECC_ENC_REG = 1; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_WDATA_REG = 0; // only one of CFG_ECC_ENC_REG / CFG_WDATA_REG can be set to '1'
localparam CFG_DISABLE_READ_REODERING = 0;
localparam CFG_ENABLE_SHADOW_TBP = 0;
localparam CFG_CTL_SHADOW_TBP_NUM = CFG_CTL_TBP_NUM; // similar to TBP number
// Datapath buffer & fifo size calculation
localparam CFG_MAX_PENDING_RD_CMD = 16; // temporary
localparam CFG_MAX_PENDING_WR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_ERR_CMD = 8; // temporary
localparam CFG_MAX_PENDING_RD_CMD_WIDTH = log2(CFG_MAX_PENDING_RD_CMD);
localparam CFG_WRDATA_ID_WIDTH = log2(CFG_MAX_PENDING_WR_CMD);
localparam CFG_ERRCMD_FIFO_ADDR_WIDTH = log2(CFG_MAX_PENDING_ERR_CMD);
localparam CFG_RDDATA_ID_WIDTH = CFG_RDBUFFER_ADDR_WIDTH - CFG_INT_SIZE_WIDTH;
localparam CFG_DATA_ID_WIDTH = (CFG_WRDATA_ID_WIDTH >= CFG_RDDATA_ID_WIDTH) ? CFG_WRDATA_ID_WIDTH : CFG_RDDATA_ID_WIDTH;
localparam integer CFG_DATA_ID_REMAINDER = 2**(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH);
localparam CFG_WRDATA_VEC_ID_WIDTH = CFG_MAX_PENDING_WR_CMD;
// AFI
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH;
localparam CFG_DRAM_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : CFG_MEM_IF_DQS_WIDTH; // Supports single / multiple DQS group of afi_wlat
localparam CFG_LOCAL_WLAT_GROUP = (CFG_WLAT_BUS_WIDTH <= 6) ? 1 : (((CFG_LOCAL_DATA_WIDTH / CFG_DWIDTH_RATIO) == CFG_MEM_IF_DQ_WIDTH) ? CFG_MEM_IF_DQS_WIDTH : CFG_MEM_IF_DQS_WIDTH - CFG_ECC_MULTIPLES_16_24_40_72); // Determine the wlat group for local data width (without ECC code)
// Derived timing parameters width
localparam T_PARAM_ACT_TO_RDWR_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_BC_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_RD_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_RD_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_BC_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6; // temporary
localparam T_PARAM_WR_TO_PCH_WIDTH = 6; // temporary
localparam T_PARAM_WR_AP_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6; // temporary
localparam T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6; // temporary
localparam T_PARAM_ARF_TO_VALID_WIDTH = 8; // temporary
localparam T_PARAM_PDN_TO_VALID_WIDTH = 6; // temporary
localparam T_PARAM_SRF_TO_VALID_WIDTH = 10; // temporary
localparam T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10; // temporary
localparam T_PARAM_ARF_PERIOD_WIDTH = 13; // temporary
localparam T_PARAM_PDN_PERIOD_WIDTH = 16; // temporary
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
localparam integer CFG_WRDATA_ID_WIDTH_SQRD = 2**CFG_WRDATA_ID_WIDTH;
// Clock and reset
input ctl_clk;
input ctl_reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// Sideband signals
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
// Controller commands to the AFI interface
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
output [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
output [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
// Controller read and write data to the AFI interface
input [CFG_WLAT_BUS_WIDTH - 1 : 0] afi_wlat;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
output [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
output [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
output [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
input [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Status and control signal to the AFI interface
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output [CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP - 1 : 0] ctl_cal_byte_lane_sel_n ;
output [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// cfg: general
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1 : 0] cfg_output_regd;
// cfg: address mapping signals
input [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
// cfg: timing parameters
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
// cfg: extra timing parameters
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// cfg: control signals
input [CFG_PORT_WIDTH_REORDER_DATA - 1 : 0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
input [CFG_PORT_WIDTH_USER_RFSH - 1 : 0] cfg_user_rfsh;
input [CFG_PORT_WIDTH_REGDIMM_ENABLE - 1 : 0] cfg_regdimm_enable;
// cfg: ecc signals
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites;
// cfg: odt
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
// sts: ecc signals
output ecc_interrupt;
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// calibration signals
input cfg_cal_req;
output sts_cal_fail;
output sts_cal_success;
// DQS enable tracking
input cfg_enable_dqs_tracking;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
//==============================================================================
//
// Wires
//
//==============================================================================
// General
wire init_done = ctl_cal_success;
wire sts_cal_success = ctl_cal_success;
wire sts_cal_fail = ctl_cal_fail;
wire ctl_cal_req = cfg_cal_req;
wire [CFG_MEM_IF_DQS_WIDTH*CFG_MEM_IF_CHIP-1: 0] ctl_cal_byte_lane_sel_n = 0;
// alt_mem_ddrx_input_if
wire itf_cmd_ready;
wire itf_wr_data_ready;
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
wire cmd_valid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] cmd_address;
wire cmd_write;
wire cmd_read;
wire cmd_multicast;
wire [CFG_LOCAL_SIZE_WIDTH - 1 : 0] cmd_size;
wire cmd_priority;
wire cmd_autoprecharge;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_id;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] write_data;
wire [CFG_LOCAL_DATA_WIDTH / 8 - 1 : 0] byte_en;
wire write_data_valid;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] write_data_id;
wire local_refresh_ack;
wire local_deep_powerdn_ack;
wire local_power_down_ack;
wire local_self_rfsh_ack;
wire local_init_done;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] deep_powerdn_chip;
wire self_rfsh_req;
wire [CFG_MEM_IF_CHIP - 1 : 0] self_rfsh_chip;
// alt_mem_ddrx_cmd_gen
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM - 1 : 0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM - 1 : 0] cmd_gen_same_shadow_row_addr;
wire cmd_gen_full;
// alt_mem_ddrx_tbp
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM - 1 : 0] row_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
wire [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
wire [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
wire [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
wire [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP - 1 : 0] tbp_timer_ready;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load_index;
wire [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
// alt_mem_ddrx_arbiter
wire [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
wire [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
wire or_row_grant;
wire or_col_grant;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// alt_mem_ddrx_burst_gen
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
wire bg_interrupt_ready_combi;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
wire bg_do_lmr_read = 0;
wire bg_do_refresh_1bank = 0;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
wire bg_doing_write;
wire bg_doing_read;
wire bg_rdwr_data_valid;
wire bg_interrupt_ready;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] bg_rddataid;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
wire [ 7 : 0] bg_to_lmr = 0;
// alt_mem_ddrx_addr_cmd_wrap
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_cs_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_ras_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_cas_n;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_ba;
wire [(CFG_AFI_IF_FR_ADDR_WIDTH*(CFG_DWIDTH_RATIO / 2))- 1 : 0] afi_addr;
wire [(CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rst_n;
wire [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2)) - 1 : 0] afi_odt;
wire [CFG_AFI_IF_FR_ADDR_WIDTH - 1 : 0] lmr_opcode = 0;
// alt_mem_ddrx_rdwr_data_tmg
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_rdata_en_full;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_read;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
wire [CFG_DRAM_WLAT_GROUP - 1 : 0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH - 1 : 0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH - 1 : 0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid;
wire [CFG_DRAM_WLAT_GROUP * CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_first;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_first;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] ecc_wdata_wrdataid_last;
wire [CFG_WRDATA_ID_WIDTH_SQRD - 1 : 0] ecc_wdata_wrdataid_vector_last;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2) - 1 : 0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO - 1 : 0] afi_dm;
// alt_mem_ddrx_wdata_path
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
wire wdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] wdatap_free_id_dataid;
wire [CFG_WRDATA_ID_WIDTH - 1 : 0] wdatap_free_id_wrdataid;
wire wr_data_mem_full;
wire [CFG_CTL_TBP_NUM - 1 : 0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [(CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS) - 1 : 0] wdatap_dm;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
wire [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// alt_mem_ddrx_rdata_path
wire rdatap_free_id_valid;
wire [CFG_DATA_ID_WIDTH - 1 : 0] rdatap_free_id_dataid;
wire [CFG_RDDATA_ID_WIDTH - 1 : 0] rdatap_free_id_rddataid;
wire read_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] read_data;
wire read_data_error;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] read_data_localid;
wire errcmd_ready;
wire errcmd_valid;
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] errcmd_chipsel;
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] errcmd_bank;
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] errcmd_row;
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] errcmd_column;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] errcmd_size;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
wire rdatap_rcvd_cmd;
wire rdatap_rcvd_corr_dropped;
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES - 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
wire ecc_rdata_valid;
wire [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
wire [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
wire ecc_interrupt;
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// alt_mem_ddrx_sideband
wire rfsh_ack;
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire stall_row_arbiter;
wire stall_col_arbiter;
wire [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
wire [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
wire [CFG_CTL_TBP_NUM - 1 : 0] sb_tbp_precharge_all;
wire [CFG_MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// alt_mem_ddrx_rank_timer
wire [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_read;
wire [CFG_CTL_TBP_NUM - 1 : 0] can_write;
// alt_mem_ddrx_timing_param
wire [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
wire [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
wire [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
wire [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
wire [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
wire [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
wire [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
wire [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
wire [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
wire [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
wire [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
wire [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
wire [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
wire [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
wire [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
wire [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
wire [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
wire [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
wire [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
wire [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
wire [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
wire [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
wire [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
wire [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
wire [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
wire [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
wire [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
// Log 2 function
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
//==============================================================================
// alt_mem_ddrx_input_if
//------------------------------------------------------------------------------
//
// Input interface block
//
// Info: Includes cmd channel, and both read and write channels
// * Optional half-rate bridge logic
//
//==============================================================================
alt_mem_ddrx_input_if #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE )
)
input_if_inst
(
.itf_cmd_ready (itf_cmd_ready ),
.itf_cmd_valid (itf_cmd_valid ),
.itf_cmd (itf_cmd ),
.itf_cmd_address (itf_cmd_address ),
.itf_cmd_burstlen (itf_cmd_burstlen ),
.itf_cmd_id (itf_cmd_id ),
.itf_cmd_priority (itf_cmd_priority ),
.itf_cmd_autopercharge (itf_cmd_autopercharge ),
.itf_cmd_multicast (itf_cmd_multicast ),
.itf_wr_data_ready (itf_wr_data_ready ),
.itf_wr_data_valid (itf_wr_data_valid ),
.itf_wr_data (itf_wr_data ),
.itf_wr_data_byte_en (itf_wr_data_byte_en ),
.itf_wr_data_begin (itf_wr_data_begin ),
.itf_wr_data_last (itf_wr_data_last ),
.itf_wr_data_id (itf_wr_data_id ),
.itf_rd_data_ready (itf_rd_data_ready ),
.itf_rd_data_valid (itf_rd_data_valid ),
.itf_rd_data (itf_rd_data ),
.itf_rd_data_error (itf_rd_data_error ),
.itf_rd_data_begin (itf_rd_data_begin ),
.itf_rd_data_last (itf_rd_data_last ),
.itf_rd_data_id (itf_rd_data_id ),
.itf_rd_data_id_early (itf_rd_data_id_early ),
.itf_rd_data_id_early_valid(itf_rd_data_id_early_valid ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.cmd_id (cmd_id ),
.write_data (write_data ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_id (write_data_id ),
.byte_en (byte_en ),
.write_data_valid (write_data_valid ),
.read_data (read_data ),
.read_data_valid (read_data_valid ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.read_data_begin ( ), // NOTICE: not connected?
.read_data_last ( ), // NOTICE: not connected?
.bg_do_read (bg_do_read ),
.bg_localid (bg_localid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.local_refresh_req (local_refresh_req ),
.local_refresh_chip (local_refresh_chip ),
.local_deep_powerdn_req (local_deep_powerdn_req ),
.local_deep_powerdn_chip (local_deep_powerdn_chip ),
.local_self_rfsh_req (local_self_rfsh_req ),
.local_self_rfsh_chip (local_self_rfsh_chip ),
.local_refresh_ack (local_refresh_ack ),
.local_deep_powerdn_ack (local_deep_powerdn_ack ),
.local_power_down_ack (local_power_down_ack ),
.local_self_rfsh_ack (local_self_rfsh_ack ),
.local_init_done (local_init_done ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.self_rfsh_ack (self_rfsh_ack ),
.init_done (init_done )
);
//==============================================================================
// alt_mem_ddrx_cmd_gen
//------------------------------------------------------------------------------
//
// Command generator block
//
// Info: * generates cmd from local and internal ECC block
// * splitting and merging of all commands
// * optional queue for latency reduction purpose when no merging is required
//
//==============================================================================
alt_mem_ddrx_cmd_gen #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_SIZE_WIDTH (CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_QUEUE_DEPTH (CFG_CTL_QUEUE_DEPTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_ENABLE_QUEUE (CFG_ENABLE_QUEUE ),
.CFG_ENABLE_BURST_MERGE (CFG_ENABLE_BURST_MERGE ),
.CFG_CMD_GEN_OUTPUT_REG (CFG_CMD_GEN_OUTPUT_REG ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM )
)
cmd_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_load (tbp_load ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_multicast (cmd_gen_multicast ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.cmd_gen_full (cmd_gen_full ),
.cmd_valid (cmd_valid ),
.cmd_address (cmd_address ),
.cmd_write (cmd_write ),
.cmd_read (cmd_read ),
.cmd_id (cmd_id ),
.cmd_multicast (cmd_multicast ),
.cmd_size (cmd_size ),
.cmd_priority (cmd_priority ),
.cmd_autoprecharge (cmd_autoprecharge ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_dataid ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_dataid ),
.tbp_load_index (tbp_load_index ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.data_partial_be (data_partial_be ),
.cfg_enable_cmd_split (CFG_ENABLE_CMD_SPLIT ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width )
);
//==============================================================================
// alt_mem_ddrx_tbp
//------------------------------------------------------------------------------
//
// Timing bank pool block
//
// Info: * parallel queue in which a cmd is present
// * tracks timer and bank status information of the command it hold
// * monitor other TBPs content to update status bit in itself such
// as the autoprecharge bit
// * pass timer value to another TBP if need arises
//
//==============================================================================
alt_mem_ddrx_tbp #
(
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_SHADOW_TBP_NUM (CFG_CTL_SHADOW_TBP_NUM ),
.CFG_ENABLE_SHADOW_TBP (CFG_ENABLE_SHADOW_TBP ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_PORT_WIDTH_STARVE_LIMIT (CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_REORDER_DATA (CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_DATA_REORDERING_TYPE (CFG_DATA_REORDERING_TYPE ),
.CFG_DISABLE_READ_REODERING (CFG_DISABLE_READ_REODERING ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH )
)
tbp_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.tbp_full (tbp_full ),
.tbp_empty (tbp_empty ),
.cmd_gen_load (cmd_gen_load ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.cmd_gen_bank (cmd_gen_bank ),
.cmd_gen_row (cmd_gen_row ),
.cmd_gen_col (cmd_gen_col ),
.cmd_gen_write (cmd_gen_write ),
.cmd_gen_read (cmd_gen_read ),
.cmd_gen_size (cmd_gen_size ),
.cmd_gen_localid (cmd_gen_localid ),
.cmd_gen_dataid (cmd_gen_dataid ),
.cmd_gen_priority (cmd_gen_priority ),
.cmd_gen_rmw_correct (cmd_gen_rmw_correct ),
.cmd_gen_rmw_partial (cmd_gen_rmw_partial ),
.cmd_gen_autopch (cmd_gen_autopch ),
.cmd_gen_complete (cmd_gen_complete ),
.cmd_gen_same_chipsel_addr (cmd_gen_same_chipsel_addr ),
.cmd_gen_same_bank_addr (cmd_gen_same_bank_addr ),
.cmd_gen_same_row_addr (cmd_gen_same_row_addr ),
.cmd_gen_same_col_addr (cmd_gen_same_col_addr ),
.cmd_gen_same_read_cmd (cmd_gen_same_read_cmd ),
.cmd_gen_same_write_cmd (cmd_gen_same_write_cmd ),
.cmd_gen_same_shadow_chipsel_addr (cmd_gen_same_shadow_chipsel_addr ),
.cmd_gen_same_shadow_bank_addr (cmd_gen_same_shadow_bank_addr ),
.cmd_gen_same_shadow_row_addr (cmd_gen_same_shadow_row_addr ),
.row_req (row_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.col_req (col_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_precharge (tbp_precharge ),
.tbp_activate (tbp_activate ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_shadow_chipsel (tbp_shadow_chipsel ),
.tbp_shadow_bank (tbp_shadow_bank ),
.tbp_shadow_row (tbp_shadow_row ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.sb_do_precharge_all (sb_do_precharge_all ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.cfg_reorder_data (cfg_reorder_data ),
.tbp_load (tbp_load ),
.data_complete (data_complete ),
.cfg_starve_limit (cfg_starve_limit ),
.cfg_type (cfg_type )
);
//==============================================================================
// alt_mem_ddrx_arbiter
//------------------------------------------------------------------------------
//
// Arbiter block
//
// Info: Priority command-aging arbiter, it will grant command with priority
// first, during tie-break situation, oldest command will be granted.
// Read comment in arbiter code for more information
//
//==============================================================================
alt_mem_ddrx_arbiter #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_REG_REQ (CFG_REG_REQ ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_DISABLE_PRIORITY (CFG_DISABLE_PRIORITY )
)
arbiter_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.row_req (row_req ),
.col_req (col_req ),
.act_req (act_req ),
.pch_req (pch_req ),
.rd_req (rd_req ),
.wr_req (wr_req ),
.row_grant (row_grant ),
.col_grant (col_grant ),
.act_grant (act_grant ),
.pch_grant (pch_grant ),
.rd_grant (rd_grant ),
.wr_grant (wr_grant ),
.log2_row_grant (log2_row_grant ),
.log2_col_grant (log2_col_grant ),
.log2_act_grant (log2_act_grant ),
.log2_pch_grant (log2_pch_grant ),
.log2_rd_grant (log2_rd_grant ),
.log2_wr_grant (log2_wr_grant ),
.or_row_grant (or_row_grant ),
.or_col_grant (or_col_grant ),
.tbp_activate (tbp_activate ),
.tbp_precharge (tbp_precharge ),
.tbp_read (tbp_read ),
.tbp_write (tbp_write ),
.tbp_chipsel (tbp_chipsel ),
.tbp_bank (tbp_bank ),
.tbp_row (tbp_row ),
.tbp_col (tbp_col ),
.tbp_size (tbp_size ),
.tbp_localid (tbp_localid ),
.tbp_dataid (tbp_dataid ),
.tbp_ap (tbp_ap ),
.tbp_burst_chop (tbp_burst_chop ),
.tbp_rmw_correct (tbp_rmw_correct ),
.tbp_rmw_partial (tbp_rmw_partial ),
.tbp_age (tbp_age ),
.tbp_priority (tbp_priority ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_write (can_write ),
.can_read (can_read ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size )
);
//==============================================================================
// alt_mem_ddrx_burst_gen
//------------------------------------------------------------------------------
//
// Burst generation block
//
// Info: Create DQ/DQS burst information for AFI block
//
//==============================================================================
alt_mem_ddrx_burst_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ENABLE_BURST_INTERRUPT (CFG_ENABLE_BURST_INTERRUPT ),
.CFG_ENABLE_BURST_TERMINATE (CFG_ENABLE_BURST_TERMINATE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_ENABLE_BURST_GEN_OUTPUT_REG (CFG_ENABLE_BURST_GEN_OUTPUT_REG)
)
burst_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_burst_length (cfg_burst_length ),
.cfg_tccd (cfg_tccd ),
.arb_do_write (arb_do_write ),
.arb_do_read (arb_do_read ),
.arb_do_burst_chop (arb_do_burst_chop ),
.arb_do_burst_terminate (arb_do_burst_terminate ),
.arb_do_auto_precharge (arb_do_auto_precharge ),
.arb_do_rmw_correct (arb_do_rmw_correct ),
.arb_do_rmw_partial (arb_do_rmw_partial ),
.arb_do_activate (arb_do_activate ),
.arb_do_precharge (arb_do_precharge ),
.arb_do_precharge_all (arb_do_precharge_all ),
.arb_do_refresh (arb_do_refresh ),
.arb_do_self_refresh (arb_do_self_refresh ),
.arb_do_power_down (arb_do_power_down ),
.arb_do_deep_pdown (arb_do_deep_pdown ),
.arb_do_zq_cal (arb_do_zq_cal ),
.arb_do_lmr (arb_do_lmr ),
.arb_to_chipsel (arb_to_chipsel ),
.arb_to_chip (arb_to_chip ),
.arb_to_bank (arb_to_bank ),
.arb_to_row (arb_to_row ),
.arb_to_col (arb_to_col ),
.arb_localid (arb_localid ),
.arb_dataid (arb_dataid ),
.arb_size (arb_size ),
.bg_do_write_combi (bg_do_write_combi ),
.bg_do_read_combi (bg_do_read_combi ),
.bg_do_burst_chop_combi (bg_do_burst_chop_combi ),
.bg_do_burst_terminate_combi (bg_do_burst_terminate_combi ),
.bg_do_activate_combi (bg_do_activate_combi ),
.bg_do_precharge_combi (bg_do_precharge_combi ),
.bg_to_chip_combi (bg_to_chip_combi ),
.bg_effective_size_combi (bg_effective_size_combi ),
.bg_interrupt_ready_combi (bg_interrupt_ready_combi ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr (bg_do_lmr ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_doing_write (bg_doing_write ),
.bg_doing_read (bg_doing_read ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.bg_interrupt_ready (bg_interrupt_ready ),
.bg_localid (bg_localid ),
.bg_dataid (bg_dataid ),
.bg_size (bg_size ),
.bg_effective_size (bg_effective_size )
);
//==============================================================================
// alt_mem_ddrx_addr_cmd_wrap
//------------------------------------------------------------------------------
//
// Address and command decoder block
//
// Info: Trasalate controller internal command into AFI command
//
//==============================================================================
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0] | bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP ];
// wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] temp_to_bank = bg_to_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0] | bg_to_bank [2 * CFG_MEM_IF_BA_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH ];
// wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] temp_to_row = bg_to_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0] | bg_to_row [2 * CFG_MEM_IF_ROW_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH];
// wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] temp_to_col = bg_to_col [CFG_MEM_IF_COL_WIDTH - 1 : 0] | bg_to_col [2 * CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
//
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_refresh = bg_do_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_power_down = bg_do_power_down [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_power_down [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_self_refresh = bg_do_self_refresh [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_self_refresh [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_precharge_all = bg_do_precharge_all [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_precharge_all [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_deep_pdown = bg_do_deep_pdown [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_deep_pdown [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
// wire [CFG_MEM_IF_CHIP - 1 : 0] temp_do_zq_cal = bg_do_zq_cal [CFG_MEM_IF_CHIP - 1 : 0] | bg_do_zq_cal [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
alt_mem_ddrx_addr_cmd_wrap #
(
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_AFI_IF_FR_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_LPDDR2_ENABLED (CFG_LPDDR2_ENABLED ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
addr_cmd_wrap_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_do_write (bg_do_write ),
.bg_do_read (bg_do_read ),
.bg_do_auto_precharge (bg_do_auto_precharge ),
.bg_do_burst_chop (bg_do_burst_chop ),
.bg_do_activate (bg_do_activate ),
.bg_do_precharge (bg_do_precharge ),
.bg_do_refresh (bg_do_refresh ),
.bg_do_power_down (bg_do_power_down ),
.bg_do_self_refresh (bg_do_self_refresh ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.bg_do_lmr (bg_do_lmr ),
.bg_do_precharge_all (bg_do_precharge_all ),
.bg_do_zq_cal (bg_do_zq_cal ),
.bg_do_lmr_read (bg_do_lmr_read ),
.bg_do_refresh_1bank (bg_do_refresh_1bank ),
.bg_do_burst_terminate (bg_do_burst_terminate ),
.bg_do_deep_pdown (bg_do_deep_pdown ),
.bg_to_chip (bg_to_chip ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_col (bg_to_col ),
.bg_to_lmr (bg_to_lmr ),
.bg_dataid (bg_dataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.lmr_opcode (lmr_opcode ),
.afi_cke (afi_cke ),
.afi_cs_n (afi_cs_n ),
.afi_ras_n (afi_ras_n ),
.afi_cas_n (afi_cas_n ),
.afi_we_n (afi_we_n ),
.afi_ba (afi_ba ),
.afi_addr (afi_addr ),
.afi_rst_n (afi_rst_n ),
.afi_odt (afi_odt )
);
//==============================================================================
// alt_mem_ddrx_odt_gen
//------------------------------------------------------------------------------
//
// ODT generation block
//
// Info: Generate ODT information based on user configuration
//
//==============================================================================
// alt_mem_ddrx_odt_gen #
// (
// .CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
// .CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
// .CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
// .CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
// .CFG_OUTPUT_REGD (CFG_OUTPUT_REGD ),
// .CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
// .CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
// .CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
// .CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE )
// )
// odt_gen_inst
// (
// .ctl_clk (ctl_clk ),
// .ctl_reset_n (ctl_reset_n ),
// .cfg_type (cfg_type ),
// .cfg_tcl (cfg_tcl ),
// .cfg_cas_wr_lat (cfg_cas_wr_lat ),
// .cfg_add_lat (cfg_add_lat ),
// .cfg_write_odt_chip (cfg_write_odt_chip ),
// .cfg_read_odt_chip (cfg_read_odt_chip ),
// .cfg_burst_length (cfg_burst_length ),
// .bg_do_read (bg_do_read ),
// .bg_do_write (bg_do_write ),
// .bg_to_chip (bg_to_chip ),
// .afi_odt (afi_odt )
// );
//==============================================================================
// alt_mem_ddrx_rdwr_data_tmg
//------------------------------------------------------------------------------
//
// Read / write data timing block
//
// Info: Adjust read and write data timing based on AFI information
//
//==============================================================================
alt_mem_ddrx_rdwr_data_tmg #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DM_WIDTH (CFG_MEM_IF_DM_WIDTH ),
.CFG_WLAT_BUS_WIDTH (CFG_WLAT_BUS_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
rdwr_data_tmg_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_output_regd (cfg_output_regd ),
.cfg_output_regd_for_afi_output (cfg_output_regd_for_afi_output ),
.bg_doing_read (bg_doing_read ),
.bg_doing_write (bg_doing_write ),
.bg_rdwr_data_valid (bg_rdwr_data_valid ),
.dataid (bg_dataid ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_wdata (ecc_wdata ),
.ecc_dm (ecc_dm ),
.afi_wlat (afi_wlat ),
.afi_doing_read (afi_rdata_en ),
.afi_doing_read_full (afi_rdata_en_full ),
.ecc_wdata_fifo_read (ecc_wdata_fifo_read ),
.ecc_wdata_fifo_dataid (ecc_wdata_fifo_dataid ),
.ecc_wdata_fifo_dataid_vector (ecc_wdata_fifo_dataid_vector ),
.ecc_wdata_fifo_rmw_correct (ecc_wdata_fifo_rmw_correct ),
.ecc_wdata_fifo_rmw_partial (ecc_wdata_fifo_rmw_partial ),
.ecc_wdata_fifo_read_first (ecc_wdata_fifo_read_first ),
.ecc_wdata_fifo_dataid_first (ecc_wdata_fifo_dataid_first ),
.ecc_wdata_fifo_dataid_vector_first (ecc_wdata_fifo_dataid_vector_first ),
.ecc_wdata_fifo_rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.ecc_wdata_fifo_rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.ecc_wdata_fifo_first_vector (ecc_wdata_fifo_first_vector ),
.ecc_wdata_fifo_read_last (ecc_wdata_fifo_read_last ),
.ecc_wdata_fifo_dataid_last (ecc_wdata_fifo_dataid_last ),
.ecc_wdata_fifo_dataid_vector_last (ecc_wdata_fifo_dataid_vector_last ),
.ecc_wdata_fifo_rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.ecc_wdata_fifo_rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.afi_dqs_burst (afi_dqs_burst ),
.afi_wdata_valid (afi_wdata_valid ),
.afi_wdata (afi_wdata ),
.afi_dm (afi_dm )
);
//==============================================================================
// alt_mem_ddrx_wdata_path
//------------------------------------------------------------------------------
//
// Write data path block
//
// Info: Handles write data processing
//
//==============================================================================
// match datapath id width, with command path id width
generate
begin : gen_resolve_datap_id
genvar i;
for (i = 0;i < CFG_DRAM_WLAT_GROUP;i = i + 1)
begin : write_dataid_per_dqs_group
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ];
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH];
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign ecc_wdata_wrdataid [(i + 1) * CFG_WRDATA_ID_WIDTH - 1 : i * CFG_WRDATA_ID_WIDTH ] = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid [(i * CFG_DATA_ID_WIDTH ) + CFG_WRDATA_ID_WIDTH - 1 : i * CFG_DATA_ID_WIDTH ]};
assign ecc_wdata_wrdataid_vector [(i + 1) * CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_WRDATA_VEC_ID_WIDTH] = {{CFG_DATA_ID_REMAINDER {1'b0}},ecc_wdata_fifo_dataid_vector [(i * CFG_DATAID_ARRAY_DEPTH) + CFG_WRDATA_VEC_ID_WIDTH - 1 : i * CFG_DATAID_ARRAY_DEPTH]};
end
end
if (CFG_WRDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_WRDATA_ID_WIDTH){1'b0}},wdatap_free_id_wrdataid};
assign ecc_wdata_wrdataid_first = ecc_wdata_fifo_dataid_first;
assign ecc_wdata_wrdataid_vector_first = ecc_wdata_fifo_dataid_vector_first;
assign ecc_wdata_wrdataid_last = ecc_wdata_fifo_dataid_last;
assign ecc_wdata_wrdataid_vector_last = ecc_wdata_fifo_dataid_vector_last;
end
else // (CFG_WRDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign wdatap_free_id_dataid = wdatap_free_id_wrdataid[CFG_DATA_ID_WIDTH-1:0];
assign ecc_wdata_wrdataid_first = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_first};
assign ecc_wdata_wrdataid_vector_first = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_first};
assign ecc_wdata_wrdataid_last = {{(CFG_WRDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},ecc_wdata_fifo_dataid_last};
assign ecc_wdata_wrdataid_vector_last = {{CFG_DATA_ID_REMAINDER{1'b0}},ecc_wdata_fifo_dataid_vector_last};
end
if (CFG_RDDATA_ID_WIDTH < CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = {{(CFG_DATA_ID_WIDTH-CFG_RDDATA_ID_WIDTH){1'b0}},rdatap_free_id_rddataid};
assign bg_rddataid = bg_dataid[CFG_RDDATA_ID_WIDTH-1:0];
end
else // (CFG_RDDATA_ID_WIDTH >= CFG_DATA_ID_WIDTH)
begin
assign rdatap_free_id_dataid = rdatap_free_id_rddataid[CFG_DATA_ID_WIDTH-1:0];
assign bg_rddataid = {{(CFG_RDDATA_ID_WIDTH-CFG_DATA_ID_WIDTH){1'b0}},bg_dataid};
end
end
endgenerate
alt_mem_ddrx_wdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_WRDATA_ID_WIDTH ),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP ),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP ),
.CFG_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_BUFFER_ADDR_WIDTH (CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_WDATA_REG (CFG_WDATA_REG ),
.CFG_PARTIAL_BE_PER_WORD_ENABLE (CFG_PARTIAL_BE_PER_WORD_ENABLE ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES (CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH )
)
wdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites (cfg_enable_ecc_code_overwrites ),
.cfg_interface_width (cfg_interface_width ),
.wdatap_free_id_valid (wdatap_free_id_valid ),
.wdatap_free_id_dataid (wdatap_free_id_wrdataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_write (proc_write ),
.tbp_load_index (tbp_load_index ),
.proc_size (proc_size ),
.wr_data_mem_full (wr_data_mem_full ),
.write_data_en (write_data_valid ),
.write_data (write_data ),
.byte_en (byte_en ),
.data_complete (data_complete ),
.data_rmw_complete (data_rmw_complete ),
.data_partial_be (data_partial_be ),
.doing_write (ecc_wdata_fifo_read ),
.dataid (ecc_wdata_wrdataid ),
.dataid_vector (ecc_wdata_wrdataid_vector ),
.rdwr_data_valid (ecc_wdata_fifo_read ),
.rmw_correct (ecc_wdata_fifo_rmw_correct ),
.rmw_partial (ecc_wdata_fifo_rmw_partial ),
.doing_write_first (ecc_wdata_fifo_read_first ),
.dataid_first (ecc_wdata_wrdataid_first ),
.dataid_vector_first (ecc_wdata_wrdataid_vector_first ),
.rdwr_data_valid_first (ecc_wdata_fifo_read_first ),
.rmw_correct_first (ecc_wdata_fifo_rmw_correct_first ),
.rmw_partial_first (ecc_wdata_fifo_rmw_partial_first ),
.doing_write_first_vector (ecc_wdata_fifo_first_vector ),
.rdwr_data_valid_first_vector (ecc_wdata_fifo_first_vector ),
.doing_write_last (ecc_wdata_fifo_read_last ),
.dataid_last (ecc_wdata_wrdataid_last ),
.dataid_vector_last (ecc_wdata_wrdataid_vector_last ),
.rdwr_data_valid_last (ecc_wdata_fifo_read_last ),
.rmw_correct_last (ecc_wdata_fifo_rmw_correct_last ),
.rmw_partial_last (ecc_wdata_fifo_rmw_partial_last ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_dm (wdatap_dm ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_rdata_path
//------------------------------------------------------------------------------
//
// Read data path block
//
// Info: Handles read data processing
//
//==============================================================================
alt_mem_ddrx_rdata_path #
(
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_DATA_ID_WIDTH (CFG_RDDATA_ID_WIDTH ),
.CFG_LOCAL_ID_WIDTH (CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_BUFFER_ADDR_WIDTH (CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MAX_READ_CMD_NUM_WIDTH (CFG_MAX_PENDING_RD_CMD_WIDTH ),
.CFG_RDATA_RETURN_MODE (CFG_RDATA_RETURN_MODE ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ERRCMD_FIFO_ADDR_WIDTH (CFG_ERRCMD_FIFO_ADDR_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR (CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_ENABLE_NO_DM (CFG_PORT_WIDTH_ENABLE_NO_DM ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_ADDR_ORDER (CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH (CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH (CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH (CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH (CFG_PORT_WIDTH_CS_ADDR_WIDTH )
)
rdata_path_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_enable_auto_corr (cfg_enable_auto_corr ),
.cfg_enable_no_dm (cfg_enable_no_dm ),
.cfg_burst_length (cfg_burst_length ),
.cfg_addr_order (cfg_addr_order ),
.cfg_col_addr_width (cfg_col_addr_width ),
.cfg_row_addr_width (cfg_row_addr_width ),
.cfg_bank_addr_width (cfg_bank_addr_width ),
.cfg_cs_addr_width (cfg_cs_addr_width ),
.rdatap_free_id_valid (rdatap_free_id_valid ),
.rdatap_free_id_dataid (rdatap_free_id_rddataid ),
.proc_busy (proc_busy ),
.proc_load (proc_load ),
.proc_load_dataid (proc_load_dataid ),
.proc_read (proc_read ),
.proc_size (proc_size ),
.proc_localid (proc_localid ),
.read_data_valid (read_data_valid ),
.read_data (read_data ),
.read_data_error (read_data_error ),
.read_data_localid (read_data_localid ),
.bg_do_read (bg_do_read ),
.bg_to_chipsel (bg_to_chipsel ),
.bg_to_bank (bg_to_bank ),
.bg_to_row (bg_to_row ),
.bg_to_column (bg_to_col ),
.bg_dataid (bg_rddataid ),
.bg_localid (bg_localid ),
.bg_size (bg_size ),
.bg_do_rmw_correct (bg_do_rmw_correct ),
.bg_do_rmw_partial (bg_do_rmw_partial ),
.ecc_rdata (ecc_rdata ),
.ecc_rdatav (ecc_rdata_valid ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.errcmd_ready (errcmd_ready ),
.errcmd_valid (errcmd_valid ),
.errcmd_chipsel (errcmd_chipsel ),
.errcmd_bank (errcmd_bank ),
.errcmd_row (errcmd_row ),
.errcmd_column (errcmd_column ),
.errcmd_size (errcmd_size ),
.errcmd_localid (errcmd_localid ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.rmwfifo_data_valid (rmwfifo_data_valid ),
.rmwfifo_data (rmwfifo_data ),
.rmwfifo_ecc_dbe (rmwfifo_ecc_dbe ),
.rmwfifo_ecc_code (rmwfifo_ecc_code )
);
//==============================================================================
// alt_mem_ddrx_ecc_encoder_decoder_wrapper
//------------------------------------------------------------------------------
//
// ECC encoder/decoder block
//
// Info: Encode write data and decode read data, correct single bit error
// and detect double bit errors
//
//==============================================================================
alt_mem_ddrx_ecc_encoder_decoder_wrapper #
(
.CFG_LOCAL_ADDR_WIDTH (CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH (CFG_LOCAL_DATA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ECC_MULTIPLES (CFG_ECC_MULTIPLES ),
.CFG_MEM_IF_DQ_WIDTH (CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH (CFG_MEM_IF_DQS_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH (CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_GEN_SBE (CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE (CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR (CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR (CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR (CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR (CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR),
.CFG_PORT_WIDTH_CLR_INTR (CFG_PORT_WIDTH_CLR_INTR ),
.STS_PORT_WIDTH_SBE_ERROR (STS_PORT_WIDTH_SBE_ERROR ),
.STS_PORT_WIDTH_DBE_ERROR (STS_PORT_WIDTH_DBE_ERROR ),
.STS_PORT_WIDTH_SBE_COUNT (STS_PORT_WIDTH_SBE_COUNT ),
.STS_PORT_WIDTH_DBE_COUNT (STS_PORT_WIDTH_DBE_COUNT ),
.STS_PORT_WIDTH_CORR_DROP_ERROR (STS_PORT_WIDTH_CORR_DROP_ERROR ),
.STS_PORT_WIDTH_CORR_DROP_COUNT (STS_PORT_WIDTH_CORR_DROP_COUNT )
)
ecc_encoder_decoder_wrapper_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_interface_width (cfg_interface_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.cfg_gen_sbe (cfg_gen_sbe ),
.cfg_gen_dbe (cfg_gen_dbe ),
.cfg_enable_intr (cfg_enable_intr ),
.cfg_mask_sbe_intr (cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr (cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr (cfg_mask_corr_dropped_intr ),
.cfg_clr_intr (cfg_clr_intr ),
.wdatap_dm (wdatap_dm ),
.wdatap_data (wdatap_data ),
.wdatap_rmw_partial_data (wdatap_rmw_partial_data ),
.wdatap_rmw_correct_data (wdatap_rmw_correct_data ),
.wdatap_rmw_partial (wdatap_rmw_partial ),
.wdatap_rmw_correct (wdatap_rmw_correct ),
.wdatap_ecc_code (wdatap_ecc_code ),
.wdatap_ecc_code_overwrite (wdatap_ecc_code_overwrite ),
.rdatap_rcvd_addr (rdatap_rcvd_addr ),
.rdatap_rcvd_cmd (rdatap_rcvd_cmd ),
.rdatap_rcvd_corr_dropped (rdatap_rcvd_corr_dropped ),
.afi_rdata (afi_rdata ),
.afi_rdata_valid (afi_rdata_valid ),
.ecc_rdata (ecc_rdata ),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_dm (ecc_dm ),
.ecc_wdata (ecc_wdata ),
.ecc_sbe (ecc_sbe ),
.ecc_dbe (ecc_dbe ),
.ecc_code (ecc_code ),
.ecc_interrupt (ecc_interrupt ),
.sts_sbe_error (sts_sbe_error ),
.sts_dbe_error (sts_dbe_error ),
.sts_sbe_count (sts_sbe_count ),
.sts_dbe_count (sts_dbe_count ),
.sts_err_addr (sts_err_addr ),
.sts_corr_dropped (sts_corr_dropped ),
.sts_corr_dropped_count (sts_corr_dropped_count ),
.sts_corr_dropped_addr (sts_corr_dropped_addr )
);
//==============================================================================
// alt_mem_ddrx_sideband
//------------------------------------------------------------------------------
//
// Sideband block
//
// Info: Monitor and issue sideband specific commands such as user/auto
// refresh, self refresh, power down, deep power down,
// precharge all and zq calibration commands
//
//==============================================================================
alt_mem_ddrx_sideband #
(
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_MEM_IF_CLK_PAIR_COUNT (CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH )
)
sideband_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.rfsh_req (rfsh_req ),
.rfsh_chip (rfsh_chip ),
.rfsh_ack (rfsh_ack ),
.self_rfsh_req (self_rfsh_req ),
.self_rfsh_chip (self_rfsh_chip ),
.self_rfsh_ack (self_rfsh_ack ),
.deep_powerdn_req (deep_powerdn_req ),
.deep_powerdn_chip (deep_powerdn_chip ),
.deep_powerdn_ack (deep_powerdn_ack ),
.power_down_ack (power_down_ack ),
.stall_row_arbiter (stall_row_arbiter ),
.stall_col_arbiter (stall_col_arbiter ),
.stall_chip (stall_chip ),
.sb_do_precharge_all (sb_do_precharge_all ),
.sb_do_refresh (sb_do_refresh ),
.sb_do_self_refresh (sb_do_self_refresh ),
.sb_do_power_down (sb_do_power_down ),
.sb_do_deep_pdown (sb_do_deep_pdown ),
.sb_do_zq_cal (sb_do_zq_cal ),
.sb_tbp_precharge_all (sb_tbp_precharge_all ),
.ctl_mem_clk_disable (ctl_mem_clk_disable ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_pdn_period (t_param_pdn_period ),
.tbp_empty (tbp_empty ),
.tbp_bank_active (tbp_bank_active ),
.tbp_timer_ready (tbp_timer_ready ),
.row_grant (or_row_grant ),
.col_grant (or_col_grant ),
.afi_ctl_refresh_done (afi_ctl_refresh_done ),
.afi_seq_busy (afi_seq_busy ),
.afi_ctl_long_idle (afi_ctl_long_idle ),
.cfg_enable_dqs_tracking (cfg_enable_dqs_tracking ),
.cfg_user_rfsh (cfg_user_rfsh ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_regdimm_enable (cfg_regdimm_enable )
);
//==============================================================================
// alt_mem_ddrx_rank_timer
//------------------------------------------------------------------------------
//
// Rank timer block
//
// Info: Monitor rank specific timing parameter for activate, precharge,
// read and write commands
//
//==============================================================================
alt_mem_ddrx_rank_timer #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_TBP_NUM (CFG_CTL_TBP_NUM ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CS_WIDTH (CFG_MEM_IF_CS_WIDTH ),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH ),
.CFG_AFI_INTF_PHASE_NUM (CFG_AFI_INTF_PHASE_NUM ),
.CFG_ENABLE_BURST_INTERRUPT (CFG_ENABLE_BURST_INTERRUPT ),
.CFG_ENABLE_BURST_TERMINATE (CFG_ENABLE_BURST_TERMINATE ),
.CFG_REG_GRANT (CFG_REG_GRANT ),
.CFG_RANK_TIMER_OUTPUT_REG (CFG_RANK_TIMER_OUTPUT_REG ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH )
)
rank_timer_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.bg_do_write (bg_do_write_combi ),
.bg_do_read (bg_do_read_combi ),
.bg_do_burst_chop (bg_do_burst_chop_combi ),
.bg_do_burst_terminate (bg_do_burst_terminate_combi ),
.bg_do_activate (bg_do_activate_combi ),
.bg_do_precharge (bg_do_precharge_combi ),
.bg_to_chip (bg_to_chip_combi ),
.bg_effective_size (bg_effective_size_combi ),
.bg_interrupt_ready (bg_interrupt_ready_combi ),
.cmd_gen_chipsel (cmd_gen_chipsel ),
.tbp_chipsel (tbp_chipsel ),
.tbp_load (tbp_load ),
.stall_chip (stall_chip ),
.can_activate (can_activate ),
.can_precharge (can_precharge ),
.can_read (can_read ),
.can_write (can_write )
);
//==============================================================================
// alt_mem_ddrx_timing_param
//------------------------------------------------------------------------------
//
// Timing parameter block
//
// Info: Pre-calculate required timing parameters for each memory commands
// based on memory type
//
//==============================================================================
alt_mem_ddrx_timing_param #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_CTL_ARBITER_TYPE (CFG_CTL_ARBITER_TYPE ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD (CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW (CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC (CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI (CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD (CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP (CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR (CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR (CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP (CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS (CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC (CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD (CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD (CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES (CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES (CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES (CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD (CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.T_PARAM_ACT_TO_RDWR_WIDTH (T_PARAM_ACT_TO_RDWR_WIDTH ),
.T_PARAM_ACT_TO_PCH_WIDTH (T_PARAM_ACT_TO_PCH_WIDTH ),
.T_PARAM_ACT_TO_ACT_WIDTH (T_PARAM_ACT_TO_ACT_WIDTH ),
.T_PARAM_RD_TO_RD_WIDTH (T_PARAM_RD_TO_RD_WIDTH ),
.T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_WR_WIDTH (T_PARAM_RD_TO_WR_WIDTH ),
.T_PARAM_RD_TO_WR_BC_WIDTH (T_PARAM_RD_TO_WR_BC_WIDTH ),
.T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_RD_TO_PCH_WIDTH (T_PARAM_RD_TO_PCH_WIDTH ),
.T_PARAM_RD_AP_TO_VALID_WIDTH (T_PARAM_RD_AP_TO_VALID_WIDTH ),
.T_PARAM_WR_TO_WR_WIDTH (T_PARAM_WR_TO_WR_WIDTH ),
.T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_RD_WIDTH (T_PARAM_WR_TO_RD_WIDTH ),
.T_PARAM_WR_TO_RD_BC_WIDTH (T_PARAM_WR_TO_RD_BC_WIDTH ),
.T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH (T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH ),
.T_PARAM_WR_TO_PCH_WIDTH (T_PARAM_WR_TO_PCH_WIDTH ),
.T_PARAM_WR_AP_TO_VALID_WIDTH (T_PARAM_WR_AP_TO_VALID_WIDTH ),
.T_PARAM_PCH_TO_VALID_WIDTH (T_PARAM_PCH_TO_VALID_WIDTH ),
.T_PARAM_PCH_ALL_TO_VALID_WIDTH (T_PARAM_PCH_ALL_TO_VALID_WIDTH ),
.T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH (T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH ),
.T_PARAM_FOUR_ACT_TO_ACT_WIDTH (T_PARAM_FOUR_ACT_TO_ACT_WIDTH ),
.T_PARAM_ARF_TO_VALID_WIDTH (T_PARAM_ARF_TO_VALID_WIDTH ),
.T_PARAM_PDN_TO_VALID_WIDTH (T_PARAM_PDN_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_VALID_WIDTH (T_PARAM_SRF_TO_VALID_WIDTH ),
.T_PARAM_SRF_TO_ZQ_CAL_WIDTH (T_PARAM_SRF_TO_ZQ_CAL_WIDTH ),
.T_PARAM_ARF_PERIOD_WIDTH (T_PARAM_ARF_PERIOD_WIDTH ),
.T_PARAM_PDN_PERIOD_WIDTH (T_PARAM_PDN_PERIOD_WIDTH )
)
timing_param_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_burst_length (cfg_burst_length ),
.cfg_type (cfg_type ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_tcl (cfg_tcl ),
.cfg_trrd (cfg_trrd ),
.cfg_tfaw (cfg_tfaw ),
.cfg_trfc (cfg_trfc ),
.cfg_trefi (cfg_trefi ),
.cfg_trcd (cfg_trcd ),
.cfg_trp (cfg_trp ),
.cfg_twr (cfg_twr ),
.cfg_twtr (cfg_twtr ),
.cfg_trtp (cfg_trtp ),
.cfg_tras (cfg_tras ),
.cfg_trc (cfg_trc ),
.cfg_tccd (cfg_tccd ),
.cfg_tmrd (cfg_tmrd ),
.cfg_self_rfsh_exit_cycles (cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles (cfg_pdn_exit_cycles ),
.cfg_auto_pd_cycles (cfg_auto_pd_cycles ),
.cfg_extra_ctl_clk_act_to_rdwr (cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch (cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act (cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd (cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip (cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr (cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc (cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip (cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch (cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid (cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr (cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip (cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd (cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc (cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip (cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch (cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid (cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid (cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid (cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank (cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act (cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid (cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid (cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid (cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal (cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period (cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period (cfg_extra_ctl_clk_pdn_period ),
.t_param_act_to_rdwr (t_param_act_to_rdwr ),
.t_param_act_to_pch (t_param_act_to_pch ),
.t_param_act_to_act (t_param_act_to_act ),
.t_param_rd_to_rd (t_param_rd_to_rd ),
.t_param_rd_to_rd_diff_chip (t_param_rd_to_rd_diff_chip ),
.t_param_rd_to_wr (t_param_rd_to_wr ),
.t_param_rd_to_wr_bc (t_param_rd_to_wr_bc ),
.t_param_rd_to_wr_diff_chip (t_param_rd_to_wr_diff_chip ),
.t_param_rd_to_pch (t_param_rd_to_pch ),
.t_param_rd_ap_to_valid (t_param_rd_ap_to_valid ),
.t_param_wr_to_wr (t_param_wr_to_wr ),
.t_param_wr_to_wr_diff_chip (t_param_wr_to_wr_diff_chip ),
.t_param_wr_to_rd (t_param_wr_to_rd ),
.t_param_wr_to_rd_bc (t_param_wr_to_rd_bc ),
.t_param_wr_to_rd_diff_chip (t_param_wr_to_rd_diff_chip ),
.t_param_wr_to_pch (t_param_wr_to_pch ),
.t_param_wr_ap_to_valid (t_param_wr_ap_to_valid ),
.t_param_pch_to_valid (t_param_pch_to_valid ),
.t_param_pch_all_to_valid (t_param_pch_all_to_valid ),
.t_param_act_to_act_diff_bank (t_param_act_to_act_diff_bank ),
.t_param_four_act_to_act (t_param_four_act_to_act ),
.t_param_arf_to_valid (t_param_arf_to_valid ),
.t_param_pdn_to_valid (t_param_pdn_to_valid ),
.t_param_srf_to_valid (t_param_srf_to_valid ),
.t_param_srf_to_zq_cal (t_param_srf_to_zq_cal ),
.t_param_arf_period (t_param_arf_period ),
.t_param_pdn_period (t_param_pdn_period )
);
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// this program was cloned from: https://github.com/fast-switch/fast
// license: apache license 2.0
// (c) 2001-2014 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// (c) 2001-2010 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
//
// -----------------------------------------------
// false path marker module
// this module creates a level of flops for the
// targetted clock, and cut the timing path to the
// flops using embedded sdc constraint
//
// only use this module to clock cross the path
// that is being clock crossed properly by correct
// concept.
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_false_path_marker
#(
parameter marker_width = 1
)
(
input reset,
input clk,
input [marker_width - 1 : 0] data_in,
output [marker_width - 1 : 0] data_out
);
(* altera_attribute = "-name sdc_statement \" set_false_path -to [get_registers *altera_tse_false_path_marker:*|data_out_reg*]\"" *)
(*preserve*) reg [marker_width - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {marker_width{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module is a rom for auto initializing the trdb d5m digital camera. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_d5m (
// inputs
rom_address,
exposure,
// bidirectionals
// outputs
rom_data
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
parameter d5m_column_size = 16'd2591;
parameter d5m_row_size = 16'd1943;
parameter d5m_column_bin = 16'h0000;
parameter d5m_row_bin = 16'h0000;
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input [ 4: 0] rom_address;
input [15: 0] exposure;
// bidirectionals
// outputs
output [35: 0] rom_data;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
// states
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
reg [31: 0] data;
// internal registers
// state machine registers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
// output registers
// internal registers
/*****************************************************************************
* combinational logic *
*****************************************************************************/
// output assignments
assign rom_data = {data[31:24], 1'b0,
data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// internal assignments
always @(*)
begin
case (rom_address)
0 : data <= {8'hba, 8'h00, 16'h0000};
1 : data <= {8'hba, 8'h20, 16'hc000}; // mirror row and columns
2 : data <= {8'hba, 8'h09, exposure}; // exposure
3 : data <= {8'hba, 8'h05, 16'h0000}; // h_blanking
4 : data <= {8'hba, 8'h06, 16'h0019}; // v_blanking
5 : data <= {8'hba, 8'h0a, 16'h8000}; // change latch
6 : data <= {8'hba, 8'h2b, 16'h000b}; // green 1 gain
7 : data <= {8'hba, 8'h2c, 16'h000f}; // blue gain
8 : data <= {8'hba, 8'h2d, 16'h000f}; // red gain
9 : data <= {8'hba, 8'h2e, 16'h000b}; // green 2 gain
10 : data <= {8'hba, 8'h10, 16'h0051}; // set up pll power on
11 : data <= {8'hba, 8'h11, 16'h1807}; // pll_m_factor<<8+pll_n_divider
12 : data <= {8'hba, 8'h12, 16'h0002}; // pll_p1_divider
13 : data <= {8'hba, 8'h10, 16'h0053}; // set use pll
14 : data <= {8'hba, 8'h98, 16'h0000}; // disble calibration
`ifdef enable_test_pattern
15 : data <= {8'hba, 8'ha0, 16'h0001}; // test pattern control
16 : data <= {8'hba, 8'ha1, 16'h0123}; // test green pattern value
17 : data <= {8'hba, 8'ha2, 16'h0456}; // test red pattern value
`else
15 : data <= {8'hba, 8'ha0, 16'h0000}; // test pattern control
16 : data <= {8'hba, 8'ha1, 16'h0000}; // test green pattern value
17 : data <= {8'hba, 8'ha2, 16'h0fff}; // test red pattern value
`endif
18 : data <= {8'hba, 8'h01, 16'h0036}; // set start row
19 : data <= {8'hba, 8'h02, 16'h0010}; // set start column
20 : data <= {8'hba, 8'h03, d5m_row_size}; // set row size
21 : data <= {8'hba, 8'h04, d5m_column_size}; // set column size
22 : data <= {8'hba, 8'h22, d5m_row_bin}; // set row mode in bin mode
23 : data <= {8'hba, 8'h23, d5m_column_bin}; // set column mode in bin mode
24 : data <= {8'hba, 8'h49, 16'h01a8}; // row black target
default : data <= {8'h00, 8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* internal modules *
*****************************************************************************/
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
// (c) 2001-2011 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_xcvr_reconfig_eyemon
#(
parameter device_family = "stratix iv",
parameter number_of_reconfig_interfaces = 1
)
(
input wire reconfig_clk, // this will be the reconfig clk
input wire reset,
//avalon mm slave
input wire [2:0] eyemon_address, // mm address
input wire [31:0] eyemon_writedata,
input wire eyemon_write,
input wire eyemon_read,
//output mm slave
output wire [31:0] eyemon_readdata, // from mm
output wire eyemon_waitrequest, // from mm
output wire eyemon_done,
// input from base_reconfig
input wire eyemon_irq_from_base,
input wire eyemon_waitrequest_from_base,
// output to base_reconfig
// avalon mm master
output wire [4:0] eyemon_address_base, // 3 bit mm
output wire [31:0] eyemon_writedata_base,
output wire eyemon_write_base, // start write to gxb
output wire eyemon_read_base, // start read from gxb
// input from base reconfig
input wire [31:0] eyemon_readdata_base // data from read command
);
generate
if ((device_family == "stratix iv"))
begin
alt_xcvr_reconfig_eyemon_tgx
#(
.device_family(device_family),
.number_of_reconfig_interfaces(number_of_reconfig_interfaces)
) eyemon_tgx
(
.reconfig_clk(reconfig_clk),
.reset(reset),
.eyemon_address(eyemon_address),
.eyemon_writedata(eyemon_writedata),
.eyemon_write(eyemon_write),
.eyemon_read(eyemon_read),
.eyemon_readdata(eyemon_readdata),
.eyemon_waitrequest(eyemon_waitrequest),
.eyemon_irq(eyemon_done),
.eyemon_irq_from_base(eyemon_irq_from_base),
.eyemon_waitrequest_from_base(eyemon_waitrequest_from_base),
.eyemon_address_base(eyemon_address_base),
.eyemon_writedata_base(eyemon_writedata_base),
.eyemon_write_base(eyemon_write_base),
.eyemon_read_base(eyemon_read_base),
.eyemon_readdata_base(eyemon_readdata_base)
);
end else begin
assign eyemon_readdata = 32'b0;
assign eyemon_done = 1'b0;
assign eyemon_address_base = 5'b0;
assign eyemon_writedata_base = 32'b0;
assign eyemon_write_base = 1'b0;
assign eyemon_read_base = 1'b0;
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_encoder_output;
// Assign bit 39 to '0'
assign int_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (int_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// this program was cloned from: https://github.com/fast-switch/fast
// license: apache license 2.0
//legal notice: (c)2010 altera corporation. all rights reserved. your
//use of altera corporation's design tools, logic functions and other
//software and tools, and its ampp partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the altera program
//license subscription agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by altera and sold by altera
//or its authorized distributors. please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// title :
//
// file : alt_ddrx_bank_timer_info.v
//
// abstract :
///////////////////////////////////////////////////////////////////////////////
module alt_ddrx_bank_timer_info #
( parameter
act_to_rdwr_width = 0, // these parameters need to be set for this module to work correctly
act_to_act_width = 0, // these parameters need to be set for this module to work correctly
act_to_pch_width = 0, // these parameters need to be set for this module to work correctly
rd_to_pch_width = 0, // these parameters need to be set for this module to work correctly
wr_to_pch_width = 0, // these parameters need to be set for this module to work correctly
rd_ap_to_act_width = 0, // these parameters need to be set for this module to work correctly
wr_ap_to_act_width = 0, // these parameters need to be set for this module to work correctly
pch_to_act_width = 0, // these parameters need to be set for this module to work correctly
bank_timer_counter_offset = 3,
mem_if_row_width = 16,
close_page_policy = 1
)
(
ctl_clk,
ctl_reset_n,
// timing information
act_to_rdwr,
act_to_act,
act_to_pch,
rd_to_pch,
wr_to_pch,
rd_ap_to_act,
wr_ap_to_act,
pch_to_act,
less_than_x2_act_to_rdwr,
// inputs
open,
close,
read,
write,
row_addr,
// outputs
current_state,
current_row,
rdwr_ready,
act_ready,
pch_ready
);
input ctl_clk;
input ctl_reset_n;
// timing information
input [act_to_rdwr_width - 1 : 0] act_to_rdwr;
input [act_to_act_width - 1 : 0] act_to_act;
input [act_to_pch_width - 1 : 0] act_to_pch;
input [rd_to_pch_width - 1 : 0] rd_to_pch;
input [wr_to_pch_width - 1 : 0] wr_to_pch;
input [rd_ap_to_act_width - 1 : 0] rd_ap_to_act;
input [wr_ap_to_act_width - 1 : 0] wr_ap_to_act;
input [pch_to_act_width - 1 : 0] pch_to_act;
input less_than_x2_act_to_rdwr;
// inputs
input open;
input close;
input read;
input write;
input [mem_if_row_width - 1 : 0] row_addr;
// outputs
output current_state; // 0/1 represents idle/active state
output [mem_if_row_width - 1 : 0] current_row;
output rdwr_ready;
output act_ready;
output pch_ready;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[start] registers & wires
------------------------------------------------------------------------------*/
localparam act_counter_width = act_to_act_width; // similar to act_to_act width
localparam general_counter_width = 6; // 0 - 63, should be enough for all timing values
reg current_state;
reg [mem_if_row_width - 1 : 0] current_row;
reg rdwr_ready;
reg act_ready;
reg pch_ready;
reg doing_read;
reg doing_auto_precharge;
reg doing_precharge;
reg int_act_to_act_ready;
reg int_act_to_pch_ready;
reg int_rdwr_to_valid_ready;
reg [act_counter_width - 1 : 0] act_counter;
reg [general_counter_width - 1 : 0] general_counter;
/*------------------------------------------------------------------------------
[end] registers & wires
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[start] general logics
------------------------------------------------------------------------------*/
// general counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_counter <= 0;
end
else
begin
if (open)
act_counter <= bank_timer_counter_offset;
else if (act_counter != {act_counter_width{1'b1}})
act_counter <= act_counter + 1'b1;
end
end
// read write counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
general_counter <= 0;
end
else
begin
if (read || write || close)
general_counter <= bank_timer_counter_offset;
else if (general_counter != {general_counter_width{1'b1}})
general_counter <= general_counter + 1'b1;
end
end
// keep track of read/write command
// '1' during read
// '0' during write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read <= 1'b0;
else
begin
if (write)
doing_read <= 1'b0;
else if (read)
doing_read <= 1'b1;
end
end
// keep track of precharge command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
else
begin
if (close)
begin
if (read || write)
begin
doing_auto_precharge <= 1'b1;
doing_precharge <= 1'b0;
end
else
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b1;
end
end
else if (open)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
bank status
------------------------------------------------------------------------------*/
// store current state, 0 for idle and 1 for active
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_state <= 1'b0;
end
else
begin
if (open)
current_state <= 1'b1;
else if (close)
current_state <= 1'b0;
end
end
/*------------------------------------------------------------------------------
act to rd/wr (trcd)
------------------------------------------------------------------------------*/
// keep track of trcd
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_ready <= 1'b0;
end
else
begin
if (close)
rdwr_ready <= 1'b0;
else if (open && less_than_x2_act_to_rdwr)
rdwr_ready <= 1'b1;
else if (current_state && act_counter >= act_to_rdwr) // only enable after page opened
rdwr_ready <= 1'b1;
else
rdwr_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
act to act (trc)
------------------------------------------------------------------------------*/
// keep track of trc
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_act_ready <= 1'b1;
end
else
begin
if (open) // immediately de-assert act_ready after an activate is issued to a bank
int_act_to_act_ready <= 1'b0;
else if (act_counter >= act_to_act)
int_act_to_act_ready <= 1'b1;
else
int_act_to_act_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
rd/wr(ap) to valid
------------------------------------------------------------------------------*/
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_rdwr_to_valid_ready <= 1'b0;
end
else
begin
if (close)
int_rdwr_to_valid_ready <= 1'b0; // deassert immediately after close signal detected
else
begin
if (doing_precharge && general_counter >= pch_to_act) // pch to act
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_precharge)
begin
if (!doing_read && doing_auto_precharge && general_counter >= wr_ap_to_act) // wrap to act
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && doing_auto_precharge && general_counter >= rd_ap_to_act) // rdap to act
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_read && !doing_auto_precharge && general_counter >= wr_to_pch) // wr to pch
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && !doing_auto_precharge && general_counter >= rd_to_pch) // rd to pch
int_rdwr_to_valid_ready <= 1'b1;
else
int_rdwr_to_valid_ready <= 1'b0;
end
else
int_rdwr_to_valid_ready <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
act to pch (tras)
------------------------------------------------------------------------------*/
// keep track of tras
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_pch_ready <= 1'b0;
end
else
begin
if (open) // immediately de-assert pch_ready after an activate is issued to a bank
int_act_to_pch_ready <= 1'b0;
else if (act_counter >= act_to_pch)
int_act_to_pch_ready <= 1'b1;
else
int_act_to_pch_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
act/pch ready
------------------------------------------------------------------------------*/
always @ (*)
begin
act_ready = int_act_to_act_ready & int_rdwr_to_valid_ready;
end
always @ (*)
begin
pch_ready = int_act_to_pch_ready & int_rdwr_to_valid_ready;
end
/*------------------------------------------------------------------------------
[end] general logics
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
// opp /*------------------------------------------------------------------------------
// opp
// opp [start] open page policy logics
// opp
// opp ------------------------------------------------------------------------------*/
// opp generate
// opp if (!close_page_policy) // only enable during open page policy
// opp begin
// opp // store row information
// opp always @ (posedge ctl_clk or negedge ctl_reset_n)
// opp begin
// opp if (!ctl_reset_n)
// opp begin
// opp current_row <= 0;
// opp end
// opp else
// opp begin
// opp // update when there is an activate
// opp if (open)
// opp current_row <= row_addr;
// opp end
// opp end
// opp end
// opp endgenerate
// opp /*------------------------------------------------------------------------------
// opp
// opp [end] open page policy logics
// opp
// opp ------------------------------------------------------------------------------*/
endmodule
|
// this program was cloned from: https://github.com/fast-switch/fast
// license: apache license 2.0
//legal notice: (c)2010 altera corporation. all rights reserved. your
//use of altera corporation's design tools, logic functions and other
//software and tools, and its ampp partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the altera program
//license subscription agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by altera and sold by altera
//or its authorized distributors. please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// title : ddr controller input interface
//
// file : alt_ddrx_input_if.v
//
// abstract : input interface
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_input_if
#(parameter mem_type = "ddr3",
internal_size_width = 7,
internal_data_width = 64,
ctl_hrb_enabled = 0,
ctl_csr_enabled = 0,
ctl_regdimm_enabled = 0,
mem_if_csr_col_width = 4,
mem_if_csr_row_width = 5,
mem_if_csr_bank_width = 2,
mem_if_csr_cs_width = 2,
wdata_beats_width = 9,
local_data_width = 64,
local_addr_width = 33,
local_size_width = 6,
ctl_look_ahead_depth = 4,
ctl_cmd_queue_depth = 4,
mem_if_row_width = 16,
mem_if_col_width = 12,
mem_if_ba_width = 3,
mem_if_chip_bits = 2,
dwidth_ratio = 2,
memory_burstlength = 8,
enable_burst_merge = 1,
family = "stratix",
min_col = 8,
min_row = 12,
min_bank = 2,
min_cs = 1,
local_if_type = "avalon"
)(
// port connections
ctl_clk ,
ctl_reset_n ,
ctl_half_clk ,
ctl_half_clk_reset_n ,
//---------------------------------------------------------------------
// user side signals
//---------------------------------------------------------------------
local_read_req ,
local_write_req ,
local_ready ,
local_size ,
local_autopch_req ,
local_multicast ,
local_burstbegin ,
local_init_done ,
local_addr ,
local_rdata_error ,
local_rdata_valid ,
local_rdata ,
local_wdata ,
local_be ,
local_wdata_req ,
ecc_rdata ,
ecc_rdata_valid ,
ecc_rdata_error ,
wdata_fifo_wdata ,
wdata_fifo_be ,
beats_in_wfifo ,
write_req_to_wfifo ,
be_to_wfifo ,
addr_order ,
col_width_from_csr ,
row_width_from_csr ,
bank_width_from_csr ,
cs_width_from_csr ,
regdimm_enable ,
wdata_fifo_read ,
fetch ,
ctl_cal_success ,
ctl_cal_fail ,
cmd_fifo_empty ,
cmd_fifo_full ,
cmd_fifo_wren ,
cmd0_is_a_read ,
cmd0_is_a_write ,
cmd0_autopch_req ,
cmd0_burstcount ,
cmd0_chip_addr ,
cmd0_row_addr ,
cmd0_bank_addr ,
cmd0_col_addr ,
cmd0_is_valid ,
cmd0_multicast_req ,
cmd1_is_a_read ,
cmd1_is_a_write ,
cmd1_chip_addr ,
cmd1_row_addr ,
cmd1_bank_addr ,
cmd1_is_valid ,
cmd1_multicast_req ,
cmd2_is_a_read ,
cmd2_is_a_write ,
cmd2_chip_addr ,
cmd2_row_addr ,
cmd2_bank_addr ,
cmd2_is_valid ,
cmd2_multicast_req ,
cmd3_is_a_read ,
cmd3_is_a_write ,
cmd3_chip_addr ,
cmd3_row_addr ,
cmd3_bank_addr ,
cmd3_is_valid ,
cmd3_multicast_req ,
cmd4_is_a_read ,
cmd4_is_a_write ,
cmd4_chip_addr ,
cmd4_row_addr ,
cmd4_bank_addr ,
cmd4_is_valid ,
cmd4_multicast_req ,
cmd5_is_a_read ,
cmd5_is_a_write ,
cmd5_chip_addr ,
cmd5_row_addr ,
cmd5_bank_addr ,
cmd5_is_valid ,
cmd5_multicast_req ,
cmd6_is_a_read ,
cmd6_is_a_write ,
cmd6_chip_addr ,
cmd6_row_addr ,
cmd6_bank_addr ,
cmd6_is_valid ,
cmd6_multicast_req ,
cmd7_is_a_read ,
cmd7_is_a_write ,
cmd7_chip_addr ,
cmd7_row_addr ,
cmd7_bank_addr ,
cmd7_is_valid ,
cmd7_multicast_req
);
localparam local_be_width = local_data_width/8;
localparam internal_addr_width = local_addr_width + ctl_hrb_enabled;
input ctl_clk ;
input [4 : 0] ctl_reset_n ; // resynced reset to remove revocery failure in hcx
input ctl_half_clk ;
input ctl_half_clk_reset_n;
input local_read_req ;
input local_write_req ;
input [local_size_width-1:0] local_size ;
input local_autopch_req ;
input local_multicast ;
input local_burstbegin ;
input [local_addr_width-1:0] local_addr ;
input [local_data_width -1 : 0] local_wdata ;
input [local_be_width -1 : 0] local_be ;
input [1:0] addr_order ;
input [mem_if_csr_col_width-1:0] col_width_from_csr ;
input [mem_if_csr_row_width-1:0] row_width_from_csr ;
input [mem_if_csr_bank_width-1:0] bank_width_from_csr ;
input [mem_if_csr_cs_width-1:0] cs_width_from_csr ;
input regdimm_enable ;
input [internal_data_width -1 : 0] ecc_rdata ;
input [dwidth_ratio/2-1:0] ecc_rdata_valid ;
input ecc_rdata_error ;
//input from state machine
input wdata_fifo_read ;
input fetch ;
//input from phy
input ctl_cal_success ;
input ctl_cal_fail ;
output local_init_done ;
output local_ready ;
output local_rdata_valid ;
output local_rdata_error ;
output [local_data_width -1 : 0] local_rdata ;
output local_wdata_req ;
output [internal_data_width -1 : 0]wdata_fifo_wdata ;
output [internal_data_width/8 -1 : 0]wdata_fifo_be ;
output [wdata_beats_width-1:0] beats_in_wfifo ;
output write_req_to_wfifo ;
output [internal_data_width/8 -1 : 0]be_to_wfifo ;
output cmd_fifo_empty ;
output cmd_fifo_full ;
output cmd_fifo_wren ;
output cmd0_is_a_read ;
output cmd0_is_a_write ;
output cmd0_autopch_req ;
output [1:0] cmd0_burstcount ;
output [mem_if_chip_bits-1:0] cmd0_chip_addr ;
output [mem_if_row_width-1:0] cmd0_row_addr ;
output [mem_if_ba_width-1:0] cmd0_bank_addr ;
output [mem_if_col_width-1:0] cmd0_col_addr ;
output cmd0_is_valid ;
output cmd0_multicast_req ;
output cmd1_is_a_read ;
output cmd1_is_a_write ;
output [mem_if_chip_bits-1:0] cmd1_chip_addr ;
output [mem_if_row_width-1:0] cmd1_row_addr ;
output [mem_if_ba_width-1:0] cmd1_bank_addr ;
output cmd1_is_valid ;
output cmd1_multicast_req ;
output cmd2_is_a_read ;
output cmd2_is_a_write ;
output [mem_if_chip_bits-1:0] cmd2_chip_addr ;
output [mem_if_row_width-1:0] cmd2_row_addr ;
output [mem_if_ba_width-1:0] cmd2_bank_addr ;
output cmd2_is_valid ;
output cmd2_multicast_req ;
output cmd3_is_a_read ;
output cmd3_is_a_write ;
output [mem_if_chip_bits-1:0] cmd3_chip_addr ;
output [mem_if_row_width-1:0] cmd3_row_addr ;
output [mem_if_ba_width-1:0] cmd3_bank_addr ;
output cmd3_is_valid ;
output cmd3_multicast_req ;
output cmd4_is_a_read ;
output cmd4_is_a_write ;
output [mem_if_chip_bits-1:0] cmd4_chip_addr ;
output [mem_if_row_width-1:0] cmd4_row_addr ;
output [mem_if_ba_width-1:0] cmd4_bank_addr ;
output cmd4_is_valid ;
output cmd4_multicast_req ;
output cmd5_is_a_read ;
output cmd5_is_a_write ;
output [mem_if_chip_bits-1:0] cmd5_chip_addr ;
output [mem_if_row_width-1:0] cmd5_row_addr ;
output [mem_if_ba_width-1:0] cmd5_bank_addr ;
output cmd5_is_valid ;
output cmd5_multicast_req ;
output cmd6_is_a_read ;
output cmd6_is_a_write ;
output [mem_if_chip_bits-1:0] cmd6_chip_addr ;
output [mem_if_row_width-1:0] cmd6_row_addr ;
output [mem_if_ba_width-1:0] cmd6_bank_addr ;
output cmd6_is_valid ;
output cmd6_multicast_req ;
output cmd7_is_a_read ;
output cmd7_is_a_write ;
output [mem_if_chip_bits-1:0] cmd7_chip_addr ;
output [mem_if_row_width-1:0] cmd7_row_addr ;
output [mem_if_ba_width-1:0] cmd7_bank_addr ;
output cmd7_is_valid ;
output cmd7_multicast_req ;
wire local_ready ;
wire internal_ready ;
wire wdata_fifo_full;
wire read_req_to_cmd_gen ;
wire write_req_to_cmd_gen ;
wire write_req_to_wfifo;
wire [internal_data_width -1 : 0] wdata_to_wfifo;
wire [internal_data_width/8 -1 : 0]be_to_wfifo;
wire avalon_write_req;
wire [internal_data_width -1 : 0] avalon_wdata;
wire [internal_addr_width -1 : 0] avalon_addr;
wire [internal_addr_width -1 : 0] addr_to_cmd_gen;
wire [internal_size_width -1 : 0] avalon_size;
wire [internal_size_width -1 : 0] size_to_cmd_gen;
wire [internal_data_width/8 -1 : 0]avalon_be;
wire avalon_read_req;
wire avalon_burstbegin;
wire avalon_multicast;
wire avalon_autopch_req;
wire multicast_to_cmd_gen;
wire autopch_to_cmd_gen;
reg gate_ready_in_reset;
wire int_local_multicast;
wire ready_from_cmd_gen;
wire read_req_from_cmd_gen;
wire write_req_from_cmd_gen;
wire [1 : 0] size_from_cmd_gen;
wire autopch_from_cmd_gen;
wire [mem_if_chip_bits -1 : 0] cs_addr_from_cmd_gen;
wire [mem_if_ba_width -1 : 0] bank_addr_from_cmd_gen;
wire [mem_if_row_width -1 : 0] row_addr_from_cmd_gen;
wire [mem_if_col_width -1 : 0] col_addr_from_cmd_gen;
wire multicast_from_cmd_gen;
//======================= instantiation of alt_ddrx_wdata_fifo =========================
alt_ddrx_wdata_fifo #(
.wdata_beats_width (wdata_beats_width),
.local_data_width (internal_data_width),
.local_size_width (local_size_width),
.dwidth_ratio (dwidth_ratio),
.family (family)
) wdata_fifo_inst (
// input
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[0]),
.write_req_to_wfifo (write_req_to_wfifo),
.wdata_to_wfifo (wdata_to_wfifo),
.be_to_wfifo (be_to_wfifo),
.wdata_fifo_read (wdata_fifo_read),
//output
.wdata_fifo_full (wdata_fifo_full),
.wdata_fifo_wdata (wdata_fifo_wdata),
.wdata_fifo_be (wdata_fifo_be),
.beats_in_wfifo (beats_in_wfifo)
);
//======================= end of instantiation of alt_ddrx_wdata_fifo ===================
//======================= instantiation of alt_ddrx_cmd_gen ===========================
alt_ddrx_cmd_gen #(
.mem_if_csr_col_width (mem_if_csr_col_width ),
.mem_if_csr_row_width (mem_if_csr_row_width ),
.mem_if_csr_bank_width (mem_if_csr_bank_width ),
.mem_if_csr_cs_width (mem_if_csr_cs_width ),
.mem_if_row_width (mem_if_row_width),
.mem_if_col_width (mem_if_col_width),
.mem_if_ba_width (mem_if_ba_width),
.mem_if_chip_bits (mem_if_chip_bits),
.local_addr_width (internal_addr_width),
.internal_size_width (internal_size_width),
.dwidth_ratio (dwidth_ratio),
.memory_burstlength (memory_burstlength),
.min_col (min_col),
.min_row (min_row),
.min_bank (min_bank),
.min_cs (min_cs)
) cmd_gen_inst (
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[1]),
//local input
.local_read_req (read_req_to_cmd_gen),
.local_write_req (avalon_write_req),
.processed_write_req (write_req_to_cmd_gen),
.local_size (size_to_cmd_gen),
.local_autopch_req (autopch_to_cmd_gen),
.local_addr (addr_to_cmd_gen),
.local_multicast (multicast_to_cmd_gen),
//input from csr
.addr_order (addr_order),
.col_width_from_csr (col_width_from_csr ),
.row_width_from_csr (row_width_from_csr ),
.bank_width_from_csr (bank_width_from_csr),
.cs_width_from_csr (cs_width_from_csr),
//misc
.ready_out (ready_from_cmd_gen),
.ready_in (internal_ready),
//output
.read_req (read_req_from_cmd_gen),
.write_req (write_req_from_cmd_gen),
.size (size_from_cmd_gen),
.autopch_req (autopch_from_cmd_gen),
.cs_addr (cs_addr_from_cmd_gen),
.bank_addr (bank_addr_from_cmd_gen),
.row_addr (row_addr_from_cmd_gen),
.col_addr (col_addr_from_cmd_gen),
.multicast (multicast_from_cmd_gen)
);
//================= end of instantiation of alt_ddrx_cmd_gen ======================
//======================= instantiation of alt_ddrx_cmd_queue ===========================
alt_ddrx_cmd_queue #(
.mem_if_csr_col_width (mem_if_csr_col_width ),
.mem_if_csr_row_width (mem_if_csr_row_width ),
.mem_if_csr_bank_width (mem_if_csr_bank_width ),
.mem_if_csr_cs_width (mem_if_csr_cs_width ),
.ctl_cmd_queue_depth (ctl_cmd_queue_depth),
.ctl_look_ahead_depth (ctl_look_ahead_depth),
.mem_if_row_width (mem_if_row_width),
.mem_if_col_width (mem_if_col_width),
.mem_if_ba_width (mem_if_ba_width),
.mem_if_chip_bits (mem_if_chip_bits),
.local_addr_width (internal_addr_width),
.dwidth_ratio (dwidth_ratio),
.enable_burst_merge (enable_burst_merge),
.min_col (min_col),
.min_row (min_row),
.min_bank (min_bank),
.min_cs (min_cs)
) cmd_queue_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n[2] ),
.read_req_to_cmd_queue (read_req_from_cmd_gen),
.write_req_to_cmd_queue (write_req_from_cmd_gen),
.local_size (size_from_cmd_gen ),
.local_autopch_req (autopch_from_cmd_gen ),
.local_cs_addr (cs_addr_from_cmd_gen ),
.local_bank_addr (bank_addr_from_cmd_gen ),
.local_row_addr (row_addr_from_cmd_gen ),
.local_col_addr (col_addr_from_cmd_gen ),
.local_multicast (multicast_from_cmd_gen ),
//input from state machine
.fetch (fetch ),
.cmd_fifo_empty (cmd_fifo_empty ),
.cmd_fifo_full (cmd_fifo_full ),
//output
.cmd_fifo_wren (cmd_fifo_wren ),
.cmd0_is_a_read (cmd0_is_a_read ),
.cmd0_is_a_write (cmd0_is_a_write ),
.cmd0_autopch_req (cmd0_autopch_req ),
.cmd0_burstcount (cmd0_burstcount ),
.cmd0_chip_addr (cmd0_chip_addr ),
.cmd0_row_addr (cmd0_row_addr ),
.cmd0_bank_addr (cmd0_bank_addr ),
.cmd0_col_addr (cmd0_col_addr ),
.cmd0_is_valid (cmd0_is_valid ),
.cmd0_multicast_req (cmd0_multicast_req ),
.cmd1_is_a_read (cmd1_is_a_read ),
.cmd1_is_a_write (cmd1_is_a_write ),
.cmd1_chip_addr (cmd1_chip_addr ),
.cmd1_row_addr (cmd1_row_addr ),
.cmd1_bank_addr (cmd1_bank_addr ),
.cmd1_is_valid (cmd1_is_valid ),
.cmd1_multicast_req (cmd1_multicast_req ),
.cmd2_is_a_read (cmd2_is_a_read ),
.cmd2_is_a_write (cmd2_is_a_write ),
.cmd2_chip_addr (cmd2_chip_addr ),
.cmd2_row_addr (cmd2_row_addr ),
.cmd2_bank_addr (cmd2_bank_addr ),
.cmd2_is_valid (cmd2_is_valid ),
.cmd2_multicast_req (cmd2_multicast_req ),
.cmd3_is_a_read (cmd3_is_a_read ),
.cmd3_is_a_write (cmd3_is_a_write ),
.cmd3_chip_addr (cmd3_chip_addr ),
.cmd3_row_addr (cmd3_row_addr ),
.cmd3_bank_addr (cmd3_bank_addr ),
.cmd3_is_valid (cmd3_is_valid ),
.cmd3_multicast_req (cmd3_multicast_req ),
.cmd4_is_a_read (cmd4_is_a_read ),
.cmd4_is_a_write (cmd4_is_a_write ),
.cmd4_chip_addr (cmd4_chip_addr ),
.cmd4_row_addr (cmd4_row_addr ),
.cmd4_bank_addr (cmd4_bank_addr ),
.cmd4_is_valid (cmd4_is_valid ),
.cmd4_multicast_req (cmd4_multicast_req ),
.cmd5_is_a_read (cmd5_is_a_read ),
.cmd5_is_a_write (cmd5_is_a_write ),
.cmd5_chip_addr (cmd5_chip_addr ),
.cmd5_row_addr (cmd5_row_addr ),
.cmd5_bank_addr (cmd5_bank_addr ),
.cmd5_is_valid (cmd5_is_valid ),
.cmd5_multicast_req (cmd5_multicast_req ),
.cmd6_is_a_read (cmd6_is_a_read ),
.cmd6_is_a_write (cmd6_is_a_write ),
.cmd6_chip_addr (cmd6_chip_addr ),
.cmd6_row_addr (cmd6_row_addr ),
.cmd6_bank_addr (cmd6_bank_addr ),
.cmd6_is_valid (cmd6_is_valid ),
.cmd6_multicast_req (cmd6_multicast_req ),
.cmd7_is_a_read (cmd7_is_a_read ),
.cmd7_is_a_write (cmd7_is_a_write ),
.cmd7_chip_addr (cmd7_chip_addr ),
.cmd7_row_addr (cmd7_row_addr ),
.cmd7_bank_addr (cmd7_bank_addr ),
.cmd7_is_valid (cmd7_is_valid ),
.cmd7_multicast_req (cmd7_multicast_req )
);
//================= end of instantiation of alt_ddrx_cmd_queue ======================
assign internal_ready = (cmd_fifo_full == 1'b0) & (wdata_fifo_full == 1'b0) & (gate_ready_in_reset == 1'b1);
assign local_init_done = ctl_cal_success & ~ctl_cal_fail;
//registered gate_ready_in_reset
always @(posedge ctl_clk or negedge ctl_reset_n[4]) begin
if (~ctl_reset_n[4]) begin
gate_ready_in_reset <= 1'b0;
end
else begin
gate_ready_in_reset <= 1'b1;
end
end
generate if(local_if_type == "avalon") begin
assign local_wdata_req = 1'b0;
assign write_req_to_wfifo = avalon_write_req;
assign read_req_to_cmd_gen = avalon_read_req;
assign be_to_wfifo = avalon_be;
assign wdata_to_wfifo = avalon_wdata;
assign addr_to_cmd_gen = avalon_addr;
assign size_to_cmd_gen = avalon_size;
assign multicast_to_cmd_gen = avalon_multicast;
assign autopch_to_cmd_gen = avalon_autopch_req;
if (ctl_hrb_enabled == 0) begin
reg prolong_burstbegin;
assign write_req_to_cmd_gen = avalon_write_req & (avalon_burstbegin | prolong_burstbegin);
// removed reset logic in order to capture burst begin signal when request is issued before internal resynced reset signal de-asserted
always @(posedge ctl_clk) begin
//to detect the case where internal_ready gone low at the start of the burst.
//burst begin gone high for one clock cycle only, so we need to manually prolong
//burst begin signal until internal_ready goes high.
if(ready_from_cmd_gen == 1'b0 & local_write_req == 1'b1)begin
if(avalon_burstbegin == 1'b1) begin
prolong_burstbegin <= 1'b1;
end
else
prolong_burstbegin <= prolong_burstbegin;
end
else if(ready_from_cmd_gen == 1'b1 & local_write_req == 1'b1)begin
prolong_burstbegin <= 1'b0;
end
end
end
else begin
assign write_req_to_cmd_gen = avalon_write_req & avalon_burstbegin;
end
//======================= instantiation of alt_ddrx_avalon_if =========================
alt_ddrx_avalon_if #(
.internal_size_width (internal_size_width),
.dwidth_ratio (dwidth_ratio),
.local_data_width (local_data_width),
.internal_data_width (internal_data_width),
.ctl_hrb_enabled (ctl_hrb_enabled ),
.local_addr_width (local_addr_width),
.internal_addr_width (internal_addr_width),
.local_size_width (local_size_width)
) avalon_if_inst (
// input
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[3]),
.ctl_half_clk (ctl_half_clk),
.ctl_half_clk_reset_n (ctl_half_clk_reset_n),
.local_write_req (local_write_req),
.local_wdata (local_wdata),
.local_be (local_be),
.local_addr (local_addr),
.internal_ready (ready_from_cmd_gen),
.local_read_req (local_read_req),
.local_size (local_size),
.local_burstbegin (local_burstbegin),
.ecc_rdata (ecc_rdata),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_rdata_error (ecc_rdata_error),
.local_multicast (int_local_multicast),
.local_autopch_req (local_autopch_req),
//output
.avalon_wdata (avalon_wdata),
.avalon_be (avalon_be),
.avalon_write_req (avalon_write_req),
.avalon_read_req (avalon_read_req),
.avalon_addr (avalon_addr),
.avalon_size (avalon_size),
.local_ready (local_ready),
.avalon_burstbegin (avalon_burstbegin),
.local_rdata (local_rdata),
.local_rdata_error (local_rdata_error),
.local_rdata_valid (local_rdata_valid),
.avalon_multicast (avalon_multicast),
.avalon_autopch_req (avalon_autopch_req)
);
//======================= end of instantiation of alt_ddrx_avalon_if ===================
end
else begin //native mode
reg wdata_req;
reg wdata_req_r;
reg [wdata_beats_width-1:0] beats_to_ask_for;
assign local_wdata_req = wdata_req;
assign write_req_to_cmd_gen = local_write_req;
assign write_req_to_wfifo = wdata_req_r;
assign read_req_to_cmd_gen = local_read_req;
assign be_to_wfifo = local_be;
assign wdata_to_wfifo = local_wdata;
assign addr_to_cmd_gen = local_addr;
assign size_to_cmd_gen = local_size;
assign multicast_to_cmd_gen = int_local_multicast;
assign autopch_to_cmd_gen = local_autopch_req;
//used only in native mode
always @(posedge ctl_clk or negedge ctl_reset_n[4]) begin
if (~ctl_reset_n[4]) begin
wdata_req <= 1'b0; //request signal to user
wdata_req_r <= 1'b0; //request signal to wdata fifo
beats_to_ask_for <= 0;
end
else begin
wdata_req_r <= wdata_req;
if ((internal_ready == 1'b1) & (local_write_req == 1'b1) & (local_if_type == "native")) begin
if (wdata_req == 1'b1) begin
wdata_req <= beats_to_ask_for > 0;
beats_to_ask_for <= beats_to_ask_for + local_size - 1;
end
else begin
if (local_init_done == 1'b1) begin
wdata_req <= 1'b1;
end
beats_to_ask_for <= beats_to_ask_for + local_size;
end
end
else if ((beats_to_ask_for > 0) & (wdata_req == 1'b1) & (local_init_done == 1'b1)) begin
beats_to_ask_for <= beats_to_ask_for - 1;
wdata_req <= beats_to_ask_for > 1;
end
else begin
wdata_req <= 1'b0;
beats_to_ask_for <= beats_to_ask_for;
end
end
end
end
endgenerate
generate
if ((ctl_csr_enabled == 1) && (mem_type == "ddr3")) begin
assign int_local_multicast = (regdimm_enable == 1) ? 0 : local_multicast ;
end
else if ((ctl_regdimm_enabled == 1) && (mem_type == "ddr3")) begin
assign int_local_multicast = 0;
end
else begin
assign int_local_multicast = local_multicast ;
end
endgenerate
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
(
clkout,
oscena);
parameter DEVICE_FAMILY = "MAX 10";
parameter DEVICE_ID = "08";
parameter CLOCK_FREQUENCY = "dummy";
output clkout;
input oscena;
wire wire_clkout;
assign clkout = wire_clkout;
// -------------------------------------------------------------------
// Instantiate wysiwyg for chipidblock according to device family
// -------------------------------------------------------------------
generate
if (DEVICE_FAMILY == "MAX 10") begin
fiftyfivenm_oscillator # ( //MAX 10
.device_id(DEVICE_ID),
.clock_frequency(CLOCK_FREQUENCY)
) oscillator_dut (
.clkout(wire_clkout),
.clkout1(),
.oscena(oscena));
end
endgenerate
endmodule //altera_int_osc
//VALID FILE
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2017/08/13 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_core
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
// MIF Streaming parameters
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata,
//other
output wire mif_start_out,
output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr
);
localparam mode_WR = 1'b0;
localparam mode_POLL = 1'b1;
localparam MODE_REG = 6'b000000;
localparam STATUS_REG = 6'b000001;
localparam START_REG = 6'b000010;
localparam N_REG = 6'b000011;
localparam M_REG = 6'b000100;
localparam C_COUNTERS_REG = 6'b000101;
localparam DPS_REG = 6'b000110;
localparam DSM_REG = 6'b000111;
localparam BWCTRL_REG = 6'b001000;
localparam CP_CURRENT_REG = 6'b001001;
localparam ANY_DPRIO = 6'b100000;
localparam CNT_BASE = 5'b001010;
localparam MIF_REG = 6'b011111;
//C Counters
localparam number_of_counters = 5'd18;
localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
//C counter addresses
localparam C_CNT_0_DIV_ADDR = 5'h00;
localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
//N counter addresses
localparam N_CNT_DIV_ADDR = 5'h13;
localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
//M counter addresses
localparam M_CNT_DIV_ADDR = 5'h12;
localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
//DSM address
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
localparam DSM_K_READY_ADDR = 5'h17;
localparam DSM_K_DITHER_ADDR = 5'h17;
localparam DSM_OUT_SEL_ADDR = 6'h30;
//Other DSM params
localparam DSM_K_READY_BIT_INDEX = 4'd11;
//BWCTRL address
//Bit 0-3 of addr
localparam BWCTRL_ADDR = 6'h30;
//CP_CURRENT address
//Bit 0-2 of addr
localparam CP_CURRENT_ADDR = 6'h31;
localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
wire clk;
wire reset;
wire gnd;
wire [5: 0] slave_address;
wire slave_read;
wire slave_write;
wire [31: 0] slave_writedata;
reg [31: 0] slave_readdata_d;
reg [31: 0] slave_readdata_q;
wire slave_waitrequest;
assign clk = mgmt_clk;
assign slave_address = mgmt_address;
assign slave_read = mgmt_read;
assign slave_write = mgmt_write;
assign slave_writedata = mgmt_writedata;
// Outputs
assign mgmt_readdata = slave_readdata_q;
assign mgmt_waitrequest = slave_waitrequest;
//internal signals
wire locked;
wire pll_start;
wire pll_start_valid;
reg status_read;
wire read_slave_mode_asserted;
wire pll_start_asserted;
reg [1:0] current_state;
reg [1:0] next_state;
reg slave_mode;
reg status;//0=busy, 1=ready
//user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
//declaring the init wires. These will have 0 on them for 64 clk cycles
wire [ 5:0] init_dprio_address;
wire init_dprio_read;
wire [ 1:0] init_dprio_byteen;
wire init_dprio_write;
wire [15:0] init_dprio_writedata;
wire init_atpgmode;
wire init_mdio_dis;
wire init_scanen;
wire init_ser_shift_load;
wire dprio_init_done;
//DPRIO output signals after initialization is done
wire dprio_clk;
reg avmm_dprio_write;
reg avmm_dprio_read;
reg [5:0] avmm_dprio_address;
reg [15:0] avmm_dprio_writedata;
reg [1:0] avmm_dprio_byteen;
wire avmm_atpgmode;
wire avmm_mdio_dis;
wire avmm_scanen;
//Final output wires that are muxed between the init and avmm wires.
wire dprio_init_reset;
wire [5:0] dprio_address /*synthesis keep*/;
wire dprio_read/*synthesis keep*/;
wire [1:0] dprio_byteen/*synthesis keep*/;
wire dprio_write/*synthesis keep*/;
wire [15:0] dprio_writedata/*synthesis keep*/;
wire dprio_mdio_dis/*synthesis keep*/;
wire dprio_ser_shift_load/*synthesis keep*/;
wire dprio_atpgmode/*synthesis keep*/;
wire dprio_scanen/*synthesis keep*/;
//other PLL signals for dyn ph shift
wire phase_done/*synthesis keep*/;
wire phase_en/*synthesis keep*/;
wire up_dn/*synthesis keep*/;
wire [4:0] cnt_sel;
//DPRIO input signals
wire [15:0] dprio_readdata;
//internal logic signals
//storage registers for user sent data
reg dprio_temp_read_1;
reg dprio_temp_read_2;
reg dprio_start;
reg mif_start_assert;
reg dps_start_assert;
wire usr_valid_changes;
reg [3:0] dprio_cur_state;
reg [3:0] dprio_next_state;
reg [15:0] dprio_temp_m_n_c_readdata_1_d;
reg [15:0] dprio_temp_m_n_c_readdata_2_d;
reg [15:0] dprio_temp_m_n_c_readdata_1_q;
reg [15:0] dprio_temp_m_n_c_readdata_2_q;
reg dprio_write_done;
//C counters signals
reg [7:0] usr_c_cnt_lo;
reg [7:0] usr_c_cnt_hi;
reg usr_c_cnt_bypass_en;
reg usr_c_cnt_odd_duty_div_en;
reg [7:0] temp_c_cnt_lo [0:17];
reg [7:0] temp_c_cnt_hi [0:17];
reg temp_c_cnt_bypass_en [0:17];
reg temp_c_cnt_odd_duty_div_en [0:17];
reg any_c_cnt_changed;
reg all_c_cnt_done_q;
reg all_c_cnt_done_d;
reg [17:0] c_cnt_changed;
reg [17:0] c_cnt_done_d;
reg [17:0] c_cnt_done_q;
//N counter signals
reg [7:0] usr_n_cnt_lo;
reg [7:0] usr_n_cnt_hi;
reg usr_n_cnt_bypass_en;
reg usr_n_cnt_odd_duty_div_en;
reg n_cnt_changed;
reg n_cnt_done_d;
reg n_cnt_done_q;
//M counter signals
reg [7:0] usr_m_cnt_lo;
reg [7:0] usr_m_cnt_hi;
reg usr_m_cnt_bypass_en;
reg usr_m_cnt_odd_duty_div_en;
reg m_cnt_changed;
reg m_cnt_done_d;
reg m_cnt_done_q;
//dyn phase regs
reg [15:0] usr_num_shifts;
reg [4:0] usr_cnt_sel /*synthesis preserve*/;
reg usr_up_dn;
reg dps_changed;
wire dps_changed_valid;
wire dps_done;
//DSM Signals
reg [31:0] usr_k_value;
reg dsm_k_changed;
reg dsm_k_done_d;
reg dsm_k_done_q;
reg dsm_k_ready_false_done_d;
//BW signals
reg [3:0] usr_bwctrl_value;
reg bwctrl_changed;
reg bwctrl_done_d;
reg bwctrl_done_q;
//CP signals
reg [2:0] usr_cp_current_value;
reg cp_current_changed;
reg cp_current_done_d;
reg cp_current_done_q;
//Manual DPRIO signals
reg manual_dprio_done_q;
reg manual_dprio_done_d;
reg manual_dprio_changed;
reg [5:0] usr_dprio_address;
reg [15:0] usr_dprio_writedata_0;
reg usr_r_w;
//keeping track of which operation happened last
reg [5:0] operation_address;
// Address wires for all C_counter DPRIO registers
// These are outputs of LUTS, changing depending
// on whether PLL_0 or PLL_1 being used
//Fitter will tell if FPLL1 is being used
wire fpll_1;
// other
reg mif_reg_asserted;
// MAIN FSM
always @(posedge clk)
begin
if (reset)
begin
dprio_cur_state <= DPRIO_IDLE;
current_state <= IDLE;
end
else
begin
current_state <= next_state;
dprio_cur_state <= dprio_next_state;
end
end
always @(*)
begin
case(current_state)
IDLE:
begin
if (pll_start & !slave_waitrequest & usr_valid_changes)
next_state = WAIT_ON_LOCK;
else
next_state = IDLE;
end
WAIT_ON_LOCK:
begin
if (locked & dps_done & dprio_write_done) // received locked high from PLL
begin
if (slave_mode==mode_WR) //if the mode is waitrequest, then
// goto IDLE state directly
next_state = IDLE;
else
next_state = LOCKED; //otherwise go the locked state
end
else
next_state = WAIT_ON_LOCK;
end
LOCKED:
begin
if (status_read) // stay in LOCKED until user reads status
next_state = IDLE;
else
next_state = LOCKED;
end
default: next_state = 2'bxx;
endcase
end
// ask the pll to start reconfig
assign pll_start = (pll_start_asserted & (current_state==IDLE)) ;
assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ;
// WRITE OPERATIONS
assign pll_start_asserted = slave_write & (slave_address == START_REG);
assign mif_start_out = pll_start & mif_reg_asserted;
//reading the mode register to determine what mode the slave will operate
//in.
always @(posedge clk)
begin
if (reset)
slave_mode <= mode_WR;
else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
slave_mode <= slave_writedata[0];
end
//record which values user wants to change.
//reading in the actual values that need to be reconfigged and sending
//them to the PLL
always @(posedge clk)
begin
if (reset)
begin
//reset all regs here
//BW signals reset
usr_bwctrl_value <= 0;
bwctrl_changed <= 0;
bwctrl_done_q <= 0;
//CP signals reset
usr_cp_current_value <= 0;
cp_current_changed <= 0;
cp_current_done_q <= 0;
//DSM signals reset
usr_k_value <= 0;
dsm_k_changed <= 0;
dsm_k_done_q <= 0;
//N counter signals reset
usr_n_cnt_lo <= 0;
usr_n_cnt_hi <= 0;
usr_n_cnt_bypass_en <= 0;
usr_n_cnt_odd_duty_div_en <= 0;
n_cnt_changed <= 0;
n_cnt_done_q <= 0;
//M counter signals reset
usr_m_cnt_lo <= 0;
usr_m_cnt_hi <= 0;
usr_m_cnt_bypass_en <= 0;
usr_m_cnt_odd_duty_div_en <= 0;
m_cnt_changed <= 0;
m_cnt_done_q <= 0;
//C counter signals reset
usr_c_cnt_lo <= 0;
usr_c_cnt_hi <= 0;
usr_c_cnt_bypass_en <= 0;
usr_c_cnt_odd_duty_div_en <= 0;
any_c_cnt_changed <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
//generic signals
dprio_start <= 0;
mif_start_assert <= 0;
dps_start_assert <= 0;
dprio_temp_m_n_c_readdata_1_q <= 0;
dprio_temp_m_n_c_readdata_2_q <= 0;
c_cnt_done_q <= 0;
//DPS signals
usr_up_dn <= 0;
usr_cnt_sel <= 0;
usr_num_shifts <= 0;
dps_changed <= 0;
//manual DPRIO signals
manual_dprio_changed <= 0;
usr_dprio_address <= 0;
usr_dprio_writedata_0 <= 0;
usr_r_w <= 0;
operation_address <= 0;
mif_reg_asserted <= 0;
mif_base_addr <= 0;
end
else
begin
if (dprio_temp_read_1)
begin
dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d;
end
if (dprio_temp_read_2)
begin
dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d;
end
if ((dps_done)) dps_changed <= 0;
if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
if (mif_start_out == 1'b1)
mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
if (dps_done != 1'b1)
dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
if (dprio_next_state == ONE)
dprio_start <= 0;
if (dprio_write_done)
begin
bwctrl_done_q <= 0;
cp_current_done_q <= 0;
dsm_k_done_q <= 0;
dsm_k_done_q <= 0;
n_cnt_done_q <= 0;
m_cnt_done_q <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
dsm_k_changed <= 0;
n_cnt_changed <= 0;
m_cnt_changed <= 0;
any_c_cnt_changed <= 0;
bwctrl_changed <= 0;
cp_current_changed <= 0;
manual_dprio_changed <= 0;
manual_dprio_done_q <= 0;
if (dps_changed | dps_changed_valid | !dps_done )
begin
usr_cnt_sel <= usr_cnt_sel;
end
else
begin
usr_cnt_sel <= 0;
end
mif_reg_asserted <= 0;
end
else
begin
dsm_k_changed <= dsm_k_changed;
n_cnt_changed <= n_cnt_changed;
m_cnt_changed <= m_cnt_changed;
any_c_cnt_changed <= any_c_cnt_changed;
manual_dprio_changed <= manual_dprio_changed;
mif_reg_asserted <= mif_reg_asserted;
usr_cnt_sel <= usr_cnt_sel;
end
if(slave_write & !slave_waitrequest)
begin
case(slave_address)
//read in the values here from the user and act on them
DSM_REG:
begin
operation_address <= DSM_REG;
usr_k_value <= slave_writedata[31:0];
dsm_k_changed <= 1'b1;
dsm_k_done_q <= 0;
dprio_start <= 1'b1;
end
N_REG:
begin
operation_address <= N_REG;
usr_n_cnt_lo <= slave_writedata[7:0];
usr_n_cnt_hi <= slave_writedata[15:8];
usr_n_cnt_bypass_en <= slave_writedata[16];
usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
n_cnt_changed <= 1'b1;
n_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
M_REG:
begin
operation_address <= M_REG;
usr_m_cnt_lo <= slave_writedata[7:0];
usr_m_cnt_hi <= slave_writedata[15:8];
usr_m_cnt_bypass_en <= slave_writedata[16];
usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
m_cnt_changed <= 1'b1;
m_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
DPS_REG:
begin
operation_address <= DPS_REG;
usr_num_shifts <= slave_writedata[15:0];
usr_cnt_sel <= slave_writedata[20:16];
usr_up_dn <= slave_writedata[21];
dps_changed <= 1;
dps_start_assert <= 1;
end
C_COUNTERS_REG:
begin
operation_address <= C_COUNTERS_REG;
usr_c_cnt_lo <= slave_writedata[7:0];
usr_c_cnt_hi <= slave_writedata[15:8];
usr_c_cnt_bypass_en <= slave_writedata[16];
usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
usr_cnt_sel <= slave_writedata[22:18];
any_c_cnt_changed <= 1'b1;
all_c_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
BWCTRL_REG:
begin
usr_bwctrl_value <= slave_writedata[3:0];
bwctrl_changed <= 1'b1;
bwctrl_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= BWCTRL_REG;
end
CP_CURRENT_REG:
begin
usr_cp_current_value <= slave_writedata[2:0];
cp_current_changed <= 1'b1;
cp_current_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= CP_CURRENT_REG;
end
ANY_DPRIO:
begin
operation_address <= ANY_DPRIO;
manual_dprio_changed <= 1'b1;
usr_dprio_address <= slave_writedata[5:0];
usr_dprio_writedata_0 <= slave_writedata[21:6];
usr_r_w <= slave_writedata[22];
manual_dprio_done_q <= 0;
dprio_start <= 1'b1;
end
MIF_REG:
begin
mif_reg_asserted <= 1'b1;
mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
mif_start_assert <= 1'b1;
end
endcase
end
end
end
//C Counter assigning values to the 2-d array of values for each C counter
reg [4:0] j;
always @(posedge clk)
begin
if (reset)
begin
c_cnt_changed[17:0] <= 0;
for (j = 0; j < number_of_counters; j = j + 1'b1)
begin : c_cnt_reset
temp_c_cnt_bypass_en[j] <= 0;
temp_c_cnt_odd_duty_div_en[j] <= 0;
temp_c_cnt_lo[j][7:0] <= 0;
temp_c_cnt_hi[j][7:0] <= 0;
end
end
else
begin
if (dprio_write_done)
begin
c_cnt_changed <= 0;
end
if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
begin
case (cnt_sel)
CNT_0:
begin
temp_c_cnt_lo [0] <= usr_c_cnt_lo;
temp_c_cnt_hi [0] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [0] <= 1'b1;
end
CNT_1:
begin
temp_c_cnt_lo [1] <= usr_c_cnt_lo;
temp_c_cnt_hi [1] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [1] <= 1'b1;
end
CNT_2:
begin
temp_c_cnt_lo [2] <= usr_c_cnt_lo;
temp_c_cnt_hi [2] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [2] <= 1'b1;
end
CNT_3:
begin
temp_c_cnt_lo [3] <= usr_c_cnt_lo;
temp_c_cnt_hi [3] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [3] <= 1'b1;
end
CNT_4:
begin
temp_c_cnt_lo [4] <= usr_c_cnt_lo;
temp_c_cnt_hi [4] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [4] <= 1'b1;
end
CNT_5:
begin
temp_c_cnt_lo [5] <= usr_c_cnt_lo;
temp_c_cnt_hi [5] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [5] <= 1'b1;
end
CNT_6:
begin
temp_c_cnt_lo [6] <= usr_c_cnt_lo;
temp_c_cnt_hi [6] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [6] <= 1'b1;
end
CNT_7:
begin
temp_c_cnt_lo [7] <= usr_c_cnt_lo;
temp_c_cnt_hi [7] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [7] <= 1'b1;
end
CNT_8:
begin
temp_c_cnt_lo [8] <= usr_c_cnt_lo;
temp_c_cnt_hi [8] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [8] <= 1'b1;
end
CNT_9:
begin
temp_c_cnt_lo [9] <= usr_c_cnt_lo;
temp_c_cnt_hi [9] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [9] <= 1'b1;
end
CNT_10:
begin
temp_c_cnt_lo [10] <= usr_c_cnt_lo;
temp_c_cnt_hi [10] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [10] <= 1'b1;
end
CNT_11:
begin
temp_c_cnt_lo [11] <= usr_c_cnt_lo;
temp_c_cnt_hi [11] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [11] <= 1'b1;
end
CNT_12:
begin
temp_c_cnt_lo [12] <= usr_c_cnt_lo;
temp_c_cnt_hi [12] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [12] <= 1'b1;
end
CNT_13:
begin
temp_c_cnt_lo [13] <= usr_c_cnt_lo;
temp_c_cnt_hi [13] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [13] <= 1'b1;
end
CNT_14:
begin
temp_c_cnt_lo [14] <= usr_c_cnt_lo;
temp_c_cnt_hi [14] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [14] <= 1'b1;
end
CNT_15:
begin
temp_c_cnt_lo [15] <= usr_c_cnt_lo;
temp_c_cnt_hi [15] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [15] <= 1'b1;
end
CNT_16:
begin
temp_c_cnt_lo [16] <= usr_c_cnt_lo;
temp_c_cnt_hi [16] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [16] <= 1'b1;
end
CNT_17:
begin
temp_c_cnt_lo [17] <= usr_c_cnt_lo;
temp_c_cnt_hi [17] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [17] <= 1'b1;
end
endcase
end
end
end
//logic to handle which writes the user indicated and wants to start.
assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed;
//start the reconfig operations by writing to the DPRIO
reg break_loop;
reg [4:0] i;
always @(*)
begin
dprio_temp_read_1 = 0;
dprio_temp_read_2 = 0;
dprio_temp_m_n_c_readdata_1_d = 0;
dprio_temp_m_n_c_readdata_2_d = 0;
break_loop = 0;
dprio_next_state = DPRIO_IDLE;
avmm_dprio_write = 0;
avmm_dprio_read = 0;
avmm_dprio_address = 0;
avmm_dprio_writedata = 0;
avmm_dprio_byteen = 0;
dprio_write_done = 1;
manual_dprio_done_d = 0;
n_cnt_done_d = 0;
dsm_k_done_d = 0;
dsm_k_ready_false_done_d = 0;
m_cnt_done_d = 0;
c_cnt_done_d[17:0] = 0;
all_c_cnt_done_d = 0;
bwctrl_done_d = 0;
cp_current_done_d = 0;
i = 0;
// Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes)
if (dprio_start | mif_start_assert)
dprio_write_done = 0;
if (current_state == WAIT_ON_LOCK)
begin
case (dprio_cur_state)
ONE:
begin
if (n_cnt_changed & !n_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = N_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = M_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_hilo
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
//To break from the loop, since only one counter
//is addressed at a time
break_loop = 1'b1;
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (cp_current_changed & !cp_current_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_write = usr_r_w;
avmm_dprio_address = usr_dprio_address;
avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
end
else dprio_next_state = DPRIO_IDLE;
end
TWO:
begin
//handle reading the two setting bits on n_cnt, then
//writing them back while preserving other bits.
//Issue two consecutive reads then wait; readLatency=3
dprio_write_done = 0;
dprio_next_state = THREE;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
//reading the K ready 16 bit word. Need to write 0 to it
//afterwards to indicate that K has not been done writing
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
dprio_next_state = FOUR;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
dprio_next_state = FOUR;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
dprio_next_state = FOUR;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
avmm_dprio_read = ~usr_r_w;
avmm_dprio_address = usr_dprio_address;
dprio_next_state = DPRIO_DONE;
end
else dprio_next_state = DPRIO_IDLE;
end
THREE:
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
dprio_next_state = FOUR;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
else dprio_next_state = DPRIO_IDLE;
end
FOUR:
begin
dprio_temp_read_1 = 1'b1;
dprio_write_done = 0;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
dprio_next_state = FIVE;
end
else dprio_next_state = DPRIO_IDLE;
end
FIVE:
begin
dprio_write_done = 0;
dprio_temp_read_2 = 1'b1;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
//this is where DSM ready value comes.
//Need to store in a register to be used later
dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
dprio_next_state = SIX;
end
else dprio_next_state = DPRIO_IDLE;
end
SIX:
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = SEVEN;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_write = 0;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_write = 0;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_write = 0;
end
else dprio_next_state = DPRIO_IDLE;
end
SEVEN:
begin
dprio_write_done = 0;
dprio_next_state = EIGHT;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
n_cnt_done_d = 1'b1;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
m_cnt_done_d = 1'b1;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
dsm_k_ready_false_done_d = 1'b1;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
avmm_dprio_writedata[3:0] = usr_bwctrl_value;
bwctrl_done_d = 1'b1;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
avmm_dprio_writedata[2:0] = usr_cp_current_value;
cp_current_done_d = 1'b1;
end
//if all C_cnt that were changed are done, then assert all_c_cnt_done
if (c_cnt_done_d == c_cnt_changed)
all_c_cnt_done_d = 1'b1;
if (n_cnt_changed & n_cnt_done_d)
dprio_next_state = DPRIO_DONE;
if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
dprio_next_state = ONE;
else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
dprio_next_state = ONE;
else if (dsm_k_changed & !dsm_k_ready_false_done_d)
dprio_next_state = TWO;
else if (dsm_k_changed & !dsm_k_done_q)
dprio_next_state = EIGHT;
else if (bwctrl_changed & !bwctrl_done_d)
dprio_next_state = TWO;
else if (cp_current_changed & !cp_current_done_d)
dprio_next_state = TWO;
else
begin
dprio_next_state = DPRIO_DONE;
dprio_write_done = 1'b1;
end
end
//finish the rest of the DSM reads/writes
//writing k value, writing k_ready to 1.
EIGHT:
begin
dprio_write_done = 0;
dprio_next_state = NINE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
avmm_dprio_writedata[15:0] = usr_k_value[15:0];
end
end
NINE:
begin
dprio_write_done = 0;
dprio_next_state = TEN;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
avmm_dprio_writedata[15:0] = usr_k_value[31:16];
end
end
TEN:
begin
dprio_write_done = 0;
dprio_next_state = ONE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
//already have the readdata for DSM_K_READY_ADDR since we read it
//earlier. Just reuse here
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
dsm_k_done_d = 1'b1;
end
end
DPRIO_DONE:
begin
dprio_write_done = 1'b1;
if (dprio_start) dprio_next_state = DPRIO_IDLE;
else dprio_next_state = DPRIO_DONE;
end
DPRIO_IDLE:
begin
if (dprio_start) dprio_next_state = ONE;
else dprio_next_state = DPRIO_IDLE;
end
default: dprio_next_state = 4'bxxxx;
endcase
end
end
//assert the waitreq signal according to the state of the slave
assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
// Read operations
always @(*)
begin
status = 0;
if (slave_mode == mode_POLL)
//asserting status to 1 if the slave is done.
status = (current_state == LOCKED);
end
//************************************************************//
//************************************************************//
//******************** READ STATE MACHINE ********************//
//************************************************************//
//************************************************************//
reg [1:0] current_read_state;
reg [1:0] next_read_state;
reg [5:0] slave_address_int_d;
reg [5:0] slave_address_int_q;
reg dprio_read_1;
reg [5:0] dprio_address_1;
reg [1:0] dprio_byteen_1;
reg [4:0] usr_cnt_sel_1;
localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10;
always @(posedge clk)
begin
if (reset)
begin
current_read_state <= READ_IDLE;
slave_address_int_q <= 0;
slave_readdata_q <= 0;
end
else
begin
current_read_state <= next_read_state;
slave_address_int_q <= slave_address_int_d;
slave_readdata_q <= slave_readdata_d;
end
end
always @(*)
begin
dprio_read_1 = 0;
dprio_address_1 = 0;
dprio_byteen_1 = 0;
slave_address_int_d = 0;
slave_readdata_d = 0;
status_read = 0;
usr_cnt_sel_1 = 0;
case(current_read_state)
READ_IDLE:
begin
slave_address_int_d = 0;
next_read_state = READ_IDLE;
if ((current_state != WAIT_ON_LOCK) && slave_read)
begin
slave_address_int_d = slave_address;
if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
begin
next_read_state = READ_WAIT;
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
end
else
begin
case (slave_address)
MODE_REG:
begin
next_read_state = READ_WAIT;
slave_readdata_d = slave_mode;
end
STATUS_REG:
begin
next_read_state = READ_WAIT;
status_read = 1'b1;
slave_readdata_d = status;
end
N_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = N_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
M_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = M_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
BWCTRL_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = BWCTRL_ADDR;
next_read_state = READ_WAIT;
end
CP_CURRENT_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = CP_CURRENT_ADDR;
next_read_state = READ_WAIT;
end
default : next_read_state = READ_IDLE;
endcase
end
end
else
next_read_state = READ_IDLE;
end
READ_WAIT:
begin
next_read_state = READ;
slave_address_int_d = slave_address_int_q;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
endcase
end
READ:
begin
next_read_state = READ_IDLE;
slave_address_int_d = slave_address_int_q;
slave_readdata_d = dprio_readdata;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
BWCTRL_REG:
begin
slave_readdata_d = dprio_readdata[3:0];
end
CP_CURRENT_REG:
begin
slave_readdata_d = dprio_readdata[2:0];
end
endcase
end
default: next_read_state = 2'bxx;
endcase
end
dyn_phase_shift dyn_phase_shift_inst (
.clk(clk),
.reset(reset),
.phase_done(phase_done),
.pll_start_valid(pll_start_valid),
.dps_changed(dps_changed),
.dps_changed_valid(dps_changed_valid),
.dprio_write_done(dprio_write_done),
.usr_num_shifts(usr_num_shifts),
.usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
.usr_up_dn(usr_up_dn),
.locked(locked),
.dps_done(dps_done),
.phase_en(phase_en),
.up_dn(up_dn),
.cnt_sel(cnt_sel));
defparam dyn_phase_shift_inst.device_family = device_family;
assign dprio_clk = clk;
self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
dprio_mux dprio_mux_inst (
.init_dprio_address(init_dprio_address),
.init_dprio_read(init_dprio_read),
.init_dprio_byteen(init_dprio_byteen),
.init_dprio_write(init_dprio_write),
.init_dprio_writedata(init_dprio_writedata),
.init_atpgmode(init_atpgmode),
.init_mdio_dis(init_mdio_dis),
.init_scanen(init_scanen),
.init_ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done),
// Inputs from avmm master
.avmm_dprio_address(avmm_dprio_address | dprio_address_1),
.avmm_dprio_read(avmm_dprio_read | dprio_read_1),
.avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
.avmm_dprio_write(avmm_dprio_write),
.avmm_dprio_writedata(avmm_dprio_writedata),
.avmm_atpgmode(avmm_atpgmode),
.avmm_mdio_dis(avmm_mdio_dis),
.avmm_scanen(avmm_scanen),
// Outputs to fpll
.dprio_address(dprio_address),
.dprio_read(dprio_read),
.dprio_byteen(dprio_byteen),
.dprio_write(dprio_write),
.dprio_writedata(dprio_writedata),
.atpgmode(dprio_atpgmode),
.mdio_dis(dprio_mdio_dis),
.scanen(dprio_scanen),
.ser_shift_load(dprio_ser_shift_load)
);
fpll_dprio_init fpll_dprio_init_inst (
.clk(clk),
.reset_n(~reset),
.locked(locked),
//outputs
.dprio_address(init_dprio_address),
.dprio_read(init_dprio_read),
.dprio_byteen(init_dprio_byteen),
.dprio_write(init_dprio_write),
.dprio_writedata(init_dprio_writedata),
.atpgmode(init_atpgmode),
.mdio_dis(init_mdio_dis),
.scanen(init_scanen),
.ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done));
//address luts, to be reconfigged by the Fitter
//FPLL_1 or 0 address lut
generic_lcell_comb lcell_fpll_0_1 (
.dataa(1'b0),
.combout (fpll_1));
defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_fpll_0_1.dont_touch = "on";
defparam lcell_fpll_0_1.family = device_family;
wire dprio_read_combout;
generic_lcell_comb lcell_dprio_read (
.dataa(fpll_1),
.datab(dprio_read),
.datac(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.combout (dprio_read_combout));
defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_dprio_read.dont_touch = "on";
defparam lcell_dprio_read.family = device_family;
//assign reconfig_to_pll signals
assign reconfig_to_pll[0] = dprio_clk;
assign reconfig_to_pll[1] = ~dprio_init_reset;
assign reconfig_to_pll[2] = dprio_write;
assign reconfig_to_pll[3] = dprio_read_combout;
assign reconfig_to_pll[9:4] = dprio_address;
assign reconfig_to_pll[25:10] = dprio_writedata;
assign reconfig_to_pll[27:26] = dprio_byteen;
assign reconfig_to_pll[28] = dprio_ser_shift_load;
assign reconfig_to_pll[29] = dprio_mdio_dis;
assign reconfig_to_pll[30] = phase_en;
assign reconfig_to_pll[31] = up_dn;
assign reconfig_to_pll[36:32] = cnt_sel;
assign reconfig_to_pll[37] = dprio_scanen;
assign reconfig_to_pll[38] = dprio_atpgmode;
//assign reconfig_to_pll[40:37] = clken;
assign reconfig_to_pll[63:39] = 0;
//assign reconfig_from_pll signals
assign dprio_readdata = reconfig_from_pll [15:0];
assign locked = reconfig_from_pll [16];
assign phase_done = reconfig_from_pll [17];
endmodule
module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0]counter;
reg local_reset;
reg usr_mode_init_wait;
initial
begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk)
begin
if (mgmt_reset)
begin
counter <= 0;
end
else
begin
if (!usr_mode_init_wait)
begin
if (counter == INITIAL_WAIT_VALUE)
begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
end
end
else
begin
if (counter == RESET_COUNTER_VALUE)
local_reset <= 0;
else
counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load ;
endmodule
module fpll_dprio_init (
input clk,
input reset_n,
input locked,
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output reg atpgmode,
output reg mdio_dis,
output reg scanen,
output reg ser_shift_load,
output reg dprio_init_done
);
reg [1:0] rst_n = 2'b00;
reg [6:0] count = 7'd0;
reg init_done_forever;
// Internal versions of control signals
wire int_mdio_dis;
wire int_ser_shift_load;
wire int_dprio_init_done;
wire int_atpgmode/*synthesis keep*/;
wire int_scanen/*synthesis keep*/;
assign dprio_address = count[6] ? 5'b0 : count[5:0] ;
assign dprio_byteen = 2'b11; // always enabled
assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles
assign dprio_read = 1'b0;
assign dprio_writedata = 16'd0;
assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1;
assign int_mdio_dis = count[6] ? ~count[2] : 1'b1;
assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0)
: 1'b1;
assign int_atpgmode = 0;
assign int_scanen = 0;
initial begin
count = 7'd0;
init_done_forever = 0;
mdio_dis = 1'b1;
ser_shift_load = 1'b1;
dprio_init_done = 1'b0;
scanen = 1'b0;
atpgmode = 1'b0;
end
// reset synch.
always @(posedge clk or negedge reset_n)
if(!reset_n) rst_n <= 2'b00;
else rst_n <= {rst_n[0],1'b1};
// counter
always @(posedge clk)
begin
if (!rst_n[1])
init_done_forever <= 1'b0;
else
begin
if (count[6] && &count[1:0])
init_done_forever <= 1'b1;
end
end
always @(posedge clk or negedge rst_n[1])
begin
if(!rst_n[1])
begin
count <= 7'd0;
end
else if(~int_dprio_init_done)
begin
count <= count + 7'd1;
end
else
begin
count <= count;
end
end
// outputs
always @(posedge clk) begin
mdio_dis <= int_mdio_dis;
ser_shift_load <= int_ser_shift_load;
dprio_init_done <= int_dprio_init_done;
atpgmode <= int_atpgmode;
scanen <= int_scanen;
end
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
) (
input wire clk,
input wire reset,
input wire phase_done,
input wire pll_start_valid,
input wire dps_changed,
input wire dprio_write_done,
input wire [15:0] usr_num_shifts,
input wire [4:0] usr_cnt_sel,
input wire usr_up_dn,
input wire locked,
//output
output wire dps_done,
output reg phase_en,
output wire up_dn,
output wire dps_changed_valid,
output wire [4:0] cnt_sel);
reg first_phase_shift_d;
reg first_phase_shift_q;
reg [15:0] phase_en_counter;
reg [3:0] dps_current_state;
reg [3:0] dps_next_state;
localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5;
localparam PHASE_EN_WAIT_COUNTER = 5'd1;
reg [15:0] shifts_done_counter;
reg phase_done_final;
wire gnd /*synthesis keep*/;
//fsm
//always block controlling the state regs
always @(posedge clk)
begin
if (reset)
begin
dps_current_state <= DPS_DONE;
end
else
begin
dps_current_state <= dps_next_state;
end
end
//the combinational part. assigning the next state
//this turns on the phase_done_final signal when phase_done does this:
//_____ ______
// |______|
always @(*)
begin
phase_done_final = 0;
first_phase_shift_d = 0;
phase_en = 0;
dps_next_state = DPS_DONE;
case (dps_current_state)
DPS_START:
begin
phase_en = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
DPS_WAIT_PHASE_EN:
begin
phase_en = 1'b1;
if (first_phase_shift_q)
begin
first_phase_shift_d = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
else
begin
if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
dps_next_state = DPS_WAIT_PHASE_DONE;
else dps_next_state = DPS_WAIT_PHASE_EN;
end
end
DPS_WAIT_PHASE_DONE:
begin
if (!phase_done | !locked)
begin
dps_next_state = DPS_WAIT_PHASE_DONE;
end
else
begin
if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
begin
dps_next_state = DPS_START;
phase_done_final = 1'b1;
end
else
begin
dps_next_state = DPS_DONE;
end
end
end
DPS_DONE:
begin
phase_done_final = 0;
if (dps_changed)
dps_next_state = DPS_CHANGED;
else dps_next_state = DPS_DONE;
end
DPS_CHANGED:
begin
if (pll_start_valid)
dps_next_state = DPS_WAIT_DPRIO_WRITING;
else
dps_next_state = DPS_CHANGED;
end
DPS_WAIT_DPRIO_WRITING:
begin
if (dprio_write_done)
dps_next_state = DPS_START;
else
dps_next_state = DPS_WAIT_DPRIO_WRITING;
end
default: dps_next_state = 4'bxxxx;
endcase
end
always @(posedge clk)
begin
if (dps_current_state == DPS_WAIT_PHASE_DONE)
phase_en_counter <= 0;
else if (dps_current_state == DPS_WAIT_PHASE_EN)
phase_en_counter <= phase_en_counter + 1'b1;
if (reset)
begin
phase_en_counter <= 0;
shifts_done_counter <= 1'b1;
first_phase_shift_q <= 1;
end
else
begin
if (first_phase_shift_d)
first_phase_shift_q <= 0;
if (dps_done)
begin
shifts_done_counter <= 1'b1;
end
else
begin
if (phase_done_final & (dps_next_state!= DPS_DONE))
shifts_done_counter <= shifts_done_counter + 1'b1;
else
shifts_done_counter <= shifts_done_counter;
end
end
end
assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
assign up_dn = usr_up_dn;
assign gnd = 1'b0;
//cnt select luts (5)
generic_lcell_comb lcell_cnt_sel_0 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[0]));
defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_cnt_sel_0.dont_touch = "on";
defparam lcell_cnt_sel_0.family = device_family;
generic_lcell_comb lcell_cnt_sel_1 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[1]));
defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_cnt_sel_1.dont_touch = "on";
defparam lcell_cnt_sel_1.family = device_family;
generic_lcell_comb lcell_cnt_sel_2 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[2]));
defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam lcell_cnt_sel_2.dont_touch = "on";
defparam lcell_cnt_sel_2.family = device_family;
generic_lcell_comb lcell_cnt_sel_3 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[3]));
defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
defparam lcell_cnt_sel_3.dont_touch = "on";
defparam lcell_cnt_sel_3.family = device_family;
generic_lcell_comb lcell_cnt_sel_4 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[4]));
defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
defparam lcell_cnt_sel_4.dont_touch = "on";
defparam lcell_cnt_sel_4.family = device_family;
endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V")
begin
stratixv_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V")
begin
arriav_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V GZ")
begin
arriavgz_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Cyclone V")
begin
cyclonev_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
(
clkout,
oscena);
parameter DEVICE_FAMILY = "MAX 10";
parameter DEVICE_ID = "08";
parameter CLOCK_FREQUENCY = "dummy";
output clkout;
input oscena;
wire wire_clkout;
assign clkout = wire_clkout;
// -------------------------------------------------------------------
// Instantiate wysiwyg for chipidblock according to device family
// -------------------------------------------------------------------
generate
if (DEVICE_FAMILY == "MAX 10") begin
fiftyfivenm_oscillator # ( //MAX 10
.device_id(DEVICE_ID),
.clock_frequency(CLOCK_FREQUENCY)
) oscillator_dut (
.clkout(wire_clkout),
.clkout1(),
.oscena(oscena));
end
endgenerate
endmodule //altera_int_osc
//VALID FILE
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// (c) 2001-2010 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// $id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
// $revision: #7 $
// $date: 2010/04/27 $
// $author: jyeap $
// -----------------------------------------------
// reset synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_reset_synchronizer
#(
parameter async_reset = 1,
parameter depth = 2
)
(
input reset_in /* synthesis altera_attribute = "suppress_da_rule_internal=\"r101,r105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// synchronizer register chain. we cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// we omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
// please check the false paths setting in tse sdc
(*preserve*) reg [depth-1:0] altera_tse_reset_synchronizer_chain;
reg altera_tse_reset_synchronizer_chain_out;
generate if (async_reset) begin
// -----------------------------------------------
// assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {depth{1'b1}};
altera_tse_reset_synchronizer_chain_out <= 1'b1;
end
else begin
altera_tse_reset_synchronizer_chain[depth-2:0] <= altera_tse_reset_synchronizer_chain[depth-1:1];
altera_tse_reset_synchronizer_chain[depth-1] <= 0;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end else begin
// -----------------------------------------------
// assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[depth-2:0] <= altera_tse_reset_synchronizer_chain[depth-1:1];
altera_tse_reset_synchronizer_chain[depth-1] <= reset_in;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end
endgenerate
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
else
begin
assign encoder_output = {CFG_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (c) 2001-2018 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
module altera_up_edge_detection_hysteresis (
// inputs
clk,
reset,
data_in,
data_en,
// bidirectionals
// outputs
data_out
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
parameter width = 640; // image width in pixels
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input clk;
input reset;
input [ 7: 0] data_in;
input data_en;
// bidirectionals
// outputs
output [ 7: 0] data_out;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
wire [ 8: 0] shift_reg_out[ 1: 0];
wire data_above_high_threshold;
wire [ 8: 0] data_to_shift_register_1;
wire above_threshold;
wire overflow;
// internal registers
reg [ 8: 0] data_line_2[ 1: 0];
reg [ 2: 0] thresholds[ 2: 0];
reg [ 7: 0] result;
// state machine registers
// integers
integer i;
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
begin
data_line_2[0] <= 8'h00;
data_line_2[1] <= 8'h00;
for (i = 2; i >= 0; i = i-1)
thresholds[i] <= 3'h0;
end
else if (data_en == 1'b1)
begin
// increase edge visibility by 32 and saturate at 255
data_line_2[1] <= data_line_2[0] | {9{data_line_2[0][8]}};
data_line_2[0] <= {1'b0, shift_reg_out[0][7:0]} + 32;
thresholds[0] <= {thresholds[0][1:0], data_above_high_threshold};
thresholds[1] <= {thresholds[1][1:0], shift_reg_out[0][8]};
thresholds[2] <= {thresholds[2][1:0], shift_reg_out[1][8]};
result <= (above_threshold) ? data_line_2[1][7:0] : 8'h00;
end
end
/*****************************************************************************
* combinational logic *
*****************************************************************************/
// external assignments
assign data_out = result;
// internal assignments
assign data_above_high_threshold = (data_in >= 8'h0a) ? 1'b1 : 1'b0;
assign data_to_shift_register_1 = {data_above_high_threshold,data_in};
assign above_threshold =
((|(thresholds[0])) | (|(thresholds[1])) | (|(thresholds[2])));
/*****************************************************************************
* internal modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// inputs
.clock (clk),
.clken (data_en),
.shiftin (data_to_shift_register_1),
// bidirectionals
// outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.dw = 9,
shift_register_1.size = width;
altera_up_edge_detection_data_shift_register shift_register_2 (
// inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// bidirectionals
// outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.dw = 9,
shift_register_2.size = width;
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/02/13 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= 1'b0;
data1 <= 1'b0;
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (c) 2001-2011 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
module altera_eth_mdio #(
parameter mdc_divisor = 32 // mdc frequency is avalon clock / mdc_divisor. must be <2.5mhz
) (
input clk,
input reset,
input csr_read,
input csr_write,
input [5:0] csr_address,
input [31:0] csr_writedata,
output reg [31:0] csr_readdata,
output wire csr_waitrequest,
output reg mdc,
input mdio_in,
output reg mdio_out,
output reg mdio_oen
);
localparam p_mdc_divide_bits = log2ceil(mdc_divisor) - 1; // need to count to (mdc_divisor/2) - 1
//param for case state
localparam s_preamble = 4'b0000; // 0
localparam s_idle = 4'b0001; // 1
localparam s_ctrl_cl22 = 4'b0010; // 2
localparam s_write = 4'b0011; // 3
localparam s_read = 4'b0100; // 4
localparam s_addr_cl45 = 4'b0101; // 5
localparam s_write_addr_cl45 = 4'b0110; // 6
localparam s_ctrl_cl45 = 4'b0111; // 7
localparam s_preamble2 = 4'b1000; // 7
localparam s_preamble3 = 4'b1001; // 7
reg [p_mdc_divide_bits-1:0] mdc_divide;
reg mdc_tick;
reg mdc_sample;
reg [3:0] state;
reg [4:0] count;
reg read_pending;
reg write_pending;
reg [4:0] address;
reg [15:0] data;
reg clause45_reg;
reg [4:0] phy_address_latched;
reg [4:0] prt_address_latched;
reg [4:0] dev_address_latched;
reg [15:0] cl45_reg_address_latched;
// address register and wiring
reg [31:0] dev_prt_phy_address_reg;
wire [4:0] phy_address = dev_prt_phy_address_reg[4:0]; // clause 22 phyad
wire [4:0] dev_address = dev_prt_phy_address_reg[4:0]; // clause 45 devad
wire [4:0] prt_address = dev_prt_phy_address_reg[12:8]; // clasue 45 prtad
wire clause45 = csr_address[5];
wire [15:0] cl45_reg_address = dev_prt_phy_address_reg[31:16]; // clause 45 address
// csr waitrequest
reg avalon_waitrequest_reg;
assign csr_waitrequest = avalon_waitrequest_reg;
// identifies that avalon is accessing the address registers
wire address_reg_acc;
assign address_reg_acc = (csr_address == 6'h21);
always @ (posedge clk or posedge reset) begin
if (reset) begin
mdc <= 1'b0;
mdio_oen <= 1'b1;
mdio_out <= 1'b1;
mdc_divide <= 0;
mdc_tick <= 1'b0;
mdc_sample <= 1'b0;
state <= s_preamble;
count <= 5'h0;
avalon_waitrequest_reg <= 1'b1;
csr_readdata <= 32'h0;
read_pending <= 1'b0;
write_pending <= 1'b0;
address <= 5'b0;
data <= 16'b0;
clause45_reg <= 1'b0;
phy_address_latched <= {5{1'b0}};
prt_address_latched <= {5{1'b0}};
dev_address_latched <= {5{1'b0}};
cl45_reg_address_latched <= {16{1'b0}};
dev_prt_phy_address_reg <= {32{1'b0}};
end
else begin
// divide avalon clock to make mdio clock
if (mdc_divide==0) begin
mdc <= ~mdc;
mdc_divide <= (mdc_divisor/2) - 1'b1;
end
else begin
mdc_divide <= mdc_divide - 1'b1;
end
// data is output on mdc_tick. delay it slightly from the clock to ensure setup and hold timing is met
mdc_tick <= ~mdc & (mdc_divide==(mdc_divisor/2) -1);
// sample read data just before rising edge of mdc
mdc_sample <= ~mdc & (mdc_divide==2);
// from mdio readdata
if (!address_reg_acc) begin
if ((state==s_read) & count>5'd0 & mdc_sample)
csr_readdata <= {16'h0, csr_readdata[14:0], mdio_in};
end
// register space read
else begin
if(csr_write) begin
dev_prt_phy_address_reg <= csr_writedata;
end
if(csr_read) begin
csr_readdata <= dev_prt_phy_address_reg & {16'hffff, 3'b000, 5'b11111, 3'b000, 5'b11111};
end
end
// service avalon read and write requests
avalon_waitrequest_reg <= 1'b1;
if(address_reg_acc && (csr_write || csr_read)) begin
avalon_waitrequest_reg <= 1'b0;
end
else begin
if (state == s_preamble) begin
avalon_waitrequest_reg <= 1'b1;
end
else if (csr_write & avalon_waitrequest_reg & ~write_pending & ~read_pending) begin
write_pending <= 1'b1;
avalon_waitrequest_reg <= 1'b0;
address <= csr_address[4:0];
phy_address_latched <= phy_address;
prt_address_latched <= prt_address;
dev_address_latched <= dev_address;
cl45_reg_address_latched <= cl45_reg_address;
data <= csr_writedata[15:0];
clause45_reg <= clause45;
end
else if (csr_read & avalon_waitrequest_reg & ~write_pending & ~read_pending) begin
read_pending <= 1'b1;
address <= csr_address[4:0];
clause45_reg <= clause45;
phy_address_latched <= phy_address;
prt_address_latched <= prt_address;
dev_address_latched <= dev_address;
cl45_reg_address_latched <= cl45_reg_address;
end
end
// state machine to control access to phy
if (mdc_tick) begin
case (state)
// wait for 32 clocks before first operation in order to establish synchronization
s_preamble : begin
mdio_oen <= 1'b1; // use pullup resistor
mdio_out <= 1'b1;
count <= count + 5'h1;
if (count==5'd31) begin
state <= s_idle;
end
end
// wait for write or read request from avalon
s_idle : begin
count <= 5'd0;
mdio_oen <= 1'b1;
mdio_out <= 1'b1;
if(!address_reg_acc) begin
if (write_pending || read_pending) begin
mdio_out <= 1'b1; // output first bit of start word
mdio_oen <= 1'b0;
state <= s_preamble2;
end
end
end
s_preamble2 : begin
mdio_oen <= 1'b0;
mdio_out <= 1'b1;
count <= count + 5'd1;
if (count==5'd31) begin
count <= 5'd0;
if (write_pending) begin
mdio_out <= 1'b0; // output first bit of start word
mdio_oen <= 1'b0;
if (clause45_reg)
state <= s_addr_cl45;
else
state <= s_ctrl_cl22;
end
else if (read_pending) begin
mdio_out <= 1'b0; // output first bit of start word
mdio_oen <= 1'b0;
if (clause45_reg)
state <= s_addr_cl45;
else
state <= s_ctrl_cl22;
end
end
end
// send control data
s_ctrl_cl22 : begin
//
case (count)
// second bit of start word
0 : mdio_out <= 1'b1;
// opcode. 1 then 0 for read, 0 then 1 for write
1 : mdio_out <= read_pending;
2 : mdio_out <= ~read_pending;
// phy address
3 : mdio_out <= phy_address_latched[4];
4 : mdio_out <= phy_address_latched[3];
5 : mdio_out <= phy_address_latched[2];
6 : mdio_out <= phy_address_latched[1];
7 : mdio_out <= phy_address_latched[0];
// register address
8 : mdio_out <= address[4];
9 : mdio_out <= address[3];
10 : mdio_out <= address[2];
11 : mdio_out <= address[1];
12 : mdio_out <= address[0];
// ta
13 : mdio_out <= 1'b1;
14 : mdio_out <= 1'b0;
endcase
count <= count + 5'd1;
// for read, turn off output for ta cycle
if (count==13 & read_pending)
mdio_oen <= 1'b1;
if (count==5'd14) begin
count <= 5'd0;
if (read_pending)
state <= s_read;
else
state <= s_write;
end
end
s_addr_cl45 : begin
//
case (count)
// second bit of start word
0 : mdio_out <= 1'b0;
// opcode. 1 then 0 for read, 0 then 1 for write
1 : mdio_out <= 1'b0;
2 : mdio_out <= 1'b0;
// phy address
3 : mdio_out <= prt_address_latched[4];
4 : mdio_out <= prt_address_latched[3];
5 : mdio_out <= prt_address_latched[2];
6 : mdio_out <= prt_address_latched[1];
7 : mdio_out <= prt_address_latched[0];
// register address
8 : mdio_out <= dev_address_latched[4];
9 : mdio_out <= dev_address_latched[3];
10 : mdio_out <= dev_address_latched[2];
11 : mdio_out <= dev_address_latched[1];
12 : mdio_out <= dev_address_latched[0];
// ta
13 : mdio_out <= 1'b1;
14 : mdio_out <= 1'b0;
endcase
count <= count + 5'd1;
if (count==5'd14) begin
count <= 5'd16;
state <= s_write_addr_cl45;
end
end
// send write data
s_write_addr_cl45 : begin
mdio_out <= cl45_reg_address_latched[count -5'd1];
count <= count - 5'd1;
if (count==5'd0) begin
count <= 5'd0;
mdio_out <= 1'b1; // output first bit of start word
state <= s_preamble3;
end
end
s_preamble3 : begin
mdio_oen <= 1'b0;
mdio_out <= 1'b1;
count <= count + 5'd1;
if (count==5'd31) begin
mdio_oen <= 1'b0;
count <= 5'd0;
mdio_out <= 1'b0; // output first bit of start word
state <= s_ctrl_cl45;
end
end
s_ctrl_cl45 : begin
//
case (count)
// second bit of start word
0 : mdio_out <= 1'b0;
// opcode. 1 then 0 for read, 0 then 1 for write
1 : mdio_out <= read_pending;
2 : mdio_out <= 1'b1;
// phy address
3 : mdio_out <= prt_address_latched[4];
4 : mdio_out <= prt_address_latched[3];
5 : mdio_out <= prt_address_latched[2];
6 : mdio_out <= prt_address_latched[1];
7 : mdio_out <= prt_address_latched[0];
// register address
8 : mdio_out <= dev_address_latched[4];
9 : mdio_out <= dev_address_latched[3];
10 : mdio_out <= dev_address_latched[2];
11 : mdio_out <= dev_address_latched[1];
12 : mdio_out <= dev_address_latched[0];
// ta
13 : mdio_out <= 1'b1;
14 : mdio_out <= 1'b0;
endcase
count <= count + 5'd1;
// for read, turn off output for ta cycle
if (count==5'd13 & read_pending)
mdio_oen <= 1'b1;
if (count==5'd14) begin
count <= 5'd0;
if (read_pending)
state <= s_read;
else
state <= s_write;
end
end
// send write data
s_write : begin
mdio_out <= data[15];
data <= data << 1;
count <= count + 5'd1;
if (count==5'd15) begin
count <= 5'd30;
state <= s_preamble;
write_pending <= 1'b0;
clause45_reg <= 1'b0;
end
end
// wait for read data
s_read : begin
count <= count + 5'd1;
if (count==5'd16) begin
count <= 5'd30;
state <= s_preamble;
read_pending <= 1'b0;
clause45_reg <= 1'b0;
avalon_waitrequest_reg <= 1'b0;
end
end
endcase
end
end
end
//---------------------------------------------------------------------------------------------------
// function - calculates the log2ceil of the input value
//---------------------------------------------------------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// $id: $
// $revision: $
// $date: $
// $author: $
//-----------------------------------------------------------------------------
// copyright 2012 altera corporation. all rights reserved.
// altera products are protected under numerous u.s. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// this reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable altera reference design
// license agreement (either as signed by you or found at www.altera.com). by
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and altera corporation. in the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// this reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. by making this reference
// design file available, altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by altera.
/////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module gray_cntr_4_sl #(
parameter sld_val = 4'h0,
parameter target_chip = 2,
parameter load_implies_ena = 1'b1
)(
input clk,
input ena,
input sld,
output [3:0] cntr
);
wire [5:0] din = {2'b11,cntr};
wire [3:0] dout_w;
wys_lut w0 (.a(din[5]),.b(din[4]),.c(din[3]),.d(din[2]),.e(din[1]),.f(din[0]),.out(dout_w[0]));
defparam w0 .mask = 64'h0ff0f00f0ff0f00f;
defparam w0 .target_chip = target_chip;
wys_lut w1 (.a(din[5]),.b(din[4]),.c(din[3]),.d(din[2]),.e(din[1]),.f(din[0]),.out(dout_w[1]));
defparam w1 .mask = 64'hf00ff00fffff0000;
defparam w1 .target_chip = target_chip;
wys_lut w2 (.a(din[5]),.b(din[4]),.c(din[3]),.d(din[2]),.e(din[1]),.f(din[0]),.out(dout_w[2]));
defparam w2 .mask = 64'hff00ff000f0fff00;
defparam w2 .target_chip = target_chip;
wys_lut w3 (.a(din[5]),.b(din[4]),.c(din[3]),.d(din[2]),.e(din[1]),.f(din[0]),.out(dout_w[3]));
defparam w3 .mask = 64'hf0f0f0f0f0f0ff00;
defparam w3 .target_chip = target_chip;
wire mod_ena = load_implies_ena ? (sld | ena) : ena;
wire local_gnd_cell = 1'b0 /* synthesis keep */;
genvar i;
generate
for (i=0; i<4; i=i+1) begin : rl
dffeas df (.d(dout_w[i]),
.clk(clk),
.ena(mod_ena),
.sload(sld),
.sclr(1'b0),
.clrn(1'b1),
// synthesis translate_off
.prn(1'b1),
.devclrn(1'b1),
.devpor(1'b1),
// synthesis translate_on
.asdata(sld_val[i] ? 1'b1 : local_gnd_cell),
.aload(1'b0),
.q(cntr[i])
);
defparam df .power_up = "low";
defparam df .is_wysiwyg = "false";
end
endgenerate
endmodule
// benchmark info : 5sgxea7n2f45c2
// benchmark info : max depth : 1.0 luts
// benchmark info : total registers : 4
// benchmark info : total pins : 7
// benchmark info : total virtual pins : 0
// benchmark info : total block memory bits : 0
// benchmark info : comb aluts : ; 7 ; ;
// benchmark info : alms : 4 / 234,720 ( < 1 % )
// benchmark info : worst setup path @ 468.75mhz : 1.547 ns, from rl[3].df, to rl[2].df}
// benchmark info : worst setup path @ 468.75mhz : 1.498 ns, from rl[2].df, to rl[1].df}
// benchmark info : worst setup path @ 468.75mhz : 1.524 ns, from rl[3].df, to rl[2].df}
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
cfg_local_data_width = 80,
cfg_local_addr_width = 32,
cfg_dwidth_ratio = 2,
cfg_mem_if_dq_width = 40,
cfg_mem_if_dqs_width = 5,
cfg_ecc_code_width = 8,
cfg_ecc_multiples = 1,
cfg_ecc_enc_reg = 0,
cfg_ecc_dec_reg = 0,
cfg_ecc_decoder_reg = 0,
cfg_ecc_rdata_reg = 0,
cfg_port_width_interface_width = 8,
cfg_port_width_enable_ecc = 1,
cfg_port_width_gen_sbe = 1,
cfg_port_width_gen_dbe = 1,
cfg_port_width_enable_intr = 1,
cfg_port_width_mask_sbe_intr = 1,
cfg_port_width_mask_dbe_intr = 1,
cfg_port_width_mask_corr_dropped_intr = 1,
cfg_port_width_clr_intr = 1,
sts_port_width_sbe_error = 1,
sts_port_width_dbe_error = 1,
sts_port_width_sbe_count = 8,
sts_port_width_dbe_count = 8,
sts_port_width_corr_drop_error = 1,
sts_port_width_corr_drop_count = 8
)
(
ctl_clk,
ctl_reset_n,
// mmr interface
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// wdata & rdata interface inputs
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// afi interface inputs
afi_rdata,
afi_rdata_valid,
// wdata & rdata interface outputs
ecc_rdata,
ecc_rdata_valid,
// afi inteface outputs
ecc_dm,
ecc_wdata,
// ecc error information
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
// mmr ecc information
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
//--------------------------------------------------------------------------------------------------------
//
// important note:
//
// this block is coded with the following consideration in mind
// - parameter
// - maximum local_data_width will be (40 * dwidth_ratio)
// - maximum ecc_data_width will be (40 * dwidth_ratio)
// - mmr configuration
// - ecc option disabled:
// - maximum dq width is 40
// - maximum local_data width is (40 * dwidth_ratio)
// - wdatap_data and ecc_data size will match (no ecc code)
// - ecc option enabled:
// - maximum dq width is 40
// - maximum local_data width is (32 * dwidth_ratio)
// - wdatap_data width will be (8 * dwidth_ratio) lesser than ecc_data (ecc code)
//
// block level diagram
// -----------------------------------
// write data path (per drate)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// local write data | data | | | | |
// ---- 40 bits ---->| mask |---- 32 bits ---->| encoder |---- 40 bits ---->| ecc mux |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//
// -----------------------------------
// read data path (per drate)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// afi read data | data | | | | |
// ---- 40 bits ---->| mask |---- 40 bits ---->| decoder |---- 32 bits ---->| ecc mux |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//--------------------------------------------------------------------------------------------------------
localparam cfg_mem_if_dq_per_dqs = cfg_mem_if_dq_width / cfg_mem_if_dqs_width;
localparam cfg_ecc_data_width = cfg_mem_if_dq_width * cfg_dwidth_ratio;
localparam cfg_local_dm_width = cfg_local_data_width / cfg_mem_if_dq_per_dqs;
localparam cfg_ecc_dm_width = cfg_ecc_data_width / cfg_mem_if_dq_per_dqs;
localparam cfg_local_data_per_word_width = cfg_local_data_width / cfg_ecc_multiples;
localparam cfg_local_dm_per_word_width = cfg_local_dm_width / cfg_ecc_multiples;
localparam cfg_ecc_data_per_word_width = cfg_ecc_data_width / cfg_ecc_multiples;
localparam cfg_ecc_dm_per_word_width = cfg_ecc_dm_width / cfg_ecc_multiples;
localparam cfg_mmr_dram_data_width = cfg_port_width_interface_width;
localparam cfg_mmr_local_data_width = cfg_port_width_interface_width;
localparam cfg_mmr_dram_dm_width = cfg_port_width_interface_width - 2; // minus 3 because byte enable will be divided by 4/8
localparam cfg_mmr_local_dm_width = cfg_port_width_interface_width - 2; // minus 3 because byte enable will be divided by 4/8
// the following 2 parameters should match!
localparam cfg_encoder_data_width = cfg_ecc_data_per_word_width; // supports only 24, 40 and 72
localparam cfg_decoder_data_width = cfg_ecc_data_per_word_width; // supports only 24, 40 and 72
input ctl_clk;
input ctl_reset_n;
// mmr interface
input [cfg_port_width_interface_width - 1 : 0] cfg_interface_width;
input [cfg_port_width_enable_ecc - 1 : 0] cfg_enable_ecc;
input [cfg_port_width_gen_sbe - 1 : 0] cfg_gen_sbe;
input [cfg_port_width_gen_dbe - 1 : 0] cfg_gen_dbe;
input [cfg_port_width_enable_intr - 1 : 0] cfg_enable_intr;
input [cfg_port_width_mask_sbe_intr - 1 : 0] cfg_mask_sbe_intr;
input [cfg_port_width_mask_dbe_intr - 1 : 0] cfg_mask_dbe_intr;
input [cfg_port_width_mask_corr_dropped_intr - 1 : 0] cfg_mask_corr_dropped_intr;
input [cfg_port_width_clr_intr - 1 : 0] cfg_clr_intr;
// wdata & rdata interface inputs
input [cfg_local_dm_width - 1 : 0] wdatap_dm;
input [cfg_local_data_width - 1 : 0] wdatap_data;
input [cfg_local_data_width - 1 : 0] wdatap_rmw_partial_data;
input [cfg_local_data_width - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] wdatap_ecc_code;
input [cfg_ecc_multiples - 1 : 0] wdatap_ecc_code_overwrite;
input [cfg_local_addr_width - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
// afi interface inputs
input [cfg_ecc_data_width - 1 : 0] afi_rdata;
input [cfg_dwidth_ratio / 2 - 1 : 0] afi_rdata_valid;
// wdata & rdata interface outputs
output [cfg_local_data_width - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
// afi inteface outputs
output [cfg_ecc_dm_width - 1 : 0] ecc_dm;
output [cfg_ecc_data_width - 1 : 0] ecc_wdata;
// ecc error information
output [cfg_ecc_multiples - 1 : 0] ecc_sbe;
output [cfg_ecc_multiples - 1 : 0] ecc_dbe;
output [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] ecc_code;
output ecc_interrupt;
// mmr ecc information
output [sts_port_width_sbe_error - 1 : 0] sts_sbe_error;
output [sts_port_width_dbe_error - 1 : 0] sts_dbe_error;
output [sts_port_width_sbe_count - 1 : 0] sts_sbe_count;
output [sts_port_width_dbe_count - 1 : 0] sts_dbe_count;
output [cfg_local_addr_width - 1 : 0] sts_err_addr;
output [sts_port_width_corr_drop_error - 1 : 0] sts_corr_dropped;
output [sts_port_width_corr_drop_count - 1 : 0] sts_corr_dropped_count;
output [cfg_local_addr_width - 1 : 0] sts_corr_dropped_addr;
//--------------------------------------------------------------------------------------------------------
//
// [start] register & wires
//
//--------------------------------------------------------------------------------------------------------
// output registers
reg [cfg_local_data_width - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [cfg_ecc_dm_width - 1 : 0] ecc_dm;
reg [cfg_ecc_data_width - 1 : 0] ecc_wdata;
reg [cfg_ecc_multiples - 1 : 0] ecc_sbe;
reg [cfg_ecc_multiples - 1 : 0] ecc_dbe;
reg [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [sts_port_width_sbe_error - 1 : 0] sts_sbe_error;
reg [sts_port_width_dbe_error - 1 : 0] sts_dbe_error;
reg [sts_port_width_sbe_count - 1 : 0] sts_sbe_count;
reg [sts_port_width_dbe_count - 1 : 0] sts_dbe_count;
reg [cfg_local_addr_width - 1 : 0] sts_err_addr;
reg [sts_port_width_corr_drop_error - 1 : 0] sts_corr_dropped;
reg [sts_port_width_corr_drop_count - 1 : 0] sts_corr_dropped_count;
reg [cfg_local_addr_width - 1 : 0] sts_corr_dropped_addr;
// common
reg [cfg_mmr_dram_data_width - 1 : 0] cfg_dram_data_width;
reg [cfg_mmr_local_data_width - 1 : 0] cfg_local_data_width;
reg [cfg_mmr_dram_dm_width - 1 : 0] cfg_dram_dm_width;
reg [cfg_mmr_local_dm_width - 1 : 0] cfg_local_dm_width;
// input logic
reg [cfg_local_data_width - 1 : 0] int_encoder_input_data;
reg [cfg_local_data_width - 1 : 0] int_encoder_input_rmw_partial_data;
reg [cfg_local_data_width - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [cfg_ecc_data_width - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
// output logic
reg [cfg_ecc_multiples - 1 : 0] int_sbe;
reg [cfg_ecc_multiples - 1 : 0] int_dbe;
reg [cfg_ecc_dm_width - 1 : 0] int_encoder_output_dm;
reg [cfg_ecc_dm_width - 1 : 0] int_encoder_output_dm_r;
wire [cfg_ecc_multiples - 1 : 0] int_decoder_output_data_valid;
reg [cfg_ecc_data_width - 1 : 0] int_encoder_output_data;
reg [cfg_ecc_data_width - 1 : 0] int_encoder_output_data_r;
wire [cfg_local_data_width - 1 : 0] int_decoder_output_data;
wire [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] int_ecc_code;
// ecc specific logic
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [sts_port_width_sbe_error - 1 : 0] int_sbe_error;
reg [sts_port_width_dbe_error - 1 : 0] int_dbe_error;
reg [sts_port_width_sbe_count - 1 : 0] int_sbe_count;
reg [sts_port_width_dbe_count - 1 : 0] int_dbe_count;
reg [cfg_local_addr_width - 1 : 0] int_err_addr ;
reg [sts_port_width_corr_drop_error - 1 : 0] int_corr_dropped;
reg [sts_port_width_corr_drop_count - 1 : 0] int_corr_dropped_count;
reg [cfg_local_addr_width - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
//--------------------------------------------------------------------------------------------------------
//
// [end] register & wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [start] common
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// dram and local data width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
// important note, if we set memory interface width (dq width) to 8 and enable_ecc to 1,
// this will result in local data width of 0, this case is not supported
// this must be checked with assertion so that this case will not happen in regression
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - cfg_ecc_code_width;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
//----------------------------------------------------------------------------------------------------
// dram and local be width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / cfg_mem_if_dq_per_dqs;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / cfg_mem_if_dq_per_dqs;
end
end
// registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [enc] common
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [start] input logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// write data & byte enable from wdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (cfg_ecc_enc_reg)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < cfg_ecc_multiples;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [cfg_local_dm_per_word_width-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * cfg_local_dm_per_word_width - 1 : i_drate * cfg_local_dm_per_word_width];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
reg [cfg_local_dm_per_word_width + cfg_ecc_dm_per_word_width - 1 : 0] int_encoder_input_dm_tmp;
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_input_dm_tmp = { {cfg_ecc_dm_per_word_width{1'b0}}, int_encoder_input_dm };
end
else
begin
int_encoder_input_dm_tmp = { {cfg_ecc_dm_per_word_width{1'b1}}, int_encoder_input_dm };
end
end
else
begin
int_encoder_input_dm_tmp = { {cfg_ecc_dm_per_word_width{1'b0}}, int_encoder_input_dm };
end
int_encoder_output_dm [ ((i_drate + 1) * cfg_ecc_dm_per_word_width) - 1 : (i_drate * cfg_ecc_dm_per_word_width)] = int_encoder_input_dm_tmp[cfg_ecc_dm_per_word_width-1:0];
end // always @ begin
end
endgenerate
//----------------------------------------------------------------------------------------------------
// read data & read data valid from afi
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
//--------------------------------------------------------------------------------------------------------
//
// [end] input logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [start] output logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// write data & byte enable to afi interface
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (cfg_ecc_enc_reg)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
//----------------------------------------------------------------------------------------------------
// read data to rdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
//----------------------------------------------------------------------------------------------------
// ecc specific logic
//----------------------------------------------------------------------------------------------------
// single bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
// double bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
// ecc code
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
// interrupt signal
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
//----------------------------------------------------------------------------------------------------
// mmr ecc specific logic
//----------------------------------------------------------------------------------------------------
// single bit error
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
// double bit error
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
// single bit error count
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
// double bit error count
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
// error address
always @ (*)
begin
sts_err_addr = int_err_addr;
end
// correctable error dropped
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
// single bit error count
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
// correctable error dropped address
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
//--------------------------------------------------------------------------------------------------------
//
// [end] output logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [start] encoder / decoder instantiation
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// encoder
//----------------------------------------------------------------------------------------------------
generate
genvar m_drate;
for (m_drate = 0;m_drate < cfg_ecc_multiples;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [cfg_encoder_data_width + cfg_local_data_per_word_width - 1 : 0] input_data_tmp = {{cfg_encoder_data_width{1'b0}}, int_encoder_input_data [(m_drate + 1) * cfg_local_data_per_word_width - 1 : m_drate * cfg_local_data_per_word_width]};
wire [cfg_encoder_data_width - 1 : 0] input_data = input_data_tmp[cfg_encoder_data_width - 1 : 0];
wire [cfg_encoder_data_width + cfg_local_data_per_word_width - 1 : 0] input_rmw_partial_data_tmp = {{cfg_encoder_data_width{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * cfg_local_data_per_word_width - 1 : m_drate * cfg_local_data_per_word_width]};
wire [cfg_encoder_data_width - 1 : 0] input_rmw_partial_data = input_rmw_partial_data_tmp[ cfg_encoder_data_width - 1 : 0 ];
wire [cfg_encoder_data_width + cfg_local_data_per_word_width - 1 : 0] input_rmw_correct_data_tmp = {{cfg_encoder_data_width{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * cfg_local_data_per_word_width - 1 : m_drate * cfg_local_data_per_word_width]};
wire [cfg_encoder_data_width - 1 : 0] input_rmw_correct_data = input_rmw_correct_data_tmp[ cfg_encoder_data_width - 1 : 0 ];
wire [cfg_ecc_code_width - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * cfg_ecc_code_width - 1 : m_drate * cfg_ecc_code_width];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [cfg_encoder_data_width - 1 : 0] output_data;
wire [cfg_encoder_data_width - 1 : 0] output_rmw_partial_data;
wire [cfg_encoder_data_width - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * cfg_ecc_data_per_word_width - 1 : m_drate * cfg_ecc_data_per_word_width] = {output_rmw_partial_data [cfg_ecc_data_per_word_width - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * cfg_ecc_data_per_word_width - 1 : m_drate * cfg_ecc_data_per_word_width] = {output_rmw_correct_data [cfg_ecc_data_per_word_width - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * cfg_ecc_data_per_word_width - 1 : m_drate * cfg_ecc_data_per_word_width] = {output_data [cfg_ecc_data_per_word_width - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.cfg_data_width (cfg_encoder_data_width ),
.cfg_ecc_code_width (cfg_ecc_code_width ),
.cfg_ecc_enc_reg (cfg_ecc_enc_reg ),
.cfg_mmr_dram_data_width (cfg_mmr_dram_data_width ),
.cfg_mmr_local_data_width (cfg_mmr_local_data_width ),
.cfg_port_width_enable_ecc (cfg_port_width_enable_ecc )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ecc code overwrite feature is only needed during rmw correct phase
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.cfg_data_width (cfg_encoder_data_width ),
.cfg_ecc_code_width (cfg_ecc_code_width ),
.cfg_ecc_enc_reg (cfg_ecc_enc_reg ),
.cfg_mmr_dram_data_width (cfg_mmr_dram_data_width ),
.cfg_mmr_local_data_width (cfg_mmr_local_data_width ),
.cfg_port_width_enable_ecc (cfg_port_width_enable_ecc )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ecc code overwrite feature is only needed during rmw correct phase
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.cfg_data_width (cfg_encoder_data_width ),
.cfg_ecc_code_width (cfg_ecc_code_width ),
.cfg_ecc_enc_reg (cfg_ecc_enc_reg ),
.cfg_mmr_dram_data_width (cfg_mmr_dram_data_width ),
.cfg_mmr_local_data_width (cfg_mmr_local_data_width ),
.cfg_port_width_enable_ecc (cfg_port_width_enable_ecc )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
//----------------------------------------------------------------------------------------------------
// decoder
//----------------------------------------------------------------------------------------------------
generate
genvar n_drate;
for (n_drate = 0;n_drate < cfg_ecc_multiples;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire err_sbe;
wire [cfg_decoder_data_width + cfg_ecc_data_per_word_width - 1 : 0] input_data_tmp = {{cfg_ecc_data_per_word_width{1'b0}}, int_decoder_input_data [(n_drate + 1) * cfg_ecc_data_per_word_width - 1 : n_drate * cfg_ecc_data_per_word_width]};
wire [cfg_decoder_data_width - 1 : 0] input_data = input_data_tmp[ cfg_decoder_data_width - 1 : 0 ];
wire input_data_valid = int_decoder_input_data_valid;
wire [cfg_decoder_data_width - 1 : 0] output_data;
wire output_data_valid;
wire [cfg_ecc_code_width - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * cfg_local_data_per_word_width - 1 : n_drate * cfg_local_data_per_word_width] = output_data [cfg_local_data_per_word_width - 1 : 0];
assign int_ecc_code [(n_drate + 1) * cfg_ecc_code_width - 1 : n_drate * cfg_ecc_code_width ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.cfg_data_width (cfg_decoder_data_width ),
.cfg_ecc_code_width (cfg_ecc_code_width ),
.cfg_ecc_dec_reg (cfg_ecc_dec_reg ),
.cfg_ecc_decoder_reg (cfg_ecc_decoder_reg ),
.cfg_ecc_rdata_reg (cfg_ecc_rdata_reg ),
.cfg_mmr_dram_data_width (cfg_mmr_dram_data_width ),
.cfg_mmr_local_data_width (cfg_mmr_local_data_width ),
.cfg_port_width_enable_ecc (cfg_port_width_enable_ecc )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal ),
.err_sbe (err_sbe )
);
// error detection
/*
always @ (*)
begin
if (err_detected || err_sbe)
begin
if (err_corrected || err_sbe)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
*/
always @ (*)
begin
int_sbe [n_drate] = err_corrected | err_sbe;
int_dbe [n_drate] = err_fatal;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [end] encoder / decoder instantiation
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [start] ecc specific logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// common logic
//----------------------------------------------------------------------------------------------------
// below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
// - int_sbe_detected
// - int_dbe_detected
// - int_be_detected
// - int_corr_dropped_detected
// - rdatap_rcvd_addr
//
// see spr:362993
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
//----------------------------------------------------------------------------------------------------
// error innjection logic
//----------------------------------------------------------------------------------------------------
// data error injection, this will cause output data to be injected with single/double bit error
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
// put dbe 1st so that when user sets both gen_sbe and gen_dbe, dbe will have higher priority
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
//----------------------------------------------------------------------------------------------------
// single bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// single bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {sts_port_width_sbe_count{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// double bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// double bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {sts_port_width_dbe_count{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {cfg_local_addr_width{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// dropped correctable error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// dropped correctable error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {sts_port_width_corr_drop_count{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// dropped correctable error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {cfg_local_addr_width{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// interrupt logic
//----------------------------------------------------------------------------------------------------
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [end] ecc specific logic
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module alt_mem_ddrx_buffer_manager
# (
parameter
cfg_buffer_addr_width = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam ctl_buffer_depth = two_pow_n(cfg_buffer_addr_width);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [cfg_buffer_addr_width-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [cfg_buffer_addr_width-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [cfg_buffer_addr_width-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [cfg_buffer_addr_width-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [cfg_buffer_addr_width-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [cfg_buffer_addr_width-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [cfg_buffer_addr_width-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [cfg_buffer_addr_width-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [ctl_buffer_depth-1:0] mux_writeif_ready;
reg [ctl_buffer_depth-1:0] buffer_valid_array;
reg [cfg_buffer_addr_width-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < ctl_buffer_depth; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [cfg_buffer_addr_width-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_n;
input integer value;
begin
two_pow_n = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
// this program was cloned from: https://github.com/fast-switch/fast
// license: apache license 2.0
//legal notice: (c)2010 altera corporation. all rights reserved. your
//use of altera corporation's design tools, logic functions and other
//software and tools, and its ampp partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the altera program
//license subscription agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by altera and sold by altera
//or its authorized distributors. please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// title :
//
// file : alt_ddrx_timing_param.v
//
// abstract :
///////////////////////////////////////////////////////////////////////////////
module alt_ddrx_timing_param #
( parameter
mem_if_rd_to_wr_turnaround_oct = 0,
mem_if_wr_to_rd_turnaround_oct = 0,
mem_if_wr_to_rd_diff_chips_turnaround_oct = 0,
mem_type = "ddr3",
dwidth_ratio = 2, // 2 - fullrate, 4 - halfrate
memory_burstlength = 8,
// timing parameters width
cas_wr_lat_bus_width = 4, // max will be 8 in ddr3
add_lat_bus_width = 3, // max will be 6 in ddr2
tcl_bus_width = 4, // max will be 11 in ddr3
trrd_bus_width = 4, // 2 - 8
tfaw_bus_width = 6, // 6 - 32
trfc_bus_width = 8, // 12 - 140?
trefi_bus_width = 13, // 780 - 6240
trcd_bus_width = 4, // 2 - 11
trp_bus_width = 4, // 2 - 11
twr_bus_width = 4, // 2 - 12
twtr_bus_width = 4, // 1 - 10
trtp_bus_width = 4, // 2 - 8
tras_bus_width = 5, // 4 - 29
trc_bus_width = 6, // 8 - 40
auto_pd_bus_width = 16, // same as csr
burst_length_bus_width = 4,
self_rfsh_exit_cycles_bus_width = 10,
act_to_rdwr_width = 4,
act_to_pch_width = 5,
act_to_act_width = 6,
rd_to_rd_width = 3,
rd_to_wr_width = 5,
rd_to_wr_bc_width = 4,
rd_to_pch_width = 4,
wr_to_wr_width = 3,
wr_to_rd_width = 5,
wr_to_pch_width = 5,
rd_ap_to_act_width = 5,
wr_ap_to_act_width = 6,
pch_to_act_width = 4,
pch_all_to_valid_width = 4,
arf_to_valid_width = 8,
pdn_to_valid_width = 2,
srf_to_valid_width = 10,
arf_period_width = 13,
pdn_period_width = 16,
act_to_act_diff_bank_width = 4,
four_act_to_act_width = 6
)
(
ctl_clk,
ctl_reset_n,
// timing parameters
mem_cas_wr_lat,
mem_add_lat,
mem_tcl,
mem_trrd,
mem_tfaw,
mem_trfc,
mem_trefi,
mem_trcd,
mem_trp,
mem_twr,
mem_twtr,
mem_trtp,
mem_tras,
mem_trc,
mem_auto_pd_cycles,
// timing value outputs
mem_burst_length,
mem_self_rfsh_exit_cycles,
mem_rd_to_wr_turnaround_oct,
mem_wr_to_rd_turnaround_oct,
act_to_rdwr,
act_to_pch,
act_to_act,
rd_to_rd,
rd_to_wr,
rd_to_wr_bc,
rd_to_pch,
wr_to_wr,
wr_to_rd,
wr_to_rd_diff_chips,
wr_to_pch,
rd_ap_to_act,
wr_ap_to_act,
pch_to_act,
pch_all_to_valid,
arf_to_valid,
pdn_to_valid,
srf_to_valid,
srf_to_zq,
arf_period,
pdn_period,
act_to_act_diff_bank,
four_act_to_act,
// timing value comparison outputs
more_than_2_act_to_rdwr,
more_than_2_act_to_pch,
more_than_2_act_to_act,
more_than_2_rd_to_rd,
more_than_2_rd_to_wr,
more_than_2_rd_to_wr_bc,
more_than_2_rd_to_pch,
more_than_2_wr_to_wr,
more_than_2_wr_to_rd,
more_than_2_wr_to_pch,
more_than_2_rd_ap_to_act,
more_than_2_wr_ap_to_act,
more_than_2_pch_to_act,
more_than_2_act_to_act_diff_bank,
more_than_2_four_act_to_act,
less_than_2_act_to_rdwr,
less_than_2_act_to_pch,
less_than_2_act_to_act,
less_than_2_rd_to_rd,
less_than_2_rd_to_wr,
less_than_2_rd_to_wr_bc,
less_than_2_rd_to_pch,
less_than_2_wr_to_wr,
less_than_2_wr_to_rd,
less_than_2_wr_to_rd_diff_chips,
less_than_2_wr_to_pch,
less_than_2_rd_ap_to_act,
less_than_2_wr_ap_to_act,
less_than_2_pch_to_act,
less_than_2_act_to_act_diff_bank,
less_than_2_four_act_to_act,
more_than_3_act_to_rdwr,
more_than_3_act_to_pch,
more_than_3_act_to_act,
more_than_3_rd_to_rd,
more_than_3_rd_to_wr,
more_than_3_rd_to_wr_bc,
more_than_3_rd_to_pch,
more_than_3_wr_to_wr,
more_than_3_wr_to_rd,
more_than_3_wr_to_pch,
more_than_3_rd_ap_to_act,
more_than_3_wr_ap_to_act,
more_than_3_pch_to_act,
more_than_3_act_to_act_diff_bank,
more_than_3_four_act_to_act,
less_than_3_act_to_rdwr,
less_than_3_act_to_pch,
less_than_3_act_to_act,
less_than_3_rd_to_rd,
less_than_3_rd_to_wr,
less_than_3_rd_to_wr_bc,
less_than_3_rd_to_pch,
less_than_3_wr_to_wr,
less_than_3_wr_to_rd,
less_than_3_wr_to_rd_diff_chips,
less_than_3_wr_to_pch,
less_than_3_rd_ap_to_act,
less_than_3_wr_ap_to_act,
less_than_3_pch_to_act,
less_than_3_act_to_act_diff_bank,
less_than_3_four_act_to_act,
more_than_4_act_to_rdwr,
more_than_4_act_to_pch,
more_than_4_act_to_act,
more_than_4_rd_to_rd,
more_than_4_rd_to_wr,
more_than_4_rd_to_wr_bc,
more_than_4_rd_to_pch,
more_than_4_wr_to_wr,
more_than_4_wr_to_rd,
more_than_4_wr_to_pch,
more_than_4_rd_ap_to_act,
more_than_4_wr_ap_to_act,
more_than_4_pch_to_act,
more_than_4_act_to_act_diff_bank,
more_than_4_four_act_to_act,
less_than_4_act_to_rdwr,
less_than_4_act_to_pch,
less_than_4_act_to_act,
less_than_4_rd_to_rd,
less_than_4_rd_to_wr,
less_than_4_rd_to_wr_bc,
less_than_4_rd_to_pch,
less_than_4_wr_to_wr,
less_than_4_wr_to_rd,
less_than_4_wr_to_rd_diff_chips,
less_than_4_wr_to_pch,
less_than_4_rd_ap_to_act,
less_than_4_wr_ap_to_act,
less_than_4_pch_to_act,
less_than_4_act_to_act_diff_bank,
less_than_4_four_act_to_act,
more_than_5_act_to_rdwr,
more_than_5_act_to_pch,
more_than_5_act_to_act,
more_than_5_rd_to_rd,
more_than_5_rd_to_wr,
more_than_5_rd_to_wr_bc,
more_than_5_rd_to_pch,
more_than_5_wr_to_wr,
more_than_5_wr_to_rd,
more_than_5_wr_to_pch,
more_than_5_rd_ap_to_act,
more_than_5_wr_ap_to_act,
more_than_5_pch_to_act,
more_than_5_act_to_act_diff_bank,
more_than_5_four_act_to_act,
less_than_5_act_to_rdwr,
less_than_5_act_to_pch,
less_than_5_act_to_act,
less_than_5_rd_to_rd,
less_than_5_rd_to_wr,
less_than_5_rd_to_wr_bc,
less_than_5_rd_to_pch,
less_than_5_wr_to_wr,
less_than_5_wr_to_rd,
less_than_5_wr_to_rd_diff_chips,
less_than_5_wr_to_pch,
less_than_5_rd_ap_to_act,
less_than_5_wr_ap_to_act,
less_than_5_pch_to_act,
less_than_5_act_to_act_diff_bank,
less_than_5_four_act_to_act,
add_lat_on
);
input ctl_clk;
input ctl_reset_n;
// timing parameters
input [cas_wr_lat_bus_width - 1 : 0] mem_cas_wr_lat;
input [add_lat_bus_width - 1 : 0] mem_add_lat;
input [tcl_bus_width - 1 : 0] mem_tcl;
input [trrd_bus_width - 1 : 0] mem_trrd;
input [tfaw_bus_width - 1 : 0] mem_tfaw;
input [trfc_bus_width - 1 : 0] mem_trfc;
input [trefi_bus_width - 1 : 0] mem_trefi;
input [trcd_bus_width - 1 : 0] mem_trcd;
input [trp_bus_width - 1 : 0] mem_trp;
input [twr_bus_width - 1 : 0] mem_twr;
input [twtr_bus_width - 1 : 0] mem_twtr;
input [trtp_bus_width - 1 : 0] mem_trtp;
input [tras_bus_width - 1 : 0] mem_tras;
input [trc_bus_width - 1 : 0] mem_trc;
input [auto_pd_bus_width - 1 : 0] mem_auto_pd_cycles;
// timing value outputs
output [burst_length_bus_width - 1 : 0] mem_burst_length;
output [self_rfsh_exit_cycles_bus_width - 1 : 0] mem_self_rfsh_exit_cycles;
output [rd_to_wr_width - 1 : 0] mem_rd_to_wr_turnaround_oct;
output [wr_to_rd_width - 1 : 0] mem_wr_to_rd_turnaround_oct;
output [act_to_rdwr_width - 1 : 0] act_to_rdwr;
output [act_to_pch_width - 1 : 0] act_to_pch;
output [act_to_act_width - 1 : 0] act_to_act;
output [rd_to_rd_width - 1 : 0] rd_to_rd;
output [rd_to_wr_width - 1 : 0] rd_to_wr;
output [rd_to_wr_bc_width - 1 : 0] rd_to_wr_bc;
output [rd_to_pch_width - 1 : 0] rd_to_pch;
output [wr_to_wr_width - 1 : 0] wr_to_wr;
output [wr_to_rd_width - 1 : 0] wr_to_rd;
output [wr_to_rd_width - 1 : 0] wr_to_rd_diff_chips;
output [wr_to_pch_width - 1 : 0] wr_to_pch;
output [rd_ap_to_act_width - 1 : 0] rd_ap_to_act;
output [wr_ap_to_act_width - 1 : 0] wr_ap_to_act;
output [pch_to_act_width - 1 : 0] pch_to_act;
output [pch_all_to_valid_width - 1 : 0] pch_all_to_valid;
output [arf_to_valid_width - 1 : 0] arf_to_valid;
output [pdn_to_valid_width - 1 : 0] pdn_to_valid;
output [srf_to_valid_width - 1 : 0] srf_to_valid;
output [srf_to_valid_width - 1 : 0] srf_to_zq;
output [arf_period_width - 1 : 0] arf_period;
output [pdn_period_width - 1 : 0] pdn_period;
output [act_to_act_diff_bank_width - 1 : 0] act_to_act_diff_bank;
output [four_act_to_act_width - 1 : 0] four_act_to_act;
// timing value comparison outputs
output more_than_2_act_to_rdwr;
output more_than_2_act_to_pch;
output more_than_2_act_to_act;
output more_than_2_rd_to_rd;
output more_than_2_rd_to_wr;
output more_than_2_rd_to_wr_bc;
output more_than_2_rd_to_pch;
output more_than_2_wr_to_wr;
output more_than_2_wr_to_rd;
output more_than_2_wr_to_pch;
output more_than_2_rd_ap_to_act;
output more_than_2_wr_ap_to_act;
output more_than_2_pch_to_act;
output more_than_2_act_to_act_diff_bank;
output more_than_2_four_act_to_act;
output less_than_2_act_to_rdwr;
output less_than_2_act_to_pch;
output less_than_2_act_to_act;
output less_than_2_rd_to_rd;
output less_than_2_rd_to_wr;
output less_than_2_rd_to_wr_bc;
output less_than_2_rd_to_pch;
output less_than_2_wr_to_wr;
output less_than_2_wr_to_rd;
output less_than_2_wr_to_rd_diff_chips;
output less_than_2_wr_to_pch;
output less_than_2_rd_ap_to_act;
output less_than_2_wr_ap_to_act;
output less_than_2_pch_to_act;
output less_than_2_act_to_act_diff_bank;
output less_than_2_four_act_to_act;
output more_than_3_act_to_rdwr;
output more_than_3_act_to_pch;
output more_than_3_act_to_act;
output more_than_3_rd_to_rd;
output more_than_3_rd_to_wr;
output more_than_3_rd_to_wr_bc;
output more_than_3_rd_to_pch;
output more_than_3_wr_to_wr;
output more_than_3_wr_to_rd;
output more_than_3_wr_to_pch;
output more_than_3_rd_ap_to_act;
output more_than_3_wr_ap_to_act;
output more_than_3_pch_to_act;
output more_than_3_act_to_act_diff_bank;
output more_than_3_four_act_to_act;
output less_than_3_act_to_rdwr;
output less_than_3_act_to_pch;
output less_than_3_act_to_act;
output less_than_3_rd_to_rd;
output less_than_3_rd_to_wr;
output less_than_3_rd_to_wr_bc;
output less_than_3_rd_to_pch;
output less_than_3_wr_to_wr;
output less_than_3_wr_to_rd;
output less_than_3_wr_to_rd_diff_chips;
output less_than_3_wr_to_pch;
output less_than_3_rd_ap_to_act;
output less_than_3_wr_ap_to_act;
output less_than_3_pch_to_act;
output less_than_3_act_to_act_diff_bank;
output less_than_3_four_act_to_act;
output more_than_4_act_to_rdwr;
output more_than_4_act_to_pch;
output more_than_4_act_to_act;
output more_than_4_rd_to_rd;
output more_than_4_rd_to_wr;
output more_than_4_rd_to_wr_bc;
output more_than_4_rd_to_pch;
output more_than_4_wr_to_wr;
output more_than_4_wr_to_rd;
output more_than_4_wr_to_pch;
output more_than_4_rd_ap_to_act;
output more_than_4_wr_ap_to_act;
output more_than_4_pch_to_act;
output more_than_4_act_to_act_diff_bank;
output more_than_4_four_act_to_act;
output less_than_4_act_to_rdwr;
output less_than_4_act_to_pch;
output less_than_4_act_to_act;
output less_than_4_rd_to_rd;
output less_than_4_rd_to_wr;
output less_than_4_rd_to_wr_bc;
output less_than_4_rd_to_pch;
output less_than_4_wr_to_wr;
output less_than_4_wr_to_rd;
output less_than_4_wr_to_rd_diff_chips;
output less_than_4_wr_to_pch;
output less_than_4_rd_ap_to_act;
output less_than_4_wr_ap_to_act;
output less_than_4_pch_to_act;
output less_than_4_act_to_act_diff_bank;
output less_than_4_four_act_to_act;
output more_than_5_act_to_rdwr;
output more_than_5_act_to_pch;
output more_than_5_act_to_act;
output more_than_5_rd_to_rd;
output more_than_5_rd_to_wr;
output more_than_5_rd_to_wr_bc;
output more_than_5_rd_to_pch;
output more_than_5_wr_to_wr;
output more_than_5_wr_to_rd;
output more_than_5_wr_to_pch;
output more_than_5_rd_ap_to_act;
output more_than_5_wr_ap_to_act;
output more_than_5_pch_to_act;
output more_than_5_act_to_act_diff_bank;
output more_than_5_four_act_to_act;
output less_than_5_act_to_rdwr;
output less_than_5_act_to_pch;
output less_than_5_act_to_act;
output less_than_5_rd_to_rd;
output less_than_5_rd_to_wr;
output less_than_5_rd_to_wr_bc;
output less_than_5_rd_to_pch;
output less_than_5_wr_to_wr;
output less_than_5_wr_to_rd;
output less_than_5_wr_to_rd_diff_chips;
output less_than_5_wr_to_pch;
output less_than_5_rd_ap_to_act;
output less_than_5_wr_ap_to_act;
output less_than_5_pch_to_act;
output less_than_5_act_to_act_diff_bank;
output less_than_5_four_act_to_act;
output add_lat_on;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[start] timing parameters
------------------------------------------------------------------------------*/
wire [burst_length_bus_width - 1 : 0] mem_burst_length = memory_burstlength;
wire [self_rfsh_exit_cycles_bus_width - 1 : 0] mem_self_rfsh_exit_cycles = (mem_type == "ddr3") ? 520 : 210; // added extra cycles
wire [rd_to_wr_width - 1 : 0] mem_rd_to_wr_turnaround_oct = mem_if_rd_to_wr_turnaround_oct;
wire [wr_to_rd_width - 1 : 0] mem_wr_to_rd_turnaround_oct = mem_if_wr_to_rd_turnaround_oct;
wire [wr_to_rd_width - 1 : 0] mem_wr_to_rd_diff_chips_turnaround_oct = mem_if_wr_to_rd_diff_chips_turnaround_oct;
// activate
reg [act_to_rdwr_width - 1 : 0] act_to_rdwr;
reg [act_to_pch_width - 1 : 0] act_to_pch;
reg [act_to_act_width - 1 : 0] act_to_act;
// read
reg [rd_to_rd_width - 1 : 0] rd_to_rd;
reg [rd_to_wr_width - 1 : 0] rd_to_wr;
reg [rd_to_wr_bc_width - 1 : 0] rd_to_wr_bc; // burst chop support, only affects ddr3 rd - wr
reg [rd_to_pch_width - 1 : 0] rd_to_pch;
// write
reg [wr_to_wr_width - 1 : 0] wr_to_wr;
reg [wr_to_rd_width - 1 : 0] wr_to_rd;
reg [wr_to_rd_width - 1 : 0] wr_to_rd_diff_chips;
reg [wr_to_pch_width - 1 : 0] wr_to_pch;
// auto precharge
reg [rd_ap_to_act_width - 1 : 0] rd_ap_to_act;
reg [wr_ap_to_act_width - 1 : 0] wr_ap_to_act;
// precharge
reg [pch_to_act_width - 1 : 0] pch_to_act;
reg [pch_all_to_valid_width - 1 : 0] pch_all_to_valid;
// others
reg [arf_to_valid_width - 1 : 0] arf_to_valid; // trfc
reg [pdn_to_valid_width - 1 : 0] pdn_to_valid; // power down exit time, not used currently
reg [srf_to_valid_width - 1 : 0] srf_to_valid; // self refresh exit time
reg [srf_to_valid_width - 1 : 0] srf_to_zq; // self refresh to zq calibration
reg [arf_period_width - 1 : 0] arf_period; // trefi
reg [pdn_period_width - 1 : 0] pdn_period; // will request power down if controller is idle for x number of clock cycles
reg [act_to_act_diff_bank_width - 1 : 0] act_to_act_diff_bank; // trrd
reg [four_act_to_act_width - 1 : 0] four_act_to_act; // tfaw
reg [four_act_to_act_width - 1 : 0] temp_four_act_to_act;
reg add_lat_on;
// div is a divider for our timinf parameters, div will be '1' in fullrate and '2' in halfrate
localparam div = dwidth_ratio / 2;
// all timing parameters will be divided by div and added with modulo of div
// this is to maximize out timing parameter in our halfrate memory controller
// eg: if we have 5 + 4 + 3 = 12 which is an odd number, the desired value we need in halfrate is 6
// we don't want to divide all timing parameters in java by '2'
// because this will result in 3 + 2 + 2 = 7 (5/2 gives 3 because we don't want any floating points in rtl)
// common timing parameters
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_to_rdwr <= 0;
act_to_pch <= 0;
act_to_act <= 0;
arf_to_valid <= 0;
pdn_to_valid <= 0;
srf_to_valid <= 0;
arf_period <= 0;
pdn_period <= 0;
act_to_act_diff_bank <= 0;
four_act_to_act <= 0;
end
else
begin
// set act_to_rdwr to zero when additive latency is enabled
if (mem_add_lat >= (mem_trcd - 1))
act_to_rdwr <= 0;
else
act_to_rdwr <= ((mem_trcd - mem_add_lat) / div) + ((mem_trcd - mem_add_lat) % div) - 1; // act to rd/wr - trcd (minus '1' because state machine requires another extra clock cycle for pre-processing)
act_to_pch <= (mem_tras / div) + (mem_tras % div); // act to pch - tras
act_to_act <= (mem_trc / div) + (mem_trc % div); // act to act (same bank) - trc
pch_to_act <= (mem_trp / div) + (mem_trp % div); // pch to act - trp
arf_to_valid <= (mem_trfc / div) + (mem_trfc % div); // arf to valid - trfc
pdn_to_valid <= (3 / div) + (3 % div); // pdn to valid - normally 3 clock cycles
srf_to_valid <= (mem_self_rfsh_exit_cycles / div) + (mem_self_rfsh_exit_cycles % div); // srf to valid - normally 200 clock cycles
arf_period <= (mem_trefi / div) + (mem_trefi % div); // arf period - trefi
pdn_period <= (mem_auto_pd_cycles / div) + (mem_auto_pd_cycles % div); // pdn count after cmd_queue is empty - spepcified by users, 10 maybe?
act_to_act_diff_bank <= (mem_trrd / div) + (mem_trrd % div); // act to act (diff banks) - trrd
temp_four_act_to_act <= (mem_tfaw / div) + (mem_tfaw % div);
// prevent four_act_to_act from getting negative value
if (temp_four_act_to_act >= 4)
four_act_to_act <= temp_four_act_to_act - 4; // valid window for 4 act - tfaw (minus '4' because of the tfaw logic)
else
four_act_to_act <= 0;
end
end
// memory specific timing parameters
generate
if (mem_type == "ddr")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_pch <= 0;
rd_ap_to_act <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
wr_ap_to_act <= 0;
wr_to_rd_diff_chips <= 0;
pch_all_to_valid <= 0;
end
else
begin
rd_to_rd <= ((mem_burst_length / 2) / div); // rd to rd - tccd
rd_to_wr <= ((mem_tcl + (mem_burst_length / 2) + mem_rd_to_wr_turnaround_oct) / div) + ((mem_tcl + (mem_burst_length / 2) + mem_rd_to_wr_turnaround_oct) % div); // rd to wr - cas + (bl/2)
rd_to_pch <= ((mem_burst_length / 2) / div); // rd to pch - (bl/2)
rd_ap_to_act <= (((mem_burst_length / 2) + mem_trp) / div) + (((mem_burst_length / 2) + mem_trp) % div);
wr_to_wr <= ((mem_burst_length / 2) / div); // wr to wr - tccd
wr_to_rd <= ((1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) / div) + ((1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) % div); // wr to rd - wl + (bl/2) + twtr (wl is always 1 in ddr)
wr_to_pch <= ((1 + (mem_burst_length / 2) + mem_twr) / div) + ((1 + (mem_burst_length / 2) + mem_twr) % div); // wr to pch - wl + (bl/2) + twr
wr_ap_to_act <= ((1 + (mem_burst_length / 2) + mem_twr + mem_trp) / div) + ((1 + (mem_burst_length / 2) + mem_twr + mem_trp) % div);
wr_to_rd_diff_chips <= (((mem_burst_length / 2) + 3 + mem_wr_to_rd_diff_chips_turnaround_oct) / div) + (((mem_burst_length / 2) + 3 + mem_wr_to_rd_diff_chips_turnaround_oct) % div); // wr to rd different rank - (wl - rl) + (bl/2) + 2 (dead cycles)
pch_all_to_valid <= (mem_trp / div) + (mem_trp % div);
end
end
end
else if (mem_type == "ddr2")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_pch <= 0;
rd_ap_to_act <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
wr_ap_to_act <= 0;
wr_to_rd_diff_chips <= 0;
pch_all_to_valid <= 0;
end
else
begin
rd_to_rd <= ((mem_burst_length / 2) / div); // tccd is 2 but we set to 4 because we do burst length of 8
rd_to_wr <= (((mem_burst_length / 2) + 2 + mem_rd_to_wr_turnaround_oct) / div) + (((mem_burst_length / 2) + 2 + mem_rd_to_wr_turnaround_oct) % div);
rd_to_pch <= ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2)) / div) + ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2)) % div);
rd_ap_to_act <= ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2) + mem_trp) / div) + ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2) + mem_trp) % div);
wr_to_wr <= ((mem_burst_length / 2) / div); // tccd is 2 but we set to 4 because we do burst length of 8
wr_to_rd <= ((mem_tcl - 1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) / div) + ((mem_tcl - 1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) % div); // removed add lat because write and read is cas command (add lat)
wr_to_pch <= ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr) / div) + ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr) % div);
wr_ap_to_act <= ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr + mem_trp) / div) + ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr + mem_trp) % div);
wr_to_rd_diff_chips <= (((mem_burst_length / 2) + 1 + mem_wr_to_rd_diff_chips_turnaround_oct) / div) + (((mem_burst_length / 2) + 1 + mem_wr_to_rd_diff_chips_turnaround_oct) % div);
pch_all_to_valid <= ((mem_trp + 1) / div) + ((mem_trp + 1) % div); // trpa = trp + 1
end
end
end
else if (mem_type == "ddr3")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_wr_bc <= 0;
rd_to_pch <= 0;
rd_ap_to_act <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
wr_ap_to_act <= 0;
wr_to_rd_diff_chips <= 0;
pch_all_to_valid <= 0;
srf_to_zq <= 0; // ddr3 specific
end
else
begin
rd_to_rd <= ((mem_burst_length / 2) / div);
rd_to_wr <= ((mem_tcl - mem_cas_wr_lat + 4 + 2 + mem_rd_to_wr_turnaround_oct) / div) + ((mem_tcl - mem_cas_wr_lat + 4 + 2 + mem_rd_to_wr_turnaround_oct) % div); // cas lat - cas wr lat + tccd + 2
rd_to_wr_bc <= ((mem_tcl - mem_cas_wr_lat + 2 + 2 + mem_rd_to_wr_turnaround_oct) / div) + ((mem_tcl - mem_cas_wr_lat + 2 + 2 + mem_rd_to_wr_turnaround_oct) % div); // tccd/2 <= 2
rd_to_pch <= ((mem_add_lat + max(mem_trtp, 4)) / div) + ((mem_add_lat + max(mem_trtp, 4)) % div);
rd_ap_to_act <= ((mem_add_lat + max(mem_trtp, 4) + mem_trp) / div) + ((mem_add_lat + max(mem_trtp, 4) + mem_trp) % div);
wr_to_wr <= ((mem_burst_length / 2) / div);
wr_to_rd <= ((mem_cas_wr_lat + (mem_burst_length / 2) + max(mem_twtr, 4) + mem_wr_to_rd_turnaround_oct) / div) + ((mem_cas_wr_lat + (mem_burst_length / 2) + max(mem_twtr, 4) + mem_wr_to_rd_turnaround_oct) % div); // reported by denali, wr to rd delay is add_lat + cas_wr_lat + (bl/2) + max(tccd or twtr)
wr_to_pch <= ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr) / div) + ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr) % div);
wr_ap_to_act <= ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr + mem_trp) / div) + ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr + mem_trp) % div);
wr_to_rd_diff_chips <= (((mem_cas_wr_lat - mem_tcl) + (mem_burst_length / 2) + 2 + mem_wr_to_rd_diff_chips_turnaround_oct) / div) + (((mem_cas_wr_lat - mem_tcl) + (mem_burst_length / 2) + 2 + mem_wr_to_rd_diff_chips_turnaround_oct) % div);
pch_all_to_valid <= (mem_trp / div) + (mem_trp % div);
srf_to_zq <= (256 / div);
end
end
end
endgenerate
// function to determine max of 2 inputs
function [wr_to_rd_width - 1 : 0] max;
input [wr_to_rd_width - 1 : 0] value1;
input [wr_to_rd_width - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
// indicate additive latency is on to state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
add_lat_on <= 1'b0;
end
else
begin
if (mem_add_lat == 0)
begin
if (act_to_rdwr == 0)
add_lat_on <= 1'b1;
else
add_lat_on <= 1'b0;
end
else
begin
// if al is greater than trcd-1, then we can do back to back activate-read/write
if (mem_add_lat >= (mem_trcd - 1))
add_lat_on <= 1'b1;
else
add_lat_on <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
[end] timing parameters
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[start] more / less compare logic
------------------------------------------------------------------------------*/
// more/less than n signal, this signal will be used in timer block, this will reduce timing violation
// because we will abstract away the comparator and set the compared value in a register
reg more_than_2_act_to_rdwr;
reg more_than_2_act_to_pch;
reg more_than_2_act_to_act;
reg more_than_2_rd_to_rd;
reg more_than_2_rd_to_wr;
reg more_than_2_rd_to_wr_bc;
reg more_than_2_rd_to_pch;
reg more_than_2_wr_to_wr;
reg more_than_2_wr_to_rd;
reg more_than_2_wr_to_pch;
reg more_than_2_rd_ap_to_act;
reg more_than_2_wr_ap_to_act;
reg more_than_2_pch_to_act;
reg more_than_2_act_to_act_diff_bank;
reg more_than_2_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_act_to_rdwr <= 1'b0;
more_than_2_act_to_pch <= 1'b0;
more_than_2_act_to_act <= 1'b0;
more_than_2_rd_to_rd <= 1'b0;
more_than_2_rd_to_wr <= 1'b0;
more_than_2_rd_to_wr_bc <= 1'b0;
more_than_2_rd_to_pch <= 1'b0;
more_than_2_wr_to_wr <= 1'b0;
more_than_2_wr_to_rd <= 1'b0;
more_than_2_wr_to_pch <= 1'b0;
more_than_2_rd_ap_to_act <= 1'b0;
more_than_2_wr_ap_to_act <= 1'b0;
more_than_2_pch_to_act <= 1'b0;
more_than_2_act_to_act_diff_bank <= 1'b0;
more_than_2_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr >= 2)
more_than_2_act_to_rdwr <= 1'b1;
else
more_than_2_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch >= 2)
more_than_2_act_to_pch <= 1'b1;
else
more_than_2_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 2)
more_than_2_act_to_act <= 1'b1;
else
more_than_2_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 2)
more_than_2_rd_to_rd <= 1'b1;
else
more_than_2_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 2)
more_than_2_rd_to_wr <= 1'b1;
else
more_than_2_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 2)
more_than_2_rd_to_wr_bc <= 1'b1;
else
more_than_2_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 2)
more_than_2_rd_to_pch <= 1'b1;
else
more_than_2_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 2)
more_than_2_wr_to_wr <= 1'b1;
else
more_than_2_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 2)
more_than_2_wr_to_rd <= 1'b1;
else
more_than_2_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 2)
more_than_2_wr_to_pch <= 1'b1;
else
more_than_2_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 2)
more_than_2_rd_ap_to_act <= 1'b1;
else
more_than_2_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 2)
more_than_2_wr_ap_to_act <= 1'b1;
else
more_than_2_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act >= 2)
more_than_2_pch_to_act <= 1'b1;
else
more_than_2_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 2)
more_than_2_act_to_act_diff_bank <= 1'b1;
else
more_than_2_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 2)
more_than_2_four_act_to_act <= 1'b1;
else
more_than_2_four_act_to_act <= 1'b0;
end
end
reg less_than_2_act_to_rdwr;
reg less_than_2_act_to_pch;
reg less_than_2_act_to_act;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_rd_to_pch;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_wr_to_rd_diff_chips;
reg less_than_2_wr_to_pch;
reg less_than_2_rd_ap_to_act;
reg less_than_2_wr_ap_to_act;
reg less_than_2_pch_to_act;
reg less_than_2_act_to_act_diff_bank;
reg less_than_2_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_rdwr <= 1'b0;
less_than_2_act_to_pch <= 1'b0;
less_than_2_act_to_act <= 1'b0;
less_than_2_rd_to_rd <= 1'b0;
less_than_2_rd_to_wr <= 1'b0;
less_than_2_rd_to_wr_bc <= 1'b0;
less_than_2_rd_to_pch <= 1'b0;
less_than_2_wr_to_wr <= 1'b0;
less_than_2_wr_to_rd <= 1'b0;
less_than_2_wr_to_rd_diff_chips <= 1'b0;
less_than_2_wr_to_pch <= 1'b0;
less_than_2_rd_ap_to_act <= 1'b0;
less_than_2_wr_ap_to_act <= 1'b0;
less_than_2_pch_to_act <= 1'b0;
less_than_2_act_to_act_diff_bank <= 1'b0;
less_than_2_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr <= 2)
less_than_2_act_to_rdwr <= 1'b1;
else
less_than_2_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch <= 2)
less_than_2_act_to_pch <= 1'b1;
else
less_than_2_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 2)
less_than_2_act_to_act <= 1'b1;
else
less_than_2_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 2)
less_than_2_rd_to_pch <= 1'b1;
else
less_than_2_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 2)
less_than_2_wr_to_rd_diff_chips <= 1'b1;
else
less_than_2_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 2)
less_than_2_wr_to_pch <= 1'b1;
else
less_than_2_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 2)
less_than_2_rd_ap_to_act <= 1'b1;
else
less_than_2_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 2)
less_than_2_wr_ap_to_act <= 1'b1;
else
less_than_2_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act <= 2)
less_than_2_pch_to_act <= 1'b1;
else
less_than_2_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 2)
less_than_2_four_act_to_act <= 1'b1;
else
less_than_2_four_act_to_act <= 1'b0;
end
end
reg more_than_3_act_to_rdwr;
reg more_than_3_act_to_pch;
reg more_than_3_act_to_act;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_rd_to_pch;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_wr_to_pch;
reg more_than_3_rd_ap_to_act;
reg more_than_3_wr_ap_to_act;
reg more_than_3_pch_to_act;
reg more_than_3_act_to_act_diff_bank;
reg more_than_3_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_act_to_rdwr <= 1'b0;
more_than_3_act_to_pch <= 1'b0;
more_than_3_act_to_act <= 1'b0;
more_than_3_rd_to_rd <= 1'b0;
more_than_3_rd_to_wr <= 1'b0;
more_than_3_rd_to_wr_bc <= 1'b0;
more_than_3_rd_to_pch <= 1'b0;
more_than_3_wr_to_wr <= 1'b0;
more_than_3_wr_to_rd <= 1'b0;
more_than_3_wr_to_pch <= 1'b0;
more_than_3_rd_ap_to_act <= 1'b0;
more_than_3_wr_ap_to_act <= 1'b0;
more_than_3_pch_to_act <= 1'b0;
more_than_3_act_to_act_diff_bank <= 1'b0;
more_than_3_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr >= 3)
more_than_3_act_to_rdwr <= 1'b1;
else
more_than_3_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch >= 3)
more_than_3_act_to_pch <= 1'b1;
else
more_than_3_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 3)
more_than_3_act_to_act <= 1'b1;
else
more_than_3_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 3)
more_than_3_rd_to_pch <= 1'b1;
else
more_than_3_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 3)
more_than_3_wr_to_pch <= 1'b1;
else
more_than_3_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 3)
more_than_3_rd_ap_to_act <= 1'b1;
else
more_than_3_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 3)
more_than_3_wr_ap_to_act <= 1'b1;
else
more_than_3_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act >= 3)
more_than_3_pch_to_act <= 1'b1;
else
more_than_3_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 3)
more_than_3_act_to_act_diff_bank <= 1'b1;
else
more_than_3_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 3)
more_than_3_four_act_to_act <= 1'b1;
else
more_than_3_four_act_to_act <= 1'b0;
end
end
reg less_than_3_act_to_rdwr;
reg less_than_3_act_to_pch;
reg less_than_3_act_to_act;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_rd_to_pch;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_wr_to_rd_diff_chips;
reg less_than_3_wr_to_pch;
reg less_than_3_rd_ap_to_act;
reg less_than_3_wr_ap_to_act;
reg less_than_3_pch_to_act;
reg less_than_3_act_to_act_diff_bank;
reg less_than_3_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_rdwr <= 1'b0;
less_than_3_act_to_pch <= 1'b0;
less_than_3_act_to_act <= 1'b0;
less_than_3_rd_to_rd <= 1'b0;
less_than_3_rd_to_wr <= 1'b0;
less_than_3_rd_to_wr_bc <= 1'b0;
less_than_3_rd_to_pch <= 1'b0;
less_than_3_wr_to_wr <= 1'b0;
less_than_3_wr_to_rd <= 1'b0;
less_than_3_wr_to_rd_diff_chips <= 1'b0;
less_than_3_wr_to_pch <= 1'b0;
less_than_3_rd_ap_to_act <= 1'b0;
less_than_3_wr_ap_to_act <= 1'b0;
less_than_3_pch_to_act <= 1'b0;
less_than_3_act_to_act_diff_bank <= 1'b0;
less_than_3_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr <= 3)
less_than_3_act_to_rdwr <= 1'b1;
else
less_than_3_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch <= 3)
less_than_3_act_to_pch <= 1'b1;
else
less_than_3_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 3)
less_than_3_act_to_act <= 1'b1;
else
less_than_3_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 3)
less_than_3_rd_to_pch <= 1'b1;
else
less_than_3_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 3)
less_than_3_wr_to_rd_diff_chips <= 1'b1;
else
less_than_3_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 3)
less_than_3_wr_to_pch <= 1'b1;
else
less_than_3_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 3)
less_than_3_rd_ap_to_act <= 1'b1;
else
less_than_3_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 3)
less_than_3_wr_ap_to_act <= 1'b1;
else
less_than_3_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act <= 3)
less_than_3_pch_to_act <= 1'b1;
else
less_than_3_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 3)
less_than_3_four_act_to_act <= 1'b1;
else
less_than_3_four_act_to_act <= 1'b0;
end
end
reg more_than_4_act_to_rdwr;
reg more_than_4_act_to_pch;
reg more_than_4_act_to_act;
reg more_than_4_rd_to_rd;
reg more_than_4_rd_to_wr;
reg more_than_4_rd_to_wr_bc;
reg more_than_4_rd_to_pch;
reg more_than_4_wr_to_wr;
reg more_than_4_wr_to_rd;
reg more_than_4_wr_to_pch;
reg more_than_4_rd_ap_to_act;
reg more_than_4_wr_ap_to_act;
reg more_than_4_pch_to_act;
reg more_than_4_act_to_act_diff_bank;
reg more_than_4_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_4_act_to_rdwr <= 1'b0;
more_than_4_act_to_pch <= 1'b0;
more_than_4_act_to_act <= 1'b0;
more_than_4_rd_to_rd <= 1'b0;
more_than_4_rd_to_wr <= 1'b0;
more_than_4_rd_to_wr_bc <= 1'b0;
more_than_4_rd_to_pch <= 1'b0;
more_than_4_wr_to_wr <= 1'b0;
more_than_4_wr_to_rd <= 1'b0;
more_than_4_wr_to_pch <= 1'b0;
more_than_4_rd_ap_to_act <= 1'b0;
more_than_4_wr_ap_to_act <= 1'b0;
more_than_4_pch_to_act <= 1'b0;
more_than_4_act_to_act_diff_bank <= 1'b0;
more_than_4_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr >= 4)
more_than_4_act_to_rdwr <= 1'b1;
else
more_than_4_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch >= 4)
more_than_4_act_to_pch <= 1'b1;
else
more_than_4_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 4)
more_than_4_act_to_act <= 1'b1;
else
more_than_4_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 4)
more_than_4_rd_to_rd <= 1'b1;
else
more_than_4_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 4)
more_than_4_rd_to_wr <= 1'b1;
else
more_than_4_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 4)
more_than_4_rd_to_wr_bc <= 1'b1;
else
more_than_4_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 4)
more_than_4_rd_to_pch <= 1'b1;
else
more_than_4_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 4)
more_than_4_wr_to_wr <= 1'b1;
else
more_than_4_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 4)
more_than_4_wr_to_rd <= 1'b1;
else
more_than_4_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 4)
more_than_4_wr_to_pch <= 1'b1;
else
more_than_4_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 4)
more_than_4_rd_ap_to_act <= 1'b1;
else
more_than_4_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 4)
more_than_4_wr_ap_to_act <= 1'b1;
else
more_than_4_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act >= 4)
more_than_4_pch_to_act <= 1'b1;
else
more_than_4_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 4)
more_than_4_act_to_act_diff_bank <= 1'b1;
else
more_than_4_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 4)
more_than_4_four_act_to_act <= 1'b1;
else
more_than_4_four_act_to_act <= 1'b0;
end
end
reg less_than_4_act_to_rdwr;
reg less_than_4_act_to_pch;
reg less_than_4_act_to_act;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_rd_to_pch;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_wr_to_rd_diff_chips;
reg less_than_4_wr_to_pch;
reg less_than_4_rd_ap_to_act;
reg less_than_4_wr_ap_to_act;
reg less_than_4_pch_to_act;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_rdwr <= 1'b0;
less_than_4_act_to_pch <= 1'b0;
less_than_4_act_to_act <= 1'b0;
less_than_4_rd_to_rd <= 1'b0;
less_than_4_rd_to_wr <= 1'b0;
less_than_4_rd_to_wr_bc <= 1'b0;
less_than_4_rd_to_pch <= 1'b0;
less_than_4_wr_to_wr <= 1'b0;
less_than_4_wr_to_rd <= 1'b0;
less_than_4_wr_to_rd_diff_chips <= 1'b0;
less_than_4_wr_to_pch <= 1'b0;
less_than_4_rd_ap_to_act <= 1'b0;
less_than_4_wr_ap_to_act <= 1'b0;
less_than_4_pch_to_act <= 1'b0;
less_than_4_act_to_act_diff_bank <= 1'b0;
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr <= 4)
less_than_4_act_to_rdwr <= 1'b1;
else
less_than_4_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch <= 4)
less_than_4_act_to_pch <= 1'b1;
else
less_than_4_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 4)
less_than_4_act_to_act <= 1'b1;
else
less_than_4_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 4)
less_than_4_rd_to_pch <= 1'b1;
else
less_than_4_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 4)
less_than_4_wr_to_rd_diff_chips <= 1'b1;
else
less_than_4_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 4)
less_than_4_wr_to_pch <= 1'b1;
else
less_than_4_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 4)
less_than_4_rd_ap_to_act <= 1'b1;
else
less_than_4_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 4)
less_than_4_wr_ap_to_act <= 1'b1;
else
less_than_4_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act <= 4)
less_than_4_pch_to_act <= 1'b1;
else
less_than_4_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
reg more_than_5_act_to_rdwr;
reg more_than_5_act_to_pch;
reg more_than_5_act_to_act;
reg more_than_5_rd_to_rd;
reg more_than_5_rd_to_wr;
reg more_than_5_rd_to_wr_bc;
reg more_than_5_rd_to_pch;
reg more_than_5_wr_to_wr;
reg more_than_5_wr_to_rd;
reg more_than_5_wr_to_pch;
reg more_than_5_rd_ap_to_act;
reg more_than_5_wr_ap_to_act;
reg more_than_5_pch_to_act;
reg more_than_5_act_to_act_diff_bank;
reg more_than_5_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_5_act_to_rdwr <= 1'b0;
more_than_5_act_to_pch <= 1'b0;
more_than_5_act_to_act <= 1'b0;
more_than_5_rd_to_rd <= 1'b0;
more_than_5_rd_to_wr <= 1'b0;
more_than_5_rd_to_wr_bc <= 1'b0;
more_than_5_rd_to_pch <= 1'b0;
more_than_5_wr_to_wr <= 1'b0;
more_than_5_wr_to_rd <= 1'b0;
more_than_5_wr_to_pch <= 1'b0;
more_than_5_rd_ap_to_act <= 1'b0;
more_than_5_wr_ap_to_act <= 1'b0;
more_than_5_pch_to_act <= 1'b0;
more_than_5_act_to_act_diff_bank <= 1'b0;
more_than_5_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr >= 5)
more_than_5_act_to_rdwr <= 1'b1;
else
more_than_5_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch >= 5)
more_than_5_act_to_pch <= 1'b1;
else
more_than_5_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 5)
more_than_5_act_to_act <= 1'b1;
else
more_than_5_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 5)
more_than_5_rd_to_rd <= 1'b1;
else
more_than_5_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 5)
more_than_5_rd_to_wr <= 1'b1;
else
more_than_5_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 5)
more_than_5_rd_to_wr_bc <= 1'b1;
else
more_than_5_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 5)
more_than_5_rd_to_pch <= 1'b1;
else
more_than_5_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 5)
more_than_5_wr_to_wr <= 1'b1;
else
more_than_5_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 5)
more_than_5_wr_to_rd <= 1'b1;
else
more_than_5_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 5)
more_than_5_wr_to_pch <= 1'b1;
else
more_than_5_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 5)
more_than_5_rd_ap_to_act <= 1'b1;
else
more_than_5_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 5)
more_than_5_wr_ap_to_act <= 1'b1;
else
more_than_5_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act >= 5)
more_than_5_pch_to_act <= 1'b1;
else
more_than_5_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 5)
more_than_5_act_to_act_diff_bank <= 1'b1;
else
more_than_5_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 5)
more_than_5_four_act_to_act <= 1'b1;
else
more_than_5_four_act_to_act <= 1'b0;
end
end
reg less_than_5_act_to_rdwr;
reg less_than_5_act_to_pch;
reg less_than_5_act_to_act;
reg less_than_5_rd_to_rd;
reg less_than_5_rd_to_wr;
reg less_than_5_rd_to_wr_bc;
reg less_than_5_rd_to_pch;
reg less_than_5_wr_to_wr;
reg less_than_5_wr_to_rd;
reg less_than_5_wr_to_rd_diff_chips;
reg less_than_5_wr_to_pch;
reg less_than_5_rd_ap_to_act;
reg less_than_5_wr_ap_to_act;
reg less_than_5_pch_to_act;
reg less_than_5_act_to_act_diff_bank;
reg less_than_5_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_5_act_to_rdwr <= 1'b0;
less_than_5_act_to_pch <= 1'b0;
less_than_5_act_to_act <= 1'b0;
less_than_5_rd_to_rd <= 1'b0;
less_than_5_rd_to_wr <= 1'b0;
less_than_5_rd_to_wr_bc <= 1'b0;
less_than_5_rd_to_pch <= 1'b0;
less_than_5_wr_to_wr <= 1'b0;
less_than_5_wr_to_rd <= 1'b0;
less_than_5_wr_to_rd_diff_chips <= 1'b0;
less_than_5_wr_to_pch <= 1'b0;
less_than_5_rd_ap_to_act <= 1'b0;
less_than_5_wr_ap_to_act <= 1'b0;
less_than_5_pch_to_act <= 1'b0;
less_than_5_act_to_act_diff_bank <= 1'b0;
less_than_5_four_act_to_act <= 1'b0;
end
else
begin
// act_to_rdwr
if (act_to_rdwr <= 5)
less_than_5_act_to_rdwr <= 1'b1;
else
less_than_5_act_to_rdwr <= 1'b0;
// act_to_pch
if (act_to_pch <= 5)
less_than_5_act_to_pch <= 1'b1;
else
less_than_5_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 5)
less_than_5_act_to_act <= 1'b1;
else
less_than_5_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 5)
less_than_5_rd_to_rd <= 1'b1;
else
less_than_5_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 5)
less_than_5_rd_to_wr <= 1'b1;
else
less_than_5_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 5)
less_than_5_rd_to_wr_bc <= 1'b1;
else
less_than_5_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 5)
less_than_5_rd_to_pch <= 1'b1;
else
less_than_5_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 5)
less_than_5_wr_to_wr <= 1'b1;
else
less_than_5_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 5)
less_than_5_wr_to_rd <= 1'b1;
else
less_than_5_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 5)
less_than_5_wr_to_rd_diff_chips <= 1'b1;
else
less_than_5_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 5)
less_than_5_wr_to_pch <= 1'b1;
else
less_than_5_wr_to_pch <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 5)
less_than_5_rd_ap_to_act <= 1'b1;
else
less_than_5_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 5)
less_than_5_wr_ap_to_act <= 1'b1;
else
less_than_5_wr_ap_to_act <= 1'b0;
// pch_to_act
if (pch_to_act <= 5)
less_than_5_pch_to_act <= 1'b1;
else
less_than_5_pch_to_act <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 5)
less_than_5_act_to_act_diff_bank <= 1'b1;
else
less_than_5_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 5)
less_than_5_four_act_to_act <= 1'b1;
else
less_than_5_four_act_to_act <= 1'b0;
end
end
/*------------------------------------------------------------------------------
[end] more / less compare logic
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ?
(address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR2 controller ODT block
//
// File : alt_ddrx_ddr2_odt_gen.v
//
// Abstract : DDR2 ODT signal generator block
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_ddr2_odt_gen
# (parameter
DWIDTH_RATIO = 2,
MEMORY_BURSTLENGTH = 8,
ADD_LAT_BUS_WIDTH = 3,
CTL_OUTPUT_REGD = 0,
TCL_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_add_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [ADD_LAT_BUS_WIDTH-1:0] mem_add_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
localparam TCL_PIPE_LENGTH = 2**TCL_BUS_WIDTH; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam TAOND = 2;
localparam TAOFD = 2.5;
wire do_write;
wire do_read;
wire [1:0] regd_output;
wire [TCL_BUS_WIDTH-1:0] int_tcwl_unreg;
reg [TCL_BUS_WIDTH-1:0] int_tcwl;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [TCL_PIPE_LENGTH-1:0] do_read_pipe;
assign int_odt_l = combi_odt_l | reg_odt_l;
assign int_odt_h = combi_odt_h | reg_odt_h;
assign regd_output = (DWIDTH_RATIO == 2) ? (CTL_OUTPUT_REGD ? 2'd1 : 2'd0) : (CTL_OUTPUT_REGD ? 2'd2 : 2'd0);
assign int_tcwl_unreg = (mem_tcl + mem_add_lat + regd_output - 1'b1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[int_tcwl - 4];
end
else // half rate
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[(int_tcwl - 4)/2];
end
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[int_tcwl - 3];
end
else // half rate
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[(int_tcwl - 3)/2];
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (do_write)
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],do_write};
else
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (do_read)
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],do_read};
else
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
// these blocks already assumes burstlength 8 in half rate and BL4 in full rate
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
combi_odt_l <= 1'b1;
else
combi_odt_l <= 1'b0;
end
else // half rate
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_read)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
else
begin
if (start_odt_read)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_write)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else
if (DWIDTH_RATIO == 2)
begin
reg_odt_h <= 1'b0;
if (start_odt_write || start_odt_read)
begin
reg_odt_l <= 1'b1;
offset_code <= 2;
end
else if (offset_code == 2)
offset_code <= 3;
else if (offset_code == 3)
begin
offset_code <= 0;
reg_odt_l <= 1'b0;
end
end
else
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
else
begin
if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
end
end
endmodule
|
// (c) 2001-2018 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// megafunction wizard: %shift register (ram-based)%
// generation: standard
// version: wm1.0
// module: altshift_taps
// ============================================================
// file name: altera_up_edge_detection_data_shift_register.v
// megafunction name(s):
// altshift_taps
//
// simulation library files(s):
// altera_mf
// ============================================================
// ************************************************************
// this is a wizard-generated file. do not edit this file!
//
// 6.1 build 201 11/27/2006 sj full version
// ************************************************************
//copyright (c) 1991-2014 altera corporation
//your use of altera corporation's design tools, logic functions
//and other software and tools, and its ampp partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the altera program license
//subscription agreement, altera megacore function license
//agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by altera and sold by
//altera or its authorized distributors. please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_up_edge_detection_data_shift_register (
clken,
clock,
shiftin,
shiftout,
taps);
parameter dw = 10;
parameter size = 720;
input clken;
input clock;
input [dw:1] shiftin;
output [dw:1] shiftout;
output [dw:1] taps;
wire [dw:1] sub_wire0;
wire [dw:1] sub_wire1;
wire [dw:1] taps = sub_wire0[dw:1];
wire [dw:1] shiftout = sub_wire1[dw:1];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire1));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 1,
altshift_taps_component.tap_distance = size,
altshift_taps_component.width = dw;
endmodule
// ============================================================
// cnx file retrieval info
// ============================================================
// retrieval info: private: clken numeric "1"
// retrieval info: private: group_taps numeric "0"
// retrieval info: private: intended_device_family string "cyclone ii"
// retrieval info: private: number_of_taps numeric "1"
// retrieval info: private: ram_block_type numeric "0"
// retrieval info: private: tap_distance numeric "720"
// retrieval info: private: width numeric "10"
// retrieval info: constant: lpm_type string "altshift_taps"
// retrieval info: constant: number_of_taps numeric "1"
// retrieval info: constant: tap_distance numeric "720"
// retrieval info: constant: width numeric "10"
// retrieval info: used_port: clken 0 0 0 0 input vcc clken
// retrieval info: used_port: clock 0 0 0 0 input nodefval clock
// retrieval info: used_port: shiftin 0 0 10 0 input nodefval shiftin[9..0]
// retrieval info: used_port: shiftout 0 0 10 0 output nodefval shiftout[9..0]
// retrieval info: used_port: taps 0 0 10 0 output nodefval taps[9..0]
// retrieval info: connect: @shiftin 0 0 10 0 shiftin 0 0 10 0
// retrieval info: connect: shiftout 0 0 10 0 @shiftout 0 0 10 0
// retrieval info: connect: taps 0 0 10 0 @taps 0 0 10 0
// retrieval info: connect: @clock 0 0 0 0 clock 0 0 0 0
// retrieval info: connect: @clken 0 0 0 0 clken 0 0 0 0
// retrieval info: library: altera_mf altera_mf.altera_mf_components.all
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register.v true
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register.inc false
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register.cmp false
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register.bsf false
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register_inst.v false
// retrieval info: gen_file: type_normal altera_up_edge_detection_data_shift_register_bb.v true
// retrieval info: lib_file: altera_mf
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $
// $Revision: #2 $
// $Date: 2013/06/03 $
// $Author: wkleong $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reg reset_out,
output reg reset_req
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
localparam DEPTH = 2;
localparam CLKEN_LAGS_RESET = 0;
localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1;
wire merged_reset;
wire reset_out_pre;
// Registers and Interconnect
(*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain;
reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain;
reg r_sync_rst_dly;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out_pre = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
end
endgenerate
generate if (RESET_REQUEST_PRESENT == 0) begin
always @* begin
reset_out = reset_out_pre;
reset_req = 1'b0;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= 3'b111;
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {DEPTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[2] == 1'b1)
begin
r_sync_rst_chain <= {DEPTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
initial
begin
r_sync_rst_dly <= 1'b1;
r_sync_rst <= 1'b1;
r_early_rst <= 1'b1;
end
always @(posedge clk)
begin
// Delayed reset pipeline register
r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1];
case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// megafunction wizard: %altecc%
// generation: standard
// version: wm1.0
// module: altecc_encoder
// ============================================================
// file name: alt_mem_ddrx_ecc_encoder_32.v
// megafunction name(s):
// altecc_encoder
//
// simulation library files(s):
//
// ============================================================
// ************************************************************
// this is a wizard-generated file. do not edit this file!
//
// 10.0 internal build 257 07/26/2010 sp 1 pn full version
// ************************************************************
//copyright (c) 1991-2010 altera corporation
//your use of altera corporation's design tools, logic functions
//and other software and tools, and its ampp partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the altera program license
//subscription agreement, altera megacore function license
//agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by altera and sold by
//altera or its authorized distributors. please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="stratix iii" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
//version_begin 10.0sp1 cbx_altecc_encoder 2010:07:26:21:21:15:pn cbx_mgl 2010:07:26:21:25:47:pn version_end
// synthesis verilog_input_version verilog_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
( parameter
cfg_ecc_enc_reg = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final;
wire [37:0] parity_final_wire;
reg [37:0] parity_final_reg;
wire [37:0] q_wire;
reg [37:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
(data_wire[31] ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_final_wire = {
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[37] ^ parity_final[36]),
(q_reg[36] ^ parity_final[35]),
(q_reg[35] ^ parity_final[34]),
(q_reg[34] ^ parity_final[33]),
(q_reg[33] ^ parity_final[32]),
(q_reg[32] ^ parity_final[31]),
parity_final_reg[31 : 0]
},
q = {parity_final[37], q_reg},
q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
generate
if (cfg_ecc_enc_reg)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
//valid file
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32 #
( parameter
cfg_ecc_enc_reg = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
(
.cfg_ecc_enc_reg (cfg_ecc_enc_reg)
)
alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// cnx file retrieval info
// ============================================================
// retrieval info: private: intended_device_family string "stratix iii"
// retrieval info: private: synth_wrapper_gen_postfix string "1"
// retrieval info: library: altera_mf altera_mf.altera_mf_components.all
// retrieval info: constant: intended_device_family string "stratix iii"
// retrieval info: constant: lpm_pipeline numeric "0"
// retrieval info: constant: width_codeword numeric "39"
// retrieval info: constant: width_dataword numeric "32"
// retrieval info: used_port: data 0 0 32 0 input nodefval "data[31..0]"
// retrieval info: used_port: q 0 0 39 0 output nodefval "q[38..0]"
// retrieval info: connect: @data 0 0 32 0 data 0 0 32 0
// retrieval info: connect: q 0 0 39 0 @q 0 0 39 0
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder.v false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder.inc false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder.cmp false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder.bsf false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_inst.v false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_bb.v false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32.v true
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32.inc false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32.cmp false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32.bsf false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32_inst.v false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32_bb.v false
// retrieval info: gen_file: type_normal alt_mem_ddrx_ecc_encoder_32_syn.v true
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036 10762
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_2_rd_to_rd;
reg more_than_2_rd_to_wr;
reg more_than_2_wr_to_wr;
reg more_than_2_wr_to_rd;
reg more_than_2_rd_to_wr_bc;
reg more_than_2_wr_to_rd_bc;
reg more_than_2_rd_to_rd_diff_chip;
reg more_than_2_rd_to_wr_diff_chip;
reg more_than_2_wr_to_wr_diff_chip;
reg more_than_2_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
reg more_than_x0_rd_to_rd;
reg more_than_x0_rd_to_wr;
reg more_than_x0_wr_to_wr;
reg more_than_x0_wr_to_rd;
reg more_than_x0_rd_to_wr_bc;
reg more_than_x0_wr_to_rd_bc;
reg more_than_x0_rd_to_rd_diff_chip;
reg more_than_x0_rd_to_wr_diff_chip;
reg more_than_x0_wr_to_wr_diff_chip;
reg more_than_x0_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 2'b00;
localparam WR = 2'b01;
localparam RD = 2'b10;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_x0_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_x0_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_x0_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_x0_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_x0_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_x0_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 2)
more_than_2_rd_to_rd <= 1'b1;
else
more_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 2)
more_than_2_rd_to_wr <= 1'b1;
else
more_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 2)
more_than_2_wr_to_wr <= 1'b1;
else
more_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 2)
more_than_2_wr_to_rd <= 1'b1;
else
more_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 2)
more_than_2_rd_to_wr_bc <= 1'b1;
else
more_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 2)
more_than_2_wr_to_rd_bc <= 1'b1;
else
more_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 2)
more_than_2_rd_to_rd_diff_chip <= 1'b1;
else
more_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 2)
more_than_2_rd_to_wr_diff_chip <= 1'b1;
else
more_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 2)
more_than_2_wr_to_wr_diff_chip <= 1'b1;
else
more_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 2)
more_than_2_wr_to_rd_diff_chip <= 1'b1;
else
more_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
always @ (*)
begin
more_than_x0_rd_to_rd = more_than_3_rd_to_rd;
more_than_x0_rd_to_wr = more_than_3_rd_to_wr;
more_than_x0_wr_to_wr = more_than_3_wr_to_wr;
more_than_x0_wr_to_rd = more_than_3_wr_to_rd;
more_than_x0_rd_to_wr_bc = more_than_3_rd_to_wr_bc;
more_than_x0_wr_to_rd_bc = more_than_3_wr_to_rd_bc;
more_than_x0_rd_to_rd_diff_chip = more_than_3_rd_to_rd_diff_chip;
more_than_x0_rd_to_wr_diff_chip = more_than_3_rd_to_wr_diff_chip;
more_than_x0_wr_to_wr_diff_chip = more_than_3_wr_to_wr_diff_chip;
more_than_x0_wr_to_rd_diff_chip = more_than_3_wr_to_rd_diff_chip;
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
always @ (*)
begin
more_than_x0_rd_to_rd = more_than_2_rd_to_rd;
more_than_x0_rd_to_wr = more_than_2_rd_to_wr;
more_than_x0_wr_to_wr = more_than_2_wr_to_wr;
more_than_x0_wr_to_rd = more_than_2_wr_to_rd;
more_than_x0_rd_to_wr_bc = more_than_2_rd_to_wr_bc;
more_than_x0_wr_to_rd_bc = more_than_2_wr_to_rd_bc;
more_than_x0_rd_to_rd_diff_chip = more_than_2_rd_to_rd_diff_chip;
more_than_x0_rd_to_wr_diff_chip = more_than_2_rd_to_wr_diff_chip;
more_than_x0_wr_to_wr_diff_chip = more_than_2_wr_to_wr_diff_chip;
more_than_x0_wr_to_rd_diff_chip = more_than_2_wr_to_rd_diff_chip;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
always @ (*)
begin
act_tfaw_shift_reg [2] <= 1'b0;
act_tfaw_shift_reg [1] <= 1'b0;
act_tfaw_shift_reg [0] <= 1'b0;
end
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (*)
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr_combi = t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip;
effective_wr_to_rd_combi = t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_combi = t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_combi = 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip_combi = t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip_combi = 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_combi = t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_combi = 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip_combi = t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip_combi = 1'b1;
end
else
begin
effective_rd_to_wr_combi = effective_rd_to_wr;
effective_rd_to_wr_diff_chip_combi = effective_rd_to_wr_diff_chip;
effective_wr_to_rd_combi = effective_wr_to_rd;
effective_wr_to_rd_diff_chip_combi = effective_wr_to_rd_diff_chip;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
effective_rd_to_wr <= effective_rd_to_wr_combi;
effective_rd_to_wr_diff_chip <= effective_rd_to_wr_diff_chip_combi;
effective_wr_to_rd <= effective_wr_to_rd_combi;
effective_wr_to_rd_diff_chip <= effective_wr_to_rd_diff_chip_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [1 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate && int_to_chip_c [s_cs]) // to current chip only
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr_combi - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip_combi - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd_combi - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip_combi - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE2_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
parameter ADDR_RANGE3_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address <= ADDR_RANGE2_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE3_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = ""
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata
);
localparam MIF_ADDR_REG = 6'b011111;
localparam START_REG = 6'b000010;
generate
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
endgenerate
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// (c) 2001-2018 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module sram_sram_0 (
// inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// bi-directional
sram_dq,
// outputs
readdata,
readdatavalid,
sram_addr,
sram_lb_n,
sram_ub_n,
sram_ce_n,
sram_oe_n,
sram_we_n
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input clk;
input reset;
input [19: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// bi-directional
inout [15: 0] sram_dq; // sram data bus 16 bits
// outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [19: 0] sram_addr; // sram address bus 18 bits
output reg sram_lb_n; // sram low-byte data mask
output reg sram_ub_n; // sram high-byte data mask
output reg sram_ce_n; // sram chip chipselect
output reg sram_oe_n; // sram output chipselect
output reg sram_we_n; // sram write chipselect
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
// internal registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// state machine registers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
// output registers
always @(posedge clk)
begin
readdata <= sram_dq;
readdatavalid <= is_read;
sram_addr <= address;
sram_lb_n <= ~(byteenable[0] & (read | write));
sram_ub_n <= ~(byteenable[1] & (read | write));
sram_ce_n <= ~(read | write);
sram_oe_n <= ~read;
sram_we_n <= ~write;
end
// internal registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* combinational logic *
*****************************************************************************/
// output assignments
assign sram_dq = (is_write) ? writedata_reg : 16'hzzzz;
// internal assignments
/*****************************************************************************
* internal modules *
*****************************************************************************/
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
// (c) 2001-2012 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_mif_reader
#(
parameter reconfig_addr_width = 6,
parameter reconfig_data_width = 32,
parameter mif_addr_width = 6,
parameter rom_addr_width = 9, // 512 words x
parameter rom_data_width = 32, // 32 bits per word = 20kb
parameter rom_num_words = 512, // default 512 32-bit words = 1 m20k
parameter device_family = "stratix v",
parameter enable_mif = 0,
parameter mif_file_name = ""
) (
// inputs
input wire mif_clk,
input wire mif_rst,
// reconfig module interface for internal register mapping
input wire reconfig_busy, // waitrequest
input wire [reconfig_data_width-1:0] reconfig_read_data,
output reg [reconfig_data_width-1:0] reconfig_write_data,
output reg [reconfig_addr_width-1:0] reconfig_addr,
output reg reconfig_write,
output reg reconfig_read,
// mif controller interface
input wire [rom_addr_width-1:0] mif_base_addr,
input wire mif_start,
output wire mif_busy
);
// note: assumes settings opcodes/registers are continguous and op_mode is 0
// rom interface ctlr states
localparam num_states = 5;
localparam state_reg_width = 32;
localparam mif_idle = 32'd0;
localparam set_instr_addr = 32'd1;
localparam fetch_instr = 32'd2;
localparam wait_for_rom_instr = 32'd3;
localparam store_instr = 32'd4;
localparam decode_rom_instr = 32'd5;
localparam set_data_addr = 32'd6;
localparam set_data_addr_dly = 32'd34;
localparam fetch_data = 32'd7;
localparam wait_for_rom_data = 32'd8;
localparam store_data = 32'd9;
localparam set_index = 32'd35;
localparam change_settings_reg = 32'd10;
localparam set_mode_reg_info = 32'd11;
localparam wait_mode_reg = 32'd12;
localparam save_mode_reg = 32'd13;
localparam set_wr_mode = 32'd14;
localparam wait_write_mode = 32'd15;
localparam init_reconfig_params = 32'd16;
localparam check_reconfig_setting = 32'd17;
localparam write_reconfig_setting = 32'd18;
localparam decrement_setting_num = 32'd19;
localparam check_c_settings = 32'd20;
localparam write_c_settings = 32'd21;
localparam decrement_c_num = 32'd22;
localparam check_dps_settings = 32'd23;
localparam write_dps_settings = 32'd24;
localparam decrement_dps_num = 32'd25;
localparam start_reconfig_change = 32'd26;
localparam start_reconfig_delay = 32'd27;
localparam start_reconfig_delay2 = 32'd28;
localparam wait_done_signal = 32'd29;
localparam set_mode_reg = 32'd30;
localparam write_final_mode = 32'd31;
localparam wait_final_mode = 32'd32;
localparam mif_streaming_done = 32'd33;
// mif opcodes
// addresses for settings from pll reconfig module
localparam op_mode = 6'b000000;
localparam op_status = 6'b000001; // read only
localparam op_start = 6'b000010;
localparam op_n = 6'b000011;
localparam op_m = 6'b000100;
localparam op_c_counters = 6'b000101;
localparam op_dps = 6'b000110;
localparam op_dsm = 6'b000111;
localparam op_bwctrl = 6'b001000;
localparam op_cp_current = 6'b001001;
localparam op_som = 6'b111110;
localparam op_eom = 6'b111111;
localparam inval_setting = 6'b111100;
localparam mode_wr = 1'b0;
localparam mode_poll = 1'b1;
// total mif changeable settings = 8
// + total non-mif changeable settings = 2 (status, start)
// + startofmif, endofmif, invalid = 3
// = 13 total settings
localparam num_settings = 6'd13;
localparam num_mif_settings = 6'd10; // mode = 0.. cp_current=9
localparam log2num_settings = 6; // consistent with reconfig addr width
localparam num_c_counters = 5'd18;
localparam log2num_c_counters = 3'd5;
localparam num_dps_counters = 6'd32;
localparam log2num_dps_counters = 3'd6;
// reconfig module parameters
localparam waitrequest_mode = 1'b1;
// control flow registers
reg [state_reg_width-1:0] mif_curstate;
reg [state_reg_width-1:0] mif_nextstate;
wire is_done;
// internal data registers
reg [rom_addr_width-1:0] reg_mif_base_addr;
reg [log2num_settings-1:0] reg_instr;
reg [reconfig_data_width-1:0] reg_data;
reg [reconfig_data_width-1:0] settings_reg [num_mif_settings-1:0];
reg [reconfig_data_width-1:0] c_settings_reg [num_c_counters-1:0];
reg [reconfig_data_width-1:0] dps_settings_reg [num_dps_counters-1:0];
reg [4:0] c_cntr_index; // c cntr is data[22:18];
reg [4:0] dps_index; // dps is data[20:16];
reg [num_settings-1:0] is_setting_changed; // 1 bit per setting
reg [num_c_counters-1:0] is_c_cntr_changed;
reg [num_dps_counters-1:0] is_dps_changed;
reg user_mode_setting; // 0 for waitrequest mode, 1 for polling
reg mif_started;
reg saved_mode;
reg mode_reg;
reg [reconfig_addr_width-1:0] setting_number;
reg [log2num_c_counters-1:0] c_cntr_number;
reg [log2num_dps_counters-1:0] dps_number;
reg c_done;
reg dps_done;
reg is_mode_changed;
// rom interface
wire [rom_data_width-1:0] rom_q;
reg [rom_addr_width-1:0] rom_addr;
assign mif_busy = (is_done) ? 1'b0 : 1'b1;
// mif_started register
always @(posedge mif_clk)
begin
if (mif_curstate == mif_idle)
mif_started <= 0;
else if (reg_instr == op_som && mif_curstate == decode_rom_instr)
mif_started <= 1;
else
mif_started <= mif_started;
end
// is_done logic
assign is_done = (mif_curstate == mif_idle && mif_nextstate == mif_idle) ? 1'b1 : 1'b0;
// state register
always @(posedge mif_clk)
begin
if (mif_rst)
mif_curstate <= mif_idle;
else
mif_curstate <= mif_nextstate;
end
// next state logic
always @(*)
begin
case (mif_curstate)
mif_idle:
begin
if (mif_start)
mif_nextstate = set_instr_addr;
else
mif_nextstate = mif_idle;
end
// set address for instruction to be fetched from rom
set_instr_addr: // set_rom_info
begin
mif_nextstate = fetch_instr;
end
fetch_instr:
begin
mif_nextstate = wait_for_rom_instr;
end
wait_for_rom_instr:
begin
mif_nextstate = store_instr;
end
store_instr:
begin
mif_nextstate = decode_rom_instr;
end
decode_rom_instr:
begin
if (reg_instr == op_som)
mif_nextstate = set_instr_addr;
else if (reg_instr == op_eom)
mif_nextstate = set_mode_reg_info; // done reading mif, send it to reconfig module
else
mif_nextstate = set_data_addr;
end
set_data_addr:
begin
mif_nextstate = set_data_addr_dly;
end
set_data_addr_dly:
begin
mif_nextstate = fetch_data;
end
fetch_data:
begin
mif_nextstate = wait_for_rom_data;
end
wait_for_rom_data:
begin
mif_nextstate = store_data;
end
store_data:
begin
mif_nextstate = set_index;
end
set_index:
begin
mif_nextstate = change_settings_reg;
end
change_settings_reg:
begin
mif_nextstate = set_instr_addr; // loop back to read rest of mif file
end
// --- change reconfig registers --- //
// general steps for managing with reconfig module:
// 1) save user's configured mode register,
// 2) change mode to waitrequest mode,
// 3) send all settings that have changed to
// 4) start reconfig
// 5) wait till pll has locked again.
// 6) restore user's mode register
set_mode_reg_info:
begin
mif_nextstate = wait_mode_reg;
end
wait_mode_reg:
begin
mif_nextstate = save_mode_reg;
end
save_mode_reg:
begin
mif_nextstate = set_wr_mode;
end
set_wr_mode:
begin
mif_nextstate = wait_write_mode;
end
wait_write_mode:
begin
mif_nextstate = init_reconfig_params;
end
init_reconfig_params:
begin
mif_nextstate = check_reconfig_setting;
end
// parent loop (writing to reconfig)
check_reconfig_setting: // loop over changed settings until setting_num = 0 = mode
begin
// don't write the user's mode reg just yet
// stay in wr mode till we're done with reconfig ip
// then restore the user's old mode/the new mode
// they wrote in the mif
if (setting_number == 6'b0)
mif_nextstate = start_reconfig_change;
else
begin
if(is_setting_changed[setting_number])
// c and dps settings are different,
// since multiple can be reconfigured in
// one mif. if they are changed, check them all.
// in their respective loops
if (setting_number == op_c_counters)
begin
mif_nextstate = decrement_c_num;
end
else if (setting_number == op_dps)
begin
mif_nextstate = decrement_dps_num;
end
else
begin
mif_nextstate = write_reconfig_setting;
end
else
mif_nextstate = decrement_setting_num;
end
end
// c loop
// we need to check the 0th setting always (unlike the parent loop) so decrement first.
decrement_c_num:
begin
if (c_done)
begin
// done checking and writing c counters
// check next setting in parent loop
mif_nextstate = decrement_setting_num;
end
else
mif_nextstate = check_c_settings;
end
check_c_settings:
begin
if (is_c_cntr_changed[c_cntr_number])
mif_nextstate = write_c_settings;
else
mif_nextstate = decrement_c_num;
end
write_c_settings:
begin
mif_nextstate = decrement_c_num;
end
//end c loop
// dps loop
// same as c loop, decrement first.
decrement_dps_num:
begin
if (dps_done)
begin
// done checking and writing dps counters
// check next setting in parent loop
mif_nextstate = decrement_setting_num;
end
else
mif_nextstate = check_dps_settings; // check next dps setting
end
check_dps_settings:
begin
if(is_dps_changed[dps_number])
mif_nextstate = write_dps_settings;
else
mif_nextstate = decrement_dps_num;
end
write_dps_settings:
begin
mif_nextstate = decrement_dps_num;
end
//end dps loop
write_reconfig_setting:
begin
mif_nextstate = decrement_setting_num;
end
decrement_setting_num:
begin
mif_nextstate = check_reconfig_setting; // loop back
end
// --- done changing settings, start reconfig --- //
start_reconfig_change:
begin
mif_nextstate = start_reconfig_delay;
end
start_reconfig_delay:
begin
mif_nextstate = start_reconfig_delay2;
end
start_reconfig_delay2: // register at top level before we mux into reconfig
begin
mif_nextstate = wait_done_signal;
end
wait_done_signal:
begin
if (reconfig_busy)
mif_nextstate = wait_done_signal;
else
mif_nextstate = set_mode_reg;
end
set_mode_reg:
begin
mif_nextstate = write_final_mode;
end
write_final_mode:
begin
mif_nextstate = wait_final_mode;
end
wait_final_mode:
begin
mif_nextstate = mif_streaming_done;
end
mif_streaming_done:
begin
mif_nextstate = mif_idle;
end
default:
begin
mif_nextstate = mif_idle;
end
endcase
end
// data flow
reg [log2num_settings-1:0] i;
reg [log2num_c_counters-1:0] j;
reg [log2num_dps_counters-1:0] k;
always @(posedge mif_clk)
begin
if (mif_rst)
begin
reg_mif_base_addr <= 0;
is_setting_changed <= 0;
is_c_cntr_changed <= 0;
is_dps_changed <= 0;
rom_addr <= 0;
reg_instr <= 0;
reg_data <= 0;
for (i = 0; i < num_mif_settings; i = i + 1'b1)
begin
settings_reg [i] <= 0;
end
for (j = 0; j < num_c_counters; j = j + 1'b1)
begin
c_settings_reg [j] <= 0;
end
for (k = 0; k < num_dps_counters; k = k + 1'b1)
begin
dps_settings_reg [k] <= 0;
end
setting_number <= 0;
c_cntr_number <= 0;
dps_number <= 0;
c_done <= 0;
dps_done <= 0;
c_cntr_index <= 0;
dps_index <= 0;
reconfig_write_data <= 0;
reconfig_addr <= 0;
reconfig_write <= 0;
reconfig_read <= 0;
end
else
begin
case (mif_curstate)
mif_idle:
begin
reg_mif_base_addr <= mif_base_addr;
is_setting_changed <= 0;
is_c_cntr_changed <= 0;
is_dps_changed <= 0;
rom_addr <= 0;
reg_instr <= 0;
reg_data <= 0;
for (i = 0; i < num_mif_settings; i = i + 1'b1)
begin
settings_reg [i] <= 0;
end
for (j = 0; j < num_c_counters; j = j + 1'b1)
begin
c_settings_reg [j] <= 0;
end
for (k = 0; k < num_dps_counters; k = k + 1'b1)
begin
dps_settings_reg [k] <= 0;
end
setting_number <= 0;
c_cntr_number <= 0;
dps_number <= 0;
c_done <= 0;
dps_done <= 0;
c_cntr_index <= 0;
dps_index <= 0;
reconfig_write_data <= 0;
reconfig_addr <= 0;
reconfig_write <= 0;
reconfig_read <= 0;
end
// ----- rom flow ----- //
set_instr_addr: rom_addr <= (mif_started) ? rom_addr + 9'd1 : reg_mif_base_addr; // rom_addr_width = 9
fetch_instr: ;
wait_for_rom_instr: ;
store_instr: reg_instr <= rom_q [log2num_settings-1:0]; // only the last 6 bits are instr bits, rest is reserved
decode_rom_instr: ;
set_data_addr: rom_addr <= rom_addr + 9'd1; // rom_addr_width = 9
set_data_addr_dly: ;
fetch_data: ;
wait_for_rom_data: ;
store_data: reg_data <= rom_q; // data is 32 bits
set_index:
begin
c_cntr_index <= reg_data[22:18];
dps_index <= reg_data[20:16];
end
change_settings_reg:
begin
if (reg_instr == op_c_counters)
begin
c_settings_reg [c_cntr_index] <= reg_data; //22:18 is c cnt number
is_c_cntr_changed [c_cntr_index] <= 1'b1;
end
else if (reg_instr == op_dps)
begin
dps_settings_reg [dps_index] <= reg_data; //20:16 is dps number
is_dps_changed [dps_index] <= 1'b1;
end
else
begin
c_settings_reg [c_cntr_index] <= c_settings_reg [c_cntr_index];
is_c_cntr_changed [c_cntr_index] <= is_c_cntr_changed[c_cntr_index];
dps_settings_reg [dps_index] <= dps_settings_reg [dps_index];
is_dps_changed [dps_index] <= is_dps_changed [dps_index];
end
settings_reg [reg_instr] <= reg_data;
is_setting_changed [reg_instr] <= 1'b1;
end
// ---------- reconfig flow ---------- //
// reading/writing mode takes only one cycle
// (we don't know what mode its in initally)
set_mode_reg_info:
begin
reconfig_addr <= op_mode;
reconfig_read <= 1'b1;
reconfig_write <= 1'b0;
reconfig_write_data <= 0;
end
wait_mode_reg: reconfig_read <= 1'b0;
save_mode_reg: saved_mode <= reconfig_read_data[0];
set_wr_mode:
begin
reconfig_addr <= op_mode;
reconfig_write <= 1'b1;
reconfig_write_data[0] <= mode_wr; // want waitrequest mode while mif reader changes reconfig regs
end
wait_write_mode: reconfig_write <= 1'b0;
// done saving the mode reg, start writing the reconfig regs
// start with the highest setting and work our way down
init_reconfig_params:
begin
setting_number <= num_mif_settings - 6'd1;
c_cntr_number <= num_c_counters;
dps_number <= num_dps_counters;
end
check_reconfig_setting: ;
// c loop
decrement_c_num:
begin
c_cntr_number <= c_cntr_number - 5'd1;
reconfig_write <= 1'b0;
end
check_c_settings:
begin
if (c_cntr_number == 5'b0)
c_done <= 1'b1;
else
c_done <= c_done;
end
write_c_settings:
begin
reconfig_addr <= op_c_counters;
reconfig_write_data <= c_settings_reg[c_cntr_number];
reconfig_read <= 1'b0;
reconfig_write <= 1'b1;
end
//end c loop
// dps loop
decrement_dps_num:
begin
dps_number <= dps_number - 5'd1;
reconfig_write <= 1'b0;
end
check_dps_settings:
begin
if (dps_number == 5'b0)
dps_done <= 1'b1;
else
dps_done <= dps_done;
end
write_dps_settings:
begin
reconfig_addr <= op_dps;
reconfig_write_data <= dps_settings_reg[dps_number];
reconfig_read <= 1'b0;
reconfig_write <= 1'b1;
end
//end dps loop
write_reconfig_setting:
begin
reconfig_addr <= setting_number; // setting_number = op_code
reconfig_write_data <= settings_reg[setting_number];
reconfig_read <= 1'b0;
reconfig_write <= 1'b1;
end
decrement_setting_num:
begin
reconfig_write <= 1'b0;
setting_number <= setting_number - 6'd1; // decrement for looping back
end
// --- wrote all the changed settings to the reconfig ip except mode
// --- start the reconfig process (write to start reg) and wait for
// --- waitrequest signal to deassert
start_reconfig_change:
begin
reconfig_addr <= op_start;
reconfig_write_data <= 1;
reconfig_read <= 1'b0;
reconfig_write <= 1'b1;
end
start_reconfig_delay:
begin
reconfig_write <= 1'b0;
end
wait_done_signal: ;
// --- restore saved mode reg only if mode hasn't been changed by mif
set_mode_reg:
mode_reg <= (is_setting_changed[op_mode]) ? settings_reg [op_mode][0] : saved_mode;
write_final_mode:
begin
reconfig_addr <= op_mode;
reconfig_write_data[0] <= mode_reg;
reconfig_read <= 1'b0;
reconfig_write <= 1'b1;
end
wait_final_mode:
begin
reconfig_write <= 1'b0;
end
mif_streaming_done: ;
default : ;
endcase
end
end
// ram block
altsyncram altsyncram_component (
.address_a (rom_addr),
.clock0 (mif_clk),
.q_a (rom_q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "none",
altsyncram_component.clock_enable_input_a = "bypass",
altsyncram_component.clock_enable_output_a = "bypass",
altsyncram_component.init_file = mif_file_name,
altsyncram_component.intended_device_family = "stratix v",
altsyncram_component.lpm_hint = "enable_runtime_mod=no",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = rom_num_words,
altsyncram_component.operation_mode = "rom",
altsyncram_component.outdata_aclr_a = "none",
altsyncram_component.outdata_reg_a = "clock0",
altsyncram_component.widthad_a = rom_addr_width,
altsyncram_component.width_a = rom_data_width,
altsyncram_component.width_byteena_a = 1;
endmodule // mif_reader
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_csr_controller (
// To/From System
clock,
reset_n,
// To/From Avalon_MM csr slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_readdata,
// To/From Avalon_MM data slave interface
csr_status,
csr_control
);
parameter AVMM_CSR_DATA_WIDTH = 32;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
// To/From System
input clock;
input reset_n;
// To/From Avalon_MM csr slave interface
input avmm_read;
input avmm_write;
input avmm_addr;
input [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
output [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM data slave interface
input [9:0] csr_status;
output [31:0] csr_control;
reg [22:0] csr_sector_page_erase_addr_reg;
reg [4:0] csr_wp_mode;
reg [1:0] csr_erase_state;
reg csr_control_access;
reg reset_n_reg1;
reg reset_n_reg2;
wire reset_n_w;
wire is_idle;
wire is_erase_busy;
wire valid_csr_erase_addr;
wire valid_csr_write;
wire [31:0] csr_control_signal;
wire [22:0] csr_erase_addr;
assign is_idle = (csr_status[1:0] == STATUS_IDLE);
assign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
assign csr_erase_addr = avmm_writedata[22:0];
assign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
assign valid_csr_write = (avmm_write & avmm_addr);
assign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
assign csr_control = csr_control_signal;
assign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// Initiate register value for simulation. The initiate value can't be xx
initial begin
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode = {(5){1'b1}};
csr_erase_state = ERASE_ST_IDLE;
csr_control_access = 1'b0;
reset_n_reg1 = 1'b0;
reset_n_reg2 = 1'b0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Avalon_MM read/write
// -------------------------------------------------------------------
always @ (posedge clock) begin
// synchronous reset
if (~reset_n_w) begin
// reset all register
csr_sector_page_erase_addr_reg <= {(23){1'b1}};
csr_wp_mode <= {(5){1'b1}};
csr_erase_state <= ERASE_ST_IDLE;
csr_control_access <= 1'b0;
end
else begin
// store read address
if (avmm_read) begin
csr_control_access <= avmm_addr;
end
// write control register
if (valid_csr_write) begin
csr_wp_mode <= avmm_writedata[27:23];
if (is_idle) begin
csr_sector_page_erase_addr_reg <= avmm_writedata[22:0];
end
end
// erase control fsm
case (csr_erase_state)
ERASE_ST_IDLE:
if (is_idle && valid_csr_write && valid_csr_erase_addr) begin
csr_erase_state <= ERASE_ST_PENDING;
end
ERASE_ST_PENDING:
if (is_erase_busy) begin
csr_erase_state <= ERASE_ST_BUSY;
end
ERASE_ST_BUSY:
if (is_idle) begin
csr_erase_state <= ERASE_ST_IDLE;
end
default: begin
csr_erase_state <= ERASE_ST_IDLE;
end
endcase
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
module hi_us_12( // @[tage.scala:89:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:89:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:89:27]
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_avalon_sysid_qsys #(
parameter ID_VALUE = 1,
parameter TIMESTAMP = 1
)(
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? TIMESTAMP : ID_VALUE;
endmodule
|
// (c) 2001-2015 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module is used to create a reset from the clock locked signal. *
* *
******************************************************************************/
module altera_up_avalon_reset_from_locked_signal (
// inputs
locked,
// bidirectional
// outputs
reset
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input locked;
// bidirectionals
// outputs
output reset;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
// internal registers
// state machine registers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
// output registers
// internal registers
/*****************************************************************************
* combinational logic *
*****************************************************************************/
assign reset = ~locked;
/*****************************************************************************
* internal modules *
*****************************************************************************/
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
//legal notice: (c)2012 altera corporation. all rights reserved. your
//use of altera corporation's design tools, logic functions and other
//software and tools, and its ampp partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the altera program
//license subscription agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by altera and sold by altera
//or its authorized distributors. please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "unused";
parameter intended_device_family = "stratix v";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "clock0",
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "dual_port",
the_altsyncram.outdata_reg_b = "unregistered",
the_altsyncram.ram_block_type = "auto",
the_altsyncram.rdcontrol_reg_b = "clock0",
the_altsyncram.read_during_write_mode_mixed_ports = "dont_care",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5,
the_altsyncram.intended_device_family = intended_device_family;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "unused";
parameter intended_device_family = "stratix v";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "clock0",
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "dual_port",
the_altsyncram.outdata_reg_b = "unregistered",
the_altsyncram.ram_block_type = "auto",
the_altsyncram.rdcontrol_reg_b = "clock0",
the_altsyncram.read_during_write_mode_mixed_ports = "dont_care",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5,
the_altsyncram.intended_device_family = intended_device_family;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
no_ci_readra
)
;
output [ 19: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 16: 0] i_address;
output i_read;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire [ 1: 0] d_compare_op;
wire d_ctrl_alu_force_xor;
wire d_ctrl_alu_signed_comparison;
wire d_ctrl_alu_subtract;
wire d_ctrl_b_is_dst;
wire d_ctrl_br;
wire d_ctrl_br_cmp;
wire d_ctrl_br_uncond;
wire d_ctrl_break;
wire d_ctrl_crst;
wire d_ctrl_custom;
wire d_ctrl_custom_multi;
wire d_ctrl_exception;
wire d_ctrl_force_src2_zero;
wire d_ctrl_hi_imm16;
wire d_ctrl_ignore_dst;
wire d_ctrl_implicit_dst_eretaddr;
wire d_ctrl_implicit_dst_retaddr;
wire d_ctrl_jmp_direct;
wire d_ctrl_jmp_indirect;
wire d_ctrl_ld;
wire d_ctrl_ld_io;
wire d_ctrl_ld_non_io;
wire d_ctrl_ld_signed;
wire d_ctrl_logic;
wire d_ctrl_rdctl_inst;
wire d_ctrl_retaddr;
wire d_ctrl_rot_right;
wire d_ctrl_shift_logical;
wire d_ctrl_shift_right_arith;
wire d_ctrl_shift_rot;
wire d_ctrl_shift_rot_right;
wire d_ctrl_src2_choose_imm;
wire d_ctrl_st;
wire d_ctrl_uncond_cti_non_br;
wire d_ctrl_unsigned_lo_imm16;
wire d_ctrl_wrctl_inst;
wire [ 4: 0] d_dst_regnum;
wire [ 55: 0] d_inst;
reg [ 31: 0] d_iw /* synthesis altera_ip_debug_visible = 1 */;
wire [ 4: 0] d_iw_a;
wire [ 4: 0] d_iw_b;
wire [ 4: 0] d_iw_c;
wire [ 2: 0] d_iw_control_regnum;
wire [ 7: 0] d_iw_custom_n;
wire d_iw_custom_readra;
wire d_iw_custom_readrb;
wire d_iw_custom_writerc;
wire [ 15: 0] d_iw_imm16;
wire [ 25: 0] d_iw_imm26;
wire [ 4: 0] d_iw_imm5;
wire [ 1: 0] d_iw_memsz;
wire [ 5: 0] d_iw_op;
wire [ 5: 0] d_iw_opx;
wire [ 4: 0] d_iw_shift_imm5;
wire [ 4: 0] d_iw_trap_break_imm5;
wire [ 14: 0] d_jmp_direct_target_waddr;
wire [ 1: 0] d_logic_op;
wire [ 1: 0] d_logic_op_raw;
wire d_mem16;
wire d_mem32;
wire d_mem8;
wire d_op_add;
wire d_op_addi;
wire d_op_and;
wire d_op_andhi;
wire d_op_andi;
wire d_op_beq;
wire d_op_bge;
wire d_op_bgeu;
wire d_op_blt;
wire d_op_bltu;
wire d_op_bne;
wire d_op_br;
wire d_op_break;
wire d_op_bret;
wire d_op_call;
wire d_op_callr;
wire d_op_cmpeq;
wire d_op_cmpeqi;
wire d_op_cmpge;
wire d_op_cmpgei;
wire d_op_cmpgeu;
wire d_op_cmpgeui;
wire d_op_cmplt;
wire d_op_cmplti;
wire d_op_cmpltu;
wire d_op_cmpltui;
wire d_op_cmpne;
wire d_op_cmpnei;
wire d_op_crst;
wire d_op_custom;
wire d_op_div;
wire d_op_divu;
wire d_op_eret;
wire d_op_flushd;
wire d_op_flushda;
wire d_op_flushi;
wire d_op_flushp;
wire d_op_hbreak;
wire d_op_initd;
wire d_op_initda;
wire d_op_initi;
wire d_op_intr;
wire d_op_jmp;
wire d_op_jmpi;
wire d_op_ldb;
wire d_op_ldbio;
wire d_op_ldbu;
wire d_op_ldbuio;
wire d_op_ldh;
wire d_op_ldhio;
wire d_op_ldhu;
wire d_op_ldhuio;
wire d_op_ldl;
wire d_op_ldw;
wire d_op_ldwio;
wire d_op_mul;
wire d_op_muli;
wire d_op_mulxss;
wire d_op_mulxsu;
wire d_op_mulxuu;
wire d_op_nextpc;
wire d_op_nor;
wire d_op_opx;
wire d_op_or;
wire d_op_orhi;
wire d_op_ori;
wire d_op_rdctl;
wire d_op_rdprs;
wire d_op_ret;
wire d_op_rol;
wire d_op_roli;
wire d_op_ror;
wire d_op_rsv02;
wire d_op_rsv09;
wire d_op_rsv10;
wire d_op_rsv17;
wire d_op_rsv18;
wire d_op_rsv25;
wire d_op_rsv26;
wire d_op_rsv33;
wire d_op_rsv34;
wire d_op_rsv41;
wire d_op_rsv42;
wire d_op_rsv49;
wire d_op_rsv57;
wire d_op_rsv61;
wire d_op_rsv62;
wire d_op_rsv63;
wire d_op_rsvx00;
wire d_op_rsvx10;
wire d_op_rsvx15;
wire d_op_rsvx17;
wire d_op_rsvx21;
wire d_op_rsvx25;
wire d_op_rsvx33;
wire d_op_rsvx34;
wire d_op_rsvx35;
wire d_op_rsvx42;
wire d_op_rsvx43;
wire d_op_rsvx44;
wire d_op_rsvx47;
wire d_op_rsvx50;
wire d_op_rsvx51;
wire d_op_rsvx55;
wire d_op_rsvx56;
wire d_op_rsvx60;
wire d_op_rsvx63;
wire d_op_sll;
wire d_op_slli;
wire d_op_sra;
wire d_op_srai;
wire d_op_srl;
wire d_op_srli;
wire d_op_stb;
wire d_op_stbio;
wire d_op_stc;
wire d_op_sth;
wire d_op_sthio;
wire d_op_stw;
wire d_op_stwio;
wire d_op_sub;
wire d_op_sync;
wire d_op_trap;
wire d_op_wrctl;
wire d_op_wrprs;
wire d_op_xor;
wire d_op_xorhi;
wire d_op_xori;
reg d_valid;
wire [ 55: 0] d_vinst;
wire d_wr_dst_reg;
wire [ 31: 0] e_alu_result;
reg e_alu_sub;
wire [ 32: 0] e_arith_result;
wire [ 31: 0] e_arith_src1;
wire [ 31: 0] e_arith_src2;
wire e_ci_multi_stall;
wire [ 31: 0] e_ci_result;
wire e_cmp_result;
wire [ 31: 0] e_control_rd_data;
wire e_eq;
reg e_invert_arith_src_msb;
wire e_ld_stall;
wire [ 31: 0] e_logic_result;
wire e_logic_result_is_0;
wire e_lt;
wire [ 19: 0] e_mem_baddr;
wire [ 3: 0] e_mem_byte_en;
reg e_new_inst;
reg [ 4: 0] e_shift_rot_cnt;
wire [ 4: 0] e_shift_rot_cnt_nxt;
wire e_shift_rot_done;
wire e_shift_rot_fill_bit;
reg [ 31: 0] e_shift_rot_result;
wire [ 31: 0] e_shift_rot_result_nxt;
wire e_shift_rot_stall;
reg [ 31: 0] e_src1;
reg [ 31: 0] e_src2;
wire [ 31: 0] e_st_data;
wire e_st_stall;
wire e_stall;
reg e_valid;
wire [ 55: 0] e_vinst;
wire e_wrctl_bstatus;
wire e_wrctl_estatus;
wire e_wrctl_ienable;
wire e_wrctl_status;
wire [ 31: 0] f_av_iw;
wire [ 4: 0] f_av_iw_a;
wire [ 4: 0] f_av_iw_b;
wire [ 4: 0] f_av_iw_c;
wire [ 2: 0] f_av_iw_control_regnum;
wire [ 7: 0] f_av_iw_custom_n;
wire f_av_iw_custom_readra;
wire f_av_iw_custom_readrb;
wire f_av_iw_custom_writerc;
wire [ 15: 0] f_av_iw_imm16;
wire [ 25: 0] f_av_iw_imm26;
wire [ 4: 0] f_av_iw_imm5;
wire [ 1: 0] f_av_iw_memsz;
wire [ 5: 0] f_av_iw_op;
wire [ 5: 0] f_av_iw_opx;
wire [ 4: 0] f_av_iw_shift_imm5;
wire [ 4: 0] f_av_iw_trap_break_imm5;
wire f_av_mem16;
wire f_av_mem32;
wire f_av_mem8;
wire [ 55: 0] f_inst;
wire [ 31: 0] f_iw;
wire [ 4: 0] f_iw_a;
wire [ 4: 0] f_iw_b;
wire [ 4: 0] f_iw_c;
wire [ 2: 0] f_iw_control_regnum;
wire [ 7: 0] f_iw_custom_n;
wire f_iw_custom_readra;
wire f_iw_custom_readrb;
wire f_iw_custom_writerc;
wire [ 15: 0] f_iw_imm16;
wire [ 25: 0] f_iw_imm26;
wire [ 4: 0] f_iw_imm5;
wire [ 1: 0] f_iw_memsz;
wire [ 5: 0] f_iw_op;
wire [ 5: 0] f_iw_opx;
wire [ 4: 0] f_iw_shift_imm5;
wire [ 4: 0] f_iw_trap_break_imm5;
wire f_mem16;
wire f_mem32;
wire f_mem8;
wire f_op_add;
wire f_op_addi;
wire f_op_and;
wire f_op_andhi;
wire f_op_andi;
wire f_op_beq;
wire f_op_bge;
wire f_op_bgeu;
wire f_op_blt;
wire f_op_bltu;
wire f_op_bne;
wire f_op_br;
wire f_op_break;
wire f_op_bret;
wire f_op_call;
wire f_op_callr;
wire f_op_cmpeq;
wire f_op_cmpeqi;
wire f_op_cmpge;
wire f_op_cmpgei;
wire f_op_cmpgeu;
wire f_op_cmpgeui;
wire f_op_cmplt;
wire f_op_cmplti;
wire f_op_cmpltu;
wire f_op_cmpltui;
wire f_op_cmpne;
wire f_op_cmpnei;
wire f_op_crst;
wire f_op_custom;
wire f_op_div;
wire f_op_divu;
wire f_op_eret;
wire f_op_flushd;
wire f_op_flushda;
wire f_op_flushi;
wire f_op_flushp;
wire f_op_hbreak;
wire f_op_initd;
wire f_op_initda;
wire f_op_initi;
wire f_op_intr;
wire f_op_jmp;
wire f_op_jmpi;
wire f_op_ldb;
wire f_op_ldbio;
wire f_op_ldbu;
wire f_op_ldbuio;
wire f_op_ldh;
wire f_op_ldhio;
wire f_op_ldhu;
wire f_op_ldhuio;
wire f_op_ldl;
wire f_op_ldw;
wire f_op_ldwio;
wire f_op_mul;
wire f_op_muli;
wire f_op_mulxss;
wire f_op_mulxsu;
wire f_op_mulxuu;
wire f_op_nextpc;
wire f_op_nor;
wire f_op_opx;
wire f_op_or;
wire f_op_orhi;
wire f_op_ori;
wire f_op_rdctl;
wire f_op_rdprs;
wire f_op_ret;
wire f_op_rol;
wire f_op_roli;
wire f_op_ror;
wire f_op_rsv02;
wire f_op_rsv09;
wire f_op_rsv10;
wire f_op_rsv17;
wire f_op_rsv18;
wire f_op_rsv25;
wire f_op_rsv26;
wire f_op_rsv33;
wire f_op_rsv34;
wire f_op_rsv41;
wire f_op_rsv42;
wire f_op_rsv49;
wire f_op_rsv57;
wire f_op_rsv61;
wire f_op_rsv62;
wire f_op_rsv63;
wire f_op_rsvx00;
wire f_op_rsvx10;
wire f_op_rsvx15;
wire f_op_rsvx17;
wire f_op_rsvx21;
wire f_op_rsvx25;
wire f_op_rsvx33;
wire f_op_rsvx34;
wire f_op_rsvx35;
wire f_op_rsvx42;
wire f_op_rsvx43;
wire f_op_rsvx44;
wire f_op_rsvx47;
wire f_op_rsvx50;
wire f_op_rsvx51;
wire f_op_rsvx55;
wire f_op_rsvx56;
wire f_op_rsvx60;
wire f_op_rsvx63;
wire f_op_sll;
wire f_op_slli;
wire f_op_sra;
wire f_op_srai;
wire f_op_srl;
wire f_op_srli;
wire f_op_stb;
wire f_op_stbio;
wire f_op_stc;
wire f_op_sth;
wire f_op_sthio;
wire f_op_stw;
wire f_op_stwio;
wire f_op_sub;
wire f_op_sync;
wire f_op_trap;
wire f_op_wrctl;
wire f_op_wrprs;
wire f_op_xor;
wire f_op_xorhi;
wire f_op_xori;
reg [ 14: 0] f_pc /* synthesis altera_ip_debug_visible = 1 */;
wire f_pc_en;
wire [ 14: 0] f_pc_no_crst_nxt;
wire [ 14: 0] f_pc_nxt;
wire [ 14: 0] f_pc_plus_one;
wire [ 1: 0] f_pc_sel_nxt;
wire [ 16: 0] f_pcb;
wire [ 16: 0] f_pcb_nxt;
wire [ 16: 0] f_pcb_plus_four;
wire f_valid;
wire [ 55: 0] f_vinst;
reg [ 1: 0] r_compare_op;
reg r_ctrl_alu_force_xor;
wire r_ctrl_alu_force_xor_nxt;
reg r_ctrl_alu_signed_comparison;
wire r_ctrl_alu_signed_comparison_nxt;
reg r_ctrl_alu_subtract;
wire r_ctrl_alu_subtract_nxt;
reg r_ctrl_b_is_dst;
wire r_ctrl_b_is_dst_nxt;
reg r_ctrl_br;
reg r_ctrl_br_cmp;
wire r_ctrl_br_cmp_nxt;
wire r_ctrl_br_nxt;
reg r_ctrl_br_uncond;
wire r_ctrl_br_uncond_nxt;
reg r_ctrl_break;
wire r_ctrl_break_nxt;
reg r_ctrl_crst;
wire r_ctrl_crst_nxt;
reg r_ctrl_custom;
reg r_ctrl_custom_multi;
wire r_ctrl_custom_multi_nxt;
wire r_ctrl_custom_nxt;
reg r_ctrl_exception;
wire r_ctrl_exception_nxt;
reg r_ctrl_force_src2_zero;
wire r_ctrl_force_src2_zero_nxt;
reg r_ctrl_hi_imm16;
wire r_ctrl_hi_imm16_nxt;
reg r_ctrl_ignore_dst;
wire r_ctrl_ignore_dst_nxt;
reg r_ctrl_implicit_dst_eretaddr;
wire r_ctrl_implicit_dst_eretaddr_nxt;
reg r_ctrl_implicit_dst_retaddr;
wire r_ctrl_implicit_dst_retaddr_nxt;
reg r_ctrl_jmp_direct;
wire r_ctrl_jmp_direct_nxt;
reg r_ctrl_jmp_indirect;
wire r_ctrl_jmp_indirect_nxt;
reg r_ctrl_ld;
reg r_ctrl_ld_io;
wire r_ctrl_ld_io_nxt;
reg r_ctrl_ld_non_io;
wire r_ctrl_ld_non_io_nxt;
wire r_ctrl_ld_nxt;
reg r_ctrl_ld_signed;
wire r_ctrl_ld_signed_nxt;
reg r_ctrl_logic;
wire r_ctrl_logic_nxt;
reg r_ctrl_rdctl_inst;
wire r_ctrl_rdctl_inst_nxt;
reg r_ctrl_retaddr;
wire r_ctrl_retaddr_nxt;
reg r_ctrl_rot_right;
wire r_ctrl_rot_right_nxt;
reg r_ctrl_shift_logical;
wire r_ctrl_shift_logical_nxt;
reg r_ctrl_shift_right_arith;
wire r_ctrl_shift_right_arith_nxt;
reg r_ctrl_shift_rot;
wire r_ctrl_shift_rot_nxt;
reg r_ctrl_shift_rot_right;
wire r_ctrl_shift_rot_right_nxt;
reg r_ctrl_src2_choose_imm;
wire r_ctrl_src2_choose_imm_nxt;
reg r_ctrl_st;
wire r_ctrl_st_nxt;
reg r_ctrl_uncond_cti_non_br;
wire r_ctrl_uncond_cti_non_br_nxt;
reg r_ctrl_unsigned_lo_imm16;
wire r_ctrl_unsigned_lo_imm16_nxt;
reg r_ctrl_wrctl_inst;
wire r_ctrl_wrctl_inst_nxt;
reg [ 4: 0] r_dst_regnum /* synthesis altera_ip_debug_visible = 1 */;
wire r_en;
reg [ 1: 0] r_logic_op;
wire [ 31: 0] r_rf_a;
wire [ 31: 0] r_rf_b;
wire [ 31: 0] r_src1;
wire [ 31: 0] r_src2;
wire [ 15: 0] r_src2_hi;
wire [ 15: 0] r_src2_lo;
reg r_src2_use_imm;
wire [ 7: 0] r_stb_data;
wire [ 15: 0] r_sth_data;
reg r_valid;
wire [ 55: 0] r_vinst;
reg r_wr_dst_reg;
reg [ 31: 0] w_alu_result;
wire w_br_taken;
reg w_bstatus_reg;
wire w_bstatus_reg_inst_nxt;
wire w_bstatus_reg_nxt;
reg w_cmp_result;
reg [ 31: 0] w_control_rd_data;
reg w_estatus_reg;
wire w_estatus_reg_inst_nxt;
wire w_estatus_reg_nxt;
reg [ 31: 0] w_ienable_reg;
wire [ 31: 0] w_ienable_reg_nxt;
reg [ 31: 0] w_ipending_reg;
wire [ 31: 0] w_ipending_reg_nxt;
wire [ 19: 0] w_mem_baddr;
wire [ 31: 0] w_rf_wr_data;
wire w_rf_wren;
wire w_status_reg;
reg w_status_reg_pie;
wire w_status_reg_pie_inst_nxt;
wire w_status_reg_pie_nxt;
reg w_valid /* synthesis altera_ip_debug_visible = 1 */;
wire [ 55: 0] w_vinst;
wire [ 31: 0] w_wr_data;
wire [ 31: 0] w_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 19: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
wire hbreak_req;
wire [ 16: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire no_ci_readra;
wire [ 31: 0] oci_ienable;
wire test_has_ended;
parameter device_family = "cyclone v";
//the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench, which is an e_instance
altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench the_altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench
(
.d_iw (d_iw),
.d_iw_op (d_iw_op),
.d_iw_opx (d_iw_opx),
.d_valid (d_valid),
.e_alu_result (e_alu_result),
.e_mem_byte_en (e_mem_byte_en),
.e_st_data (e_st_data),
.e_valid (e_valid),
.f_pcb (f_pcb),
.f_valid (f_valid),
.r_ctrl_exception (r_ctrl_exception),
.r_ctrl_ld (r_ctrl_ld),
.r_ctrl_ld_non_io (r_ctrl_ld_non_io),
.r_dst_regnum (r_dst_regnum),
.r_wr_dst_reg (r_wr_dst_reg),
.w_bstatus_reg (w_bstatus_reg),
.w_cmp_result (w_cmp_result),
.w_estatus_reg (w_estatus_reg),
.w_ienable_reg (w_ienable_reg),
.w_ipending_reg (w_ipending_reg),
.w_mem_baddr (w_mem_baddr),
.w_rf_wr_data (w_rf_wr_data),
.w_status_reg (w_status_reg),
.w_valid (w_valid),
.w_vinst (w_vinst),
.w_wr_data (w_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign f_av_iw_a = f_av_iw[31 : 27];
assign f_av_iw_b = f_av_iw[26 : 22];
assign f_av_iw_c = f_av_iw[21 : 17];
assign f_av_iw_custom_n = f_av_iw[13 : 6];
assign f_av_iw_custom_readra = f_av_iw[16];
assign f_av_iw_custom_readrb = f_av_iw[15];
assign f_av_iw_custom_writerc = f_av_iw[14];
assign f_av_iw_opx = f_av_iw[16 : 11];
assign f_av_iw_op = f_av_iw[5 : 0];
assign f_av_iw_shift_imm5 = f_av_iw[10 : 6];
assign f_av_iw_trap_break_imm5 = f_av_iw[10 : 6];
assign f_av_iw_imm5 = f_av_iw[10 : 6];
assign f_av_iw_imm16 = f_av_iw[21 : 6];
assign f_av_iw_imm26 = f_av_iw[31 : 6];
assign f_av_iw_memsz = f_av_iw[4 : 3];
assign f_av_iw_control_regnum = f_av_iw[8 : 6];
assign f_av_mem8 = f_av_iw_memsz == 2'b00;
assign f_av_mem16 = f_av_iw_memsz == 2'b01;
assign f_av_mem32 = f_av_iw_memsz[1] == 1'b1;
assign f_iw_a = f_iw[31 : 27];
assign f_iw_b = f_iw[26 : 22];
assign f_iw_c = f_iw[21 : 17];
assign f_iw_custom_n = f_iw[13 : 6];
assign f_iw_custom_readra = f_iw[16];
assign f_iw_custom_readrb = f_iw[15];
assign f_iw_custom_writerc = f_iw[14];
assign f_iw_opx = f_iw[16 : 11];
assign f_iw_op = f_iw[5 : 0];
assign f_iw_shift_imm5 = f_iw[10 : 6];
assign f_iw_trap_break_imm5 = f_iw[10 : 6];
assign f_iw_imm5 = f_iw[10 : 6];
assign f_iw_imm16 = f_iw[21 : 6];
assign f_iw_imm26 = f_iw[31 : 6];
assign f_iw_memsz = f_iw[4 : 3];
assign f_iw_control_regnum = f_iw[8 : 6];
assign f_mem8 = f_iw_memsz == 2'b00;
assign f_mem16 = f_iw_memsz == 2'b01;
assign f_mem32 = f_iw_memsz[1] == 1'b1;
assign d_iw_a = d_iw[31 : 27];
assign d_iw_b = d_iw[26 : 22];
assign d_iw_c = d_iw[21 : 17];
assign d_iw_custom_n = d_iw[13 : 6];
assign d_iw_custom_readra = d_iw[16];
assign d_iw_custom_readrb = d_iw[15];
assign d_iw_custom_writerc = d_iw[14];
assign d_iw_opx = d_iw[16 : 11];
assign d_iw_op = d_iw[5 : 0];
assign d_iw_shift_imm5 = d_iw[10 : 6];
assign d_iw_trap_break_imm5 = d_iw[10 : 6];
assign d_iw_imm5 = d_iw[10 : 6];
assign d_iw_imm16 = d_iw[21 : 6];
assign d_iw_imm26 = d_iw[31 : 6];
assign d_iw_memsz = d_iw[4 : 3];
assign d_iw_control_regnum = d_iw[8 : 6];
assign d_mem8 = d_iw_memsz == 2'b00;
assign d_mem16 = d_iw_memsz == 2'b01;
assign d_mem32 = d_iw_memsz[1] == 1'b1;
assign f_op_call = f_iw_op == 0;
assign f_op_jmpi = f_iw_op == 1;
assign f_op_ldbu = f_iw_op == 3;
assign f_op_addi = f_iw_op == 4;
assign f_op_stb = f_iw_op == 5;
assign f_op_br = f_iw_op == 6;
assign f_op_ldb = f_iw_op == 7;
assign f_op_cmpgei = f_iw_op == 8;
assign f_op_ldhu = f_iw_op == 11;
assign f_op_andi = f_iw_op == 12;
assign f_op_sth = f_iw_op == 13;
assign f_op_bge = f_iw_op == 14;
assign f_op_ldh = f_iw_op == 15;
assign f_op_cmplti = f_iw_op == 16;
assign f_op_initda = f_iw_op == 19;
assign f_op_ori = f_iw_op == 20;
assign f_op_stw = f_iw_op == 21;
assign f_op_blt = f_iw_op == 22;
assign f_op_ldw = f_iw_op == 23;
assign f_op_cmpnei = f_iw_op == 24;
assign f_op_flushda = f_iw_op == 27;
assign f_op_xori = f_iw_op == 28;
assign f_op_stc = f_iw_op == 29;
assign f_op_bne = f_iw_op == 30;
assign f_op_ldl = f_iw_op == 31;
assign f_op_cmpeqi = f_iw_op == 32;
assign f_op_ldbuio = f_iw_op == 35;
assign f_op_muli = f_iw_op == 36;
assign f_op_stbio = f_iw_op == 37;
assign f_op_beq = f_iw_op == 38;
assign f_op_ldbio = f_iw_op == 39;
assign f_op_cmpgeui = f_iw_op == 40;
assign f_op_ldhuio = f_iw_op == 43;
assign f_op_andhi = f_iw_op == 44;
assign f_op_sthio = f_iw_op == 45;
assign f_op_bgeu = f_iw_op == 46;
assign f_op_ldhio = f_iw_op == 47;
assign f_op_cmpltui = f_iw_op == 48;
assign f_op_initd = f_iw_op == 51;
assign f_op_orhi = f_iw_op == 52;
assign f_op_stwio = f_iw_op == 53;
assign f_op_bltu = f_iw_op == 54;
assign f_op_ldwio = f_iw_op == 55;
assign f_op_rdprs = f_iw_op == 56;
assign f_op_flushd = f_iw_op == 59;
assign f_op_xorhi = f_iw_op == 60;
assign f_op_rsv02 = f_iw_op == 2;
assign f_op_rsv09 = f_iw_op == 9;
assign f_op_rsv10 = f_iw_op == 10;
assign f_op_rsv17 = f_iw_op == 17;
assign f_op_rsv18 = f_iw_op == 18;
assign f_op_rsv25 = f_iw_op == 25;
assign f_op_rsv26 = f_iw_op == 26;
assign f_op_rsv33 = f_iw_op == 33;
assign f_op_rsv34 = f_iw_op == 34;
assign f_op_rsv41 = f_iw_op == 41;
assign f_op_rsv42 = f_iw_op == 42;
assign f_op_rsv49 = f_iw_op == 49;
assign f_op_rsv57 = f_iw_op == 57;
assign f_op_rsv61 = f_iw_op == 61;
assign f_op_rsv62 = f_iw_op == 62;
assign f_op_rsv63 = f_iw_op == 63;
assign f_op_eret = f_op_opx & (f_iw_opx == 1);
assign f_op_roli = f_op_opx & (f_iw_opx == 2);
assign f_op_rol = f_op_opx & (f_iw_opx == 3);
assign f_op_flushp = f_op_opx & (f_iw_opx == 4);
assign f_op_ret = f_op_opx & (f_iw_opx == 5);
assign f_op_nor = f_op_opx & (f_iw_opx == 6);
assign f_op_mulxuu = f_op_opx & (f_iw_opx == 7);
assign f_op_cmpge = f_op_opx & (f_iw_opx == 8);
assign f_op_bret = f_op_opx & (f_iw_opx == 9);
assign f_op_ror = f_op_opx & (f_iw_opx == 11);
assign f_op_flushi = f_op_opx & (f_iw_opx == 12);
assign f_op_jmp = f_op_opx & (f_iw_opx == 13);
assign f_op_and = f_op_opx & (f_iw_opx == 14);
assign f_op_cmplt = f_op_opx & (f_iw_opx == 16);
assign f_op_slli = f_op_opx & (f_iw_opx == 18);
assign f_op_sll = f_op_opx & (f_iw_opx == 19);
assign f_op_wrprs = f_op_opx & (f_iw_opx == 20);
assign f_op_or = f_op_opx & (f_iw_opx == 22);
assign f_op_mulxsu = f_op_opx & (f_iw_opx == 23);
assign f_op_cmpne = f_op_opx & (f_iw_opx == 24);
assign f_op_srli = f_op_opx & (f_iw_opx == 26);
assign f_op_srl = f_op_opx & (f_iw_opx == 27);
assign f_op_nextpc = f_op_opx & (f_iw_opx == 28);
assign f_op_callr = f_op_opx & (f_iw_opx == 29);
assign f_op_xor = f_op_opx & (f_iw_opx == 30);
assign f_op_mulxss = f_op_opx & (f_iw_opx == 31);
assign f_op_cmpeq = f_op_opx & (f_iw_opx == 32);
assign f_op_divu = f_op_opx & (f_iw_opx == 36);
assign f_op_div = f_op_opx & (f_iw_opx == 37);
assign f_op_rdctl = f_op_opx & (f_iw_opx == 38);
assign f_op_mul = f_op_opx & (f_iw_opx == 39);
assign f_op_cmpgeu = f_op_opx & (f_iw_opx == 40);
assign f_op_initi = f_op_opx & (f_iw_opx == 41);
assign f_op_trap = f_op_opx & (f_iw_opx == 45);
assign f_op_wrctl = f_op_opx & (f_iw_opx == 46);
assign f_op_cmpltu = f_op_opx & (f_iw_opx == 48);
assign f_op_add = f_op_opx & (f_iw_opx == 49);
assign f_op_break = f_op_opx & (f_iw_opx == 52);
assign f_op_hbreak = f_op_opx & (f_iw_opx == 53);
assign f_op_sync = f_op_opx & (f_iw_opx == 54);
assign f_op_sub = f_op_opx & (f_iw_opx == 57);
assign f_op_srai = f_op_opx & (f_iw_opx == 58);
assign f_op_sra = f_op_opx & (f_iw_opx == 59);
assign f_op_intr = f_op_opx & (f_iw_opx == 61);
assign f_op_crst = f_op_opx & (f_iw_opx == 62);
assign f_op_rsvx00 = f_op_opx & (f_iw_opx == 0);
assign f_op_rsvx10 = f_op_opx & (f_iw_opx == 10);
assign f_op_rsvx15 = f_op_opx & (f_iw_opx == 15);
assign f_op_rsvx17 = f_op_opx & (f_iw_opx == 17);
assign f_op_rsvx21 = f_op_opx & (f_iw_opx == 21);
assign f_op_rsvx25 = f_op_opx & (f_iw_opx == 25);
assign f_op_rsvx33 = f_op_opx & (f_iw_opx == 33);
assign f_op_rsvx34 = f_op_opx & (f_iw_opx == 34);
assign f_op_rsvx35 = f_op_opx & (f_iw_opx == 35);
assign f_op_rsvx42 = f_op_opx & (f_iw_opx == 42);
assign f_op_rsvx43 = f_op_opx & (f_iw_opx == 43);
assign f_op_rsvx44 = f_op_opx & (f_iw_opx == 44);
assign f_op_rsvx47 = f_op_opx & (f_iw_opx == 47);
assign f_op_rsvx50 = f_op_opx & (f_iw_opx == 50);
assign f_op_rsvx51 = f_op_opx & (f_iw_opx == 51);
assign f_op_rsvx55 = f_op_opx & (f_iw_opx == 55);
assign f_op_rsvx56 = f_op_opx & (f_iw_opx == 56);
assign f_op_rsvx60 = f_op_opx & (f_iw_opx == 60);
assign f_op_rsvx63 = f_op_opx & (f_iw_opx == 63);
assign f_op_opx = f_iw_op == 58;
assign f_op_custom = f_iw_op == 50;
assign d_op_call = d_iw_op == 0;
assign d_op_jmpi = d_iw_op == 1;
assign d_op_ldbu = d_iw_op == 3;
assign d_op_addi = d_iw_op == 4;
assign d_op_stb = d_iw_op == 5;
assign d_op_br = d_iw_op == 6;
assign d_op_ldb = d_iw_op == 7;
assign d_op_cmpgei = d_iw_op == 8;
assign d_op_ldhu = d_iw_op == 11;
assign d_op_andi = d_iw_op == 12;
assign d_op_sth = d_iw_op == 13;
assign d_op_bge = d_iw_op == 14;
assign d_op_ldh = d_iw_op == 15;
assign d_op_cmplti = d_iw_op == 16;
assign d_op_initda = d_iw_op == 19;
assign d_op_ori = d_iw_op == 20;
assign d_op_stw = d_iw_op == 21;
assign d_op_blt = d_iw_op == 22;
assign d_op_ldw = d_iw_op == 23;
assign d_op_cmpnei = d_iw_op == 24;
assign d_op_flushda = d_iw_op == 27;
assign d_op_xori = d_iw_op == 28;
assign d_op_stc = d_iw_op == 29;
assign d_op_bne = d_iw_op == 30;
assign d_op_ldl = d_iw_op == 31;
assign d_op_cmpeqi = d_iw_op == 32;
assign d_op_ldbuio = d_iw_op == 35;
assign d_op_muli = d_iw_op == 36;
assign d_op_stbio = d_iw_op == 37;
assign d_op_beq = d_iw_op == 38;
assign d_op_ldbio = d_iw_op == 39;
assign d_op_cmpgeui = d_iw_op == 40;
assign d_op_ldhuio = d_iw_op == 43;
assign d_op_andhi = d_iw_op == 44;
assign d_op_sthio = d_iw_op == 45;
assign d_op_bgeu = d_iw_op == 46;
assign d_op_ldhio = d_iw_op == 47;
assign d_op_cmpltui = d_iw_op == 48;
assign d_op_initd = d_iw_op == 51;
assign d_op_orhi = d_iw_op == 52;
assign d_op_stwio = d_iw_op == 53;
assign d_op_bltu = d_iw_op == 54;
assign d_op_ldwio = d_iw_op == 55;
assign d_op_rdprs = d_iw_op == 56;
assign d_op_flushd = d_iw_op == 59;
assign d_op_xorhi = d_iw_op == 60;
assign d_op_rsv02 = d_iw_op == 2;
assign d_op_rsv09 = d_iw_op == 9;
assign d_op_rsv10 = d_iw_op == 10;
assign d_op_rsv17 = d_iw_op == 17;
assign d_op_rsv18 = d_iw_op == 18;
assign d_op_rsv25 = d_iw_op == 25;
assign d_op_rsv26 = d_iw_op == 26;
assign d_op_rsv33 = d_iw_op == 33;
assign d_op_rsv34 = d_iw_op == 34;
assign d_op_rsv41 = d_iw_op == 41;
assign d_op_rsv42 = d_iw_op == 42;
assign d_op_rsv49 = d_iw_op == 49;
assign d_op_rsv57 = d_iw_op == 57;
assign d_op_rsv61 = d_iw_op == 61;
assign d_op_rsv62 = d_iw_op == 62;
assign d_op_rsv63 = d_iw_op == 63;
assign d_op_eret = d_op_opx & (d_iw_opx == 1);
assign d_op_roli = d_op_opx & (d_iw_opx == 2);
assign d_op_rol = d_op_opx & (d_iw_opx == 3);
assign d_op_flushp = d_op_opx & (d_iw_opx == 4);
assign d_op_ret = d_op_opx & (d_iw_opx == 5);
assign d_op_nor = d_op_opx & (d_iw_opx == 6);
assign d_op_mulxuu = d_op_opx & (d_iw_opx == 7);
assign d_op_cmpge = d_op_opx & (d_iw_opx == 8);
assign d_op_bret = d_op_opx & (d_iw_opx == 9);
assign d_op_ror = d_op_opx & (d_iw_opx == 11);
assign d_op_flushi = d_op_opx & (d_iw_opx == 12);
assign d_op_jmp = d_op_opx & (d_iw_opx == 13);
assign d_op_and = d_op_opx & (d_iw_opx == 14);
assign d_op_cmplt = d_op_opx & (d_iw_opx == 16);
assign d_op_slli = d_op_opx & (d_iw_opx == 18);
assign d_op_sll = d_op_opx & (d_iw_opx == 19);
assign d_op_wrprs = d_op_opx & (d_iw_opx == 20);
assign d_op_or = d_op_opx & (d_iw_opx == 22);
assign d_op_mulxsu = d_op_opx & (d_iw_opx == 23);
assign d_op_cmpne = d_op_opx & (d_iw_opx == 24);
assign d_op_srli = d_op_opx & (d_iw_opx == 26);
assign d_op_srl = d_op_opx & (d_iw_opx == 27);
assign d_op_nextpc = d_op_opx & (d_iw_opx == 28);
assign d_op_callr = d_op_opx & (d_iw_opx == 29);
assign d_op_xor = d_op_opx & (d_iw_opx == 30);
assign d_op_mulxss = d_op_opx & (d_iw_opx == 31);
assign d_op_cmpeq = d_op_opx & (d_iw_opx == 32);
assign d_op_divu = d_op_opx & (d_iw_opx == 36);
assign d_op_div = d_op_opx & (d_iw_opx == 37);
assign d_op_rdctl = d_op_opx & (d_iw_opx == 38);
assign d_op_mul = d_op_opx & (d_iw_opx == 39);
assign d_op_cmpgeu = d_op_opx & (d_iw_opx == 40);
assign d_op_initi = d_op_opx & (d_iw_opx == 41);
assign d_op_trap = d_op_opx & (d_iw_opx == 45);
assign d_op_wrctl = d_op_opx & (d_iw_opx == 46);
assign d_op_cmpltu = d_op_opx & (d_iw_opx == 48);
assign d_op_add = d_op_opx & (d_iw_opx == 49);
assign d_op_break = d_op_opx & (d_iw_opx == 52);
assign d_op_hbreak = d_op_opx & (d_iw_opx == 53);
assign d_op_sync = d_op_opx & (d_iw_opx == 54);
assign d_op_sub = d_op_opx & (d_iw_opx == 57);
assign d_op_srai = d_op_opx & (d_iw_opx == 58);
assign d_op_sra = d_op_opx & (d_iw_opx == 59);
assign d_op_intr = d_op_opx & (d_iw_opx == 61);
assign d_op_crst = d_op_opx & (d_iw_opx == 62);
assign d_op_rsvx00 = d_op_opx & (d_iw_opx == 0);
assign d_op_rsvx10 = d_op_opx & (d_iw_opx == 10);
assign d_op_rsvx15 = d_op_opx & (d_iw_opx == 15);
assign d_op_rsvx17 = d_op_opx & (d_iw_opx == 17);
assign d_op_rsvx21 = d_op_opx & (d_iw_opx == 21);
assign d_op_rsvx25 = d_op_opx & (d_iw_opx == 25);
assign d_op_rsvx33 = d_op_opx & (d_iw_opx == 33);
assign d_op_rsvx34 = d_op_opx & (d_iw_opx == 34);
assign d_op_rsvx35 = d_op_opx & (d_iw_opx == 35);
assign d_op_rsvx42 = d_op_opx & (d_iw_opx == 42);
assign d_op_rsvx43 = d_op_opx & (d_iw_opx == 43);
assign d_op_rsvx44 = d_op_opx & (d_iw_opx == 44);
assign d_op_rsvx47 = d_op_opx & (d_iw_opx == 47);
assign d_op_rsvx50 = d_op_opx & (d_iw_opx == 50);
assign d_op_rsvx51 = d_op_opx & (d_iw_opx == 51);
assign d_op_rsvx55 = d_op_opx & (d_iw_opx == 55);
assign d_op_rsvx56 = d_op_opx & (d_iw_opx == 56);
assign d_op_rsvx60 = d_op_opx & (d_iw_opx == 60);
assign d_op_rsvx63 = d_op_opx & (d_iw_opx == 63);
assign d_op_opx = d_iw_op == 58;
assign d_op_custom = d_iw_op == 50;
assign r_en = 1'b1;
assign e_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign e_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000000;
assign f_pc_sel_nxt = r_ctrl_exception ? 2'b00 :
r_ctrl_break ? 2'b01 :
(w_br_taken | r_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign f_pc_no_crst_nxt = (f_pc_sel_nxt == 2'b00)? 16392 :
(f_pc_sel_nxt == 2'b01)? 16392 :
(f_pc_sel_nxt == 2'b10)? e_arith_result[16 : 2] :
f_pc_plus_one;
assign f_pc_nxt = f_pc_no_crst_nxt;
assign f_pcb_nxt = {f_pc_nxt, 2'b00};
assign f_pc_en = w_valid;
assign f_pc_plus_one = f_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
f_pc <= 16384;
else if (f_pc_en)
f_pc <= f_pc_nxt;
end
assign f_pcb = {f_pc, 2'b00};
assign f_pcb_plus_four = {f_pc_plus_one, 2'b00};
assign f_valid = i_read & ~i_waitrequest;
assign i_read_nxt = w_valid | (i_read & i_waitrequest);
assign i_address = {f_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign hbreak_req = 1'b0;
assign intr_req = w_status_reg_pie & (w_ipending_reg != 0);
assign f_av_iw = i_readdata;
assign f_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
f_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_iw <= 0;
else if (f_valid)
d_iw <= f_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_valid <= 0;
else
d_valid <= f_valid;
end
assign d_dst_regnum = d_ctrl_implicit_dst_retaddr ? 5'd31 :
d_ctrl_implicit_dst_eretaddr ? 5'd29 :
d_ctrl_b_is_dst ? d_iw_b :
d_iw_c;
assign d_wr_dst_reg = (d_dst_regnum != 0) & ~d_ctrl_ignore_dst;
assign d_logic_op_raw = d_op_opx ? d_iw_opx[4 : 3] :
d_iw_op[4 : 3];
assign d_logic_op = d_ctrl_alu_force_xor ? 2'b11 : d_logic_op_raw;
assign d_compare_op = d_op_opx ? d_iw_opx[4 : 3] :
d_iw_op[4 : 3];
assign d_jmp_direct_target_waddr = d_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_valid <= 0;
else
r_valid <= d_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_wr_dst_reg <= 0;
else
r_wr_dst_reg <= d_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_dst_regnum <= 0;
else
r_dst_regnum <= d_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_logic_op <= 0;
else
r_logic_op <= d_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_compare_op <= 0;
else
r_compare_op <= d_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_src2_use_imm <= 0;
else
r_src2_use_imm <= d_ctrl_src2_choose_imm | (d_ctrl_br & r_valid);
end
assign w_rf_wren = (r_wr_dst_reg & w_valid) | ~reset_n;
assign w_rf_wr_data = r_ctrl_ld ? av_ld_data_aligned_filtered : w_wr_data;
//altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a, which is an nios_sdp_ram
altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a_module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a
(
.clock (clk),
.data (w_rf_wr_data),
.q (r_rf_a),
.rdaddress (d_iw_a),
.wraddress (r_dst_regnum),
.wren (w_rf_wren)
);
//synthesis translate_off
`ifdef no_pli
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.dat";
`else
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_hdl on
//defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_a.mif";
//synthesis read_comments_as_hdl off
//altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b, which is an nios_sdp_ram
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_a.intended_device_family = device_family;
altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b_module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b
(
.clock (clk),
.data (w_rf_wr_data),
.q (r_rf_b),
.rdaddress (d_iw_b),
.wraddress (r_dst_regnum),
.wren (w_rf_wren)
);
//synthesis translate_off
`ifdef no_pli
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.dat";
`else
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_hdl on
//defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_rf_ram_b.mif";
//synthesis read_comments_as_hdl off
defparam altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_register_bank_b.intended_device_family = device_family;
assign r_src1 = (((r_ctrl_br & e_valid) | (r_ctrl_retaddr & r_valid)))? {f_pc_plus_one, 2'b00} :
((r_ctrl_jmp_direct & e_valid))? {d_jmp_direct_target_waddr, 2'b00} :
r_rf_a;
assign r_src2_lo = ((r_ctrl_force_src2_zero|r_ctrl_hi_imm16))? 16'b0 :
(r_src2_use_imm)? d_iw_imm16 :
r_rf_b[15 : 0];
assign r_src2_hi = ((r_ctrl_force_src2_zero|r_ctrl_unsigned_lo_imm16))? 16'b0 :
(r_ctrl_hi_imm16)? d_iw_imm16 :
(r_src2_use_imm)? {16 {d_iw_imm16[15]}} :
r_rf_b[31 : 16];
assign r_src2 = {r_src2_hi, r_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_valid <= 0;
else
e_valid <= r_valid | e_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_new_inst <= 0;
else
e_new_inst <= r_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_src1 <= 0;
else
e_src1 <= r_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_src2 <= 0;
else
e_src2 <= r_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_invert_arith_src_msb <= 0;
else
e_invert_arith_src_msb <= d_ctrl_alu_signed_comparison & r_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_alu_sub <= 0;
else
e_alu_sub <= d_ctrl_alu_subtract & r_valid;
end
assign e_stall = e_shift_rot_stall | e_ld_stall | e_st_stall | e_ci_multi_stall;
assign e_arith_src1 = { e_src1[31] ^ e_invert_arith_src_msb,
e_src1[30 : 0]};
assign e_arith_src2 = { e_src2[31] ^ e_invert_arith_src_msb,
e_src2[30 : 0]};
assign e_arith_result = e_alu_sub ?
e_arith_src1 - e_arith_src2 :
e_arith_src1 + e_arith_src2;
assign e_mem_baddr = e_arith_result[19 : 0];
assign e_logic_result = (r_logic_op == 2'b00)? (~(e_src1 | e_src2)) :
(r_logic_op == 2'b01)? (e_src1 & e_src2) :
(r_logic_op == 2'b10)? (e_src1 | e_src2) :
(e_src1 ^ e_src2);
assign e_logic_result_is_0 = e_logic_result == 0;
assign e_eq = e_logic_result_is_0;
assign e_lt = e_arith_result[32];
assign e_cmp_result = (r_compare_op == 2'b00)? e_eq :
(r_compare_op == 2'b01)? ~e_lt :
(r_compare_op == 2'b10)? e_lt :
~e_eq;
assign e_shift_rot_cnt_nxt = e_new_inst ? e_src2[4 : 0] : e_shift_rot_cnt-1;
assign e_shift_rot_done = (e_shift_rot_cnt == 0) & ~e_new_inst;
assign e_shift_rot_stall = r_ctrl_shift_rot & e_valid & ~e_shift_rot_done;
assign e_shift_rot_fill_bit = r_ctrl_shift_logical ? 1'b0 :
(r_ctrl_rot_right ? e_shift_rot_result[0] :
e_shift_rot_result[31]);
assign e_shift_rot_result_nxt = (e_new_inst)? e_src1 :
(r_ctrl_shift_rot_right)? {e_shift_rot_fill_bit, e_shift_rot_result[31 : 1]} :
{e_shift_rot_result[30 : 0], e_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_shift_rot_result <= 0;
else
e_shift_rot_result <= e_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
e_shift_rot_cnt <= 0;
else
e_shift_rot_cnt <= e_shift_rot_cnt_nxt;
end
assign e_control_rd_data = (d_iw_control_regnum == 3'd0)? w_status_reg :
(d_iw_control_regnum == 3'd1)? w_estatus_reg :
(d_iw_control_regnum == 3'd2)? w_bstatus_reg :
(d_iw_control_regnum == 3'd3)? w_ienable_reg :
(d_iw_control_regnum == 3'd4)? w_ipending_reg :
0;
assign e_alu_result = ((r_ctrl_br_cmp | r_ctrl_rdctl_inst))? 0 :
(r_ctrl_shift_rot)? e_shift_rot_result :
(r_ctrl_logic)? e_logic_result :
(r_ctrl_custom)? e_ci_result :
e_arith_result;
assign r_stb_data = r_rf_b[7 : 0];
assign r_sth_data = r_rf_b[15 : 0];
assign e_st_data = (d_mem8)? {r_stb_data, r_stb_data, r_stb_data, r_stb_data} :
(d_mem16)? {r_sth_data, r_sth_data} :
r_rf_b;
assign e_mem_byte_en = ({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({d_iw_memsz, e_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (r_ctrl_ld & e_new_inst) | (d_read & d_waitrequest);
assign e_ld_stall = r_ctrl_ld & ((e_valid & ~av_ld_done) | e_new_inst);
assign d_write_nxt = (r_ctrl_st & e_new_inst) | (d_write & d_waitrequest);
assign e_st_stall = d_write_nxt;
assign d_address = w_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= e_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= e_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (d_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~d_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(r_ctrl_ld & e_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (d_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (w_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & d_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = d_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & r_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_valid <= 0;
else
w_valid <= e_valid & ~e_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_control_rd_data <= 0;
else
w_control_rd_data <= e_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_cmp_result <= 0;
else
w_cmp_result <= e_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_alu_result <= 0;
else
w_alu_result <= e_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_status_reg_pie <= 0;
else
w_status_reg_pie <= w_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_estatus_reg <= 0;
else
w_estatus_reg <= w_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_bstatus_reg <= 0;
else
w_bstatus_reg <= w_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_ienable_reg <= 0;
else
w_ienable_reg <= w_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
w_ipending_reg <= 0;
else
w_ipending_reg <= w_ipending_reg_nxt;
end
assign w_wr_data_non_zero = r_ctrl_br_cmp ? w_cmp_result :
r_ctrl_rdctl_inst ? w_control_rd_data :
w_alu_result[31 : 0];
assign w_wr_data = w_wr_data_non_zero;
assign w_br_taken = r_ctrl_br & w_cmp_result;
assign w_mem_baddr = w_alu_result[19 : 0];
assign w_status_reg = w_status_reg_pie;
assign e_wrctl_status = r_ctrl_wrctl_inst &
(d_iw_control_regnum == 3'd0);
assign e_wrctl_estatus = r_ctrl_wrctl_inst &
(d_iw_control_regnum == 3'd1);
assign e_wrctl_bstatus = r_ctrl_wrctl_inst &
(d_iw_control_regnum == 3'd2);
assign e_wrctl_ienable = r_ctrl_wrctl_inst &
(d_iw_control_regnum == 3'd3);
assign w_status_reg_pie_inst_nxt = (r_ctrl_exception | r_ctrl_break | r_ctrl_crst) ? 1'b0 :
(d_op_eret) ? w_estatus_reg :
(d_op_bret) ? w_bstatus_reg :
(e_wrctl_status) ? e_src1[0] :
w_status_reg_pie;
assign w_status_reg_pie_nxt = e_valid ? w_status_reg_pie_inst_nxt : w_status_reg_pie;
assign w_estatus_reg_inst_nxt = (r_ctrl_crst) ? 0 :
(r_ctrl_exception) ? w_status_reg :
(e_wrctl_estatus) ? e_src1[0] :
w_estatus_reg;
assign w_estatus_reg_nxt = e_valid ? w_estatus_reg_inst_nxt : w_estatus_reg;
assign w_bstatus_reg_inst_nxt = (r_ctrl_break) ? w_status_reg :
(e_wrctl_bstatus) ? e_src1[0] :
w_bstatus_reg;
assign w_bstatus_reg_nxt = e_valid ? w_bstatus_reg_inst_nxt : w_bstatus_reg;
assign w_ienable_reg_nxt = ((e_wrctl_ienable & e_valid) ?
e_src1[31 : 0] : w_ienable_reg) & 32'b00000000000000000000000000000000;
assign w_ipending_reg_nxt = iactive & w_ienable_reg & oci_ienable & 32'b00000000000000000000000000000000;
assign oci_ienable = {32{1'b1}};
assign d_ctrl_custom = 1'b0;
assign r_ctrl_custom_nxt = d_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_custom <= 0;
else if (r_en)
r_ctrl_custom <= r_ctrl_custom_nxt;
end
assign d_ctrl_custom_multi = 1'b0;
assign r_ctrl_custom_multi_nxt = d_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_custom_multi <= 0;
else if (r_en)
r_ctrl_custom_multi <= r_ctrl_custom_multi_nxt;
end
assign d_ctrl_jmp_indirect = d_op_eret|
d_op_bret|
d_op_rsvx17|
d_op_rsvx25|
d_op_ret|
d_op_jmp|
d_op_rsvx21|
d_op_callr;
assign r_ctrl_jmp_indirect_nxt = d_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_jmp_indirect <= 0;
else if (r_en)
r_ctrl_jmp_indirect <= r_ctrl_jmp_indirect_nxt;
end
assign d_ctrl_jmp_direct = d_op_call|d_op_jmpi;
assign r_ctrl_jmp_direct_nxt = d_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_jmp_direct <= 0;
else if (r_en)
r_ctrl_jmp_direct <= r_ctrl_jmp_direct_nxt;
end
assign d_ctrl_implicit_dst_retaddr = d_op_call|d_op_rsv02;
assign r_ctrl_implicit_dst_retaddr_nxt = d_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_implicit_dst_retaddr <= 0;
else if (r_en)
r_ctrl_implicit_dst_retaddr <= r_ctrl_implicit_dst_retaddr_nxt;
end
assign d_ctrl_implicit_dst_eretaddr = d_op_div|d_op_divu|d_op_mul|d_op_muli|d_op_mulxss|d_op_mulxsu|d_op_mulxuu;
assign r_ctrl_implicit_dst_eretaddr_nxt = d_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_implicit_dst_eretaddr <= 0;
else if (r_en)
r_ctrl_implicit_dst_eretaddr <= r_ctrl_implicit_dst_eretaddr_nxt;
end
assign d_ctrl_exception = d_op_trap|
d_op_rsvx44|
d_op_div|
d_op_divu|
d_op_mul|
d_op_muli|
d_op_mulxss|
d_op_mulxsu|
d_op_mulxuu|
d_op_intr|
d_op_rsvx60;
assign r_ctrl_exception_nxt = d_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_exception <= 0;
else if (r_en)
r_ctrl_exception <= r_ctrl_exception_nxt;
end
assign d_ctrl_break = d_op_break|d_op_hbreak;
assign r_ctrl_break_nxt = d_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_break <= 0;
else if (r_en)
r_ctrl_break <= r_ctrl_break_nxt;
end
assign d_ctrl_crst = d_op_crst|d_op_rsvx63;
assign r_ctrl_crst_nxt = d_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_crst <= 0;
else if (r_en)
r_ctrl_crst <= r_ctrl_crst_nxt;
end
assign d_ctrl_uncond_cti_non_br = d_op_call|
d_op_jmpi|
d_op_eret|
d_op_bret|
d_op_rsvx17|
d_op_rsvx25|
d_op_ret|
d_op_jmp|
d_op_rsvx21|
d_op_callr;
assign r_ctrl_uncond_cti_non_br_nxt = d_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_uncond_cti_non_br <= 0;
else if (r_en)
r_ctrl_uncond_cti_non_br <= r_ctrl_uncond_cti_non_br_nxt;
end
assign d_ctrl_retaddr = d_op_call|
d_op_rsv02|
d_op_nextpc|
d_op_callr|
d_op_trap|
d_op_rsvx44|
d_op_div|
d_op_divu|
d_op_mul|
d_op_muli|
d_op_mulxss|
d_op_mulxsu|
d_op_mulxuu|
d_op_intr|
d_op_rsvx60|
d_op_break|
d_op_hbreak;
assign r_ctrl_retaddr_nxt = d_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_retaddr <= 0;
else if (r_en)
r_ctrl_retaddr <= r_ctrl_retaddr_nxt;
end
assign d_ctrl_shift_logical = d_op_slli|d_op_sll|d_op_srli|d_op_srl;
assign r_ctrl_shift_logical_nxt = d_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_shift_logical <= 0;
else if (r_en)
r_ctrl_shift_logical <= r_ctrl_shift_logical_nxt;
end
assign d_ctrl_shift_right_arith = d_op_srai|d_op_sra;
assign r_ctrl_shift_right_arith_nxt = d_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_shift_right_arith <= 0;
else if (r_en)
r_ctrl_shift_right_arith <= r_ctrl_shift_right_arith_nxt;
end
assign d_ctrl_rot_right = d_op_rsvx10|d_op_ror|d_op_rsvx42|d_op_rsvx43;
assign r_ctrl_rot_right_nxt = d_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_rot_right <= 0;
else if (r_en)
r_ctrl_rot_right <= r_ctrl_rot_right_nxt;
end
assign d_ctrl_shift_rot_right = d_op_srli|
d_op_srl|
d_op_srai|
d_op_sra|
d_op_rsvx10|
d_op_ror|
d_op_rsvx42|
d_op_rsvx43;
assign r_ctrl_shift_rot_right_nxt = d_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_shift_rot_right <= 0;
else if (r_en)
r_ctrl_shift_rot_right <= r_ctrl_shift_rot_right_nxt;
end
assign d_ctrl_shift_rot = d_op_slli|
d_op_rsvx50|
d_op_sll|
d_op_rsvx51|
d_op_roli|
d_op_rsvx34|
d_op_rol|
d_op_rsvx35|
d_op_srli|
d_op_srl|
d_op_srai|
d_op_sra|
d_op_rsvx10|
d_op_ror|
d_op_rsvx42|
d_op_rsvx43;
assign r_ctrl_shift_rot_nxt = d_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_shift_rot <= 0;
else if (r_en)
r_ctrl_shift_rot <= r_ctrl_shift_rot_nxt;
end
assign d_ctrl_logic = d_op_and|
d_op_or|
d_op_xor|
d_op_nor|
d_op_andhi|
d_op_orhi|
d_op_xorhi|
d_op_andi|
d_op_ori|
d_op_xori;
assign r_ctrl_logic_nxt = d_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_logic <= 0;
else if (r_en)
r_ctrl_logic <= r_ctrl_logic_nxt;
end
assign d_ctrl_hi_imm16 = d_op_andhi|d_op_orhi|d_op_xorhi;
assign r_ctrl_hi_imm16_nxt = d_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_hi_imm16 <= 0;
else if (r_en)
r_ctrl_hi_imm16 <= r_ctrl_hi_imm16_nxt;
end
assign d_ctrl_unsigned_lo_imm16 = d_op_cmpgeui|
d_op_cmpltui|
d_op_andi|
d_op_ori|
d_op_xori|
d_op_roli|
d_op_rsvx10|
d_op_slli|
d_op_srli|
d_op_rsvx34|
d_op_rsvx42|
d_op_rsvx50|
d_op_srai;
assign r_ctrl_unsigned_lo_imm16_nxt = d_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_unsigned_lo_imm16 <= 0;
else if (r_en)
r_ctrl_unsigned_lo_imm16 <= r_ctrl_unsigned_lo_imm16_nxt;
end
assign d_ctrl_br_uncond = d_op_br|d_op_rsv02;
assign r_ctrl_br_uncond_nxt = d_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_br_uncond <= 0;
else if (r_en)
r_ctrl_br_uncond <= r_ctrl_br_uncond_nxt;
end
assign d_ctrl_br = d_op_br|
d_op_bge|
d_op_blt|
d_op_bne|
d_op_beq|
d_op_bgeu|
d_op_bltu|
d_op_rsv62;
assign r_ctrl_br_nxt = d_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_br <= 0;
else if (r_en)
r_ctrl_br <= r_ctrl_br_nxt;
end
assign d_ctrl_alu_subtract = d_op_sub|
d_op_rsvx25|
d_op_cmplti|
d_op_cmpltui|
d_op_cmplt|
d_op_cmpltu|
d_op_blt|
d_op_bltu|
d_op_cmpgei|
d_op_cmpgeui|
d_op_cmpge|
d_op_cmpgeu|
d_op_bge|
d_op_rsv10|
d_op_bgeu|
d_op_rsv42;
assign r_ctrl_alu_subtract_nxt = d_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_alu_subtract <= 0;
else if (r_en)
r_ctrl_alu_subtract <= r_ctrl_alu_subtract_nxt;
end
assign d_ctrl_alu_signed_comparison = d_op_cmpge|d_op_cmpgei|d_op_cmplt|d_op_cmplti|d_op_bge|d_op_blt;
assign r_ctrl_alu_signed_comparison_nxt = d_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_alu_signed_comparison <= 0;
else if (r_en)
r_ctrl_alu_signed_comparison <= r_ctrl_alu_signed_comparison_nxt;
end
assign d_ctrl_br_cmp = d_op_br|
d_op_bge|
d_op_blt|
d_op_bne|
d_op_beq|
d_op_bgeu|
d_op_bltu|
d_op_rsv62|
d_op_cmpgei|
d_op_cmplti|
d_op_cmpnei|
d_op_cmpgeui|
d_op_cmpltui|
d_op_cmpeqi|
d_op_rsvx00|
d_op_cmpge|
d_op_cmplt|
d_op_cmpne|
d_op_cmpgeu|
d_op_cmpltu|
d_op_cmpeq|
d_op_rsvx56;
assign r_ctrl_br_cmp_nxt = d_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_br_cmp <= 0;
else if (r_en)
r_ctrl_br_cmp <= r_ctrl_br_cmp_nxt;
end
assign d_ctrl_ld_signed = d_op_ldb|
d_op_ldh|
d_op_ldl|
d_op_ldw|
d_op_ldbio|
d_op_ldhio|
d_op_ldwio|
d_op_rsv63;
assign r_ctrl_ld_signed_nxt = d_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_ld_signed <= 0;
else if (r_en)
r_ctrl_ld_signed <= r_ctrl_ld_signed_nxt;
end
assign d_ctrl_ld = d_op_ldb|
d_op_ldh|
d_op_ldl|
d_op_ldw|
d_op_ldbio|
d_op_ldhio|
d_op_ldwio|
d_op_rsv63|
d_op_ldbu|
d_op_ldhu|
d_op_ldbuio|
d_op_ldhuio;
assign r_ctrl_ld_nxt = d_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_ld <= 0;
else if (r_en)
r_ctrl_ld <= r_ctrl_ld_nxt;
end
assign d_ctrl_ld_non_io = d_op_ldbu|d_op_ldhu|d_op_ldb|d_op_ldh|d_op_ldw|d_op_ldl;
assign r_ctrl_ld_non_io_nxt = d_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_ld_non_io <= 0;
else if (r_en)
r_ctrl_ld_non_io <= r_ctrl_ld_non_io_nxt;
end
assign d_ctrl_st = d_op_stb|
d_op_sth|
d_op_stw|
d_op_stc|
d_op_stbio|
d_op_sthio|
d_op_stwio|
d_op_rsv61;
assign r_ctrl_st_nxt = d_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_st <= 0;
else if (r_en)
r_ctrl_st <= r_ctrl_st_nxt;
end
assign d_ctrl_ld_io = d_op_ldbuio|d_op_ldhuio|d_op_ldbio|d_op_ldhio|d_op_ldwio|d_op_rsv63;
assign r_ctrl_ld_io_nxt = d_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_ld_io <= 0;
else if (r_en)
r_ctrl_ld_io <= r_ctrl_ld_io_nxt;
end
assign d_ctrl_b_is_dst = d_op_addi|
d_op_andhi|
d_op_orhi|
d_op_xorhi|
d_op_andi|
d_op_ori|
d_op_xori|
d_op_call|
d_op_rdprs|
d_op_cmpgei|
d_op_cmplti|
d_op_cmpnei|
d_op_cmpgeui|
d_op_cmpltui|
d_op_cmpeqi|
d_op_jmpi|
d_op_rsv09|
d_op_rsv17|
d_op_rsv25|
d_op_rsv33|
d_op_rsv41|
d_op_rsv49|
d_op_rsv57|
d_op_ldb|
d_op_ldh|
d_op_ldl|
d_op_ldw|
d_op_ldbio|
d_op_ldhio|
d_op_ldwio|
d_op_rsv63|
d_op_ldbu|
d_op_ldhu|
d_op_ldbuio|
d_op_ldhuio|
d_op_initd|
d_op_initda|
d_op_flushd|
d_op_flushda;
assign r_ctrl_b_is_dst_nxt = d_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_b_is_dst <= 0;
else if (r_en)
r_ctrl_b_is_dst <= r_ctrl_b_is_dst_nxt;
end
assign d_ctrl_ignore_dst = d_op_br|
d_op_bge|
d_op_blt|
d_op_bne|
d_op_beq|
d_op_bgeu|
d_op_bltu|
d_op_rsv62|
d_op_stb|
d_op_sth|
d_op_stw|
d_op_stc|
d_op_stbio|
d_op_sthio|
d_op_stwio|
d_op_rsv61|
d_op_jmpi|
d_op_rsv09|
d_op_rsv17|
d_op_rsv25|
d_op_rsv33|
d_op_rsv41|
d_op_rsv49|
d_op_rsv57;
assign r_ctrl_ignore_dst_nxt = d_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_ignore_dst <= 0;
else if (r_en)
r_ctrl_ignore_dst <= r_ctrl_ignore_dst_nxt;
end
assign d_ctrl_src2_choose_imm = d_op_addi|
d_op_andhi|
d_op_orhi|
d_op_xorhi|
d_op_andi|
d_op_ori|
d_op_xori|
d_op_call|
d_op_rdprs|
d_op_cmpgei|
d_op_cmplti|
d_op_cmpnei|
d_op_cmpgeui|
d_op_cmpltui|
d_op_cmpeqi|
d_op_jmpi|
d_op_rsv09|
d_op_rsv17|
d_op_rsv25|
d_op_rsv33|
d_op_rsv41|
d_op_rsv49|
d_op_rsv57|
d_op_ldb|
d_op_ldh|
d_op_ldl|
d_op_ldw|
d_op_ldbio|
d_op_ldhio|
d_op_ldwio|
d_op_rsv63|
d_op_ldbu|
d_op_ldhu|
d_op_ldbuio|
d_op_ldhuio|
d_op_initd|
d_op_initda|
d_op_flushd|
d_op_flushda|
d_op_stb|
d_op_sth|
d_op_stw|
d_op_stc|
d_op_stbio|
d_op_sthio|
d_op_stwio|
d_op_rsv61|
d_op_roli|
d_op_rsvx10|
d_op_slli|
d_op_srli|
d_op_rsvx34|
d_op_rsvx42|
d_op_rsvx50|
d_op_srai;
assign r_ctrl_src2_choose_imm_nxt = d_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_src2_choose_imm <= 0;
else if (r_en)
r_ctrl_src2_choose_imm <= r_ctrl_src2_choose_imm_nxt;
end
assign d_ctrl_wrctl_inst = d_op_wrctl;
assign r_ctrl_wrctl_inst_nxt = d_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_wrctl_inst <= 0;
else if (r_en)
r_ctrl_wrctl_inst <= r_ctrl_wrctl_inst_nxt;
end
assign d_ctrl_rdctl_inst = d_op_rdctl;
assign r_ctrl_rdctl_inst_nxt = d_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_rdctl_inst <= 0;
else if (r_en)
r_ctrl_rdctl_inst <= r_ctrl_rdctl_inst_nxt;
end
assign d_ctrl_force_src2_zero = d_op_call|
d_op_rsv02|
d_op_nextpc|
d_op_callr|
d_op_trap|
d_op_rsvx44|
d_op_intr|
d_op_rsvx60|
d_op_break|
d_op_hbreak|
d_op_eret|
d_op_bret|
d_op_rsvx17|
d_op_rsvx25|
d_op_ret|
d_op_jmp|
d_op_rsvx21|
d_op_jmpi;
assign r_ctrl_force_src2_zero_nxt = d_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_force_src2_zero <= 0;
else if (r_en)
r_ctrl_force_src2_zero <= r_ctrl_force_src2_zero_nxt;
end
assign d_ctrl_alu_force_xor = d_op_cmpgei|
d_op_cmpgeui|
d_op_cmpeqi|
d_op_cmpge|
d_op_cmpgeu|
d_op_cmpeq|
d_op_cmpnei|
d_op_cmpne|
d_op_bge|
d_op_rsv10|
d_op_bgeu|
d_op_rsv42|
d_op_beq|
d_op_rsv34|
d_op_bne|
d_op_rsv62|
d_op_br|
d_op_rsv02;
assign r_ctrl_alu_force_xor_nxt = d_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
r_ctrl_alu_force_xor <= 0;
else if (r_en)
r_ctrl_alu_force_xor <= r_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// simulation-only contents
assign f_inst = (f_op_call)? 56'h20202063616c6c :
(f_op_jmpi)? 56'h2020206a6d7069 :
(f_op_ldbu)? 56'h2020206c646275 :
(f_op_addi)? 56'h20202061646469 :
(f_op_stb)? 56'h20202020737462 :
(f_op_br)? 56'h20202020206272 :
(f_op_ldb)? 56'h202020206c6462 :
(f_op_cmpgei)? 56'h20636d70676569 :
(f_op_ldhu)? 56'h2020206c646875 :
(f_op_andi)? 56'h202020616e6469 :
(f_op_sth)? 56'h20202020737468 :
(f_op_bge)? 56'h20202020626765 :
(f_op_ldh)? 56'h202020206c6468 :
(f_op_cmplti)? 56'h20636d706c7469 :
(f_op_initda)? 56'h20696e69746461 :
(f_op_ori)? 56'h202020206f7269 :
(f_op_stw)? 56'h20202020737477 :
(f_op_blt)? 56'h20202020626c74 :
(f_op_ldw)? 56'h202020206c6477 :
(f_op_cmpnei)? 56'h20636d706e6569 :
(f_op_flushda)? 56'h666c7573686461 :
(f_op_xori)? 56'h202020786f7269 :
(f_op_bne)? 56'h20202020626e65 :
(f_op_cmpeqi)? 56'h20636d70657169 :
(f_op_ldbuio)? 56'h206c646275696f :
(f_op_muli)? 56'h2020206d756c69 :
(f_op_stbio)? 56'h2020737462696f :
(f_op_beq)? 56'h20202020626571 :
(f_op_ldbio)? 56'h20206c6462696f :
(f_op_cmpgeui)? 56'h636d7067657569 :
(f_op_ldhuio)? 56'h206c646875696f :
(f_op_andhi)? 56'h2020616e646869 :
(f_op_sthio)? 56'h2020737468696f :
(f_op_bgeu)? 56'h20202062676575 :
(f_op_ldhio)? 56'h20206c6468696f :
(f_op_cmpltui)? 56'h636d706c747569 :
(f_op_initd)? 56'h2020696e697464 :
(f_op_orhi)? 56'h2020206f726869 :
(f_op_stwio)? 56'h2020737477696f :
(f_op_bltu)? 56'h202020626c7475 :
(f_op_ldwio)? 56'h20206c6477696f :
(f_op_flushd)? 56'h20666c75736864 :
(f_op_xorhi)? 56'h2020786f726869 :
(f_op_eret)? 56'h20202065726574 :
(f_op_roli)? 56'h202020726f6c69 :
(f_op_rol)? 56'h20202020726f6c :
(f_op_flushp)? 56'h20666c75736870 :
(f_op_ret)? 56'h20202020726574 :
(f_op_nor)? 56'h202020206e6f72 :
(f_op_mulxuu)? 56'h206d756c787575 :
(f_op_cmpge)? 56'h2020636d706765 :
(f_op_bret)? 56'h20202062726574 :
(f_op_ror)? 56'h20202020726f72 :
(f_op_flushi)? 56'h20666c75736869 :
(f_op_jmp)? 56'h202020206a6d70 :
(f_op_and)? 56'h20202020616e64 :
(f_op_cmplt)? 56'h2020636d706c74 :
(f_op_slli)? 56'h202020736c6c69 :
(f_op_sll)? 56'h20202020736c6c :
(f_op_or)? 56'h20202020206f72 :
(f_op_mulxsu)? 56'h206d756c787375 :
(f_op_cmpne)? 56'h2020636d706e65 :
(f_op_srli)? 56'h20202073726c69 :
(f_op_srl)? 56'h2020202073726c :
(f_op_nextpc)? 56'h206e6578747063 :
(f_op_callr)? 56'h202063616c6c72 :
(f_op_xor)? 56'h20202020786f72 :
(f_op_mulxss)? 56'h206d756c787373 :
(f_op_cmpeq)? 56'h2020636d706571 :
(f_op_divu)? 56'h20202064697675 :
(f_op_div)? 56'h20202020646976 :
(f_op_rdctl)? 56'h2020726463746c :
(f_op_mul)? 56'h202020206d756c :
(f_op_cmpgeu)? 56'h20636d70676575 :
(f_op_initi)? 56'h2020696e697469 :
(f_op_trap)? 56'h20202074726170 :
(f_op_wrctl)? 56'h2020777263746c :
(f_op_cmpltu)? 56'h20636d706c7475 :
(f_op_add)? 56'h20202020616464 :
(f_op_break)? 56'h2020627265616b :
(f_op_sync)? 56'h20202073796e63 :
(f_op_sub)? 56'h20202020737562 :
(f_op_srai)? 56'h20202073726169 :
(f_op_sra)? 56'h20202020737261 :
(f_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign d_inst = (d_op_call)? 56'h20202063616c6c :
(d_op_jmpi)? 56'h2020206a6d7069 :
(d_op_ldbu)? 56'h2020206c646275 :
(d_op_addi)? 56'h20202061646469 :
(d_op_stb)? 56'h20202020737462 :
(d_op_br)? 56'h20202020206272 :
(d_op_ldb)? 56'h202020206c6462 :
(d_op_cmpgei)? 56'h20636d70676569 :
(d_op_ldhu)? 56'h2020206c646875 :
(d_op_andi)? 56'h202020616e6469 :
(d_op_sth)? 56'h20202020737468 :
(d_op_bge)? 56'h20202020626765 :
(d_op_ldh)? 56'h202020206c6468 :
(d_op_cmplti)? 56'h20636d706c7469 :
(d_op_initda)? 56'h20696e69746461 :
(d_op_ori)? 56'h202020206f7269 :
(d_op_stw)? 56'h20202020737477 :
(d_op_blt)? 56'h20202020626c74 :
(d_op_ldw)? 56'h202020206c6477 :
(d_op_cmpnei)? 56'h20636d706e6569 :
(d_op_flushda)? 56'h666c7573686461 :
(d_op_xori)? 56'h202020786f7269 :
(d_op_bne)? 56'h20202020626e65 :
(d_op_cmpeqi)? 56'h20636d70657169 :
(d_op_ldbuio)? 56'h206c646275696f :
(d_op_muli)? 56'h2020206d756c69 :
(d_op_stbio)? 56'h2020737462696f :
(d_op_beq)? 56'h20202020626571 :
(d_op_ldbio)? 56'h20206c6462696f :
(d_op_cmpgeui)? 56'h636d7067657569 :
(d_op_ldhuio)? 56'h206c646875696f :
(d_op_andhi)? 56'h2020616e646869 :
(d_op_sthio)? 56'h2020737468696f :
(d_op_bgeu)? 56'h20202062676575 :
(d_op_ldhio)? 56'h20206c6468696f :
(d_op_cmpltui)? 56'h636d706c747569 :
(d_op_initd)? 56'h2020696e697464 :
(d_op_orhi)? 56'h2020206f726869 :
(d_op_stwio)? 56'h2020737477696f :
(d_op_bltu)? 56'h202020626c7475 :
(d_op_ldwio)? 56'h20206c6477696f :
(d_op_flushd)? 56'h20666c75736864 :
(d_op_xorhi)? 56'h2020786f726869 :
(d_op_eret)? 56'h20202065726574 :
(d_op_roli)? 56'h202020726f6c69 :
(d_op_rol)? 56'h20202020726f6c :
(d_op_flushp)? 56'h20666c75736870 :
(d_op_ret)? 56'h20202020726574 :
(d_op_nor)? 56'h202020206e6f72 :
(d_op_mulxuu)? 56'h206d756c787575 :
(d_op_cmpge)? 56'h2020636d706765 :
(d_op_bret)? 56'h20202062726574 :
(d_op_ror)? 56'h20202020726f72 :
(d_op_flushi)? 56'h20666c75736869 :
(d_op_jmp)? 56'h202020206a6d70 :
(d_op_and)? 56'h20202020616e64 :
(d_op_cmplt)? 56'h2020636d706c74 :
(d_op_slli)? 56'h202020736c6c69 :
(d_op_sll)? 56'h20202020736c6c :
(d_op_or)? 56'h20202020206f72 :
(d_op_mulxsu)? 56'h206d756c787375 :
(d_op_cmpne)? 56'h2020636d706e65 :
(d_op_srli)? 56'h20202073726c69 :
(d_op_srl)? 56'h2020202073726c :
(d_op_nextpc)? 56'h206e6578747063 :
(d_op_callr)? 56'h202063616c6c72 :
(d_op_xor)? 56'h20202020786f72 :
(d_op_mulxss)? 56'h206d756c787373 :
(d_op_cmpeq)? 56'h2020636d706571 :
(d_op_divu)? 56'h20202064697675 :
(d_op_div)? 56'h20202020646976 :
(d_op_rdctl)? 56'h2020726463746c :
(d_op_mul)? 56'h202020206d756c :
(d_op_cmpgeu)? 56'h20636d70676575 :
(d_op_initi)? 56'h2020696e697469 :
(d_op_trap)? 56'h20202074726170 :
(d_op_wrctl)? 56'h2020777263746c :
(d_op_cmpltu)? 56'h20636d706c7475 :
(d_op_add)? 56'h20202020616464 :
(d_op_break)? 56'h2020627265616b :
(d_op_sync)? 56'h20202073796e63 :
(d_op_sub)? 56'h20202020737562 :
(d_op_srai)? 56'h20202073726169 :
(d_op_sra)? 56'h20202020737261 :
(d_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign f_vinst = f_valid ? f_inst : {7{8'h2d}};
assign d_vinst = d_valid ? d_inst : {7{8'h2d}};
assign r_vinst = r_valid ? d_inst : {7{8'h2d}};
assign e_vinst = e_valid ? d_inst : {7{8'h2d}};
assign w_vinst = w_valid ? d_inst : {7{8'h2d}};
//////////////// end simulation-only contents
//synthesis translate_on
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
// (c) 2001-2018 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module changes the alpha value of every pixel of a specific color. *
* *
******************************************************************************/
module computer_system_vga_subsystem_char_buf_subsystem_set_black_transparent (
// global signals
clk,
reset,
// input stream
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_in_ready,
// output stream
stream_out_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
parameter cw = 29; // frame's data width (color portion only)
parameter dw = 39; // frame's data width
parameter color = 30'd0; // color to apply alpha value
parameter alpha = 10'd0; // the alpha value to apply
/*****************************************************************************
* port declarations *
*****************************************************************************/
// global signals
input clk;
input reset;
// input stream
input [dw: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
output stream_in_ready;
// output stream
input stream_out_ready;
output reg [dw: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
wire [dw: 0] converted_data;
// internal registers
// state machine registers
// integers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
// output registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_valid <= stream_in_valid;
end
end
// internal registers
/*****************************************************************************
* combinational logic *
*****************************************************************************/
// output assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// internal assignments
assign converted_data = (stream_in_data[cw:0] == color) ?
{alpha, stream_in_data[cw:0]} :
stream_in_data;
/*****************************************************************************
* internal modules *
*****************************************************************************/
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
//-----------------------------------------------------------------
// usb cdc device
// v0.1
// ultra-embedded.com
// copyright 2014-2019
//
// email: admin@ultra-embedded.com
//
// license: lgpl
//-----------------------------------------------------------------
//
// this source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// this source file is free software; you can redistribute it
// and/or modify it under the terms of the gnu lesser general
// public license as published by the free software foundation;
// either version 2.1 of the license, or (at your option) any
// later version.
//
// this source is distributed in the hope that it will be
// useful, but without any warranty; without even the implied
// warranty of merchantability or fitness for a particular
// purpose. see the gnu lesser general public license for more
// details.
//
// you should have received a copy of the gnu lesser general
// public license along with this source; if not, write to the
// free software foundation, inc., 59 temple place, suite 330,
// boston, ma 02111-1307 usa
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// generated file
//-----------------------------------------------------------------
module usb_desc_rom
(
input hs_i,
input [7:0] addr_i,
output [7:0] data_o
);
reg [7:0] desc_rom_r;
always @ *
begin
case (addr_i)
8'd0: desc_rom_r = 8'h12;
8'd1: desc_rom_r = 8'h01;
8'd2: desc_rom_r = 8'h00;
8'd3: desc_rom_r = 8'h02;
8'd4: desc_rom_r = 8'h02;
8'd5: desc_rom_r = 8'h00;
8'd6: desc_rom_r = 8'h00;
8'd7: desc_rom_r = hs_i ? 8'h40 : 8'h08;
8'd8: desc_rom_r = 8'h50; // vid_l
8'd9: desc_rom_r = 8'h1d; // vid_h
8'd10: desc_rom_r = 8'h49; // pid_l
8'd11: desc_rom_r = 8'h61; // pid_h
8'd12: desc_rom_r = 8'h01;
8'd13: desc_rom_r = 8'h01;
8'd14: desc_rom_r = 8'h00;
8'd15: desc_rom_r = 8'h00;
8'd16: desc_rom_r = 8'h00;
8'd17: desc_rom_r = 8'h01;
8'd18: desc_rom_r = 8'h09;
8'd19: desc_rom_r = 8'h02;
8'd20: desc_rom_r = 8'h43;
8'd21: desc_rom_r = 8'h00;
8'd22: desc_rom_r = 8'h02;
8'd23: desc_rom_r = 8'h01;
8'd24: desc_rom_r = 8'h00;
8'd25: desc_rom_r = 8'h80;
8'd26: desc_rom_r = 8'h32;
8'd27: desc_rom_r = 8'h09;
8'd28: desc_rom_r = 8'h04;
8'd29: desc_rom_r = 8'h00;
8'd30: desc_rom_r = 8'h00;
8'd31: desc_rom_r = 8'h01;
8'd32: desc_rom_r = 8'h02;
8'd33: desc_rom_r = 8'h02;
8'd34: desc_rom_r = 8'h01;
8'd35: desc_rom_r = 8'h00;
8'd36: desc_rom_r = 8'h05;
8'd37: desc_rom_r = 8'h24;
8'd38: desc_rom_r = 8'h00;
8'd39: desc_rom_r = 8'h10;
8'd40: desc_rom_r = 8'h01;
8'd41: desc_rom_r = 8'h05;
8'd42: desc_rom_r = 8'h24;
8'd43: desc_rom_r = 8'h01;
8'd44: desc_rom_r = 8'h03;
8'd45: desc_rom_r = 8'h01;
8'd46: desc_rom_r = 8'h04;
8'd47: desc_rom_r = 8'h24;
8'd48: desc_rom_r = 8'h02;
8'd49: desc_rom_r = 8'h06;
8'd50: desc_rom_r = 8'h05;
8'd51: desc_rom_r = 8'h24;
8'd52: desc_rom_r = 8'h06;
8'd53: desc_rom_r = 8'h00;
8'd54: desc_rom_r = 8'h01;
8'd55: desc_rom_r = 8'h07;
8'd56: desc_rom_r = 8'h05;
8'd57: desc_rom_r = 8'h83;
8'd58: desc_rom_r = 8'h03;
8'd59: desc_rom_r = 8'h40;
8'd60: desc_rom_r = 8'h00;
8'd61: desc_rom_r = 8'h02;
8'd62: desc_rom_r = 8'h09;
8'd63: desc_rom_r = 8'h04;
8'd64: desc_rom_r = 8'h01;
8'd65: desc_rom_r = 8'h00;
8'd66: desc_rom_r = 8'h02;
8'd67: desc_rom_r = 8'h0a;
8'd68: desc_rom_r = 8'h00;
8'd69: desc_rom_r = 8'h00;
8'd70: desc_rom_r = 8'h00;
8'd71: desc_rom_r = 8'h07;
8'd72: desc_rom_r = 8'h05;
8'd73: desc_rom_r = 8'h01;
8'd74: desc_rom_r = 8'h02;
8'd75: desc_rom_r = hs_i ? 8'h00 : 8'h40;
8'd76: desc_rom_r = hs_i ? 8'h02 : 8'h00;
8'd77: desc_rom_r = 8'h00;
8'd78: desc_rom_r = 8'h07;
8'd79: desc_rom_r = 8'h05;
8'd80: desc_rom_r = 8'h82;
8'd81: desc_rom_r = 8'h02;
8'd82: desc_rom_r = hs_i ? 8'h00 : 8'h40;
8'd83: desc_rom_r = hs_i ? 8'h02 : 8'h00;
8'd84: desc_rom_r = 8'h00;
8'd85: desc_rom_r = 8'h04;
8'd86: desc_rom_r = 8'h03;
8'd87: desc_rom_r = 8'h09;
8'd88: desc_rom_r = 8'h04;
8'd89: desc_rom_r = 8'h1e;
8'd90: desc_rom_r = 8'h03;
8'd91: desc_rom_r = 8'h55;
8'd92: desc_rom_r = 8'h00;
8'd93: desc_rom_r = 8'h4c;
8'd94: desc_rom_r = 8'h00;
8'd95: desc_rom_r = 8'h54;
8'd96: desc_rom_r = 8'h00;
8'd97: desc_rom_r = 8'h52;
8'd98: desc_rom_r = 8'h00;
8'd99: desc_rom_r = 8'h41;
8'd100: desc_rom_r = 8'h00;
8'd101: desc_rom_r = 8'h2d;
8'd102: desc_rom_r = 8'h00;
8'd103: desc_rom_r = 8'h45;
8'd104: desc_rom_r = 8'h00;
8'd105: desc_rom_r = 8'h4d;
8'd106: desc_rom_r = 8'h00;
8'd107: desc_rom_r = 8'h42;
8'd108: desc_rom_r = 8'h00;
8'd109: desc_rom_r = 8'h45;
8'd110: desc_rom_r = 8'h00;
8'd111: desc_rom_r = 8'h44;
8'd112: desc_rom_r = 8'h00;
8'd113: desc_rom_r = 8'h44;
8'd114: desc_rom_r = 8'h00;
8'd115: desc_rom_r = 8'h45;
8'd116: desc_rom_r = 8'h00;
8'd117: desc_rom_r = 8'h44;
8'd118: desc_rom_r = 8'h00;
8'd119: desc_rom_r = 8'h1e;
8'd120: desc_rom_r = 8'h03;
8'd121: desc_rom_r = 8'h55;
8'd122: desc_rom_r = 8'h00;
8'd123: desc_rom_r = 8'h53;
8'd124: desc_rom_r = 8'h00;
8'd125: desc_rom_r = 8'h42;
8'd126: desc_rom_r = 8'h00;
8'd127: desc_rom_r = 8'h20;
8'd128: desc_rom_r = 8'h00;
8'd129: desc_rom_r = 8'h44;
8'd130: desc_rom_r = 8'h00;
8'd131: desc_rom_r = 8'h45;
8'd132: desc_rom_r = 8'h00;
8'd133: desc_rom_r = 8'h4d;
8'd134: desc_rom_r = 8'h00;
8'd135: desc_rom_r = 8'h4f;
8'd136: desc_rom_r = 8'h00;
8'd137: desc_rom_r = 8'h20;
8'd138: desc_rom_r = 8'h00;
8'd139: desc_rom_r = 8'h20;
8'd140: desc_rom_r = 8'h00;
8'd141: desc_rom_r = 8'h20;
8'd142: desc_rom_r = 8'h00;
8'd143: desc_rom_r = 8'h20;
8'd144: desc_rom_r = 8'h00;
8'd145: desc_rom_r = 8'h20;
8'd146: desc_rom_r = 8'h00;
8'd147: desc_rom_r = 8'h20;
8'd148: desc_rom_r = 8'h00;
8'd149: desc_rom_r = 8'h0e;
8'd150: desc_rom_r = 8'h03;
8'd151: desc_rom_r = 8'h30;
8'd152: desc_rom_r = 8'h00;
8'd153: desc_rom_r = 8'h30;
8'd154: desc_rom_r = 8'h00;
8'd155: desc_rom_r = 8'h30;
8'd156: desc_rom_r = 8'h00;
8'd157: desc_rom_r = 8'h30;
8'd158: desc_rom_r = 8'h00;
8'd159: desc_rom_r = 8'h30;
8'd160: desc_rom_r = 8'h00;
8'd161: desc_rom_r = 8'h30;
8'd162: desc_rom_r = 8'h00;
8'd163: desc_rom_r = 8'h00;
8'd164: desc_rom_r = 8'hc2;
8'd165: desc_rom_r = 8'h01;
8'd166: desc_rom_r = 8'h00;
8'd167: desc_rom_r = 8'h00;
8'd168: desc_rom_r = 8'h00;
8'd169: desc_rom_r = 8'h08;
default: desc_rom_r = 8'h00;
endcase
end
assign data_o = desc_rom_r;
endmodule
|
//
// Copyright (c) 2002 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Binary ~| (nor) operator.
module main;
reg A, B;
reg result1;
wire result2 = A ~| B;
initial
begin
A = 0;
B = 0;
#1 result1 = A ~| B;
if (result1 !== 1'b1) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b1) begin
$display("FAILED");
$finish;
end
A = 1;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
B = 1;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
A = 0;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule // main
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 6.0 Build 202 04/27/2006
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
module cycloneii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneii_latch
module cycloneii_latch(D, ENA, PRE, CLR, Q);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup (D, posedge ENA, 0) ;
$hold (negedge ENA, D, 0) ;
(D => Q) = (0, 0);
(posedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
(negedge CLR => (Q +: q_out)) = (0, 0);
endspecify
wire D_in;
wire ENA_in;
wire PRE_in;
wire CLR_in;
buf (D_in, D);
buf (ENA_in, ENA);
buf (PRE_in, PRE);
buf (CLR_in, CLR);
initial
begin
q_out = 1'b0;
end
always @(D_in or ENA_in or PRE_in or CLR_in)
begin
if (PRE_in == 1'b0)
begin
// latch being preset, preset is active low
q_out = 1'b1;
end
else if (CLR_in == 1'b0)
begin
// latch being cleared, clear is active low
q_out = 1'b0;
end
else if (ENA_in == 1'b1)
begin
// latch is transparent
q_out = D_in;
end
end
and (Q, q_out, 1'b1);
endmodule
// ***** cycloneii_mux21
module cycloneii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_mux41
module cycloneii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_and1
module cycloneii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneii_and16
module cycloneii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneii_bmux21
module cycloneii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_b17mux21
module cycloneii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_nmux21
module cycloneii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneii_b5mux21
module cycloneii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
reg state;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(1) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
always @(posedge clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena) state <= 1'b1;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneii_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_data_out_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock0";
parameter port_b_address_clock = "clock0";
parameter port_b_read_enable_write_enable_clock = "clock0";
parameter port_b_byte_enable_clock = "none";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
parameter port_a_byte_size = 0;
parameter port_a_disable_ce_on_input_registers = "off";
parameter port_a_disable_ce_on_output_registers = "off";
parameter port_b_byte_size = 0;
parameter port_b_disable_ce_on_input_registers = "off";
parameter port_b_disable_ce_on_output_registers = "off";
parameter safe_write = "err_on_2clk";
// -------- LOCAL PARAMETERS ---------
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a,active_a_in,active_b,active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0 : clk1);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0 : clk1;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0 : clk1);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0 : clk1);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0 : clr1);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0 : clr1);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0 : clr1);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0 : clr1);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0 : clr1);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0 : clr1);
assign active_a_in = ena0 || (port_a_disable_ce_on_input_registers == "on");
assign active_b_in = ((port_b_read_enable_write_enable_clock == "clock0") ? ena0 : ena1) ||
(port_b_disable_ce_on_input_registers == "on");
// Store clock enable value for SEAB/MEAB
// port A active
cycloneii_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
cycloneii_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
cycloneii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
cycloneii_ram_register addr_a_register (
.d(portaaddr),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneii_ram_register datain_a_register (
.d(portadatain),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneii_ram_register byteena_a_register (
.d(portabyteenamasks),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
cycloneii_ram_register rewe_b_register (
.d(portbrewe),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
cycloneii_ram_register addr_b_register (
.d(portbaddr),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneii_ram_register datain_b_register (
.d(portbdatain),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneii_ram_register byteena_b_register (
.d(portbbyteenamasks),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
cycloneii_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
cycloneii_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
cycloneii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),.cycle()
);
cycloneii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (i = 0; i < port_b_data_width; i = i + 1)
begin
mask_vector_b[i] = (byteena_b_reg[i/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[i] = (byteena_b_reg[i/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime) read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
cycloneii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// -------- Async clear logic ---------
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
ena0 || (port_a_disable_ce_on_output_registers == "on") :
ena1 || (port_a_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
ena0 || (port_b_disable_ce_on_output_registers == "on") :
ena1 || (port_b_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneii_ram_block
//--------------------------------------------------------------------
//
// Module Name : cycloneii_jtag
//
// Description : CycloneII JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_jtag (tms, tck, tdi, ntrst, tdoutap, tdouser, tdo, tmsutap, tckutap, tdiutap, shiftuser, clkdruser, updateuser, runidleuser, usr1user);
input tms, tck, tdi, ntrst, tdoutap, tdouser;
output tdo, tmsutap, tckutap, tdiutap, shiftuser, clkdruser;
output updateuser, runidleuser, usr1user;
parameter lpm_type = "cycloneii_jtag";
initial
begin
end
always @(tms or tck or tdi or ntrst or tdoutap or tdouser)
begin
end
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneii_crcblock
//
// Description : CycloneII CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_crcblock
(
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneii_crcblock";
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_asmiblock
//
// Description : CycloneII ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "cycloneii_asmiblock";
endmodule // cycloneii_asmiblock
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0, C1, C2, C3, C4 and
// C5 output counters of the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneii_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll
//
// Description : Timing simulation model for the CycloneII PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 6 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneii_pll (inclk,
ena,
clkswitch,
areset,
pfdena,
testclearlock,
clk,
locked,
testupout,
testdownout,
sbdin,
sbdout
);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clk0";
parameter feedback_source = "clk0";
parameter qualify_conf_done = "off";
parameter test_input_comp_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter self_reset_on_gated_loss_lock = "off";
parameter valid_lock_multiplier = 1;
parameter invalid_lock_multiplier = 5;
parameter switch_over_type = "manual";
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "on";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter down_spread = "0.0";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter rx_outclock_resource = "auto";
parameter use_dc_coupling = "false";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 1;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "c0";
parameter clk1_counter = "c1";
parameter clk2_counter = "c2";
parameter clk3_counter = "c3";
parameter clk4_counter = "c4";
parameter clk5_counter = "c5";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter m_test_source = 5;
parameter c0_test_source = 5;
parameter c1_test_source = 5;
parameter c2_test_source = 5;
parameter c3_test_source = 5;
parameter c4_test_source = 5;
parameter c5_test_source = 5;
// LVDS mode parameters
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter charge_pump_current = 0;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 1;
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneii_pll";
//parameter for cycloneii lvds
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
// INPUT PORTS
input [1:0] inclk;
input ena;
input clkswitch;
input areset;
input pfdena;
input testclearlock;
input sbdin;
// OUTPUT PORTS
output [2:0] clk;
output locked;
output sbdout;
// lvds specific output ports
// test ports
output testupout;
output testdownout;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire clkswitch_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire scanclk_ipd;
wire scanread_ipd;
wire scanwrite_ipd;
wire scandata_ipd;
wire sbdin_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, 1'b0);
buf (clkswitch_ipd, clkswitch);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (scanclk_ipd, 1'b0);
buf (scanread_ipd, 1'b0);
buf (scanwrite_ipd, 1'b0);
buf (scandata_ipd, 1'b0);
buf (sbdin_ipd, sbdin);
// TIMING CHECKS
specify
(sbdin => sbdout) = (0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer c0_count;
integer c0_initial_count;
integer c1_count;
integer c1_initial_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time next_vco_sched_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg c0_got_first_rising_edge;
reg c1_got_first_rising_edge;
reg vco_c0_last_value;
reg vco_c1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:5];
reg [31:0] c_low_val[0:5];
reg [8*6:1] c_mode_val[0:5];
reg [31:0] c_initial_val[0:5];
integer c_ph_val[0:5];
// temporary registers for reprogramming
integer c_ph_val_tmp[0:5];
reg [31:0] c_high_val_tmp[0:5];
reg [31:0] c_low_val_tmp[0:5];
reg [8*6:1] c_mode_val_tmp[0:5];
// hold registers for reprogramming
integer c_ph_val_hold[0:5];
reg [31:0] c_high_val_hold[0:5];
reg [31:0] c_low_val_hold[0:5];
reg [8*6:1] c_mode_val_hold[0:5];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:5];
reg [31:0] c_low_val_old[0:5];
reg [8*6:1] c_mode_val_old[0:5];
integer c_ph_val_old[0:5];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [31:0] m_hi;
reg [31:0] m_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:5];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
reg inclk_c0_from_vco;
reg inclk_c1_from_vco;
reg inclk_c2_from_vco;
reg inclk_c3_from_vco;
reg inclk_c4_from_vco;
reg inclk_c5_from_vco;
reg inclk_m_from_vco;
wire inclk_m;
wire [5:0] clk_tmp;
wire ena_pll;
wire n_cntr_inclk;
reg vco_c0;
reg vco_c1;
wire [5:0] clk_out;
wire sclkout0;
wire sclkout1;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
wire sbdout_tmp;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
integer ext_fbk_cntr_index;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandone_tmp;
reg scandone_tmp_last_value;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
reg scanread_reg;
reg scanwrite_reg;
reg scanwrite_enabled;
reg scanwrite_last_value;
reg [173:0] scan_data;
reg [173:0] tmp_scan_data;
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// INTERNAL PARAMETERS
parameter GPP_SCAN_CHAIN = 174;
parameter FAST_SCAN_CHAIN = 75;
// primary clk is always inclk0
parameter primary_clock = "inclk0";
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_c_high[0:5];
integer i_c_low[0:5];
integer i_c_initial[0:5];
integer i_c_ph[0:5];
reg [8*6:1] i_c_mode[0:5];
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg [9*8:1] loop_filter_r_arr[0:39];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_is_disabled;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
integer current_clock;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg op_mode;
reg init;
reg tap0_is_active;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360)/45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
display_msg = 1;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_primary_clock = alpha_tolower(primary_clock);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_switch_over_type = alpha_tolower(switch_over_type);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 57;
loop_filter_c_arr[1] = 16;
loop_filter_c_arr[2] = 36;
loop_filter_c_arr[3] = 5;
fpll_loop_filter_c_arr[0] = 18;
fpll_loop_filter_c_arr[1] = 13;
fpll_loop_filter_c_arr[2] = 8;
fpll_loop_filter_c_arr[3] = 2;
charge_pump_curr_arr[0] = 6;
charge_pump_curr_arr[1] = 12;
charge_pump_curr_arr[2] = 30;
charge_pump_curr_arr[3] = 36;
charge_pump_curr_arr[4] = 52;
charge_pump_curr_arr[5] = 57;
charge_pump_curr_arr[6] = 72;
charge_pump_curr_arr[7] = 77;
charge_pump_curr_arr[8] = 92;
charge_pump_curr_arr[9] = 96;
charge_pump_curr_arr[10] = 110;
charge_pump_curr_arr[11] = 114;
charge_pump_curr_arr[12] = 127;
charge_pump_curr_arr[13] = 131;
charge_pump_curr_arr[14] = 144;
charge_pump_curr_arr[15] = 148;
loop_filter_r_arr[0] = " 1.000000";
loop_filter_r_arr[1] = " 1.500000";
loop_filter_r_arr[2] = " 2.000000";
loop_filter_r_arr[3] = " 2.500000";
loop_filter_r_arr[4] = " 3.000000";
loop_filter_r_arr[5] = " 3.500000";
loop_filter_r_arr[6] = " 4.000000";
loop_filter_r_arr[7] = " 4.500000";
loop_filter_r_arr[8] = " 5.000000";
loop_filter_r_arr[9] = " 5.500000";
loop_filter_r_arr[10] = " 6.000000";
loop_filter_r_arr[11] = " 6.500000";
loop_filter_r_arr[12] = " 7.000000";
loop_filter_r_arr[13] = " 7.500000";
loop_filter_r_arr[14] = " 8.000000";
loop_filter_r_arr[15] = " 8.500000";
loop_filter_r_arr[16] = " 9.000000";
loop_filter_r_arr[17] = " 9.500000";
loop_filter_r_arr[18] = "10.000000";
loop_filter_r_arr[19] = "10.500000";
loop_filter_r_arr[20] = "11.000000";
loop_filter_r_arr[21] = "11.500000";
loop_filter_r_arr[22] = "12.000000";
loop_filter_r_arr[23] = "12.500000";
loop_filter_r_arr[24] = "13.000000";
loop_filter_r_arr[25] = "13.500000";
loop_filter_r_arr[26] = "14.000000";
loop_filter_r_arr[27] = "14.500000";
loop_filter_r_arr[28] = "15.000000";
loop_filter_r_arr[29] = "15.500000";
loop_filter_r_arr[30] = "16.000000";
loop_filter_r_arr[31] = "16.500000";
loop_filter_r_arr[32] = "17.000000";
loop_filter_r_arr[33] = "17.500000";
loop_filter_r_arr[34] = "18.000000";
loop_filter_r_arr[35] = "18.500000";
loop_filter_r_arr[36] = "19.000000";
loop_filter_r_arr[37] = "19.500000";
loop_filter_r_arr[38] = "20.000000";
loop_filter_r_arr[39] = "20.500000";
if (m == 0)
begin
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
// VCO feedback loop settings for external feedback mode
// first find which counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
op_mode = 1;
if (l_feedback_source == "clk0")
ext_fbk_cntr = i_clk0_counter;
else if (l_feedback_source == "clk1")
ext_fbk_cntr = i_clk1_counter;
else if (l_feedback_source == "clk2")
ext_fbk_cntr = i_clk2_counter;
else if (l_feedback_source == "clk3")
ext_fbk_cntr = i_clk3_counter;
else if (l_feedback_source == "clk4")
ext_fbk_cntr = i_clk4_counter;
else if (l_feedback_source == "clk5")
ext_fbk_cntr = i_clk5_counter;
else ext_fbk_cntr = "c0";
if (ext_fbk_cntr == "c0")
ext_fbk_cntr_index = 0;
else if (ext_fbk_cntr == "c1")
ext_fbk_cntr_index = 1;
else if (ext_fbk_cntr == "c2")
ext_fbk_cntr_index = 2;
else if (ext_fbk_cntr == "c3")
ext_fbk_cntr_index = 3;
else if (ext_fbk_cntr == "c4")
ext_fbk_cntr_index = 4;
else if (ext_fbk_cntr == "c5")
ext_fbk_cntr_index = 5;
end
else op_mode = 0;
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
// convert user parameters to advanced
if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (i_c_mode[ext_fbk_cntr_index] == "bypass")
output_count = 1;
else
output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index];
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
refclk_period = inclk0_input_frequency * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
c0_got_first_rising_edge = 0;
c1_got_first_rising_edge = 0;
vco_c0_last_value = 0;
c0_count = 2;
c0_initial_count = 1;
c1_count = 2;
c1_initial_count = 1;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_c0 = 0;
vco_c1 = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandone_tmp = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
m_val[1] = m2;
n_val[1] = n2;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 6; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
if (l_primary_clock == "inclk0")
current_clock = 0;
else current_clock = 1;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast")
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
end
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
scanread_active_edge = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 4;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 6;
end
scanread_reg = 0;
scanwrite_reg = 0;
scanwrite_enabled = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
// initialize the scan_chain contents
// CP/LF bits
scan_data[11:0] = 12'b0;
for (i = 0; i <= 3; i = i + 1)
begin
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
if (fpll_loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
else begin
if (loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
end
for (i = 0; i <= 15; i = i + 1)
begin
if (charge_pump_curr_arr[i] == charge_pump_current)
scan_data[3:0] = i;
end
for (i = 0; i <= 39; i = i + 1)
begin
if (loop_filter_r_arr[i] == loop_filter_r)
begin
if ((i >= 16) && (i <= 23))
scan_data[9:4] = i+8;
else if ((i >= 24) && (i <= 31))
scan_data[9:4] = i+16;
else if (i >= 32)
scan_data[9:4] = i+24;
else
scan_data[9:4] = i;
end
end
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
scan_data[21:12] = 10'b0; // M, C3-C0 ph
// C0-C3 high
scan_data[25:22] = c_high_val[0];
scan_data[35:32] = c_high_val[1];
scan_data[45:42] = c_high_val[2];
scan_data[55:52] = c_high_val[3];
// C0-C3 low
scan_data[30:27] = c_low_val[0];
scan_data[40:37] = c_low_val[1];
scan_data[50:47] = c_low_val[2];
scan_data[60:57] = c_low_val[3];
// C0-C3 mode
for (i = 0; i < 4; i = i + 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[26 + (10*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
else begin
scan_data[26 + (10*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
end
// M
if (m_mode_val[0] == "bypass")
begin
scan_data[66] = 1;
scan_data[71] = 0;
scan_data[65:62] = 4'b0;
scan_data[70:67] = 4'b0;
end
else begin
scan_data[66] = 0; // set BYPASS bit to 0
scan_data[70:67] = m_val[0]/2; // set M low
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[65:62] = scan_data[70:67];
scan_data[71] = 0;
end
else begin // M is odd : M high = low + 1
scan_data[65:62] = (m_val[0]/2) + 1;
scan_data[71] = 1;
end
end
// N
scan_data[73:72] = n_val[0];
if (n_mode_val[0] == "bypass")
begin
scan_data[74] = 1;
scan_data[73:72] = 2'b0;
end
end
else begin // PLL type is enhanced/auto
scan_data[25:12] = 14'b0;
// C5-C0 high
scan_data[33:26] = c_high_val[5];
scan_data[51:44] = c_high_val[4];
scan_data[69:62] = c_high_val[3];
scan_data[87:80] = c_high_val[2];
scan_data[105:98] = c_high_val[1];
scan_data[123:116] = c_high_val[0];
// C5-C0 low
scan_data[42:35] = c_low_val[5];
scan_data[60:53] = c_low_val[4];
scan_data[78:71] = c_low_val[3];
scan_data[96:89] = c_low_val[2];
scan_data[114:107] = c_low_val[1];
scan_data[132:125] = c_low_val[0];
for (i = 5; i >= 0; i = i - 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[124 - (18*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
else begin
scan_data[124 - (18*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
end
scan_data[142:134] = m_val[0];
scan_data[143] = 0;
scan_data[152:144] = m_val[1];
scan_data[153] = 0;
if (m_mode_val[0] == "bypass")
begin
scan_data[143] = 1;
scan_data[142:134] = 9'b0;
end
if (m_mode_val[1] == "bypass")
begin
scan_data[153] = 1;
scan_data[152:144] = 9'b0;
end
scan_data[162:154] = n_val[0];
scan_data[172:164] = n_val[1];
if (n_mode_val[0] == "bypass")
begin
scan_data[163] = 1;
scan_data[162:154] = 9'b0;
end
if (n_mode_val[1] == "bypass")
begin
scan_data[173] = 1;
scan_data[172:164] = 9'b0;
end
end
// now save this counter's parameters
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 1'b0;
// check if pll is in test mode
if (m_test_source == 1 || c0_test_source == 1 || c0_test_source == 2 || c1_test_source == 1 || c1_test_source == 2 || c2_test_source == 1 || c2_test_source == 2)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_is_disabled = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
tap0_is_active = 1;
next_vco_sched_time = 0;
end
always @(clkswitch_ipd)
begin
if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if (clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
inclk_n = inclk1_ipd;
end
else if (clkswitch_ipd === 1'b0)
begin
current_clock = 0;
active_clock = 0;
inclk_n = inclk0_ipd;
end
end
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk0_ipd !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
else clkloss_tmp = clkswitch_ipd;
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
cycloneii_pll_reg ena_reg ( .clk(!inclk_n),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(1'b1),
.q(pllena_reg));
and (test_mode_inclk, inclk_n, pllena_reg);
assign n_cntr_inclk = inclk_n;
assign ena_pll = ena_ipd;
assign inclk_m = (m_test_source == 1) ? refclk : (m_test_source == 2) ? 1'b0 : (m_test_source == 3) ? 1'b0 : op_mode == 1 ? (l_feedback_source == "clk0" ? clk_tmp[0] :
l_feedback_source == "clk1" ? clk_tmp[1] :
l_feedback_source == "clk2" ? clk_tmp[2] :
l_feedback_source == "clk3" ? clk_tmp[3] :
l_feedback_source == "clk4" ? clk_tmp[4] :
l_feedback_source == "clk5" ? clk_tmp[5] : 'b0) :
inclk_m_from_vco;
cycloneii_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneii_n_cntr n1 (.clk(n_cntr_inclk),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val[0]));
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (!pll_is_disabled) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_tap[x] !== vco_tap_last_value[x])
begin
if (c_ph_val[0] == x)
begin
inclk_c0_from_vco <= vco_tap[x];
end
if (c_ph_val[1] == x)
begin
inclk_c1_from_vco <= vco_tap[x];
end
if (c_ph_val[2] == x)
inclk_c2_from_vco <= vco_tap[x];
if (c_ph_val[3] == x)
inclk_c3_from_vco <= vco_tap[x];
if (c_ph_val[4] == x)
inclk_c4_from_vco <= vco_tap[x];
if (c_ph_val[5] == x)
inclk_c5_from_vco <= vco_tap[x];
if (m_ph_val == x)
inclk_m_from_vco <= vco_tap[x];
end
end
if (scanwrite_enabled === 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y <= 5; y = y + 1)
begin
if (c_ph_val[y] == x)
c_ph_val[y] <= c_ph_val_tmp[y];
end
if (m_ph_val == x)
m_ph_val <= m_ph_val_tmp;
end
end
end
// reset all counter phase tap values to POF programmed values
if (areset_ipd === 1'b1)
begin
m_ph_val <= m_ph_val_orig;
m_ph_val_tmp <= m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
begin
c_ph_val[i] <= c_ph_val_orig[i];
c_ph_val_tmp[i] <= c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 1) ? refclk : (c0_test_source == 2) ? fbclk : (c0_test_source == 3) ? 1'b0 : inclk_c0_from_vco;
cycloneii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
always @(posedge c0_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[0] <= c_high_val_tmp[0];
c_mode_val_hold[0] <= c_mode_val_tmp[0];
c_high_val[0] <= c_high_val_hold[0];
c_mode_val[0] <= c_mode_val_hold[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge c0_clk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val_hold[0] <= c_low_val_tmp[0];
c_low_val[0] <= c_low_val_hold[0];
end
end
assign inclk_c1 = (c1_test_source == 1) ? refclk : (c1_test_source == 2) ? fbclk : (c1_test_source == 3) ? 1'b0 : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge c1_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[1] <= c_high_val_tmp[1];
c_mode_val_hold[1] <= c_mode_val_tmp[1];
c_high_val[1] <= c_high_val_hold[1];
c_mode_val[1] <= c_mode_val_hold[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge c1_clk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val_hold[1] <= c_low_val_tmp[1];
c_low_val[1] <= c_low_val_hold[1];
end
end
assign inclk_c2 = (c2_test_source == 1) ? refclk : (c2_test_source == 2) ? fbclk : (c2_test_source == 3) ? 1'b0 : (ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge c2_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[2] <= c_high_val_tmp[2];
c_mode_val_hold[2] <= c_mode_val_tmp[2];
c_high_val[2] <= c_high_val_hold[2];
c_mode_val[2] <= c_mode_val_hold[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge c2_clk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val_hold[2] <= c_low_val_tmp[2];
c_low_val[2] <= c_low_val_hold[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge c3_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[3] <= c_high_val_tmp[3];
c_mode_val_hold[3] <= c_mode_val_tmp[3];
c_high_val[3] <= c_high_val_hold[3];
c_mode_val[3] <= c_mode_val_hold[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge c3_clk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val_hold[3] <= c_low_val_tmp[3];
c_low_val[3] <= c_low_val_hold[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? n_cntr_inclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge c4_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[4] <= c_high_val_tmp[4];
c_mode_val_hold[4] <= c_mode_val_tmp[4];
c_high_val[4] <= c_high_val_hold[4];
c_mode_val[4] <= c_mode_val_hold[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge c4_clk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val_hold[4] <= c_low_val_tmp[4];
c_low_val[4] <= c_low_val_hold[4];
end
end
assign inclk_c5 = ((c5_test_source == 0) ? n_cntr_inclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco);
cycloneii_scale_cntr c5 (.clk(inclk_c5),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge c5_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[5] <= c_high_val_tmp[5];
c_mode_val_hold[5] <= c_mode_val_tmp[5];
c_high_val[5] <= c_high_val_hold[5];
c_mode_val[5] <= c_mode_val_hold[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge c5_clk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val_hold[5] <= c_low_val_tmp[5];
c_low_val[5] <= c_low_val_hold[5];
end
end
always @ (inclk_n or ena_pll or areset_ipd)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
begin
gate_count = gate_count + 1;
if (gate_count == gate_lock_counter)
gate_out = 1;
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @(posedge scanread_ipd)
begin
scanread_active_edge = $time;
end
always @ (scanclk_ipd)
begin
if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1)
begin
// enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end
if (scanread_reg === 1'b1)
gated_scanclk <= scanclk_ipd && scanread_reg;
else
gated_scanclk <= 1'b1;
if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0)
begin
// register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk)
scanclk_period = $time - scanclk_last_rising_edge;
else begin
got_first_scanclk = 1;
end
// reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd == 1'b0 && scanread_reg == 1'b1)
begin
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
end
scanclk_last_rising_edge = $time;
end
scanclk_last_value = scanclk_ipd;
end
always @(posedge gated_scanclk)
begin
if ($time > 0)
begin
if (!got_first_gated_scanclk)
begin
got_first_gated_scanclk = 1;
// if ($time - scanread_active_edge < scanclk_period)
// begin
// scanread_setup_violation = 1;
// $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in.");
// $display ("Time: %0t Instance: %m", $time);
// end
end
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] <= scandata_ipd;
end
end
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1];
always @(posedge scandone_tmp)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : CycloneII PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
$display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old);
if (ss > 0)
begin
$display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]);
$display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]);
end
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]);
end
// display Charge pump and loop filter values
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(scanwrite_enabled)
begin
if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1)
begin
// falling edge : deassert scandone
scandone_tmp <= #(1.5*scanclk_period) 1'b0;
// reset counter transfer flags
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
end
if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled)
begin
$display ("NOTE : CycloneII PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// make temp. copy of scan_data for processing
tmp_scan_data = scan_data;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
// CP
// Bits 0-3 : all values are legal
cp_curr_val = charge_pump_curr_arr[scan_data[3:0]];
// LF Resistance : bits 4-9
// values from 010000 - 010111, 100000 - 100111,
// 110000- 110111 are illegal
if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) ||
((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) ||
((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111)))
begin
$display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work.");
reconfig_err = 1;
end
else begin
i = scan_data[9:4];
if (i >= 56 )
i = i - 24;
else if ((i >= 40) && (i <= 47))
i = i - 16;
else if ((i >= 24) && (i <= 31))
i = i - 8;
lfr_val = loop_filter_r_arr[i];
end
// LF Capacitance : bits 10,11 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]];
else
lfc_val = loop_filter_c_arr[scan_data[11:10]];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
m_ph_val_old = m_ph_val;
for (i=0; i<=5; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_ph_val_old[i] = c_ph_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// first the M counter phase : bit order same for fast and GPP
if (scan_data[12] == 1'b0)
begin
// do nothing
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1)
begin
m_ph_val_tmp = m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7)
m_ph_val_tmp = 0;
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0)
begin
m_ph_val_tmp = m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0)
m_ph_val_tmp = 7;
end
else begin
$display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work.");
reconfig_err = 1;
end
// read the fast PLL bits.
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
// C3-C0 phase bits
for (i = 3; i >= 0; i=i-1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
// C0-C3 counter moduli
tmp_scan_data = scan_data;
for (i = 0; i < 4; i=i+1)
begin
if (tmp_scan_data[26] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[31] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
end
end
else if (tmp_scan_data[31] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[25:22] === 4'b0000)
c_high_val_tmp[i] = 5'b10000;
else
c_high_val_tmp[i] = tmp_scan_data[25:22];
if (tmp_scan_data[30:27] === 4'b0000)
c_low_val_tmp[i] = 5'b10000;
else
c_low_val_tmp[i] = tmp_scan_data[30:27];
tmp_scan_data = tmp_scan_data >> 10;
end
// M
error = 0;
// some temporary storage
if (scan_data[65:62] == 4'b0000)
m_hi = 5'b10000;
else
m_hi = scan_data[65:62];
if (scan_data[70:67] == 4'b0000)
m_lo = 5'b10000;
else
m_lo = scan_data[70:67];
m_val_tmp[0] = m_hi + m_lo;
if (scan_data[66] === 1'b1)
begin
if (scan_data[71] === 1'b1)
begin
// this will turn off the M counter : error
reconfig_err = 1;
error = 1;
$display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work.");
end
else begin
// M counter is being bypassed
if (m_mode_val[0] !== "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 4);
end
m_val_tmp[0] = 32'b1;
m_mode_val[0] = "bypass";
end
end
else begin
if (m_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 1);
end
m_mode_val[0] = "";
if (scan_data[71] === 1'b1)
begin
// odd : check for duty cycle, if not 50% -- error
if (m_hi - m_lo !== 1)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the CycloneII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
end
end
else begin // even mode
if (m_hi !== m_lo)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the CycloneII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
end
end
end
// N
error = 0;
n_val[0] = scan_data[73:72];
if (scan_data[74] !== 1'b1)
begin
if (scan_data[73:72] == 2'b01)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 2);
end
else if (scan_data[73:72] == 2'b00)
n_val[0] = 3'b100;
if (error == 1'b0)
begin
if (n_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 1);
end
n_mode_val[0] = "";
end
end
else if (scan_data[74] == 1'b1) // bypass
begin
if (scan_data[72] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 3);
end
else begin
if (n_mode_val[0] != "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 4);
end
n_val[0] = 2'b01;
n_mode_val[0] = "bypass";
end
end
end
else begin // pll type is auto or enhanced
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[124] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[133] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
end
end
else if (tmp_scan_data[133] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[123:116] === 8'b00000000)
c_high_val_tmp[i] = 9'b100000000;
else
c_high_val_tmp[i] = tmp_scan_data[123:116];
if (tmp_scan_data[132:125] === 8'b00000000)
c_low_val_tmp[i] = 9'b100000000;
else
c_low_val_tmp[i] = tmp_scan_data[132:125];
tmp_scan_data = tmp_scan_data << 18;
end
// the phase_taps
tmp_scan_data = scan_data;
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
// cntrs M/M2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
m_val_tmp[i] = tmp_scan_data[142:134];
if (tmp_scan_data[143] !== 1'b1)
begin
if (tmp_scan_data[142:134] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 2);
else
d_msg = display_msg("M2", 2);
end
else if (tmp_scan_data[142:134] == 9'b000000000)
m_val_tmp[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" M", 1);
else
d_msg = display_msg("M2", 1);
end
m_mode_val[i] = "";
end
end
else if (tmp_scan_data[143] == 1'b1)
begin
if (tmp_scan_data[134] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 3);
else
d_msg = display_msg("M2", 3);
end
else begin
if (m_mode_val[i] !== "bypass")
begin
// Mode is switched: give warning
if (i == 0)
d_msg = display_msg(" M", 4);
else
d_msg = display_msg("M2", 4);
end
m_val_tmp[i] = 10'b0000000001;
m_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (m_mode_val[0] != m_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
end
end
// cntrs N/N2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
n_val[i] = tmp_scan_data[162:154];
if (tmp_scan_data[163] !== 1'b1)
begin
if (tmp_scan_data[162:154] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 2);
else
d_msg = display_msg("N2", 2);
end
else if (tmp_scan_data[162:154] == 9'b000000000)
n_val[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 1);
else
d_msg = display_msg("N2", 1);
end
n_mode_val[i] = "";
end
end
else if (tmp_scan_data[163] == 1'b1) // bypass
begin
if (tmp_scan_data[154] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 3);
else
d_msg = display_msg("N2", 3);
end
else begin
if (n_mode_val[i] != "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 4);
else
d_msg = display_msg("N2", 4);
end
n_val[i] = 10'b0000000001;
n_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (n_mode_val[0] != n_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
end
end
end
slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val[0], c_mode_val_tmp[0],
c_high_val_tmp[1]+c_low_val[1], c_mode_val_tmp[1],
c_high_val_tmp[2]+c_low_val[2], c_mode_val_tmp[2],
c_high_val_tmp[3]+c_low_val[3], c_mode_val_tmp[3],
c_high_val_tmp[4]+c_low_val[4], c_mode_val_tmp[4],
c_high_val_tmp[5]+c_low_val[5], c_mode_val_tmp[5],
refclk_period, m_val[0]);
quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old;
// get quiet time in terms of scanclk cycles
my_rem = quiet_time % scanclk_period;
scanclk_cycles = quiet_time/scanclk_period;
if (my_rem != 0)
scanclk_cycles = scanclk_cycles + 1;
scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1;
end
scanwrite_last_value = scanwrite_enabled;
end
always @(schedule_vco or areset_ipd or ena_pll)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : CycloneII PLL was reset");
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
pll_is_in_reset = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// areset deasserted : note time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
if ((ena_pll === 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// if ena was deasserted
if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : CycloneII PLL is disabled");
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
if (ena_pll == 1'b1 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : CycloneII PLL is enabled");
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 0;
if ((areset_ipd !== 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end
if ( ($time == 0 && first_schedule == 1'b1) || (schedule_vco !== schedule_vco_last_value && (stop_vco !== 1'b1) && (ena_pll === 1'b1) && (areset_ipd !== 1'b1)) )
begin
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
if (op_mode == 1)
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val[0] * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus);
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (op_mode == 1)
begin
pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_M = initial_delay + fbk_phase;
end
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
if (op_mode == 1)
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
next_vco_sched_time = $time + sched_time;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_pll;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : CycloneII PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : CycloneII PLL lost lock");
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (scanwrite_enabled === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : CycloneII PLL lost lock due to loss of input clock");
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : CycloneII PLL locked to incoming clock");
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : CycloneII PLL lost lock");
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 'b0;
assign clk_out[0] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[0] : 'bx;
assign clk_out[1] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[1] : 'bx;
assign clk_out[2] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[2] : 'bx;
assign clk_out[3] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[3] : 'bx;
assign clk_out[4] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[4] : 'bx;
assign clk_out[5] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[5] : 'bx;
assign sbdout_tmp = sbdin_ipd;
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (sbdout, 1'b1, sbdout_tmp);
endmodule // cycloneii_pll
//------------------------------------------------------------------
//
// Module Name : cycloneii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneii_routing_wire
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_ff
//
// Description : Cyclone II LCELL_FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_ff (
datain,
clk,
aclr,
sclr,
sload,
sdata,
ena,
devclrn,
devpor,
regout
);
parameter x_on_violation = "on";
parameter lpm_type = "cycloneii_lcell_ff";
input datain;
input clk;
input aclr;
input sclr;
input sload;
input sdata;
input ena;
input devclrn;
input devpor;
output regout;
reg regout_tmp;
wire reset;
reg datain_viol;
reg sclr_viol;
reg sload_viol;
reg sdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire datain_in;
wire clk_in;
wire aclr_in;
wire sclr_in;
wire sload_in;
wire sdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (datain_in, datain);
buf (clk_in, clk);
buf (aclr_in, aclr);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (sdata_in, sdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && (!aclr_in) && (ena_in);
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, sdata, 0, 0, sdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: regout_tmp)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
regout_tmp = 'b0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (datain_viol or sclr_viol or sload_viol or ena_viol or sdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (sdata_in or aclr_in or devclrn or devpor)
begin
if (devpor == 'b0)
regout_tmp <= 'b0;
else if (devclrn == 'b0)
regout_tmp <= 'b0;
else if (aclr_in == 'b1)
regout_tmp <= 'b0;
end
always @ (clk_in or posedge aclr_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
regout_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || aclr_in === 'b1)
regout_tmp <= 'b0;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
regout_tmp <= 'b0 ;
else if (sload_in === 'b1)
regout_tmp <= sdata_in;
else
regout_tmp <= datain_in;
end
end
clk_last_value = clk_in;
end
and (regout, regout_tmp, 'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_comb
//
// Description : Cyclone II LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter lpm_type = "cycloneii_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
cout_tmp = lut4(lut_mask, dataa_in, datab_in, datac_in, 'b0);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII ASYNCH IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_asynch_io (datain, oe, regin,
differentialin, differentialout,
padio, combout, regout);
input datain, oe;
input regin;
input differentialin;
output differentialout;
output combout;
output regout;
inout padio;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter use_differential_input = "false";
reg prev_value;
reg tmp_padio, tmp_combout;
reg buf_control;
wire differentialout_tmp;
wire tmp_combout_differentialin_or_pad;
wire datain_in;
wire differentialin_in;
wire oe_in;
buf(differentialin_in, differentialin);
buf(oe_in, oe);
buf(datain_in, datain);
tri padio_tmp;
specify
(padio => differentialout) = (0,0);
(differentialin => combout) = (0,0);
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio === 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 1'b0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in === 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if ( operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end // bidir or output
if ( operation_mode == "output")
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_combout = padio;
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in === 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
$display ("Error: Invalid operation_mode specified in cycloneii io atom!\n");
end
end
assign differentialout_tmp = (operation_mode == "input" || operation_mode == "bidir") ? padio : 1'bx;
assign tmp_combout_differentialin_or_pad = (use_differential_input == "true") ? differentialin_in : tmp_combout;
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, tmp_combout_differentialin_or_pad, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
pmos (differentialout, differentialout_tmp, 'b0);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_io (datain, oe, outclk, outclkena, inclk, inclkena, areset, sreset,
devclrn, devpor, devoe, linkin,
differentialin, differentialout,
padio, combout, regout, linkout);
parameter operation_mode = "input";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter lpm_type = "cycloneii_io";
parameter use_differential_input = "false";
inout padio;
input datain, oe;
input outclk, outclkena, inclk, inclkena, areset, sreset;
input devclrn, devpor, devoe;
input linkin;
input differentialin;
output differentialout;
output combout, regout;
output linkout;
wire out_reg_clk_ena, oe_reg_clk_ena;
wire tmp_oe_reg_out, tmp_input_reg_out, tmp_output_reg_out;
wire inreg_sreset_is_used, outreg_sreset_is_used, oereg_sreset_is_used;
wire inreg_sreset, outreg_sreset, oereg_sreset;
wire in_reg_aclr, in_reg_apreset;
wire oe_reg_aclr, oe_reg_apreset, oe_reg_sel;
wire out_reg_aclr, out_reg_apreset, out_reg_sel;
wire input_reg_pu_low, output_reg_pu_low, oe_reg_pu_low;
wire inreg_D, outreg_D, oereg_D;
wire tmp_datain, tmp_oe;
wire iareset, isreset;
wire pad_or_differentialin;
assign pad_or_differentialin = (use_differential_input == "true") ? differentialin : padio;
assign input_reg_pu_low = ( input_power_up == "low") ? 'b0 : 'b1;
assign output_reg_pu_low = ( output_power_up == "low") ? 'b0 : 'b1;
assign oe_reg_pu_low = ( oe_power_up == "low") ? 'b0 : 'b1;
assign out_reg_sel = (output_register_mode == "register" ) ? 'b1 : 'b0;
assign oe_reg_sel = ( oe_register_mode == "register" ) ? 'b1 : 'b0;
assign iareset = ( areset === 'b0 || areset === 'b1 ) ? !areset : 'b1;
assign isreset = ( sreset === 'b0 || sreset === 'b1 ) ? sreset : 'b0;
// output register signals
assign out_reg_aclr = (output_async_reset == "clear") ? iareset : 'b1;
assign out_reg_apreset = ( output_async_reset == "preset") ? iareset : 'b1;
assign outreg_sreset_is_used = ( output_sync_reset == "none") ? 'b0 : 'b1;
assign outreg_sreset = (output_sync_reset == "clear") ? 'b0 : 'b1;
// oe register signals
assign oe_reg_aclr = ( oe_async_reset == "clear") ? iareset : 'b1;
assign oe_reg_apreset = ( oe_async_reset == "preset") ? iareset : 'b1;
assign oereg_sreset_is_used = ( oe_sync_reset == "none") ? 'b0 : 'b1;
assign oereg_sreset = (oe_sync_reset == "clear") ? 'b0 : 'b1;
// input register signals
assign in_reg_aclr = ( input_async_reset == "clear") ? iareset : 'b1;
assign in_reg_apreset = ( input_async_reset == "preset") ? iareset : 'b1;
assign inreg_sreset_is_used = ( input_sync_reset == "none") ? 'b0 : 'b1;
assign inreg_sreset = (input_sync_reset == "clear") ? 'b0 : 'b1;
// oe and output register clock enable signals
assign out_reg_clk_ena = ( tie_off_output_clock_enable == "true") ? 'b1 : outclkena;
assign oe_reg_clk_ena = ( tie_off_oe_clock_enable == "true") ? 'b1 : outclkena;
// input reg
cycloneii_mux21 inreg_D_mux (.MO (inreg_D),
.A (pad_or_differentialin),
.B (inreg_sreset),
.S (isreset && inreg_sreset_is_used));
cycloneii_dffe input_reg (.Q (tmp_input_reg_out),
.CLK (inclk),
.ENA (inclkena),
.D (inreg_D),
.CLRN (in_reg_aclr && devclrn && (input_reg_pu_low || devpor)),
.PRN (in_reg_apreset && (!input_reg_pu_low || devpor)));
//output reg
cycloneii_mux21 outreg_D_mux (.MO (outreg_D),
.A (datain),
.B (outreg_sreset),
.S (isreset && outreg_sreset_is_used));
cycloneii_dffe output_reg (.Q (tmp_output_reg_out),
.CLK (outclk),
.ENA (out_reg_clk_ena),
.D (outreg_D),
.CLRN (out_reg_aclr && devclrn && (output_reg_pu_low || devpor)),
.PRN (out_reg_apreset && (!output_reg_pu_low || devpor)));
//oe reg
cycloneii_mux21 oereg_D_mux (.MO (oereg_D),
.A (oe),
.B (oereg_sreset),
.S (isreset && oereg_sreset_is_used));
cycloneii_dffe oe_reg (.Q (tmp_oe_reg_out),
.CLK (outclk),
.ENA (oe_reg_clk_ena),
.D (oereg_D),
.CLRN (oe_reg_aclr && devclrn && (oe_reg_pu_low || devpor)),
.PRN (oe_reg_apreset && (!oe_reg_pu_low || devpor)));
// asynchronous block
assign tmp_oe = (oe_reg_sel == 'b1) ? tmp_oe_reg_out : oe;
assign tmp_datain = ((operation_mode == "output" || operation_mode == "bidir") && out_reg_sel == 'b1 ) ? tmp_output_reg_out : datain;
cycloneii_asynch_io asynch_inst(.datain(tmp_datain),
.oe(tmp_oe),
.regin(tmp_input_reg_out),
.differentialin(differentialin),
.differentialout(differentialout),
.padio(padio),
.combout(combout),
.regout(regout));
defparam asynch_inst.operation_mode = operation_mode;
defparam asynch_inst.bus_hold = bus_hold;
defparam asynch_inst.open_drain_output = open_drain_output;
defparam asynch_inst.use_differential_input = use_differential_input;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_ctrl
//
// Description : Cycloneii CLK DELAY CTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_ctrl (
clk,
delayctrlin,
disablecalibration,
pllcalibrateclkdelayedin,
devpor,
devclrn,
clkout
);
input clk;
input [5:0] delayctrlin;
input disablecalibration;
input pllcalibrateclkdelayedin;
input devpor;
input devclrn;
output clkout;
parameter behavioral_sim_delay = 0;
parameter delay_chain = "54"; // or "1362ps"
parameter delay_chain_mode = "static";
parameter uses_calibration = "false";
parameter use_new_style_dq_detection = "false";
parameter tan_delay_under_delay_ctrl_signal = "unused";
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_ctrl";
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TMP OUTPUTS
wire clk_out_w;
wire clk_after_calib_mux_w;
reg clk_after_dly_chain_r;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
// TIMING HOOKS
wire clk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
wire pllcalibrateclkdelayed_in;
buf (clk_in, clk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
buf (pllcalibrateclkdelayed_in, pllcalibrateclkdelayedin);
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(clk => clkout) = (0,0);
(disablecalibration => clkout) = (0,0);
(pllcalibrateclkdelayedin => clkout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
// dly_table_r = delay_ctrl_sim_delay_all_r;
for (i=0; i<64; i=i+1)
begin
// dly_table_r[i] = delay_ctrl_sim_delay_all_r[32*i+31 : 32*i];
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generating post delay chain clock
always @(clk_in)
begin
if (delay_chain_mode == "dynamic")
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) clk_in;
else if (delay_chain_mode == "static")
clk_after_dly_chain_r <= #(behavioral_sim_delay) clk_in;
end
// generating post calib mux clock
assign clk_after_calib_mux_w = (uses_calibration == "true" && disablecalibration_in === 1'b0) ?
pllcalibrateclkdelayed_in : clk_after_dly_chain_r;
// final clock
assign clk_out_w = (delay_chain_mode == "none") ? clk_in : clk_after_calib_mux_w;
and (clkout, clk_out_w, 1'b1);
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_cal_ctrl
//
// Description : Cycloneii CLK DELAY CALIBRATION CTRL Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_cal_ctrl(
pllcalibrateclk, plldataclk, delayctrlin, disablecalibration,
devclrn, devpor,
calibratedata, pllcalibrateclkdelayedout);
input pllcalibrateclk;
input plldataclk;
input [5:0] delayctrlin;
input disablecalibration;
input devclrn;
input devpor;
output calibratedata;
output pllcalibrateclkdelayedout;
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_cal_ctrl";
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TIMING HOOKS
wire plldataclk_in;
wire pllcalibrateclk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
buf (plldataclk_in, plldataclk);
buf (pllcalibrateclk_in, pllcalibrateclk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
// TMP OUTPUTS
wire cal_clk_out_w;
wire cal_data_out_w;
reg clk_after_dly_chain_r;
reg cal_clk_by2_r;
reg cal_data_by2_r;
reg cal_clk_prev;
reg cal_data_prev;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(plldataclk => calibratedata) = (0,0);
(disablecalibration => calibratedata) = (0,0);
(pllcalibrateclk => pllcalibrateclkdelayedout) = (0,0);
(disablecalibration => pllcalibrateclkdelayedout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
for (i=0; i<64; i=i+1)
begin
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CAL_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generate divided by 2 clocks
initial
begin
cal_clk_by2_r = 1'b0;
end
always @(pllcalibrateclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_clk_prev <= 1'bx;
cal_clk_by2_r <= 1'b0;
end
else
begin
cal_clk_prev <= pllcalibrateclk_in;
if (pllcalibrateclk_in === 1'b1 && cal_clk_prev === 1'b0)
cal_clk_by2_r <= ~cal_clk_by2_r;
end
end
initial
begin
cal_data_by2_r = 1'b0;
end
always @(plldataclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_data_prev <= 1'bx;
cal_data_by2_r <= 1'b0;
end
else
begin
cal_data_prev <= plldataclk_in;
if (plldataclk_in === 1'b1 && cal_data_prev === 1'b0)
cal_data_by2_r <= ~cal_data_by2_r;
end
end
// generating post delay chain clock
always @(cal_clk_by2_r)
begin
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) cal_clk_by2_r;
end
// final clocks
assign cal_clk_out_w = clk_after_dly_chain_r;
assign cal_data_out_w = cal_data_by2_r;
and (calibratedata, cal_data_out_w, 1'b1);
and (pllcalibrateclkdelayedout, cal_clk_out_w, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
end
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_clkctrl
//
// Description : Cycloneii CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneii_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg_out; // output of ENA register
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
cycloneii_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneii_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg_out : ena_ipd;
and (outclk, ena_out, clkmux_out);
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone II MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneii_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone II MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult_internal
//
// Description : Cyclone II MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult
//
// Description : Cyclone II MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_mult";
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneii_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneii_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneii_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneii_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneii_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_out
//
// Description : Cyclone II MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter dataout_width = dataa_width;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_out";
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// this file is provided "as is", without warranty of any kind, express or
// implied, including but not limited to the warranties of merchantability,
// fitness for a particular purpose and noninfringement. in no event shall
// the authors or copyright holders be liable for any claim, damages or other
// liability, whether in an action of contract, tort or otherwise, arising
// from, out of or in connection with this file or the use or other dealings
// in this file.
/******************************************************************************
* *
* this module scales video streams on the de boards. *
* *
******************************************************************************/
module raster_laser_projector_video_in_video_scaler_0 (
// inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// bidirectional
// outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* parameter declarations *
*****************************************************************************/
parameter cw = 0; // frame's channel width
parameter dw = 7; // frame's data width
parameter ew = 0; // frame's empty width
parameter wiw = 9; // incoming frame's width's address width
parameter hiw = 7; // incoming frame's height's address width
parameter width_in = 640;
parameter width_drop_mask = 4'b0000;
parameter height_drop_mask = 4'b0000;
parameter mh_ww = 9; // multiply height's incoming width's address width
parameter mh_width_in = 640; // multiply height's incoming width
parameter mh_cw = 0; // multiply height's counter width
parameter mw_cw = 0; // multiply width's counter width
/*****************************************************************************
* port declarations *
*****************************************************************************/
// inputs
input clk;
input reset;
input [dw: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [ew: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// bidirectional
// outputs
output stream_in_ready;
output [cw: 0] stream_out_channel;
output [dw: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [ew: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* constant declarations *
*****************************************************************************/
/*****************************************************************************
* internal wires and registers declarations *
*****************************************************************************/
// internal wires
wire [cw: 0] internal_channel;
wire [dw: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// internal registers
// state machine registers
// integers
/*****************************************************************************
* finite state machine(s) *
*****************************************************************************/
/*****************************************************************************
* sequential logic *
*****************************************************************************/
// output registers
// internal registers
/*****************************************************************************
* combinational logic *
*****************************************************************************/
// output assignments
assign stream_out_empty = 'h0;
// internal assignments
/*****************************************************************************
* internal modules *
*****************************************************************************/
altera_up_video_scaler_multiply_height multiply_height (
// inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// bi-directional
// outputs
.stream_in_ready (stream_in_ready),
.stream_out_channel (stream_out_channel),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
multiply_height.dw = dw,
multiply_height.ww = mh_ww,
multiply_height.width = mh_width_in,
multiply_height.mcw = mh_cw;
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdata_path
# (
// module parameter port list
parameter
cfg_local_data_width = 8,
cfg_int_size_width = 2,
cfg_data_id_width = 3, // number of buckets
cfg_local_id_width = 3,
cfg_local_addr_width = 32,
cfg_buffer_addr_width = 5,
cfg_mem_if_cs_width = 2,
cfg_mem_if_ba_width = 3,
cfg_mem_if_row_width = 13,
cfg_mem_if_col_width = 10,
cfg_max_read_cmd_num_width = 4, // expected in-flight read commands at a time
cfg_rdata_return_mode = "passthrough", // inorder, passthrough
cfg_afi_intf_phase_num = 2,
cfg_errcmd_fifo_addr_width = 3,
cfg_dwidth_ratio = 2,
cfg_ecc_multiples = 1,
cfg_ecc_code_width = 8,
cfg_port_width_type = 3,
cfg_port_width_enable_ecc = 1,
cfg_port_width_enable_auto_corr = 1,
cfg_port_width_enable_no_dm = 1,
cfg_port_width_burst_length = 5,
cfg_port_width_addr_order = 2,
cfg_port_width_col_addr_width = 9,
cfg_port_width_row_addr_width = 12,
cfg_port_width_bank_addr_width = 3,
cfg_port_width_cs_addr_width = 2,
cfg_errcmd_fifo_reg = 1 // set 1 to improve timing for errcmd_fifo
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration
cfg_type,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_burst_length,
cfg_addr_order,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width,
// command generator & tbp command load interface / cmd update interface
rdatap_free_id_valid,
rdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_read,
proc_size,
proc_localid,
// input interface data channel / buffer read interface
read_data_valid, // data sent to either dataid_manager, or input interface
read_data,
read_data_error,
read_data_localid,
// arbiter issued reads interface
bg_do_read,
bg_to_chipsel,
bg_to_bank,
bg_to_row,
bg_to_column,
bg_dataid,
bg_localid,
bg_size,
bg_do_rmw_correct,
bg_do_rmw_partial,
// read data from memory interface
ecc_rdata,
ecc_rdatav,
ecc_sbe,
ecc_dbe,
ecc_code,
// ecc error commands interface, to command generator
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
// ecc error address interface, to ecc block
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// rmw fifo interface, to wdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam cfg_ecc_rdata_counter_reg = 0; // set to 1 to improve timing
localparam cfg_rmw_bit_width = 1;
localparam cfg_rmw_partial_bit_width = 1;
localparam cfg_pending_rd_fifo_width = cfg_mem_if_cs_width + cfg_mem_if_ba_width + cfg_mem_if_row_width + cfg_mem_if_col_width + cfg_local_id_width + cfg_int_size_width + cfg_data_id_width + cfg_rmw_bit_width + cfg_rmw_partial_bit_width;
localparam cfg_errcmd_fifo_width = cfg_mem_if_cs_width + cfg_mem_if_ba_width + cfg_mem_if_row_width + cfg_mem_if_col_width + cfg_int_size_width + cfg_local_id_width;
localparam cfg_inorder_info_fifo_width = cfg_int_size_width+cfg_local_id_width;
localparam integer cfg_dataid_array_depth = 2**cfg_data_id_width;
localparam cfg_rdata_error_width = 1;
localparam cfg_in_order_buffer_data_width = cfg_local_data_width + cfg_rdata_error_width;
localparam cfg_max_read_cmd_num = 2**cfg_max_read_cmd_num_width;
localparam min_col = 8;
localparam min_row = 12;
localparam min_bank = 2;
localparam min_cs = 1;
localparam max_col = cfg_mem_if_col_width;
localparam max_row = cfg_mem_if_row_width;
localparam max_bank = cfg_mem_if_ba_width;
localparam max_cs = cfg_mem_if_cs_width;
localparam cfg_ignore_num_bits_col = log2 (cfg_dwidth_ratio);
localparam cfg_local_addr_bitselect_width = log2 (cfg_local_addr_width);
integer j,k,m,n;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// configuration
input [cfg_port_width_type- 1:0] cfg_type;
input [cfg_port_width_enable_ecc-1:0] cfg_enable_ecc;
input [cfg_port_width_enable_auto_corr-1:0] cfg_enable_auto_corr;
input [cfg_port_width_enable_no_dm-1:0] cfg_enable_no_dm;
input [cfg_port_width_burst_length-1:0] cfg_burst_length;
input [cfg_port_width_addr_order - 1 : 0] cfg_addr_order;
input [cfg_port_width_col_addr_width - 1 : 0] cfg_col_addr_width;
input [cfg_port_width_row_addr_width - 1 : 0] cfg_row_addr_width;
input [cfg_port_width_bank_addr_width - 1 : 0] cfg_bank_addr_width;
input [cfg_port_width_cs_addr_width - 1 : 0] cfg_cs_addr_width;
// command generator & tbp command load interface / cmd update interface
output rdatap_free_id_valid;
output [cfg_data_id_width-1:0] rdatap_free_id_dataid;
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_read;
input [cfg_int_size_width-1:0] proc_size;
input [cfg_local_id_width-1:0] proc_localid;
// input interface data channel
output read_data_valid;
output [cfg_local_data_width-1:0] read_data;
output read_data_error;
output [cfg_local_id_width-1:0] read_data_localid;
// arbiter issued reads interface
input [cfg_afi_intf_phase_num-1:0] bg_do_read;
input [cfg_afi_intf_phase_num-1:0] bg_do_rmw_correct;
input [cfg_afi_intf_phase_num-1:0] bg_do_rmw_partial;
input [(cfg_afi_intf_phase_num*cfg_mem_if_cs_width ) -1:0] bg_to_chipsel;
input [(cfg_afi_intf_phase_num*cfg_mem_if_ba_width ) -1:0] bg_to_bank;
input [(cfg_afi_intf_phase_num*cfg_mem_if_row_width ) -1:0] bg_to_row;
input [(cfg_afi_intf_phase_num*cfg_mem_if_col_width ) -1:0] bg_to_column;
input [( cfg_data_id_width ) -1:0] bg_dataid;
input [( cfg_local_id_width ) -1:0] bg_localid;
input [( cfg_int_size_width ) -1:0] bg_size;
// read data from memory interface
input [cfg_local_data_width-1:0] ecc_rdata;
input ecc_rdatav;
input [cfg_ecc_multiples - 1 : 0] ecc_sbe;
input [cfg_ecc_multiples - 1 : 0] ecc_dbe;
input [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] ecc_code;
// ecc error commands interface, to command generator
input errcmd_ready;
output errcmd_valid;
output [cfg_mem_if_cs_width-1:0] errcmd_chipsel;
output [cfg_mem_if_ba_width-1:0] errcmd_bank;
output [cfg_mem_if_row_width-1:0] errcmd_row;
output [cfg_mem_if_col_width-1:0] errcmd_column;
output [cfg_int_size_width-1:0] errcmd_size;
output [cfg_local_id_width-1:0] errcmd_localid;
// ecc error address interface, to ecc block
output [cfg_local_addr_width-1:0] rdatap_rcvd_addr;
output rdatap_rcvd_cmd;
output rdatap_rcvd_corr_dropped;
// rmw fifo interface, to wdatap
output rmwfifo_data_valid;
output [cfg_local_data_width-1:0] rmwfifo_data;
output [cfg_ecc_multiples - 1 : 0] rmwfifo_ecc_dbe;
output [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// configuration
wire [cfg_port_width_type- 1:0] cfg_type;
wire [cfg_port_width_enable_ecc-1:0] cfg_enable_ecc;
wire [cfg_port_width_enable_auto_corr-1:0] cfg_enable_auto_corr;
wire [cfg_port_width_burst_length-1:0] cfg_burst_length;
wire [cfg_port_width_addr_order - 1 : 0] cfg_addr_order;
wire [cfg_port_width_col_addr_width - 1 : 0] cfg_col_addr_width;
wire [cfg_port_width_row_addr_width - 1 : 0] cfg_row_addr_width;
wire [cfg_port_width_bank_addr_width - 1 : 0] cfg_bank_addr_width;
wire [cfg_port_width_cs_addr_width - 1 : 0] cfg_cs_addr_width;
// command generator & tbp command load interface / cmd update interface
reg rdatap_free_id_valid;
reg [cfg_data_id_width-1:0] rdatap_free_id_dataid;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_read;
wire [cfg_int_size_width-1:0] proc_size;
wire [cfg_local_id_width-1:0] proc_localid;
// input interface data channel
reg read_data_valid;
reg [cfg_local_data_width-1:0] read_data;
reg read_data_error;
reg [cfg_local_id_width-1:0] read_data_localid;
// arbiter issued reads interface
wire [cfg_afi_intf_phase_num-1:0] bg_do_read;
wire [cfg_afi_intf_phase_num-1:0] bg_do_rmw_correct;
wire [cfg_afi_intf_phase_num-1:0] bg_do_rmw_partial;
wire [(cfg_afi_intf_phase_num*cfg_mem_if_cs_width ) -1:0] bg_to_chipsel;
wire [(cfg_afi_intf_phase_num*cfg_mem_if_ba_width ) -1:0] bg_to_bank;
wire [(cfg_afi_intf_phase_num*cfg_mem_if_row_width ) -1:0] bg_to_row;
wire [(cfg_afi_intf_phase_num*cfg_mem_if_col_width ) -1:0] bg_to_column;
wire [( cfg_data_id_width ) -1:0] bg_dataid;
wire [( cfg_local_id_width ) -1:0] bg_localid;
wire [( cfg_int_size_width ) -1:0] bg_size;
reg [cfg_afi_intf_phase_num-1:0] int_bg_do_read;
reg [cfg_afi_intf_phase_num-1:0] int_bg_do_rmw_correct;
reg [cfg_afi_intf_phase_num-1:0] int_bg_do_rmw_partial;
reg [cfg_mem_if_cs_width -1:0] int_bg_to_chipsel[cfg_afi_intf_phase_num-1:0];
reg [cfg_mem_if_ba_width -1:0] int_bg_to_bank [cfg_afi_intf_phase_num-1:0];
reg [cfg_mem_if_row_width -1:0] int_bg_to_row [cfg_afi_intf_phase_num-1:0];
reg [cfg_mem_if_col_width -1:0] int_bg_to_column [cfg_afi_intf_phase_num-1:0];
reg [cfg_data_id_width -1:0] int_bg_dataid;
reg [cfg_local_id_width -1:0] int_bg_localid;
reg [cfg_int_size_width -1:0] int_bg_size;
// read data from memory interface
wire [cfg_local_data_width-1:0] ecc_rdata;
wire ecc_rdatav;
wire [cfg_ecc_multiples- 1 : 0] ecc_sbe;
wire [cfg_ecc_multiples- 1 : 0] ecc_dbe;
wire [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] ecc_code;
// ecc error commands interface, to command generator
wire errcmd_ready;
wire errcmd_valid;
wire [cfg_mem_if_cs_width-1:0] errcmd_chipsel;
wire [cfg_mem_if_ba_width-1:0] errcmd_bank;
wire [cfg_mem_if_row_width-1:0] errcmd_row;
wire [cfg_mem_if_col_width-1:0] errcmd_column;
wire [cfg_int_size_width-1:0] errcmd_size;
wire [cfg_local_id_width-1:0] errcmd_localid;
// rmw fifo interface, to wdatap
wire rmwfifo_data_valid;
wire [cfg_local_data_width-1:0] rmwfifo_data;
wire [cfg_ecc_multiples- 1 : 0] rmwfifo_ecc_dbe;
wire [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] rmwfifo_ecc_code;
reg rdatap_rcvd_cmd;
reg rdatap_rcvd_corr_dropped;
// -----------------------------
// signal declaration
// -----------------------------
wire[cfg_int_size_width-1:0] cfg_max_cmd_burstcount;
reg [cfg_local_addr_bitselect_width -1 : 0] cfg_addr_bitsel_chipsel;
reg [cfg_local_addr_bitselect_width -1 : 0] cfg_addr_bitsel_bank;
reg [cfg_local_addr_bitselect_width -1 : 0] cfg_addr_bitsel_row;
wire cmdload_valid;
reg [cfg_max_read_cmd_num_width-1:0] cmd_counter;
reg cmd_counter_full;
wire cmd_counter_load;
wire free_id_get_ready;
wire free_id_valid;
wire [cfg_data_id_width-1:0] free_id_dataid;
wire [cfg_dataid_array_depth-1:0]free_id_dataid_vector;
wire allocated_put_ready;
wire allocated_put_valid;
wire int_free_id_valid;
wire [cfg_pending_rd_fifo_width-1:0] pfifo_input;
wire [cfg_pending_rd_fifo_width-1:0] pfifo_output;
wire pfifo_output_valid;
wire pfifo_input_ready;
wire rdata_burst_complete;
reg rdata_burst_complete_r;
reg rout_data_valid; // rout_data sent to dataid_manager
reg rout_cmd_valid; // rout_cmd sent to dataid_manager
reg rout_data_rmwfifo_valid; // rout_data sent to rmwfifo
reg rout_cmd_rmwfifo_valid; // rout_cmd sent to rmwfifo
wire rout_rmw_rmwpartial;
reg rout_data_error;
reg rout_sbecmd_valid;
reg rout_errnotify_valid;
wire [cfg_local_data_width-1:0] rout_data;
wire [cfg_data_id_width-1:0] rout_data_dataid;
wire [cfg_local_id_width-1:0] rout_data_localid;
wire [cfg_int_size_width-1:0] rout_data_burstcount;
wire [cfg_ecc_multiples- 1 : 0] rout_ecc_dbe;
wire [cfg_ecc_multiples * cfg_ecc_code_width - 1 : 0] rout_ecc_code;
reg pfifo_input_do_read;
reg pfifo_input_rmw;
reg pfifo_input_rmw_partial;
reg [cfg_mem_if_cs_width-1:0] pfifo_input_chipsel;
reg [cfg_mem_if_ba_width-1:0] pfifo_input_bank;
reg [cfg_mem_if_row_width-1:0] pfifo_input_row;
reg [cfg_mem_if_col_width-1:0] pfifo_input_column;
reg [cfg_data_id_width-1:0] pfifo_input_dataid;
reg [cfg_local_id_width-1:0] pfifo_input_localid;
reg [cfg_int_size_width-1:0] pfifo_input_size;
reg mux_pfifo_input_rmw [cfg_afi_intf_phase_num -1 : 0];
reg mux_pfifo_input_rmw_partial [cfg_afi_intf_phase_num -1 : 0];
reg [cfg_mem_if_cs_width-1:0] mux_pfifo_input_chipsel [cfg_afi_intf_phase_num -1 : 0];
reg [cfg_mem_if_ba_width-1:0] mux_pfifo_input_bank [cfg_afi_intf_phase_num -1 : 0];
reg [cfg_mem_if_row_width-1:0] mux_pfifo_input_row [cfg_afi_intf_phase_num -1 : 0];
reg [cfg_mem_if_col_width-1:0] mux_pfifo_input_column [cfg_afi_intf_phase_num -1 : 0];
wire pfifo_rmw;
wire pfifo_rmw_partial;
wire [cfg_mem_if_cs_width-1:0] pfifo_chipsel;
wire [cfg_mem_if_ba_width-1:0] pfifo_bank;
wire [cfg_mem_if_row_width-1:0] pfifo_row;
wire [cfg_mem_if_col_width-1:0] pfifo_column;
wire [cfg_mem_if_col_width-1:0] pfifo_column_burst_aligned;
reg [cfg_mem_if_cs_width-1:0] pfifo_chipsel_r;
reg [cfg_mem_if_ba_width-1:0] pfifo_bank_r;
reg [cfg_mem_if_row_width-1:0] pfifo_row_r;
reg [cfg_mem_if_col_width-1:0] pfifo_column_r;
reg [cfg_mem_if_col_width-1:0] pfifo_column_burst_aligned_r;
wire [cfg_data_id_width-1:0] pfifo_dataid;
wire [cfg_local_id_width-1:0] pfifo_localid;
wire [cfg_int_size_width-1:0] pfifo_size;
reg [cfg_local_addr_width-1:0] pfifo_addr;
wire [cfg_int_size_width-1:0] ecc_rdata_current_count;
reg [cfg_int_size_width-1:0] ecc_rdata_counter;
wire [cfg_int_size_width-1:0] ecc_rdatavalid_count;
wire [cfg_int_size_width-1:0] ecc_rdata_burst_complete_count;
reg ecc_sbe_cmd_detected;
reg ecc_dbe_cmd_detected;
wire [cfg_dataid_array_depth-1:0] dataid_array_valid;
reg [cfg_dataid_array_depth-1:0] dataid_array_data_ready;
reg [cfg_buffer_addr_width-1:0] dataid_array_burstcount [cfg_dataid_array_depth-1:0];
reg [cfg_local_id_width-1:0] dataid_array_localid [cfg_dataid_array_depth-1:0];
wire inordr_id_data_complete;
reg inordr_id_data_complete_r;
wire inordr_id_valid;
wire inordr_id_list_valid;
wire inordr_read_data_valid;
reg inordr_read_data_valid_r;
wire [cfg_local_data_width-1:0] inordr_read_data;
wire inordr_read_data_error;
wire [cfg_data_id_width-1:0] inordr_id_dataid;
wire [cfg_dataid_array_depth-1:0] inordr_id_dataid_vector;
wire [cfg_local_id_width-1:0] inordr_id_localid;
reg [cfg_local_id_width-1:0] inordr_id_localid_r;
reg [cfg_int_size_width-1:0] inordr_data_counter;
reg [cfg_int_size_width-1:0] inordr_data_counter_plus_1;
wire [cfg_int_size_width-1:0] inordr_next_data_counter;
wire [cfg_int_size_width-1:0] inordr_id_expected_burstcount;
reg [cfg_dataid_array_depth-1:0] mux_inordr_data_ready;
wire inordr_info_input_ready;
wire inordr_info_output_valid;
wire [cfg_inorder_info_fifo_width-1:0] inordr_info_input;
wire [cfg_inorder_info_fifo_width-1:0] inordr_info_output;
wire [cfg_buffer_addr_width-1:0] buffwrite_address;
wire [cfg_int_size_width-1:0] buffwrite_offset;
wire [cfg_in_order_buffer_data_width-1:0] buffwrite_data;
wire [cfg_buffer_addr_width-1:0] buffread_address;
wire [cfg_int_size_width-1:0] buffread_offset;
wire [cfg_in_order_buffer_data_width-1:0] buffread_data;
wire int_ecc_sbe;
wire int_ecc_dbe;
wire errcmd_fifo_in_cmddropped;
reg errcmd_fifo_in_cmddropped_r;
wire errcmd_fifo_in_ready;
wire errcmd_fifo_in_valid_wire;
wire [cfg_errcmd_fifo_width-1:0] errcmd_fifo_in_wire;
wire [cfg_errcmd_fifo_width-1:0] errcmd_fifo_out;
reg errcmd_fifo_in_valid;
reg [cfg_errcmd_fifo_width-1:0] errcmd_fifo_in;
// -----------------------------
// module definition
// -----------------------------
//
// read data main output mux
//
generate
begin : gen_rdata_output_mux
if (cfg_rdata_return_mode == "passthrough")
begin
always @ (*)
begin
read_data_valid = rout_data_valid;
read_data = rout_data;
read_data_error = rout_data_error;
read_data_localid = rout_data_localid;
rdatap_free_id_valid = ~cmd_counter_full;
rdatap_free_id_dataid = 0;
end
end
else
begin
always @ (*)
begin
read_data_valid = inordr_read_data_valid_r;
read_data = inordr_read_data;
read_data_error = inordr_read_data_error;
read_data_localid = inordr_id_localid_r;
rdatap_free_id_valid = ~cmd_counter_full & free_id_valid;
rdatap_free_id_dataid = free_id_dataid;
end
end
end
endgenerate
//
// rdata_router
//
// mux to select correct burst gen output phase for read command
// assumes bg_do_read only asserted for 1 of the cfg_afi_intf_phase_num
genvar rdp_k;
generate
for (rdp_k = 0; rdp_k < cfg_afi_intf_phase_num; rdp_k = rdp_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_read [rdp_k] = bg_do_read [rdp_k];
int_bg_do_rmw_correct [rdp_k] = bg_do_rmw_correct [rdp_k];
int_bg_do_rmw_partial [rdp_k] = bg_do_rmw_partial [rdp_k];
int_bg_to_chipsel [rdp_k] = bg_to_chipsel [(((rdp_k+1)*cfg_mem_if_cs_width )-1):(rdp_k*cfg_mem_if_cs_width )];
int_bg_to_bank [rdp_k] = bg_to_bank [(((rdp_k+1)*cfg_mem_if_ba_width )-1):(rdp_k*cfg_mem_if_ba_width )];
int_bg_to_row [rdp_k] = bg_to_row [(((rdp_k+1)*cfg_mem_if_row_width)-1):(rdp_k*cfg_mem_if_row_width)];
int_bg_to_column [rdp_k] = bg_to_column [(((rdp_k+1)*cfg_mem_if_col_width)-1):(rdp_k*cfg_mem_if_col_width)];
end
end
endgenerate
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
end
always @ (*)
begin
mux_pfifo_input_rmw [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_correct [0] : 0;
mux_pfifo_input_rmw_partial [0] = (int_bg_do_read [0]) ? int_bg_do_rmw_partial [0] : 0;
mux_pfifo_input_chipsel [0] = (int_bg_do_read [0]) ? int_bg_to_chipsel [0] : 0;
mux_pfifo_input_bank [0] = (int_bg_do_read [0]) ? int_bg_to_bank [0] : 0;
mux_pfifo_input_row [0] = (int_bg_do_read [0]) ? int_bg_to_row [0] : 0;
mux_pfifo_input_column [0] = (int_bg_do_read [0]) ? int_bg_to_column [0] : 0;
end
genvar rdp_j;
generate
for (rdp_j = 1; rdp_j < cfg_afi_intf_phase_num; rdp_j = rdp_j + 1)
begin : gen_bg_afi_phase_mux
always @ (*)
begin
mux_pfifo_input_rmw [rdp_j] = mux_pfifo_input_rmw [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_correct [rdp_j] : 0);
mux_pfifo_input_rmw_partial [rdp_j] = mux_pfifo_input_rmw_partial [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_do_rmw_partial [rdp_j] : 0);
mux_pfifo_input_chipsel [rdp_j] = mux_pfifo_input_chipsel [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_chipsel [rdp_j] : 0);
mux_pfifo_input_bank [rdp_j] = mux_pfifo_input_bank [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_bank [rdp_j] : 0);
mux_pfifo_input_row [rdp_j] = mux_pfifo_input_row [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_row [rdp_j] : 0);
mux_pfifo_input_column [rdp_j] = mux_pfifo_input_column [rdp_j - 1] | ((int_bg_do_read [rdp_j]) ? int_bg_to_column [rdp_j] : 0);
end
end
endgenerate
always @ (*)
begin
pfifo_input_do_read = |int_bg_do_read;
pfifo_input_rmw = mux_pfifo_input_rmw [cfg_afi_intf_phase_num-1];
pfifo_input_rmw_partial = mux_pfifo_input_rmw_partial [cfg_afi_intf_phase_num-1];
pfifo_input_chipsel = mux_pfifo_input_chipsel [cfg_afi_intf_phase_num-1];
pfifo_input_bank = mux_pfifo_input_bank [cfg_afi_intf_phase_num-1];
pfifo_input_row = mux_pfifo_input_row [cfg_afi_intf_phase_num-1];
pfifo_input_column = mux_pfifo_input_column [cfg_afi_intf_phase_num-1];
pfifo_input_dataid = int_bg_dataid ;
pfifo_input_localid = int_bg_localid ;
pfifo_input_size = int_bg_size ;
end
// format for pfifo_input & pfifo_output must be same
assign pfifo_input = {pfifo_input_chipsel, pfifo_input_bank, pfifo_input_row, pfifo_input_column, pfifo_input_localid, pfifo_input_size, pfifo_input_rmw, pfifo_input_rmw_partial, pfifo_input_dataid};
assign {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column, pfifo_localid, pfifo_size, pfifo_rmw, pfifo_rmw_partial, pfifo_dataid} = pfifo_output;
// read data for this command has been fully received from memory
assign rdata_burst_complete = (pfifo_output_valid & (pfifo_size == ecc_rdata_current_count)) ? 1 : 0;
alt_mem_ddrx_fifo
#(
.ctl_fifo_data_width (cfg_pending_rd_fifo_width),
.ctl_fifo_addr_width (cfg_max_read_cmd_num_width)
)
pending_rd_fifo
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rdata_burst_complete),
.get_valid (pfifo_output_valid),
.get_data (pfifo_output),
.put_ready (pfifo_input_ready), // no back-pressure allowed
.put_valid (pfifo_input_do_read),
.put_data (pfifo_input)
);
assign cmd_counter_load = ~proc_busy & proc_load & proc_read;
assign cmdload_valid = cmd_counter_load & proc_load_dataid;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cmd_counter <= 0;
cmd_counter_full <= 1'b0;
end
else
begin
if (cmd_counter_load & rdata_burst_complete)
begin
cmd_counter <= cmd_counter;
cmd_counter_full <= cmd_counter_full;
end
else if (cmd_counter_load)
begin
cmd_counter <= cmd_counter + 1;
if (cmd_counter == {{(cfg_max_read_cmd_num_width - 1){1'b1}}, 1'b0}) // when cmd counter is counting up to all_ones
begin
cmd_counter_full <= 1'b1;
end
else
begin
cmd_counter_full <= 1'b0;
end
end
else if (rdata_burst_complete)
begin
cmd_counter <= cmd_counter - 1;
cmd_counter_full <= 1'b0;
end
end
end
assign rout_data = ecc_rdata;
assign rout_data_dataid = pfifo_dataid;
assign rout_data_localid = pfifo_localid;
assign rout_data_burstcount = ecc_rdata_current_count;
assign rout_rmw_rmwpartial = (pfifo_rmw | pfifo_rmw_partial);
assign rout_ecc_dbe = ecc_dbe;
assign rout_ecc_code = ecc_code;
always @ (*)
begin
//rout_data_valid = 0;
//rout_cmd_valid = 0;
rout_data_rmwfifo_valid = 0;
rout_cmd_rmwfifo_valid = 0;
rout_sbecmd_valid = 0;
rout_data_error = 0;
rout_errnotify_valid = 0;
if (~cfg_enable_ecc & ~cfg_enable_no_dm)
begin
rout_data_valid = ecc_rdatav;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
end
else
begin
rout_data_rmwfifo_valid = ecc_rdatav & rout_rmw_rmwpartial;
rout_data_valid = ecc_rdatav & ~rout_rmw_rmwpartial;
rout_cmd_valid = rout_data_valid & rdata_burst_complete;
rout_cmd_rmwfifo_valid = rout_data_rmwfifo_valid & rdata_burst_complete;
rout_data_error = int_ecc_dbe;
rout_errnotify_valid = ecc_rdatav & ( int_ecc_sbe | int_ecc_dbe );
if (cfg_enable_auto_corr)
begin
rout_sbecmd_valid = rout_cmd_valid & (ecc_sbe_cmd_detected | int_ecc_sbe);
end
end
end
// rmwfifo interface
assign rmwfifo_data_valid = rout_data_rmwfifo_valid;
assign rmwfifo_data = rout_data;
assign rmwfifo_ecc_dbe = rout_ecc_dbe;
assign rmwfifo_ecc_code = rout_ecc_code;
// ecc_sbe_cmd_detected
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_sbe_cmd_detected <= 0;
ecc_dbe_cmd_detected <= 0;
end
else if (int_ecc_sbe)
begin
ecc_sbe_cmd_detected <= 1;
end
else if (int_ecc_dbe)
begin
ecc_dbe_cmd_detected <= 1;
end
end
end
assign int_ecc_sbe = ecc_rdatav & (|ecc_sbe);
assign int_ecc_dbe = ecc_rdatav & (|ecc_dbe);
//
// ecc_rdata counter
//
assign ecc_rdata_current_count = (cfg_ecc_rdata_counter_reg) ? ecc_rdata_counter : ecc_rdatavalid_count;
assign ecc_rdatavalid_count = (ecc_rdatav) ? ecc_rdata_counter + 1 : ecc_rdata_counter;
assign ecc_rdata_burst_complete_count = pfifo_size;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
ecc_rdata_counter <= 0;
end
else
begin
if (rdata_burst_complete)
begin
ecc_rdata_counter <= ecc_rdatavalid_count - ecc_rdata_burst_complete_count;
end
else
begin
ecc_rdata_counter <= ecc_rdatavalid_count;
end
end
end
assign errcmd_fifo_in_valid_wire = rout_sbecmd_valid;
assign errcmd_fifo_in_wire = {pfifo_chipsel, pfifo_bank, pfifo_row, pfifo_column_burst_aligned, cfg_max_cmd_burstcount, pfifo_localid};
assign {errcmd_chipsel, errcmd_bank, errcmd_row, errcmd_column, errcmd_size, errcmd_localid} = errcmd_fifo_out;
assign errcmd_fifo_in_cmddropped = ~errcmd_fifo_in_ready & errcmd_fifo_in_valid_wire;
assign cfg_max_cmd_burstcount = (cfg_burst_length / cfg_dwidth_ratio);
// ddr3, pfifo_column_burst_aligned is burst length 8 aligned
// ddr2, pfifo_column is already burst aligned
assign pfifo_column_burst_aligned = (cfg_type == `mmr_type_ddr3) ? {pfifo_column[(cfg_mem_if_col_width-1):3],{3{1'b0}} } : pfifo_column;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pfifo_chipsel_r <= 0;
pfifo_bank_r <= 0;
pfifo_row_r <= 0;
pfifo_column_r <= 0;
pfifo_column_burst_aligned_r <= 0;
end
else
begin
pfifo_chipsel_r <= pfifo_chipsel ;
pfifo_bank_r <= pfifo_bank ;
pfifo_row_r <= pfifo_row ;
pfifo_column_r <= pfifo_column ;
pfifo_column_burst_aligned_r <= pfifo_column_burst_aligned;
end
end
generate
if (cfg_errcmd_fifo_reg == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
errcmd_fifo_in_valid <= 1'b0;
errcmd_fifo_in <= {cfg_errcmd_fifo_width{1'b0}};
end else
begin
errcmd_fifo_in_valid <= errcmd_fifo_in_valid_wire;
errcmd_fifo_in <= errcmd_fifo_in_wire;
end
end
end else // (cfg_errcmd_fifo_reg == 0)
begin
always @ (*)
begin
errcmd_fifo_in_valid = errcmd_fifo_in_valid_wire;
errcmd_fifo_in = errcmd_fifo_in_wire;
end
end
endgenerate
alt_mem_ddrx_fifo
# (
.ctl_fifo_data_width (cfg_errcmd_fifo_width),
.ctl_fifo_addr_width (cfg_errcmd_fifo_addr_width)
)
errcmd_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (errcmd_ready && cfg_enable_auto_corr),
.get_valid (errcmd_valid),
.get_data (errcmd_fifo_out),
.put_ready (errcmd_fifo_in_ready),
.put_valid (errcmd_fifo_in_valid),
.put_data (errcmd_fifo_in)
);
//
// error address information for mmr's
//
// - rdatap_rcvd_addr, rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped
// - rdatap_rcvd_addr generation takes 1 cycle after an error, so need to register
// rdatap_rcvd_cmd & rdatap_rcvd_corr_dropped to keep in sync, see spr:362993
//
assign rdatap_rcvd_addr = pfifo_addr;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rdata_burst_complete_r <= 0;
errcmd_fifo_in_cmddropped_r <= 0;
rdatap_rcvd_cmd <= 0;
rdatap_rcvd_corr_dropped <= 0;
end
else
begin
rdata_burst_complete_r <= rdata_burst_complete;
errcmd_fifo_in_cmddropped_r <= errcmd_fifo_in_cmddropped;
rdatap_rcvd_cmd <= rdata_burst_complete;
rdatap_rcvd_corr_dropped <= errcmd_fifo_in_cmddropped;
end
end
// generate local address from chip, bank, row, column addresses
always @(*)
begin : addr_loop
pfifo_addr = 0;
// column
pfifo_addr[min_col - cfg_ignore_num_bits_col - 1 : 0] = pfifo_column_burst_aligned_r[min_col - 1 : cfg_ignore_num_bits_col];
for (n=min_col; n<max_col; n=n+1'b1) begin
if(n < cfg_col_addr_width) begin // bit of col_addr can be configured in csr using cfg_col_addr_width
pfifo_addr[n - cfg_ignore_num_bits_col] = pfifo_column_burst_aligned_r[n];
end
end
// row
for (j=0; j<min_row; j=j+1'b1) begin //the purpose of using this for-loop is to get rid of "if(j < cfg_row_addr_width) begin" which causes multiplexers
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
for (j=min_row; j<max_row; j=j+1'b1) begin
if(j < cfg_row_addr_width) begin // bit of row_addr can be configured in csr using cfg_row_addr_width
pfifo_addr[j + cfg_addr_bitsel_row] = pfifo_row_r[j];
end
end
// bank
for (k=0; k<min_bank; k=k+1'b1) begin //the purpose of using this for-loop is to get rid of "if(k < cfg_bank_addr_width) begin" which causes multiplexers
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
for (k=min_bank; k<max_bank; k=k+1'b1) begin
if(k < cfg_bank_addr_width) begin // bit of bank_addr can be configured in csr using cfg_bank_addr_width
pfifo_addr[k + cfg_addr_bitsel_bank] = pfifo_bank_r[k];
end
end
// cs
m = 0;
if (cfg_cs_addr_width > 1'b0) begin //if cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
for (m=0; m<min_cs; m=m+1'b1) begin //the purpose of using this for-loop is to get rid of "if(m < cfg_cs_addr_width) begin" which causes multiplexers
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
for (m=min_cs; m<max_cs; m=m+1'b1) begin
if(m < cfg_cs_addr_width) begin // bit of cs_addr can be configured in csr using cfg_cs_addr_width
pfifo_addr[m + cfg_addr_bitsel_chipsel] = pfifo_chipsel_r[m];
end
end
end
end
// pre-calculate pfifo_addr chipsel, bank, row, col bit select offsets
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
cfg_addr_bitsel_chipsel <= 0;
cfg_addr_bitsel_bank <= 0;
cfg_addr_bitsel_row <= 0;
end
else
begin
//row
if(cfg_addr_order == `mmr_addr_order_row_cs_ba_col)
cfg_addr_bitsel_row <= cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - cfg_ignore_num_bits_col;
else if(cfg_addr_order == `mmr_addr_order_cs_ba_row_col)
cfg_addr_bitsel_row <= cfg_col_addr_width - cfg_ignore_num_bits_col;
else // cfg_addr_order == `mmr_addr_order_cs_row_ba_col
cfg_addr_bitsel_row <= cfg_bank_addr_width + cfg_col_addr_width - cfg_ignore_num_bits_col;
// bank
if(cfg_addr_order == `mmr_addr_order_cs_ba_row_col)
cfg_addr_bitsel_bank <= cfg_row_addr_width + cfg_col_addr_width - cfg_ignore_num_bits_col;
else // cfg_addr_order == `mmr_addr_order_row_cs_ba_col || `mmr_addr_order_cs_row_ba_col
cfg_addr_bitsel_bank <= cfg_col_addr_width - cfg_ignore_num_bits_col;
//chipsel
if(cfg_addr_order == `mmr_addr_order_row_cs_ba_col)
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_col_addr_width - cfg_ignore_num_bits_col;
else // cfg_addr_order == `mmr_addr_order_cs_ba_row_col || `mmr_addr_order_cs_row_ba_col
cfg_addr_bitsel_chipsel <= cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - cfg_ignore_num_bits_col;
end
end
//
// everything below is for
// cfg_rdata_return_mode == inorder support
//
generate
begin : gen_rdata_return_inorder
if (cfg_rdata_return_mode == "inorder")
begin
//
// dataid management
//
genvar i;
for (i = 0; i < cfg_dataid_array_depth; i = i + 1)
begin : gen_dataid_array
assign dataid_array_valid[i] = |(dataid_array_burstcount[i]);
// dataid_array
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
dataid_array_localid [i] <= 0;
end
else
begin
// update command
if (cmdload_valid & free_id_dataid_vector[i])
begin
dataid_array_burstcount[i] <= proc_size;
end
// writing data to buffer
if (rout_data_valid & (rout_data_dataid == i))
begin
dataid_array_data_ready[i] <= 1'b1;
dataid_array_localid[i] <= rout_data_localid;
end
// completed reading data from buffer
if (inordr_id_data_complete & inordr_id_dataid_vector[i])
begin
dataid_array_data_ready[i] <= 1'b0;
dataid_array_burstcount[i] <= 0;
end
end
end
// dataid_array output decode mux
always @ (*)
begin
if (inordr_id_valid & inordr_id_dataid_vector[i])
begin
mux_inordr_data_ready[i] = dataid_array_data_ready[i];
end
else
begin
mux_inordr_data_ready[i] = 1'b0;
end
end
end
assign inordr_read_data_valid = |mux_inordr_data_ready;
//
// free & allocated dataid list
//
assign free_id_get_ready = cmdload_valid;
assign allocated_put_valid = free_id_get_ready & free_id_valid;
// list & fifo ready & valid assertion/de-assertion behavior may differ based on implementation, spr:358527
assign free_id_valid = int_free_id_valid & inordr_info_input_ready;
assign inordr_id_valid = inordr_id_list_valid & inordr_info_output_valid;
alt_mem_ddrx_list
#(
.ctl_list_width (cfg_data_id_width),
.ctl_list_depth (cfg_dataid_array_depth),
.ctl_list_init_value_type ("incr"),
.ctl_list_init_valid ("valid")
)
list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (free_id_get_ready),
.list_get_entry_valid (int_free_id_valid),
.list_get_entry_id (free_id_dataid),
.list_get_entry_id_vector (free_id_dataid_vector),
// ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (),
.list_put_entry_valid (inordr_id_data_complete),
.list_put_entry_id (inordr_id_dataid)
);
alt_mem_ddrx_list
#(
.ctl_list_width (cfg_data_id_width),
.ctl_list_depth (cfg_dataid_array_depth),
.ctl_list_init_value_type ("zero"),
.ctl_list_init_valid ("invalid")
)
list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (inordr_id_data_complete),
.list_get_entry_valid (inordr_id_list_valid),
.list_get_entry_id (inordr_id_dataid),
.list_get_entry_id_vector (inordr_id_dataid_vector),
// allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (allocated_put_ready),
.list_put_entry_valid (allocated_put_valid),
.list_put_entry_id (free_id_dataid)
);
// format for inordr_info_input & inordr_info_output must be same
assign inordr_info_input = {proc_localid,proc_size};
assign {inordr_id_localid,inordr_id_expected_burstcount} = inordr_info_output;
alt_mem_ddrx_fifo
# (
.ctl_fifo_data_width (cfg_inorder_info_fifo_width),
.ctl_fifo_addr_width (cfg_data_id_width)
)
inordr_info_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (inordr_id_data_complete),
.get_valid (inordr_info_output_valid),
.get_data (inordr_info_output),
.put_ready (inordr_info_input_ready),
.put_valid (allocated_put_valid),
.put_data (inordr_info_input)
);
//
// in-order read manager
//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 0;
inordr_read_data_valid_r <= 0;
inordr_id_data_complete_r <= 0;
inordr_id_localid_r <= 0;
end
else
begin
if (inordr_id_data_complete)
begin
inordr_data_counter <= 0;
inordr_data_counter_plus_1 <= 1;
end
else
begin
inordr_data_counter <= inordr_next_data_counter;
inordr_data_counter_plus_1 <= inordr_next_data_counter + 1;
end
inordr_id_localid_r <= inordr_id_localid;
// original signal used to read from buffer
// _r version used to pop the fifos
inordr_read_data_valid_r <= inordr_read_data_valid;
inordr_id_data_complete_r <= inordr_id_data_complete;
end
end
assign inordr_next_data_counter = (inordr_read_data_valid) ? (inordr_data_counter_plus_1) : inordr_data_counter;
assign inordr_id_data_complete = inordr_read_data_valid & (inordr_data_counter_plus_1 == inordr_id_expected_burstcount);
//
// buffer
//
assign buffwrite_offset = ecc_rdata_counter;
assign buffwrite_address = {rout_data_dataid,buffwrite_offset};
assign buffwrite_data = {rout_data_error,rout_data};
assign buffread_offset = inordr_data_counter;
assign buffread_address = {inordr_id_dataid,buffread_offset};
assign {inordr_read_data_error,inordr_read_data} = buffread_data;
alt_mem_ddrx_buffer
# (
.addr_width (cfg_buffer_addr_width),
.data_width (cfg_in_order_buffer_data_width)
)
in_order_buffer_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (rout_data_valid),
.write_address (buffwrite_address),
.write_data (buffwrite_data),
// read interface
.read_valid (inordr_read_data_valid),
.read_address (buffread_address),
.read_data (buffread_data)
);
end
end
endgenerate
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
//
// assert
//
// - rdatap_free_id_valid xor rdatap_allocated_put_ready must always be 1
// - cfg_buffer_addr_width must be >= cfg_int_size_width. must have enough location to store 1 dram command worth of data
// - put_ready goes low
// - ecc_rdatav is high, but pfifo_output_valid is low
// - buffer size must be dataid x max size per command
// - is rdata_burst_complete allowed to be high every cycle?
// - cfg_buffer_addr_width > cfg_data_id_width
// - if cfg_enable_ecc is low, sbe, dbe, rdata error must all be low
// - if cfg_enable_auto_corr is low, rmw & rmw_partial must be low, errcmd_valid must never be high
// - cmd_counter_full & cmdload_valid
|
// copyright (c) 2020 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the intel program license
// subscription agreement, the intel quartus prime license agreement,
// the intel fpga ip license agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// intel and sold by intel or its authorized distributors. please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
// *****************************************************************************
// this file contains a verilog test bench with test vectors .the test vectors
// are exported from a vector file in the quartus waveform editor and apply to
// the top level entity of the current quartus project .the user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// generated on "03/20/2022 12:29:40"
// verilog test bench (with test vectors) for design : bresen
//
// simulation tool : 3rd party
//
`timescale 1 ps/ 1 ps
module tbt3();
// constants
// general purpose registers
reg clk50;
reg plot;
reg [7:0] r;
reg [7:0] xc;
reg [6:0] yc;
// wires
wire holdclk;
wire [7:0] xo;
wire [6:0] yo;
// assign statements (if any)
bresen i1 (
// port map - connection between master ports and signals/registers
.clk50(clk50),
.plot(plot),
.r(r),
.xc(xc),
.xo(xo),
.yc(yc),
.yo(yo)
);
initial
begin
#3000000 $finish;
end
// clk50
always
begin
clk50 = 1'b0;
clk50 = #5000 1'b1;
#5000;
end
// xc[ 7 ]
initial
begin
xc[7] = 1'b0;
end
// xc[ 6 ]
initial
begin
xc[6] = 1'b1;
end
// xc[ 5 ]
initial
begin
xc[5] = 1'b0;
end
// xc[ 4 ]
initial
begin
xc[4] = 1'b1;
end
// xc[ 3 ]
initial
begin
xc[3] = 1'b0;
end
// xc[ 2 ]
initial
begin
xc[2] = 1'b0;
end
// xc[ 1 ]
initial
begin
xc[1] = 1'b0;
end
// xc[ 0 ]
initial
begin
xc[0] = 1'b0;
end
// yc[ 6 ]
initial
begin
yc[6] = 1'b0;
end
// yc[ 5 ]
initial
begin
yc[5] = 1'b1;
end
// yc[ 4 ]
initial
begin
yc[4] = 1'b1;
end
// yc[ 3 ]
initial
begin
yc[3] = 1'b1;
end
// yc[ 2 ]
initial
begin
yc[2] = 1'b1;
end
// yc[ 1 ]
initial
begin
yc[1] = 1'b0;
end
// yc[ 0 ]
initial
begin
yc[0] = 1'b0;
end
// r[ 7 ]
initial
begin
r[7] = 1'b0;
end
// r[ 6 ]
initial
begin
r[6] = 1'b0;
end
// r[ 5 ]
initial
begin
r[5] = 1'b0;
end
// r[ 4 ]
initial
begin
r[4] = 1'b1;
end
// r[ 3 ]
initial
begin
r[3] = 1'b0;
end
// r[ 2 ]
initial
begin
r[2] = 1'b1;
end
// r[ 1 ]
initial
begin
r[1] = 1'b0;
end
// r[ 0 ]
initial
begin
r[0] = 1'b0;
end
// plot
initial
begin
plot = 1'b1;
//plot = #10000 1'b0;
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1459998803 : 0;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
//-----------------------------------------------------------------
// usb full speed (12mbps) phy
// v0.2
// ultra-embedded.com
// copyright 2015
//
// email: admin@ultra-embedded.com
//
// license: lgpl
//-----------------------------------------------------------------
//
// this source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// this source file is free software; you can redistribute it
// and/or modify it under the terms of the gnu lesser general
// public license as published by the free software foundation;
// either version 2.1 of the license, or (at your option) any
// later version.
//
// this source is distributed in the hope that it will be
// useful, but without any warranty; without even the implied
// warranty of merchantability or fitness for a particular
// purpose. see the gnu lesser general public license for more
// details.
//
// you should have received a copy of the gnu lesser general
// public license along with this source; if not, write to the
// free software foundation, inc., 59 temple place, suite 330,
// boston, ma 02111-1307 usa
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// generated file
//-----------------------------------------------------------------
module usb_transceiver
(
// inputs
input usb_phy_tx_dp_i
,input usb_phy_tx_dn_i
,input usb_phy_tx_oen_i
,input mode_i
// outputs
,inout usb_dp_io
,inout usb_dn_io
,output usb_phy_rx_rcv_o
,output usb_phy_rx_dp_o
,output usb_phy_rx_dn_o
);
//-----------------------------------------------------------------
// module: usb_transceiver
// emulate standard usb phy interface and produce a d+/d- outputs.
// allows direct connection of usb port to fpga.
// limitations:
// as no differential amplifier present, no common mode noise
// rejection occurs.
// unlikely to work well with longer connections!
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// wires
//-----------------------------------------------------------------
//reg out_dp;
//reg out_dn;
//-----------------------------------------------------------------
// assignments
//-----------------------------------------------------------------
// d+/d- tristate buffers
assign usb_dp_io = (usb_phy_tx_oen_i == 1'b0) ? usb_phy_tx_dp_i : 1'bz;
assign usb_dn_io = (usb_phy_tx_oen_i == 1'b0) ? usb_phy_tx_dn_i : 1'bz;
// receive d+/d-
assign usb_phy_rx_dp_o = usb_dp_io;
assign usb_phy_rx_dn_o = usb_dn_io;
// receive output
assign usb_phy_rx_rcv_o = (usb_dp_io == 1'b1 && usb_dn_io == 1'b0) ? 1'b1 : 1'b0;
//assign usb_phy_rx_rcv_o = ((usb_dp_io == 1) && (usb_dn_io == 0)) ? 1'b1:
//((usb_dp_io == 0) && (usb_dn_io == 1)) ? 1'b0: 1'b0;
// phy transmit mode:
// when phy_tx_mode_i is '0' the outputs are encoded as:
// vmo_i, vpo_i
// 0 0 differential logic '0'
// 0 1 differential logic '1'
// 1 0 single ended '0'
// 1 1 single ended '0'
// when phy_tx_mode_i is '1' the outputs are encoded as:
// vmo_i, vpo_i
// 0 0 single ended '0'
// 0 1 differential logic '1'
// 1 0 differential logic '0'
// 1 1 illegal state
/*always @ (mode_i or usb_phy_tx_dp_i or usb_phy_tx_dn_i)
begin : mux
case(mode_i)
1'b0:
begin
if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b0)
begin
// logic "0"
out_dp = 1'b0;
out_dn = 1'b1;
end
else if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b1)
begin
// se0 (both low)
out_dp = 1'b0;
out_dn = 1'b0;
end
else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b0)
begin
// logic "1"
out_dp = 1'b1;
out_dn = 1'b0;
end
else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
begin
// se0 (both low)
out_dp = 1'b0;
out_dn = 1'b0;
end
end
1'b1 :
begin
if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b0)
begin
// se0 (both low)
out_dp = 1'b0;
out_dn = 1'b0;
end
else if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b1)
begin
// logic "0"
out_dp = 1'b0;
out_dn = 1'b1;
end
else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b0)
begin
// logic "1"
out_dp = 1'b1;
out_dn = 1'b0;
end
else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
begin
// illegal
out_dp = 1'b1;
out_dn = 1'b1;
end
end
endcase
end
*/
endmodule
|
// (c) 2001-2011 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// title : pci express bfm with avalon-st root port
// project : pci express megacore function
//-----------------------------------------------------------------------------
// file : altpcietb_bfm_vc_intf_ast.v
// author : altera corporation
//-----------------------------------------------------------------------------
// description :
// this entity is the entire pci ecpress root port bfm
//-----------------------------------------------------------------------------
// copyright (c) 2008 altera corporation. all rights reserved. altera products are
// protected under numerous u.s. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// this reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable altera reference design license agreement.
// by using this reference design file, you indicate your acceptance of such terms and
// conditions between you and altera corporation. in the event that you do not agree with
// such terms and conditions, you may not use the reference design file. please promptly
// destroy any copies you have made.
//
// this reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. by making this reference design file available, altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by altera.
//-----------------------------------------------------------------------------
module altpcietb_bfm_vc_intf_ast (clk_in, rstn,
rx_mask, rx_st_be, rx_st_sop, rx_st_eop, rx_st_empty, rx_st_data, rx_st_valid, rx_st_ready,
tx_cred, tx_st_ready, tx_st_sop, tx_st_eop, tx_st_empty, tx_st_valid, tx_st_data, tx_fifo_empty,
cfg_io_bas, cfg_np_bas, cfg_pr_bas);
parameter vc_num = 0;
parameter avalon_st_128 = 0;
parameter ecrc_forward_check = 1;
parameter ecrc_forward_gener = 1;
input clk_in;
input rstn;
output rx_mask;
input[35:0] tx_cred;
input[19:0] cfg_io_bas;
input[11:0] cfg_np_bas;
input[43:0] cfg_pr_bas;
input rx_st_sop;
input rx_st_valid;
output rx_st_ready;
input rx_st_eop;
input rx_st_empty;
input[127:0] rx_st_data;
input[15:0] rx_st_be;
input tx_st_ready;
output tx_st_sop;
output tx_st_eop;
output tx_st_empty;
output tx_st_valid;
output[127:0] tx_st_data;
input tx_fifo_empty;
wire [ 81: 0] rx_stream_data_0;
wire [ 81: 0] rx_stream_data_1;
// rx fifo
wire rx_st_sop_int;
wire rx_st_eop_int;
wire rx_st_empty_int;
wire[127:0] rx_st_data_int;
wire[15:0] rx_st_be_int;
wire rx_st_ready_int;
wire rx_valid_int;
wire[7:0] rx_st_bardec;
wire empty;
wire almost_full;
wire[19:0] unused_st;
wire tx_st_ready_int;
wire[127:0] tx_st_data_int;
wire tx_st_sop_int;
wire tx_st_eop_int;
wire tx_st_empty_int;
wire tx_st_valid_int;
wire [ 81: 0] rx_stream_data_0_int;
wire [ 81: 0] rx_stream_data_1_int;
wire rx_st_valid_int;
wire rx_ecrc_check_valid;
wire[15:0] ecrc_bad_cnt;
reg ecrc_err;
assign rx_st_bardec = 8'h0;
always @ (posedge clk_in or negedge rstn) begin
if (rstn==1'b0)
ecrc_err <= 1'b0;
else begin
if (ecrc_bad_cnt > 0)
ecrc_err <= 1'b1; // assert and hold when ecrc error is detected
end
end
//////////////////////////////////////////////////////////////
// receive rx avalon-st input
// if ecrc forwarding is enabled, then first route thru the
// ecrc checker to remove ecrc from data stream.
//////////////////////////////////////////////////////////////
generate begin: rx_ecrc_genblk
wire [ 81: 0] rx_stream_data_0_ecrc;
wire [ 81: 0] rx_stream_data_1_ecrc;
wire rx_st_valid_ecrc;
wire rx_st_ready_ecrc;
wire[15:0] rx_st_be_ecrc;
wire[7:0] rx_st_bardec_ecrc;
wire rx_st_sop_ecrc;
wire rx_st_eop_ecrc;
wire rx_st_empty_ecrc;
wire [139:0] rx_st_data_ecrc;
///////////////////////////////////////////////
// rx ecrc checking
// ecrc is checked and removed from the data
///////////////////////////////////////////////
if (ecrc_forward_check==1) begin: rx_ecrc
altpcierd_cdma_ecrc_check #(.avalon_st_128(avalon_st_128)) cdma_ecrc_check(
// input avalon-st prior to check ecrc
.rxdata ({rx_st_sop, 1'b0, rx_st_empty, rx_st_eop, rx_st_bardec, rx_st_data}),
.rxdata_be (rx_st_be),
.rx_stream_ready0 (~almost_full),
.rx_stream_valid0 (rx_st_valid),
// output avalon-st after checking ecrc
.rxdata_ecrc (rx_st_data_ecrc),
.rxdata_be_ecrc (rx_st_be_ecrc),
.rx_stream_ready0_ecrc (rx_st_ready_ecrc),
.rx_stream_valid0_ecrc (rx_st_valid_ecrc),
.rx_ecrc_check_valid (rx_ecrc_check_valid),
.ecrc_bad_cnt (ecrc_bad_cnt),
.clk_in (clk_in),
.srst (~rstn)
);
/*
// simulation monitor
initial begin
wait (rstn==1);
wait (ecrc_bad_cnt==0);
wait (ecrc_bad_cnt>0);
$display (" >>>> rp: bad ecrc received <<<<");
end
*/
///////////////////////////////////////////////
// ecrc sources data to vcintf (via rx fifo)
assign rx_st_bardec_ecrc = rx_st_data_ecrc[135:128];
assign rx_st_sop_ecrc = rx_st_data_ecrc[139];
assign rx_st_eop_ecrc = rx_st_data_ecrc[136];
assign rx_st_empty_ecrc = rx_st_data_ecrc[137];
assign rx_stream_data_0_int = {rx_st_be_ecrc[7:0], rx_st_sop_ecrc, rx_st_eop_ecrc, rx_st_bardec_ecrc, rx_st_data_ecrc[63:0]};
assign rx_stream_data_1_int = {rx_st_be_ecrc[15:8], 1'b0, rx_st_empty_ecrc, 8'h0, rx_st_data_ecrc[127:64]};
assign rx_st_valid_int = rx_st_valid_ecrc;
assign rx_st_ready = rx_st_ready_ecrc;
end
///////////////////////////
// no ecrc forwarding
///////////////////////////
else begin
/////////////////////////////////////////////////////////////
// avalon-st io sources data to vcintf (via rx fifo)
assign rx_stream_data_0_int = {rx_st_be[7:0], rx_st_sop, rx_st_eop, rx_st_bardec, rx_st_data[63:0]};
assign rx_stream_data_1_int = {rx_st_be[15:8], 1'b0, rx_st_empty, 8'h0, rx_st_data[127:64]};
assign rx_st_valid_int = rx_st_valid;
assign rx_st_ready = ~almost_full;
assign rx_ecrc_check_valid = 0;
assign ecrc_bad_cnt = 0;
end
end
endgenerate
//////////////////////////////////////////////////////////////////////
// rx fifo
// avalon-st data is held in a fifo until rp (vc intf) can process it
//////////////////////////////////////////////////////////////////////
// fifo parameters
parameter rxfifo_depth = 32;
parameter rxfifo_width = 164;
parameter rxfifo_widthu = 5;
scfifo # (
.add_ram_output_register ("off") ,
.intended_device_family ("stratix ii gx"),
.lpm_numwords (rxfifo_depth),
.lpm_showahead ("on") ,
.lpm_type ("scfifo") ,
.lpm_width (rxfifo_width) ,
.lpm_widthu (rxfifo_widthu),
.overflow_checking ("off") ,
.underflow_checking ("off") ,
.almost_full_value (rxfifo_depth/2) ,
.use_eab ("off")
) rx_data_fifo (
.clock ( clk_in),
.sclr (~rstn ),
.data ({rx_stream_data_1_int, rx_stream_data_0_int}),
.wrreq (rx_st_valid_int),
.rdreq (rx_st_ready_int & ~empty),
.q ({ rx_st_be_int[15:8], unused_st[16], rx_st_empty_int, unused_st[15:8], rx_st_data_int[127:64],
rx_st_be_int[7:0], rx_st_sop_int, rx_st_eop_int, unused_st[7:0], rx_st_data_int[63:0]
}),
.empty (empty),
.full ( ),
.usedw ()
// synopsys translate_off
,
.aclr (1'b0),
.almost_empty (),
.almost_full (almost_full)
// synopsys translate_on
);
////////////////////////////////////////////////////////////////////////
// vc interface module
// receives, generates, and processes rp traffic.
//
// instantiate 128-bit avalon-st version, or 64-bit avalon-st version.
/////////////////////////////////////////////////////////////////////////
assign rx_valid_int = ~empty;
generate begin: vc_intf_genblk
if (avalon_st_128==1) begin: vc_intf_128_genblk
altpcietb_bfm_vc_intf_128 #(.vc_num (vc_num)) vc_intf_128(
.clk_in (clk_in),
.rstn (rstn),
.rx_mask (rx_mask),
.rx_be (rx_st_be_int),
.rx_ecrc_err (ecrc_err),
.tx_cred (tx_cred),
.tx_st_ready (tx_st_ready_int),
.cfg_io_bas (cfg_io_bas),
.cfg_np_bas (cfg_np_bas),
.cfg_pr_bas (cfg_pr_bas),
.rx_st_sop (rx_st_sop_int),
.rx_st_eop (rx_st_eop_int),
.rx_st_empty (rx_st_empty_int),
.rx_st_data (rx_st_data_int[127:0]),
.rx_st_valid (rx_valid_int),
.rx_st_ready (rx_st_ready_int),
.tx_st_sop (tx_st_sop_int),
.tx_st_eop (tx_st_eop_int),
.tx_st_empty (tx_st_empty_int),
.tx_st_data (tx_st_data_int),
.tx_st_valid (tx_st_valid_int),
.tx_fifo_empty (tx_fifo_empty)
);
end
else begin: vc_intf_64_genblk
altpcietb_bfm_vc_intf_64 #(.vc_num (vc_num)) vc_intf_64(
.clk_in (clk_in),
.rstn (rstn),
.rx_mask (rx_mask),
.rx_be (rx_st_be_int),
.rx_ecrc_err (ecrc_err),
.tx_cred (tx_cred),
.cfg_io_bas (cfg_io_bas),
.cfg_np_bas (cfg_np_bas),
.cfg_pr_bas (cfg_pr_bas),
.rx_st_sop (rx_st_sop_int),
.rx_st_eop (rx_st_eop_int),
.rx_st_empty (rx_st_empty_int),
.rx_st_data (rx_st_data_int[63:0]),
.rx_st_valid (rx_valid_int),
.rx_st_ready (rx_st_ready_int),
.tx_st_sop (tx_st_sop_int),
.tx_st_eop (tx_st_eop_int),
.tx_st_empty (tx_st_empty_int),
.tx_st_data (tx_st_data_int[63:0]),
.tx_st_valid (tx_st_valid_int),
.tx_st_ready ((tx_st_ready_int)),
.tx_fifo_empty (tx_fifo_empty)
);
end
end
endgenerate
////////////////////////////////////////////////////////////////
// drive avalon-st tx output
// if ecrc forwarding is enabled, then calculate and append
// the ecrc to the avalon-st output.
///////////////////////////////////////////////////////////////
generate begin: tx_ecrc_genblk
////////////////////////////////////////////////////////////
// ecrc forwarding
// ecrc is calculated and appended to the vc intf traffic
// if ecrc forwarding is enabled.
if (ecrc_forward_gener==1) begin: tx_ecrc
// ecrc output side
wire[127:0] tx_st_data_ecrc;
wire tx_st_sop_ecrc;
wire tx_st_eop_ecrc;
wire tx_st_empty_ecrc;
wire[73:0] tx_st_data_ecrc0;
wire[73:0] tx_st_data_ecrc1;
wire tx_st_ready_ecrc;
wire tx_st_valid_ecrc;
// ecrc input side
reg[127:0] user_data_reg;
reg user_valid_reg;
reg user_sop_reg;
reg user_eop_reg;
reg user_empty_reg;
wire[127:0] user_data_ecrc;
wire user_valid_ecrc;
wire user_sop_ecrc;
wire user_eop_ecrc;
wire user_empty_ecrc;
reg tx_st_ready_ecrc_reg;
///////////////////////////////////////////////////////////////
// glue logic to hold the vc_intf signals until it is 'acked'
// by the ecrc module (via tx_st_ready_ecrc).
/*
ecrc interface:
________ ________________
tx_st_ready_ecrc (ack) |___|
________________________
user_valid_ecrc ____|
______________________________
user_data_ecrc ____|_0_|_1_____|_2_|_3_|_4_|_
*/
always @ (posedge clk_in or negedge rstn) begin
if (rstn==1'b0) begin
user_data_reg <= 0;
user_valid_reg <= 0;
user_sop_reg <= 0;
user_eop_reg <= 0;
user_empty_reg <= 0;
tx_st_ready_ecrc_reg <= 0;
end
else begin
if ((tx_st_ready_ecrc==1'b0) & (tx_st_ready_ecrc_reg==1'b1)) begin
user_data_reg <= {tx_st_data_int[31:0],tx_st_data_int[63:32], tx_st_data_int[95:64],tx_st_data_int[127:96]};
user_valid_reg <= tx_st_valid_int;
user_sop_reg <= tx_st_sop_int;
user_eop_reg <= tx_st_eop_int;
user_empty_reg <= tx_st_empty_int;
end
tx_st_ready_ecrc_reg <= tx_st_ready_ecrc;
end
end
assign user_data_ecrc = ((tx_st_ready_ecrc_reg==0) & (tx_st_ready_ecrc==1'b1)) ? user_data_reg :
{tx_st_data_int[31:0],tx_st_data_int[63:32], tx_st_data_int[95:64],tx_st_data_int[127:96]} ;
assign user_valid_ecrc = ((tx_st_ready_ecrc_reg==0) & (tx_st_ready_ecrc==1'b1)) ? user_valid_reg : tx_st_valid_int;
assign user_sop_ecrc = ((tx_st_ready_ecrc_reg==0) & (tx_st_ready_ecrc==1'b1)) ? user_sop_reg : tx_st_sop_int;
assign user_eop_ecrc = ((tx_st_ready_ecrc_reg==0) & (tx_st_ready_ecrc==1'b1)) ? user_eop_reg : tx_st_eop_int;
assign user_empty_ecrc = ((tx_st_ready_ecrc_reg==0) & (tx_st_ready_ecrc==1'b1)) ? user_empty_reg : tx_st_empty_int;
/////////////////////////////
// tx ecrc module
// ecrc generate and append
altpcierd_cdma_ecrc_gen #(.avalon_st_128(avalon_st_128))
cdma_ecrc_gen (
.clk (clk_in),
.rstn (rstn),
.user_rd_req (tx_st_ready_ecrc),
.user_sop (user_sop_ecrc),
.user_eop ({user_eop_ecrc, user_empty_ecrc}),
.user_data (user_data_ecrc),
.user_valid (user_valid_ecrc),
.tx_stream_ready0 (tx_st_ready),
.tx_stream_data0_0 (tx_st_data_ecrc0),
.tx_stream_data0_1 (tx_st_data_ecrc1),
.tx_stream_valid0 (tx_st_valid_ecrc));
///////////////////////////
// drive avalon-st output
assign tx_st_data[63:0] = {tx_st_data_ecrc0[31:0], tx_st_data_ecrc0[63:32]};
assign tx_st_empty = tx_st_data_ecrc0[73];
assign tx_st_sop = tx_st_data_ecrc0[72];
// assign tx_st_data[132] = 1'b0;
assign tx_st_eop = tx_st_data_ecrc1[73];
// assign tx_st_data[129] = tx_st_data_ecrc1[72];
assign tx_st_data[127:64] = {tx_st_data_ecrc1[31:0], tx_st_data_ecrc1[63:32]};
assign tx_st_ready_int = tx_st_ready_ecrc;
assign tx_st_valid = tx_st_valid_ecrc;
end
////////////////////////////////////////////////////
// no ecrc forwarding
// wire directly from vc_intf
else begin
assign tx_st_data = tx_st_data_int;
assign tx_st_eop = tx_st_eop_int;
assign tx_st_sop = tx_st_sop_int;
assign tx_st_empty = tx_st_empty_int;
assign tx_st_ready_int = tx_st_ready;
assign tx_st_valid = tx_st_valid_int;
end
end
endgenerate
endmodule
|
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// $id: $
// $revision: $
// $date: $
// $author: $
//-----------------------------------------------------------------------------
// copyright 2012 altera corporation. all rights reserved.
// altera products are protected under numerous u.s. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// this reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable altera reference design
// license agreement (either as signed by you or found at www.altera.com). by
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and altera corporation. in the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// this reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. by making this reference
// design file available, altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 01-31-2012
`timescale 1ps/1ps
module dcfifo_mlab #(
parameter target_chip = 2, // 1=s4, 2=s5, 5=a10
parameter width = 80, // typical 20,40,60,80
parameter prevent_overflow = 1'b1, // ignore requests that would cause overflow
parameter prevent_underflow = 1'b1, // ignore requests that would cause underflow
parameter ram_groups = (width < 20) ? 1 : (width / 20), // min 1, width must be divisible by ram_groups
parameter group_raddr = (width < 20) ? 1'b0 : 1'b1, // 1 to duplicate raddr per group as well as waddr
parameter flag_dupes = 1, // if > 1 replicate full / empty flags for fanout balancing
parameter addr_width = 5, // 4 or 5
parameter sync_stages = 2, // meta hardening - min 2 (1 capture 1 harden)
parameter disable_wused = 1'b0,
parameter disable_rused = 1'b0,
parameter aclr_wr_sync = 1'b1, // at least one of aclr_wr_sync and aclr_rd_sync
parameter aclr_rd_sync = 1'b1, // must be 1
parameter xpmlab = 1'b0 // use sub-fifos for pointer crossing instead of synchronizers
)(
input aclr, // no domain
input wclk,
input [width-1:0] wdata,
input wreq,
output [flag_dupes-1:0] wfull, // optional duplicates for loading
output [addr_width-1:0] wused,
input rclk,
output [width-1:0] rdata,
input rreq,
output [flag_dupes-1:0] rempty, // optional duplicates for loading
output [addr_width-1:0] rused
);
// __ __ __ __ __ __ __
// rclk | | | | | | | | | | | | | |
// ___| |__| |__| |__| |__| |__| |__| |__
// _____
// rreq | |
// ______| |________________________________
// _____
// rdata | |
// ____________| |__________________________
// synthesis translate_off
initial begin
if (width > 20 && (ram_groups * 20 != width)) begin
$display ("error in dcfifo_mlab parameters - the physical width is a multiple of 20, this needs to match");
$stop();
end
end
// synthesis translate_on
////////////////////////////////////
// resync aclr
////////////////////////////////////
wire waclr, raclr;
generate
if( aclr_rd_sync ) begin
aclr_filter afr (
.aclr(aclr), // no domain
.clk(rclk),
.aclr_sync(raclr));
end
else begin
assign raclr = aclr; // must be externally synchronized to rclk
end
endgenerate
generate
if( aclr_wr_sync ) begin
aclr_filter afw (
.aclr(aclr), // no domain
.clk(wclk),
.aclr_sync(waclr));
end
else begin
assign waclr = aclr; // must be externally synchronized to wclk
end
endgenerate
////////////////////////////////////
// addr pointers
////////////////////////////////////
wire winc, rinc;
wire [ram_groups*addr_width-1:0] rptr;
wire [addr_width-1:0] wptr;
wire [addr_width-1:0] waddr_g;
wire [addr_width-1:0] raddr_g;
assign wptr = waddr_g;
generate
if (addr_width == 4) begin : a4
// gray write pointer
gray_cntr_4_sl wcntr (
.clk(wclk),
.ena(winc),
.sld(waclr),
.cntr(waddr_g)
);
defparam wcntr .sld_val = 4'h1;
defparam wcntr .target_chip = target_chip;
// gray read pointer
gray_cntr_4_sl rcntr (
.clk(rclk),
.ena(rinc),
.sld(raclr),
.cntr(raddr_g)
);
defparam rcntr .sld_val = group_raddr ? 4'h3 : 4'h1;
defparam rcntr .target_chip = target_chip;
end
else begin : a5
// gray write pointer
gray_cntr_5_sl wcntr (
.clk(wclk),
.ena(winc),
.sld(waclr),
.cntr(waddr_g)
);
defparam wcntr .sld_val = 5'h1;
defparam wcntr .target_chip = target_chip;
// gray read pointer
gray_cntr_5_sl rcntr (
.clk(rclk),
.ena(rinc),
.sld(raclr),
.cntr(raddr_g)
);
defparam rcntr .sld_val = group_raddr ? 5'h3 : 5'h1;
defparam rcntr .target_chip = target_chip;
end
endgenerate
// optional duplication of the read address
generate
if (group_raddr) begin : gr
reg [ram_groups*addr_width-1:0] raddr_g_r = {ram_groups{{addr_width{1'b0}} | 1'b1}}
/* synthesis preserve */;
always @(posedge rclk or posedge raclr) begin
if (raclr) raddr_g_r <= {ram_groups{{addr_width{1'b0}} | 1'b1}};
else if (rinc) raddr_g_r <= {ram_groups{raddr_g}};
end
assign rptr = raddr_g_r;
end
else begin : ngr
assign rptr = {ram_groups{raddr_g}};
end
endgenerate
//////////////////////////////////////////////////
// adjust pointers for ram latency
//////////////////////////////////////////////////
reg [addr_width-1:0] raddr_g_completed = {addr_width{1'b0}};
always @(posedge rclk or posedge raclr) begin
if (raclr) begin
raddr_g_completed <= {addr_width{1'b0}};
end
else begin
if (rinc) raddr_g_completed <= rptr[addr_width-1:0];
end
end
reg [addr_width-1:0] waddr_g_d = {addr_width{1'b0}};
reg [addr_width-1:0] waddr_g_completed = {addr_width{1'b0}};
wire [addr_width-1:0] waddr_g_d_w = winc ? waddr_g : waddr_g_d /* synthesis keep */;
always @(posedge wclk or posedge waclr) begin
if (waclr) begin
waddr_g_d <= {addr_width{1'b0}};
waddr_g_completed <= {addr_width{1'b0}};
end
else begin
waddr_g_d <= waddr_g_d_w;
waddr_g_completed <= waddr_g_d;
end
end
//////////////////////////////////////////////////
// cross clock domains
//////////////////////////////////////////////////
wire [addr_width-1:0] rside_waddr_g_completed;
wire [addr_width-1:0] wside_raddr_g_completed;
generate
if (xpmlab) begin
cross_ptr_mlab xp0 (
.din_clk(rclk),
.din_reg(raddr_g_completed), // must be a register
.dout_clk(wclk),
.dout(wside_raddr_g_completed)
);
defparam xp0 .width = addr_width;
defparam xp0 .target_chip = target_chip;
cross_ptr_mlab xp1 (
.din_clk(wclk),
.din_reg(waddr_g_completed), // must be a register
.dout_clk(rclk),
.dout(rside_waddr_g_completed)
);
defparam xp1 .width = addr_width;
defparam xp1 .target_chip = target_chip;
end
else begin
sync_regs_aclr_m2 sr0 (
.clk(rclk),
.aclr(raclr),
.din(waddr_g_completed),
.dout(rside_waddr_g_completed)
);
defparam sr0 .width = addr_width;
defparam sr0 .depth = sync_stages;
sync_regs_aclr_m2 sr1 (
.clk(wclk),
.aclr(waclr),
.din(raddr_g_completed),
.dout(wside_raddr_g_completed)
);
defparam sr1 .width = addr_width;
defparam sr1 .depth = sync_stages;
end
endgenerate
//////////////////////////////////////////////////
// compare pointers
//////////////////////////////////////////////////
genvar i;
generate
for (i=0; i<flag_dupes; i=i+1) begin : fg
//assign wfull[i] = ~|(wside_raddr_g_completed ^ waddr_g);
//assign rempty[i] = ~|(raddr_g_completed ^ rside_waddr_g_completed);
eq_5_ena eq0 (
.da(5'h0 | wside_raddr_g_completed),
.db(5'h0 | waddr_g),
.ena(1'b1),
.eq(wfull[i])
);
defparam eq0 .target_chip = target_chip; // 0 generic, 1 s4, 2 s5
eq_5_ena eq1 (
.da(5'h0 | raddr_g_completed),
.db(5'h0 | rside_waddr_g_completed),
.ena(1'b1),
.eq(rempty[i])
);
defparam eq1 .target_chip = target_chip; // 0 generic, 1 s4, 2 s5
end
endgenerate
//////////////////////////////////////////////////
// storage array - split in addr reg groups
//////////////////////////////////////////////////
reg [addr_width*ram_groups-1:0] waddr_reg = {(ram_groups*addr_width){1'b0}} /* synthesis preserve */;
reg [width-1:0] wdata_reg = {width{1'b0}};
wire [width-1:0] ram_q;
reg [width-1:0] rdata_reg = {width{1'b0}};
always @(posedge wclk) begin
waddr_reg <= {ram_groups{wptr}};
wdata_reg <= wdata;
end
generate
for (i=0; i<ram_groups;i=i+1) begin : sm
if (target_chip == 1) begin : tc1
s4mlab sm0 (
.wclk(wclk),
.wena(1'b1),
.waddr_reg(waddr_reg[((i+1)*addr_width)-1:i*addr_width]),
.wdata_reg(wdata_reg[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)]),
.raddr(rptr[((i+1)*addr_width)-1:i*addr_width]),
.rdata(ram_q[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)])
);
defparam sm0 .width = width / ram_groups;
defparam sm0 .addr_width = addr_width;
end
else if (target_chip == 2) begin : tc2
s5mlab sm0 (
.wclk(wclk),
.wena(1'b1),
.waddr_reg(waddr_reg[((i+1)*addr_width)-1:i*addr_width]),
.wdata_reg(wdata_reg[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)]),
.raddr(rptr[((i+1)*addr_width)-1:i*addr_width]),
.rdata(ram_q[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)])
);
defparam sm0 .width = width / ram_groups;
defparam sm0 .addr_width = addr_width;
end
else if (target_chip == 5) begin : tc3
a10mlab sm0 (
.wclk(wclk),
.wena(1'b1),
.waddr_reg(waddr_reg[((i+1)*addr_width)-1:i*addr_width]),
.wdata_reg(wdata_reg[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)]),
.raddr(rptr[((i+1)*addr_width)-1:i*addr_width]),
.rdata(ram_q[(i+1)*(width/ram_groups)-1:i*(width/ram_groups)])
);
defparam sm0 .width = width / ram_groups;
defparam sm0 .addr_width = addr_width;
end
else begin : tc66
// synthesis translate_off
initial begin
$display ("error - unsure how to make mlab cells for this target chip");
$stop();
end
// synthesis translate_on
end
end
endgenerate
// output reg - don't defeat clock enable - works really well on s5 mlabs
wire [width-1:0] rdata_mx = rinc ? ram_q: rdata_reg;
always @(posedge rclk) begin
rdata_reg <= rdata_mx;
end
assign rdata = rdata_reg;
//////////////////////////////////////////////////
// write used words
//////////////////////////////////////////////////
generate
if (disable_wused) begin : nwu
assign wused = {addr_width{1'b0}};
end
else begin : wu
wire [addr_width-1:0] wside_raddr_b_completed_w, waddr_b_w;
if (addr_width == 4) begin : wu4
gray_to_bin_4 gtb0 (
.gray (wside_raddr_g_completed),
.bin (wside_raddr_b_completed_w)
);
gray_to_bin_4 gtb1 (
.gray (waddr_g_d),
.bin (waddr_b_w)
);
end else begin : wu5
gray_to_bin_5 gtb0 (
.gray (wside_raddr_g_completed),
.bin (wside_raddr_b_completed_w)
);
gray_to_bin_5 gtb1 (
.gray (waddr_g_d),
.bin (waddr_b_w)
);
end
reg [addr_width-1:0] wside_raddr_b_completed = {addr_width{1'b0}};
reg [addr_width-1:0] waddr_b = {addr_width{1'b0}};
reg [addr_width-1:0] wused_r = {addr_width{1'b0}};
always @(posedge wclk or posedge waclr) begin
if (waclr) begin
wused_r <= {addr_width{1'b0}};
wside_raddr_b_completed <= {addr_width{1'b0}};
waddr_b <= {addr_width{1'b0}};
end
else begin
wused_r <= waddr_b - wside_raddr_b_completed;
wside_raddr_b_completed <= wside_raddr_b_completed_w;
waddr_b <= waddr_b_w;
end
end
assign wused = wused_r;
end
endgenerate
//////////////////////////////////////////////////
// read used words
//////////////////////////////////////////////////
generate
if (disable_rused) begin : nru
assign rused = {addr_width{1'b0}};
end
else begin : ru
wire [addr_width-1:0] rside_waddr_b_completed_w, raddr_b_completed_w;
if (addr_width == 4) begin : ru4
gray_to_bin_4 gtb2 (
.gray (rside_waddr_g_completed),
.bin (rside_waddr_b_completed_w)
);
gray_to_bin_4 gtb3 (
.gray (raddr_g_completed),
.bin (raddr_b_completed_w)
);
end else begin : ru5
gray_to_bin_5 gtb2 (
.gray (rside_waddr_g_completed),
.bin (rside_waddr_b_completed_w)
);
gray_to_bin_5 gtb3 (
.gray (raddr_g_completed),
.bin (raddr_b_completed_w)
);
end
reg [addr_width-1:0] rside_waddr_b_completed = {addr_width{1'b0}};
reg [addr_width-1:0] raddr_b_completed = {addr_width{1'b0}};
reg [addr_width-1:0] rused_r = {addr_width{1'b0}};
always @(posedge rclk or posedge raclr) begin
if (raclr) begin
rused_r <= {addr_width{1'b0}};
rside_waddr_b_completed <= {addr_width{1'b0}};
raddr_b_completed <= {addr_width{1'b0}};
end
else begin
rused_r <= rside_waddr_b_completed - raddr_b_completed;
rside_waddr_b_completed <= rside_waddr_b_completed_w;
raddr_b_completed <= raddr_b_completed_w;
end
end
assign rused = rused_r;
end
endgenerate
////////////////////////////////////
// qualified requests
////////////////////////////////////
//assign wfull[i] = ~|(wside_raddr_g_completed ^ waddr_g);
//assign rempty[i] = ~|(raddr_g_completed ^ rside_waddr_g_completed);
//wire winc = wreq & (~wfull[0] | ~prevent_overflow);
//wire rinc = rreq & (~rempty[0] | ~prevent_underflow);
generate
if (prevent_overflow) begin
neq_5_ena eq2 (
.da(5'h0 | wside_raddr_g_completed),
.db(5'h0 | waddr_g),
.ena(wreq),
.eq(winc)
);
defparam eq2 .target_chip = target_chip; // 0 generic, 1 s4, 2 s5
end
else assign winc = wreq;
endgenerate
generate
if (prevent_underflow) begin
neq_5_ena eq3 (
.da(5'h0 | raddr_g_completed),
.db(5'h0 | rside_waddr_g_completed),
.ena(rreq),
.eq(rinc)
);
defparam eq3 .target_chip = target_chip; // 0 generic, 1 s4, 2 s5
end
else assign rinc = rreq;
endgenerate
endmodule
// fivemark info : 5sgxea7n2f45c2
// fivemark info : max depth : 3.0 luts
// fivemark info : total registers : 282
// fivemark info : total pins : 177
// fivemark info : total virtual pins : 0
// fivemark info : total block memory bits : 0
// fivemark info : comb aluts : ; 69 ; ;
// fivemark info : alms : 126 / 234,720 ( < 1 % )
// fivemark info : worst setup path @ 468.75mhz : 0.491 ns, from gray_cntr_5_sl:a5.wcntr|rl[2].df, to gray_cntr_5_sl:a5.wcntr|rl[1].df}
// fivemark info : worst setup path @ 468.75mhz : 0.612 ns, from cross_ptr_mlab:xp0|dout[2], to gray_cntr_5_sl:a5.wcntr|rl[0].df}
// fivemark info : worst setup path @ 468.75mhz : 0.447 ns, from cross_ptr_mlab:xp0|sync_regs_m2:sr1|sync_sr[0], to cross_ptr_mlab:xp0|s5mlab:s5.sm|ml[3].lrm~ena1regout}
// benchmark info : 10ax115r2f40i1sges
// benchmark info : max depth : 3.0 luts
// benchmark info : total registers : 281
// benchmark info : total pins : 177
// benchmark info : total virtual pins : 0
// benchmark info : total block memory bits : 0
// benchmark info : comb aluts : ; 63 ; ;
// benchmark info : alms : 108 / 427,200 ( < 1 % )
// benchmark info : worst setup path @ 468.75mhz : 0.123 ns, from wdata_reg[46], to a10mlab:sm[2].tc3.sm0|ml[19].lrm~register_clock0}
// benchmark info : worst setup path @ 468.75mhz : 0.159 ns, from gray_cntr_5_sl:a5.wcntr|rl[2].df, to gray_cntr_5_sl:a5.wcntr|rl[1].df}
// benchmark info : worst setup path @ 468.75mhz : 0.129 ns, from gray_cntr_5_sl:a5.wcntr|rl[1].df, to gray_cntr_5_sl:a5.wcntr|rl[3].df}
|
// this program was cloned from: https://github.com/myriadrf/limesdr-mini_gw
// license: apache license 2.0
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
//legal notice: (c)2010 altera corporation. all rights reserved. your
//use of altera corporation's design tools, logic functions and other
//software and tools, and its ampp partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the altera program
//license subscription agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by altera and sold by altera
//or its authorized distributors. please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lms_ctr_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1661603672 : 4920;
endmodule
|
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// $id: $
// $revision: $
// $date: $
// $author: $
//-----------------------------------------------------------------------------
// copyright 2012 altera corporation. all rights reserved.
// altera products are protected under numerous u.s. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// this reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable altera reference design
// license agreement (either as signed by you or found at www.altera.com). by
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and altera corporation. in the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// this reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. by making this reference
// design file available, altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by altera.
/////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
// baeckler - 08-21-2012
// treat me like a register, continually shifts through 5 slices
module a10_5way_register #(
parameter width = 8
)(
input clk,
input [width-1:0] d_reg,
output [width-1:0] q
);
localparam addr_width = 3;
reg [addr_width-1:0] waddr_reg = 0 /* synthesis preserve */;
reg [addr_width-1:0] raddr = 0 /* synthesis preserve */;
always @(posedge clk) begin
case (waddr_reg)
3'h0 : begin waddr_reg <= 3'h1; raddr <= 3'h3; end
3'h1 : begin waddr_reg <= 3'h2; raddr <= 3'h4; end
3'h2 : begin waddr_reg <= 3'h3; raddr <= 3'h0; end
3'h3 : begin waddr_reg <= 3'h4; raddr <= 3'h1; end
3'h4 : begin waddr_reg <= 3'h0; raddr <= 3'h2; end
// error
3'h5 : begin waddr_reg <= 3'h0; raddr <= 3'h0; end
3'h6 : begin waddr_reg <= 3'h0; raddr <= 3'h0; end
3'h7 : begin waddr_reg <= 3'h0; raddr <= 3'h0; end
endcase
end
wire [width-1:0] rdata;
reg [width-1:0] q_r = 0;
always @(posedge clk) begin
q_r <= rdata;
end
assign q = q_r;
wire wena = 1'b1;
genvar i;
generate
for (i=0; i<width; i=i+1) begin : ml
twentynm_mlab_cell lrm (
.clk0(clk),
.ena0(wena),
// synthesis translate off
.clk1(1'b0),
.ena1(1'b1),
.ena2(1'b1),
.clr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
// synthesis translate on
.portabyteenamasks(1'b1),
.portadatain(d_reg[i]),
.portaaddr(waddr_reg),
.portbaddr(raddr),
.portbdataout(rdata[i])
);
defparam lrm .mixed_port_feed_through_mode = "dont_care";
defparam lrm .logical_ram_name = "lrm";
defparam lrm .logical_ram_depth = 1 << addr_width;
defparam lrm .logical_ram_width = width;
defparam lrm .first_address = 0;
defparam lrm .last_address = (1 << addr_width)-1;
defparam lrm .first_bit_number = i;
defparam lrm .data_width = 1;
defparam lrm .address_width = addr_width;
end
endgenerate
endmodule
// benchmark info : 5sgxea7n2f45c2
// benchmark info : max depth : 1.0 luts
// benchmark info : total registers : 14
// benchmark info : total pins : 17
// benchmark info : total virtual pins : 0
// benchmark info : total block memory bits : 0
// benchmark info : comb aluts : ; 7 ; ;
// benchmark info : alms : 14 / 234,720 ( < 1 % )
// benchmark info : worst setup path @ 468.75mhz : 1.313 ns, from raddr[2], to q_r[6]}
// benchmark info : worst setup path @ 468.75mhz : 1.290 ns, from raddr[0], to q_r[7]}
// benchmark info : worst setup path @ 468.75mhz : 1.302 ns, from raddr[0], to q_r[6]}
|
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