code
string |
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// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
// (c) 2001-2015 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
module altera_avalon_mailbox #(
parameter dwidth = 32,
parameter awidth = 2
)(
input clk,
input rst_n,
output irq_msg,
output irq_space,
input [awidth-1:0] avmm_snd_address,
input [dwidth-1:0] avmm_snd_writedata,
input avmm_snd_write,
input avmm_snd_read,
output [dwidth-1:0] avmm_snd_readdata,
output avmm_snd_waitrequest,
input [awidth-1:0] avmm_rcv_address,
input [dwidth-1:0] avmm_rcv_writedata,
input avmm_rcv_write,
input avmm_rcv_read,
output [dwidth-1:0] avmm_rcv_readdata
);
// status register bit definition
localparam full_bit = 1;
localparam msg_pending_bit = 0;
localparam snd_int_bit = 1;
localparam rcv_int_bit = 0;
// wires & registers declaration
reg [dwidth-1:0] command_reg;
reg [dwidth-1:0] pointer_reg;
reg [dwidth-1:0] status_reg;
reg [dwidth-1:0] mask_reg;
wire [dwidth-1:0] command_comb;
wire [dwidth-1:0] pointer_comb;
wire [dwidth-1:0] status_comb;
wire [dwidth-1:0] mask_comb;
wire [dwidth-1:0] snd_act_readdata;
wire [dwidth-1:0] snd_int_readdata;
wire [dwidth-1:0] snd_cmd_reg_rddata;
wire [dwidth-1:0] snd_ptr_reg_rddata;
wire [dwidth-1:0] snd_sts_reg_rddata;
wire [dwidth-1:0] snd_msk_reg_rddata;
wire [dwidth-1:0] rcv_act_readdata;
wire [dwidth-1:0] rcv_int_readdata;
wire [dwidth-1:0] rcv_cmd_reg_rddata;
wire [dwidth-1:0] rcv_ptr_reg_rddata;
wire [dwidth-1:0] rcv_sts_reg_rddata;
wire [dwidth-1:0] rcv_msk_reg_rddata;
reg [dwidth-1:0] readdata_with_waitstate;
wire cmd_reg_snd_access;
wire ptr_reg_snd_access;
wire sts_reg_snd_access;
wire msk_reg_snd_access;
wire cmd_reg_rcv_access;
wire ptr_reg_rcv_access;
wire sts_reg_rcv_access;
wire msk_reg_rcv_access;
wire snd_wr_valid;
wire snd_rd_valid;
wire rcv_rd_valid;
wire rcv_wr_valid;
wire full;
wire pending;
wire snd_mask, rcv_mask;
reg rst_for_bp;
// decoding of address for register target
assign cmd_reg_snd_access = (avmm_snd_address == 2'b00);
assign ptr_reg_snd_access = (avmm_snd_address == 2'b01);
assign sts_reg_snd_access = (avmm_snd_address == 2'b10);
assign msk_reg_snd_access = (avmm_snd_address == 2'b11);
assign cmd_reg_rcv_access = (avmm_rcv_address == 2'b00);
assign ptr_reg_rcv_access = (avmm_rcv_address == 2'b01);
assign sts_reg_rcv_access = (avmm_rcv_address == 2'b10);
assign msk_reg_rcv_access = (avmm_rcv_address == 2'b11);
// registers assignment
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
command_reg <= {(dwidth){1'b0}};
pointer_reg <= {(dwidth){1'b0}};
status_reg <= {(dwidth){1'b0}};
mask_reg <= {(dwidth){1'b0}};
end
else begin
command_reg <= command_comb;
pointer_reg <= pointer_comb;
status_reg <= status_comb;
mask_reg <= mask_comb;
end
end
assign command_comb = (snd_wr_valid & cmd_reg_snd_access) ?
avmm_snd_writedata :
command_reg;
assign pointer_comb = (snd_wr_valid & ptr_reg_snd_access) ?
avmm_snd_writedata :
pointer_reg;
assign mask_comb = {{30{1'b0}},snd_mask, rcv_mask};
assign snd_mask = (snd_wr_valid & msk_reg_snd_access) ?
avmm_snd_writedata[snd_int_bit]:
mask_reg[snd_int_bit];
assign rcv_mask = (rcv_wr_valid & msk_reg_rcv_access) ?
avmm_rcv_writedata[rcv_int_bit]:
mask_reg[rcv_int_bit];
assign status_comb = {30'b0, full, pending};
assign full = status_reg[full_bit] ? !(cmd_reg_rcv_access & rcv_rd_valid): /*(read from rcv will set 0)*/
(cmd_reg_snd_access & snd_wr_valid); /*(write of cmd_reg will set 1)*/
assign pending = status_reg[msg_pending_bit] ? !(cmd_reg_rcv_access & rcv_rd_valid): /*(read from rcv will set 0)*/
(cmd_reg_snd_access & snd_wr_valid); /*(write of cmd_reg will set 1)*/
// for time being, with 1 message mailbox availability, full and pending logic is the same.
// however, if a message queue >1 is implemented, full and pending condition will be different.
// the pending logic will then honor the empty status of the queue.
// avalon mm interface handling
// avalon mm slave interfaces of the sender has backpressure flow control with waitrequest signal
// avalon mm slave interfaces of the receiver has readwaittime = 1, and has write capability only to the mask_reg
// assert waitreq during reset to avoid lockup
assign snd_wr_valid = avmm_snd_write & !avmm_snd_waitrequest;
assign snd_rd_valid = avmm_snd_read & !avmm_snd_waitrequest;
assign avmm_snd_waitrequest = (avmm_snd_write & cmd_reg_snd_access & status_reg[full_bit]) |
(avmm_snd_write & ptr_reg_snd_access & status_reg[full_bit]) |
// add condition for read transaction if location being read is empty, no need for now, but maybe for future
rst_for_bp;
assign avmm_snd_readdata = snd_act_readdata;
assign snd_act_readdata = snd_rd_valid ? snd_int_readdata : {(dwidth){1'b0}};
assign snd_int_readdata = snd_cmd_reg_rddata |
snd_ptr_reg_rddata |
snd_sts_reg_rddata |
snd_msk_reg_rddata ;
assign snd_cmd_reg_rddata = command_reg & {(dwidth){cmd_reg_snd_access}};
assign snd_ptr_reg_rddata = pointer_reg & {(dwidth){ptr_reg_snd_access}};
assign snd_sts_reg_rddata = status_reg & {(dwidth){sts_reg_snd_access}};
assign snd_msk_reg_rddata = mask_reg & {(dwidth){msk_reg_snd_access}};
assign rcv_wr_valid = avmm_rcv_write;
assign rcv_rd_valid = avmm_rcv_read;
assign avmm_rcv_readdata = readdata_with_waitstate;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) rst_for_bp <= 1'b1;
else rst_for_bp <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) readdata_with_waitstate <= {(dwidth){1'b0}};
else readdata_with_waitstate <= rcv_act_readdata;
end
assign rcv_act_readdata = rcv_rd_valid ? rcv_int_readdata : {(dwidth){1'b0}};
assign rcv_int_readdata = rcv_cmd_reg_rddata |
rcv_ptr_reg_rddata |
rcv_sts_reg_rddata |
rcv_msk_reg_rddata ;
assign rcv_cmd_reg_rddata = command_reg & {(dwidth){cmd_reg_rcv_access}};
assign rcv_ptr_reg_rddata = pointer_reg & {(dwidth){ptr_reg_rcv_access}};
assign rcv_sts_reg_rddata = status_reg & {(dwidth){sts_reg_rcv_access}};
assign rcv_msk_reg_rddata = mask_reg & {(dwidth){msk_reg_rcv_access}};
assign irq_space = ~status_reg[full_bit] & mask_reg[snd_int_bit];
assign irq_msg = status_reg[msg_pending_bit] & mask_reg[rcv_int_bit];
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
module UBCSe_11_0_10_1 (S, X, Y);
output [12:0] S;
input [11:0] X;
input [10:1] Y;
wire [11:1] Z;
UBExtender_10_1_1000 U0 (Z[11:1], Y[10:1]);
UBPureCSe_11_1 U1 (S[12:1], X[11:1], Z[11:1]);
UB1DCON_0 U2 (S[0], X[0]);
endmodule
|
module hi_us_3( // @[tage.scala:89:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:89:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:89:27]
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Write Data FIFO
//
// File : alt_ddrx_wdata_fifo.v
//
// Abstract : Store write data
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_wdata_fifo
#(parameter WDATA_BEATS_WIDTH = 9,
LOCAL_DATA_WIDTH = 32,
LOCAL_SIZE_WIDTH = 6,
DWIDTH_RATIO = 2,
FAMILY = "Stratix"
)(
// input
ctl_clk,
ctl_reset_n,
write_req_to_wfifo,
wdata_to_wfifo,
be_to_wfifo,
wdata_fifo_read,
//output
wdata_fifo_full,
wdata_fifo_wdata,
wdata_fifo_be,
beats_in_wfifo
);
localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8;
localparam LOCAL_WFIFO_Q_WIDTH = LOCAL_DATA_WIDTH + LOCAL_BE_WIDTH;
input ctl_clk; // controller clock
input ctl_reset_n; // controller reset_n, synchronous to ctl_clk
input write_req_to_wfifo;
input wdata_fifo_read;
input [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
input [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
output [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
output [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
output wdata_fifo_full;
output [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
wire ctl_clk;
wire ctl_reset_n;
wire reset;
wire write_req_to_wfifo;
wire wdata_fifo_read;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
wire [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_data;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_q;
wire wdata_fifo_full;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
wire [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
reg [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
assign wfifo_data = {be_to_wfifo,wdata_to_wfifo};
assign wdata_fifo_be = wfifo_q[LOCAL_WFIFO_Q_WIDTH-1 : LOCAL_DATA_WIDTH];
assign wdata_fifo_wdata = wfifo_q[LOCAL_DATA_WIDTH-1 : 0];
assign reset = !ctl_reset_n; // scfifo has an active high async reset
//We fix the fifo depth to 256 in order to match the depth of the M9k memories that has the maximum data width (256 depth x 36 width),
//by doing this, we can minimize the usage of M9k.
//Currently, we need at lease 18 M9k (256 x 36)
//Calculation : Maximum data width that we support, 72 (with ecc) * 8 (quarter rate) = 576, byteen bit = 576 / 8 = 72, LOCAL_WFIFO_Q_WIDTH = 576 + 72 = 648
//Number of M9k we need = 648 / 36 = 18.
scfifo #(
.intended_device_family (FAMILY),
.lpm_width (LOCAL_WFIFO_Q_WIDTH), // one BE per byte, not per DQS
.lpm_numwords (256),
.lpm_widthu (log2 (256)),
.almost_full_value (256-16), // a bit of slack to avoid overflowing
.lpm_type ("scfifo"),
.lpm_showahead ("OFF"), // Always OFF at the moment
.overflow_checking ("OFF"),
.underflow_checking ("OFF"),
.use_eab ("ON"),
.add_ram_output_register ("ON") // Always ON at the moment
) wdata_fifo (
.rdreq (wdata_fifo_read),
.aclr (reset),
.clock (ctl_clk),
.wrreq (write_req_to_wfifo),
.data (wfifo_data),
.full (),
.q (wfifo_q),
.sclr (1'b0),
.usedw (),
.empty (),
.almost_full (wdata_fifo_full),
.almost_empty ()
);
// Tell the state machine how many data entry is in the write data fifo
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (~ctl_reset_n) begin
beats_in_wfifo <= 0;
end
else if(write_req_to_wfifo) begin
if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo;
end
else begin
beats_in_wfifo <= beats_in_wfifo + 1'b1;
end
end
else if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo - 1'b1;
end
end
function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule
|
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel fpga ip license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
ctl_list_width = 3, // number of dram commands that can be tracked at a time
ctl_list_depth = 8,
ctl_list_init_value_type = "incr", // incr, zero
ctl_list_init_valid = "valid" // valid, invalid
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [ctl_list_width-1:0] list_get_entry_id;
output [ctl_list_depth-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [ctl_list_width-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [ctl_list_width-1:0] list_get_entry_id;
reg [ctl_list_depth-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [ctl_list_width-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [ctl_list_width-1:0] list [ctl_list_depth-1:0];
reg list_v [ctl_list_depth-1:0];
reg [ctl_list_depth-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[ctl_list_depth-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < ctl_list_depth; i = i + 1'b1)
begin
// initialize every entry
if (ctl_list_init_value_type == "incr")
begin
list [i] <= i;
end
else
begin
list [i] <= {ctl_list_width{1'b0}};
end
if (ctl_list_init_valid == "valid")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {ctl_list_depth{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [ctl_list_depth-1] <= 0;
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < ctl_list_depth; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < ctl_list_depth;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the intel program license subscription
// agreement, intel megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by intel and sold by
// intel or its authorized distributors. please refer to the applicable
// agreement for further details.
// $file: //acds/rel/16.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $revision: #1 $
// $date: 2016/08/07 $
// $author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter symbols_per_beat = 1;
parameter bits_per_symbol = 8;
parameter pipeline_ready = 1;
localparam data_width = symbols_per_beat * bits_per_symbol;
input clk;
input reset;
output in_ready;
input in_valid;
input [data_width-1:0] in_data;
input out_ready;
output out_valid;
output [data_width-1:0] out_data;
reg full0;
reg full1;
reg [data_width-1:0] data0;
reg [data_width-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (pipeline_ready == 1)
begin : registered_ready_pline
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {data_width{1'b0}};
data1 <= {data_width{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : unregistered_ready_pline
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the altera program license subscription
// agreement, altera megacore function license agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by altera and sold by
// altera or its authorized distributors. please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** reset logic for application layer (app_rstn) triggered by hip reset behavior +
//*/
module altpcierd_hip_rs # (
parameter hiprst_use_ltssm_hotreset = 1,
parameter hiprst_use_ltssm_disable = 1,
parameter hiprst_use_l2 = 1,
parameter hiprst_use_dlup_exit = 1
) (
input dlup_exit,
input hotrst_exit,
input l2_exit,
input [ 4: 0] ltssm,
input npor,
input pld_clk,
input test_sim,
output reg app_rstn
);
localparam [4:0] ltssm_pol = 5'b00010;
localparam [4:0] ltssm_cpl = 5'b00011;
localparam [4:0] ltssm_det = 5'b00000;
localparam [4:0] ltssm_rcv = 5'b01100;
localparam [4:0] ltssm_dis = 5'b10000;
localparam [23:0] rcv_timeout = 24'd6000000;
localparam [10:0] rstn_cnt_max = 11'h400;
localparam [10:0] rstn_cnt_maxsim = 11'h20;
//synthesis translate_off
localparam altpcie_sv_hip_ast_hwtcl_sim_only = 1;
//synthesis translate_on
//synthesis read_comments_as_hdl on
//localparam altpcie_sv_hip_ast_hwtcl_sim_only = 0;
//synthesis read_comments_as_hdl off
reg [1:0] npor_syncr ;
reg npor_sync_pld_clk;
reg app_rstn0;
reg crst0;
reg [ 4: 0] ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
reg [ 10: 0] rsnt_cntn;
reg [23:0] recovery_cnt;
reg recovery_rst;
reg ltssm_disable;
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
dlup_exit_r <= 1'b1;
hotrst_exit_r <= 1'b1;
l2_exit_r <= 1'b1;
exits_r <= 1'b0;
ltssm_r <= 5'h0;
app_rstn <= 1'b0;
ltssm_disable <= 1'b0;
end
else begin
ltssm_r <= ltssm;
dlup_exit_r <= (hiprst_use_dlup_exit==0) ?1'b1:dlup_exit;
hotrst_exit_r <= (hiprst_use_ltssm_hotreset==0)?1'b1:hotrst_exit;
l2_exit_r <= (hiprst_use_l2==0) ?1'b1:l2_exit;
ltssm_disable <= (hiprst_use_ltssm_disable==0) ?1'b0:(ltssm_r == ltssm_dis)?1'b1:1'b0;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (ltssm_disable == 1'b1)| (recovery_rst == 1'b1);
app_rstn <= app_rstn0;
end
end
//reset synchronizer npor --> npor_sync_pld_clk
always @(posedge pld_clk or negedge npor) begin
if (npor == 1'b0) begin
npor_syncr <= 2'b00;
npor_sync_pld_clk <= 1'b0;
end
else begin
npor_syncr[0] <= 1'b1;
npor_syncr[1] <= npor_syncr[0];
npor_sync_pld_clk <= npor_syncr[1];
end
end
//delay hip reset upon npor
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
app_rstn0 <= 1'b0;
rsnt_cntn <= 11'h0;
end
else if (exits_r == 1'b1) begin
app_rstn0 <= 1'b0;
rsnt_cntn <= 11'h3f0;
end
else begin
rsnt_cntn <= rsnt_cntn + 11'h1;
if ((test_sim == 1'b1) &&
(rsnt_cntn >= rstn_cnt_maxsim) &&
(altpcie_sv_hip_ast_hwtcl_sim_only==1)) begin
app_rstn0 <= 1'b1;
end
else if (rsnt_cntn == rstn_cnt_max) begin
app_rstn0 <= 1'b1;
end
end
end
// monitor if ltssm is frozen in recovery state
// issue reset if timeout rcv_timeout
always @(posedge pld_clk or negedge npor_sync_pld_clk) begin
if (npor_sync_pld_clk == 1'b0) begin
recovery_cnt <= {24{1'b0}};
recovery_rst <= 1'b0;
end
else begin
if (ltssm_r != ltssm_rcv) begin
recovery_cnt <= {24{1'b0}};
end
else if (recovery_cnt == rcv_timeout) begin
recovery_cnt <= recovery_cnt;
end
else if (ltssm_r == ltssm_rcv) begin
recovery_cnt <= recovery_cnt + 24'h1;
end
if (recovery_cnt == rcv_timeout) begin
recovery_rst <= 1'b1;
end
else if (ltssm_r != ltssm_rcv) begin
recovery_rst <= 1'b0;
end
end
end
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_arbiter #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_REG_REQ = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_DISABLE_PRIORITY = 1
)
(
ctl_clk,
ctl_reset_n,
// Common
stall_row_arbiter,
stall_col_arbiter,
// Sideband Interface
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
// TBP Interface
row_req,
col_req,
act_req,
pch_req,
rd_req,
wr_req,
row_grant,
col_grant,
act_grant,
pch_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_activate,
tbp_precharge,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_rmw_correct,
tbp_rmw_partial,
tbp_age,
tbp_priority,
// Rank Timer Interface
can_activate,
can_precharge,
can_write,
can_read,
// Arbiter Output Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// Common
input stall_row_arbiter;
input stall_col_arbiter;
// Sideband Interface
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
// TBP Interface
input [CFG_CTL_TBP_NUM - 1 : 0] row_req;
input [CFG_CTL_TBP_NUM - 1 : 0] col_req;
input [CFG_CTL_TBP_NUM - 1 : 0] act_req;
input [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
input [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
input [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
output [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
output or_row_grant;
output or_col_grant;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
input [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
input [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
input [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
input [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
// Rank Timer Interface
input [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] can_write;
input [CFG_CTL_TBP_NUM - 1 : 0] can_read;
// Arbiter Output Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
wire one = 1'b1;
wire zero = 1'b0;
// TBP Interface
reg [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
reg or_row_grant;
reg or_col_grant;
// Arbiter Output Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// Common
reg granted_read [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_write [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_c ;
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_INT_SIZE_WIDTH - 1 : 0] granted_size [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_DATA_ID_WIDTH - 1 : 0] granted_dataid [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] granted_localid [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_ap [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_burst_chop [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
// Arbiter
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
reg int_or_row_grant;
reg int_or_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Granted logic specific grant signals
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
granted_row_grant = row_grant;
granted_col_grant = col_grant;
granted_act_grant = act_grant;
granted_pch_grant = pch_grant;
granted_rd_grant = rd_grant;
granted_wr_grant = wr_grant;
log2_granted_row_grant = log2_row_grant;
log2_granted_col_grant = log2_col_grant;
log2_granted_act_grant = log2_act_grant;
log2_granted_pch_grant = log2_pch_grant;
log2_granted_rd_grant = log2_rd_grant;
log2_granted_wr_grant = log2_wr_grant;
end
//----------------------------------------------------------------------------------------------------
// Sideband outputs
//----------------------------------------------------------------------------------------------------
// Precharge all
always @ (*)
begin
arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
end
// Refresh
always @ (*)
begin
arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
end
// Self refresh
always @ (*)
begin
arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
end
// Power down
always @ (*)
begin
arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
end
// Power down
always @ (*)
begin
arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
end
// ZQ calibration
always @ (*)
begin
arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
end
// LMR
always @ (*)
begin
arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
end
//----------------------------------------------------------------------------------------------------
// Non arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
// Burst chop
always @ (*)
begin
arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
end
// Burst terminate
always @ (*)
begin
arb_do_burst_terminate = 0;
end
// RMW Correct
always @ (*)
begin
arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
end
// RMW Partial
always @ (*)
begin
arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
end
// LMR
always @ (*)
begin
arb_do_lmr = 0;
end
// Local ID
always @ (*)
begin
arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
end
// Data ID
always @ (*)
begin
arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
end
// Size
always @ (*)
begin
arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
end
// Column address
// column command will only require column address, therefore there will be no conflcting column addresses
always @ (*)
begin
arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
end
//----------------------------------------------------------------------------------------------------
// Arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_LOW_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_LOW_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_HIGH_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_HIGH_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_r [CFG_CTL_TBP_NUM - 1], granted_chipsel_c [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
end
end
else
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_CTL_TBP_NUM - 1]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_c [CFG_CTL_TBP_NUM - 1], granted_chipsel_r [CFG_CTL_TBP_NUM - 1]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Granted outputs
//----------------------------------------------------------------------------------------------------
// Chip address
always @ (*)
begin
granted_chipsel_r [0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
granted_chipsel_c [0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
end
// Bank address
always @ (*)
begin
granted_bank_r [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
granted_bank_c [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
end
// Row address
always @ (*)
begin
granted_row_r [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
granted_row_c [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
end
// Column address
always @ (*)
begin
granted_col [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col [CFG_MEM_IF_COL_WIDTH - 1 : 0];
end
// Size
always @ (*)
begin
granted_size [0] = {CFG_INT_SIZE_WIDTH {granted_col_grant [0]}} & tbp_size [CFG_INT_SIZE_WIDTH - 1 : 0];
end
// Local ID
always @ (*)
begin
granted_localid [0] = {CFG_LOCAL_ID_WIDTH {granted_col_grant [0]}} & tbp_localid [CFG_LOCAL_ID_WIDTH - 1 : 0];
end
// Data ID
always @ (*)
begin
granted_dataid [0] = {CFG_DATA_ID_WIDTH {granted_col_grant [0]}} & tbp_dataid [CFG_DATA_ID_WIDTH - 1 : 0];
end
// Auto precharge
always @ (*)
begin
granted_ap [0] = granted_col_grant [0] & tbp_ap [ 0];
end
// Burst Chop
always @ (*)
begin
granted_burst_chop [0] = granted_col_grant [0] & tbp_burst_chop [ 0];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [0] = granted_col_grant [0] & tbp_rmw_correct [ 0];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [0] = granted_col_grant [0] & tbp_rmw_partial [ 0];
end
generate
begin
genvar j_tbp;
for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : granted_information_per_tbp
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] chipsel_addr = tbp_chipsel [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] bank_addr = tbp_bank [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr = tbp_row [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr = tbp_col [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
wire [CFG_INT_SIZE_WIDTH - 1 : 0] size = tbp_size [(j_tbp + 1) * CFG_INT_SIZE_WIDTH - 1 : j_tbp * CFG_INT_SIZE_WIDTH ];
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] localid = tbp_localid [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH - 1 : j_tbp * CFG_LOCAL_ID_WIDTH ];
wire [CFG_DATA_ID_WIDTH - 1 : 0] dataid = tbp_dataid [(j_tbp + 1) * CFG_DATA_ID_WIDTH - 1 : j_tbp * CFG_DATA_ID_WIDTH ];
wire ap = tbp_ap [(j_tbp + 1) - 1 : j_tbp ];
wire burst_chop = tbp_burst_chop [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_correct = tbp_rmw_correct [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_partial = tbp_rmw_partial [(j_tbp + 1) - 1 : j_tbp ];
// Chip address
always @ (*)
begin
granted_chipsel_r [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r [j_tbp - 1];
granted_chipsel_c [j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c [j_tbp - 1];
end
// Bank address
always @ (*)
begin
granted_bank_r [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr ) | granted_bank_r [j_tbp - 1];
granted_bank_c [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr ) | granted_bank_c [j_tbp - 1];
end
// Row address
always @ (*)
begin
granted_row_r [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr ) | granted_row_r [j_tbp - 1];
granted_row_c [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr ) | granted_row_c [j_tbp - 1];
end
// Column address
always @ (*)
begin
granted_col [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr ) | granted_col [j_tbp - 1];
end
// Size
always @ (*)
begin
granted_size [j_tbp] = ({CFG_INT_SIZE_WIDTH {granted_col_grant [j_tbp]}} & size ) | granted_size [j_tbp - 1];
end
// Local ID
always @ (*)
begin
granted_localid [j_tbp] = ({CFG_LOCAL_ID_WIDTH {granted_col_grant [j_tbp]}} & localid ) | granted_localid [j_tbp - 1];
end
// Data ID
always @ (*)
begin
granted_dataid [j_tbp] = ({CFG_DATA_ID_WIDTH {granted_col_grant [j_tbp]}} & dataid ) | granted_dataid [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_ap [j_tbp] = ( granted_col_grant [j_tbp] & ap ) | granted_ap [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_burst_chop [j_tbp] = ( granted_col_grant [j_tbp] & burst_chop ) | granted_burst_chop [j_tbp - 1];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [j_tbp] = ( granted_col_grant [j_tbp] & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [j_tbp] = ( granted_col_grant [j_tbp] & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Arbiter
//
// Arbitration Rules (Priority Command-Aging Arbiter):
//
// - If only one master is requesting, grant that master immediately ELSE
// - If two of more masters are requesting:
// - Grant the request with priority ELSE
// - Grant read request over write request ELSE
// - Grant oldest request
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common logic
//----------------------------------------------------------------------------------------------------
// Indicate OR of both grant signal
assign all_grant = row_grant | col_grant;
//----------------------------------------------------------------------------------------------------
// Priority Command-aging logic
//----------------------------------------------------------------------------------------------------
// ==========Command-Aging==========
//
// The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies will have the following value:
// TBP0 age - 0000
// TBP1 age - 0001
// TBP2 age - 0011
// TBP3 age - 0111
// Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
// TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
// TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
// So the oldest_req signal will have "0010"
//
// ==========Priority==========
//
// The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
// if there are more than 1 priority command, it will pick the oldest priority command
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies and priority bit will have the following value:
// TBP0 age - 0000 priority - 0
// TBP1 age - 0001 priority - 1
// TBP2 age - 0011 priority - 1
// TBP3 age - 0111 priority - 0
// Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
// and the rest will be set to '0'
// If there is/are priority command/s, we need to select between those priority command
// if there is no priority command, we set int_priority to all '1'
// this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
always @ (*)
begin
int_act_priority = {CFG_CTL_TBP_NUM{one}};
int_pch_priority = {CFG_CTL_TBP_NUM{one}};
if (CFG_DISABLE_PRIORITY == 1)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
if ((tbp_priority & col_req) == 0)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
int_col_priority = tbp_priority;
end
end
end
generate
begin
genvar k_tbp;
for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
begin : priority_request_per_tbp
wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
reg pre_calculated_act_info;
reg pre_calculated_pch_info;
reg pre_calculated_rd_info;
reg pre_calculated_wr_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
if (CFG_REG_REQ)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_info <= 1'b0;
pre_calculated_pch_info <= 1'b0;
pre_calculated_rd_info <= 1'b0;
pre_calculated_wr_info <= 1'b0;
end
else
begin
pre_calculated_act_info <= int_act_priority [k_tbp];
pre_calculated_pch_info <= int_pch_priority [k_tbp];
pre_calculated_rd_info <= int_col_priority [k_tbp];
pre_calculated_wr_info <= int_col_priority [k_tbp];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_age_info <= 0;
pre_calculated_pch_age_info <= 0;
pre_calculated_rd_age_info <= 0;
pre_calculated_wr_age_info <= 0;
end
else
begin
pre_calculated_act_age_info <= current_age & int_act_priority;
pre_calculated_pch_age_info <= current_age & int_pch_priority;
pre_calculated_rd_age_info <= current_age & int_col_priority;
pre_calculated_wr_age_info <= current_age & int_col_priority;
end
end
end
else
begin
always @ (*)
begin
pre_calculated_act_info = int_act_priority [k_tbp];
pre_calculated_pch_info = int_pch_priority [k_tbp];
pre_calculated_rd_info = int_col_priority [k_tbp];
pre_calculated_wr_info = int_col_priority [k_tbp];
end
always @ (*)
begin
pre_calculated_act_age_info = current_age & int_act_priority;
pre_calculated_pch_age_info = current_age & int_pch_priority;
pre_calculated_rd_age_info = current_age & int_col_priority;
pre_calculated_wr_age_info = current_age & int_col_priority;
end
end
always @ (*)
begin
oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
oldest_rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp] & ~|(pre_calculated_rd_age_info & rd_req & can_read );
oldest_wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp] & ~|(pre_calculated_wr_age_info & wr_req & can_write );
end
always @ (*)
begin
act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp];
pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp];
wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp];
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Arbiter logic
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
// Full rate arbiter
always @ (*)
begin
int_row_grant = 0;
int_col_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_row_grant = 1'b0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
end
else
begin
// Half and quarter rate arbiter
// Row arbiter
always @ (*)
begin
int_row_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_or_row_grant = 1'b0;
if (!stall_row_arbiter && !or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
end
else if (!stall_row_arbiter && !or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
end
end
// Column arbiter
always @ (*)
begin
int_col_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_col_grant = 1'b0;
if (!stall_col_arbiter && !or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
end
else if (!stall_col_arbiter && !or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
end
end
end
end
endgenerate
generate
begin
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_grant <= 0;
col_grant <= 0;
act_grant <= 0;
pch_grant <= 0;
rd_grant <= 0;
wr_grant <= 0;
or_row_grant <= 0;
or_col_grant <= 0;
end
else
begin
row_grant <= int_row_grant;
col_grant <= int_col_grant;
act_grant <= int_act_grant;
pch_grant <= int_pch_grant;
rd_grant <= int_rd_grant;
wr_grant <= int_wr_grant;
or_row_grant <= int_or_row_grant;
or_col_grant <= int_or_col_grant;
end
end
always @ (*)
begin
log2_row_grant = log2(row_grant);
log2_col_grant = log2(col_grant);
log2_act_grant = log2(act_grant);
log2_pch_grant = log2(pch_grant);
log2_rd_grant = log2(rd_grant );
log2_wr_grant = log2(wr_grant );
end
end
else
begin
always @ (*)
begin
row_grant = int_row_grant;
col_grant = int_col_grant;
act_grant = int_act_grant;
pch_grant = int_pch_grant;
rd_grant = int_rd_grant;
wr_grant = int_wr_grant;
log2_row_grant = log2(int_row_grant);
log2_col_grant = log2(int_col_grant);
log2_act_grant = log2(int_act_grant);
log2_pch_grant = log2(int_pch_grant);
log2_rd_grant = log2(int_rd_grant );
log2_wr_grant = log2(int_wr_grant );
or_row_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
or_col_grant = 1'b0; // Hardwire this to 0 in non register-grant mode
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Arbiter
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
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// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500011272 : 255;
endmodule
|
module Router_20( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_5_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_5_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_2_to_8_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_2_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_5_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [36:0] _ingress_unit_2_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_5_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_1_from_8_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_5_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
|
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: v_sync.v
//
// Description:
// This is the VSYNC signal generator. It generates
// the appropriate VSYNC signal for the target TFT display. The core
// of this module is a state machine that controls 4 counters and the
// VSYNC and V_DE signals.
//
// Design Notes:
// -- Input clock is (~HSYNC)
// -- Input rst is vsync_rst signal generated from the h_sync.v module
// -- V_DE is and with H_DE to generate DE signal for the TFT display
// -- v_bp_cnt_tc is the terminal count of the back porch time counter. Used to
// -- generate get_line_start pulse.
// -- v_l_cnt_tc is the terminal count of the line time counter. Used to not
// -- generate get_line_start pulse.
//
//-----------------------------------------------------------------------------
// Structure:
// -- v_sync.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/ 100 ps
module v_sync(
clk, // I
clk_stb, // I
rst, // I
VSYNC, // O
V_DE, // O
v_bp_cnt_tc, // O
v_l_cnt_tc); // O
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input clk_stb;
input rst;
output VSYNC;
output V_DE;
output v_bp_cnt_tc;
output v_l_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg V_DE;
reg VSYNC;
reg [0:1] v_p_cnt; // 2-bit counter (2 HSYNCs for pulse time)
reg [0:4] v_bp_cnt; // 5-bit counter (31 HSYNCs for back porch time)
reg [0:8] v_l_cnt; // 9-bit counter (480 HSYNCs for line time)
reg [0:3] v_fp_cnt; // 4-bit counter (12 HSYNCs for front porch time)
reg v_p_cnt_ce;
reg v_bp_cnt_ce;
reg v_l_cnt_ce;
reg v_fp_cnt_ce;
reg v_p_cnt_clr;
reg v_bp_cnt_clr;
reg v_l_cnt_clr;
reg v_fp_cnt_clr;
reg v_p_cnt_tc;
reg v_bp_cnt_tc;
reg v_l_cnt_tc;
reg v_fp_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - State Declaration
///////////////////////////////////////////////////////////////////////////////
parameter [0:4] SET_COUNTERS = 5'b00001;
parameter [0:4] PULSE = 5'b00010;
parameter [0:4] BACK_PORCH = 5'b00100;
parameter [0:4] LINE = 5'b01000;
parameter [0:4] FRONT_PORCH = 5'b10000;
reg [0:4] VSYNC_cs /*synthesis syn_encoding="onehot"*/;
reg [0:4] VSYNC_ns;
///////////////////////////////////////////////////////////////////////////////
// clock enable State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
reg clk_stb_d1;
reg clk_ce_neg;
reg clk_ce_pos;
always @ (posedge clk)
begin
clk_stb_d1 <= clk_stb;
clk_ce_pos <= clk_stb & ~clk_stb_d1;
clk_ce_neg <= ~clk_stb & clk_stb_d1;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (rst) VSYNC_cs = SET_COUNTERS;
else if (clk_ce_pos) VSYNC_cs = VSYNC_ns;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Combinatorial Block
///////////////////////////////////////////////////////////////////////////////
always @ (VSYNC_cs or v_p_cnt_tc or v_bp_cnt_tc or v_l_cnt_tc or v_fp_cnt_tc)
begin
case (VSYNC_cs)
/////////////////////////////////////////////////////////////////////////
// SET COUNTERS STATE
// -- Clear and de-enable all counters on frame_start signal
/////////////////////////////////////////////////////////////////////////
SET_COUNTERS: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// PULSE STATE
// -- Enable pulse counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
PULSE: begin
v_p_cnt_ce = 1;
v_p_cnt_clr = 0;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 0;
V_DE = 0;
if (v_p_cnt_tc == 0) VSYNC_ns = PULSE;
else VSYNC_ns = BACK_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// BACK PORCH STATE
// -- Enable back porch counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
BACK_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 1;
v_bp_cnt_clr = 0;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
if (v_bp_cnt_tc == 0) VSYNC_ns = BACK_PORCH;
else VSYNC_ns = LINE;
end
/////////////////////////////////////////////////////////////////////////
// LINE STATE
// -- Enable line counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
LINE: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 1;
v_l_cnt_clr = 0;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 1;
if (v_l_cnt_tc == 0) VSYNC_ns = LINE;
else VSYNC_ns = FRONT_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// FRONT PORCH STATE
// -- Enable front porch counter
// -- De-enable others
// -- Wraps to PULSE state
/////////////////////////////////////////////////////////////////////////
FRONT_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
if (v_fp_cnt_tc == 0) VSYNC_ns = FRONT_PORCH;
else VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// DEFAULT STATE
/////////////////////////////////////////////////////////////////////////
default: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = SET_COUNTERS;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Pulse Counter - Counts 2 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_p_cnt_clr) begin
v_p_cnt = 2'b0;
v_p_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_p_cnt_ce) begin
if (v_p_cnt == 1) begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 1;
end
else begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Back Porch Counter - Counts 31 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_bp_cnt_clr) begin
v_bp_cnt = 5'b0;
v_bp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_bp_cnt_ce) begin
if (v_bp_cnt == 30) begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 1;
end
else begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Line Counter - Counts 480 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_l_cnt_clr) begin
v_l_cnt = 9'b0;
v_l_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_l_cnt_ce) begin
if (v_l_cnt == 479) begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 1;
end
else begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Front Porch Counter - Counts 12 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_fp_cnt_clr) begin
v_fp_cnt = 4'b0;
v_fp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_fp_cnt_ce) begin
if (v_fp_cnt == 11) begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 1;
end
else begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 0;
end
end
end
end
endmodule
|
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