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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg alu_ltu, alu_lts;
logic [3:0] in_op1;
logic [3:0] in_op2;
reg aaa_ltu, aaa_lts;
always @(posedge clk) begin
in_op1 = 4'sb1110;
in_op2 = 4'b0010;
aaa_ltu = in_op1 < in_op2;
// bug999
aaa_lts = $signed(in_op1) < $signed(in_op2);
`checkh (aaa_ltu, 1'b0);
`checkh (aaa_lts, 1'b1);
end
generate if (1) begin
always @(posedge clk) begin
in_op1 = 4'sb1110;
in_op2 = 4'b0010;
alu_ltu = in_op1 < in_op2;
// bug999
alu_lts = $signed(in_op1) < $signed(in_op2);
`checkh (alu_ltu, 1'b0);
`checkh (alu_lts, 1'b1);
$write("*-* All Finished *-*\n");
$finish;
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
//
// This code instantiates a module that calls the various array querying
// functions.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
// Check the array sizing functions work correctly.
module array_test
#( parameter
LEFT = 5,
RIGHT = 55)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
reg [7:0] a [LEFT:RIGHT];
// verilator lint_on LITENDIAN
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This files is used to generated the BLKLOOPINIT error which
// is actually caused by not being able to unroll the for loop.
//
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] tmp [3:0];
initial begin
tmp[0] = 4'b0000;
tmp[2] = 4'b0010;
tmp[3] = 4'b0011;
end
// Test loop
always @ (posedge clk) begin
int i;
int j;
for (i = 0;(i < 4) && (i > 1); i++) begin
tmp[i] <= tmp[i-i];
end
if (tmp[0] != 4'b0000) $stop;
if (tmp[3] != 4'b0011) $stop;
j = 0; for (i=$c32("1"); i<3; ++i) j++;
if (j!=2) $stop;
j = 0; for (i=1; i<$c32("3"); ++i) j++;
if (j!=2) $stop;
j = 0; for (i=1; i<3; i=i+$c32("1")) j++;
if (j!=2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 8;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
|
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, dato
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input [3:0] we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] dato; // output data bus
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
`ifdef ETH_XILINX_RAMB4
/*RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);*/
RAMB4_S8 ram0
(
.DO (dato[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
.CLK (clk),
.WE (we[0]),
.RST (rst)
);
RAMB4_S8 ram1
(
.DO (dato[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
.CLK (clk),
.WE (we[1]),
.RST (rst)
);
RAMB4_S8 ram2
(
.DO (dato[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
.CLK (clk),
.WE (we[2]),
.RST (rst)
);
RAMB4_S8 ram3
(
.DO (dato[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
.CLK (clk),
.WE (we[3]),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
//vs_hdsp_256x32_bist ram0_bist
vs_hdsp_256x32_bw_bist ram0_bist
`else
//vs_hdsp_256x32 ram0
vs_hdsp_256x32_bw ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (dato)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_ARTISAN_RAM
`ifdef ETH_BIST
//art_hssp_256x32_bist ram0_bist
art_hssp_256x32_bw_bist ram0_bist
`else
//art_hssp_256x32 ram0
art_hssp_256x32_bw ram0
`endif
(
.CLK (clk),
.CEN (!ce),
.WEN (~we),
.OEN (!oe),
.A (addr),
.D (di),
.Q (dato)
`ifdef ETH_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // !ETH_ARTISAN_RAM
`ifdef ETH_ALTERA_ALTSYNCRAM
/*
altera_spram_256x32 altera_spram_256x32_inst
(
.address (addr),
.wren (ce & we),
.clock (clk),
.data (di),
.q (dato)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// bug598
module t (/*AUTOARG*/
// Outputs
val,
// Inputs
clk
);
input clk;
output integer val;
integer dbg_addr = 0;
function func1;
input en;
input [31:0] a;
func1 = en && (a == 1);
endfunction
function func2;
input en;
input [31:0] a;
func2 = en && (a == 2);
endfunction
always @(posedge clk) begin
case( 1'b1 )
// This line is OK:
func1(1'b1, dbg_addr) : val = 1;
// This fails:
// %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement
// %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
func2(1'b1, dbg_addr) : val = 2;
default : val = 0;
endcase
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
case (in[3:0]) inside
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
4'h4: {out1,out2} = {1'b1,5'h04};
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
endcase
end
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 8;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
begin
/* data transfer */
inj_data = {16{1'b0}};
for (j = 0; j < len; j = j + 1) begin
#(STEP)
case(inj_data)
{16'b0000000000000000} : inj_data = {16'b1111110000000000};
{16'b1111110000000000} : inj_data = {16'b1111111111110000};
{16'b1111111111110000} : inj_data = {16'b0011111111111111};
{16'b0011111111111111} : inj_data = {16'b0000000011111111};
{16'b0000000011111111} : inj_data = {16'b0000000000000011};
{16'b0000000000000011} : inj_data = {16'b1111000000000000};
{16'b1111000000000000} : inj_data = {16'b1111111111000000};
{16'b1111111111000000} : inj_data = {16'b1111111111111111};
{16'b1111111111111111} : inj_data = {16'b0000001111111111};
{16'b0000001111111111} : inj_data = {16'b0000000000001111};
{16'b0000000000001111} : inj_data = {16'b1100000000000000};
{16'b1100000000000000} : inj_data = {16'b1111111100000000};
{16'b1111111100000000} : inj_data = {16'b1111111111111100};
{16'b1111111111111100} : inj_data = {16'b0000111111111111};
{16'b0000111111111111} : inj_data = {16'b0000000000111111};
{16'b0000000000111111} : inj_data = {16'b0000000000000000};
default : inj_data = {16{1'b0}};
endcase
input1 <= inj_data[(N-1):0]; //first half
input2 <= inj_data[(N*2)-1:N]; //second half
end
end
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0)
module t (/*AUTOARG*/);
bit fail;
// IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below.
initial begin
// NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21
$display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
// NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed)
$display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
// NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321
$display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
$display("\n");
`checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21);
`checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730
`checkh( (-4'd1 ** -4'd2), 4'h1);
`checkh( (4'd15 ** 4'd14), 4'h1);
`checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
`checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27)
`checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0
`checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1
`checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b
`checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
`checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug
`checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1
// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug
`checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1
`checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
`checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
if (fail) $stop;
else $write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// model of fifo in altera
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 1024;
//`define rd_req 0; // set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output wrempty;
output [9:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [9:0] rdusedw;
reg [9:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_1k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
int q[5];
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
string v;
q = '{1, 2, 2, 4, 3};
v = $sformatf("%p", q); `checks(v, "'{1, 2, 2, 4, 3} ");
// NOT tested: with ... selectors
q.sort;
v = $sformatf("%p", q); `checks(v, "'{1, 2, 2, 3, 4} ");
q.sort with (item == 2);
v = $sformatf("%p", q); `checks(v, "'{4, 3, 1, 2, 2} ");
q.sort(x) with (x == 3);
v = $sformatf("%p", q); `checks(v, "'{2, 1, 2, 4, 3} ");
q.rsort;
v = $sformatf("%p", q); `checks(v, "'{4, 3, 2, 2, 1} ");
q.rsort with (item == 2);
v = $sformatf("%p", q); `checks(v, "'{2, 2, 4, 1, 3} ");
qv = q.unique;
v = $sformatf("%p", qv); `checks(v, "'{2, 4, 1, 3} ");
qi = q.unique_index; qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{0, 2, 3, 4} ");
q.reverse;
v = $sformatf("%p", q); `checks(v, "'{3, 1, 4, 2, 2} ");
q.shuffle(); q.sort;
v = $sformatf("%p", q); `checks(v, "'{1, 2, 2, 3, 4} ");
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = q.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{2, 2} ");
qv = q.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{2} ");
qv = q.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{2} ");
qv = q.find with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_first with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_last with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.find_index with (item == 2); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{1, 2} ");
qi = q.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{1} ");
qi = q.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{2} ");
qi = q.find_index with (item == 20); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_first_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_last_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qv = q.min;
v = $sformatf("%p", qv); `checks(v, "'{1} ");
qv = q.max;
v = $sformatf("%p", qv); `checks(v, "'{4} ");
// Reduction methods
i = q.sum; `checkh(i, 32'hc);
i = q.sum with (item + 1); `checkh(i, 32'h11);
i = q.product; `checkh(i, 32'h30);
i = q.product with (item + 1); `checkh(i, 32'h168);
q = '{32'b1100, 32'b1010, 32'b1100, 32'b1010, 32'b1010};
i = q.and; `checkh(i, 32'b1000);
i = q.and with (item + 1); `checkh(i, 32'b1001);
i = q.or; `checkh(i, 32'b1110);
i = q.or with (item + 1); `checkh(i, 32'b1111);
i = q.xor; `checkh(i, 32'ha);
i = q.xor with (item + 1); `checkh(i, 32'hb);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION:tor:ilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] o;
wire [31:0] oe;
Test test (/*AUTOINST*/
// Outputs
.o (o[31:0]),
.oe (oe[31:0]));
// Test loop
always @ (posedge clk) begin
if (o !== 32'h00000001) $stop;
if (oe !== 32'h00000001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module subimp(o,oe);
output [31:0] o;
assign o = 32'h12345679;
output [31:0] oe;
assign oe = 32'hab345679;
endmodule
module Test(o,oe);
output [31:0] o;
output [31:0] oe;
wire [31:0] xe;
assign xe[31:1] = 0;
// verilator lint_off IMPLICIT
// verilator lint_off WIDTH
subimp subimp(x, // x is implicit and one bit
xe[0]); // xe explicit one bit
assign o = x;
assign oe = xe;
// verilator lint_on WIDTH
// verilator lint_on IMPLICIT
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {48'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module callee (input [7:0] port [7:0], output [7:0] o);
assign o = ^{port[0], port[1], port[2], port[3],
port[4], port[5], port[6], port[7]};
endmodule // callee
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output reg [15:0] out;
wire [7:0] port [15:0];
wire [7:0] goodport [7:0];
always_comb begin
port[0][7:0] = in[7:0];
port[1][7:0] = in[16:8];
port[2] = '0;
port[3] = '0;
port[4] = '0;
port[5] = '0;
port[6] = '0;
port[7] = '0;
end
always_comb begin
goodport[0][7:0] = in[7:0];
goodport[1][7:0] = in[16:8];
goodport[2] = '0;
goodport[3] = '0;
goodport[4] = '0;
goodport[5] = '0;
goodport[6] = '0;
goodport[7] = '0;
end
callee good (.port(goodport), .o(out[7:0]));
// This is a slice, unsupported by other tools, bug711
callee bad (.port(port[7:0]), .o(out[15:8]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[6:0]),
// Inputs
.clk (clk),
.operand_a (operand_a[7:0]),
.operand_b (operand_b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\\n");
$finish;
end
end
endmodule
module Test
(
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a
(
// Inputs
.data_i (operand_a),
.out (clz_a));
clz u_clz_b
(
// Inputs
.data_i (operand_b),
.out (clz_b));
assign out = clz_a - clz_b;
`ifdef TEST_VERBOSE
always @(posedge clk)
$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
`endif
endmodule
`define def_0000_001x 8'b0000_0010, 8'b0000_0011
`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011
`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111
`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx
`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011
`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111
`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011
`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111
`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011
`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111
`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011
`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111
`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011
`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111
`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011
`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111
`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011
`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111
`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011
`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111
`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011
`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111
`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011
`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111
`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011
`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111
`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011
`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111
`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011
`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111
`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011
`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111
`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011
`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111
`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011
`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111
`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011
`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111
`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011
`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111
`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011
`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111
`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011
`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111
`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011
`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111
`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011
`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111
`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011
`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111
`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011
`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111
`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011
`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111
`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011
`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111
`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011
`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111
`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011
`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111
`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011
`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111
`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011
`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111
`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx
`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx
`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx
`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx
`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx
`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx
`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx
`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx
`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx
`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx
`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx
`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx
`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx
`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx
`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx
`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \\
`def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx
`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx
`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
module clz(
input wire [7:0] data_i,
output wire [6:0] out
);
// -----------------------------
// Reg declarations
// -----------------------------
reg [2:0] clz_byte0;
reg [2:0] clz_byte1;
reg [2:0] clz_byte2;
reg [2:0] clz_byte3;
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte0 = 3'b000;
`def_01xx_xxxx : clz_byte0 = 3'b001;
`def_001x_xxxx : clz_byte0 = 3'b010;
`def_0001_xxxx : clz_byte0 = 3'b011;
`def_0000_1xxx : clz_byte0 = 3'b100;
`def_0000_01xx : clz_byte0 = 3'b101;
`def_0000_001x : clz_byte0 = 3'b110;
8'b0000_0001 : clz_byte0 = 3'b111;
8'b0000_0000 : clz_byte0 = 3'b111;
default : clz_byte0 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte1 = 3'b000;
`def_01xx_xxxx : clz_byte1 = 3'b001;
`def_001x_xxxx : clz_byte1 = 3'b010;
`def_0001_xxxx : clz_byte1 = 3'b011;
`def_0000_1xxx : clz_byte1 = 3'b100;
`def_0000_01xx : clz_byte1 = 3'b101;
`def_0000_001x : clz_byte1 = 3'b110;
8'b0000_0001 : clz_byte1 = 3'b111;
8'b0000_0000 : clz_byte1 = 3'b111;
default : clz_byte1 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte2 = 3'b000;
`def_01xx_xxxx : clz_byte2 = 3'b001;
`def_001x_xxxx : clz_byte2 = 3'b010;
`def_0001_xxxx : clz_byte2 = 3'b011;
`def_0000_1xxx : clz_byte2 = 3'b100;
`def_0000_01xx : clz_byte2 = 3'b101;
`def_0000_001x : clz_byte2 = 3'b110;
8'b0000_0001 : clz_byte2 = 3'b111;
8'b0000_0000 : clz_byte2 = 3'b111;
default : clz_byte2 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte3 = 3'b000;
`def_01xx_xxxx : clz_byte3 = 3'b001;
`def_001x_xxxx : clz_byte3 = 3'b010;
`def_0001_xxxx : clz_byte3 = 3'b011;
`def_0000_1xxx : clz_byte3 = 3'b100;
`def_0000_01xx : clz_byte3 = 3'b101;
`def_0000_001x : clz_byte3 = 3'b110;
8'b0000_0001 : clz_byte3 = 3'b111;
8'b0000_0000 : clz_byte3 = 3'b111;
default : clz_byte3 = 3'bxxx;
endcase
assign out = {4'b0000, clz_byte1};
endmodule // clz
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("this->publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
task test_task(input [19:0] in [2], output [19:0] out [2]);
// Issue 3316
// verilator public
out[0] = in[1];
out[1] = in[0];
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("this->publicNoArgs();");
$c("this->publicSetBool(true);");
$c("this->publicSetLong(0x11bca);");
$c("this->publicSetQuad(0x66655554444ULL);");
$c("this->publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("this->got_bool = this->publicGetSetBool(true);");
$c("this->got_long = this->publicGetSetLong(0x11bca);");
$c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);");
end
if (cyc==13) begin
$c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("this->publicGetLong(this->got_long);");
if (24'h11bca != got_long) $stop;
$c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("this->publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] O_out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.O_out (O_out[31:0]));
initial begin
if (O_out != 32'h4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test
(
output [31:0] O_out
);
test
#(
.pFOO(5),
.pBAR(2)
) U_test
(
.O_out(O_out)
);
endmodule
module test
#(parameter pFOO = 7,
parameter pBAR = 3,
parameter pBAZ = ceiling(pFOO, pBAR)
)
(
output [31:0] O_out
);
assign O_out = pBAZ;
function integer ceiling;
input [31:0] x, y;
ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1;
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef reg [2:0] threeansi_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
localparam type three_t = reg [2:0];
three_t outna;
three_t outa;
TestNonAnsi #( .p_t (reg [2:0]) )
test (// Outputs
.out (outna),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[2:0]));
TestAnsi #( .p_t (reg [2:0]))
testa (// Outputs
.out (outa),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, outna, 1'b0, outa};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module TestNonAnsi (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
parameter type p_t = shortint;
input clk;
input p_t in;
output p_t out;
always @(posedge clk) begin
out <= ~in;
end
endmodule
module TestAnsi
#( parameter type p_t = shortint )
(
input clk,
input p_t in,
output p_t out
);
always @(posedge clk) begin
out <= ~in;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
module InstMemory2 (input [12:0] abus, output reg [15:0] dbus);
reg [15:0] im_array [0:1023];
always @(abus) dbus = im_array[abus];
initial begin
im_array [0] = 16'h0000; // LDA, dm[0] = 5 in AC, Ac = 5
im_array [1] = 16'h4001; // ADD, add AC with dm[1], AC= 5 + 1 = 6
im_array [2] = 16'h2002; // STA, store Ac in dm[2], dm[2] = 6
im_array [3] = 16'h6003; // SUB, Sub AC from dm[3], AC = 6-6 = 0;
im_array [4] = 16'hA007; // JEZ, jump to address 7 if AC = 0;
im_array [5] = 16'h0000;
im_array [6] = 16'h0000;
im_array [7] = 16'hC00B; // LDI, load 16'h000B in AC
im_array [8] = 16'h2004; // STA, store Ac in dm[4], dm[4] = 16'h000B
im_array [9] = 16'hE000; // Halt, hlat the system until start
im_array [10] = 16'h8000; // JMP 0, jump to address 0 an all the above operations are executed again.
end
endmodule
//
module DataMemory2 (input rd, wr, input [12:0] abus, input [15:0] in_dbus, output reg [15:0] out_dbus);
reg [15:0] dm_array [0:1023];
always @(rd or abus)
if (rd) out_dbus = dm_array [abus];
always @ (wr or abus or in_dbus)
if (wr) dm_array[abus] = in_dbus;
initial begin
dm_array[0] = 16'h0005;
dm_array[1] = 16'h0001;
dm_array[2] = 16'h0000;
dm_array[3] = 16'h0006;
dm_array[4] = 16'h0000;
dm_array[5] = 16'h0000;
dm_array[6] = 16'h0000;
dm_array[7] = 16'h0000;
dm_array[8] = 16'h0000;
dm_array[9] = 16'h0000;
dm_array[10] = 16'h0000;
dm_array[11] = 16'h0000;
dm_array[12] = 16'h0000;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc = 0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc + 8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");");
c_worked <= $c("this->my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
uint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
fastclk
);
input fastclk;
t_netlist tnetlist
(.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
.fastclk (fastclk));
endmodule
module t_netlist (/*AUTOARG*/
// Inputs
fastclk, also_fastclk
);
// surefire lint_off ASWEMB
input fastclk;
input also_fastclk;
integer _mode; initial _mode = 0;
// This entire module should optimize to nearly nothing...
// verilator lint_off UNOPTFLAT
reg [4:0] a,a2,b,c,d,e;
// verilator lint_on UNOPTFLAT
initial a=5'd1;
always @ (posedge fastclk) begin
b <= a+5'd1;
c <= b+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_off UNOPT
always @ (d or /*AS*/a or c) begin
e = d+5'd1;
a2 = a+5'd1; // This can be pulled out of the middle of the always
d = c+5'd1; // Better for ordering if this moves before previous statement
end
// verilator lint_on UNOPT
always @ (posedge also_fastclk) begin
if (_mode==5) begin
if (a2 != 5'd2) $stop;
if (e != 5'd5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg check; initial check = 1'b0;
// verilator lint_off WIDTH
//============================================================
reg [ 1:0] W0095; //=3
reg [ 58:0] W0101; //=0000000FFFFFFFF
always @(posedge clk) begin
if (cyc==1) begin
W0095 = ((2'h3));
W0101 = ({27'h0,({16{(W0095)}})});
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop;
end
end
//============================================================
reg [ 0:0] W1243; //=1
always @(posedge clk) begin
if (cyc==1) begin
W1243 = ((1'h1));
end
end
always @(posedge clk) begin
if (cyc==2) begin
// Width violation, but still...
if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop;
if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop;
end
end
//============================================================
reg [ 0:0] W0344; //=0
always @(posedge clk) begin
if (cyc==1) begin
W0344 = 1'b0;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0344) != (1'h0)) if (check) $stop;
if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop;
end
end
//============================================================
reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF
reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF
reg [115:0] W0421; //=00000000000000000000000000000
always @(posedge clk) begin
if (cyc==1) begin
W0372 = ({64{((1'h1))}});
W0421 = 116'h0;
W0420 = ({119{((W0372) <= (W0372))}});
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop;
end
end
//============================================================
// gcc_2_96_bug
reg [ 31:0] W0161; //=FFFFFFFF
reg [ 62:0] W0217; //=0000000000000000
reg [ 53:0] W0219; //=00000000000000
always @(posedge clk) begin
if (cyc==1) begin
W0161 = 32'hFFFFFFFF;
W0217 = 63'h0;
W0219 = 54'h0;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0161) != (32'hFFFFFFFF)) if (check) $stop;
if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop;
end
end
//============================================================
reg [119:0] W0592; //=000000000000000000000000000000
reg [ 7:0] W0593; //=70
always @(posedge clk) begin
if (cyc==1) begin
W0593 = (((8'h90)) * ((8'hFF)));
W0592 = 120'h000000000000000000000000000000;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop;
end
end
//============================================================
reg [127:0] WA1063 ; //=00000000000000000000000000000001
reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF
reg [ 62:0] WA1065 ; //=0000000000000000
reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001
reg [ 34:0] WA1067 ; //=7FFFFFFFF
reg [111:0] WA1068;
always @(check) begin
WA1067 = (~ (35'h0));
WA1066 = (90'h00000000000000000000001);
WA1065 = (WA1066[89:27]);
WA1064 = (WA1067);
WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001))));
end
always @(posedge clk) begin
if (cyc==2) begin
if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop;
end
end
//============================================================
reg [127:0] WB1063 ; //=00000000000000000000000000000001
reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF
reg [ 62:0] WB1065 ; //=0000000000000000
reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001
reg [ 34:0] WB1067 ; //=7FFFFFFFF
reg [111:0] WB1068;
always @(posedge clk) begin
if (cyc==1) begin
WB1067 = (~ (35'h0));
WB1066 = (90'h00000000000000000000001);
end
if (cyc==2) WB1065 <= (WB1066[89:27]);
if (cyc==3) WB1064 <= (WB1067);
if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001))));
if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]);
end
always @(posedge clk) begin
if (cyc==9) begin
if (WB1068 != 112'h0) if (check) $stop;
if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop;
end
end
//============================================================
reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF
reg signed [ 6:0] WC0065 ; //=00
reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF
always @(check) begin
WC0064 = 61'sh1FFFFFFFFFFFFFFF;
WC0065 = 7'sh0;
if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop;
end
//============================================================
reg signed [ 76:0] W0234 ; //=00000000000000000000
reg signed [ 7:0] W0235 /*verilator public*/; //=B6
always @(check) begin
W0235 = 8'shb6;
W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235));
if ((W0234) != 77'sh0) if (check) $stop;
end
//============================================================
reg signed [ 30:0] W0146 ; //=00000001
always @(check) begin : Block71
W0146 = (31'sh00000001);
if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop;
end
//============================================================
reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF
always @(check) begin : Block405
W0857 = 55'sh7fffffffffffff;
if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop;
if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop;
end
//============================================================
reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA
always @* begin : Block144
W0226 = 83'sh47A4301EE3FB4133EE3DA;
if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop;
end
//============================================================
reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C
reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A
always @(posedge clk) begin
W0793 <= 69'sh1f_ffffffff_4eb1a91a;
W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E);
if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop;
end
//============================================================
reg signed [ 2:0] DW0515 /*verilator public*/; //=7
always @(posedge clk) begin
DW0515 <= 3'sh7;
if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop;
end
//============================================================
reg signed [ 62:0] W0753 ; //=004E20004ED93E26
reg [ 2:0] W0772 /*verilator public*/; //=7
always @(posedge clk) begin
W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff)));
W0772 <= 3'h7;
if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop;
if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop;
end
//============================================================
reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF
always @(posedge clk) begin
W1027 <= ~99'h0;
// verilator lint_off CMPCONST
if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop;
// verilator lint_on CMPCONST
end
//============================================================
reg signed [ 5:0] W123_is_3f ; //=3F
always @(posedge clk) begin
W123_is_3f <= 6'sh3f;
end
always @(posedge clk) begin
if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop;
end
//============================================================
reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1
always @(check) begin : Block237
W0032 = 106'sh3ff0000000100000000bd597bb1;
if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop;
if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop;
end
//============================================================
reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094
reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c
always @(posedge clk) begin
W0024 <= 84'h0000000000000e1fe9094;
W0025 <= 84'h0f66afffffffe308b3d7c;
if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop;
end
//============================================================
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==18) begin
check <= 1'b1;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
typedef integer q_t[$];
initial begin
q_t iq;
iq.push_back(42);
end
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Very simple test using bit
bit q[$];
bit x;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 1);
// $bits is unsupported in several other simulators, see bug1646
// Unsup: `checkh($bits(q), 0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 0);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), 0);
`checkh($size(q), 1);
`checkh($dimensions(q), 1);
// Unsup: `checkh($bits(q), 2);
`checkh(q.size(), 1);
q.push_back(1'b1);
q.push_back(1'b0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 3);
`checkh($low(q), 0);
`checkh($high(q), 3);
`checkh($size(q), 4);
// Unsup: `checkh($bits(q), 4);
`checkh(q.size(), 4);
x = q.pop_back(); `checkh(x, 1'b1);
`checkh($left(q), 0);
`checkh($right(q), 2);
`checkh($low(q), 0);
`checkh($high(q), 2);
`checkh($size(q), 3);
// sure those are working now..
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b0);
`checkh(q.size(), 0);
end
begin
// Simple test using integer
typedef bit [3:0] nibble_t;
nibble_t q[$];
nibble_t v;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
i = q.size(); `checkh(i, 0);
q.push_back(4'd1); // 1
q.push_front(4'd2); // 2 1
q.push_back(4'd3); // 2 1 3
i = q.size; `checkh(i, 3); // Also checks no parens
end
begin
// Strings
string q[$];
string v;
int j = 0;
// Empty queue checks
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
q.push_front("f1");
//Unsup: `checkh($bits(q), 16);
q.push_back("b1");
q.push_front("f2");
q.push_back("b2");
i = q.size(); `checkh(i, 4);
v = q[0]; `checks(v, "f2");
v = q[1]; `checks(v, "f1");
v = q[2]; `checks(v, "b1");
v = q[3]; `checks(v, "b2");
v = q[4]; `checks(v, "");
//Unsup: `checkh(q[$], "b2");
v = $sformatf("%p", q); `checks(v, "'{\"f2\", \"f1\", \"b1\", \"b2\"} ");
//Unsup: q.delete(1);
//Unsup: v = q[1]; `checks(v, "b1");
//Unsup: q.insert(0, "ins0");
//Unsup: q.insert(3, "ins3");
//v = q[0]; `checks(v, "ins0");
//v = q[3]; `checks(v, "ins3");
foreach (q[i]) begin
j++;
v = q[i];
if (i == 0) `checks(v, "f2");
if (i == 1) `checks(v, "f1");
if (i == 2) `checks(v, "b1");
if (i == 3) `checks(v, "b2");
end
`checkh(j,4);
q.pop_front();
v = q.pop_front(); `checks(v, "f1");
v = q.pop_back(); `checks(v, "b2");
v = q.pop_back(); `checks(v, "b1");
i = q.size(); `checkh(i, 0);
// Empty queue, this should be 0
foreach (q[i]) begin
j++;
end
`checkh(j,4);
q.push_front("non-empty");
i = q.size(); `checkh(i, 1);
q.delete();
i = q.size(); `checkh(i, 0);
v = q.pop_front(); `checks(v, ""); // Was empty, optional warning
v = q.pop_back(); `checks(v, ""); // Was empty, optional warning
// Conversion of insert/delete with zero to operator
q.push_front("front");
q.insert(0, "newfront");
i = q.size(); `checkh(i, 2);
q.delete(0);
i = q.size(); `checkh(i, 1);
`checks(q[0], "front");
//Unsup: `checks(q[$], "front");
end
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction q[$];
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
end
// testing a wide queue
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
bit [127:0] data;
} instructionW; // named structure type
instructionW inst_push;
instructionW inst_pop;
instructionW q[$];
`checkh($dimensions(q), 2);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
inst_push.opcode = 1;
inst_push.addr = 42;
inst_push.data = {4{32'hdeadbeef}};
q.push_back(inst_push);
`checkh(q[0].opcode, 1);
`checkh(q[0].addr, 42);
`checkh(q[0].data, {4{32'hdeadbeef}});
inst_pop = q.pop_front();
`checkh(inst_pop.opcode, 1);
`checkh(inst_pop.addr, 42);
`checkh(inst_pop.data, {4{32'hdeadbeef}});
`checkh(q.size(), 0);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
end
/* Unsup:
begin
int q[4][$];
q[0].push_back(0);
q[0].push_back(1);
q[1].push_back(2);
q[2].push_back(3);
end
*/
// See t_queue_unsup_bad for more unsupported stuff
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
reg GSR;
task setGSR;
`ifdef ATTRIBUTES
/* verilator public */
`endif
input value;
GSR = value;
endtask
`else
`ifdef ATTRIBUTES
reg GSR /*verilator public*/;
`else
reg GSR;
`endif
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [43:0] mi;
reg [5:0] index;
integer indexi;
reg read;
initial begin
// Static
mi = 44'b01010101010101010101010101010101010101010101;
if (mi[0] !== 1'b1) $stop;
if (mi[1 -: 2] !== 2'b01) $stop;
`ifdef VERILATOR
// verilator lint_off SELRANGE
if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
// verilator lint_on SELRANGE
`else
if (mi[-1] !== 1'bx) $stop;
if (mi[0 -: 2] !== 2'b1x) $stop;
if (mi[-1 -: 2] !== 2'bxx) $stop;
`endif
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
mi = 44'h123;
end
if (cyc==2) begin
index = 6'd43;
indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
read = mi[indexi];
if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
indexi = -1;
end
if (cyc==7) begin
read = mi[indexi];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module main();///// changes////////
reg CLK;
reg CLK1p;
reg CLK1n;
reg CLKrx;
////// changes end ///////////
// reg CLK_GATE;
///////// changes////////
reg RST;
reg RST1;
////// changes end ///////////
reg [31:0] cycle;
reg do_vcd;
reg do_fsdb;
reg do_fst;
reg do_cycles;
// changes
// `TOP top(.CLK(CLK), /* .CLK_GATE(CLK_GATE), */ .`BSV_RESET_NAME(RST));
`TOP top(.sys0_clk(CLK), /* .CLK_GATE(CLK_GATE), */ .`BSV_RESET_NAME(RST), .CLK_sys1_clkp(CLK1p), .CLK_sys1_clkn(CLK1n), .CLK_gmii_rx_clk(CLKrx)/*, .RST_N_gmii_rstn(RST1)*/);
// end changes
// For Sce-Mi linkage, insert code here
`ifdef BSV_SCEMI_LINK
`include `BSV_SCEMI_LINK
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
string q[$];
string v;
int i;
int qi[$:5];
int ri[$];
q.push_front("non-empty");
i = q.size(); `checkh(i, 1);
v = $sformatf("%p", q); `checks(v, "'{\"non-empty\"} ");
q = '{};
i = q.size(); `checkh(i, 0);
q = '{"q"};
v = $sformatf("%p", q); `checks(v, "'{\"q\"} ");
q = {};
i = q.size(); `checkh(i, 0);
q = '{"q", "b", "c", "d", "e", "f"};
if (q[0] !== "q") $stop;
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} ");
q = {"q", "b", "c", "d", "e", "f"};
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} ");
q.delete(1);
v = q[1]; `checks(v, "c");
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"c\", \"d\", \"e\", \"f\"} ");
q.insert(0, "ins0");
q.insert(2, "ins2");
v = q[0]; `checks(v, "ins0");
v = q[2]; `checks(v, "ins2");
v = $sformatf("%p", q); `checks(v, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"} ");
// Slicing
q = '{"q", "b", "c", "d", "e", "f"};
q = q[-1:0];
v = $sformatf("%p", q); `checks(v, "'{\"q\"} ");
q = '{"q", "b", "c", "d", "e", "f"};
q = q[2:3];
v = $sformatf("%p", q); `checks(v, "'{\"c\", \"d\"} ");
q = '{"q", "b", "c", "d", "e", "f"};
q = q[3:$];
v = $sformatf("%p", q); `checks(v, "'{\"d\", \"e\", \"f\"} ");
q = q[$:$];
v = $sformatf("%p", q); `checks(v, "'{\"f\"} ");
// Similar using implied notation
q = '{"f"};
q = {q, "f1"}; // push_front
q = {q, "f2"}; // push_front
q = {"b1", q}; // push_back
q = {"b2", q}; // push_back
v = $sformatf("%p", q); `checks(v, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"} ");
q = {q[0], q[2:$]}; // delete element 1
v = $sformatf("%p", q); `checks(v, "'{\"b2\", \"f\", \"f1\", \"f2\"} ");
q = {"a", "b"};
q = {q, q};
v = $sformatf("%p", q); `checks(v, "'{\"a\", \"b\", \"a\", \"b\"} ");
begin
string ai[$] = '{ "Foo", "Bar" };
q = ai; // Copy
i = q.size(); `checkh(i, 2);
v = q.pop_front(); `checks(v, "Foo");
v = q.pop_front(); `checks(v, "Bar");
q = '{ "BB", "CC" }; // Note '{} not {}
v = q.pop_front(); `checks(v, "BB");
v = q.pop_front(); `checks(v, "CC");
q = { "BB", "CC" }; // Note {} not '{}
v = q.pop_front(); `checks(v, "BB");
v = q.pop_front(); `checks(v, "CC");
end
begin
qi.push_back(0);
qi.push_back(1);
qi.push_back(2);
qi.push_back(3);
qi.push_back(4);
qi.push_back(5);
// Assignment to unsized queue from sized queue
ri = qi[ 2 : 4 ];
`checkh(ri.size, 3);
ri = qi[ 4 : 2 ];
`checkh(ri.size, 0);
ri = qi[ 2 : 2 ];
`checkh(ri.size, 1);
ri = qi[ -2 : 2 ]; // 2 - 0 + 1 = 3
`checkh(ri.size, 3);
ri = qi[ 2 : 10 ]; // 5 - 2 + 1 = 4
`checkh(ri.size, 4);
// Assignment from unsized to sized
ri = '{1,2,3,4,5,6,7,8,9};
qi = ri;
`checkh(qi.size, 5);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assume (0) else $info("Info message from failing assumption");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2017 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/);
// Note that a packed array is required, otherwise some simulators will return bad
// results using *ElemVecVal() routines instead of scalar *Elem() routines.
bit [0:0] i_bit_p1_u1 [2:-2];
bit [0:0] o_bit_p1_u1 [2:-2];
bit [0:0] q_bit_p1_u1 [2:-2];
bit [60:0] i_bit61_p1_u1 [2:-2];
bit [60:0] o_bit61_p1_u1 [2:-2];
bit [60:0] q_bit61_p1_u1 [2:-2];
bit [91:0] i_bit92_p1_u1 [2:-2];
bit [91:0] o_bit92_p1_u1 [2:-2];
bit [91:0] q_bit92_p1_u1 [2:-2];
bit [11:0] i_bit12_p1_u2 [2:-2] [-3:3];
bit [11:0] o_bit12_p1_u2 [2:-2] [-3:3];
bit [11:0] q_bit12_p1_u2 [2:-2] [-3:3];
bit [29:1] i_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
bit [29:1] o_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
bit [29:1] q_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
import "DPI-C" function void dpii_bit_vecval_p1_u1
(int bits, int p, int u, input bit [0:0] i [], output bit [0:0] o [], output bit [0:0] q []);
import "DPI-C" function void dpii_bit61_vecval_p1_u1
(int bits, int p, int u, input bit [60:0] i [], output bit [60:0] o [], output bit [60:0] q []);
import "DPI-C" function void dpii_bit92_vecval_p1_u1
(int bits, int p, int u, input bit [91:0] i [], output bit [91:0] o [], output bit [91:0] q []);
import "DPI-C" function void dpii_bit12_vecval_p1_u2
(int bits, int p, int u, input bit [11:0] i [] [], output bit [11:0] o [] [], output bit [11:0] q [] []);
import "DPI-C" function void dpii_bit29_vecval_p1_u3
(int bits, int p, int u, input bit [29:1] i [] [] [], output bit [29:1] o [] [] [], output bit [29:1] q [] [] []);
logic [0:0] i_logic_p1_u1 [2:-2];
logic [0:0] o_logic_p1_u1 [2:-2];
logic [0:0] q_logic_p1_u1 [2:-2];
logic [60:0] i_logic61_p1_u1 [2:-2];
logic [60:0] o_logic61_p1_u1 [2:-2];
logic [60:0] q_logic61_p1_u1 [2:-2];
logic [91:0] i_logic92_p1_u1 [2:-2];
logic [91:0] o_logic92_p1_u1 [2:-2];
logic [91:0] q_logic92_p1_u1 [2:-2];
logic [11:0] i_logic12_p1_u2 [2:-2] [-3:3];
logic [11:0] o_logic12_p1_u2 [2:-2] [-3:3];
logic [11:0] q_logic12_p1_u2 [2:-2] [-3:3];
logic [29:1] i_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
logic [29:1] o_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
logic [29:1] q_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
import "DPI-C" function void dpii_logic_vecval_p1_u1
(int logics, int p, int u, input logic [0:0] i [], output logic [0:0] o [], output logic [0:0] q []);
import "DPI-C" function void dpii_logic61_vecval_p1_u1
(int logics, int p, int u, input logic [60:0] i [], output logic [60:0] o [], output logic [60:0] q []);
import "DPI-C" function void dpii_logic92_vecval_p1_u1
(int logics, int p, int u, input logic [91:0] i [], output logic [91:0] o [], output logic [91:0] q []);
import "DPI-C" function void dpii_logic12_vecval_p1_u2
(int logics, int p, int u, input logic [11:0] i [] [], output logic [11:0] o [] [], output logic [11:0] q [] []);
import "DPI-C" function void dpii_logic29_vecval_p1_u3
(int logics, int p, int u, input logic [29:1] i [] [] [], output logic [29:1] o [] [] [], output logic [29:1] q [] [] []);
import "DPI-C" function int dpii_failure();
reg [95:0] crc;
initial begin
crc = 96'h8a10a572_5aef0c8d_d70a4497;
begin
for (int a=-2; a<=2; a=a+1) begin
i_bit_p1_u1[a] = crc[0];
i_bit61_p1_u1[a] = crc[60:0];
i_bit92_p1_u1[a] = crc[91:0];
for (int b=-3; b<=3; b=b+1) begin
i_bit12_p1_u2[a][b] = crc[11:0];
for (int c=-4; c<=4; c=c+1) begin
i_bit29_p1_u3[a][b][c] = crc[29:1];
crc = {crc[94:0], crc[95]^crc[2]^crc[0]};
end
end
end
dpii_bit_vecval_p1_u1(1, 1, 1, i_bit_p1_u1, o_bit_p1_u1, q_bit_p1_u1);
dpii_bit61_vecval_p1_u1(61, 1, 1, i_bit61_p1_u1, o_bit61_p1_u1, q_bit61_p1_u1);
dpii_bit92_vecval_p1_u1(92, 1, 1, i_bit92_p1_u1, o_bit92_p1_u1, q_bit92_p1_u1);
dpii_bit12_vecval_p1_u2(12, 1, 2, i_bit12_p1_u2, o_bit12_p1_u2, q_bit12_p1_u2);
dpii_bit29_vecval_p1_u3(29, 1, 3, i_bit29_p1_u3, o_bit29_p1_u3, q_bit29_p1_u3);
for (int a=-2; a<=2; a=a+1) begin
`checkh(o_bit_p1_u1[a], ~i_bit_p1_u1[a]);
`checkh(q_bit_p1_u1[a], ~i_bit_p1_u1[a]);
`checkh(o_bit61_p1_u1[a], ~i_bit61_p1_u1[a]);
`checkh(q_bit61_p1_u1[a], ~i_bit61_p1_u1[a]);
`checkh(o_bit92_p1_u1[a], ~i_bit92_p1_u1[a]);
`checkh(q_bit92_p1_u1[a], ~i_bit92_p1_u1[a]);
for (int b=-3; b<=3; b=b+1) begin
`checkh(o_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]);
`checkh(q_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]);
for (int c=-4; c<=4; c=c+1) begin
`checkh(o_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]);
`checkh(q_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]);
end
end
end
end
begin
for (int a=-2; a<=2; a=a+1) begin
i_logic_p1_u1[a] = crc[0];
i_logic61_p1_u1[a] = crc[60:0];
i_logic92_p1_u1[a] = crc[91:0];
for (int b=-3; b<=3; b=b+1) begin
i_logic12_p1_u2[a][b] = crc[11:0];
for (int c=-4; c<=4; c=c+1) begin
i_logic29_p1_u3[a][b][c] = crc[29:1];
crc = {crc[94:0], crc[95]^crc[2]^crc[0]};
end
end
end
dpii_logic_vecval_p1_u1(1, 1, 1, i_logic_p1_u1, o_logic_p1_u1, q_logic_p1_u1);
dpii_logic61_vecval_p1_u1(61, 1, 1, i_logic61_p1_u1, o_logic61_p1_u1, q_logic61_p1_u1);
dpii_logic92_vecval_p1_u1(92, 1, 1, i_logic92_p1_u1, o_logic92_p1_u1, q_logic92_p1_u1);
dpii_logic12_vecval_p1_u2(12, 1, 2, i_logic12_p1_u2, o_logic12_p1_u2, q_logic12_p1_u2);
dpii_logic29_vecval_p1_u3(29, 1, 3, i_logic29_p1_u3, o_logic29_p1_u3, q_logic29_p1_u3);
for (int a=-2; a<=2; a=a+1) begin
`checkh(o_logic_p1_u1[a], ~i_logic_p1_u1[a]);
`checkh(q_logic_p1_u1[a], ~i_logic_p1_u1[a]);
`checkh(o_logic61_p1_u1[a], ~i_logic61_p1_u1[a]);
`checkh(q_logic61_p1_u1[a], ~i_logic61_p1_u1[a]);
`checkh(o_logic92_p1_u1[a], ~i_logic92_p1_u1[a]);
`checkh(q_logic92_p1_u1[a], ~i_logic92_p1_u1[a]);
for (int b=-3; b<=3; b=b+1) begin
`checkh(o_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]);
`checkh(q_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]);
for (int c=-4; c<=4; c=c+1) begin
`checkh(o_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]);
`checkh(q_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]);
end
end
end
end
if (dpii_failure()!=0) begin
$write("%%Error: Failure in DPI tests\n");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assume (0) else $info("Info message from failing assumption");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/);
parameter int sliceddn[7:0] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
parameter int slicedup[0:7] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
int alldn[7:0];
int allup[0:7];
int twodn[1:0];
int twoup[0:1];
initial begin
`checkh(sliceddn[7], 'h100);
alldn[7:0] = sliceddn[7:0];
`checkh(alldn[7], 'h100);
alldn[7:0] = sliceddn[0 +: 8]; // down: lsb/lo +: width
`checkh(alldn[7], 'h100);
alldn[7:0] = sliceddn[7 -: 8]; // down: msb/hi -: width
`checkh(alldn[7], 'h100);
twodn[1:0] = sliceddn[6:5];
`checkh(twodn[1], 'h101);
`checkh(twodn[0], 'h102);
twodn[1:0] = sliceddn[4 +: 2];
`checkh(twodn[1], 'h102);
`checkh(twodn[0], 'h103);
twodn[1:0] = sliceddn[4 -: 2];
`checkh(twodn[1], 'h103);
`checkh(twodn[0], 'h104);
`checkh(slicedup[7], 'h107);
allup[0:7] = slicedup[0:7];
`checkh(alldn[7], 'h100);
allup[0:7] = slicedup[0 +: 8]; // up: msb/lo +: width
`checkh(alldn[7], 'h100);
allup[0:7] = slicedup[7 -: 8]; // up: lsb/hi -: width
`checkh(alldn[7], 'h100);
twoup[0:1] = slicedup[5:6];
`checkh(twoup[1], 'h106);
`checkh(twoup[0], 'h105);
twoup[0:1] = slicedup[4 +: 2];
`checkh(twoup[1], 'h105);
`checkh(twoup[0], 'h104);
twoup[0:1] = slicedup[4 -: 2];
`checkh(twoup[1], 'h104);
`checkh(twoup[0], 'h103);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module main();///// changes////////
reg CLK;
reg CLK1p;
reg CLK1n;
reg CLKrx;
////// changes end ///////////
// reg CLK_GATE;
///////// changes////////
reg RST;
reg RST1;
////// changes end ///////////
reg [31:0] cycle;
reg do_vcd;
reg do_fsdb;
reg do_fst;
reg do_cycles;
// changes
// `TOP top(.CLK(CLK), /* .CLK_GATE(CLK_GATE), */ .`BSV_RESET_NAME(RST));
`TOP top(.sys0_clk(CLK), /* .CLK_GATE(CLK_GATE), */ .`BSV_RESET_NAME(RST), .CLK_sys1_clkp(CLK1p), .CLK_sys1_clkn(CLK1n), .CLK_gmii_rx_clk(CLKrx)/*, .RST_N_gmii_rstn(RST1)*/);
// end changes
// For Sce-Mi linkage, insert code here
`ifdef BSV_SCEMI_LINK
`include `BSV_SCEMI_LINK
`endif
`ifdef BSV_DUMP_LEVEL
`else
`define BSV_DUMP_LEVEL 0
`endif
`ifdef BSV_DUMP_TOP
`else
`define BSV_DUMP_TOP main
`endif
initial begin
// CLK_GATE = 1'b1;
// CLK = 1'b0; // This line will cause a neg edge of clk at t=0!
// RST = !`BSV_RESET_VALUE'b0; // This needs #0, to allow always blocks to wait
cycle = 0;
do_vcd = $test$plusargs("bscvcd") ;
do_fst = $test$plusargs("bscfst") ;
do_fsdb = $test$plusargs("bscfsdb") ;
do_cycles = $test$plusargs("bsccycle") ;
`ifdef BSC_FSDB
if (do_fsdb) begin
$fsdbDumpfile("dump.fsdb");
$fsdbDumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`else
// if (do_fst && ! do_vcd) begin
// $dumpfile("|vcd2fst -F -f dump.fst -");
// $dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
// end
if (do_vcd) begin
$dumpfile("dump.vcd");
$dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`endif
#0
|
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: one_wire_io.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// Rev: Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module one_wire_io (
CLK, DDIR, DOUT, DQ_CONTROL, MR, DIN, DQ_IN, DATA_IN, DATA_OUT,
DQ0_T, DQ1_T, DQ2_T, DQ3_T, DQ4_T, DQ5_T, DQ6_T, DQ7_T,
DQ0_O, DQ1_O, DQ2_O, DQ3_O, DQ4_O, DQ5_O, DQ6_O, DQ7_O,
DQ0_I, DQ1_I, DQ2_I, DQ3_I, DQ4_I, DQ5_I, DQ6_I, DQ7_I, DQ_SEL);
input CLK;
input DDIR;
input [7:0] DOUT;
input DQ_CONTROL;
input MR;
output [7:0] DIN;
output DQ_IN;
input [7:0] DATA_IN;
output [7:0] DATA_OUT;
output DQ0_T;
output DQ1_T;
output DQ2_T;
output DQ3_T;
output DQ4_T;
output DQ5_T;
output DQ6_T;
output DQ7_T;
output DQ0_O;
output DQ1_O;
output DQ2_O;
output DQ3_O;
output DQ4_O;
output DQ5_O;
output DQ6_O;
output DQ7_O;
input DQ0_I;
input DQ1_I;
input DQ2_I;
input DQ3_I;
input DQ4_I;
input DQ5_I;
input DQ6_I;
input DQ7_I;
input [2:0] DQ_SEL;
reg DQ_IN;
assign DATA_OUT = DOUT;
assign DIN = DATA_IN;
//assign DQ =DQ_CONTROL==1?1'bz:1'b0;
wire DQ_INTERNAL;
// IOBUF xIOBUF(
// .T (DQ_CONTROL ),
// .I (1'b0 ),
// .O (DQ_INTERNAL),
// .IO (DQ )
// );
// assign DQ_T = DQ_CONTROL;
// assign DQ_O = 1'b0;
// assign DQ_INTERNAL = DQ_I;
assign DQ0_T = (DQ_SEL [2:0] == 0) ? DQ_CONTROL : 1'b1;
assign DQ1_T = (DQ_SEL [2:0] == 1) ? DQ_CONTROL : 1'b1;
assign DQ2_T = (DQ_SEL [2:0] == 2) ? DQ_CONTROL : 1'b1;
assign DQ3_T = (DQ_SEL [2:0] == 3) ? DQ_CONTROL : 1'b1;
assign DQ4_T = (DQ_SEL [2:0] == 4) ? DQ_CONTROL : 1'b1;
assign DQ5_T = (DQ_SEL [2:0] == 5) ? DQ_CONTROL : 1'b1;
assign DQ6_T = (DQ_SEL [2:0] == 6) ? DQ_CONTROL : 1'b1;
assign DQ7_T = (DQ_SEL [2:0] == 7) ? DQ_CONTROL : 1'b1;
assign DQ0_O = 1'b0;
assign DQ1_O = 1'b0;
assign DQ2_O = 1'b0;
assign DQ3_O = 1'b0;
assign DQ4_O = 1'b0;
assign DQ5_O = 1'b0;
assign DQ6_O = 1'b0;
assign DQ7_O = 1'b0;
assign DQ_INTERNAL = (DQ_SEL [2:0] == 0) & DQ0_I
| (DQ_SEL [2:0] == 1) & DQ1_I
| (DQ_SEL [2:0] == 2) & DQ2_I
| (DQ_SEL [2:0] == 3) & DQ3_I
| (DQ_SEL [2:0] == 4) & DQ4_I
| (DQ_SEL [2:0] == 5) & DQ5_I
| (DQ_SEL [2:0] == 6) & DQ6_I
| (DQ_SEL [2:0] == 7) & DQ7_I;
//
// Synchronize DQ_IN
//
always @(posedge MR or negedge CLK)
if (MR)
DQ_IN <= 1'b1;
else
DQ_IN <= DQ_INTERNAL;
endmodule // one_wire_io
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
wire GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
wire GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0)
module t (/*AUTOARG*/);
bit fail;
// IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below.
initial begin
// NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21
$display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110);
// NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed)
$display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2)));
// NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1
$display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14)));
// NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321
$display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321);
$display("\n");
`checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21);
`checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730
`checkh( (-4'd1 ** -4'd2), 4'h1);
`checkh( (4'd15 ** 4'd14), 4'h1);
`checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321);
`checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27)
`checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0
`checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1
`checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b
`checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
`checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216)
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1
`checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug
`checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1
// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug
`checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1
`checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
`checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug
if (fail) $stop;
else $write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
wire o0, o1;
sub #(1) a(.i(1'b0), .o(o0));
sub #(2) b(.i(1'b0), .o(o1));
always @(posedge clk) begin
if (o0 != 1'b0) begin
$write("Bad o0\n");
$stop;
end
if (o1 != 1'b1) begin
$write("Bad o1\n");
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub
#(
parameter int W
)
(
input wire i,
output wire o
);
typedef struct packed {
logic [W-1:0] a;
} s;
sub2 #(s) c(.i(i), .o(o));
endmodule
module sub2
# (
parameter type T = logic
)
(
input wire i,
output wire o
);
if ($bits(T) % 2 == 1) begin
assign o = i;
end else begin
assign o = ~i;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// simplistic example, should choose 1st conditional generate and assign straight through
// the tool also compiles the special case and determines an error (replication value is 0)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
`timescale 1ns / 1ps
module t(data_i, data_o, single);
parameter op_bits = 32;
input [op_bits -1:0] data_i;
output [31:0] data_o;
input single;
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate
if (op_bits == 32) begin : general_case
assign data_o = data_i;
// Test implicit signals
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
else begin : special_case
assign data_o = {{(32 -op_bits){1'b0}},data_i};
/* verilator lint_off IMPLICIT */
assign imp = single;
/* verilator lint_on IMPLICIT */
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [15:0]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module RotatingSingleVCAllocator_9( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_5_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [1:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [1:0] _in_arb_filter_T_3 = {in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{57,84,86}, :32:39]
wire [3:0] in_arb_filter = _in_arb_filter_T_3[0] ? 4'h1 : _in_arb_filter_T_3[1] ? 4'h2 : in_arb_vals_0 ? 4'h4 : {in_arb_vals_1, 3'h0}; // @[OneHot.scala:85:71]
wire [1:0] in_arb_sel = in_arb_filter[1:0] | in_arb_filter[3:2]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1; // @[package.scala:81:59]
wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0); // @[package.scala:81:59]
wire _in_vc_sel_T_4 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_7 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_16 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_19 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_25 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36]
reg [7:0] mask_1; // @[ISLIP.scala:17:25]
wire [7:0] _full_T_1 = {_in_vc_sel_T_25, _in_vc_sel_T_22, _in_vc_sel_T_19, _in_vc_sel_T_16, _in_vc_sel_T_13, _in_vc_sel_T_10, _in_vc_sel_T_7, _in_vc_sel_T_4} & ~mask_1; // @[Mux.scala:30:73]
wire [15:0] oh = _full_T_1[0] ? 16'h1 : _full_T_1[1] ? 16'h2 : _full_T_1[2] ? 16'h4 : _full_T_1[3] ? 16'h8 : _full_T_1[4] ? 16'h10 : _full_T_1[5] ? 16'h20 : _full_T_1[6] ? 16'h40 : _full_T_1[7] ? 16'h80 : _in_vc_sel_T_4 ? 16'h100 : _in_vc_sel_T_7 ? 16'h200 : _in_vc_sel_T_10 ? 16'h400 : _in_vc_sel_T_13 ? 16'h800 : _in_vc_sel_T_16 ? 16'h1000 : _in_vc_sel_T_19 ? 16'h2000 : _in_vc_sel_T_22 ? 16'h4000 : {_in_vc_sel_T_25, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] sel = oh[7:0] | oh[15:8]; // @[Mux.scala:50:70]
wire in_alloc_2_0 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59]
|
module t (clk);
input clk;
reg [43:0] mi;
reg [5:0] index;
integer indexi;
reg read;
initial begin
// Static
mi = 44'b01010101010101010101010101010101010101010101;
if (mi[0] !== 1'b1) $stop;
if (mi[1 -: 2] !== 2'b01) $stop;
`ifdef VERILATOR
// verilator lint_off SELRANGE
if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
// verilator lint_on SELRANGE
`else
if (mi[-1] !== 1'bx) $stop;
if (mi[0 -: 2] !== 2'b1x) $stop;
if (mi[-1 -: 2] !== 2'bxx) $stop;
`endif
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
mi = 44'h123;
end
if (cyc==2) begin
index = 6'd43;
indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
read = mi[indexi];
if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
indexi = -1;
end
if (cyc==7) begin
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
string v;
// verilator lint_off UNUSED
integer unused[];
// verilator lint_on UNUSED
typedef bit [7:0] byte_t;
byte_t a[];
byte_t b[];
// wide data array
typedef struct packed {
logic [15:0] header;
logic [223:0] payload;
logic [15:0] checksum;
} pck256_t;
pck256_t p256[];
string s[] = { "hello", "sad", "world" };
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
`checkh(a.size, 0);
v = $sformatf("%p", a); `checks(v, "'{}");
`checkh(s.size, 3);
`checks(s[0], "hello");
`checks(s[1], "sad");
`checks(s[2], "world");
a = new [3];
`checkh(a.size, 3);
a[0] = 10;
a[1] = 11;
a[2] = 12;
`checkh(a[0], 10);
`checkh(a[1], 11);
`checkh(a[2], 12);
v = $sformatf("%p", a); `checks(v, "'{'ha, 'hb, 'hc} ");
a.delete;
`checkh(a.size, 0);
a = '{15, 16};
`checkh(a.size, 2);
`checkh(a[0], 15);
`checkh(a[1], 16)
a = {17, 18};
`checkh(a.size, 2);
`checkh(a[0], 17);
`checkh(a[1], 18)
a = '{17};
`checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern
`checkh(a[0], 17);
a = new[2];
a[0] = 5;
a[1] = 6;
`checkh(a[0], 5);
`checkh(a[1], 6);
a = new[2];
`ifdef verilator // bug2618
a[0] = 0;
a[1] = 0;
`endif
`checkh(a[0], 0);
`checkh(a[1], 0);
a[0] = 5;
a[1] = 6;
`checkh(a[0], 5);
`checkh(a[1], 6);
b = new [4](a);
`checkh(b.size, 4);
`checkh(b[0], 5);
`checkh(b[1], 6);
`ifdef verilator // bug2618
b[2] = 0;
b[3] = 0;
`endif
`checkh(b[2], 0);
`checkh(b[3], 0);
a = b;
`checkh(a.size, 4);
`checkh(a[0], 5);
`checkh(a[1], 6);
`checkh(a[2], 0);
`checkh(a[3], 0);
a = new [0];
`checkh(a.size, 0);
b = new [4](a);
`checkh(b.size, 4);
`ifdef verilator // bug2618
b[0] = 0;
b[1] = 0;
b[2] = 0;
b[3] = 0;
`endif
`checkh(b[0], 0);
`checkh(b[1], 0);
`checkh(b[2], 0);
`checkh(b[3], 0);
a = new[4] ('{8'd1,8'd2,8'd3,8'd4});
`checkh(a.size, 4);
`checkh(a[0], 1);
`checkh(a[1], 2);
`checkh(a[2], 3);
`checkh(a[3], 4);
i = 0;
foreach (a[j]) i += int'(a[j]);
`checkh(i, 1 + 2 + 3 + 4);
// test wide dynamic array
p256 = new [11];
`checkh(p256.size, 11);
`checkh(p256.size(), 11);
p256[1].header = 16'hcafe;
p256[1].payload = {14{16'hbabe}};
p256[1].checksum = 16'hdead;
`checkh(p256[1].header, 16'hcafe);
`checkh(p256[1], {16'hcafe,{14{16'hbabe}},16'hdead});
//X's: `checkh(p256[0], 'x);
p256[5] = '1;
`checkh(p256[5], {32{8'hff}});
p256[5].header = 16'h2;
`checkh(p256[5], {16'h2,{30{8'hff}}});
p256[2] = ( p256[5].header == 2 ) ? p256[1] : p256[5];
`checkh(p256[2], {16'hcafe,{14{16'hbabe}},16'hdead});
p256.delete();
`checkh(p256.size, 0);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module fifo_packer_128 (
input CLK,
input RST,
input [127:0] DATA_IN, // Incoming data
input [2:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [127:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);reg [2:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [223:0] rPackedData=224'd0, _rPackedData=224'd0;
reg [127:0] rDataIn=128'd0, _rDataIn=128'd0;
reg [2:0] rDataInEn=0, _rDataInEn=0;
reg [127:0] rDataMasked=128'd0, _rDataMasked=128'd0;
reg [2:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[127:0];
assign PACKED_WEN = rPackedCount[2];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 4 words are available, then writes 4 words out.
wire [127:0] wMask = {128{1'b1}}<<(32*rDataInEn);
wire [127:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 3'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 224'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 3'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 3'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// bug420
typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
wire [6:0] out = line_wb_ind( in[6:0] );
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc918fa0aa882a206
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function wb_ind_t line_wb_ind( id_t id );
if( id[$bits(id_t)-1] == 0 )
return {2'b00, id[$bits(wb_ind_t)-3:0]};
else
return {2'b01, id[$bits(wb_ind_t)-3:0]};
endfunction // line_wb_ind
endmodule
|
// Model of FIFO in Altera
module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 1024;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output wrempty;
output [9:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [9:0] rdusedw;
reg [9:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
assign wrempty = (wrusedw == 0);
assign wrfull = (wrusedw == depth-1);
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
endmodule // fifo_1c_1k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg check; initial check = 1'b0;
// verilator lint_off WIDTH
//============================================================
reg [ 1:0] W0095; //=3
reg [ 58:0] W0101; //=0000000FFFFFFFF
always @(posedge clk) begin
if (cyc==1) begin
W0095 = ((2'h3));
W0101 = ({27'h0,({16{(W0095)}})});
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop;
end
end
//============================================================
reg [ 0:0] W1243; //=1
always @(posedge clk) begin
if (cyc==1) begin
W1243 = ((1'h1));
end
end
always @(posedge clk) begin
if (cyc==2) begin
// Width violation, but still...
if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop;
if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop;
end
end
//============================================================
reg [ 0:0] W0344; //=0
always @(posedge clk) begin
if (cyc==1) begin
W0344 = 1'b0;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0344) != (1'h0)) if (check) $stop;
if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop;
end
end
//============================================================
reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF
reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF
reg [115:0] W0421; //=00000000000000000000000000000
always @(posedge clk) begin
if (cyc==1) begin
W0372 = ({64{((1'h1))}});
W0421 = 116'h0;
W0420 = ({119{((W0372) <= (W0372))}});
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop;
end
end
//============================================================
// gcc_2_96_bug
reg [ 31:0] W0161; //=FFFFFFFF
reg [ 62:0] W0217; //=0000000000000000
reg [ 53:0] W0219; //=00000000000000
always @(posedge clk) begin
if (cyc==1) begin
W0161 = 32'hFFFFFFFF;
W0217 = 63'h0;
W0219 = 54'h0;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if ((W0161) != (32'hFFFFFFFF)) if (check) $stop;
if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop;
end
end
//============================================================
reg [119:0] W0592; //=000000000000000000000000000000
reg [ 7:0] W0593; //=70
always @(posedge clk) begin
if (cyc==1) begin
W0593 = (((8'h90)) * ((8'hFF)));
W0592 = 120'h000000000000000000000000000000;
end
end
always @(posedge clk) begin
if (cyc==2) begin
if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop;
end
end
//============================================================
reg [127:0] WA1063 ; //=00000000000000000000000000000001
reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF
reg [ 62:0] WA1065 ; //=0000000000000000
reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001
reg [ 34:0] WA1067 ; //=7FFFFFFFF
reg [111:0] WA1068;
always @(check) begin
WA1067 = (~ (35'h0));
WA1066 = (90'h00000000000000000000001);
WA1065 = (WA1066[89:27]);
WA1064 = (WA1067);
WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001))));
end
always @(posedge clk) begin
if (cyc==2) begin
if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop;
end
end
//============================================================
reg [127:0] WB1063 ; //=00000000000000000000000000000001
reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF
reg [ 62:0] WB1065 ; //=0000000000000000
reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001
reg [ 34:0] WB1067 ; //=7FFFFFFFF
reg [111:0] WB1068;
always @(posedge clk) begin
if (cyc==1) begin
WB1067 = (~ (35'h0));
WB1066 = (90'h00000000000000000000001);
end
if (cyc==2) WB1065 <= (WB1066[89:27]);
if (cyc==3) WB1064 <= (WB1067);
if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001))));
if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]);
end
always @(posedge clk) begin
if (cyc==9) begin
if (WB1068 != 112'h0) if (check) $stop;
if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop;
end
end
//============================================================
reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF
reg signed [ 6:0] WC0065 ; //=00
reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF
always @(check) begin
WC0064 = 61'sh1FFFFFFFFFFFFFFF;
WC0065 = 7'sh0;
if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop;
end
//============================================================
reg signed [ 76:0] W0234 ; //=00000000000000000000
reg signed [ 7:0] W0235 /*verilator public*/; //=B6
always @(check) begin
W0235 = 8'shb6;
W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235));
if ((W0234) != 77'sh0) if (check) $stop;
end
//============================================================
reg signed [ 30:0] W0146 ; //=00000001
always @(check) begin : Block71
W0146 = (31'sh00000001);
if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop;
end
//============================================================
reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF
always @(check) begin : Block405
W0857 = 55'sh7fffffffffffff;
if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop;
end
//============================================================
always @(posedge clk) begin
if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop;
if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop;
end
//============================================================
reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA
always @* begin : Block144
W0226 = 83'sh47A4301EE3FB4133EE3DA;
if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop;
end
//============================================================
reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C
reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A
always @(posedge clk) begin
W0793 <= 69'sh1f_ffffffff_4eb1a91a;
W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E);
if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop;
end
//============================================================
reg signed [ 2:0] DW0515 /*verilator public*/; //=7
always @(posedge clk) begin
DW0515 <= 3'sh7;
if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop;
end
//============================================================
reg signed [ 62:0] W0753 ; //=004E20004ED93E26
reg [ 2:0] W0772 /*verilator public*/; //=7
always @(posedge clk) begin
W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff)));
W0772 <= 3'h7;
if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop;
if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop;
end
//============================================================
reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF
always @(posedge clk) begin
W1027 <= ~99'h0;
// verilator lint_off CMPCONST
if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop;
// verilator lint_on CMPCONST
end
//============================================================
reg signed [ 5:0] W123_is_3f ; //=3F
always @(posedge clk) begin
W123_is_3f <= 6'sh3f;
end
always @(posedge clk) begin
if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop;
end
//============================================================
reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1
always @(check) begin : Block237
W0032 = 106'sh3ff0000000100000000bd597bb1;
if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop;
if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop;
end
//============================================================
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==18) begin
check <= 1'b1;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`include "verilated.v"
module t;
`verilator_file_descriptor file;
integer chars;
reg [1*8:1] letterl;
reg [8*8:1] letterq;
reg [16*8:1] letterw;
reg [16*8:1] letterz;
real r;
string s;
reg [7:0] v_a,v_b,v_c,v_d;
reg [31:0] v_worda;
reg [31:0] v_wordb;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
`define verbose 1'b0
`endif
initial begin
// Display formatting
`ifdef verilator
if (file != 0) $stop;
$fwrite(file, "Never printed, file closed\n");
if (!$feof(file)) $stop;
`endif
`ifdef AUTOFLUSH
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_autoflush/t_sys_file_autoflush.log","w");
`else
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/t_sys_file_basic_test.log","w");
`endif
if ($feof(file)) $stop;
$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
$fwrite(file, "[%0t] %s\n", $time, "Hello2");
$fflush(file);
$fclose(file);
`ifdef verilator
if (file != 0) $stop(1); // Also test arguments to stop
$fwrite(file, "Never printed, file closed\n");
`endif
begin
// Check for opening errors
// The "r" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/DOES_NOT_EXIST","r");
if (|file) $stop; // Should not exist, IE must return 0
end
begin
// Check quadword access; a little strange, but it's legal to open "."
file = $fopen(".","r");
$fclose(file);
end
begin
// Check read functions w/string
s = "t/t_sys_file_basic_input.dat";
file = $fopen(s,"r");
if ($feof(file)) $stop;
$fclose(file);
end
begin
// Check read functions
file = $fopen("t/t_sys_file_basic_input.dat","r");
if ($feof(file)) $stop;
// $fgetc
if ($fgetc(file) != "h") $stop;
if ($fgetc(file) != "i") $stop;
if ($fgetc(file) != "\n") $stop;
// $fgets
chars = $fgets(letterl, file);
if (`verbose) $write("c=%0d l=%s\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "l") $stop;
chars = $fgets(letterq, file);
if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline
if (chars != 5) $stop;
if (letterq != "\0\0\0quad\n") $stop;
letterw = "5432109876543210";
chars = $fgets(letterw, file);
if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline
if (chars != 10) $stop;
if (letterw != "\0\0\0\0\0\0widestuff\n") $stop;
// $sscanf
if ($sscanf("x","")!=0) $stop;
if ($sscanf("z","z")!=0) $stop;
chars = $sscanf("blabcdefghijklmnop",
"%s", letterq);
if (`verbose) $write("c=%0d sa=%s\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != "ijklmnop") $stop;
chars = $sscanf("xa=1f xb=12898971238912389712783490823_237904689_02348923",
"xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h38971278349082323790468902348923) $stop;
chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ",
"ba=%b bb=%b%s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop;
chars = $sscanf("oa=23 ob=125634123615234123681236",
"oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h55ce14f1a9c29e) $stop;
chars = $sscanf("r=0.1 d=-236123",
"r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
s = "r=0.2 d=-236124";
chars = $sscanf(s, "r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.2) $stop;
if (letterq != 64'hfffffffffffc65a4) $stop;
// $fscanf
if ($fscanf(file,"")!=0) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h23790468902348923) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != "\0\0\0\0note_the_two") $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h1573) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "d=%d", letterq);
if (`verbose) $write("c=%0d d=%0x\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "%c%s", letterl, letterw);
if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw);
if (chars != 2) $stop;
if (letterl != "f") $stop;
if (letterw != "\0\0\0\0\0redfishblah") $stop;
chars = $fscanf(file, "%c", letterl);
if (`verbose) $write("c=%0d l=%x\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "\n") $stop;
// msg1229
v_a = $fgetc(file);
v_b = $fgetc(file);
v_c = $fgetc(file);
v_d = $fgetc(file);
v_worda = { v_d, v_c, v_b, v_a };
if (v_worda != "4321") $stop;
v_wordb[7:0] = $fgetc(file);
v_wordb[15:8] = $fgetc(file);
v_wordb[23:16] = $fgetc(file);
v_wordb[31:24] = $fgetc(file);
if (v_wordb != "9876") $stop;
if ($fgetc(file) != "\n") $stop;
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
function sync;
input [7:0] cexp;
reg [7:0] cgot;
begin
cgot = $fgetc(file);
if (`verbose) $write("sync=%x='%c'\n", cgot,cgot);
sync = (cgot == cexp);
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
//
// This code instantiates a module that calls the various array querying
// functions.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
// Check the array sizing functions work correctly.
module array_test
#( parameter
LEFT = 5,
RIGHT = 55)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
reg [7:0] a [LEFT:RIGHT];
// verilator lint_on LITENDIAN
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module hct7474 #(parameter BLOCKS = 2, DELAY_RISE = 18, DELAY_FALL = 18, LOG = 0, NAME = "7474FF")
(
input [BLOCKS-1:0] _SD,
input [BLOCKS-1:0] _RD,
input [BLOCKS-1:0] D,
input [BLOCKS-1:0] CP,
output [BLOCKS-1:0] Q,
output [BLOCKS-1:0] _Q
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg [BLOCKS-1:0] Qb_current;
reg [BLOCKS-1:0] _SD_previous;
reg [BLOCKS-1:0] Q_defined = 0;
if (LOG)
always @*
$display("%9t ", $time, "%m CP=%1b D=%1b _SD=%1b _RD=%1b => Q=%1b _Q=%1b", CP,D,_SD, _RD, Q, _Q);
//if (LOG) always @* $display("%8d ", $time, "%s CP=%1b D=%1b _SD=%1b _RD=%1b Q=%1b _Q=%1b (Qc=%1b, _Qc=%1b)", NAME, CP,D,_SD, _RD, Q, _Q, Q_current, Qb_current);
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1)
begin: gen_blocks
always @(posedge CP[i])
begin
if (_RD[i] && _SD[i])
begin
if (LOG>1) $display("%9t", $time, " %s CLOCK IN DATA Q=%1b", NAME, D);
Q_defined[i] = 1'b1;
Q_current[i] = D[i];
Qb_current[i] = !D[i];
end
else
begin
if (LOG>1) $display("%9t", $time, " %s CLOCK IN DISABLED BY CLEAR or PRESET", NAME);
end
end
always @(_RD[i] or _SD[i])
begin
if (!_RD[i] && !_SD[i])
begin
if (LOG>1) $display("%9t", $time, " %s FORCE Q=_Q=1", NAME);
Q_current[i] = 1'b1;
Qb_current[i] = 1'b1;
end
else if (!_RD[i])
begin
if (LOG>1) $display("%9t", $time, " %s Q=0", NAME);
Q_defined[i] = 1'b1;
Q_current[i] = 1'b0;
Qb_current[i] = 1'b1;
end
else if (!_SD[i])
begin
if (LOG>1) $display("%9t", $time, " %s Q=1", NAME);
Q_defined[i] = 1'b1;
Q_current[i] = 1'b1;
Qb_current[i] = 1'b0;
end
else //
begin
if (!Q_defined[i]) begin
if (LOG) $display("%9t", $time, " %s Q=X NOT CLEAR AND NOT PRESET", NAME);
// no value has been defined - realistically a random value would be settled on, we'll use X
Q_current[i] = 1'bx;
Qb_current[i] = 1'bx;
end
else
if (LOG>1) $display("%9t", $time, " %s Q=%1b - HOLD", NAME, Q_current);
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) _Q = Qb_current;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [2:0] sum;
wire [2:0] in = crc[2:0];
wire [2:0] out;
MxN_pipeline pipe (in, out, clk);
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 3'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[1:0],sum[2]} ^ out;
end
else if (cyc==99) begin
if (crc !== 8'b01110000) $stop;
if (sum !== 3'h3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module dffn (q,d,clk);
parameter BITS = 1;
input [BITS-1:0] d;
output reg [BITS-1:0] q;
input clk;
always @ (posedge clk) begin
q <= d;
end
endmodule
module MxN_pipeline (in, out, clk);
parameter M=3, N=4;
input [M-1:0] in;
output [M-1:0] out;
input clk;
// Unsupported: Per-bit array instantiations with output connections to non-wires.
//wire [M*(N-1):1] t;
//dffn #(M) p[N:1] ({out,t},{t,in},clk);
wire [M*(N-1):1] w;
wire [M*N:1] q;
dffn #(M) p[N:1] (q,{w,in},clk);
assign {out,w} = q;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [43:0] mi;
reg [5:0] index;
integer indexi;
reg read;
initial begin
// Static
mi = 44'b01010101010101010101010101010101010101010101;
if (mi[0] !== 1'b1) $stop;
if (mi[1 -: 2] !== 2'b01) $stop;
`ifdef VERILATOR
// verilator lint_off SELRANGE
if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
// verilator lint_on SELRANGE
`else
if (mi[-1] !== 1'bx) $stop;
if (mi[0 -: 2] !== 2'b1x) $stop;
if (mi[-1 -: 2] !== 2'bxx) $stop;
`endif
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
mi = 44'h123;
end
if (cyc==2) begin
index = 6'd43;
indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
read = mi[indexi];
if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
indexi = -1;
end
if (cyc==7) begin
read = mi[indexi];
$display("-Illegal read value: %x", read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\\n",$time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Sean Moore.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] tripline = crc[7:0];
/*AUTOWIRE*/
wire valid;
wire [3-1:0] value;
PriorityChoice #(.OCODEWIDTH(3))
pe (.out(valid), .outN(value[2:0]), .tripline(tripline));
// Aggregate outputs into a single result vector
wire [63:0] result = {59'h0, valid, value};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc5fc632f816568fb
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module PriorityChoice (out, outN, tripline);
parameter OCODEWIDTH = 1;
localparam CODEWIDTH=OCODEWIDTH-1;
localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH;
output reg out;
output reg [OCODEWIDTH-1:0] outN;
input wire [(1<<OCODEWIDTH)-1:0] tripline;
wire left;
wire [SCODEWIDTH-1:0] leftN;
wire right;
wire [SCODEWIDTH-1:0] rightN;
generate
if(OCODEWIDTH==1) begin
assign left = tripline[1];
assign right = tripline[0];
always @(*) begin
out <= left || right ;
if(right) begin outN <= {1'b0}; end
else begin outN <= {1'b1}; end
end
end else begin
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
leftMap
(
.out(left),
.outN(leftN),
.tripline(tripline[(2<<CODEWIDTH)-1:(1<<CODEWIDTH)])
);
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
rightMap
(
.out(right),
.outN(rightN),
.tripline(tripline[(1<<CODEWIDTH)-1:0])
);
always @(*) begin
if(right) begin
out <= right;
outN <= {1'b0, rightN[OCODEWIDTH-2:0]};
end else begin
out <= left;
outN <= {1'b1, leftN[OCODEWIDTH-2:0]};
end
end
end
endgenerate
endmodule
|
module pipeline_bridge_PERIPHERALS_downstream_adapter (
// inputs:
m1_clk,
m1_endofpacket,
m1_readdata,
m1_readdatavalid,
m1_reset_n,
m1_waitrequest,
s1_address,
s1_arbiterlock,
s1_arbiterlock2,
s1_burstcount,
s1_byteenable,
s1_chipselect,
s1_debugaccess,
s1_nativeaddress,
s1_read,
s1_write,
s1_writedata,
// outputs:
m1_address,
m1_arbiterlock,
m1_arbiterlock2,
m1_burstcount,
m1_byteenable,
m1_chipselect,
m1_debugaccess,
m1_nativeaddress,
m1_read,
m1_write,
m1_writedata,
s1_endofpacket,
s1_readdata,
s1_readdatavalid,
s1_waitrequest
)
;output [ 11: 0] m1_address;
output m1_arbiterlock;
output m1_arbiterlock2;
output m1_burstcount;
output [ 3: 0] m1_byteenable;
output m1_chipselect;
output m1_debugaccess;
output [ 9: 0] m1_nativeaddress;
output m1_read;
output m1_write;
output [ 31: 0] m1_writedata;
output s1_endofpacket;
output [ 31: 0] s1_readdata;
output s1_readdatavalid;
output s1_waitrequest;
input m1_clk;
input m1_endofpacket;
input [ 31: 0] m1_readdata;
input m1_readdatavalid;
input m1_reset_n;
input m1_waitrequest;
input [ 11: 0] s1_address;
input s1_arbiterlock;
input s1_arbiterlock2;
input s1_burstcount;
input [ 3: 0] s1_byteenable;
input s1_chipselect;
input s1_debugaccess;
input [ 9: 0] s1_nativeaddress;
input s1_read;
input s1_write;
input [ 31: 0] s1_writedata;
reg [ 11: 0] m1_address;
reg m1_arbiterlock;
reg m1_arbiterlock2;
reg m1_burstcount;
reg [ 3: 0] m1_byteenable;
reg m1_chipselect;
reg m1_debugaccess;
reg [ 9: 0] m1_nativeaddress;
reg m1_read;
reg m1_write;
reg [ 31: 0] m1_writedata;
wire s1_endofpacket;
wire [ 31: 0] s1_readdata;
wire s1_readdatavalid;
wire s1_waitrequest;
//s1, which is an e_avalon_adapter_slave
//m1, which is an e_avalon_adapter_master
assign s1_endofpacket = m1_endofpacket;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign s1_waitrequest = m1_waitrequest;
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_address <= 0;
else if (~m1_waitrequest)
m1_address <= s1_address;
end
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_arbiterlock <= 0;
else if (~m1_waitrequest)
m1_arbiterlock <= s1_arbiterlock;
end
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_arbiterlock2 <= 0;
else if (~m1_waitrequest)
m1_arbiterlock2 <= s1_arbiterlock2;
end
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_burstcount <= 0;
else if (~m1_waitrequest)
m1_burstcount <= s1_burstcount;
end
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_byteenable <= 0;
else if (~m1_waitrequest)
m1_byteenable <= s1_byteenable;
end
always @(posedge m1_clk or negedge m1_reset_n)
begin
if (m1_reset_n == 0)
m1_chipselect <= 0;
else if (~m1_waitrequest)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_clk (/*AUTOARG*/
// Outputs
passed,
// Inputs
fastclk, clk, reset_l
);
input fastclk;
input clk;
input reset_l;
output passed; reg passed; initial passed = 0;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
//$write("CLK1 %x\n", reset_l);
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_clk: Running\n",$time);
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
//$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
//$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
passed <= 1'b1;
$write("[%0t] t_clk: Passed\n",$time);
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
//$write("CLK4 %x\n", reset_l);
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
|
module pipeline_bridge_PERIPHERALS_waitrequest_adapter (
// inputs:
m1_endofpacket,
m1_readdata,
m1_readdatavalid,
m1_waitrequest,
s1_address,
s1_arbiterlock,
s1_arbiterlock2,
s1_burstcount,
s1_byteenable,
s1_chipselect,
s1_debugaccess,
s1_nativeaddress,
s1_read,
s1_write,
s1_writedata,
// outputs:
m1_address,
m1_arbiterlock,
m1_arbiterlock2,
m1_burstcount,
m1_byteenable,
m1_chipselect,
m1_debugaccess,
m1_nativeaddress,
m1_read,
m1_write,
m1_writedata,
s1_endofpacket,
s1_readdata,
s1_readdatavalid,
s1_waitrequest
)
;output [ 13: 0] m1_address;
output m1_arbiterlock;
output m1_arbiterlock2;
output m1_burstcount;
output [ 3: 0] m1_byteenable;
output m1_chipselect;
output m1_debugaccess;
output [ 11: 0] m1_nativeaddress;
output m1_read;
output m1_write;
output [ 31: 0] m1_writedata;
output s1_endofpacket;
output [ 31: 0] s1_readdata;
output s1_readdatavalid;
output s1_waitrequest;
input m1_endofpacket;
input [ 31: 0] m1_readdata;
input m1_readdatavalid;
input m1_waitrequest;
input [ 13: 0] s1_address;
input s1_arbiterlock;
input s1_arbiterlock2;
input s1_burstcount;
input [ 3: 0] s1_byteenable;
input s1_chipselect;
input s1_debugaccess;
input [ 11: 0] s1_nativeaddress;
input s1_read;
input s1_write;
input [ 31: 0] s1_writedata;
wire [ 13: 0] m1_address;
wire m1_arbiterlock;
wire m1_arbiterlock2;
wire m1_burstcount;
wire [ 3: 0] m1_byteenable;
wire m1_chipselect;
wire m1_debugaccess;
wire [ 11: 0] m1_nativeaddress;
wire m1_read;
wire m1_write;
wire [ 31: 0] m1_writedata;
wire s1_endofpacket;
wire [ 31: 0] s1_readdata;
wire s1_readdatavalid;
wire s1_waitrequest;
|
/* Proiectati un codificator binar de prioritati 8-la-3, unde iesirea va reprezenta indexul intrarii active cu prioritatea cea mai mare.
Prioritatea bitilor este: in[7] > in[6] > in[5] > in[4] > in[3] > in[2] > in[1] > in[0]. */
module prioirty_enc(input[7:0] prio_in, output[2:0] prio_out);
reg [2:0] pozitie;
integer i;
always@(*) begin
for(i=0;i<8;i=i+1) begin
if(prio_in[i]) begin
pozitie=i;
end
end
end
assign prio_out=pozitie;
endmodule
module priority_enc_tb;
reg[7:0] prio_in;
wire[2:0] act_prio_out;
reg[2:0] exp_prio_out;
wire verdict;
prioirty_enc uut(.prio_in(prio_in), .prio_out(act_prio_out));
integer tests_total, tests_passed, nota;
integer data_file, random_int;
assign verdict = exp_prio_out === act_prio_out;
initial begin
$display("prio_in\\t\\texpected_prio_out\\tactual_prio_out\\tPassed(1)/Failed(0)");
$monitor("%8b\\t\\t%16b\\t%15b\\t%18d", prio_in, exp_prio_out, act_prio_out, verdict);
tests_total = 0;
tests_passed = 0;
data_file = 0;
data_file = $fopen("ex2_tests.dat", "r");
if (data_file == 0) begin
$display("Adauga fisierul ex2_tests.dat in acelasi folder");
$finish;
end
while(!$feof(data_file)) begin
random_int = $fscanf(data_file, "%b %b\\n", prio_in, exp_prio_out);
tests_total = tests_total +1;
#1;
tests_passed = tests_passed + verdict;
end
$display("Passed / Total: %2d / %2d", tests_passed, tests_total);
nota = tests_passed * 1000 / tests_total * 2;
$display("Nota: %1d.%03d", nota / 1000, nota % 1000);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Wildcard
string a [*];
int k;
string v;
a[32'd1234] = "fooed";
a[4'd3] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size(); `checkh(i, 2);
v = a[32'd1234]; `checks(v, "fooed");
v = a[4'd3]; `checks(v, "bared");
i = a.exists("baz"); `checkh(i, 0);
i = a.exists(4'd3); `checkh(i, 1);
i = a.first(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.next(k); `checkh(i, 1); `checks(k, 32'd1234);
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, 32'd1234);
i = a.prev(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.prev(k); `checkh(i, 0);
a.delete(4'd3);
i = a.size(); `checkh(i, 1);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 19;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
begin
/* data transfer */
inj_data = {38{1'b0}};
for (j = 0; j < len; j = j + 1) begin
#(STEP)
case(inj_data)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Sub sub1 (.*);
Sub sub2 (.*);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
always_ff @ (posedge clk) begin
labeled_icov: cover (cyc==3 || cyc==4);
end
// Immediate cover
labeled_imm0: cover #0 (cyc == 0);
labeled_immf: cover final (cyc == 0);
// Immediate assert
labeled_imas: assert #0 (1);
assert final (1);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
module Sub
(
input clk,
input integer cyc
);
// Simple cover, per-instance
pi_sub:
cover property (@(posedge clk) cyc == 3);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
interface counter_if;
logic [3:0] value;
logic reset;
modport counter_mp (input reset, output value);
modport core_mp (output reset, input value);
endinterface
// Check can have inst module before top module
module counter_ansi
(
input clkm,
counter_if c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_if c1_data();
counter_if c2_data();
counter_if c3_data();
counter_if c4_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data.counter_mp),
.i_value(4'h1));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c2 (.clkm(clk),
.c_data(c2_data.counter_mp),
.i_value(4'h2));
counter_ansi_m c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
`ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif
/**/ c4 (.clkm(clk),
.c_data(c4_data),
.i_value(4'h4));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
c4_data.value = 4'h7;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
c4_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
c4_data.reset <= 0;
end
if (cyc==20) begin
$write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset,
c4_data.value, c4_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
if (c4_data.value != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi
(clkm, c_data, i_value);
input clkm;
counter_if c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module counter_ansi_m
(
input clkm,
counter_if.counter_mp c_data,
input logic [3:0] i_value
);
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi_m
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi_m
(clkm, c_data, i_value);
input clkm;
counter_if.counter_mp c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi_m
`endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverybkb_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverybkb_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverybkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverybkb_ram contact_discoverybkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// bug998
interface intf
#(parameter PARAM = 0)
();
logic val;
function integer func (); return 5; endfunction
endinterface
module t1(intf mod_intf);
initial begin
$display("%m %d", mod_intf.val);
end
endmodule
module t();
intf #(.PARAM(1)) my_intf [1:0] ();
generate
genvar the_genvar;
begin : ia
for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
begin
assign my_intf[the_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_genvar]));
end
end
end
endgenerate
generate
genvar the_second_genvar;
begin : ib
intf #(.PARAM(1)) my_intf [1:0] ();
for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf
begin
assign my_intf[the_second_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_second_genvar]));
end
end
end
endgenerate
generate
genvar the_third_genvar;
begin : ic
for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf
begin
intf #(.PARAM(1)) my_intf [1:0] ();
assign my_intf[the_third_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_third_genvar]));
end
end
end
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\n",$time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
//bug456
typedef logic signed [34:0] rc_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [34:0] rc = crc[34:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic o; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.rc (rc),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, o};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7211d24a17b25ec9
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test( output logic o,
input rc_t rc,
input logic clk);
localparam RATIO = 2;
rc_t rc_d[RATIO:1];
always_ff @(posedge clk) begin
integer k;
rc_d[1] <= rc;
for( k=2; k<RATIO+1; k++ ) begin
rc_d[k] <= rc_d[k-1];
end
end // always_ff @
assign o = rc_d[RATIO] < 0;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer j;
integer hit_count;
reg [63:0] cam_lookup_hit_vector;
strings strings ();
task show;
input [8*8-1:0] str;
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
end
$write("\n");
end
endtask
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
show("hello\000xx");
end
if (cyc==2) begin
show("world\000xx");
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module strings;
// **NOT** reentrant, just a test!
integer index;
task stringStart;
input [31:0] bits;
begin
index = (bits-1)/8;
end
endtask
function isNull;
input [7:0] chr;
isNull = (chr == 8'h0);
endfunction
function [7:0] stringByte;
input [8*8-1:0] str;
begin
if (index<=0) stringByte=8'h0;
else stringByte = str[index*8 +: 8];
index = index - 1;
end
endfunction
endmodule
|
module for an adder */
`timescale 10ns/10ps
module tb_adder;parameter PAYLOAD = 20; //how many flits per packet
parameter N = 8;
parameter STEP = 1.0;
integer i;
// Inputs
reg [N-1:0] input1; //time is unsigned 64 bit integer
reg [N-1:0] input2;
// Outputs
wire [N-1:0] sum;
integer count, seed;
reg clk;
always #( STEP / 2 ) begin
clk <= ~clk;
end
always #( STEP ) begin
count = count + 1;
seed = seed + 1;
end
// Instantiate the Unit Under Test (UUT)
adder adder (
.input1(input1),
.input2(input2),
.sum(sum)
);
initial begin
// Initialize Inputs
$dumpfile("dump_adder.vcd");
$dumpvars(0,tb_adder.adder);
$dumpoff;
/* Initialization */
#0
clk <= {1'b0};
count = 0;
input1 <= 0;
input2 <= 0;
#(STEP)
#(STEP / 2)
$write("Start clock %d \n", count);
$dumpon;
for (i = 0; i < 10; i = i + 1) begin //10 packets are sent. each packet has 20 data flits (payload, len=20)
send_data( PAYLOAD );
#(STEP*7) // Link utilization 4/13=0.30 (flit_rate injection)
$write("------------------------\n");
end
#(STEP)
$write("Stop clock %d \n", count);
$dumpoff;
$finish;
end
task send_data;
input [31:0] len; //payload
integer j;
//reg [31:0] ran0;
//reg [31:0] ran1;
time inj_data; //"time" is unsigned 64 bit datatype
begin
/* data transfer */
inj_data = {16{1'b0}};
for (j = 0; j < len; j = j + 1) begin
#(STEP)
case(inj_data)
{16'b0000000000000000} : inj_data = {16'b1111100000000000};
{16'b1111100000000000} : inj_data = {16'b1111111111000000};
{16'b1111111111000000} : inj_data = {16'b1111111111111110};
{16'b1111111111111110} : inj_data = {16'b0000111111111111};
{16'b0000111111111111} : inj_data = {16'b0000000001111111};
{16'b0000000001111111} : inj_data = {16'b0000000000000011};
{16'b0000000000000011} : inj_data = {16'b1110000000000000};
{16'b1110000000000000} : inj_data = {16'b1111111100000000};
{16'b1111111100000000} : inj_data = {16'b1111111111111000};
{16'b1111111111111000} : inj_data = {16'b0011111111111111};
{16'b0011111111111111} : inj_data = {16'b0000000111111111};
{16'b0000000111111111} : inj_data = {16'b0000000000001111};
{16'b0000000000001111} : inj_data = {16'b1000000000000000};
{16'b1000000000000000} : inj_data = {16'b1111110000000000};
{16'b1111110000000000} : inj_data = {16'b1111111111100000};
{16'b1111111111100000} : inj_data = {16'b1111111111111111};
{16'b1111111111111111} : inj_data = {16'b0000011111111111};
{16'b0000011111111111} : inj_data = {16'b0000000000111111};
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`include "verilated.v"
module t;
`verilator_file_descriptor file;
integer chars;
reg [1*8:1] letterl;
reg [8*8:1] letterq;
reg [16*8:1] letterw;
reg [16*8:1] letterz;
real r;
string s;
reg [7:0] v_a,v_b,v_c,v_d;
reg [31:0] v_worda;
reg [31:0] v_wordb;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
`define verbose 1'b0
`endif
initial begin
// Display formatting
`ifdef verilator
if (file != 0) $stop;
$fwrite(file, "Never printed, file closed\n");
if (!$feof(file)) $stop;
`endif
`ifdef AUTOFLUSH
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_autoflush/t_sys_file_autoflush.log","w");
`else
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/t_sys_file_basic_test.log","w");
`endif
if ($feof(file)) $stop;
$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
$fwrite(file, "[%0t] %s\n", $time, "Hello2");
$fflush(file);
$fclose(file);
`ifdef verilator
if (file != 0) $stop(1); // Also test arguments to stop
$fwrite(file, "Never printed, file closed\n");
`endif
begin
// Check for opening errors
// The "r" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/DOES_NOT_EXIST","r");
if (|file) $stop; // Should not exist, IE must return 0
end
begin
// Check quadword access; a little strange, but it's legal to open "."
file = $fopen(".","r");
$fclose(file);
end
begin
// Check read functions w/string
s = "t/t_sys_file_basic_input.dat";
file = $fopen(s,"r");
if ($feof(file)) $stop;
$fclose(file);
end
begin
// Check read functions
file = $fopen("t/t_sys_file_basic_input.dat","r");
if ($feof(file)) $stop;
// $fgetc
if ($fgetc(file) != "h") $stop;
if ($fgetc(file) != "i") $stop;
if ($fgetc(file) != "\n") $stop;
// $fgets
chars = $fgets(letterl, file);
if (`verbose) $write("c=%0d l=%s\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "l") $stop;
chars = $fgets(letterq, file);
if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline
if (chars != 5) $stop;
if (letterq != "\0\0\0quad\n") $stop;
letterw = "5432109876543210";
chars = $fgets(letterw, file);
if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline
if (chars != 10) $stop;
if (letterw != "\0\0\0\0\0\0widestuff\n") $stop;
// $sscanf
if ($sscanf("x","")!=0) $stop;
if ($sscanf("z","z")!=0) $stop;
chars = $sscanf("blabcdefghijklmnop",
"%s", letterq);
if (`verbose) $write("c=%0d sa=%s\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != "ijklmnop") $stop;
chars = $sscanf("xa=1f xb=12898971238912389712783490823_237904689_02348923",
"xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h38971278349082323790468902348923) $stop;
chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ",
"ba=%b bb=%b%s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop;
chars = $sscanf("oa=23 ob=125634123615234123681236",
"oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h55ce14f1a9c29e) $stop;
chars = $sscanf("r=0.1 d=-236123",
"r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
s = "r=0.2 d=-236124";
chars = $sscanf(s, "r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.2) $stop;
if (letterq != 64'hfffffffffffc65a4) $stop;
// $fscanf
if ($fscanf(file,"")!=0) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h23790468902348923) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != "\0\0\0\0note_the_two") $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h1573) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "d=%d", letterq);
if (`verbose) $write("c=%0d d=%0x\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "%c%s", letterl, letterw);
if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw);
if (chars != 2) $stop;
if (letterl != "f") $stop;
if (letterw != "\0\0\0\0\0redfishblah") $stop;
chars = $fscanf(file, "%c", letterl);
if (`verbose) $write("c=%0d l=%x\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "\n") $stop;
// msg1229
v_a = $fgetc(file);
v_b = $fgetc(file);
v_c = $fgetc(file);
v_d = $fgetc(file);
v_worda = { v_d, v_c, v_b, v_a };
if (v_worda != "4321") $stop;
v_wordb[7:0] = $fgetc(file);
v_wordb[15:8] = $fgetc(file);
v_wordb[23:16] = $fgetc(file);
v_wordb[31:24] = $fgetc(file);
if (v_wordb != "9876") $stop;
if ($fgetc(file) != "\n") $stop;
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
function sync;
input [7:0] cexp;
reg [7:0] cgot;
begin
cgot = $fgetc(file);
if (`verbose) $write("sync=%x='%c'\n", cgot,cgot);
sync = (cgot == cexp);
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2015 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub #(1)
sub0 (allbits, onebit[1:0], bitout[10]),
sub1 (allbits, onebit[3:2], bitout[11]),
sub2 (allbits, onebit[5:4], bitout[12]),
sub3 (allbits, onebit[7:6], bitout[13]),
sub4 (allbits, onebit[9:8], bitout[14]),
sub5 (allbits, onebit[11:10], bitout[15]),
sub6 (allbits, onebit[13:12], bitout[16]),
sub7 (allbits, onebit[15:14], bitout[17]);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub0.bitout !== 1'b1) $stop;
if (sub1.bitout !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
parameter integer P = 0;
initial if (P != 1) $stop;
assign bitout = (^ onebit) ^ (^ allbits);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [19:0] in = crc[19:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [19:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[19:0]),
// Inputs
.in (in[19:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {44'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdb7bc61592f31b99
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
typedef struct packed {
logic [7:0] cn;
logic vbfval;
logic vabval;
} rel_t;
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [19:0] in;
output [19:0] out;
rel_t [1:0] i; // From ifb0 of ifb.v, ...
rel_t [1:0] o; // From ifb0 of ifb.v, ...
assign i = in;
assign out = o;
sub sub
(
.i (i[1:0]),
.o (o[1:0]));
endmodule
module sub (/*AUTOARG*/
// Outputs
o,
// Inputs
i
);
input rel_t [1:0] i;
output rel_t [1:0] o;
assign o = i;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
// that should not work.
//
// The given generate loops should attempt to access invalid bits of mask and
// trigger errors.
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
`define MAX_SIZE 3
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, so we can immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that all have errors in applying short-circuting to
// generate "if" conditionals.
// Attempt to access invalid bits of MASK in different ways
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE + 1)) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g + 1]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise AND
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE)) & MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise OR
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) | ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
wire GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
wire GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
module lab2_task3(SW,LEDG,LEDR);
input[17:0] SW;
output[7:0] LEDG;
output[17:0] LEDR;
assign LEDR=SW;
SR_flipflop DUT(.clk(SW[2]),.s(SW[1]),.r(SW[0]),.q(LEDG[0]),.q_bar(LEDG[1]));
endmodule
module SR_flipflop (
input clk, rst_n,
input s,r,
output reg q,
output q_bar
);
// always@(posedge clk or negedge rst_n) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(rst_n) q <= 0;
else begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
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