type stringclasses 5
values | content stringlengths 9 163k |
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includes | #include <linux/kernel.h> |
includes | #include <linux/module.h> |
includes | #include <linux/of.h> |
includes | #include <linux/of_irq.h> |
includes | #include <linux/of_device.h> |
includes | #include <linux/spi/spi.h> |
defines |
#define DRIVER_NAME "armada_3700_spi" |
defines |
#define A3700_SPI_TIMEOUT 10 /* 10 msec */ |
defines | #define A3700_SPI_IF_CTRL_REG 0x00 |
defines | #define A3700_SPI_IF_CFG_REG 0x04 |
defines | #define A3700_SPI_DATA_OUT_REG 0x08 |
defines | #define A3700_SPI_DATA_IN_REG 0x0C |
defines | #define A3700_SPI_IF_INST_REG 0x10 |
defines | #define A3700_SPI_IF_ADDR_REG 0x14 |
defines | #define A3700_SPI_IF_RMODE_REG 0x18 |
defines | #define A3700_SPI_IF_HDR_CNT_REG 0x1C |
defines | #define A3700_SPI_IF_DIN_CNT_REG 0x20 |
defines | #define A3700_SPI_IF_TIME_REG 0x24 |
defines | #define A3700_SPI_INT_STAT_REG 0x28 |
defines | #define A3700_SPI_INT_MASK_REG 0x2C |
defines | #define A3700_SPI_EN (1 << 16) |
defines | #define A3700_SPI_ADDR_NOT_CONFIG (1 << 12) |
defines | #define A3700_SPI_WFIFO_OVERFLOW (1 << 11) |
defines | #define A3700_SPI_WFIFO_UNDERFLOW (1 << 10) |
defines | #define A3700_SPI_RFIFO_OVERFLOW (1 << 9) |
defines | #define A3700_SPI_RFIFO_UNDERFLOW (1 << 8) |
defines | #define A3700_SPI_WFIFO_FULL (1 << 7) |
defines | #define A3700_SPI_WFIFO_EMPTY (1 << 6) |
defines | #define A3700_SPI_RFIFO_FULL (1 << 5) |
defines | #define A3700_SPI_RFIFO_EMPTY (1 << 4) |
defines | #define A3700_SPI_WFIFO_RDY (1 << 3) |
defines | #define A3700_SPI_RFIFO_RDY (1 << 2) |
defines | #define A3700_SPI_XFER_RDY (1 << 1) |
defines | #define A3700_SPI_XFER_DONE (1 << 0) |
defines | #define A3700_SPI_WFIFO_THRS (1 << 28) |
defines | #define A3700_SPI_RFIFO_THRS (1 << 24) |
defines | #define A3700_SPI_AUTO_CS (1 << 20) |
defines | #define A3700_SPI_DMA_RD_EN (1 << 18) |
defines | #define A3700_SPI_FIFO_MODE (1 << 17) |
defines | #define A3700_SPI_SRST (1 << 16) |
defines | #define A3700_SPI_XFER_START (1 << 15) |
defines | #define A3700_SPI_XFER_STOP (1 << 14) |
defines | #define A3700_SPI_INST_PIN (1 << 13) |
defines | #define A3700_SPI_ADDR_PIN (1 << 12) |
defines | #define A3700_SPI_FIFO_FLUSH (1 << 9) |
defines | #define A3700_SPI_RW_EN (1 << 8) |
defines | #define A3700_SPI_CLK_POL (1 << 7) |
defines | #define A3700_SPI_CLK_PHA (1 << 6) |
defines | #define A3700_SPI_BYTE_LEN (1 << 5) |
defines | #define A3700_SPI_CLK_PRESCALE (1 << 0) |
defines | #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) |
defines |
#define A3700_SPI_WFIFO_THRS_BIT 28 |
defines | #define A3700_SPI_RFIFO_THRS_BIT 24 |
defines | #define A3700_SPI_FIFO_THRS_MASK 0x7 |
defines |
#define A3700_SPI_DATA_PIN_BIT 10 |
defines | #define A3700_SPI_DATA_PIN_MASK 0x3 |
defines | #define A3700_SPI_DUMMY_CNT_BIT 12 |
defines | #define A3700_SPI_DUMMY_CNT_MASK 0x7 |
defines | #define A3700_SPI_RMODE_CNT_BIT 8 |
defines | #define A3700_SPI_RMODE_CNT_MASK 0x3 |
defines | #define A3700_SPI_ADDR_CNT_BIT 4 |
defines | #define A3700_SPI_ADDR_CNT_MASK 0x7 |
defines | #define A3700_SPI_INSTR_CNT_BIT 0 |
defines | #define A3700_SPI_INSTR_CNT_MASK 0x3 |
defines | #define HAS_FIFO (1 << 0) |
defines | #define AUTO_CS (1 << 1) |
defines | #define XFER_POLL (1 << 2) |
structs | struct a3700_spi_initdata {
unsigned int cs_num;
unsigned int mode;
unsigned int bits_per_word_mask;
unsigned int instr_cnt;
unsigned int addr_cnt;
}; |
structs | struct a3700_spi_status {
bool cs_active;
bool last_xfer;
const u8 *tx_buf;
u8 *rx_buf;
unsigned int buf_len;
unsigned int byte_len;
unsigned int wait_mask;
struct completion done;
}; |
structs | struct a3700_max_hdr_cnt {
unsigned int addr_cnt;
unsigned int instr_cnt;
unsigned int hdr_cnt; /* addr_cnt + instr_cnt = hdr_cnt */
}; |
structs | struct a3700_spi {
struct spi_master *master;
void __iomem *base;
struct clk *clk;
unsigned int input_clk_freq;
unsigned int max_clk_freq;
unsigned int irq;
unsigned int flags;
enum a3700_spi_pin_mode pin_mode;
struct a3700_max_hdr_cnt max_cnt;
struct a3700_sp... |
functions | u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
{
return readl(a3700_spi->base + offset);
} |
functions | void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
{
writel(data, a3700_spi->base + offset);
} |
functions | void a3700_spi_auto_cs_set(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (a3700_spi->flags & AUTO_CS)
val |= A3700_SPI_AUTO_CS;
else
val &= ~A3700_SPI_AUTO_CS;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
} |
functions | void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
val |= (A3700_SPI_EN << cs);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
a3700_spi->status.cs_active = true;
} |
functions | void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
unsigned int cs)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
val &= ~(A3700_SPI_EN << cs);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
a3700_spi->status.cs_active = false;
} |
functions | int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi)
{
u32 val;
if (a3700_spi->pin_mode > A3700_SPI_SGL_PIN)
return -EINVAL;
/*
* Only support single mode: 1x_instr_pin,
* 1x_addr_pin and 1x_data_pin.
*/
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_... |
functions | void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (a3700_spi->flags & HAS_FIFO)
val |= A3700_SPI_FIFO_MODE;
else
val &= ~A3700_SPI_FIFO_MODE;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
} |
functions | int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
{
int timeout = A3700_SPI_TIMEOUT;
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_FIFO_FLUSH;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
while (--timeout) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (!... |
functions | void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
unsigned int mode_bits)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (mode_bits & SPI_CPOL)
val |= A3700_SPI_CLK_POL;
if (mode_bits & SPI_CPHA)
val |= A3700_SPI_CLK_PHA;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
} |
functions | int a3700_spi_baudrate_set(struct a3700_spi *a3700_spi,
unsigned int speed_hz)
{
u32 val;
u32 prescale;
/* calculate Prescaler = (spi_input_freq / spi_max_freq) */
prescale = a3700_spi->input_clk_freq / a3700_spi->max_clk_freq;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val = val & ~A3700_SPI_CLK_PRES... |
functions | void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (len == 4)
val |= A3700_SPI_BYTE_LEN;
else
val &= ~A3700_SPI_BYTE_LEN;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
a3700_spi->status.byte_len = len;
} |
functions | void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
unsigned int bytes)
{
u32 val;
if (a3700_spi->flags & HAS_FIFO) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
val &= ~(A3700_SPI_... |
functions | int a3700_spi_init(struct a3700_spi *a3700_spi)
{
struct spi_master *master = a3700_spi->master;
u32 val;
int ret = 0;
int i;
/* Reset SPI unit */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_SRST;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
for (i = 0; i < A3700_SPI_TIMEOUT; ... |
functions | bool a3700_spi_wait_ctl_bit_set(struct spi_device *spi)
{
struct a3700_spi *a3700_spi;
int i;
u32 val;
a3700_spi = spi_master_get_devdata(spi->master);
for (i = 0; i < A3700_SPI_TIMEOUT; i++) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
if (val & a3700_spi->status.wait_mask)
break;
udelay(1);
... |
functions | irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
{
struct spi_master *master = dev_id;
struct a3700_spi *a3700_spi;
u32 cause;
a3700_spi = spi_master_get_devdata(master);
/* Get interrupt causes */
cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
/* mask and acknowledge the SPI interrupts */
spi... |
functions | bool a3700_spi_wait_completion(struct spi_device *spi)
{
struct a3700_spi *a3700_spi;
unsigned int timeout;
unsigned int ctrl_reg;
a3700_spi = spi_master_get_devdata(spi->master);
/* SPI interrupt is edge-triggered, which means a interrupt will
* be generated only when detecting specific status bit changed
... |
functions | bool a3700_spi_transfer_wait(struct spi_device *spi,
unsigned int bit_mask)
{
struct a3700_spi *a3700_spi;
a3700_spi = spi_master_get_devdata(spi->master);
a3700_spi->status.wait_mask = bit_mask;
return a3700_spi->spi_wait_xfer(spi);
} |
functions | int a3700_spi_transfer_setup(struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi;
unsigned int byte_len;
int ret = 0;
a3700_spi = spi_master_get_devdata(spi->master);
if (!(a3700_spi->flags & AUTO_CS) && !a3700_spi->status.cs_active) {
/* Set SPI clock prescaler */
ret = a3700_s... |
functions | int a3700_spi_transfer_start_legacy(struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi;
a3700_spi = spi_master_get_devdata(spi->master);
a3700_spi->status.tx_buf = xfer->tx_buf;
a3700_spi->status.rx_buf = xfer->rx_buf;
a3700_spi->status.buf_len = xfer->len;
if (!a3700_spi_trans... |
functions | int a3700_spi_read_data(struct a3700_spi *a3700_spi)
{
struct a3700_spi_status *status = &a3700_spi->status;
u32 val;
if (status->buf_len % status->byte_len)
return -EINVAL;
/* Read bytes from data in register */
val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
if (status->byte_len == 4) {
status->rx_bu... |
functions | int a3700_spi_write_data(struct a3700_spi *a3700_spi)
{
struct a3700_spi_status *status = &a3700_spi->status;
u32 val;
if (status->buf_len % status->byte_len)
return -EINVAL;
/* Write bytes from data out register */
val = 0;
if (status->byte_len == 4) {
val |= status->tx_buf[0] << 24;
val |= status->tx_bu... |
functions | int a3700_spi_do_transfer_legacy(struct spi_device *spi)
{
struct a3700_spi *a3700_spi;
int ret = 0;
a3700_spi = spi_master_get_devdata(spi->master);
while (a3700_spi->status.buf_len) {
if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
dev_err(&spi->dev, "wait transfer ready timed out\n");
ret = -E... |
functions | int a3700_spi_transfer_finish_legacy(struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi;
a3700_spi = spi_master_get_devdata(spi->master);
if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
dev_err(&spi->dev, "wait transfer ready timed out\n");
return -ETIMEDOUT;
} |
functions | void a3700_spi_header_set(struct a3700_spi *a3700_spi)
{
struct a3700_spi_status *status = &a3700_spi->status;
struct a3700_max_hdr_cnt *max_cnt = &a3700_spi->max_cnt;
unsigned int instr_cnt, addr_cnt;
u32 val;
instr_cnt = addr_cnt = 0;
/* Clear the header registers */
spireg_write(a3700_spi, A3700_SPI_IF_INST... |
functions | int a3700_spi_transfer_start_non_legacy(struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi;
u32 val;
a3700_spi = spi_master_get_devdata(spi->master);
a3700_spi->status.tx_buf = xfer->tx_buf;
a3700_spi->status.rx_buf = xfer->rx_buf;
a3700_spi->status.buf_len = xfer->len;
/* Tra... |
functions | else if (xfer->tx_buf) {
/* Start Write transfer */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
} |
functions | int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
{
u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
return (val & A3700_SPI_RFIFO_EMPTY);
} |
functions | int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
{
struct a3700_spi_status *status = &a3700_spi->status;
u32 val;
if (status->buf_len % status->byte_len)
return -EINVAL;
while (!a3700_is_rfifo_empty(a3700_spi) && status->buf_len) {
/* Read bytes from data in register */
val = spireg_read(a3700_spi, A370... |
functions | int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
return (val & A3700_SPI_WFIFO_FULL);
} |
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