type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
functions | __devinit gxt4500_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int err;
unsigned long reg_phys, fb_phys;
struct gxt4500_par *par;
struct fb_info *info;
struct fb_var_screeninfo var;
enum gxt_cards cardtype;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "gxt4500: canno... |
functions | __devexit gxt4500_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct gxt4500_par *par;
if (!info)
return;
par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
iounmap(par->regs);
iounmap(info->screen_base);
release_mem_region(pci_resource_start(pdev, ... |
functions | __devinit gxt4500_init(void)
{
#ifndef MODULE
if (fb_get_options("gxt4500", &mode_option))
return -ENODEV;
#endif
return pci_register_driver(&gxt4500_driver);
} |
functions | __exit gxt4500_exit(void)
{
pci_unregister_driver(&gxt4500_driver);
} |
includes |
#include <linux/kernel.h> |
includes | #include <linux/init.h> |
includes | #include <linux/module.h> |
includes | #include <linux/string.h> |
includes | #include <linux/slab.h> |
includes | #include <linux/delay.h> |
defines |
#define dprintk(arg...) do { \ |
structs | struct s5h1411_state {
struct i2c_adapter *i2c;
/* */
const struct s5h1411_config *config;
struct dvb_frontend frontend;
fe_modulation_t current_modulation;
unsigned int first_tune:1;
u32 current_frequency;
int if_freq;
u8 inversion;
}; |
functions | int s5h1411_writereg(struct s5h1411_state *state,
u8 addr, u8 reg, u16 data)
{
int ret;
u8 buf[] = { reg, data >> 8, data & 0xff } |
functions | u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
{
int ret;
u8 b0[] = { reg } |
functions | int s5h1411_softreset(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
return 0;
} |
functions | int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d KHz)\n", __func__, KHz);
switch (KHz) {
case 3250:
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
s5h1411_... |
functions | int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, mode);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
switch (mode) {
case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
val |= 0x0000... |
functions | int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, inversion);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
if (inversion == 1)
val |= 0x1000; /* */
state->inver... |
functions | int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, serial);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
if (serial == 1)
val |= 0x100;
return s5h1411_writereg(state, S5H1411_I2C_TO... |
functions | int s5h1411_enable_modulation(struct dvb_frontend *fe,
fe_modulation_t m)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(0x%08x)\n", __func__, m);
if ((state->first_tune == 0) && (m == state->current_modulation)) {
dprintk("%s() Already at desired modulation. Skipping...\n",
__fun... |
functions | int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
else
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
} |
functions | int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 val;
dprintk("%s(%d)\n", __func__, enable);
val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
if (enable)
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
val | 0x0... |
functions | int s5h1411_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(%d)\n", __func__, enable);
if (enable)
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
else {
s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
s5h1411_softreset(fe... |
functions | int s5h1411_sleep(struct dvb_frontend *fe)
{
return s5h1411_set_powerstate(fe, 1);
} |
functions | int s5h1411_register_reset(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s()\n", __func__);
return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
} |
functions | int s5h1411_set_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s5h1411_state *state = fe->demodulator_priv;
dprintk("%s(frequency=%d)\n", __func__, p->frequency);
s5h1411_softreset(fe);
state->current_frequency = p->frequency;
s5h1411_enable_modulation(... |
functions | int s5h1411_init(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
int i;
dprintk("%s()\n", __func__);
s5h1411_set_powerstate(fe, 0);
s5h1411_register_reset(fe);
for (i = 0; i < ARRAY_SIZE(init_tab); i++)
s5h1411_writereg(state, init_tab[i].addr,
init_tab[i].reg,
init_tab[i... |
functions | int s5h1411_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 reg;
u32 tuner_status = 0;
*status = 0;
/* */
switch (state->current_modulation) {
case QAM_64:
case QAM_256:
reg = s5h1411_readreg(state... |
functions | int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
if (v < qam256_snr_tab[i].val) {
*snr = qam256_snr_tab[i].data;
ret = 0;
break;
} |
functions | int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
if (v < qam64_snr_tab[i].val) {
*snr = qam64_snr_tab[i].data;
ret = 0;
break;
} |
functions | int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
{
int i, ret = -EINVAL;
dprintk("%s()\n", __func__);
for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
if (v > vsb_snr_tab[i].val) {
*snr = vsb_snr_tab[i].data;
ret = 0;
break;
} |
functions | int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct s5h1411_state *state = fe->demodulator_priv;
u16 reg;
dprintk("%s()\n", __func__);
switch (state->current_modulation) {
case QAM_64:
reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
return s5h1411_qam64_lookup_snr(fe, snr, reg);
case Q... |
functions | int s5h1411_read_signal_strength(struct dvb_frontend *fe,
u16 *signal_strength)
{
/*
*/
u16 snr;
u... |
functions | int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct s5h1411_state *state = fe->demodulator_priv;
*ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
return 0;
} |
functions | int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
{
return s5h1411_read_ucblocks(fe, ber);
} |
functions | int s5h1411_get_frontend(struct dvb_frontend *fe)
{
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct s5h1411_state *state = fe->demodulator_priv;
p->frequency = state->current_frequency;
p->modulation = state->current_modulation;
return 0;
} |
functions | int s5h1411_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
} |
functions | void s5h1411_release(struct dvb_frontend *fe)
{
struct s5h1411_state *state = fe->demodulator_priv;
kfree(state);
} |
includes | #include <linux/delay.h> |
includes | #include <linux/sched.h> |
defines | #define SOURCEFILE_NAME "hpios.c" |
functions | void hpios_delay_micro_seconds(u32 num_micro_sec)
{
if ((usecs_to_jiffies(num_micro_sec) > 1) && !in_interrupt()) {
/* */
schedule_timeout_uninterruptible(usecs_to_jiffies
(num_micro_sec));
} |
functions | u16 hpios_locked_mem_alloc(struct consistent_dma_area *p_mem_area, u32 size,
struct pci_dev *pdev)
{
/* */
p_mem_area->vaddr =
dma_alloc_coherent(&pdev->dev, size, &p_mem_area->dma_handle,
GFP_DMA32 | GFP_KERNEL);
if (p_mem_area->vaddr) {
HPI_DEBUG_LOG(DEBU... |
functions | u16 hpios_locked_mem_free(struct consistent_dma_area *p_mem_area)
{
if (p_mem_area->size) {
dma_free_coherent(p_mem_area->pdev, p_mem_area->size,
p_mem_area->vaddr, p_mem_area->dma_handle);
HPI_DEBUG_LOG(DEBUG, "freed %lu bytes, dma 0x%x vma %p\n",
(unsigned long)p_mem_area->size,
(unsigned int)p_mem_area... |
defines |
#define TEST_MAIN |
functions | int
check_result (impl_t *impl, const CHAR *s, int c, const CHAR *exp_res)
{
CHAR *res = CALL (impl, s, c);
if (res != exp_res)
{
error (0, 0, "Wrong result in function %s %#x %p %p", impl->name,
c, res, exp_res);
ret = 1;
return -1;
} |
functions | void
do_one_test (impl_t *impl, const CHAR *s, int c, const CHAR *exp_res)
{
if (check_result (impl, s, c, exp_res) < 0)
return;
} |
functions | void
do_random_tests (void)
{
size_t i, j, n, align, pos, len;
int seek_char;
CHAR *result;
UCHAR *p = (UCHAR *) (buf1 + page_size - 512 * sizeof (CHAR));
for (n = 0; n < ITERATIONS; n++)
{
/* For wcschr: align here means align not in bytes, but in wchar_ts,
in bytes it will equal to align * (siz... |
functions | void
check1 (void)
{
char s[] __attribute__((aligned(16))) = "\xff";
char c = '\xfe';
char *exp_result = stupid_STRCHR (s, c);
FOR_EACH_IMPL (impl, 0)
check_result (impl, s, c, exp_result);
} |
functions | int
test_main (void)
{
size_t i;
test_init ();
check1 ();
printf ("%20s", "");
FOR_EACH_IMPL (impl, 0)
printf ("\t%s", impl->name);
putchar ('\n');
for (i = 1; i < 8; ++i)
{
do_test (0, 16 << i, 2048, SMALL_CHAR, MIDDLE_CHAR);
do_test (i, 16 << i, 2048, SMALL_CHAR, MIDDLE_CHAR);
... |
defines |
#define IIR_8k5_numStages 8 |
functions | int sha384_init(hash_state * md)
{
LTC_ARGCHK(md != NULL);
md->sha512.curlen = 0;
md->sha512.length = 0;
md->sha512.state[0] = CONST64(0xcbbb9d5dc1059ed8);
md->sha512.state[1] = CONST64(0x629a292a367cd507);
md->sha512.state[2] = CONST64(0x9159015a3070dd17);
md->sha512.state[3] = CO... |
functions | int sha384_done(hash_state * md, unsigned char *out)
{
unsigned char buf[64];
LTC_ARGCHK(md != NULL);
LTC_ARGCHK(out != NULL);
if (md->sha512.curlen >= sizeof(md->sha512.buf)) {
return CRYPT_INVALID_ARG;
} |
functions | int sha384_test(void)
{
#ifndef LTC_TEST
return CRYPT_NOP;
#else
static const struct {
char *msg;
unsigned char hash[48];
} |
defines |
#define DATA_LENGTH 128 |
functions | int Xil_TestDCacheRange(void)
{
int Index;
int Status;
u32 Value;
xil_printf("-- Cache Range Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0xA0A00505;
xil_printf(" initialize Data done:\r\n");
Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32));
xil_printf(" fl... |
functions | int Xil_TestDCacheAll(void)
{
int Index;
int Status;
u32 Value;
xil_printf("-- Cache All Test --\n\r");
for (Index = 0; Index < DATA_LENGTH; Index++)
Data[Index] = 0x50500A0A;
xil_printf(" initialize Data done:\r\n");
Xil_DCacheFlush();
xil_printf(" flush all done\r\n");
for (Index = 0; Index < ... |
functions | int Xil_TestICacheRange(void)
{
Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024);
Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024);
Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024);
xil_printf("-- Invalidate icache range done --\r\n");
return 0;
} |
functions | int Xil_TestICacheAll(void)
{
Xil_ICacheInvalidate();
xil_printf("-- Invalidate icache all done --\r\n");
return 0;
} |
functions | uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
{
uint32_t u32Src;
uint32_t u32EPWMClockSrc;
uint32_t u32NearestUnitTimeNsec;
uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU;
if(epwm == EPWM0)
{
u32Src = CLK->CLKSEL... |
functions | uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
uint32_t u32Src;
uint32_t u32EPWMClockSrc;
uint32_t i;
uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
if(epwm == EPWM0)
{
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Ms... |
functions | void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->CNTEN |= u32ChannelMask;
} |
functions | void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
{
uint32_t i;
for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
{
if(u32ChannelMask & (1UL << i))
{
(epwm)->PERIOD[i] = 0U;
} |
functions | void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->CNTEN &= ~u32ChannelMask;
} |
functions | void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
if(u32ChannelNum < 4U)
{
(epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U));
(epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
} |
functions | void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
{
if(u32ChannelNum < 4U)
{
(epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U));
} |
functions | int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt)
{
/* User can write only when PSCENn(n = 0 ~ 5) is 0 */
if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum))
return (-1);
if(u32ChannelNum < 4UL)
{
(epwm)->EADCPSC0 = (... |
functions | void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum);
} |
functions | void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
(epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
} |
functions | uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL);
} |
functions | void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
(epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
} |
functions | void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \
EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
} |
functions | void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
(epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
} |
functions | uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL);
} |
functions | void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
{
uint32_t i;
for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
{
if(u32ChannelMask & (1UL << i))
{
if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_E... |
functions | void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->CAPINEN |= u32ChannelMask;
(epwm)->CAPCTL |= u32ChannelMask;
} |
functions | void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->CAPINEN &= ~u32ChannelMask;
(epwm)->CAPCTL &= ~u32ChannelMask;
} |
functions | void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->POEN |= u32ChannelMask;
} |
functions | void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
{
(epwm)->POEN &= ~u32ChannelMask;
} |
functions | void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
{
uint32_t u32IsOddCh;
u32IsOddCh = u32ChannelNum & 0x1U;
(epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1... |
functions | void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U));
} |
functions | void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
{
/* every two channels share the same setting */
(epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
(epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
} |
functions | void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
{
/* every two channels shares the same setting */
(epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk;
} |
functions | void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
} |
functions | void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
} |
functions | void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(epwm)->CAPIF = (u32Edge << u32ChannelNum);
} |
functions | uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
(((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
} |
functions | void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
{
(epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
} |
functions | void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
} |
functions | void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
} |
functions | uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
} |
functions | void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
{
(epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
} |
functions | void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
{
(epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
} |
functions | void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
{
(epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
} |
functions | uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
{
return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
} |
functions | void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
{
(epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
} |
functions | void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
} |
functions | void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum);
} |
functions | uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
{
return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
} |
functions | void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
} |
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