type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
defines | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
functions | void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------... |
functions | void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
if (SetSysClock_PLL_HSE(0) == 0)
#endi... |
functions | uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding... |
functions | uint8_t SetSysClock_PLL_HSI(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system fr... |
includes |
#include <linux/kernel.h> |
includes | #include <linux/platform_device.h> |
includes | #include <linux/dma-mapping.h> |
includes | #include <mach/kgsl.h> |
includes | #include <linux/regulator/machine.h> |
includes | #include <linux/init.h> |
includes | #include <linux/irq.h> |
includes | #include <linux/notifier.h> |
includes | #include <mach/irqs.h> |
includes | #include <mach/msm_iomap.h> |
includes | #include <mach/board.h> |
includes | #include <mach/dma.h> |
includes | #include <mach/dal_axi.h> |
includes | #include <asm/mach/flash.h> |
includes | #include <asm/hardware/gic.h> |
includes | #include <asm/hardware/cache-l2x0.h> |
includes | #include <asm/mach/mmc.h> |
includes | #include <asm/cacheflush.h> |
includes | #include <mach/rpc_hsusb.h> |
includes | #include <mach/socinfo.h> |
defines | #define MSM_GSBI0_PHYS 0xA1200000 |
defines | #define MSM_GSBI1_PHYS 0xA1300000 |
defines | #define MSM_GSBI0_QUP_PHYS (MSM_GSBI0_PHYS + 0x80000) |
defines | #define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000) |
defines |
#define MSM_HSUSB_PHYS 0xA0800000 |
defines |
#define MSM_UART1DM_PHYS 0xA0200000 |
defines |
#define MSM_UART2DM_PHYS 0xA0300000 |
defines |
#define MSM_NAND_PHYS 0xA0A00000 |
defines | #define MSM_NANDC01_PHYS 0xA0A40000 |
defines | #define MSM_NANDC10_PHYS 0xA0A80000 |
defines | #define MSM_NANDC11_PHYS 0xA0AC0000 |
defines | #define EBI2_REG_BASE 0xA0D00000 |
defines |
#define MSM_SDC1_BASE 0xA0400000 |
defines | #define MSM_SDC2_BASE 0xA0500000 |
defines | #define MSM_SDC3_BASE 0xA0600000 |
defines | #define MSM_SDC4_BASE 0xA0700000 |
defines |
#define MDP_BASE 0xAA200000 |
defines | #define MIPI_DSI_HW_BASE 0xA1100000 |
defines |
#define PERPH_WEB_BLOCK_ADDR (0xA9D00040) |
defines | #define PDM0_CTL_OFFSET (0x04) |
defines | #define SIZE_8B (0x08) |
functions | __init msm_pm_register_irqs(void)
{
if (cpu_is_msm8625())
msm_pm_set_irq_extns(&msm8625_pm_irq_calls);
else
msm_pm_set_irq_extns(&msm7x27a_pm_irq_calls);
} |
functions | __init msm8x25_spm_device_init(void)
{
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
} |
functions | __init msm7x25a_kgsl_3d0_init(void)
{
if (cpu_is_msm7x25a() || cpu_is_msm7x25aa() || cpu_is_msm7x25ab()) {
kgsl_3d0_pdata.num_levels = 2;
kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 133330000;
kgsl_3d0_pdata.pwrlevel[0].bus_freq = 160000000;
kgsl_3d0_pdata.pwrlevel[1].gpu_freq = 96000000;
kgsl_3d0_pdata.pwrlevel[1... |
functions | __init msm8x25_kgsl_3d0_init(void)
{
if (cpu_is_msm8625()) {
kgsl_3d0_pdata.idle_timeout = HZ/5;
kgsl_3d0_pdata.strtstp_sleepwake = false;
/* 8x25 supports a higher GPU frequency */
kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 320000000;
kgsl_3d0_pdata.pwrlevel[0].bus_freq = 200000000;
} |
functions | __init msm_register_device(struct platform_device *pdev, void *data)
{
int ret;
pdev->dev.platform_data = data;
ret = platform_device_register(pdev);
if (ret)
dev_err(&pdev->dev,
"%s: platform_device_register() failed = %d\n",
__func__, ret);
} |
functions | __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
{
struct platform_device *pdev;
if (controller < 1 || controller > 4)
return -EINVAL;
if (cpu_is_msm8625())
pdev = msm8625_sdcc_devices[controller-1];
else
pdev = msm_sdcc_devices[controller-1];
pdev->dev.platform_data = plat;
r... |
functions | int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat)
{
struct platform_device *pdev;
if (cpu_is_msm8625())
pdev = msm8625_host_devices[host];
else
pdev = msm_host_devices[host];
if (!pdev)
return -ENODEV;
pdev->dev.platform_data = plat;
return platform_device_register(pdev);
} |
functions | __init msm_fb_register_device(char *name, void *data)
{
if (!strncmp(name, "mdp", 3)) {
if (cpu_is_msm8625())
msm_register_device(&msm8625_mdp_device, data);
else
msm_register_device(&msm_mdp_device, data);
} |
functions | __init msm8625_cpu_id(void)
{
int raw_id, cpu;
raw_id = socinfo_get_raw_id();
switch (raw_id) {
/* Part number for 1GHz part */
case 0x770:
case 0x771:
case 0x77C:
case 0x780:
case 0x8D0:
cpu = MSM8625;
break;
/* Part number for 1.2GHz part */
case 0x773:
case 0x774:
case 0x781:
case 0x8D1:
cpu = M... |
functions | __init msm7x2x_misc_init(void)
{
if (machine_is_msm8625_rumi3()) {
msm_clock_init(&msm8625_dummy_clock_init_data);
return 0;
} |
functions | __init msm7x27x_cache_init(void)
{
int aux_ctrl = 0;
int pctrl = 0;
/* Way Size 010(0x2) 32KB */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
(0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
(0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT);
if (cpu_is_msm8625()) {
/* Way Size 011(0x3) 64KB */
au... |
functions | __init msm7x27x_cache_init(void){ return 0; } |
functions | __init msm_common_io_init(void)
{
msm_map_common_io();
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
msm7x27x_cache_init();
} |
functions | __init msm8625_init_irq(void)
{
msm_gic_irq_extn_init();
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
} |
functions | __init msm8625_map_io(void)
{
msm_map_msm8625_io();
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
msm7x27x_cache_init();
} |
functions | int msm7627a_init_gpio(void)
{
if (cpu_is_msm8625())
platform_device_register(&msm8625_device_gpio);
else
platform_device_register(&msm_device_gpio);
return 0;
} |
functions | int msm7627a_panic_handler(struct notifier_block *this,
unsigned long event, void *ptr)
{
flush_cache_all();
outer_flush_all();
return NOTIFY_DONE;
} |
functions | __init panic_register(void)
{
atomic_notifier_chain_register(&panic_notifier_list,
&panic_handler);
return 0;
} |
includes |
#include <linux/kernel.h> |
includes | #include <linux/module.h> |
includes | #include <linux/platform_device.h> |
includes | #include <linux/pci.h> |
functions | u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr)
{
u32 base, offset;
if (is_mt7663(&dev->mt76)) {
base = addr & MT7663_MCU_PCIE_REMAP_2_BASE;
offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET;
} |
functions | void
mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
mt7615_irq_enable(dev, MT_INT_RX_DONE(q));
} |
functions | irqreturn_t mt7615_irq_handler(int irq, void *dev_instance)
{
struct mt7615_dev *dev = dev_instance;
mt76_wr(dev, MT_INT_MASK_CSR, 0);
if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
return IRQ_NONE;
tasklet_schedule(&dev->irq_tasklet);
return IRQ_HANDLED;
} |
functions | void mt7615_irq_tasklet(struct tasklet_struct *t)
{
struct mt7615_dev *dev = from_tasklet(dev, t, irq_tasklet);
u32 intr, mask = 0, tx_mcu_mask = mt7615_tx_mcu_int_mask(dev);
u32 mcu_int;
mt76_wr(dev, MT_INT_MASK_CSR, 0);
intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
intr &= dev->mt76.mmio.irqmask;
mt76_wr(dev, MT_I... |
functions | u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)
{
if (addr < 0x100000)
return addr;
return mt7615_reg_map(dev, addr);
} |
functions | u32 mt7615_rr(struct mt76_dev *mdev, u32 offset)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
return dev->bus_ops->rr(mdev, addr);
} |
functions | void mt7615_wr(struct mt76_dev *mdev, u32 offset, u32 val)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
dev->bus_ops->wr(mdev, addr, val);
} |
functions | u32 mt7615_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
{
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
u32 addr = __mt7615_reg_addr(dev, offset);
return dev->bus_ops->rmw(mdev, addr, mask, val);
} |
functions | int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
int irq, const u32 *map)
{
static const struct mt76_driver_ops drv_ops = {
/* txwi_size = txd size + txp size */
.txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common),
.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
.survey... |
functions | __init mt7615_init(void)
{
int ret;
ret = pci_register_driver(&mt7615_pci_driver);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_MT7622_WMAC)) {
ret = platform_driver_register(&mt7622_wmac_driver);
if (ret)
pci_unregister_driver(&mt7615_pci_driver);
} |
functions | __exit mt7615_exit(void)
{
if (IS_ENABLED(CONFIG_MT7622_WMAC))
platform_driver_unregister(&mt7622_wmac_driver);
pci_unregister_driver(&mt7615_pci_driver);
} |
includes | #include <linux/init.h> |
includes | #include <linux/suspend.h> |
includes | #include <linux/errno.h> |
includes | #include <linux/time.h> |
includes |
#include <asm/hardware.h> |
includes | #include <asm/memory.h> |
includes | #include <asm/system.h> |
includes | #include <asm/mach/time.h> |
defines |
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
defines | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] |
functions | int sa11x0_pm_enter(suspend_state_t state)
{
unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE];
struct timespec delta, rtc;
if (state != PM_SUSPEND_MEM)
return -EINVAL;
/* preserve current time */
rtc.tv_sec = RCNR;
rtc.tv_nsec = 0;
save_time_delta(&delta, &rtc);
gpio = GPLR;
/* save vital registers */
SAV... |
functions | long sleep_phys_sp(void *sp)
{
return virt_to_phys(sp);
} |
functions | int sa11x0_pm_prepare(suspend_state_t state)
{
return 0;
} |
functions | int sa11x0_pm_finish(suspend_state_t state)
{
return 0;
} |
functions | __init sa11x0_pm_init(void)
{
pm_set_ops(&sa11x0_pm_ops);
return 0;
} |
includes |
#include <common.h> |
includes | #include <div64.h> |
includes | #include <netdev.h> |
includes | #include <asm/io.h> |
includes | #include <asm/arch/imx-regs.h> |
includes | #include <asm/arch/imx25-pinmux.h> |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.