type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
includes | #include <asm/arch/clock.h> |
includes | #include <fsl_esdhc.h> |
functions | int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
& CC... |
functions | ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
} |
functions | ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_mpllclk();
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
return f... |
functions | ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_armclk();
ulong div;
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
return fref / div;
} |
functions | ulong imx_get_ipgclk(void)
{
return imx_get_ahbclk() / 2;
} |
functions | ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = imx_get_ahbclk();
ulong div;
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
return fref / div;
} |
functions | int mxc_get_clock(enum mxc_clock clk)
{
if (clk >= MXC_CLK_NUM)
return -1;
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_AHB_CLK:
return imx_get_ahbclk();
case MXC_IPG_CLK:
case MXC_CSPI_CLK:
case MXC_FEC_CLK:
return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
} |
functions | u32 get_cpu_rev(void)
{
u32 srev;
u32 system_rev = 0x25000;
/* read SREV register from IIM module */
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
srev = readl(&iim->iim_srev);
switch (srev) {
case 0x00:
system_rev |= CHIP_REV_1_0;
break;
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
case 0... |
functions | int print_cpuinfo(void)
{
char buf[32];
u32 cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
((cpurev & 0x8000) ? " unknown" : ""),
strmhz(buf, imx_get_armclk()));
printf("Reset cause: %s\n\n", get_reset_cause());
return 0;
} |
functions | void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
} |
functions | int cpu_eth_init(bd_t *bis)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val = readl(&ccm->cgr0);
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
} |
functions | int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
} |
functions | int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
} |
functions | void mx25_uart1_init_pins(void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 inpadctl;
u32 outpadctl;
u32 muxmode0;
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
muxmode0 = MX25_PIN_MUX_MODE(0);
/*
* set up input pins with hy... |
functions | void mx25_fec_init_pins(void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 inpadctl_100kpd;
u32 inpadctl_22kpu;
u32 outpadctl;
u32 muxmode0;
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
muxmode0 = MX25_PIN_MUX_MODE(0);
inpadc... |
functions | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
} |
includes |
#include <stdio.h> |
includes |
#include <ac/string.h> |
includes | #include <ac/socket.h> |
functions | int
monitor_back_operational(
Operation *op,
SlapReply *rs )
{
Attribute **ap;
assert( rs->sr_entry != NULL );
for ( ap = &rs->sr_operational_attrs; *ap; ap = &(*ap)->a_next ) {
if ( (*ap)->a_desc == slap_schema.si_ad_hasSubordinates ) {
break;
} |
includes | #include <linux/types.h> |
includes | #include <linux/interrupt.h> |
includes | #include <linux/irq.h> |
includes | #include <linux/smp.h> |
includes | #include <linux/time.h> |
includes | #include <linux/clockchips.h> |
includes |
#include <asm/i8253.h> |
includes | #include <asm/sni.h> |
includes | #include <asm/time.h> |
includes | #include <asm-generic/rtc.h> |
defines |
#define SNI_CLOCK_TICK_RATE 3686400 |
defines | #define SNI_COUNTER2_DIV 64 |
defines | #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) |
defines |
#define SNI_8254_TICK_RATE 1193182UL |
defines |
#define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255) |
functions | void a20r_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
wmb();
*(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV;
wmb();
*(volatile u8 *)(A20R_PT_CLOC... |
functions | irqreturn_t a20r_interrupt(int irq, void *dev_id)
{
struct clock_event_device *cd = dev_id;
*(volatile u8 *)A20R_PT_TIM0_ACK = 0;
wmb();
cd->event_handler(cd);
return IRQ_HANDLED;
} |
functions | __init sni_a20r_timer_setup(void)
{
struct clock_event_device *cd = &a20r_clockevent_device;
struct irqaction *action = &a20r_irqaction;
unsigned int cpu = smp_processor_id();
cd->cpumask = cpumask_of(cpu);
clockevents_register_device(cd);
action->dev_id = cd;
setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irq... |
functions | long dosample(void)
{
u32 ct0, ct1;
volatile u8 msb;
/* Start the counter. */
outb_p(0x34, 0x43);
outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
/* Get initial counter invariant */
ct0 = read_c0_count();
/* Latch and spin until top byte of counter0 is zero */
do {
... |
functions | __init plat_time_init(void)
{
unsigned long r4k_ticks[3];
unsigned long r4k_tick;
/*
* Figure out the r4k offset, the algorithm is very simple and works in
* _all_ cases as long as the 8254 counter register itself works ok (as
* an interrupt driving timer it does not because of bug, this is why
* we are usi... |
functions | void read_persistent_clock(struct timespec *ts)
{
ts->tv_sec = -1;
ts->tv_nsec = 0;
} |
includes | #include <linux/export.h> |
includes | #include <linux/init.h> |
includes | #include <linux/pci.h> |
includes | #include <linux/acpi.h> |
includes |
#include <linux/io.h> |
includes | #include <asm/io_apic.h> |
includes | #include <asm/pci_x86.h> |
includes |
#include <asm/xen/hypervisor.h> |
includes |
#include <xen/features.h> |
includes | #include <xen/events.h> |
includes | #include <asm/xen/pci.h> |
includes | #include <asm/xen/cpuid.h> |
includes | #include <asm/apic.h> |
includes | #include <asm/acpi.h> |
includes | #include <asm/i8259.h> |
includes | #include <linux/msi.h> |
includes | #include <asm/msidef.h> |
defines |
#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \ |
defines | #define xen_initdom_setup_msi_irqs NULL |
defines | #define xen_initdom_restore_msi_irqs NULL |
structs | struct xen_msi_ops {
int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
void (*teardown_msi_irqs)(struct pci_dev *dev);
}; |
structs | struct xen_device_domain_owner {
domid_t domain;
struct pci_dev *dev;
struct list_head list;
}; |
functions | int xen_pcifront_enable_irq(struct pci_dev *dev)
{
int rc;
int share = 1;
int pirq;
u8 gsi;
rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
if (rc < 0) {
dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
rc);
return rc;
} |
functions | int xen_register_pirq(u32 gsi, int triggering, bool set_pirq)
{
int rc, pirq = -1, irq;
struct physdev_map_pirq map_irq;
int shareable = 0;
char *name;
irq = xen_irq_from_gsi(gsi);
if (irq > 0)
return irq;
if (set_pirq)
pirq = gsi;
map_irq.domid = DOMID_SELF;
map_irq.type = MAP_PIRQ_TYPE_GSI;
map_irq.i... |
functions | int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
int trigger, int polarity)
{
if (!xen_hvm_domain())
return -1;
return xen_register_pirq(gsi, trigger,
false /* no mapping of GSI to PIRQ */);
} |
functions | int xen_register_gsi(u32 gsi, int triggering, int polarity)
{
int rc, irq;
struct physdev_setup_gsi setup_gsi;
if (!xen_pv_domain())
return -1;
printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
gsi, triggering, polarity);
irq = xen_register_pirq(gsi, triggering, true);
setup_gsi.gs... |
functions | int acpi_register_gsi_xen(struct device *dev, u32 gsi,
int trigger, int polarity)
{
return xen_register_gsi(gsi, trigger, polarity);
} |
functions | int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
int irq, ret, i;
struct msi_desc *msidesc;
int *v;
if (type == PCI_CAP_ID_MSI && nvec > 1)
return 1;
v = kcalloc(max(1, nvec), sizeof(int), GFP_KERNEL);
if (!v)
return -ENOMEM;
if (type == PCI_CAP_ID_MSIX)
ret = xen_pci_frontend_enable_ms... |
functions | void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
struct msi_msg *msg)
{
/* We set vector == 0 to tell the hypervisor we don't care about it,
* but we want a pirq setup instead.
* We use the dest_id field to pass the pirq that we want. */
msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID... |
functions | int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
int irq, pirq;
struct msi_desc *msidesc;
struct msi_msg msg;
if (type == PCI_CAP_ID_MSI && nvec > 1)
return 1;
for_each_pci_msi_entry(msidesc, dev) {
pirq = xen_allocate_pirq_msi(dev, msidesc);
if (pirq < 0) {
irq = -ENODEV;
goto e... |
functions | int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
int ret = 0;
struct msi_desc *msidesc;
for_each_pci_msi_entry(msidesc, dev) {
struct physdev_map_pirq map_irq;
domid_t domid;
domid = ret = xen_find_device_domain_owner(dev);
/* N.B. Casting int's -ENODEV to uint16_t results in 0xFFE... |
functions | else if (type == PCI_CAP_ID_MSIX) {
int pos;
unsigned long flags;
u32 table_offset, bir;
pos = dev->msix_cap;
pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
&table_offset);
bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
flags = pci_resource_flags(dev, bir);
if (!flags || (flags & I... |
functions | void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
{
int ret = 0;
if (pci_seg_supported) {
struct physdev_pci_device restore_ext;
restore_ext.seg = pci_domain_nr(dev->bus);
restore_ext.bus = dev->bus->number;
restore_ext.devfn = dev->devfn;
ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
&... |
functions | void xen_teardown_msi_irqs(struct pci_dev *dev)
{
struct msi_desc *msidesc;
int i;
for_each_pci_msi_entry(msidesc, dev) {
if (msidesc->irq) {
for (i = 0; i < msidesc->nvec_used; i++)
xen_destroy_irq(msidesc->irq + i);
} |
functions | void xen_pv_teardown_msi_irqs(struct pci_dev *dev)
{
struct msi_desc *msidesc = first_pci_msi_entry(dev);
if (msidesc->msi_attrib.is_msix)
xen_pci_frontend_disable_msix(dev);
else
xen_pci_frontend_disable_msi(dev);
xen_teardown_msi_irqs(dev);
} |
functions | int xen_msi_domain_alloc_irqs(struct irq_domain *domain,
struct device *dev, int nvec)
{
int type;
if (WARN_ON_ONCE(!dev_is_pci(dev)))
return -EINVAL;
if (first_msi_entry(dev)->msi_attrib.is_msix)
type = PCI_CAP_ID_MSIX;
else
type = PCI_CAP_ID_MSI;
return xen_msi_ops.setup_msi_irqs(to_pci_dev(de... |
functions | void xen_msi_domain_free_irqs(struct irq_domain *domain,
struct device *dev)
{
if (WARN_ON_ONCE(!dev_is_pci(dev)))
return;
xen_msi_ops.teardown_msi_irqs(to_pci_dev(dev));
} |
functions | void xen_setup_pci_msi(void)
{
if (xen_pv_domain()) {
if (xen_initial_domain()) {
xen_msi_ops.setup_msi_irqs = xen_initdom_setup_msi_irqs;
x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
} |
functions | void xen_setup_pci_msi(void) { } |
functions | __init pci_xen_init(void)
{
if (!xen_pv_domain() || xen_initial_domain())
return -ENODEV;
printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
pcibios_set_cache_line_size();
pcibios_enable_irq = xen_pcifront_enable_irq;
pcibios_disable_irq = NULL;
/* Keep ACPI out of the picture */
acpi_noirq_set()... |
functions | __init xen_hvm_msi_init(void)
{
if (!disable_apic) {
/*
* If hardware supports (x2)APIC virtualization (as indicated
* by hypervisor's leaf 4) then we don't need to use pirqs/
* event channels for MSI handling and instead use regular
* APIC processing
*/
uint32_t eax = cpuid_eax(xen_cpuid_base() + 4... |
functions | __init pci_xen_hvm_init(void)
{
if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
return 0;
#ifdef CONFIG_ACPI
/*
* We don't want to change the actual ACPI delivery model,
* just how GSIs get registered.
*/
__acpi_register_gsi = acpi_register_gsi_xen_hvm;
__acpi_unregister_gsi = NULL;
#endi... |
functions | __init pci_xen_initial_domain(void)
{
int irq;
xen_setup_pci_msi();
__acpi_register_gsi = acpi_register_gsi_xen;
__acpi_unregister_gsi = NULL;
/*
* Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here
* because we don't have a PIC and thus nr_legacy_irqs() is zero.
*/
for (irq = 0; irq < NR_IRQS_LEGACY; ... |
functions | int xen_find_device_domain_owner(struct pci_dev *dev)
{
struct xen_device_domain_owner *owner;
int domain = -ENODEV;
spin_lock(&dev_domain_list_spinlock);
owner = find_device(dev);
if (owner)
domain = owner->domain;
spin_unlock(&dev_domain_list_spinlock);
return domain;
} |
functions | int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
{
struct xen_device_domain_owner *owner;
owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
if (!owner)
return -ENODEV;
spin_lock(&dev_domain_list_spinlock);
if (find_device(dev)) {
spin_unlock(&dev_domain_list_spinl... |
functions | int xen_unregister_device_domain_owner(struct pci_dev *dev)
{
struct xen_device_domain_owner *owner;
spin_lock(&dev_domain_list_spinlock);
owner = find_device(dev);
if (!owner) {
spin_unlock(&dev_domain_list_spinlock);
return -ENODEV;
} |
includes |
#include <linux/capability.h> |
includes | #include <linux/mman.h> |
includes | #include <linux/mm.h> |
includes | #include <linux/swap.h> |
includes | #include <linux/swapops.h> |
includes | #include <linux/pagemap.h> |
includes | #include <linux/pagevec.h> |
includes | #include <linux/mempolicy.h> |
includes | #include <linux/syscalls.h> |
includes | #include <linux/sched.h> |
includes | #include <linux/export.h> |
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