0thbit_CRC_parallel/simulations.jsonl

{"tb_file_path": "CRC_tb.v", "simulator": "iverilog", "top_module": "tb", "work_subdir": null, "requires_submodules": false, "compile": {"args": ["-g2012"], "sources": ["CRC.v", "CRC_tb.v"]}, "run": {"args": ["-fst"]}, "waveform": "wave_crc.fst"}