Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/testbenches.json

[
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    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "alu",
    "rtl_files": [
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    ]
  },
  {
    "file_path": "Source Code/ControlUnits/main_control_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "control_unit",
    "rtl_files": [
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    ]
  },
  {
    "file_path": "Source Code/ControlUnits/pc_control_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "pc_control",
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  {
    "file_path": "Source Code/ControlUnits/stack_control_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "stack_control",
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  {
    "file_path": "Source Code/DataPath/TB.v",
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    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "MCRP",
    "rtl_files": [
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      "Source Code/ALU/alu.v",
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      "Source Code/ControlUnits/pc_control.v",
      "Source Code/ControlUnits/stack_control.v",
      "Source Code/Memory/memory.v",
      "Source Code/extenders/immediate_extender.v",
      "Source Code/extenders/shift_extender.v",
      "Source Code/extenders/offset_extednder.v",
      "Source Code/instruction_memory/instruction_memory.v",
      "Source Code/registers/register_file.v",
      "Source Code/stack/stack_memory.v"
    ]
  },
  {
    "file_path": "Source Code/Memory/memory_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "memory",
    "rtl_files": [
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  {
    "file_path": "Source Code/Memory/memory_tb2.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "memory",
    "rtl_files": [
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    "file_path": "Source Code/extenders/immediate_extender_tb.v",
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    "simulator": "icarus",
    "makefile_path": null,
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      "Source Code/extenders/immediate_extender.v"
    ]
  },
  {
    "file_path": "Source Code/instruction_memory/instruction_memory_tb.v",
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    "makefile_path": null,
    "top_module": "instruction_memory",
    "rtl_files": [
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    ]
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  {
    "file_path": "Source Code/registers/register_file_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "register_file",
    "rtl_files": [
      "Source Code/registers/register_file.v"
    ]
  },
  {
    "file_path": "Source Code/stack/stack_memory_tb.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "stack_memory",
    "rtl_files": [
      "Source Code/stack/stack_memory.v"
    ]
  }
]