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qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s ALU_TB -o /tmp/sim_ALU_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/alu/ALU.v"
+vvp /tmp/sim_ALU_TB -fst

qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s Compare_TB -o /tmp/sim_Compare_TB "$SRCDIR/PipelineProcessor/src/utilities/Compare.v"
+vvp /tmp/sim_Compare_TB -fst

qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s EXEStage_TB -o /tmp/sim_EXEStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/alu/ALU.v" "$SRCDIR/PipelineProcessor/src/stages/EXEStage.v"
+vvp /tmp/sim_EXEStage_TB -fst

qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s Extender_TB -o /tmp/sim_Extender_TB "$SRCDIR/PipelineProcessor/src/utilities/Extender.v"
+vvp /tmp/sim_Extender_TB -fst

qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s IFStage_TB -o /tmp/sim_IFStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v" "$SRCDIR/PipelineProcessor/src/utilities/mux.v" "$SRCDIR/PipelineProcessor/src/stages/IFStage.v"
+vvp /tmp/sim_IFStage_TB -fst

qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s IFStage_TB -o /tmp/sim_IFStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v" "$SRCDIR/PipelineProcessor/src/utilities/mux.v" "$SRCDIR/PipelineProcessor/src/stages/IFStage.v"
+vvp /tmp/sim_IFStage_TB -fst

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/diff.patch

@@ -0,0 +1,11 @@
+--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v
++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v
+@@ -11,7 +11,7 @@
+ 	always @(posedge clk) begin
+ 			
+ 		if (!stall)
+-			instruction <= {instructionMemory[address + 1], instructionMemory[address]};
++			instruction <= {instructionMemory[address], instructionMemory[address + 1]};
+ 			
+ 	end 
+ 

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "concat_swap",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "PipelineProcessor/src/instruction_memory/InstructionMemory.v"
+  ],
+  "bug_description": "Reordered concatenation {instructionMemory[address + 1], instructionMemory[address]} to {instructionMemory[address], instructionMemory[address + 1]} \u2014 swaps the high and low bytes of the fetched instruction, causing the instruction word to be byte-swapped",
+  "signals_affected": [
+    "instruction"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "Instruction fetch produces incorrect byte ordering beginning at t=5ns. When the instruction pointer accesses memory, the instruction signal outputs 0x0052 (0000000101010010), but the byte arrangement does not conform to the defined memory layout. The high and low bytes appear to be reversed relative to the memory addresses being accessed, resulting in corrupted opcodes being presented to the decode stage. This discrepancy is consistent across all instruction fetches, suggesting a systematic error in how instruction bytes are assembled from memory.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/sim_log.txt

@@ -0,0 +1,18 @@
+FST info: dumpfile wave_InstructionMemory.fst opened for output.
+At time                    0, Address = 0000, Instruction = xxxx
+At time                    5, Address = 0000, Instruction = 0152
+At time                   20, Address = 0002, Instruction = 0152
+At time                   25, Address = 0002, Instruction = 0354
+At time                   30, Address = 0004, Instruction = 0354
+At time                   35, Address = 0004, Instruction = 5016
+At time                   40, Address = 0006, Instruction = 5016
+At time                   45, Address = 0006, Instruction = 0576
+At time                   50, Address = 0008, Instruction = 0576
+At time                   55, Address = 0008, Instruction = xxxx
+At time                   60, Address = 000a, Instruction = xxxx
+At time                   70, Address = 000c, Instruction = xxxx
+At time                   80, Address = 000e, Instruction = xxxx
+At time                   90, Address = 0010, Instruction = xxxx
+At time                  100, Address = 0012, Instruction = xxxx
+At time                  110, Address = 0014, Instruction = xxxx
+/tmp/sim4_simsh_mf_7s8z9/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:131: $finish called at 130 (1s)

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/diff.patch

@@ -0,0 +1,12 @@
+--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v
++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v
+@@ -10,8 +10,7 @@
+ 
+ 	always @(posedge clk) begin
+ 			
+-		if (!stall)
+-			instruction <= {instructionMemory[address + 1], instructionMemory[address]};
++		instruction <= {instructionMemory[address + 1], instructionMemory[address]};
+ 			
+ 	end 
+ 

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "missing_enable",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "PipelineProcessor/src/instruction_memory/InstructionMemory.v"
+  ],
+  "bug_description": "Removed '!stall' enable condition from sequential block \u2014 instruction output now updates every clock edge regardless of the stall signal",
+  "signals_affected": [
+    "instruction"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "When the stall signal is asserted, the instruction register should hold its current value across clock edges. However, the waveform shows that the instruction signal continues to update on every clock cycle, ignoring the stall condition. At t=5, the instruction signal updates to 0101001000000001 while stall is active, when it should have remained unchanged. This indicates the instruction output is not properly responding to stall assertions, causing the pipeline to advance instructions even during stall periods and breaking pipeline flow control.",
+  "diff_summary": "5 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/sim_log.txt

@@ -0,0 +1,18 @@
+FST info: dumpfile wave_InstructionMemory.fst opened for output.
+At time                    0, Address = 0000, Instruction = xxxx
+At time                    5, Address = 0000, Instruction = 5201
+At time                   20, Address = 0002, Instruction = 5201
+At time                   25, Address = 0002, Instruction = 5403
+At time                   30, Address = 0004, Instruction = 5403
+At time                   35, Address = 0004, Instruction = 1650
+At time                   40, Address = 0006, Instruction = 1650
+At time                   45, Address = 0006, Instruction = 7605
+At time                   50, Address = 0008, Instruction = 7605
+At time                   55, Address = 0008, Instruction = xxxx
+At time                   60, Address = 000a, Instruction = xxxx
+At time                   70, Address = 000c, Instruction = xxxx
+At time                   80, Address = 000e, Instruction = xxxx
+At time                   90, Address = 0010, Instruction = xxxx
+At time                  100, Address = 0012, Instruction = xxxx
+At time                  110, Address = 0014, Instruction = xxxx
+/tmp/sim4_simsh_hb2xb6lt/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:130: $finish called at 130 (1s)

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/diff.patch

@@ -0,0 +1,11 @@
+--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v
++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v
+@@ -87,7 +87,7 @@
+         .kill(kill),
+         .stall(stall),
+         .address(address),
+-        .instruction(instruction)
++        .instruction()
+     );
+ 
+     // Clock generation

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "unconnected_port",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "PipelineProcessor/src/instruction_memory/InstructionMemory.v"
+  ],
+  "bug_description": "Disconnected 'instruction' output port of InstructionMemory instantiation in testbench \u2014 'instruction' wire in InstructionMemory_TB is now floating",
+  "signals_affected": [
+    "instruction"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During testbench execution, the `instruction` output signal from InstructionMemory fails to update with valid instruction values. At t=5, when the module is expected to present the first instruction fetch result, `instruction` is observed at 0101001000000001 and does not transition to subsequent instruction values as memory addresses change. The signal appears to be stuck at this initial value or not properly propagating from the memory output, suggesting a potential issue with the output data path or signal connectivity in the instantiation. This prevents proper verification of the instruction fetch functionality and downstream pipeline stages that depend on receiving correct instruction encodings.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/sim_log.txt

@@ -0,0 +1,13 @@
+FST info: dumpfile wave_InstructionMemory.fst opened for output.
+At time                    0, Address = 0000, Instruction = zzzz
+At time                   20, Address = 0002, Instruction = zzzz
+At time                   30, Address = 0004, Instruction = zzzz
+At time                   40, Address = 0006, Instruction = zzzz
+At time                   50, Address = 0008, Instruction = zzzz
+At time                   60, Address = 000a, Instruction = zzzz
+At time                   70, Address = 000c, Instruction = zzzz
+At time                   80, Address = 000e, Instruction = zzzz
+At time                   90, Address = 0010, Instruction = zzzz
+At time                  100, Address = 0012, Instruction = zzzz
+At time                  110, Address = 0014, Instruction = zzzz
+/tmp/sim4_simsh_o7_64cgo/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:131: $finish called at 130 (1s)

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/diff.patch

@@ -0,0 +1,11 @@
+--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v
++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v
+@@ -5,7 +5,7 @@
+ );
+ 
+  
+-    reg [7:0] instructionMemory [0:255];		  // the size will be 2 ^ 16
++    reg [5:0] instructionMemory [0:255];		  // the size will be 2 ^ 16
+ 
+ 
+ 	always @(posedge clk) begin

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "wrong_bitwidth",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "PipelineProcessor/src/instruction_memory/InstructionMemory.v"
+  ],
+  "bug_description": "Truncated 'instructionMemory' register array from 8 bits to 6 bits, causing upper 2 bits of each stored byte to be lost, resulting in corrupted instructions being fetched",
+  "signals_affected": [
+    "instructionMemory"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "Instructions fetched from instructionMemory are being corrupted during storage or retrieval. At t=5ns, the instruction signal shows 0x0201, but based on the instruction encoding for this operation, the upper bits [7:6] should be set, not zeroed. This pattern is consistent across multiple test cycles\u2014any instruction with high-valued bytes written to instructionMemory comes back with those upper bits lost, causing invalid or unexpected opcodes to be executed. The 8-bit values being stored should be fully preserved, but it appears only 6 bits are being retained. Need to verify that instructionMemory is sized correctly to hold complete instruction bytes without truncation.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/sim.sh

@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+if ! command -v python &>/dev/null; then
+    _TMPBIN=$(mktemp -d)
+    ln -s "$(command -v python3)" "$_TMPBIN/python"
+    export PATH="$_TMPBIN:$PATH"
+    trap 'rm -rf "$_TMPBIN"' EXIT
+fi
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -s InstructionMemory_TB -o /tmp/sim_InstructionMemory_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v"
+vvp /tmp/sim_InstructionMemory_TB -fst

qossayrida_PipelineProcessorDesign/source/PipelineProcessor/Edfmap.ini

@@ -0,0 +1,1380 @@
+
+[$GENERAL$]
+INIT=Z
+prefix=EDF_
+user_names=no
+edif2sdf_mapfile=
+logfile=efd2vhd.log
+
+[$EXPORT$]
+FMAP=NO
+HMAP=NO
+
+[$properties$]
+AMULTSEL=
+CYMODE=
+INIT=
+FD INIT=integer
+FDC INIT=integer
+FDCE INIT=integer
+FDCE_1 INIT=integer
+FDCP INIT=integer
+FDCPE INIT=integer
+FDCPE_1 INIT=integer
+FDCP_1 INIT=integer
+FDC_1 INIT=integer
+FDD INIT=integer
+FDDC INIT=integer
+FDDCE INIT=integer
+FDDCP INIT=integer
+FDDCPE INIT=integer
+FDDP INIT=integer
+FDDPE INIT=integer
+FDDRCPE INIT=integer
+FDDRRSE INIT=integer
+FDE INIT=integer
+FDE_1 INIT=integer
+FDP INIT=integer
+FDPE INIT=integer
+FDPE_1 INIT=integer
+FDP_1 INIT=integer
+FDR INIT=integer
+FDRE INIT=integer
+FDRE_1 INIT=integer
+FDRS INIT=integer
+FDRSE INIT=integer
+FDRSE_1 INIT=integer
+FDRS_1 INIT=integer
+FDR_1 INIT=integer
+FDS INIT=integer
+FDSE INIT=integer
+FDSE_1 INIT=integer
+FDS_1 INIT=integer
+FD_1 INIT=integer
+FJKC INIT=integer
+FJKCE INIT=integer
+FJKP INIT=integer
+FJKPE INIT=integer
+FJKRSE INIT=integer
+FJKSRE INIT=integer
+FTC INIT=integer
+FTCE INIT=integer
+FTCLE INIT=integer
+FTCLEX INIT=integer
+FTP INIT=integer
+FTPE INIT=integer
+FTPLE INIT=integer
+FTRSE INIT=integer
+FTRSLE INIT=integer
+FTSRE INIT=integer
+FTSRLE INIT=integer
+FTCP INIT=integer
+GTPA1_DUAL RXPRBSERR_LOOPBACK_0=integer
+GTPA1_DUAL RXPRBSERR_LOOPBACK_1=integer
+GTXE1 RXPRBSERR_LOOPBACK=integer
+IDDR INIT_Q1=integer
+IDDR INIT_Q2=integer
+IDDR2 INIT_Q0=integer
+IDDR2 INIT_Q1=integer
+IDDR_2CLK INIT_Q1=integer
+IDDR_2CLK INIT_Q2=integer
+IFD INIT=integer
+IFD_1 INIT=integer
+IFDI INIT=integer
+IFDI_1 INIT=integer
+IFDX INIT=integer
+IFDX_1 INIT=integer
+IFDXI INIT=integer
+IFDXI_1 INIT=integer
+ILD INIT=integer
+ILD_1 INIT=integer
+ILDI INIT=integer
+ILDI_1 INIT=integer
+ILDX INIT=integer
+ILDX_1 INIT=integer
+ILDXI INIT=integer
+ILDXI_1 INIT=integer
+ISERDES INIT_Q1=integer
+ISERDES INIT_Q2=integer
+ISERDES INIT_Q3=integer
+ISERDES INIT_Q4=integer
+ISERDES SRVAL_Q1=integer
+ISERDES SRVAL_Q2=integer
+ISERDES SRVAL_Q3=integer
+ISERDES SRVAL_Q4=integer
+ISERDES_NODELAY INIT_Q1=integer
+ISERDES_NODELAY INIT_Q2=integer
+ISERDES_NODELAY INIT_Q3=integer
+ISERDES_NODELAY INIT_Q4=integer
+ISERDES_NODELAY SRVAL_Q1=integer
+ISERDES_NODELAY SRVAL_Q2=integer
+ISERDES_NODELAY SRVAL_Q3=integer
+ISERDES_NODELAY SRVAL_Q4=integer
+LD INIT=integer
+LDC INIT=integer
+LDCE INIT=integer
+LDCE_1 INIT=integer
+LDCP INIT=integer
+LDCPE INIT=integer
+LDCPE_1 INIT=integer
+LDCP_1 INIT=integer
+LDC_1 INIT=integer
+LDE INIT=integer
+LDE_1 INIT=integer
+LDG INIT=integer
+LDP INIT=integer
+LDPE INIT=integer
+LDPE_1 INIT=integer
+LDP_1 INIT=integer
+LD_1 INIT=integer
+ODDR INIT=integer
+ODDR2 INIT=integer
+OFD INIT=integer
+OFD_1 INIT=integer
+OFDE INIT=integer
+OFDE_1 INIT=integer
+OFDI INIT=integer
+OFDI_1 INIT=integer
+OFDT INIT=integer
+OFDT_1 INIT=integer
+OFDX INIT=integer
+OFDX_1 INIT=integer
+OFDXI INIT=integer
+OFDXI_1 INIT=integer
+OSERDES INIT_OQ=integer
+OSERDES SRVAL_OQ=integer
+OSERDES INIT_TQ=integer
+OSERDES SRVAL_TQ=integer
+OSERDES INIT_OQ=integer
+OSERDES INIT_TQ=integer
+OSERDES SRVAL_OQ=integer
+OSERDES SRVAL_TQ=integer
+lut_function=
+eqn=
+INIT_00=
+INIT_01=
+INIT_02=
+INIT_03=
+INIT_04=
+INIT_05=
+INIT_06=
+INIT_07=
+INIT_08=
+INIT_09=
+INIT_0A=
+INIT_0B=
+INIT_0C=
+INIT_0D=
+INIT_0E=
+INIT_0F=
+
+INIT_10=
+INIT_11=
+INIT_12=
+INIT_13=
+INIT_14=
+INIT_15=
+INIT_16=
+INIT_17=
+INIT_18=
+INIT_19=
+INIT_1A=
+INIT_1B=
+INIT_1C=
+INIT_1D=
+INIT_1E=
+INIT_1F=
+
+INIT_20=
+INIT_21=
+INIT_22=
+INIT_23=
+INIT_24=
+INIT_25=
+INIT_26=
+INIT_27=
+INIT_28=
+INIT_29=
+INIT_2A=
+INIT_2B=
+INIT_2C=
+INIT_2D=
+INIT_2E=
+INIT_2F=
+
+INIT_30=
+INIT_31=
+INIT_32=
+INIT_33=
+INIT_34=
+INIT_35=
+INIT_36=
+INIT_37=
+INIT_38=
+INIT_39=
+INIT_3A=
+INIT_3B=
+INIT_3C=
+INIT_3D=
+INIT_3E=
+INIT_3F=
+
+INIT_40=
+INIT_41=
+INIT_42=
+INIT_43=
+INIT_44=
+INIT_45=
+INIT_46=
+INIT_47=
+INIT_48=
+INIT_49=
+INIT_4A=
+INIT_4B=
+INIT_4C=
+INIT_4D=
+INIT_4E=
+INIT_4F=
+
+INIT_50=
+INIT_51=
+INIT_52=
+INIT_53=
+INIT_54=
+INIT_55=
+INIT_56=
+INIT_57=
+INIT_58=
+INIT_59=
+INIT_5A=
+INIT_5B=
+INIT_5C=
+INIT_5D=
+INIT_5E=
+INIT_5F=
+
+INIT_60=
+INIT_61=
+INIT_62=
+INIT_63=
+INIT_64=
+INIT_65=
+INIT_66=
+INIT_67=
+INIT_68=
+INIT_69=
+INIT_6A=
+INIT_6B=
+INIT_6C=
+INIT_6D=
+INIT_6E=
+INIT_6F=
+
+INITP_00=
+INITP_01=
+INITP_02=
+INITP_03=
+INITP_04=
+INITP_05=
+INITP_06=
+INITP_07=
+
+LPM_TYPE=
+LPM_WIDTH=integer
+LPM_DIRECTION=
+P_WIDTH=
+P_OFFSET=
+CLKDV_DIVIDE=real
+DUTY_CYCLE_CORRECTION=bool
+WIDTH=integer
+DIVIDE1_BY=integer
+DIVIDE2_BY=integer
+TimingChecksOn=bool
+Xon=bool
+MsgOn=bool
+SEL_F500K=bool
+SEL_F16K=bool
+SEL_F490=bool
+SEL_F15=bool
+
+;added for virtex4 library
+CLKFX_DIVIDE=integer
+CLKFX_MULTIPLY=integer
+CLKIN_DIVIDE_BY_2=bool
+CLKIN_PERIOD=real
+CLKOUT_PHASE_SHIFT=
+CLK_FEEDBACK=
+DCM_PERFORMANCE_MODE= 
+DESKEW_ADJUST=
+DFS_FREQUENCY_MODE=
+DLL_FREQUENCY_MODE=
+FACTORY_JF=
+STARTUP_WAIT=bool
+PHASE_SHIFT=integer
+MONITOR_MODE=
+SIM_MONITOR_FILE=
+JTAG_CHAIN=integer
+INIT_OUT=integer
+PRESELECT_I0=bool
+PRESELECT_I1=bool
+BUFR_DIVIDE=
+DSS_MODE=
+AREG=integer
+B_INPUT=
+BREG=integer
+CARRYINREG=integer
+CARRYINSELREG=integer
+CREG=integer
+LEGACY_MODE=
+MREG=integer
+OPMODEREG=integer
+PREG=integer
+SUBTRACTREG=integer
+ALMOST_FULL_OFFSET=
+ALMOST_EMPTY_OFFSET=    
+DATA_WIDTH=integer
+FIRST_WORD_FALL_THROUGH=bool
+REFCLKSEL=
+SYNCLK1OUTEN=
+SYNCLK2OUTEN=
+CAPACITANCE=
+IOSTANDARD=
+DIFF_TERM=bool
+ICAP_WIDTH=
+DDR_CLK_EDGE=
+INIT_Q1=
+INIT_Q2=
+INIT_Q3=
+INIT_Q4=
+SRTYPE=
+IOBDELAY=
+IOBDELAY_TYPE=
+IOBDELAY_VALUE=integer
+DRIVE=integer
+SLEW=
+INIT_BITSLIPCNT=
+;INIT_CE=   ;2 elems bit_vector
+;INIT_RANK1_PARTIAL=  ;5 elems bit_vector
+;INIT_RANK2=  ;6 elems bit_vector
+;INIT_RANK3=  ;6 elems bit_vector
+BITSLIP_ENABLE=bool
+DATA_RATE=
+INTERFACE_TYPE=
+NUM_CE=integer
+SERDES_MODE=
+SRVAL_Q1=
+SRVAL_Q2=
+SRVAL_Q3=
+SRVAL_Q4=
+INIT_LOADCNT=
+SERDES_MODE=
+DATA_RATE_OQ=
+INIT_OQ=
+;INIT_ORANK1=  ;6 elems bit_vector
+INIT_ORANK2_PARTIAL=
+DATA_RATE_TQ=
+TRISTATE_WIDTH=integer
+INIT_TQ=
+INIT_TRANK1=
+SRVAL_OQ=
+SRVAL_TQ=
+EN_REL=bool
+RST_DEASSERT_CLK=
+DOA_REG=integer
+DOB_REG=integer
+INIT_A=
+INIT_B=
+INVERT_CLK_DOA_REG=bool
+INVERT_CLK_DOB_REG=bool
+RAM_EXTENSION_A=
+RAM_EXTENSION_B=
+READ_WIDTH_A=integer
+READ_WIDTH_B=integer
+SIM_COLLISION_CHECK=
+SRVAL_A=
+SRVAL_B=
+WRITE_MODE_A=
+WRITE_MODE_B=
+WRITE_WIDTH_A=integer
+WRITE_WIDTH_B=integer
+SRVAL=
+WRITE_MODE=
+DISABLE_COLLISION_CHECK=bool	
+ALIGN_COMMA_WORD=integer
+BANDGAPSEL=bool
+CCCB_ARBITRATOR_DISABLE=bool
+CHAN_BOND_LIMIT=integer
+CHAN_BOND_MODE=
+CHAN_BOND_ONE_SHOT=bool
+;CHAN_BOND_SEQ_1_1=  ;11 elems bit_vector
+;CHAN_BOND_SEQ_1_2=  ;11 elems bit_vector
+;CHAN_BOND_SEQ_1_3=  ;11 elems bit_vector 
+;CHAN_BOND_SEQ_1_4=  ;11 elems bit_vector
+CHAN_BOND_SEQ_1_MASK=
+;CHAN_BOND_SEQ_2_1=  ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_2=  ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_3=  ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_4=  ;11 elems bit_vector
+CHAN_BOND_SEQ_2_MASK=
+CHAN_BOND_SEQ_2_USE=bool
+CHAN_BOND_SEQ_LEN=integer
+CLK_CORRECT_USE=bool
+CLK_COR_8B10B_DE=bool
+CLK_COR_MAX_LAT=integer
+CLK_COR_MIN_LAT=integer
+;CLK_COR_SEQ_1_2=  ;11 elems bit_vector
+;CLK_COR_SEQ_1_3=  ;11 elems bit_vector
+;CLK_COR_SEQ_1_4=  ;11 elems bit_vector
+CLK_COR_SEQ_1_MASK=
+;CLK_COR_SEQ_2_1=  ;11 elems bit_vector
+;CLK_COR_SEQ_2_2=  ;11 elems bit_vector
+;CLK_COR_SEQ_2_3=  ;11 elems bit_vector
+;CLK_COR_SEQ_2_4=  ;11 elems bit_vector
+CLK_COR_SEQ_2_MASK=
+CLK_COR_SEQ_2_USE=bool
+CLK_COR_SEQ_DROP=bool
+CLK_COR_SEQ_LEN=integer
+COMMA32=bool
+;COMMA_10B_MASK=  ;10 elems bit_vector
+;CYCLE_LIMIT_SEL=  ;2 elems bit_vector
+;DCDR_FILTER=  ;3 elems bit_vector
+DEC_MCOMMA_DETECT=bool
+DEC_PCOMMA_DETECT=bool
+DEC_VALID_COMMA_ONLY=bool
+;DIGRX_FWDCLK=  ;2 elems bit_vector
+DIGRX_SYNC_MODE=bool
+ENABLE_DCDR=bool
+;FDET_HYS_CAL=  ;3 elems bit_vector
+;FDET_HYS_SEL=  ;3 elems bit_vector
+;FDET_LCK_CAL=  ;3 elems bit_vector
+;FDET_LCK_SEL=  ;3 elems bit_vector
+;LOOPCAL_WAIT=  ;2 elems bit_vector
+MCOMMA_32B_VALUE=
+MCOMMA_DETECT=bool
+OPPOSITE_SELECT=bool
+PCOMMA_32B_VALUE=
+PCOMMA_DETECT=bool
+PCS_BIT_SLIP=bool
+PMACLKENABLE=bool
+PMACOREPWRENABLE=bool
+PMA_BIT_SLIP=bool
+POWER_ENABLE=bool
+REPEATER=bool
+;RXAFEEQ=  ;9 elems bit_vector
+;RXASYNCDIVIDE=  ;2 elems bit_vector
+RXBY_32=bool
+;RXCDRLOS=  ;6 elems bit_vector
+RXCLK0_FORCE_PMACLK=bool
+;RXCLKMODE=  ;6 elems bit_vector
+RXCPSEL=bool
+RXCRCCLOCKDOUBLE=bool
+RXCRCENABLE=bool
+RXCRCINITVAL=
+RXCRCINVERTGEN=bool
+RXCRCSAMECLOCK=bool
+;RXCYCLE_LIMIT_SEL=  ;2 elems bit_vector
+;RXDATA_SEL=  ;2 elems bit_vector
+RXDCCOUPLE=bool
+RXDIGRESET=bool
+RXDIGRX=bool
+RXENABLE=bool
+RXEQ=
+RXFDCAL_CLOCK_DIVIDE=
+;RXFDET_HYS_CAL=  ;3 elems bit_vector
+;RXFDET_HYS_SEL=  ;3 elems bit_vector
+;RXFDET_LCK_CAL=  ;3 elems bit_vector
+;RXFDET_LCK_SEL=  ;3 elems bit_vector
+RXLB=bool
+;RXLKADJ=  ;5 elems bit_vector
+;RXLOOPCAL_WAIT=  ;2 elems bit_vector
+RXLOOPFILT=
+RXOUTDIV2SEL_A=
+RXOUTDIV2SEL_B=
+RXPD=bool
+RXPLLNDIVSEL=
+RXPMACLKSEL=
+;RXRCPADJ=  ;3 elems bit_vector
+RXRECCLK1_USE_SYNC=bool
+;RXSLOWDOWN_CAL=  ;2 elems bit_vector
+RXTADJ=bool
+RXUSRDIVISOR=integer
+;RXVCODAC_INIT=  ;10 elems bit_vector
+RXVCO_CTRL_ENABLE=bool
+RX_BUFFER_USE=bool
+;RX_CLOCK_DIVIDER=  ;2 elems bit_vector
+RX_LOS_INVALID_INCR=integer
+RX_LOS_THRESHOLD=integer
+SAMPLE_8X=bool
+SH_CNT_MAX=integer
+SH_INVALID_CNT_MAX=integer
+;SLOWDOWN_CAL=  ;2 elems bit_vector
+TXABPMACLKSEL=
+;TXASYNCDIVIDE=  ;2 elems bit_vector
+TXCLK0_FORCE_PMACLK=bool
+TXCLKMODE=
+TXCPSEL=bool
+TXCRCCLOCKDOUBLE=bool
+TXCRCENABLE=bool
+TXCRCINITVAL=
+TXCRCINVERTGEN=bool
+TXCRCSAMECLOCK=bool
+;TXDATA_SEL=  ;2 elems bit_vector
+;TXDAT_PRDRV_DAC=  ;3 elems bit_vector
+;TXDAT_TAP_DAC=  ;5 elems bit_vector
+TXENABLE=bool
+TXFDCAL_CLOCK_DIVIDE=
+TXHIGHSIGNALEN=bool
+TXLOOPFILT=
+TXOUTCLK1_USE_SYNC=bool
+TXOUTDIV2SEL=
+TXPD=bool
+TXPHASESEL=bool
+TXPLLNDIVSEL=
+;TXPOST_PRDRV_DAC=  ;3 elems bit_vector
+;TXPOST_TAP_DAC=  ;5 elems bit_vector
+TXPOST_TAP_PD=bool
+;TXPRE_PRDRV_DAC=  ;3 elems bit_vector
+;TXPRE_TAP_DAC=  ;5 elems bit_vector
+TXPRE_TAP_PD=bool
+TXSLEWRATE=bool
+TXTERMTRIM=
+TX_BUFFER_USE=bool
+;TX_CLOCK_DIVIDER=  ;2 elems bit_vector
+;VCODAC_INIT=  ;10 elems bit_vector
+VCO_CTRL_ENABLE=bool
+
+
+;added for virtex5 library
+A_INPUT=
+ACASCREG=integer
+ALUMODEREG=integer
+AUTORESET_PATTERN_DETEC=bool
+AUTORESET_PATTERN_DETECT_OPTINV=
+BANDWIDTH=
+BCASCREG=integer
+CLKFBOUT_MULT=integer
+CLKFBOUT_PHASE=real
+CLKIN1_PERIOD=real
+CLKIN2_PERIOD=real
+CLKOUT0_DIVIDE=integer
+CLKOUT0_DUTY_CYCLE=real
+CLKOUT0_PHASE=real
+CLKOUT1_DIVIDE=integer
+CLKOUT1_DUTY_CYCLE=real
+CLKOUT1_PHASE=real
+CLKOUT2_DIVIDE=integer
+CLKOUT2_DUTY_CYCLE=real
+CLKOUT2_PHASE=real 
+CLKOUT3_DIVIDE=integer
+CLKOUT3_DUTY_CYCLE=real
+CLKOUT3_PHASE=real 
+CLKOUT4_DIVIDE=integer 
+CLKOUT4_DUTY_CYCLE=real 
+CLKOUT4_PHASE=real 
+CLKOUT5_DIVIDE=integer 
+CLKOUT5_DUTY_CYCLE=real 
+CLKOUT5_PHASE=real
+COMPENSATION=
+CRC_INIT=
+DELAY_SRC=
+DIVCLK_DIVIDE=integer
+DO_REG=integer
+EN_ECC_READ=bool
+EN_ECC_SCRUB=bool
+EN_ECC_WRITE=bool
+EN_SYN=bool
+IDELAY_TYPE=
+IDELAY_VALUE=integer
+INIT_70= 
+INIT_71= 
+INIT_72= 
+INIT_73= 
+INIT_74= 
+INIT_75= 
+INIT_76= 
+INIT_77= 
+INIT_78= 
+INIT_79= 
+INIT_7A= 
+INIT_7B= 
+INIT_7C= 
+INIT_7D= 
+INIT_7E= 
+INIT_7F= 
+INIT_C=
+INIT_D=
+INITP_08=
+INITP_09=
+INITP_0A=
+INITP_0B=
+INITP_0C=
+INITP_0D=
+INITP_0E=
+INITP_0F=
+MASK=  
+MULTCARRYINREG=integer
+ODELAY_VALUE=integer
+PATTERN=
+PLL_PMCD_MODE=bool
+POLYNOMIAL=
+REF_JITTER=real
+RESET_ON_LOSS_OF_LOCK=bool
+SEL_MASK=
+SEL_PATTERN=
+SEL_ROUNDING_MASK=
+USE_MULT=
+USE_PATTERN_DETECT=
+USE_SIMD=
+;end of virtex5
+
+;added for virtex5 (ise9.1i sp2)
+CLKFBOUT_DESKEW_ADJUST=
+CLKOUT0_DESKEW_ADJUST=
+CLKOUT1_DESKEW_ADJUST=
+CLKOUT2_DESKEW_ADJUST=
+CLKOUT3_DESKEW_ADJUST=
+CLKOUT4_DESKEW_ADJUST=
+CLKOUT5_DESKEW_ADJUST=
+;end of virtex5 (ise9.1i sp2)
+
+;added for virtex5 (ise9.2i sp1)
+PCS_COM_CFG=
+SIGNAL_PATTERN=
+INIT_FILE=
+;end of virtex5 (ise9.2i sp1)
+
+;added for virtex5 (ise 10.1i)
+SIM_MODE=
+;end
+
+;added for spartan6, virtex6 (ise 11.2)
+A0REG=integer
+A1REG=integer
+AC_CAP_DIS_0=bool
+AC_CAP_DIS_1=bool
+ADREG=integer
+AUTORESET_PATDET=
+B0REG=integer
+B1REG=integer
+BUFFER_TYPE=
+BYPASS_GCLK_FF=bool
+CARRYINSEL=
+CARRYOUTREG=integer
+CHAN_BOND_2_MAX_SKEW_0=integer
+CINVCTRL_SEL=bool
+CLK_SEL_TYPE=
+CLKCM_CFG=bool
+CLKFBOUT_MULT_F=real
+CLKFXDV_DIVIDE=integer
+CLKFX_MD_MAX=real
+CLKFBOUT_USE_FINE_PS=bool
+CLKOUT0_DIVIDE_F=real
+CLKOUT0_USE_FINE_PS=bool
+CLKOUT1_USE_FINE_PS=bool
+CLKOUT2_USE_FINE_PS=bool
+CLKOUT3_USE_FINE_PS=bool
+CLKOUT4_CASCADE=bool
+CLKOUT4_USE_FINE_PS=bool
+CLKOUT5_USE_FINE_PS=bool
+CLKOUT6_DIVIDE=integer 
+CLKOUT6_DUTY_CYCLE=real 
+CLKOUT6_PHASE=real
+CLKOUT6_USE_FINE_PS=bool
+CLKRCV_TRST=bool
+CLOCK_HOLD=bool
+COUNTER_WRAPAROUND=
+DATA_RATE_OT=
+DDR3_DATA=integer
+DISABLE_JTAG=bool
+DIVIDE_BYPASS=bool
+DIVIDE=integer
+DFS_BANDWIDTH=
+DQSMASK_ENABLE=bool
+DYN_CLK_INV_EN=bool
+DYN_CLKDIV_INV_EN=bool
+EN_RSTRAM_A=bool
+EN_RSTRAM_B=bool
+FARSRC=
+HIGH_PERFORMANCE_MODE=bool
+I_INVERT=bool
+IBUF_DELAY_VALUE=
+IBUF_LOW_PWR=bool
+IDELAY2_VALUE=integer
+IDELAY_MODE=
+IFD_DELAY_VALUE=
+ISERDESE1 INIT_Q1=integer
+ISERDESE1 INIT_Q2=integer
+ISERDESE1 INIT_Q3=integer
+ISERDESE1 INIT_Q4=integer
+OSERDESE1 INIT_OQ=integer
+OSERDESE1 INIT_TQ=integer
+INMODEREG=integer
+InstancePath=
+ODELAY_TYPE=
+OFB_USED=bool
+ONESHOT=bool
+OUTPUT_MODE=
+PROG_MD_BANDWIDTH=
+PROG_USR=bool
+RAM_MODE=
+REF_JITTER1=real
+REF_JITTER2=real
+REFCLK_FREQUENCY=real
+;REFCLKOUT_DLY=  ;10 elems bit_vector
+RST_PRIORITY_A=
+RST_PRIORITY_B=
+RSTREG_PRIORITY_A=
+RSTREG_PRIORITY_B=
+RSTTYPE=
+SETUP_ALL=
+SIM_DEVICE=
+SIM_EFUSE_VALUE=
+SIM_TAPDELAY_VALUE=integer
+SPREAD_SPECTRUM=
+ISERDESE1 SRVAL_Q1=integer
+ISERDESE1 SRVAL_Q2=integer
+ISERDESE1 SRVAL_Q3=integer
+ISERDESE1 SRVAL_Q4=integer
+OSERDESE1 SRVAL_OQ=integer
+OSERDESE1 SRVAL_TQ=integer
+TRAIN_PATTERN=integer
+USE_DOUBLER=bool
+USE_DPORT=bool
+;end of spartan6, virtex6 (ise 11.2)
+
+; added for virtex6 (ise 11.3)
+TX_PMADATA_OPT=integer
+ENABLE_SYNC=bool
+;end of virtex6 (ise 11.3) 
+
+
+; added for virtex7 (ise 13.3)
+IBUFDS_DIFF_OUT_IBUFDISABLE DIFF_TERM=
+IBUFDS_DIFF_OUT_INTERMDISABLE DIFF_TERM=
+IBUFDS_IBUFDISABLE DIFF_TERM=
+IBUFDS_INTERMDISABLE DIFF_TERM=
+IOBUFDS_DCIEN DIFF_TERM=
+IOBUFDS_DIFF_OUT_DCIEN DIFF_TERM=
+IOBUFDS_INTERMDISABLE DIFF_TERM=
+DQS_BIAS_MODE=
+IBUF_IBUFDISABLE IBUF_LOW_PWR=
+IBUF_INTERMDISABLE IBUF_LOW_PWR=
+IBUFDS_DIFF_OUT_IBUFDISABLE IBUF_LOW_PWR=
+IBUFDS_DIFF_OUT_INTERMDISABLE IBUF_LOW_PWR=
+IBUFDS_IBUFDISABLE IBUF_LOW_PWR=
+IBUFDS_INTERMDISABLE IBUF_LOW_PWR=
+IOBUF_DCIEN IBUF_LOW_PWR=
+IOBUF_INTERMDISABLE IBUF_LOW_PWR=
+IOBUFDS_DCIEN IBUF_LOW_PWR=
+IOBUFDS_DIFF_OUT_DCIEN IBUF_LOW_PWR=
+IOBUFDS_INTERMDISABLE IBUF_LOW_PWR=
+MEMREFCLK_PERIOD=real
+PHASEREFCLK_PERIOD=real
+SEL_CLK_OFFSET=integer
+USE_IBUFDISABLE=
+;end of virtex7 (ise 13.3)
+
+; added for virtex7 (ise 13.4)
+;CLKSWING_CFG= ;2 elems bit_vector
+SS_EN=
+SS_MODE=
+SS_MOD_PERIOD=integer
+;end of virtex7 (ISE 13.4)
+
+IS_C_INVERTED=integer
+IS_CLR_INVERTED=integer
+IS_D_INVERTED=integer
+
+[$LIBMAP$]
+work=.
+xilinx=xabelsim
+xilinxun=
+simprims=simprim
+DESIGNS=
+
+;FPGA Express
+VIRTEXE=VIRTEX
+COOLRUNNER=XC9500
+COOLRUNNER2=COOLRUNNERII
+SPARTAN2E=SPARTAN2E
+SPARTAN3=SPARTAN3
+SPARTAN3A=SPARTAN3A
+SPARTAN3E=SPARTAN3E
+SPARTANXL=SPARTANX
+XC3000A=XC3000
+XC3000L=XC3000
+XC3100A=XC3000
+XC3100L=XC3000
+XC4000EX=XC4000X
+XC4000L=XC4000E
+XC4000XL=XC4000X
+XC4000XLA=XC4000X
+XC4000XV=XC4000X
+XC9500XL=XC9500
+XC9500XV=XC9500
+
+;Synplify
+COOLRUNNERII=COOLRUNNERII
+Unilib=unisim
+XC4000=unisim
+XC5000=unisim
+
+;Exemplar
+xcv=unisim
+xcv2=unisim
+xcv2p=unisim
+xcve=unisim
+xi3=unisim
+xi31=unisim
+xi31a=unisim
+xi3a=unisim
+xi3l=unisim
+xi3t=unisim
+xi4=unisim
+xi4a=unisim
+xi4e=unisim
+xi4et=unisim
+xi4ex=unisim
+xi4h=unisim
+xi4l=unisim
+xi4t=unisim
+xi4xl=unisim
+xi4xla=unisim
+xi4xv=unisim
+xi5=unisim
+xi5t=unisim
+xi72a=unisim
+xi73=unisim
+xi7t=unisim
+xi95=unisim
+xi95xl=unisim
+xi95xv=unisim
+xis=unisim
+xis2=unisim
+xis2e=unisim
+xis3=unisim
+xis3e=unisim
+xisxl=unisim
+Active_lib=
+UnlinkedDesignLibrary=
+
+[$GSRGTS$]
+GSR=
+GR=
+GTS=
+PRLD=
+
+[$INCLUDE$]
+line1=library IEEE;
+line2=use IEEE.std_logic_1164.all;
+line3=library UNISIM;
+line4=use UNISIM.vcomponents.all;
+line5=library SIMPRIM;
+line6=use SIMPRIM.vcomponents.all;
+
+[TBUF]
+.=BUFT
+
+[VCC]
+VCC=P
+
+[GND]
+ground=G
+
+[X_FF]
+IN=I
+OUT=O
+
+;[OPAD]
+;OPAD=I
+;PAD=I
+
+;[IPAD]
+;IPAD=I
+;PAD=I
+
+;[IOPAD]
+;IOPAD=I
+;PAD=I
+
+[X_PU]
+OUT=O
+
+[X_LATCH]
+IN=I
+OUT=O
+
+[X_LATCHE]
+IN=I
+OUT=O
+
+[x_tri]
+IN=I
+OUT=O
+
+[x_buf]
+IN=I
+OUT=O
+
+[x_zero]
+OUT=O
+[x_one]
+OUT=O
+
+[x_and2]
+OUT=O
+IN1=I1
+IN0=I0
+
+[x_inv]
+IN=I
+OUT=O
+
+[x_or2]
+IN0=I0
+IN1=I1
+OUT=O
+
+[x_ckbuf]
+IN=I
+OUT=O
+
+[x_and3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_and4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_and5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+[x_and6]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+OUT=O
+
+[x_and7]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+OUT=O
+
+[x_and8]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+OUT=O
+
+[x_and16]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+OUT=O
+
+[x_or2]
+IN0=I0
+IN1=I1
+OUT=O
+
+[x_or3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_or4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_or5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+[x_or6]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+OUT=O
+
+[x_or7]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+OUT=O
+
+
+[x_or8]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+OUT=O
+
+[x_or16]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+OUT=O
+
+[x_xor2]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_xor3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_xor4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_xor5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+
+[x_lut2]
+OUT=O
+
+[x_lut3]
+OUT=O
+
+[x_lut4]
+OUT=O
+
+[x_RAM16]
+OUT=O
+IN=I
+
+[x_RAM32]
+OUT=O
+IN=I
+
+[x_RAMS16]
+OUT=O
+IN=I
+
+[x_RAMS32]
+OUT=O
+IN=I
+
+[x_RAMD16]
+OUT=O
+IN=I
+
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+[MEM2WB]
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+[MEMStage]
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+[MEMStage_TB]
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+[MEMStage_tb]
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+[PC]
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+[PipelineProcessor]
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+[RegisterFile]
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+[RegisterFile_TB]
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+[UnitScopePackage_31]
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+[UnitScopePackage_680]
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+[controller]
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+[instructionMemory_TB]
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+[main]
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+[mux_3]
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+[mux_4]
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+
+[~U]
+$root=12|0*11597655|
+ALU=12|0*11598173|
+ALU_TB=12|0*11598414||0x10
+ALU_tb=12|0*167035||0x10
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+Compare=12|0*11605372|
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+DataMemory=12|0*11598603|
+DataMemory_TB=12|0*11598868||0x10
+EXE2MEM=12|0*11603019|
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+Extender=12|0*11604910|
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+IFStage_tb=12|0*11324412||0x10
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+MEM2WB=12|0*11603621|
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+MEMStage_TB=12|0*11604532||0x10
+MEMStage_tb=12|0*11175658||0x10
+MainAluControl=12|0*11599953|
+PC=12|0*410888|
+PcControl=12|0*11600226|
+PipelineProcessor=12|0*11601021||0x10
+RegisterFile=12|0*11599512|
+RegisterFile_TB=12|0*11599774||0x10
+UnitScopePackage_31=12|0*170064||0x40200000
+UnitScopePackage_680=12|0*11606141||0x40200000
+WBStage=12|0*4475664|
+compare=12|0*113486|
+compare_tb=12|0*113703||0x10
+controller=12|0*112201||0x10
+instructionMemory_TB=12|0*10837107||0x10
+main=12|0*119952||0x10
+mux_2=12|0*11603872|
+mux_3=12|0*11604298|
+mux_4=12|0*11605132|
+

qossayrida_PipelineProcessorDesign/source/PipelineProcessor/PipelineProcessor/elaboration.log

@@ -0,0 +1,45 @@
+Active-HDL 15.0.261.9132 2024-06-22 23:45:59
+
+Elaboration top modules:
+Verilog Module                PipelineProcessor
+SystemVerilog Package         UnitScopePackage_678
+
+
+-----------------------------------------------------------------------------------------------------
+Verilog Module          | Library           | Info | Compiler Version          | Compilation Options
+-----------------------------------------------------------------------------------------------------
+PipelineProcessor       | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+ClockGenerator          | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+MainAluControl          | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+PcControl               | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+HazardDetect            | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+IFStage                 | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+IF2ID                   | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+IDStage                 | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+ID2EXE                  | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+EXEStage                | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+EXE2MEM                 | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+MEMStage                | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+MEM2WB                  | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+InstructionMemory       | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+mux_2                   | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+Extender                | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+RegisterFile            | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+mux_4                   | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+Compare                 | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+ALU                     | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+DataMemory              | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+mux_3                   | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+-----------------------------------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------------------------------
+SystemVerilog Package   | Library           | Info | Compiler Version          | Compilation Options
+-----------------------------------------------------------------------------------------------------
+UnitScopePackage_678    | pipelineprocessor |      | 15.0.261.9132 (Windows64) | -O2 -sv2k17
+-----------------------------------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------------------------------
+Library                 | Comment
+-----------------------------------------------------------------------------------------------------
+pipelineprocessor       | None
+-----------------------------------------------------------------------------------------------------