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Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/diff.patch

@@ -0,0 +1,11 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -294,7 +294,7 @@
+                 end
+             end
+             FIND_VALUE: begin  
+-                if(data_rd_buf == data_in) begin 
++                if(data_rd_buf != data_in) begin 
+                     // update curr pos to invalid
+                     wr_req <= 1'b1;
+                     target_idx <= cur_ptr;

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/metadata.json

@@ -0,0 +1,17 @@
+{
+  "bug_type": "inverted_condition",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Doubly_Linked_List/src/doubly_linked_list.sv"
+  ],
+  "bug_description": "Inverted 'data_rd_buf == data_in' condition in FIND_VALUE state \u2014 delete-by-value now deletes the first node that does NOT match the target value instead of the matching one",
+  "signals_affected": [
+    "data_rd_buf",
+    "data_in"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "The delete-by-value operation is not functioning correctly. When attempting to remove a specific node from the list by matching its data field, the operation fails to complete (op_done remains low at t=132000). Additionally, the list state becomes corrupted immediately after a delete-by-value attempt: the empty flag incorrectly asserts to 1, while head and tail both point to address 1000, and length shows 0000, indicating the list thinks it's empty when it shouldn't be. On subsequent operations, the wrong node is deleted from the list\u2014inspection of the waveform shows data_out reads the wrong value (00000000 at t=828000) and pre_node_addr/next_node_addr point to incorrect addresses (1000 at t=828000 and t=876000 respectively). This suggests the comparison logic for matching the target data value is inverted, causing nodes that do NOT match to be selected for deletion instead of the correct matching node. The list structure remains corrupted throughout, with the full flag never asserting as expected and the fault flag remaining inactive even as the list becomes logically invalid.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/sim_log.txt

@@ -0,0 +1,123 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2413000 Data 7 at Index 0 is Deleted_by_Value
+2413000 linked_list_exp = 3 4 6 0 3 5 3 
+2413000 linked_list_addr = 5 6 3 1 0 2 7 
+2413000 OP_Delete_At_Index 0 index
+2485000 Data 3 at Front is Deleted
+2485000 linked_list_exp = 4 6 0 3 5 3 
+2485000 linked_list_addr = 6
+--- STDERR ---
+/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/diff.patch

@@ -0,0 +1,11 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -371,7 +371,7 @@
+             data_out <= {DATA_WIDTH{1'b0}};
+             next_node_addr <= ADDR_NULL;
+             pre_node_addr <= ADDR_NULL;
+-        end else if (op_is_read & (next_state == EXECUTE)) begin
++        end else begin
+             data_out <=  node_data[target_idx];
+             next_node_addr <= (addr_in == tail) ? ADDR_NULL : node_next_node_addr[target_idx];
+             pre_node_addr <= (addr_in == head) ? ADDR_NULL : node_pre_node_addr[target_idx];

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/metadata.json

@@ -0,0 +1,18 @@
+{
+  "bug_type": "missing_enable",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Doubly_Linked_List/src/doubly_linked_list.sv"
+  ],
+  "bug_description": "Removed 'op_is_read & (next_state == EXECUTE)' enable condition from the data_out sequential block \u2014 data_out, next_node_addr, and pre_node_addr now update on every clock edge instead of only during a read operation reaching the EXECUTE state",
+  "signals_affected": [
+    "data_out",
+    "next_node_addr",
+    "pre_node_addr"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During verification of the read operation, we observed that output registers are becoming corrupted with unexpected values at t=108000. The signals `data_out`, `next_node_addr`, and `pre_node_addr` all display unknown/garbage values when they should be maintaining the previously transferred data. This corruption occurs during normal operation when no read transaction should be occurring, suggesting these registers are being unintentionally modified outside their intended update windows. The issue prevents correct data retrieval and appears to affect all three related output signals simultaneously, indicating a shared control issue rather than isolated signal corruption.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/sim_log.txt

@@ -0,0 +1,123 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2389000 Data 7 at Index 0 is Deleted_by_Value
+2389000 linked_list_exp = 3 4 6 0 3 5 3 
+2389000 linked_list_addr = 5 6 3 1 0 2 7 
+2389000 OP_Delete_At_Index 0 index
+2461000 Data 3 at Front is Deleted
+2461000 linked_list_exp = 4 6 0 3 5 3 
+2461000 linked_list_addr = 6
+--- STDERR ---
+/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/diff.patch

@@ -0,0 +1,16 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -365,10 +365,11 @@
+             pre_addr_rd_buf <= node_pre_node_addr[target_idx];
+         end
+     end
+-    
++
++    initial data_out = {DATA_WIDTH{1'bx}};
++
+     always @ (posedge clk, posedge rst) begin
+         if (rst) begin
+-            data_out <= {DATA_WIDTH{1'b0}};
+             next_node_addr <= ADDR_NULL;
+             pre_node_addr <= ADDR_NULL;
+         end else if (op_is_read & (next_state == EXECUTE)) begin

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "missing_reset",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Doubly_Linked_List/src/doubly_linked_list.sv"
+  ],
+  "bug_description": "Removed synchronous reset for 'data_out' register; kept resets for next_node_addr and pre_node_addr intact. Added initial block setting data_out to unknown (x) so the missing reset is observable in simulation.",
+  "signals_affected": [
+    "data_out"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "Signal `data_out` fails to initialize to a known state at t=0, remaining undefined (xxxxxxxx) throughout the initial reset phase. While other module registers reset as expected, `data_out` appears to lack proper reset handling. This inconsistency could cause unpredictable behavior when the module transitions from reset, as downstream logic may encounter an unknown initial value instead of the expected cleared state.",
+  "diff_summary": "7 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/sim_log.txt

@@ -0,0 +1,123 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2389000 Data 7 at Index 0 is Deleted_by_Value
+2389000 linked_list_exp = 3 4 6 0 3 5 3 
+2389000 linked_list_addr = 5 6 3 1 0 2 7 
+2389000 OP_Delete_At_Index 0 index
+2461000 Data 3 at Front is Deleted
+2461000 linked_list_exp = 4 6 0 3 5 3 
+2461000 linked_list_addr = 6
+--- STDERR ---
+/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/diff.patch

@@ -0,0 +1,11 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -240,7 +240,7 @@
+                         // update pre_node_addr of next post to pre pos
+                         pre_node_addr_idx <= next_addr_rd_buf;
+                         pre_node_addr_in <= pre_addr_rd_buf;
+-                        next_state <= EXECUTE; 
++                        next_state <= FAULT; 
+                     end else if (op_is_insert_at_addr) begin
+                         // insert new pos 
+                         wr_req <= 1'b1;

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/metadata.json

@@ -0,0 +1,18 @@
+{
+  "bug_type": "state_transition",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Doubly_Linked_List/src/doubly_linked_list.sv"
+  ],
+  "bug_description": "Changed FIND_ADDR\u2192EXECUTE transition to FIND_ADDR\u2192FAULT for op_is_delete_by_addr \u2014 when a valid node is found by address, the FSM incorrectly transitions to FAULT instead of EXECUTE, causing delete_by_addr to always report fault and leaving length/head/tail unmodified",
+  "signals_affected": [
+    "state",
+    "fault",
+    "op_done"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "When executing a delete_by_addr operation to remove a linked-list node at a specific address, the operation fails to complete successfully even when the target node is found. The op_done signal remains low throughout the operation, and the list metadata (length, head, tail) remain unchanged at t=132000, indicating the deletion was never applied. The operation eventually enters a fault state (fault asserts at t=780000), incorrectly flagging this as a fault condition despite the node being successfully located and traversed (as evidenced by pre_node_addr and next_node_addr updates). This prevents delete_by_addr from functioning when a valid address is provided, completely breaking the address-based deletion feature of the linked-list controller.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/sim_log.txt

@@ -0,0 +1,123 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2389000 Data 7 at Index 0 is Deleted_by_Value
+2389000 linked_list_exp = 3 4 6 0 3 5 3 
+2389000 linked_list_addr = 5 6 3 1 0 2 7 
+2389000 OP_Delete_At_Index 0 index
+2461000 Data 3 at Front is Deleted
+2461000 linked_list_exp = 4 6 0 3 5 3 
+2461000 linked_list_addr = 6
+--- STDERR ---
+/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/diff.patch

@@ -0,0 +1,11 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -102,7 +102,7 @@
+     assign op_is_insert_at_index = op[2:0] == 3'd5 & op_start; 
+     assign op_is_insert_at_addr = op[2:0] == 3'd1 & op_start; 
+     assign op_is_delete_by_value = op[2:0] == 3'd2 & op_start;
+-    assign op_is_delete_by_index = op[2:0] == 3'd7 & op_start; 
++    assign op_is_delete_by_index = op[2:0] == 2'd7 & op_start; 
+     assign op_is_delete_by_addr = op[2:0] == 3'd3 & op_start;
+ 
+     always @ (posedge clk or posedge rst) begin

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "width_bit_cutoff",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Doubly_Linked_List/src/doubly_linked_list.sv"
+  ],
+  "bug_description": "Changed '3'd7' to '2'd7' in the op_is_delete_by_index assignment \u2014 2'd7 truncates to decimal 3 (7 mod 4 = 3), so Delete_Index (op=7) is never recognized; instead op=3 (which matches op_is_delete_by_addr) is incorrectly double-matched",
+  "signals_affected": [
+    "op_is_delete_by_index"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During verification of delete operations on index values, the design fails to properly handle Delete_Index commands. When executing a delete-by-index operation (op=7), the op_done signal fails to assert at t=132000, and multiple state signals (head, tail, length, empty) retain incorrect values instead of updating. Simultaneously, the fault signal incorrectly asserts at t=780000 and remains stuck, while data_out at t=828000 shows all zeros rather than the expected node data. The traversal signals pre_node_addr and next_node_addr also diverge at t=828000 and t=876000 respectively, both stuck at 1000 instead of progressing through the linked list. Additionally, the full flag incorrectly reads 0 at t=732000 when the structure should be full. These symptoms suggest that delete-by-index operations are not being recognized or executed at all, causing the entire operation pipeline to stall and state management to fail.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/sim_log.txt

@@ -0,0 +1,122 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2389000 Data 7 at Index 0 is Deleted_by_Value
+2389000 linked_list_exp = 3 4 6 0 3 5 3 
+2389000 linked_list_addr = 5 6 3 1 0 2 7 
+2389000 OP_Delete_At_Index 0 index
+ERROR: /tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:353: 2437000 fault flag is asser
+--- STDERR ---
+/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/src/doubly_linked_list.sv:105: warning: Numeric constant truncated to 2 bits.
+/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/diff.patch

@@ -0,0 +1,11 @@
+--- a/Doubly_Linked_List/src/doubly_linked_list.sv
++++ b/Doubly_Linked_List/src/doubly_linked_list.sv
+@@ -81,7 +81,7 @@
+     reg valid_wr; 
+     reg [ADDR_WIDTH-1:0] next_addr_rd_buf;
+     reg [ADDR_WIDTH-1:0] pre_addr_rd_buf;
+-    reg [DATA_WIDTH-1:0] data_rd_buf;
++    reg [DATA_WIDTH-2:0] data_rd_buf;
+     reg [ADDR_WIDTH-1:0] target_idx; 
+     reg [ADDR_WIDTH-1:0] next_node_addr_idx;
+     reg [ADDR_WIDTH-1:0] next_node_addr_in;

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/metadata.json

@@ -0,0 +1,5 @@
+{
+  "bug_type": "wrong_bitwidth",
+  "simulation_status": "waveform_identical",
+  "signals_compared": 10
+}

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/sim_log.txt

@@ -0,0 +1,123 @@
+FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output.
+
+======================================
+Direct Index Op Test
+======================================
+100000 OP_Insert_At_Index 0 index, 3 value
+133000 Next Addr = 0
+133000 Data Written to Front : 3
+133000 linked_list_exp = 3 
+133000 linked_list_addr = 0 
+133000 OP_Insert_At_Index 0 index, 0 value
+181000 Addr 0 found at Index 0
+181000 Next Addr = 1
+181000 Data Written to Front : 0
+181000 linked_list_exp = 0 3 
+181000 linked_list_addr = 1 0 
+281000 OP_Insert_At_Index 4 index, 5 value
+325000 Addr 0 found at Index 1
+325000 Addr 1 found at Index 0
+325000 Next Addr = 2
+325000 Data Written to Back : 5
+325000 linked_list_exp = 0 3 5 
+325000 linked_list_addr = 1 0 2 
+325000 OP_Insert_At_Index 0 index, 6 value
+373000 Addr 0 found at Index 1
+373000 Addr 1 found at Index 0
+373000 Addr 2 found at Index 2
+373000 Next Addr = 3
+373000 Data Written to Front : 6
+373000 linked_list_exp = 6 0 3 5 
+373000 linked_list_addr = 3 1 0 2 
+373000 OP_Insert_At_Index 0 index, 7 value
+421000 Addr 0 found at Index 2
+421000 Addr 1 found at Index 1
+421000 Addr 2 found at Index 3
+421000 Addr 3 found at Index 0
+421000 Next Addr = 4
+421000 Data Written to Front : 7
+421000 linked_list_exp = 7 6 0 3 5 
+421000 linked_list_addr = 4 3 1 0 2 
+421000 OP_Insert_At_Index 1 index, 3 value
+541000 Addr 0 found at Index 3
+541000 Addr 1 found at Index 2
+541000 Addr 2 found at Index 4
+541000 Addr 3 found at Index 1
+541000 Addr 4 found at Index 0
+541000 Next Addr = 5
+541000 Data Written to Index 1 : 3
+541000 linked_list_exp = 7 3 6 0 3 5 
+541000 linked_list_addr = 4 5 3 1 0 2 
+541000 OP_Insert_At_Index 2 index, 4 value
+685000 Addr 0 found at Index 4
+685000 Addr 1 found at Index 3
+685000 Addr 2 found at Index 5
+685000 Addr 3 found at Index 2
+685000 Addr 4 found at Index 0
+685000 Addr 5 found at Index 1
+685000 Next Addr = 6
+685000 Data Written to Index 2 : 4
+685000 linked_list_exp = 7 3 4 6 0 3 5 
+685000 linked_list_addr = 4 5 6 3 1 0 2 
+685000 OP_Insert_At_Index 8 index, 3 value
+733000 Addr 0 found at Index 5
+733000 Addr 1 found at Index 4
+733000 Addr 2 found at Index 6
+733000 Addr 3 found at Index 3
+733000 Addr 4 found at Index 0
+733000 Addr 5 found at Index 1
+733000 Addr 6 found at Index 2
+733000 Next Addr = 7
+733000 Data Written to Back : 3
+733000 Queue is full and full flag is asserted correctly
+733000 linked_list_exp = 7 3 4 6 0 3 5 3 
+733000 linked_list_addr = 4 5 6 3 1 0 2 7 
+733000 OP_Insert_At_Index 8 index, 4 value
+781000 Fault flag is asserted correctly
+781000 Queue is full and full flag is asserted correctly
+781000 linked_list_exp = 7 3 4 6 0 3 5 3 
+781000 linked_list_addr = 4 5 6 3 1 0 2 7 
+781000 OP_Read from back 8 times
+829000 Data read: 3
+877000 Data read: 5
+925000 Data read: 3
+973000 Data read: 0
+1021000 Data read: 6
+1069000 Data read: 4
+1117000 Data read: 3
+1165000 Data read: 7
+1165000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1165000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1165000 OP_Insert_At_Index 8 index, 1 value
+1213000 Fault flag is asserted correctly
+1213000 Queue is full and full flag is asserted correctly
+1213000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1213000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1213000 OP_Insert_At_Index 0 index, 3 value
+1261000 Fault flag is asserted correctly
+1261000 Queue is full and full flag is asserted correctly
+1261000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1261000 linked_list_addr = 4 5 6 3 1 0 2 7 
+1461000 OP_Read from front 8 times
+1501000 Data read: 7
+1549000 Data read: 3
+1597000 Data read: 4
+1645000 Data read: 6
+1693000 Data read: 0
+1741000 Data read: 3
+1789000 Data read: 5
+1837000 Data read: 3
+1837000 linked_list_exp = 7 3 4 6 0 3 5 3 
+1837000 linked_list_addr = 4 5 6 3 1 0 2 7 
+2337000 OP_Delete_Value 7 value
+2389000 Data 7 at Index 0 is Deleted_by_Value
+2389000 linked_list_exp = 3 4 6 0 3 5 3 
+2389000 linked_list_addr = 5 6 3 1 0 2 7 
+2389000 OP_Delete_At_Index 0 index
+2461000 Data 3 at Front is Deleted
+2461000 linked_list_exp = 4 6 0 3 5 3 
+2461000 linked_list_addr = 6
+--- STDERR ---
+/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list!
+/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list!
+/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/sim.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+set -euo pipefail
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -o /tmp/sim_doubly_linked_list "$SRCDIR/Doubly_Linked_List/src/doubly_linked_list.sv" "$SRCDIR/Doubly_Linked_List/tb/sv/tb.sv"
+vvp /tmp/sim_doubly_linked_list -fst +VCDFILE=Doubly_Linked_List/tb/sv/dump.fst +VCDLEVEL=0

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/diff.patch

@@ -0,0 +1,11 @@
+--- a/Dual_Edge_FF/src/dual_edge_ff.sv
++++ b/Dual_Edge_FF/src/dual_edge_ff.sv
+@@ -40,7 +40,7 @@
+         always @ (posedge clk or negedge rst_n) begin
+             if(!rst_n) 
+                 q_out_pos[i] <= RESET_VALUE[i];
+-            else if(pos_edge_latch_en[i])
++            else if(!pos_edge_latch_en[i])
+                 q_out_pos[i] <= d_in_pos[i];
+         end
+         

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "inverted_condition",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Dual_Edge_FF/src/dual_edge_ff.sv"
+  ],
+  "bug_description": "Inverted 'pos_edge_latch_en' condition in positive-edge flip-flop \u2014 q_out_pos now latches when pos_edge_latch_en is deasserted instead of asserted",
+  "signals_affected": [
+    "pos_edge_latch_en"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "Data output signal data_out fails to update despite pos_edge_latch_en being asserted to enable latching. At t=120000, when the latch enable signal is asserted and new data is available on the input, data_out remains stuck at 00000000 instead of capturing the expected value. The signal continues to hold this value through subsequent clock cycles, indicating that the latch is not responding correctly to the enable control signal. Simulation waveforms show pos_edge_latch_en transitioning as expected, but the data capture mechanism is not functioning properly.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/sim_log.txt

@@ -0,0 +1,51 @@
+FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output.
+Starting direct operation test
+121000 Data out is correctly latched at negedge with value 129
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 133000 Data out is incorrect, should not be updated at posedge, EXP: 129, ACT: 130
+       Time: 133000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 157000 Data out is incorrect at posedge, EXP: 99, ACT: 130
+       Time: 157000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 169000 Data out is incorrect, should not be updated at posedge, EXP: 99, ACT: 130
+       Time: 169000 Scope: tb.direct_test
+193000 Data out is correctly latched at negedge with value 141
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 205000 Data out is incorrect, should not be updated at posedge, EXP: 141, ACT: 142
+       Time: 205000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 229000 Data out is incorrect at posedge, EXP: 18, ACT: 142
+       Time: 229000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 241000 Data out is incorrect, should not be updated at posedge, EXP: 18, ACT: 142
+       Time: 241000 Scope: tb.direct_test
+265000 Data out is correctly latched at negedge with value 13
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 277000 Data out is incorrect, should not be updated at posedge, EXP: 13, ACT: 14
+       Time: 277000 Scope: tb.direct_test
+313000 Data out is correctly latched at negedge with value 61
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 325000 Data out is incorrect at posedge, EXP: 237, ACT: 61
+       Time: 325000 Scope: tb.direct_test
+361000 Data out is correctly latched at negedge with value 249
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 373000 Data out is incorrect at posedge, EXP: 198, ACT: 249
+       Time: 373000 Scope: tb.direct_test
+409000 Data out is correctly latched at negedge with value 170
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 421000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171
+       Time: 421000 Scope: tb.direct_test
+457000 Data out is correctly latched at negedge with value 119
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 469000 Data out is incorrect at posedge, EXP: 18, ACT: 119
+       Time: 469000 Scope: tb.direct_test
+505000 Data out is correctly latched at negedge with value 242
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 517000 Data out is incorrect at posedge, EXP: 206, ACT: 242
+       Time: 517000 Scope: tb.direct_test
+553000 Data out is correctly latched at negedge with value 197
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 565000 Data out is incorrect, should not be updated at posedge, EXP: 197, ACT: 198
+       Time: 565000 Scope: tb.direct_test
+601000 Data out is correctly latched at negedge with value 189
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 613000 Data out is incorrect at posedge, EXP: 45, ACT: 189
+       Time: 613000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 637000 Data out is incorrect at posedge, EXP: 99, ACT: 189
+       Time: 637000 Scope: tb.direct_test
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 649000 Data out is incorrect, should not be updated at posedge, EXP: 99, ACT: 189
+       Time: 649000 Scope: tb.direct_test
+673000 Data out is correctly latched at negedge with value 128
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 685000 Data out is incorrect, should not be updated at posedge, EXP: 128, ACT: 129
+       Time: 685000 Scope: tb.direct_test
+721000 Data out is correctly latched at negedge with value 170
+ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/
+--- STDERR ---
+/tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/diff.patch

@@ -0,0 +1,11 @@
+--- a/Dual_Edge_FF/src/dual_edge_ff.sv
++++ b/Dual_Edge_FF/src/dual_edge_ff.sv
+@@ -40,7 +40,7 @@
+         always @ (posedge clk or negedge rst_n) begin
+             if(!rst_n) 
+                 q_out_pos[i] <= RESET_VALUE[i];
+-            else if(pos_edge_latch_en[i])
++            else
+                 q_out_pos[i] <= d_in_pos[i];
+         end
+         

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/metadata.json

@@ -0,0 +1,17 @@
+{
+  "bug_type": "missing_enable",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Dual_Edge_FF/src/dual_edge_ff.sv"
+  ],
+  "bug_description": "Removed 'pos_edge_latch_en[i]' enable condition from the posedge clk sequential block \u2014 q_out_pos[i] now updates on every positive clock edge instead of only when pos_edge_latch_en[i] is high",
+  "signals_affected": [
+    "q_out_pos",
+    "data_out"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During verification of the data latch module, we observed that `data_out` is not maintaining stable values across clock cycles as expected. Specifically, at t=120000, `data_out` shows 00000000 when it should have retained the previously latched value based on the pos_edge_latch_en signal control. The `q_out_pos` register appears to be updating on every positive clock edge regardless of the enable signal state, causing `data_out` to be overwritten continuously instead of only updating when pos_edge_latch_en is asserted. This violates the expected behavior where the output should remain constant except when an explicit latch enable pulse is received. The issue prevents proper data capture and holding, breaking the intended control flow of the module.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/sim_log.txt

@@ -0,0 +1,55 @@
+FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output.
+Starting direct operation test
+121000 Data out is correctly latched at negedge with value 129
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 133000 Data out is incorrect, should not be updated at posedge, EXP: 129, ACT: 130
+       Time: 133000 Scope: tb.direct_test
+157000 Data out is correctly latched at posedge with value 99
+193000 Data out is correctly latched at negedge with value 141
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 205000 Data out is incorrect, should not be updated at posedge, EXP: 141, ACT: 142
+       Time: 205000 Scope: tb.direct_test
+229000 Data out is correctly latched at posedge with value 18
+265000 Data out is correctly latched at negedge with value 13
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 277000 Data out is incorrect, should not be updated at posedge, EXP: 13, ACT: 14
+       Time: 277000 Scope: tb.direct_test
+313000 Data out is correctly latched at negedge with value 61
+325000 Data out is correctly latched at posedge with value 237
+361000 Data out is correctly latched at negedge with value 249
+373000 Data out is correctly latched at posedge with value 198
+409000 Data out is correctly latched at negedge with value 170
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 421000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171
+       Time: 421000 Scope: tb.direct_test
+457000 Data out is correctly latched at negedge with value 119
+469000 Data out is correctly latched at posedge with value 18
+505000 Data out is correctly latched at negedge with value 242
+517000 Data out is correctly latched at posedge with value 206
+553000 Data out is correctly latched at negedge with value 197
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 565000 Data out is incorrect, should not be updated at posedge, EXP: 197, ACT: 198
+       Time: 565000 Scope: tb.direct_test
+601000 Data out is correctly latched at negedge with value 189
+613000 Data out is correctly latched at posedge with value 45
+637000 Data out is correctly latched at posedge with value 99
+673000 Data out is correctly latched at negedge with value 128
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 685000 Data out is incorrect, should not be updated at posedge, EXP: 128, ACT: 129
+       Time: 685000 Scope: tb.direct_test
+721000 Data out is correctly latched at negedge with value 170
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 733000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171
+       Time: 733000 Scope: tb.direct_test
+757000 Data out is correctly latched at posedge with value 150
+805000 Data out is correctly latched at posedge with value 13
+853000 Data out is correctly latched at posedge with value 107
+889000 Data out is correctly latched at negedge with value 2
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 901000 Data out is incorrect, should not be updated at posedge, EXP: 2, ACT: 3
+       Time: 901000 Scope: tb.direct_test
+937000 Data out is correctly latched at negedge with value 29
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 949000 Data out is incorrect, should not be updated at posedge, EXP: 29, ACT: 30
+       Time: 949000 Scope: tb.direct_test
+985000 Data out is correctly latched at negedge with value 35
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 997000 Data out is incorrect, should not be updated at posedge, EXP: 35, ACT: 36
+       Time: 997000 Scope: tb.direct_test
+1033000 Data out is correctly latched at negedge with value 202
+ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 1045000 Data out is incorrect, should not be updated at posedge, EXP: 202, ACT: 203
+       Time: 1045000 Scope: tb.direct_test
+1069000 Data out is correctly latched at posedge with value 242
+1105000 Data out is cor
+--- STDERR ---
+/tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/diff.patch

@@ -0,0 +1,21 @@
+--- a/Dual_Edge_FF/src/dual_edge_ff.sv
++++ b/Dual_Edge_FF/src/dual_edge_ff.sv
+@@ -28,6 +28,7 @@
+     reg [DATA_WIDTH-1:0] d_in_neg;
+     reg [DATA_WIDTH-1:0] q_out_neg;
+     
++    initial q_out_pos = {DATA_WIDTH{1'bx}};
+ 
+     assign clk_n = ~clk; // Invert clock for negative edge latching
+ 
+@@ -38,9 +39,7 @@
+     
+         assign d_in_pos[i] = data_in[i] ^ q_out_neg[i];
+         always @ (posedge clk or negedge rst_n) begin
+-            if(!rst_n) 
+-                q_out_pos[i] <= RESET_VALUE[i];
+-            else if(pos_edge_latch_en[i])
++            if(pos_edge_latch_en[i])
+                 q_out_pos[i] <= d_in_pos[i];
+         end
+         

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "missing_reset",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Dual_Edge_FF/src/dual_edge_ff.sv"
+  ],
+  "bug_description": "Removed asynchronous reset for 'q_out_pos' register; added initial block setting q_out_pos to unknown (x) to make the missing reset observable in simulation",
+  "signals_affected": [
+    "q_out_pos"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "Upon simulation startup, the `data_out` signal exhibits undefined values (xxxxxxxx) at t=0, when it should be initialized to a known state following the reset sequence. The output register does not properly initialize to its expected reset value, instead holding unknown bits throughout the initial cycles. This causes the data output bus to drive X-states onto downstream logic immediately at the start of simulation, preventing proper initialization-dependent checks and breaking any verification assertions that depend on known output values after reset de-assertion.",
+  "diff_summary": "7 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/sim_log.txt

@@ -0,0 +1,68 @@
+FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output.
+Starting direct operation test
+121000 Data out is correctly latched at negedge with value x
+157000 Data out is correctly latched at posedge with value x
+193000 Data out is correctly latched at negedge with value x
+229000 Data out is correctly latched at posedge with value x
+265000 Data out is correctly latched at negedge with value x
+313000 Data out is correctly latched at negedge with value x
+325000 Data out is correctly latched at posedge with value x
+361000 Data out is correctly latched at negedge with value x
+373000 Data out is correctly latched at posedge with value x
+409000 Data out is correctly latched at negedge with value x
+457000 Data out is correctly latched at negedge with value x
+469000 Data out is correctly latched at posedge with value x
+505000 Data out is correctly latched at negedge with value x
+517000 Data out is correctly latched at posedge with value x
+553000 Data out is correctly latched at negedge with value x
+601000 Data out is correctly latched at negedge with value x
+613000 Data out is correctly latched at posedge with value x
+637000 Data out is correctly latched at posedge with value x
+673000 Data out is correctly latched at negedge with value x
+721000 Data out is correctly latched at negedge with value x
+757000 Data out is correctly latched at posedge with value x
+805000 Data out is correctly latched at posedge with value x
+853000 Data out is correctly latched at posedge with value x
+889000 Data out is correctly latched at negedge with value x
+937000 Data out is correctly latched at negedge with value x
+985000 Data out is correctly latched at negedge with value x
+1033000 Data out is correctly latched at negedge with value x
+1069000 Data out is correctly latched at posedge with value x
+1105000 Data out is correctly latched at negedge with value x
+1117000 Data out is correctly latched at posedge with value x
+1153000 Data out is correctly latched at negedge with value x
+1165000 Data out is correctly latched at posedge with value x
+1201000 Data out is correctly latched at negedge with value x
+1213000 Data out is correctly latched at posedge with value x
+1249000 Data out is correctly latched at negedge with value x
+1285000 Data out is correctly latched at posedge with value x
+1321000 Data out is correctly latched at negedge with value x
+1333000 Data out is correctly latched at posedge with value x
+1369000 Data out is correctly latched at negedge with value x
+1417000 Data out is correctly latched at negedge with value x
+1465000 Data out is correctly latched at negedge with value x
+1477000 Data out is correctly latched at posedge with value x
+1513000 Data out is correctly latched at negedge with value x
+1525000 Data out is correctly latched at posedge with value x
+1561000 Data out is correctly latched at negedge with value x
+1597000 Data out is correctly latched at posedge with value x
+1633000 Data out is correctly latched at negedge with value x
+1645000 Data out is correctly latched at posedge with value x
+1681000 Data out is correctly latched at negedge with value x
+1729000 Data out is correctly latched at negedge with value x
+1741000 Data out is correctly latched at posedge with value x
+1777000 Data out is correctly latched at negedge with value x
+1789000 Data out is correctly latched at posedge with value x
+1825000 Data out is correctly latched at negedge with value x
+1873000 Data out is correctly latched at negedge with value x
+1885000 Data out is correctly latched at posedge with value x
+1921000 Data out is correctly latched at negedge with value x
+1957000 Data out is correctly latched at posedge with value x
+1993000 Data out is correctly latched at negedge with value x
+2041000 Data out is correctly latched at negedge with value x
+2077000 Data out is correctly latched at posedge with value x
+2125000 Data out is correctly latched at posedge with value x
+2173000 Data out is correctly latched at posedge with value x
+2221000 Data out is cor
+--- STDERR ---
+/tmp/sim4_simsh_1_i_5s5y/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/diff.patch

@@ -0,0 +1,11 @@
+--- a/Dual_Edge_FF/src/dual_edge_ff.sv
++++ b/Dual_Edge_FF/src/dual_edge_ff.sv
+@@ -24,7 +24,7 @@
+     );
+     
+     reg [DATA_WIDTH-1:0] d_in_pos;
+-    reg [DATA_WIDTH-1:0] q_out_pos;
++    reg [DATA_WIDTH-3:0] q_out_pos;
+     reg [DATA_WIDTH-1:0] d_in_neg;
+     reg [DATA_WIDTH-1:0] q_out_neg;
+     

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "wrong_bitwidth",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "Dual_Edge_FF/src/dual_edge_ff.sv"
+  ],
+  "bug_description": "Truncated 'q_out_pos' register from DATA_WIDTH bits to DATA_WIDTH-2 bits, causing upper 2 bits to be stuck at 0 when driving data_out",
+  "signals_affected": [
+    "q_out_pos"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "The `data_out` signal is not transferring data correctly. At t=0 and throughout simulation, the upper 2 bits remain stuck at 0, while the lower bits show expected transitions. When verifying data transfer operations, the `data_out` output fails to reflect the full value that should be driven from the internal register\u2014specifically, bits that should be set to 1 in the upper positions of the word are consistently observed as 0. This causes mismatches in data integrity checks and prevents correct operation of the data path. The issue appears to affect all data transfers, suggesting a systematic problem with how the output register is connected to the `data_out` port.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/sim_log.txt

@@ -0,0 +1,68 @@
+FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output.
+Starting direct operation test
+121000 Data out is correctly latched at negedge with value X
+157000 Data out is correctly latched at posedge with value X
+193000 Data out is correctly latched at negedge with value X
+229000 Data out is correctly latched at posedge with value X
+265000 Data out is correctly latched at negedge with value X
+313000 Data out is correctly latched at negedge with value X
+325000 Data out is correctly latched at posedge with value X
+361000 Data out is correctly latched at negedge with value X
+373000 Data out is correctly latched at posedge with value X
+409000 Data out is correctly latched at negedge with value X
+457000 Data out is correctly latched at negedge with value X
+469000 Data out is correctly latched at posedge with value X
+505000 Data out is correctly latched at negedge with value X
+517000 Data out is correctly latched at posedge with value X
+553000 Data out is correctly latched at negedge with value X
+601000 Data out is correctly latched at negedge with value X
+613000 Data out is correctly latched at posedge with value X
+637000 Data out is correctly latched at posedge with value X
+673000 Data out is correctly latched at negedge with value X
+721000 Data out is correctly latched at negedge with value X
+757000 Data out is correctly latched at posedge with value X
+805000 Data out is correctly latched at posedge with value X
+853000 Data out is correctly latched at posedge with value X
+889000 Data out is correctly latched at negedge with value X
+937000 Data out is correctly latched at negedge with value X
+985000 Data out is correctly latched at negedge with value X
+1033000 Data out is correctly latched at negedge with value X
+1069000 Data out is correctly latched at posedge with value X
+1105000 Data out is correctly latched at negedge with value X
+1117000 Data out is correctly latched at posedge with value X
+1153000 Data out is correctly latched at negedge with value X
+1165000 Data out is correctly latched at posedge with value X
+1201000 Data out is correctly latched at negedge with value X
+1213000 Data out is correctly latched at posedge with value X
+1249000 Data out is correctly latched at negedge with value X
+1285000 Data out is correctly latched at posedge with value X
+1321000 Data out is correctly latched at negedge with value X
+1333000 Data out is correctly latched at posedge with value X
+1369000 Data out is correctly latched at negedge with value X
+1417000 Data out is correctly latched at negedge with value X
+1465000 Data out is correctly latched at negedge with value X
+1477000 Data out is correctly latched at posedge with value X
+1513000 Data out is correctly latched at negedge with value X
+1525000 Data out is correctly latched at posedge with value X
+1561000 Data out is correctly latched at negedge with value X
+1597000 Data out is correctly latched at posedge with value X
+1633000 Data out is correctly latched at negedge with value X
+1645000 Data out is correctly latched at posedge with value X
+1681000 Data out is correctly latched at negedge with value X
+1729000 Data out is correctly latched at negedge with value X
+1741000 Data out is correctly latched at posedge with value X
+1777000 Data out is correctly latched at negedge with value X
+1789000 Data out is correctly latched at posedge with value X
+1825000 Data out is correctly latched at negedge with value X
+1873000 Data out is correctly latched at negedge with value X
+1885000 Data out is correctly latched at posedge with value X
+1921000 Data out is correctly latched at negedge with value X
+1957000 Data out is correctly latched at posedge with value X
+1993000 Data out is correctly latched at negedge with value X
+2041000 Data out is correctly latched at negedge with value X
+2077000 Data out is correctly latched at posedge with value X
+2125000 Data out is correctly latched at posedge with value X
+2173000 Data out is correctly latched at posedge with value X
+2221000 Data out is cor
+--- STDERR ---
+/tmp/sim4_simsh_hhfr_x00/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/sim.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+set -euo pipefail
+SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+iverilog -g2012 -o /tmp/sim_dual_edge_ff "$SRCDIR/Dual_Edge_FF/src/dual_edge_ff.sv" "$SRCDIR/Dual_Edge_FF/tb/sv/tb.sv"
+vvp /tmp/sim_dual_edge_ff -fst +VCDFILE=Dual_Edge_FF/tb/sv/dump.fst +VCDLEVEL=0

Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/diff.patch

@@ -0,0 +1,11 @@
+--- a/FIFO/src/fifo.sv
++++ b/FIFO/src/fifo.sv
+@@ -31,7 +31,7 @@
+                 if(rst) begin
+                     {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {(2*CNTR_WIDTH){1'b0}};
+                 end else begin
+-                    {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {wr_gray_pointer_sync[0], wr_gray_pointer};
++                    {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {wr_gray_pointer, wr_gray_pointer_sync[0]};
+                 end
+             end
+ 

Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/metadata.json

@@ -0,0 +1,16 @@
+{
+  "bug_type": "concat_swap",
+  "task_type": "behavioral_bug",
+  "files_modified": [
+    "FIFO/src/fifo.sv"
+  ],
+  "bug_description": "Reordered concatenation {wr_gray_pointer_sync[0], wr_gray_pointer} to {wr_gray_pointer, wr_gray_pointer_sync[0]} in the wr_gray_pointer synchronizer shift register \u2014 the new write-pointer value is loaded into sync[1] instead of sync[0], breaking the two-stage synchronizer so wr_gray_pointer_sync[1] immediately reflects the unsynchronized write pointer rather than the properly delayed version",
+  "signals_affected": [
+    "wr_gray_pointer_sync"
+  ],
+  "simulation_status": "sim_ok",
+  "problem_statement": "During FIFO cross-clock-domain verification, the `fifo_empty` signal exhibits incorrect behavior at t=16000, transitioning to 'x' when it should reflect a valid logic state. The write-side gray pointer synchronizer (`wr_gray_pointer_sync`) appears to be responding too quickly to write-pointer changes, suggesting the multi-stage synchronization pipeline is not functioning as designed. This causes the FIFO empty flag calculation to become unstable and unreliable across clock domain crossings. The issue manifests consistently when write pointer updates occur, indicating a systematic failure in the synchronization mechanism rather than a transient metastability event. Further investigation of the pointer synchronizer path is needed to restore proper FIFO operation.",
+  "diff_summary": "4 changed lines",
+  "buggy_waveform": "buggy_waveform.fst",
+  "golden_waveform": "golden_waveform.fst"
+}

Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/sim_log.txt

@@ -0,0 +1,77 @@
+FST info: dumpfile FIFO/tb/sv/dump.fst opened for output.
+
+100000 FIFO WRITE BURST SEQ
+110000 Data written = 146, FIFO entry = 1
+130000 Data written = 64, FIFO entry = 2
+150000 Data written = 4, FIFO entry = 3
+170000 Data written = 49, FIFO entry = 4
+190000 Data written = 134, FIFO entry = 5
+210000 Data written = 198, FIFO entry = 6
+230000 Data written = 50, FIFO entry = 7
+250000 Data written = 9, FIFO entry = 8
+270000 Data written = 128, FIFO entry = 9
+290000 Data written = 134, FIFO entry = 10
+310000 Data written = 187, FIFO entry = 11
+330000 Data written = 158, FIFO entry = 12
+351000 FIFO is full, fifo_full flag is asserted correctly
+371000 FIFO is full, fifo_full flag is asserted correctly
+391000 FIFO is full, fifo_full flag is asserted correctly
+
+1410000 FIFO READ BURST SEQ
+1458000 Data read =         146, FIFO entry =          11
+1490000 Data read =          64, FIFO entry =          10
+1522000 Data read =           4, FIFO entry =           9
+1554000 Data read =          49, FIFO entry =           8
+1586000 Data read =         134, FIFO entry =           7
+1618000 Data read =         198, FIFO entry =           6
+1650000 Data read =          50, FIFO entry =           5
+1682000 Data read =           9, FIFO entry =           4
+1714000 Data read =         128, FIFO entry =           3
+1746000 Data read =         134, FIFO entry =           2
+1778000 Data read =         187, FIFO entry =           1
+1810000 Data read =         158, FIFO entry =           0
+1841000 FIFO is empty, fifo_empty flag is asserted correctly
+1873000 FIFO is empty, fifo_empty flag is asserted correctly
+1905000 FIFO is empty, fifo_empty flag is asserted correctly
+
+2905000 FIFO RANDOM READ WRITE SEQ
+2910000 Data written = 85, FIFO entry = 1
+2930000 Data written = 242, FIFO entry = 2
+2950000 Data written = 59, FIFO entry = 3
+2970000 Data written = 9, FIFO entry = 4
+2990000 Data written = 199, FIFO entry = 5
+3130000 Data written = 116, FIFO entry = 6
+3150000 Data written = 98, FIFO entry = 7
+3170000 Data written = 174, FIFO entry = 8
+3346000 Data read =          85, FIFO entry =           7
+3474000 Data read =         242, FIFO entry =           6
+3570000 Data written = 144, FIFO entry = 7
+3710000 Data written = 78, FIFO entry = 8
+4466000 Data read =          59, FIFO entry =           7
+
+5558000 FIFO SIMULTANEOUS RANDOM READ WRITE SEQ
+5618000 Data read =           9, FIFO entry =           6
+5650000 Data read =         199, FIFO entry =           5
+5682000 Data read =         116, FIFO entry =           4
+5714000 Data read =          98, FIFO entry =           3
+5746000 Data read =         174, FIFO entry =           2
+5778000 Data read =         144, FIFO entry =           1
+5810000 Data read =          78, FIFO entry =           0
+5830000 Data written =         101, FIFO entry =           1
+5850000 Data written =          30, FIFO entry =           2
+5870000 Data written =         250, FIFO entry =           3
+5890000 Data written =         197, FIFO entry =           4
+5910000 Data written =         161, FIFO entry =           5
+5930000 Data written =         108, FIFO entry =           6
+5950000 Data written =         188, FIFO entry =           7
+5970000 Data written =          68, FIFO entry =           8
+5990000 Data written =         246, FIFO entry =           9
+6010000 Data written =         219, FIFO entry =          10
+6030000 Data written =         228, FIFO entry =          11
+6050000 Data written =         215, FIFO entry =          12
+
+7070000 TEST PASSED
+
+
+--- STDERR ---
+/tmp/sim4_simsh_al8_3h79/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list!

Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/diff.patch

@@ -0,0 +1,11 @@
+--- a/FIFO/src/fifo.sv
++++ b/FIFO/src/fifo.sv
+@@ -64,7 +64,7 @@
+         if(rst) begin
+             for (i = 0; i < DEPTH; i = i + 1)
+                 fifo_stored[i] <= {DATA_WIDTH{1'b0}};
+-        end else if (wr_en & !fifo_full) begin
++        end else if (wr_en & fifo_full) begin
+             fifo_stored[wr_binary_pointer] <= data_wr;
+         end
+     end