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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3

Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
Dataset card Files Files and versions
xet
Community
1
rtl-augmented-v3 / Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog /source
  • 4 contributors
History: 1 commit
googhieman's picture
googhieman
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78c261f verified about 1 month ago
  • Source Code
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  • photos
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  • ArchReport_2.pdf
    2.43 MB
    xet
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  • README.md
    2.34 kB
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