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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
like
0
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ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
Dataset card
Files
Files and versions
xet
Community
1
main
rtl-augmented-v3
/
Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog
/
source
/
Source Code
/
ControlUnits
4 contributors
History:
1 commit
googhieman
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main_control.v
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main_control_tb.v
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pc_control.v
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pc_control_tb.v
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stack_control.v
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674 Bytes
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stack_control_tb.v
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about 1 month ago
