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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3

Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
Dataset card Files Files and versions
xet
Community
1
rtl-augmented-v3 / ayushc13_32-bit-RISC-processor-using-HDL-Verilog
25.9 kB
  • 4 contributors
History: 1 commit
googhieman's picture
googhieman
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  • candidates
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  • source
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  • sim_script_map.json
    72 Bytes
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  • simulations.jsonl
    504 Bytes
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  • testbenches.json
    386 Bytes
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  • waveform_map.json
    74 Bytes
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