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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3

Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
Dataset card Files Files and versions
xet
Community
1
rtl-augmented-v3 / ayushc13_32-bit-RISC-processor-using-HDL-Verilog /source
9.37 kB
  • 4 contributors
History: 1 commit
googhieman's picture
googhieman
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  • README.md
    1.39 kB
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  • mips32.v
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  • mips32_tb1.v
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  • mips32_tb2.v
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