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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3
like
0
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ubc-capstone
5
Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
mit
Dataset card
Files
Files and versions
xet
Community
1
main
rtl-augmented-v3
/
nimanaqavi_Verilog-MathFunctions
/
source
/
Verilog-MathFunctions
/
sin_cos_Ln_exp_SRC
13.3 kB
4 contributors
History:
3 commits
AveryWong03
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2 months ago
Ln_CO.v
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Ln_DP.v
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Ln_TOP.v
448 Bytes
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Part2TOP.v
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part1CO.v
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2 months ago
part1Dp.v
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part1TOP.v
477 Bytes
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part2CO.v
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part2DP.v
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2 months ago
