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Meltdown is a well-known attack on dynamically-scheduled
processors which exploits the fact that loads may be executed
speculatively before determining whether they represent a memory
access violation. Intel Itanium has a speculative load instruction
which allows a compiler to perform a load speculatively and needs a
check instruction at a later point in the code to verify whether the
load did in fact raise an exception. Would you imagine that a
Meltdown attach on Itanium based on this instruction could be
possible? Explain clearly your reasoning. | A check load instruction aids speculative loads by checking whether a speculative load was dependent on a later store, and thus must be reloaded.The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP: Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken. Delayed exceptions, using a not a thing bit within the general purpose registers, allow speculative execution past possible exceptions. Very large architectural register files avoid the need for register renaming. Multi-way branch instructions improve branch prediction by combining many alternative branches into one bundle.The Itanium architecture also added rotating register files, a tool useful for software pipelining since it avoids having to manually unroll and rename registers. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Meltdown is a well-known attack on dynamically-scheduled
processors which exploits the fact that loads may be executed
speculatively before determining whether they represent a memory
access violation. Intel Itanium has a speculative load instruction
which allows a compiler to perform a load speculatively and needs a
check instruction at a later point in the code to verify whether the
load did in fact raise an exception. Would you imagine that a
Meltdown attach on Itanium based on this instruction could be
possible? Explain clearly your reasoning. | They are all based on exploiting side effects of speculative execution, a common means of hiding memory latency and so speeding up execution in modern microprocessors. In particular, Spectre centers on branch prediction, which is a special case of speculative execution. Unlike the related Meltdown vulnerability disclosed at the same time, Spectre does not rely on a specific feature of a single processor's memory management and protection system, but is instead a more generalized idea. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider a DSP with an Address Generation Unit which has a single
address register which can only be automodified to point to the next
or previous word in memory without using the main ALU nor reloading
the address register. A program uses five integer variables erb+i+,
erb+j+, erb+x_coord+, erb+y_coord+, and erb+sum+, and the
sequence of accesses in the main program loop is statically known and
is
egin{verbatim}
i → j → x_coord → y_coord → x_coord → i → y_coord →
→ x_coord → y_coord → j → sum → x_coord → y_coord
\end{verbatim}
Note that these accesses are all inside a loop which repeats many
times. What is an optimal placement of the five integers in memory?
Show how you have arrived to the result. | However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider a DSP with an Address Generation Unit which has a single
address register which can only be automodified to point to the next
or previous word in memory without using the main ALU nor reloading
the address register. A program uses five integer variables erb+i+,
erb+j+, erb+x_coord+, erb+y_coord+, and erb+sum+, and the
sequence of accesses in the main program loop is statically known and
is
egin{verbatim}
i → j → x_coord → y_coord → x_coord → i → y_coord →
→ x_coord → y_coord → j → sum → x_coord → y_coord
\end{verbatim}
Note that these accesses are all inside a loop which repeats many
times. What is an optimal placement of the five integers in memory?
Show how you have arrived to the result. | The DEC PDP-8 minicomputer had eight special locations (at addresses 8 through 15). When accessed via memory indirect addressing, these locations would automatically increment prior to use. This made it easy to step through memory in a loop without needing to use the accumulator to increment the address. The Data General Nova minicomputer had 16 special memory locations at addresses 16 through 31. When accessed via memory indirect addressing, 16 through 23 would automatically increment before use, and 24 through 31 would automatically decrement before use. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of superscalar processors, what is the function of a Load Store Queue (LSQ)? | Modern out-of-order CPUs can use a number of techniques to detect a RAW dependence violation, but all techniques require tracking in-flight loads from execution until retirement. When a load executes, it accesses the memory system and/or store queue to obtain its data value, and then its address and data are buffered in a load queue until retirement. The load queue is similar in structure and function to the store queue, and in fact in some processors may be combined with the store queue in a single structure called a load-store queue, or LSQ. The following techniques are used or have been proposed to detect RAW dependence violations: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of superscalar processors, what is the function of a Load Store Queue (LSQ)? | The multi queue algorithm or MQ was developed to improve the performance of second level buffer cache for e.g. a server buffer cache. It is introduced in a paper by Zhou, Philbin, and Li. The MQ cache contains an m number of LRU queues: Q0, Q1, ..., Qm-1. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
If several elements are ready in a reservation station, which
one do you think should be selected? extbf{Very briefly} discuss
the options. | Furthermore, the reservation station scheme has four places (Future File, Reservation Station, Reorder Buffer and Architectural File) where a result value can be stored, whereas the tag-indexed scheme has just one (the physical register file). Because the results from the functional units, broadcast to all these storage locations, must reach a much larger number of locations in the machine than in the tag-indexed scheme, this function consumes more power, area, and time. Still, in machines equipped with very accurate branch prediction schemes and if execute latencies are a major concern, reservation stations can work remarkably well. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
If several elements are ready in a reservation station, which
one do you think should be selected? extbf{Very briefly} discuss
the options. | POWER1 also doesn't have reservation stations needed for out-of-order use of a same execution unit. The next year IBM's ES/9000 model 900 had register renaming also for the general-purpose registers. It also has reservation stations with six entries for the dual integer unit (each cycle, from the six instructions up to two can be selected and then executed) and six entries for the FPU. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Are VLIWs capable of speculative execution? Explain precisely
your answer and provide examples for Itanium, if appropriate.. | In a VLIW, the compiler uses heuristics or profile information to guess the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics. Vector processor cores (designed for large one-dimensional arrays of data called vectors) can be combined with the VLIW architecture such as in the Fujitsu FR-V microprocessor, further increasing throughput and speed. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Are VLIWs capable of speculative execution? Explain precisely
your answer and provide examples for Itanium, if appropriate.. | Speculative execution is an optimization technique where a computer system performs some task that may not be needed. Work is done before it is known whether it is actually needed, so as to prevent a delay that would have to be incurred by doing the work after it is known that it is needed. If it turns out the work was not needed after all, most changes made by the work are reverted and the results are ignored. The objective is to provide more concurrency if extra resources are available. This approach is employed in a variety of areas, including branch prediction in pipelined processors, value prediction for exploiting value locality, prefetching memory and files, and optimistic concurrency control in database systems.Speculative multithreading is a special case of speculative execution. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of Load Store Queue, What conditions must be satisfied in the LSQ for a load to be executed and the result to be returned to the processor? | Modern out-of-order CPUs can use a number of techniques to detect a RAW dependence violation, but all techniques require tracking in-flight loads from execution until retirement. When a load executes, it accesses the memory system and/or store queue to obtain its data value, and then its address and data are buffered in a load queue until retirement. The load queue is similar in structure and function to the store queue, and in fact in some processors may be combined with the store queue in a single structure called a load-store queue, or LSQ. The following techniques are used or have been proposed to detect RAW dependence violations: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of Load Store Queue, What conditions must be satisfied in the LSQ for a load to be executed and the result to be returned to the processor? | With this technique, the load queue, like the store queue, is a CAM searched using the memory access address, and keeps track of all in-flight loads. When a store executes, it searches the load queue for completed loads from the same address that are logically later in program order. If such a matching load exists, it must have executed before the store and thus read an incorrect, old value from the memory system/store queue. Any instructions that used the load's value have also used bad data. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
For the same processor, with the Memory to Execute forwarding
path, see if there exists a way to optimize this snippet of a
program (assume all instructions require a single cycle in the
Execute unit):
egin{verbatim}
add r5, r2, r1
mul r7, r12, r5
add r5, r3, r1
mul r8, r12, r5
add r5, r4, r1
\end{verbatim}
If there is one, show the modified code, explain the reason of the
change(s), and say how many cycles you expect to gain with the
modification(s). If there is none possible, explain why. Assume that
the processor has 31 general purpose registers and
exttt{r18}-- exttt{r23} are unused in this program. | For example, with six executions units, six new instructions are fetched in stage 1 only after the six previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least two execution units. For example, with two executions units, two new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore two different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1). | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
For the same processor, with the Memory to Execute forwarding
path, see if there exists a way to optimize this snippet of a
program (assume all instructions require a single cycle in the
Execute unit):
egin{verbatim}
add r5, r2, r1
mul r7, r12, r5
add r5, r3, r1
mul r8, r12, r5
add r5, r4, r1
\end{verbatim}
If there is one, show the modified code, explain the reason of the
change(s), and say how many cycles you expect to gain with the
modification(s). If there is none possible, explain why. Assume that
the processor has 31 general purpose registers and
exttt{r18}-- exttt{r23} are unused in this program. | So, programs can be further optimized by assigning the same register to a source and destination of a move instruction whenever possible. This is especially important if the compiler is using an intermediate representation such as static single-assignment form (SSA). In particular, when SSA is not fully optimized it can artificially generate additional move instructions. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Give an example of an exception whose precise implementation is
arguably irrelevant in practice. | It also wastes the least amount of work. Exceptions can be made to operate like interrupts in very simple computers. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Give an example of an exception whose precise implementation is
arguably irrelevant in practice. | Even the term "exception" may be misleading because its typical connotation of "outlier" indicates that something infrequent or unusual has occurred, when in fact raising the exception may be a normal and usual situation in the program. For example, suppose a lookup function for an associative array throws an exception if the key has no value associated. Depending on context, this "key absent" exception may occur much more often than a successful lookup.A major influence on the scope and use of exceptions is social pressure, i.e. "examples of use, typically found in core libraries, and code examples in technical books, magazine articles, and online discussion forums, and in an organization’s code standards". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the following code snippet, explain if it would be better
scheduled with static HLS or dynamic HLS. Assume erb+acc+ to be a
floating point variable; floating-point multiplications have a
latency of four and all other operations a latency of one. If good
static scheduling requires some typical trasformations, explain
clearly which ones.
egin{verbatim}
0: for i = 0 to N do
1: acc = 0.0
2: for j = 0 to M do
3: cond = (j % 5) == 0
4: if (cond) then
5: acc = acc * acc
6: else
7: acc = acc + a[i * M + j] + 1.0
8: end if
9: end for
10: b[i] = acc
11: end for
\end{verbatim}
| The 6600 is, of course, much faster. With good compiler instruction scheduling, the machine can approach its theoretical peak of 10 MIPS. Floating-point additions take four clock cycles, and floating-point multiplications take 10 clocks (but there are two multiply functional units, so two operations can be processing at the same time.) | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the following code snippet, explain if it would be better
scheduled with static HLS or dynamic HLS. Assume erb+acc+ to be a
floating point variable; floating-point multiplications have a
latency of four and all other operations a latency of one. If good
static scheduling requires some typical trasformations, explain
clearly which ones.
egin{verbatim}
0: for i = 0 to N do
1: acc = 0.0
2: for j = 0 to M do
3: cond = (j % 5) == 0
4: if (cond) then
5: acc = acc * acc
6: else
7: acc = acc + a[i * M + j] + 1.0
8: end if
9: end for
10: b[i] = acc
11: end for
\end{verbatim}
| This is a considerable disadvantage to a real time systems designer. The algorithm is also difficult to implement in hardware and there is a tricky issue of representing deadlines in different ranges (deadlines can not be more precise than the granularity of the clock used for the scheduling). If a modular arithmetic is used to calculate future deadlines relative to now, the field storing a future relative deadline must accommodate at least the value of the (("duration" {of the longest expected time to completion} * 2) + "now"). | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Would VLIW processors benefit from a Load Store Queue? | The data obtained by the load will be incorrect. To solve this problem, processors employ a technique called store-to-load forwarding using the store queue. In addition to buffering stores until retirement, the store queue serves a second purpose: forwarding data from completed but not-yet-retired ("in-flight") stores to later loads. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Would VLIW processors benefit from a Load Store Queue? | However, this has proven difficult in practice, and VLIW processors have not become widely popular. Even in the case of VLIW, another problem has grown to become an issue. In all traditional designs the data and instructions are handled by different parts of the CPU. When processing speeds were low this did not cause problems, but as performance increased, the communication times from one side of the chip (the registers) to the other (the functional units) grew to become a significant fraction of overall processing time. For further gains in performance, the registers should be distributed closer to their functional units. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
How does a Prime+Probe cache attack works? What information does
it typically reveal to the attacker about the victim code?
| It then goes on to show that the subsequent difference between cache hits and misses can be reliably timed, so that what should have been a simple non-functional difference can in fact be subverted into a covert channel which extracts information from an unrelated process's inner workings. Thirdly, the paper synthesizes the results with return-oriented programming exploits and other principles with a simple example program and a JavaScript snippet run under a sandboxing browser; in both cases, the entire address space of the victim process (i.e. the contents of a running program) is shown to be readable by simply exploiting speculative execution of conditional branches in code generated by a stock compiler or the JavaScript machinery present in an existing browser. The basic idea is to search existing code for places where speculation touches upon otherwise inaccessible data, manipulate the processor into a state where speculative execution has to contact that data, and then time the side effect of the processor being faster, if its by-now-prepared prefetch machinery indeed did load a cache line. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
How does a Prime+Probe cache attack works? What information does
it typically reveal to the attacker about the victim code?
| However, this speculative execution may affect the state of certain components of the microprocessor, such as the cache, and this effect may be discovered by careful monitoring of the timing of subsequent operations. If an attacker can arrange that the speculatively executed code (which may be directly written by the attacker, or may be a suitable gadget that they have found in the targeted system) operates on secret data that they are unauthorized to access, and has a different effect on the cache for different values of the secret data, they may be able to discover the value of the secret data. Starting in 2017, multiple examples of such vulnerabilities were identified, with publication starting in early 2018. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In Itanium's procedure call and return mechanism, What problem might arise when the processor executes
erb+alloc+? Which mechanisms could be used to handle the problem?
Feel free to mention what Itanium actually does (if you recall it),
but list any effective solution that comes to mind. Just outline the
basic ideas, do not try to describe or solve the details. | The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA-64 architecture. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In Itanium's procedure call and return mechanism, What problem might arise when the processor executes
erb+alloc+? Which mechanisms could be used to handle the problem?
Feel free to mention what Itanium actually does (if you recall it),
but list any effective solution that comes to mind. Just outline the
basic ideas, do not try to describe or solve the details. | The only sticking point is that it is unclear to the caller, who is unaware of the implementation details of the component methods, when it should attempt to re-execute the transaction if it fails. In response, the authors proposed a retry command which uses the transaction log generated by the failed transaction to determine which memory cells it read, and automatically retries the transaction when one of these cells is modified, based on the logic that the transaction will not behave differently until at least one such value is changed. The authors also proposed a mechanism for composition of alternatives, the orElse function. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the following code snippet, explain if it would be better
scheduled with static HLS or dynamic HLS. Assume erb+acc+ to be a
floating point variable; floating-point multiplications have a
latency of four and all other operations a latency of one. If good
static scheduling requires some typical trasformations, explain
clearly which ones.
egin{verbatim}
0: for i = 0 to N do
1: acc = 0.0
2: for j = 0 to M do
3: cond = (c[j] % 5) == 0
4: if (cond) then
5: acc = acc * acc
6: else
7: acc = acc + a[i * M + j] + 1.0
8: end if
9: end for
10: b[i] = acc
11: end for
\end{verbatim}
| The 6600 is, of course, much faster. With good compiler instruction scheduling, the machine can approach its theoretical peak of 10 MIPS. Floating-point additions take four clock cycles, and floating-point multiplications take 10 clocks (but there are two multiply functional units, so two operations can be processing at the same time.) | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the following code snippet, explain if it would be better
scheduled with static HLS or dynamic HLS. Assume erb+acc+ to be a
floating point variable; floating-point multiplications have a
latency of four and all other operations a latency of one. If good
static scheduling requires some typical trasformations, explain
clearly which ones.
egin{verbatim}
0: for i = 0 to N do
1: acc = 0.0
2: for j = 0 to M do
3: cond = (c[j] % 5) == 0
4: if (cond) then
5: acc = acc * acc
6: else
7: acc = acc + a[i * M + j] + 1.0
8: end if
9: end for
10: b[i] = acc
11: end for
\end{verbatim}
| This is a considerable disadvantage to a real time systems designer. The algorithm is also difficult to implement in hardware and there is a tricky issue of representing deadlines in different ranges (deadlines can not be more precise than the granularity of the clock used for the scheduling). If a modular arithmetic is used to calculate future deadlines relative to now, the field storing a future relative deadline must accommodate at least the value of the (("duration" {of the longest expected time to completion} * 2) + "now"). | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What differentiates VLIW processors from out-of-order
superscalar processors? | Since determining the order of execution of operations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the scheduling hardware that the three methods described above require. Thus, VLIW CPUs offer more computing with less hardware complexity (but greater compiler complexity) than do most superscalar CPUs. This is also complementary to the idea that as many computations as possible should be done before the program is executed, at compile time. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What differentiates VLIW processors from out-of-order
superscalar processors? | The traditional means to improve performance in processors include dividing instructions into substeps so the instructions can be executed partly at the same time (termed pipelining), dispatching individual instructions to be executed independently, in different parts of the processor (superscalar architectures), and even executing instructions in an order different from the program (out-of-order execution). These methods all complicate hardware (larger circuits, higher cost and energy use) because the processor must make all of the decisions internally for these methods to work. In contrast, the VLIW method depends on the programs providing all the decisions regarding which instructions to execute simultaneously and how to resolve conflicts. As a practical matter, this means that the compiler (software used to create the final programs) becomes more complex, but the hardware is simpler than in many other means of parallelism. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What kind of exceptions require the processor to implement them precisely? Why? Give three examples of such exceptions. | For example floating point instructions may be implemented in hardware on some systems and emulated on lower-cost systems. In the latter case, execution of an unimplemented floating point instruction will cause an "illegal instruction" exception interrupt. The interrupt handler will implement the floating point function in software and then return to the interrupted program as if the hardware-implemented instruction had been executed. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What kind of exceptions require the processor to implement them precisely? Why? Give three examples of such exceptions. | The simplest one involved merely marking the page containing interrupt descriptors as non-cacheable. Again, the extra memory cycles that the processor was forced to go through to fetch data from RAM every time it needed to invoke an exception handler appeared to be all that was needed to prevent the processor from locking up. In this case, no modification whatsoever to any exception handler was required. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In which class of processors do you expect to find reservation
stations? | A unified reservation station, also known as unified scheduler, is a decentralized feature of the microarchitecture of a CPU that allows for register renaming, and is used by the Tomasulo algorithm for dynamic instruction scheduling. Reservation stations permit the CPU to fetch and re-use a data value as soon as it has been computed, rather than waiting for it to be stored in a register and re-read. When instructions are issued, they can designate the reservation station from which they want their input to read. When multiple instructions need to write to the same register, all can proceed and only the (logically) last one need actually be written. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In which class of processors do you expect to find reservation
stations? | The concepts of reservation stations, register renaming, and the common data bus in Tomasulo's algorithm presents significant advancements in the design of high-performance computers. Reservation stations take on the responsibility of waiting for operands in the presence of data dependencies and other inconsistencies such as varying storage access time and circuit speeds, thus freeing up the functional units. This improvement overcomes long floating point delays and memory accesses. In particular the algorithm is more tolerant of cache misses. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
List two common types of exceptions which could possibly be
implemented imprecisely. Explain why. | Although exceptions themselves cannot be generic, generic parameters can appear in a throws clause: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
List two common types of exceptions which could possibly be
implemented imprecisely. Explain why. | Practically speaking, there may be exceptions for which not enough status information about an exception is available, in which case the processor may raise a special exception, called an "imprecise" exception. Imprecise exceptions cannot occur in in-order implementations, as processor state is changed only in program order (see RISC Pipeline Exceptions). Programs that experience "precise" exceptions, where the specific instruction that took the exception can be determined, can restart or re-execute at the point of the exception. However, those that experience "imprecise" exceptions generally cannot restart or re-execute, as the system cannot determine the specific instruction that took the exception. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider the following snippet used to produce a
high-performance circuit using a statically scheduled HLS tool, such
as Xilinx Vivado HLS. Assume that a erb+double+ multiplication
takes several cycles (latency) to compute.
egin{verbatim}
double a[ARRAY_SIZE] = ...;
int b = 1;
for (int i = 0; i < ARRAY_SIZE; i++)
if (a[i] * (double) b >= CONST)
b++;
\end{verbatim}
Would a compiler for a VLIW processor like Itanium experience more, less, or different problems in scheduling efficiently the snippet above? Explain.
| Since determining the order of execution of operations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the scheduling hardware that the three methods described above require. Thus, VLIW CPUs offer more computing with less hardware complexity (but greater compiler complexity) than do most superscalar CPUs. This is also complementary to the idea that as many computations as possible should be done before the program is executed, at compile time. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider the following snippet used to produce a
high-performance circuit using a statically scheduled HLS tool, such
as Xilinx Vivado HLS. Assume that a erb+double+ multiplication
takes several cycles (latency) to compute.
egin{verbatim}
double a[ARRAY_SIZE] = ...;
int b = 1;
for (int i = 0; i < ARRAY_SIZE; i++)
if (a[i] * (double) b >= CONST)
b++;
\end{verbatim}
Would a compiler for a VLIW processor like Itanium experience more, less, or different problems in scheduling efficiently the snippet above? Explain.
| In a VLIW, the compiler uses heuristics or profile information to guess the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics. Vector processor cores (designed for large one-dimensional arrays of data called vectors) can be combined with the VLIW architecture such as in the Fujitsu FR-V microprocessor, further increasing throughput and speed. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What does it mean that a processor supports precise exceptions? | The program counter is set to the address of a special exception handler, and special registers are written with the exception location and cause. To make it easy (and fast) for the software to fix the problem and restart the program, the CPU must take a precise exception. A precise exception means that all instructions up to the excepting instruction have been executed, and the excepting instruction and everything afterwards have not been executed. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What does it mean that a processor supports precise exceptions? | Practically speaking, there may be exceptions for which not enough status information about an exception is available, in which case the processor may raise a special exception, called an "imprecise" exception. Imprecise exceptions cannot occur in in-order implementations, as processor state is changed only in program order (see RISC Pipeline Exceptions). Programs that experience "precise" exceptions, where the specific instruction that took the exception can be determined, can restart or re-execute at the point of the exception. However, those that experience "imprecise" exceptions generally cannot restart or re-execute, as the system cannot determine the specific instruction that took the exception. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In context of Meltdown Attack, what are the basic ideas of the attack and how they relate to
the snippet above? What is the microarchitectural mechanism targeted
by the attack? Is it likely to work on all processors with such
architectural mechanism or some processors may be intrinsically not
vulnerable? Explain.
| Meltdown relies on a CPU race condition that can arise between instruction execution and privilege checking. Put briefly, the instruction execution leaves side effects that constitute information not hidden to the process by the privilege check. The process carrying out Meltdown then uses these side effects to infer the values of memory mapped data, bypassing the privilege check. The following provides an overview of the exploit, and the memory mapping that is its target. The attack is described in terms of an Intel processor running Microsoft Windows or Linux, the main test targets used in the original paper, but it also affects other processors and operating systems, including macOS (aka OS X), iOS, and Android. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In context of Meltdown Attack, what are the basic ideas of the attack and how they relate to
the snippet above? What is the microarchitectural mechanism targeted
by the attack? Is it likely to work on all processors with such
architectural mechanism or some processors may be intrinsically not
vulnerable? Explain.
| Finally, the paper concludes by generalizing the attack to any non-functional state of the victim process. It briefly discusses even such highly non-obvious non-functional effects as bus arbitration latency.Meltdown can be used to read privileged memory in a process's address space which even the process itself would normally be unable to access (on some unprotected OSes this includes data belonging to the kernel or other processes). It was shown that under certain circumstances, the Spectre vulnerability is also capable of reading memory outside of the current process's memory space. The Meltdown paper distinguishes the two vulnerabilities thus: "Meltdown is distinct from the Spectre Attacks in several ways, notably that Spectre requires tailoring to the victim process's software environment, but applies more broadly to CPUs and is not mitigated by KAISER." | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In which type of processors do you expect to find a reorder buffer? | Due to a store buffer, a load can access cache ahead of a preceding store.PowerPC 604 (1995) was the first single-chip processor with execution unit-level re-ordering, as three out of its six units each had a two-entry reservation station permitting the newer entry to execute before the older. The re-order buffer capacity is 16 instructions. A four-entry load queue and a six-entry store queue track the re-ordering of loads and stores upon cache misses. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In which type of processors do you expect to find a reorder buffer? | It differs from a history buffer because the reorder buffer typically comes after the future file (if it exists) and before the architectural register file. Reorder buffers can be data-less or data-ful. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In Itanium's procedure call and return mechanism, What is the purpose of the erb+alloc+ instruction? Where do
you expect a compiler to place it? What is the meaning of its two
arguments and how would a compiler determine their values? Describe
what the processor does when it executes it (ignore here potential
problems due to the limited number of registers). | The CPU sends the decoded instruction as a set of control signals to the corresponding computer components. If the instruction involves arithmetic or logic, the ALU is utilized. This is the only stage of the instruction cycle that is useful from the perspective of the end-user. Everything else is overhead required to make the execute step happen. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In Itanium's procedure call and return mechanism, What is the purpose of the erb+alloc+ instruction? Where do
you expect a compiler to place it? What is the meaning of its two
arguments and how would a compiler determine their values? Describe
what the processor does when it executes it (ignore here potential
problems due to the limited number of registers). | The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA-64 architecture. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What is the main difficulty in performing a Prime+Probe attack
on a system with L1 caches private to each core and a shared LLC,
and with attacker and victim running on different cores? How can
this difficulty be circumvented?
| The miss penalty has been already used to attack symmetric encryption algorithms, like DES. The basic idea proposed in this paper is to force a cache miss while the processor is executing the AES encryption algorithm on a known plain text. The attacks allow an unprivileged process to attack other process running in parallel on the same processor, despite partitioning methods such as memory protection, sandboxing and virtualization. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What is the main difficulty in performing a Prime+Probe attack
on a system with L1 caches private to each core and a shared LLC,
and with attacker and victim running on different cores? How can
this difficulty be circumvented?
| The authors needed several thousand CPU cores for a week to precompute data for a single 512-bit prime. Once that was done, however, individual logarithms could be solved in about a minute using two 18-core Intel Xeon CPUs. Its CVE ID is CVE-2015-4000.The authors also estimated the feasibility of the attack against 1024-bit Diffie–Hellman primes. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What hardware support is necessary in a processor to implement
modulo scheduling? Name all hardware features involved and give a
brief explanation of each of them. | Lam showed that special hardware is unnecessary for effective modulo scheduling. Her technique, modulo variable expansion is widely used in practice. Gao et al. formulated optimal software pipelining in integer linear programming, culminating in validation of advanced heuristics in an evaluation paper. This paper has a good set of references on the topic. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What hardware support is necessary in a processor to implement
modulo scheduling? Name all hardware features involved and give a
brief explanation of each of them. | Processors may have hardware support for some critical sections. Examples include supporting atomic access to bits or bytes within a word, or other atomic access primitives like the LDREX/STREX exclusive access primitives introduced in the ARMv6 architecture. Interrupt nesting. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of Load Store Queue, How does the LSQ gets ordering information? | Modern out-of-order CPUs can use a number of techniques to detect a RAW dependence violation, but all techniques require tracking in-flight loads from execution until retirement. When a load executes, it accesses the memory system and/or store queue to obtain its data value, and then its address and data are buffered in a load queue until retirement. The load queue is similar in structure and function to the store queue, and in fact in some processors may be combined with the store queue in a single structure called a load-store queue, or LSQ. The following techniques are used or have been proposed to detect RAW dependence violations: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the context of Load Store Queue, How does the LSQ gets ordering information? | With this technique, the load queue, like the store queue, is a CAM searched using the memory access address, and keeps track of all in-flight loads. When a store executes, it searches the load queue for completed loads from the same address that are logically later in program order. If such a matching load exists, it must have executed before the store and thus read an incorrect, old value from the memory system/store queue. Any instructions that used the load's value have also used bad data. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The MIPS R10000 fetches four instructions at once and, therefore,
there are four such circuits working in parallel inside the processor. What is the function of the ``Old dest'' field in the ``Active
List''? And what is the function of ``Log dest''? Why are they
needed in the ``Active list''? | To improve access to operands, an indexed addressing mode (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes). MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The MIPS R10000 fetches four instructions at once and, therefore,
there are four such circuits working in parallel inside the processor. What is the function of the ``Old dest'' field in the ``Active
List''? And what is the function of ``Log dest''? Why are they
needed in the ``Active list''? | C-instructions direct the ALU computation engine and program flow control capabilities of the Hack computer. The instruction syntax is defined by three fields, referred to as “comp”, “dest”, and “jump”. The comp field is required in every C-instruction. The C-instruction syntax is “dest=comp;jump”. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
To avoid the effect of the prefetcher, one could use a hash
table to randomize the access order during probing so that the
prefetcher cannot anticipate the access pattern. What is the
potential problem with this idea? | Because linear probing is especially sensitive to unevenly distributed hash values, it is important to combine it with a high-quality hash function that does not produce such irregularities. The analysis above assumes that each key's hash is a random number independent of the hashes of all the other keys. This assumption is unrealistic for most applications of hashing. However, random or pseudorandom hash values may be used when hashing objects by their identity rather than by their value. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
To avoid the effect of the prefetcher, one could use a hash
table to randomize the access order during probing so that the
prefetcher cannot anticipate the access pattern. What is the
potential problem with this idea? | However, the adversary has to make this choice before (or independent of) the algorithm's random choice of a hash function. If the adversary can observe the random choice of the algorithm, randomness serves no purpose, and the situation is the same as deterministic hashing. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Explain how precise exceptions are implemented in
dynamically-scheduled out-of-order processors. | Practically speaking, there may be exceptions for which not enough status information about an exception is available, in which case the processor may raise a special exception, called an "imprecise" exception. Imprecise exceptions cannot occur in in-order implementations, as processor state is changed only in program order (see RISC Pipeline Exceptions). Programs that experience "precise" exceptions, where the specific instruction that took the exception can be determined, can restart or re-execute at the point of the exception. However, those that experience "imprecise" exceptions generally cannot restart or re-execute, as the system cannot determine the specific instruction that took the exception. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Explain how precise exceptions are implemented in
dynamically-scheduled out-of-order processors. | Structured exception handling. Proceedings of the 2nd ACM SIGACT-SIGPLAN symposium on Principles of programming languages - POPL '75. pp. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Since exploiting the cache side-channel requires precise time
measurement, many security researchers suggest reducing the
precision of this time measurement. Can this proposal fully disable
all possible cache side-channel attacks? Discuss.? | The starting point of the white paper is that of a side-channel timing attack applied to the branch prediction machinery of modern out-of-order executing microprocessors. While at the architectural level documented in processor data books, any results of misprediction are specified to be discarded after the fact, the resulting speculative execution may still leave side effects, like loaded cache lines. These can then affect the so-called non-functional aspects of the computing environment later on. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Since exploiting the cache side-channel requires precise time
measurement, many security researchers suggest reducing the
precision of this time measurement. Can this proposal fully disable
all possible cache side-channel attacks? Discuss.? | {{cite book}}: |periodical= ignored (help) Page, Daniel (2005), "Partitioned cache architecture as a side-channel defence mechanism" (PDF), Cryptology ePrint Archive Bertoni, Guido; Zaccaria, Vittorio; Breveglieri, Luca; Monchiero, Matteo; Palermo, Gianluca (2005). "AES power attack based on induced cache miss and countermeasure" (PDF). International Conference on Information Technology: Coding and Computing (ITCC'05) – Volume II. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider the following snippet used to produce a
high-performance circuit using a statically scheduled HLS tool, such
as Xilinx Vivado HLS. Assume that a erb+double+ multiplication
takes several cycles (latency) to compute.
egin{verbatim}
double a[ARRAY_SIZE] = ...;
int b = 1;
for (int i = 0; i < ARRAY_SIZE; i++)
if (a[i] * (double) b >= CONST)
b++;
\end{verbatim}
For the same snippet, would a dynamically scheduled circuit
naturally achieve better performance? If so, does the answer depend
on some particular technique applied in the design of the
dynamically scheduled circuit? Which one? Explain.
| For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. static RAM from dynamic RAM, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Consider the following snippet used to produce a
high-performance circuit using a statically scheduled HLS tool, such
as Xilinx Vivado HLS. Assume that a erb+double+ multiplication
takes several cycles (latency) to compute.
egin{verbatim}
double a[ARRAY_SIZE] = ...;
int b = 1;
for (int i = 0; i < ARRAY_SIZE; i++)
if (a[i] * (double) b >= CONST)
b++;
\end{verbatim}
For the same snippet, would a dynamically scheduled circuit
naturally achieve better performance? If so, does the answer depend
on some particular technique applied in the design of the
dynamically scheduled circuit? Which one? Explain.
| Because signals don't have to move as far, the clock can tick much faster. .. There is still a need to convert the result to binary at the end of a calculation, which effectively just means letting the carries travel all the way through the number just as in a conventional adder. But if we have done 512 additions in the process of performing a 512-bit multiplication, the cost of that final conversion is effectively split across those 512 additions, so each addition bears 1/512 of the cost of that final "conventional" addition. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Why does Intel Itanium contain more general-purpose registers (128) than most RISC instruction sets (usually 32)? | The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA-64 architecture. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Why does Intel Itanium contain more general-purpose registers (128) than most RISC instruction sets (usually 32)? | One of the key advances in the RISC concept was to include more processor registers than earlier designs, typically several dozen rather than two or three. Instructions that formerly were provided memory locations were eliminated, replaced by ones that worked only on registers. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The MIPS R10000 fetches four instructions at once and, therefore,
there are four such circuits working in parallel inside the processor. What do ``WrPtr'' and ``RdPtr'' represent, respectively? Very
briefly explain what they are used for and when their value changes. | The first MIPS microprocessor, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the processor register file; these result-retrieving instructions were interlocked. The R2000 could be booted either big-endian or little-endian. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The MIPS R10000 fetches four instructions at once and, therefore,
there are four such circuits working in parallel inside the processor. What do ``WrPtr'' and ``RdPtr'' represent, respectively? Very
briefly explain what they are used for and when their value changes. | For the multi-cycle MIPS, there are five types of instructions: Load (5 cycles) Store (4 cycles) R-type (4 cycles) Branch (3 cycles) Jump (3 cycles)If a program has: 50% load instructions 25% store instructions 15% R-type instructions 8% branch instructions 2% jump instructionsthen, the CPI is: CPI = 5 × 50 + 4 × 25 + 4 × 15 + 3 × 8 + 3 × 2 100 = 4.4 {\displaystyle {\text{CPI}}={\frac {5\times 50+4\times 25+4\times 15+3\times 8+3\times 2}{100}}=4.4} | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
List two common types of exceptions which must be implemented
precisely. Explain why. | Although exceptions themselves cannot be generic, generic parameters can appear in a throws clause: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
List two common types of exceptions which must be implemented
precisely. Explain why. | A range of standard exceptions are available to programmers. Methods in standard libraries regularly throw system exceptions in some circumstances and the range of exceptions thrown is normally documented. Custom exception classes can be defined for classes allowing handling to be put in place for particular circumstances as needed.Checked exceptions are not present in C# (in contrast to Java). This has been a conscious decision based on the issues of scalability and versionability. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Is the processors in recoder buffers ordered (e.g., FIFO-like) or an unordered structure?
Why? | A re-order buffer (ROB) is a hardware unit used in an extension to the Tomasulo algorithm to support out-of-order and speculative instruction execution. The extension forces instructions to be committed in-order. The buffer is a circular buffer (to provide a FIFO instruction ordering queue) implemented as an array/vector (which allows recording of results against instructions as they complete out of order). There are three stages to the Tomasulo algorithm: "Issue", "Execute", "Write Result". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Is the processors in recoder buffers ordered (e.g., FIFO-like) or an unordered structure?
Why? | The previous physical register allocated for that architectural register is saved with the instruction in the reorder buffer, which is a FIFO that holds the instructions in program order between the decode and graduation stages. The instructions are then placed in various issue queues. As instructions are executed, the tags for their results are broadcast, and the issue queues match these tags against the tags of their non-ready source operands. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following is TRUE for Recommender Systems (RS)? | Recommender systems are information filtering systems which attempt to predict the rating or preference that a user would give, based on ratings that similar users gave and ratings that the user gave on previous occasions. These systems have become increasingly popular and are used for movies, music, news, books, research articles, search queries, social tags, and products in general. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following is TRUE for Recommender Systems (RS)? | A recommender system, or a recommendation system (sometimes replacing 'system' with a synonym such as platform or engine), is a subclass of information filtering system that provide suggestions for items that are most pertinent to a particular user. Typically, the suggestions refer to various decision-making processes, such as what product to purchase, what music to listen to, or what online news to read. Recommender systems are particularly useful when an individual needs to choose an item from a potentially overwhelming number of items that a service may offer.Recommender systems are used in a variety of areas, with commonly recognised examples taking the form of playlist generators for video and music services, product recommenders for online stores, or content recommenders for social media platforms and open web content recommenders. These systems can operate using a single input, like music, or multiple inputs within and across platforms like news, books and search queries. There are also popular recommender systems for specific topics like restaurants and online dating. Recommender systems have also been developed to explore research articles and experts, collaborators, and financial services. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following properties is part of the RDF Schema Language? | RDF Schema (Resource Description Framework Schema, variously abbreviated as RDFS, RDF(S), RDF-S, or RDF/S) is a set of classes with certain properties using the RDF extensible knowledge representation data model, providing basic elements for the description of ontologies. It uses various forms of RDF vocabularies, intended to structure RDF resources. RDF and RDFS can be saved in a triplestore, then one can extract some knowledge from them using a query language, like SPARQL. The first version was published by the World-Wide Web Consortium (W3C) in April 1998, and the final W3C recommendation was released in February 2014. Many RDFS components are included in the more expressive Web Ontology Language (OWL). | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following properties is part of the RDF Schema Language? | An RDF-based model can be represented in a variety of syntaxes, e.g., RDF/XML, N3, Turtle, and RDFa. RDF is a fundamental standard of the Semantic Web. RDF Schema extends RDF and is a vocabulary for describing properties and classes of RDF-based resources, with semantics for generalized-hierarchies of such properties and classes. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given a document collection with a vocabulary consisting of three words, $V = {a,b,c}$, and two documents $d_1$ = aabc and $d_2 = abc$. The query is $q = ab$. Using smoothed probabilistic retrieval (with $\lambda=0.5$), is it possible to enforce both a ranking $d_1 > d_2$ and $d_2 > d_1$ by adding suitable documents to the collection. If yes, give examples of such documents to be added, if no, provide an argument why this cannot be the case. | Rather than retrieving a document that exactly matches the query we should rank the documents based on their plausibility in regards to that query. Since d and q are both generated by users, they are error prone; thus d → q {\displaystyle d\to q} is uncertain. This will affect the plausibility of a given query. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given a document collection with a vocabulary consisting of three words, $V = {a,b,c}$, and two documents $d_1$ = aabc and $d_2 = abc$. The query is $q = ab$. Using smoothed probabilistic retrieval (with $\lambda=0.5$), is it possible to enforce both a ranking $d_1 > d_2$ and $d_2 > d_1$ by adding suitable documents to the collection. If yes, give examples of such documents to be added, if no, provide an argument why this cannot be the case. | Rather than retrieving a document that exactly matches the query we should rank the documents based on their plausibility in regards to that query. Since d and q are both generated by users, they are error prone; thus d → q {\displaystyle d\to q} is uncertain. This will affect the plausibility of a given query. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following is correct regarding crowdsourcing? | Crowdsourcing is a type of participative online activity in which an individual, an institution, a nonprofit organization, or company proposes to a group of individuals of varying knowledge, heterogeneity, and number, the voluntary undertaking of a task via a flexible open call. The undertaking of the task, of variable complexity and modularity, and in which the crowd should participate, bringing their work, money, knowledge and/or experience, always entails mutual benefit. The user will receive the satisfaction of a given type of need, be it economic, social recognition, self-esteem, or the development of individual skills, while the crowdsourcer will obtain and use to their advantage that which the user has brought to the venture, whose form will depend on the type of activity undertaken. Caveats in pursuing a Crowdsourcing strategy are to induce a substantial market model or incentive, and care has to be taken that the whole thing doesn't end up in an open source anarchy of adware and spyware plagiates, with a lot of broken solutions, started by people who just wanted to try it out, then gave up early, and a few winners. Popular examples for Crowdsourcing are Linux, Google Android, the Pirate Party movement, and Wikipedia. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which of the following is correct regarding crowdsourcing? | In contrast to outsourcing, crowdsourcing usually involves less specific and more public groups of participants.Advantages of using crowdsourcing include lowered costs, improved speed, improved quality, increased flexibility, and/or increased scalability of the work, as well as promoting diversity. Crowdsourcing methods include competitions, virtual labor markets, open online collaboration and data donation. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the 2-itemsets {1, 2}, {1, 3}, {1, 5}, {2, 3}, {2, 5}, when generating the 3-itemset we will: | For item set 5, the terminals '0' and '1' and the nonterminal B must be considered, but the resulting closed item sets are equal to already found item sets 1 and 2, respectively. For the nonterminal B, the transition goes to: Item set 7 E → E * B •For item set 6, the terminal '0' and '1' and the nonterminal B must be considered, but as before, the resulting item sets for the terminals are equal to the already found item sets 1 and 2. For the nonterminal B the transition goes to: Item set 8 E → E + B •These final item sets 7 and 8 have no symbols beyond their dots so no more new item sets are added, so the item generating procedure is complete. The finite automaton, with item sets as its states is shown below. The transition table for the automaton now looks as follows: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Given the 2-itemsets {1, 2}, {1, 3}, {1, 5}, {2, 3}, {2, 5}, when generating the 3-itemset we will: | Now we will make our minimum support value 4 so only {a, d} and {c, d} will remain after pruning. Now we will use the frequent item set to make combinations of triplets. We will then repeat the process by counting occurrences of triplets of mutations in the input set. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
When using bootstrapping in Random Forests, the number of different data items used to construct a single tree is: | Creating the bootstrap and out-of-bag datasets is crucial since it is used to test the accuracy of a random forest algorithm. For example, a model that produces 50 trees using the bootstrap/out-of-bag datasets will have a better accuracy than if it produced 10 trees. Since the algorithm generates multiple trees and therefore multiple datasets the chance that an object is left out of the bootstrap dataset is low. The next few sections talk about how the random forest algorithm works in more detail. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
When using bootstrapping in Random Forests, the number of different data items used to construct a single tree is: | The next part of the algorithm involves introducing yet another element of variability amongst the bootstrapped trees. In addition to each tree only examining a bootstrapped set of samples, only a small but consistent number of unique features are considered when ranking them as classifiers. This means that each tree only knows about the data pertaining to a small constant number of features, and a variable number of samples that is less than or equal to that of the original dataset. Consequently, the trees are more likely to return a wider array of answers, derived from more diverse knowledge. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
To constrain an object of an RDF statement from being of an atomic type (e.g., String), one has to use the following RDF/RDFS property: | rdf:type an instance of rdf:Property used to state that a resource is an instance of a class rdf:first the first item in the subject RDF list rdf:rest the rest of the subject RDF list after rdf:first rdf:value idiomatic property used for structured values rdf:subject the subject of the RDF statement rdf:predicate the predicate of the RDF statement rdf:object the object of the RDF statementrdf:Statement, rdf:subject, rdf:predicate, rdf:object are used for reification (see below). | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
To constrain an object of an RDF statement from being of an atomic type (e.g., String), one has to use the following RDF/RDFS property: | In particular, the notion of a "value that cannot be decomposed" is problematic, as it would seem to imply that few, if any, data types are atomic: A character string would seem not to be atomic, as the RDBMS typically provides operators to decompose it into substrings. A fixed-point number would seem not to be atomic, as the RDBMS typically provides operators to decompose it into integer and fractional components. An ISBN would seem not to be atomic, as it includes language and publisher identifier.Date suggests that "the notion of atomicity has no absolute meaning": a value may be considered atomic for some purposes, but may be considered an assemblage of more basic elements for other purposes. If this position is accepted, 1NF cannot be defined with reference to atomicity. Columns of any conceivable data type (from string types and numeric types to array types and table types) are then acceptable in a 1NF table—although perhaps not always desirable; for example, it may be more desirable to separate a Customer Name column into two separate columns as First Name, Surname. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
We learnt in the lecture that terms are typically stored in an inverted list. Now, in the inverted list, instead of only storing document identifiers of the documents in which the term appears, assume we also store an *offset* of the appearance of a term in a document. An $offset$ of a term $l_k$ given a document is defined as the number of words between the start of the document and $l_k$. Thus our inverted list is now: $l_k= \langle f_k: \{d_{i_1} \rightarrow [o_1,\ldots,o_{n_{i_1}}]\}, \{d_{i_2} \rightarrow [o_1,\ldots,o_{n_{i_2}}]\}, \ldots, \{d_{i_k} \rightarrow [o_1,\ldots,o_{n_{i_k}}]\} \rangle$ This means that in document $d_{i_1}$ term $l_k$ appears $n_{i_1}$ times and at offset $[o_1,\ldots,o_{n_{i_1}}]$, where $[o_1,\ldots,o_{n_{i_1}}]$ are sorted in ascending order, these type of indices are also known as term-offset indices. An example of a term-offset index is as follows: **Obama** = $⟨4 : {1 → [3]},{2 → [6]},{3 → [2,17]},{4 → [1]}⟩$ **Governor** = $⟨2 : {4 → [3]}, {7 → [14]}⟩$ **Election** = $⟨4 : {1 → [1]},{2 → [1,21]},{3 → [3]},{5 → [16,22,51]}⟩$ Which is to say that the term **Governor** appear in 2 documents. In document 4 at offset 3, in document 7 at offset 14. Now let us consider the *SLOP/x* operator in text retrieval. This operator has the syntax: *QueryTerm1 SLOP/x QueryTerm2* finds occurrences of *QueryTerm1* within $x$ (but not necessarily in that order) words of *QueryTerm2*, where $x$ is a positive integer argument ($x \geq 1$). Thus $x = 1$ demands that *QueryTerm1* be adjacent to *QueryTerm2*. Consider the general procedure for "merging" two term-offset inverted lists for a given document, to determine where the document satisfies a *SLOP/x* clause (since in general there will be many offsets at which each term occurs in a document). Let $L$ denote the total number of occurrences of the two terms in the document. Assume we have a pointer to the list of occurrences of each term and can move the pointer along this list. As we do so we check whether we have a hit for $SLOP/x$ (i.e. the $SLOP/x$ clause is satisfied). Each move of either pointer counts as a step. Based on this assumption is there a general "merging" procedure to determine whether the document satisfies a $SLOP/x$ clause, for which the following is true? Justify your answer. 1. The merge can be accomplished in a number of steps linear in $L$ regardless of $x$, and we can ensure that each pointer moves only to the right (i.e. forward). 2. The merge can be accomplished in a number of steps linear in $L$, but a pointer may be forced to move to the left (i.e. backwards). 3. The merge can require $x \times L$ steps in some cases. | A major drawback is that storing a word in the tree may require space beyond that required to store the word itself. An alternate representation is a suffix array, which is considered to require less virtual memory and supports data compression such as the BWT algorithm.Inverted index Stores a list of occurrences of each atomic search criterion, typically in the form of a hash table or binary tree.Citation index Stores citations or hyperlinks between documents to support citation analysis, a subject of bibliometrics. n-gram index Stores sequences of length of data to support other types of retrieval or text mining. Document-term matrix Used in latent semantic analysis, stores the occurrences of words in documents in a two-dimensional sparse matrix. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
We learnt in the lecture that terms are typically stored in an inverted list. Now, in the inverted list, instead of only storing document identifiers of the documents in which the term appears, assume we also store an *offset* of the appearance of a term in a document. An $offset$ of a term $l_k$ given a document is defined as the number of words between the start of the document and $l_k$. Thus our inverted list is now: $l_k= \langle f_k: \{d_{i_1} \rightarrow [o_1,\ldots,o_{n_{i_1}}]\}, \{d_{i_2} \rightarrow [o_1,\ldots,o_{n_{i_2}}]\}, \ldots, \{d_{i_k} \rightarrow [o_1,\ldots,o_{n_{i_k}}]\} \rangle$ This means that in document $d_{i_1}$ term $l_k$ appears $n_{i_1}$ times and at offset $[o_1,\ldots,o_{n_{i_1}}]$, where $[o_1,\ldots,o_{n_{i_1}}]$ are sorted in ascending order, these type of indices are also known as term-offset indices. An example of a term-offset index is as follows: **Obama** = $⟨4 : {1 → [3]},{2 → [6]},{3 → [2,17]},{4 → [1]}⟩$ **Governor** = $⟨2 : {4 → [3]}, {7 → [14]}⟩$ **Election** = $⟨4 : {1 → [1]},{2 → [1,21]},{3 → [3]},{5 → [16,22,51]}⟩$ Which is to say that the term **Governor** appear in 2 documents. In document 4 at offset 3, in document 7 at offset 14. Now let us consider the *SLOP/x* operator in text retrieval. This operator has the syntax: *QueryTerm1 SLOP/x QueryTerm2* finds occurrences of *QueryTerm1* within $x$ (but not necessarily in that order) words of *QueryTerm2*, where $x$ is a positive integer argument ($x \geq 1$). Thus $x = 1$ demands that *QueryTerm1* be adjacent to *QueryTerm2*. Consider the general procedure for "merging" two term-offset inverted lists for a given document, to determine where the document satisfies a *SLOP/x* clause (since in general there will be many offsets at which each term occurs in a document). Let $L$ denote the total number of occurrences of the two terms in the document. Assume we have a pointer to the list of occurrences of each term and can move the pointer along this list. As we do so we check whether we have a hit for $SLOP/x$ (i.e. the $SLOP/x$ clause is satisfied). Each move of either pointer counts as a step. Based on this assumption is there a general "merging" procedure to determine whether the document satisfies a $SLOP/x$ clause, for which the following is true? Justify your answer. 1. The merge can be accomplished in a number of steps linear in $L$ regardless of $x$, and we can ensure that each pointer moves only to the right (i.e. forward). 2. The merge can be accomplished in a number of steps linear in $L$, but a pointer may be forced to move to the left (i.e. backwards). 3. The merge can require $x \times L$ steps in some cases. | A major drawback is that storing a word in the tree may require space beyond that required to store the word itself. An alternate representation is a suffix array, which is considered to require less virtual memory and supports data compression such as the BWT algorithm.Inverted index Stores a list of occurrences of each atomic search criterion, typically in the form of a hash table or binary tree.Citation index Stores citations or hyperlinks between documents to support citation analysis, a subject of bibliometrics. n-gram index Stores sequences of length of data to support other types of retrieval or text mining. Document-term matrix Used in latent semantic analysis, stores the occurrences of words in documents in a two-dimensional sparse matrix. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Implement RSME score based on the following formula. \begin{equation} \mathit{RMSE} =\sqrt{\frac{1}{N} \sum_i (r_i -\hat{r_i})^2} \end{equation} You can use the mean_squared_error function from sklearn.metrics. | The RMSD of an estimator θ ^ {\displaystyle {\hat {\theta }}} with respect to an estimated parameter θ {\displaystyle \theta } is defined as the square root of the mean squared error: RMSD ( θ ^ ) = MSE ( θ ^ ) = E ( ( θ ^ − θ ) 2 ) . {\displaystyle \operatorname {RMSD} ({\hat {\theta }})={\sqrt {\operatorname {MSE} ({\hat {\theta }})}}={\sqrt {\operatorname {E} (({\hat {\theta }}-\theta )^{2})}}.} For an unbiased estimator, the RMSD is the square root of the variance, known as the standard deviation. The RMSD of predicted values y ^ t {\displaystyle {\hat {y}}_{t}} for times t of a regression's dependent variable y t , {\displaystyle y_{t},} with variables observed over T times, is computed for T different predictions as the square root of the mean of the squares of the deviations: RMSD = ∑ t = 1 T ( y ^ t − y t ) 2 T . | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Implement RSME score based on the following formula. \begin{equation} \mathit{RMSE} =\sqrt{\frac{1}{N} \sum_i (r_i -\hat{r_i})^2} \end{equation} You can use the mean_squared_error function from sklearn.metrics. | General-purpose statistical software such as SPSS and SAS include a function to calculate ρ T {\displaystyle \rho _{T}} . Users who don't know the formula ρ T {\displaystyle \rho _{T}} have no problem in obtaining the estimates with just a few mouse clicks. SEM software such as AMOS, LISREL, and MPLUS does not have a function to calculate SEM-based reliability coefficients. Users need to calculate the result by inputting it to the formula. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What is a correct pruning strategy for decision tree induction? | J.R. Quinlan (1986). "Induction of Decision Trees". Machine Learning. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
What is a correct pruning strategy for decision tree induction? | J.R. Quinlan (1986). "Induction of Decision Trees". Machine Learning. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the first pass over the database of the FP Growth algorithm | If many transactions share most frequent items, the FP-tree provides high compression close to tree root. Recursive processing of this compressed version of the main dataset grows frequent item sets directly, instead of generating candidate items and testing them against the entire database (as in the apriori algorithm). Growth begins from the bottom of the header table i.e. the item with the smallest support by finding all sorted transactions that end in that item. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In the first pass over the database of the FP Growth algorithm | doi:10.1023/A:1010822518073. Ayhan Demiriz and Kristin P. Bennett and John Shawe-Taylor (2002). "Linear Programming Boosting via Column Generation". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In a FP tree, the leaf nodes are the ones with: | Trees can also be represented radially: | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
In a FP tree, the leaf nodes are the ones with: | The tree elements are called "nodes". The lines connecting elements are called "branches". Nodes without children are called leaf nodes, "end-nodes", or "leaves". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The number of parameters of the fasttext classifier and the simple self-attention classifier | doi:10.1023/A:1007614523901. Robert E. Schapire and Yoram Singer (2000). "BoosTexter: A Boosting-based System for Text Categorization". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
The number of parameters of the fasttext classifier and the simple self-attention classifier | doi:10.1023/A:1007614523901. Robert E. Schapire and Yoram Singer (2000). "BoosTexter: A Boosting-based System for Text Categorization". | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Your input is "Distributed Information Systems". Your model tries to predict "Distributed" and "Systems" by leveraging the fact that these words are in the neighborhood of "Information". This model can be: | First Monday, 21(12). http://dx.doi.org/10.5210/fm.v21i12.7113 Hassan, S., Arroyo, J., Galán, J. M., Antunes, L., & Pavón, J. (2013). Asking the oracle: Introducing forecasting principles into agent-based modelling. Journal of Artificial Societies and Social Simulation, 16(3), 13 https://doi.org/10.18564/jasss.2241 | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Your input is "Distributed Information Systems". Your model tries to predict "Distributed" and "Systems" by leveraging the fact that these words are in the neighborhood of "Information". This model can be: | Distributed cognition can be used to explain how information is passed and processed, with a focus on both interactions between people, in addition to their interactions with the environment. These interactions are analysed in terms of the trajectories of information. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Considering the transaction below, which one is WRONG?
|Transaction ID |Items Bought|
|--|--|
|1|Tea|
|2|Tea, Yoghurt|
|3|Tea, Yoghurt, Kebap|
|4 |Kebap |
|5|Tea, Kebap| | "I bought a bag of apples from T shop." "I bought a bag of apples from the shop." "I bought a bag of apples from my brother. "The algorithm will then terminate. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Considering the transaction below, which one is WRONG?
|Transaction ID |Items Bought|
|--|--|
|1|Tea|
|2|Tea, Yoghurt|
|3|Tea, Yoghurt, Kebap|
|4 |Kebap |
|5|Tea, Kebap| | Given that a customer previously bought a black sweater from me and I have three black sweaters in inventory, when they return the black sweater for a refund, then I should have four black sweaters in inventory. Scenario 2: Exchanged items should be returned to inventory. Given that a customer previously bought a blue garment from me and I have two blue garments in inventory and three black garments in inventory, when they exchange the blue garment for a black garment, then I should have three blue garments in inventory and two black garments in inventory. The scenarios are ideally phrased declaratively rather than imperatively — in the business language, with no reference to elements of the UI through which the interactions take place.This format is referred to as the Gherkin language, which has a syntax similar to the above example. The term Gherkin, however, is specific to the Cucumber, JBehave, Lettuce, behave and Behat software tools. | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which is an appropriate method for fighting skewed distributions of class labels in
classification? | It was observed some conventional classification problems can be generalized in the framework of label ranking problem: if a training instance x {\displaystyle x\,\!} is labeled as class y i {\displaystyle y_{i}\,\!} , it implies that ∀ j ≠ i , y i ≻ x y j {\displaystyle \forall j\neq i,y_{i}\succ _{x}y_{j}\,\!} | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
Which is an appropriate method for fighting skewed distributions of class labels in
classification? | It was observed some conventional classification problems can be generalized in the framework of label ranking problem: if a training instance x {\displaystyle x\,\!} is labeled as class y i {\displaystyle y_{i}\,\!} , it implies that ∀ j ≠ i , y i ≻ x y j {\displaystyle \forall j\neq i,y_{i}\succ _{x}y_{j}\,\!} | https://www.kaggle.com/datasets/conjuring92/wiki-stem-corpus |
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